From 001e7a52b1a823f41ae9706d935fccfe1bb1ec5a Mon Sep 17 00:00:00 2001 From: Laszlo Nagy Date: Fri, 30 Apr 2021 09:49:21 +0100 Subject: [PATCH] util_adxcvr: Add LANE_RATE parameter so it can be used for automatic constraint generation Add separate LANE_RATE for TX and RX --- library/xilinx/util_adxcvr/util_adxcvr.v | 3 +++ library/xilinx/util_adxcvr/util_adxcvr_ip.tcl | 24 +++++++++++++++++++ 2 files changed, 27 insertions(+) diff --git a/library/xilinx/util_adxcvr/util_adxcvr.v b/library/xilinx/util_adxcvr/util_adxcvr.v index a65d8a89f..f1510f001 100644 --- a/library/xilinx/util_adxcvr/util_adxcvr.v +++ b/library/xilinx/util_adxcvr/util_adxcvr.v @@ -42,6 +42,9 @@ module util_adxcvr #( parameter integer XCVR_TYPE = 0, + parameter real RX_LANE_RATE = 12.5, + parameter real TX_LANE_RATE = 12.5, + parameter LINK_MODE = 1, // 2 - 64B/66B; 1 - 8B/10B /* Only 4 is supported at the moment for 8b/10b and 8 for 64b */ parameter DATA_PATH_WIDTH = LINK_MODE == 2 ? 8 : 4, diff --git a/library/xilinx/util_adxcvr/util_adxcvr_ip.tcl b/library/xilinx/util_adxcvr/util_adxcvr_ip.tcl index 33014c428..ae76c9121 100644 --- a/library/xilinx/util_adxcvr/util_adxcvr_ip.tcl +++ b/library/xilinx/util_adxcvr/util_adxcvr_ip.tcl @@ -45,6 +45,30 @@ set_property -dict [list \ value_tcl_expr {expr $LINK_MODE*4} \ ] $param +set p [ipgui::get_guiparamspec -name "RX_LANE_RATE" -component $cc] +ipgui::move_param -component $cc -order 1 $p -parent $page0 +set_property -dict [list \ + display_name {Rx Lane Rate (Gbps)} \ + widget {textEdit} \ +] $p +set_property -dict [list \ + value_resolve_type user \ + value 12.5 \ + value_format float \ +] [ipx::get_user_parameters $p -of_objects $cc] + +set p [ipgui::get_guiparamspec -name "TX_LANE_RATE" -component $cc] +ipgui::move_param -component $cc -order 2 $p -parent $page0 +set_property -dict [list \ + display_name {Tx Lane Rate (Gbps)} \ + widget {textEdit} \ +] $p +set_property -dict [list \ + value_resolve_type user \ + value 12.5 \ + value_format float \ +] [ipx::get_user_parameters $p -of_objects $cc] + ipx::remove_all_bus_interface [ipx::current_core] ipx::infer_bus_interface up_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]