c5soc- remove unused hps ports
Rejeesh Kutty
parent
89b20f2a35
commit
0041bf69be
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@ -135,76 +135,81 @@
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<parameter name="useTestBenchNamingPattern" value="false" />
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<instanceScript></instanceScript>
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<interface
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name="axi_ad9361_device_clock"
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internal="arradio.axi_ad9361_device_clock"
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name="axi_ad9361_delay_clk"
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internal="arradio.axi_ad9361_delay_clk"
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type="clock"
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dir="end" />
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<interface
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name="axi_ad9361_device_clock"
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internal="arradio.axi_ad9361_device_clock" />
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<interface
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name="axi_ad9361_device_if"
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internal="arradio.axi_ad9361_device_if"
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type="conduit"
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dir="end" />
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<interface name="axi_ad9361_l_clk" internal="arradio.axi_ad9361_l_clk" />
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<interface
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name="axi_ad9361_l_clk"
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internal="arradio.axi_ad9361_l_clk"
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type="clock"
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dir="start" />
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<interface name="clk" internal="sys_clk.clk_in" type="clock" dir="end" />
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name="axi_ad9361_up_enable"
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internal="arradio.axi_ad9361_up_enable"
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type="conduit"
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dir="end" />
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<interface
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name="gpio_external_connection"
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name="axi_ad9361_up_txnrx"
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internal="arradio.axi_ad9361_up_txnrx"
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type="conduit"
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dir="end" />
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<interface
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name="gpio"
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internal="arradio.gpio_external_connection"
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type="conduit"
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dir="end" />
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<interface name="reset" internal="sys_clk.clk_in_reset" type="reset" dir="end" />
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<interface
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name="spi_ad9361_external"
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name="spi"
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internal="arradio.spi_ad9361_external"
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type="conduit"
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dir="end" />
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<interface name="sys_clk" internal="sys_clk.clk_in" type="clock" dir="end" />
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<interface
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name="sys_gpio_external_connection"
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name="sys_gpio"
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internal="c5soc.sys_gpio_external_connection"
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type="conduit"
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dir="end" />
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<interface
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name="sys_hps_h2f_reset"
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internal="c5soc.sys_hps_h2f_reset"
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type="reset"
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dir="start" />
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<interface
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name="sys_hps_hps_io"
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name="sys_hps_io"
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internal="c5soc.sys_hps_hps_io"
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type="conduit"
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dir="end" />
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<interface
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name="sys_hps_memory"
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name="sys_hps_mem"
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internal="c5soc.sys_hps_memory"
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type="conduit"
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dir="end" />
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<interface
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name="sys_hps_spim0"
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internal="c5soc.sys_hps_spim0"
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type="conduit"
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dir="end" />
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<interface
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name="sys_hps_spim0_sclk_out"
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internal="c5soc.sys_hps_spim0_sclk_out"
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type="clock"
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name="sys_hps_reset"
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internal="c5soc.sys_hps_h2f_reset"
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type="reset"
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dir="start" />
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<interface name="sys_hps_spim0" internal="c5soc.sys_hps_spim0" />
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<interface name="sys_hps_spim0_sclk_out" internal="c5soc.sys_hps_spim0_sclk_out" />
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<interface
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name="vga_clock_video_output_clocked_video"
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internal="c5soc.vga_clock_video_output_clocked_video"
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type="conduit"
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name="sys_reset"
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internal="sys_clk.clk_in_reset"
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type="reset"
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dir="end" />
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<interface
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name="vga_pixel_clock_bridge_out_clk"
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name="vga_clk"
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internal="c5soc.vga_pixel_clock_bridge_out_clk"
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type="clock"
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dir="start" />
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<interface
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name="vga_if"
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internal="c5soc.vga_clock_video_output_clocked_video"
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type="conduit"
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dir="end" />
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<module name="arradio" kind="arradio_bd" version="1.0" enabled="1">
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<parameter name="AUTO_AXI_AD9361_DEVICE_CLOCK_CLOCK_DOMAIN" value="1" />
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<parameter name="AUTO_AXI_AD9361_DEVICE_CLOCK_CLOCK_RATE" value="0" />
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<parameter name="AUTO_AXI_AD9361_DEVICE_CLOCK_RESET_DOMAIN" value="1" />
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<parameter name="AUTO_AXI_AD9361_DELAY_CLK_CLOCK_DOMAIN" value="1" />
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<parameter name="AUTO_AXI_AD9361_DELAY_CLK_CLOCK_RATE" value="0" />
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<parameter name="AUTO_AXI_AD9361_DELAY_CLK_RESET_DOMAIN" value="1" />
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<parameter name="AUTO_AXI_DMAC_ADC_M_DEST_AXI_ADDRESS_MAP"><![CDATA[<address-map><slave name='c5soc_sys_hps_bridges.f2h_sdram1_data' start='0x0' end='0x100000000' /></address-map>]]></parameter>
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<parameter
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name="AUTO_AXI_DMAC_ADC_M_DEST_AXI_ADDRESS_WIDTH"
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@ -217,12 +222,12 @@
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<parameter name="AUTO_DEVICE_FAMILY" value="Cyclone V" />
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<parameter name="AUTO_DEVICE_SPEEDGRADE" value="8_H6" />
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<parameter name="AUTO_GENERATION_ID" value="0" />
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<parameter name="AUTO_MEM_CLK_CLOCK_DOMAIN" value="8" />
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<parameter name="AUTO_MEM_CLK_CLOCK_DOMAIN" value="6" />
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<parameter name="AUTO_MEM_CLK_CLOCK_RATE" value="80000000" />
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<parameter name="AUTO_MEM_CLK_RESET_DOMAIN" value="8" />
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<parameter name="AUTO_SYS_CLK_CLOCK_DOMAIN" value="3" />
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<parameter name="AUTO_MEM_CLK_RESET_DOMAIN" value="6" />
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<parameter name="AUTO_SYS_CLK_CLOCK_DOMAIN" value="2" />
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<parameter name="AUTO_SYS_CLK_CLOCK_RATE" value="50000000" />
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<parameter name="AUTO_SYS_CLK_RESET_DOMAIN" value="3" />
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<parameter name="AUTO_SYS_CLK_RESET_DOMAIN" value="2" />
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<parameter name="AUTO_UNIQUE_ID">$${FILENAME}_arradio</parameter>
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</module>
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<module name="c5soc" kind="c5soc_system_bd" version="1.0" enabled="1">
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@ -230,9 +235,9 @@
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<parameter name="AUTO_DEVICE_FAMILY" value="Cyclone V" />
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<parameter name="AUTO_DEVICE_SPEEDGRADE" value="8_H6" />
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<parameter name="AUTO_GENERATION_ID" value="0" />
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<parameter name="AUTO_SYS_CLK_CLOCK_DOMAIN" value="3" />
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<parameter name="AUTO_SYS_CLK_CLOCK_DOMAIN" value="2" />
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<parameter name="AUTO_SYS_CLK_CLOCK_RATE" value="50000000" />
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<parameter name="AUTO_SYS_CLK_RESET_DOMAIN" value="3" />
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<parameter name="AUTO_SYS_CLK_RESET_DOMAIN" value="2" />
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<parameter name="AUTO_SYS_CPU_INTERCONNECT_M0_ADDRESS_MAP"><![CDATA[<address-map><slave name='arradio_axi_dmac_adc.s_axi' start='0x0' end='0x4000' /><slave name='arradio_axi_dmac_dac.s_axi' start='0x4000' end='0x8000' /><slave name='arradio_spi_ad9361.spi_control_port' start='0x8000' end='0x8020' /><slave name='arradio_gpio.s1' start='0x9000' end='0x9010' /><slave name='arradio_axi_ad9361.s_axi' start='0x20000' end='0x30000' /></address-map>]]></parameter>
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<parameter
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name="AUTO_SYS_CPU_INTERCONNECT_M0_ADDRESS_WIDTH"
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@ -1,25 +1,14 @@
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create_clock -period "20.000 ns" -name clk_50m [get_ports {sys_clk}]
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create_clock -period "4.000 ns" -name clk_250m [get_ports {rx_clk_in}]
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create_clock -period "12.500 ns" -name clk_80m [get_pins {i_system_bd|c5soc|sys_hps|fpga_interfaces|clocks_resets|h2f_user0_clk}]
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create_clock -period "20.000 ns" -name sys_clk [get_ports {sys_clk}]
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create_clock -period "12.500 ns" -name dma_clk [get_pins {*sys_hps*h2f_user0_clk}]
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create_clock -period 4.0 -name rx_clk [get_ports {rx_clk_in}]
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create_clock -period 4.0 -name v_rx_clk
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derive_pll_clocks
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derive_clock_uncertainty
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set clk_125m [get_clocks {i_system_bd|arradio|axi_ad9361|i_dev_if|i_rx|i_altlvds_rx|auto_generated|pll_sclk~PLL_OUTPUT_COUNTER|divclk}]
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set clk_vga [get_clocks {i_system_bd|c5soc|vga_pll|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}]
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set_false_path -from clk_50m -to clk_80m
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set_false_path -from clk_50m -to $clk_125m
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set_false_path -from clk_80m -to clk_50m
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set_false_path -from clk_80m -to $clk_125m
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set_false_path -from $clk_125m -to clk_50m
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set_false_path -from $clk_125m -to clk_80m
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set_false_path -from clk_50m -to $clk_vga
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set_false_path -from $clk_vga -to clk_50m
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create_clock -period 4.0 -name v_rx_clk
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create_generated_clock -source [get_clocks {*axi_ad9361*alt_clk*divclk}] -name v_fb_clk [get_ports {tx_clk_out}]
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set_input_delay -clock {v_rx_clk} -max 1.2 [get_ports {rx_frame_in}]
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set_input_delay -clock {v_rx_clk} -max 1.2 [get_ports {rx_data_in[0]}]
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@ -36,23 +25,19 @@ set_input_delay -clock {v_rx_clk} -min 0.2 [get_ports {rx_data_in[3]}] -clo
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set_input_delay -clock {v_rx_clk} -min 0.2 [get_ports {rx_data_in[4]}] -clock_fall -add_delay
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set_input_delay -clock {v_rx_clk} -min 0.2 [get_ports {rx_data_in[5]}] -clock_fall -add_delay
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create_generated_clock -source [get_ports {rx_clk_in}] -name v_tx_clk [get_ports {tx_clk_out}] -phase 90
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set_false_path -from clk_250m -to v_tx_clk
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set_false_path -from v_tx_clk -to clk_250m
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set_output_delay -clock {v_tx_clk} -max 1.2 [get_ports {tx_frame_out}]
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set_output_delay -clock {v_tx_clk} -max 1.2 [get_ports {tx_data_out[0]}]
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set_output_delay -clock {v_tx_clk} -max 1.2 [get_ports {tx_data_out[1]}]
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set_output_delay -clock {v_tx_clk} -max 1.2 [get_ports {tx_data_out[2]}]
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set_output_delay -clock {v_tx_clk} -max 1.2 [get_ports {tx_data_out[3]}]
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set_output_delay -clock {v_tx_clk} -max 1.2 [get_ports {tx_data_out[4]}]
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set_output_delay -clock {v_tx_clk} -max 1.2 [get_ports {tx_data_out[5]}]
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set_output_delay -clock {v_tx_clk} -min 0.2 [get_ports {tx_frame_out}] -clock_fall -add_delay
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set_output_delay -clock {v_tx_clk} -min 0.2 [get_ports {tx_data_out[0]}] -clock_fall -add_delay
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set_output_delay -clock {v_tx_clk} -min 0.2 [get_ports {tx_data_out[1]}] -clock_fall -add_delay
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set_output_delay -clock {v_tx_clk} -min 0.2 [get_ports {tx_data_out[2]}] -clock_fall -add_delay
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set_output_delay -clock {v_tx_clk} -min 0.2 [get_ports {tx_data_out[3]}] -clock_fall -add_delay
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set_output_delay -clock {v_tx_clk} -min 0.2 [get_ports {tx_data_out[4]}] -clock_fall -add_delay
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set_output_delay -clock {v_tx_clk} -min 0.2 [get_ports {tx_data_out[5]}] -clock_fall -add_delay
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set_output_delay -clock {v_fb_clk} -max 1.2 [get_ports {tx_frame_out}]
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set_output_delay -clock {v_fb_clk} -max 1.2 [get_ports {tx_data_out[0]}]
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set_output_delay -clock {v_fb_clk} -max 1.2 [get_ports {tx_data_out[1]}]
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set_output_delay -clock {v_fb_clk} -max 1.2 [get_ports {tx_data_out[2]}]
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set_output_delay -clock {v_fb_clk} -max 1.2 [get_ports {tx_data_out[3]}]
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set_output_delay -clock {v_fb_clk} -max 1.2 [get_ports {tx_data_out[4]}]
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set_output_delay -clock {v_fb_clk} -max 1.2 [get_ports {tx_data_out[5]}]
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set_output_delay -clock {v_fb_clk} -min 0.2 [get_ports {tx_frame_out}] -clock_fall -add_delay
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set_output_delay -clock {v_fb_clk} -min 0.2 [get_ports {tx_data_out[0]}] -clock_fall -add_delay
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set_output_delay -clock {v_fb_clk} -min 0.2 [get_ports {tx_data_out[1]}] -clock_fall -add_delay
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set_output_delay -clock {v_fb_clk} -min 0.2 [get_ports {tx_data_out[2]}] -clock_fall -add_delay
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set_output_delay -clock {v_fb_clk} -min 0.2 [get_ports {tx_data_out[3]}] -clock_fall -add_delay
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set_output_delay -clock {v_fb_clk} -min 0.2 [get_ports {tx_data_out[4]}] -clock_fall -add_delay
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set_output_delay -clock {v_fb_clk} -min 0.2 [get_ports {tx_data_out[5]}] -clock_fall -add_delay
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@ -5,16 +5,46 @@ source ../../scripts/adi_env.tcl
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project_new arradio_c5soc -overwrite
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source "../../common/c5soc/c5soc_system_assign.tcl"
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set_global_assignment -name IP_SEARCH_PATHS "../common/;../../common/**/*;../../../library/**/*"
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set_user_option -name USER_IP_SEARCH_PATHS "../common/;../../common/**/*;../../../library/**/*"
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set_global_assignment -name QSYS_FILE system_bd.qsys
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set_global_assignment -name QSYS_FILE system_bd.qsys
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set_global_assignment -name VERILOG_FILE "../../../library/common/ad_iobuf.v"
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set_global_assignment -name VERILOG_FILE system_top.v
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set_global_assignment -name SDC_FILE system_constr.sdc
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set_global_assignment -name TOP_LEVEL_ENTITY system_top
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set_location_assignment PIN_H15 -to rx_clk_in
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set_location_assignment PIN_G15 -to "rx_clk_in(n)"
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set_location_assignment PIN_F13 -to rx_frame_in
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set_location_assignment PIN_E13 -to "rx_frame_in(n)"
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set_location_assignment PIN_D11 -to rx_data_in[0]
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set_location_assignment PIN_D10 -to "rx_data_in[0](n)"
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set_location_assignment PIN_E12 -to rx_data_in[1]
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set_location_assignment PIN_D12 -to "rx_data_in[1](n)"
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set_location_assignment PIN_E9 -to rx_data_in[2]
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set_location_assignment PIN_D9 -to "rx_data_in[2](n)"
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set_location_assignment PIN_B6 -to rx_data_in[3]
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set_location_assignment PIN_B5 -to "rx_data_in[3](n)"
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set_location_assignment PIN_F11 -to rx_data_in[4]
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set_location_assignment PIN_E11 -to "rx_data_in[4](n)"
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set_location_assignment PIN_C13 -to rx_data_in[5]
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set_location_assignment PIN_B12 -to "rx_data_in[5](n)"
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set_location_assignment PIN_A11 -to tx_clk_out
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set_location_assignment PIN_A10 -to "tx_clk_out(n)"
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set_location_assignment PIN_E3 -to tx_frame_out
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set_location_assignment PIN_E2 -to "tx_frame_out(n)"
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set_location_assignment PIN_E1 -to tx_data_out[0]
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set_location_assignment PIN_D1 -to "tx_data_out[0](n)"
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set_location_assignment PIN_D2 -to tx_data_out[1]
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set_location_assignment PIN_C2 -to "tx_data_out[1](n)"
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set_location_assignment PIN_C3 -to tx_data_out[2]
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set_location_assignment PIN_B3 -to "tx_data_out[2](n)"
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set_location_assignment PIN_B2 -to tx_data_out[3]
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set_location_assignment PIN_B1 -to "tx_data_out[3](n)"
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set_location_assignment PIN_A4 -to tx_data_out[4]
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set_location_assignment PIN_A3 -to "tx_data_out[4](n)"
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set_location_assignment PIN_E4 -to tx_data_out[5]
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set_location_assignment PIN_D4 -to "tx_data_out[5](n)"
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set_instance_assignment -name IO_STANDARD LVDS -to rx_clk_in
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set_instance_assignment -name IO_STANDARD LVDS -to rx_frame_in
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set_instance_assignment -name IO_STANDARD LVDS -to rx_data_in[0]
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@ -41,60 +71,28 @@ set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to rx_data_in[3]
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set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to rx_data_in[4]
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set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to rx_data_in[5]
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set_location_assignment PIN_H15 -to rx_clk_in
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set_location_assignment PIN_G15 -to "rx_clk_in(n)"
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set_location_assignment PIN_F13 -to rx_frame_in
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set_location_assignment PIN_E13 -to "rx_frame_in(n)"
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set_location_assignment PIN_D11 -to rx_data_in[0]
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set_location_assignment PIN_D10 -to "rx_data_in[0](n)"
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set_location_assignment PIN_E12 -to rx_data_in[1]
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set_location_assignment PIN_D12 -to "rx_data_in[1](n)"
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set_location_assignment PIN_E9 -to rx_data_in[2]
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set_location_assignment PIN_D9 -to "rx_data_in[2](n)"
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set_location_assignment PIN_B6 -to rx_data_in[3]
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set_location_assignment PIN_B5 -to "rx_data_in[3](n)"
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set_location_assignment PIN_F11 -to rx_data_in[4]
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set_location_assignment PIN_E11 -to "rx_data_in[4](n)"
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set_location_assignment PIN_C13 -to rx_data_in[5]
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set_location_assignment PIN_B12 -to "rx_data_in[5](n)"
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set_location_assignment PIN_A11 -to tx_clk_out
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set_location_assignment PIN_A10 -to "tx_clk_out(n)"
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set_location_assignment PIN_E3 -to tx_frame_out
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set_location_assignment PIN_E2 -to "tx_frame_out(n)"
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set_location_assignment PIN_E1 -to tx_data_out[0]
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set_location_assignment PIN_D1 -to "tx_data_out[0](n)"
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set_location_assignment PIN_D2 -to tx_data_out[1]
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set_location_assignment PIN_C2 -to "tx_data_out[1](n)"
|
||||
set_location_assignment PIN_C3 -to tx_data_out[2]
|
||||
set_location_assignment PIN_B3 -to "tx_data_out[2](n)"
|
||||
set_location_assignment PIN_B2 -to tx_data_out[3]
|
||||
set_location_assignment PIN_B1 -to "tx_data_out[3](n)"
|
||||
set_location_assignment PIN_A4 -to tx_data_out[4]
|
||||
set_location_assignment PIN_A3 -to "tx_data_out[4](n)"
|
||||
set_location_assignment PIN_E4 -to tx_data_out[5]
|
||||
set_location_assignment PIN_D4 -to "tx_data_out[5](n)"
|
||||
set_location_assignment PIN_B11 -to enable
|
||||
set_location_assignment PIN_C12 -to txnrx
|
||||
set_instance_assignment -name IO_STANDARD "2.5 V" -to enable
|
||||
set_instance_assignment -name IO_STANDARD "2.5 V" -to txnrx
|
||||
|
||||
set_location_assignment PIN_C4 -to ad9361_resetb
|
||||
set_location_assignment PIN_C5 -to ad9361_en_agc
|
||||
set_location_assignment PIN_D5 -to ad9361_sync
|
||||
set_instance_assignment -name IO_STANDARD "2.5 V" -to ad9361_resetb
|
||||
set_instance_assignment -name IO_STANDARD "2.5 V" -to ad9361_en_agc
|
||||
set_instance_assignment -name IO_STANDARD "2.5 V" -to ad9361_sync
|
||||
set_instance_assignment -name IO_STANDARD "2.5 V" -to ad9361_enable
|
||||
set_instance_assignment -name IO_STANDARD "2.5 V" -to ad9361_txnrx
|
||||
|
||||
set_location_assignment PIN_A8 -to spi_csn
|
||||
set_location_assignment PIN_H12 -to spi_clk
|
||||
set_location_assignment PIN_H13 -to spi_mosi
|
||||
set_location_assignment PIN_G11 -to spi_miso
|
||||
set_instance_assignment -name IO_STANDARD "2.5 V" -to spi_csn
|
||||
set_instance_assignment -name IO_STANDARD "2.5 V" -to spi_clk
|
||||
set_instance_assignment -name IO_STANDARD "2.5 V" -to spi_mosi
|
||||
set_instance_assignment -name IO_STANDARD "2.5 V" -to spi_miso
|
||||
|
||||
set_location_assignment PIN_C4 -to ad9361_resetb
|
||||
set_location_assignment PIN_C5 -to ad9361_en_agc
|
||||
set_location_assignment PIN_D5 -to ad9361_sync
|
||||
set_location_assignment PIN_B11 -to ad9361_enable
|
||||
set_location_assignment PIN_C12 -to ad9361_txnrx
|
||||
set_location_assignment PIN_A8 -to spi_csn
|
||||
set_location_assignment PIN_H12 -to spi_clk
|
||||
set_location_assignment PIN_H13 -to spi_mosi
|
||||
set_location_assignment PIN_G11 -to spi_miso
|
||||
set_instance_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -to * -entity axi_ad9361
|
||||
|
||||
execute_flow -compile
|
||||
|
||||
|
|
|
|||
|
|
@ -41,379 +41,139 @@ module system_top (
|
|||
|
||||
// clock and resets
|
||||
|
||||
sys_clk,
|
||||
input sys_clk,
|
||||
|
||||
// hps
|
||||
// hps-ddr
|
||||
|
||||
ddr3_a,
|
||||
ddr3_ba,
|
||||
ddr3_ck_p,
|
||||
ddr3_ck_n,
|
||||
ddr3_cke,
|
||||
ddr3_cs_n,
|
||||
ddr3_ras_n,
|
||||
ddr3_cas_n,
|
||||
ddr3_we_n,
|
||||
ddr3_reset_n,
|
||||
ddr3_dq,
|
||||
ddr3_dqs_p,
|
||||
ddr3_dqs_n,
|
||||
ddr3_odt,
|
||||
ddr3_dm,
|
||||
ddr3_oct_rzqin,
|
||||
eth1_tx_clk,
|
||||
eth1_tx_ctl,
|
||||
eth1_txd0,
|
||||
eth1_txd1,
|
||||
eth1_txd2,
|
||||
eth1_txd3,
|
||||
eth1_rx_clk,
|
||||
eth1_rx_ctl,
|
||||
eth1_rxd0,
|
||||
eth1_rxd1,
|
||||
eth1_rxd2,
|
||||
eth1_rxd3,
|
||||
eth1_mdc,
|
||||
eth1_mdio,
|
||||
qspi_ss0,
|
||||
qspi_clk,
|
||||
qspi_io0,
|
||||
qspi_io1,
|
||||
qspi_io2,
|
||||
qspi_io3,
|
||||
sdio_clk,
|
||||
sdio_cmd,
|
||||
sdio_d0,
|
||||
sdio_d1,
|
||||
sdio_d2,
|
||||
sdio_d3,
|
||||
usb1_clk,
|
||||
usb1_stp,
|
||||
usb1_dir,
|
||||
usb1_nxt,
|
||||
usb1_d0,
|
||||
usb1_d1,
|
||||
usb1_d2,
|
||||
usb1_d3,
|
||||
usb1_d4,
|
||||
usb1_d5,
|
||||
usb1_d6,
|
||||
usb1_d7,
|
||||
spim1_ss0,
|
||||
spim1_clk,
|
||||
spim1_mosi,
|
||||
spim1_miso,
|
||||
uart0_rx,
|
||||
uart0_tx,
|
||||
output [ 14:0] ddr3_a,
|
||||
output [ 2:0] ddr3_ba,
|
||||
output ddr3_reset_n,
|
||||
output ddr3_ck_p,
|
||||
output ddr3_ck_n,
|
||||
output ddr3_cke,
|
||||
output ddr3_cs_n,
|
||||
output ddr3_ras_n,
|
||||
output ddr3_cas_n,
|
||||
output ddr3_we_n,
|
||||
inout [ 31:0] ddr3_dq,
|
||||
inout [ 3:0] ddr3_dqs_p,
|
||||
inout [ 3:0] ddr3_dqs_n,
|
||||
output [ 3:0] ddr3_dm,
|
||||
output ddr3_odt,
|
||||
input ddr3_rzq,
|
||||
|
||||
// hps-ethernet
|
||||
|
||||
output eth1_tx_clk,
|
||||
output eth1_tx_ctl,
|
||||
output [ 3:0] eth1_tx_d,
|
||||
input eth1_rx_clk,
|
||||
input eth1_rx_ctl,
|
||||
input [ 3:0] eth1_rx_d,
|
||||
output eth1_mdc,
|
||||
inout eth1_mdio,
|
||||
|
||||
// hps-qspi
|
||||
|
||||
output qspi_ss0,
|
||||
output qspi_clk,
|
||||
inout [ 3:0] qspi_io,
|
||||
|
||||
// hps-sdio
|
||||
|
||||
output sdio_clk,
|
||||
inout sdio_cmd,
|
||||
inout [ 3:0] sdio_d,
|
||||
|
||||
// hps-usb
|
||||
|
||||
input usb1_clk,
|
||||
output usb1_stp,
|
||||
input usb1_dir,
|
||||
input usb1_nxt,
|
||||
inout [ 7:0] usb1_d,
|
||||
|
||||
// hps-spim1-lcd
|
||||
|
||||
output spim1_ss0,
|
||||
output spim1_clk,
|
||||
output spim1_mosi,
|
||||
input spim1_miso,
|
||||
|
||||
// hps-uart
|
||||
|
||||
input uart0_rx,
|
||||
output uart0_tx,
|
||||
|
||||
// board gpio
|
||||
|
||||
led,
|
||||
push_buttons,
|
||||
dip_switches,
|
||||
output [ 3:0] gpio_bd_o,
|
||||
input [ 7:0] gpio_bd_i,
|
||||
|
||||
// display
|
||||
|
||||
vga_clk,
|
||||
vga_blank_n,
|
||||
vga_sync_n,
|
||||
vga_hs,
|
||||
vga_vs,
|
||||
vga_r,
|
||||
vga_g,
|
||||
vga_b,
|
||||
output vga_clk,
|
||||
output vga_blank_n,
|
||||
output vga_sync_n,
|
||||
output vga_hsync,
|
||||
output vga_vsync,
|
||||
output [ 7:0] vga_red,
|
||||
output [ 7:0] vga_grn,
|
||||
output [ 7:0] vga_blu,
|
||||
|
||||
// data interface
|
||||
// ad9361
|
||||
|
||||
rx_clk_in,
|
||||
rx_frame_in,
|
||||
rx_data_in,
|
||||
tx_clk_out,
|
||||
tx_frame_out,
|
||||
tx_data_out,
|
||||
input rx_clk_in,
|
||||
input rx_frame_in,
|
||||
input [ 5:0] rx_data_in,
|
||||
output tx_clk_out,
|
||||
output tx_frame_out,
|
||||
output [ 5:0] tx_data_out,
|
||||
output enable,
|
||||
output txnrx,
|
||||
|
||||
// gpio interface
|
||||
|
||||
ad9361_resetb,
|
||||
ad9361_en_agc,
|
||||
ad9361_sync,
|
||||
ad9361_enable,
|
||||
ad9361_txnrx,
|
||||
|
||||
// spi
|
||||
|
||||
spi_csn,
|
||||
spi_clk,
|
||||
spi_mosi,
|
||||
spi_miso);
|
||||
|
||||
// clock and resets
|
||||
|
||||
input sys_clk;
|
||||
|
||||
// hps
|
||||
|
||||
output [ 14:0] ddr3_a;
|
||||
output [ 2:0] ddr3_ba;
|
||||
output ddr3_ck_p;
|
||||
output ddr3_ck_n;
|
||||
output ddr3_cke;
|
||||
output ddr3_cs_n;
|
||||
output ddr3_ras_n;
|
||||
output ddr3_cas_n;
|
||||
output ddr3_we_n;
|
||||
output ddr3_reset_n;
|
||||
inout [ 31:0] ddr3_dq;
|
||||
inout [ 3:0] ddr3_dqs_p;
|
||||
inout [ 3:0] ddr3_dqs_n;
|
||||
output ddr3_odt;
|
||||
output [ 3:0] ddr3_dm;
|
||||
input ddr3_oct_rzqin;
|
||||
output eth1_tx_clk;
|
||||
output eth1_tx_ctl;
|
||||
output eth1_txd0;
|
||||
output eth1_txd1;
|
||||
output eth1_txd2;
|
||||
output eth1_txd3;
|
||||
input eth1_rx_clk;
|
||||
input eth1_rx_ctl;
|
||||
input eth1_rxd0;
|
||||
input eth1_rxd1;
|
||||
input eth1_rxd2;
|
||||
input eth1_rxd3;
|
||||
output eth1_mdc;
|
||||
inout eth1_mdio;
|
||||
output qspi_ss0;
|
||||
output qspi_clk;
|
||||
inout qspi_io0;
|
||||
inout qspi_io1;
|
||||
inout qspi_io2;
|
||||
inout qspi_io3;
|
||||
output sdio_clk;
|
||||
inout sdio_cmd;
|
||||
inout sdio_d0;
|
||||
inout sdio_d1;
|
||||
inout sdio_d2;
|
||||
inout sdio_d3;
|
||||
input usb1_clk;
|
||||
output usb1_stp;
|
||||
input usb1_dir;
|
||||
input usb1_nxt;
|
||||
inout usb1_d0;
|
||||
inout usb1_d1;
|
||||
inout usb1_d2;
|
||||
inout usb1_d3;
|
||||
inout usb1_d4;
|
||||
inout usb1_d5;
|
||||
inout usb1_d6;
|
||||
inout usb1_d7;
|
||||
output spim1_ss0;
|
||||
output spim1_clk;
|
||||
output spim1_mosi;
|
||||
input spim1_miso;
|
||||
input uart0_rx;
|
||||
output uart0_tx;
|
||||
|
||||
// board gpio
|
||||
|
||||
output [ 3:0] led;
|
||||
input [ 3:0] push_buttons;
|
||||
input [ 3:0] dip_switches;
|
||||
|
||||
// display
|
||||
|
||||
output vga_clk;
|
||||
output vga_blank_n;
|
||||
output vga_sync_n;
|
||||
output vga_hs;
|
||||
output vga_vs;
|
||||
output [ 7:0] vga_r;
|
||||
output [ 7:0] vga_g;
|
||||
output [ 7:0] vga_b;
|
||||
|
||||
// data interface
|
||||
|
||||
input rx_clk_in;
|
||||
input rx_frame_in;
|
||||
input [ 5:0] rx_data_in;
|
||||
output tx_clk_out;
|
||||
output tx_frame_out;
|
||||
output [ 5:0] tx_data_out;
|
||||
|
||||
// gpio interface
|
||||
|
||||
output ad9361_resetb;
|
||||
output ad9361_en_agc;
|
||||
output ad9361_sync;
|
||||
output ad9361_enable;
|
||||
output ad9361_txnrx;
|
||||
output ad9361_resetb,
|
||||
output ad9361_en_agc,
|
||||
output ad9361_sync,
|
||||
|
||||
// spi interface
|
||||
|
||||
output spi_csn;
|
||||
output spi_clk;
|
||||
output spi_mosi;
|
||||
input spi_miso;
|
||||
|
||||
// internal clocks and resets
|
||||
|
||||
wire [ 31:0] gpio_open;
|
||||
wire sys_resetn;
|
||||
wire clk;
|
||||
output spi_csn,
|
||||
output spi_clk,
|
||||
output spi_mosi,
|
||||
input spi_miso);
|
||||
|
||||
// internal signals
|
||||
|
||||
wire adc_enable_i0;
|
||||
wire adc_enable_q0;
|
||||
wire adc_enable_i1;
|
||||
wire adc_enable_q1;
|
||||
wire adc_valid_i0;
|
||||
wire adc_valid_q0;
|
||||
wire adc_valid_i1;
|
||||
wire adc_valid_q1;
|
||||
wire adc_dwr;
|
||||
wire adc_dsync;
|
||||
wire [ 15:0] adc_chan_i0;
|
||||
wire [ 15:0] adc_chan_q0;
|
||||
wire [ 15:0] adc_chan_i1;
|
||||
wire [ 15:0] adc_chan_q1;
|
||||
wire [ 63:0] adc_ddata;
|
||||
wire adc_dovf;
|
||||
wire dac_enable_i0;
|
||||
wire dac_enable_q0;
|
||||
wire dac_enable_i1;
|
||||
wire dac_enable_q1;
|
||||
wire dac_valid_i0;
|
||||
wire dac_valid_q0;
|
||||
wire dac_valid_i1;
|
||||
wire dac_valid_q1;
|
||||
wire [ 15:0] dac_data_i0;
|
||||
wire [ 15:0] dac_data_q0;
|
||||
wire [ 15:0] dac_data_i1;
|
||||
wire [ 15:0] dac_data_q1;
|
||||
wire [ 63:0] dac_ddata;
|
||||
wire dac_dunf;
|
||||
wire dac_rd_en;
|
||||
wire dac_fifo_valid;
|
||||
wire vga_pixel_clock;
|
||||
wire vid_v_sync;
|
||||
wire vid_h_sync;
|
||||
wire [7:0] vid_r,vid_g,vid_b;
|
||||
wire sys_resetn;
|
||||
wire [ 31:0] sys_gpio_i;
|
||||
wire [ 31:0] sys_gpio_o;
|
||||
wire [ 4:0] gpio;
|
||||
|
||||
// defaults
|
||||
|
||||
assign gpio_bd_o = sys_gpio_o[3:0];
|
||||
|
||||
assign sys_gpio_i[31:8] = sys_gpio_o[31:8];
|
||||
assign sys_gpio_i[ 7:0] = gpio_bd_i;
|
||||
|
||||
assign vga_clk = vga_pixel_clock;
|
||||
assign vga_blank_n = 1'b1;
|
||||
assign vga_sync_n = 1'b0;
|
||||
assign vga_hs = vid_h_sync;
|
||||
assign vga_vs = vid_v_sync;
|
||||
assign {vga_b,vga_g,vga_r} = {vid_b,vid_g,vid_r};
|
||||
|
||||
assign ad9361_resetb = gpio[4];
|
||||
assign ad9361_en_agc = gpio[3];
|
||||
assign ad9361_sync = gpio[2];
|
||||
|
||||
// instantiations
|
||||
|
||||
sld_signaltap #(
|
||||
.sld_advanced_trigger_entity ("basic,1,"),
|
||||
.sld_data_bits (64),
|
||||
.sld_data_bit_cntr_bits (7),
|
||||
.sld_enable_advanced_trigger (0),
|
||||
.sld_mem_address_bits (10),
|
||||
.sld_node_crc_bits (32),
|
||||
.sld_node_crc_hiword (13323),
|
||||
.sld_node_crc_loword (24084),
|
||||
.sld_node_info (1076736),
|
||||
.sld_ram_block_type ("AUTO"),
|
||||
.sld_sample_depth (1024),
|
||||
.sld_storage_qualifier_gap_record (0),
|
||||
.sld_storage_qualifier_mode ("OFF"),
|
||||
.sld_trigger_bits (1),
|
||||
.sld_trigger_in_enabled (0),
|
||||
.sld_trigger_level (1),
|
||||
.sld_trigger_level_pipeline (1))
|
||||
i_ila_adc (
|
||||
.acq_clk (clk),
|
||||
.acq_data_in (adc_ddata),
|
||||
.acq_trigger_in (adc_valid_i0));
|
||||
|
||||
system_bd i_system_bd (
|
||||
.clk_clk (sys_clk),
|
||||
.reset_reset_n (sys_resetn),
|
||||
.sys_hps_memory_mem_a (ddr3_a),
|
||||
.sys_hps_memory_mem_ba (ddr3_ba),
|
||||
.sys_hps_memory_mem_ck (ddr3_ck_p),
|
||||
.sys_hps_memory_mem_ck_n (ddr3_ck_n),
|
||||
.sys_hps_memory_mem_cke (ddr3_cke),
|
||||
.sys_hps_memory_mem_cs_n (ddr3_cs_n),
|
||||
.sys_hps_memory_mem_ras_n (ddr3_ras_n),
|
||||
.sys_hps_memory_mem_cas_n (ddr3_cas_n),
|
||||
.sys_hps_memory_mem_we_n (ddr3_we_n),
|
||||
.sys_hps_memory_mem_reset_n (ddr3_reset_n),
|
||||
.sys_hps_memory_mem_dq (ddr3_dq),
|
||||
.sys_hps_memory_mem_dqs (ddr3_dqs_p),
|
||||
.sys_hps_memory_mem_dqs_n (ddr3_dqs_n),
|
||||
.sys_hps_memory_mem_odt (ddr3_odt),
|
||||
.sys_hps_memory_mem_dm (ddr3_dm),
|
||||
.sys_hps_memory_oct_rzqin (ddr3_oct_rzqin),
|
||||
.sys_hps_hps_io_hps_io_emac1_inst_TX_CLK (eth1_tx_clk),
|
||||
.sys_hps_hps_io_hps_io_emac1_inst_TXD0 (eth1_txd0),
|
||||
.sys_hps_hps_io_hps_io_emac1_inst_TXD1 (eth1_txd1),
|
||||
.sys_hps_hps_io_hps_io_emac1_inst_TXD2 (eth1_txd2),
|
||||
.sys_hps_hps_io_hps_io_emac1_inst_TXD3 (eth1_txd3),
|
||||
.sys_hps_hps_io_hps_io_emac1_inst_RXD0 (eth1_rxd0),
|
||||
.sys_hps_hps_io_hps_io_emac1_inst_MDIO (eth1_mdio),
|
||||
.sys_hps_hps_io_hps_io_emac1_inst_MDC (eth1_mdc),
|
||||
.sys_hps_hps_io_hps_io_emac1_inst_RX_CTL (eth1_rx_ctl),
|
||||
.sys_hps_hps_io_hps_io_emac1_inst_TX_CTL (eth1_tx_ctl),
|
||||
.sys_hps_hps_io_hps_io_emac1_inst_RX_CLK (eth1_rx_clk),
|
||||
.sys_hps_hps_io_hps_io_emac1_inst_RXD1 (eth1_rxd1),
|
||||
.sys_hps_hps_io_hps_io_emac1_inst_RXD2 (eth1_rxd2),
|
||||
.sys_hps_hps_io_hps_io_emac1_inst_RXD3 (eth1_rxd3),
|
||||
.sys_hps_hps_io_hps_io_qspi_inst_IO0 (qspi_io0),
|
||||
.sys_hps_hps_io_hps_io_qspi_inst_IO1 (qspi_io1),
|
||||
.sys_hps_hps_io_hps_io_qspi_inst_IO2 (qspi_io2),
|
||||
.sys_hps_hps_io_hps_io_qspi_inst_IO3 (qspi_io3),
|
||||
.sys_hps_hps_io_hps_io_qspi_inst_SS0 (qspi_ss0),
|
||||
.sys_hps_hps_io_hps_io_qspi_inst_CLK (qspi_clk),
|
||||
.sys_hps_hps_io_hps_io_sdio_inst_CMD (sdio_cmd),
|
||||
.sys_hps_hps_io_hps_io_sdio_inst_D0 (sdio_d0),
|
||||
.sys_hps_hps_io_hps_io_sdio_inst_D1 (sdio_d1),
|
||||
.sys_hps_hps_io_hps_io_sdio_inst_CLK (sdio_clk),
|
||||
.sys_hps_hps_io_hps_io_sdio_inst_D2 (sdio_d2),
|
||||
.sys_hps_hps_io_hps_io_sdio_inst_D3 (sdio_d3),
|
||||
.sys_hps_hps_io_hps_io_usb1_inst_D0 (usb1_d0),
|
||||
.sys_hps_hps_io_hps_io_usb1_inst_D1 (usb1_d1),
|
||||
.sys_hps_hps_io_hps_io_usb1_inst_D2 (usb1_d2),
|
||||
.sys_hps_hps_io_hps_io_usb1_inst_D3 (usb1_d3),
|
||||
.sys_hps_hps_io_hps_io_usb1_inst_D4 (usb1_d4),
|
||||
.sys_hps_hps_io_hps_io_usb1_inst_D5 (usb1_d5),
|
||||
.sys_hps_hps_io_hps_io_usb1_inst_D6 (usb1_d6),
|
||||
.sys_hps_hps_io_hps_io_usb1_inst_D7 (usb1_d7),
|
||||
.sys_hps_hps_io_hps_io_usb1_inst_CLK (usb1_clk),
|
||||
.sys_hps_hps_io_hps_io_usb1_inst_STP (usb1_stp),
|
||||
.sys_hps_hps_io_hps_io_usb1_inst_DIR (usb1_dir),
|
||||
.sys_hps_hps_io_hps_io_usb1_inst_NXT (usb1_nxt),
|
||||
.sys_hps_hps_io_hps_io_spim1_inst_CLK (spim1_clk),
|
||||
.sys_hps_hps_io_hps_io_spim1_inst_MOSI (spim1_mosi),
|
||||
.sys_hps_hps_io_hps_io_spim1_inst_MISO (spim1_miso),
|
||||
.sys_hps_hps_io_hps_io_spim1_inst_SS0 (spim1_ss0),
|
||||
.sys_hps_hps_io_hps_io_uart0_inst_RX (uart0_rx),
|
||||
.sys_hps_hps_io_hps_io_uart0_inst_TX (uart0_tx),
|
||||
.sys_gpio_external_connection_in_port ({16'd0, 4'd0, led, push_buttons, dip_switches}),
|
||||
.sys_gpio_external_connection_out_port ({gpio_open[31:16], gpio_open[15:12], led, gpio_open[7:0]}),
|
||||
.sys_hps_h2f_reset_reset_n (sys_resetn),
|
||||
.sys_hps_spim0_txd (),
|
||||
.sys_hps_spim0_rxd (),
|
||||
.sys_hps_spim0_ss_in_n (1'b1),
|
||||
.sys_hps_spim0_ssi_oe_n (),
|
||||
.sys_hps_spim0_ss_0_n (),
|
||||
.sys_hps_spim0_ss_1_n (),
|
||||
.sys_hps_spim0_ss_2_n (),
|
||||
.sys_hps_spim0_ss_3_n (),
|
||||
.sys_hps_spim0_sclk_out_clk (),
|
||||
.axi_ad9361_device_clock_clk (clk),
|
||||
.axi_ad9361_delay_clk_clk (1'd0),
|
||||
.axi_ad9361_device_if_rx_clk_in_p (rx_clk_in),
|
||||
.axi_ad9361_device_if_rx_clk_in_n (1'b0),
|
||||
.axi_ad9361_device_if_rx_clk_in_n (1'd0),
|
||||
.axi_ad9361_device_if_rx_frame_in_p (rx_frame_in),
|
||||
.axi_ad9361_device_if_rx_frame_in_n (1'b0),
|
||||
.axi_ad9361_device_if_rx_frame_in_n (1'd0),
|
||||
.axi_ad9361_device_if_rx_data_in_p (rx_data_in),
|
||||
.axi_ad9361_device_if_rx_data_in_n (6'd0),
|
||||
.axi_ad9361_device_if_tx_clk_out_p (tx_clk_out),
|
||||
|
|
@ -422,23 +182,90 @@ module system_top (
|
|||
.axi_ad9361_device_if_tx_frame_out_n (),
|
||||
.axi_ad9361_device_if_tx_data_out_p (tx_data_out),
|
||||
.axi_ad9361_device_if_tx_data_out_n (),
|
||||
.axi_ad9361_l_clk_clk (clk),
|
||||
.spi_ad9361_external_MISO (spi_miso),
|
||||
.spi_ad9361_external_MOSI (spi_mosi),
|
||||
.spi_ad9361_external_SCLK (spi_clk),
|
||||
.spi_ad9361_external_SS_n (spi_csn),
|
||||
.vga_pixel_clock_bridge_out_clk_clk (vga_pixel_clock),
|
||||
.vga_clock_video_output_clocked_video_vid_clk (vga_pixel_clock),
|
||||
.vga_clock_video_output_clocked_video_vid_data ({vid_r,vid_g,vid_b}),
|
||||
.vga_clock_video_output_clocked_video_underflow (),
|
||||
.vga_clock_video_output_clocked_video_vid_datavalid (),
|
||||
.vga_clock_video_output_clocked_video_vid_v_sync (vid_v_sync),
|
||||
.vga_clock_video_output_clocked_video_vid_h_sync (vid_h_sync),
|
||||
.vga_clock_video_output_clocked_video_vid_f (),
|
||||
.vga_clock_video_output_clocked_video_vid_h (),
|
||||
.vga_clock_video_output_clocked_video_vid_v (),
|
||||
.gpio_external_connection_export ({ad9361_resetb, ad9361_en_agc, ad9361_sync, ad9361_enable, ad9361_txnrx})
|
||||
);
|
||||
.axi_ad9361_device_if_enable (enable),
|
||||
.axi_ad9361_device_if_txnrx (txnrx),
|
||||
.axi_ad9361_up_enable_up_enable (gpio[1]),
|
||||
.axi_ad9361_up_txnrx_up_txnrx (gpio[0]),
|
||||
.gpio_export (gpio),
|
||||
.spi_MISO (spi_miso),
|
||||
.spi_MOSI (spi_mosi),
|
||||
.spi_SCLK (spi_clk),
|
||||
.spi_SS_n (spi_csn),
|
||||
.sys_clk_clk (sys_clk),
|
||||
.sys_gpio_in_port (sys_gpio_i),
|
||||
.sys_gpio_out_port (sys_gpio_o),
|
||||
.sys_hps_io_hps_io_emac1_inst_TX_CLK (eth1_tx_clk),
|
||||
.sys_hps_io_hps_io_emac1_inst_TXD0 (eth1_tx_d[0]),
|
||||
.sys_hps_io_hps_io_emac1_inst_TXD1 (eth1_tx_d[1]),
|
||||
.sys_hps_io_hps_io_emac1_inst_TXD2 (eth1_tx_d[2]),
|
||||
.sys_hps_io_hps_io_emac1_inst_TXD3 (eth1_tx_d[3]),
|
||||
.sys_hps_io_hps_io_emac1_inst_RXD0 (eth1_rx_d[0]),
|
||||
.sys_hps_io_hps_io_emac1_inst_MDIO (eth1_mdio),
|
||||
.sys_hps_io_hps_io_emac1_inst_MDC (eth1_mdc),
|
||||
.sys_hps_io_hps_io_emac1_inst_RX_CTL (eth1_rx_ctl),
|
||||
.sys_hps_io_hps_io_emac1_inst_TX_CTL (eth1_tx_ctl),
|
||||
.sys_hps_io_hps_io_emac1_inst_RX_CLK (eth1_rx_clk),
|
||||
.sys_hps_io_hps_io_emac1_inst_RXD1 (eth1_rx_d[1]),
|
||||
.sys_hps_io_hps_io_emac1_inst_RXD2 (eth1_rx_d[2]),
|
||||
.sys_hps_io_hps_io_emac1_inst_RXD3 (eth1_rx_d[3]),
|
||||
.sys_hps_io_hps_io_qspi_inst_IO0 (qspi_io[0]),
|
||||
.sys_hps_io_hps_io_qspi_inst_IO1 (qspi_io[1]),
|
||||
.sys_hps_io_hps_io_qspi_inst_IO2 (qspi_io[2]),
|
||||
.sys_hps_io_hps_io_qspi_inst_IO3 (qspi_io[3]),
|
||||
.sys_hps_io_hps_io_qspi_inst_SS0 (qspi_ss0),
|
||||
.sys_hps_io_hps_io_qspi_inst_CLK (qspi_clk),
|
||||
.sys_hps_io_hps_io_sdio_inst_CMD (sdio_cmd),
|
||||
.sys_hps_io_hps_io_sdio_inst_D0 (sdio_d[0]),
|
||||
.sys_hps_io_hps_io_sdio_inst_D1 (sdio_d[1]),
|
||||
.sys_hps_io_hps_io_sdio_inst_CLK (sdio_clk),
|
||||
.sys_hps_io_hps_io_sdio_inst_D2 (sdio_d[2]),
|
||||
.sys_hps_io_hps_io_sdio_inst_D3 (sdio_d[3]),
|
||||
.sys_hps_io_hps_io_usb1_inst_D0 (usb1_d[0]),
|
||||
.sys_hps_io_hps_io_usb1_inst_D1 (usb1_d[1]),
|
||||
.sys_hps_io_hps_io_usb1_inst_D2 (usb1_d[2]),
|
||||
.sys_hps_io_hps_io_usb1_inst_D3 (usb1_d[3]),
|
||||
.sys_hps_io_hps_io_usb1_inst_D4 (usb1_d[4]),
|
||||
.sys_hps_io_hps_io_usb1_inst_D5 (usb1_d[5]),
|
||||
.sys_hps_io_hps_io_usb1_inst_D6 (usb1_d[6]),
|
||||
.sys_hps_io_hps_io_usb1_inst_D7 (usb1_d[7]),
|
||||
.sys_hps_io_hps_io_usb1_inst_CLK (usb1_clk),
|
||||
.sys_hps_io_hps_io_usb1_inst_STP (usb1_stp),
|
||||
.sys_hps_io_hps_io_usb1_inst_DIR (usb1_dir),
|
||||
.sys_hps_io_hps_io_usb1_inst_NXT (usb1_nxt),
|
||||
.sys_hps_io_hps_io_spim1_inst_CLK (spim1_clk),
|
||||
.sys_hps_io_hps_io_spim1_inst_MOSI (spim1_mosi),
|
||||
.sys_hps_io_hps_io_spim1_inst_MISO (spim1_miso),
|
||||
.sys_hps_io_hps_io_spim1_inst_SS0 (spim1_ss0),
|
||||
.sys_hps_io_hps_io_uart0_inst_RX (uart0_rx),
|
||||
.sys_hps_io_hps_io_uart0_inst_TX (uart0_tx),
|
||||
.sys_hps_mem_mem_a (ddr3_a),
|
||||
.sys_hps_mem_mem_ba (ddr3_ba),
|
||||
.sys_hps_mem_mem_ck (ddr3_ck_p),
|
||||
.sys_hps_mem_mem_ck_n (ddr3_ck_n),
|
||||
.sys_hps_mem_mem_cke (ddr3_cke),
|
||||
.sys_hps_mem_mem_cs_n (ddr3_cs_n),
|
||||
.sys_hps_mem_mem_ras_n (ddr3_ras_n),
|
||||
.sys_hps_mem_mem_cas_n (ddr3_cas_n),
|
||||
.sys_hps_mem_mem_we_n (ddr3_we_n),
|
||||
.sys_hps_mem_mem_reset_n (ddr3_reset_n),
|
||||
.sys_hps_mem_mem_dq (ddr3_dq),
|
||||
.sys_hps_mem_mem_dqs (ddr3_dqs_p),
|
||||
.sys_hps_mem_mem_dqs_n (ddr3_dqs_n),
|
||||
.sys_hps_mem_mem_odt (ddr3_odt),
|
||||
.sys_hps_mem_mem_dm (ddr3_dm),
|
||||
.sys_hps_mem_oct_rzqin (ddr3_rzq),
|
||||
.sys_hps_reset_reset_n (sys_resetn),
|
||||
.sys_reset_reset_n (sys_resetn),
|
||||
.vga_clk_clk (vga_clk),
|
||||
.vga_if_vid_clk (vga_clk),
|
||||
.vga_if_vid_data ({vga_red, vga_grn, vga_blu}),
|
||||
.vga_if_underflow (),
|
||||
.vga_if_vid_datavalid (),
|
||||
.vga_if_vid_v_sync (vga_vsync),
|
||||
.vga_if_vid_h_sync (vga_hsync),
|
||||
.vga_if_vid_f (),
|
||||
.vga_if_vid_h (),
|
||||
.vga_if_vid_v ());
|
||||
|
||||
endmodule
|
||||
|
||||
|
|
|
|||
|
|
@ -9,19 +9,11 @@
|
|||
categories="System" />
|
||||
<parameter name="bonusData"><![CDATA[bonusData
|
||||
{
|
||||
element ad9361_clk_bridge
|
||||
{
|
||||
datum _sortIndex
|
||||
{
|
||||
value = "4";
|
||||
type = "int";
|
||||
}
|
||||
}
|
||||
element adc_pack
|
||||
{
|
||||
datum _sortIndex
|
||||
{
|
||||
value = "6";
|
||||
value = "5";
|
||||
type = "int";
|
||||
}
|
||||
datum sopceditor_expanded
|
||||
|
|
@ -90,7 +82,7 @@
|
|||
{
|
||||
datum _sortIndex
|
||||
{
|
||||
value = "5";
|
||||
value = "4";
|
||||
type = "int";
|
||||
}
|
||||
datum sopceditor_expanded
|
||||
|
|
@ -111,7 +103,7 @@
|
|||
{
|
||||
datum _sortIndex
|
||||
{
|
||||
value = "7";
|
||||
value = "6";
|
||||
type = "int";
|
||||
}
|
||||
datum sopceditor_expanded
|
||||
|
|
@ -132,7 +124,7 @@
|
|||
{
|
||||
datum _sortIndex
|
||||
{
|
||||
value = "9";
|
||||
value = "8";
|
||||
type = "int";
|
||||
}
|
||||
datum sopceditor_expanded
|
||||
|
|
@ -153,7 +145,7 @@
|
|||
{
|
||||
datum _sortIndex
|
||||
{
|
||||
value = "8";
|
||||
value = "7";
|
||||
type = "int";
|
||||
}
|
||||
datum sopceditor_expanded
|
||||
|
|
@ -166,7 +158,7 @@
|
|||
{
|
||||
datum _sortIndex
|
||||
{
|
||||
value = "11";
|
||||
value = "10";
|
||||
type = "int";
|
||||
}
|
||||
}
|
||||
|
|
@ -190,7 +182,7 @@
|
|||
{
|
||||
datum _sortIndex
|
||||
{
|
||||
value = "10";
|
||||
value = "9";
|
||||
type = "int";
|
||||
}
|
||||
datum sopceditor_expanded
|
||||
|
|
@ -245,25 +237,31 @@
|
|||
<parameter name="useTestBenchNamingPattern" value="false" />
|
||||
<instanceScript></instanceScript>
|
||||
<interface
|
||||
name="axi_ad9361_device_clock"
|
||||
internal="axi_ad9361.device_clock"
|
||||
name="axi_ad9361_delay_clk"
|
||||
internal="axi_ad9361.if_delay_clk"
|
||||
type="clock"
|
||||
dir="end" />
|
||||
<interface name="axi_ad9361_device_clock" internal="axi_ad9361.device_clock" />
|
||||
<interface
|
||||
name="axi_ad9361_device_if"
|
||||
internal="axi_ad9361.device_if"
|
||||
type="conduit"
|
||||
dir="end" />
|
||||
<interface
|
||||
name="axi_ad9361_l_clk"
|
||||
internal="ad9361_clk_bridge.out_clk"
|
||||
type="clock"
|
||||
dir="start" />
|
||||
<interface
|
||||
name="axi_ad9361_s_axi"
|
||||
internal="axi_ad9361.s_axi"
|
||||
type="axi4lite"
|
||||
dir="end" />
|
||||
<interface
|
||||
name="axi_ad9361_up_enable"
|
||||
internal="axi_ad9361.if_up_enable"
|
||||
type="conduit"
|
||||
dir="end" />
|
||||
<interface
|
||||
name="axi_ad9361_up_txnrx"
|
||||
internal="axi_ad9361.if_up_txnrx"
|
||||
type="conduit"
|
||||
dir="end" />
|
||||
<interface
|
||||
name="axi_dmac_adc_fifo_wr_clock"
|
||||
internal="axi_dmac_adc.fifo_wr_clock" />
|
||||
|
|
@ -327,21 +325,16 @@
|
|||
dir="end" />
|
||||
<interface name="sys_clk" internal="sys_clk.in_clk" type="clock" dir="end" />
|
||||
<interface name="sys_rst" internal="sys_rst.in_reset" type="reset" dir="end" />
|
||||
<module
|
||||
name="ad9361_clk_bridge"
|
||||
kind="altera_clock_bridge"
|
||||
version="15.1"
|
||||
enabled="1">
|
||||
<parameter name="DERIVED_CLOCK_RATE" value="0" />
|
||||
<parameter name="EXPLICIT_CLOCK_RATE" value="0" />
|
||||
<parameter name="NUM_CLOCK_OUTPUTS" value="1" />
|
||||
</module>
|
||||
<module name="adc_pack" kind="util_cpack" version="1.0" enabled="1">
|
||||
<parameter name="CHANNEL_DATA_WIDTH" value="16" />
|
||||
<parameter name="NUM_OF_CHANNELS" value="4" />
|
||||
</module>
|
||||
<module name="axi_ad9361" kind="axi_ad9361" version="1.0" enabled="1">
|
||||
<parameter name="DEVICE_TYPE" value="0" />
|
||||
<parameter name="ADC_DATAPATH_DISABLE" value="0" />
|
||||
<parameter name="CMOS_OR_LVDS_N" value="0" />
|
||||
<parameter name="DAC_DATAPATH_DISABLE" value="0" />
|
||||
<parameter name="DEVICE_FAMILY" value="Cyclone V" />
|
||||
<parameter name="DEVICE_TYPE" value="1" />
|
||||
<parameter name="ID" value="0" />
|
||||
</module>
|
||||
<module name="axi_dmac_adc" kind="axi_dmac" version="1.0" enabled="1">
|
||||
|
|
@ -441,6 +434,11 @@
|
|||
version="15.1"
|
||||
start="axi_ad9361.if_l_clk"
|
||||
end="adc_pack.if_adc_clk" />
|
||||
<connection
|
||||
kind="clock"
|
||||
version="15.1"
|
||||
start="axi_ad9361.if_l_clk"
|
||||
end="axi_ad9361.if_clk" />
|
||||
<connection
|
||||
kind="clock"
|
||||
version="15.1"
|
||||
|
|
@ -456,22 +454,12 @@
|
|||
version="15.1"
|
||||
start="axi_ad9361.if_l_clk"
|
||||
end="axi_dmac_adc.if_fifo_wr_clk" />
|
||||
<connection
|
||||
kind="clock"
|
||||
version="15.1"
|
||||
start="axi_ad9361.if_l_clk"
|
||||
end="ad9361_clk_bridge.in_clk" />
|
||||
<connection
|
||||
kind="clock"
|
||||
version="15.1"
|
||||
start="sys_clk.out_clk"
|
||||
end="spi_ad9361.clk" />
|
||||
<connection kind="clock" version="15.1" start="sys_clk.out_clk" end="gpio.clk" />
|
||||
<connection
|
||||
kind="clock"
|
||||
version="15.1"
|
||||
start="sys_clk.out_clk"
|
||||
end="axi_ad9361.delay_clock" />
|
||||
<connection
|
||||
kind="clock"
|
||||
version="15.1"
|
||||
|
|
|
|||
Loading…
Reference in New Issue