axi_dmac: Control s_axis_user/fifo_wr_sync validity
The ports s_axis_user or fifo_wr_sync will be active just if the SYNC_TRANSFER_START is enabled.main
parent
899b8436ad
commit
0064004d34
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@ -333,9 +333,6 @@ ad_alt_intf signal s_axis_ready output 1 ready
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ad_alt_intf signal s_axis_xfer_req output 1 xfer_req
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ad_alt_intf signal s_axis_user input 1 user
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set_port_property s_axis_user termination true
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set_port_property s_axis_user termination_value 1
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# fifo destination/source
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ad_alt_intf clock fifo_rd_clk input 1 clk
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@ -386,6 +383,12 @@ proc axi_dmac_elaborate {} {
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if_s_axis_xfer_req if_s_axis_user
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}
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if {[get_parameter_value DMA_TYPE_SRC] == 1 &&
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[get_parameter_value SYNC_TRANSFER_START] == 0} {
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set_port_property s_axis_user termination true
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set_port_property s_axis_user termination_value 1
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}
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# fifo destination/source
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if {[get_parameter_value DMA_TYPE_DEST] != 2} {
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@ -400,6 +403,12 @@ proc axi_dmac_elaborate {} {
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if_fifo_wr_sync if_fifo_wr_xfer_req
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}
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if {[get_parameter_value DMA_TYPE_SRC] == 2 &&
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[get_parameter_value SYNC_TRANSFER_START] == 0} {
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set_port_property fifo_wr_sync termination true
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set_port_property fifo_wr_sync termination_value 1
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}
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foreach intf $disabled_intfs {
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set_interface_property $intf ENABLED false
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}
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