zcy
/
pluto_hdl_adi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

common/ad_iqcor: process multiple samples per clock cycle

main
Laszlo Nagy 2020-03-06 13:20:25 +00:00 committed by Laszlo Nagy
parent 341221dc91
commit 007d03c034
1 changed files with 57 additions and 39 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

96
library/common/ad_iqcor.v
View File

@ -36,6 +36,8 @@
// if SCALE_ONLY is set to 1, b*(q+y) is set to 0, and the module is used for
// scale correction of channel I
// Assumption CR smaller or equal to 16
`timescale 1ns/100ps
module ad_iqcor #(
@ -44,43 +46,36 @@ module ad_iqcor #(
parameter Q_OR_I_N = 0,
parameter SCALE_ONLY = 0,
parameter DISABLE = 0) (
parameter DISABLE = 0,
parameter CR = 16, // Converter Resolution
parameter DPW = 1 // Data Path Width
) (
// data interface
input clk,
input valid,
input [15:0] data_in,
input [15:0] data_iq,
input [DPW*CR-1:0] data_in,
input [DPW*CR-1:0] data_iq,
output valid_out,
output [15:0] data_out,
output [DPW*CR-1:0] data_out,
// control interface
input iqcor_enable,
input [15:0] iqcor_coeff_1,
input [15:0] iqcor_coeff_2);
input [15:0] iqcor_coeff_2
);
// internal registers
reg p1_valid = 'd0;
reg [33:0] p1_data_p = 'd0;
reg valid_int = 'd0;
reg [15:0] data_int = 'd0;
reg [15:0] iqcor_coeff_1_r = 'd0;
reg [15:0] iqcor_coeff_2_r = 'd0;
// internal signals
wire [DPW-1:0] valid_int_loc;
wire [DPW*CR-1:0] data_int_loc;
wire [15:0] data_i_s;
wire [15:0] data_q_s;
wire [33:0] p1_data_p_i_s;
wire p1_valid_s;
wire [15:0] p1_data_i_s;
wire [33:0] p1_data_p_q_s;
wire [15:0] p1_data_q_s;
wire [15:0] p1_data_i_int;
wire [15:0] p1_data_q_int;
// data-path disable
@ -89,15 +84,11 @@ module ad_iqcor #(
assign valid_out = valid;
assign data_out = data_in;
end else begin
assign valid_out = valid_int;
assign data_out = data_int;
assign valid_out = valid_int_loc;
assign data_out = data_int_loc;
end
endgenerate
// swap i & q
assign data_i_s = (Q_OR_I_N == 1 && SCALE_ONLY == 1'b0) ? data_iq : data_in;
assign data_q_s = (Q_OR_I_N == 1) ? data_in : data_iq;
// coefficients are flopped to remove warnings from vivado
@ -106,63 +97,85 @@ module ad_iqcor #(
iqcor_coeff_2_r <= iqcor_coeff_2;
end
genvar i;
generate
for (i=0; i<DPW; i=i+1) begin
wire [CR-1:0] data_i_s;
wire [CR-1:0] data_q_s;
wire [CR-1:0] p1_data_i_s;
wire p1_valid_s;
wire [33:0] p1_data_p_i_s;
wire [33:0] p1_data_p_q_s;
wire [CR-1:0] p1_data_q_s;
wire [CR-1:0] p1_data_i_int;
wire [CR-1:0] p1_data_q_int;
reg p1_valid = 'd0;
reg [33:0] p1_data_p = 'd0;
reg valid_int = 'd0;
reg [15:0] data_int = 'd0;
// swap i & q
assign data_i_s = (Q_OR_I_N == 1 && SCALE_ONLY == 1'b0) ? data_iq[i*CR+:CR] : data_in[i*CR+:CR];
assign data_q_s = (Q_OR_I_N == 1) ? data_in[i*CR+:CR] : data_iq[i*CR+:CR];
// scaling functions - i
ad_mul #(.DELAY_DATA_WIDTH(17)) i_mul_i (
ad_mul #(.DELAY_DATA_WIDTH(CR+1)) i_mul_i (
.clk (clk),
.data_a ({data_i_s[15], data_i_s}),
.data_a ({data_i_s[CR-1], data_i_s, {16-CR{1'b0}}}),
.data_b ({iqcor_coeff_1_r[15], iqcor_coeff_1_r}),
.data_p (p1_data_p_i_s),
.ddata_in ({valid, data_i_s}),
.ddata_out ({p1_valid_s, p1_data_i_s}));
generate
if (SCALE_ONLY == 0) begin
// scaling functions - q
ad_mul #(.DELAY_DATA_WIDTH(16)) i_mul_q (
ad_mul #(.DELAY_DATA_WIDTH(CR)) i_mul_q (
.clk (clk),
.data_a ({data_q_s[15], data_q_s}),
.data_a ({data_q_s[CR-1], data_q_s, {16-CR{1'b0}}}),
.data_b ({iqcor_coeff_2_r[15], iqcor_coeff_2_r}),
.data_p (p1_data_p_q_s),
.ddata_in (data_q_s),
.ddata_out (p1_data_q_s));
// sum
end else begin
assign p1_data_p_q_s = 34'h0;
assign p1_data_q_s = 16'h0;
assign p1_data_q_s = {CR{1'b0}};
end
endgenerate
generate
if (Q_OR_I_N == 1 && SCALE_ONLY == 0) begin
reg [15:0] p1_data_q = 'd0;
reg [CR-1:0] p1_data_q = 'd0;
always @(posedge clk) begin
p1_data_q <= p1_data_q_s;
end
assign p1_data_i_int = 16'h0;
assign p1_data_i_int = {CR{1'b0}};
assign p1_data_q_int = p1_data_q;
// sum
end else begin
reg [15:0] p1_data_i = 'd0;
reg [CR-1:0] p1_data_i = 'd0;
always @(posedge clk) begin
p1_data_i <= p1_data_i_s;
end
assign p1_data_i_int = p1_data_i;
assign p1_data_q_int = 16'h0;
assign p1_data_q_int = {CR{1'b0}};
end
endgenerate
always @(posedge clk) begin
p1_valid <= p1_valid_s;
p1_data_p <= p1_data_p_i_s + p1_data_p_q_s;
end
// output registers
always @(posedge clk) begin
@ -175,7 +188,12 @@ module ad_iqcor #(
data_int <= p1_data_i_int;
end
end
assign valid_int_loc[i] = valid_int;
assign data_int_loc[i*CR+:CR] = data_int[15-:CR];
end
endgenerate
endmodule