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fmcomms2_ALL: Preserve backward compatibility for ENABLE/TXNRX control 

By default the ENABLE/TXNRX pins are controlled by GPIOs, if the TDD module is enabled, the TDD FSM will take over the control of these two pins.
main
Istvan Csomortani 2015-07-01 13:54:01 +03:00
parent a497dcabb5
commit 0102e3e02c
15 changed files with 368 additions and 236 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
projects/fmcomms2/ac701/system_constr.xdc
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@ -50,8 +50,9 @@ set_property -dict {PACKAGE_PIN F22 IOSTANDARD LVCMOS25} [get_ports gpio_ctl[
set_property -dict {PACKAGE_PIN M14 IOSTANDARD LVCMOS25} [get_ports gpio_en_agc] ; ## H22 FMC_LPC_LA19_P
set_property -dict {PACKAGE_PIN L14 IOSTANDARD LVCMOS25} [get_ports gpio_sync] ; ## H23 FMC_LPC_LA19_N
set_property -dict {PACKAGE_PIN K22 IOSTANDARD LVCMOS25} [get_ports gpio_resetb] ; ## H31 FMC_LPC_LA28_P
set_property -dict {PACKAGE_PIN E21 IOSTANDARD LVCMOS25} [get_ports gpio_enable] ; ## G18 FMC_LPC_LA16_P
set_property -dict {PACKAGE_PIN D21 IOSTANDARD LVCMOS25} [get_ports gpio_txnrx] ; ## G19 FMC_LPC_LA16_N
set_property -dict {PACKAGE_PIN E21 IOSTANDARD LVCMOS25} [get_ports enable] ; ## G18 FMC_LPC_LA16_P
set_property -dict {PACKAGE_PIN D21 IOSTANDARD LVCMOS25} [get_ports txnrx] ; ## G19 FMC_LPC_LA16_N
set_property -dict {PACKAGE_PIN J24 IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports spi_csn_0] ; ## D26 FMC_LPC_LA26_P
set_property -dict {PACKAGE_PIN H24 IOSTANDARD LVCMOS25} [get_ports spi_clk] ; ## D27 FMC_LPC_LA26_N

24
projects/fmcomms2/ac701/system_top.v
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@ -97,8 +97,9 @@ module system_top (
tx_data_out_p,
tx_data_out_n,
gpio_txnrx,
gpio_enable,
txnrx,
enable,
gpio_resetb,
gpio_sync,
gpio_en_agc,
@ -167,8 +168,9 @@ module system_top (
output [ 5:0] tx_data_out_p;
output [ 5:0] tx_data_out_n;
inout gpio_txnrx;
inout gpio_enable;
output txnrx;
output enable;
inout gpio_resetb;
inout gpio_sync;
inout gpio_en_agc;
@ -190,12 +192,21 @@ module system_top (
wire spi_mosi;
wire spi_miso;
wire tdd_enable_s;
wire gpio_enable;
wire gpio_txnrx;
wire enable_s;
wire txnrx_s;
// assignments
assign fan_pwm = 1'b1;
assign iic_rstn = 1'b1;
assign spi_csn_0 = spi_csn[0];
assign enable = (tdd_enable_s == 1'b1) ? enable_s : gpio_enable;
assign txnrx = (tdd_enable_s == 1'b1) ? txnrx_s : gpio_txnrx;
// instantiations
ad_iobuf #(.DATA_WIDTH(17)) i_iobuf (
@ -278,7 +289,10 @@ module system_top (
.tx_frame_out_n (tx_frame_out_n),
.tx_frame_out_p (tx_frame_out_p),
.uart_sin (uart_sin),
.uart_sout (uart_sout));
.uart_sout (uart_sout),
.enable (enable_s),
.txnrx (txnrx_s),
.tdd_enable (tdd_enable_s));
endmodule

19
projects/fmcomms2/common/fmcomms2_bd.tcl
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@ -17,6 +17,7 @@ create_bd_port -dir O -from 5 -to 0 tx_data_out_n
create_bd_port -dir O enable
create_bd_port -dir O txnrx
create_bd_port -dir O tdd_enable
# ad9361 core
@ -135,6 +136,7 @@ ad_connect util_ad9361_dac_upack/dac_data_3 axi_ad9361/dac_data_q1
ad_connect util_ad9361_dac_upack/dac_valid axi_ad9361_dac_dma/fifo_rd_en
ad_connect util_ad9361_dac_upack/dac_data axi_ad9361_dac_dma/fifo_rd_dout
ad_connect axi_ad9361_dac_dma/fifo_rd_underflow axi_ad9361/dac_dunf
ad_connect tdd_enable axi_ad9361/tdd_enable
# interconnects
@ -173,3 +175,20 @@ ad_connect util_ad9361_adc_fifo/dout_data_3 ila_adc/probe3
ad_connect util_ad9361_adc_fifo/dout_valid_0 ila_adc/probe4
ad_connect sys_cpu_clk ila_adc/clk
# ila (tdd)
set ila_tdd [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:5.0 ila_tdd]
set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_tdd
set_property -dict [list CONFIG.C_TRIGIN_EN {false}] $ila_tdd
set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila_tdd
set_property -dict [list CONFIG.C_NUM_OF_PROBES {4}] $ila_tdd
set_property -dict [list CONFIG.C_PROBE0_WIDTH {1}] $ila_adc
set_property -dict [list CONFIG.C_PROBE1_WIDTH {1}] $ila_adc
set_property -dict [list CONFIG.C_PROBE2_WIDTH {1}] $ila_adc
set_property -dict [list CONFIG.C_PROBE3_WIDTH {35}] $ila_adc
ad_connect axi_ad9361_clk ila_tdd/clk
ad_connect axi_ad9361/enable ila_tdd/probe0
ad_connect axi_ad9361/txnrx ila_tdd/probe1
ad_connect axi_ad9361/tdd_enable ila_tdd/probe2
ad_connect axi_ad9361/tdd_dbg ila_tdd/probe3

5
projects/fmcomms2/kc705/system_constr.xdc
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@ -50,8 +50,9 @@ set_property -dict {PACKAGE_PIN AD26 IOSTANDARD LVCMOS25} [get_ports gpio_ctl
set_property -dict {PACKAGE_PIN AJ26 IOSTANDARD LVCMOS25} [get_ports gpio_en_agc] ; ## H22 FMC_LPC_LA19_P
set_property -dict {PACKAGE_PIN AK26 IOSTANDARD LVCMOS25} [get_ports gpio_sync] ; ## H23 FMC_LPC_LA19_N
set_property -dict {PACKAGE_PIN AE30 IOSTANDARD LVCMOS25} [get_ports gpio_resetb] ; ## H31 FMC_LPC_LA28_P
set_property -dict {PACKAGE_PIN AC22 IOSTANDARD LVCMOS25} [get_ports gpio_enable] ; ## G18 FMC_LPC_LA16_P
set_property -dict {PACKAGE_PIN AD22 IOSTANDARD LVCMOS25} [get_ports gpio_txnrx] ; ## G19 FMC_LPC_LA16_N
set_property -dict {PACKAGE_PIN AC22 IOSTANDARD LVCMOS25} [get_ports enable] ; ## G18 FMC_LPC_LA16_P
set_property -dict {PACKAGE_PIN AD22 IOSTANDARD LVCMOS25} [get_ports txnrx] ; ## G19 FMC_LPC_LA16_N
set_property -dict {PACKAGE_PIN AK29 IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports spi_csn_0] ; ## D26 FMC_LPC_LA26_P
set_property -dict {PACKAGE_PIN AK30 IOSTANDARD LVCMOS25} [get_ports spi_clk] ; ## D27 FMC_LPC_LA26_N

24
projects/fmcomms2/kc705/system_top.v
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@ -109,8 +109,9 @@ module system_top (
tx_data_out_p,
tx_data_out_n,
gpio_txnrx,
gpio_enable,
txnrx,
enable,
gpio_resetb,
gpio_sync,
gpio_en_agc,
@ -191,8 +192,9 @@ module system_top (
output [ 5:0] tx_data_out_p;
output [ 5:0] tx_data_out_n;
inout gpio_txnrx;
inout gpio_enable;
output txnrx;
output enable;
inout gpio_resetb;
inout gpio_sync;
inout gpio_en_agc;
@ -214,6 +216,12 @@ module system_top (
wire spi_mosi;
wire spi_miso;
wire tdd_enable_s;
wire gpio_enable;
wire gpio_txnrx;
wire enable_s;
wire txnrx_s;
// default logic
assign ddr3_1_p = 2'b11;
@ -222,6 +230,9 @@ module system_top (
assign iic_rstn = 1'b1;
assign spi_csn_0 = spi_csn[0];
assign enable = (tdd_enable_s == 1'b1) ? enable_s : gpio_enable;
assign txnrx = (tdd_enable_s == 1'b1) ? txnrx_s : gpio_txnrx;
// instantiations
ad_iobuf #(.DATA_WIDTH(17)) i_iobuf (
@ -314,7 +325,10 @@ module system_top (
.tx_frame_out_n (tx_frame_out_n),
.tx_frame_out_p (tx_frame_out_p),
.uart_sin (uart_sin),
.uart_sout (uart_sout));
.uart_sout (uart_sout),
.enable (enable_s),
.txnrx (txnrx_s),
.tdd_enable (tdd_enable_s));
endmodule

4
projects/fmcomms2/mitx045/system_constr.xdc
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@ -50,8 +50,8 @@ set_property -dict {PACKAGE_PIN T28 IOSTANDARD LVCMOS25} [get_ports gpio_ctl
set_property -dict {PACKAGE_PIN AJ14 IOSTANDARD LVCMOS25} [get_ports gpio_en_agc] ; ## H22 FMC_LPC_LA19_P
set_property -dict {PACKAGE_PIN AJ13 IOSTANDARD LVCMOS25} [get_ports gpio_sync] ; ## H23 FMC_LPC_LA19_N
set_property -dict {PACKAGE_PIN W29 IOSTANDARD LVCMOS25} [get_ports gpio_resetb] ; ## H31 FMC_LPC_LA28_P
set_property -dict {PACKAGE_PIN AD14 IOSTANDARD LVCMOS25} [get_ports gpio_enable] ; ## G18 FMC_LPC_LA16_P
set_property -dict {PACKAGE_PIN AD13 IOSTANDARD LVCMOS25} [get_ports gpio_txnrx] ; ## G19 FMC_LPC_LA16_N
set_property -dict {PACKAGE_PIN AD14 IOSTANDARD LVCMOS25} [get_ports enable] ; ## G18 FMC_LPC_LA16_P
set_property -dict {PACKAGE_PIN AD13 IOSTANDARD LVCMOS25} [get_ports txnrx] ; ## G19 FMC_LPC_LA16_N
set_property -dict {PACKAGE_PIN W25 IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports spi_csn] ; ## D26 FMC_LPC_LA26_P
set_property -dict {PACKAGE_PIN W26 IOSTANDARD LVCMOS25} [get_ports spi_clk] ; ## D27 FMC_LPC_LA26_N

24
projects/fmcomms2/mitx045/system_top.v
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@ -96,8 +96,8 @@ module system_top (
tx_data_out_p,
tx_data_out_n,
gpio_txnrx,
gpio_enable,
txnrx,
enable,
gpio_resetb,
gpio_sync,
gpio_en_agc,
@ -164,8 +164,8 @@ module system_top (
output [ 5:0] tx_data_out_p;
output [ 5:0] tx_data_out_n;
inout gpio_txnrx;
inout gpio_enable;
output txnrx;
output enable;
inout gpio_resetb;
inout gpio_sync;
inout gpio_en_agc;
@ -183,6 +183,17 @@ module system_top (
wire [63:0] gpio_o;
wire [63:0] gpio_t;
wire tdd_enable_s;
wire gpio_enable;
wire gpio_txnrx;
wire enable_s;
wire txnrx_s;
// assignments
assign enable = (tdd_enable_s == 1'b1) ? enable_s : gpio_enable;
assign txnrx = (tdd_enable_s == 1'b1) ? txnrx_s : gpio_txnrx;
// instantiations
ad_iobuf #(.DATA_WIDTH(17)) i_iobuf (
@ -282,7 +293,10 @@ module system_top (
.tx_data_out_n (tx_data_out_n),
.tx_data_out_p (tx_data_out_p),
.tx_frame_out_n (tx_frame_out_n),
.tx_frame_out_p (tx_frame_out_p));
.tx_frame_out_p (tx_frame_out_p),
.enable (enable_s),
.txnrx (txnrx_s),
.tdd_enable (tdd_enable_s));
endmodule

23
projects/fmcomms2/rfsom/system_top.v
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@ -213,18 +213,28 @@ module system_top (
wire [63:0] gpio_o;
wire [63:0] gpio_t;
wire tdd_enable_s;
wire gpio_enable;
wire gpio_txnrx;
wire enable_s;
wire txnrx_s;
// assignments
assign hdmi_pd = 1'b0;
assign enable = (tdd_enable_s == 1'b1) ? enable_s : gpio_enable;
assign txnrx = (tdd_enable_s == 1'b1) ? txnrx_s : gpio_txnrx;
// instantiations
ad_iobuf #(.DATA_WIDTH(17)) i_iobuf (
.dio_t ({gpio_t[50:49], gpio_t[46:32]}),
.dio_i ({gpio_o[50:49], gpio_o[46:32]}),
.dio_o ({gpio_i[50:49], gpio_i[46:32]}),
ad_iobuf #(.DATA_WIDTH(21)) i_iobuf (
.dio_t ({gpio_t[51:50], gpio_t[48:32]}),
.dio_i ({gpio_o[51:50], gpio_o[48:32]}),
.dio_o ({gpio_i[51:50], gpio_i[48:32]}),
.dio_p ({ gpio_rfpwr_enable,
gpio_clksel,
gpio_txnrx,
gpio_enable,
gpio_resetb,
gpio_sync,
gpio_en_agc,
@ -253,7 +263,7 @@ module system_top (
.ddr_ras_n (ddr_ras_n),
.ddr_reset_n (ddr_reset_n),
.ddr_we_n (ddr_we_n),
.enable (enable),
.enable (enable_s),
.eth1_125mclk (),
.eth1_25mclk (),
.eth1_2m5clk (),
@ -336,7 +346,8 @@ module system_top (
.tx_data_out_p (tx_data_out_p),
.tx_frame_out_n (tx_frame_out_n),
.tx_frame_out_p (tx_frame_out_p),
.txnrx (txnrx));
.txnrx (txnrx_s),
.tdd_enable (tdd_enable_s));
endmodule

4
projects/fmcomms2/vc707/system_constr.xdc
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@ -50,8 +50,8 @@ set_property -dict {PACKAGE_PIN K30 IOSTANDARD LVCMOS18} [get_ports gpio_ctl[
set_property -dict {PACKAGE_PIN W30 IOSTANDARD LVCMOS18} [get_ports gpio_en_agc] ; ## H22 FMC_LPC_LA19_P
set_property -dict {PACKAGE_PIN W31 IOSTANDARD LVCMOS18} [get_ports gpio_sync] ; ## H23 FMC_LPC_LA19_N
set_property -dict {PACKAGE_PIN L29 IOSTANDARD LVCMOS18} [get_ports gpio_resetb] ; ## H31 FMC_LPC_LA28_P
set_property -dict {PACKAGE_PIN K37 IOSTANDARD LVCMOS18} [get_ports gpio_enable] ; ## G18 FMC_LPC_LA16_P
set_property -dict {PACKAGE_PIN K38 IOSTANDARD LVCMOS18} [get_ports gpio_txnrx] ; ## G19 FMC_LPC_LA16_N
set_property -dict {PACKAGE_PIN K37 IOSTANDARD LVCMOS18} [get_ports enable] ; ## G18 FMC_LPC_LA16_P
set_property -dict {PACKAGE_PIN K38 IOSTANDARD LVCMOS18} [get_ports txnrx] ; ## G19 FMC_LPC_LA16_N
set_property -dict {PACKAGE_PIN J30 IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports spi_csn_0] ; ## D26 FMC_LPC_LA26_P
set_property -dict {PACKAGE_PIN H30 IOSTANDARD LVCMOS18} [get_ports spi_clk] ; ## D27 FMC_LPC_LA26_N

23
projects/fmcomms2/vc707/system_top.v
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@ -104,8 +104,9 @@ module system_top (
tx_data_out_p,
tx_data_out_n,
gpio_txnrx,
gpio_enable,
txnrx,
enable,
gpio_resetb,
gpio_sync,
gpio_en_agc,
@ -183,8 +184,8 @@ module system_top (
output [ 5:0] tx_data_out_p;
output [ 5:0] tx_data_out_n;
inout gpio_txnrx;
inout gpio_enable;
output txnrx;
output enable;
inout gpio_resetb;
inout gpio_sync;
inout gpio_en_agc;
@ -206,12 +207,21 @@ module system_top (
wire spi_mosi;
wire spi_miso;
wire tdd_enable_s;
wire gpio_enable;
wire gpio_txnrx;
wire enable_s;
wire txnrx_s;
// default logic
assign fan_pwm = 1'b1;
assign iic_rstn = 1'b1;
assign spi_csn_0 = spi_csn[0];
assign enable = (tdd_enable_s == 1'b1) ? enable_s : gpio_enable;
assign txnrx = (tdd_enable_s == 1'b1) ? txnrx_s : gpio_txnrx;
// instantiations
ad_iobuf #(.DATA_WIDTH(17)) i_iobuf (
@ -301,7 +311,10 @@ module system_top (
.tx_frame_out_n (tx_frame_out_n),
.tx_frame_out_p (tx_frame_out_p),
.uart_sin (uart_sin),
.uart_sout (uart_sout));
.uart_sout (uart_sout),
.enable (enable_s),
.txnrx (txnrx_s),
.tdd_enable (tdd_enable_s));
endmodule

4
projects/fmcomms2/zc702/system_constr.xdc
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@ -50,8 +50,8 @@ set_property -dict {PACKAGE_PIN B15 IOSTANDARD LVCMOS25} [get_ports gpio_ctl[
set_property -dict {PACKAGE_PIN E19 IOSTANDARD LVCMOS25} [get_ports gpio_en_agc] ; ## H22 FMC_LPC_LA19_P
set_property -dict {PACKAGE_PIN E20 IOSTANDARD LVCMOS25} [get_ports gpio_sync] ; ## H23 FMC_LPC_LA19_N
set_property -dict {PACKAGE_PIN D22 IOSTANDARD LVCMOS25} [get_ports gpio_resetb] ; ## H31 FMC_LPC_LA28_P
set_property -dict {PACKAGE_PIN N15 IOSTANDARD LVCMOS25} [get_ports gpio_enable] ; ## G18 FMC_LPC_LA16_P
set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS25} [get_ports gpio_txnrx] ; ## G19 FMC_LPC_LA16_N
set_property -dict {PACKAGE_PIN N15 IOSTANDARD LVCMOS25} [get_ports enable] ; ## G18 FMC_LPC_LA16_P
set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS25} [get_ports txnrx] ; ## G19 FMC_LPC_LA16_N
set_property -dict {PACKAGE_PIN F18 IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports spi_csn] ; ## D26 FMC_LPC_LA26_P
set_property -dict {PACKAGE_PIN E18 IOSTANDARD LVCMOS25} [get_ports spi_clk] ; ## D27 FMC_LPC_LA26_N

25
projects/fmcomms2/zc702/system_top.v
View File

@ -90,8 +90,9 @@ module system_top (
tx_data_out_p,
tx_data_out_n,
gpio_txnrx,
gpio_enable,
txnrx,
enable,
gpio_resetb,
gpio_sync,
gpio_en_agc,
@ -152,8 +153,8 @@ module system_top (
output [ 5:0] tx_data_out_p;
output [ 5:0] tx_data_out_n;
inout gpio_txnrx;
inout gpio_enable;
output txnrx;
output enable;
inout gpio_resetb;
inout gpio_sync;
inout gpio_en_agc;
@ -176,6 +177,17 @@ module system_top (
wire spi_udc_sclk;
wire spi_udc_data;
wire tdd_enable_s;
wire gpio_enable;
wire gpio_txnrx;
wire enable_s;
wire txnrx_s;
// internal logic
assign enable = (tdd_enable_s == 1'b1) ? enable_s : gpio_enable;
assign txnrx = (tdd_enable_s == 1'b1) ? txnrx_s : gpio_txnrx;
// instantiations
ad_iobuf #(.DATA_WIDTH(29)) i_iobuf (
@ -273,7 +285,10 @@ module system_top (
.spi1_csn_2_o(),
.spi1_sdo_i (spi_udc_data),
.spi1_sdo_o (spi_udc_data),
.spi1_sdi_i (1'b0));
.spi1_sdi_i (1'b0),
.enable (enable_s),
.txnrx (txnrx_s),
.tdd_enable (tdd_enable_s));
endmodule

18
projects/fmcomms2/zc706/system_top.v
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@ -89,6 +89,7 @@ module system_top (
tx_frame_out_n,
tx_data_out_p,
tx_data_out_n,
enable,
txnrx,
@ -158,6 +159,7 @@ module system_top (
output tx_frame_out_n;
output [ 5:0] tx_data_out_p;
output [ 5:0] tx_data_out_n;
output enable;
output txnrx;
@ -206,6 +208,15 @@ module system_top (
wire [31:0] dac_gpio_input;
wire [31:0] dac_gpio_output;
wire tdd_enable_s;
wire gpio_enable;
wire gpio_txnrx;
wire enable_s;
wire txnrx_s;
assign enable = (tdd_enable_s == 1'b1) ? enable_s : gpio_enable;
assign txnrx = (tdd_enable_s == 1'b1) ? txnrx_s : gpio_txnrx;
// instantiations
ad_iobuf #(.DATA_WIDTH(17)) i_iobuf (
@ -214,6 +225,8 @@ module system_top (
.dio_o (gpio_i[49:32]),
.dio_p ({ gpio_muxout_tx,
gpio_muxout_rx,
gpio_txnrx,
gpio_enable,
gpio_resetb,
gpio_sync,
gpio_en_agc,
@ -242,7 +255,7 @@ module system_top (
.ddr_ras_n (ddr_ras_n),
.ddr_reset_n (ddr_reset_n),
.ddr_we_n (ddr_we_n),
.enable (enable),
.enable (enable_s),
.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
.fixed_io_mio (fixed_io_mio),
@ -302,7 +315,8 @@ module system_top (
.tx_data_out_p (tx_data_out_p),
.tx_frame_out_n (tx_frame_out_n),
.tx_frame_out_p (tx_frame_out_p),
.txnrx (txnrx));
.txnrx (txnrx_s),
.tdd_enable (tdd_enable_s));
endmodule

4
projects/fmcomms2/zed/system_constr.xdc
View File

@ -50,8 +50,8 @@ set_property -dict {PACKAGE_PIN C22 IOSTANDARD LVCMOS25} [get_ports gpio_ctl[
set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVCMOS25} [get_ports gpio_en_agc] ; ## H22 FMC_LPC_LA19_P
set_property -dict {PACKAGE_PIN G16 IOSTANDARD LVCMOS25} [get_ports gpio_sync] ; ## H23 FMC_LPC_LA19_N
set_property -dict {PACKAGE_PIN A16 IOSTANDARD LVCMOS25} [get_ports gpio_resetb] ; ## H31 FMC_LPC_LA28_P
set_property -dict {PACKAGE_PIN J20 IOSTANDARD LVCMOS25} [get_ports gpio_enable] ; ## G18 FMC_LPC_LA16_P
set_property -dict {PACKAGE_PIN K21 IOSTANDARD LVCMOS25} [get_ports gpio_txnrx] ; ## G19 FMC_LPC_LA16_N
set_property -dict {PACKAGE_PIN J20 IOSTANDARD LVCMOS25} [get_ports enable] ; ## G18 FMC_LPC_LA16_P
set_property -dict {PACKAGE_PIN K21 IOSTANDARD LVCMOS25} [get_ports txnrx] ; ## G19 FMC_LPC_LA16_N
set_property -dict {PACKAGE_PIN F18 IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports spi_csn] ; ## D26 FMC_LPC_LA26_P
set_property -dict {PACKAGE_PIN E18 IOSTANDARD LVCMOS25} [get_ports spi_clk] ; ## D27 FMC_LPC_LA26_N

26
projects/fmcomms2/zed/system_top.v
View File

@ -100,10 +100,11 @@ module system_top (
tx_data_out_p,
tx_data_out_n,
txnrx,
enable,
gpio_muxout_tx,
gpio_muxout_rx,
gpio_txnrx,
gpio_enable,
gpio_resetb,
gpio_sync,
gpio_en_agc,
@ -179,10 +180,11 @@ module system_top (
output [ 5:0] tx_data_out_p;
output [ 5:0] tx_data_out_n;
output txnrx;
output enable;
inout gpio_muxout_tx;
inout gpio_muxout_rx;
inout gpio_txnrx;
inout gpio_enable;
inout gpio_resetb;
inout gpio_sync;
inout gpio_en_agc;
@ -211,6 +213,17 @@ module system_top (
wire [ 1:0] iic_mux_sda_o_s;
wire iic_mux_sda_t_s;
wire tdd_enable_s;
wire gpio_enable;
wire gpio_txnrx;
wire enable_s;
wire txnrx_s;
// internal logic
assign enable = (tdd_enable_s == 1'b1) ? enable_s : gpio_enable;
assign txnrx = (tdd_enable_s == 1'b1) ? txnrx_s : gpio_txnrx;
// instantiations
ad_iobuf #(.DATA_WIDTH(51)) i_iobuf_gpio (
@ -325,7 +338,10 @@ module system_top (
.tx_data_out_n (tx_data_out_n),
.tx_data_out_p (tx_data_out_p),
.tx_frame_out_n (tx_frame_out_n),
.tx_frame_out_p (tx_frame_out_p));
.tx_frame_out_p (tx_frame_out_p),
.enable (enable_s),
.txnrx (txnrx_s),
.tdd_enable (tdd_enable_s));
endmodule