library: Add JESD204 PHY wrapper for Arria10 Native PHY
Add a wrapper that instantiates the Arria10 Native PHY and configures it for JESD204 operation. The datapath width is set to 4 octets per beat. The maximum lane rate that is achievable with hard-logic PCS included in the PHY is below the requirements of the JESD204 for some of the PHY speed grades. For projects that require a lane rate that is higher than what the hard-logic PCS can support a soft-logic PCS module can be instantiated. The external interface of the jesd204_phy is identical regardless of whether soft- or hard-logic PCS is used. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>main
Lars-Peter Clausen
parent
4df841addc
commit
0108d01043
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsabilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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module jesd204_glue #(
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parameter WIDTH = 20,
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parameter CONST_WIDTH = 1
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) (
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input [WIDTH-1:0] in,
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output [WIDTH-1:0] out,
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output [CONST_WIDTH-1:0] const_out
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);
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/* There really should be a standard component in Qsys that allows to do this */
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assign out = in;
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assign const_out = {CONST_WIDTH{1'b0}};
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endmodule
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#
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# The ADI JESD204 Core is released under the following license, which is
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# different than all other HDL cores in this repository.
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#
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# Please read this, and understand the freedoms and responsibilities you have
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# by using this source code/core.
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#
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# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
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#
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# This core is free software, you can use run, copy, study, change, ask
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# questions about and improve this core. Distribution of source, or resulting
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# binaries (including those inside an FPGA or ASIC) require you to release the
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# source of the entire project (excluding the system libraries provide by the
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# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
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# License version 2 as published by the Free Software Foundation.
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#
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# This core is distributed in the hope that it will be useful, but WITHOUT ANY
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# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License version 2
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# along with this source code, and binary. If not, see
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# <http://www.gnu.org/licenses/>.
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#
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# Commercial licenses (with commercial support) of this JESD204 core are also
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# available under terms different than the General Public License. (e.g. they
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# do not require you to accompany any image (FPGA or ASIC) using the JESD204
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# core with any corresponding source code.) For these alternate terms you must
|
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# purchase a license from Analog Devices Technology Licensing Office. Users
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# interested in such a license should contact jesd204-licensing@analog.com for
|
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# more information. This commercial license is sub-licensable (if you purchase
|
||||
# chips from Analog Devices, incorporate them into your PCB level product, and
|
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# purchase a JESD204 license, end users of your product will also have a
|
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# license to use this core in a commercial setting without releasing their
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# source code).
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#
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# In addition, we kindly ask you to acknowledge ADI in any program, application
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# or publication in which you use this JESD204 HDL core. (You are not required
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# to do so; it is up to your common sense to decide whether you want to comply
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# with this request or not.) For general publications, we suggest referencing :
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# “The design and implementation of the JESD204 HDL Core used in this project
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# is copyright © 2016-2017, Analog Devices, Inc.”
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#
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package require qsys
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source ../../scripts/adi_env.tcl
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source ../../scripts/adi_ip_alt.tcl
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#
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# For whatever strange reason all the interface of the native PHY become
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# conduits when it is instantiated in a compose callback. This glue logic module
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# converts the interfaces to their proper type.
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#
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ad_ip_create jesd204_phy_glue {Native PHY to JESD204 glue logic} \
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jesd204_phy_glue_elab
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set_module_property INTERNAL true
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# files
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ad_ip_files jesd204_glue [list \
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jesd204_phy_glue.v \
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]
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# parameters
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ad_ip_parameter TX_OR_RX_N BOOLEAN false false
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ad_ip_parameter SOFT_PCS BOOLEAN false false
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ad_ip_parameter NUM_OF_LANES POSITIVE 4 false
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ad_ip_parameter WIDTH NATURAL 20 true { \
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DERIVED true \
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}
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ad_ip_parameter CONST_WIDTH NATURAL 1 true { \
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DERIVED true \
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}
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proc glue_add_if {num name type dir {bcast false}} {
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if {$bcast} {
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add_interface ${name} $type $dir
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} else {
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for {set i 0} {$i < $num} {incr i} {
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add_interface ${name}_${i} $type $dir
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}
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}
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add_interface phy_${name} conduit end
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}
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proc glue_add_if_port {num ifname port role dir width {bcast false}} {
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variable sig_offset
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set phy_width [expr $num * $width]
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if {$dir == "Input"} {
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set sig "in"
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set phy_dir "Output"
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set phy_sig "out"
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} else {
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set sig "out"
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set phy_dir "Input"
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set phy_sig "in"
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}
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if {$bcast} {
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add_interface_port ${ifname} ${port} $role $dir $width
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set_port_property ${port} fragment_list \
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[format "%s(%d:%d)" $sig [expr $sig_offset + $width - 1] $sig_offset]
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} else {
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for {set i 0} {$i < $num} {incr i} {
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set base [expr $sig_offset + $width * $i]
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add_interface_port ${ifname}_${i} ${port}_${i} $role $dir $width
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set_port_property ${port}_${i} fragment_list \
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[format "%s(%d:%d)" $sig [expr $base + $width - 1] $base]
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}
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}
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add_interface_port phy_${ifname} phy_${port} $role $phy_dir $phy_width
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if {$bcast} {
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set _frag [format "%s(%d:%d)" $phy_sig [expr $sig_offset + $width - 1] $sig_offset]
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set sig_offset [expr $sig_offset + $width]
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set frag "${_frag}"
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for {set i 1} {$i < $num} {incr i} {
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set frag [concat ${frag} ${_frag}]
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}
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} else {
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set frag [format "%s(%d:%d)" $phy_sig [expr $sig_offset + $phy_width - 1] $sig_offset]
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set sig_offset [expr $sig_offset + $phy_width]
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}
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set_port_property phy_${port} fragment_list $frag
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}
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proc glue_add_if_port_conduit {num ifname port phy_port dir width} {
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variable sig_offset
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set phy_width [expr $num * $width]
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if {$dir == "Input"} {
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set sig "in"
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set phy_dir "Output"
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set phy_sig "out"
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} else {
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set sig "out"
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set phy_dir "Input"
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set phy_sig "in"
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}
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for {set i 0} {$i < $num} {incr i} {
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set base [expr $sig_offset + $width * $i]
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add_interface_port ${ifname}_${i} ${ifname}_${port}_${i} $port $dir $width
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set_port_property ${ifname}_${port}_${i} fragment_list \
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[format "%s(%d:%d)" $sig [expr $base + $width - 1] $base]
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}
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add_interface phy_${phy_port} conduit end
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add_interface_port phy_${phy_port} phy_${phy_port} $phy_port $phy_dir $phy_width
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set_port_property phy_${phy_port} fragment_list \
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[format "%s(%d:%d)" $phy_sig [expr $sig_offset + $phy_width - 1] $sig_offset]
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set sig_offset [expr $sig_offset + $phy_width]
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}
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proc glue_add_const_conduit {port width} {
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variable const_offset
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set ifname phy_${port}
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add_interface $ifname conduit end
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add_interface_port $ifname $ifname $port Output $width
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set_port_property $ifname fragment_list [format "const_out(%d:%d)" \
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[expr $const_offset + $width - 1] $const_offset]
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set const_offset [expr $const_offset + $width]
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}
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proc jesd204_phy_glue_elab {} {
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variable sig_offset
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variable const_offset
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set soft_pcs [get_parameter SOFT_PCS]
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set num_of_lanes [get_parameter NUM_OF_LANES]
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set sig_offset 0
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set const_offset 0
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glue_add_if $num_of_lanes reconfig_clk clock sink true
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glue_add_if_port $num_of_lanes reconfig_clk reconfig_clk clk Input 1 true
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glue_add_if $num_of_lanes reconfig_reset reset sink true
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glue_add_if_port $num_of_lanes reconfig_reset reconfig_reset reset Input 1 true
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glue_add_if $num_of_lanes reconfig_avmm avalon sink
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for {set i 0} {$i < $num_of_lanes} {incr i} {
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set_interface_property reconfig_avmm_${i} associatedClock reconfig_clk
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set_interface_property reconfig_avmm_${i} associatedReset reconfig_reset
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}
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glue_add_if_port $num_of_lanes reconfig_avmm reconfig_address address Input 10
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glue_add_if_port $num_of_lanes reconfig_avmm reconfig_read read Input 1
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glue_add_if_port $num_of_lanes reconfig_avmm reconfig_readdata readdata Output 32
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glue_add_if_port $num_of_lanes reconfig_avmm reconfig_waitrequest waitrequest Output 1
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glue_add_if_port $num_of_lanes reconfig_avmm reconfig_write write Input 1
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glue_add_if_port $num_of_lanes reconfig_avmm reconfig_writedata writedata Input 32
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if {[get_parameter TX_OR_RX_N]} {
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glue_add_if $num_of_lanes tx_clkout clock source
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glue_add_if_port $num_of_lanes tx_clkout tx_clkout clk Output 1
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glue_add_if $num_of_lanes tx_coreclkin clock sink true
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glue_add_if_port $num_of_lanes tx_coreclkin tx_coreclkin clk Input 1 true
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glue_add_if $num_of_lanes tx_serial_clk0 hssi_serial_clock sink true
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glue_add_if_port $num_of_lanes tx_serial_clk0 tx_serial_clk0 clk Input 1 true
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if {$soft_pcs} {
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set unused_width [expr $num_of_lanes * 88]
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glue_add_const_conduit tx_enh_data_valid $num_of_lanes
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for {set i 0} {$i < $num_of_lanes} {incr i} {
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add_interface tx_raw_data_${i} conduit start
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}
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glue_add_if_port_conduit $num_of_lanes tx_raw_data raw_data tx_parallel_data Input 40
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} else {
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set unused_width [expr $num_of_lanes * 92]
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for {set i 0} {$i < $num_of_lanes} {incr i} {
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add_interface tx_phy_${i} conduit start
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}
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glue_add_if_port_conduit $num_of_lanes tx_phy char tx_parallel_data Input 32
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glue_add_if_port_conduit $num_of_lanes tx_phy charisk tx_datak Input 4
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}
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glue_add_const_conduit unused_tx_parallel_data $unused_width
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} else {
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glue_add_if 1 rx_cdr_refclk0 clock sink true
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glue_add_if_port 1 rx_cdr_refclk0 rx_cdr_refclk0 clk Input 1 true
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glue_add_if $num_of_lanes rx_coreclkin clock sink true
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glue_add_if_port $num_of_lanes rx_coreclkin rx_coreclkin clk Input 1 true
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glue_add_if $num_of_lanes rx_clkout clock source
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glue_add_if_port $num_of_lanes rx_clkout rx_clkout clk Output 1
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if {$soft_pcs} {
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for {set i 0} {$i < $num_of_lanes} {incr i} {
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add_interface rx_raw_data_${i} conduit start
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}
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glue_add_if_port_conduit $num_of_lanes rx_raw_data raw_data rx_parallel_data Output 40
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} else {
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for {set i 0} {$i < $num_of_lanes} {incr i} {
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add_interface rx_phy_${i} conduit start
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}
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glue_add_if_port_conduit $num_of_lanes rx_phy char rx_parallel_data Output 32
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glue_add_if_port_conduit $num_of_lanes rx_phy charisk rx_datak Output 4
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glue_add_if_port_conduit $num_of_lanes rx_phy disperr rx_disperr Output 4
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glue_add_if_port_conduit $num_of_lanes rx_phy notintable rx_errdetect Output 4
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glue_add_if_port_conduit $num_of_lanes rx_phy patternalign_en rx_std_wa_patternalign Input 1
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}
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add_interface const_out conduit end
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add_interface_port const_out const_out const_out Output 1
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set_port_property const_out TERMINATION true
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set const_offset 1
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}
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set_interface_property reconfig_reset associatedClock reconfig_clk
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set_interface_property reconfig_reset synchronousEdges DEASSERT
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set_parameter_value WIDTH $sig_offset
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set_parameter_value CONST_WIDTH $const_offset
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}
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@ -0,0 +1,228 @@
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#
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# The ADI JESD204 Core is released under the following license, which is
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# different than all other HDL cores in this repository.
|
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#
|
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# Please read this, and understand the freedoms and responsibilities you have
|
||||
# by using this source code/core.
|
||||
#
|
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# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
#
|
||||
# This core is free software, you can use run, copy, study, change, ask
|
||||
# questions about and improve this core. Distribution of source, or resulting
|
||||
# binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
# source of the entire project (excluding the system libraries provide by the
|
||||
# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
# License version 2 as published by the Free Software Foundation.
|
||||
#
|
||||
# This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License version 2
|
||||
# along with this source code, and binary. If not, see
|
||||
# <http://www.gnu.org/licenses/>.
|
||||
#
|
||||
# Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
# available under terms different than the General Public License. (e.g. they
|
||||
# do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
# core with any corresponding source code.) For these alternate terms you must
|
||||
# purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
# interested in such a license should contact jesd204-licensing@analog.com for
|
||||
# more information. This commercial license is sub-licensable (if you purchase
|
||||
# chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
# purchase a JESD204 license, end users of your product will also have a
|
||||
# license to use this core in a commercial setting without releasing their
|
||||
# source code).
|
||||
#
|
||||
# In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
# or publication in which you use this JESD204 HDL core. (You are not required
|
||||
# to do so; it is up to your common sense to decide whether you want to comply
|
||||
# with this request or not.) For general publications, we suggest referencing :
|
||||
# “The design and implementation of the JESD204 HDL Core used in this project
|
||||
# is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
#
|
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|
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package require qsys
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source ../../scripts/adi_env.tcl
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source $ad_hdl_dir/library/scripts/adi_ip_alt.tcl
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#
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# Instantiates the Arria 10 native PHY and configures it for JESD204 operation.
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# The datapath width is configured for 4 octets per beat.
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#
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# Optionally a soft-logic PCS is instantiated, this can be used if the lane rate
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# is too high for the hard-logic PCS.
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#
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ad_ip_create jesd204_phy "ADI JESD204 PHY"
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set_module_property COMPOSITION_CALLBACK jesd204_phy_composition_callback
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set_module_property INTERNAL true
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# parameters
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ad_ip_parameter ID NATURAL 0 false
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ad_ip_parameter SOFT_PCS BOOLEAN false false
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ad_ip_parameter TX_OR_RX_N BOOLEAN false false
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ad_ip_parameter LANE_RATE FLOAT 10000 false
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ad_ip_parameter REFCLK_FREQUENCY FLOAT 500.0 false
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ad_ip_parameter NUM_OF_LANES POSITIVE 4 false
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proc jesd204_phy_composition_callback {} {
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set soft_pcs [get_parameter_value "SOFT_PCS"]
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set tx [get_parameter_value "TX_OR_RX_N"]
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set lane_rate [get_parameter_value "LANE_RATE"]
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set refclk_frequency [get_parameter_value "REFCLK_FREQUENCY"]
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set id [get_parameter_value "ID"]
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set num_of_lanes [get_parameter_value "NUM_OF_LANES"]
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set link_clk_frequency [expr $lane_rate / 40]
|
||||
|
||||
add_instance link_clock clock_source
|
||||
set_instance_parameter_value link_clock {clockFrequency} [expr $link_clk_frequency*1000000]
|
||||
add_interface link_clk clock sink
|
||||
set_interface_property link_clk EXPORT_OF link_clock.clk_in
|
||||
add_interface link_reset reset sink
|
||||
set_interface_property link_reset EXPORT_OF link_clock.clk_in_reset
|
||||
|
||||
add_instance native_phy altera_xcvr_native_a10
|
||||
set_instance_property native_phy SUPPRESS_ALL_WARNINGS true
|
||||
set_instance_property native_phy SUPPRESS_ALL_INFO_MESSAGES true
|
||||
if {$soft_pcs} {
|
||||
set_instance_parameter_value native_phy {protocol_mode} "basic_enh"
|
||||
} else {
|
||||
set_instance_parameter_value native_phy {protocol_mode} "basic_std"
|
||||
set_instance_parameter_value native_phy {std_pcs_pma_width} 20
|
||||
|
||||
if {$tx} {
|
||||
set_instance_parameter_value native_phy {std_tx_byte_ser_mode} "Serialize x2"
|
||||
set_instance_parameter_value native_phy {std_tx_8b10b_enable} 1
|
||||
} else {
|
||||
set_instance_parameter_value native_phy {std_rx_byte_deser_mode} "Deserialize x2"
|
||||
set_instance_parameter_value native_phy {std_rx_8b10b_enable} 1
|
||||
set_instance_parameter_value native_phy {std_rx_word_aligner_mode} "manual (PLD controlled)"
|
||||
set_instance_parameter_value native_phy {std_rx_word_aligner_pattern_len} 20
|
||||
set_instance_parameter_value native_phy {std_rx_word_aligner_pattern} 0xA0D7C
|
||||
set_instance_parameter_value native_phy {enable_port_rx_std_wa_patternalign} 1
|
||||
}
|
||||
}
|
||||
|
||||
if {$tx} {
|
||||
set_instance_parameter_value native_phy {duplex_mode} "tx"
|
||||
set_instance_parameter_value native_phy {bonded_mode} "not_bonded"
|
||||
set_instance_parameter_value native_phy {enable_port_tx_pma_elecidle} 0
|
||||
set_instance_parameter_value native_phy {enh_txfifo_mode} "Phase compensation"
|
||||
} else {
|
||||
set_instance_parameter_value native_phy {duplex_mode} "rx"
|
||||
set_instance_parameter_value native_phy {set_cdr_refclk_freq} $refclk_frequency
|
||||
set_instance_parameter_value native_phy {enable_port_rx_is_lockedtodata} 1
|
||||
set_instance_parameter_value native_phy {enable_port_rx_is_lockedtoref} 0
|
||||
set_instance_parameter_value native_phy {enable_ports_rx_manual_cdr_mode} 0
|
||||
set_instance_parameter_value native_phy {enh_rxfifo_mode} "Phase compensation"
|
||||
}
|
||||
|
||||
set_instance_parameter_value native_phy {channels} $num_of_lanes
|
||||
set_instance_parameter_value native_phy {set_data_rate} $lane_rate
|
||||
set_instance_parameter_value native_phy {enable_simple_interface} 1
|
||||
set_instance_parameter_value native_phy {enh_pcs_pma_width} 40
|
||||
set_instance_parameter_value native_phy {enh_pld_pcs_width} 40
|
||||
set_instance_parameter_value native_phy {rcfg_enable} 1
|
||||
set_instance_parameter_value native_phy {rcfg_shared} 0
|
||||
set_instance_parameter_value native_phy {rcfg_jtag_enable} 0
|
||||
set_instance_parameter_value native_phy {rcfg_sv_file_enable} 0
|
||||
set_instance_parameter_value native_phy {rcfg_h_file_enable} 0
|
||||
set_instance_parameter_value native_phy {rcfg_mif_file_enable} 0
|
||||
set_instance_parameter_value native_phy {set_user_identifier} $id
|
||||
set_instance_parameter_value native_phy {set_capability_reg_enable} 1
|
||||
set_instance_parameter_value native_phy {set_csr_soft_logic_enable} 1
|
||||
set_instance_parameter_value native_phy {set_prbs_soft_logic_enable} 0
|
||||
|
||||
add_instance phy_glue jesd204_phy_glue
|
||||
set_instance_parameter_value phy_glue TX_OR_RX_N $tx
|
||||
set_instance_parameter_value phy_glue SOFT_PCS $soft_pcs
|
||||
set_instance_parameter_value phy_glue NUM_OF_LANES $num_of_lanes
|
||||
|
||||
add_interface reconfig_clk clock sink
|
||||
set_interface_property reconfig_clk EXPORT_OF phy_glue.reconfig_clk
|
||||
|
||||
add_interface reconfig_reset reset sink
|
||||
set_interface_property reconfig_reset EXPORT_OF phy_glue.reconfig_reset
|
||||
|
||||
if {$tx} {
|
||||
add_interface serial_clk hssi_serial_clock end
|
||||
set_interface_property serial_clk EXPORT_OF phy_glue.tx_serial_clk0
|
||||
|
||||
add_connection link_clock.clk phy_glue.tx_coreclkin
|
||||
|
||||
if {$soft_pcs} {
|
||||
add_connection phy_glue.phy_tx_enh_data_valid native_phy.tx_enh_data_valid
|
||||
}
|
||||
|
||||
foreach x {reconfig_clk reconfig_reset reconfig_avmm tx_coreclkin \
|
||||
tx_clkout tx_serial_clk0 tx_parallel_data unused_tx_parallel_data} {
|
||||
add_connection phy_glue.phy_${x} native_phy.${x}
|
||||
}
|
||||
|
||||
foreach x {serial_data analogreset digitalreset cal_busy} {
|
||||
add_interface ${x} conduit end
|
||||
set_interface_property ${x} EXPORT_OF native_phy.tx_${x}
|
||||
}
|
||||
|
||||
if {$soft_pcs == false} {
|
||||
add_connection phy_glue.phy_tx_datak native_phy.tx_datak
|
||||
}
|
||||
} else {
|
||||
add_interface ref_clk clock sink
|
||||
set_interface_property ref_clk EXPORT_OF phy_glue.rx_cdr_refclk0
|
||||
|
||||
add_connection link_clock.clk phy_glue.rx_coreclkin
|
||||
|
||||
foreach x {serial_data analogreset digitalreset cal_busy is_lockedtodata} {
|
||||
add_interface ${x} conduit end
|
||||
set_interface_property ${x} EXPORT_OF native_phy.rx_${x}
|
||||
}
|
||||
|
||||
foreach x {reconfig_clk reconfig_reset reconfig_avmm rx_coreclkin \
|
||||
rx_clkout rx_parallel_data rx_cdr_refclk0} {
|
||||
add_connection phy_glue.phy_${x} native_phy.${x}
|
||||
}
|
||||
|
||||
if {$soft_pcs == false} {
|
||||
foreach x {rx_datak rx_disperr rx_errdetect rx_std_wa_patternalign} {
|
||||
add_connection phy_glue.phy_${x} native_phy.${x}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
for {set i 0} {$i < $num_of_lanes} {incr i} {
|
||||
add_interface reconfig_avmm_${i} avalon slave
|
||||
set_interface_property reconfig_avmm_${i} EXPORT_OF phy_glue.reconfig_avmm_${i}
|
||||
|
||||
add_interface phy_${i} conduit start
|
||||
|
||||
if {$tx} {
|
||||
if {$soft_pcs} {
|
||||
add_instance soft_pcs_${i} jesd204_soft_pcs_tx
|
||||
add_connection link_clock.clk soft_pcs_${i}.clock
|
||||
add_connection link_clock.clk_reset soft_pcs_${i}.reset
|
||||
add_connection soft_pcs_${i}.tx_raw_data phy_glue.tx_raw_data_${i}
|
||||
|
||||
set_interface_property phy_${i} EXPORT_OF soft_pcs_${i}.tx_phy
|
||||
} else {
|
||||
set_interface_property phy_${i} EXPORT_OF phy_glue.tx_phy_${i}
|
||||
}
|
||||
} else {
|
||||
|
||||
if {$soft_pcs} {
|
||||
add_instance soft_pcs_${i} jesd204_soft_pcs_rx
|
||||
add_connection link_clock.clk soft_pcs_${i}.clock
|
||||
add_connection link_clock.clk_reset soft_pcs_${i}.reset
|
||||
add_connection phy_glue.rx_raw_data_${i} soft_pcs_${i}.rx_raw_data
|
||||
|
||||
set_interface_property phy_${i} EXPORT_OF soft_pcs_${i}.rx_phy
|
||||
} else {
|
||||
set_interface_property phy_${i} EXPORT_OF phy_glue.rx_phy_${i}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
Loading…
Reference in New Issue