fmcomms8: ZCU102: Initial commit
Adrian Costina
parent
ea06fcd7b6
commit
016a1d540d
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####################################################################################
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## Copyright 2018(c) Analog Devices, Inc.
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## Auto-generated, do not modify!
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####################################################################################
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include ../scripts/project-toplevel.mk
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create_bd_port -dir I ref_clk_c
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create_bd_port -dir I ref_clk_d
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create_bd_port -dir I core_clk_c
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create_bd_port -dir I core_clk_d
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# TX parameters
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set TX_NUM_OF_LANES 8 ; # L
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set TX_NUM_OF_CONVERTERS 8 ; # M
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set TX_SAMPLES_PER_FRAME 1 ; # S
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set TX_SAMPLE_WIDTH 16 ; # N/NP
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set TX_SAMPLES_PER_CHANNEL 2 ; # L * 32 / (M * N)
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# RX parameters
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set RX_NUM_OF_LANES 4 ; # L
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set RX_NUM_OF_CONVERTERS 8 ; # M
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set RX_SAMPLES_PER_FRAME 1 ; # S
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set RX_SAMPLE_WIDTH 16 ; # N/NP
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set RX_SAMPLES_PER_CHANNEL 1 ; # L * 32 / (M * N)
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# RX Observation parameters
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set OBS_NUM_OF_LANES 4 ; # L
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set OBS_NUM_OF_CONVERTERS 4 ; # M
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set OBS_SAMPLES_PER_FRAME 1 ; # S
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set OBS_SAMPLE_WIDTH 16 ; # N/NP
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set OBS_SAMPLES_PER_CHANNEL 2 ; # L * 32 / (M * N)
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source $ad_hdl_dir/library/jesd204/scripts/jesd204.tcl
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ad_ip_instance axi_adxcvr axi_adrv9009_fmc_tx_xcvr
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ad_ip_parameter axi_adrv9009_fmc_tx_xcvr CONFIG.NUM_OF_LANES $TX_NUM_OF_LANES
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ad_ip_parameter axi_adrv9009_fmc_tx_xcvr CONFIG.QPLL_ENABLE 1
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ad_ip_parameter axi_adrv9009_fmc_tx_xcvr CONFIG.TX_OR_RX_N 1
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adi_axi_jesd204_tx_create axi_adrv9009_fmc_tx_jesd $TX_NUM_OF_LANES
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set_property -dict [list CONFIG.SYSREF_IOB {false}] [get_bd_cells axi_adrv9009_fmc_tx_jesd/tx]
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ad_ip_instance util_upack2 util_fmc_tx_upack [list \
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NUM_OF_CHANNELS $TX_NUM_OF_CONVERTERS \
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SAMPLES_PER_CHANNEL $TX_SAMPLES_PER_CHANNEL \
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SAMPLE_DATA_WIDTH $TX_SAMPLE_WIDTH \
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]
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adi_tpl_jesd204_tx_create tx_adrv9009_fmc_tpl_core $TX_NUM_OF_LANES \
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$TX_NUM_OF_CONVERTERS \
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$TX_SAMPLES_PER_FRAME \
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$TX_SAMPLE_WIDTH
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ad_ip_instance axi_dmac axi_adrv9009_fmc_tx_dma
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ad_ip_parameter axi_adrv9009_fmc_tx_dma CONFIG.DMA_TYPE_SRC 0
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ad_ip_parameter axi_adrv9009_fmc_tx_dma CONFIG.DMA_TYPE_DEST 1
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ad_ip_parameter axi_adrv9009_fmc_tx_dma CONFIG.CYCLIC 1
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ad_ip_parameter axi_adrv9009_fmc_tx_dma CONFIG.AXI_SLICE_SRC 1
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ad_ip_parameter axi_adrv9009_fmc_tx_dma CONFIG.AXI_SLICE_DEST 1
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ad_ip_parameter axi_adrv9009_fmc_tx_dma CONFIG.DMA_2D_TRANSFER 0
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ad_ip_parameter axi_adrv9009_fmc_tx_dma CONFIG.DMA_DATA_WIDTH_DEST 128
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ad_ip_parameter axi_adrv9009_fmc_tx_dma CONFIG.DMA_DATA_WIDTH_SRC 128
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ad_ip_parameter axi_adrv9009_fmc_tx_dma CONFIG.FIFO_SIZE 32
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ad_ip_parameter axi_adrv9009_fmc_tx_dma CONFIG.MAX_BYTES_PER_BURST 512
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ad_ip_instance axi_adxcvr axi_adrv9009_fmc_rx_xcvr
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ad_ip_parameter axi_adrv9009_fmc_rx_xcvr CONFIG.NUM_OF_LANES $RX_NUM_OF_LANES
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ad_ip_parameter axi_adrv9009_fmc_rx_xcvr CONFIG.QPLL_ENABLE 0
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ad_ip_parameter axi_adrv9009_fmc_rx_xcvr CONFIG.TX_OR_RX_N 0
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adi_axi_jesd204_rx_create axi_adrv9009_fmc_rx_jesd $RX_NUM_OF_LANES
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ad_ip_instance util_cpack2 util_fmc_rx_cpack [list \
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NUM_OF_CHANNELS $RX_NUM_OF_CONVERTERS \
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SAMPLES_PER_CHANNEL $RX_SAMPLES_PER_CHANNEL \
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SAMPLE_DATA_WIDTH $RX_SAMPLE_WIDTH \
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]
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adi_tpl_jesd204_rx_create rx_adrv9009_fmc_tpl_core $RX_NUM_OF_LANES \
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$RX_NUM_OF_CONVERTERS \
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$RX_SAMPLES_PER_FRAME \
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$RX_SAMPLE_WIDTH
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ad_ip_instance axi_dmac axi_adrv9009_fmc_rx_dma
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ad_ip_parameter axi_adrv9009_fmc_rx_dma CONFIG.DMA_TYPE_SRC 2
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ad_ip_parameter axi_adrv9009_fmc_rx_dma CONFIG.DMA_TYPE_DEST 0
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ad_ip_parameter axi_adrv9009_fmc_rx_dma CONFIG.CYCLIC 0
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ad_ip_parameter axi_adrv9009_fmc_rx_dma CONFIG.SYNC_TRANSFER_START 0
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ad_ip_parameter axi_adrv9009_fmc_rx_dma CONFIG.AXI_SLICE_SRC 1
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ad_ip_parameter axi_adrv9009_fmc_rx_dma CONFIG.AXI_SLICE_DEST 1
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ad_ip_parameter axi_adrv9009_fmc_rx_dma CONFIG.DMA_2D_TRANSFER 0
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ad_ip_parameter axi_adrv9009_fmc_rx_dma CONFIG.DMA_DATA_WIDTH_SRC 128
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ad_ip_parameter axi_adrv9009_fmc_rx_dma CONFIG.DMA_DATA_WIDTH_DEST 128
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ad_ip_instance axi_adxcvr axi_adrv9009_fmc_obs_xcvr
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ad_ip_parameter axi_adrv9009_fmc_obs_xcvr CONFIG.NUM_OF_LANES $RX_NUM_OF_LANES
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ad_ip_parameter axi_adrv9009_fmc_obs_xcvr CONFIG.QPLL_ENABLE 0
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ad_ip_parameter axi_adrv9009_fmc_obs_xcvr CONFIG.TX_OR_RX_N 0
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adi_axi_jesd204_rx_create axi_adrv9009_fmc_obs_jesd $OBS_NUM_OF_LANES
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ad_ip_instance util_cpack2 util_fmc_obs_cpack [list \
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NUM_OF_CHANNELS $OBS_NUM_OF_CONVERTERS \
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SAMPLES_PER_CHANNEL $OBS_SAMPLES_PER_CHANNEL\
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SAMPLE_DATA_WIDTH $OBS_SAMPLE_WIDTH \
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]
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adi_tpl_jesd204_rx_create obs_adrv9009_fmc_tpl_core $OBS_NUM_OF_LANES \
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$OBS_NUM_OF_CONVERTERS \
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$OBS_SAMPLES_PER_FRAME \
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$OBS_SAMPLE_WIDTH
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ad_ip_instance axi_dmac axi_adrv9009_fmc_obs_dma
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ad_ip_parameter axi_adrv9009_fmc_obs_dma CONFIG.DMA_TYPE_SRC 2
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ad_ip_parameter axi_adrv9009_fmc_obs_dma CONFIG.DMA_TYPE_DEST 0
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ad_ip_parameter axi_adrv9009_fmc_obs_dma CONFIG.CYCLIC 0
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ad_ip_parameter axi_adrv9009_fmc_obs_dma CONFIG.SYNC_TRANSFER_START 1
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ad_ip_parameter axi_adrv9009_fmc_obs_dma CONFIG.AXI_SLICE_SRC 1
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ad_ip_parameter axi_adrv9009_fmc_obs_dma CONFIG.AXI_SLICE_DEST 1
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ad_ip_parameter axi_adrv9009_fmc_obs_dma CONFIG.DMA_2D_TRANSFER 0
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ad_ip_parameter axi_adrv9009_fmc_obs_dma CONFIG.DMA_DATA_WIDTH_SRC 128
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ad_ip_parameter axi_adrv9009_fmc_obs_dma CONFIG.DMA_DATA_WIDTH_DEST 128
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ad_ip_instance util_adxcvr util_adrv9009_fmc_xcvr
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ad_ip_parameter util_adrv9009_fmc_xcvr CONFIG.RX_NUM_OF_LANES [expr $RX_NUM_OF_LANES+$OBS_NUM_OF_LANES]
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ad_ip_parameter util_adrv9009_fmc_xcvr CONFIG.TX_NUM_OF_LANES $TX_NUM_OF_LANES
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ad_ip_parameter util_adrv9009_fmc_xcvr CONFIG.TX_OUT_DIV 2
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ad_ip_parameter util_adrv9009_fmc_xcvr CONFIG.CPLL_FBDIV 4
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ad_ip_parameter util_adrv9009_fmc_xcvr CONFIG.RX_CLK25_DIV 10
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ad_ip_parameter util_adrv9009_fmc_xcvr CONFIG.TX_CLK25_DIV 10
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ad_ip_parameter util_adrv9009_fmc_xcvr CONFIG.QPLL_FBDIV 80
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ad_ip_parameter util_adrv9009_fmc_xcvr CONFIG.QPLL_REFCLK_DIV 1
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ad_xcvrpll ref_clk_c util_adrv9009_fmc_xcvr/qpll_ref_clk_0
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ad_xcvrpll ref_clk_d util_adrv9009_fmc_xcvr/cpll_ref_clk_0
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ad_xcvrpll ref_clk_d util_adrv9009_fmc_xcvr/cpll_ref_clk_1
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ad_xcvrpll ref_clk_c util_adrv9009_fmc_xcvr/cpll_ref_clk_2
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ad_xcvrpll ref_clk_c util_adrv9009_fmc_xcvr/cpll_ref_clk_3
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ad_xcvrpll ref_clk_c util_adrv9009_fmc_xcvr/qpll_ref_clk_4
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ad_xcvrpll ref_clk_d util_adrv9009_fmc_xcvr/cpll_ref_clk_4
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ad_xcvrpll ref_clk_d util_adrv9009_fmc_xcvr/cpll_ref_clk_5
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ad_xcvrpll ref_clk_c util_adrv9009_fmc_xcvr/cpll_ref_clk_6
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ad_xcvrpll ref_clk_c util_adrv9009_fmc_xcvr/cpll_ref_clk_7
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ad_xcvrpll axi_adrv9009_fmc_tx_xcvr/up_pll_rst util_adrv9009_fmc_xcvr/up_qpll_rst_0
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ad_xcvrpll axi_adrv9009_fmc_rx_xcvr/up_pll_rst util_adrv9009_fmc_xcvr/up_cpll_rst_0
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ad_xcvrpll axi_adrv9009_fmc_rx_xcvr/up_pll_rst util_adrv9009_fmc_xcvr/up_cpll_rst_1
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ad_xcvrpll axi_adrv9009_fmc_obs_xcvr/up_pll_rst util_adrv9009_fmc_xcvr/up_cpll_rst_2
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ad_xcvrpll axi_adrv9009_fmc_obs_xcvr/up_pll_rst util_adrv9009_fmc_xcvr/up_cpll_rst_3
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ad_xcvrpll axi_adrv9009_fmc_tx_xcvr/up_pll_rst util_adrv9009_fmc_xcvr/up_qpll_rst_4
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ad_xcvrpll axi_adrv9009_fmc_rx_xcvr/up_pll_rst util_adrv9009_fmc_xcvr/up_cpll_rst_4
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ad_xcvrpll axi_adrv9009_fmc_rx_xcvr/up_pll_rst util_adrv9009_fmc_xcvr/up_cpll_rst_5
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ad_xcvrpll axi_adrv9009_fmc_obs_xcvr/up_pll_rst util_adrv9009_fmc_xcvr/up_cpll_rst_6
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ad_xcvrpll axi_adrv9009_fmc_obs_xcvr/up_pll_rst util_adrv9009_fmc_xcvr/up_cpll_rst_7
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ad_connect sys_cpu_resetn util_adrv9009_fmc_xcvr/up_rstn
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ad_connect sys_cpu_clk util_adrv9009_fmc_xcvr/up_clk
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ad_xcvrcon util_adrv9009_fmc_xcvr axi_adrv9009_fmc_tx_xcvr axi_adrv9009_fmc_tx_jesd {} core_clk_c
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ad_xcvrcon util_adrv9009_fmc_xcvr axi_adrv9009_fmc_rx_xcvr axi_adrv9009_fmc_rx_jesd {0 1 4 5} core_clk_d
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ad_xcvrcon util_adrv9009_fmc_xcvr axi_adrv9009_fmc_obs_xcvr axi_adrv9009_fmc_obs_jesd {2 3 6 7} core_clk_c
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ad_connect core_clk_c tx_adrv9009_fmc_tpl_core/link_clk
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ad_connect axi_adrv9009_fmc_tx_jesd/tx_data tx_adrv9009_fmc_tpl_core/link
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ad_connect core_clk_c util_fmc_tx_upack/clk
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ad_connect core_clk_c_rstgen/peripheral_reset util_fmc_tx_upack/reset
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ad_connect tx_adrv9009_fmc_tpl_core/dac_valid_0 util_fmc_tx_upack/fifo_rd_en
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for {set i 0} {$i < $TX_NUM_OF_CONVERTERS} {incr i} {
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ad_connect util_fmc_tx_upack/fifo_rd_data_$i tx_adrv9009_fmc_tpl_core/dac_data_$i
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ad_connect tx_adrv9009_fmc_tpl_core/dac_enable_$i util_fmc_tx_upack/enable_$i
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}
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ad_connect tx_adrv9009_fmc_tpl_core/dac_dunf util_fmc_tx_upack/fifo_rd_underflow
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ad_connect core_clk_d rx_adrv9009_fmc_tpl_core/link_clk
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ad_connect axi_adrv9009_fmc_rx_jesd/rx_sof rx_adrv9009_fmc_tpl_core/link_sof
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ad_connect axi_adrv9009_fmc_rx_jesd/rx_data_tdata rx_adrv9009_fmc_tpl_core/link_data
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ad_connect axi_adrv9009_fmc_rx_jesd/rx_data_tvalid rx_adrv9009_fmc_tpl_core/link_valid
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ad_connect core_clk_d util_fmc_rx_cpack/clk
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ad_connect core_clk_d_rstgen/peripheral_reset util_fmc_rx_cpack/reset
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ad_connect rx_adrv9009_fmc_tpl_core/adc_valid_0 util_fmc_rx_cpack/fifo_wr_en
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for {set i 0} {$i < $RX_NUM_OF_CONVERTERS} {incr i} {
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ad_connect rx_adrv9009_fmc_tpl_core/adc_enable_$i util_fmc_rx_cpack/enable_$i
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ad_connect rx_adrv9009_fmc_tpl_core/adc_data_$i util_fmc_rx_cpack/fifo_wr_data_$i
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}
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ad_connect rx_adrv9009_fmc_tpl_core/adc_dovf util_fmc_rx_cpack/fifo_wr_overflow
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ad_connect axi_adrv9009_fmc_rx_dma/fifo_wr util_fmc_rx_cpack/packed_fifo_wr
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ad_connect core_clk_d axi_adrv9009_fmc_rx_dma/fifo_wr_clk
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# connections (adc-os)
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ad_connect core_clk_c obs_adrv9009_fmc_tpl_core/link_clk
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ad_connect axi_adrv9009_fmc_obs_jesd/rx_sof obs_adrv9009_fmc_tpl_core/link_sof
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ad_connect axi_adrv9009_fmc_obs_jesd/rx_data_tdata obs_adrv9009_fmc_tpl_core/link_data
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ad_connect axi_adrv9009_fmc_obs_jesd/rx_data_tvalid obs_adrv9009_fmc_tpl_core/link_valid
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ad_connect core_clk_c util_fmc_obs_cpack/clk
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ad_connect core_clk_c_rstgen/peripheral_reset util_fmc_obs_cpack/reset
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ad_connect core_clk_c axi_adrv9009_fmc_obs_dma/fifo_wr_clk
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ad_connect obs_adrv9009_fmc_tpl_core/adc_valid_0 util_fmc_obs_cpack/fifo_wr_en
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for {set i 0} {$i < $OBS_NUM_OF_CONVERTERS} {incr i} {
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ad_connect obs_adrv9009_fmc_tpl_core/adc_enable_$i util_fmc_obs_cpack/enable_$i
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ad_connect obs_adrv9009_fmc_tpl_core/adc_data_$i util_fmc_obs_cpack/fifo_wr_data_$i
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}
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ad_connect obs_adrv9009_fmc_tpl_core/adc_dovf util_fmc_obs_cpack/fifo_wr_overflow
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ad_connect util_fmc_obs_cpack/packed_fifo_wr axi_adrv9009_fmc_obs_dma/fifo_wr
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ad_connect core_clk_c axi_adrv9009_fmc_tx_dma/m_axis_aclk
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ad_connect util_fmc_tx_upack/s_axis_valid VCC_1/dout
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ad_cpu_interconnect 0x45A00000 rx_adrv9009_fmc_tpl_core
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ad_cpu_interconnect 0x45A04000 tx_adrv9009_fmc_tpl_core
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ad_cpu_interconnect 0x45A08000 obs_adrv9009_fmc_tpl_core
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ad_cpu_interconnect 0x45A20000 axi_adrv9009_fmc_tx_xcvr
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ad_cpu_interconnect 0x45A30000 axi_adrv9009_fmc_tx_jesd
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ad_cpu_interconnect 0x45A40000 axi_adrv9009_fmc_rx_xcvr
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ad_cpu_interconnect 0x45A50000 axi_adrv9009_fmc_rx_jesd
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ad_cpu_interconnect 0x45A60000 axi_adrv9009_fmc_obs_xcvr
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ad_cpu_interconnect 0x45A70000 axi_adrv9009_fmc_obs_jesd
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ad_cpu_interconnect 0x7d400000 axi_adrv9009_fmc_tx_dma
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ad_cpu_interconnect 0x7d420000 axi_adrv9009_fmc_rx_dma
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ad_cpu_interconnect 0x7d440000 axi_adrv9009_fmc_obs_dma
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ad_mem_hp0_interconnect $sys_cpu_clk axi_adrv9009_fmc_rx_xcvr/m_axi
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ad_mem_hp0_interconnect $sys_cpu_clk axi_adrv9009_fmc_obs_xcvr/m_axi
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# interconnect (mem/dac)
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ad_mem_hp1_interconnect $sys_dma_clk sys_ps7/S_AXI_HP1
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|
ad_mem_hp1_interconnect $sys_dma_clk axi_adrv9009_fmc_tx_dma/m_src_axi
|
||||||
|
ad_mem_hp2_interconnect $sys_dma_clk sys_ps7/S_AXI_HP2
|
||||||
|
ad_mem_hp2_interconnect $sys_dma_clk axi_adrv9009_fmc_rx_dma/m_dest_axi
|
||||||
|
ad_mem_hp3_interconnect $sys_dma_clk sys_ps7/S_AXI_HP3
|
||||||
|
ad_mem_hp3_interconnect $sys_dma_clk axi_adrv9009_fmc_obs_dma/m_dest_axi
|
||||||
|
ad_connect $sys_dma_resetn axi_adrv9009_fmc_rx_dma/m_dest_axi_aresetn
|
||||||
|
ad_connect $sys_dma_resetn axi_adrv9009_fmc_tx_dma/m_src_axi_aresetn
|
||||||
|
ad_connect $sys_dma_resetn axi_adrv9009_fmc_obs_dma/m_dest_axi_aresetn
|
||||||
|
|
||||||
|
ad_cpu_interrupt ps-2 mb-2 axi_adrv9009_fmc_obs_dma/irq
|
||||||
|
ad_cpu_interrupt ps-3 mb-3 axi_adrv9009_fmc_tx_dma/irq
|
||||||
|
ad_cpu_interrupt ps-4 mb-4 axi_adrv9009_fmc_rx_dma/irq
|
||||||
|
ad_cpu_interrupt ps-5 mb-5 axi_adrv9009_fmc_obs_jesd/irq
|
||||||
|
ad_cpu_interrupt ps-6 mb-6 axi_adrv9009_fmc_tx_jesd/irq
|
||||||
|
ad_cpu_interrupt ps-7 mb-7 axi_adrv9009_fmc_rx_jesd/irq
|
||||||
|
|
@ -0,0 +1,100 @@
|
||||||
|
// ***************************************************************************
|
||||||
|
// ***************************************************************************
|
||||||
|
// Copyright 2014 - 2019 (c) Analog Devices, Inc. All rights reserved.
|
||||||
|
//
|
||||||
|
// In this HDL repository, there are many different and unique modules, consisting
|
||||||
|
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||||
|
// developed independently, and may be accompanied by separate and unique license
|
||||||
|
// terms.
|
||||||
|
//
|
||||||
|
// The user should read each of these license terms, and understand the
|
||||||
|
// freedoms and responsibilities that he or she has by using this source/core.
|
||||||
|
//
|
||||||
|
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||||
|
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||||
|
// A PARTICULAR PURPOSE.
|
||||||
|
//
|
||||||
|
// Redistribution and use of source or resulting binaries, with or without modification
|
||||||
|
// of this file, are permitted under one of the following two license terms:
|
||||||
|
//
|
||||||
|
// 1. The GNU General Public License version 2 as published by the
|
||||||
|
// Free Software Foundation, which can be found in the top level directory
|
||||||
|
// of this repository (LICENSE_GPL2), and also online at:
|
||||||
|
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||||
|
//
|
||||||
|
// OR
|
||||||
|
//
|
||||||
|
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||||
|
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||||
|
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||||
|
// This will allow to generate bit files and not release the source code,
|
||||||
|
// as long as it attaches to an ADI device.
|
||||||
|
//
|
||||||
|
// ***************************************************************************
|
||||||
|
// ***************************************************************************
|
||||||
|
|
||||||
|
`timescale 1ns/100ps
|
||||||
|
|
||||||
|
module fmcomms8_spi (
|
||||||
|
|
||||||
|
input [ 7:0] spi_csn,
|
||||||
|
input spi_clk,
|
||||||
|
input spi_mosi,
|
||||||
|
input spi_miso_i,
|
||||||
|
output spi_miso_o,
|
||||||
|
|
||||||
|
inout spi_sdio);
|
||||||
|
|
||||||
|
// internal registers
|
||||||
|
|
||||||
|
reg [ 5:0] spi_count = 'd0;
|
||||||
|
reg spi_rd_wr_n = 'd0;
|
||||||
|
reg spi_enable = 'd0;
|
||||||
|
|
||||||
|
// internal signals
|
||||||
|
|
||||||
|
wire spi_csn_s;
|
||||||
|
wire spi_enable_s;
|
||||||
|
wire spi_miso_io;
|
||||||
|
|
||||||
|
// check on rising edge and change on falling edge
|
||||||
|
|
||||||
|
assign spi_csn_s = & spi_csn;
|
||||||
|
assign spi_enable_s = spi_enable & (~spi_csn[2]);
|
||||||
|
|
||||||
|
always @(posedge spi_clk or posedge spi_csn_s) begin
|
||||||
|
if (spi_csn_s == 1'b1) begin
|
||||||
|
spi_count <= 6'd0;
|
||||||
|
spi_rd_wr_n <= 1'd0;
|
||||||
|
end else begin
|
||||||
|
spi_count <= (spi_count < 6'h3f) ? spi_count + 1'b1 : spi_count;
|
||||||
|
if (spi_count == 6'd0) begin
|
||||||
|
spi_rd_wr_n <= spi_mosi;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
always @(negedge spi_clk or posedge spi_csn_s) begin
|
||||||
|
if (spi_csn_s == 1'b1) begin
|
||||||
|
spi_enable <= 1'b0;
|
||||||
|
end else begin
|
||||||
|
if (spi_count == 6'd16) begin
|
||||||
|
spi_enable <= spi_rd_wr_n;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
// io buffer
|
||||||
|
|
||||||
|
IOBUF i_iobuf_sdio (
|
||||||
|
.T (spi_enable_s),
|
||||||
|
.I (spi_mosi),
|
||||||
|
.O (spi_miso_io),
|
||||||
|
.IO (spi_sdio));
|
||||||
|
|
||||||
|
assign spi_miso_o = spi_enable_s ? spi_miso_io : spi_miso_i;
|
||||||
|
|
||||||
|
endmodule
|
||||||
|
|
||||||
|
// ***************************************************************************
|
||||||
|
// ***************************************************************************
|
||||||
|
|
@ -0,0 +1,33 @@
|
||||||
|
|
||||||
|
####################################################################################
|
||||||
|
## Copyright 2018(c) Analog Devices, Inc.
|
||||||
|
## Auto-generated, do not modify!
|
||||||
|
####################################################################################
|
||||||
|
|
||||||
|
PROJECT_NAME := fmcomms8_zcu102
|
||||||
|
|
||||||
|
M_DEPS += ../common/fmcomms8_bd.tcl
|
||||||
|
M_DEPS += ../../common/zcu102/zcu102_system_constr.xdc
|
||||||
|
M_DEPS += ../../common/zcu102/zcu102_system_bd.tcl
|
||||||
|
M_DEPS += ../../common/xilinx/dacfifo_bd.tcl
|
||||||
|
M_DEPS += ../../common/xilinx/adi_fir_filter_bd.tcl
|
||||||
|
M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
|
||||||
|
M_DEPS += ../../../library/jesd204/scripts/jesd204.tcl
|
||||||
|
|
||||||
|
LIB_DEPS += jesd204/ad_ip_jesd204_tpl_adc
|
||||||
|
LIB_DEPS += jesd204/ad_ip_jesd204_tpl_dac
|
||||||
|
LIB_DEPS += axi_dmac
|
||||||
|
LIB_DEPS += axi_sysid
|
||||||
|
LIB_DEPS += jesd204/axi_jesd204_rx
|
||||||
|
LIB_DEPS += jesd204/axi_jesd204_tx
|
||||||
|
LIB_DEPS += jesd204/jesd204_rx
|
||||||
|
LIB_DEPS += jesd204/jesd204_tx
|
||||||
|
LIB_DEPS += util_pack/util_cpack2
|
||||||
|
LIB_DEPS += util_pack/util_upack2
|
||||||
|
LIB_DEPS += sysid_rom
|
||||||
|
LIB_DEPS += xilinx/axi_adcfifo
|
||||||
|
LIB_DEPS += xilinx/axi_dacfifo
|
||||||
|
LIB_DEPS += xilinx/axi_adxcvr
|
||||||
|
LIB_DEPS += xilinx/util_adxcvr
|
||||||
|
|
||||||
|
include ../../scripts/project-xilinx.mk
|
||||||
|
|
@ -0,0 +1,12 @@
|
||||||
|
|
||||||
|
source $ad_hdl_dir/projects/common/zcu102/zcu102_system_bd.tcl
|
||||||
|
source $ad_hdl_dir/projects/common/xilinx/dacfifo_bd.tcl
|
||||||
|
|
||||||
|
#system ID
|
||||||
|
ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9
|
||||||
|
ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "[pwd]/mem_init_sys.txt"
|
||||||
|
ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9
|
||||||
|
set sys_cstring "sys rom custom string placeholder"
|
||||||
|
sysid_gen_sys_init_file $sys_cstring
|
||||||
|
|
||||||
|
source ../common/fmcomms8_bd.tcl
|
||||||
|
|
@ -0,0 +1,129 @@
|
||||||
|
|
||||||
|
set_property PACKAGE_PIN G8 [get_ports ref_clk_c_p]; # D04 FMC_HPC0_GBTCLK0_M2C_C_P
|
||||||
|
set_property PACKAGE_PIN G7 [get_ports ref_clk_c_n]; # D05 FMC_HPC0_GBTCLK0_M2C_C_N
|
||||||
|
|
||||||
|
set_property PACKAGE_PIN H2 [get_ports {rx_data_c_p[0]}]; # C06 FMC_HPC0_DP0_M2C_P
|
||||||
|
set_property PACKAGE_PIN H1 [get_ports {rx_data_c_n[0]}]; # C07 FMC_HPC0_DP0_M2C_N
|
||||||
|
set_property PACKAGE_PIN J4 [get_ports {rx_data_c_p[1]}]; # A02 FMC_HPC0_DP1_M2C_P
|
||||||
|
set_property PACKAGE_PIN J3 [get_ports {rx_data_c_n[1]}]; # A03 FMC_HPC0_DP1_M2C_N
|
||||||
|
set_property PACKAGE_PIN F2 [get_ports {rx_data_c_p[2]}]; # A06 FMC_HPC0_DP2_M2C_P
|
||||||
|
set_property PACKAGE_PIN F1 [get_ports {rx_data_c_n[2]}]; # A07 FMC_HPC0_DP2_M2C_N
|
||||||
|
set_property PACKAGE_PIN K2 [get_ports {rx_data_c_p[3]}]; # A10 FMC_HPC0_DP3_M2C_P
|
||||||
|
set_property PACKAGE_PIN K1 [get_ports {rx_data_c_n[3]}]; # A11 FMC_HPC0_DP3_M2C_N
|
||||||
|
set_property PACKAGE_PIN H6 [get_ports {tx_data_c_p[0]}]; # A22 FMC_HPC0_DP1_C2M_P
|
||||||
|
set_property PACKAGE_PIN H5 [get_ports {tx_data_c_n[0]}]; # A23 FMC_HPC0_DP1_C2M_N
|
||||||
|
set_property PACKAGE_PIN G4 [get_ports {tx_data_c_p[1]}]; # C02 FMC_HPC0_DP0_C2M_P
|
||||||
|
set_property PACKAGE_PIN G3 [get_ports {tx_data_c_n[1]}]; # C03 FMC_HPC0_DP0_C2M_N
|
||||||
|
set_property PACKAGE_PIN F6 [get_ports {tx_data_c_p[2]}]; # A26 FMC_HPC0_DP2_C2M_P
|
||||||
|
set_property PACKAGE_PIN F5 [get_ports {tx_data_c_n[2]}]; # A27 FMC_HPC0_DP2_C2M_N
|
||||||
|
set_property PACKAGE_PIN K6 [get_ports {tx_data_c_p[3]}]; # A30 FMC_HPC0_DP3_C2M_P
|
||||||
|
set_property PACKAGE_PIN K5 [get_ports {tx_data_c_n[3]}]; # A31 FMC_HPC0_DP3_C2M_N
|
||||||
|
|
||||||
|
set_property PACKAGE_PIN L8 [get_ports ref_clk_d_p]; # B20 FMC_HPC0_GBTCLK1_M2C_C_P
|
||||||
|
set_property PACKAGE_PIN L7 [get_ports ref_clk_d_n]; # B21 FMC_HPC0_GBTCLK1_M2C_C_N
|
||||||
|
|
||||||
|
set_property PACKAGE_PIN L4 [get_ports {rx_data_d_p[0]}]; # A14 FMC_HPC0_DP4_M2C_P
|
||||||
|
set_property PACKAGE_PIN L3 [get_ports {rx_data_d_n[0]}]; # A15 FMC_HPC0_DP4_M2C_N
|
||||||
|
set_property PACKAGE_PIN P2 [get_ports {rx_data_d_p[1]}]; # A18 FMC_HPC0_DP5_M2C_P
|
||||||
|
set_property PACKAGE_PIN P1 [get_ports {rx_data_d_n[1]}]; # A19 FMC_HPC0_DP5_M2C_N
|
||||||
|
set_property PACKAGE_PIN T2 [get_ports {rx_data_d_p[2]}]; # B16 FMC_HPC0_DP6_M2C_P
|
||||||
|
set_property PACKAGE_PIN T1 [get_ports {rx_data_d_n[2]}]; # B17 FMC_HPC0_DP6_M2C_N
|
||||||
|
set_property PACKAGE_PIN M2 [get_ports {rx_data_d_p[3]}]; # B12 FMC_HPC0_DP7_M2C_P
|
||||||
|
set_property PACKAGE_PIN M1 [get_ports {rx_data_d_n[3]}]; # B13 FMC_HPC0_DP7_M2C_N
|
||||||
|
set_property PACKAGE_PIN M6 [get_ports {tx_data_d_p[0]}]; # A34 FMC_HPC0_DP4_C2M_P
|
||||||
|
set_property PACKAGE_PIN M5 [get_ports {tx_data_d_n[0]}]; # A35 FMC_HPC0_DP4_C2M_N
|
||||||
|
set_property PACKAGE_PIN P6 [get_ports {tx_data_d_p[1]}]; # A38 FMC_HPC0_DP5_C2M_P
|
||||||
|
set_property PACKAGE_PIN P5 [get_ports {tx_data_d_n[1]}]; # A39 FMC_HPC0_DP5_C2M_N
|
||||||
|
set_property PACKAGE_PIN R4 [get_ports {tx_data_d_p[2]}]; # B36 FMC_HPC0_DP6_C2M_P
|
||||||
|
set_property PACKAGE_PIN R3 [get_ports {tx_data_d_n[2]}]; # B37 FMC_HPC0_DP6_C2M_N
|
||||||
|
set_property PACKAGE_PIN N4 [get_ports {tx_data_d_p[3]}]; # B32 FMC_HPC0_DP7_C2M_P
|
||||||
|
set_property PACKAGE_PIN N3 [get_ports {tx_data_d_n[3]}]; # B33 FMC_HPC0_DP7_C2M_N
|
||||||
|
|
||||||
|
set_property -dict {PACKAGE_PIN AA7 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports core_clk_c_p]; # H04 FMC_HPC0_CLK0_M2C_P
|
||||||
|
set_property -dict {PACKAGE_PIN AA6 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports core_clk_c_n]; # H05 FMC_HPC0_CLK0_M2C_N
|
||||||
|
set_property -dict {PACKAGE_PIN T8 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports core_clk_d_p]; # G02 FMC_HPC0_CLK1_M2C_P
|
||||||
|
set_property -dict {PACKAGE_PIN R8 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports core_clk_d_n]; # G03 FMC_HPC0_CLK1_M2C_N
|
||||||
|
|
||||||
|
set_property -dict {PACKAGE_PIN AB6 IOSTANDARD LVDS} [get_ports rx_sync_c_p]; # H16 FMC_HPC0_LA11_P
|
||||||
|
set_property -dict {PACKAGE_PIN AB5 IOSTANDARD LVDS} [get_ports rx_sync_c_n]; # H17 FMC_HPC0_LA11_N
|
||||||
|
set_property -dict {PACKAGE_PIN W7 IOSTANDARD LVDS} [get_ports rx_os_sync_c_p]; # G15 FMC_HPC0_LA12_P
|
||||||
|
set_property -dict {PACKAGE_PIN W6 IOSTANDARD LVDS} [get_ports rx_os_sync_c_n]; # G16 FMC_HPC0_LA12_N
|
||||||
|
set_property -dict {PACKAGE_PIN L13 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports tx_sync_c_p]; # H22 FMC_HPC0_LA19_P
|
||||||
|
set_property -dict {PACKAGE_PIN K13 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports tx_sync_c_n]; # H23 FMC_HPC0_LA19_N
|
||||||
|
set_property -dict {PACKAGE_PIN N13 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports tx_sync_c_1_p]; # G21 FMC_HPC0_LA20_P
|
||||||
|
set_property -dict {PACKAGE_PIN M13 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports tx_sync_c_1_n]; # G22 FMC_HPC0_LA20_N
|
||||||
|
set_property -dict {PACKAGE_PIN AB4 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports sysref_c_p]; # D08 FMC_HPC0_LA01_CC_P
|
||||||
|
set_property -dict {PACKAGE_PIN AC4 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports sysref_c_n]; # D09 FMC_HPC0_LA01_CC_N
|
||||||
|
|
||||||
|
set_property -dict {PACKAGE_PIN W5 IOSTANDARD LVCMOS18} [get_ports adrv9009_tx1_enable_c]; # C14 FMC_HPC0_LA10_P
|
||||||
|
set_property -dict {PACKAGE_PIN W4 IOSTANDARD LVCMOS18} [get_ports adrv9009_tx2_enable_c]; # C15 FMC_HPC0_LA10_N
|
||||||
|
set_property -dict {PACKAGE_PIN AC2 IOSTANDARD LVCMOS18} [get_ports adrv9009_rx1_enable_c]; # C10 FMC_HPC0_LA06_P
|
||||||
|
set_property -dict {PACKAGE_PIN AC1 IOSTANDARD LVCMOS18} [get_ports adrv9009_rx2_enable_c]; # C11 FMC_HPC0_LA06_N
|
||||||
|
set_property -dict {PACKAGE_PIN AB8 IOSTANDARD LVCMOS18} [get_ports adrv9009_reset_b_c]; # D17 FMC_HPC0_LA13_P
|
||||||
|
set_property -dict {PACKAGE_PIN M11 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpint_c]; # G27 FMC_HPC2_LA25_P
|
||||||
|
|
||||||
|
set_property -dict {PACKAGE_PIN U9 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_00_c]; # G30 FMC_HPC0_LA29_P
|
||||||
|
set_property -dict {PACKAGE_PIN V8 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_01_c]; # G33 FMC_HPC0_LA31_P
|
||||||
|
set_property -dict {PACKAGE_PIN V12 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_02_c]; # G36 FMC_HPC0_LA33_P
|
||||||
|
set_property -dict {PACKAGE_PIN V2 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_03_c]; # H07 FMC_HPC0_LA02_P
|
||||||
|
set_property -dict {PACKAGE_PIN AA2 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_04_c]; # H10 FMC_HPC0_LA04_P
|
||||||
|
set_property -dict {PACKAGE_PIN L12 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_05_c]; # H28 FMC_HPC0_LA24_P
|
||||||
|
set_property -dict {PACKAGE_PIN T7 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_06_c]; # H31 FMC_HPC0_LA28_P
|
||||||
|
set_property -dict {PACKAGE_PIN V6 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_07_c]; # H34 FMC_HPC0_LA30_P
|
||||||
|
set_property -dict {PACKAGE_PIN U11 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_08_c]; # H37 FMC_HPC0_LA32_P
|
||||||
|
|
||||||
|
set_property -dict {PACKAGE_PIN Y10 IOSTANDARD LVDS} [get_ports rx_sync_d_p]; # H19 FMC_HPC0_LA15_P
|
||||||
|
set_property -dict {PACKAGE_PIN Y9 IOSTANDARD LVDS} [get_ports rx_sync_d_n]; # H20 FMC_HPC0_LA15_N
|
||||||
|
set_property -dict {PACKAGE_PIN Y12 IOSTANDARD LVDS} [get_ports rx_os_sync_d_p]; # G18 FMC_HPC0_LA16_P
|
||||||
|
set_property -dict {PACKAGE_PIN AA12 IOSTANDARD LVDS} [get_ports rx_os_sync_d_n]; # G19 FMC_HPC0_LA16_N
|
||||||
|
set_property -dict {PACKAGE_PIN P12 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports tx_sync_d_p]; # H25 FMC_HPC0_LA21_P
|
||||||
|
set_property -dict {PACKAGE_PIN N12 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports tx_sync_d_n]; # H26 FMC_HPC0_LA21_N
|
||||||
|
set_property -dict {PACKAGE_PIN M15 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports tx_sync_d_1_p]; # G24 FMC_HPC0_LA22_P
|
||||||
|
set_property -dict {PACKAGE_PIN M14 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports tx_sync_d_1_n]; # G25 FMC_HPC0_LA22_N
|
||||||
|
set_property -dict {PACKAGE_PIN Y4 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports sysref_d_p]; # G06 FMC_HPC0_LA00_CC_P
|
||||||
|
set_property -dict {PACKAGE_PIN Y3 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports sysref_d_n]; # G07 FMC_HPC0_LA00_CC_N
|
||||||
|
|
||||||
|
set_property -dict {PACKAGE_PIN M10 IOSTANDARD LVCMOS18} [get_ports adrv9009_tx1_enable_d]; # C26 FMC_HPC0_LA27_P
|
||||||
|
set_property -dict {PACKAGE_PIN L10 IOSTANDARD LVCMOS18} [get_ports adrv9009_tx2_enable_d]; # C27 FMC_HPC0_LA27_N
|
||||||
|
set_property -dict {PACKAGE_PIN AC7 IOSTANDARD LVCMOS18} [get_ports adrv9009_rx1_enable_d]; # C18 FMC_HPC0_LA14_P
|
||||||
|
set_property -dict {PACKAGE_PIN AC6 IOSTANDARD LVCMOS18} [get_ports adrv9009_rx2_enable_d]; # C19 FMC_HPC0_LA14_N
|
||||||
|
set_property -dict {PACKAGE_PIN AC8 IOSTANDARD LVCMOS18} [get_ports adrv9009_reset_b_d]; # D18 FMC_HPC0_LA13_N
|
||||||
|
set_property -dict {PACKAGE_PIN L11 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpint_d]; # G28 FMC_HPC0_LA25_N
|
||||||
|
set_property -dict {PACKAGE_PIN U8 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_00_d]; # G31 FMC_HPC0_LA29_N
|
||||||
|
set_property -dict {PACKAGE_PIN V7 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_01_d]; # G34 FMC_HPC0_LA31_N
|
||||||
|
set_property -dict {PACKAGE_PIN V11 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_02_d]; # G37 FMC_HPC0_LA33_N
|
||||||
|
set_property -dict {PACKAGE_PIN V1 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_03_d]; # H08 FMC_HPC0_LA02_N
|
||||||
|
set_property -dict {PACKAGE_PIN AA1 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_04_d]; # H11 FMC_HPC0_LA04_N
|
||||||
|
set_property -dict {PACKAGE_PIN K12 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_05_d]; # H29 FMC_HPC0_LA24_N
|
||||||
|
set_property -dict {PACKAGE_PIN T6 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_06_d]; # H32 FMC_HPC0_LA28_N
|
||||||
|
set_property -dict {PACKAGE_PIN U6 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_07_d]; # H35 FMC_HPC0_LA30_N
|
||||||
|
set_property -dict {PACKAGE_PIN T11 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_08_d]; # H38 FMC_HPC0_LA32_N
|
||||||
|
|
||||||
|
set_property -dict {PACKAGE_PIN Y2 IOSTANDARD LVCMOS18} [get_ports hmc7044_reset]; # G09 FMC_HPC0_LA03_P
|
||||||
|
set_property -dict {PACKAGE_PIN Y1 IOSTANDARD LVCMOS18} [get_ports hmc7044_sync]; # G10 FMC_HPC0_LA03_N
|
||||||
|
set_property -dict {PACKAGE_PIN V4 IOSTANDARD LVCMOS18} [get_ports hmc7044_gpio_1]; # G12 FMC_HPC0_LA08_P
|
||||||
|
set_property -dict {PACKAGE_PIN V3 IOSTANDARD LVCMOS18} [get_ports hmc7044_gpio_2]; # G13 FMC_HPC0_LA08_N
|
||||||
|
set_property -dict {PACKAGE_PIN U5 IOSTANDARD LVCMOS18} [get_ports hmc7044_gpio_3]; # H13 FMC_HPC0_LA07_P
|
||||||
|
set_property -dict {PACKAGE_PIN U4 IOSTANDARD LVCMOS18} [get_ports hmc7044_gpio_4]; # H14 FMC_HPC0_LA07_N
|
||||||
|
|
||||||
|
set_property -dict {PACKAGE_PIN L16 IOSTANDARD LVCMOS18} [get_ports spi_clk]; # D23 FMC_HPC0_LA23_P
|
||||||
|
set_property -dict {PACKAGE_PIN K15 IOSTANDARD LVCMOS18} [get_ports spi_sdio]; # D27 FMC_HPC0_LA26_N
|
||||||
|
set_property -dict {PACKAGE_PIN L15 IOSTANDARD LVCMOS18} [get_ports spi_miso]; # D26 FMC_HPC0_LA26_P
|
||||||
|
|
||||||
|
set_property -dict {PACKAGE_PIN AB3 IOSTANDARD LVCMOS18} [get_ports spi_csn_adrv9009_c]; # D11 FMC_HPC0_LA05_P
|
||||||
|
set_property -dict {PACKAGE_PIN W2 IOSTANDARD LVCMOS18} [get_ports spi_csn_adrv9009_d]; # D14 FMC_HPC0_LA09_P
|
||||||
|
set_property -dict {PACKAGE_PIN K16 IOSTANDARD LVCMOS18} [get_ports spi_csn_hmc7044]; # D24 FMC_HPC0_LA23_N
|
||||||
|
|
||||||
|
set_property -dict {PACKAGE_PIN N9 IOSTANDARD LVCMOS18} [get_ports fan_tach]; # C22 FMC_HPC0_LA18_CC_P
|
||||||
|
set_property -dict {PACKAGE_PIN N8 IOSTANDARD LVCMOS18} [get_ports fan_pwm]; # C23 FMC_HPC0_LA18_CC_N
|
||||||
|
|
||||||
|
create_clock -name tx_fmc_dev_clk -period 4.00 [get_ports core_clk_c_p]
|
||||||
|
create_clock -name rx_fmc_dev_clk -period 4.00 [get_ports core_clk_d_p]
|
||||||
|
create_clock -name jesd_tx_fmc_ref_clk -period 4.00 [get_ports ref_clk_c_p]
|
||||||
|
create_clock -name jesd_rx_fmc_ref_clk -period 4.00 [get_ports ref_clk_d_p]
|
||||||
|
|
||||||
|
set_input_delay -clock rx_fmc_dev_clk -max 4 [get_ports sysref_c_p];
|
||||||
|
set_input_delay -clock rx_fmc_dev_clk -min 4 [get_ports sysref_c_p];
|
||||||
|
|
||||||
|
set_input_delay -clock tx_fmc_dev_clk -max 4 [get_ports sysref_d_p];
|
||||||
|
set_input_delay -clock tx_fmc_dev_clk -min 4 [get_ports sysref_d_p];
|
||||||
|
|
@ -0,0 +1,14 @@
|
||||||
|
|
||||||
|
source ../../scripts/adi_env.tcl
|
||||||
|
source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl
|
||||||
|
source $ad_hdl_dir/projects/scripts/adi_board.tcl
|
||||||
|
|
||||||
|
adi_project fmcomms8_zcu102
|
||||||
|
adi_project_files fmcomms8_zcu102 [list \
|
||||||
|
"system_top.v" \
|
||||||
|
"system_constr.xdc"\
|
||||||
|
"../common/fmcomms8_spi.v" \
|
||||||
|
"$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
|
||||||
|
"$ad_hdl_dir/projects/common/zcu102/zcu102_system_constr.xdc" ]
|
||||||
|
|
||||||
|
adi_project_run fmcomms8_zcu102
|
||||||
|
|
@ -0,0 +1,362 @@
|
||||||
|
// ***************************************************************************
|
||||||
|
// ***************************************************************************
|
||||||
|
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
||||||
|
//
|
||||||
|
// In this HDL repository, there are many different and unique modules, consisting
|
||||||
|
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||||
|
// developed independently, and may be accompanied by separate and unique license
|
||||||
|
// terms.
|
||||||
|
//
|
||||||
|
// The user should read each of these license terms, and understand the
|
||||||
|
// freedoms and responsibilities that he or she has by using this source/core.
|
||||||
|
//
|
||||||
|
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||||
|
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||||
|
// A PARTICULAR PURPOSE.
|
||||||
|
//
|
||||||
|
// Redistribution and use of source or resulting binaries, with or without modification
|
||||||
|
// of this file, are permitted under one of the following two license terms:
|
||||||
|
//
|
||||||
|
// 1. The GNU General Public License version 2 as published by the
|
||||||
|
// Free Software Foundation, which can be found in the top level directory
|
||||||
|
// of this repository (LICENSE_GPL2), and also online at:
|
||||||
|
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||||
|
//
|
||||||
|
// OR
|
||||||
|
//
|
||||||
|
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||||
|
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||||
|
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||||
|
// This will allow to generate bit files and not release the source code,
|
||||||
|
// as long as it attaches to an ADI device.
|
||||||
|
//
|
||||||
|
// ***************************************************************************
|
||||||
|
// ***************************************************************************
|
||||||
|
|
||||||
|
`timescale 1ns/100ps
|
||||||
|
|
||||||
|
module system_top (
|
||||||
|
|
||||||
|
input [12:0] gpio_bd_i,
|
||||||
|
output [ 7:0] gpio_bd_o,
|
||||||
|
|
||||||
|
inout iic_scl,
|
||||||
|
inout iic_sda,
|
||||||
|
|
||||||
|
input ref_clk_c_p,
|
||||||
|
input ref_clk_c_n,
|
||||||
|
input core_clk_c_p,
|
||||||
|
input core_clk_c_n,
|
||||||
|
input [ 3:0] rx_data_c_p,
|
||||||
|
input [ 3:0] rx_data_c_n,
|
||||||
|
output [ 3:0] tx_data_c_p,
|
||||||
|
output [ 3:0] tx_data_c_n,
|
||||||
|
|
||||||
|
output rx_sync_c_p,
|
||||||
|
output rx_sync_c_n,
|
||||||
|
output rx_os_sync_c_p,
|
||||||
|
output rx_os_sync_c_n,
|
||||||
|
input tx_sync_c_p,
|
||||||
|
input tx_sync_c_n,
|
||||||
|
input tx_sync_c_1_p,
|
||||||
|
input tx_sync_c_1_n,
|
||||||
|
input sysref_c_p,
|
||||||
|
input sysref_c_n,
|
||||||
|
|
||||||
|
inout adrv9009_tx1_enable_c,
|
||||||
|
inout adrv9009_tx2_enable_c,
|
||||||
|
inout adrv9009_rx1_enable_c,
|
||||||
|
inout adrv9009_rx2_enable_c,
|
||||||
|
inout adrv9009_test_c,
|
||||||
|
inout adrv9009_reset_b_c,
|
||||||
|
inout adrv9009_gpint_c,
|
||||||
|
|
||||||
|
inout adrv9009_gpio_00_c,
|
||||||
|
inout adrv9009_gpio_01_c,
|
||||||
|
inout adrv9009_gpio_02_c,
|
||||||
|
inout adrv9009_gpio_03_c,
|
||||||
|
inout adrv9009_gpio_04_c,
|
||||||
|
inout adrv9009_gpio_05_c,
|
||||||
|
inout adrv9009_gpio_06_c,
|
||||||
|
inout adrv9009_gpio_07_c,
|
||||||
|
inout adrv9009_gpio_08_c,
|
||||||
|
|
||||||
|
input ref_clk_d_p,
|
||||||
|
input ref_clk_d_n,
|
||||||
|
input core_clk_d_p,
|
||||||
|
input core_clk_d_n,
|
||||||
|
input [ 3:0] rx_data_d_p,
|
||||||
|
input [ 3:0] rx_data_d_n,
|
||||||
|
output [ 3:0] tx_data_d_p,
|
||||||
|
output [ 3:0] tx_data_d_n,
|
||||||
|
|
||||||
|
output rx_sync_d_p,
|
||||||
|
output rx_sync_d_n,
|
||||||
|
output rx_os_sync_d_p,
|
||||||
|
output rx_os_sync_d_n,
|
||||||
|
input tx_sync_d_p,
|
||||||
|
input tx_sync_d_n,
|
||||||
|
input tx_sync_d_1_p,
|
||||||
|
input tx_sync_d_1_n,
|
||||||
|
input sysref_d_p,
|
||||||
|
input sysref_d_n,
|
||||||
|
|
||||||
|
inout adrv9009_tx1_enable_d,
|
||||||
|
inout adrv9009_tx2_enable_d,
|
||||||
|
inout adrv9009_rx1_enable_d,
|
||||||
|
inout adrv9009_rx2_enable_d,
|
||||||
|
inout adrv9009_test_d,
|
||||||
|
inout adrv9009_reset_b_d,
|
||||||
|
inout adrv9009_gpint_d,
|
||||||
|
|
||||||
|
inout adrv9009_gpio_00_d,
|
||||||
|
inout adrv9009_gpio_01_d,
|
||||||
|
inout adrv9009_gpio_02_d,
|
||||||
|
inout adrv9009_gpio_03_d,
|
||||||
|
inout adrv9009_gpio_04_d,
|
||||||
|
inout adrv9009_gpio_05_d,
|
||||||
|
inout adrv9009_gpio_06_d,
|
||||||
|
inout adrv9009_gpio_07_d,
|
||||||
|
inout adrv9009_gpio_08_d,
|
||||||
|
|
||||||
|
input fan_tach,
|
||||||
|
input fan_pwm,
|
||||||
|
output hmc7044_reset,
|
||||||
|
inout hmc7044_sync,
|
||||||
|
inout hmc7044_gpio_1,
|
||||||
|
inout hmc7044_gpio_2,
|
||||||
|
inout hmc7044_gpio_3,
|
||||||
|
inout hmc7044_gpio_4,
|
||||||
|
output spi_csn_hmc7044,
|
||||||
|
output spi_csn_adrv9009_c,
|
||||||
|
output spi_csn_adrv9009_d,
|
||||||
|
|
||||||
|
output spi_clk,
|
||||||
|
inout spi_sdio,
|
||||||
|
input spi_miso
|
||||||
|
);
|
||||||
|
|
||||||
|
// internal signals
|
||||||
|
|
||||||
|
wire [94:0] gpio_i;
|
||||||
|
wire [94:0] gpio_o;
|
||||||
|
wire [94:0] gpio_t;
|
||||||
|
wire [20:0] gpio_bd;
|
||||||
|
|
||||||
|
wire [2:0] spi_csn;
|
||||||
|
|
||||||
|
wire ref_clk_c;
|
||||||
|
wire core_clk_c;
|
||||||
|
wire rx_sync_rx;
|
||||||
|
wire tx_sync_c;
|
||||||
|
wire sysref_c;
|
||||||
|
wire ref_clk_d;
|
||||||
|
wire core_clk_d;
|
||||||
|
wire rx_sync_obs;
|
||||||
|
wire rx_os_sync_d;
|
||||||
|
wire tx_sync_d;
|
||||||
|
wire sysref_d;
|
||||||
|
wire tx_sync;
|
||||||
|
wire spi_mosi;
|
||||||
|
wire spi0_miso;
|
||||||
|
|
||||||
|
reg [7:0] spi_3_to_8_csn;
|
||||||
|
|
||||||
|
always @(*) begin
|
||||||
|
case (spi_csn)
|
||||||
|
3'h0: spi_3_to_8_csn = 8'b11111110;
|
||||||
|
3'h1: spi_3_to_8_csn = 8'b11111101;
|
||||||
|
3'h2: spi_3_to_8_csn = 8'b11111011;
|
||||||
|
default: spi_3_to_8_csn = 8'b11111111;
|
||||||
|
endcase
|
||||||
|
end
|
||||||
|
|
||||||
|
assign spi_csn_adrv9009_c = spi_3_to_8_csn[0];
|
||||||
|
assign spi_csn_adrv9009_d = spi_3_to_8_csn[1];
|
||||||
|
assign spi_csn_hmc7044 = spi_3_to_8_csn[2];
|
||||||
|
|
||||||
|
fmcomms8_spi i_spi (
|
||||||
|
.spi_csn(spi_3_to_8_csn),
|
||||||
|
.spi_clk(spi_clk),
|
||||||
|
.spi_mosi(spi_mosi),
|
||||||
|
.spi_miso_i(spi_miso),
|
||||||
|
.spi_miso_o(spi0_miso),
|
||||||
|
.spi_sdio(spi_sdio));
|
||||||
|
|
||||||
|
assign tx_sync = tx_sync_c & tx_sync_d;
|
||||||
|
|
||||||
|
assign gpio_i[94:68] = gpio_o[94:68];
|
||||||
|
assign gpio_i[31:21] = gpio_o[31:21];
|
||||||
|
assign gpio_i[ 7: 0] = gpio_o[ 7: 0];
|
||||||
|
assign gpio_i[20: 8] = gpio_bd_i;
|
||||||
|
assign gpio_bd_o = gpio_o[ 7: 0];
|
||||||
|
|
||||||
|
// instantiations
|
||||||
|
ad_iobuf #(.DATA_WIDTH(36)) i_iobuf (
|
||||||
|
.dio_t ({gpio_t[67:32]}),
|
||||||
|
.dio_i ({gpio_o[67:32]}),
|
||||||
|
.dio_o ({gpio_i[67:32]}),
|
||||||
|
.dio_p ({
|
||||||
|
hmc7044_gpio_4, // 67
|
||||||
|
hmc7044_gpio_3, // 66
|
||||||
|
hmc7044_gpio_2, // 65
|
||||||
|
hmc7044_gpio_1, // 64
|
||||||
|
hmc7044_sync, // 63
|
||||||
|
hmc7044_reset, // 62
|
||||||
|
adrv9009_tx2_enable_d, // 61
|
||||||
|
adrv9009_tx1_enable_d, // 60
|
||||||
|
adrv9009_rx2_enable_d, // 59
|
||||||
|
adrv9009_rx1_enable_d, // 58
|
||||||
|
adrv9009_reset_b_d, // 57
|
||||||
|
adrv9009_gpint_d, // 56
|
||||||
|
adrv9009_gpio_08_d, // 55
|
||||||
|
adrv9009_gpio_07_d, // 54
|
||||||
|
adrv9009_gpio_06_d, // 53
|
||||||
|
adrv9009_gpio_05_d, // 52
|
||||||
|
adrv9009_gpio_04_d, // 51
|
||||||
|
adrv9009_gpio_03_d, // 50
|
||||||
|
adrv9009_gpio_02_d, // 49
|
||||||
|
adrv9009_gpio_01_d, // 48
|
||||||
|
adrv9009_gpio_00_d, // 47
|
||||||
|
adrv9009_tx2_enable_c, // 46
|
||||||
|
adrv9009_tx1_enable_c, // 45
|
||||||
|
adrv9009_rx2_enable_c, // 44
|
||||||
|
adrv9009_rx1_enable_c, // 43
|
||||||
|
adrv9009_reset_b_c, // 42
|
||||||
|
adrv9009_gpint_c, // 41
|
||||||
|
adrv9009_gpio_08_c, // 40
|
||||||
|
adrv9009_gpio_07_c, // 39
|
||||||
|
adrv9009_gpio_06_c, // 38
|
||||||
|
adrv9009_gpio_05_c, // 37
|
||||||
|
adrv9009_gpio_04_c, // 36
|
||||||
|
adrv9009_gpio_03_c, // 35
|
||||||
|
adrv9009_gpio_02_c, // 34
|
||||||
|
adrv9009_gpio_01_c, // 33
|
||||||
|
adrv9009_gpio_00_c})); // 32
|
||||||
|
|
||||||
|
IBUFDS_GTE4 i_ibufds_ref_clk_1 (
|
||||||
|
.CEB (1'd0),
|
||||||
|
.I (ref_clk_c_p),
|
||||||
|
.IB (ref_clk_c_n),
|
||||||
|
.O (ref_clk_c),
|
||||||
|
.ODIV2 ());
|
||||||
|
|
||||||
|
IBUFDS_GTE4 i_ibufds_ref_clk_2 (
|
||||||
|
.CEB (1'd0),
|
||||||
|
.I (ref_clk_d_p),
|
||||||
|
.IB (ref_clk_d_n),
|
||||||
|
.O (ref_clk_d),
|
||||||
|
.ODIV2 ());
|
||||||
|
|
||||||
|
IBUFDS i_ibufds_sysref_1 (
|
||||||
|
.I (sysref_c_p),
|
||||||
|
.IB (sysref_c_n),
|
||||||
|
.O (sysref_c));
|
||||||
|
|
||||||
|
IBUFDS i_ibufds_sysref_2 (
|
||||||
|
.I (sysref_d_p),
|
||||||
|
.IB (sysref_d_n),
|
||||||
|
.O (sysref_d));
|
||||||
|
|
||||||
|
IBUFGDS i_rx_clk_ibufg_1 (
|
||||||
|
.I (core_clk_c_p),
|
||||||
|
.IB (core_clk_c_n),
|
||||||
|
.O (core_clk_c));
|
||||||
|
|
||||||
|
IBUFGDS i_rx_clk_ibufg_2 (
|
||||||
|
.I (core_clk_d_p),
|
||||||
|
.IB (core_clk_d_n),
|
||||||
|
.O (core_clk_d));
|
||||||
|
|
||||||
|
IBUFDS i_ibufds_tx_sync_1 (
|
||||||
|
.I (tx_sync_c_p),
|
||||||
|
.IB (tx_sync_c_n),
|
||||||
|
.O (tx_sync_c));
|
||||||
|
|
||||||
|
IBUFDS i_ibufds_tx_sync_2 (
|
||||||
|
.I (tx_sync_d_p),
|
||||||
|
.IB (tx_sync_d_n),
|
||||||
|
.O (tx_sync_d));
|
||||||
|
|
||||||
|
OBUFDS i_obufds_rx_sync_1 (
|
||||||
|
.I (rx_sync_rx),
|
||||||
|
.O (rx_sync_c_p),
|
||||||
|
.OB (rx_sync_c_n));
|
||||||
|
|
||||||
|
OBUFDS i_obufds_rx_os_sync_1 (
|
||||||
|
.I (rx_sync_obs),
|
||||||
|
.O (rx_os_sync_c_p),
|
||||||
|
.OB (rx_os_sync_c_n));
|
||||||
|
|
||||||
|
OBUFDS i_obufds_rx_sync_2 (
|
||||||
|
.I (rx_sync_rx),
|
||||||
|
.O (rx_sync_d_p),
|
||||||
|
.OB (rx_sync_d_n));
|
||||||
|
|
||||||
|
OBUFDS i_obufds_rx_os_sync_2 (
|
||||||
|
.I (rx_sync_obs),
|
||||||
|
.O (rx_os_sync_d_p),
|
||||||
|
.OB (rx_os_sync_d_n));
|
||||||
|
|
||||||
|
system_wrapper i_system_wrapper (
|
||||||
|
.gpio_i (gpio_i),
|
||||||
|
.gpio_o (gpio_o),
|
||||||
|
.gpio_t (gpio_t),
|
||||||
|
|
||||||
|
.core_clk_c(core_clk_c),
|
||||||
|
.core_clk_d(core_clk_d),
|
||||||
|
.ref_clk_c(ref_clk_c),
|
||||||
|
.ref_clk_d(ref_clk_d),
|
||||||
|
.rx_data_0_n (rx_data_c_n[0]),
|
||||||
|
.rx_data_0_p (rx_data_c_p[0]),
|
||||||
|
.rx_data_1_n (rx_data_c_n[1]),
|
||||||
|
.rx_data_1_p (rx_data_c_p[1]),
|
||||||
|
.rx_data_2_n (rx_data_c_n[2]),
|
||||||
|
.rx_data_2_p (rx_data_c_p[2]),
|
||||||
|
.rx_data_3_n (rx_data_c_n[3]),
|
||||||
|
.rx_data_3_p (rx_data_c_p[3]),
|
||||||
|
.rx_data_4_n (rx_data_d_n[0]),
|
||||||
|
.rx_data_4_p (rx_data_d_p[0]),
|
||||||
|
.rx_data_5_n (rx_data_d_n[1]),
|
||||||
|
.rx_data_5_p (rx_data_d_p[1]),
|
||||||
|
.rx_data_6_n (rx_data_d_n[2]),
|
||||||
|
.rx_data_6_p (rx_data_d_p[2]),
|
||||||
|
.rx_data_7_n (rx_data_d_n[3]),
|
||||||
|
.rx_data_7_p (rx_data_d_p[3]),
|
||||||
|
.rx_sync_0 (rx_sync_rx),
|
||||||
|
.rx_sync_4 (rx_sync_obs),
|
||||||
|
.rx_sysref_0 (sysref_d),
|
||||||
|
.rx_sysref_4 (sysref_c),
|
||||||
|
.tx_data_0_n (tx_data_c_n[0]),
|
||||||
|
.tx_data_0_p (tx_data_c_p[0]),
|
||||||
|
.tx_data_1_n (tx_data_c_n[1]),
|
||||||
|
.tx_data_1_p (tx_data_c_p[1]),
|
||||||
|
.tx_data_2_n (tx_data_c_n[2]),
|
||||||
|
.tx_data_2_p (tx_data_c_p[2]),
|
||||||
|
.tx_data_3_n (tx_data_c_n[3]),
|
||||||
|
.tx_data_3_p (tx_data_c_p[3]),
|
||||||
|
.tx_data_4_n (tx_data_d_n[0]),
|
||||||
|
.tx_data_4_p (tx_data_d_p[0]),
|
||||||
|
.tx_data_5_n (tx_data_d_n[1]),
|
||||||
|
.tx_data_5_p (tx_data_d_p[1]),
|
||||||
|
.tx_data_6_n (tx_data_d_n[2]),
|
||||||
|
.tx_data_6_p (tx_data_d_p[2]),
|
||||||
|
.tx_data_7_n (tx_data_d_n[3]),
|
||||||
|
.tx_data_7_p (tx_data_d_p[3]),
|
||||||
|
.tx_sync_0 (tx_sync),
|
||||||
|
.tx_sysref_0 (sysref_c),
|
||||||
|
//.dac_fifo_bypass(gpio_o[90]),
|
||||||
|
|
||||||
|
.spi0_sclk (spi_clk),
|
||||||
|
.spi0_csn (spi_csn),
|
||||||
|
.spi0_miso (spi_miso),
|
||||||
|
.spi0_mosi (spi_mosi),
|
||||||
|
.spi1_sclk (),
|
||||||
|
.spi1_csn (),
|
||||||
|
.spi1_miso (1'b0),
|
||||||
|
.spi1_mosi ());
|
||||||
|
|
||||||
|
endmodule
|
||||||
|
|
||||||
|
// ***************************************************************************
|
||||||
|
// ***************************************************************************
|
||||||
Loading…
Reference in New Issue