From 01748d4364595c0d93cc798944a9fe1f50bcf2d8 Mon Sep 17 00:00:00 2001 From: Laszlo Nagy Date: Fri, 12 Apr 2019 15:44:07 +0100 Subject: [PATCH] jesd204:axi_jesd204_tx: set OOC default clock constraints --- library/jesd204/axi_jesd204_tx/Makefile | 1 + .../axi_jesd204_tx/axi_jesd204_tx_ip.tcl | 3 + .../axi_jesd204_tx/axi_jesd204_tx_ooc.ttcl | 61 +++++++++++++++++++ 3 files changed, 65 insertions(+) create mode 100644 library/jesd204/axi_jesd204_tx/axi_jesd204_tx_ooc.ttcl diff --git a/library/jesd204/axi_jesd204_tx/Makefile b/library/jesd204/axi_jesd204_tx/Makefile index b650e067a..35a67ddd9 100644 --- a/library/jesd204/axi_jesd204_tx/Makefile +++ b/library/jesd204/axi_jesd204_tx/Makefile @@ -10,6 +10,7 @@ GENERIC_DEPS += axi_jesd204_tx.v GENERIC_DEPS += jesd204_up_tx.v XILINX_DEPS += axi_jesd204_tx_constr.xdc +XILINX_DEPS += axi_jesd204_tx_ooc.ttcl XILINX_DEPS += axi_jesd204_tx_ip.tcl XILINX_DEPS += ../../jesd204/interfaces/jesd204_tx_cfg.xml diff --git a/library/jesd204/axi_jesd204_tx/axi_jesd204_tx_ip.tcl b/library/jesd204/axi_jesd204_tx/axi_jesd204_tx_ip.tcl index 9371a18f5..cebc9bbb2 100644 --- a/library/jesd204/axi_jesd204_tx/axi_jesd204_tx_ip.tcl +++ b/library/jesd204/axi_jesd204_tx/axi_jesd204_tx_ip.tcl @@ -49,12 +49,15 @@ adi_ip_create axi_jesd204_tx adi_ip_files axi_jesd204_tx [list \ "../../common/up_axi.v" \ "axi_jesd204_tx_constr.xdc" \ + "axi_jesd204_tx_ooc.ttcl" \ "jesd204_up_tx.v" \ "axi_jesd204_tx.v" \ ] adi_ip_properties axi_jesd204_tx +adi_ip_ttcl axi_jesd204_tx "axi_jesd204_tx_ooc.ttcl" + set_property PROCESSING_ORDER LATE [ipx::get_files axi_jesd204_tx_constr.xdc \ -of_objects [ipx::get_file_groups -of_objects [ipx::current_core] \ -filter {NAME =~ *synthesis*}]] diff --git a/library/jesd204/axi_jesd204_tx/axi_jesd204_tx_ooc.ttcl b/library/jesd204/axi_jesd204_tx/axi_jesd204_tx_ooc.ttcl new file mode 100644 index 000000000..e2732e424 --- /dev/null +++ b/library/jesd204/axi_jesd204_tx/axi_jesd204_tx_ooc.ttcl @@ -0,0 +1,61 @@ +# +# The ADI JESD204 Core is released under the following license, which is +# different than all other HDL cores in this repository. +# +# Please read this, and understand the freedoms and responsibilities you have +# by using this source code/core. +# +# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc. +# +# This core is free software, you can use run, copy, study, change, ask +# questions about and improve this core. Distribution of source, or resulting +# binaries (including those inside an FPGA or ASIC) require you to release the +# source of the entire project (excluding the system libraries provide by the +# tools/compiler/FPGA vendor). These are the terms of the GNU General Public +# License version 2 as published by the Free Software Foundation. +# +# This core is distributed in the hope that it will be useful, but WITHOUT ANY +# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +# A PARTICULAR PURPOSE. See the GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License version 2 +# along with this source code, and binary. If not, see +# . +# +# Commercial licenses (with commercial support) of this JESD204 core are also +# available under terms different than the General Public License. (e.g. they +# do not require you to accompany any image (FPGA or ASIC) using the JESD204 +# core with any corresponding source code.) For these alternate terms you must +# purchase a license from Analog Devices Technology Licensing Office. Users +# interested in such a license should contact jesd204-licensing@analog.com for +# more information. This commercial license is sub-licensable (if you purchase +# chips from Analog Devices, incorporate them into your PCB level product, and +# purchase a JESD204 license, end users of your product will also have a +# license to use this core in a commercial setting without releasing their +# source code). +# +# In addition, we kindly ask you to acknowledge ADI in any program, application +# or publication in which you use this JESD204 HDL core. (You are not required +# to do so; it is up to your common sense to decide whether you want to comply +# with this request or not.) For general publications, we suggest referencing : +# “The design and implementation of the JESD204 HDL Core used in this project +# is copyright © 2016-2017, Analog Devices, Inc.” +# + +<: setFileUsedIn { out_of_context synthesis implementation } :> +<: ;#Component and file information :> +<: set ComponentName [getComponentNameString] :> +<: setOutputDirectory "./" :> +<: setFileName $ComponentName :> +<: setFileExtension "_ooc.xdc" :> + +# This XDC is used only for OOC mode of synthesis, implementation. +# These are default values for timing driven synthesis during OOC flow. +# These values will be overwritten during implementation with information +# from top level. + +create_clock -name s_axi_aclk -period 10 [get_ports s_axi_aclk] +create_clock -name core_clk -period 2.5 [get_ports core_clk] + +################################################################################ +