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axi_dmac: fix transfer length reporting cyclic mode 

Let the measured transfer length to be cleared at the end of each
transfer, other case in cyclic mode the counter will overflow and will
not present any useful information.
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Laszlo Nagy 2018-11-21 14:24:54 +00:00 committed by Laszlo Nagy
parent 42a7e87cb3
commit 01a2bab978
1 changed files with 1 additions and 1 deletions
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2
library/axi_dmac/axi_dmac_regmap_request.v
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@ -277,7 +277,7 @@ always @(posedge clk)
begin begin
if (response_valid == 1'b1 && response_ready == 1'b1) begin if (response_valid == 1'b1 && response_ready == 1'b1) begin
up_tlf_s_valid <= up_bl_partial; up_tlf_s_valid <= up_bl_partial;
up_clear_tl <= up_eot; up_clear_tl <= response_eot;
end else if (up_tlf_s_ready == 1'b1) begin end else if (up_tlf_s_ready == 1'b1) begin
up_tlf_s_valid <= 1'b0; up_tlf_s_valid <= 1'b0;
end end