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Create CDC helper library 

Move the CDC helper modules to a dedicated helper modules. This makes it
possible to reference them without having to use file paths that go outside
of the referencing project's directory.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
main
Lars-Peter Clausen 2017-05-18 15:12:01 +02:00
parent ed23eb950e
commit 01aea161fa
26 changed files with 151 additions and 42 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
library/Makefile
View File

@ -64,6 +64,7 @@ clean:
make -C util_axis_resize clean
make -C util_bsplit clean
make -C util_ccat clean
make -C util_cdc clean
make -C util_cic clean
make -C util_clkdiv clean
make -C util_cpack clean
@ -150,6 +151,7 @@ lib:
make -C util_axis_resize
make -C util_bsplit
make -C util_ccat
make -C util_cdc
make -C util_cic
make -C util_clkdiv
make -C util_cpack

9
library/axi_ad5766/Makefile
View File

@ -6,7 +6,6 @@
####################################################################################
M_DEPS += ../common/ad_rst.v
M_DEPS += ../common/sync_bits.v
M_DEPS += ../common/up_axi.v
M_DEPS += ../common/up_clock_mon.v
M_DEPS += ../common/up_dac_common.v
@ -19,6 +18,8 @@ M_DEPS += axi_ad5766.v
M_DEPS += axi_ad5766_ip.tcl
M_DEPS += up_ad5766_sequencer.v
M_DEPS += ../util_cdc/util_cdc.xpr
M_DEPS += ../interfaces/fifo_rd.xml
M_DEPS += ../interfaces/fifo_rd_rtl.xml
M_DEPS += ../spi_engine/interfaces/spi_engine_ctrl.xml
@ -43,8 +44,8 @@ M_FLIST += .Xil
.PHONY: all clean clean-all
all: axi_ad5766.xpr
.PHONY: all dep clean clean-all
all: dep axi_ad5766.xpr
clean:clean-all
@ -58,5 +59,7 @@ axi_ad5766.xpr: $(M_DEPS)
-rm -rf $(M_FLIST)
$(M_VIVADO) axi_ad5766_ip.tcl >> axi_ad5766_ip.log 2>&1
dep:
make -C ../util_cdc/
####################################################################################
####################################################################################

5
library/axi_ad5766/axi_ad5766_ip.tcl
View File

@ -7,7 +7,6 @@ adi_ip_create axi_ad5766
adi_ip_files axi_ad5766 [list \
"$ad_hdl_dir/library/common/up_xfer_cntrl.v" \
"$ad_hdl_dir/library/common/up_xfer_status.v" \
"$ad_hdl_dir/library/common/sync_bits.v" \
"$ad_hdl_dir/library/common/ad_rst.v" \
"$ad_hdl_dir/library/common/up_dac_common.v" \
"$ad_hdl_dir/library/common/up_clock_mon.v" \
@ -18,6 +17,10 @@ adi_ip_files axi_ad5766 [list \
adi_ip_properties axi_ad5766
adi_ip_add_core_dependencies { \
analog.com:user:util_cdc:1.0 \
}
adi_add_bus "spi_engine_ctrl" "master" \
"analog.com:interface:spi_engine_ctrl_rtl:1.0" \
"analog.com:interface:spi_engine_ctrl:1.0" \

3
library/axi_dmac/Makefile
View File

@ -5,7 +5,6 @@
####################################################################################
####################################################################################
M_DEPS += ../common/sync_bits.v
M_DEPS += ../common/up_axi.v
M_DEPS += ../scripts/adi_env.tcl
M_DEPS += ../scripts/adi_ip.tcl
@ -29,6 +28,7 @@ M_DEPS += src_fifo_inf.v
M_DEPS += ../util_axis_fifo/util_axis_fifo.xpr
M_DEPS += ../util_axis_resize/util_axis_resize.xpr
M_DEPS += ../util_cdc/util_cdc.xpr
M_DEPS += ../interfaces/fifo_rd.xml
M_DEPS += ../interfaces/fifo_rd_rtl.xml
@ -70,5 +70,6 @@ axi_dmac.xpr: $(M_DEPS)
dep:
make -C ../util_axis_fifo/
make -C ../util_axis_resize/
make -C ../util_cdc/
####################################################################################
####################################################################################

4
library/axi_dmac/axi_dmac_hw.tcl
View File

@ -15,8 +15,8 @@ set_module_property ELABORATION_CALLBACK axi_dmac_elaborate
add_fileset quartus_synth QUARTUS_SYNTH "" "Quartus Synthesis"
set_fileset_property quartus_synth TOP_LEVEL axi_dmac
add_fileset_file sync_bits.v VERILOG PATH $ad_hdl_dir/library/common/sync_bits.v
add_fileset_file sync_gray.v VERILOG PATH $ad_hdl_dir/library/common/sync_gray.v
add_fileset_file sync_bits.v VERILOG PATH $ad_hdl_dir/library/util_cdc/sync_bits.v
add_fileset_file sync_gray.v VERILOG PATH $ad_hdl_dir/library/util_cdc/sync_gray.v
add_fileset_file up_axi.v VERILOG PATH $ad_hdl_dir/library/common/up_axi.v
add_fileset_file axi_repack.v VERILOG PATH $ad_hdl_dir/library/util_axis_resize/util_axis_resize.v
add_fileset_file fifo.v VERILOG PATH $ad_hdl_dir/library/util_axis_fifo/util_axis_fifo.v

2
library/axi_dmac/axi_dmac_ip.tcl
View File

@ -5,7 +5,6 @@ source $ad_hdl_dir/library/scripts/adi_ip.tcl
adi_ip_create axi_dmac
adi_ip_files axi_dmac [list \
"$ad_hdl_dir/library/common/sync_bits.v" \
"$ad_hdl_dir/library/common/up_axi.v" \
"address_generator.v" \
"data_mover.v" \
@ -34,6 +33,7 @@ adi_ip_bd axi_dmac "bd/bd.tcl"
adi_ip_add_core_dependencies { \
analog.com:user:util_axis_resize:1.0 \
analog.com:user:util_axis_fifo:1.0 \
analog.com:user:util_cdc:1.0 \
}
set_property display_name "ADI AXI DMA Controller" [ipx::current_core]

4
library/spi_engine/axi_spi_engine/Makefile
View File

@ -6,8 +6,6 @@
####################################################################################
M_DEPS += ../../common/ad_rst.v
M_DEPS += ../../common/sync_bits.v
M_DEPS += ../../common/sync_gray.v
M_DEPS += ../../common/up_axi.v
M_DEPS += ../../scripts/adi_env.tcl
M_DEPS += ../../scripts/adi_ip.tcl
@ -15,6 +13,7 @@ M_DEPS += axi_spi_engine.v
M_DEPS += axi_spi_engine_ip.tcl
M_DEPS += ../../util_axis_fifo/util_axis_fifo.xpr
M_DEPS += ../../util_cdc/util_cdc.xpr
M_DEPS += ../../spi_engine/interfaces/spi_engine_ctrl.xml
M_DEPS += ../../spi_engine/interfaces/spi_engine_ctrl_rtl.xml
@ -55,5 +54,6 @@ axi_spi_engine.xpr: $(M_DEPS)
dep:
make -C ../../util_axis_fifo/
make -C ../../util_cdc/
####################################################################################
####################################################################################

3
library/spi_engine/axi_spi_engine/axi_spi_engine_ip.tcl
View File

@ -6,8 +6,6 @@ source $ad_hdl_dir/library/scripts/adi_ip.tcl
adi_ip_create axi_spi_engine
adi_ip_files axi_spi_engine [list \
"axi_spi_engine.v" \
"$ad_hdl_dir/library/common/sync_bits.v" \
"$ad_hdl_dir/library/common/sync_gray.v" \
"$ad_hdl_dir/library/common/up_axi.v" \
"$ad_hdl_dir/library/common/ad_rst.v" \
]
@ -20,6 +18,7 @@ ipx::remove_bus_interface spi_signal_reset [ipx::current_core]
adi_ip_add_core_dependencies { \
analog.com:user:util_axis_fifo:1.0 \
analog.com:user:util_cdc:1.0 \
}
adi_add_bus "spi_engine_ctrl" "master" \

9
library/spi_engine/spi_engine_offload/Makefile
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@ -5,12 +5,13 @@
####################################################################################
####################################################################################
M_DEPS += ../../common/sync_bits.v
M_DEPS += ../../scripts/adi_env.tcl
M_DEPS += ../../scripts/adi_ip.tcl
M_DEPS += spi_engine_offload.v
M_DEPS += spi_engine_offload_ip.tcl
M_DEPS += ../../util_cdc/util_cdc.xpr
M_DEPS += ../../spi_engine/interfaces/spi_engine_ctrl.xml
M_DEPS += ../../spi_engine/interfaces/spi_engine_ctrl_rtl.xml
M_DEPS += ../../spi_engine/interfaces/spi_engine_offload_ctrl.xml
@ -33,8 +34,8 @@ M_FLIST += .Xil
.PHONY: all clean clean-all
all: spi_engine_offload.xpr
.PHONY: all dep clean clean-all
all: dep spi_engine_offload.xpr
clean:clean-all
@ -48,5 +49,7 @@ spi_engine_offload.xpr: $(M_DEPS)
-rm -rf $(M_FLIST)
$(M_VIVADO) spi_engine_offload_ip.tcl >> spi_engine_offload_ip.log 2>&1
dep:
make -C ../../util_cdc/
####################################################################################
####################################################################################

5
library/spi_engine/spi_engine_offload/spi_engine_offload_ip.tcl
View File

@ -3,7 +3,6 @@ source $ad_hdl_dir/library/scripts/adi_ip.tcl
adi_ip_create spi_engine_offload
adi_ip_files spi_engine_offload [list \
"$ad_hdl_dir/library/common/sync_bits.v" \
"spi_engine_offload.v" \
]
@ -11,6 +10,10 @@ adi_ip_properties_lite spi_engine_offload
# Remove all inferred interfaces
ipx::remove_all_bus_interface [ipx::current_core]
adi_ip_add_core_dependencies { \
analog.com:user:util_cdc:1.0 \
}
adi_add_bus "spi_engine_ctrl" "master" \
"analog.com:interface:spi_engine_ctrl_rtl:1.0" \
"analog.com:interface:spi_engine_ctrl:1.0" \

10
library/util_axis_fifo/Makefile
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@ -5,8 +5,6 @@
####################################################################################
####################################################################################
M_DEPS += ../common/sync_bits.v
M_DEPS += ../common/sync_gray.v
M_DEPS += ../scripts/adi_env.tcl
M_DEPS += ../scripts/adi_ip.tcl
M_DEPS += address_gray.v
@ -15,6 +13,8 @@ M_DEPS += address_sync.v
M_DEPS += util_axis_fifo.v
M_DEPS += util_axis_fifo_ip.tcl
M_DEPS += ../util_cdc/util_cdc.xpr
M_VIVADO := vivado -mode batch -source
M_FLIST := *.cache
@ -32,8 +32,8 @@ M_FLIST += .Xil
.PHONY: all clean clean-all
all: util_axis_fifo.xpr
.PHONY: all dep clean clean-all
all: dep util_axis_fifo.xpr
clean:clean-all
@ -47,5 +47,7 @@ util_axis_fifo.xpr: $(M_DEPS)
-rm -rf $(M_FLIST)
$(M_VIVADO) util_axis_fifo_ip.tcl >> util_axis_fifo_ip.log 2>&1
dep:
make -C ../util_cdc/
####################################################################################
####################################################################################

6
library/util_axis_fifo/util_axis_fifo_ip.tcl
View File

@ -4,8 +4,6 @@ source $ad_hdl_dir/library/scripts/adi_ip.tcl
adi_ip_create util_axis_fifo
adi_ip_files util_axis_fifo [list \
"$ad_hdl_dir/library/common/sync_bits.v" \
"$ad_hdl_dir/library/common/sync_gray.v" \
"address_gray.v" \
"address_gray_pipelined.v" \
"address_sync.v" \
@ -14,6 +12,10 @@ adi_ip_files util_axis_fifo [list \
adi_ip_properties_lite util_axis_fifo
adi_ip_add_core_dependencies { \
analog.com:user:util_cdc:1.0 \
}
adi_add_bus "s_axis" "slave" \
"xilinx.com:interface:axis_rtl:1.0" \
"xilinx.com:interface:axis:1.0" \

49
library/util_cdc/Makefile Normal file
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@ -0,0 +1,49 @@
####################################################################################
####################################################################################
## Copyright 2011(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################
####################################################################################
M_DEPS += ../scripts/adi_env.tcl
M_DEPS += ../scripts/adi_ip.tcl
M_DEPS += sync_bits.v
M_DEPS += sync_data.v
M_DEPS += sync_event.v
M_DEPS += sync_gray.v
M_DEPS += util_cdc_ip.tcl
M_VIVADO := vivado -mode batch -source
M_FLIST := *.cache
M_FLIST += *.data
M_FLIST += *.xpr
M_FLIST += *.log
M_FLIST += component.xml
M_FLIST += *.jou
M_FLIST += xgui
M_FLIST += *.ip_user_files
M_FLIST += *.srcs
M_FLIST += *.hw
M_FLIST += *.sim
M_FLIST += .Xil
.PHONY: all clean clean-all
all: util_cdc.xpr
clean:clean-all
clean-all:
rm -rf $(M_FLIST)
util_cdc.xpr: $(M_DEPS)
-rm -rf $(M_FLIST)
$(M_VIVADO) util_cdc_ip.tcl >> util_cdc_ip.log 2>&1
####################################################################################
####################################################################################

0
library/common/sync_bits.v → library/util_cdc/sync_bits.v
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0
library/common/sync_gray.v → library/util_cdc/sync_gray.v
View File

42
library/util_cdc/util_cdc_ip.tcl Normal file
View File

@ -0,0 +1,42 @@
# ***************************************************************************
# ***************************************************************************
# Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
#
# Each core or library found in this collection may have its own licensing terms.
# The user should keep this in in mind while exploring these cores.
#
# Redistribution and use in source and binary forms,
# with or without modification of this file, are permitted under the terms of either
# (at the option of the user):
#
# 1. The GNU General Public License version 2 as published by the
# Free Software Foundation, which can be found in the top level directory, or at:
# https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html
#
# OR
#
# 2. An ADI specific BSD license as noted in the top level directory, or on-line at:
# https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
#
# ***************************************************************************
# ***************************************************************************
source ../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip.tcl
adi_ip_create util_cdc
adi_ip_files util_cdc [list \
"sync_gray.v" \
"sync_bits.v" \
"sync_data.v" \
"sync_event.v" \
]
adi_ip_properties_lite util_cdc
set_property name "util_cdc" [ipx::current_core]
set_property display_name "ADI Clock-Domain-Crossing Utils" [ipx::current_core]
set_property description "ADI Clock-Domain-Crossing Utils" [ipx::current_core]
set_property hide_in_gui {1} [ipx::current_core]
ipx::save_core [ipx::current_core]

4
projects/adrv9371x/a10gx/Makefile
View File

@ -69,8 +69,6 @@ M_DEPS += ../../../library/common/ad_iqcor.v
M_DEPS += ../../../library/common/ad_mem.v
M_DEPS += ../../../library/common/ad_rst.v
M_DEPS += ../../../library/common/ad_xcvr_rx_if.v
M_DEPS += ../../../library/common/sync_bits.v
M_DEPS += ../../../library/common/sync_gray.v
M_DEPS += ../../../library/common/up_adc_channel.v
M_DEPS += ../../../library/common/up_adc_common.v
M_DEPS += ../../../library/common/up_axi.v
@ -89,6 +87,8 @@ M_DEPS += ../../../library/util_axis_fifo/address_gray_pipelined.v
M_DEPS += ../../../library/util_axis_fifo/address_sync.v
M_DEPS += ../../../library/util_axis_fifo/util_axis_fifo.v
M_DEPS += ../../../library/util_axis_resize/util_axis_resize.v
M_DEPS += ../../../library/util_cdc/sync_bits.v
M_DEPS += ../../../library/util_cdc/sync_gray.v
M_DEPS += ../../../library/util_cpack/util_cpack.v
M_DEPS += ../../../library/util_cpack/util_cpack_dsf.v
M_DEPS += ../../../library/util_cpack/util_cpack_hw.tcl

4
projects/adrv9371x/a10soc/Makefile
View File

@ -74,8 +74,6 @@ M_DEPS += ../../../library/common/ad_dds_sine.v
M_DEPS += ../../../library/common/ad_iqcor.v
M_DEPS += ../../../library/common/ad_rst.v
M_DEPS += ../../../library/common/ad_xcvr_rx_if.v
M_DEPS += ../../../library/common/sync_bits.v
M_DEPS += ../../../library/common/sync_gray.v
M_DEPS += ../../../library/common/up_adc_channel.v
M_DEPS += ../../../library/common/up_adc_common.v
M_DEPS += ../../../library/common/up_axi.v
@ -95,6 +93,8 @@ M_DEPS += ../../../library/util_axis_fifo/address_gray_pipelined.v
M_DEPS += ../../../library/util_axis_fifo/address_sync.v
M_DEPS += ../../../library/util_axis_fifo/util_axis_fifo.v
M_DEPS += ../../../library/util_axis_resize/util_axis_resize.v
M_DEPS += ../../../library/util_cdc/sync_bits.v
M_DEPS += ../../../library/util_cdc/sync_gray.v
M_DEPS += ../../../library/util_cpack/util_cpack.v
M_DEPS += ../../../library/util_cpack/util_cpack_dsf.v
M_DEPS += ../../../library/util_cpack/util_cpack_hw.tcl

4
projects/arradio/c5soc/Makefile
View File

@ -69,8 +69,6 @@ M_DEPS += ../../../library/common/ad_mem.v
M_DEPS += ../../../library/common/ad_pnmon.v
M_DEPS += ../../../library/common/ad_rst.v
M_DEPS += ../../../library/common/ad_tdd_control.v
M_DEPS += ../../../library/common/sync_bits.v
M_DEPS += ../../../library/common/sync_gray.v
M_DEPS += ../../../library/common/up_adc_channel.v
M_DEPS += ../../../library/common/up_adc_common.v
M_DEPS += ../../../library/common/up_axi.v
@ -88,6 +86,8 @@ M_DEPS += ../../../library/util_axis_fifo/address_gray_pipelined.v
M_DEPS += ../../../library/util_axis_fifo/address_sync.v
M_DEPS += ../../../library/util_axis_fifo/util_axis_fifo.v
M_DEPS += ../../../library/util_axis_resize/util_axis_resize.v
M_DEPS += ../../../library/util_cdc/sync_bits.v
M_DEPS += ../../../library/util_cdc/sync_gray.v
M_DEPS += ../../../library/util_cpack/util_cpack.v
M_DEPS += ../../../library/util_cpack/util_cpack_dsf.v
M_DEPS += ../../../library/util_cpack/util_cpack_hw.tcl

4
projects/daq1/a10gx/Makefile
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@ -64,8 +64,6 @@ M_DEPS += ../../../library/common/ad_dds_1.v
M_DEPS += ../../../library/common/ad_dds_sine.v
M_DEPS += ../../../library/common/ad_pnmon.v
M_DEPS += ../../../library/common/ad_rst.v
M_DEPS += ../../../library/common/sync_bits.v
M_DEPS += ../../../library/common/sync_gray.v
M_DEPS += ../../../library/common/up_adc_channel.v
M_DEPS += ../../../library/common/up_adc_common.v
M_DEPS += ../../../library/common/up_axi.v
@ -85,6 +83,8 @@ M_DEPS += ../../../library/util_axis_fifo/address_gray_pipelined.v
M_DEPS += ../../../library/util_axis_fifo/address_sync.v
M_DEPS += ../../../library/util_axis_fifo/util_axis_fifo.v
M_DEPS += ../../../library/util_axis_resize/util_axis_resize.v
M_DEPS += ../../../library/util_cdc/sync_bits.v
M_DEPS += ../../../library/util_cdc/sync_gray.v
M_DEPS += ../../../library/util_cpack/util_cpack.v
M_DEPS += ../../../library/util_cpack/util_cpack_dsf.v
M_DEPS += ../../../library/util_cpack/util_cpack_hw.tcl

4
projects/daq2/a10gx/Makefile
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@ -69,8 +69,6 @@ M_DEPS += ../../../library/common/ad_dds_sine.v
M_DEPS += ../../../library/common/ad_pnmon.v
M_DEPS += ../../../library/common/ad_rst.v
M_DEPS += ../../../library/common/ad_xcvr_rx_if.v
M_DEPS += ../../../library/common/sync_bits.v
M_DEPS += ../../../library/common/sync_gray.v
M_DEPS += ../../../library/common/up_adc_channel.v
M_DEPS += ../../../library/common/up_adc_common.v
M_DEPS += ../../../library/common/up_axi.v
@ -90,6 +88,8 @@ M_DEPS += ../../../library/util_axis_fifo/address_gray_pipelined.v
M_DEPS += ../../../library/util_axis_fifo/address_sync.v
M_DEPS += ../../../library/util_axis_fifo/util_axis_fifo.v
M_DEPS += ../../../library/util_axis_resize/util_axis_resize.v
M_DEPS += ../../../library/util_cdc/sync_bits.v
M_DEPS += ../../../library/util_cdc/sync_gray.v
M_DEPS += ../../../library/util_cpack/util_cpack.v
M_DEPS += ../../../library/util_cpack/util_cpack_dsf.v
M_DEPS += ../../../library/util_cpack/util_cpack_hw.tcl

4
projects/daq3/a10gx/Makefile
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@ -69,8 +69,6 @@ M_DEPS += ../../../library/common/ad_dds_sine.v
M_DEPS += ../../../library/common/ad_pnmon.v
M_DEPS += ../../../library/common/ad_rst.v
M_DEPS += ../../../library/common/ad_xcvr_rx_if.v
M_DEPS += ../../../library/common/sync_bits.v
M_DEPS += ../../../library/common/sync_gray.v
M_DEPS += ../../../library/common/up_adc_channel.v
M_DEPS += ../../../library/common/up_adc_common.v
M_DEPS += ../../../library/common/up_axi.v
@ -90,6 +88,8 @@ M_DEPS += ../../../library/util_axis_fifo/address_gray_pipelined.v
M_DEPS += ../../../library/util_axis_fifo/address_sync.v
M_DEPS += ../../../library/util_axis_fifo/util_axis_fifo.v
M_DEPS += ../../../library/util_axis_resize/util_axis_resize.v
M_DEPS += ../../../library/util_cdc/sync_bits.v
M_DEPS += ../../../library/util_cdc/sync_gray.v
M_DEPS += ../../../library/util_cpack/util_cpack.v
M_DEPS += ../../../library/util_cpack/util_cpack_dsf.v
M_DEPS += ../../../library/util_cpack/util_cpack_hw.tcl

4
projects/fmcjesdadc1/a5gt/Makefile
View File

@ -57,8 +57,6 @@ M_DEPS += ../../../library/common/ad_datafmt.v
M_DEPS += ../../../library/common/ad_pnmon.v
M_DEPS += ../../../library/common/ad_rst.v
M_DEPS += ../../../library/common/ad_xcvr_rx_if.v
M_DEPS += ../../../library/common/sync_bits.v
M_DEPS += ../../../library/common/sync_gray.v
M_DEPS += ../../../library/common/up_adc_channel.v
M_DEPS += ../../../library/common/up_adc_common.v
M_DEPS += ../../../library/common/up_axi.v
@ -73,6 +71,8 @@ M_DEPS += ../../../library/util_axis_fifo/address_gray_pipelined.v
M_DEPS += ../../../library/util_axis_fifo/address_sync.v
M_DEPS += ../../../library/util_axis_fifo/util_axis_fifo.v
M_DEPS += ../../../library/util_axis_resize/util_axis_resize.v
M_DEPS += ../../../library/util_cdc/sync_bits.v
M_DEPS += ../../../library/util_cdc/sync_gray.v
M_DEPS += ../../../library/util_cpack/util_cpack.v
M_DEPS += ../../../library/util_cpack/util_cpack_dsf.v
M_DEPS += ../../../library/util_cpack/util_cpack_hw.tcl

4
projects/fmcjesdadc1/a5soc/Makefile
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@ -57,8 +57,6 @@ M_DEPS += ../../../library/common/ad_datafmt.v
M_DEPS += ../../../library/common/ad_pnmon.v
M_DEPS += ../../../library/common/ad_rst.v
M_DEPS += ../../../library/common/ad_xcvr_rx_if.v
M_DEPS += ../../../library/common/sync_bits.v
M_DEPS += ../../../library/common/sync_gray.v
M_DEPS += ../../../library/common/up_adc_channel.v
M_DEPS += ../../../library/common/up_adc_common.v
M_DEPS += ../../../library/common/up_axi.v
@ -73,6 +71,8 @@ M_DEPS += ../../../library/util_axis_fifo/address_gray_pipelined.v
M_DEPS += ../../../library/util_axis_fifo/address_sync.v
M_DEPS += ../../../library/util_axis_fifo/util_axis_fifo.v
M_DEPS += ../../../library/util_axis_resize/util_axis_resize.v
M_DEPS += ../../../library/util_cdc/sync_bits.v
M_DEPS += ../../../library/util_cdc/sync_gray.v
M_DEPS += ../../../library/util_cpack/util_cpack.v
M_DEPS += ../../../library/util_cpack/util_cpack_dsf.v
M_DEPS += ../../../library/util_cpack/util_cpack_hw.tcl

4
projects/fmcomms2/a10gx/Makefile
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@ -69,8 +69,6 @@ M_DEPS += ../../../library/common/ad_mem.v
M_DEPS += ../../../library/common/ad_pnmon.v
M_DEPS += ../../../library/common/ad_rst.v
M_DEPS += ../../../library/common/ad_tdd_control.v
M_DEPS += ../../../library/common/sync_bits.v
M_DEPS += ../../../library/common/sync_gray.v
M_DEPS += ../../../library/common/up_adc_channel.v
M_DEPS += ../../../library/common/up_adc_common.v
M_DEPS += ../../../library/common/up_axi.v
@ -88,6 +86,8 @@ M_DEPS += ../../../library/util_axis_fifo/address_gray_pipelined.v
M_DEPS += ../../../library/util_axis_fifo/address_sync.v
M_DEPS += ../../../library/util_axis_fifo/util_axis_fifo.v
M_DEPS += ../../../library/util_axis_resize/util_axis_resize.v
M_DEPS += ../../../library/util_cdc/sync_bits.v
M_DEPS += ../../../library/util_cdc/sync_gray.v
M_DEPS += ../../../library/util_cpack/util_cpack.v
M_DEPS += ../../../library/util_cpack/util_cpack_dsf.v
M_DEPS += ../../../library/util_cpack/util_cpack_hw.tcl

4
projects/usdrx1/a5gt/Makefile
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@ -60,8 +60,6 @@ M_DEPS += ../../../library/common/ad_mem.v
M_DEPS += ../../../library/common/ad_pnmon.v
M_DEPS += ../../../library/common/ad_rst.v
M_DEPS += ../../../library/common/ad_xcvr_rx_if.v
M_DEPS += ../../../library/common/sync_bits.v
M_DEPS += ../../../library/common/sync_gray.v
M_DEPS += ../../../library/common/up_adc_channel.v
M_DEPS += ../../../library/common/up_adc_common.v
M_DEPS += ../../../library/common/up_axi.v
@ -79,6 +77,8 @@ M_DEPS += ../../../library/util_axis_fifo/address_gray_pipelined.v
M_DEPS += ../../../library/util_axis_fifo/address_sync.v
M_DEPS += ../../../library/util_axis_fifo/util_axis_fifo.v
M_DEPS += ../../../library/util_axis_resize/util_axis_resize.v
M_DEPS += ../../../library/util_cdc/sync_bits.v
M_DEPS += ../../../library/util_cdc/sync_gray.v
M_ALTERA := quartus_sh --64bit -t