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motor_control: Changed controller to PID controller. Some estetic changes

main
Adrian Costina 2014-04-28 17:57:51 +03:00
parent fa998a406b
commit 01de117b5f
31 changed files with 4503 additions and 569 deletions
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153
library/axi_mc_torque_ctrl/axi_mc_torque_ctrl.v → library/axi_mc_controller/axi_mc_controller.v
View File

@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2013(c) Analog Devices, Inc.
// Copyright 2014(c) Analog Devices, Inc.
//
// All rights reserved.
//
@ -37,7 +37,7 @@
`timescale 1ns/100ps
module axi_mc_torque_ctrl
module axi_mc_controller
#(
parameter C_S_AXI_MIN_SIZE = 32'hffff,
parameter C_BASEADDR = 32'hffffffff,
@ -58,14 +58,23 @@ module axi_mc_torque_ctrl
output pwm_cl_o,
output [7:0] gpo_o,
// controller connections
input [31:0] err_i,
input [31:0] pwm_i,
input [31:0] speed_rpm_i,
output ctrl_rst_o,
output [31:0] ref_speed_o,
output [31:0] kp_o,
output [31:0] ki_o,
output [31:0] kd_o,
// interconnection with other modules
output [1:0] sensors_o,
input [2:0] position_i,
input new_speed_i,
input [31:0] speed_i,
input [15:0] it_i,
input i_ready_i,
// dma interface
@ -112,11 +121,7 @@ reg adc_valid = 'd0;
reg [31:0] adc_data = 'd0;
reg [31:0] up_rdata = 'd0;
reg up_ack = 'd0;
reg [15:0] tmr_dv_reg = 'd0;
reg datavalid_reg = 'd0;
reg [15:0] tmr_ctrl_reg = 'd0;
reg pwm_gen_clk = 'd0;
reg ctrl_gen_clk = 'd0;
reg one_chan_reg = 'd0;
//------------------------------------------------------------------------------
@ -145,25 +150,14 @@ wire ack_actual_speed_s;
wire run_s;
wire star_delta_s;
wire oloop_matlab_s; // 0 - open loop, 1 matlab controlls pwm
wire dir_s;
wire [10:0] pwm_open_s;
wire [31:0] pwm_controller_s;
wire [10:0] pwm_s;
wire [31:0] err_s;
wire [31:0] pid_s;
wire [2:0] position_s;
wire [31:0] ki_s;
wire [31:0] kp_s;
wire [31:0] ki1_s;
wire [31:0] kp1_s;
wire [31:0] kd1_s;
wire [31:0] reference_speed_s;
wire [31:0] speed_rpm_s; // speed in RPM from the controller
wire enable_ref_speed_s;
wire enable_actual_speed_s;
wire [10:0] gpo_s;
wire [31:0] it_max_s;
//------------------------------------------------------------------------------
//----------- Assign/Always Blocks ---------------------------------------------
@ -171,79 +165,50 @@ wire [31:0] it_max_s;
// signal name changes
assign up_clk = s_axi_aclk;
assign up_rstn = s_axi_aresetn;
assign up_clk = s_axi_aclk;
assign up_rstn = s_axi_aresetn;
assign adc_clk_o = ref_clk;
assign adc_dwr_o = adc_valid;
assign adc_ddata_o = adc_data;
assign adc_clk_o = ref_clk;
assign adc_dwr_o = adc_valid;
assign adc_ddata_o = adc_data;
assign ctrl_rst_o = !run_s;
// monitor signals
assign adc_mon_valid = i_ready_i;
assign adc_mon_data = {25'h0 ,fmc_m1_en_o, pwm_ah_o, pwm_al_o, pwm_bh_o, pwm_bl_o, pwm_ch_o, pwm_cl_o};
assign adc_mon_valid = adc_valid;
assign adc_mon_data = {25'h0 ,fmc_m1_en_o, pwm_ah_o, pwm_al_o, pwm_bh_o, pwm_bl_o, pwm_ch_o, pwm_cl_o};
// multiple instances synchronization
assign pid_s = 32'd0;
assign fmc_m1_en_o = run_s;
assign pwm_s = oloop_matlab_s ? pwm_controller_s[10:0] : pwm_open_s ;
assign position_s = position_i;
assign fmc_m1_en_o = run_s;
assign pwm_s = oloop_matlab_s ? pwm_i[10:0] : pwm_open_s ;
// assign gpo
assign gpo_o[7:4] = gpo_s[10:7];
assign gpo_o[3:0] = gpo_s[3:0];
assign gpo_o[7:4] = gpo_s[10:7];
assign gpo_o[3:0] = gpo_s[3:0];
// clock generation for controller
// clock generation
always @(posedge ref_clk)
begin
pwm_gen_clk <= ~pwm_gen_clk; // generate 50 MHz clk
if(tmr_ctrl_reg == 16'd4) // generate 10 MHz clk
begin
tmr_ctrl_reg <= 16'd0;
ctrl_gen_clk <= ~ctrl_gen_clk;
end
else
begin
tmr_ctrl_reg <= tmr_ctrl_reg + 16'd1;
end
end
// CE generation for controller
always @(posedge ref_clk)
begin
if(tmr_dv_reg == 16'd999)
begin
datavalid_reg <= 1'b1;
tmr_dv_reg <= 16'd0;
end
else
begin
datavalid_reg <= 1'b0;
tmr_dv_reg <= tmr_dv_reg + 16'd1;
end
pwm_gen_clk <= ~pwm_gen_clk; // generate 50 MHz clk
end
// adc channels - dma interface
always @(posedge ref_clk)
begin
if(datavalid_reg == 1)
if(new_speed_i == 1)
begin
case({enable_actual_speed_s , enable_ref_speed_s})
2'b11:
begin
adc_data <= {speed_rpm_s[29:14],reference_speed_s[15:0]};
adc_data <= {speed_rpm_i[31:16], ref_speed_o[15:0]};
adc_valid <= 1'b1;
end
2'b01:
begin
adc_data <= { adc_data[15:0], reference_speed_s[15:0]};
adc_data <= { adc_data[15:0], ref_speed_o[15:0]};
one_chan_reg <= ~one_chan_reg;
if(one_chan_reg == 1'b1)
begin
@ -256,7 +221,7 @@ begin
end
2'b10:
begin
adc_data <= { adc_data[15:0], speed_rpm_s[29:14]};
adc_data <= { adc_data[15:0], speed_rpm_i[31:16]};
one_chan_reg <= ~one_chan_reg;
if(one_chan_reg == 1'b1)
begin
@ -302,9 +267,9 @@ motor_driver_inst(
.pwm_clk_i(pwm_gen_clk),
.rst_n_i(up_rstn) ,
.run_i(run_s),
.star_delta_i(1'b0),
//.dir_i(1'b1),
.position_i(position_s),
.star_delta_i(star_delta_s),
.dir_i(dir_s),
.position_i(position_i),
.pwm_duty_i(pwm_s),
.AH_o(pwm_ah_o),
.BH_o(pwm_bh_o),
@ -323,45 +288,24 @@ control_registers control_reg_inst(
.up_rdata(up_control_rdata_s),
.up_ack(up_control_ack_s),
//control pins
.run_o(run_s),
.break_o(),
.dir_o(dir_s),
.star_delta_o(star_delta_s),
.sensors_o(sensors_o),
.kp_o(kp_s),
.ki_o(ki_s),
.kp1_o(kp1_s),
.ki1_o(ki1_s),
.kd1_o(kd1_s),
.kp_o(kp_o),
.ki_o(ki_o),
.kd_o(kd_o),
.kp1_o(),
.ki1_o(),
.kd1_o(),
.gpo_o(gpo_s),
.reference_speed_o(reference_speed_s),
.reference_speed_o(ref_speed_o),
.oloop_matlab_o(oloop_matlab_s),
.err_i(err_s),
.err_i(err_i),
.calibrate_adcs_o(),
.pwm_open_o( pwm_open_s));
bldc_sim_fpga_cw torque_controller(
.ce(1'b1),
.clk(ctrl_gen_clk),
.clk_x0(ctrl_gen_clk),
.it({16'h0,it_i}),
.kd1(kd1_s),
.ki(ki_s),
.ki1(ki1_s),
.kp(kp_s),
.kp1(kp1_s),
.motor_speed(speed_i),
.new_current(i_ready_i),
.new_speed(new_speed_i),
.ref_speed(reference_speed_s),
.reset(!up_rstn),
.reset_acc(!run_s),
.err(err_s),
.it_max(it_max_s),
.pwm(pwm_controller_s),
.speed(speed_rpm_s));
up_adc_channel #(.PCORE_ADC_CHID(0)) adc_channel_ref_speed(
.adc_clk(ref_clk),
.adc_rst(adc_rst),
@ -380,8 +324,8 @@ up_adc_channel #(.PCORE_ADC_CHID(0)) adc_channel_ref_speed(
.adc_pn_err(1'b0),
.adc_pn_oos(1'b0),
.adc_or(1'b0),
.up_adc_pn_err(1'b0),
.up_adc_pn_oos(1'b0),
.up_adc_pn_err(),
.up_adc_pn_oos(),
.up_adc_or(),
.up_usr_datatype_be(),
.up_usr_datatype_signed(),
@ -406,7 +350,6 @@ up_adc_channel #(.PCORE_ADC_CHID(0)) adc_channel_ref_speed(
.up_rdata(rdata_ref_speed_s),
.up_ack(ack_ref_speed_s));
up_adc_channel #(.PCORE_ADC_CHID(1)) adc_channel_actual_speed(
.adc_clk(ref_clk),
.adc_rst(adc_rst),
@ -451,8 +394,8 @@ up_adc_channel #(.PCORE_ADC_CHID(1)) adc_channel_actual_speed(
.up_rdata(rdata_actual_speed_s),
.up_ack(ack_actual_speed_s));
// common processor control
up_adc_common i_up_adc_common(
.mmcm_rst(),
.adc_clk(ref_clk),

12
library/axi_mc_torque_ctrl/axi_mc_torque_ctrl_ip.tcl → library/axi_mc_controller/axi_mc_controller_ip.tcl
View File

@ -3,9 +3,10 @@
source ../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip.tcl
adi_ip_create axi_mc_torque_ctrl
adi_ip_files axi_mc_torque_ctrl [list \
adi_ip_create axi_mc_controller
adi_ip_files axi_mc_controller [list \
"$ad_hdl_dir/library/common/up_axi.v" \
"$ad_hdl_dir/library/common/ad_rst.v" \
"$ad_hdl_dir/library/common/up_delay_cntrl.v" \
"$ad_hdl_dir/library/common/up_drp_cntrl.v" \
"$ad_hdl_dir/library/common/up_xfer_cntrl.v" \
@ -15,14 +16,11 @@ adi_ip_files axi_mc_torque_ctrl [list \
"$ad_hdl_dir/library/common/up_delay_cntrl.v" \
"$ad_hdl_dir/library/common/up_adc_common.v" \
"$ad_hdl_dir/library/common/up_adc_channel.v" \
"bldc_sim_fpga_cw.ngc" \
"bldc_sim_fpga_cw.xdc" \
"motor_driver.v" \
"control_registers.v" \
"bldc_sim_fpga_cw_bb.v" \
"axi_mc_torque_ctrl.v" ]
"axi_mc_controller.v" ]
adi_ip_properties axi_mc_torque_ctrl
adi_ip_properties axi_mc_controller
ipx::save_core [ipx::current_core]

31
library/axi_mc_torque_ctrl/control_registers.v → library/axi_mc_controller/control_registers.v
View File

@ -56,11 +56,13 @@ module control_registers
output [31:0] reference_speed_o,
output [31:0] kp_o,
output [31:0] ki_o,
output [31:0] kd_o,
output [31:0] kp1_o,
output [31:0] ki1_o,
output [31:0] kd1_o,
output run_o,
output break_o,
output dir_o,
output star_delta_o,
output [1:0] sensors_o,
output [10:0] gpo_o,
@ -71,6 +73,7 @@ module control_registers
//------------------------------------------------------------------------------
//----------- Registers Declarations -------------------------------------------
//------------------------------------------------------------------------------
//internal registers
reg [31:0] control_r;
@ -84,12 +87,13 @@ reg [31:0] pwm_open_r;
reg [31:0] pwm_break_r;
reg [31:0] status_r;
reg [31:0] reserved_r1;
reg [31:0] reserved_r2;
reg [31:0] kd_r;
reg [10:0] gpo_r;
//------------------------------------------------------------------------------
//----------- Wires Declarations -----------------------------------------------
//------------------------------------------------------------------------------
//internal signals
wire up_sel_s;
@ -98,28 +102,28 @@ wire up_wr_s;
//------------------------------------------------------------------------------
//----------- Assign/Always Blocks ---------------------------------------------
//------------------------------------------------------------------------------
//decode block select
assign up_sel_s = (up_addr[13:4] == 10'h00) ? up_sel : 1'b0;
assign up_wr_s = up_sel_s & up_wr;
assign run_o = control_r[0]; // Run the motor
assign break_o = control_r[2]; // Activate the Break circuit
assign dir_o = control_r[3]; // 0 CCW, 1 CW
assign star_delta_o = control_r[4]; // Select between star [0] or delta [1] controller
assign sensors_o = control_r[9:8]; // Select between Hall[00] and BEMF[01] sensors
assign calibrate_adcs_o = control_r[16];
assign oloop_matlab_o = control_r[12]; // Select between open loop control [0] and matlab control [1]
assign oloop_matlab_o = control_r[12]; // Select between open loop control [0] and matlab control [1]
assign gpo_o = control_r[30:20];
assign pwm_open_o = pwm_open_r; // PWM value, for open loop control
assign reference_speed_o = reference_speed_r;
assign kp_o = kp_r;
assign ki_o = ki_r;
assign kp_o = kp_r; // KP controller parameter
assign ki_o = ki_r; // KI controller parameter
assign kd_o = kd_r; // KD controller parameter
assign kp1_o = kp1_r;
assign kd1_o = kd1_r;
assign ki1_o = ki1_r;
// processor write interface
always @(negedge up_rstn or posedge up_clk)
@ -128,11 +132,12 @@ begin
begin
control_r <= 'h0;
reference_speed_r <= 'd1000;
kp_r <= 'd35000;
ki_r <= 'd30;
kp1_r <= 'd400000;
ki1_r <= 'd250;
kd1_r <= 'd200000;
kp_r <= 'd6554;
ki_r <= 'd26;
kd_r <= 'd655360;
kp1_r <= 'd0;
ki1_r <= 'd0;
kd1_r <= 'd0;
pwm_open_r <= 'h5ff;
pwm_break_r <= 'd0;
status_r <= 'd0;
@ -161,7 +166,7 @@ begin
end
if ((up_wr_s == 1'b1) && (up_addr[3:0] == 4'h8))
begin
reserved_r2 <= up_wdata;
kd_r <= up_wdata;
end
if ((up_wr_s == 1'b1) && (up_addr[3:0] == 4'h9))
begin
@ -208,7 +213,7 @@ begin
4'h5: up_rdata <= reference_speed_r;
4'h6: up_rdata <= kp_r;
4'h7: up_rdata <= ki_r;
4'h8: up_rdata <= reserved_r2;
4'h8: up_rdata <= kd_r;
4'h9: up_rdata <= kp1_r;
4'ha: up_rdata <= ki1_r;
4'hb: up_rdata <= kd1_r;

205
library/axi_mc_controller/motor_driver.v Executable file
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@ -0,0 +1,205 @@
// -----------------------------------------------------------------------------
//
// Copyright 2014(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED
// WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
// INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// -----------------------------------------------------------------------------
// FILE NAME : motor_driver.v
// MODULE NAME :motor_driver
// AUTHOR : acozma
// AUTHOR'S EMAIL : andrei.cozma@analog.com
//
// -----------------------------------------------------------------------------
`timescale 1ns / 1ps
//------------------------------------------------------------------------------
//----------- Module Declaration -----------------------------------------------
//------------------------------------------------------------------------------
module motor_driver
//----------- Parameters Declarations -------------------------------------------
#(
parameter PWM_BITS = 11,
localparam PWMBW = PWM_BITS - 1
)
//----------- Ports Declarations -----------------------------------------------
(
input clk_i,
input pwm_clk_i,
input rst_n_i,
input run_i,
input star_delta_i, // 1 STAR, 0 DELTA
input dir_i, // 1 CW, 0 CCW
input [2:0] position_i,
input [PWMBW:0] pwm_duty_i,
output AH_o,
output BH_o,
output CH_o,
output AL_o,
output BL_o,
output CL_o
);
//------------------------------------------------------------------------------
//----------- Registers Declarations -------------------------------------------
//------------------------------------------------------------------------------
reg pwm_s;
reg [ 3:0] motor_state;
reg [15:0] align_counter;
reg [ 2:0] position_s;
reg [PWMBW:0] pwm_cnt;
//------------------------------------------------------------------------------
//----------- Wires Declarations -----------------------------------------------
//------------------------------------------------------------------------------
wire align_complete;
wire [PWMBW:0] pwm_duty_s;
wire [1:0] commutation_table[0:2];
//------------------------------------------------------------------------------
//----------- Local Parameters -------------------------------------------------
//------------------------------------------------------------------------------
localparam OFF = 3'b001;
localparam ALIGN = 3'b010;
localparam RUN = 3'b100;
localparam [PWMBW:0] ALIGN_PWM_DUTY = 2**(PWMBW) + 2**(PWMBW-3);
localparam [15:0] ALIGN_TIME = 16'h4000;
localparam [1:0] COMMUTATION_TABLE_DELTA_CW_0[0:5] = { 2'd1,-2'd1, 2'd1,-2'd1, 2'd1,-2'd1};
localparam [1:0] COMMUTATION_TABLE_DELTA_CW_1[0:5] = {-2'd1, 2'd1, 2'd1,-2'd1,-2'd1, 2'd1};
localparam [1:0] COMMUTATION_TABLE_DELTA_CW_2[0:5] = {-2'd1,-2'd1,-2'd1, 2'd1, 2'd1, 2'd1};
localparam [1:0] COMMUTATION_TABLE_DELTA_CCW_0[0:5] = {-2'd1, 2'd1,-2'd1, 2'd1,-2'd1, 2'd1};
localparam [1:0] COMMUTATION_TABLE_DELTA_CCW_1[0:5] = { 2'd1,-2'd1,-2'd1, 2'd1, 2'd1,-2'd1};
localparam [1:0] COMMUTATION_TABLE_DELTA_CCW_2[0:5] = { 2'd1, 2'd1, 2'd1,-2'd1,-2'd1,-2'd1};
localparam [1:0] COMMUTATION_TABLE_STAR_CW_0[0:5] = { 2'd1,-2'd1, 2'd0, 2'd0, 2'd1,-2'd1};
localparam [1:0] COMMUTATION_TABLE_STAR_CW_1[0:5] = { 2'd0, 2'd1, 2'd1,-2'd1,-2'd1, 2'd0};
localparam [1:0] COMMUTATION_TABLE_STAR_CW_2[0:5] = {-2'd1, 2'd0,-2'd1, 2'd1, 2'd0, 2'd1};
localparam [1:0] COMMUTATION_TABLE_STAR_CCW_0[0:5] = {-2'd1, 2'd1, 2'd0, 2'd0, -2'd1, 2'd1};
localparam [1:0] COMMUTATION_TABLE_STAR_CCW_1[0:5] = { 2'd0,-2'd1,-2'd1, 2'd1, 2'd1, 2'd0};
localparam [1:0] COMMUTATION_TABLE_STAR_CCW_2[0:5] = { 2'd1, 2'd0, 2'd1,-2'd1, 2'd0,-2'd1};
//------------------------------------------------------------------------------
//----------- Assign/Always Blocks ---------------------------------------------
//------------------------------------------------------------------------------
assign align_complete = align_counter < ALIGN_TIME ? 0 : 1;
assign pwm_duty_s = motor_state == OFF ? 0 :
motor_state == ALIGN ? ALIGN_PWM_DUTY : pwm_duty_i;
assign commutation_table[0] = star_delta_i ?
dir_i ? COMMUTATION_TABLE_STAR_CW_0[position_s] : COMMUTATION_TABLE_STAR_CCW_0[position_s] :
dir_i ? COMMUTATION_TABLE_DELTA_CW_0[position_s] : COMMUTATION_TABLE_DELTA_CCW_0[position_s];
assign commutation_table[1] = star_delta_i ?
dir_i ? COMMUTATION_TABLE_STAR_CW_1[position_s] : COMMUTATION_TABLE_STAR_CCW_1[position_s] :
dir_i ? COMMUTATION_TABLE_DELTA_CW_1[position_s] : COMMUTATION_TABLE_DELTA_CCW_1[position_s];
assign commutation_table[2] = star_delta_i ?
dir_i ? COMMUTATION_TABLE_STAR_CW_2[position_s] : COMMUTATION_TABLE_STAR_CCW_2[position_s] :
dir_i ? COMMUTATION_TABLE_DELTA_CW_2[position_s] : COMMUTATION_TABLE_DELTA_CCW_2[position_s];
//Motor Phases Control
assign AH_o = commutation_table[0] == 2'd1 ? ~pwm_s : commutation_table[0] == -2'd1 ? pwm_s : 1;
assign AL_o = commutation_table[0] == 2'd1 ? pwm_s : commutation_table[0] == -2'd1 ? ~pwm_s : 1;
assign BH_o = commutation_table[1] == 2'd1 ? ~pwm_s : commutation_table[1] == -2'd1 ? pwm_s : 1;
assign BL_o = commutation_table[1] == 2'd1 ? pwm_s : commutation_table[1] == -2'd1 ? ~pwm_s : 1;
assign CH_o = commutation_table[2] == 2'd1 ? ~pwm_s : commutation_table[2] == -2'd1 ? pwm_s : 1;
assign CL_o = commutation_table[2] == 2'd1 ? pwm_s : commutation_table[2] == -2'd1 ? ~pwm_s : 1;
//Control the current motor state
always @(posedge clk_i)
begin
if(rst_n_i == 1'b0)
begin
motor_state <= OFF;
align_counter <= 0;
end
else
begin
case(motor_state)
OFF:
begin
position_s <= 0;
motor_state <= (run_i == 1'b1 ? ALIGN : OFF);
end
ALIGN:
begin
position_s <= 0;
if(align_complete == 1'b1)
begin
motor_state <= (run_i == 1'b1 ? RUN : OFF);
end
else
begin
motor_state <= (run_i == 1'b1 ? ALIGN : OFF);
end
end
RUN:
begin
position_s <= position_i - 1;
motor_state <= (run_i == 1'b1 ? RUN : OFF);
end
default:
begin
motor_state <= OFF;
end
endcase
align_counter <= motor_state == ALIGN ? align_counter + 1 : 0;
end
end
//Generate the PWM signal
always @(posedge pwm_clk_i)
begin
if((rst_n_i == 1'b0))
begin
pwm_cnt <= 0;
end
else
begin
pwm_cnt <= pwm_cnt < (2**PWM_BITS - 1) ? pwm_cnt + 1 : 0;
end
pwm_s <= pwm_cnt < pwm_duty_s ? 1 : 0;
end
endmodule

4
library/axi_mc_current_monitor/ad7401.v
View File

@ -116,7 +116,7 @@ localparam WAIT_DATA_RDY_LOW_STATE = 5'b10000;
assign adc_mclkin_o = adc_clk_i; // use clock signal for driver and for ADC
// synchronize data on fpga_clki
always @(posedge fpga_clk_i )
always @(posedge fpga_clk_i)
begin
data_rdy_s_d1 <= data_rdy_s;
data_rdy_s_d2 <= data_rdy_s_d1;
@ -160,7 +160,7 @@ begin
end
end
always @(present_state, data_rdy_s_d2 )
always @(present_state, data_rdy_s_d2)
begin
next_state <= present_state;
case (present_state)

19
library/axi_mc_current_monitor/axi_mc_current_monitor.v
View File

@ -39,7 +39,6 @@
module axi_mc_current_monitor
#(
parameter C_S_AXI_MIN_SIZE = 32'hffff,
parameter C_BASEADDR = 32'hffffffff,
parameter C_HIGHADDR = 32'h00000000
@ -169,6 +168,8 @@ wire adc_enable_ib;
wire adc_enable_it;
wire adc_enable_vbus;
wire adc_clk_s;
//------------------------------------------------------------------------------
//----------- Assign/Always Blocks ---------------------------------------------
//------------------------------------------------------------------------------
@ -182,6 +183,7 @@ assign adc_clk_o = ref_clk; // use reference clock to send data to th
assign adc_dwr_o = adc_valid;
assign adc_ddata_o = adc_data;
assign adc_dsync_o = adc_dsync_r;
// monitor signals
assign adc_mon_valid = data_rd_ready_ia_s;
@ -190,13 +192,14 @@ assign adc_mon_data[31:16] = {adc_enable_vbus, adc_enable_it, adc_enable_ib, ad
// current outputs
assign i_ready_o = data_rd_ready_ia_s;
assign ia_o = adc_data_ia_s;
assign ib_o = adc_data_ib_s;
assign it_o = adc_data_it_n_s;
assign adc_data_it_n_s = 65535 - adc_data_it_s;
assign i_ready_o = data_rd_ready_ia_s;
assign ia_o = adc_data_ia_s;
assign ib_o = adc_data_ib_s;
assign it_o = adc_data_it_n_s;
assign adc_data_it_n_s = 65535 - adc_data_it_s;
// adc clock
assign adc_clk_s = adc_clk_reg;
// ADC clock generation
@ -551,8 +554,8 @@ up_adc_channel #(.PCORE_ADC_CHID(0)) i_up_adc_channel_ia(
.adc_pn_err(1'b0),
.adc_pn_oos(1'b0),
.adc_or(1'b0),
.up_adc_pn_err(1'b0),
.up_adc_pn_oos(1'b0),
.up_adc_pn_err(),
.up_adc_pn_oos(),
.up_adc_or(),
.up_usr_datatype_be(),
.up_usr_datatype_signed(),

2
library/axi_mc_current_monitor/dec256sinc24b.v
View File

@ -92,7 +92,7 @@ reg word_clk;
assign data_rdy_o = word_clk;
/* Perform the Sinc ACTION*/
/* Perform the Sinc ACTION */
always @(mdata_i)
begin
if(mdata_i == 0)

10
library/axi_mc_speed/axi_mc_speed.v
View File

@ -42,7 +42,7 @@ module axi_mc_speed
parameter C_S_AXI_MIN_SIZE = 32'hffff,
parameter C_BASEADDR = 32'hffffffff,
parameter C_HIGHADDR = 32'h00000000,
parameter MOTOR_CONTROL_REVISION = 1
parameter MOTOR_CONTROL_REVISION = 2
)
//----------- Ports Declarations -----------------------------------------------
(
@ -155,8 +155,8 @@ assign speed_o = speed_data_s;
always @(posedge ref_clk)
begin
adc_data <= speed_data_s;
adc_valid <= new_speed_s;
adc_data <= speed_data_s;
adc_valid <= new_speed_s;
end
// processor read interface
@ -233,9 +233,9 @@ delay_30_degrees delay_30_degrees_i1(
.position_o(bemf_delayed_s));
speed_detector
#( .AVERAGE_WINDOW(1024),
#( .AVERAGE_WINDOW(1024),
.LOG_2_AW(10),
.SAMPLE_CLK_DECIM(10000))
.SAMPLE_CLK_DECIM(1000))
speed_detector_inst(
.clk_i(ref_clk),
.rst_i(adc_rst),

2
library/axi_mc_speed/delay_30_degrees.v
View File

@ -72,7 +72,7 @@ module delay_30_degrees
//------------------------------------------------------------------------------
//----------- Local Parameters -------------------------------------------------
//------------------------------------------------------------------------------
localparam MAX_SPEED_COUNT= 32'h1000000;
localparam MAX_SPEED_COUNT = 32'h1000000;
//State machine
localparam RESET = 6'b000001;
localparam INIT = 6'b000010;

14
library/axi_mc_speed/speed_detector.v
View File

@ -78,9 +78,9 @@ module speed_detector
//----------- Local Parameters -------------------------------------------------
//------------------------------------------------------------------------------
localparam AW = LOG_2_AW - 1;
localparam AW = LOG_2_AW - 1;
localparam MAX_SPEED_CNT= 32'h10000;
localparam MAX_SPEED_CNT = 32'h10000;
//State machine
localparam RESET = 8'b00000001;
@ -95,7 +95,7 @@ localparam IDLE = 8'b10000000;
//----------- Registers Declarations -------------------------------------------
//------------------------------------------------------------------------------
reg [2:0] position_old;
reg [ 2:0] position_old;
reg [63:0] avg_register;
reg [63:0] avg_register_stable;
reg [31:0] cnt_period;
@ -107,8 +107,8 @@ reg [AW:0] read_addr;
reg [31:0] sample_clk_div;
reg [7:0] state;
reg [7:0] next_state;
reg [ 7:0] state;
reg [ 7:0] next_state;
//------------------------------------------------------------------------------
//----------- Assign/Always Blocks ---------------------------------------------
@ -244,7 +244,7 @@ begin
end
else
begin
if(sample_clk_div == SAMPLE_CLK_DECIM )
if(sample_clk_div == SAMPLE_CLK_DECIM)
begin
sample_clk_div <= 0;
speed_o <=(avg_register_stable >> LOG_2_AW);
@ -253,8 +253,8 @@ begin
end
else
begin
sample_clk_div <= sample_clk_div + 1;
new_speed_o <= 0;
sample_clk_div <= sample_clk_div + 1;
end
end
end

3
library/axi_mc_torque_ctrl/bldc_sim_fpga_cw.ngc
View File

File diff suppressed because one or more lines are too long

4
library/axi_mc_torque_ctrl/bldc_sim_fpga_cw.xdc
View File

@ -1,4 +0,0 @@
# Global period constraint
create_clock -name clk -period 100.0 [get_ports clk]

53
library/axi_mc_torque_ctrl/bldc_sim_fpga_cw_bb.v
View File

@ -1,53 +0,0 @@
// Declare the module black box
module bldc_sim_fpga_cw (
ce ,
clk ,
clk_x0 ,
it ,
kd1 ,
ki ,
ki1 ,
kp ,
kp1 ,
motor_speed ,
new_current ,
new_speed ,
ref_speed ,
reset ,
reset_acc ,
err ,
it_max ,
pwm ,
speed
); // synthesis black_box
// Inputs
input ce;
input clk;
input clk_x0;
input [31:0] it;
input [31:0] kd1;
input [31:0] ki;
input [31:0] ki1;
input [31:0] kp;
input [31:0] kp1;
input [31:0] motor_speed;
input new_current;
input new_speed;
input [31:0] ref_speed;
input reset;
input reset_acc;
// Outputs
output [31:0] err;
output [31:0] it_max;
output [31:0] pwm;
output [31:0] speed;
//synthesis attribute box_type bldc_sim_fpga_cw "black_box"
endmodule

272
library/axi_mc_torque_ctrl/motor_driver.v
View File

@ -1,272 +0,0 @@
// -----------------------------------------------------------------------------
//
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED
// WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
// INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// -----------------------------------------------------------------------------
// FILE NAME : motor_driver.v
// MODULE NAME :motor_driver
// AUTHOR : acozma
// AUTHOR'S EMAIL : andrei.cozma@analog.com
// -----------------------------------------------------------------------------
// SVN REVISION: $WCREV$
// -----------------------------------------------------------------------------
// KEYWORDS :
// -----------------------------------------------------------------------------
// PURPOSE : Module for driving a BLDC motor
// -----------------------------------------------------------------------------
// REUSE ISSUES
// Reset Strategy : Active low reset signal
// Clock Domains :
// Critical Timing : N/A
// Test Features : N/A
// Asynchronous I/F : N/A
// Instantiations : N/A
// Synthesizable (y/n) : Y
// Target Device :
// Other :
// -----------------------------------------------------------------------------
// -----------------------------------------------------------------------------
`timescale 1ns / 1ps
//------------------------------------------------------------------------------
//----------- Module Declaration -----------------------------------------------
//------------------------------------------------------------------------------
module motor_driver
//----------- Paramters Declarations -------------------------------------------
#(
parameter PWM_BITS = 11
)
//----------- Ports Declarations -----------------------------------------------
(
input clk_i,
input pwm_clk_i,
input rst_n_i,
input run_i,
input star_delta_i, // 0 star configuration, 1 delta configuration
input [2:0] position_i,
input [PWM_BITS-1:0] pwm_duty_i,
output AH_o,
output BH_o,
output CH_o,
output AL_o,
output BL_o,
output CL_o
);
//------------------------------------------------------------------------------
//----------- Registers Declarations -------------------------------------------
//------------------------------------------------------------------------------
reg [ 7:0] motor_state;
reg [ 7:0] motor_next_state;
reg [31:0] align_counter;
reg pwm_s;
reg [PWM_BITS-1:0] pwm_cnt;
reg [32:0] stall_counter;
//------------------------------------------------------------------------------
//----------- Wires Declarations -----------------------------------------------
//------------------------------------------------------------------------------
wire align_complete;
wire [PWM_BITS-1:0] pwm_duty_s;
//------------------------------------------------------------------------------
//----------- Local Parameters -------------------------------------------------
//------------------------------------------------------------------------------
parameter OFF = 8'b00000001;
parameter ALIGN = 8'b00000010;
parameter PHASE1 = 8'b00000100;
parameter PHASE2 = 8'b00001000;
parameter PHASE3 = 8'b00010000;
parameter PHASE4 = 8'b00100000;
parameter PHASE5 = 8'b01000000;
parameter PHASE6 = 8'b10000000;
parameter [PWM_BITS-1:0] ALIGN_PWM_DUTY = 2**(PWM_BITS-1) + 2**(PWM_BITS-4);
parameter [31:0] ALIGN_TIME = 32'h01000000;
//------------------------------------------------------------------------------
//----------- Assign/Always Blocks ---------------------------------------------
//------------------------------------------------------------------------------
assign align_complete = align_counter < ALIGN_TIME ? 0 : 1;
assign pwm_duty_s = motor_state == OFF ? 0 :
motor_state == ALIGN ? ALIGN_PWM_DUTY : pwm_duty_i;
//Motor Phases Control
// assign AH_o = star_delta_i ? ( (motor_state == ALIGN || motor_state == PHASE1 || motor_state == PHASE2 || motor_state == PHASE3) ? pwm_s : ~pwm_s ) :
// ( (motor_state == ALIGN || motor_state == PHASE1 || motor_state == PHASE6) ? ~pwm_s : (motor_state == PHASE3 || motor_state == PHASE4) ? pwm_s : 0) ;
// assign AL_o = star_delta_i ? ( (motor_state == ALIGN || motor_state == PHASE1 || motor_state == PHASE2 || motor_state == PHASE3) ? ~pwm_s : pwm_s ) :
// ( (motor_state == ALIGN || motor_state == PHASE1 || motor_state == PHASE6) ? pwm_s : (motor_state == PHASE3 || motor_state == PHASE4) ? ~pwm_s : 0) ;
// assign BH_o = star_delta_i ? ( (motor_state == PHASE3 || motor_state == PHASE4 || motor_state == PHASE5 ) ? pwm_s : ~pwm_s ) :
// ( (motor_state == PHASE2 || motor_state == PHASE3) ? ~pwm_s : (motor_state == PHASE5 || motor_state == PHASE6) ? pwm_s : 0 );
// assign BL_o = star_delta_i ? ( (motor_state == PHASE3 || motor_state == PHASE4 || motor_state == PHASE5 ) ? ~pwm_s : pwm_s ) :
// ( (motor_state == PHASE2 || motor_state == PHASE3) ? pwm_s : (motor_state == PHASE5 || motor_state == PHASE6) ? ~pwm_s : 0 );
// assign CH_o = star_delta_i ? ( (motor_state == ALIGN || motor_state == PHASE1 || motor_state == PHASE5 || motor_state == PHASE6) ? pwm_s : ~pwm_s ) :
// ( (motor_state == PHASE4 || motor_state == PHASE5) ? ~pwm_s : (motor_state == ALIGN || motor_state == PHASE1 || motor_state == PHASE2) ? pwm_s : 0 );
// assign CL_o = star_delta_i ? ( (motor_state == ALIGN || motor_state == PHASE1 || motor_state == PHASE5 || motor_state == PHASE6) ? ~pwm_s : pwm_s ) :
// ( (motor_state == PHASE4 || motor_state == PHASE5) ? pwm_s : (motor_state == ALIGN || motor_state == PHASE1 || motor_state == PHASE2) ? ~pwm_s : 0 );
assign AH_o = ( (motor_state == PHASE3 || motor_state == PHASE4 || motor_state == PHASE5 ) ? ~pwm_s : 1 );
assign AL_o = ( (motor_state == PHASE3 || motor_state == PHASE4 || motor_state == PHASE5 ) ? pwm_s : ~pwm_s );
assign BH_o = ( (motor_state == ALIGN || motor_state == PHASE1 || motor_state == PHASE5 || motor_state == PHASE6) ? ~pwm_s : 1 );
assign BL_o = ( (motor_state == ALIGN || motor_state == PHASE1 || motor_state == PHASE5 || motor_state == PHASE6) ? pwm_s : ~pwm_s );
assign CH_o = ( (motor_state == ALIGN || motor_state == PHASE1 || motor_state == PHASE2 || motor_state == PHASE3) ? ~pwm_s : 1 );
assign CL_o = ( (motor_state == ALIGN || motor_state == PHASE1 || motor_state == PHASE2 || motor_state == PHASE3) ? pwm_s : ~pwm_s );
//Control the current motor state
always @(posedge clk_i)
begin
if(rst_n_i == 1'b0)
begin
motor_state <= OFF;
align_counter <= 0;
end
else
begin
motor_state <= (run_i == 1'b1 ? motor_next_state : OFF);
align_counter <= motor_state == ALIGN ? align_counter + 1 : 0;
end
end
//Determine the next motor state
always @(motor_state, position_i, align_complete,run_i, stall_counter)
begin
motor_next_state <= motor_state;
case(motor_state)
OFF:
begin
if(run_i == 1'b1)
begin
motor_next_state <= ALIGN;
end
end
ALIGN:
begin
if(align_complete == 1'b1)
begin
motor_next_state <= PHASE2;
end
end
PHASE1:
begin
if(position_i == 3'b010 || stall_counter == 0 )
begin
motor_next_state <= PHASE2;
end
end
PHASE2:
begin
if(position_i == 3'b110 || stall_counter == 0)
begin
motor_next_state <= PHASE3;
end
end
PHASE3:
begin
if(position_i == 3'b100 || stall_counter == 0 )
begin
motor_next_state <= PHASE4;
end
end
PHASE4:
begin
if(position_i == 3'b101 || stall_counter == 0 )
begin
motor_next_state <= PHASE5;
end
end
PHASE5:
begin
if(position_i == 3'b001 || stall_counter == 0 )
begin
motor_next_state <= PHASE6;
end
end
PHASE6:
begin
if(position_i == 3'b011 || stall_counter == 0 )
begin
motor_next_state <= PHASE1;
end
end
default:
begin
motor_next_state <= OFF;
end
endcase
end
always @(posedge clk_i)
begin
if (rst_n_i == 1'b0)
begin
stall_counter <= 32'd5000000;
end
else
begin
if (motor_next_state == motor_state && motor_state != OFF && motor_state != ALIGN)
begin
if(stall_counter > 0)
begin
stall_counter <= stall_counter - 1;
end
end
else
begin
stall_counter <= 32'd5000000;
end
end
end
//Generate the PWM signal
always @(posedge pwm_clk_i)
begin
if((rst_n_i == 1'b0))
begin
pwm_cnt <= 0;
end
else
begin
pwm_cnt <= pwm_cnt < (2**PWM_BITS - 1) ? pwm_cnt + 1 : 0;
end
pwm_s <= pwm_cnt < pwm_duty_s ? 1 : 0;
end
endmodule

626
library/ip_pid_controller/component.xml Executable file
View File

@ -0,0 +1,626 @@
<?xml version="1.0" encoding="UTF-8"?>
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<spirit:vendor>analog.com</spirit:vendor>
<spirit:library>user</spirit:library>
<spirit:name>ip_pid_controller</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:busInterfaces>
<spirit:busInterface>
<spirit:name>clk</spirit:name>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
<spirit:slave/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>CLK</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>clk</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>rst</spirit:name>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="data" spirit:version="1.0"/>
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4
library/ip_pid_controller/constrs/ip_pid_controller.xdc Executable file
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@ -0,0 +1,4 @@
#######################################################################
# This file is automatically generated from System Generator for DSP #
# design. Consult the documentation before making any modifications #
#######################################################################

57
library/ip_pid_controller/hdl/conv_pkg.v Executable file
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@ -0,0 +1,57 @@
// HIERARCHY
// ENDHIERARCHY
`ifndef xlConvPkgIncluded
`define xlConvPkgIncluded 1
`endif
// synopsys translate_off
`ifndef simulating
`define simulating 1
`endif
// synopsys translate_on
`ifndef simulating
`define simulating 0
`endif
`ifndef xlUnsigned
`define xlUnsigned 1
`endif
`ifndef xlSigned
`define xlSigned 2
`endif
`ifndef xlFloat
`define xlFloat 3
`endif
`ifndef xlWrap
`define xlWrap 1
`endif
`ifndef xlSaturate
`define xlSaturate 2
`endif
`ifndef xlTruncate
`define xlTruncate 1
`endif
`ifndef xlRound
`define xlRound 2
`endif
`ifndef xlRoundBanker
`define xlRoundBanker 3
`endif
`ifndef xlAddMode
`define xlAddMode 1
`endif
`ifndef xlSubMode
`define xlSubMode 2
`endif

854
library/ip_pid_controller/hdl/convert_type.v Executable file
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@ -0,0 +1,854 @@
// HIERARCHY
// ENDHIERARCHY
`ifndef xlConvertType
`define xlConvertType
`timescale 1 ns / 10 ps
`ifndef xlConvPkgIncluded
`include "conv_pkg.v"
`endif
// Cast type by zero pading or Sign extending MSB and
// zero pading or truncating LSB
module cast (inp, res);
parameter signed [31:0] old_width = 4;
parameter signed [31:0] old_bin_pt = 1;
parameter signed [31:0] new_width = 4;
parameter signed [31:0] new_bin_pt = 1;
parameter signed [31:0] new_arith = `xlSigned;
input [old_width - 1 : 0] inp;
output [new_width - 1 : 0] res;
// Number of digits to add/subract to the right of the decimal point
parameter signed [31:0] right_of_dp = new_bin_pt - old_bin_pt; // Not required since new_bin_pt is always equal to old_bin_pt
wire [new_width-1:0] result;
genvar i;
assign res = result;
generate
for (i = 0; i<new_width; i = i+1)
begin:cast_loop
if ((i-right_of_dp) > old_width - 1) // Bits to the left of the decimal point
begin:u0
if (new_arith == `xlUnsigned)
begin:u1
assign result[i] = 1'b0; // If unsigned, zero pad MSB
end
if (new_arith == `xlSigned)
begin:u2
assign result[i] = inp[old_width-1]; // If signed, sign extend MSB
end
end
else if ((i-right_of_dp) >= 0)
begin:u3
assign result[i] = inp[i-right_of_dp]; // Copy bits from input
end
else
begin:u4
assign result[i] = 1'b0; // zero pad LSB
end
end // for (i =0; i < new_width; i = i+1)
endgenerate
endmodule // cast
module shift_division_result (quotient, fraction, res);
parameter signed [31:0] q_width = 16;
parameter signed [31:0] f_width = 16;
parameter signed [31:0] fraction_width = 8;
parameter signed [31:0] shift_value = 8;
parameter signed [31:0] shift_dir = 0;
parameter signed [31:0] vec_MSB = q_width + f_width - 1;
parameter signed [31:0] result_MSB = q_width + fraction_width - 1;
parameter signed [31:0] result_LSB = vec_MSB - result_MSB;
input [q_width - 1 : 0] quotient;
input [f_width - 1 : 0] fraction;
output [result_MSB : 0] res;
wire [vec_MSB:0] vec;
wire [vec_MSB:0] temp;
genvar i;
assign res = vec[vec_MSB:result_LSB];
assign temp = { quotient, fraction };
generate
if (shift_dir == 1)
begin:left_shift_loop
for (i = vec_MSB; i>=0; i = i-1)
begin:u0
if (i < shift_value)
begin:u1
assign vec[i] = 1'b0;
end
else
begin:u2
assign vec[i] = temp[i-shift_value];
end
end
end
else
begin:right_shift_loop
for (i = 0; i <= vec_MSB; i = i+1)
begin:u3
if (i > vec_MSB - shift_value)
begin:u4
assign vec[i] = temp[vec_MSB];
end
else
begin:u5
assign vec[i] = temp[i+shift_value];
end
end
end
endgenerate
endmodule // shift_division_result
module shift_op (inp, res);
parameter signed [31:0] inp_width = 16;
parameter signed [31:0] result_width = 16;
parameter signed [31:0] shift_value = 8;
parameter signed [31:0] shift_dir = 0;
parameter signed [31:0] vec_MSB = inp_width - 1;
parameter signed [31:0] result_MSB = result_width - 1;
parameter signed [31:0] result_LSB = vec_MSB - result_MSB;
input [vec_MSB : 0] inp;
output [result_MSB : 0] res;
wire [vec_MSB:0] vec;
genvar i;
assign res = vec[vec_MSB:result_LSB];
generate
if (shift_dir == 1)
begin:left_shift_loop
for (i = vec_MSB; i>=0; i = i-1)
begin:u0
if (i < shift_value)
begin:u1
assign vec[i] = 1'b0;
end
else
begin:u2
assign vec[i] = inp[i-shift_value];
end
end
end
else
begin:right_shift_loop
for (i = 0; i <= vec_MSB; i = i+1)
begin:u3
if (i > vec_MSB - shift_value)
begin:u4
assign vec[i] = inp[vec_MSB];
end
else
begin:u5
assign vec[i] = inp[i+shift_value];
end
end
end
endgenerate
endmodule // shift_op
module pad_lsb (inp, res);
parameter signed [31:0] orig_width = 4;
parameter signed [31:0] new_width = 2;
input [orig_width - 1 : 0] inp;
output [new_width - 1 : 0] res;
parameter signed [31:0] pad_pos = new_width - orig_width -1;
wire [new_width-1:0] result;
genvar i;
assign res = result;
generate
if (new_width >= orig_width)
begin:u0
assign result[new_width-1:new_width-orig_width] = inp[orig_width-1:0];
end
endgenerate
generate
if (pad_pos >= 0)
begin:u1
assign result[pad_pos:0] = {(pad_pos+1){1'b0}};
end
endgenerate
endmodule // pad_lsb
// zero extend the MSB
module zero_ext (inp, res);
parameter signed [31:0] old_width = 4;
parameter signed [31:0] new_width = 2;
input [old_width - 1 : 0] inp;
output [new_width - 1 : 0] res;
wire [new_width-1:0] result;
genvar i;
assign res = result;
generate
if (new_width > old_width)
begin:u0
assign result = { {(new_width-old_width){1'b0}}, inp}; //zero extend
end // if (new_width >= old_width)
else
begin:u1
assign result[new_width-1:0] = inp[new_width-1:0];
end // else: !if(new_width >= old_width)
endgenerate
endmodule // zero_ext
// sign extend the MSB
module sign_ext (inp, res);
parameter signed [31:0] old_width = 4;
parameter signed [31:0] new_width = 2;
input [old_width - 1 : 0] inp;
output [new_width - 1 : 0] res;
wire [new_width-1:0] result;
assign res = result;
generate
if (new_width > old_width)
begin:u0
assign result = { {(new_width-old_width){inp[old_width-1]}}, inp};//sign extend
end // if (new_width >= old_width)
else
begin:u1
assign result[new_width-1:0] = inp[new_width-1:0];
end // else: !if(new_width >= old_width)
endgenerate
endmodule // sign_ext
// zero or sign extend the MSB
module extend_msb (inp, res);
parameter signed [31:0] old_width = 4;
parameter signed [31:0] new_width = 4;
parameter signed [31:0] new_arith = `xlSigned;
input [old_width - 1 : 0] inp;
output [new_width - 1 : 0] res;
wire [new_width-1:0] result;
assign res = result;
generate
if (new_arith ==`xlUnsigned)
begin:u0
zero_ext # (old_width, new_width)
em_zero_ext (.inp(inp), .res(result));
end
else
begin:u1
sign_ext # (old_width, new_width)
em_sign_ext (.inp(inp), .res(result));
end
endgenerate
endmodule //extend_msb
// Align input by padding LSB with zeros and sign or zero extending
module align_input (inp, res);
parameter signed [31:0] old_width = 4;
parameter signed [31:0] delta = 1;
parameter signed [31:0] new_arith = `xlSigned;
parameter signed [31:0] new_width = 4;
input [old_width - 1 : 0] inp;
output [new_width - 1 : 0] res;
parameter signed [31:0] abs_delta = (delta >= 0) ? (delta) : (-delta);
wire [new_width-1:0] result;
wire [(old_width+abs_delta)-1:0] padded_inp;
assign res = result;
generate
if (delta > 0)
begin:u0
pad_lsb # (old_width, old_width+delta)
ai_pad_lsb (.inp(inp), .res(padded_inp));
extend_msb # (old_width+delta, new_width, new_arith)
ai_extend_msb (.inp(padded_inp), .res(result));
end
else
begin:u1
extend_msb # (old_width, new_width, new_arith)
ai_extend_msb (.inp(inp), .res(result));
end
endgenerate
endmodule //align_input
/////////////////////////////////////////////////////////////////////////////
// Overflow Functions
////////////////////////////////////////////////////////////////////////////
// Round Towards Infinity
module round_towards_inf (inp, res);
parameter signed [31:0] old_width = 4;
parameter signed [31:0] old_bin_pt = 2;
parameter signed [31:0] old_arith = `xlSigned;
parameter signed [31:0] new_width = 4;
parameter signed [31:0] new_bin_pt = 1;
parameter signed [31:0] new_arith = `xlSigned;
input [old_width - 1 : 0] inp;
output [new_width - 1 : 0] res;
// Number of binary digits to add/subract to the right of the decimal point
parameter signed [31:0] right_of_dp = old_bin_pt - new_bin_pt;
// Absolute value of right of DP
parameter signed [31:0] abs_right_of_dp = (new_bin_pt > old_bin_pt) ? (new_bin_pt-old_bin_pt) : (old_bin_pt - new_bin_pt);
parameter signed [31:0] right_of_dp_2 = (right_of_dp >=2) ? right_of_dp-2 : 0;
parameter signed [31:0] right_of_dp_1 = (right_of_dp >=1) ? right_of_dp-1 : 0;
//parameter signed [31:0] expected_new_width = old_width - right_of_dp + 1;
reg [new_width-1:0] one_or_zero;
wire [new_width-1:0] truncated_val;
wire signed [new_width-1:0] result_signed;
wire [abs_right_of_dp+old_width-1 : 0] padded_val;
initial
begin
one_or_zero = {new_width{1'b0}};
end
generate
if (right_of_dp >= 0)
begin:u0 // Sign extend or zero extend to size of output
if (new_arith ==`xlUnsigned)
begin:u1
zero_ext # (old_width-right_of_dp, new_width)
rti_zero_ext (.inp(inp[old_width-1:right_of_dp]), .res(truncated_val));
end
else
begin:u2
sign_ext # (old_width-right_of_dp, new_width)
rti_sign_ext (.inp(inp[old_width-1:right_of_dp]), .res(truncated_val));
end
end // if (right_of_dp >= 0)
else
begin:u3 // Pad LSB with zeros and sign extend by one bit
pad_lsb # (old_width, abs_right_of_dp+old_width)
rti_pad_lsb (.inp(inp), .res(padded_val));
if (new_arith ==`xlUnsigned)
begin:u4
zero_ext # (abs_right_of_dp+old_width, new_width)
rti_zero_ext1 (.inp(padded_val), .res(truncated_val));
end
else
begin:u5
sign_ext # (abs_right_of_dp+old_width, new_width)
rti_sign_ext1 (.inp(padded_val), .res(truncated_val));
end
end // else: !if(right_of_dp >= 0)
endgenerate
generate
if (new_arith == `xlSigned)
begin:u6
always @(inp)
begin
// Figure out if '1' should be added to the truncated number
one_or_zero = {new_width{1'b0}};
// Rounding logic for signed numbers
// Example:
// Fix(5,-2) = 101.11 (bin) -2.25 (dec)
// Converted to: Fix(4,-1) = 101.1 (bin) -2.5 (dec)
// Note: same algorithm used for unsigned numbers can't be used.
// 1st check the sign bit of the input to see if it is a positive number
if (inp[old_width-1] == 1'b0)
begin
one_or_zero[0] = 1'b1;
end
// 2nd check if digits being truncated are all zeros
// (in example if is bit zero)
if ((right_of_dp >=2) && (right_of_dp <= old_width))
begin
if(|inp[right_of_dp_2:0] == 1'b1)
begin
one_or_zero[0] = 1'b1;
end
end
// 3rd check if the bit right before the truncation point is '1'
// or '0' (in example it is bit one)
if ((right_of_dp >=1) && (right_of_dp <= old_width))
begin
if(inp[right_of_dp_1] == 1'b0)
begin
one_or_zero[0] = 1'b0;
end
end // if((right_of_dp >=1) && (right_of_dp <= old_width))
else
// No rounding to be performed
begin
one_or_zero[0] = 1'b0;
end // else: !if((right_of_dp >=1) && (right_of_dp <= old_width))
end // always @ (inp)
assign result_signed = truncated_val + one_or_zero;
assign res = result_signed;
end // if (new_arith = `xlSigned)
else
// For an unsigned number just check if the bit right before the
// truncation point is '1' or '0'
begin:u7
always @(inp)
begin
// Figure out if '1' should be added to the truncated number
one_or_zero = {new_width{1'b0}};
if ((right_of_dp >=1) && (right_of_dp <= old_width))
begin
one_or_zero[0] = inp[right_of_dp_1];
end // if((right_of_dp >=1) && (right_of_dp <= old_width))
end // always @ (inp)
assign res = truncated_val + one_or_zero;
end // else: !if(new_arith = `xlSigned)
endgenerate
endmodule // round_towards_inf
// Round towards even values
module round_towards_even (inp, res);
parameter signed [31:0] old_width = 4;
parameter signed [31:0] old_bin_pt = 2;
parameter signed [31:0] old_arith = `xlSigned;
parameter signed [31:0] new_width = 4;
parameter signed [31:0] new_bin_pt = 1;
parameter signed [31:0] new_arith = `xlSigned;
input [old_width - 1 : 0] inp;
output [new_width - 1 : 0] res;
//Number of binary digits to add/subract to the right of the decimal point
parameter signed [31:0] right_of_dp = old_bin_pt - new_bin_pt;
// Absolute value of right of DP
parameter signed [31:0] abs_right_of_dp = (new_bin_pt > old_bin_pt) ? (new_bin_pt-old_bin_pt) : (old_bin_pt - new_bin_pt);
parameter signed [31:0] expected_new_width = old_width - right_of_dp + 1;
reg [new_width-1:0] one_or_zero;
wire signed [new_width-1:0] result_signed;
wire [new_width-1:0] truncated_val;
wire [abs_right_of_dp+old_width-1 : 0] padded_val;
initial
begin
one_or_zero = { new_width{1'b0}};
end
generate
if (right_of_dp >= 0)
// Sign extend or zero extend to size of output
begin:u0
if (new_arith == `xlUnsigned)
begin:u1
zero_ext # (old_width-right_of_dp, new_width)
rte_zero_ext (.inp(inp[old_width-1:right_of_dp]), .res(truncated_val));
end
else
begin:u2
sign_ext # (old_width-right_of_dp, new_width)
rte_sign_ext (.inp(inp[old_width-1:right_of_dp]), .res(truncated_val));
end
end // if (right_of_dp >= 0)
else
// Pad LSB with zeros and sign extend by one bit
begin:u3
pad_lsb # (old_width, abs_right_of_dp+old_width)
rte_pad_lsb (.inp(inp), .res(padded_val));
if (new_arith == `xlUnsigned)
begin:u4
zero_ext # (abs_right_of_dp+old_width, new_width)
rte_zero_ext1 (.inp(padded_val), .res(truncated_val));
end
else
begin:u5
sign_ext # (abs_right_of_dp+old_width, new_width)
rte_sign_ext1 (.inp(padded_val), .res(truncated_val));
end
end // else: !if(right_of_dp >= 0)
endgenerate
generate
// Figure out if '1' should be added to the truncated number
// For the truncated bits just check if the bits after the
// truncation point are 0.5
if ((right_of_dp ==1) && (right_of_dp <= old_width))
begin:u6a
always @(inp)
begin
one_or_zero = { new_width{1'b0}};
if(inp[right_of_dp-1] == 1'b1)
begin
one_or_zero[0] = inp[right_of_dp];
end
else
begin
one_or_zero[0] = inp[right_of_dp-1];
end
end // always @ (inp)
end // block: u6
else if ((right_of_dp >=2) && (right_of_dp <= old_width))
begin:u6b
always @(inp)
begin
one_or_zero = { new_width{1'b0}};
if( (inp[right_of_dp-1] == 'b1) && !(|inp[right_of_dp-2:0]) )
begin
one_or_zero[0] = inp[right_of_dp];
end
else
begin
one_or_zero[0] = inp[right_of_dp-1];
end
end // always @ (inp)
end // block: u6
else
begin:u7
always @(inp)
begin
one_or_zero = { new_width{1'b0}};
end
end
endgenerate
generate
if (new_arith == `xlSigned)
begin:u8
assign result_signed = truncated_val + one_or_zero;
assign res = result_signed;
end
else
begin:u9
assign res = truncated_val + one_or_zero;
end
endgenerate
endmodule // round_towards_even
// Truncate LSB bits
module trunc (inp, res);
parameter signed [31:0] old_width = 4;
parameter signed [31:0] old_bin_pt = 2;
parameter signed [31:0] old_arith = `xlSigned;
parameter signed [31:0] new_width = 4;
parameter signed [31:0] new_bin_pt = 1;
parameter signed [31:0] new_arith = `xlSigned;
input [old_width - 1 : 0] inp;
output [new_width - 1 : 0] res;
//Number of binary digits to add/subract to the right of the decimal point
parameter signed [31:0] right_of_dp = old_bin_pt - new_bin_pt;
// Absolute value of right of DP
parameter signed [31:0] abs_right_of_dp = (new_bin_pt > old_bin_pt) ? (new_bin_pt-old_bin_pt) : (old_bin_pt - new_bin_pt);
wire [new_width-1:0] result;
wire [abs_right_of_dp+old_width-1 : 0] padded_val;
assign res = result;
generate
if (new_bin_pt > old_bin_pt)
begin:tr_u2
pad_lsb # (old_width, abs_right_of_dp+old_width)
tr_pad_lsb (.inp(inp), .res(padded_val));
extend_msb # (old_width+abs_right_of_dp, new_width, new_arith)
tr_extend_msb (.inp(padded_val), .res(result));
end
else
begin:tr_u1
extend_msb # (old_width-right_of_dp, new_width, new_arith)
tr_extend_msb (.inp(inp[old_width-1:right_of_dp]), .res(result));
end
endgenerate
endmodule // trunc
/////////////////////////////////////////////////////////////////////////////
// Overflow Functions
////////////////////////////////////////////////////////////////////////////
// -- Apply Saturation arithmetic. The new_bin_pt and old bin_pt should be
// -- equal. The function chops bits off MSB bits.
module saturation_arith (inp, res);
parameter signed [31:0] old_width = 4;
parameter signed [31:0] old_bin_pt = 2;
parameter signed [31:0] old_arith = `xlSigned;
parameter signed [31:0] new_width = 4;
parameter signed [31:0] new_bin_pt = 1;
parameter signed [31:0] new_arith = `xlSigned;
input [old_width - 1 : 0] inp;
output [new_width - 1 : 0] res;
// -- Number of digits to add/subract to the left of the decimal point
parameter signed [31:0] abs_right_of_dp = (new_bin_pt > old_bin_pt) ? (new_bin_pt-old_bin_pt) : (old_bin_pt - new_bin_pt);
parameter signed [31:0] abs_width = (new_width > old_width) ? (new_width-old_width) : 1;
parameter signed [31:0] abs_new_width = (old_width > new_width) ? new_width : 1;
reg overflow;
reg [old_width-1:0] vec;
reg [new_width-1:0] result;
assign res = result;
////////////////////////////////////////////////////
// For input width less than output width overflow
///////////////////////////////////////////////////
generate
if (old_width > new_width)
begin:sa_u0
always @ (inp)
begin
vec = inp;
overflow = 1;
////////////////////////////////////////////////////
// Check for cases when overflow does not occur
///////////////////////////////////////////////////
// Case #1:
// Both the input and output are signed and the bits that will
// be truncated plus the sign bit are all the same
// (i.e., number has been sign extended)
if ( (old_arith == `xlSigned) && (new_arith == `xlSigned) )
begin
if (~|inp[old_width-1:abs_new_width-1] || &inp[old_width-1:abs_new_width-1])
begin
overflow = 0;
end
end
// Case #2:
// If the input is converted to a unsigned from signed then only
// check the bits that will be truncated are all zero
if ( (old_arith == `xlSigned) && (new_arith == `xlUnsigned))
begin
if (~|inp[old_width-1 : abs_new_width])
begin
overflow = 0;
end
end
// Case #3:
// Input is unsigned and the bits that will be truncated are all zero
if ((old_arith == `xlUnsigned) && (new_arith == `xlUnsigned))
begin
if (~|inp[old_width-1 : abs_new_width])
begin
overflow = 0;
end
end
// Case #4:
// Input is unsigned but output signed and the bits that will be
// truncated are all the same
if ( (old_arith == `xlUnsigned) && (new_arith == `xlSigned))
begin
if (~|inp[old_width-1:abs_new_width-1] || &inp[old_width-1:abs_new_width-1])
begin
overflow = 0;
end
end
if (overflow == 1) //overflow occured
begin
if (new_arith == `xlSigned)
begin
if (inp[old_width-1] == 'b0)
begin
result = (new_width ==1) ? 1'b0 : {1'b0, {(new_width-1){1'b1}} };//max_signed with fix for CR#434004
end
else
begin
result = (new_width ==1) ? 1'b1 : {1'b1, {(new_width-1){1'b0}} };//min_signed with fix for CR#434004
end
end // if (new_arith = `xlsigned)
else
begin
if ((old_arith == `xlSigned) && (inp[old_width-1] == 'b1))
begin
result = {new_width{1'b0}};
end
else
begin
result = {new_width{1'b1}};
end
end // else: !if(new_arith = `xlsigned)
end // if (overflow = 1)
else //overflow did not occur
begin
// Check for case when input type is signed and output type
// unsigned
//If negative number set to zero
if ( (old_arith == `xlSigned) && (new_arith == `xlUnsigned) && (inp[old_width-1] == 'b1) )
begin
vec = {old_width{1'b0}};
end
result = vec[new_width-1:0];
end
end // else: !if(overflow = 1)
end
endgenerate
////////////////////////////////////////////////////
// For input width greater than output width overflow
///////////////////////////////////////////////////
generate
if (new_width > old_width)
begin:sa_u1
always @ (inp)
begin
vec = inp;
// Check for case when input type is signed and output type
// unsigned
//If negative number set to zero
if ( (old_arith == `xlSigned) && (new_arith == `xlUnsigned) && (inp[old_width-1] == 1'b1) )
begin
vec = {old_width{1'b0}};
end
// Sign or zero extend number depending on arith of new number
if (new_arith == `xlUnsigned)
begin
result = { {abs_width{1'b0}}, vec};
end
else
begin
result = { {abs_width{inp[old_width-1]}}, vec};
end
end
end
endgenerate
////////////////////////////////////////////////////
// For input width equal to output width overflow
///////////////////////////////////////////////////
generate
if (new_width == old_width)
begin:sa_u2
always @ (inp)
begin
// Check for case when input type is signed and output type
// unsigned
//If negative number set to zero
if ( (old_arith == `xlSigned) && (new_arith == `xlUnsigned) && (inp[old_width-1] == 'b1) )
begin
result = {old_width{1'b0}};
end
else
begin
result = inp;
end
end
end
endgenerate
endmodule
module wrap_arith (inp, res);
parameter signed [31:0] old_width = 4;
parameter signed [31:0] old_bin_pt = 2;
parameter signed [31:0] old_arith = `xlSigned;
parameter signed [31:0] new_width = 4;
parameter signed [31:0] new_bin_pt = 1;
parameter signed [31:0] new_arith = `xlSigned;
parameter signed [31:0] result_arith = ((old_arith==`xlSigned)&&(new_arith==`xlUnsigned))? `xlSigned : new_arith;
input [old_width - 1 : 0] inp;
output [new_width - 1 : 0] res;
wire [new_width-1:0] result;
cast # (old_width, old_bin_pt, new_width, new_bin_pt, result_arith)
wrap_cast (.inp(inp), .res(result));
assign res = result;
endmodule // wrap_arith
// Convert one Fix point type to another fixed point type with a
// different bin_pt, width, and arithmetic type
module convert_type (inp, res);
parameter signed [31:0] old_width = 4;
parameter signed [31:0] old_bin_pt = 2;
parameter signed [31:0] old_arith = `xlSigned;
parameter signed [31:0] new_width = 4;
parameter signed [31:0] new_bin_pt = 1;
parameter signed [31:0] new_arith = `xlSigned;
parameter signed [31:0] quantization = `xlTruncate;
parameter signed [31:0] overflow = `xlWrap;
input [old_width - 1 : 0] inp;
output [new_width - 1 : 0] res;
parameter signed [31:0] fp_width = old_width + 2;
parameter signed [31:0] fp_bin_pt = old_bin_pt;
parameter signed [31:0] fp_arith = old_arith;
parameter signed [31:0] q_width = fp_width + new_bin_pt - old_bin_pt;
parameter signed [31:0] q_bin_pt = new_bin_pt;
parameter signed [31:0] q_arith = old_arith;
wire [fp_width-1:0] full_precision_result;
wire [new_width-1:0] result;
wire [q_width-1:0] quantized_result;
assign res = result;
// old_bin_pt = fp_bin_pt
cast # (old_width, old_bin_pt, fp_width, fp_bin_pt, fp_arith)
fp_cast (.inp(inp), .res(full_precision_result));
generate
// Apply quantization functions. This will remove LSB bits.
if (quantization == `xlRound)
begin:ct_u0
round_towards_inf # (fp_width, fp_bin_pt, fp_arith, q_width, q_bin_pt, q_arith)
quant_rtf (.inp(full_precision_result), .res(quantized_result));
end
endgenerate
generate
if (quantization == `xlRoundBanker)
begin:ct_u1
round_towards_even # (fp_width, fp_bin_pt, fp_arith, q_width, q_bin_pt, q_arith)
quant_rte (.inp(full_precision_result), .res(quantized_result));
end
endgenerate
generate
if (quantization == `xlTruncate)
begin:ct_u2
trunc # (fp_width, fp_bin_pt, fp_arith, q_width, q_bin_pt, q_arith)
quant_tr (.inp(full_precision_result), .res(quantized_result));
end
endgenerate
generate
// Apply overflow function. This will remove MSB bits.
if (overflow == `xlSaturate)
begin:ct_u3
// q_bin_pt = new_bin_pt
saturation_arith # (q_width, q_bin_pt, q_arith, new_width, new_bin_pt, new_arith)
ovflo_sat (.inp(quantized_result), .res(result));
end
endgenerate
// Apply Wrap behavior if saturate is not selected
// The legal values that could be passed are 1 and 2
// Some blocks pass illegal value of 3 (Flag as error)
// in which case we should use xlWrap also.
generate
if ((overflow == `xlWrap) || (overflow == 3))
begin:ct_u4
wrap_arith # (q_width, q_bin_pt, q_arith, new_width, new_bin_pt, new_arith)
ovflo_wrap (.inp(quantized_result), .res(result));
end
endgenerate
endmodule // convert_type
`endif

975
library/ip_pid_controller/hdl/ip_pid_controller.v Executable file
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@ -0,0 +1,975 @@
//-----------------------------------------------------------------
// System Generator version 2013.4 Verilog source file.
//
// Copyright(C) 2013 by Xilinx, Inc. All rights reserved. This
// text/file contains proprietary, confidential information of Xilinx,
// Inc., is distributed under license from Xilinx, Inc., and may be used,
// copied and/or disclosed only pursuant to the terms of a valid license
// agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
// this text/file solely for design, simulation, implementation and
// creation of design files limited to Xilinx devices or technologies.
// Use with non-Xilinx devices or technologies is expressly prohibited
// and immediately terminates your license unless covered by a separate
// agreement.
//
// Xilinx is providing this design, code, or information "as is" solely
// for use in developing programs and solutions for Xilinx devices. By
// providing this design, code, or information as one possible
// implementation of this feature, application or standard, Xilinx is
// making no representation that this implementation is free from any
// claims of infringement. You are responsible for obtaining any rights
// you may require for your implementation. Xilinx expressly disclaims
// any warranty whatsoever with respect to the adequacy of the
// implementation, including but not limited to warranties of
// merchantability or fitness for a particular purpose.
//
// Xilinx products are not intended for use in life support appliances,
// devices, or systems. Use in such applications is expressly prohibited.
//
// Any modifications that are made to the source code are done at the user's
// sole risk and will be unsupported.
//
// This copyright and support notice must be retained as part of this
// text at all times. (c) Copyright 1995-2013 Xilinx, Inc. All rights
// reserved.
//-----------------------------------------------------------------
`ifndef xlConvPkgIncluded
`include "conv_pkg.v"
`endif
// Generated from Simulink block "ip_pid_controller/Edge Detection"
module edge_detection_69f9d322be (
clk_1,
ce_1,
in1,
out1
);
input clk_1;
input ce_1;
input in1;
output out1;
wire clk_1_net;
wire ce_1_net;
wire [7:0] constant_op_net;
wire [7:0] counter_op_net;
wire delay_q_net;
wire inverter_op_net;
wire logical_y_net;
wire register_q_net;
wire register1_q_net;
wire relational_op_net;
wire new_motor_speed_net;
wire logical1_y_net;
assign clk_1_net = clk_1;
assign ce_1_net = ce_1;
assign new_motor_speed_net = in1;
assign out1 = logical1_y_net;
sysgen_constant_383443dd88 constant_x0 (
.clk(1'b0),
.ce(1'b0),
.clr(1'b0),
.op(constant_op_net)
);
xlcounter_limit_ip_pid_controller #(
.cnt_15_0(99),
.cnt_31_16(0),
.cnt_47_32(0),
.cnt_63_48(0),
.core_name0("ip_pid_controller_c_counter_binary_v12_0_0"),
.count_limited(1),
.op_arith(`xlUnsigned),
.op_width(8))
counter (
.ce(ce_1_net),
.clk(clk_1_net),
.rst(1'b0),
.clr(1'b0),
.en(delay_q_net),
.op(counter_op_net)
);
xldelay_ip_pid_controller #(
.latency(25),
.reg_retiming(0),
.reset(0),
.width(1))
delay (
.ce(ce_1_net),
.clk(clk_1_net),
.en(1'b1),
.rst(1'b1),
.d(logical_y_net),
.q(delay_q_net)
);
sysgen_inverter_91fd45ca5a inverter (
.ce(ce_1_net),
.clk(clk_1_net),
.clr(1'b0),
.ip(register1_q_net),
.op(inverter_op_net)
);
sysgen_logical_098c9fa070 logical (
.clk(1'b0),
.ce(1'b0),
.clr(1'b0),
.d0(register_q_net),
.d1(inverter_op_net),
.y(logical_y_net)
);
sysgen_logical_098c9fa070 logical1 (
.clk(1'b0),
.ce(1'b0),
.clr(1'b0),
.d0(delay_q_net),
.d1(relational_op_net),
.y(logical1_y_net)
);
xlregister_ip_pid_controller #(
.d_width(1),
.init_value(1'b0))
register_x0 (
.ce(ce_1_net),
.clk(clk_1_net),
.en(1'b1),
.rst(1'b0),
.d(new_motor_speed_net),
.q(register_q_net)
);
xlregister_ip_pid_controller #(
.d_width(1),
.init_value(1'b0))
register1 (
.ce(ce_1_net),
.clk(clk_1_net),
.en(1'b1),
.rst(1'b0),
.d(new_motor_speed_net),
.q(register1_q_net)
);
sysgen_relational_0c5dbda85b relational (
.clk(1'b0),
.ce(1'b0),
.clr(1'b0),
.a(constant_op_net),
.b(counter_op_net),
.op(relational_op_net)
);
endmodule
// Generated from Simulink block "ip_pid_controller/PID Controller/Accumulator"
module accumulator_0c8f1c90b9 (
clk_1,
ce_1,
rst,
en,
err,
pwm
);
input clk_1;
input ce_1;
input rst;
input en;
input [31:0] err;
output [31:0] pwm;
wire clk_1_net;
wire ce_1_net;
wire [31:0] constant4_op_net;
wire [31:0] constant5_op_net;
wire [31:0] constant6_op_net;
wire [31:0] constant7_op_net;
wire logical_y_net_x0;
wire logical1_y_net_x0;
wire logical2_y_net;
wire relational_op_net_x0;
wire relational1_op_net;
wire relational2_op_net;
wire relational3_op_net;
wire rst_net;
wire logical1_y_net;
wire [31:0] mult_p_net;
wire [31:0] accumulator_q_net;
assign clk_1_net = clk_1;
assign ce_1_net = ce_1;
assign rst_net = rst;
assign logical1_y_net = en;
assign mult_p_net = err;
assign pwm = accumulator_q_net;
sysgen_accum_ac23432ab2 accumulator (
.ce(ce_1_net),
.clk(clk_1_net),
.clr(1'b0),
.b(mult_p_net),
.rst(rst_net),
.en(logical2_y_net),
.q(accumulator_q_net)
);
sysgen_constant_b4741603e8 constant4 (
.clk(1'b0),
.ce(1'b0),
.clr(1'b0),
.op(constant4_op_net)
);
sysgen_constant_a7c2a996dd constant5 (
.clk(1'b0),
.ce(1'b0),
.clr(1'b0),
.op(constant5_op_net)
);
sysgen_constant_bd840882a6 constant6 (
.clk(1'b0),
.ce(1'b0),
.clr(1'b0),
.op(constant6_op_net)
);
sysgen_constant_a7c2a996dd constant7 (
.clk(1'b0),
.ce(1'b0),
.clr(1'b0),
.op(constant7_op_net)
);
sysgen_logical_0c47d61908 logical (
.clk(1'b0),
.ce(1'b0),
.clr(1'b0),
.d0(relational_op_net_x0),
.d1(relational1_op_net),
.y(logical_y_net_x0)
);
sysgen_logical_0c47d61908 logical1 (
.clk(1'b0),
.ce(1'b0),
.clr(1'b0),
.d0(relational2_op_net),
.d1(relational3_op_net),
.y(logical1_y_net_x0)
);
sysgen_logical_7913ccf482 logical2 (
.clk(1'b0),
.ce(1'b0),
.clr(1'b0),
.d0(logical1_y_net),
.d1(logical1_y_net_x0),
.d2(logical_y_net_x0),
.y(logical2_y_net)
);
sysgen_relational_56046aa836 relational (
.clk(1'b0),
.ce(1'b0),
.clr(1'b0),
.a(accumulator_q_net),
.b(constant4_op_net),
.op(relational_op_net_x0)
);
sysgen_relational_56046aa836 relational1 (
.clk(1'b0),
.ce(1'b0),
.clr(1'b0),
.a(mult_p_net),
.b(constant5_op_net),
.op(relational1_op_net)
);
sysgen_relational_860373682b relational2 (
.clk(1'b0),
.ce(1'b0),
.clr(1'b0),
.a(accumulator_q_net),
.b(constant6_op_net),
.op(relational2_op_net)
);
sysgen_relational_860373682b relational3 (
.clk(1'b0),
.ce(1'b0),
.clr(1'b0),
.a(mult_p_net),
.b(constant7_op_net),
.op(relational3_op_net)
);
endmodule
// Generated from Simulink block "ip_pid_controller/PID Controller"
module pid_controller_dfc330003e (
clk_1,
ce_1,
en_acc,
rst_acc,
kd,
ki,
kp,
err,
pwm
);
input clk_1;
input ce_1;
input en_acc;
input rst_acc;
input [31:0] kd;
input [31:0] ki;
input [31:0] kp;
input [31:0] err;
output [31:0] pwm;
wire clk_1_net;
wire ce_1_net;
wire [31:0] addsub1_s_net;
wire [31:0] addsub2_s_net;
wire [31:0] delay_q_net_x0;
wire [31:0] delay1_q_net;
wire [31:0] mult_p_net;
wire [31:0] mult1_p_net;
wire [31:0] mult2_p_net;
wire logical1_y_net;
wire rst_net;
wire [31:0] kd_net;
wire [31:0] ki_net;
wire [31:0] kp_net;
wire [31:0] addsub_s_net;
wire [31:0] addsub3_s_net;
wire [31:0] accumulator_q_net;
assign clk_1_net = clk_1;
assign ce_1_net = ce_1;
assign logical1_y_net = en_acc;
assign rst_net = rst_acc;
assign kd_net = kd;
assign ki_net = ki;
assign kp_net = kp;
assign addsub_s_net = err;
assign pwm = addsub3_s_net;
xladdsub_ip_pid_controller #(
.a_arith(`xlSigned),
.a_bin_pt(16),
.a_width(32),
.b_arith(`xlSigned),
.b_bin_pt(16),
.b_width(32),
.c_has_c_out(0),
.c_latency(0),
.c_output_width(33),
.core_name0("ip_pid_controller_c_addsub_v12_0_0"),
.extra_registers(0),
.full_s_arith(2),
.full_s_width(33),
.latency(0),
.overflow(1),
.quantization(1),
.s_arith(`xlSigned),
.s_bin_pt(16),
.s_width(32))
addsub1 (
.ce(ce_1_net),
.clk(clk_1_net),
.clr(1'b0),
.en(1'b1),
.a(addsub_s_net),
.b(delay1_q_net),
.s(addsub1_s_net)
);
xladdsub_ip_pid_controller #(
.a_arith(`xlSigned),
.a_bin_pt(16),
.a_width(32),
.b_arith(`xlSigned),
.b_bin_pt(16),
.b_width(32),
.c_has_c_out(0),
.c_latency(0),
.c_output_width(33),
.core_name0("ip_pid_controller_c_addsub_v12_0_1"),
.extra_registers(0),
.full_s_arith(2),
.full_s_width(33),
.latency(0),
.overflow(1),
.quantization(1),
.s_arith(`xlSigned),
.s_bin_pt(16),
.s_width(32))
addsub2 (
.ce(ce_1_net),
.clk(clk_1_net),
.clr(1'b0),
.en(1'b1),
.a(mult1_p_net),
.b(mult2_p_net),
.s(addsub2_s_net)
);
xladdsub_ip_pid_controller #(
.a_arith(`xlSigned),
.a_bin_pt(16),
.a_width(32),
.b_arith(`xlSigned),
.b_bin_pt(16),
.b_width(32),
.c_has_c_out(0),
.c_latency(0),
.c_output_width(33),
.core_name0("ip_pid_controller_c_addsub_v12_0_1"),
.extra_registers(0),
.full_s_arith(2),
.full_s_width(33),
.latency(0),
.overflow(1),
.quantization(1),
.s_arith(`xlSigned),
.s_bin_pt(16),
.s_width(32))
addsub3 (
.ce(ce_1_net),
.clk(clk_1_net),
.clr(1'b0),
.en(1'b1),
.a(accumulator_q_net),
.b(addsub2_s_net),
.s(addsub3_s_net)
);
xldelay_ip_pid_controller #(
.latency(1),
.reg_retiming(0),
.reset(0),
.width(32))
delay (
.ce(ce_1_net),
.clk(clk_1_net),
.rst(1'b1),
.d(addsub_s_net),
.en(logical1_y_net),
.q(delay_q_net_x0)
);
xldelay_ip_pid_controller #(
.latency(1),
.reg_retiming(0),
.reset(0),
.width(32))
delay1 (
.ce(ce_1_net),
.clk(clk_1_net),
.rst(1'b1),
.d(delay_q_net_x0),
.en(logical1_y_net),
.q(delay1_q_net)
);
xlmult_ip_pid_controller #(
.a_arith(`xlSigned),
.a_bin_pt(16),
.a_width(32),
.b_arith(`xlSigned),
.b_bin_pt(16),
.b_width(32),
.c_a_type(0),
.c_a_width(32),
.c_b_type(0),
.c_b_width(32),
.c_baat(32),
.c_output_width(64),
.c_type(0),
.core_name0("ip_pid_controller_mult_gen_v12_0_0"),
.extra_registers(1),
.multsign(2),
.overflow(2),
.p_arith(`xlSigned),
.p_bin_pt(16),
.p_width(32),
.quantization(1))
mult (
.core_ce(ce_1_net),
.core_clk(clk_1_net),
.ce(ce_1_net),
.clk(clk_1_net),
.clr(1'b0),
.core_clr(1'b1),
.en(1'b1),
.rst(1'b0),
.a(addsub_s_net),
.b(ki_net),
.p(mult_p_net)
);
xlmult_ip_pid_controller #(
.a_arith(`xlSigned),
.a_bin_pt(16),
.a_width(32),
.b_arith(`xlSigned),
.b_bin_pt(16),
.b_width(32),
.c_a_type(0),
.c_a_width(32),
.c_b_type(0),
.c_b_width(32),
.c_baat(32),
.c_output_width(64),
.c_type(0),
.core_name0("ip_pid_controller_mult_gen_v12_0_0"),
.extra_registers(1),
.multsign(2),
.overflow(2),
.p_arith(`xlSigned),
.p_bin_pt(16),
.p_width(32),
.quantization(1))
mult1 (
.core_ce(ce_1_net),
.core_clk(clk_1_net),
.ce(ce_1_net),
.clk(clk_1_net),
.clr(1'b0),
.core_clr(1'b1),
.en(1'b1),
.rst(1'b0),
.a(addsub_s_net),
.b(kp_net),
.p(mult1_p_net)
);
xlmult_ip_pid_controller #(
.a_arith(`xlSigned),
.a_bin_pt(16),
.a_width(32),
.b_arith(`xlSigned),
.b_bin_pt(16),
.b_width(32),
.c_a_type(0),
.c_a_width(32),
.c_b_type(0),
.c_b_width(32),
.c_baat(32),
.c_output_width(64),
.c_type(0),
.core_name0("ip_pid_controller_mult_gen_v12_0_0"),
.extra_registers(1),
.multsign(2),
.overflow(2),
.p_arith(`xlSigned),
.p_bin_pt(16),
.p_width(32),
.quantization(1))
mult2 (
.core_ce(ce_1_net),
.core_clk(clk_1_net),
.ce(ce_1_net),
.clk(clk_1_net),
.clr(1'b0),
.core_clr(1'b1),
.en(1'b1),
.rst(1'b0),
.a(addsub1_s_net),
.b(kd_net),
.p(mult2_p_net)
);
accumulator_0c8f1c90b9 accumulator (
.clk_1(clk_1_net),
.ce_1(ce_1_net),
.rst(rst_net),
.en(logical1_y_net),
.err(mult_p_net),
.pwm(accumulator_q_net)
);
endmodule
// Generated from Simulink block "ip_pid_controller/Speed Computation"
module speed_computation_8d613ce520 (
clk_1,
ce_1,
speed_cnt,
speed_rpm
);
input clk_1;
input ce_1;
input [31:0] speed_cnt;
output [31:0] speed_rpm;
wire clk_1_net;
wire ce_1_net;
wire [31:0] constant_op_net_x0;
wire [37:0] divide_op_net;
wire [31:0] motor_speed_net;
wire [31:0] convert_dout_net_x0;
assign clk_1_net = clk_1;
assign ce_1_net = ce_1;
assign motor_speed_net = speed_cnt;
assign speed_rpm = convert_dout_net_x0;
sysgen_constant_61a644b4c8 constant_x0 (
.clk(1'b0),
.ce(1'b0),
.clr(1'b0),
.op(constant_op_net_x0)
);
xlconvert_ip_pid_controller #(
.bool_conversion(0),
.din_arith(2),
.din_bin_pt(6),
.din_width(38),
.dout_arith(2),
.dout_bin_pt(16),
.dout_width(32),
.latency(1),
.overflow(`xlSaturate),
.quantization(`xlTruncate))
convert (
.ce(ce_1_net),
.clk(clk_1_net),
.clr(1'b0),
.en(1'b1),
.din(divide_op_net),
.dout(convert_dout_net_x0)
);
xldivider_generator_c21cb25008addda87fe275acdfb605e1 divide (
.ce(ce_1_net),
.clk(clk_1_net),
.a_tvalid(1'b1),
.b_tvalid(1'b1),
.a(constant_op_net_x0),
.b(motor_speed_net),
.op(divide_op_net)
);
endmodule
// Generated from Simulink block "ip_pid_controller/ip_pid_controller_struct"
module ip_pid_controller_struct (
clk_1,
ce_1,
rst,
ref_speed,
new_motor_speed,
motor_speed,
kp,
ki,
kd,
err,
pwm,
speed
);
input clk_1;
input ce_1;
input rst;
input [31:0] ref_speed;
input new_motor_speed;
input [31:0] motor_speed;
input [31:0] kp;
input [31:0] ki;
input [31:0] kd;
output [31:0] err;
output [31:0] pwm;
output [31:0] speed;
wire clk_1_net;
wire ce_1_net;
wire [31:0] addsub_s_net;
wire [31:0] convert_dout_net;
wire [31:0] convert1_dout_net;
wire [31:0] convert2_dout_net;
wire [31:0] mcode_z_net;
wire rst_net;
wire [31:0] ref_speed_net;
wire new_motor_speed_net;
wire [31:0] motor_speed_net;
wire [31:0] kp_net;
wire [31:0] ki_net;
wire [31:0] kd_net;
wire [31:0] err_net;
wire [31:0] pwm_net;
wire [31:0] speed_net;
wire logical1_y_net;
wire [31:0] addsub3_s_net;
wire [31:0] convert_dout_net_x0;
assign clk_1_net = clk_1;
assign ce_1_net = ce_1;
assign rst_net = rst;
assign ref_speed_net = ref_speed;
assign new_motor_speed_net = new_motor_speed;
assign motor_speed_net = motor_speed;
assign kp_net = kp;
assign ki_net = ki;
assign kd_net = kd;
assign err = err_net;
assign pwm = pwm_net;
assign speed = speed_net;
assign err_net = convert_dout_net;
assign pwm_net = convert1_dout_net;
assign speed_net = convert_dout_net_x0;
xladdsub_ip_pid_controller #(
.a_arith(`xlSigned),
.a_bin_pt(16),
.a_width(32),
.b_arith(`xlSigned),
.b_bin_pt(16),
.b_width(32),
.c_has_c_out(0),
.c_latency(0),
.c_output_width(33),
.core_name0("ip_pid_controller_c_addsub_v12_0_0"),
.extra_registers(0),
.full_s_arith(2),
.full_s_width(33),
.latency(0),
.overflow(1),
.quantization(1),
.s_arith(`xlSigned),
.s_bin_pt(16),
.s_width(32))
addsub (
.ce(ce_1_net),
.clk(clk_1_net),
.clr(1'b0),
.en(1'b1),
.a(convert2_dout_net),
.b(convert_dout_net_x0),
.s(addsub_s_net)
);
xlconvert_ip_pid_controller #(
.bool_conversion(0),
.din_arith(2),
.din_bin_pt(16),
.din_width(32),
.dout_arith(2),
.dout_bin_pt(0),
.dout_width(32),
.latency(0),
.overflow(`xlWrap),
.quantization(`xlTruncate))
convert (
.ce(ce_1_net),
.clk(clk_1_net),
.clr(1'b0),
.en(1'b1),
.din(addsub_s_net),
.dout(convert_dout_net)
);
xlconvert_ip_pid_controller #(
.bool_conversion(0),
.din_arith(2),
.din_bin_pt(16),
.din_width(32),
.dout_arith(2),
.dout_bin_pt(0),
.dout_width(32),
.latency(0),
.overflow(`xlWrap),
.quantization(`xlTruncate))
convert1 (
.ce(ce_1_net),
.clk(clk_1_net),
.clr(1'b0),
.en(1'b1),
.din(mcode_z_net),
.dout(convert1_dout_net)
);
xlconvert_ip_pid_controller #(
.bool_conversion(0),
.din_arith(2),
.din_bin_pt(0),
.din_width(32),
.dout_arith(2),
.dout_bin_pt(16),
.dout_width(32),
.latency(0),
.overflow(`xlWrap),
.quantization(`xlTruncate))
convert2 (
.ce(ce_1_net),
.clk(clk_1_net),
.clr(1'b0),
.en(1'b1),
.din(ref_speed_net),
.dout(convert2_dout_net)
);
sysgen_mcode_block_698c2b186c mcode (
.clk(1'b0),
.ce(1'b0),
.clr(1'b0),
.x(addsub3_s_net),
.z(mcode_z_net)
);
edge_detection_69f9d322be edge_detection (
.clk_1(clk_1_net),
.ce_1(ce_1_net),
.in1(new_motor_speed_net),
.out1(logical1_y_net)
);
pid_controller_dfc330003e pid_controller (
.clk_1(clk_1_net),
.ce_1(ce_1_net),
.en_acc(logical1_y_net),
.rst_acc(rst_net),
.kd(kd_net),
.ki(ki_net),
.kp(kp_net),
.err(addsub_s_net),
.pwm(addsub3_s_net)
);
speed_computation_8d613ce520 speed_computation (
.clk_1(clk_1_net),
.ce_1(ce_1_net),
.speed_cnt(motor_speed_net),
.speed_rpm(convert_dout_net_x0)
);
endmodule
// Generated from Simulink block "ip_pid_controller/default_clock_driver_ip_pid_controller"
module default_clock_driver_ip_pid_controller (
sysclk,
sysce,
sysce_clr,
clk_1,
ce_1
);
input sysclk;
input sysce;
input sysce_clr;
output ce_1;
output clk_1;
wire xlclockdriver_1_clk;
wire xlclockdriver_1_ce;
assign clk_1 = xlclockdriver_1_clk;
assign ce_1 = xlclockdriver_1_ce;
xlclockdriver #(
.log_2_period(1),
.period(1),
.use_bufg(0))
xlclockdriver_1 (
.sysce(sysce),
.sysclk(sysclk),
.sysclr(sysce_clr),
.ce(xlclockdriver_1_ce),
.clk(xlclockdriver_1_clk)
);
endmodule
// Generated from Simulink block "ip_pid_controller"
(* core_generation_info = "ip_pid_controller,sysgen_core_2013_4,{compilation=IP Catalog,block_icon_display=Default,family=zynq,part=xc7z020,speed=-1,package=clg484,synthesis_tool=Vivado,synthesis_language=verilog,hdl_library=work,proj_type=Vivado,synth_file=Vivado Synthesis Defaults,impl_file=Vivado Implementation Defaults,clock_loc=,clock_wrapper=Clock Enables,directory=./netlist,testbench=0,create_interface_document=0,ce_clr=0,base_system_period_hardware=10,dcm_input_clock_period=10,base_system_period_simulink=1,sim_time=1e+06,sim_status=0,}" *)
module ip_pid_controller (
clk,
rst,
ref_speed,
new_motor_speed,
motor_speed,
kp,
ki,
kd,
err,
pwm,
speed
);
input clk;
input rst;
input [31:0] ref_speed;
input new_motor_speed;
input [31:0] motor_speed;
input [31:0] kp;
input [31:0] ki;
input [31:0] kd;
output [31:0] err;
output [31:0] pwm;
output [31:0] speed;
wire clk_1_net;
wire ce_1_net;
wire clk_net;
wire rst_net;
wire [31:0] ref_speed_net;
wire new_motor_speed_net;
wire [31:0] motor_speed_net;
wire [31:0] kp_net;
wire [31:0] ki_net;
wire [31:0] kd_net;
wire [31:0] err_net;
wire [31:0] pwm_net;
wire [31:0] speed_net;
assign clk_net = clk;
assign rst_net = rst;
assign ref_speed_net = ref_speed;
assign new_motor_speed_net = new_motor_speed;
assign motor_speed_net = motor_speed;
assign kp_net = kp;
assign ki_net = ki;
assign kd_net = kd;
assign err = err_net;
assign pwm = pwm_net;
assign speed = speed_net;
ip_pid_controller_struct ip_pid_controller_struct (
.clk_1(clk_1_net),
.ce_1(ce_1_net),
.rst(rst_net),
.ref_speed(ref_speed_net),
.new_motor_speed(new_motor_speed_net),
.motor_speed(motor_speed_net),
.kp(kp_net),
.ki(ki_net),
.kd(kd_net),
.err(err_net),
.pwm(pwm_net),
.speed(speed_net)
);
default_clock_driver_ip_pid_controller default_clock_driver_ip_pid_controller (
.sysclk(clk_net),
.sysce(1'b1),
.sysce_clr(1'b0),
.clk_1(clk_1_net),
.ce_1(ce_1_net)
);
endmodule

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library/ip_pid_controller/hdl/ip_pid_controller_entity_declarations.v Executable file
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//-----------------------------------------------------------------
// System Generator version 2013.4 Verilog source file.
//
// Copyright(C) 2013 by Xilinx, Inc. All rights reserved. This
// text/file contains proprietary, confidential information of Xilinx,
// Inc., is distributed under license from Xilinx, Inc., and may be used,
// copied and/or disclosed only pursuant to the terms of a valid license
// agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
// this text/file solely for design, simulation, implementation and
// creation of design files limited to Xilinx devices or technologies.
// Use with non-Xilinx devices or technologies is expressly prohibited
// and immediately terminates your license unless covered by a separate
// agreement.
//
// Xilinx is providing this design, code, or information "as is" solely
// for use in developing programs and solutions for Xilinx devices. By
// providing this design, code, or information as one possible
// implementation of this feature, application or standard, Xilinx is
// making no representation that this implementation is free from any
// claims of infringement. You are responsible for obtaining any rights
// you may require for your implementation. Xilinx expressly disclaims
// any warranty whatsoever with respect to the adequacy of the
// implementation, including but not limited to warranties of
// merchantability or fitness for a particular purpose.
//
// Xilinx products are not intended for use in life support appliances,
// devices, or systems. Use in such applications is expressly prohibited.
//
// Any modifications that are made to the source code are done at the user's
// sole risk and will be unsupported.
//
// This copyright and support notice must be retained as part of this
// text at all times. (c) Copyright 1995-2013 Xilinx, Inc. All rights
// reserved.
//-----------------------------------------------------------------
`include "conv_pkg.v"
module xlconvert_ip_pid_controller (din, clk, ce, clr, en, dout);
//Parameter Definitions
parameter din_width= 16;
parameter din_bin_pt= 4;
parameter din_arith= `xlUnsigned;
parameter dout_width= 8;
parameter dout_bin_pt= 2;
parameter dout_arith= `xlUnsigned;
parameter en_width = 1;
parameter en_bin_pt = 0;
parameter en_arith = `xlUnsigned;
parameter bool_conversion = 0;
parameter latency = 0;
parameter quantization= `xlTruncate;
parameter overflow= `xlWrap;
//Port Declartions
input [din_width-1:0] din;
input clk, ce, clr;
input [en_width-1:0] en;
output [dout_width-1:0] dout;
//Wire Declartions
wire [dout_width-1:0] result;
wire internal_ce;
assign internal_ce = ce & en[0];
generate
if (bool_conversion == 1)
begin:bool_converion_generate
assign result = din;
end
else
begin:std_conversion
convert_type #(din_width,
din_bin_pt,
din_arith,
dout_width,
dout_bin_pt,
dout_arith,
quantization,
overflow)
conv_udp (.inp(din), .res(result));
end
endgenerate
generate
if (latency > 0)
begin:latency_test
synth_reg # (dout_width, latency)
reg1 (
.i(result),
.ce(internal_ce),
.clr(clr),
.clk(clk),
.o(dout));
end
else
begin:latency0
assign dout = result;
end
endgenerate
endmodule
module sysgen_mcode_block_698c2b186c (
input [(32 - 1):0] x,
output [(32 - 1):0] z,
input clk,
input ce,
input clr);
wire signed [(32 - 1):0] x_1_22;
localparam [(11 - 1):0] const_value = 11'b10010000000;
localparam [(11 - 1):0] const_value_x_000000 = 11'b11111111111;
localparam [(11 - 1):0] const_value_x_000001 = 11'b10010000000;
localparam signed [(32 - 1):0] const_value_x_000002 = 32'sb00000100100000000000000000000000;
wire rel_3_6;
localparam [(11 - 1):0] const_value_x_000003 = 11'b11111111111;
localparam signed [(32 - 1):0] const_value_x_000004 = 32'sb00000111111111110000000000000000;
wire rel_5_10;
reg signed [(32 - 1):0] z_join_3_3;
localparam signed [(32 - 1):0] const_value_x_000005 = 32'sb00000100100000000000000000000000;
localparam signed [(32 - 1):0] const_value_x_000006 = 32'sb00000111111111110000000000000000;
assign x_1_22 = x;
assign rel_3_6 = x_1_22 < const_value_x_000002;
assign rel_5_10 = x_1_22 > const_value_x_000004;
always @(rel_3_6 or rel_5_10 or x_1_22)
begin:proc_if_3_3
if (rel_3_6)
begin
z_join_3_3 = const_value_x_000005;
end
else if (rel_5_10)
begin
z_join_3_3 = const_value_x_000006;
end
else
begin
z_join_3_3 = x_1_22;
end
end
assign z = z_join_3_3;
endmodule
module sysgen_constant_383443dd88 (
output [(8 - 1):0] op,
input clk,
input ce,
input clr);
assign op = 8'b00000000;
endmodule
module xldelay_ip_pid_controller #(parameter width = -1, latency = -1, reg_retiming = 0, reset = 0)
(input [width-1:0] d,
input ce, clk, en, rst,
output [width-1:0] q);
generate
if ((latency == 0) || ((reg_retiming == 0) && (reset == 0)))
begin:srl_delay
synth_reg # (width, latency)
reg1 (
.i(d),
.ce(ce & en),
.clr(1'b0),
.clk(clk),
.o(q));
end
if ((latency>=1) && ((reg_retiming) || (reset)))
begin:reg_delay
synth_reg_reg # (width, latency)
reg2 (
.i(d),
.ce(ce & en),
.clr(rst),
.clk(clk),
.o(q));
end
endgenerate
endmodule
module sysgen_inverter_91fd45ca5a (
input [(1 - 1):0] ip,
output [(1 - 1):0] op,
input clk,
input ce,
input clr);
wire ip_1_26;
reg op_mem_22_20[0:(1 - 1)];
initial
begin
op_mem_22_20[0] = 1'b0;
end
wire op_mem_22_20_front_din;
wire op_mem_22_20_back;
wire op_mem_22_20_push_front_pop_back_en;
localparam [(1 - 1):0] const_value = 1'b1;
wire internal_ip_12_1_bitnot;
assign ip_1_26 = ip;
assign op_mem_22_20_back = op_mem_22_20[0];
always @(posedge clk)
begin:proc_op_mem_22_20
integer i;
if (((ce == 1'b1) && (op_mem_22_20_push_front_pop_back_en == 1'b1)))
begin
op_mem_22_20[0] <= op_mem_22_20_front_din;
end
end
assign internal_ip_12_1_bitnot = ~ip_1_26;
assign op_mem_22_20_front_din = internal_ip_12_1_bitnot;
assign op_mem_22_20_push_front_pop_back_en = 1'b1;
assign op = op_mem_22_20_back;
endmodule
module sysgen_logical_098c9fa070 (
input [(1 - 1):0] d0,
input [(1 - 1):0] d1,
output [(1 - 1):0] y,
input clk,
input ce,
input clr);
wire d0_1_24;
wire d1_1_27;
wire fully_2_1_bit;
assign d0_1_24 = d0;
assign d1_1_27 = d1;
assign fully_2_1_bit = d0_1_24 & d1_1_27;
assign y = fully_2_1_bit;
endmodule
module xlregister_ip_pid_controller (d, rst, en, ce, clk, q);
parameter d_width = 5;
parameter init_value = 'b0;
input [d_width-1:0] d;
input rst, en, ce, clk;
output [d_width-1:0] q;
wire internal_clr, internal_ce;
assign internal_clr = rst & ce;
assign internal_ce = ce & en;
synth_reg_w_init #(.width(d_width),
.init_index(2),
.init_value(init_value),
.latency(1))
synth_reg_inst(.i(d),
.ce(internal_ce),
.clr(internal_clr),
.clk(clk),
.o(q));
endmodule
module sysgen_relational_0c5dbda85b (
input [(8 - 1):0] a,
input [(8 - 1):0] b,
output [(1 - 1):0] op,
input clk,
input ce,
input clr);
wire [(8 - 1):0] a_1_31;
wire [(8 - 1):0] b_1_34;
localparam [(1 - 1):0] const_value = 1'b1;
wire result_12_3_rel;
assign a_1_31 = a;
assign b_1_34 = b;
assign result_12_3_rel = a_1_31 == b_1_34;
assign op = result_12_3_rel;
endmodule
module sysgen_constant_61a644b4c8 (
output [(32 - 1):0] op,
input clk,
input ce,
input clr);
assign op = 32'b01011111010111100001000000000000;
endmodule
module sysgen_accum_ac23432ab2 (
input [(32 - 1):0] b,
input [(1 - 1):0] rst,
input [(1 - 1):0] en,
output [(32 - 1):0] q,
input clk,
input ce,
input clr);
wire signed [(32 - 1):0] b_17_24;
wire rst_17_27;
wire en_17_32;
reg signed [(32 - 1):0] accum_reg_41_23 = 32'b00000000000000000000000000000000;
wire accum_reg_41_23_rst;
wire accum_reg_41_23_en;
localparam [(1 - 1):0] const_value = 1'b0;
localparam [(1 - 1):0] const_value_x_000000 = 1'b1;
localparam [(1 - 1):0] const_value_x_000001 = 1'b0;
localparam [(1 - 1):0] const_value_x_000002 = 1'b1;
reg signed [(33 - 1):0] accum_reg_join_47_1;
reg accum_reg_join_47_1_en;
reg accum_reg_join_47_1_rst;
assign b_17_24 = b;
assign rst_17_27 = rst;
assign en_17_32 = en;
always @(posedge clk)
begin:proc_accum_reg_41_23
if (((ce == 1'b1) && (accum_reg_41_23_rst == 1'b1)))
begin
accum_reg_41_23 <= 32'b00000000000000000000000000000000;
end
else if (((ce == 1'b1) && (accum_reg_41_23_en == 1'b1)))
begin
accum_reg_41_23 <= accum_reg_41_23 + b_17_24;
end
end
always @(accum_reg_41_23 or b_17_24 or en_17_32 or rst_17_27)
begin:proc_if_47_1
if (rst_17_27)
begin
accum_reg_join_47_1_rst = 1'b1;
end
else if (en_17_32)
begin
accum_reg_join_47_1_rst = 1'b0;
end
else
begin
accum_reg_join_47_1_rst = 1'b0;
end
if (en_17_32)
begin
accum_reg_join_47_1_en = 1'b1;
end
else
begin
accum_reg_join_47_1_en = 1'b0;
end
end
assign accum_reg_41_23_rst = accum_reg_join_47_1_rst;
assign accum_reg_41_23_en = accum_reg_join_47_1_en;
assign q = accum_reg_41_23;
endmodule
module sysgen_constant_b4741603e8 (
output [(32 - 1):0] op,
input clk,
input ce,
input clr);
assign op = 32'b00000111111111110000000000000000;
endmodule
module sysgen_constant_a7c2a996dd (
output [(32 - 1):0] op,
input clk,
input ce,
input clr);
assign op = 32'b00000000000000000000000000000000;
endmodule
module sysgen_constant_bd840882a6 (
output [(32 - 1):0] op,
input clk,
input ce,
input clr);
assign op = 32'b00000100100000000000000000000000;
endmodule
module sysgen_logical_0c47d61908 (
input [(1 - 1):0] d0,
input [(1 - 1):0] d1,
output [(1 - 1):0] y,
input clk,
input ce,
input clr);
wire d0_1_24;
wire d1_1_27;
wire bit_2_27;
wire fully_2_1_bitnot;
assign d0_1_24 = d0;
assign d1_1_27 = d1;
assign bit_2_27 = d0_1_24 & d1_1_27;
assign fully_2_1_bitnot = ~bit_2_27;
assign y = fully_2_1_bitnot;
endmodule
module sysgen_logical_7913ccf482 (
input [(1 - 1):0] d0,
input [(1 - 1):0] d1,
input [(1 - 1):0] d2,
output [(1 - 1):0] y,
input clk,
input ce,
input clr);
wire d0_1_24;
wire d1_1_27;
wire d2_1_30;
wire fully_2_1_bit;
assign d0_1_24 = d0;
assign d1_1_27 = d1;
assign d2_1_30 = d2;
assign fully_2_1_bit = d0_1_24 & d1_1_27 & d2_1_30;
assign y = fully_2_1_bit;
endmodule
module sysgen_relational_56046aa836 (
input [(32 - 1):0] a,
input [(32 - 1):0] b,
output [(1 - 1):0] op,
input clk,
input ce,
input clr);
wire signed [(32 - 1):0] a_1_31;
wire signed [(32 - 1):0] b_1_34;
localparam [(1 - 1):0] const_value = 1'b1;
wire result_18_3_rel;
assign a_1_31 = a;
assign b_1_34 = b;
assign result_18_3_rel = a_1_31 > b_1_34;
assign op = result_18_3_rel;
endmodule
module sysgen_relational_860373682b (
input [(32 - 1):0] a,
input [(32 - 1):0] b,
output [(1 - 1):0] op,
input clk,
input ce,
input clr);
wire signed [(32 - 1):0] a_1_31;
wire signed [(32 - 1):0] b_1_34;
localparam [(1 - 1):0] const_value = 1'b1;
wire result_16_3_rel;
assign a_1_31 = a;
assign b_1_34 = b;
assign result_16_3_rel = a_1_31 < b_1_34;
assign op = result_16_3_rel;
endmodule
module xladdsub_ip_pid_controller (a, b, c_in, ce, clr, clk, rst, en, c_out, s);
parameter core_name0= "";
parameter a_width= 16;
parameter signed a_bin_pt= 4;
parameter a_arith= `xlUnsigned;
parameter c_in_width= 16;
parameter c_in_bin_pt= 4;
parameter c_in_arith= `xlUnsigned;
parameter c_out_width= 16;
parameter c_out_bin_pt= 4;
parameter c_out_arith= `xlUnsigned;
parameter b_width= 8;
parameter signed b_bin_pt= 2;
parameter b_arith= `xlUnsigned;
parameter s_width= 17;
parameter s_bin_pt= 4;
parameter s_arith= `xlUnsigned;
parameter rst_width= 1;
parameter rst_bin_pt= 0;
parameter rst_arith= `xlUnsigned;
parameter en_width= 1;
parameter en_bin_pt= 0;
parameter en_arith= `xlUnsigned;
parameter full_s_width= 17;
parameter full_s_arith= `xlUnsigned;
parameter mode= `xlAddMode;
parameter extra_registers= 0;
parameter latency= 0;
parameter quantization= `xlTruncate;
parameter overflow= `xlWrap;
parameter c_a_width= 16;
parameter c_b_width= 8;
parameter c_a_type= 1;
parameter c_b_type= 1;
parameter c_has_sclr= 0;
parameter c_has_ce= 0;
parameter c_latency= 0;
parameter c_output_width= 17;
parameter c_enable_rlocs= 1;
parameter c_has_c_in= 0;
parameter c_has_c_out= 0;
input [a_width-1:0] a;
input [b_width-1:0] b;
input c_in, ce, clr, clk, rst, en;
output c_out;
output [s_width-1:0] s;
parameter full_a_width = full_s_width;
parameter full_b_width = full_s_width;
parameter full_s_bin_pt = (a_bin_pt > b_bin_pt) ? a_bin_pt : b_bin_pt;
wire [full_a_width-1:0] full_a;
wire [full_b_width-1:0] full_b;
wire [full_s_width-1:0] full_s;
wire [full_s_width-1:0] core_s;
wire [s_width-1:0] conv_s;
wire temp_cout;
wire real_a,real_b,real_s;
wire internal_clr;
wire internal_ce;
wire extra_reg_ce;
wire override;
wire logic1;
wire temp_cin;
assign internal_clr = (clr | rst) & ce;
assign internal_ce = ce & en;
assign logic1 = 1'b1;
assign temp_cin = (c_has_c_in) ? c_in : 1'b0;
align_input # (a_width, b_bin_pt - a_bin_pt, a_arith, full_a_width)
align_inp_a(.inp(a),.res(full_a));
align_input # (b_width, a_bin_pt - b_bin_pt, b_arith, full_b_width)
align_inp_b(.inp(b),.res(full_b));
convert_type # (full_s_width, full_s_bin_pt, full_s_arith, s_width,
s_bin_pt, s_arith, quantization, overflow)
conv_typ_s(.inp(core_s),.res(conv_s));
generate
if (core_name0 == "ip_pid_controller_c_addsub_v12_0_0")
begin:comp0
ip_pid_controller_c_addsub_v12_0_0 core_instance0 (
.A(full_a),
.S(core_s),
.B(full_b)
);
end
if (core_name0 == "ip_pid_controller_c_addsub_v12_0_1")
begin:comp1
ip_pid_controller_c_addsub_v12_0_1 core_instance1 (
.A(full_a),
.S(core_s),
.B(full_b)
);
end
endgenerate
generate
if (extra_registers > 0)
begin:latency_test
if (c_latency > 1)
begin:override_test
synth_reg # (1, c_latency)
override_pipe (
.i(logic1),
.ce(internal_ce),
.clr(internal_clr),
.clk(clk),
.o(override));
assign extra_reg_ce = ce & en & override;
end // override_test
if ((c_latency == 0) || (c_latency == 1))
begin:no_override
assign extra_reg_ce = ce & en;
end // no_override
synth_reg # (s_width, extra_registers)
extra_reg (
.i(conv_s),
.ce(extra_reg_ce),
.clr(internal_clr),
.clk(clk),
.o(s));
if (c_has_c_out == 1)
begin:cout_test
synth_reg # (1, extra_registers)
c_out_extra_reg (
.i(temp_cout),
.ce(extra_reg_ce),
.clr(internal_clr),
.clk(clk),
.o(c_out));
end // cout_test
end // latency_test
endgenerate
generate
if ((latency == 0) || (extra_registers == 0))
begin:latency_s
assign s = conv_s;
end // latency_s
endgenerate
generate
if (((latency == 0) || (extra_registers == 0)) &&
(c_has_c_out == 1))
begin:latency0
assign c_out = temp_cout;
end // latency0
endgenerate
generate
if (c_has_c_out == 0)
begin:tie_dangling_cout
assign c_out = 0;
end // tie_dangling_cout
endgenerate
endmodule
module xlcounter_limit_ip_pid_controller (ce, clr, clk, op, up, en, rst);
parameter core_name0= "";
parameter op_width= 5;
parameter op_arith= `xlSigned;
parameter cnt_63_48 = 0;
parameter cnt_47_32 = 0;
parameter cnt_31_16 = 0;
parameter cnt_15_0 = 0;
parameter count_limited= 0;
input ce, clr, clk;
input rst, en;
input up;
output [op_width-1:0] op;
parameter [63:0] cnt_to = { cnt_63_48[15:0], cnt_47_32[15:0], cnt_31_16[15:0], cnt_15_0[15:0]};
parameter [(8*op_width)-1:0] oneStr = { op_width{"1"}};
reg op_thresh0;
wire core_sinit, core_ce;
wire rst_overrides_en;
wire [op_width-1:0] op_net;
assign op = op_net;
assign core_ce = ce & en;
assign rst_overrides_en = rst | en;
generate
if (count_limited == 1)
begin :limit
always @(op_net)
begin:eq_cnt_to
op_thresh0 = (op_net == cnt_to[op_width-1:0])? 1'b1 : 1'b0;
end
assign core_sinit = (op_thresh0 | clr | rst) & ce & rst_overrides_en;
end
if (count_limited == 0)
begin :no_limit
assign core_sinit = (clr | rst) & ce & rst_overrides_en;
end
if (core_name0 == "ip_pid_controller_c_counter_binary_v12_0_0")
begin:comp0
ip_pid_controller_c_counter_binary_v12_0_0 core_instance0 (
.CLK(clk),
.CE(core_ce),
.SINIT(core_sinit),
.Q(op_net)
);
end
endgenerate
endmodule
module xldivider_generator_c21cb25008addda87fe275acdfb605e1 (a,a_tvalid,b,b_tvalid,ce,clk,op);
input[31:0] a;
input a_tvalid;
input[31:0] b;
input b_tvalid;
input ce;
input clk;
output[37:0] op;
wire[39:0] m_axis_dout_tdata_net;
wire[37:0] m_axis_dout_tdata_shift_in_net;
wire[37:0] m_axis_dout_tdata_shift_out_net;
wire result_tvalid;
wire[31:0] s_axis_dividend_tdata_net;
wire[31:0] s_axis_divisor_tdata_net;
assign m_axis_dout_tdata_shift_in_net = m_axis_dout_tdata_net[37 : 0];
assign op = m_axis_dout_tdata_shift_out_net;
assign s_axis_dividend_tdata_net[31 : 0] = a;
assign s_axis_divisor_tdata_net[31 : 0] = b;
shift_op # ( .inp_width(38), .result_width(38), .shift_value(6), .shift_dir(0))
shift_op_m_axis_dout_tdata_shift_in_net(.inp(m_axis_dout_tdata_shift_in_net), .res(m_axis_dout_tdata_shift_out_net));
ip_pid_controller_div_gen_v5_1_0 ip_pid_controller_div_gen_v5_1_0_instance(
.aclk(clk),
.m_axis_dout_tdata(m_axis_dout_tdata_net),
.m_axis_dout_tvalid(result_tvalid),
.s_axis_dividend_tdata(s_axis_dividend_tdata_net),
.s_axis_dividend_tvalid(a_tvalid),
.s_axis_divisor_tdata(s_axis_divisor_tdata_net),
.s_axis_divisor_tvalid(b_tvalid)
);
endmodule
module xlmult_ip_pid_controller (a, b, ce, clr, clk, core_ce, core_clr,core_clk, rst, en,p);
parameter core_name0 = "";
parameter a_width = 4;
parameter a_bin_pt = 2;
parameter a_arith = `xlSigned;
parameter b_width = 4;
parameter b_bin_pt = 1;
parameter b_arith = `xlSigned;
parameter p_width = 8;
parameter p_bin_pt = 2;
parameter p_arith = `xlSigned;
parameter rst_width = 1;
parameter rst_bin_pt = 0;
parameter rst_arith = `xlUnsigned;
parameter en_width = 1;
parameter en_bin_pt = 0;
parameter en_arith = `xlUnsigned;
parameter quantization = `xlTruncate;
parameter overflow = `xlWrap;
parameter extra_registers = 0;
parameter c_a_width = 7;
parameter c_b_width = 7;
parameter c_type = 0;
parameter c_a_type = 0;
parameter c_b_type = 0;
parameter c_baat = 4;
parameter oversample = 1;
parameter multsign = `xlSigned;
parameter c_output_width = 16;
input [a_width - 1 : 0] a;
input [b_width - 1 : 0] b;
input ce, clr, clk;
input core_ce, core_clr, core_clk;
input en, rst;
output [p_width - 1 : 0] p;
wire [c_a_width - 1 : 0] tmp_a, conv_a;
wire [c_b_width - 1 : 0] tmp_b, conv_b;
wire [c_output_width - 1 : 0] tmp_p;
wire [p_width - 1 : 0] conv_p;
wire internal_ce, internal_clr, internal_core_ce;
wire rfd, rdy, nd;
assign internal_ce = ce & en;
assign internal_core_ce = core_ce & en;
assign internal_clr = (clr | rst) & en;
assign nd = ce & en;
zero_ext # (a_width, c_a_width) zero_ext_a (.inp(a), .res(tmp_a));
zero_ext # (b_width, c_b_width) zero_ext_b (.inp(b), .res(tmp_b));
//Output Process
convert_type # (c_output_width, a_bin_pt+b_bin_pt, multsign,
p_width, p_bin_pt, p_arith, quantization, overflow)
conv_udp (.inp(tmp_p), .res(conv_p));
generate
if (core_name0 == "ip_pid_controller_mult_gen_v12_0_0")
begin:comp0
ip_pid_controller_mult_gen_v12_0_0 core_instance0 (
.A(tmp_a),
.B(tmp_b),
.CLK(clk),
.CE(internal_ce),
.SCLR(internal_clr),
.P(tmp_p)
);
end
if (extra_registers > 0)
begin:latency_gt_0
synth_reg # (p_width, extra_registers)
reg1 (
.i(conv_p),
.ce(internal_ce),
.clr(internal_clr),
.clk(clk),
.o(p));
end
if (extra_registers == 0)
begin:latency_eq_0
assign p = conv_p;
end
endgenerate
endmodule

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//-----------------------------------------------------------------
//
// Filename : synth_reg.v
//
// Date : 4/19/2005
//
// Description : Verilog description of SRL16E based delay and
// retiming register module.
// This code is synthesizable.
//
//
// Mod. History : Translated VHDL code to Verilog
// : Fixed synth_reg_reg
//
// Mod. Dates : 6/29/2004
// : 12/14/2004
//
//-------------------------------------------------------------------
`timescale 1 ns / 10 ps
module srl17e (clk, ce, d, q);
parameter width = 16;
parameter latency = 8;
input clk, ce;
input [width-1:0] d;
output [width-1:0] q;
parameter signed [5:0] a = latency - 2;
wire[width - 1:0] #0.2 d_delayed;
wire[width - 1:0] srl16_out;
genvar i;
assign d_delayed = d ;
generate
for(i=0; i<width; i=i+1)
begin:reg_array
if (latency > 1)
begin: has_2_latency
SRL16E u1 (.CLK(clk), .D(d_delayed[i]), .Q(srl16_out[i]), .CE(ce), .A0(a[0]), .A1(a[1]), .A2(a[2]), .A3(a[3]));
end
if (latency <= 1)
begin: has_1_latency
assign srl16_out[i] = d_delayed[i];
end
if (latency != 0)
begin: has_latency
FDE u2 (.C(clk), .D(srl16_out[i]), .Q(q[i]), .CE(ce));
end
if (latency == 0)
begin:has_0_latency
assign q[i] = srl16_out[i];
end
end
endgenerate
endmodule
module synth_reg (i, ce, clr, clk, o);
parameter width = 8;
parameter latency = 1;
input[width - 1:0] i;
input ce,clr,clk;
output[width - 1:0] o;
parameter complete_num_srl17es = latency/17;
parameter remaining_latency = latency%17;
parameter temp_num_srl17es = (latency/17) + ((latency%17)?1:0);
parameter num_srl17es = temp_num_srl17es ? temp_num_srl17es : 1;
wire [width - 1:0] z [0:num_srl17es-1];
genvar t;
generate
if (latency <= 17)
begin:has_only_1
srl17e #(width, latency) srl17e_array0(.clk(clk), .ce(ce), .d(i), .q(o));
end
endgenerate
generate
if (latency > 17)
begin:has_1
assign o = z[num_srl17es-1];
srl17e #(width, 17) srl17e_array0(.clk(clk), .ce(ce), .d(i), .q(z[0]));
end
endgenerate
generate
if (latency > 17)
begin:more_than_1
for (t=1; t < complete_num_srl17es; t=t+1)
begin:left_complete_ones
srl17e #(width, 17) srl17e_array(.clk(clk), .ce(ce), .d(z[t-1]), .q(z[t]));
end
end
endgenerate
generate
if ((remaining_latency > 0) && (latency>17))
begin:remaining_ones
srl17e #(width, (latency%17)) last_srl17e (.clk(clk), .ce(ce), .d(z[num_srl17es-2]), .q(z[num_srl17es-1]));
end
endgenerate
endmodule
module synth_reg_reg (i, ce, clr, clk, o);
parameter width = 8;
parameter latency = 1;
input[width - 1:0] i;
input ce, clr, clk;
output[width - 1:0] o;
wire[width - 1:0] o;
genvar idx;
reg[width - 1:0] reg_bank [latency:0];
integer j;
initial
begin
for (j=0; j < latency+1; j=j+1)
begin
reg_bank[j] = {width{1'b0}};
end
end
generate
if (latency == 0)
begin:has_0_latency
assign o = i;
end
endgenerate
always @(i)
begin
reg_bank[0] = i;
end
generate
if (latency > 0)
begin:more_than_1
assign o = reg_bank[latency];
for (idx=0; idx < latency; idx=idx+1) begin:sync_loop
always @(posedge clk)
begin
if(clr)
begin
//for (j=0; j < latency+1; j=j+1)
// begin
reg_bank[idx+1] = {width{1'b0}};
// end
end
else if (ce)
begin
reg_bank[idx+1] <= reg_bank[idx] ;
end
end
end
end
endgenerate
endmodule

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library/ip_pid_controller/hdl/synth_reg_w_init.v Executable file
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`timescale 1 ns / 10 ps
module synth_reg_w_init (i, ce, clr, clk, o);
parameter width = 8;
parameter init_index = 0;
parameter [width-1 : 0] init_value = 'b0000;
parameter latency = 1;
input[width - 1:0] i;
input ce, clr, clk;
output[width - 1:0] o;
wire[(latency + 1) * width - 1:0] dly_i;
wire #0.2 dly_clr;
genvar index;
generate
if (latency == 0)
begin:has_0_latency
assign o = i;
end
else
begin:has_latency
assign dly_i[(latency + 1) * width - 1:latency * width] = i ;
assign dly_clr = clr ;
for (index=1; index<=latency; index=index+1)
begin:fd_array
// synopsys translate_off
defparam reg_comp_1.width = width;
defparam reg_comp_1.init_index = init_index;
defparam reg_comp_1.init_value = init_value;
// synopsys translate_on
single_reg_w_init #(width, init_index, init_value)
reg_comp_1(.clk(clk),
.i(dly_i[(index + 1)*width-1:index*width]),
.o(dly_i[index * width - 1:(index - 1) * width]),
.ce(ce),
.clr(dly_clr));
end
assign o = dly_i[width-1:0];
end
endgenerate
endmodule
module single_reg_w_init (i, ce, clr, clk, o);
parameter width = 8;
parameter init_index = 0;
parameter [width-1 : 0] init_value = 8'b00000000;
input[width - 1:0] i;
input ce;
input clr;
input clk;
output[width - 1:0] o;
parameter [0:0] init_index_val = (init_index == 1) ? 1'b1 : 1'b0;
parameter [width-1:0] result = (width > 1) ? { {(width-1){1'b0}}, init_index_val } : init_index_val;
parameter [width-1:0] init_const = (init_index > 1) ? init_value : result;
wire[width - 1:0] o;
genvar index;
generate
for (index=0;index < width; index=index+1) begin:fd_prim_array
if (init_const[index] == 0)
begin:rst_comp
FDRE fdre_comp(.C(clk),
.D(i[index]),
.Q(o[index]),
.CE(ce),
.R(clr));
end
else
begin:set_comp
FDSE fdse_comp(.C(clk),
.D(i[index]),
.Q(o[index]),
.CE(ce),
.S(clr));
end
end
endgenerate
endmodule

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library/ip_pid_controller/hdl/xlclockdriver_rd.v Executable file
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//-----------------------------------------------------------------
//
// Filename : xlclockdriver.v
//
// Date : 6/29/2004
//
// Description : Verilog description of a clock enable generator block.
// This code is synthesizable.
//
// Assumptions : period >= 1
//
// Mod. History : Translated VHDL clockdriver to Verilog
// : Added pipeline registers
//
// Mod. Dates : 6/29/2004
// : 12/14/2004
//
//-------------------------------------------------------------------
`timescale 1 ns / 10 ps
module xlclockdriver (sysclk, sysclr, sysce, clk, clr, ce, ce_logic);
parameter signed [31:0] log_2_period = 1;
parameter signed [31:0] period = 2;
parameter signed [31:0] use_bufg = 1'b0;
parameter signed [31:0] pipeline_regs = 5;
input sysclk;
input sysclr;
input sysce;
output clk;
output clr;
output ce;
output ce_logic;
//A maximum value of 8 would allow register balancing to the tune of 10^8
//It is set to 8 since we do not have more than 10^8 nets in an FPGA
parameter signed [31:0] max_pipeline_regs = 8;
//Check if requested pipeline regs are greater than the max amount
parameter signed [31:0] num_pipeline_regs = (max_pipeline_regs > pipeline_regs)? pipeline_regs : max_pipeline_regs;
parameter signed [31:0] factor = num_pipeline_regs/period;
parameter signed [31:0] rem_pipeline_regs = num_pipeline_regs - (period * factor) + 1;
//Old constant values
parameter [log_2_period-1:0] trunc_period = ~period + 1;
parameter signed [31:0] period_floor = (period>2)? period : 2;
parameter signed [31:0] power_of_2_counter = (trunc_period == period) ? 1 : 0;
parameter signed [31:0] cnt_width = (power_of_2_counter & (log_2_period>1)) ? (log_2_period - 1) : log_2_period;
parameter [cnt_width-1:0] clk_for_ce_pulse_minus1 = period_floor-2;
parameter [cnt_width-1:0] clk_for_ce_pulse_minus2 = (period-3>0)? period-3 : 0;
parameter [cnt_width-1:0] clk_for_ce_pulse_minus_regs = ((period-rem_pipeline_regs)>0)? (period-rem_pipeline_regs) : 0;
reg [cnt_width-1:0] clk_num;
reg temp_ce_vec;
wire [num_pipeline_regs:0] ce_vec;
wire [num_pipeline_regs:0] ce_vec_logic;
wire internal_ce;
wire internal_ce_logic;
reg cnt_clr;
wire cnt_clr_dly;
genvar index;
initial
begin
clk_num = 'b0;
end
assign clk = sysclk ;
assign clr = sysclr ;
// Clock Number Counter
always @(posedge sysclk)
begin : cntr_gen
if (sysce == 1'b1)
begin:hc
if ((cnt_clr_dly == 1'b1) || (sysclr == 1'b1))
begin:u1
clk_num = {cnt_width{1'b0}};
end
else
begin:u2
clk_num = clk_num + 1 ;
end
end
end
// Clear logic for counter
generate
if (power_of_2_counter == 1)
begin:clr_gen_p2
always @(sysclr)
begin:u1
cnt_clr = sysclr;
end
end
endgenerate
generate
if (power_of_2_counter == 0)
begin:clr_gen
always @(clk_num or sysclr)
begin:u1
if ( (clk_num == clk_for_ce_pulse_minus1) | (sysclr == 1'b1) )
begin:u2
cnt_clr = 1'b1 ;
end
else
begin:u3
cnt_clr = 1'b0 ;
end
end
end // block: clr_gen
endgenerate
synth_reg_w_init #(1, 0, 'b0000, 1)
clr_reg(.i(cnt_clr),
.ce(sysce),
.clr(sysclr),
.clk(sysclk),
.o(cnt_clr_dly));
//Clock Enable Generation
generate
if (period > 1)
begin:pipelined_ce
always @(clk_num)
begin:np_ce_gen
if (clk_num == clk_for_ce_pulse_minus_regs)
begin
temp_ce_vec = 1'b1 ;
end
else
begin
temp_ce_vec = 1'b0 ;
end
end
for(index=0; index<num_pipeline_regs; index=index+1)
begin:ce_pipeline
synth_reg_w_init #(1, ((((index+1)%period)>0)?0:1), 1'b0, 1)
ce_reg(.i(ce_vec[index+1]),
.ce(sysce),
.clr(sysclr),
.clk(sysclk),
.o(ce_vec[index]));
end //block ce_pipeline
for(index=0; index<num_pipeline_regs; index=index+1)
begin:ce_pipeline_logic
synth_reg_w_init #(1, ((((index+1)%period)>0)?0:1), 1'b0, 1)
ce_reg_logic(.i(ce_vec_logic[index+1]),
.ce(sysce),
.clr(sysclr),
.clk(sysclk),
.o(ce_vec_logic[index]));
end //block ce_pipeline
assign ce_vec_logic[num_pipeline_regs] = temp_ce_vec;
assign ce_vec[num_pipeline_regs] = temp_ce_vec;
assign internal_ce = ce_vec[0];
assign internal_ce_logic = ce_vec_logic[0];
end // block: pipelined_ce
endgenerate
generate
if (period > 1)
begin:period_greater_than_1
if (use_bufg == 1'b1)
begin:use_bufg
BUFG ce_bufg_inst(.I(internal_ce), .O(ce));
BUFG ce_logic_bufg_inst(.I(internal_ce_logic), .O(ce_logic));
end
else
begin:no_bufg
assign ce = internal_ce;
assign ce_logic = internal_ce_logic;
end
end
endgenerate
generate
if (period == 1)
begin:period_1
assign ce = sysce;
assign ce_logic = sysce;
end
endgenerate
endmodule

84
library/ip_pid_controller/ip_pid_controller_c_addsub_v12_0_0/ip_pid_controller_c_addsub_v12_0_0.xci Executable file
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<?xml version="1.0" encoding="UTF-8"?>
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<spirit:vendor>xilinx.com</spirit:vendor>
<spirit:library>xci</spirit:library>
<spirit:name>unknown</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:componentInstances>
<spirit:componentInstance>
<spirit:instanceName>ip_pid_controller_c_addsub_v12_0_0</spirit:instanceName>
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="c_addsub" spirit:version="12.0"/>
<spirit:configurableElementValues>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">ip_pid_controller_c_addsub_v12_0_0</spirit:configurableElementValue>
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84
library/ip_pid_controller/ip_pid_controller_c_addsub_v12_0_1/ip_pid_controller_c_addsub_v12_0_1.xci Executable file
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77
library/ip_pid_controller/ip_pid_controller_c_counter_binary_v12_0_0/ip_pid_controller_c_counter_binary_v12_0_0.xci Executable file
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79
library/ip_pid_controller/ip_pid_controller_div_gen_v5_1_0/ip_pid_controller_div_gen_v5_1_0.xci Executable file
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73
library/ip_pid_controller/ip_pid_controller_mult_gen_v12_0_0/ip_pid_controller_mult_gen_v12_0_0.xci Executable file
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@ -0,0 +1,73 @@
<?xml version="1.0" encoding="UTF-8"?>
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<spirit:vendor>xilinx.com</spirit:vendor>
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<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="mult_gen" spirit:version="12.0"/>
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BIN
library/ip_pid_controller/sysgen_icon_100.png Executable file
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11
library/ip_pid_controller/xgui/ip_pid_controller_v1_0.tcl Executable file
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@ -0,0 +1,11 @@
#Definitional proc to organize widgets for parameters.
proc init_gui { IPINST } {
set Page0 [ ipgui::add_page $IPINST -name "Page 0" -layout vertical]
set canvas_spec [ipgui::get_canvasspec -of $IPINST]
set_property ip_logo "sysgen_icon_100.png" $canvas_spec
set iconfile [ipgui::find_file [ipgui::get_coredir] "sysgen_icon_100.png"]
set image [ipgui::add_image -width 100 -height 100 -parent $Page0 -name $iconfile $IPINST]
set_property load_image $iconfile $image
set Component_Name [ ipgui::add_param $IPINST -parent $Page0 -name Component_Name ]
}

157
projects/motor_control/common/motor_control_bd.tcl
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@ -66,7 +66,6 @@
set_property -dict [list CONFIG.C_DMA_TYPE_DEST {0}] $axi_current_monitor_1_dma
set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_current_monitor_1_dma
set_property -dict [list CONFIG.C_CYCLIC {0}] $axi_current_monitor_1_dma
# set_property -dict [list CONFIG.C_ADDR_ALIGN_BITS {3}] $axi_current_monitor_1_dma
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $axi_current_monitor_1_dma
set_property -dict [list CONFIG.C_SYNC_TRANSFER_START {1}] $axi_current_monitor_1_dma
@ -79,7 +78,6 @@
set_property -dict [list CONFIG.C_DMA_TYPE_DEST {0}] $axi_current_monitor_2_dma
set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_current_monitor_2_dma
set_property -dict [list CONFIG.C_CYCLIC {0}] $axi_current_monitor_2_dma
# set_property -dict [list CONFIG.C_ADDR_ALIGN_BITS {3}] $axi_current_monitor_2_dma
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $axi_current_monitor_2_dma
set_property -dict [list CONFIG.C_SYNC_TRANSFER_START {1}] $axi_current_monitor_2_dma
@ -92,22 +90,22 @@
set_property -dict [list CONFIG.C_DMA_TYPE_DEST {0}] $axi_speed_detector_dma
set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_speed_detector_dma
set_property -dict [list CONFIG.C_CYCLIC {0}] $axi_speed_detector_dma
# set_property -dict [list CONFIG.C_ADDR_ALIGN_BITS {2}] $axi_speed_detector_dma
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $axi_speed_detector_dma
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {32}] $axi_speed_detector_dma
# torque controller
# controller
set axi_mc_torque_controller [ create_bd_cell -type ip -vlnv analog.com:user:axi_mc_torque_ctrl:1.0 axi_mc_torque_controller ]
set axi_mc_controller [ create_bd_cell -type ip -vlnv analog.com:user:axi_mc_controller:1.0 axi_mc_controller ]
set axi_torque_controller_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_torque_controller_dma]
set_property -dict [list CONFIG.C_DMA_TYPE_SRC {2}] $axi_torque_controller_dma
set_property -dict [list CONFIG.C_DMA_TYPE_DEST {0}] $axi_torque_controller_dma
set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_torque_controller_dma
set_property -dict [list CONFIG.C_CYCLIC {0}] $axi_torque_controller_dma
# set_property -dict [list CONFIG.C_ADDR_ALIGN_BITS {2}] $axi_torque_controller_dma
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $axi_torque_controller_dma
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {32}] $axi_torque_controller_dma
set pid_controller [create_bd_cell -type ip -vlnv analog.com:user:ip_pid_controller:1.0 pid_controller]
set axi_controller_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_controller_dma]
set_property -dict [list CONFIG.C_DMA_TYPE_SRC {2}] $axi_controller_dma
set_property -dict [list CONFIG.C_DMA_TYPE_DEST {0}] $axi_controller_dma
set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_controller_dma
set_property -dict [list CONFIG.C_CYCLIC {0}] $axi_controller_dma
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $axi_controller_dma
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {32}] $axi_controller_dma
# xadc
@ -147,15 +145,11 @@
connect_bd_net -net axi_mc_current_monitor_1_adc_it_clk_o [get_bd_ports adc_it_clk_o] [get_bd_pins axi_mc_current_monitor_1/adc_it_clk_o]
connect_bd_net -net axi_mc_current_monitor_1_adc_vbus_clk_o [get_bd_ports adc_vbus_clk_o] [get_bd_pins axi_mc_current_monitor_1/adc_vbus_clk_o]
connect_bd_net -net axi_mc_current_monitor_1_adc_clk [get_bd_pins axi_mc_current_monitor_1/adc_clk_o] [get_bd_pins axi_current_monitor_1_dma/fifo_wr_clk]
connect_bd_net -net axi_mc_current_monitor_1_adc_dwr [get_bd_pins axi_mc_current_monitor_1/adc_dwr_o] [get_bd_pins axi_current_monitor_1_dma/fifo_wr_en]
connect_bd_net -net axi_mc_current_monitor_1_adc_ddata [get_bd_pins axi_mc_current_monitor_1/adc_ddata_o] [get_bd_pins axi_current_monitor_1_dma/fifo_wr_din]
connect_bd_net -net axi_mc_current_monitor_1_adc_dsync [get_bd_pins axi_mc_current_monitor_1/adc_dsync_o] [get_bd_pins axi_current_monitor_1_dma/fifo_wr_sync]
connect_bd_net -net axi_mc_current_monitor_1_adc_mon_data [get_bd_pins axi_mc_current_monitor_1/adc_mon_data]
#connect_bd_net -net axi_mc_current_monitor_1_adc_dovf [get_bd_pins axi_mc_current_monitor_1/adc_dovf_i]
#connect_bd_net -net axi_mc_current_monitor_1_adc_dunf [get_bd_pins axi_mc_current_monitor_1/adc_dunf_i]
connect_bd_net [get_bd_pins axi_mc_current_monitor_1/i_ready_o] [get_bd_pins axi_mc_torque_controller/i_ready_i]
connect_bd_net -net axi_mc_current_monitor_1_adc_clk [get_bd_pins axi_mc_current_monitor_1/adc_clk_o] [get_bd_pins axi_current_monitor_1_dma/fifo_wr_clk]
connect_bd_net -net axi_mc_current_monitor_1_adc_dwr [get_bd_pins axi_mc_current_monitor_1/adc_dwr_o] [get_bd_pins axi_current_monitor_1_dma/fifo_wr_en]
connect_bd_net -net axi_mc_current_monitor_1_adc_ddata [get_bd_pins axi_mc_current_monitor_1/adc_ddata_o] [get_bd_pins axi_current_monitor_1_dma/fifo_wr_din]
connect_bd_net -net axi_mc_current_monitor_1_adc_dsync [get_bd_pins axi_mc_current_monitor_1/adc_dsync_o] [get_bd_pins axi_current_monitor_1_dma/fifo_wr_sync]
connect_bd_net -net axi_mc_current_monitor_1_adc_dovf [get_bd_pins axi_mc_current_monitor_1/adc_dovf_i] [get_bd_pins axi_current_monitor_1_dma/fifo_wr_overflow]
# interrupt
@ -172,12 +166,11 @@
connect_bd_net -net adc_it_dat_d_i [get_bd_ports adc_it_dat_d_i] [get_bd_pins axi_mc_current_monitor_2/adc_it_dat_i]
connect_bd_net -net axi_mc_current_monitor_2_adc_it_clk_o [get_bd_ports adc_it_clk_d_o] [get_bd_pins axi_mc_current_monitor_2/adc_it_clk_o]
connect_bd_net -net axi_mc_current_monitor_2_adc_clk [get_bd_pins axi_mc_current_monitor_2/adc_clk_o] [get_bd_pins axi_current_monitor_2_dma/fifo_wr_clk]
connect_bd_net -net axi_mc_current_monitor_2_adc_dwr [get_bd_pins axi_mc_current_monitor_2/adc_dwr_o] [get_bd_pins axi_current_monitor_2_dma/fifo_wr_en]
connect_bd_net -net axi_mc_current_monitor_2_adc_ddata [get_bd_pins axi_mc_current_monitor_2/adc_ddata_o] [get_bd_pins axi_current_monitor_2_dma/fifo_wr_din]
connect_bd_net -net axi_mc_current_monitor_2_adc_dsync [get_bd_pins axi_mc_current_monitor_2/adc_dsync_o] [get_bd_pins axi_current_monitor_2_dma/fifo_wr_sync]
#connect_bd_net -net axi_mc_current_monitor_2_adc_dovf [get_bd_pins axi_mc_current_monitor_2/adc_dovf_i]
#connect_bd_net -net axi_mc_current_monitor_2_adc_dunf [get_bd_pins axi_mc_current_monitor_2/adc_dunf_i]
connect_bd_net -net axi_mc_current_monitor_2_adc_clk [get_bd_pins axi_mc_current_monitor_2/adc_clk_o] [get_bd_pins axi_current_monitor_2_dma/fifo_wr_clk]
connect_bd_net -net axi_mc_current_monitor_2_adc_dwr [get_bd_pins axi_mc_current_monitor_2/adc_dwr_o] [get_bd_pins axi_current_monitor_2_dma/fifo_wr_en]
connect_bd_net -net axi_mc_current_monitor_2_adc_ddata [get_bd_pins axi_mc_current_monitor_2/adc_ddata_o] [get_bd_pins axi_current_monitor_2_dma/fifo_wr_din]
connect_bd_net -net axi_mc_current_monitor_2_adc_dsync [get_bd_pins axi_mc_current_monitor_2/adc_dsync_o] [get_bd_pins axi_current_monitor_2_dma/fifo_wr_sync]
connect_bd_net -net axi_mc_current_monitor_2_adc_dovf [get_bd_pins axi_mc_current_monitor_2/adc_dovf_i] [get_bd_pins axi_current_monitor_2_dma/fifo_wr_overflow]
#interrupt
@ -188,49 +181,55 @@
connect_bd_net -net sys_100m_clk [get_bd_pins axi_mc_speed_1/ref_clk] $sys_100m_clk_source
connect_bd_net -net axi_mc_speed_1_position_o [get_bd_pins axi_mc_speed_1/position_o]
connect_bd_net -net axi_mc_speed_1_position_o [get_bd_pins axi_mc_speed_1/position_o] [get_bd_pins axi_mc_torque_controller/position_i]
connect_bd_net -net axi_mc_speed_1_position_o [get_bd_pins axi_mc_speed_1/position_o] [get_bd_pins axi_mc_controller/position_i]
connect_bd_net -net axi_mc_speed_1_new_speed_o [get_bd_pins axi_mc_speed_1/new_speed_o]
connect_bd_net -net axi_mc_speed_1_new_speed_o [get_bd_pins axi_mc_speed_1/new_speed_o] [get_bd_pins axi_mc_torque_controller/new_speed_i]
connect_bd_net -net axi_mc_speed_1_new_speed_o [get_bd_pins axi_mc_speed_1/new_speed_o] [get_bd_pins pid_controller/new_motor_speed]
connect_bd_net -net axi_mc_speed_1_speed_o [get_bd_pins axi_mc_speed_1/speed_o]
connect_bd_net -net axi_mc_speed_1_speed_o [get_bd_pins axi_mc_speed_1/speed_o] [get_bd_pins axi_mc_torque_controller/speed_i]
connect_bd_net -net axi_mc_speed_1_speed_o [get_bd_pins axi_mc_speed_1/speed_o] [get_bd_pins pid_controller/motor_speed] [get_bd_pins axi_mc_controller/new_speed_i]
connect_bd_net [get_bd_pins /axi_mc_torque_controller/fmc_m1_fault_i] [get_bd_ports /fmc_m1_fault_i]
connect_bd_net -net speed_detector_adc_clk [get_bd_pins axi_mc_speed_1/adc_clk_o] [get_bd_pins axi_speed_detector_dma/fifo_wr_clk]
connect_bd_net -net speed_detector_adc_dwr [get_bd_pins axi_mc_speed_1/adc_dwr_o] [get_bd_pins axi_speed_detector_dma/fifo_wr_en]
connect_bd_net -net speed_detector_adc_ddata [get_bd_pins axi_mc_speed_1/adc_ddata_o] [get_bd_pins axi_speed_detector_dma/fifo_wr_din]
#connect_bd_net -net speed_detector_adc_dovf [get_bd_pins axi_mc_speed_1/adc_dovf_i]
#connect_bd_net -net speed_detector_adc_dunf [get_bd_pins axi_mc_speed_1/adc_dunf_i]
connect_bd_net -net speed_detector_adc_clk [get_bd_pins axi_mc_speed_1/adc_clk_o] [get_bd_pins axi_speed_detector_dma/fifo_wr_clk]
connect_bd_net -net speed_detector_adc_dwr [get_bd_pins axi_mc_speed_1/adc_dwr_o] [get_bd_pins axi_speed_detector_dma/fifo_wr_en]
connect_bd_net -net speed_detector_adc_ddata [get_bd_pins axi_mc_speed_1/adc_ddata_o] [get_bd_pins axi_speed_detector_dma/fifo_wr_din]
connect_bd_net -net speed_detector_adc_dovf [get_bd_pins axi_mc_speed_1/adc_dovf_i] [get_bd_pins axi_speed_detector_dma/fifo_wr_overflow]
# interrupt
connect_bd_net -net axi_speed_detector_dma_irq [get_bd_pins axi_speed_detector_dma/irq] [get_bd_pins sys_concat_intc/In3]
# torque controller
# controller
connect_bd_net -net sys_100m_clk [get_bd_pins axi_mc_torque_controller/ref_clk] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_mc_controller/ref_clk] $sys_100m_clk_source
connect_bd_net -net axi_mc_current_monitor_1_it_o [get_bd_pins axi_mc_current_monitor_1/it_o] [get_bd_pins axi_mc_torque_controller/it_i]
connect_bd_net -net axi_mc_torque_controller_fmc_m1_en_o [get_bd_ports fmc_m1_en_o] [get_bd_pins axi_mc_torque_controller/fmc_m1_en_o]
connect_bd_net -net axi_mc_torque_controller_pwm_al_o [get_bd_ports pwm_al_o] [get_bd_pins axi_mc_torque_controller/pwm_al_o]
connect_bd_net -net axi_mc_torque_controller_pwm_ah_o [get_bd_ports pwm_ah_o] [get_bd_pins axi_mc_torque_controller/pwm_ah_o]
connect_bd_net -net axi_mc_torque_controller_pwm_cl_o [get_bd_ports pwm_cl_o] [get_bd_pins axi_mc_torque_controller/pwm_cl_o]
connect_bd_net -net axi_mc_torque_controller_pwm_ch_o [get_bd_ports pwm_ch_o] [get_bd_pins axi_mc_torque_controller/pwm_ch_o]
connect_bd_net -net axi_mc_torque_controller_pwm_bl_o [get_bd_ports pwm_bl_o] [get_bd_pins axi_mc_torque_controller/pwm_bl_o]
connect_bd_net -net axi_mc_torque_controller_pwm_bh_o [get_bd_ports pwm_bh_o] [get_bd_pins axi_mc_torque_controller/pwm_bh_o]
connect_bd_net -net axi_mc_torque_controller_gpo_o [get_bd_ports gpo_o] [get_bd_pins axi_mc_torque_controller/gpo_o]
connect_bd_net -net axi_mc_torque_controller_sensors_o [get_bd_pins axi_mc_torque_controller/sensors_o] [get_bd_pins axi_mc_speed_1/hall_bemf_i]
connect_bd_net -net axi_mc_controller_fmc_m1_en_o [get_bd_ports fmc_m1_en_o] [get_bd_pins axi_mc_controller/fmc_m1_en_o]
connect_bd_net -net axi_mc_controller_pwm_al_o [get_bd_ports pwm_al_o] [get_bd_pins axi_mc_controller/pwm_al_o]
connect_bd_net -net axi_mc_controller_pwm_ah_o [get_bd_ports pwm_ah_o] [get_bd_pins axi_mc_controller/pwm_ah_o]
connect_bd_net -net axi_mc_controller_pwm_cl_o [get_bd_ports pwm_cl_o] [get_bd_pins axi_mc_controller/pwm_cl_o]
connect_bd_net -net axi_mc_controller_pwm_ch_o [get_bd_ports pwm_ch_o] [get_bd_pins axi_mc_controller/pwm_ch_o]
connect_bd_net -net axi_mc_controller_pwm_bl_o [get_bd_ports pwm_bl_o] [get_bd_pins axi_mc_controller/pwm_bl_o]
connect_bd_net -net axi_mc_controller_pwm_bh_o [get_bd_ports pwm_bh_o] [get_bd_pins axi_mc_controller/pwm_bh_o]
connect_bd_net -net axi_mc_controller_gpo_o [get_bd_ports gpo_o] [get_bd_pins axi_mc_controller/gpo_o]
connect_bd_net -net axi_mc_controller_sensors_o [get_bd_pins axi_mc_controller/sensors_o] [get_bd_pins axi_mc_speed_1/hall_bemf_i]
connect_bd_net -net axi_mc_controller_fault [get_bd_pins /axi_mc_controller/fmc_m1_fault_i] [get_bd_ports /fmc_m1_fault_i]
connect_bd_net -net axi_mc_torque_controller_adc_clk [get_bd_pins axi_mc_torque_controller/adc_clk_o] [get_bd_pins axi_torque_controller_dma/fifo_wr_clk]
connect_bd_net -net axi_mc_torque_controller_adc_dwr [get_bd_pins axi_mc_torque_controller/adc_dwr_o] [get_bd_pins axi_torque_controller_dma/fifo_wr_en]
connect_bd_net -net axi_mc_torque_controller_adc_ddata [get_bd_pins axi_mc_torque_controller/adc_ddata_o] [get_bd_pins axi_torque_controller_dma/fifo_wr_din]
#connect_bd_net -net axi_mc_torque_controller_adc_dsync [get_bd_pins axi_mc_torque_controller/adc_dsync_o] [get_bd_pins axi_torque_controller_dma/fifo_wr_sync]
#connect_bd_net -net axi_mc_torque_controller_adc_dovf [get_bd_pins axi_mc_torque_controller/adc_dovf_i]
#connect_bd_net -net axi_mc_torque_controller_adc_dunf [get_bd_pins axi_mc_torque_controller/adc_dunf_i]
connect_bd_net -net axi_mc_controller_adc_clk [get_bd_pins axi_mc_controller/adc_clk_o] [get_bd_pins axi_controller_dma/fifo_wr_clk]
connect_bd_net -net axi_mc_controller_adc_dwr [get_bd_pins axi_mc_controller/adc_dwr_o] [get_bd_pins axi_controller_dma/fifo_wr_en]
connect_bd_net -net axi_mc_controller_adc_ddata [get_bd_pins axi_mc_controller/adc_ddata_o] [get_bd_pins axi_controller_dma/fifo_wr_din]
connect_bd_net -net axi_mc_controller_adc_dovf [get_bd_pins axi_mc_controller/adc_dovf_i] [get_bd_pins axi_controller_dma/fifo_wr_overflow]
connect_bd_net -net sys_100m_clk [get_bd_pins pid_controller/clk]
connect_bd_net -net axi_mc_controller_ctrl_rst_o [get_bd_pins axi_mc_controller/ctrl_rst_o] [get_bd_pins pid_controller/rst]
connect_bd_net -net axi_mc_controller_err_i [get_bd_pins axi_mc_controller/err_i] [get_bd_pins pid_controller/err]
connect_bd_net -net axi_mc_controller_pwm_i [get_bd_pins axi_mc_controller/pwm_i] [get_bd_pins pid_controller/pwm]
connect_bd_net -net axi_mc_controller_speed_rpm_i [get_bd_pins axi_mc_controller/speed_rpm_i] [get_bd_pins pid_controller/speed]
connect_bd_net -net axi_mc_controller_ref_speed_o [get_bd_pins axi_mc_controller/ref_speed_o] [get_bd_pins pid_controller/ref_speed]
connect_bd_net -net axi_mc_controller_kp_o [get_bd_pins axi_mc_controller/kp_o] [get_bd_pins pid_controller/kp]
connect_bd_net -net axi_mc_controller_ki_o [get_bd_pins axi_mc_controller/ki_o] [get_bd_pins pid_controller/ki]
connect_bd_net -net axi_mc_controller_kd_o [get_bd_pins axi_mc_controller/kd_o] [get_bd_pins pid_controller/kd]
# interrupt
connect_bd_net -net axi_torque_controller_dma_irq [get_bd_pins axi_torque_controller_dma/irq] [get_bd_pins sys_concat_intc/In5]
connect_bd_net -net axi_controller_dma_irq [get_bd_pins axi_controller_dma/irq] [get_bd_pins sys_concat_intc/In5]
# xadc
@ -245,35 +244,17 @@
connect_bd_net -net vauxn8_1 [get_bd_ports vauxn8] [get_bd_pins xadc_wiz_1/vauxn8]
connect_bd_net -net xadc_wiz_1_muxaddr_out [get_bd_ports muxaddr_out] [get_bd_pins xadc_wiz_1/muxaddr_out]
# ila
set ila_current_monitor [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:3.0 ila_current_monitor]
set_property -dict [list CONFIG.C_NUM_OF_PROBES {5}] $ila_current_monitor
set_property -dict [list CONFIG.C_PROBE0_WIDTH {1}] $ila_current_monitor
set_property -dict [list CONFIG.C_PROBE1_WIDTH {1}] $ila_current_monitor
set_property -dict [list CONFIG.C_PROBE2_WIDTH {1}] $ila_current_monitor
set_property -dict [list CONFIG.C_PROBE3_WIDTH {64}] $ila_current_monitor
set_property -dict [list CONFIG.C_PROBE4_WIDTH {32}] $ila_current_monitor
set_property -dict [list CONFIG.C_EN_STRG_QUAL {1} ] $ila_current_monitor
set_property -dict [list CONFIG.C_ADV_TRIGGER {true}] $ila_current_monitor
connect_bd_net -net axi_mc_current_monitor_1_adc_clk [get_bd_pins ila_current_monitor/probe0]
connect_bd_net -net axi_mc_current_monitor_1_adc_dwr [get_bd_pins ila_current_monitor/probe1]
connect_bd_net -net axi_mc_current_monitor_1_adc_dsync [get_bd_pins ila_current_monitor/probe2]
connect_bd_net -net axi_mc_current_monitor_1_adc_ddata [get_bd_pins ila_current_monitor/probe3]
connect_bd_net -net axi_mc_current_monitor_1_adc_mon_data [get_bd_pins ila_current_monitor/probe4]
connect_bd_net -net sys_100m_clk [get_bd_pins ila_current_monitor/clk]
# interconnect (cpu)
connect_bd_intf_net -intf_net axi_cpu_interconnect_m07_axi [get_bd_intf_pins axi_cpu_interconnect/M07_AXI] [get_bd_intf_pins axi_mc_current_monitor_1/s_axi]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m08_axi [get_bd_intf_pins axi_cpu_interconnect/M08_AXI] [get_bd_intf_pins axi_mc_speed_1/s_axi]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m09_axi [get_bd_intf_pins axi_cpu_interconnect/M09_AXI] [get_bd_intf_pins axi_mc_torque_controller/s_axi]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m09_axi [get_bd_intf_pins axi_cpu_interconnect/M09_AXI] [get_bd_intf_pins axi_mc_controller/s_axi]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m10_axi [get_bd_intf_pins axi_cpu_interconnect/M10_AXI] [get_bd_intf_pins axi_mc_current_monitor_2/s_axi]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m11_axi [get_bd_intf_pins axi_cpu_interconnect/M11_AXI] [get_bd_intf_pins xadc_wiz_1/s_axi_lite]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m12_axi [get_bd_intf_pins axi_cpu_interconnect/M12_AXI] [get_bd_intf_pins axi_speed_detector_dma/s_axi]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m13_axi [get_bd_intf_pins axi_cpu_interconnect/M13_AXI] [get_bd_intf_pins axi_current_monitor_1_dma/s_axi]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m14_axi [get_bd_intf_pins axi_cpu_interconnect/M14_AXI] [get_bd_intf_pins axi_current_monitor_2_dma/s_axi]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m15_axi [get_bd_intf_pins axi_cpu_interconnect/M15_AXI] [get_bd_intf_pins axi_torque_controller_dma/s_axi]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m15_axi [get_bd_intf_pins axi_cpu_interconnect/M15_AXI] [get_bd_intf_pins axi_controller_dma/s_axi]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M07_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M08_ACLK] $sys_100m_clk_source
@ -337,17 +318,17 @@
connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/S00_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/S00_ARESETN] $sys_100m_resetn_source
# interconnect (torque controller)
# interconnect (controller)
connect_bd_net -net sys_100m_clk [get_bd_pins axi_mc_torque_controller/s_axi_aclk] $sys_100m_clk_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mc_torque_controller/s_axi_aresetn] $sys_100m_resetn_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_mc_controller/s_axi_aclk] $sys_100m_clk_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mc_controller/s_axi_aresetn] $sys_100m_resetn_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_torque_controller_dma/s_axi_aclk] $sys_100m_clk_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_torque_controller_dma/s_axi_aresetn] $sys_100m_resetn_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_torque_controller_dma/m_dest_axi_aclk] $sys_100m_clk_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_torque_controller_dma/m_dest_axi_aresetn] $sys_100m_resetn_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_controller_dma/s_axi_aclk] $sys_100m_clk_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_controller_dma/s_axi_aresetn] $sys_100m_resetn_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_controller_dma/m_dest_axi_aclk] $sys_100m_clk_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_controller_dma/m_dest_axi_aresetn] $sys_100m_resetn_source
connect_bd_intf_net -intf_net axi_mem_interconnect_s03_axi [get_bd_intf_pins axi_mem_interconnect/S03_AXI] [get_bd_intf_pins axi_torque_controller_dma/m_dest_axi]
connect_bd_intf_net -intf_net axi_mem_interconnect_s03_axi [get_bd_intf_pins axi_mem_interconnect/S03_AXI] [get_bd_intf_pins axi_controller_dma/m_dest_axi]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/S03_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/S03_ARESETN] $sys_100m_resetn_source
@ -366,15 +347,15 @@
create_bd_addr_seg -range 0x10000 -offset 0x40400000 $sys_addr_cntrl_space [get_bd_addr_segs axi_current_monitor_1_dma/s_axi/axi_lite] SEG_data_c_m_1_dma
create_bd_addr_seg -range 0x10000 -offset 0x40410000 $sys_addr_cntrl_space [get_bd_addr_segs axi_speed_detector_dma/s_axi/axi_lite] SEG_data_s_d_dma
create_bd_addr_seg -range 0x10000 -offset 0x40420000 $sys_addr_cntrl_space [get_bd_addr_segs axi_torque_controller_dma/s_axi/axi_lite] SEG_data_t_c_dma
create_bd_addr_seg -range 0x10000 -offset 0x40420000 $sys_addr_cntrl_space [get_bd_addr_segs axi_controller_dma/s_axi/axi_lite] SEG_data_t_c_dma
create_bd_addr_seg -range 0x10000 -offset 0x40430000 $sys_addr_cntrl_space [get_bd_addr_segs axi_current_monitor_2_dma/s_axi/axi_lite] SEG_data_c_m_2_dma
create_bd_addr_seg -range 0x10000 -offset 0x40500000 $sys_addr_cntrl_space [get_bd_addr_segs axi_mc_current_monitor_1/s_axi/axi_lite] SEG_data_c_m_1
create_bd_addr_seg -range 0x10000 -offset 0x40510000 $sys_addr_cntrl_space [get_bd_addr_segs axi_mc_speed_1/s_axi/axi_lite] SEG_data_s_d
create_bd_addr_seg -range 0x10000 -offset 0x40520000 $sys_addr_cntrl_space [get_bd_addr_segs axi_mc_torque_controller/s_axi/axi_lite] SEG_data_t_c
create_bd_addr_seg -range 0x10000 -offset 0x40520000 $sys_addr_cntrl_space [get_bd_addr_segs axi_mc_controller/s_axi/axi_lite] SEG_data_t_c
create_bd_addr_seg -range 0x10000 -offset 0x40530000 $sys_addr_cntrl_space [get_bd_addr_segs axi_mc_current_monitor_2/s_axi/axi_lite] SEG_data_c_m_2
create_bd_addr_seg -range 0x10000 -offset 0x43200000 $sys_addr_cntrl_space [get_bd_addr_segs xadc_wiz_1/s_axi_lite/Reg] SEG_data_xadc
create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_current_monitor_1_dma/m_dest_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_sys_ps7_hp1_ddr_lowocm
create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_speed_detector_dma/m_dest_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_sys_ps7_hp1_ddr_lowocm
create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_torque_controller_dma/m_dest_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_sys_ps7_hp1_ddr_lowocm
create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_controller_dma/m_dest_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_sys_ps7_hp1_ddr_lowocm
create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_current_monitor_2_dma/m_dest_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_sys_ps7_hp1_ddr_lowocm