diff --git a/docs/library/axi_tdd/diagram.svg b/docs/library/axi_tdd/diagram.svg new file mode 100644 index 000000000..da34c7ef7 --- /dev/null +++ b/docs/library/axi_tdd/diagram.svg @@ -0,0 +1,285 @@ + + + +TCH1OFFTCH0OFFTCH1ONCH2Frame 0Frame 1CH1CH00TCH0ONTCH2ONTCH2OFFTframet diff --git a/docs/library/axi_tdd/fsm.svg b/docs/library/axi_tdd/fsm.svg new file mode 100644 index 000000000..5b48c1b00 --- /dev/null +++ b/docs/library/axi_tdd/fsm.svg @@ -0,0 +1,4 @@ + + + +
IDLE
IDLE
1 PPS Sync
1 PPS Sync
ARMED
ARMED
Startup Delay Passed
Startup Delay Passed
WAITING
WAITING
Frame Done
Frame Done
RUNNING
RUNNING
Yes
Yes
Burst Count
Reached
Burst Count...
Yes
Yes
No
No
Enabled
Enabled
No
No
burst_count == 0
&& !Enabled
burst_count == 0...Text is not SVG - cannot display \ No newline at end of file diff --git a/docs/library/axi_tdd/index.rst b/docs/library/axi_tdd/index.rst new file mode 100644 index 000000000..72746bdbb --- /dev/null +++ b/docs/library/axi_tdd/index.rst @@ -0,0 +1,192 @@ +.. _axi_tdd: + +AXI TDD +================================================================================ + +.. hdl-component-diagram:: + +The :git-hdl:`AXI Time-Division Duplexing ` Controller IP core +is a pulse wave generator capable of addressing RF applications which require +Time Division Duplexing, as well as controlling other modules of general +applications through its dedicated 32 channel outputs. + +The reason of creating the generic TDD controller was to reduce the naming +confusion around the existing repurposed +:dokuwiki:`TDD core ` +built for AD9361, as well as expanding its number of output channels for systems +which require more than six controlling signals. + +.. note:: + + TDD (Time-Division Duplex) mode allows the user to control the time period of + the receive and transmit bursts. + +Features +-------------------------------------------------------------------------------- + +* Up to 32 independent output channels +* Start/stop time values per channel +* Enable and polarity bit values per channel +* 32 bit-max internal reference counter +* Initial startup delay before wave generation +* Configurable frame length and number of frames per burst +* 3 sources of synchronization: external, internal and software generated + +Files +-------------------------------------------------------------------------------- + +.. list-table:: + :header-rows: 1 + + * - Name + - Description + * - :git-hdl:`library/axi_tdd/axi_tdd.sv` + - Top module. + * - :git-hdl:`library/axi_tdd/axi_tdd_pkg.sv` + - SystemVerilog Package. + * - :git-hdl:`library/axi_tdd/axi_tdd_regmap.sv` + - Register Map with CDC synchronizers. + * - :git-hdl:`library/axi_tdd/axi_tdd_counter.sv` + - Internal counters and FSM logic. + * - :git-hdl:`library/axi_tdd/axi_tdd_channel.sv` + - Channel waveform generator. + * - :git-hdl:`library/axi_tdd/axi_tdd_sync_gen.sv` + - Synchronization pulse generator. + * - :git-hdl:`library/axi_tdd/axi_tdd_ip.tcl` + - TCL script to generate the Vivado IP-integrator project. + * - :git-hdl:`library/axi_tdd/axi_tdd_hw.tcl` + - TCL script to generate the Quartus IP-integrator project. + +Configuration Parameters +-------------------------------------------------------------------------------- + +.. hdl-parameters:: + + * - ID + - Instance identification number + * - CHANNEL_COUNT + - Number of channels + * - DEFAULT_POLARITY + - Initial channel polarity + * - REGISTER_WIDTH + - Internal counter and register width + * - BURST_COUNT_WIDTH + - Burst counter width + * - SYNC_INTERNAL + - Enable support for internal sync signal + * - SYNC_EXTERNAL + - Enable support for external sync signal + * - SYNC_EXTERNAL_CDC + - Enable synchronization of external sync signal + * - SYNC_COUNT_WIDTH + - Sync generator counter width + + +Interface +-------------------------------------------------------------------------------- + +.. hdl-interfaces:: + + * - s_axi_aclk + - System clock. + * - s_axi_aresetn + - System reset, synchronous active low reset. + * - s_axi + - AXI-Lite bus slave, memory mapped AXI-Lite bus that provides access to module's + register map. + * - clk + - Core clock. + * - resetn + - Core reset, synchronous active low reset. + * - sync_in + - External synchronization input signal. + * - sync_out + - Module synchronization output signal. + * - tdd_channel + - Channels output. + +Theory of Operation +-------------------------------------------------------------------------------- + +The central idea of the TDD controller is “frame”-based operation, i.e. all the +timing defined for the individual channels is relative to the beginning of a +frame. The ``FRAME_LENGTH`` value controls the length of a single frame, while +the ``BURST_COUNT`` value controls how many frames should be played after +enabling the device (a value of 0 means the frames will be repeated indefinitely). +Before the start of a burst, an optional startup delay is inserted, defined by +the ``STARTUP_DELAY`` value in clock cycles. + +.. image:: diagram.svg + +This diagram illustrates how different channels can be enabled at different +times relative to the beginning of a frame. + +.. note:: + + While the above graphic shows all channels being enabled in a stacked + manner, they are completely independent of each other. + +Detailed Description +-------------------------------------------------------------------------------- + +In order to begin its operation, the peripheral must be enabled. This is done by +setting the ``ENABLE`` bit. Next, the peripheral waits to receive a synchronization +signal. There are 3 possible sync sources, which can be independently activated +through their corresponding enabling bits: ``SYNC_INT``, ``SYNC_EXT`` and ``SYNC_SOFT`` +can all be active at the same time. + +The external synchronization capability allows the alignment of frames between +multiple devices in different locations, for example using a GPSDO 1 PPS output. +The internal sync signal is generated based on a dedicated counter, when its +value matches the one defined in ``SYNC_COUNTER_LOW`` / ``SYNC_COUNTER_HIGH``. +The software generated sync pulse is triggered at an arbitrary point in time +when writing a ‘1’ value in ``SYNC_SOFT``. + +The next diagram shows the peripheral’s FSM, which transitions between 4 states: +IDLE, ARMED, WAITING and RUNNING. + +.. image:: fsm.svg + +In case a synchronization signal is received while the TDD core is running, the +signal can reset the internal counter to zero by setting ``SYNC_RST`` to ‘1’. +This can alter the counter value in both WAITING or RUNNING states. + +The generic TDD controller can have up to 32 output channels, each of them +having its unique values when the channel is set/reset under ``CHX_ON`` / +``CHX_OFF``. They are continuously compared to the internal counter’s value +while the core is RUNNING. + +Every bit in ``CHANNEL_ENABLE`` / ``CHANNEL_POLARITY`` corresponds to a specific +channel. The bit position is correlated to the channel index, so the LSB will +always be associated with CH0 and the MSB with CH31. + +The following registers will not be updated unless the peripheral is disabled: + +- ``BURST_COUNT`` +- ``STARTUP_DELAY`` +- ``FRAME_LENGTH`` +- ``CHANNEL_POLARITY`` +- ``SYNC_COUNTER_LOW`` +- ``SYNC_COUNTER_HIGH`` +- ``CHX_ON`` +- ``CHX_OFF`` + +The user must configure them before enabling the peripheral. Any subsequent +write while the peripheral is enabled will be ignored. + +An exception to this rule is ``CHANNEL_ENABLE``, which allows enabling / +disabling independent channels on-the-fly. The new value will come into effect +when in ARMED state or at the end of a frame. ``CONTROL`` can also be modified +on-the-fly with immediate effect (after going through the synchronization stage). + +``STATUS`` can be used for debugging purposes, reflecting the current peripheral +state. + +By adapting the synthesis parameters to the application requirements, the module +is highly flexible and can substantially reduce resource utilization. + +Register Map +-------------------------------------------------------------------------------- + +.. hdl-regmap:: + :name: TDDN_CNTRL diff --git a/docs/regmap/adi_regmap_tdd_gen.txt b/docs/regmap/adi_regmap_tdd_gen.txt index 9253b0e25..4e14c267e 100644 --- a/docs/regmap/adi_regmap_tdd_gen.txt +++ b/docs/regmap/adi_regmap_tdd_gen.txt @@ -13,19 +13,19 @@ Version of the peripheral. Follows semantic versioning. Current version 2.00.61. ENDREG FIELD -[31:16] 0x0002 +[31:16] 0x00000002 VERSION_MAJOR R ENDFIELD FIELD -[15:8] 0x00 +[15:8] 0x00000000 VERSION_MINOR R ENDFIELD FIELD -[7:0] 0x61 +[7:0] 0x00000061 VERSION_PATCH R ENDFIELD @@ -87,49 +87,49 @@ FIELD [30:24] ''SYNC_COUNT_WIDTH'' SYNC_COUNT_WIDTH R -Width of internal synchronization counter +Width of internal synchronization counter. ENDFIELD FIELD [21:16] ''BURST_COUNT_WIDTH'' BURST_COUNT_WIDTH R -Width of burst counter +Width of burst counter. ENDFIELD FIELD [13:8] ''REGISTER_WIDTH'' REGISTER_WIDTH R -Width of internal reference counter and timing registers +Width of internal reference counter and timing registers. ENDFIELD FIELD [7] ''SYNC_EXTERNAL_CDC'' SYNC_EXTERNAL_CDC R -Enable CDC for external synchronization pulse +Enable CDC for external synchronization pulse. ENDFIELD FIELD [6] ''SYNC_EXTERNAL'' SYNC_EXTERNAL R -Enable external synchronization support +Enable external synchronization support. ENDFIELD FIELD [5] ''SYNC_INTERNAL'' SYNC_INTERNAL R -Enable internal synchronization support +Enable internal synchronization support. ENDFIELD FIELD [4:0] ''CHANNEL_COUNT''-1 CHANNEL_COUNT_EXTRA R -Number of channels starting from CH1, excluding CH0 +Number of channels starting from CH1, excluding CH0. ENDFIELD ############################################################################################ @@ -144,7 +144,7 @@ FIELD [31:0] ''DEFAULT_POLARITY'' DEFAULT_POLARITY R -Default polarity per every channel - LSB corresponds to CH0, MSB to CH31 +Default polarity per every channel - LSB corresponds to CH0, MSB to CH31. ENDFIELD ############################################################################################ @@ -157,38 +157,38 @@ TDD Control ENDREG FIELD -[4] 0x0 +[4] 0x00000000 SYNC_SOFT -RW -Trigger the TDD core through a register write. This bit self clears. +RW1C +Trigger the TDD core through a register write. ENDFIELD FIELD -[3] 0x0 +[3] 0x00000000 SYNC_EXT RW Enable external sync trigger. This bit is implemented if ''SYNC_EXTERNAL'' is set. ENDFIELD FIELD -[2] 0x0 +[2] 0x00000000 SYNC_INT RW Enable internal sync trigger. This bit is implemented if ''SYNC_INTERNAL'' is set. ENDFIELD FIELD -[1] 0x0 +[1] 0x00000000 SYNC_RST RW -Reset the internal counter while running when receiving a sync event +Reset the internal counter while running when receiving a sync event. ENDFIELD FIELD -[0] 0x0 +[0] 0x00000000 ENABLE RW -Module enable +Module enable. ENDFIELD ############################################################################################ @@ -204,7 +204,7 @@ FIELD [31:0] 0x00000000 CHANNEL_ENABLE RW -Enable bits per channel - LSB corresponds to CH0, MSB to CH31 +Enable bits per channel - LSB corresponds to CH0, MSB to CH31. ENDFIELD ############################################################################################ @@ -220,7 +220,7 @@ FIELD [31:0] 0x00000000 CHANNEL_POLARITY RW -Polarity bits per channel - LSB corresponds to CH0, MSB to CH31 +Polarity bits per channel - LSB corresponds to CH0, MSB to CH31. ENDFIELD ############################################################################################ @@ -236,7 +236,7 @@ FIELD [31:0] 0x00000000 BURST_COUNT RW -If set to 0x0 and enabled - the controller operates in TDD mode as long as the ENABLE bit is set. If set to a non-zero value, the controller operates for the set number of frames and then stops. +If set to 0 and enabled - the controller operates in TDD mode as long as the ENABLE bit is set. If set to a non-zero value, the controller operates for the set number of frames and then stops. ENDFIELD ############################################################################################ @@ -313,7 +313,7 @@ Peripheral Status ENDREG FIELD -[1:0] 0x0 +[1:0] 0x00000000 STATE R The current state of the peripheral FSM; used for debugging purposes. @@ -323,1026 +323,35 @@ ENDFIELD ############################################################################################ REG -0x0020 -CH0_ON +0x0020 + 0x2*n +WHERE n IS FROM 0 TO 31 +CHn_ON Channel Set ENDREG FIELD [31:0] 0x00000000 -CH0_ON +CHn_ON RW -The offset (from frame count equal zero), when CH0 is set. +The offset (from frame count equal zero), when CHn is set. ENDFIELD ############################################################################################ ############################################################################################ REG -0x0021 -CH0_OFF +0x0021 + 0x2*n +WHERE n IS FROM 0 TO 31 +CHn_OFF Channel Reset ENDREG FIELD [31:0] 0x00000000 -CH0_OFF +CHn_OFF RW -The offset (from frame count equal zero), when CH0 is reset. +The offset (from frame count equal zero), when CHn is reset. ENDFIELD ############################################################################################ ############################################################################################ - -REG -0x0022 -CH1_ON -Channel Set -ENDREG - -FIELD -[31:0] 0x00000000 -CH1_ON -RW -The offset (from frame count equal zero), when CH1 is set. This register is implemented if ''CHANNEL_COUNT''>1. -ENDFIELD - -############################################################################################ -############################################################################################ - -REG -0x0023 -CH1_OFF -Channel Reset -ENDREG - -FIELD -[31:0] 0x00000000 -CH1_OFF -RW -The offset (from frame count equal zero), when CH1 is reset. This register is implemented if ''CHANNEL_COUNT''>1. -ENDFIELD - -############################################################################################ -############################################################################################ - -REG -0x0024 -CH2_ON -Channel Set -ENDREG - -FIELD -[31:0] 0x00000000 -CH2_ON -RW -The offset (from frame count equal zero), when CH2 is set. This register is implemented if ''CHANNEL_COUNT''>2. -ENDFIELD - -############################################################################################ -############################################################################################ - -REG -0x0025 -CH2_OFF -Channel Reset -ENDREG - -FIELD -[31:0] 0x00000000 -CH2_OFF -RW -The offset (from frame count equal zero), when CH2 is reset. This register is implemented if ''CHANNEL_COUNT''>2. -ENDFIELD - -############################################################################################ -############################################################################################ - -REG -0x0026 -CH3_ON -Channel Set -ENDREG - -FIELD -[31:0] 0x00000000 -CH3_ON -RW -The offset (from frame count equal zero), when CH3 is set. This register is implemented if ''CHANNEL_COUNT''>3. -ENDFIELD - -############################################################################################ -############################################################################################ - -REG -0x0027 -CH3_OFF -Channel Reset -ENDREG - -FIELD -[31:0] 0x00000000 -CH3_OFF -RW -The offset (from frame count equal zero), when CH3 is reset. This register is implemented if ''CHANNEL_COUNT''>3. -ENDFIELD - -############################################################################################ -############################################################################################ - -REG -0x0028 -CH4_ON -Channel Set -ENDREG - -FIELD -[31:0] 0x00000000 -CH4_ON -RW -The offset (from frame count equal zero), when CH4 is set. This register is implemented if ''CHANNEL_COUNT''>4. -ENDFIELD - -############################################################################################ -############################################################################################ - -REG -0x0029 -CH4_OFF -Channel Reset -ENDREG - -FIELD -[31:0] 0x00000000 -CH4_OFF -RW -The offset (from frame count equal zero), when CH4 is reset. This register is implemented if ''CHANNEL_COUNT''>4. -ENDFIELD - -############################################################################################ -############################################################################################ - -REG -0x002A -CH5_ON -Channel Set -ENDREG - -FIELD -[31:0] 0x00000000 -CH5_ON -RW -The offset (from frame count equal zero), when CH5 is set. This register is implemented if ''CHANNEL_COUNT''>5. -ENDFIELD - -############################################################################################ -############################################################################################ - -REG -0x002B -CH5_OFF -Channel Reset -ENDREG - -FIELD -[31:0] 0x00000000 -CH5_OFF -RW -The offset (from frame count equal zero), when CH5 is reset. This register is implemented if ''CHANNEL_COUNT''>5. -ENDFIELD - -############################################################################################ -############################################################################################ - -REG -0x002C -CH6_ON -Channel Set -ENDREG - -FIELD -[31:0] 0x00000000 -CH6_ON -RW -The offset (from frame count equal zero), when CH6 is set. This register is implemented if ''CHANNEL_COUNT''>6. -ENDFIELD - -############################################################################################ -############################################################################################ - -REG -0x002D -CH6_OFF -Channel Reset -ENDREG - -FIELD -[31:0] 0x00000000 -CH6_OFF -RW -The offset (from frame count equal zero), when CH6 is reset. This register is implemented if ''CHANNEL_COUNT''>6. -ENDFIELD - -############################################################################################ -############################################################################################ - -REG -0x002E -CH7_ON -Channel Set -ENDREG - -FIELD -[31:0] 0x00000000 -CH7_ON -RW -The offset (from frame count equal zero), when CH7 is set. This register is implemented if ''CHANNEL_COUNT''>7. -ENDFIELD - -############################################################################################ -############################################################################################ - -REG -0x002F -CH7_OFF -Channel Reset -ENDREG - -FIELD -[31:0] 0x00000000 -CH7_OFF -RW -The offset (from frame count equal zero), when CH7 is reset. This register is implemented if ''CHANNEL_COUNT''>7. -ENDFIELD - -############################################################################################ -############################################################################################ - -REG -0x0030 -CH8_ON -Channel Set -ENDREG - -FIELD -[31:0] 0x00000000 -CH8_ON -RW -The offset (from frame count equal zero), when CH8 is set. This register is implemented if ''CHANNEL_COUNT''>8. -ENDFIELD - -############################################################################################ -############################################################################################ - -REG -0x0031 -CH8_OFF -Channel Reset -ENDREG - -FIELD -[31:0] 0x00000000 -CH8_OFF -RW -The offset (from frame count equal zero), when CH8 is reset. This register is implemented if ''CHANNEL_COUNT''>8. -ENDFIELD - -############################################################################################ -############################################################################################ - -REG -0x0032 -CH9_ON -Channel Set -ENDREG - -FIELD -[31:0] 0x00000000 -CH9_ON -RW -The offset (from frame count equal zero), when CH9 is set. This register is implemented if ''CHANNEL_COUNT''>9. -ENDFIELD - -############################################################################################ -############################################################################################ - -REG -0x0033 -CH9_OFF -Channel Reset -ENDREG - -FIELD -[31:0] 0x00000000 -CH9_OFF -RW -The offset (from frame count equal zero), when CH9 is reset. This register is implemented if ''CHANNEL_COUNT''>9. -ENDFIELD - -############################################################################################ -############################################################################################ - -REG -0x0034 -CH10_ON -Channel Set -ENDREG - -FIELD -[31:0] 0x00000000 -CH10_ON -RW -The offset (from frame count equal zero), when CH10 is set. This register is implemented if ''CHANNEL_COUNT''>10. -ENDFIELD - -############################################################################################ -############################################################################################ - -REG -0x0035 -CH10_OFF -Channel Reset -ENDREG - -FIELD -[31:0] 0x00000000 -CH10_OFF -RW -The offset (from frame count equal zero), when CH10 is reset. This register is implemented if ''CHANNEL_COUNT''>10. -ENDFIELD - -############################################################################################ -############################################################################################ - -REG -0x0036 -CH11_ON -Channel Set -ENDREG - -FIELD -[31:0] 0x00000000 -CH11_ON -RW -The offset (from frame count equal zero), when CH11 is set. This register is implemented if ''CHANNEL_COUNT''>11. -ENDFIELD - -############################################################################################ -############################################################################################ - -REG -0x0037 -CH11_OFF -Channel Reset -ENDREG - -FIELD -[31:0] 0x00000000 -CH11_OFF -RW -The offset (from frame count equal zero), when CH11 is reset. This register is implemented if ''CHANNEL_COUNT''>11. -ENDFIELD - -############################################################################################ -############################################################################################ - -REG -0x0038 -CH12_ON -Channel Set -ENDREG - -FIELD -[31:0] 0x00000000 -CH12_ON -RW -The offset (from frame count equal zero), when CH12 is set. This register is implemented if ''CHANNEL_COUNT''>12. -ENDFIELD - -############################################################################################ -############################################################################################ - -REG -0x0039 -CH12_OFF -Channel Reset -ENDREG - -FIELD -[31:0] 0x00000000 -CH12_OFF -RW -The offset (from frame count equal zero), when CH12 is reset. This register is implemented if ''CHANNEL_COUNT''>12. -ENDFIELD - -############################################################################################ -############################################################################################ - -REG -0x003A -CH13_ON -Channel Set -ENDREG - -FIELD -[31:0] 0x00000000 -CH13_ON -RW -The offset (from frame count equal zero), when CH13 is set. This register is implemented if ''CHANNEL_COUNT''>13. -ENDFIELD - -############################################################################################ -############################################################################################ - -REG -0x003B -CH13_OFF -Channel Reset -ENDREG - -FIELD -[31:0] 0x00000000 -CH13_OFF -RW -The offset (from frame count equal zero), when CH13 is reset. This register is implemented if ''CHANNEL_COUNT''>13. -ENDFIELD - -############################################################################################ -############################################################################################ - -REG -0x003C -CH14_ON -Channel Set -ENDREG - -FIELD -[31:0] 0x00000000 -CH14_ON -RW -The offset (from frame count equal zero), when CH14 is set. This register is implemented if ''CHANNEL_COUNT''>14. -ENDFIELD - -############################################################################################ -############################################################################################ - -REG -0x003D -CH14_OFF -Channel Reset -ENDREG - -FIELD -[31:0] 0x00000000 -CH14_OFF -RW -The offset (from frame count equal zero), when CH14 is reset. This register is implemented if ''CHANNEL_COUNT''>14. -ENDFIELD - -############################################################################################ -############################################################################################ - -REG -0x003E -CH15_ON -Channel Set -ENDREG - -FIELD -[31:0] 0x00000000 -CH15_ON -RW -The offset (from frame count equal zero), when CH15 is set. This register is implemented if ''CHANNEL_COUNT''>15. -ENDFIELD - -############################################################################################ -############################################################################################ - -REG -0x003F -CH15_OFF -Channel Reset -ENDREG - -FIELD -[31:0] 0x00000000 -CH15_OFF -RW -The offset (from frame count equal zero), when CH15 is reset. This register is implemented if ''CHANNEL_COUNT''>15. -ENDFIELD - -############################################################################################ -############################################################################################ - -REG -0x0040 -CH16_ON -Channel Set -ENDREG - -FIELD -[31:0] 0x00000000 -CH16_ON -RW -The offset (from frame count equal zero), when CH16 is set. This register is implemented if ''CHANNEL_COUNT''>16. -ENDFIELD - -############################################################################################ -############################################################################################ - -REG -0x0041 -CH16_OFF -Channel Reset -ENDREG - -FIELD -[31:0] 0x00000000 -CH16_OFF -RW -The offset (from frame count equal zero), when CH16 is reset. This register is implemented if ''CHANNEL_COUNT''>16. -ENDFIELD - -############################################################################################ -############################################################################################ - -REG -0x0042 -CH17_ON -Channel Set -ENDREG - -FIELD -[31:0] 0x00000000 -CH17_ON -RW -The offset (from frame count equal zero), when CH17 is set. This register is implemented if ''CHANNEL_COUNT''>17. -ENDFIELD - -############################################################################################ -############################################################################################ - -REG -0x0043 -CH17_OFF -Channel Reset -ENDREG - -FIELD -[31:0] 0x00000000 -CH17_OFF -RW -The offset (from frame count equal zero), when CH17 is reset. This register is implemented if ''CHANNEL_COUNT''>17. -ENDFIELD - -############################################################################################ -############################################################################################ - -REG -0x0044 -CH18_ON -Channel Set -ENDREG - -FIELD -[31:0] 0x00000000 -CH18_ON -RW -The offset (from frame count equal zero), when CH18 is set. This register is implemented if ''CHANNEL_COUNT''>18. -ENDFIELD - -############################################################################################ -############################################################################################ - -REG -0x0045 -CH18_OFF -Channel Reset -ENDREG - -FIELD -[31:0] 0x00000000 -CH18_OFF -RW -The offset (from frame count equal zero), when CH18 is reset. This register is implemented if ''CHANNEL_COUNT''>18. -ENDFIELD - -############################################################################################ -############################################################################################ - -REG -0x0046 -CH19_ON -Channel Set -ENDREG - -FIELD -[31:0] 0x00000000 -CH19_ON -RW -The offset (from frame count equal zero), when CH19 is set. This register is implemented if ''CHANNEL_COUNT''>19. -ENDFIELD - -############################################################################################ -############################################################################################ - -REG -0x0047 -CH19_OFF -Channel Reset -ENDREG - -FIELD -[31:0] 0x00000000 -CH19_OFF -RW -The offset (from frame count equal zero), when CH19 is reset. This register is implemented if ''CHANNEL_COUNT''>19. -ENDFIELD - -############################################################################################ -############################################################################################ - -REG -0x0048 -CH20_ON -Channel Set -ENDREG - -FIELD -[31:0] 0x00000000 -CH20_ON -RW -The offset (from frame count equal zero), when CH20 is set. This register is implemented if ''CHANNEL_COUNT''>20. -ENDFIELD - -############################################################################################ -############################################################################################ - -REG -0x0049 -CH20_OFF -Channel Reset -ENDREG - -FIELD -[31:0] 0x00000000 -CH20_OFF -RW -The offset (from frame count equal zero), when CH20 is reset. This register is implemented if ''CHANNEL_COUNT''>20. -ENDFIELD - -############################################################################################ -############################################################################################ - -REG -0x004A -CH21_ON -Channel Set -ENDREG - -FIELD -[31:0] 0x00000000 -CH21_ON -RW -The offset (from frame count equal zero), when CH21 is set. This register is implemented if ''CHANNEL_COUNT''>21. -ENDFIELD - -############################################################################################ -############################################################################################ - -REG -0x004B -CH21_OFF -Channel Reset -ENDREG - -FIELD -[31:0] 0x00000000 -CH21_OFF -RW -The offset (from frame count equal zero), when CH21 is reset. This register is implemented if ''CHANNEL_COUNT''>21. -ENDFIELD - -############################################################################################ -############################################################################################ - -REG -0x004C -CH22_ON -Channel Set -ENDREG - -FIELD -[31:0] 0x00000000 -CH22_ON -RW -The offset (from frame count equal zero), when CH22 is set. This register is implemented if ''CHANNEL_COUNT''>22. -ENDFIELD - -############################################################################################ -############################################################################################ - -REG -0x004D -CH22_OFF -Channel Reset -ENDREG - -FIELD -[31:0] 0x00000000 -CH22_OFF -RW -The offset (from frame count equal zero), when CH22 is reset. This register is implemented if ''CHANNEL_COUNT''>22. -ENDFIELD - -############################################################################################ -############################################################################################ - -REG -0x004E -CH23_ON -Channel Set -ENDREG - -FIELD -[31:0] 0x00000000 -CH23_ON -RW -The offset (from frame count equal zero), when CH23 is set. This register is implemented if ''CHANNEL_COUNT''>23. -ENDFIELD - -############################################################################################ -############################################################################################ - -REG -0x004F -CH23_OFF -Channel Reset -ENDREG - -FIELD -[31:0] 0x00000000 -CH23_OFF -RW -The offset (from frame count equal zero), when CH23 is reset. This register is implemented if ''CHANNEL_COUNT''>23. -ENDFIELD - -############################################################################################ -############################################################################################ - -REG -0x0050 -CH24_ON -Channel Set -ENDREG - -FIELD -[31:0] 0x00000000 -CH24_ON -RW -The offset (from frame count equal zero), when CH24 is set. This register is implemented if ''CHANNEL_COUNT''>24. -ENDFIELD - -############################################################################################ -############################################################################################ - -REG -0x0051 -CH24_OFF -Channel Reset -ENDREG - -FIELD -[31:0] 0x00000000 -CH24_OFF -RW -The offset (from frame count equal zero), when CH24 is reset. This register is implemented if ''CHANNEL_COUNT''>24. -ENDFIELD - -############################################################################################ -############################################################################################ - -REG -0x0052 -CH25_ON -Channel Set -ENDREG - -FIELD -[31:0] 0x00000000 -CH25_ON -RW -The offset (from frame count equal zero), when CH25 is set. This register is implemented if ''CHANNEL_COUNT''>25. -ENDFIELD - -############################################################################################ -############################################################################################ - -REG -0x0053 -CH25_OFF -Channel Reset -ENDREG - -FIELD -[31:0] 0x00000000 -CH25_OFF -RW -The offset (from frame count equal zero), when CH25 is reset. This register is implemented if ''CHANNEL_COUNT''>25. -ENDFIELD - -############################################################################################ -############################################################################################ - -REG -0x0054 -CH26_ON -Channel Set -ENDREG - -FIELD -[31:0] 0x00000000 -CH26_ON -RW -The offset (from frame count equal zero), when CH26 is set. This register is implemented if ''CHANNEL_COUNT''>26. -ENDFIELD - -############################################################################################ -############################################################################################ - -REG -0x0055 -CH26_OFF -Channel Reset -ENDREG - -FIELD -[31:0] 0x00000000 -CH26_OFF -RW -The offset (from frame count equal zero), when CH26 is reset. This register is implemented if ''CHANNEL_COUNT''>26. -ENDFIELD - -############################################################################################ -############################################################################################ - -REG -0x0056 -CH27_ON -Channel Set -ENDREG - -FIELD -[31:0] 0x00000000 -CH27_ON -RW -The offset (from frame count equal zero), when CH27 is set. This register is implemented if ''CHANNEL_COUNT''>27. -ENDFIELD - -############################################################################################ -############################################################################################ - -REG -0x0057 -CH27_OFF -Channel Reset -ENDREG - -FIELD -[31:0] 0x00000000 -CH27_OFF -RW -The offset (from frame count equal zero), when CH27 is reset. This register is implemented if ''CHANNEL_COUNT''>27. -ENDFIELD - -############################################################################################ -############################################################################################ - -REG -0x0058 -CH28_ON -Channel Set -ENDREG - -FIELD -[31:0] 0x00000000 -CH28_ON -RW -The offset (from frame count equal zero), when CH28 is set. This register is implemented if ''CHANNEL_COUNT''>28. -ENDFIELD - -############################################################################################ -############################################################################################ - -REG -0x0059 -CH28_OFF -Channel Reset -ENDREG - -FIELD -[31:0] 0x00000000 -CH28_OFF -RW -The offset (from frame count equal zero), when CH28 is reset. This register is implemented if ''CHANNEL_COUNT''>28. -ENDFIELD - -############################################################################################ -############################################################################################ - -REG -0x005A -CH29_ON -Channel Set -ENDREG - -FIELD -[31:0] 0x00000000 -CH29_ON -RW -The offset (from frame count equal zero), when CH29 is set. This register is implemented if ''CHANNEL_COUNT''>29. -ENDFIELD - -############################################################################################ -############################################################################################ - -REG -0x005B -CH29_OFF -Channel Reset -ENDREG - -FIELD -[31:0] 0x00000000 -CH29_OFF -RW -The offset (from frame count equal zero), when CH29 is reset. This register is implemented if ''CHANNEL_COUNT''>29. -ENDFIELD - -############################################################################################ -############################################################################################ - -REG -0x005C -CH30_ON -Channel Set -ENDREG - -FIELD -[31:0] 0x00000000 -CH30_ON -RW -The offset (from frame count equal zero), when CH30 is set. This register is implemented if ''CHANNEL_COUNT''>30. -ENDFIELD - -############################################################################################ -############################################################################################ - -REG -0x005D -CH30_OFF -Channel Reset -ENDREG - -FIELD -[31:0] 0x00000000 -CH30_OFF -RW -The offset (from frame count equal zero), when CH30 is reset. This register is implemented if ''CHANNEL_COUNT''>30. -ENDFIELD - -############################################################################################ -############################################################################################ - -REG -0x005E -CH31_ON -Channel Set -ENDREG - -FIELD -[31:0] 0x00000000 -CH31_ON -RW -The offset (from frame count equal zero), when CH31 is set. This register is implemented if ''CHANNEL_COUNT''>31. -ENDFIELD - -############################################################################################ -############################################################################################ - -REG -0x005F -CH31_OFF -Channel Reset -ENDREG - -FIELD -[31:0] 0x00000000 -CH31_OFF -RW -The offset (from frame count equal zero), when CH31 is reset. This register is implemented if ''CHANNEL_COUNT''>31. -ENDFIELD - -############################################################################################ -############################################################################################ - diff --git a/docs/regmap/adi_regmap_tdd_trans.txt b/docs/regmap/adi_regmap_tdd_trans.txt index 9c9ade5db..e5ff99ea8 100644 --- a/docs/regmap/adi_regmap_tdd_trans.txt +++ b/docs/regmap/adi_regmap_tdd_trans.txt @@ -8,12 +8,12 @@ ENDTITLE REG 0x0010 -REG_TDD_CONTROL_0 +TDD_CONTROL_0 TDD Control & Status ENDREG FIELD -[5] 0x0 +[5] 0x00000000 TDD_GATED_TX_DMAPATH RW If this bit is set, the core requests data from the TX DMA, just when the data path is active. @@ -22,7 +22,7 @@ facilitate debug. This bit must be SET to preserve data integrity. ENDFIELD FIELD -[4] 0x0 +[4] 0x00000000 TDD_GATED_RX_DMAPATH RW If this bit is set, the core provides data for the RX DMA, just when the data path is active. @@ -31,7 +31,7 @@ facilitate debug. This bit must be SET to preserve data integrity. ENDFIELD FIELD -[3] 0x0 +[3] 0x00000000 TDD_TXONLY RW If this bit is set- the TDD controller ignores all the TX_* timing registers @@ -39,7 +39,7 @@ below and assumes continuous receive operation within a frame. ENDFIELD FIELD -[2] 0x0 +[2] 0x00000000 TDD_RXONLY RW If this bit is set- the TDD controller ignores all the RX_* timing registers @@ -47,7 +47,7 @@ below and assumes continuous transmit operation within a frame. ENDFIELD FIELD -[1] 0x0 +[1] 0x00000000 TDD_SECONDARY RW Enable the secondary transmit/receive on the active frame. If this bit is clear - @@ -56,7 +56,7 @@ the controller uses the _1 and _2 timing registers below. ENDFIELD FIELD -[0] 0x0 +[0] 0x00000000 TDD_ENABLE RW If set, enables the TDD controller- software must set this bit after programming @@ -71,12 +71,12 @@ ENDFIELD REG 0x0011 -REG_TDD_CONTROL_1 +TDD_CONTROL_1 TDD Control & Status ENDREG FIELD -[7:0] 0x00 +[7:0] 0x00000000 TDD_BURST_COUNT RW If set to 0x0 and enabled (TDD_ENABLE is set) - the controller operates in TDD mode @@ -89,12 +89,12 @@ ENDFIELD REG 0x0012 -REG_TDD_CONTROL_2 +TDD_CONTROL_2 TDD Control & Status ENDREG FIELD -[23:0] 0x000000 +[23:0] 0x00000000 TDD_COUNTER_INIT RW The controller sets the frame counter to this value when starting TDD operation. @@ -106,12 +106,12 @@ ENDFIELD REG 0x0013 -REG_TDD_FRAME_LENGTH +TDD_FRAME_LENGTH TDD Control & Status ENDREG FIELD -[23:0] 0x000000 +[23:0] 0x00000000 TDD_FRAME_LENGTH RW The frame length is the terminal count for the 10ms counter running at the digital @@ -123,12 +123,12 @@ ENDFIELD REG 0x0014 -REG_TDD_SYNC_TERMINAL_TYPE +TDD_SYNC_TERMINAL_TYPE TDD Control & Status ENDREG FIELD -[0] 0x0 +[0] 0x00000000 TDD_SYNC_TERMINAL_TYPE RW Set this bit, if the current terminal will generate the syncronization pulse, reset otherwise. @@ -139,19 +139,19 @@ ENDFIELD REG 0x0018 -REG_TDD_STATUS +TDD_STATUS TDD Control & Status ENDREG FIELD -[0] 0x0 +[0] 0x00000000 TDD_RXTX_VCO_OVERLAP RO This bit is asserted, if exist a time interval when both the TX and RX VCOs are powered up. ENDFIELD FIELD -[1] 0x0 +[1] 0x00000000 TDD_RXTX_RF_OVERLAP RO This bit is asserted, if exist a time interval when both the TX and RX RF datapath are powered up. @@ -162,12 +162,12 @@ ENDFIELD REG 0x0020 -REG_TDD_VCO_RX_ON_1 +TDD_VCO_RX_ON_1 TDD Control & Status ENDREG FIELD -[23:0] 0x000000 +[23:0] 0x00000000 TDD_VCO_RX_ON_1 RW Defines the offset (from frame count equal zero), when the RX VCO powers up at the first time. @@ -181,12 +181,12 @@ ENDFIELD REG 0x0021 -REG_TDD_VCO_RX_OFF_1 +TDD_VCO_RX_OFF_1 TDD Control & Status ENDREG FIELD -[23:0] 0x000000 +[23:0] 0x00000000 TDD_VCO_RX_OFF_1 RW Defines the offset (from frame count equal zero), when the RX VCO powers down at the first @@ -200,12 +200,12 @@ ENDFIELD REG 0x0022 -REG_TDD_VCO_TX_ON_1 +TDD_VCO_TX_ON_1 TDD Control & Status ENDREG FIELD -[23:0] 0x000000 +[23:0] 0x00000000 TDD_VCO_TX_ON_1 RW Defines the offset (from frame count equal zero), when the TX VCO powers up at the first time. @@ -218,12 +218,12 @@ ENDFIELD REG 0x0023 -REG_TDD_VCO_TX_OFF_1 +TDD_VCO_TX_OFF_1 TDD Control & Status ENDREG FIELD -[23:0] 0x000000 +[23:0] 0x00000000 TDD_VCO_TX_OFF_1 RW Defines the offset (from frame count equal zero), when the TX VCO powers down at the first @@ -237,12 +237,12 @@ ENDFIELD REG 0x0024 -REG_TDD_RX_ON_1 +TDD_RX_ON_1 TDD Control & Status ENDREG FIELD -[23:0] 0x000000 +[23:0] 0x00000000 TDD_RX_ON_1 RW Defines the offset (from frame count equal zero), when the RX data path is activated at the @@ -255,12 +255,12 @@ ENDFIELD REG 0x0025 -REG_TDD_RX_OFF_1 +TDD_RX_OFF_1 TDD Control & Status ENDREG FIELD -[23:0] 0x000000 +[23:0] 0x00000000 TDD_RX_OFF_1 RW Defines the offset (from frame count equal zero), when the RX data path is deactivated the @@ -274,12 +274,12 @@ ENDFIELD REG 0x0026 -REG_TDD_TX_ON_1 +TDD_TX_ON_1 TDD Control & Status ENDREG FIELD -[23:0] 0x000000 +[23:0] 0x00000000 TDD_TX_ON_1 RW Defines the offset (from frame count equal zero), when the TX data path is activated at the @@ -294,12 +294,12 @@ ENDFIELD REG 0x0027 -REG_TDD_TX_OFF_1 +TDD_TX_OFF_1 TDD Control & Status ENDREG FIELD -[23:0] 0x000000 +[23:0] 0x00000000 TDD_TX_OFF_1 RW Defines the offset (from frame count equal zero), when the TX data path is deactivated at the @@ -314,12 +314,12 @@ ENDFIELD REG 0x0028 -REG_TDD_RX_DP_ON_1 +TDD_RX_DP_ON_1 TDD Control & Status ENDREG FIELD -[23:0] 0x000000 +[23:0] 0x00000000 TDD_RX_DP_ON_1 RW Defines the offset (from frame count equal zero), when the controller starts to accept data from @@ -331,12 +331,12 @@ ENDFIELD REG 0x0029 -REG_TDD_RX_DP_OFF_1 +TDD_RX_DP_OFF_1 TDD Control & Status ENDREG FIELD -[23:0] 0x000000 +[23:0] 0x00000000 TDD_RX_DP_OFF_1 RW Defines the offset (from frame count equal zero), when the controller stops to accept data from @@ -349,12 +349,12 @@ ENDFIELD REG 0x002A -REG_TDD_TX_DP_ON_1 +TDD_TX_DP_ON_1 TDD Control & Status ENDREG FIELD -[23:0] 0x000000 +[23:0] 0x00000000 TDD_TX_DP_ON_1 RW Defines the offset (from frame count equal zero), when the controller starts to request data from the system @@ -366,12 +366,12 @@ ENDFIELD REG 0x002B -REG_TDD_TX_DP_OFF_1 +TDD_TX_DP_OFF_1 TDD Control & Status ENDREG FIELD -[23:0] 0x000000 +[23:0] 0x00000000 TDD_TX_DP_OFF_1 RW Defines the offset (from frame count equal zero), when the controller stop requesting data from the system @@ -383,12 +383,12 @@ ENDFIELD REG 0x0030 -REG_TDD_VCO_RX_ON_2 +TDD_VCO_RX_ON_2 TDD Control & Status ENDREG FIELD -[23:0] 0x000000 +[23:0] 0x00000000 TDD_VCO_RX_ON_2 RW The secondary pointer for VCO_RX_ON. @@ -399,12 +399,12 @@ ENDFIELD REG 0x0031 -REG_TDD_VCO_RX_OFF_2 +TDD_VCO_RX_OFF_2 TDD Control & Status ENDREG FIELD -[23:0] 0x000000 +[23:0] 0x00000000 TDD_VCO_RX_OFF_2 RW The secondary pointer for VCO_RX_OFF. @@ -415,12 +415,12 @@ ENDFIELD REG 0x0032 -REG_TDD_VCO_TX_ON_2 +TDD_VCO_TX_ON_2 TDD Control & Status ENDREG FIELD -[23:0] 0x000000 +[23:0] 0x00000000 TDD_VCO_TX_ON_2 RW The secondary pointer for VCO_TX_ON. @@ -431,12 +431,12 @@ ENDFIELD REG 0x0033 -REG_TDD_VCO_TX_OFF_2 +TDD_VCO_TX_OFF_2 TDD Control & Status ENDREG FIELD -[23:0] 0x000000 +[23:0] 0x00000000 TDD_VCO_TX_OFF_2 RW The secondary pointer for VCO_TX_OFF. @@ -447,12 +447,12 @@ ENDFIELD REG 0x0034 -REG_TDD_RX_ON_2 +TDD_RX_ON_2 TDD Control & Status ENDREG FIELD -[23:0] 0x000000 +[23:0] 0x00000000 TDD_RX_ON_2 RW The secondary pointer for RX_ON. @@ -463,12 +463,12 @@ ENDFIELD REG 0x0035 -REG_TDD_RX_OFF_2 +TDD_RX_OFF_2 TDD Control & Status ENDREG FIELD -[23:0] 0x000000 +[23:0] 0x00000000 TDD_RX_OFF_2 RW The secondary pointer for RX_OFF. @@ -479,12 +479,12 @@ ENDFIELD REG 0x0036 -REG_TDD_TX_ON_2 +TDD_TX_ON_2 TDD Control & Status ENDREG FIELD -[23:0] 0x000000 +[23:0] 0x00000000 TDD_TX_ON_2 RW The secondary pointer for TX_ON. @@ -495,12 +495,12 @@ ENDFIELD REG 0x0037 -REG_TDD_TX_OFF_2 +TDD_TX_OFF_2 TDD Control & Status ENDREG FIELD -[23:0] 0x000000 +[23:0] 0x00000000 TDD_TX_OFF_2 RW The secondary pointer for TX_OFF. @@ -511,12 +511,12 @@ ENDFIELD REG 0x0038 -REG_TDD_RX_DP_ON_2 +TDD_RX_DP_ON_2 TDD Control & Status ENDREG FIELD -[23:0] 0x000000 +[23:0] 0x00000000 TDD_RX_DP_ON_2 RW The secondary pointer for RX_DP_ON. @@ -527,12 +527,12 @@ ENDFIELD REG 0x0039 -REG_TDD_RX_DP_OFF_2 +TDD_RX_DP_OFF_2 TDD Control & Status ENDREG FIELD -[23:0] 0x000000 +[23:0] 0x00000000 TDD_RX_DP_OFF_2 RW The secondary pointer for RX_DP_OFF. @@ -543,12 +543,12 @@ ENDFIELD REG 0x003A -REG_TDD_TX_DP_ON_2 +TDD_TX_DP_ON_2 TDD Control & Status ENDREG FIELD -[23:0] 0x000000 +[23:0] 0x00000000 TDD_TX_DP_ON_2 RW The secondary pointer for TX_DP_ON. @@ -559,12 +559,12 @@ ENDFIELD REG 0x003B -REG_TDD_TX_DP_OFF_2 +TDD_TX_DP_OFF_2 TDD Control & Status ENDREG FIELD -[23:0] 0x000000 +[23:0] 0x00000000 TDD_TX_DP_OFF_2 RW The secondary pointer for TX_DP_OFF. @@ -572,4 +572,3 @@ ENDFIELD ############################################################################################ ############################################################################################ -