docs: axi_tdd: Add TDD docs (#1334)
Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Ionut Podgoreanu <ionut.podgoreanu@analog.com>main
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@ -0,0 +1,192 @@
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.. _axi_tdd:
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AXI TDD
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================================================================================
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.. hdl-component-diagram::
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The :git-hdl:`AXI Time-Division Duplexing <library/axi_tdd>` Controller IP core
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is a pulse wave generator capable of addressing RF applications which require
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Time Division Duplexing, as well as controlling other modules of general
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applications through its dedicated 32 channel outputs.
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The reason of creating the generic TDD controller was to reduce the naming
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confusion around the existing repurposed
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:dokuwiki:`TDD core <resources/eval/user-guides/ad-pzsdr2400tdd-eb/reference_hdl#TDD Controller>`
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built for AD9361, as well as expanding its number of output channels for systems
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which require more than six controlling signals.
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.. note::
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TDD (Time-Division Duplex) mode allows the user to control the time period of
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the receive and transmit bursts.
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Features
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--------------------------------------------------------------------------------
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* Up to 32 independent output channels
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* Start/stop time values per channel
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* Enable and polarity bit values per channel
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* 32 bit-max internal reference counter
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* Initial startup delay before wave generation
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* Configurable frame length and number of frames per burst
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* 3 sources of synchronization: external, internal and software generated
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Files
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--------------------------------------------------------------------------------
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.. list-table::
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:header-rows: 1
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||||||
|
|
||||||
|
* - Name
|
||||||
|
- Description
|
||||||
|
* - :git-hdl:`library/axi_tdd/axi_tdd.sv`
|
||||||
|
- Top module.
|
||||||
|
* - :git-hdl:`library/axi_tdd/axi_tdd_pkg.sv`
|
||||||
|
- SystemVerilog Package.
|
||||||
|
* - :git-hdl:`library/axi_tdd/axi_tdd_regmap.sv`
|
||||||
|
- Register Map with CDC synchronizers.
|
||||||
|
* - :git-hdl:`library/axi_tdd/axi_tdd_counter.sv`
|
||||||
|
- Internal counters and FSM logic.
|
||||||
|
* - :git-hdl:`library/axi_tdd/axi_tdd_channel.sv`
|
||||||
|
- Channel waveform generator.
|
||||||
|
* - :git-hdl:`library/axi_tdd/axi_tdd_sync_gen.sv`
|
||||||
|
- Synchronization pulse generator.
|
||||||
|
* - :git-hdl:`library/axi_tdd/axi_tdd_ip.tcl`
|
||||||
|
- TCL script to generate the Vivado IP-integrator project.
|
||||||
|
* - :git-hdl:`library/axi_tdd/axi_tdd_hw.tcl`
|
||||||
|
- TCL script to generate the Quartus IP-integrator project.
|
||||||
|
|
||||||
|
Configuration Parameters
|
||||||
|
--------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
.. hdl-parameters::
|
||||||
|
|
||||||
|
* - ID
|
||||||
|
- Instance identification number
|
||||||
|
* - CHANNEL_COUNT
|
||||||
|
- Number of channels
|
||||||
|
* - DEFAULT_POLARITY
|
||||||
|
- Initial channel polarity
|
||||||
|
* - REGISTER_WIDTH
|
||||||
|
- Internal counter and register width
|
||||||
|
* - BURST_COUNT_WIDTH
|
||||||
|
- Burst counter width
|
||||||
|
* - SYNC_INTERNAL
|
||||||
|
- Enable support for internal sync signal
|
||||||
|
* - SYNC_EXTERNAL
|
||||||
|
- Enable support for external sync signal
|
||||||
|
* - SYNC_EXTERNAL_CDC
|
||||||
|
- Enable synchronization of external sync signal
|
||||||
|
* - SYNC_COUNT_WIDTH
|
||||||
|
- Sync generator counter width
|
||||||
|
|
||||||
|
|
||||||
|
Interface
|
||||||
|
--------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
.. hdl-interfaces::
|
||||||
|
|
||||||
|
* - s_axi_aclk
|
||||||
|
- System clock.
|
||||||
|
* - s_axi_aresetn
|
||||||
|
- System reset, synchronous active low reset.
|
||||||
|
* - s_axi
|
||||||
|
- AXI-Lite bus slave, memory mapped AXI-Lite bus that provides access to module's
|
||||||
|
register map.
|
||||||
|
* - clk
|
||||||
|
- Core clock.
|
||||||
|
* - resetn
|
||||||
|
- Core reset, synchronous active low reset.
|
||||||
|
* - sync_in
|
||||||
|
- External synchronization input signal.
|
||||||
|
* - sync_out
|
||||||
|
- Module synchronization output signal.
|
||||||
|
* - tdd_channel
|
||||||
|
- Channels output.
|
||||||
|
|
||||||
|
Theory of Operation
|
||||||
|
--------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
The central idea of the TDD controller is “frame”-based operation, i.e. all the
|
||||||
|
timing defined for the individual channels is relative to the beginning of a
|
||||||
|
frame. The ``FRAME_LENGTH`` value controls the length of a single frame, while
|
||||||
|
the ``BURST_COUNT`` value controls how many frames should be played after
|
||||||
|
enabling the device (a value of 0 means the frames will be repeated indefinitely).
|
||||||
|
Before the start of a burst, an optional startup delay is inserted, defined by
|
||||||
|
the ``STARTUP_DELAY`` value in clock cycles.
|
||||||
|
|
||||||
|
.. image:: diagram.svg
|
||||||
|
|
||||||
|
This diagram illustrates how different channels can be enabled at different
|
||||||
|
times relative to the beginning of a frame.
|
||||||
|
|
||||||
|
.. note::
|
||||||
|
|
||||||
|
While the above graphic shows all channels being enabled in a stacked
|
||||||
|
manner, they are completely independent of each other.
|
||||||
|
|
||||||
|
Detailed Description
|
||||||
|
--------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
In order to begin its operation, the peripheral must be enabled. This is done by
|
||||||
|
setting the ``ENABLE`` bit. Next, the peripheral waits to receive a synchronization
|
||||||
|
signal. There are 3 possible sync sources, which can be independently activated
|
||||||
|
through their corresponding enabling bits: ``SYNC_INT``, ``SYNC_EXT`` and ``SYNC_SOFT``
|
||||||
|
can all be active at the same time.
|
||||||
|
|
||||||
|
The external synchronization capability allows the alignment of frames between
|
||||||
|
multiple devices in different locations, for example using a GPSDO 1 PPS output.
|
||||||
|
The internal sync signal is generated based on a dedicated counter, when its
|
||||||
|
value matches the one defined in ``SYNC_COUNTER_LOW`` / ``SYNC_COUNTER_HIGH``.
|
||||||
|
The software generated sync pulse is triggered at an arbitrary point in time
|
||||||
|
when writing a ‘1’ value in ``SYNC_SOFT``.
|
||||||
|
|
||||||
|
The next diagram shows the peripheral’s FSM, which transitions between 4 states:
|
||||||
|
IDLE, ARMED, WAITING and RUNNING.
|
||||||
|
|
||||||
|
.. image:: fsm.svg
|
||||||
|
|
||||||
|
In case a synchronization signal is received while the TDD core is running, the
|
||||||
|
signal can reset the internal counter to zero by setting ``SYNC_RST`` to ‘1’.
|
||||||
|
This can alter the counter value in both WAITING or RUNNING states.
|
||||||
|
|
||||||
|
The generic TDD controller can have up to 32 output channels, each of them
|
||||||
|
having its unique values when the channel is set/reset under ``CHX_ON`` /
|
||||||
|
``CHX_OFF``. They are continuously compared to the internal counter’s value
|
||||||
|
while the core is RUNNING.
|
||||||
|
|
||||||
|
Every bit in ``CHANNEL_ENABLE`` / ``CHANNEL_POLARITY`` corresponds to a specific
|
||||||
|
channel. The bit position is correlated to the channel index, so the LSB will
|
||||||
|
always be associated with CH0 and the MSB with CH31.
|
||||||
|
|
||||||
|
The following registers will not be updated unless the peripheral is disabled:
|
||||||
|
|
||||||
|
- ``BURST_COUNT``
|
||||||
|
- ``STARTUP_DELAY``
|
||||||
|
- ``FRAME_LENGTH``
|
||||||
|
- ``CHANNEL_POLARITY``
|
||||||
|
- ``SYNC_COUNTER_LOW``
|
||||||
|
- ``SYNC_COUNTER_HIGH``
|
||||||
|
- ``CHX_ON``
|
||||||
|
- ``CHX_OFF``
|
||||||
|
|
||||||
|
The user must configure them before enabling the peripheral. Any subsequent
|
||||||
|
write while the peripheral is enabled will be ignored.
|
||||||
|
|
||||||
|
An exception to this rule is ``CHANNEL_ENABLE``, which allows enabling /
|
||||||
|
disabling independent channels on-the-fly. The new value will come into effect
|
||||||
|
when in ARMED state or at the end of a frame. ``CONTROL`` can also be modified
|
||||||
|
on-the-fly with immediate effect (after going through the synchronization stage).
|
||||||
|
|
||||||
|
``STATUS`` can be used for debugging purposes, reflecting the current peripheral
|
||||||
|
state.
|
||||||
|
|
||||||
|
By adapting the synthesis parameters to the application requirements, the module
|
||||||
|
is highly flexible and can substantially reduce resource utilization.
|
||||||
|
|
||||||
|
Register Map
|
||||||
|
--------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
.. hdl-regmap::
|
||||||
|
:name: TDDN_CNTRL
|
||||||
File diff suppressed because it is too large
Load Diff
|
|
@ -8,12 +8,12 @@ ENDTITLE
|
||||||
|
|
||||||
REG
|
REG
|
||||||
0x0010
|
0x0010
|
||||||
REG_TDD_CONTROL_0
|
TDD_CONTROL_0
|
||||||
TDD Control & Status
|
TDD Control & Status
|
||||||
ENDREG
|
ENDREG
|
||||||
|
|
||||||
FIELD
|
FIELD
|
||||||
[5] 0x0
|
[5] 0x00000000
|
||||||
TDD_GATED_TX_DMAPATH
|
TDD_GATED_TX_DMAPATH
|
||||||
RW
|
RW
|
||||||
If this bit is set, the core requests data from the TX DMA, just when the data path is active.
|
If this bit is set, the core requests data from the TX DMA, just when the data path is active.
|
||||||
|
|
@ -22,7 +22,7 @@ facilitate debug. This bit must be SET to preserve data integrity.
|
||||||
ENDFIELD
|
ENDFIELD
|
||||||
|
|
||||||
FIELD
|
FIELD
|
||||||
[4] 0x0
|
[4] 0x00000000
|
||||||
TDD_GATED_RX_DMAPATH
|
TDD_GATED_RX_DMAPATH
|
||||||
RW
|
RW
|
||||||
If this bit is set, the core provides data for the RX DMA, just when the data path is active.
|
If this bit is set, the core provides data for the RX DMA, just when the data path is active.
|
||||||
|
|
@ -31,7 +31,7 @@ facilitate debug. This bit must be SET to preserve data integrity.
|
||||||
ENDFIELD
|
ENDFIELD
|
||||||
|
|
||||||
FIELD
|
FIELD
|
||||||
[3] 0x0
|
[3] 0x00000000
|
||||||
TDD_TXONLY
|
TDD_TXONLY
|
||||||
RW
|
RW
|
||||||
If this bit is set- the TDD controller ignores all the TX_* timing registers
|
If this bit is set- the TDD controller ignores all the TX_* timing registers
|
||||||
|
|
@ -39,7 +39,7 @@ below and assumes continuous receive operation within a frame.
|
||||||
ENDFIELD
|
ENDFIELD
|
||||||
|
|
||||||
FIELD
|
FIELD
|
||||||
[2] 0x0
|
[2] 0x00000000
|
||||||
TDD_RXONLY
|
TDD_RXONLY
|
||||||
RW
|
RW
|
||||||
If this bit is set- the TDD controller ignores all the RX_* timing registers
|
If this bit is set- the TDD controller ignores all the RX_* timing registers
|
||||||
|
|
@ -47,7 +47,7 @@ below and assumes continuous transmit operation within a frame.
|
||||||
ENDFIELD
|
ENDFIELD
|
||||||
|
|
||||||
FIELD
|
FIELD
|
||||||
[1] 0x0
|
[1] 0x00000000
|
||||||
TDD_SECONDARY
|
TDD_SECONDARY
|
||||||
RW
|
RW
|
||||||
Enable the secondary transmit/receive on the active frame. If this bit is clear -
|
Enable the secondary transmit/receive on the active frame. If this bit is clear -
|
||||||
|
|
@ -56,7 +56,7 @@ the controller uses the _1 and _2 timing registers below.
|
||||||
ENDFIELD
|
ENDFIELD
|
||||||
|
|
||||||
FIELD
|
FIELD
|
||||||
[0] 0x0
|
[0] 0x00000000
|
||||||
TDD_ENABLE
|
TDD_ENABLE
|
||||||
RW
|
RW
|
||||||
If set, enables the TDD controller- software must set this bit after programming
|
If set, enables the TDD controller- software must set this bit after programming
|
||||||
|
|
@ -71,12 +71,12 @@ ENDFIELD
|
||||||
|
|
||||||
REG
|
REG
|
||||||
0x0011
|
0x0011
|
||||||
REG_TDD_CONTROL_1
|
TDD_CONTROL_1
|
||||||
TDD Control & Status
|
TDD Control & Status
|
||||||
ENDREG
|
ENDREG
|
||||||
|
|
||||||
FIELD
|
FIELD
|
||||||
[7:0] 0x00
|
[7:0] 0x00000000
|
||||||
TDD_BURST_COUNT
|
TDD_BURST_COUNT
|
||||||
RW
|
RW
|
||||||
If set to 0x0 and enabled (TDD_ENABLE is set) - the controller operates in TDD mode
|
If set to 0x0 and enabled (TDD_ENABLE is set) - the controller operates in TDD mode
|
||||||
|
|
@ -89,12 +89,12 @@ ENDFIELD
|
||||||
|
|
||||||
REG
|
REG
|
||||||
0x0012
|
0x0012
|
||||||
REG_TDD_CONTROL_2
|
TDD_CONTROL_2
|
||||||
TDD Control & Status
|
TDD Control & Status
|
||||||
ENDREG
|
ENDREG
|
||||||
|
|
||||||
FIELD
|
FIELD
|
||||||
[23:0] 0x000000
|
[23:0] 0x00000000
|
||||||
TDD_COUNTER_INIT
|
TDD_COUNTER_INIT
|
||||||
RW
|
RW
|
||||||
The controller sets the frame counter to this value when starting TDD operation.
|
The controller sets the frame counter to this value when starting TDD operation.
|
||||||
|
|
@ -106,12 +106,12 @@ ENDFIELD
|
||||||
|
|
||||||
REG
|
REG
|
||||||
0x0013
|
0x0013
|
||||||
REG_TDD_FRAME_LENGTH
|
TDD_FRAME_LENGTH
|
||||||
TDD Control & Status
|
TDD Control & Status
|
||||||
ENDREG
|
ENDREG
|
||||||
|
|
||||||
FIELD
|
FIELD
|
||||||
[23:0] 0x000000
|
[23:0] 0x00000000
|
||||||
TDD_FRAME_LENGTH
|
TDD_FRAME_LENGTH
|
||||||
RW
|
RW
|
||||||
The frame length is the terminal count for the 10ms counter running at the digital
|
The frame length is the terminal count for the 10ms counter running at the digital
|
||||||
|
|
@ -123,12 +123,12 @@ ENDFIELD
|
||||||
|
|
||||||
REG
|
REG
|
||||||
0x0014
|
0x0014
|
||||||
REG_TDD_SYNC_TERMINAL_TYPE
|
TDD_SYNC_TERMINAL_TYPE
|
||||||
TDD Control & Status
|
TDD Control & Status
|
||||||
ENDREG
|
ENDREG
|
||||||
|
|
||||||
FIELD
|
FIELD
|
||||||
[0] 0x0
|
[0] 0x00000000
|
||||||
TDD_SYNC_TERMINAL_TYPE
|
TDD_SYNC_TERMINAL_TYPE
|
||||||
RW
|
RW
|
||||||
Set this bit, if the current terminal will generate the syncronization pulse, reset otherwise.
|
Set this bit, if the current terminal will generate the syncronization pulse, reset otherwise.
|
||||||
|
|
@ -139,19 +139,19 @@ ENDFIELD
|
||||||
|
|
||||||
REG
|
REG
|
||||||
0x0018
|
0x0018
|
||||||
REG_TDD_STATUS
|
TDD_STATUS
|
||||||
TDD Control & Status
|
TDD Control & Status
|
||||||
ENDREG
|
ENDREG
|
||||||
|
|
||||||
FIELD
|
FIELD
|
||||||
[0] 0x0
|
[0] 0x00000000
|
||||||
TDD_RXTX_VCO_OVERLAP
|
TDD_RXTX_VCO_OVERLAP
|
||||||
RO
|
RO
|
||||||
This bit is asserted, if exist a time interval when both the TX and RX VCOs are powered up.
|
This bit is asserted, if exist a time interval when both the TX and RX VCOs are powered up.
|
||||||
ENDFIELD
|
ENDFIELD
|
||||||
|
|
||||||
FIELD
|
FIELD
|
||||||
[1] 0x0
|
[1] 0x00000000
|
||||||
TDD_RXTX_RF_OVERLAP
|
TDD_RXTX_RF_OVERLAP
|
||||||
RO
|
RO
|
||||||
This bit is asserted, if exist a time interval when both the TX and RX RF datapath are powered up.
|
This bit is asserted, if exist a time interval when both the TX and RX RF datapath are powered up.
|
||||||
|
|
@ -162,12 +162,12 @@ ENDFIELD
|
||||||
|
|
||||||
REG
|
REG
|
||||||
0x0020
|
0x0020
|
||||||
REG_TDD_VCO_RX_ON_1
|
TDD_VCO_RX_ON_1
|
||||||
TDD Control & Status
|
TDD Control & Status
|
||||||
ENDREG
|
ENDREG
|
||||||
|
|
||||||
FIELD
|
FIELD
|
||||||
[23:0] 0x000000
|
[23:0] 0x00000000
|
||||||
TDD_VCO_RX_ON_1
|
TDD_VCO_RX_ON_1
|
||||||
RW
|
RW
|
||||||
Defines the offset (from frame count equal zero), when the RX VCO powers up at the first time.
|
Defines the offset (from frame count equal zero), when the RX VCO powers up at the first time.
|
||||||
|
|
@ -181,12 +181,12 @@ ENDFIELD
|
||||||
|
|
||||||
REG
|
REG
|
||||||
0x0021
|
0x0021
|
||||||
REG_TDD_VCO_RX_OFF_1
|
TDD_VCO_RX_OFF_1
|
||||||
TDD Control & Status
|
TDD Control & Status
|
||||||
ENDREG
|
ENDREG
|
||||||
|
|
||||||
FIELD
|
FIELD
|
||||||
[23:0] 0x000000
|
[23:0] 0x00000000
|
||||||
TDD_VCO_RX_OFF_1
|
TDD_VCO_RX_OFF_1
|
||||||
RW
|
RW
|
||||||
Defines the offset (from frame count equal zero), when the RX VCO powers down at the first
|
Defines the offset (from frame count equal zero), when the RX VCO powers down at the first
|
||||||
|
|
@ -200,12 +200,12 @@ ENDFIELD
|
||||||
|
|
||||||
REG
|
REG
|
||||||
0x0022
|
0x0022
|
||||||
REG_TDD_VCO_TX_ON_1
|
TDD_VCO_TX_ON_1
|
||||||
TDD Control & Status
|
TDD Control & Status
|
||||||
ENDREG
|
ENDREG
|
||||||
|
|
||||||
FIELD
|
FIELD
|
||||||
[23:0] 0x000000
|
[23:0] 0x00000000
|
||||||
TDD_VCO_TX_ON_1
|
TDD_VCO_TX_ON_1
|
||||||
RW
|
RW
|
||||||
Defines the offset (from frame count equal zero), when the TX VCO powers up at the first time.
|
Defines the offset (from frame count equal zero), when the TX VCO powers up at the first time.
|
||||||
|
|
@ -218,12 +218,12 @@ ENDFIELD
|
||||||
|
|
||||||
REG
|
REG
|
||||||
0x0023
|
0x0023
|
||||||
REG_TDD_VCO_TX_OFF_1
|
TDD_VCO_TX_OFF_1
|
||||||
TDD Control & Status
|
TDD Control & Status
|
||||||
ENDREG
|
ENDREG
|
||||||
|
|
||||||
FIELD
|
FIELD
|
||||||
[23:0] 0x000000
|
[23:0] 0x00000000
|
||||||
TDD_VCO_TX_OFF_1
|
TDD_VCO_TX_OFF_1
|
||||||
RW
|
RW
|
||||||
Defines the offset (from frame count equal zero), when the TX VCO powers down at the first
|
Defines the offset (from frame count equal zero), when the TX VCO powers down at the first
|
||||||
|
|
@ -237,12 +237,12 @@ ENDFIELD
|
||||||
|
|
||||||
REG
|
REG
|
||||||
0x0024
|
0x0024
|
||||||
REG_TDD_RX_ON_1
|
TDD_RX_ON_1
|
||||||
TDD Control & Status
|
TDD Control & Status
|
||||||
ENDREG
|
ENDREG
|
||||||
|
|
||||||
FIELD
|
FIELD
|
||||||
[23:0] 0x000000
|
[23:0] 0x00000000
|
||||||
TDD_RX_ON_1
|
TDD_RX_ON_1
|
||||||
RW
|
RW
|
||||||
Defines the offset (from frame count equal zero), when the RX data path is activated at the
|
Defines the offset (from frame count equal zero), when the RX data path is activated at the
|
||||||
|
|
@ -255,12 +255,12 @@ ENDFIELD
|
||||||
|
|
||||||
REG
|
REG
|
||||||
0x0025
|
0x0025
|
||||||
REG_TDD_RX_OFF_1
|
TDD_RX_OFF_1
|
||||||
TDD Control & Status
|
TDD Control & Status
|
||||||
ENDREG
|
ENDREG
|
||||||
|
|
||||||
FIELD
|
FIELD
|
||||||
[23:0] 0x000000
|
[23:0] 0x00000000
|
||||||
TDD_RX_OFF_1
|
TDD_RX_OFF_1
|
||||||
RW
|
RW
|
||||||
Defines the offset (from frame count equal zero), when the RX data path is deactivated the
|
Defines the offset (from frame count equal zero), when the RX data path is deactivated the
|
||||||
|
|
@ -274,12 +274,12 @@ ENDFIELD
|
||||||
|
|
||||||
REG
|
REG
|
||||||
0x0026
|
0x0026
|
||||||
REG_TDD_TX_ON_1
|
TDD_TX_ON_1
|
||||||
TDD Control & Status
|
TDD Control & Status
|
||||||
ENDREG
|
ENDREG
|
||||||
|
|
||||||
FIELD
|
FIELD
|
||||||
[23:0] 0x000000
|
[23:0] 0x00000000
|
||||||
TDD_TX_ON_1
|
TDD_TX_ON_1
|
||||||
RW
|
RW
|
||||||
Defines the offset (from frame count equal zero), when the TX data path is activated at the
|
Defines the offset (from frame count equal zero), when the TX data path is activated at the
|
||||||
|
|
@ -294,12 +294,12 @@ ENDFIELD
|
||||||
|
|
||||||
REG
|
REG
|
||||||
0x0027
|
0x0027
|
||||||
REG_TDD_TX_OFF_1
|
TDD_TX_OFF_1
|
||||||
TDD Control & Status
|
TDD Control & Status
|
||||||
ENDREG
|
ENDREG
|
||||||
|
|
||||||
FIELD
|
FIELD
|
||||||
[23:0] 0x000000
|
[23:0] 0x00000000
|
||||||
TDD_TX_OFF_1
|
TDD_TX_OFF_1
|
||||||
RW
|
RW
|
||||||
Defines the offset (from frame count equal zero), when the TX data path is deactivated at the
|
Defines the offset (from frame count equal zero), when the TX data path is deactivated at the
|
||||||
|
|
@ -314,12 +314,12 @@ ENDFIELD
|
||||||
|
|
||||||
REG
|
REG
|
||||||
0x0028
|
0x0028
|
||||||
REG_TDD_RX_DP_ON_1
|
TDD_RX_DP_ON_1
|
||||||
TDD Control & Status
|
TDD Control & Status
|
||||||
ENDREG
|
ENDREG
|
||||||
|
|
||||||
FIELD
|
FIELD
|
||||||
[23:0] 0x000000
|
[23:0] 0x00000000
|
||||||
TDD_RX_DP_ON_1
|
TDD_RX_DP_ON_1
|
||||||
RW
|
RW
|
||||||
Defines the offset (from frame count equal zero), when the controller starts to accept data from
|
Defines the offset (from frame count equal zero), when the controller starts to accept data from
|
||||||
|
|
@ -331,12 +331,12 @@ ENDFIELD
|
||||||
|
|
||||||
REG
|
REG
|
||||||
0x0029
|
0x0029
|
||||||
REG_TDD_RX_DP_OFF_1
|
TDD_RX_DP_OFF_1
|
||||||
TDD Control & Status
|
TDD Control & Status
|
||||||
ENDREG
|
ENDREG
|
||||||
|
|
||||||
FIELD
|
FIELD
|
||||||
[23:0] 0x000000
|
[23:0] 0x00000000
|
||||||
TDD_RX_DP_OFF_1
|
TDD_RX_DP_OFF_1
|
||||||
RW
|
RW
|
||||||
Defines the offset (from frame count equal zero), when the controller stops to accept data from
|
Defines the offset (from frame count equal zero), when the controller stops to accept data from
|
||||||
|
|
@ -349,12 +349,12 @@ ENDFIELD
|
||||||
|
|
||||||
REG
|
REG
|
||||||
0x002A
|
0x002A
|
||||||
REG_TDD_TX_DP_ON_1
|
TDD_TX_DP_ON_1
|
||||||
TDD Control & Status
|
TDD Control & Status
|
||||||
ENDREG
|
ENDREG
|
||||||
|
|
||||||
FIELD
|
FIELD
|
||||||
[23:0] 0x000000
|
[23:0] 0x00000000
|
||||||
TDD_TX_DP_ON_1
|
TDD_TX_DP_ON_1
|
||||||
RW
|
RW
|
||||||
Defines the offset (from frame count equal zero), when the controller starts to request data from the system
|
Defines the offset (from frame count equal zero), when the controller starts to request data from the system
|
||||||
|
|
@ -366,12 +366,12 @@ ENDFIELD
|
||||||
|
|
||||||
REG
|
REG
|
||||||
0x002B
|
0x002B
|
||||||
REG_TDD_TX_DP_OFF_1
|
TDD_TX_DP_OFF_1
|
||||||
TDD Control & Status
|
TDD Control & Status
|
||||||
ENDREG
|
ENDREG
|
||||||
|
|
||||||
FIELD
|
FIELD
|
||||||
[23:0] 0x000000
|
[23:0] 0x00000000
|
||||||
TDD_TX_DP_OFF_1
|
TDD_TX_DP_OFF_1
|
||||||
RW
|
RW
|
||||||
Defines the offset (from frame count equal zero), when the controller stop requesting data from the system
|
Defines the offset (from frame count equal zero), when the controller stop requesting data from the system
|
||||||
|
|
@ -383,12 +383,12 @@ ENDFIELD
|
||||||
|
|
||||||
REG
|
REG
|
||||||
0x0030
|
0x0030
|
||||||
REG_TDD_VCO_RX_ON_2
|
TDD_VCO_RX_ON_2
|
||||||
TDD Control & Status
|
TDD Control & Status
|
||||||
ENDREG
|
ENDREG
|
||||||
|
|
||||||
FIELD
|
FIELD
|
||||||
[23:0] 0x000000
|
[23:0] 0x00000000
|
||||||
TDD_VCO_RX_ON_2
|
TDD_VCO_RX_ON_2
|
||||||
RW
|
RW
|
||||||
The secondary pointer for VCO_RX_ON.
|
The secondary pointer for VCO_RX_ON.
|
||||||
|
|
@ -399,12 +399,12 @@ ENDFIELD
|
||||||
|
|
||||||
REG
|
REG
|
||||||
0x0031
|
0x0031
|
||||||
REG_TDD_VCO_RX_OFF_2
|
TDD_VCO_RX_OFF_2
|
||||||
TDD Control & Status
|
TDD Control & Status
|
||||||
ENDREG
|
ENDREG
|
||||||
|
|
||||||
FIELD
|
FIELD
|
||||||
[23:0] 0x000000
|
[23:0] 0x00000000
|
||||||
TDD_VCO_RX_OFF_2
|
TDD_VCO_RX_OFF_2
|
||||||
RW
|
RW
|
||||||
The secondary pointer for VCO_RX_OFF.
|
The secondary pointer for VCO_RX_OFF.
|
||||||
|
|
@ -415,12 +415,12 @@ ENDFIELD
|
||||||
|
|
||||||
REG
|
REG
|
||||||
0x0032
|
0x0032
|
||||||
REG_TDD_VCO_TX_ON_2
|
TDD_VCO_TX_ON_2
|
||||||
TDD Control & Status
|
TDD Control & Status
|
||||||
ENDREG
|
ENDREG
|
||||||
|
|
||||||
FIELD
|
FIELD
|
||||||
[23:0] 0x000000
|
[23:0] 0x00000000
|
||||||
TDD_VCO_TX_ON_2
|
TDD_VCO_TX_ON_2
|
||||||
RW
|
RW
|
||||||
The secondary pointer for VCO_TX_ON.
|
The secondary pointer for VCO_TX_ON.
|
||||||
|
|
@ -431,12 +431,12 @@ ENDFIELD
|
||||||
|
|
||||||
REG
|
REG
|
||||||
0x0033
|
0x0033
|
||||||
REG_TDD_VCO_TX_OFF_2
|
TDD_VCO_TX_OFF_2
|
||||||
TDD Control & Status
|
TDD Control & Status
|
||||||
ENDREG
|
ENDREG
|
||||||
|
|
||||||
FIELD
|
FIELD
|
||||||
[23:0] 0x000000
|
[23:0] 0x00000000
|
||||||
TDD_VCO_TX_OFF_2
|
TDD_VCO_TX_OFF_2
|
||||||
RW
|
RW
|
||||||
The secondary pointer for VCO_TX_OFF.
|
The secondary pointer for VCO_TX_OFF.
|
||||||
|
|
@ -447,12 +447,12 @@ ENDFIELD
|
||||||
|
|
||||||
REG
|
REG
|
||||||
0x0034
|
0x0034
|
||||||
REG_TDD_RX_ON_2
|
TDD_RX_ON_2
|
||||||
TDD Control & Status
|
TDD Control & Status
|
||||||
ENDREG
|
ENDREG
|
||||||
|
|
||||||
FIELD
|
FIELD
|
||||||
[23:0] 0x000000
|
[23:0] 0x00000000
|
||||||
TDD_RX_ON_2
|
TDD_RX_ON_2
|
||||||
RW
|
RW
|
||||||
The secondary pointer for RX_ON.
|
The secondary pointer for RX_ON.
|
||||||
|
|
@ -463,12 +463,12 @@ ENDFIELD
|
||||||
|
|
||||||
REG
|
REG
|
||||||
0x0035
|
0x0035
|
||||||
REG_TDD_RX_OFF_2
|
TDD_RX_OFF_2
|
||||||
TDD Control & Status
|
TDD Control & Status
|
||||||
ENDREG
|
ENDREG
|
||||||
|
|
||||||
FIELD
|
FIELD
|
||||||
[23:0] 0x000000
|
[23:0] 0x00000000
|
||||||
TDD_RX_OFF_2
|
TDD_RX_OFF_2
|
||||||
RW
|
RW
|
||||||
The secondary pointer for RX_OFF.
|
The secondary pointer for RX_OFF.
|
||||||
|
|
@ -479,12 +479,12 @@ ENDFIELD
|
||||||
|
|
||||||
REG
|
REG
|
||||||
0x0036
|
0x0036
|
||||||
REG_TDD_TX_ON_2
|
TDD_TX_ON_2
|
||||||
TDD Control & Status
|
TDD Control & Status
|
||||||
ENDREG
|
ENDREG
|
||||||
|
|
||||||
FIELD
|
FIELD
|
||||||
[23:0] 0x000000
|
[23:0] 0x00000000
|
||||||
TDD_TX_ON_2
|
TDD_TX_ON_2
|
||||||
RW
|
RW
|
||||||
The secondary pointer for TX_ON.
|
The secondary pointer for TX_ON.
|
||||||
|
|
@ -495,12 +495,12 @@ ENDFIELD
|
||||||
|
|
||||||
REG
|
REG
|
||||||
0x0037
|
0x0037
|
||||||
REG_TDD_TX_OFF_2
|
TDD_TX_OFF_2
|
||||||
TDD Control & Status
|
TDD Control & Status
|
||||||
ENDREG
|
ENDREG
|
||||||
|
|
||||||
FIELD
|
FIELD
|
||||||
[23:0] 0x000000
|
[23:0] 0x00000000
|
||||||
TDD_TX_OFF_2
|
TDD_TX_OFF_2
|
||||||
RW
|
RW
|
||||||
The secondary pointer for TX_OFF.
|
The secondary pointer for TX_OFF.
|
||||||
|
|
@ -511,12 +511,12 @@ ENDFIELD
|
||||||
|
|
||||||
REG
|
REG
|
||||||
0x0038
|
0x0038
|
||||||
REG_TDD_RX_DP_ON_2
|
TDD_RX_DP_ON_2
|
||||||
TDD Control & Status
|
TDD Control & Status
|
||||||
ENDREG
|
ENDREG
|
||||||
|
|
||||||
FIELD
|
FIELD
|
||||||
[23:0] 0x000000
|
[23:0] 0x00000000
|
||||||
TDD_RX_DP_ON_2
|
TDD_RX_DP_ON_2
|
||||||
RW
|
RW
|
||||||
The secondary pointer for RX_DP_ON.
|
The secondary pointer for RX_DP_ON.
|
||||||
|
|
@ -527,12 +527,12 @@ ENDFIELD
|
||||||
|
|
||||||
REG
|
REG
|
||||||
0x0039
|
0x0039
|
||||||
REG_TDD_RX_DP_OFF_2
|
TDD_RX_DP_OFF_2
|
||||||
TDD Control & Status
|
TDD Control & Status
|
||||||
ENDREG
|
ENDREG
|
||||||
|
|
||||||
FIELD
|
FIELD
|
||||||
[23:0] 0x000000
|
[23:0] 0x00000000
|
||||||
TDD_RX_DP_OFF_2
|
TDD_RX_DP_OFF_2
|
||||||
RW
|
RW
|
||||||
The secondary pointer for RX_DP_OFF.
|
The secondary pointer for RX_DP_OFF.
|
||||||
|
|
@ -543,12 +543,12 @@ ENDFIELD
|
||||||
|
|
||||||
REG
|
REG
|
||||||
0x003A
|
0x003A
|
||||||
REG_TDD_TX_DP_ON_2
|
TDD_TX_DP_ON_2
|
||||||
TDD Control & Status
|
TDD Control & Status
|
||||||
ENDREG
|
ENDREG
|
||||||
|
|
||||||
FIELD
|
FIELD
|
||||||
[23:0] 0x000000
|
[23:0] 0x00000000
|
||||||
TDD_TX_DP_ON_2
|
TDD_TX_DP_ON_2
|
||||||
RW
|
RW
|
||||||
The secondary pointer for TX_DP_ON.
|
The secondary pointer for TX_DP_ON.
|
||||||
|
|
@ -559,12 +559,12 @@ ENDFIELD
|
||||||
|
|
||||||
REG
|
REG
|
||||||
0x003B
|
0x003B
|
||||||
REG_TDD_TX_DP_OFF_2
|
TDD_TX_DP_OFF_2
|
||||||
TDD Control & Status
|
TDD Control & Status
|
||||||
ENDREG
|
ENDREG
|
||||||
|
|
||||||
FIELD
|
FIELD
|
||||||
[23:0] 0x000000
|
[23:0] 0x00000000
|
||||||
TDD_TX_DP_OFF_2
|
TDD_TX_DP_OFF_2
|
||||||
RW
|
RW
|
||||||
The secondary pointer for TX_DP_OFF.
|
The secondary pointer for TX_DP_OFF.
|
||||||
|
|
@ -572,4 +572,3 @@ ENDFIELD
|
||||||
|
|
||||||
############################################################################################
|
############################################################################################
|
||||||
############################################################################################
|
############################################################################################
|
||||||
|
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue