From 02ada3bbf7231ae3210f9eb97451e82ed6c69b0c Mon Sep 17 00:00:00 2001 From: Istvan Csomortani Date: Wed, 4 Mar 2020 13:47:09 +0000 Subject: [PATCH] a10gx: Delete input/output delay definitions All input and output delays should be referenced to a virtual clock. If the input and output delays reference base clocks or PLL clocks rather than virtual clocks, the intra- and inter-clock transfer clock uncertainties, determined by derive_clock_uncertainty, are incorrectly applied to the I/O ports. See mnl_timequest_cookbook.pdf for more info. --- projects/adrv9009/a10gx/system_constr.sdc | 7 ------- projects/adrv9371x/a10gx/system_constr.sdc | 9 --------- projects/daq2/a10gx/system_constr.sdc | 9 --------- projects/daq3/a10gx/system_constr.sdc | 7 ------- 4 files changed, 32 deletions(-) diff --git a/projects/adrv9009/a10gx/system_constr.sdc b/projects/adrv9009/a10gx/system_constr.sdc index 0fc36520a..1a7d01576 100644 --- a/projects/adrv9009/a10gx/system_constr.sdc +++ b/projects/adrv9009/a10gx/system_constr.sdc @@ -15,12 +15,5 @@ if {[string equal "quartus_fit" $::TimeQuestInfo(nameofexecutable)]} { # flash interface -set_output_delay -clock [ get_clocks sys_clk_100mhz ] 2 [ get_ports {flash_addr[*]} ] -set_input_delay -clock [ get_clocks sys_clk_100mhz ] 2 [ get_ports {flash_data[*]} ] -set_output_delay -clock [ get_clocks sys_clk_100mhz ] 2 [ get_ports {flash_data[*]} ] -set_output_delay -clock [ get_clocks sys_clk_100mhz ] 2 [ get_ports {flash_cen[*]} ] -set_output_delay -clock [ get_clocks sys_clk_100mhz ] 2 [ get_ports {flash_oen} ] -set_output_delay -clock [ get_clocks sys_clk_100mhz ] 2 [ get_ports {flash_resetn} ] -set_output_delay -clock [ get_clocks sys_clk_100mhz ] 2 [ get_ports {flash_wen} ] set_false_path -from * -to [get_ports {flash_resetn}] diff --git a/projects/adrv9371x/a10gx/system_constr.sdc b/projects/adrv9371x/a10gx/system_constr.sdc index 985122cd7..e7e033307 100644 --- a/projects/adrv9371x/a10gx/system_constr.sdc +++ b/projects/adrv9371x/a10gx/system_constr.sdc @@ -8,14 +8,5 @@ derive_clock_uncertainty set_false_path -from [get_registers *altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out*] -# flash interface - -set_output_delay -clock [ get_clocks sys_clk_100mhz ] 2 [ get_ports {flash_addr[*]} ] -set_input_delay -clock [ get_clocks sys_clk_100mhz ] 2 [ get_ports {flash_data[*]} ] -set_output_delay -clock [ get_clocks sys_clk_100mhz ] 2 [ get_ports {flash_data[*]} ] -set_output_delay -clock [ get_clocks sys_clk_100mhz ] 2 [ get_ports {flash_cen[*]} ] -set_output_delay -clock [ get_clocks sys_clk_100mhz ] 2 [ get_ports {flash_oen} ] -set_output_delay -clock [ get_clocks sys_clk_100mhz ] 2 [ get_ports {flash_resetn} ] -set_output_delay -clock [ get_clocks sys_clk_100mhz ] 2 [ get_ports {flash_wen} ] set_false_path -from * -to [get_ports {flash_resetn}] diff --git a/projects/daq2/a10gx/system_constr.sdc b/projects/daq2/a10gx/system_constr.sdc index fdb48f29f..bad773591 100644 --- a/projects/daq2/a10gx/system_constr.sdc +++ b/projects/daq2/a10gx/system_constr.sdc @@ -8,14 +8,5 @@ derive_clock_uncertainty set_false_path -from [get_registers *altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out*] -# flash interface - -set_output_delay -clock [ get_clocks sys_clk_100mhz ] 2 [ get_ports {flash_addr[*]} ] -set_input_delay -clock [ get_clocks sys_clk_100mhz ] 2 [ get_ports {flash_data[*]} ] -set_output_delay -clock [ get_clocks sys_clk_100mhz ] 2 [ get_ports {flash_data[*]} ] -set_output_delay -clock [ get_clocks sys_clk_100mhz ] 2 [ get_ports {flash_cen[*]} ] -set_output_delay -clock [ get_clocks sys_clk_100mhz ] 2 [ get_ports {flash_oen} ] -set_output_delay -clock [ get_clocks sys_clk_100mhz ] 2 [ get_ports {flash_resetn} ] -set_output_delay -clock [ get_clocks sys_clk_100mhz ] 2 [ get_ports {flash_wen} ] set_false_path -from * -to [get_ports {flash_resetn}] diff --git a/projects/daq3/a10gx/system_constr.sdc b/projects/daq3/a10gx/system_constr.sdc index 7639fc2ed..aae81d787 100644 --- a/projects/daq3/a10gx/system_constr.sdc +++ b/projects/daq3/a10gx/system_constr.sdc @@ -10,12 +10,5 @@ set_false_path -from [get_registers *altera_reset_synchronizer:alt_rst_sync_uq1| # flash interface -set_output_delay -clock [ get_clocks sys_clk_100mhz ] 2 [ get_ports {flash_addr[*]} ] -set_input_delay -clock [ get_clocks sys_clk_100mhz ] 2 [ get_ports {flash_data[*]} ] -set_output_delay -clock [ get_clocks sys_clk_100mhz ] 2 [ get_ports {flash_data[*]} ] -set_output_delay -clock [ get_clocks sys_clk_100mhz ] 2 [ get_ports {flash_cen[*]} ] -set_output_delay -clock [ get_clocks sys_clk_100mhz ] 2 [ get_ports {flash_oen} ] -set_output_delay -clock [ get_clocks sys_clk_100mhz ] 2 [ get_ports {flash_resetn} ] -set_output_delay -clock [ get_clocks sys_clk_100mhz ] 2 [ get_ports {flash_wen} ] set_false_path -from * -to [get_ports {flash_resetn}]