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dacfifo- fix constraints

main
Rejeesh Kutty 2016-08-02 16:30:30 -04:00
parent 26a3e67a82
commit 02fcba1c96
2 changed files with 13 additions and 8 deletions
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12
library/util_dacfifo/util_dacfifo.v
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@ -91,8 +91,8 @@ module util_dacfifo (
reg [(ADDRESS_WIDTH-1):0] dma_waddr = 'b0;
reg [(ADDRESS_WIDTH-1):0] dma_lastaddr = 'b0;
reg [(ADDRESS_WIDTH-1):0] dma_lastaddr_d = 'b0;
reg [(ADDRESS_WIDTH-1):0] dma_lastaddr_2d = 'b0;
reg [(ADDRESS_WIDTH-1):0] dac_lastaddr_d = 'b0;
reg [(ADDRESS_WIDTH-1):0] dac_lastaddr_2d = 'b0;
reg dma_xfer_req_ff = 1'b0;
reg dma_ready_d = 1'b0;
@ -140,8 +140,8 @@ module util_dacfifo (
// sync lastaddr to dac clock domain
always @(posedge dac_clk) begin
dma_lastaddr_d <= dma_lastaddr;
dma_lastaddr_2d <= dma_lastaddr_d;
dac_lastaddr_d <= dma_lastaddr;
dac_lastaddr_2d <= dac_lastaddr_d;
dac_xfer_out_m <= {dac_xfer_out_m[1:0], dma_xfer_out};
end
@ -151,10 +151,10 @@ module util_dacfifo (
always @(posedge dac_clk) begin
if(dac_valid == 1'b1) begin
if (dma_lastaddr_2d == 'h0) begin
if (dac_lastaddr_2d == 'h0) begin
dac_raddr <= dac_raddr + 1;
end else begin
dac_raddr <= (dac_raddr < dma_lastaddr_2d) ? (dac_raddr + 1) : 'b0;
dac_raddr <= (dac_raddr < dac_lastaddr_2d) ? (dac_raddr + 1) : 'b0;
end
end
end

9
library/util_dacfifo/util_dacfifo_constr.xdc
View File

@ -1,2 +1,7 @@
set_false_path -from [get_cells *dma_lastaddr_reg* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}] \
-to [get_cells *dma_lastaddr_d_reg* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}]
set_property shreg_extract no [get_cells -hier -filter {name =~ *dac_lastaddr_d*}]
set_property shreg_extract no [get_cells -hier -filter {name =~ *dac_xfer_out_m*}]
set_false_path -from [get_cells -hier -filter {name =~ *dma_lastaddr_reg* && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *dac_lastaddr_d_reg* && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *dac_xfer_out_m_reg[0]* && IS_SEQUENTIAL}]