From 03043f732a3a5ecaba6f4ee9c6e78fcc920f8de6 Mon Sep 17 00:00:00 2001 From: AndreiGrozav Date: Fri, 19 Apr 2024 14:38:08 +0300 Subject: [PATCH] axi_ad9963: Fix TxQ 1 sample delay compared to TxI For ODDR in "SAME_EDGE" mode. Signed-off-by: AndreiGrozav --- library/axi_ad9963/axi_ad9963_if.v | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/library/axi_ad9963/axi_ad9963_if.v b/library/axi_ad9963/axi_ad9963_if.v index 31ee94aab..ad9c614e6 100644 --- a/library/axi_ad9963/axi_ad9963_if.v +++ b/library/axi_ad9963/axi_ad9963_if.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// Copyright (C) 2014-2024 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -228,8 +228,8 @@ module axi_ad9963_if #( .R (dac_rst), .S (1'b0), .C (dac_clk), - .D1 (tx_data_p[l_inst]), - .D2 (tx_data_n[l_inst]), + .D1 (tx_data_n[l_inst]), + .D2 (tx_data_p[l_inst]), .Q (tx_data[l_inst])); end endgenerate @@ -243,8 +243,8 @@ module axi_ad9963_if #( .R (dac_rst), .S (1'b0), .C (dac_clk), - .D1 (1'b1), - .D2 (1'b0), + .D1 (1'b0), + .D2 (1'b1), .Q (tx_iq)); endmodule