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axi_ad9963: Fix TxQ 1 sample delay compared to TxI 

For ODDR in "SAME_EDGE" mode.

Signed-off-by: AndreiGrozav <andrei.grozav@analog.com>
main
AndreiGrozav 2024-04-19 14:38:08 +03:00 committed by AndreiGrozav
parent a23ed6f715
commit 03043f732a
1 changed files with 5 additions and 5 deletions
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10
library/axi_ad9963/axi_ad9963_if.v
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@ -1,6 +1,6 @@
// *************************************************************************** // ***************************************************************************
// *************************************************************************** // ***************************************************************************
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. // Copyright (C) 2014-2024 Analog Devices, Inc. All rights reserved.
// //
// In this HDL repository, there are many different and unique modules, consisting // In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are // of various HDL (Verilog or VHDL) components. The individual modules are
@ -228,8 +228,8 @@ module axi_ad9963_if #(
.R (dac_rst), .R (dac_rst),
.S (1'b0), .S (1'b0),
.C (dac_clk), .C (dac_clk),
.D1 (tx_data_p[l_inst]), .D1 (tx_data_n[l_inst]),
.D2 (tx_data_n[l_inst]), .D2 (tx_data_p[l_inst]),
.Q (tx_data[l_inst])); .Q (tx_data[l_inst]));
end end
endgenerate endgenerate
@ -243,8 +243,8 @@ module axi_ad9963_if #(
.R (dac_rst), .R (dac_rst),
.S (1'b0), .S (1'b0),
.C (dac_clk), .C (dac_clk),
.D1 (1'b1), .D1 (1'b0),
.D2 (1'b0), .D2 (1'b1),
.Q (tx_iq)); .Q (tx_iq));
endmodule endmodule