diff --git a/projects/usdrx1/a10gx/Makefile b/projects/usdrx1/a10gx/Makefile new file mode 100644 index 000000000..8127eccb2 --- /dev/null +++ b/projects/usdrx1/a10gx/Makefile @@ -0,0 +1,137 @@ +#################################################################################### +#################################################################################### +## Copyright 2011(c) Analog Devices, Inc. +## Auto-generated, do not modify! +#################################################################################### +#################################################################################### + +ifeq ($(NIOS2_MMU),) + NIOS2_MMU := 1 +endif + +export ALT_NIOS_MMU_ENABLED := $(NIOS2_MMU) + +M_DEPS += system_top.v +M_DEPS += system_qsys.tcl +M_DEPS += system_project.tcl +M_DEPS += system_constr.sdc +M_DEPS += ../common/fmcjesdadc1_spi.v +M_DEPS += ../common/fmcjesdadc1_qsys.tcl +M_DEPS += ../../scripts/adi_tquest.tcl +M_DEPS += ../../scripts/adi_project_alt.tcl +M_DEPS += ../../scripts/adi_env.tcl +M_DEPS += ../../common/a10gx/a10gx_system_qsys.tcl +M_DEPS += ../../common/a10gx/a10gx_system_assign.tcl +M_DEPS += ../../../library/common/ad_sysref_gen.v +M_DEPS += ../../../library/altera/avl_adxcvr/avl_adxcvr_hw.tcl +M_DEPS += ../../../library/altera/axi_adxcvr/axi_adxcvr.v +M_DEPS += ../../../library/altera/axi_adxcvr/axi_adxcvr_hw.tcl +M_DEPS += ../../../library/altera/axi_adxcvr/axi_adxcvr_up.v +M_DEPS += ../../../library/altera/common/up_clock_mon_constr.sdc +M_DEPS += ../../../library/altera/common/up_rst_constr.sdc +M_DEPS += ../../../library/altera/common/up_xfer_cntrl_constr.sdc +M_DEPS += ../../../library/altera/common/up_xfer_status_constr.sdc +M_DEPS += ../../../library/axi_ad9250/axi_ad9250.v +M_DEPS += ../../../library/axi_ad9250/axi_ad9250_channel.v +M_DEPS += ../../../library/axi_ad9250/axi_ad9250_hw.tcl +M_DEPS += ../../../library/axi_ad9250/axi_ad9250_if.v +M_DEPS += ../../../library/axi_ad9250/axi_ad9250_pnmon.v +M_DEPS += ../../../library/axi_dmac/2d_transfer.v +M_DEPS += ../../../library/axi_dmac/address_generator.v +M_DEPS += ../../../library/axi_dmac/axi_dmac.v +M_DEPS += ../../../library/axi_dmac/axi_dmac_constr.sdc +M_DEPS += ../../../library/axi_dmac/axi_dmac_hw.tcl +M_DEPS += ../../../library/axi_dmac/axi_register_slice.v +M_DEPS += ../../../library/axi_dmac/data_mover.v +M_DEPS += ../../../library/axi_dmac/dest_axi_mm.v +M_DEPS += ../../../library/axi_dmac/dest_axi_stream.v +M_DEPS += ../../../library/axi_dmac/dest_fifo_inf.v +M_DEPS += ../../../library/axi_dmac/inc_id.h +M_DEPS += ../../../library/axi_dmac/request_arb.v +M_DEPS += ../../../library/axi_dmac/request_generator.v +M_DEPS += ../../../library/axi_dmac/resp.h +M_DEPS += ../../../library/axi_dmac/response_generator.v +M_DEPS += ../../../library/axi_dmac/response_handler.v +M_DEPS += ../../../library/axi_dmac/splitter.v +M_DEPS += ../../../library/axi_dmac/src_axi_mm.v +M_DEPS += ../../../library/axi_dmac/src_axi_stream.v +M_DEPS += ../../../library/axi_dmac/src_fifo_inf.v +M_DEPS += ../../../library/common/ad_datafmt.v +M_DEPS += ../../../library/common/ad_pnmon.v +M_DEPS += ../../../library/common/ad_rst.v +M_DEPS += ../../../library/common/ad_xcvr_rx_if.v +M_DEPS += ../../../library/common/up_adc_channel.v +M_DEPS += ../../../library/common/up_adc_common.v +M_DEPS += ../../../library/common/up_axi.v +M_DEPS += ../../../library/common/up_clock_mon.v +M_DEPS += ../../../library/common/up_delay_cntrl.v +M_DEPS += ../../../library/common/up_xfer_cntrl.v +M_DEPS += ../../../library/common/up_xfer_status.v +M_DEPS += ../../../library/scripts/adi_env.tcl +M_DEPS += ../../../library/scripts/adi_ip_alt.tcl +M_DEPS += ../../../library/util_axis_fifo/address_gray.v +M_DEPS += ../../../library/util_axis_fifo/address_gray_pipelined.v +M_DEPS += ../../../library/util_axis_fifo/address_sync.v +M_DEPS += ../../../library/util_axis_fifo/util_axis_fifo.v +M_DEPS += ../../../library/util_axis_resize/util_axis_resize.v +M_DEPS += ../../../library/util_cdc/sync_bits.v +M_DEPS += ../../../library/util_cdc/sync_gray.v +M_DEPS += ../../../library/util_cpack/util_cpack.v +M_DEPS += ../../../library/util_cpack/util_cpack_dsf.v +M_DEPS += ../../../library/util_cpack/util_cpack_hw.tcl +M_DEPS += ../../../library/util_cpack/util_cpack_mux.v + + +M_ALTERA := quartus_sh --64bit -t + + +M_FLIST += *.log +M_FLIST += *_INFO.txt +M_FLIST += *_dump.txt +M_FLIST += db +M_FLIST += *.asm.rpt +M_FLIST += *.done +M_FLIST += *.eda.rpt +M_FLIST += *.fit.* +M_FLIST += *.map.* +M_FLIST += *.sta.* +M_FLIST += *.qsf +M_FLIST += *.qpf +M_FLIST += *.qws +M_FLIST += *.sof +M_FLIST += *.cdf +M_FLIST += *.sld +M_FLIST += *.qdf +M_FLIST += hc_output +M_FLIST += system_bd +M_FLIST += hps_isw_handoff +M_FLIST += hps_sdram_*.csv +M_FLIST += *ddr3_*.csv +M_FLIST += incremental_db +M_FLIST += reconfig_mif +M_FLIST += *.sopcinfo +M_FLIST += *.jdi +M_FLIST += *.pin +M_FLIST += *_summary.csv +M_FLIST += *.dpf + + + +.PHONY: all clean clean-all +all: fmcjesdadc1_a10gx.sof + + + +clean:clean-all + + +clean-all: + rm -rf $(M_FLIST) + + +fmcjesdadc1_a10gx.sof: $(M_DEPS) + -rm -rf $(M_FLIST) + $(M_ALTERA) system_project.tcl >> fmcjesdadc1_a10gx_quartus.log 2>&1 + +#################################################################################### +#################################################################################### diff --git a/projects/usdrx1/a10gx/system_constr.sdc b/projects/usdrx1/a10gx/system_constr.sdc new file mode 100644 index 000000000..e736947f4 --- /dev/null +++ b/projects/usdrx1/a10gx/system_constr.sdc @@ -0,0 +1,11 @@ + +create_clock -period "10.000 ns" -name sys_clk_100mhz [get_ports {sys_clk}] + +derive_pll_clocks +derive_clock_uncertainty + +set_false_path -from [get_registers *altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out*] +set_false_path -from [get_clocks {sys_clk_100mhz}] -through [get_nets *altera_jesd204*] -to [get_clocks *outclk0*] +set_false_path -from [get_clocks *outclk0*] -through [get_nets *altera_jesd204*] -to [get_clocks {sys_clk_100mhz}] +set_false_path -to [get_registers *altera_jesd204_rx_csr_inst|phy_csr_rx_pcfifo_full_latched*] + diff --git a/projects/usdrx1/a10gx/system_project.tcl b/projects/usdrx1/a10gx/system_project.tcl new file mode 100644 index 000000000..b757f40b3 --- /dev/null +++ b/projects/usdrx1/a10gx/system_project.tcl @@ -0,0 +1,40 @@ + +source ../../scripts/adi_env.tcl +source ../../scripts/adi_project_alt.tcl + +adi_project_altera fmcjesdadc1_a10gx + +source $ad_hdl_dir/projects/common/a10gx/a10gx_system_assign.tcl + +# files + +set_global_assignment -name VERILOG_FILE ../common/fmcjesdadc1_spi.v +set_global_assignment -name VERILOG_FILE ../../../library/common/ad_sysref_gen.v + +# lane interface + +set_location_assignment PIN_AL8 -to ref_clk ; ## D04 FMCA_GBTCLK0_M2C_P +set_location_assignment PIN_AL7 -to "ref_clk(n)" ; ## D05 FMCA_GBTCLK0_M2C_N +set_location_assignment PIN_AW7 -to rx_data[0] ; ## C06 FMCA_DP0_M2C_P +set_location_assignment PIN_AW8 -to "rx_data[0](n)" ; ## C07 FMCA_DP0_M2C_N +set_location_assignment PIN_BA7 -to rx_data[1] ; ## A02 FMCA_DP1_M2C_P +set_location_assignment PIN_BA8 -to "rx_data[1](n)" ; ## A03 FMCA_DP1_M2C_N +set_location_assignment PIN_AY5 -to rx_data[2] ; ## A06 FMCA_DP2_M2C_P +set_location_assignment PIN_AY6 -to "rx_data[2](n)" ; ## A07 FMCA_DP2_M2C_N +set_location_assignment PIN_AV5 -to rx_data[3] ; ## A10 FMCA_DP3_M2C_P +set_location_assignment PIN_AV6 -to "rx_data[3](n)" ; ## A11 FMCA_DP3_M2C_N +set_location_assignment PIN_AY17 -to rx_sync ; ## G36 FMCA_HPC_LA33_P +set_location_assignment PIN_AW17 -to rx_sysref ; ## G37 FMCA_HPC_LA33_N +set_location_assignment PIN_BB18 -to spi_csn ; ## G34 FMCA_HPC_LA31_N +set_location_assignment PIN_BB17 -to spi_clk ; ## G33 FMCA_HPC_LA31_P +set_location_assignment PIN_AV20 -to spi_sdio ; ## H37 FMCA_HPC_LA32_P + +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to ref_clk +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to rx_data +set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to rx_data[0] +set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to rx_data[1] +set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to rx_data[2] +set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to rx_data[3] + +execute_flow -compile + diff --git a/projects/usdrx1/a10gx/system_qsys.tcl b/projects/usdrx1/a10gx/system_qsys.tcl new file mode 100644 index 000000000..6d540c54a --- /dev/null +++ b/projects/usdrx1/a10gx/system_qsys.tcl @@ -0,0 +1,5 @@ + +source $ad_hdl_dir/projects/common/a10gx/a10gx_system_qsys.tcl +source ../common/fmcjesdadc1_qsys.tcl + + diff --git a/projects/usdrx1/a10gx/system_top.v b/projects/usdrx1/a10gx/system_top.v new file mode 100644 index 000000000..aac06554f --- /dev/null +++ b/projects/usdrx1/a10gx/system_top.v @@ -0,0 +1,194 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsabilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top ( + + // clock and resets + + input sys_clk, + input sys_resetn, + + // ddr3 + + output ddr3_clk_p, + output ddr3_clk_n, + output [ 14:0] ddr3_a, + output [ 2:0] ddr3_ba, + output ddr3_cke, + output ddr3_cs_n, + output ddr3_odt, + output ddr3_reset_n, + output ddr3_we_n, + output ddr3_ras_n, + output ddr3_cas_n, + inout [ 7:0] ddr3_dqs_p, + inout [ 7:0] ddr3_dqs_n, + inout [ 63:0] ddr3_dq, + output [ 7:0] ddr3_dm, + input ddr3_rzq, + input ddr3_ref_clk, + + // ethernet + + input eth_ref_clk, + input eth_rxd, + output eth_txd, + output eth_mdc, + inout eth_mdio, + output eth_resetn, + input eth_intn, + + // board gpio + + input [ 10:0] gpio_bd_i, + output [ 15:0] gpio_bd_o, + + // lane interface + + input ref_clk, + input rx_sysref, + output rx_sync, + input [ 3:0] rx_data, + + // spi + + output spi_csn, + output spi_clk, + inout spi_sdio); + + // internal signals + + wire rx_clk; + wire [ 3:0] rx_ip_sof; + wire [127:0] rx_ip_data; + wire eth_reset; + wire eth_mdio_i; + wire eth_mdio_o; + wire eth_mdio_t; + wire [ 63:0] gpio_i; + wire [ 63:0] gpio_o; + wire spi_miso; + wire spi_mosi; + wire [ 7:0] spi_csn_s; + + // gpio in & out are separate cores + + assign gpio_i[63:32] = gpio_o[63:32]; + + // board stuff + + assign eth_resetn = ~eth_reset; + assign eth_mdio_i = eth_mdio; + assign eth_mdio = (eth_mdio_t == 1'b1) ? 1'bz : eth_mdio_o; + + assign ddr3_a[14:12] = 3'd0; + + assign gpio_i[31:27] = gpio_o[31:27]; + assign gpio_i[15: 0] = gpio_o[15:0]; + + // instantiations + + assign spi_csn = spi_csn_s[0]; + + fmcjesdadc1_spi i_fmcjesdadc1_spi ( + .spi_csn (spi_csn_s[0]), + .spi_clk (spi_clk), + .spi_mosi (spi_mosi), + .spi_miso (spi_miso), + .spi_sdio (spi_sdio)); + + system_bd i_system_bd ( + .rx_core_clk_clk (rx_clk), + .rx_data_0_rx_serial_data (rx_data[0]), + .rx_data_1_rx_serial_data (rx_data[1]), + .rx_data_2_rx_serial_data (rx_data[2]), + .rx_data_3_rx_serial_data (rx_data[3]), + .rx_ip_data_data (rx_ip_data), + .rx_ip_data_valid (), + .rx_ip_data_ready (1'b1), + .rx_ip_data_0_data (rx_ip_data[63:0]), + .rx_ip_data_0_valid (1'b1), + .rx_ip_data_0_ready (), + .rx_ip_data_1_data (rx_ip_data[127:64]), + .rx_ip_data_1_valid (1'b1), + .rx_ip_data_1_ready (), + .rx_ip_sof_export (rx_ip_sof), + .rx_ip_sof_0_export (rx_ip_sof), + .rx_ip_sof_1_export (rx_ip_sof), + .rx_ref_clk_clk (ref_clk), + .rx_sync_export (rx_sync), + .rx_sysref_export (rx_sysref), + .sys_clk_clk (sys_clk), + .sys_ddr3_cntrl_mem_mem_ck (ddr3_clk_p), + .sys_ddr3_cntrl_mem_mem_ck_n (ddr3_clk_n), + .sys_ddr3_cntrl_mem_mem_a (ddr3_a[11:0]), + .sys_ddr3_cntrl_mem_mem_ba (ddr3_ba), + .sys_ddr3_cntrl_mem_mem_cke (ddr3_cke), + .sys_ddr3_cntrl_mem_mem_cs_n (ddr3_cs_n), + .sys_ddr3_cntrl_mem_mem_odt (ddr3_odt), + .sys_ddr3_cntrl_mem_mem_reset_n (ddr3_reset_n), + .sys_ddr3_cntrl_mem_mem_we_n (ddr3_we_n), + .sys_ddr3_cntrl_mem_mem_ras_n (ddr3_ras_n), + .sys_ddr3_cntrl_mem_mem_cas_n (ddr3_cas_n), + .sys_ddr3_cntrl_mem_mem_dqs (ddr3_dqs_p[7:0]), + .sys_ddr3_cntrl_mem_mem_dqs_n (ddr3_dqs_n[7:0]), + .sys_ddr3_cntrl_mem_mem_dq (ddr3_dq[63:0]), + .sys_ddr3_cntrl_mem_mem_dm (ddr3_dm[7:0]), + .sys_ddr3_cntrl_oct_oct_rzqin (ddr3_rzq), + .sys_ddr3_cntrl_pll_ref_clk_clk (ddr3_ref_clk), + .sys_ethernet_mdio_mdc (eth_mdc), + .sys_ethernet_mdio_mdio_in (eth_mdio_i), + .sys_ethernet_mdio_mdio_out (eth_mdio_o), + .sys_ethernet_mdio_mdio_oen (eth_mdio_t), + .sys_ethernet_ref_clk_clk (eth_ref_clk), + .sys_ethernet_reset_reset (eth_reset), + .sys_ethernet_sgmii_rxp_0 (eth_rxd), + .sys_ethernet_sgmii_txp_0 (eth_txd), + .sys_gpio_bd_in_port (gpio_i[31:0]), + .sys_gpio_bd_out_port (gpio_o[31:0]), + .sys_gpio_in_export (gpio_i[63:32]), + .sys_gpio_out_export (gpio_o[63:32]), + .sys_rst_reset_n (sys_resetn), + .sys_spi_MISO (spi_miso), + .sys_spi_MOSI (spi_mosi_s), + .sys_spi_SCLK (spi_clk), + .sys_spi_SS_n (spi_csn_s)); + +endmodule + +// *************************************************************************** +// ***************************************************************************