usdrx1: Updated project to the latest framework
Adrian Costina
parent
6ee9b3a1e2
commit
037484e1d0
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@ -1,53 +1,49 @@
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# usdrx1
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set spi_csn_i [create_bd_port -dir I -from 4 -to 0 spi_csn_i]
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set spi_csn_o [create_bd_port -dir O -from 4 -to 0 spi_csn_o]
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set spi_clk_i [create_bd_port -dir I spi_clk_i]
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set spi_clk_o [create_bd_port -dir O spi_clk_o]
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set spi_sdo_i [create_bd_port -dir I spi_sdo_i]
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set spi_sdo_o [create_bd_port -dir O spi_sdo_o]
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set spi_sdi_i [create_bd_port -dir I spi_sdi_i]
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create_bd_port -dir I -from 4 -to 0 spi_csn_i
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create_bd_port -dir O -from 4 -to 0 spi_csn_o
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create_bd_port -dir I spi_clk_i
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create_bd_port -dir O spi_clk_o
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create_bd_port -dir I spi_sdo_i
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create_bd_port -dir O spi_sdo_o
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create_bd_port -dir I spi_sdi_i
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set rx_ref_clk [create_bd_port -dir I rx_ref_clk]
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set rx_sync [create_bd_port -dir O rx_sync]
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set rx_sysref [create_bd_port -dir O rx_sysref]
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set rx_data_p [create_bd_port -dir I -from 7 -to 0 rx_data_p]
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set rx_data_n [create_bd_port -dir I -from 7 -to 0 rx_data_n]
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create_bd_port -dir I rx_ref_clk
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create_bd_port -dir O rx_sync
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create_bd_port -dir O rx_sysref
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create_bd_port -dir I -from 7 -to 0 rx_data_p
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create_bd_port -dir I -from 7 -to 0 rx_data_n
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set gt_rx_data [create_bd_port -dir O -from 255 -to 0 gt_rx_data]
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set gt_rx_data_sof [create_bd_port -dir O -from 3 -to 0 gt_rx_data_sof]
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set gt_rx_data_0 [create_bd_port -dir I -from 63 -to 0 gt_rx_data_0]
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set gt_rx_data_sof_0 [create_bd_port -dir I gt_rx_data_sof_0]
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set gt_rx_data_1 [create_bd_port -dir I -from 63 -to 0 gt_rx_data_1]
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set gt_rx_data_sof_1 [create_bd_port -dir I gt_rx_data_sof_1]
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set gt_rx_data_2 [create_bd_port -dir I -from 63 -to 0 gt_rx_data_2]
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set gt_rx_data_sof_2 [create_bd_port -dir I gt_rx_data_sof_2]
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set gt_rx_data_3 [create_bd_port -dir I -from 63 -to 0 gt_rx_data_3]
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set gt_rx_data_sof_3 [create_bd_port -dir I gt_rx_data_sof_3]
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set adc_data_0 [create_bd_port -dir O -from 127 -to 0 adc_data_0]
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set adc_data_1 [create_bd_port -dir O -from 127 -to 0 adc_data_1]
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set adc_data_2 [create_bd_port -dir O -from 127 -to 0 adc_data_2]
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set adc_data_3 [create_bd_port -dir O -from 127 -to 0 adc_data_3]
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set adc_valid_0 [create_bd_port -dir O -from 7 -to 0 adc_valid_0]
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set adc_valid_1 [create_bd_port -dir O -from 7 -to 0 adc_valid_1]
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set adc_valid_2 [create_bd_port -dir O -from 7 -to 0 adc_valid_2]
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set adc_valid_3 [create_bd_port -dir O -from 7 -to 0 adc_valid_3]
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set adc_enable_0 [create_bd_port -dir O -from 7 -to 0 adc_enable_0]
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set adc_enable_1 [create_bd_port -dir O -from 7 -to 0 adc_enable_1]
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set adc_enable_2 [create_bd_port -dir O -from 7 -to 0 adc_enable_2]
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set adc_enable_3 [create_bd_port -dir O -from 7 -to 0 adc_enable_3]
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set adc_dovf_0 [create_bd_port -dir I adc_dovf_0]
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set adc_dovf_1 [create_bd_port -dir I adc_dovf_1]
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set adc_dovf_2 [create_bd_port -dir I adc_dovf_2]
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set adc_dovf_3 [create_bd_port -dir I adc_dovf_3]
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set adc_data [create_bd_port -dir I -from 511 -to 0 adc_data]
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set adc_wr_en [create_bd_port -dir I adc_wr_en]
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set adc_dovf [create_bd_port -dir O adc_dovf]
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# interrupts
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set usdrx1_dma_irq [create_bd_port -dir O usdrx1_dma_irq]
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set usdrx1_spi_irq [create_bd_port -dir O usdrx1_spi_irq]
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create_bd_port -dir O -from 255 -to 0 gt_rx_data
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create_bd_port -dir O -from 3 -to 0 gt_rx_data_sof
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create_bd_port -dir I -from 63 -to 0 gt_rx_data_0
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create_bd_port -dir I gt_rx_data_sof_0
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create_bd_port -dir I -from 63 -to 0 gt_rx_data_1
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create_bd_port -dir I gt_rx_data_sof_1
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create_bd_port -dir I -from 63 -to 0 gt_rx_data_2
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create_bd_port -dir I gt_rx_data_sof_2
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create_bd_port -dir I -from 63 -to 0 gt_rx_data_3
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create_bd_port -dir I gt_rx_data_sof_3
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create_bd_port -dir O -from 127 -to 0 adc_data_0
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create_bd_port -dir O -from 127 -to 0 adc_data_1
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create_bd_port -dir O -from 127 -to 0 adc_data_2
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create_bd_port -dir O -from 127 -to 0 adc_data_3
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create_bd_port -dir O -from 7 -to 0 adc_valid_0
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create_bd_port -dir O -from 7 -to 0 adc_valid_1
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create_bd_port -dir O -from 7 -to 0 adc_valid_2
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create_bd_port -dir O -from 7 -to 0 adc_valid_3
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create_bd_port -dir O -from 7 -to 0 adc_enable_0
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create_bd_port -dir O -from 7 -to 0 adc_enable_1
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create_bd_port -dir O -from 7 -to 0 adc_enable_2
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create_bd_port -dir O -from 7 -to 0 adc_enable_3
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create_bd_port -dir I adc_dovf_0
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create_bd_port -dir I adc_dovf_1
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create_bd_port -dir I adc_dovf_2
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create_bd_port -dir I adc_dovf_3
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create_bd_port -dir I -from 511 -to 0 adc_data
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create_bd_port -dir I adc_wr_en
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create_bd_port -dir O adc_dovf
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# adc peripherals
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@ -67,7 +63,7 @@ set axi_ad9671_core_3 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9671:
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set_property -dict [list CONFIG.PCORE_4L_2L_N {0}] $axi_ad9671_core_3
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set_property -dict [list CONFIG.PCORE_ID {3}] $axi_ad9671_core_3
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set axi_usdrx1_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:5.2 axi_usdrx1_jesd]
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set axi_usdrx1_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.0 axi_usdrx1_jesd]
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set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_usdrx1_jesd
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set_property -dict [list CONFIG.C_LANES {8}] $axi_usdrx1_jesd
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@ -95,212 +91,185 @@ set_property -dict [list CONFIG.C_CYCLIC {0}] $axi_usdrx1_dma
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set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {512}] $axi_usdrx1_dma
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set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $axi_usdrx1_dma
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set axi_usdrx1_gt_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_usdrx1_gt_interconnect]
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set_property -dict [list CONFIG.NUM_MI {1}] $axi_usdrx1_gt_interconnect
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set axi_usdrx1_dma_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_usdrx1_dma_interconnect]
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set_property -dict [list CONFIG.NUM_MI {1}] $axi_usdrx1_dma_interconnect
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# gpio and spi
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set axi_usdrx1_spi [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_quad_spi:3.2 axi_usdrx1_spi]
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set_property -dict [list CONFIG.C_USE_STARTUP {0}] $axi_usdrx1_spi
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set_property -dict [list CONFIG.C_NUM_SS_BITS {5}] $axi_usdrx1_spi
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set_property -dict [list CONFIG.C_SCK_RATIO {8}] $axi_usdrx1_spi
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# additions to default configuration
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# connections (spi)
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set_property -dict [list CONFIG.NUM_MI {15}] $axi_cpu_interconnect
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set_property -dict [list CONFIG.PCW_USE_S_AXI_HP2 {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_USE_S_AXI_HP3 {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_EN_CLK2_PORT {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_EN_CLK3_PORT {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_EN_RST2_PORT {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {200.0}] $sys_ps7
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set_property -dict [list CONFIG.PCW_FPGA3_PERIPHERAL_FREQMHZ {40}] $sys_ps7
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set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_IO {59}] $sys_ps7
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set_property LEFT 58 [get_bd_ports GPIO_I]
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set_property LEFT 58 [get_bd_ports GPIO_O]
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set_property LEFT 58 [get_bd_ports GPIO_T]
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# connections (spi and gpio)
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connect_bd_net -net axi_spi_1_csn_i [get_bd_ports spi_csn_i] [get_bd_pins axi_usdrx1_spi/ss_i]
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connect_bd_net -net axi_spi_1_csn_o [get_bd_ports spi_csn_o] [get_bd_pins axi_usdrx1_spi/ss_o]
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connect_bd_net -net axi_spi_1_clk_i [get_bd_ports spi_clk_i] [get_bd_pins axi_usdrx1_spi/sck_i]
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connect_bd_net -net axi_spi_1_clk_o [get_bd_ports spi_clk_o] [get_bd_pins axi_usdrx1_spi/sck_o]
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connect_bd_net -net axi_spi_1_sdo_i [get_bd_ports spi_sdo_i] [get_bd_pins axi_usdrx1_spi/io0_i]
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connect_bd_net -net axi_spi_1_sdo_o [get_bd_ports spi_sdo_o] [get_bd_pins axi_usdrx1_spi/io0_o]
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connect_bd_net -net axi_spi_1_sdi_i [get_bd_ports spi_sdi_i] [get_bd_pins axi_usdrx1_spi/io1_i]
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connect_bd_net -net sys_100m_clk [get_bd_pins axi_usdrx1_spi/ext_spi_clk]
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connect_bd_net -net axi_spi_1_irq [get_bd_pins axi_usdrx1_spi/ip2intc_irpt] [get_bd_ports usdrx1_spi_irq]
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ad_connect spi_csn_i axi_usdrx1_spi/ss_i
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ad_connect spi_csn_o axi_usdrx1_spi/ss_o
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ad_connect spi_clk_i axi_usdrx1_spi/sck_i
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ad_connect spi_clk_o axi_usdrx1_spi/sck_o
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ad_connect spi_sdo_i axi_usdrx1_spi/io0_i
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ad_connect spi_sdo_o axi_usdrx1_spi/io0_o
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ad_connect spi_sdi_i axi_usdrx1_spi/io1_i
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ad_connect sys_cpu_clk axi_usdrx1_spi/ext_spi_clk
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# connections (gt)
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connect_bd_net -net axi_usdrx1_gt_ref_clk_c [get_bd_pins axi_usdrx1_gt/ref_clk_c] [get_bd_ports rx_ref_clk]
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connect_bd_net -net axi_usdrx1_gt_rx_data_p [get_bd_pins axi_usdrx1_gt/rx_data_p] [get_bd_ports rx_data_p]
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connect_bd_net -net axi_usdrx1_gt_rx_data_n [get_bd_pins axi_usdrx1_gt/rx_data_n] [get_bd_ports rx_data_n]
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connect_bd_net -net axi_usdrx1_gt_rx_sync [get_bd_pins axi_usdrx1_gt/rx_sync] [get_bd_ports rx_sync]
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connect_bd_net -net axi_usdrx1_gt_rx_sysref [get_bd_pins axi_usdrx1_gt/rx_sysref] [get_bd_ports rx_sysref]
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ad_connect rx_ref_clk axi_usdrx1_gt/ref_clk_c
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ad_connect rx_data_p axi_usdrx1_gt/rx_data_p
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ad_connect rx_data_n axi_usdrx1_gt/rx_data_n
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ad_connect rx_sync axi_usdrx1_gt/rx_sync
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ad_connect rx_sysref axi_usdrx1_gt/rx_sysref
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# connections (adc)
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connect_bd_net -net axi_usdrx1_gt_rx_clk [get_bd_pins axi_usdrx1_gt/rx_clk_g]
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connect_bd_net -net axi_usdrx1_gt_rx_clk [get_bd_pins axi_usdrx1_gt/rx_clk]
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connect_bd_net -net axi_usdrx1_gt_rx_clk [get_bd_pins axi_ad9671_core_0/rx_clk]
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connect_bd_net -net axi_usdrx1_gt_rx_clk [get_bd_pins axi_ad9671_core_1/rx_clk]
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connect_bd_net -net axi_usdrx1_gt_rx_clk [get_bd_pins axi_ad9671_core_2/rx_clk]
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connect_bd_net -net axi_usdrx1_gt_rx_clk [get_bd_pins axi_ad9671_core_3/rx_clk]
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connect_bd_net -net axi_usdrx1_gt_rx_clk [get_bd_pins axi_usdrx1_jesd/rx_core_clk]
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ad_connect axi_usdrx1_gt_rx_clk axi_usdrx1_gt/rx_clk_g
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ad_connect axi_usdrx1_gt_rx_clk axi_usdrx1_gt/rx_clk
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ad_connect axi_usdrx1_gt_rx_clk axi_usdrx1_gt/tx_clk
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ad_connect axi_usdrx1_gt_rx_clk axi_ad9671_core_0/rx_clk
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ad_connect axi_usdrx1_gt_rx_clk axi_ad9671_core_1/rx_clk
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ad_connect axi_usdrx1_gt_rx_clk axi_ad9671_core_2/rx_clk
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ad_connect axi_usdrx1_gt_rx_clk axi_ad9671_core_3/rx_clk
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ad_connect axi_usdrx1_gt_rx_clk axi_usdrx1_jesd/rx_core_clk
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ad_connect axi_usdrx1_gt/rx_rst axi_usdrx1_jesd/rx_reset
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ad_connect axi_usdrx1_gt/rx_sysref axi_usdrx1_jesd/rx_sysref
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connect_bd_net -net axi_usdrx1_gt_rx_rst [get_bd_pins axi_usdrx1_gt/rx_rst] [get_bd_pins axi_usdrx1_jesd/rx_reset]
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connect_bd_net -net axi_usdrx1_gt_rx_sysref [get_bd_pins axi_usdrx1_jesd/rx_sysref]
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connect_bd_net -net axi_usdrx1_gt_rx_gt_charisk [get_bd_pins axi_usdrx1_gt/rx_gt_charisk] [get_bd_pins axi_usdrx1_jesd/gt_rxcharisk_in]
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connect_bd_net -net axi_usdrx1_gt_rx_gt_disperr [get_bd_pins axi_usdrx1_gt/rx_gt_disperr] [get_bd_pins axi_usdrx1_jesd/gt_rxdisperr_in]
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connect_bd_net -net axi_usdrx1_gt_rx_gt_notintable [get_bd_pins axi_usdrx1_gt/rx_gt_notintable] [get_bd_pins axi_usdrx1_jesd/gt_rxnotintable_in]
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connect_bd_net -net axi_usdrx1_gt_rx_gt_data [get_bd_pins axi_usdrx1_gt/rx_gt_data] [get_bd_pins axi_usdrx1_jesd/gt_rxdata_in]
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connect_bd_net -net axi_usdrx1_gt_rx_rst_done [get_bd_pins axi_usdrx1_gt/rx_rst_done] [get_bd_pins axi_usdrx1_jesd/rx_reset_done]
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connect_bd_net -net axi_usdrx1_gt_rx_ip_comma_align [get_bd_pins axi_usdrx1_gt/rx_ip_comma_align] [get_bd_pins axi_usdrx1_jesd/rxencommaalign_out]
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connect_bd_net -net axi_usdrx1_gt_rx_ip_sync [get_bd_pins axi_usdrx1_gt/rx_ip_sync] [get_bd_pins axi_usdrx1_jesd/rx_sync]
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connect_bd_net -net axi_usdrx1_gt_rx_ip_sof [get_bd_pins axi_usdrx1_gt/rx_ip_sof] [get_bd_pins axi_usdrx1_jesd/rx_start_of_frame]
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connect_bd_net -net axi_usdrx1_gt_rx_ip_data [get_bd_pins axi_usdrx1_gt/rx_ip_data] [get_bd_pins axi_usdrx1_jesd/rx_tdata]
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connect_bd_net -net axi_usdrx1_gt_rx_data [get_bd_pins axi_usdrx1_gt/rx_data] [get_bd_ports gt_rx_data]
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connect_bd_net -net axi_usdrx1_gt_rx_data_sof [get_bd_pins axi_usdrx1_gt/rx_data_sof] [get_bd_ports gt_rx_data_sof]
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connect_bd_net -net axi_usdrx1_gt_rx_data_0 [get_bd_pins axi_ad9671_core_0/rx_data] [get_bd_ports gt_rx_data_0]
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connect_bd_net -net axi_usdrx1_gt_rx_data_sof_0 [get_bd_pins axi_ad9671_core_0/rx_data_sof] [get_bd_ports gt_rx_data_sof_0]
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connect_bd_net -net axi_usdrx1_gt_rx_data_1 [get_bd_pins axi_ad9671_core_1/rx_data] [get_bd_ports gt_rx_data_1]
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connect_bd_net -net axi_usdrx1_gt_rx_data_sof_1 [get_bd_pins axi_ad9671_core_1/rx_data_sof] [get_bd_ports gt_rx_data_sof_1]
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connect_bd_net -net axi_usdrx1_gt_rx_data_2 [get_bd_pins axi_ad9671_core_2/rx_data] [get_bd_ports gt_rx_data_2]
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connect_bd_net -net axi_usdrx1_gt_rx_data_sof_2 [get_bd_pins axi_ad9671_core_2/rx_data_sof] [get_bd_ports gt_rx_data_sof_2]
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connect_bd_net -net axi_usdrx1_gt_rx_data_3 [get_bd_pins axi_ad9671_core_3/rx_data] [get_bd_ports gt_rx_data_3]
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connect_bd_net -net axi_usdrx1_gt_rx_data_sof_3 [get_bd_pins axi_ad9671_core_3/rx_data_sof] [get_bd_ports gt_rx_data_sof_3]
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connect_bd_net -net axi_ad9671_core_adc_clk [get_bd_pins axi_ad9671_core_0/adc_clk] [get_bd_pins axi_usdrx1_dma/fifo_wr_clk]
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connect_bd_net -net axi_ad9671_core_adc_data_0 [get_bd_pins axi_ad9671_core_0/adc_data] [get_bd_ports adc_data_0]
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connect_bd_net -net axi_ad9671_core_adc_data_1 [get_bd_pins axi_ad9671_core_1/adc_data] [get_bd_ports adc_data_1]
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connect_bd_net -net axi_ad9671_core_adc_data_2 [get_bd_pins axi_ad9671_core_2/adc_data] [get_bd_ports adc_data_2]
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connect_bd_net -net axi_ad9671_core_adc_data_3 [get_bd_pins axi_ad9671_core_3/adc_data] [get_bd_ports adc_data_3]
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connect_bd_net -net axi_ad9671_core_adc_valid_0 [get_bd_pins axi_ad9671_core_0/adc_valid] [get_bd_ports adc_valid_0]
|
||||
connect_bd_net -net axi_ad9671_core_adc_valid_1 [get_bd_pins axi_ad9671_core_1/adc_valid] [get_bd_ports adc_valid_1]
|
||||
connect_bd_net -net axi_ad9671_core_adc_valid_2 [get_bd_pins axi_ad9671_core_2/adc_valid] [get_bd_ports adc_valid_2]
|
||||
connect_bd_net -net axi_ad9671_core_adc_valid_3 [get_bd_pins axi_ad9671_core_3/adc_valid] [get_bd_ports adc_valid_3]
|
||||
connect_bd_net -net axi_ad9671_core_adc_enable_0 [get_bd_pins axi_ad9671_core_0/adc_enable] [get_bd_ports adc_enable_0]
|
||||
connect_bd_net -net axi_ad9671_core_adc_enable_1 [get_bd_pins axi_ad9671_core_1/adc_enable] [get_bd_ports adc_enable_1]
|
||||
connect_bd_net -net axi_ad9671_core_adc_enable_2 [get_bd_pins axi_ad9671_core_2/adc_enable] [get_bd_ports adc_enable_2]
|
||||
connect_bd_net -net axi_ad9671_core_adc_enable_3 [get_bd_pins axi_ad9671_core_3/adc_enable] [get_bd_ports adc_enable_3]
|
||||
connect_bd_net -net axi_ad9671_core_adc_dovf_0 [get_bd_pins axi_ad9671_core_0/adc_dovf] [get_bd_ports adc_dovf_0]
|
||||
connect_bd_net -net axi_ad9671_core_adc_dovf_1 [get_bd_pins axi_ad9671_core_1/adc_dovf] [get_bd_ports adc_dovf_1]
|
||||
connect_bd_net -net axi_ad9671_core_adc_dovf_2 [get_bd_pins axi_ad9671_core_2/adc_dovf] [get_bd_ports adc_dovf_2]
|
||||
connect_bd_net -net axi_ad9671_core_adc_dovf_3 [get_bd_pins axi_ad9671_core_3/adc_dovf] [get_bd_ports adc_dovf_3]
|
||||
connect_bd_net -net axi_ad9671_dma_wr_en [get_bd_pins axi_usdrx1_dma/fifo_wr_en] [get_bd_ports adc_wr_en]
|
||||
connect_bd_net -net axi_ad9671_dma_adc_data [get_bd_pins axi_usdrx1_dma/fifo_wr_din] [get_bd_ports adc_data]
|
||||
connect_bd_net -net axi_ad9671_dma_adc_dovf [get_bd_pins axi_usdrx1_dma/fifo_wr_overflow] [get_bd_ports adc_dovf]
|
||||
connect_bd_net -net axi_usdrx1_dma_irq [get_bd_pins axi_usdrx1_dma/irq] [get_bd_ports usdrx1_dma_irq]
|
||||
connect_bd_net -net axi_ad9671_adc_raddr [get_bd_pins axi_ad9671_core_0/adc_raddr_out]
|
||||
connect_bd_net -net axi_ad9671_adc_raddr [get_bd_pins axi_ad9671_core_1/adc_raddr_in]
|
||||
connect_bd_net -net axi_ad9671_adc_raddr [get_bd_pins axi_ad9671_core_2/adc_raddr_in]
|
||||
connect_bd_net -net axi_ad9671_adc_raddr [get_bd_pins axi_ad9671_core_3/adc_raddr_in]
|
||||
connect_bd_net -net axi_ad9671_adc_sync [get_bd_pins axi_ad9671_core_0/adc_sync_out]
|
||||
connect_bd_net -net axi_ad9671_adc_sync [get_bd_pins axi_ad9671_core_1/adc_sync_in]
|
||||
connect_bd_net -net axi_ad9671_adc_sync [get_bd_pins axi_ad9671_core_2/adc_sync_in]
|
||||
connect_bd_net -net axi_ad9671_adc_sync [get_bd_pins axi_ad9671_core_3/adc_sync_in]
|
||||
create_bd_cell -type ip -vlnv analog.com:user:util_bsplit:1.0 util_bsplit_rx_gt_charisk
|
||||
set_property -dict [list CONFIG.CH_DW {4}] [get_bd_cells util_bsplit_rx_gt_charisk]
|
||||
set_property -dict [list CONFIG.CH_CNT {8}] [get_bd_cells util_bsplit_rx_gt_charisk]
|
||||
|
||||
# interconnect (cpu)
|
||||
ad_connect util_bsplit_rx_gt_charisk/data axi_usdrx1_gt/rx_gt_charisk
|
||||
ad_connect util_bsplit_rx_gt_charisk/split_data_0 axi_usdrx1_jesd/gt0_rxcharisk
|
||||
ad_connect util_bsplit_rx_gt_charisk/split_data_1 axi_usdrx1_jesd/gt1_rxcharisk
|
||||
ad_connect util_bsplit_rx_gt_charisk/split_data_2 axi_usdrx1_jesd/gt2_rxcharisk
|
||||
ad_connect util_bsplit_rx_gt_charisk/split_data_3 axi_usdrx1_jesd/gt3_rxcharisk
|
||||
ad_connect util_bsplit_rx_gt_charisk/split_data_4 axi_usdrx1_jesd/gt4_rxcharisk
|
||||
ad_connect util_bsplit_rx_gt_charisk/split_data_5 axi_usdrx1_jesd/gt5_rxcharisk
|
||||
ad_connect util_bsplit_rx_gt_charisk/split_data_6 axi_usdrx1_jesd/gt6_rxcharisk
|
||||
ad_connect util_bsplit_rx_gt_charisk/split_data_7 axi_usdrx1_jesd/gt7_rxcharisk
|
||||
|
||||
connect_bd_intf_net -intf_net axi_cpu_interconnect_m07_axi [get_bd_intf_pins axi_cpu_interconnect/M07_AXI] [get_bd_intf_pins axi_usdrx1_gt/s_axi]
|
||||
connect_bd_intf_net -intf_net axi_cpu_interconnect_m08_axi [get_bd_intf_pins axi_cpu_interconnect/M08_AXI] [get_bd_intf_pins axi_usdrx1_jesd/s_axi]
|
||||
connect_bd_intf_net -intf_net axi_cpu_interconnect_m09_axi [get_bd_intf_pins axi_cpu_interconnect/M09_AXI] [get_bd_intf_pins axi_ad9671_core_0/s_axi]
|
||||
connect_bd_intf_net -intf_net axi_cpu_interconnect_m10_axi [get_bd_intf_pins axi_cpu_interconnect/M10_AXI] [get_bd_intf_pins axi_ad9671_core_1/s_axi]
|
||||
connect_bd_intf_net -intf_net axi_cpu_interconnect_m11_axi [get_bd_intf_pins axi_cpu_interconnect/M11_AXI] [get_bd_intf_pins axi_ad9671_core_2/s_axi]
|
||||
connect_bd_intf_net -intf_net axi_cpu_interconnect_m12_axi [get_bd_intf_pins axi_cpu_interconnect/M12_AXI] [get_bd_intf_pins axi_ad9671_core_3/s_axi]
|
||||
connect_bd_intf_net -intf_net axi_cpu_interconnect_m13_axi [get_bd_intf_pins axi_cpu_interconnect/M13_AXI] [get_bd_intf_pins axi_usdrx1_dma/s_axi]
|
||||
connect_bd_intf_net -intf_net axi_cpu_interconnect_m14_axi [get_bd_intf_pins axi_cpu_interconnect/M14_AXI] [get_bd_intf_pins axi_usdrx1_spi/axi_lite]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M07_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M08_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M09_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M10_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M11_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M12_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M13_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M14_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_usdrx1_gt/s_axi_aclk]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9671_core_0/s_axi_aclk]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9671_core_1/s_axi_aclk]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9671_core_2/s_axi_aclk]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9671_core_3/s_axi_aclk]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_usdrx1_jesd/s_axi_aclk]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_usdrx1_dma/s_axi_aclk]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_usdrx1_spi/s_axi_aclk]
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M07_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M08_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M09_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M10_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M11_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M12_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M13_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M14_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_usdrx1_gt/s_axi_aresetn]
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9671_core_0/s_axi_aresetn]
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9671_core_1/s_axi_aresetn]
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9671_core_2/s_axi_aresetn]
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9671_core_3/s_axi_aresetn]
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_usdrx1_jesd/s_axi_aresetn]
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_usdrx1_dma/s_axi_aresetn]
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_usdrx1_spi/s_axi_aresetn]
|
||||
create_bd_cell -type ip -vlnv analog.com:user:util_bsplit:1.0 util_bsplit_rx_gt_disperr
|
||||
set_property -dict [list CONFIG.CH_DW {4}] [get_bd_cells util_bsplit_rx_gt_disperr]
|
||||
set_property -dict [list CONFIG.CH_CNT {8}] [get_bd_cells util_bsplit_rx_gt_disperr]
|
||||
|
||||
# interconnect (gt es)
|
||||
ad_connect util_bsplit_rx_gt_disperr/data axi_usdrx1_gt/rx_gt_disperr
|
||||
ad_connect util_bsplit_rx_gt_disperr/split_data_0 axi_usdrx1_jesd/gt0_rxdisperr
|
||||
ad_connect util_bsplit_rx_gt_disperr/split_data_1 axi_usdrx1_jesd/gt1_rxdisperr
|
||||
ad_connect util_bsplit_rx_gt_disperr/split_data_2 axi_usdrx1_jesd/gt2_rxdisperr
|
||||
ad_connect util_bsplit_rx_gt_disperr/split_data_3 axi_usdrx1_jesd/gt3_rxdisperr
|
||||
ad_connect util_bsplit_rx_gt_disperr/split_data_4 axi_usdrx1_jesd/gt4_rxdisperr
|
||||
ad_connect util_bsplit_rx_gt_disperr/split_data_5 axi_usdrx1_jesd/gt5_rxdisperr
|
||||
ad_connect util_bsplit_rx_gt_disperr/split_data_6 axi_usdrx1_jesd/gt6_rxdisperr
|
||||
ad_connect util_bsplit_rx_gt_disperr/split_data_7 axi_usdrx1_jesd/gt7_rxdisperr
|
||||
|
||||
connect_bd_intf_net -intf_net axi_usdrx1_gt_interconnect_s00_axi [get_bd_intf_pins axi_usdrx1_gt_interconnect/S00_AXI] [get_bd_intf_pins axi_usdrx1_gt/m_axi]
|
||||
connect_bd_intf_net -intf_net axi_usdrx1_gt_interconnect_m00_axi [get_bd_intf_pins axi_usdrx1_gt_interconnect/M00_AXI] [get_bd_intf_pins sys_ps7/S_AXI_HP3]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_usdrx1_gt_interconnect/ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_usdrx1_gt_interconnect/S00_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_usdrx1_gt_interconnect/M00_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins sys_ps7/S_AXI_HP3_ACLK]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_usdrx1_gt/m_axi_aclk]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_usdrx1_gt/drp_clk]
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_usdrx1_gt_interconnect/ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_usdrx1_gt_interconnect/S00_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_usdrx1_gt_interconnect/M00_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_usdrx1_gt/m_axi_aresetn]
|
||||
create_bd_cell -type ip -vlnv analog.com:user:util_bsplit:1.0 util_bsplit_rx_gt_notintable
|
||||
set_property -dict [list CONFIG.CH_DW {4}] [get_bd_cells util_bsplit_rx_gt_notintable]
|
||||
set_property -dict [list CONFIG.CH_CNT {8}] [get_bd_cells util_bsplit_rx_gt_notintable]
|
||||
|
||||
# interconnect (dma)
|
||||
ad_connect util_bsplit_rx_gt_notintable/data axi_usdrx1_gt/rx_gt_notintable
|
||||
ad_connect util_bsplit_rx_gt_notintable/split_data_0 axi_usdrx1_jesd/gt0_rxnotintable
|
||||
ad_connect util_bsplit_rx_gt_notintable/split_data_1 axi_usdrx1_jesd/gt1_rxnotintable
|
||||
ad_connect util_bsplit_rx_gt_notintable/split_data_2 axi_usdrx1_jesd/gt2_rxnotintable
|
||||
ad_connect util_bsplit_rx_gt_notintable/split_data_3 axi_usdrx1_jesd/gt3_rxnotintable
|
||||
ad_connect util_bsplit_rx_gt_notintable/split_data_4 axi_usdrx1_jesd/gt4_rxnotintable
|
||||
ad_connect util_bsplit_rx_gt_notintable/split_data_5 axi_usdrx1_jesd/gt5_rxnotintable
|
||||
ad_connect util_bsplit_rx_gt_notintable/split_data_6 axi_usdrx1_jesd/gt6_rxnotintable
|
||||
ad_connect util_bsplit_rx_gt_notintable/split_data_7 axi_usdrx1_jesd/gt7_rxnotintable
|
||||
|
||||
set sys_fmc_dma_clk_source [get_bd_pins sys_ps7/FCLK_CLK2]
|
||||
set sys_fmc_dma_resetn_source [get_bd_pins sys_ps7/FCLK_RESET2_N]
|
||||
create_bd_cell -type ip -vlnv analog.com:user:util_bsplit:1.0 util_bsplit_rx_gt_data
|
||||
set_property -dict [list CONFIG.CH_DW {32}] [get_bd_cells util_bsplit_rx_gt_data]
|
||||
set_property -dict [list CONFIG.CH_CNT {8}] [get_bd_cells util_bsplit_rx_gt_data]
|
||||
|
||||
connect_bd_net -net sys_fmc_dma_clk $sys_fmc_dma_clk_source
|
||||
connect_bd_net -net sys_fmc_dma_resetn $sys_fmc_dma_resetn_source
|
||||
ad_connect util_bsplit_rx_gt_data/data axi_usdrx1_gt/rx_gt_data
|
||||
ad_connect util_bsplit_rx_gt_data/split_data_0 axi_usdrx1_jesd/gt0_rxdata
|
||||
ad_connect util_bsplit_rx_gt_data/split_data_1 axi_usdrx1_jesd/gt1_rxdata
|
||||
ad_connect util_bsplit_rx_gt_data/split_data_2 axi_usdrx1_jesd/gt2_rxdata
|
||||
ad_connect util_bsplit_rx_gt_data/split_data_3 axi_usdrx1_jesd/gt3_rxdata
|
||||
ad_connect util_bsplit_rx_gt_data/split_data_4 axi_usdrx1_jesd/gt4_rxdata
|
||||
ad_connect util_bsplit_rx_gt_data/split_data_5 axi_usdrx1_jesd/gt5_rxdata
|
||||
ad_connect util_bsplit_rx_gt_data/split_data_6 axi_usdrx1_jesd/gt6_rxdata
|
||||
ad_connect util_bsplit_rx_gt_data/split_data_7 axi_usdrx1_jesd/gt7_rxdata
|
||||
|
||||
connect_bd_intf_net -intf_net axi_usdrx1_dma_interconnect_m00_axi [get_bd_intf_pins axi_usdrx1_dma_interconnect/M00_AXI] [get_bd_intf_pins sys_ps7/S_AXI_HP2]
|
||||
connect_bd_intf_net -intf_net axi_usdrx1_dma_interconnect_s00_axi [get_bd_intf_pins axi_usdrx1_dma_interconnect/S00_AXI] [get_bd_intf_pins axi_usdrx1_dma/m_dest_axi]
|
||||
connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_usdrx1_dma_interconnect/ACLK] $sys_fmc_dma_clk_source
|
||||
connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_usdrx1_dma_interconnect/S00_ACLK] $sys_fmc_dma_clk_source
|
||||
connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_usdrx1_dma_interconnect/M00_ACLK] $sys_fmc_dma_clk_source
|
||||
connect_bd_net -net sys_fmc_dma_clk [get_bd_pins sys_ps7/S_AXI_HP2_ACLK]
|
||||
connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_usdrx1_dma/m_dest_axi_aclk]
|
||||
connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_usdrx1_dma_interconnect/ARESETN] $sys_fmc_dma_resetn_source
|
||||
connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_usdrx1_dma_interconnect/S00_ARESETN] $sys_fmc_dma_resetn_source
|
||||
connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_usdrx1_dma_interconnect/M00_ARESETN] $sys_fmc_dma_resetn_source
|
||||
connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_usdrx1_dma/m_dest_axi_aresetn]
|
||||
ad_connect axi_usdrx1_gt/rx_rst_done axi_usdrx1_jesd/rx_reset_done
|
||||
ad_connect axi_usdrx1_gt/rx_ip_comma_align axi_usdrx1_jesd/rxencommaalign_out
|
||||
ad_connect axi_usdrx1_gt/rx_ip_sync axi_usdrx1_jesd/rx_sync
|
||||
ad_connect axi_usdrx1_gt/rx_ip_sof axi_usdrx1_jesd/rx_start_of_frame
|
||||
ad_connect axi_usdrx1_gt/rx_ip_data axi_usdrx1_jesd/rx_tdata
|
||||
ad_connect gt_rx_data axi_usdrx1_gt/rx_data
|
||||
ad_connect gt_rx_data_sof axi_usdrx1_gt/rx_data_sof
|
||||
ad_connect gt_rx_data_0 axi_ad9671_core_0/rx_data
|
||||
ad_connect gt_rx_data_sof_0 axi_ad9671_core_0/rx_data_sof
|
||||
ad_connect gt_rx_data_1 axi_ad9671_core_1/rx_data
|
||||
ad_connect gt_rx_data_sof_1 axi_ad9671_core_1/rx_data_sof
|
||||
ad_connect gt_rx_data_2 axi_ad9671_core_2/rx_data
|
||||
ad_connect gt_rx_data_sof_2 axi_ad9671_core_2/rx_data_sof
|
||||
ad_connect gt_rx_data_3 axi_ad9671_core_3/rx_data
|
||||
ad_connect gt_rx_data_sof_3 axi_ad9671_core_3/rx_data_sof
|
||||
ad_connect axi_ad9671_core_0/adc_clk axi_usdrx1_dma/fifo_wr_clk
|
||||
ad_connect adc_data_0 axi_ad9671_core_0/adc_data
|
||||
ad_connect adc_data_1 axi_ad9671_core_1/adc_data
|
||||
ad_connect adc_data_2 axi_ad9671_core_2/adc_data
|
||||
ad_connect adc_data_3 axi_ad9671_core_3/adc_data
|
||||
ad_connect adc_valid_0 axi_ad9671_core_0/adc_valid
|
||||
ad_connect adc_valid_1 axi_ad9671_core_1/adc_valid
|
||||
ad_connect adc_valid_2 axi_ad9671_core_2/adc_valid
|
||||
ad_connect adc_valid_3 axi_ad9671_core_3/adc_valid
|
||||
ad_connect adc_enable_0 axi_ad9671_core_0/adc_enable
|
||||
ad_connect adc_enable_1 axi_ad9671_core_1/adc_enable
|
||||
ad_connect adc_enable_2 axi_ad9671_core_2/adc_enable
|
||||
ad_connect adc_enable_3 axi_ad9671_core_3/adc_enable
|
||||
ad_connect adc_dovf_0 axi_ad9671_core_0/adc_dovf
|
||||
ad_connect adc_dovf_1 axi_ad9671_core_1/adc_dovf
|
||||
ad_connect adc_dovf_2 axi_ad9671_core_2/adc_dovf
|
||||
ad_connect adc_dovf_3 axi_ad9671_core_3/adc_dovf
|
||||
ad_connect adc_wr_en axi_usdrx1_dma/fifo_wr_en
|
||||
ad_connect adc_data axi_usdrx1_dma/fifo_wr_din
|
||||
ad_connect adc_dovf axi_usdrx1_dma/fifo_wr_overflow
|
||||
ad_connect axi_ad9671_adc_raddr axi_ad9671_core_0/adc_raddr_out
|
||||
ad_connect axi_ad9671_adc_raddr axi_ad9671_core_1/adc_raddr_in
|
||||
ad_connect axi_ad9671_adc_raddr axi_ad9671_core_2/adc_raddr_in
|
||||
ad_connect axi_ad9671_adc_raddr axi_ad9671_core_3/adc_raddr_in
|
||||
ad_connect axi_ad9671_adc_sync axi_ad9671_core_0/adc_sync_out
|
||||
ad_connect axi_ad9671_adc_sync axi_ad9671_core_1/adc_sync_in
|
||||
ad_connect axi_ad9671_adc_sync axi_ad9671_core_2/adc_sync_in
|
||||
ad_connect axi_ad9671_adc_sync axi_ad9671_core_3/adc_sync_in
|
||||
|
||||
# address map
|
||||
|
||||
ad_cpu_interconnect 0x44A00000 axi_ad9671_core_0
|
||||
ad_cpu_interconnect 0x44A10000 axi_ad9671_core_1
|
||||
ad_cpu_interconnect 0x44A20000 axi_ad9671_core_2
|
||||
ad_cpu_interconnect 0x44A30000 axi_ad9671_core_3
|
||||
|
||||
ad_cpu_interconnect 0x44A60000 axi_usdrx1_gt
|
||||
ad_cpu_interconnect 0x44A91000 axi_usdrx1_jesd
|
||||
ad_cpu_interconnect 0x7c400000 axi_usdrx1_dma
|
||||
ad_cpu_interconnect 0x7c420000 axi_usdrx1_spi
|
||||
|
||||
ad_mem_hp1_interconnect sys_cpu_clk sys_ps7/S_AXI_HP1
|
||||
ad_mem_hp1_interconnect sys_cpu_clk axi_usdrx1_dma/m_dest_axi
|
||||
ad_connect sys_cpu_resetn axi_usdrx1_dma/m_dest_axi_aresetn
|
||||
|
||||
ad_mem_hp3_interconnect sys_cpu_clk sys_ps7/S_AXI_HP3
|
||||
ad_mem_hp3_interconnect sys_cpu_clk axi_usdrx1_gt/m_axi
|
||||
ad_connect sys_cpu_clk axi_usdrx1_gt/drp_clk
|
||||
ad_connect sys_cpu_resetn axi_usdrx1_gt/m_axi_aresetn
|
||||
|
||||
#interrupts
|
||||
|
||||
ad_cpu_interrupt ps-12 mb-12 axi_usdrx1_spi/ip2intc_irpt
|
||||
ad_cpu_interrupt ps-13 mb-13 axi_usdrx1_dma/irq
|
||||
|
||||
# ila
|
||||
|
||||
set ila_jesd_rx_mon [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:4.0 ila_jesd_rx_mon]
|
||||
set ila_jesd_rx_mon [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:5.0 ila_jesd_rx_mon]
|
||||
set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_jesd_rx_mon
|
||||
set_property -dict [list CONFIG.C_NUM_OF_PROBES {2}] $ila_jesd_rx_mon
|
||||
set_property -dict [list CONFIG.C_PROBE0_WIDTH {662}] $ila_jesd_rx_mon
|
||||
set_property -dict [list CONFIG.C_PROBE1_WIDTH {10}] $ila_jesd_rx_mon
|
||||
set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila_jesd_rx_mon
|
||||
|
||||
connect_bd_net -net axi_usdrx1_gt_rx_mon_data [get_bd_pins axi_usdrx1_gt/rx_mon_data]
|
||||
connect_bd_net -net axi_usdrx1_gt_rx_mon_trigger [get_bd_pins axi_usdrx1_gt/rx_mon_trigger]
|
||||
connect_bd_net -net axi_usdrx1_gt_rx_clk [get_bd_pins ila_jesd_rx_mon/CLK]
|
||||
connect_bd_net -net axi_usdrx1_gt_rx_mon_data [get_bd_pins ila_jesd_rx_mon/PROBE0]
|
||||
connect_bd_net -net axi_usdrx1_gt_rx_mon_trigger [get_bd_pins ila_jesd_rx_mon/PROBE1]
|
||||
ad_connect axi_usdrx1_gt_rx_mon_data axi_usdrx1_gt/rx_mon_data
|
||||
ad_connect axi_usdrx1_gt_rx_mon_trigger axi_usdrx1_gt/rx_mon_trigger
|
||||
ad_connect axi_usdrx1_gt_rx_clk ila_jesd_rx_mon/CLK
|
||||
ad_connect axi_usdrx1_gt_rx_mon_data ila_jesd_rx_mon/PROBE0
|
||||
ad_connect axi_usdrx1_gt_rx_mon_trigger ila_jesd_rx_mon/PROBE1
|
||||
|
||||
set ila_ad9671 [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:4.0 ila_ad9671]
|
||||
set ila_ad9671 [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:5.0 ila_ad9671]
|
||||
set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_ad9671
|
||||
set_property -dict [list CONFIG.C_NUM_OF_PROBES {8}] $ila_ad9671
|
||||
set_property -dict [list CONFIG.C_PROBE0_WIDTH {128}] $ila_ad9671
|
||||
|
|
@ -313,27 +282,12 @@ set_property -dict [list CONFIG.C_PROBE6_WIDTH {128}] $ila_ad9671
|
|||
set_property -dict [list CONFIG.C_PROBE7_WIDTH {8}] $ila_ad9671
|
||||
set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila_ad9671
|
||||
|
||||
connect_bd_net -net axi_ad9671_core_adc_clk [get_bd_pins ila_ad9671/CLK]
|
||||
connect_bd_net -net axi_ad9671_core_adc_data_0 [get_bd_pins ila_ad9671/PROBE0]
|
||||
connect_bd_net -net axi_ad9671_core_adc_valid_0 [get_bd_pins ila_ad9671/PROBE1]
|
||||
connect_bd_net -net axi_ad9671_core_adc_data_1 [get_bd_pins ila_ad9671/PROBE2]
|
||||
connect_bd_net -net axi_ad9671_core_adc_valid_1 [get_bd_pins ila_ad9671/PROBE3]
|
||||
connect_bd_net -net axi_ad9671_core_adc_data_2 [get_bd_pins ila_ad9671/PROBE4]
|
||||
connect_bd_net -net axi_ad9671_core_adc_valid_2 [get_bd_pins ila_ad9671/PROBE5]
|
||||
connect_bd_net -net axi_ad9671_core_adc_data_3 [get_bd_pins ila_ad9671/PROBE6]
|
||||
connect_bd_net -net axi_ad9671_core_adc_valid_3 [get_bd_pins ila_ad9671/PROBE7]
|
||||
# address map
|
||||
|
||||
create_bd_addr_seg -range 0x00010000 -offset 0x44A00000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9671_core_0/s_axi/axi_lite] SEG_data_ad9671_core_0
|
||||
create_bd_addr_seg -range 0x00010000 -offset 0x44A10000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9671_core_1/s_axi/axi_lite] SEG_data_ad9671_core_1
|
||||
create_bd_addr_seg -range 0x00010000 -offset 0x44A20000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9671_core_2/s_axi/axi_lite] SEG_data_ad9671_core_2
|
||||
create_bd_addr_seg -range 0x00010000 -offset 0x44A30000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9671_core_3/s_axi/axi_lite] SEG_data_ad9671_core_3
|
||||
|
||||
create_bd_addr_seg -range 0x00010000 -offset 0x44A60000 $sys_addr_cntrl_space [get_bd_addr_segs axi_usdrx1_gt/s_axi/axi_lite] SEG_data_usdrx1_gt
|
||||
create_bd_addr_seg -range 0x00001000 -offset 0x44A91000 $sys_addr_cntrl_space [get_bd_addr_segs axi_usdrx1_jesd/s_axi/Reg] SEG_data_usdrx1_jesd
|
||||
create_bd_addr_seg -range 0x00010000 -offset 0x7c400000 $sys_addr_cntrl_space [get_bd_addr_segs axi_usdrx1_dma/s_axi/axi_lite] SEG_data_usdrx1_dma
|
||||
create_bd_addr_seg -range 0x00010000 -offset 0x7c420000 $sys_addr_cntrl_space [get_bd_addr_segs axi_usdrx1_spi/axi_lite/Reg] SEG_data_usdrx1_spi
|
||||
|
||||
create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_usdrx1_dma/m_dest_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_sys_ps7_hp2_ddr_lowocm
|
||||
create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_usdrx1_gt/m_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP3/HP3_DDR_LOWOCM] SEG_sys_ps7_hp3_ddr_lowocm
|
||||
|
||||
ad_connect axi_ad9671_core_0/adc_clk ila_ad9671/CLK
|
||||
ad_connect adc_data_0 ila_ad9671/PROBE0
|
||||
ad_connect adc_valid_0 ila_ad9671/PROBE1
|
||||
ad_connect adc_data_1 ila_ad9671/PROBE2
|
||||
ad_connect adc_valid_1 ila_ad9671/PROBE3
|
||||
ad_connect adc_data_2 ila_ad9671/PROBE4
|
||||
ad_connect adc_valid_2 ila_ad9671/PROBE5
|
||||
ad_connect adc_data_3 ila_ad9671/PROBE6
|
||||
ad_connect adc_valid_3 ila_ad9671/PROBE7
|
||||
|
|
|
|||
|
|
@ -3,6 +3,7 @@
|
|||
|
||||
source ../../scripts/adi_env.tcl
|
||||
source $ad_hdl_dir/projects/scripts/adi_project.tcl
|
||||
source $ad_hdl_dir/projects/scripts/adi_board.tcl
|
||||
|
||||
adi_project_create usdrx1_zc706
|
||||
adi_project_files usdrx1_zc706 [list \
|
||||
|
|
|
|||
|
|
@ -41,28 +41,28 @@
|
|||
|
||||
module system_top (
|
||||
|
||||
DDR_addr,
|
||||
DDR_ba,
|
||||
DDR_cas_n,
|
||||
DDR_ck_n,
|
||||
DDR_ck_p,
|
||||
DDR_cke,
|
||||
DDR_cs_n,
|
||||
DDR_dm,
|
||||
DDR_dq,
|
||||
DDR_dqs_n,
|
||||
DDR_dqs_p,
|
||||
DDR_odt,
|
||||
DDR_ras_n,
|
||||
DDR_reset_n,
|
||||
DDR_we_n,
|
||||
ddr_addr,
|
||||
ddr_ba,
|
||||
ddr_cas_n,
|
||||
ddr_ck_n,
|
||||
ddr_ck_p,
|
||||
ddr_cke,
|
||||
ddr_cs_n,
|
||||
ddr_dm,
|
||||
ddr_dq,
|
||||
ddr_dqs_n,
|
||||
ddr_dqs_p,
|
||||
ddr_odt,
|
||||
ddr_ras_n,
|
||||
ddr_reset_n,
|
||||
ddr_we_n,
|
||||
|
||||
FIXED_IO_ddr_vrn,
|
||||
FIXED_IO_ddr_vrp,
|
||||
FIXED_IO_mio,
|
||||
FIXED_IO_ps_clk,
|
||||
FIXED_IO_ps_porb,
|
||||
FIXED_IO_ps_srstb,
|
||||
fixed_io_ddr_vrn,
|
||||
fixed_io_ddr_vrp,
|
||||
fixed_io_mio,
|
||||
fixed_io_ps_clk,
|
||||
fixed_io_ps_porb,
|
||||
fixed_io_ps_srstb,
|
||||
|
||||
gpio_bd,
|
||||
|
||||
|
|
@ -119,28 +119,28 @@ module system_top (
|
|||
prc_sdo_i,
|
||||
prc_sdo_q);
|
||||
|
||||
inout [14:0] DDR_addr;
|
||||
inout [ 2:0] DDR_ba;
|
||||
inout DDR_cas_n;
|
||||
inout DDR_ck_n;
|
||||
inout DDR_ck_p;
|
||||
inout DDR_cke;
|
||||
inout DDR_cs_n;
|
||||
inout [ 3:0] DDR_dm;
|
||||
inout [31:0] DDR_dq;
|
||||
inout [ 3:0] DDR_dqs_n;
|
||||
inout [ 3:0] DDR_dqs_p;
|
||||
inout DDR_odt;
|
||||
inout DDR_ras_n;
|
||||
inout DDR_reset_n;
|
||||
inout DDR_we_n;
|
||||
inout [14:0] ddr_addr;
|
||||
inout [ 2:0] ddr_ba;
|
||||
inout ddr_cas_n;
|
||||
inout ddr_ck_n;
|
||||
inout ddr_ck_p;
|
||||
inout ddr_cke;
|
||||
inout ddr_cs_n;
|
||||
inout [ 3:0] ddr_dm;
|
||||
inout [31:0] ddr_dq;
|
||||
inout [ 3:0] ddr_dqs_n;
|
||||
inout [ 3:0] ddr_dqs_p;
|
||||
inout ddr_odt;
|
||||
inout ddr_ras_n;
|
||||
inout ddr_reset_n;
|
||||
inout ddr_we_n;
|
||||
|
||||
inout FIXED_IO_ddr_vrn;
|
||||
inout FIXED_IO_ddr_vrp;
|
||||
inout [53:0] FIXED_IO_mio;
|
||||
inout FIXED_IO_ps_clk;
|
||||
inout FIXED_IO_ps_porb;
|
||||
inout FIXED_IO_ps_srstb;
|
||||
inout fixed_io_ddr_vrn;
|
||||
inout fixed_io_ddr_vrp;
|
||||
inout [53:0] fixed_io_mio;
|
||||
inout fixed_io_ps_clk;
|
||||
inout fixed_io_ps_porb;
|
||||
inout fixed_io_ps_srstb;
|
||||
|
||||
inout [14:0] gpio_bd;
|
||||
|
||||
|
|
@ -235,9 +235,9 @@ module system_top (
|
|||
wire gt_rx_data_sof_2;
|
||||
wire [63:0] gt_rx_data_3;
|
||||
wire gt_rx_data_sof_3;
|
||||
wire [58:0] gpio_i;
|
||||
wire [58:0] gpio_o;
|
||||
wire [58:0] gpio_t;
|
||||
wire [63:0] gpio_i;
|
||||
wire [63:0] gpio_o;
|
||||
wire [63:0] gpio_t;
|
||||
wire [15:0] ps_intrs;
|
||||
|
||||
// spi assignments
|
||||
|
|
@ -360,30 +360,30 @@ module system_top (
|
|||
endgenerate
|
||||
|
||||
system_wrapper i_system_wrapper (
|
||||
.DDR_addr (DDR_addr),
|
||||
.DDR_ba (DDR_ba),
|
||||
.DDR_cas_n (DDR_cas_n),
|
||||
.DDR_ck_n (DDR_ck_n),
|
||||
.DDR_ck_p (DDR_ck_p),
|
||||
.DDR_cke (DDR_cke),
|
||||
.DDR_cs_n (DDR_cs_n),
|
||||
.DDR_dm (DDR_dm),
|
||||
.DDR_dq (DDR_dq),
|
||||
.DDR_dqs_n (DDR_dqs_n),
|
||||
.DDR_dqs_p (DDR_dqs_p),
|
||||
.DDR_odt (DDR_odt),
|
||||
.DDR_ras_n (DDR_ras_n),
|
||||
.DDR_reset_n (DDR_reset_n),
|
||||
.DDR_we_n (DDR_we_n),
|
||||
.FIXED_IO_ddr_vrn (FIXED_IO_ddr_vrn),
|
||||
.FIXED_IO_ddr_vrp (FIXED_IO_ddr_vrp),
|
||||
.FIXED_IO_mio (FIXED_IO_mio),
|
||||
.FIXED_IO_ps_clk (FIXED_IO_ps_clk),
|
||||
.FIXED_IO_ps_porb (FIXED_IO_ps_porb),
|
||||
.FIXED_IO_ps_srstb (FIXED_IO_ps_srstb),
|
||||
.GPIO_I (gpio_i),
|
||||
.GPIO_O (gpio_o),
|
||||
.GPIO_T (gpio_t),
|
||||
.ddr_addr (ddr_addr),
|
||||
.ddr_ba (ddr_ba),
|
||||
.ddr_cas_n (ddr_cas_n),
|
||||
.ddr_ck_n (ddr_ck_n),
|
||||
.ddr_ck_p (ddr_ck_p),
|
||||
.ddr_cke (ddr_cke),
|
||||
.ddr_cs_n (ddr_cs_n),
|
||||
.ddr_dm (ddr_dm),
|
||||
.ddr_dq (ddr_dq),
|
||||
.ddr_dqs_n (ddr_dqs_n),
|
||||
.ddr_dqs_p (ddr_dqs_p),
|
||||
.ddr_odt (ddr_odt),
|
||||
.ddr_ras_n (ddr_ras_n),
|
||||
.ddr_reset_n (ddr_reset_n),
|
||||
.ddr_we_n (ddr_we_n),
|
||||
.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
|
||||
.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
|
||||
.fixed_io_mio (fixed_io_mio),
|
||||
.fixed_io_ps_clk (fixed_io_ps_clk),
|
||||
.fixed_io_ps_porb (fixed_io_ps_porb),
|
||||
.fixed_io_ps_srstb (fixed_io_ps_srstb),
|
||||
.gpio_i (gpio_i),
|
||||
.gpio_o (gpio_o),
|
||||
.gpio_t (gpio_t),
|
||||
.adc_data (adc_data),
|
||||
.adc_data_0 (adc_data_0),
|
||||
.adc_data_1 (adc_data_1),
|
||||
|
|
@ -420,22 +420,18 @@ module system_top (
|
|||
.hdmi_vsync (hdmi_vsync),
|
||||
.iic_main_scl_io (iic_scl),
|
||||
.iic_main_sda_io (iic_sda),
|
||||
.ps_intr_0 (ps_intrs[0]),
|
||||
.ps_intr_1 (ps_intrs[1]),
|
||||
.ps_intr_2 (ps_intrs[2]),
|
||||
.ps_intr_3 (ps_intrs[3]),
|
||||
.ps_intr_4 (ps_intrs[4]),
|
||||
.ps_intr_5 (ps_intrs[5]),
|
||||
.ps_intr_6 (ps_intrs[6]),
|
||||
.ps_intr_7 (ps_intrs[7]),
|
||||
.ps_intr_8 (ps_intrs[8]),
|
||||
.ps_intr_9 (ps_intrs[9]),
|
||||
.ps_intr_10 (ps_intrs[10]),
|
||||
.ps_intr_11 (ps_intrs[11]),
|
||||
.ps_intr_12 (ps_intrs[12]),
|
||||
.ps_intr_13 (ps_intrs[13]),
|
||||
.usdrx1_dma_irq (ps_intrs[13]),
|
||||
.usdrx1_spi_irq (ps_intrs[12]),
|
||||
.ps_intr_00 (1'b0),
|
||||
.ps_intr_01 (1'b0),
|
||||
.ps_intr_02 (1'b0),
|
||||
.ps_intr_03 (1'b0),
|
||||
.ps_intr_04 (1'b0),
|
||||
.ps_intr_05 (1'b0),
|
||||
.ps_intr_06 (1'b0),
|
||||
.ps_intr_07 (1'b0),
|
||||
.ps_intr_08 (1'b0),
|
||||
.ps_intr_09 (1'b0),
|
||||
.ps_intr_10 (1'b0),
|
||||
.ps_intr_11 (1'b0),
|
||||
.rx_data_n (rx_data_n),
|
||||
.rx_data_p (rx_data_p),
|
||||
.rx_ref_clk (rx_ref_clk),
|
||||
|
|
|
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Reference in New Issue