diff --git a/library/axi_ad9625/axi_ad9625.v b/library/axi_ad9625/axi_ad9625.v
index 940da11c3..e45ab9402 100644
--- a/library/axi_ad9625/axi_ad9625.v
+++ b/library/axi_ad9625/axi_ad9625.v
@@ -198,7 +198,6 @@ module axi_ad9625 #(
     .adc_clk_ratio (32'd16),
     .adc_start_code (),
     .adc_sync (),
-    .adc_sref_sync (),
     .adc_sref_sync (adc_sref_sync_s),
     .up_status_pn_err (up_adc_pn_err_s),
     .up_status_pn_oos (up_adc_pn_oos_s),
diff --git a/library/axi_fmcadc5_sync/axi_fmcadc5_sync.v b/library/axi_fmcadc5_sync/axi_fmcadc5_sync.v
index 6a250b91b..d4c840869 100644
--- a/library/axi_fmcadc5_sync/axi_fmcadc5_sync.v
+++ b/library/axi_fmcadc5_sync/axi_fmcadc5_sync.v
@@ -58,8 +58,8 @@ module axi_fmcadc5_sync #(parameter integer ID = 0) (
   input   [255:0]   rx_data_0,
   input             rx_enable_1,
   input   [255:0]   rx_data_1,
-  output            rx_cor_enable,
-  output  [511:0]   rx_cor_data,
+  output            rx_enable,
+  output  [511:0]   rx_data,
 
   // calibration signal
 
@@ -644,8 +644,8 @@ module axi_fmcadc5_sync #(parameter integer ID = 0) (
     .rx_data_0 (rx_data_0),
     .rx_enable_1 (rx_enable_1),
     .rx_data_1 (rx_data_1),
-    .rx_cor_enable (rx_cor_enable),
-    .rx_cor_data (rx_cor_data),
+    .rx_enable (rx_enable),
+    .rx_data (rx_data),
     .rx_cal_enable (rx_cal_enable),
     .rx_cal_done_t (rx_cal_done_t_s),
     .rx_cal_max_0 (rx_cal_max_0_s),
diff --git a/library/axi_fmcadc5_sync/axi_fmcadc5_sync_calcor.v b/library/axi_fmcadc5_sync/axi_fmcadc5_sync_calcor.v
index 60f0ae001..f2181001b 100644
--- a/library/axi_fmcadc5_sync/axi_fmcadc5_sync_calcor.v
+++ b/library/axi_fmcadc5_sync/axi_fmcadc5_sync_calcor.v
@@ -49,8 +49,8 @@ module axi_fmcadc5_sync_calcor (
   input   [255:0]   rx_data_0,
   input             rx_enable_1,
   input   [255:0]   rx_data_1,
-  output            rx_cor_enable,
-  output  [511:0]   rx_cor_data,
+  output            rx_enable,
+  output  [511:0]   rx_data,
 
   // calibration signals
 
@@ -67,7 +67,7 @@ module axi_fmcadc5_sync_calcor (
 
   // internal registers
 
-  reg               rx_cor_enable_int = 'd0;
+  reg               rx_enable_int = 'd0;
   reg     [ 15:0]   rx_cor_data_0[0:15];
   reg     [ 15:0]   rx_cor_data_1[0:15];
   reg               rx_cal_done_int_t = 'd0;
@@ -109,16 +109,16 @@ module axi_fmcadc5_sync_calcor (
 
   // offset & gain
  
-  assign rx_cor_enable = rx_cor_enable_int;
+  assign rx_enable = rx_enable_int;
 
   always @(posedge rx_clk) begin
-    rx_cor_enable_int = rx_enable_0 & rx_enable_1;
+    rx_enable_int = rx_enable_0 & rx_enable_1;
   end
 
   generate
   for (n = 0; n <= 15; n = n + 1) begin: g_rx_cal_data
-  assign rx_cor_data[((n*32)+15):((n*32)+ 0)] = rx_cor_data_0_s[n][30:15];
-  assign rx_cor_data[((n*32)+31):((n*32)+16)] = rx_cor_data_1_s[n][30:15];
+  assign rx_data[((n*32)+15):((n*32)+ 0)] = rx_cor_data_0_s[n][30:15];
+  assign rx_data[((n*32)+31):((n*32)+16)] = rx_cor_data_1_s[n][30:15];
   end
   endgenerate
 
diff --git a/projects/fmcadc5/common/fmcadc5_bd.tcl b/projects/fmcadc5/common/fmcadc5_bd.tcl
index 6cad1c8ea..98c136fa7 100644
--- a/projects/fmcadc5/common/fmcadc5_bd.tcl
+++ b/projects/fmcadc5/common/fmcadc5_bd.tcl
@@ -172,8 +172,8 @@ ad_connect  axi_ad9625_0_core/adc_enable axi_fmcadc5_sync/rx_enable_0
 ad_connect  axi_ad9625_0_core/adc_data axi_fmcadc5_sync/rx_data_0
 ad_connect  axi_ad9625_1_core/adc_enable axi_fmcadc5_sync/rx_enable_1
 ad_connect  axi_ad9625_1_core/adc_data axi_fmcadc5_sync/rx_data_1
-ad_connect  axi_fmcadc5_sync/rx_cor_enable axi_ad9625_fifo/adc_wr
-ad_connect  axi_fmcadc5_sync/rx_cor_data axi_ad9625_fifo/adc_wdata
+ad_connect  axi_fmcadc5_sync/rx_enable axi_ad9625_fifo/adc_wr
+ad_connect  axi_fmcadc5_sync/rx_data axi_ad9625_fifo/adc_wdata
 ad_connect  axi_fmcadc5_sync/rx_sysref axi_ad9625_0_jesd/rx_sysref
 ad_connect  axi_ad9625_0_jesd/rx_sync axi_fmcadc5_sync/rx_sync_0
 ad_connect  axi_fmcadc5_sync/rx_sysref axi_ad9625_1_jesd/rx_sysref
diff --git a/projects/fmcadc5/vc707/system_bd.tcl b/projects/fmcadc5/vc707/system_bd.tcl
index 8ec4f541e..37c9cbec4 100644
--- a/projects/fmcadc5/vc707/system_bd.tcl
+++ b/projects/fmcadc5/vc707/system_bd.tcl
@@ -25,8 +25,8 @@ ad_ip_parameter ila_adc CONFIG.C_PROBE1_WIDTH 16
 
 ad_connect  util_fmcadc5_0_xcvr/rx_out_clk_0 mfifo_adc/din_clk
 ad_connect  axi_ad9625_0_jesd_rstgen/peripheral_reset mfifo_adc/din_rst
-ad_connect  axi_fmcadc5_sync/rx_cor_enable mfifo_adc/din_valid
-ad_connect  axi_fmcadc5_sync/rx_cor_data mfifo_adc/din_data_0
+ad_connect  axi_fmcadc5_sync/rx_enable mfifo_adc/din_valid
+ad_connect  axi_fmcadc5_sync/rx_data mfifo_adc/din_data_0
 ad_connect  axi_ad9625_0_jesd_rstgen/peripheral_reset mfifo_adc/dout_rst
 ad_connect  util_fmcadc5_0_xcvr/rx_out_clk_0 mfifo_adc/dout_clk
 ad_connect  util_fmcadc5_0_xcvr/rx_out_clk_0 ila_adc/clk