zcy
/
pluto_hdl_adi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

daq1_zed: Lower the adc and daq clock to 450MHz 

The FPGA fabric on zedboard is a -1 speadgrade (max bufg clk 464MHz)
main
AndreiGrozav 2017-09-26 10:33:35 +03:00
parent 7a3c4ab81f
commit 03e744f0f1
1 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
projects/daq1/zed/system_constr.xdc
View File

@ -78,6 +78,6 @@ set_property -dict {PACKAGE_PIN K21 IOSTANDARD LVCMOS25} [get_ports spi_int]
# clocks # clocks
create_clock -name dac_clk_in -period 2.00 [get_ports dac_clk_in_p] create_clock -name dac_clk_in -period 2.222 [get_ports dac_clk_in_p]
create_clock -name adc_clk_in -period 2.00 [get_ports adc_clk_in_p] create_clock -name adc_clk_in -period 2.222 [get_ports adc_clk_in_p]