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usrpe31x: Add the second channel

main
Adrian Costina 2018-06-12 12:42:02 +03:00
parent da54677101
commit 03fa46f2fc
1 changed files with 18 additions and 8 deletions
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26
projects/usrpe31x/system_bd.tcl
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@ -191,10 +191,10 @@ ad_ip_parameter axi_ad9361_dac_dma CONFIG.SYNC_TRANSFER_START 0
ad_ip_parameter axi_ad9361_dac_dma CONFIG.AXI_SLICE_SRC 0 ad_ip_parameter axi_ad9361_dac_dma CONFIG.AXI_SLICE_SRC 0
ad_ip_parameter axi_ad9361_dac_dma CONFIG.AXI_SLICE_DEST 1 ad_ip_parameter axi_ad9361_dac_dma CONFIG.AXI_SLICE_DEST 1
ad_ip_parameter axi_ad9361_dac_dma CONFIG.DMA_2D_TRANSFER 0 ad_ip_parameter axi_ad9361_dac_dma CONFIG.DMA_2D_TRANSFER 0
ad_ip_parameter axi_ad9361_dac_dma CONFIG.DMA_DATA_WIDTH_DEST 32 ad_ip_parameter axi_ad9361_dac_dma CONFIG.DMA_DATA_WIDTH_DEST 64
ad_ip_instance util_upack util_ad9361_dac_upack ad_ip_instance util_upack util_ad9361_dac_upack
ad_ip_parameter util_ad9361_dac_upack CONFIG.NUM_OF_CHANNELS 2 ad_ip_parameter util_ad9361_dac_upack CONFIG.NUM_OF_CHANNELS 4
ad_ip_parameter util_ad9361_dac_upack CONFIG.CHANNEL_DATA_WIDTH 16 ad_ip_parameter util_ad9361_dac_upack CONFIG.CHANNEL_DATA_WIDTH 16
ad_ip_instance axi_dmac axi_ad9361_adc_dma ad_ip_instance axi_dmac axi_ad9361_adc_dma
@ -205,10 +205,10 @@ ad_ip_parameter axi_ad9361_adc_dma CONFIG.SYNC_TRANSFER_START 1
ad_ip_parameter axi_ad9361_adc_dma CONFIG.AXI_SLICE_SRC 0 ad_ip_parameter axi_ad9361_adc_dma CONFIG.AXI_SLICE_SRC 0
ad_ip_parameter axi_ad9361_adc_dma CONFIG.AXI_SLICE_DEST 0 ad_ip_parameter axi_ad9361_adc_dma CONFIG.AXI_SLICE_DEST 0
ad_ip_parameter axi_ad9361_adc_dma CONFIG.DMA_2D_TRANSFER 0 ad_ip_parameter axi_ad9361_adc_dma CONFIG.DMA_2D_TRANSFER 0
ad_ip_parameter axi_ad9361_adc_dma CONFIG.DMA_DATA_WIDTH_SRC 32 ad_ip_parameter axi_ad9361_adc_dma CONFIG.DMA_DATA_WIDTH_SRC 64
ad_ip_instance util_cpack util_ad9361_adc_pack ad_ip_instance util_cpack util_ad9361_adc_pack
ad_ip_parameter util_ad9361_adc_pack CONFIG.NUM_OF_CHANNELS 2 ad_ip_parameter util_ad9361_adc_pack CONFIG.NUM_OF_CHANNELS 4
ad_ip_parameter util_ad9361_adc_pack CONFIG.CHANNEL_DATA_WIDTH 16 ad_ip_parameter util_ad9361_adc_pack CONFIG.CHANNEL_DATA_WIDTH 16
# connections # connections
@ -235,6 +235,12 @@ ad_connect axi_ad9361/adc_data_i0 util_ad9361_adc_pack/adc_data_0
ad_connect axi_ad9361/adc_enable_q0 util_ad9361_adc_pack/adc_enable_1 ad_connect axi_ad9361/adc_enable_q0 util_ad9361_adc_pack/adc_enable_1
ad_connect axi_ad9361/adc_valid_q0 util_ad9361_adc_pack/adc_valid_1 ad_connect axi_ad9361/adc_valid_q0 util_ad9361_adc_pack/adc_valid_1
ad_connect axi_ad9361/adc_data_q0 util_ad9361_adc_pack/adc_data_1 ad_connect axi_ad9361/adc_data_q0 util_ad9361_adc_pack/adc_data_1
ad_connect axi_ad9361/adc_enable_i1 util_ad9361_adc_pack/adc_enable_2
ad_connect axi_ad9361/adc_valid_i1 util_ad9361_adc_pack/adc_valid_2
ad_connect axi_ad9361/adc_data_i1 util_ad9361_adc_pack/adc_data_2
ad_connect axi_ad9361/adc_enable_q1 util_ad9361_adc_pack/adc_enable_3
ad_connect axi_ad9361/adc_valid_q1 util_ad9361_adc_pack/adc_valid_3
ad_connect axi_ad9361/adc_data_q1 util_ad9361_adc_pack/adc_data_3
ad_connect axi_ad9361/l_clk axi_ad9361_adc_dma/fifo_wr_clk ad_connect axi_ad9361/l_clk axi_ad9361_adc_dma/fifo_wr_clk
ad_connect util_ad9361_adc_pack/adc_valid axi_ad9361_adc_dma/fifo_wr_en ad_connect util_ad9361_adc_pack/adc_valid axi_ad9361_adc_dma/fifo_wr_en
ad_connect util_ad9361_adc_pack/adc_sync axi_ad9361_adc_dma/fifo_wr_sync ad_connect util_ad9361_adc_pack/adc_sync axi_ad9361_adc_dma/fifo_wr_sync
@ -243,16 +249,20 @@ ad_connect axi_ad9361_adc_dma/fifo_wr_overflow axi_ad9361/adc_dovf
ad_connect axi_ad9361/l_clk util_ad9361_dac_upack/dac_clk ad_connect axi_ad9361/l_clk util_ad9361_dac_upack/dac_clk
ad_connect axi_ad9361/dac_enable_i0 util_ad9361_dac_upack/dac_enable_0 ad_connect axi_ad9361/dac_enable_i0 util_ad9361_dac_upack/dac_enable_0
ad_connect axi_ad9361/dac_valid_i0 util_ad9361_dac_upack/dac_valid_0 ad_connect axi_ad9361/dac_valid_i0 util_ad9361_dac_upack/dac_valid_0
ad_connect util_ad9361_dac_upack/dac_data_0 axi_ad9361/dac_data_i0 ad_connect axi_ad9361/dac_data_i0 util_ad9361_dac_upack/dac_data_0
ad_connect axi_ad9361/dac_enable_q0 util_ad9361_dac_upack/dac_enable_1 ad_connect axi_ad9361/dac_enable_q0 util_ad9361_dac_upack/dac_enable_1
ad_connect axi_ad9361/dac_valid_q0 util_ad9361_dac_upack/dac_valid_1 ad_connect axi_ad9361/dac_valid_q0 util_ad9361_dac_upack/dac_valid_1
ad_connect util_ad9361_dac_upack/dac_data_1 axi_ad9361/dac_data_q0 ad_connect axi_ad9361/dac_data_q0 util_ad9361_dac_upack/dac_data_1
ad_connect axi_ad9361/dac_enable_i1 util_ad9361_dac_upack/dac_enable_2
ad_connect axi_ad9361/dac_valid_i1 util_ad9361_dac_upack/dac_valid_2
ad_connect axi_ad9361/dac_data_i1 util_ad9361_dac_upack/dac_data_2
ad_connect axi_ad9361/dac_enable_q1 util_ad9361_dac_upack/dac_enable_3
ad_connect axi_ad9361/dac_valid_q1 util_ad9361_dac_upack/dac_valid_3
ad_connect axi_ad9361/dac_data_q1 util_ad9361_dac_upack/dac_data_3
ad_connect axi_ad9361/l_clk axi_ad9361_dac_dma/fifo_rd_clk ad_connect axi_ad9361/l_clk axi_ad9361_dac_dma/fifo_rd_clk
ad_connect util_ad9361_dac_upack/dac_valid axi_ad9361_dac_dma/fifo_rd_en ad_connect util_ad9361_dac_upack/dac_valid axi_ad9361_dac_dma/fifo_rd_en
ad_connect axi_ad9361_dac_dma/fifo_rd_dout util_ad9361_dac_upack/dac_data ad_connect axi_ad9361_dac_dma/fifo_rd_dout util_ad9361_dac_upack/dac_data
ad_connect axi_ad9361_dac_dma/fifo_rd_underflow axi_ad9361/dac_dunf ad_connect axi_ad9361_dac_dma/fifo_rd_underflow axi_ad9361/dac_dunf
ad_connect axi_ad9361/dac_data_i1 GND
ad_connect axi_ad9361/dac_data_q1 GND
# interconnects # interconnects