cn0540: Add de10nano reference design
Stanca Pop
István Csomortáni
parent
ad8d2d225f
commit
043ddbaf9f
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# receive dma
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add_instance axi_dmac_0 axi_dmac
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set_instance_parameter_value axi_dmac_0 {DMA_TYPE_SRC} {1}
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set_instance_parameter_value axi_dmac_0 {DMA_TYPE_DEST} {0}
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set_instance_parameter_value axi_dmac_0 {CYCLIC} {0}
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set_instance_parameter_value axi_dmac_0 {DMA_DATA_WIDTH_SRC} {32}
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set_instance_parameter_value axi_dmac_0 {DMA_DATA_WIDTH_DEST} {64}
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# axi_spi_engine
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add_instance axi_spi_engine_0 axi_spi_engine
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set_instance_parameter_value axi_spi_engine_0 {ASYNC_SPI_CLK} {1}
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set_instance_parameter_value axi_spi_engine_0 {DATA_WIDTH} {32}
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set_instance_parameter_value axi_spi_engine_0 {MM_IF_TYPE} {0}
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set_instance_parameter_value axi_spi_engine_0 {NUM_OF_SDI} {1}
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set_instance_parameter_value axi_spi_engine_0 {NUM_OFFLOAD} {1}
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# spi_engine_execution
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add_instance spi_engine_execution_0 spi_engine_execution
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set_instance_parameter_value spi_engine_execution_0 {DATA_WIDTH} {32}
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set_instance_parameter_value spi_engine_execution_0 {NUM_OF_SDI} {1}
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set_instance_parameter_value spi_engine_execution_0 {SDI_DELAY} {0}
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# spi_engine_interconnect
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add_instance spi_engine_interconnect_0 spi_engine_interconnect
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set_instance_parameter_value spi_engine_interconnect_0 {DATA_WIDTH} {32}
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set_instance_parameter_value spi_engine_interconnect_0 {NUM_OF_SDI} {1}
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# spi_engine_offload
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add_instance spi_engine_offload_0 spi_engine_offload
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set_instance_parameter_value spi_engine_offload_0 {ASYNC_TRIG} {1}
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set_instance_parameter_value spi_engine_offload_0 {ASYNC_SPI_CLK} {0}
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set_instance_parameter_value spi_engine_offload_0 {DATA_WIDTH} {32}
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set_instance_parameter_value spi_engine_offload_0 {NUM_OF_SDI} {1}
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# exported interface
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add_interface cn0540_spi_sclk clock source
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add_interface cn0540_spi_cs conduit end
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add_interface cn0540_spi_sdi conduit end
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add_interface cn0540_spi_sdo conduit end
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add_interface cn0540_spi_trigger conduit end
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set_interface_property cn0540_spi_cs EXPORT_OF spi_engine_execution_0.if_cs
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set_interface_property cn0540_spi_sclk EXPORT_OF spi_engine_execution_0.if_sclk
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set_interface_property cn0540_spi_sdi EXPORT_OF spi_engine_execution_0.if_sdi
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set_interface_property cn0540_spi_sdo EXPORT_OF spi_engine_execution_0.if_sdo
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set_interface_property cn0540_spi_trigger EXPORT_OF spi_engine_offload_0.if_trigger
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# clocks
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add_connection sys_clk.clk axi_spi_engine_0.s_axi_clock
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add_connection sys_clk.clk axi_dmac_0.s_axi_clock
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add_connection sys_dma_clk.clk spi_engine_execution_0.if_clk
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add_connection sys_dma_clk.clk spi_engine_interconnect_0.if_clk
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add_connection sys_dma_clk.clk axi_spi_engine_0.if_spi_clk
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add_connection sys_dma_clk.clk spi_engine_offload_0.if_ctrl_clk
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add_connection sys_dma_clk.clk spi_engine_offload_0.if_spi_clk
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add_connection sys_dma_clk.clk axi_dmac_0.if_s_axis_aclk
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add_connection sys_dma_clk.clk axi_dmac_0.m_dest_axi_clock
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# resets
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add_connection sys_clk.clk_reset axi_spi_engine_0.s_axi_reset
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add_connection sys_clk.clk_reset axi_dmac_0.s_axi_reset
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add_connection axi_spi_engine_0.if_spi_resetn spi_engine_execution_0.if_resetn
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add_connection axi_spi_engine_0.if_spi_resetn spi_engine_interconnect_0.if_resetn
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add_connection axi_spi_engine_0.if_spi_resetn spi_engine_offload_0.if_spi_resetn
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add_connection sys_dma_clk.clk_reset axi_dmac_0.m_dest_axi_reset
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# interfaces
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add_connection spi_engine_interconnect_0.m_cmd spi_engine_execution_0.cmd
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add_connection spi_engine_execution_0.sdi_data spi_engine_interconnect_0.m_sdi
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add_connection spi_engine_interconnect_0.m_sdo spi_engine_execution_0.sdo_data
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add_connection spi_engine_execution_0.sync spi_engine_interconnect_0.m_sync
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add_connection axi_spi_engine_0.cmd spi_engine_interconnect_0.s0_cmd
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add_connection spi_engine_interconnect_0.s0_sdi axi_spi_engine_0.sdi_data
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add_connection axi_spi_engine_0.sdo_data spi_engine_interconnect_0.s0_sdo
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add_connection spi_engine_interconnect_0.s0_sync axi_spi_engine_0.sync
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add_connection spi_engine_offload_0.cmd spi_engine_interconnect_0.s1_cmd
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add_connection spi_engine_interconnect_0.s1_sdi spi_engine_offload_0.sdi_data
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add_connection spi_engine_offload_0.sdo_data spi_engine_interconnect_0.s1_sdo
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add_connection spi_engine_interconnect_0.s1_sync spi_engine_offload_0.sync
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add_connection spi_engine_offload_0.ctrl_cmd_wr axi_spi_engine_0.offload0_cmd
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add_connection spi_engine_offload_0.ctrl_sdo_wr axi_spi_engine_0.offload0_sdo
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add_connection spi_engine_offload_0.if_ctrl_enable axi_spi_engine_0.if_offload0_enable
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add_connection spi_engine_offload_0.if_ctrl_enabled axi_spi_engine_0.if_offload0_enabled
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add_connection spi_engine_offload_0.if_ctrl_mem_reset axi_spi_engine_0.if_offload0_mem_reset
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add_connection spi_engine_offload_0.status_sync axi_spi_engine_0.offload_sync
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add_connection spi_engine_offload_0.offload_sdi axi_dmac_0.s_axis
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# cpu interconnects
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ad_cpu_interconnect 0x00020000 axi_dmac_0.s_axi
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ad_cpu_interconnect 0x00030000 axi_spi_engine_0.s_axi
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# dma interconnect
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ad_dma_interconnect axi_dmac_0.m_dest_axi
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#interrupts
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ad_cpu_interrupt 4 axi_dmac_0.interrupt_sender
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ad_cpu_interrupt 5 axi_spi_engine_0.interrupt_sender
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@ -0,0 +1,14 @@
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####################################################################################
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## Copyright 2019 - 2020(c) Analog Devices, Inc.
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## Auto-generated, do not modify!
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####################################################################################
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PROJECT_NAME := cn0540_de10nano
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M_DEPS += ../common/cn0540_qsys.tcl
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M_DEPS += ../../common/de10nano/de10nano_system_assign.tcl
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M_DEPS += ../../common/de10nano/de10nano_system_qsys.tcl
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LIB_DEPS += axi_dmac
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include ../../scripts/project-intel.mk
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create_clock -period "20.000 ns" -name sys_clk [get_ports {sys_clk}]
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create_clock -period "16.666 ns" -name usb1_clk [get_ports {usb1_clk}]
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derive_pll_clocks
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derive_clock_uncertainty
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@ -0,0 +1,57 @@
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source ../../scripts/adi_env.tcl
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source ../../scripts/adi_project_intel.tcl
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adi_project cn0540_de10nano
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source $ad_hdl_dir/projects/common/de10nano/de10nano_system_assign.tcl
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# files
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# SPI interface for ad7768-1
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set_location_assignment PIN_AH12 -to cn0540_spi_sclk ; ## Arduino_IO13
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set_location_assignment PIN_AH11 -to cn0540_spi_miso ; ## Arduino_IO12
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set_location_assignment PIN_AG16 -to cn0540_spi_mosi ; ## Arduino_IO11
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set_location_assignment PIN_AF15 -to cn0540_spi_cs ; ## Arduino_IO10
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to cn0540_spi_sclk
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to cn0540_spi_miso
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to cn0540_spi_mosi
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to cn0540_spi_cs
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# I2C
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set_location_assignment PIN_AG11 -to i2c_scl ; ## Arduino_IO15
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set_location_assignment PIN_AH9 -to i2c_sda ; ## Arduino_IO14
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to i2c_scl
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to i2c_sda
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# reset and GPIO signals
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set_location_assignment PIN_AE15 -to cn0540_shutdown ; ## Arduino_IO9
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set_location_assignment PIN_AH8 -to cn0540_reset_adc ; ## Arduino_IO7
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set_location_assignment PIN_U13 -to cn0540_csb_aux ; ## Arduino_IO5
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set_location_assignment PIN_U14 -to cn0540_sw_ff ; ## Arduino_IO4
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set_location_assignment PIN_AG9 -to cn0540_drdy_aux ; ## Arduino_IO3
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set_location_assignment PIN_AF13 -to cn0540_blue_led ; ## Arduino_IO1
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set_location_assignment PIN_AG13 -to cn0540_yellow_led ; ## Arduino_IO0
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to cn0540_shutdown
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to cn0540_reset_adc
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to cn0540_csb_aux
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to cn0540_sw_ff
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to cn0540_drdy_aux
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to cn0540_blue_led
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to cn0540_yellow_led
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# synchronization and timing
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set_location_assignment PIN_AG8 -to cn0540_sync_in ; ## Arduino_IO6
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set_location_assignment PIN_AG10 -to cn0540_drdy ; ## Arduino_IO2
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to cn0540_sync_in
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to cn0540_drdy
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execute_flow -compile
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@ -0,0 +1,6 @@
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set dac_fifo_address_width 10
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source $ad_hdl_dir/projects/common/de10nano/de10nano_system_qsys.tcl
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source ../common/cn0540_qsys.tcl
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@ -0,0 +1,302 @@
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2019 - 2020 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsabilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module system_top (
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// clock and resets
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input sys_clk,
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// hps-ddr
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output [14:0] ddr3_a,
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output [ 2:0] ddr3_ba,
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output ddr3_reset_n,
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output ddr3_ck_p,
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output ddr3_ck_n,
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output ddr3_cke,
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output ddr3_cs_n,
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output ddr3_ras_n,
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output ddr3_cas_n,
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output ddr3_we_n,
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inout [31:0] ddr3_dq,
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inout [ 3:0] ddr3_dqs_p,
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inout [ 3:0] ddr3_dqs_n,
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output [ 3:0] ddr3_dm,
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output ddr3_odt,
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input ddr3_rzq,
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// hps-ethernet
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output eth1_tx_clk,
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output eth1_tx_ctl,
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output [ 3:0] eth1_tx_d,
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input eth1_rx_clk,
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input eth1_rx_ctl,
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input [ 3:0] eth1_rx_d,
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output eth1_mdc,
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inout eth1_mdio,
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// hps-sdio
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output sdio_clk,
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inout sdio_cmd,
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inout [ 3:0] sdio_d,
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// hps-spim1
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output spim1_ss0,
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output spim1_clk,
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output spim1_mosi,
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input spim1_miso,
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// hps-usb
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input usb1_clk,
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output usb1_stp,
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input usb1_dir,
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input usb1_nxt,
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inout [ 7:0] usb1_d,
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// hps-uart
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input uart0_rx,
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output uart0_tx,
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// board gpio
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output [ 7:0] gpio_bd_o,
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input [ 5:0] gpio_bd_i,
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// hdmi
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output hdmi_out_clk,
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output hdmi_vsync,
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output hdmi_hsync,
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output hdmi_data_e,
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output [ 23:0] hdmi_data,
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inout hdmi_i2c_scl,
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inout hdmi_i2c_sda,
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// cn0540
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inout i2c_sda,
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inout i2c_scl,
|
||||||
|
|
||||||
|
input cn0540_spi_miso,
|
||||||
|
output cn0540_spi_mosi,
|
||||||
|
output cn0540_spi_sclk,
|
||||||
|
output cn0540_spi_cs,
|
||||||
|
input cn0540_drdy,
|
||||||
|
|
||||||
|
output cn0540_reset_adc,
|
||||||
|
output cn0540_shutdown,
|
||||||
|
output cn0540_csb_aux,
|
||||||
|
input cn0540_sw_ff,
|
||||||
|
output cn0540_drdy_aux,
|
||||||
|
output cn0540_blue_led,
|
||||||
|
output cn0540_yellow_led,
|
||||||
|
output cn0540_sync_in,
|
||||||
|
|
||||||
|
output ltc2308_cs,
|
||||||
|
output ltc2308_sclk,
|
||||||
|
output ltc2308_mosi,
|
||||||
|
input ltc2308_miso
|
||||||
|
);
|
||||||
|
|
||||||
|
// internal signals
|
||||||
|
|
||||||
|
wire sys_resetn;
|
||||||
|
wire [63:0] gpio_i;
|
||||||
|
wire [63:0] gpio_o;
|
||||||
|
|
||||||
|
wire i2c1_scl;
|
||||||
|
wire i2c1_scl_oe;
|
||||||
|
wire i2c1_sda;
|
||||||
|
wire i2c1_sda_oe;
|
||||||
|
|
||||||
|
wire i2c0_out_data;
|
||||||
|
wire i2c0_sda;
|
||||||
|
wire i2c0_out_clk;
|
||||||
|
wire i2c0_scl_in_clk;
|
||||||
|
|
||||||
|
// instantiations
|
||||||
|
|
||||||
|
// unused
|
||||||
|
assign gpio_i[63:42] = gpio_o[63:42];
|
||||||
|
|
||||||
|
// GPIO outputs
|
||||||
|
assign ltc2308_cs = gpio_o[41];
|
||||||
|
assign cn0540_blue_led = gpio_o[40];
|
||||||
|
assign cn0540_yellow_led = gpio_o[39];
|
||||||
|
assign cn0540_shutdown = gpio_o[36];
|
||||||
|
assign cn0540_drdy_aux = gpio_o[35];
|
||||||
|
assign cn0540_sync_in = gpio_o[33];
|
||||||
|
assign cn0540_csb_aux = gpio_o[34];
|
||||||
|
assign cn0540_reset_adc = gpio_o[32];
|
||||||
|
|
||||||
|
assign gpio_bd_o[7:0] = gpio_o[7:0];
|
||||||
|
|
||||||
|
// GPIO inputs
|
||||||
|
assign gpio_i[37] = cn0540_drdy;
|
||||||
|
assign gpio_i[38] = cn0540_sw_ff;
|
||||||
|
|
||||||
|
assign gpio_i[31:14] = gpio_o[31:14];
|
||||||
|
assign gpio_i[13:8] = gpio_bd_i[5:0];
|
||||||
|
|
||||||
|
|
||||||
|
// IO Buffers for I2C
|
||||||
|
|
||||||
|
ALT_IOBUF scl_iobuf (
|
||||||
|
.i(1'b0),
|
||||||
|
.oe(i2c1_scl_oe),
|
||||||
|
.o(i2c1_scl),
|
||||||
|
.io(i2c_scl));
|
||||||
|
|
||||||
|
ALT_IOBUF sda_iobuf (
|
||||||
|
.i(1'b0),
|
||||||
|
.oe(i2c1_sda_oe),
|
||||||
|
.o(i2c1_sda),
|
||||||
|
.io(i2c_sda));
|
||||||
|
|
||||||
|
ALT_IOBUF scl_video_iobuf (
|
||||||
|
.i(1'b0),
|
||||||
|
.oe(i2c0_out_clk),
|
||||||
|
.o(i2c0_scl_in_clk),
|
||||||
|
.io(hdmi_i2c_scl));
|
||||||
|
|
||||||
|
ALT_IOBUF sda_video_iobuf (
|
||||||
|
.i(1'b0),
|
||||||
|
.oe(i2c0_out_data),
|
||||||
|
.o(i2c0_sda),
|
||||||
|
.io(hdmi_i2c_sda));
|
||||||
|
|
||||||
|
system_bd i_system_bd (
|
||||||
|
.sys_clk_clk (sys_clk),
|
||||||
|
.sys_hps_h2f_reset_reset_n (sys_resetn),
|
||||||
|
.sys_hps_memory_mem_a (ddr3_a),
|
||||||
|
.sys_hps_memory_mem_ba (ddr3_ba),
|
||||||
|
.sys_hps_memory_mem_ck (ddr3_ck_p),
|
||||||
|
.sys_hps_memory_mem_ck_n (ddr3_ck_n),
|
||||||
|
.sys_hps_memory_mem_cke (ddr3_cke),
|
||||||
|
.sys_hps_memory_mem_cs_n (ddr3_cs_n),
|
||||||
|
.sys_hps_memory_mem_ras_n (ddr3_ras_n),
|
||||||
|
.sys_hps_memory_mem_cas_n (ddr3_cas_n),
|
||||||
|
.sys_hps_memory_mem_we_n (ddr3_we_n),
|
||||||
|
.sys_hps_memory_mem_reset_n (ddr3_reset_n),
|
||||||
|
.sys_hps_memory_mem_dq (ddr3_dq),
|
||||||
|
.sys_hps_memory_mem_dqs (ddr3_dqs_p),
|
||||||
|
.sys_hps_memory_mem_dqs_n (ddr3_dqs_n),
|
||||||
|
.sys_hps_memory_mem_odt (ddr3_odt),
|
||||||
|
.sys_hps_memory_mem_dm (ddr3_dm),
|
||||||
|
.sys_hps_memory_oct_rzqin (ddr3_rzq),
|
||||||
|
.sys_rst_reset_n (sys_resetn),
|
||||||
|
.sys_hps_i2c0_out_data (i2c0_out_data),
|
||||||
|
.sys_hps_i2c0_sda (i2c0_sda),
|
||||||
|
.sys_hps_i2c0_clk_clk (i2c0_out_clk),
|
||||||
|
.sys_hps_i2c0_scl_in_clk (i2c0_scl_in_clk),
|
||||||
|
.sys_hps_hps_io_hps_io_emac1_inst_TX_CLK (eth1_tx_clk),
|
||||||
|
.sys_hps_hps_io_hps_io_emac1_inst_TXD0 (eth1_tx_d[0]),
|
||||||
|
.sys_hps_hps_io_hps_io_emac1_inst_TXD1 (eth1_tx_d[1]),
|
||||||
|
.sys_hps_hps_io_hps_io_emac1_inst_TXD2 (eth1_tx_d[2]),
|
||||||
|
.sys_hps_hps_io_hps_io_emac1_inst_TXD3 (eth1_tx_d[3]),
|
||||||
|
.sys_hps_hps_io_hps_io_emac1_inst_RXD0 (eth1_rx_d[0]),
|
||||||
|
.sys_hps_hps_io_hps_io_emac1_inst_MDIO (eth1_mdio),
|
||||||
|
.sys_hps_hps_io_hps_io_emac1_inst_MDC (eth1_mdc),
|
||||||
|
.sys_hps_hps_io_hps_io_emac1_inst_RX_CTL (eth1_rx_ctl),
|
||||||
|
.sys_hps_hps_io_hps_io_emac1_inst_TX_CTL (eth1_tx_ctl),
|
||||||
|
.sys_hps_hps_io_hps_io_emac1_inst_RX_CLK (eth1_rx_clk),
|
||||||
|
.sys_hps_hps_io_hps_io_emac1_inst_RXD1 (eth1_rx_d[1]),
|
||||||
|
.sys_hps_hps_io_hps_io_emac1_inst_RXD2 (eth1_rx_d[2]),
|
||||||
|
.sys_hps_hps_io_hps_io_emac1_inst_RXD3 (eth1_rx_d[3]),
|
||||||
|
.sys_hps_hps_io_hps_io_sdio_inst_CMD (sdio_cmd),
|
||||||
|
.sys_hps_hps_io_hps_io_sdio_inst_D0 (sdio_d[0]),
|
||||||
|
.sys_hps_hps_io_hps_io_sdio_inst_D1 (sdio_d[1]),
|
||||||
|
.sys_hps_hps_io_hps_io_sdio_inst_CLK (sdio_clk),
|
||||||
|
.sys_hps_hps_io_hps_io_sdio_inst_D2 (sdio_d[2]),
|
||||||
|
.sys_hps_hps_io_hps_io_sdio_inst_D3 (sdio_d[3]),
|
||||||
|
.sys_hps_hps_io_hps_io_usb1_inst_D0 (usb1_d[0]),
|
||||||
|
.sys_hps_hps_io_hps_io_usb1_inst_D1 (usb1_d[1]),
|
||||||
|
.sys_hps_hps_io_hps_io_usb1_inst_D2 (usb1_d[2]),
|
||||||
|
.sys_hps_hps_io_hps_io_usb1_inst_D3 (usb1_d[3]),
|
||||||
|
.sys_hps_hps_io_hps_io_usb1_inst_D4 (usb1_d[4]),
|
||||||
|
.sys_hps_hps_io_hps_io_usb1_inst_D5 (usb1_d[5]),
|
||||||
|
.sys_hps_hps_io_hps_io_usb1_inst_D6 (usb1_d[6]),
|
||||||
|
.sys_hps_hps_io_hps_io_usb1_inst_D7 (usb1_d[7]),
|
||||||
|
.sys_hps_hps_io_hps_io_usb1_inst_CLK (usb1_clk),
|
||||||
|
.sys_hps_hps_io_hps_io_usb1_inst_STP (usb1_stp),
|
||||||
|
.sys_hps_hps_io_hps_io_usb1_inst_DIR (usb1_dir),
|
||||||
|
.sys_hps_hps_io_hps_io_usb1_inst_NXT (usb1_nxt),
|
||||||
|
.sys_hps_hps_io_hps_io_uart0_inst_RX (uart0_rx),
|
||||||
|
.sys_hps_hps_io_hps_io_uart0_inst_TX (uart0_tx),
|
||||||
|
.sys_hps_hps_io_hps_io_spim1_inst_CLK (spim1_clk),
|
||||||
|
.sys_hps_hps_io_hps_io_spim1_inst_MOSI (spim1_mosi),
|
||||||
|
.sys_hps_hps_io_hps_io_spim1_inst_MISO (spim1_miso),
|
||||||
|
.sys_hps_hps_io_hps_io_spim1_inst_SS0 (spim1_ss0),
|
||||||
|
.sys_hps_i2c1_sda (i2c1_sda),
|
||||||
|
.sys_hps_i2c1_out_data (i2c1_sda_oe),
|
||||||
|
.sys_hps_i2c1_clk_clk (i2c1_scl_oe),
|
||||||
|
.sys_hps_i2c1_scl_in_clk (i2c1_scl),
|
||||||
|
.sys_gpio_bd_in_port (gpio_i[31:0]),
|
||||||
|
.sys_gpio_bd_out_port (gpio_o[31:0]),
|
||||||
|
.sys_gpio_in_export (gpio_i[63:32]),
|
||||||
|
.sys_gpio_out_export (gpio_o[63:32]),
|
||||||
|
.cn0540_spi_sdo_sdo (cn0540_spi_mosi),
|
||||||
|
.cn0540_spi_sdi_sdi (cn0540_spi_miso),
|
||||||
|
.cn0540_spi_cs_cs (cn0540_spi_cs),
|
||||||
|
.cn0540_spi_sclk_clk (cn0540_spi_sclk),
|
||||||
|
.cn0540_spi_trigger_trigger (cn0540_drdy),
|
||||||
|
.sys_spi_MISO (1'b0),
|
||||||
|
.sys_spi_MOSI (),
|
||||||
|
.sys_spi_SCLK (),
|
||||||
|
.sys_spi_SS_n (),
|
||||||
|
.ltc2308_spi_MISO (ltc2308_miso),
|
||||||
|
.ltc2308_spi_MOSI (ltc2308_mosi),
|
||||||
|
.ltc2308_spi_SCLK (ltc2308_sclk),
|
||||||
|
.ltc2308_spi_SS_n (),
|
||||||
|
.axi_hdmi_tx_0_hdmi_if_h_clk (hdmi_out_clk),
|
||||||
|
.axi_hdmi_tx_0_hdmi_if_h24_hsync (hdmi_hsync),
|
||||||
|
.axi_hdmi_tx_0_hdmi_if_h24_vsync (hdmi_vsync),
|
||||||
|
.axi_hdmi_tx_0_hdmi_if_h24_data_e (hdmi_data_e),
|
||||||
|
.axi_hdmi_tx_0_hdmi_if_h24_data (hdmi_data));
|
||||||
|
|
||||||
|
endmodule
|
||||||
|
|
||||||
|
// ***************************************************************************
|
||||||
|
// ***************************************************************************
|
||||||
|
|
@ -1,6 +1,7 @@
|
||||||
# de10nano
|
# de10nano
|
||||||
# clocks (V11, Y13, E11 - PL 50MHz)
|
# clocks (V11, Y13, E11 - PL 50MHz)
|
||||||
# clocks (E20, D20 - HPS 25MHz)
|
# clocks (E20, D20 - HPS 25MHz)
|
||||||
|
# clocks (G4 - HPS USB 60MHz)
|
||||||
|
|
||||||
set_location_assignment PIN_V11 -to sys_clk
|
set_location_assignment PIN_V11 -to sys_clk
|
||||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sys_clk
|
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sys_clk
|
||||||
|
|
|
||||||
|
|
@ -37,6 +37,8 @@ set_instance_parameter_value sys_hps {UART1_PinMuxing} {Unused}
|
||||||
set_instance_parameter_value sys_hps {UART1_Mode} {N/A}
|
set_instance_parameter_value sys_hps {UART1_Mode} {N/A}
|
||||||
set_instance_parameter_value sys_hps {I2C0_PinMuxing} {FPGA}
|
set_instance_parameter_value sys_hps {I2C0_PinMuxing} {FPGA}
|
||||||
set_instance_parameter_value sys_hps {I2C0_Mode} {Full}
|
set_instance_parameter_value sys_hps {I2C0_Mode} {Full}
|
||||||
|
set_instance_parameter_value sys_hps {I2C1_PinMuxing} {FPGA}
|
||||||
|
set_instance_parameter_value sys_hps {I2C1_Mode} {Full}
|
||||||
set_instance_parameter_value sys_hps {desired_cfg_clk_mhz} {80.0}
|
set_instance_parameter_value sys_hps {desired_cfg_clk_mhz} {80.0}
|
||||||
set_instance_parameter_value sys_hps {S2FCLK_USER0CLK_Enable} {1}
|
set_instance_parameter_value sys_hps {S2FCLK_USER0CLK_Enable} {1}
|
||||||
set_instance_parameter_value sys_hps {S2FCLK_USER1CLK_Enable} {1}
|
set_instance_parameter_value sys_hps {S2FCLK_USER1CLK_Enable} {1}
|
||||||
|
|
@ -105,6 +107,12 @@ add_interface sys_hps_i2c0_clk clock source
|
||||||
set_interface_property sys_hps_i2c0_clk EXPORT_OF sys_hps.i2c0_clk
|
set_interface_property sys_hps_i2c0_clk EXPORT_OF sys_hps.i2c0_clk
|
||||||
add_interface sys_hps_i2c0_scl_in clock sink
|
add_interface sys_hps_i2c0_scl_in clock sink
|
||||||
set_interface_property sys_hps_i2c0_scl_in EXPORT_OF sys_hps.i2c0_scl_in
|
set_interface_property sys_hps_i2c0_scl_in EXPORT_OF sys_hps.i2c0_scl_in
|
||||||
|
add_interface sys_hps_i2c1 conduit end
|
||||||
|
set_interface_property sys_hps_i2c1 EXPORT_OF sys_hps.i2c1
|
||||||
|
add_interface sys_hps_i2c1_clk clock source
|
||||||
|
set_interface_property sys_hps_i2c1_clk EXPORT_OF sys_hps.i2c1_clk
|
||||||
|
add_interface sys_hps_i2c1_scl_in clock sink
|
||||||
|
set_interface_property sys_hps_i2c1_scl_in EXPORT_OF sys_hps.i2c1_scl_in
|
||||||
|
|
||||||
# cpu/hps handling
|
# cpu/hps handling
|
||||||
|
|
||||||
|
|
@ -204,8 +212,8 @@ set_interface_property sys_spi EXPORT_OF sys_spi.external
|
||||||
|
|
||||||
add_instance ltc2308_spi altera_avalon_spi
|
add_instance ltc2308_spi altera_avalon_spi
|
||||||
set_instance_parameter_value ltc2308_spi {clockPhase} {0}
|
set_instance_parameter_value ltc2308_spi {clockPhase} {0}
|
||||||
set_instance_parameter_value ltc2308_spi {clockPolarity} {1}
|
set_instance_parameter_value ltc2308_spi {clockPolarity} {0}
|
||||||
set_instance_parameter_value ltc2308_spi {dataWidth} {8}
|
set_instance_parameter_value ltc2308_spi {dataWidth} {12}
|
||||||
set_instance_parameter_value ltc2308_spi {masterSPI} {1}
|
set_instance_parameter_value ltc2308_spi {masterSPI} {1}
|
||||||
set_instance_parameter_value ltc2308_spi {numberOfSlaves} {1}
|
set_instance_parameter_value ltc2308_spi {numberOfSlaves} {1}
|
||||||
set_instance_parameter_value ltc2308_spi {targetClockRate} {50000000.0}
|
set_instance_parameter_value ltc2308_spi {targetClockRate} {50000000.0}
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue