diff --git a/.gitattributes b/.gitattributes index 3d7ee6dd4..96ff5a1f3 100644 --- a/.gitattributes +++ b/.gitattributes @@ -11,4 +11,5 @@ *.xdc text *.xml text *.qsys text +*.xise text Makefile text diff --git a/.gitignore b/.gitignore index e88b6e59c..fc464ba0c 100644 --- a/.gitignore +++ b/.gitignore @@ -2,6 +2,43 @@ *.data *.xpr *.log +*.bld +*.chk +*.cmd_log +*.cxt +*.gise +*.gyd +*.jed +*.lso +*.mfd +*.nga +*.ngc +*.ngd +*.ngr +*.pad +*.pnx +*.prj +*.rpt +*.stx +*.syr +*.tim +*.tspec +*.vm6 +*.xst +*.html +*.xrpt +*.err +*_html +*.sld +*.txt +*.qsys +*.csv +xst +netgen +iseconfig +xlnx_auto* +_ngo +_xmsgs component.xml *.jou xgui @@ -22,6 +59,7 @@ db *.qpf *.qws *.sof +system_qsys_script.tcl hc_output hps_isw_handoff hps_sdram_*.csv diff --git a/library/Makefile b/library/Makefile index 2a790386d..c5fcf3222 100644 --- a/library/Makefile +++ b/library/Makefile @@ -11,13 +11,16 @@ all: lib clean: make -C axi_ad6676 clean + make -C axi_ad7616 clean make -C axi_ad9122 clean make -C axi_ad9144 clean make -C axi_ad9152 clean + make -C axi_ad9162 clean make -C axi_ad9234 clean make -C axi_ad9250 clean make -C axi_ad9265 clean make -C axi_ad9361 clean + make -C axi_ad9371 clean make -C axi_ad9434 clean make -C axi_ad9467 clean make -C axi_ad9625 clean @@ -25,16 +28,21 @@ clean: make -C axi_ad9652 clean make -C axi_ad9671 clean make -C axi_ad9680 clean + make -C axi_ad9684 clean make -C axi_ad9739a clean - make -C axi_adcfifo clean + make -C axi_ad9963 clean + make -C axi_adc_decimate clean + make -C axi_adc_trigger clean make -C axi_clkgen clean + make -C axi_dac_interpolate clean make -C axi_dmac clean make -C axi_generic_adc clean make -C axi_gpreg clean make -C axi_hdmi_rx clean make -C axi_hdmi_tx clean make -C axi_i2s_adi clean - make -C axi_jesd_gt clean + make -C axi_intr_monitor clean + make -C axi_logic_analyzer clean make -C axi_mc_controller clean make -C axi_mc_current_monitor clean make -C axi_mc_speed clean @@ -44,12 +52,10 @@ clean: make -C cn0363/cn0363_dma_sequencer clean make -C cn0363/cn0363_phase_data_sync clean make -C cordic_demod clean - make -C interfaces clean make -C spi_engine/axi_spi_engine clean make -C spi_engine/spi_engine_execution clean make -C spi_engine/spi_engine_interconnect clean make -C spi_engine/spi_engine_offload clean - make -C util_adc_pack clean make -C util_adcfifo clean make -C util_axis_fifo clean make -C util_axis_resize clean @@ -57,12 +63,12 @@ clean: make -C util_ccat clean make -C util_clkdiv clean make -C util_cpack clean - make -C util_dac_unpack clean make -C util_dacfifo clean + make -C util_extract clean + make -C util_fir_dec clean + make -C util_fir_int clean make -C util_gmii_to_rgmii clean - make -C util_gtlb clean make -C util_i2c_mixer clean - make -C util_jesd_gt clean make -C util_mfifo clean make -C util_pmod_adc clean make -C util_pmod_fmeter clean @@ -70,7 +76,15 @@ clean: make -C util_sigma_delta_spi clean make -C util_tdd_sync clean make -C util_upack clean + make -C util_var_fifo clean make -C util_wfifo clean + make -C xilinx/axi_adcfifo clean + make -C xilinx/axi_adxcvr clean + make -C xilinx/axi_dacfifo clean + make -C xilinx/axi_xcvrlb clean + make -C xilinx/util_adxcvr clean + + make -C interfaces clean clean-all:clean @@ -78,13 +92,16 @@ clean-all:clean lib: -make -C axi_ad6676 + -make -C axi_ad7616 -make -C axi_ad9122 -make -C axi_ad9144 -make -C axi_ad9152 + -make -C axi_ad9162 -make -C axi_ad9234 -make -C axi_ad9250 -make -C axi_ad9265 -make -C axi_ad9361 + -make -C axi_ad9371 -make -C axi_ad9434 -make -C axi_ad9467 -make -C axi_ad9625 @@ -92,16 +109,21 @@ lib: -make -C axi_ad9652 -make -C axi_ad9671 -make -C axi_ad9680 + -make -C axi_ad9684 -make -C axi_ad9739a - -make -C axi_adcfifo + -make -C axi_ad9963 + -make -C axi_adc_decimate + -make -C axi_adc_trigger -make -C axi_clkgen + -make -C axi_dac_interpolate -make -C axi_dmac -make -C axi_generic_adc -make -C axi_gpreg -make -C axi_hdmi_rx -make -C axi_hdmi_tx -make -C axi_i2s_adi - -make -C axi_jesd_gt + -make -C axi_intr_monitor + -make -C axi_logic_analyzer -make -C axi_mc_controller -make -C axi_mc_current_monitor -make -C axi_mc_speed @@ -111,12 +133,10 @@ lib: -make -C cn0363/cn0363_dma_sequencer -make -C cn0363/cn0363_phase_data_sync -make -C cordic_demod - -make -C interfaces -make -C spi_engine/axi_spi_engine -make -C spi_engine/spi_engine_execution -make -C spi_engine/spi_engine_interconnect -make -C spi_engine/spi_engine_offload - -make -C util_adc_pack -make -C util_adcfifo -make -C util_axis_fifo -make -C util_axis_resize @@ -124,12 +144,12 @@ lib: -make -C util_ccat -make -C util_clkdiv -make -C util_cpack - -make -C util_dac_unpack -make -C util_dacfifo + -make -C util_extract + -make -C util_fir_dec + -make -C util_fir_int -make -C util_gmii_to_rgmii - -make -C util_gtlb -make -C util_i2c_mixer - -make -C util_jesd_gt -make -C util_mfifo -make -C util_pmod_adc -make -C util_pmod_fmeter @@ -137,7 +157,15 @@ lib: -make -C util_sigma_delta_spi -make -C util_tdd_sync -make -C util_upack + -make -C util_var_fifo -make -C util_wfifo + -make -C xilinx/axi_adcfifo + -make -C xilinx/axi_adxcvr + -make -C xilinx/axi_dacfifo + -make -C xilinx/axi_xcvrlb + -make -C xilinx/util_adxcvr + + -make -C interfaces #################################################################################### #################################################################################### diff --git a/library/altera/alt_serdes/alt_serdes_hw.tcl b/library/altera/alt_serdes/alt_serdes_hw.tcl new file mode 100644 index 000000000..546454ab9 --- /dev/null +++ b/library/altera/alt_serdes/alt_serdes_hw.tcl @@ -0,0 +1,245 @@ + +package require -exact qsys 14.0 + +set_module_property NAME alt_serdes +set_module_property DESCRIPTION "Altera SERDES" +set_module_property VERSION 1.0 +set_module_property GROUP "Analog Devices" +set_module_property DISPLAY_NAME alt_serdes +set_module_property COMPOSITION_CALLBACK p_alt_serdes + +# parameters + +add_parameter MODE STRING "CLK" +set_parameter_property MODE DISPLAY_NAME MODE +set_parameter_property MODE TYPE STRING +set_parameter_property MODE UNITS None +set_parameter_property MODE HDL_PARAMETER false +set_parameter_property MODE ALLOWED_RANGES {"CLK" "IN" "OUT"} + +add_parameter DDR_OR_SDR_N INTEGER 1 +set_parameter_property DDR_OR_SDR_N DISPLAY_NAME DDR_OR_SDR_N +set_parameter_property DDR_OR_SDR_N TYPE INTEGER +set_parameter_property DDR_OR_SDR_N UNITS None +set_parameter_property DDR_OR_SDR_N HDL_PARAMETER false +set_parameter_property DDR_OR_SDR_N ALLOWED_RANGES {0 1} + +add_parameter SERDES_FACTOR INTEGER 8 +set_parameter_property SERDES_FACTOR DISPLAY_NAME SERDES_FACTOR +set_parameter_property SERDES_FACTOR TYPE INTEGER +set_parameter_property SERDES_FACTOR UNITS None +set_parameter_property SERDES_FACTOR HDL_PARAMETER false +set_parameter_property SERDES_FACTOR ALLOWED_RANGES {2 4 8} + +add_parameter CLKIN_FREQUENCY FLOAT 500.0 +set_parameter_property CLKIN_FREQUENCY DISPLAY_NAME CLKIN_FREQUENCY +set_parameter_property CLKIN_FREQUENCY TYPE FLOAT +set_parameter_property CLKIN_FREQUENCY UNITS None +set_parameter_property CLKIN_FREQUENCY DISPLAY_UNITS "MHz" +set_parameter_property CLKIN_FREQUENCY HDL_PARAMETER false + +add_parameter DEVICE_FAMILY STRING "Arria 10" +set_parameter_property DEVICE_FAMILY SYSTEM_INFO {DEVICE_FAMILY} +set_parameter_property DEVICE_FAMILY AFFECTS_GENERATION true +set_parameter_property DEVICE_FAMILY HDL_PARAMETER false +set_parameter_property DEVICE_FAMILY ENABLED false +set_parameter_property DEVICE_FAMILY ALLOWED_RANGES {"Arria 10" "Cyclone V"} + +proc p_alt_serdes {} { + + set m_mode [get_parameter_value "MODE"] + set m_ddr_or_sdr_n [get_parameter_value "DDR_OR_SDR_N"] + set m_serdes_factor [get_parameter_value "SERDES_FACTOR"] + set m_clkin_frequency [get_parameter_value "CLKIN_FREQUENCY"] + set m_device_family [get_parameter_value DEVICE_FAMILY] + + set m_hs_data_rate [expr ($m_clkin_frequency * ($m_ddr_or_sdr_n + 1))] + set m_ls_data_rate [expr ($m_hs_data_rate/$m_serdes_factor)] + + set m_ls_phase 22.5 + set m_ld_phase 315.0 + set m_ld_duty_cycle 12.5 + if {$m_serdes_factor == 4} { + set m_ls_phase 45 + set m_ld_phase 270.0 + set m_ld_duty_cycle 25.0 + } + + ## arria 10, cmos data-in and data-out + + if {($m_serdes_factor == 2) && ($m_device_family == "Arria 10")} { + + add_instance alt_serdes_out altera_gpio + set_instance_parameter_value alt_serdes_out {PIN_TYPE_GUI} {Output} + set_instance_parameter_value alt_serdes_out {SIZE} {1} + set_instance_parameter_value alt_serdes_out {gui_diff_buff} {0} + set_instance_parameter_value alt_serdes_out {gui_io_reg_mode} {DDIO} + add_interface clk conduit end + set_interface_property clk EXPORT_OF alt_serdes_out.ck + add_interface din conduit end + set_interface_property din EXPORT_OF alt_serdes_out.din + add_interface pad_out conduit end + set_interface_property pad_out EXPORT_OF alt_serdes_out.pad_out + + return + } + + ## cyclone v, cmos data-in and data-out + + if {($m_serdes_factor == 2) && ($m_device_family == "Cyclone V")} { + + return + } + + ## arria 10, serdes clock, data-in and data-out + + if {($m_mode == "CLK") && ($m_device_family == "Arria 10")} { + + add_instance alt_serdes_pll altera_iopll + set_instance_parameter_value alt_serdes_pll {gui_reference_clock_frequency} $m_clkin_frequency + set_instance_parameter_value alt_serdes_pll {gui_use_locked} {1} + set_instance_parameter_value alt_serdes_pll {gui_operation_mode} {lvds} + set_instance_parameter_value alt_serdes_pll {gui_en_lvds_ports} {Enable LVDS_CLK/LOADEN 0} + set_instance_parameter_value alt_serdes_pll {gui_en_phout_ports} {true} + set_instance_parameter_value alt_serdes_pll {gui_en_reconf} {true} + set_instance_parameter_value alt_serdes_pll {gui_output_clock_frequency0} $m_hs_data_rate + set_instance_parameter_value alt_serdes_pll {gui_ps_units0} {degrees} + set_instance_parameter_value alt_serdes_pll {gui_phase_shift_deg0} {180.0} + set_instance_parameter_value alt_serdes_pll {gui_output_clock_frequency1} $m_ls_data_rate + set_instance_parameter_value alt_serdes_pll {gui_ps_units1} {degrees} + set_instance_parameter_value alt_serdes_pll {gui_phase_shift_deg1} $m_ld_phase + set_instance_parameter_value alt_serdes_pll {gui_duty_cycle1} $m_ld_duty_cycle + set_instance_parameter_value alt_serdes_pll {gui_output_clock_frequency2} $m_ls_data_rate + set_instance_parameter_value alt_serdes_pll {gui_phase_shift_deg2} $m_ls_phase + set_instance_parameter_value alt_serdes_pll {gui_ps_units2} {degrees} + add_interface rst reset sink + set_interface_property rst EXPORT_OF alt_serdes_pll.reset + add_interface ref_clk clock sink + set_interface_property ref_clk EXPORT_OF alt_serdes_pll.refclk + add_interface locked conduit end + set_interface_property locked EXPORT_OF alt_serdes_pll.locked + add_interface hs_phase conduit end + set_interface_property hs_phase EXPORT_OF alt_serdes_pll.phout + add_interface hs_clk conduit end + set_interface_property hs_clk EXPORT_OF alt_serdes_pll.lvds_clk + add_interface loaden conduit end + set_interface_property loaden EXPORT_OF alt_serdes_pll.loaden + add_interface ls_clk clock source + set_interface_property ls_clk EXPORT_OF alt_serdes_pll.outclk2 + + add_instance alt_serdes_pll_reconfig altera_pll_reconfig + add_connection alt_serdes_pll.reconfig_from_pll alt_serdes_pll_reconfig.reconfig_from_pll + add_connection alt_serdes_pll_reconfig.reconfig_to_pll alt_serdes_pll.reconfig_to_pll + add_interface drp_clk clock sink + set_interface_property drp_clk EXPORT_OF alt_serdes_pll_reconfig.mgmt_clk + add_interface drp_rst reset sink + set_interface_property drp_rst EXPORT_OF alt_serdes_pll_reconfig.mgmt_reset + add_interface pll_reconfig avalon slave + set_interface_property pll_reconfig EXPORT_OF alt_serdes_pll_reconfig.mgmt_avalon_slave + + return + } + + if {($m_mode == "IN") && ($m_device_family == "Arria 10")} { + + add_instance alt_serdes_in altera_lvds + set_instance_parameter_value alt_serdes_in {MODE} {RX_DPA-FIFO} + set_instance_parameter_value alt_serdes_in {NUM_CHANNELS} {1} + set_instance_parameter_value alt_serdes_in {DATA_RATE} $m_hs_data_rate + set_instance_parameter_value alt_serdes_in {J_FACTOR} $m_serdes_factor + set_instance_parameter_value alt_serdes_in {USE_EXTERNAL_PLL} {true} + set_instance_parameter_value alt_serdes_in {INCLOCK_FREQUENCY} $m_clkin_frequency + set_instance_parameter_value alt_serdes_in {PLL_USE_RESET} {false} + add_interface data_in conduit end + set_interface_property data_in EXPORT_OF alt_serdes_in.rx_in + add_interface clk conduit end + set_interface_property clk EXPORT_OF alt_serdes_in.ext_fclk + add_interface loaden conduit end + set_interface_property loaden EXPORT_OF alt_serdes_in.ext_loaden + add_interface div_clk conduit end + set_interface_property div_clk EXPORT_OF alt_serdes_in.ext_coreclock + add_interface hs_phase conduit end + set_interface_property hs_phase EXPORT_OF alt_serdes_in.ext_vcoph + add_interface locked conduit end + set_interface_property locked EXPORT_OF alt_serdes_in.ext_pll_locked + add_interface data_s conduit end + set_interface_property data_s EXPORT_OF alt_serdes_in.rx_out + add_interface delay_locked conduit end + set_interface_property delay_locked EXPORT_OF alt_serdes_in.rx_dpa_locked + + return + } + + if {($m_mode == "OUT") && ($m_device_family == "Arria 10")} { + + add_instance alt_serdes_out altera_lvds + set_instance_parameter_value alt_serdes_out {MODE} {TX} + set_instance_parameter_value alt_serdes_out {NUM_CHANNELS} {1} + set_instance_parameter_value alt_serdes_out {DATA_RATE} $m_hs_data_rate + set_instance_parameter_value alt_serdes_out {J_FACTOR} $m_serdes_factor + set_instance_parameter_value alt_serdes_out {TX_EXPORT_CORECLOCK} {false} + set_instance_parameter_value alt_serdes_out {TX_USE_OUTCLOCK} {false} + set_instance_parameter_value alt_serdes_out {USE_EXTERNAL_PLL} {true} + set_instance_parameter_value alt_serdes_out {INCLOCK_FREQUENCY} $m_clkin_frequency + set_instance_parameter_value alt_serdes_out {PLL_USE_RESET} {false} + add_interface data_out conduit end + set_interface_property data_out EXPORT_OF alt_serdes_out.tx_out + add_interface clk conduit end + set_interface_property clk EXPORT_OF alt_serdes_out.ext_fclk + add_interface loaden conduit end + set_interface_property loaden EXPORT_OF alt_serdes_out.ext_loaden + add_interface div_clk conduit end + set_interface_property div_clk EXPORT_OF alt_serdes_out.ext_coreclock + add_interface data_s conduit end + set_interface_property data_s EXPORT_OF alt_serdes_out.tx_in + + return + } + + ## cyclone v, serdes clock, data-in and data-out + + if {($m_mode == "CLK") && ($m_device_family == "Cyclone V")} { + + add_instance alt_serdes_pll altera_pll + set_instance_parameter_value alt_serdes_pll {gui_reference_clock_frequency} $m_clkin_frequency + set_instance_parameter_value alt_serdes_pll {gui_operation_mode} {lvds} + set_instance_parameter_value alt_serdes_pll {gui_use_locked} {1} + set_instance_parameter_value alt_serdes_pll {gui_number_of_clocks} {3} + set_instance_parameter_value alt_serdes_pll {gui_output_clock_frequency0} $m_hs_data_rate + set_instance_parameter_value alt_serdes_pll {gui_ps_units0} {degrees} + set_instance_parameter_value alt_serdes_pll {gui_phase_shift_deg0} {180.0} + set_instance_parameter_value alt_serdes_pll {gui_output_clock_frequency1} $m_ls_data_rate + set_instance_parameter_value alt_serdes_pll {gui_ps_units1} {degrees} + set_instance_parameter_value alt_serdes_pll {gui_phase_shift_deg1} $m_ld_phase + set_instance_parameter_value alt_serdes_pll {gui_duty_cycle1} $m_ld_duty_cycle + set_instance_parameter_value alt_serdes_pll {gui_output_clock_frequency2} $m_ls_data_rate + set_instance_parameter_value alt_serdes_pll {gui_ps_units2} {degrees} + set_instance_parameter_value alt_serdes_pll {gui_phase_shift_deg2} $m_ls_phase + set_instance_parameter_value alt_serdes_pll {gui_en_reconf} {true} + add_interface rst reset sink + set_interface_property rst EXPORT_OF alt_serdes_pll.reset + add_interface ref_clk clock sink + set_interface_property ref_clk EXPORT_OF alt_serdes_pll.refclk + add_interface locked conduit end + set_interface_property locked EXPORT_OF alt_serdes_pll.locked + add_interface hs_clk clock source + set_interface_property hs_clk EXPORT_OF alt_serdes_pll.outclk0 + add_interface loaden clock source + set_interface_property loaden EXPORT_OF alt_serdes_pll.outclk1 + add_interface ls_clk clock source + set_interface_property ls_clk EXPORT_OF alt_serdes_pll.outclk2 + + add_instance alt_serdes_pll_reconfig altera_pll_reconfig + add_connection alt_serdes_pll.reconfig_from_pll alt_serdes_pll_reconfig.reconfig_from_pll + add_connection alt_serdes_pll_reconfig.reconfig_to_pll alt_serdes_pll.reconfig_to_pll + add_interface drp_clk clock sink + set_interface_property drp_clk EXPORT_OF alt_serdes_pll_reconfig.mgmt_clk + add_interface drp_rst reset sink + set_interface_property drp_rst EXPORT_OF alt_serdes_pll_reconfig.mgmt_reset + add_interface pll_reconfig avalon slave + set_interface_property pll_reconfig EXPORT_OF alt_serdes_pll_reconfig.mgmt_avalon_slave + + return + } +} + diff --git a/library/altera/avl_adxcfg/avl_adxcfg.v b/library/altera/avl_adxcfg/avl_adxcfg.v new file mode 100644 index 000000000..698c7f2a6 --- /dev/null +++ b/library/altera/avl_adxcfg/avl_adxcfg.v @@ -0,0 +1,166 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/1ps + +module avl_adxcfg ( + + // reconfig sharing + + input rcfg_clk, + input rcfg_reset_n, + + input rcfg_in_read_0, + input rcfg_in_write_0, + input [ 9:0] rcfg_in_address_0, + input [31:0] rcfg_in_writedata_0, + output [31:0] rcfg_in_readdata_0, + output rcfg_in_waitrequest_0, + + input rcfg_in_read_1, + input rcfg_in_write_1, + input [ 9:0] rcfg_in_address_1, + input [31:0] rcfg_in_writedata_1, + output [31:0] rcfg_in_readdata_1, + output rcfg_in_waitrequest_1, + + output rcfg_out_read_0, + output rcfg_out_write_0, + output [ 9:0] rcfg_out_address_0, + output [31:0] rcfg_out_writedata_0, + input [31:0] rcfg_out_readdata_0, + input rcfg_out_waitrequest_0, + + output rcfg_out_read_1, + output rcfg_out_write_1, + output [ 9:0] rcfg_out_address_1, + output [31:0] rcfg_out_writedata_1, + input [31:0] rcfg_out_readdata_1, + input rcfg_out_waitrequest_1); + + // internal registers + + reg [ 1:0] rcfg_select = 'd0; + reg rcfg_read_int = 'd0; + reg rcfg_write_int = 'd0; + reg [ 9:0] rcfg_address_int = 'd0; + reg [31:0] rcfg_writedata_int = 'd0; + reg [31:0] rcfg_readdata_int = 'd0; + reg rcfg_waitrequest_int_0 = 'd1; + reg rcfg_waitrequest_int_1 = 'd1; + + // internal signals + + wire [31:0] rcfg_readdata_s; + wire rcfg_waitrequest_s; + + // xcvr sharing requires same bus (sw must make sure they are mutually exclusive access). + + assign rcfg_out_read_0 = rcfg_read_int; + assign rcfg_out_write_0 = rcfg_write_int; + assign rcfg_out_address_0 = rcfg_address_int; + assign rcfg_out_writedata_0 = rcfg_writedata_int; + assign rcfg_out_read_1 = rcfg_read_int; + assign rcfg_out_write_1 = rcfg_write_int; + assign rcfg_out_address_1 = rcfg_address_int; + assign rcfg_out_writedata_1 = rcfg_writedata_int; + assign rcfg_in_readdata_0 = rcfg_readdata_int; + assign rcfg_in_readdata_1 = rcfg_readdata_int; + assign rcfg_in_waitrequest_0 = rcfg_waitrequest_int_0; + assign rcfg_in_waitrequest_1 = rcfg_waitrequest_int_1; + + assign rcfg_readdata_s = rcfg_out_readdata_1 & rcfg_out_readdata_0; + assign rcfg_waitrequest_s = rcfg_out_waitrequest_1 & rcfg_out_waitrequest_0; + + always @(negedge rcfg_reset_n or posedge rcfg_clk) begin + if (rcfg_reset_n == 0) begin + rcfg_select <= 2'd0; + rcfg_read_int <= 1'd0; + rcfg_write_int <= 1'd0; + rcfg_address_int <= 10'd0; + rcfg_writedata_int <= 32'd0; + rcfg_readdata_int = 32'd0; + rcfg_waitrequest_int_0 <= 1'b1; + rcfg_waitrequest_int_1 <= 1'b1; + end else begin + if (rcfg_select[1] == 1'b1) begin + if (rcfg_waitrequest_s == 1'b0) begin + rcfg_select <= 2'd0; + rcfg_read_int <= 1'b0; + rcfg_write_int <= 1'b0; + rcfg_address_int <= 10'd0; + rcfg_writedata_int <= 32'd0; + end + rcfg_readdata_int = rcfg_readdata_s; + rcfg_waitrequest_int_0 <= rcfg_waitrequest_s | rcfg_select[0]; + rcfg_waitrequest_int_1 <= rcfg_waitrequest_s | ~rcfg_select[0]; + end else if ((rcfg_in_read_0 == 1'b1) || (rcfg_in_write_0 == 1'b1)) begin + rcfg_select <= 2'b10; + rcfg_read_int <= rcfg_in_read_0; + rcfg_write_int <= rcfg_in_write_0; + rcfg_address_int <= rcfg_in_address_0; + rcfg_writedata_int <= rcfg_in_writedata_0; + rcfg_readdata_int = 32'd0; + rcfg_waitrequest_int_0 <= 1'b1; + rcfg_waitrequest_int_1 <= 1'b1; + end else if ((rcfg_in_read_1 == 1'b1) || (rcfg_in_write_1 == 1'b1)) begin + rcfg_select <= 2'b11; + rcfg_read_int <= rcfg_in_read_1; + rcfg_write_int <= rcfg_in_write_1; + rcfg_address_int <= rcfg_in_address_1; + rcfg_writedata_int <= rcfg_in_writedata_1; + rcfg_readdata_int = 32'd0; + rcfg_waitrequest_int_0 <= 1'b1; + rcfg_waitrequest_int_1 <= 1'b1; + end else begin + rcfg_select <= 2'd0; + rcfg_read_int <= 1'd0; + rcfg_write_int <= 1'd0; + rcfg_address_int <= 10'd0; + rcfg_writedata_int <= 32'd0; + rcfg_readdata_int = 32'd0; + rcfg_waitrequest_int_0 <= 1'b1; + rcfg_waitrequest_int_1 <= 1'b1; + end + end + end + +endmodule + +// *************************************************************************** +// *************************************************************************** + diff --git a/library/altera/avl_adxcfg/avl_adxcfg_hw.tcl b/library/altera/avl_adxcfg/avl_adxcfg_hw.tcl new file mode 100644 index 000000000..6577b976f --- /dev/null +++ b/library/altera/avl_adxcfg/avl_adxcfg_hw.tcl @@ -0,0 +1,55 @@ + +package require -exact qsys 14.0 + +set_module_property NAME avl_adxcfg +set_module_property DESCRIPTION "Avalon ADXCFG Core" +set_module_property VERSION 1.0 +set_module_property GROUP "Analog Devices" +set_module_property DISPLAY_NAME avl_adxcfg + +# files + +add_fileset quartus_synth QUARTUS_SYNTH "" "" +set_fileset_property quartus_synth TOP_LEVEL avl_adxcfg +add_fileset_file avl_adxcfg.v VERILOG PATH avl_adxcfg.v TOP_LEVEL_FILE + +# reconfiguration interfaces + +add_interface rcfg_clk clock sink +add_interface_port rcfg_clk rcfg_clk clk Input 1 + +add_interface rcfg_reset_n reset end +set_interface_property rcfg_reset_n associatedClock rcfg_clk +add_interface_port rcfg_reset_n rcfg_reset_n reset_n Input 1 + +for {set n 0} {$n < 2} {incr n} { + + add_interface rcfg_s${n} avalon slave + add_interface rcfg_m${n} avalon master + + add_interface_port rcfg_s${n} rcfg_in_read_${n} read Input 1 + add_interface_port rcfg_s${n} rcfg_in_write_${n} write Input 1 + add_interface_port rcfg_s${n} rcfg_in_address_${n} address Input 10 + add_interface_port rcfg_s${n} rcfg_in_writedata_${n} writedata Input 32 + add_interface_port rcfg_s${n} rcfg_in_readdata_${n} readdata Output 32 + add_interface_port rcfg_s${n} rcfg_in_waitrequest_${n} waitrequest Output 1 + add_interface_port rcfg_m${n} rcfg_out_read_${n} read Output 1 + add_interface_port rcfg_m${n} rcfg_out_write_${n} write Output 1 + add_interface_port rcfg_m${n} rcfg_out_address_${n} address Output 10 + add_interface_port rcfg_m${n} rcfg_out_writedata_${n} writedata Output 32 + add_interface_port rcfg_m${n} rcfg_out_readdata_${n} readdata Input 32 + add_interface_port rcfg_m${n} rcfg_out_waitrequest_${n} waitrequest Input 1 + + set_interface_property rcfg_s${n} associatedClock rcfg_clk + set_interface_property rcfg_s${n} associatedReset rcfg_reset_n + set_interface_property rcfg_s${n} addressUnits WORDS + set_interface_property rcfg_s${n} burstCountUnits WORDS + set_interface_property rcfg_s${n} explicitAddressSpan 0 + set_interface_property rcfg_m${n} associatedClock rcfg_clk + set_interface_property rcfg_m${n} associatedReset rcfg_reset_n + set_interface_property rcfg_m${n} addressUnits WORDS + set_interface_property rcfg_m${n} burstCountUnits WORDS +} + + + diff --git a/library/altera/avl_adxcvr/avl_adxcvr_hw.tcl b/library/altera/avl_adxcvr/avl_adxcvr_hw.tcl new file mode 100755 index 000000000..f0efb0df7 --- /dev/null +++ b/library/altera/avl_adxcvr/avl_adxcvr_hw.tcl @@ -0,0 +1,436 @@ + +package require -exact qsys 14.0 + +set_module_property NAME avl_adxcvr +set_module_property DESCRIPTION "Avalon ADXCVR Core" +set_module_property VERSION 1.0 +set_module_property GROUP "Analog Devices" +set_module_property DISPLAY_NAME avl_adxcvr +set_module_property COMPOSITION_CALLBACK p_avl_adxcvr + +# parameters + +add_parameter DEVICE_FAMILY STRING +set_parameter_property DEVICE_FAMILY SYSTEM_INFO {DEVICE_FAMILY} +set_parameter_property DEVICE_FAMILY AFFECTS_GENERATION true +set_parameter_property DEVICE_FAMILY HDL_PARAMETER false +set_parameter_property DEVICE_FAMILY ENABLED false + +add_parameter TX_OR_RX_N INTEGER 0 +set_parameter_property TX_OR_RX_N DISPLAY_NAME TX_OR_RX_N +set_parameter_property TX_OR_RX_N TYPE INTEGER +set_parameter_property TX_OR_RX_N UNITS None +set_parameter_property TX_OR_RX_N HDL_PARAMETER false + +add_parameter ID INTEGER 0 +set_parameter_property ID DISPLAY_NAME ID +set_parameter_property ID TYPE INTEGER +set_parameter_property ID UNITS None +set_parameter_property ID HDL_PARAMETER false + +add_parameter PCS_CONFIG STRING "JESD_PCS_CFG2" +set_parameter_property PCS_CONFIG DISPLAY_NAME PCS_CONFIG +set_parameter_property PCS_CONFIG TYPE STRING +set_parameter_property PCS_CONFIG UNITS None +set_parameter_property PCS_CONFIG HDL_PARAMETER false + +add_parameter LANE_RATE FLOAT 10000 +set_parameter_property LANE_RATE DISPLAY_NAME LANE_RATE +set_parameter_property LANE_RATE TYPE FLOAT +set_parameter_property LANE_RATE UNITS None +set_parameter_property LANE_RATE DISPLAY_UNITS "Mbps" +set_parameter_property LANE_RATE HDL_PARAMETER false + +add_parameter SYSCLK_FREQUENCY FLOAT 100.0 +set_parameter_property SYSCLK_FREQUENCY DISPLAY_NAME SYSCLK_FREQUENCY +set_parameter_property SYSCLK_FREQUENCY TYPE FLOAT +set_parameter_property SYSCLK_FREQUENCY UNITS Megahertz +set_parameter_property SYSCLK_FREQUENCY HDL_PARAMETER false + +add_parameter PLLCLK_FREQUENCY FLOAT 5000.0 +set_parameter_property PLLCLK_FREQUENCY DISPLAY_NAME PLLCLK_FREQUENCY +set_parameter_property PLLCLK_FREQUENCY TYPE FLOAT +set_parameter_property PLLCLK_FREQUENCY UNITS Megahertz +set_parameter_property PLLCLK_FREQUENCY HDL_PARAMETER false + +add_parameter REFCLK_FREQUENCY FLOAT 500.0 +set_parameter_property REFCLK_FREQUENCY DISPLAY_NAME REFCLK_FREQUENCY +set_parameter_property REFCLK_FREQUENCY TYPE FLOAT +set_parameter_property REFCLK_FREQUENCY UNITS Megahertz +set_parameter_property REFCLK_FREQUENCY HDL_PARAMETER false + +add_parameter CORECLK_FREQUENCY FLOAT 250.0 +set_parameter_property CORECLK_FREQUENCY DISPLAY_NAME CORECLK_FREQUENCY +set_parameter_property CORECLK_FREQUENCY TYPE FLOAT +set_parameter_property CORECLK_FREQUENCY UNITS Megahertz +set_parameter_property CORECLK_FREQUENCY HDL_PARAMETER false + +add_parameter NUM_OF_LANES INTEGER 4 +set_parameter_property NUM_OF_LANES DISPLAY_NAME NUM_OF_LANES +set_parameter_property NUM_OF_LANES TYPE INTEGER +set_parameter_property NUM_OF_LANES UNITS None +set_parameter_property NUM_OF_LANES HDL_PARAMETER false + +add_parameter NUM_OF_CONVS INTEGER 2 +set_parameter_property NUM_OF_CONVS DISPLAY_NAME NUM_OF_CONVS +set_parameter_property NUM_OF_CONVS TYPE INTEGER +set_parameter_property NUM_OF_CONVS UNITS None +set_parameter_property NUM_OF_CONVS HDL_PARAMETER false + +add_parameter FRM_BCNT INTEGER 1 +set_parameter_property FRM_BCNT DISPLAY_NAME FRM_BCNT +set_parameter_property FRM_BCNT TYPE INTEGER +set_parameter_property FRM_BCNT UNITS None +set_parameter_property FRM_BCNT HDL_PARAMETER false + +add_parameter FRM_SCNT INTEGER 1 +set_parameter_property FRM_SCNT DISPLAY_NAME FRM_SCNT +set_parameter_property FRM_SCNT TYPE INTEGER +set_parameter_property FRM_SCNT UNITS None +set_parameter_property FRM_SCNT HDL_PARAMETER false + +add_parameter MF_FCNT INTEGER 32 +set_parameter_property MF_FCNT DISPLAY_NAME MF_FCNT +set_parameter_property MF_FCNT TYPE INTEGER +set_parameter_property MF_FCNT UNITS None +set_parameter_property MF_FCNT HDL_PARAMETER false + +add_parameter HD INTEGER 1 +set_parameter_property HD DISPLAY_NAME HD +set_parameter_property HD TYPE INTEGER +set_parameter_property HD UNITS None +set_parameter_property HD HDL_PARAMETER false + +proc p_avl_adxcvr {} { + + set m_id [get_parameter_value "ID"] + set m_lane_rate [get_parameter_value "LANE_RATE"] + set m_pcs_config [get_parameter_value "PCS_CONFIG"] + set m_tx_or_rx_n [get_parameter_value "TX_OR_RX_N"] + set m_num_of_lanes [get_parameter_value "NUM_OF_LANES"] + set m_device_family [get_parameter_value "DEVICE_FAMILY"] + set m_sysclk_frequency [get_parameter_value "SYSCLK_FREQUENCY"] + set m_pllclk_frequency [get_parameter_value "PLLCLK_FREQUENCY"] + set m_refclk_frequency [get_parameter_value "REFCLK_FREQUENCY"] + set m_coreclk_frequency [get_parameter_value "CORECLK_FREQUENCY"] + set m_num_of_convs [get_parameter_value "NUM_OF_CONVS"] + set m_frm_bcnt [get_parameter_value "FRM_BCNT"] + set m_frm_scnt [get_parameter_value "FRM_SCNT"] + set m_mf_fcnt [get_parameter_value "MF_FCNT"] + set m_hd [get_parameter_value "HD"] + + add_instance alt_sys_clk clock_source 16.0 + set_instance_parameter_value alt_sys_clk {clockFrequency} [expr $m_sysclk_frequency*1000000] + add_interface sys_clk clock sink + set_interface_property sys_clk EXPORT_OF alt_sys_clk.clk_in + add_interface sys_resetn reset sink + set_interface_property sys_resetn EXPORT_OF alt_sys_clk.clk_in_reset + + add_instance alt_ref_clk altera_clock_bridge 16.0 + set_instance_parameter_value alt_ref_clk {EXPLICIT_CLOCK_RATE} [expr $m_refclk_frequency*1000000] + add_interface ref_clk clock sink + set_interface_property ref_clk EXPORT_OF alt_ref_clk.in_clk + + if {$m_device_family eq "Arria V"} { + + add_instance alt_core_pll altera_pll 16.0 + set_instance_parameter_value alt_core_pll {gui_en_reconf} {1} + set_instance_parameter_value alt_core_pll {gui_reference_clock_frequency} $m_refclk_frequency + set_instance_parameter_value alt_core_pll {gui_use_locked} {1} + set_instance_parameter_value alt_core_pll {gui_output_clock_frequency0} $m_coreclk_frequency + add_connection alt_ref_clk.out_clk alt_core_pll.refclk + add_connection alt_sys_clk.clk_reset alt_core_pll.reset + add_interface core_pll_locked conduit end + set_interface_property core_pll_locked EXPORT_OF alt_core_pll.locked + + } else { + + add_instance alt_core_pll altera_iopll 16.0 + set_instance_parameter_value alt_core_pll {gui_en_reconf} {1} + set_instance_parameter_value alt_core_pll {gui_reference_clock_frequency} $m_refclk_frequency + set_instance_parameter_value alt_core_pll {gui_use_locked} {1} + set_instance_parameter_value alt_core_pll {gui_output_clock_frequency0} $m_coreclk_frequency + add_connection alt_ref_clk.out_clk alt_core_pll.refclk + add_connection alt_sys_clk.clk_reset alt_core_pll.reset + add_interface core_pll_locked conduit end + set_interface_property core_pll_locked EXPORT_OF alt_core_pll.locked + } + + add_instance alt_core_pll_reconfig altera_pll_reconfig 16.0 + add_connection alt_sys_clk.clk_reset alt_core_pll_reconfig.mgmt_reset + add_connection alt_sys_clk.clk alt_core_pll_reconfig.mgmt_clk + add_connection alt_core_pll_reconfig.reconfig_to_pll alt_core_pll.reconfig_to_pll + add_connection alt_core_pll.reconfig_from_pll alt_core_pll_reconfig.reconfig_from_pll + add_interface core_pll_reconfig avalon slave + set_interface_property core_pll_reconfig EXPORT_OF alt_core_pll_reconfig.mgmt_avalon_slave + + add_instance alt_core_clk altera_clock_bridge 16.0 + set_instance_parameter_value alt_core_clk {EXPLICIT_CLOCK_RATE} $m_coreclk_frequency + add_connection alt_core_pll.outclk0 alt_core_clk.in_clk + add_interface core_clk clock source + set_interface_property core_clk EXPORT_OF alt_core_clk.out_clk + + if {$m_tx_or_rx_n == 1} { + + add_instance alt_rst_cntrol altera_xcvr_reset_control 16.0 + set_instance_parameter_value alt_rst_cntrol {CHANNELS} $m_num_of_lanes + set_instance_parameter_value alt_rst_cntrol {SYS_CLK_IN_MHZ} $m_sysclk_frequency + set_instance_parameter_value alt_rst_cntrol {TX_PLL_ENABLE} {1} + set_instance_parameter_value alt_rst_cntrol {T_PLL_POWERDOWN} {1000} + set_instance_parameter_value alt_rst_cntrol {TX_ENABLE} {1} + set_instance_parameter_value alt_rst_cntrol {T_TX_ANALOGRESET} {70000} + set_instance_parameter_value alt_rst_cntrol {T_TX_DIGITALRESET} {70000} + set_instance_parameter_value alt_rst_cntrol {gui_pll_cal_busy} {1} + set_instance_parameter_value alt_rst_cntrol {RX_ENABLE} {0} + add_connection alt_sys_clk.clk alt_rst_cntrol.clock + add_interface rst reset sink + set_interface_property rst EXPORT_OF alt_rst_cntrol.reset + add_interface ready conduit end + set_interface_property ready EXPORT_OF alt_rst_cntrol.tx_ready + + add_instance alt_lane_pll altera_xcvr_atx_pll_a10 16.0 + set_instance_parameter_value alt_lane_pll {enable_pll_reconfig} {1} + set_instance_parameter_value alt_lane_pll {rcfg_separate_avmm_busy} {1} + set_instance_parameter_value alt_lane_pll {set_capability_reg_enable} {1} + set_instance_parameter_value alt_lane_pll {set_user_identifier} $m_id + set_instance_parameter_value alt_lane_pll {set_csr_soft_logic_enable} {1} + set_instance_parameter_value alt_lane_pll {set_output_clock_frequency} $m_pllclk_frequency + set_instance_parameter_value alt_lane_pll {set_auto_reference_clock_frequency} $m_refclk_frequency + add_connection alt_rst_cntrol.pll_powerdown alt_lane_pll.pll_powerdown + add_connection alt_lane_pll.pll_locked alt_rst_cntrol.pll_locked + add_connection alt_lane_pll.pll_cal_busy alt_rst_cntrol.pll_cal_busy + add_connection alt_ref_clk.out_clk alt_lane_pll.pll_refclk0 + add_connection alt_sys_clk.clk alt_lane_pll.reconfig_clk0 + add_connection alt_sys_clk.clk_reset alt_lane_pll.reconfig_reset0 + add_interface lane_pll_reconfig avalon slave + set_interface_property lane_pll_reconfig EXPORT_OF alt_lane_pll.reconfig_avmm0 + + add_instance alt_ip altera_jesd204 16.0 + set_instance_parameter_value alt_ip {wrapper_opt} {base} + set_instance_parameter_value alt_ip {DATA_PATH} {TX} + set_instance_parameter_value alt_ip {lane_rate} $m_lane_rate + set_instance_parameter_value alt_ip {L} $m_num_of_lanes + set_instance_parameter_value alt_ip {M} $m_num_of_convs + set_instance_parameter_value alt_ip {GUI_EN_CFG_F} {1} + set_instance_parameter_value alt_ip {GUI_CFG_F} $m_frm_bcnt + set_instance_parameter_value alt_ip {N} {16} + set_instance_parameter_value alt_ip {N_PRIME} {16} + set_instance_parameter_value alt_ip {S} $m_frm_scnt + set_instance_parameter_value alt_ip {K} $m_mf_fcnt + set_instance_parameter_value alt_ip {SCR} {1} + set_instance_parameter_value alt_ip {HD} $m_hd + add_connection alt_core_pll.outclk0 alt_ip.txlink_clk + add_connection alt_sys_clk.clk_reset alt_ip.txlink_rst_n + add_interface ip_data avalon_streaming sink + set_interface_property ip_data EXPORT_OF alt_ip.jesd204_tx_link + add_connection alt_sys_clk.clk alt_ip.jesd204_tx_avs_clk + add_connection alt_sys_clk.clk_reset alt_ip.jesd204_tx_avs_rst_n + add_interface ip_reconfig avalon slave + set_interface_property ip_reconfig EXPORT_OF alt_ip.jesd204_tx_avs + add_interface sysref conduit end + set_interface_property sysref EXPORT_OF alt_ip.sysref + add_interface sync conduit end + set_interface_property sync EXPORT_OF alt_ip.sync_n + add_connection alt_ip.dev_sync_n alt_ip.mdev_sync_n + + add_instance alt_xphy avl_adxphy 1.0 + set_instance_parameter_value alt_xphy {TX_OR_RX_N} {1} + set_instance_parameter_value alt_xphy {NUM_OF_LANES} $m_num_of_lanes + add_connection alt_rst_cntrol.tx_analogreset alt_xphy.tx_core_analogreset + add_connection alt_rst_cntrol.tx_digitalreset alt_xphy.tx_core_digitalreset + add_connection alt_xphy.tx_core_cal_busy alt_rst_cntrol.tx_cal_busy + add_connection alt_xphy.tx_ip_cal_busy alt_ip.tx_cal_busy + add_connection alt_xphy.tx_ip_pcfifo_full alt_ip.phy_csr_tx_pcfifo_full + add_connection alt_xphy.tx_ip_pcfifo_empty alt_ip.phy_csr_tx_pcfifo_empty + add_connection alt_ip.jesd204_tx_pcs_data alt_xphy.tx_ip_pcs_data + add_connection alt_ip.jesd204_tx_pcs_kchar_data alt_xphy.tx_ip_pcs_kchar_data + add_connection alt_ip.phy_tx_elecidle alt_xphy.tx_ip_elecidle + add_connection alt_ip.csr_lane_polarity alt_xphy.tx_ip_csr_lane_polarity + add_connection alt_ip.csr_lane_powerdown alt_xphy.tx_ip_csr_lane_powerdown + add_connection alt_ip.csr_bit_reversal alt_xphy.tx_ip_csr_bit_reversal + add_connection alt_ip.csr_byte_reversal alt_xphy.tx_ip_csr_byte_reversal + + for {set n 0} {$n < $m_num_of_lanes} {incr n} { + + add_interface tx_ip_s_${n} conduit end + set_interface_property tx_ip_s_${n} EXPORT_OF alt_xphy.tx_ip_s_${n} + add_interface tx_ip_d_${n} conduit end + set_interface_property tx_ip_d_${n} EXPORT_OF alt_xphy.tx_ip_d_${n} + add_interface tx_phy_s_${n} conduit end + set_interface_property tx_phy_s_${n} EXPORT_OF alt_xphy.tx_phy_s_${n} + add_interface tx_phy_d_${n} conduit end + set_interface_property tx_phy_d_${n} EXPORT_OF alt_xphy.tx_phy_d_${n} + + add_instance alt_phy_${n} altera_jesd204 16.0 + set_instance_parameter_value alt_phy_${n} {wrapper_opt} {phy} + set_instance_parameter_value alt_phy_${n} {DATA_PATH} {TX} + set_instance_parameter_value alt_phy_${n} {lane_rate} $m_lane_rate + set_instance_parameter_value alt_phy_${n} {PCS_CONFIG} $m_pcs_config + set_instance_parameter_value alt_phy_${n} {bonded_mode} {non_bonded} + set_instance_parameter_value alt_phy_${n} {pll_reconfig_enable} {1} + set_instance_parameter_value alt_phy_${n} {set_capability_reg_enable} {1} + set_instance_parameter_value alt_phy_${n} {set_user_identifier} $m_id + set_instance_parameter_value alt_phy_${n} {set_csr_soft_logic_enable} {1} + set_instance_parameter_value alt_phy_${n} {L} 1 + add_connection alt_core_pll.outclk0 alt_phy_${n}.txlink_clk + add_connection alt_sys_clk.clk_reset alt_phy_${n}.txlink_rst_n + add_interface tx_data_${n} conduit end + set_interface_property tx_data_${n} EXPORT_OF alt_phy_${n}.tx_serial_data + add_connection alt_xphy.tx_phy${n}_analogreset alt_phy_${n}.tx_analogreset + add_connection alt_xphy.tx_phy${n}_digitalreset alt_phy_${n}.tx_digitalreset + add_connection alt_lane_pll.tx_serial_clk alt_phy_${n}.tx_serial_clk0 + + if {$m_device_family eq "Arria V"} { + + add_instance alt_phy_reconfig_${n} alt_xcvr_reconfig 16.0 + set_instance_parameter_value alt_phy_reconfig_${n} {number_of_reconfig_interfaces} {1} + add_connection alt_sys_clk.clk alt_phy_reconfig_${n}.mgmt_clk_clk + add_connection alt_sys_clk.clk_reset alt_phy_reconfig_${n}.mgmt_rst_reset + add_interface phy_reconfig_${n} avalon slave + set_interface_property phy_reconfig_${n} EXPORT_OF alt_phy_reconfig_${n}.reconfig_mgmt + add_connection alt_phy_reconfig_${n}.reconfig_to_xcvr alt_phy_${n}.reconfig_to_xcvr + add_connection alt_phy_${n}.reconfig_from_xcvr alt_phy_reconfig_${n}.reconfig_from_xcvr + + } else { + + add_connection alt_sys_clk.clk alt_phy_${n}.reconfig_clk + add_connection alt_sys_clk.clk_reset alt_phy_${n}.reconfig_reset + add_interface phy_reconfig_${n} avalon slave + set_interface_property phy_reconfig_${n} EXPORT_OF alt_phy_${n}.reconfig_avmm + } + + add_connection alt_phy_${n}.tx_cal_busy alt_xphy.tx_phy${n}_cal_busy + add_connection alt_phy_${n}.phy_csr_tx_pcfifo_full alt_xphy.tx_phy${n}_pcfifo_full + add_connection alt_phy_${n}.phy_csr_tx_pcfifo_empty alt_xphy.tx_phy${n}_pcfifo_empty + add_connection alt_xphy.tx_phy${n}_pcs_data alt_phy_${n}.jesd204_tx_pcs_data + add_connection alt_xphy.tx_phy${n}_pcs_kchar_data alt_phy_${n}.jesd204_tx_pcs_kchar_data + add_connection alt_xphy.tx_phy${n}_elecidle alt_phy_${n}.phy_tx_elecidle + add_connection alt_xphy.tx_phy${n}_csr_lane_polarity alt_phy_${n}.csr_lane_polarity + add_connection alt_xphy.tx_phy${n}_csr_lane_powerdown alt_phy_${n}.csr_lane_powerdown + add_connection alt_xphy.tx_phy${n}_csr_bit_reversal alt_phy_${n}.csr_bit_reversal + add_connection alt_xphy.tx_phy${n}_csr_byte_reversal alt_phy_${n}.csr_byte_reversal + } + } + + if {$m_tx_or_rx_n == 0} { + + add_instance alt_rst_cntrol altera_xcvr_reset_control 16.0 + set_instance_parameter_value alt_rst_cntrol {CHANNELS} $m_num_of_lanes + set_instance_parameter_value alt_rst_cntrol {SYS_CLK_IN_MHZ} $m_sysclk_frequency + set_instance_parameter_value alt_rst_cntrol {TX_PLL_ENABLE} {0} + set_instance_parameter_value alt_rst_cntrol {TX_ENABLE} {0} + set_instance_parameter_value alt_rst_cntrol {RX_ENABLE} {1} + set_instance_parameter_value alt_rst_cntrol {T_RX_ANALOGRESET} {70000} + set_instance_parameter_value alt_rst_cntrol {T_RX_DIGITALRESET} {4000} + add_connection alt_sys_clk.clk alt_rst_cntrol.clock + add_interface rst reset sink + set_interface_property rst EXPORT_OF alt_rst_cntrol.reset + add_interface ready conduit end + set_interface_property ready EXPORT_OF alt_rst_cntrol.rx_ready + + add_instance alt_ip altera_jesd204 16.0 + set_instance_parameter_value alt_ip {wrapper_opt} {base} + set_instance_parameter_value alt_ip {DATA_PATH} {RX} + set_instance_parameter_value alt_ip {lane_rate} $m_lane_rate + set_instance_parameter_value alt_ip {L} $m_num_of_lanes + set_instance_parameter_value alt_ip {M} $m_num_of_convs + set_instance_parameter_value alt_ip {GUI_EN_CFG_F} {1} + set_instance_parameter_value alt_ip {GUI_CFG_F} $m_frm_bcnt + set_instance_parameter_value alt_ip {N} {16} + set_instance_parameter_value alt_ip {N_PRIME} {16} + set_instance_parameter_value alt_ip {S} $m_frm_scnt + set_instance_parameter_value alt_ip {K} $m_mf_fcnt + set_instance_parameter_value alt_ip {SCR} {1} + set_instance_parameter_value alt_ip {HD} $m_hd + add_connection alt_core_pll.outclk0 alt_ip.rxlink_clk + add_connection alt_sys_clk.clk_reset alt_ip.rxlink_rst_n + add_interface ip_sof conduit end + set_interface_property ip_sof EXPORT_OF alt_ip.sof + add_interface ip_data avalon_streaming source + set_interface_property ip_data EXPORT_OF alt_ip.jesd204_rx_link + add_connection alt_sys_clk.clk alt_ip.jesd204_rx_avs_clk + add_connection alt_sys_clk.clk_reset alt_ip.jesd204_rx_avs_rst_n + add_interface ip_reconfig avalon slave + set_interface_property ip_reconfig EXPORT_OF alt_ip.jesd204_rx_avs + add_interface sysref conduit end + set_interface_property sysref EXPORT_OF alt_ip.sysref + add_interface sync conduit end + set_interface_property sync EXPORT_OF alt_ip.dev_sync_n + add_connection alt_ip.dev_lane_aligned alt_ip.alldev_lane_aligned + + add_instance alt_xphy avl_adxphy 1.0 + set_instance_parameter_value alt_xphy {TX_OR_RX_N} {0} + set_instance_parameter_value alt_xphy {NUM_OF_LANES} $m_num_of_lanes + add_connection alt_rst_cntrol.rx_analogreset alt_xphy.rx_core_analogreset + add_connection alt_rst_cntrol.rx_digitalreset alt_xphy.rx_core_digitalreset + add_connection alt_xphy.rx_core_is_lockedtodata alt_rst_cntrol.rx_is_lockedtodata + add_connection alt_xphy.rx_core_cal_busy alt_rst_cntrol.rx_cal_busy + add_connection alt_xphy.rx_ip_is_lockedtodata alt_ip.rx_islockedtodata + add_connection alt_xphy.rx_ip_cal_busy alt_ip.rx_cal_busy + add_connection alt_xphy.rx_ip_pcs_data_valid alt_ip.jesd204_rx_pcs_data_valid + add_connection alt_xphy.rx_ip_pcs_data alt_ip.jesd204_rx_pcs_data + add_connection alt_xphy.rx_ip_pcs_disperr alt_ip.jesd204_rx_pcs_disperr + add_connection alt_xphy.rx_ip_pcs_errdetect alt_ip.jesd204_rx_pcs_errdetect + add_connection alt_xphy.rx_ip_pcs_kchar_data alt_ip.jesd204_rx_pcs_kchar_data + add_connection alt_xphy.rx_ip_pcfifo_full alt_ip.phy_csr_rx_pcfifo_full + add_connection alt_xphy.rx_ip_pcfifo_empty alt_ip.phy_csr_rx_pcfifo_empty + add_connection alt_xphy.rx_ip_patternalign_en alt_ip.patternalign_en + add_connection alt_xphy.rx_ip_csr_lane_polarity alt_ip.csr_lane_polarity + add_connection alt_xphy.rx_ip_csr_lane_powerdown alt_ip.csr_lane_powerdown + add_connection alt_xphy.rx_ip_csr_bit_reversal alt_ip.csr_bit_reversal + add_connection alt_xphy.rx_ip_csr_byte_reversal alt_ip.csr_byte_reversal + + for {set n 0} {$n < $m_num_of_lanes} {incr n} { + + add_instance alt_phy_${n} altera_jesd204 16.0 + set_instance_parameter_value alt_phy_${n} {wrapper_opt} {phy} + set_instance_parameter_value alt_phy_${n} {DATA_PATH} {RX} + set_instance_parameter_value alt_phy_${n} {lane_rate} $m_lane_rate + set_instance_parameter_value alt_phy_${n} {PCS_CONFIG} $m_pcs_config + set_instance_parameter_value alt_phy_${n} {REFCLK_FREQ} $m_refclk_frequency + set_instance_parameter_value alt_phy_${n} {pll_reconfig_enable} {1} + set_instance_parameter_value alt_phy_${n} {set_capability_reg_enable} {1} + set_instance_parameter_value alt_phy_${n} {set_user_identifier} $m_id + set_instance_parameter_value alt_phy_${n} {set_csr_soft_logic_enable} {1} + set_instance_parameter_value alt_phy_${n} {L} 1 + + if {$m_device_family eq "Arria V"} { + + add_interface phy_reconfig_to_xcvr_${n} conduit end + set_interface_property phy_reconfig_to_xcvr_${n} EXPORT_OF alt_phy_${n}.reconfig_to_xcvr + add_interface phy_reconfig_from_xcvr_${n} conduit end + set_interface_property phy_reconfig_from_xcvr_${n} EXPORT_OF alt_phy_${n}.reconfig_from_xcvr + + } else { + + add_connection alt_sys_clk.clk alt_phy_${n}.reconfig_clk + add_connection alt_sys_clk.clk_reset alt_phy_${n}.reconfig_reset + add_interface phy_reconfig_${n} avalon slave + set_interface_property phy_reconfig_${n} EXPORT_OF alt_phy_${n}.reconfig_avmm + } + + add_connection alt_ref_clk.out_clk alt_phy_${n}.pll_ref_clk + add_connection alt_core_pll.outclk0 alt_phy_${n}.rxlink_clk + add_connection alt_sys_clk.clk_reset alt_phy_${n}.rxlink_rst_n + add_interface rx_data_${n} conduit end + set_interface_property rx_data_${n} EXPORT_OF alt_phy_${n}.rx_serial_data + add_connection alt_xphy.rx_phy${n}_analogreset alt_phy_${n}.rx_analogreset + add_connection alt_xphy.rx_phy${n}_digitalreset alt_phy_${n}.rx_digitalreset + add_connection alt_phy_${n}.rx_islockedtodata alt_xphy.rx_phy${n}_is_lockedtodata + add_connection alt_phy_${n}.rx_cal_busy alt_xphy.rx_phy${n}_cal_busy + add_connection alt_phy_${n}.jesd204_rx_pcs_data_valid alt_xphy.rx_phy${n}_pcs_data_valid + add_connection alt_phy_${n}.jesd204_rx_pcs_data alt_xphy.rx_phy${n}_pcs_data + add_connection alt_phy_${n}.jesd204_rx_pcs_disperr alt_xphy.rx_phy${n}_pcs_disperr + add_connection alt_phy_${n}.jesd204_rx_pcs_errdetect alt_xphy.rx_phy${n}_pcs_errdetect + add_connection alt_phy_${n}.jesd204_rx_pcs_kchar_data alt_xphy.rx_phy${n}_pcs_kchar_data + add_connection alt_phy_${n}.phy_csr_rx_pcfifo_full alt_xphy.rx_phy${n}_pcfifo_full + add_connection alt_phy_${n}.phy_csr_rx_pcfifo_empty alt_xphy.rx_phy${n}_pcfifo_empty + add_connection alt_xphy.rx_phy${n}_patternalign_en alt_phy_${n}.patternalign_en + add_connection alt_xphy.rx_phy${n}_csr_lane_polarity alt_phy_${n}.csr_lane_polarity + add_connection alt_xphy.rx_phy${n}_csr_lane_powerdown alt_phy_${n}.csr_lane_powerdown + add_connection alt_xphy.rx_phy${n}_csr_bit_reversal alt_phy_${n}.csr_bit_reversal + add_connection alt_xphy.rx_phy${n}_csr_byte_reversal alt_phy_${n}.csr_byte_reversal + } + } +} + diff --git a/library/altera/avl_adxphy/avl_adxphy.v b/library/altera/avl_adxphy/avl_adxphy.v new file mode 100644 index 000000000..e8590ae81 --- /dev/null +++ b/library/altera/avl_adxphy/avl_adxphy.v @@ -0,0 +1,1032 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// AUTO GENERATED BY avl_adxphy.pl, DO NOT MODIFY! + +`timescale 1ns/1ps + +module avl_adxphy #( + + // parameters + + parameter integer NUM_OF_LANES = 4) ( + + // rx-ip interface + + output [((NUM_OF_LANES* 1)-1):0] rx_ip_locked, + output [((NUM_OF_LANES* 1)-1):0] rx_ip_cal_busy, + output [((NUM_OF_LANES* 1)-1):0] rx_ip_valid, + output [((NUM_OF_LANES*32)-1):0] rx_ip_data, + output [((NUM_OF_LANES* 4)-1):0] rx_ip_disperr, + output [((NUM_OF_LANES* 4)-1):0] rx_ip_deterr, + output [((NUM_OF_LANES* 4)-1):0] rx_ip_kchar, + output [((NUM_OF_LANES* 1)-1):0] rx_ip_full, + output [((NUM_OF_LANES* 1)-1):0] rx_ip_empty, + input [((NUM_OF_LANES* 1)-1):0] rx_ip_align_en, + input [((NUM_OF_LANES* 1)-1):0] rx_ip_lane_polarity, + input [((NUM_OF_LANES* 1)-1):0] rx_ip_lane_powerdown, + input rx_ip_bit_reversal, + input rx_ip_byte_reversal, + + // rx-phy interface(s) + + input rx_phy_locked_0, + input rx_phy_cal_busy_0, + input rx_phy_valid_0, + input [31:0] rx_phy_data_0, + input [ 3:0] rx_phy_disperr_0, + input [ 3:0] rx_phy_deterr_0, + input [ 3:0] rx_phy_kchar_0, + input rx_phy_full_0, + input rx_phy_empty_0, + output rx_phy_align_en_0, + output rx_phy_lane_polarity_0, + output rx_phy_lane_powerdown_0, + output rx_phy_bit_reversal_0, + output rx_phy_byte_reversal_0, + output rx_phy_analogreset_0, + output rx_phy_digitalreset_0, + + input rx_phy_locked_1, + input rx_phy_cal_busy_1, + input rx_phy_valid_1, + input [31:0] rx_phy_data_1, + input [ 3:0] rx_phy_disperr_1, + input [ 3:0] rx_phy_deterr_1, + input [ 3:0] rx_phy_kchar_1, + input rx_phy_full_1, + input rx_phy_empty_1, + output rx_phy_align_en_1, + output rx_phy_lane_polarity_1, + output rx_phy_lane_powerdown_1, + output rx_phy_bit_reversal_1, + output rx_phy_byte_reversal_1, + output rx_phy_analogreset_1, + output rx_phy_digitalreset_1, + + input rx_phy_locked_2, + input rx_phy_cal_busy_2, + input rx_phy_valid_2, + input [31:0] rx_phy_data_2, + input [ 3:0] rx_phy_disperr_2, + input [ 3:0] rx_phy_deterr_2, + input [ 3:0] rx_phy_kchar_2, + input rx_phy_full_2, + input rx_phy_empty_2, + output rx_phy_align_en_2, + output rx_phy_lane_polarity_2, + output rx_phy_lane_powerdown_2, + output rx_phy_bit_reversal_2, + output rx_phy_byte_reversal_2, + output rx_phy_analogreset_2, + output rx_phy_digitalreset_2, + + input rx_phy_locked_3, + input rx_phy_cal_busy_3, + input rx_phy_valid_3, + input [31:0] rx_phy_data_3, + input [ 3:0] rx_phy_disperr_3, + input [ 3:0] rx_phy_deterr_3, + input [ 3:0] rx_phy_kchar_3, + input rx_phy_full_3, + input rx_phy_empty_3, + output rx_phy_align_en_3, + output rx_phy_lane_polarity_3, + output rx_phy_lane_powerdown_3, + output rx_phy_bit_reversal_3, + output rx_phy_byte_reversal_3, + output rx_phy_analogreset_3, + output rx_phy_digitalreset_3, + + input rx_phy_locked_4, + input rx_phy_cal_busy_4, + input rx_phy_valid_4, + input [31:0] rx_phy_data_4, + input [ 3:0] rx_phy_disperr_4, + input [ 3:0] rx_phy_deterr_4, + input [ 3:0] rx_phy_kchar_4, + input rx_phy_full_4, + input rx_phy_empty_4, + output rx_phy_align_en_4, + output rx_phy_lane_polarity_4, + output rx_phy_lane_powerdown_4, + output rx_phy_bit_reversal_4, + output rx_phy_byte_reversal_4, + output rx_phy_analogreset_4, + output rx_phy_digitalreset_4, + + input rx_phy_locked_5, + input rx_phy_cal_busy_5, + input rx_phy_valid_5, + input [31:0] rx_phy_data_5, + input [ 3:0] rx_phy_disperr_5, + input [ 3:0] rx_phy_deterr_5, + input [ 3:0] rx_phy_kchar_5, + input rx_phy_full_5, + input rx_phy_empty_5, + output rx_phy_align_en_5, + output rx_phy_lane_polarity_5, + output rx_phy_lane_powerdown_5, + output rx_phy_bit_reversal_5, + output rx_phy_byte_reversal_5, + output rx_phy_analogreset_5, + output rx_phy_digitalreset_5, + + input rx_phy_locked_6, + input rx_phy_cal_busy_6, + input rx_phy_valid_6, + input [31:0] rx_phy_data_6, + input [ 3:0] rx_phy_disperr_6, + input [ 3:0] rx_phy_deterr_6, + input [ 3:0] rx_phy_kchar_6, + input rx_phy_full_6, + input rx_phy_empty_6, + output rx_phy_align_en_6, + output rx_phy_lane_polarity_6, + output rx_phy_lane_powerdown_6, + output rx_phy_bit_reversal_6, + output rx_phy_byte_reversal_6, + output rx_phy_analogreset_6, + output rx_phy_digitalreset_6, + + input rx_phy_locked_7, + input rx_phy_cal_busy_7, + input rx_phy_valid_7, + input [31:0] rx_phy_data_7, + input [ 3:0] rx_phy_disperr_7, + input [ 3:0] rx_phy_deterr_7, + input [ 3:0] rx_phy_kchar_7, + input rx_phy_full_7, + input rx_phy_empty_7, + output rx_phy_align_en_7, + output rx_phy_lane_polarity_7, + output rx_phy_lane_powerdown_7, + output rx_phy_bit_reversal_7, + output rx_phy_byte_reversal_7, + output rx_phy_analogreset_7, + output rx_phy_digitalreset_7, + + // rx-core interface + + input [((NUM_OF_LANES* 1)-1):0] rx_core_analogreset, + input [((NUM_OF_LANES* 1)-1):0] rx_core_digitalreset, + output [((NUM_OF_LANES* 1)-1):0] rx_core_locked, + output [((NUM_OF_LANES* 1)-1):0] rx_core_cal_busy, + + // tx-ip interface + + output [((NUM_OF_LANES* 1)-1):0] tx_ip_cal_busy, + output [((NUM_OF_LANES* 1)-1):0] tx_ip_full, + output [((NUM_OF_LANES* 1)-1):0] tx_ip_empty, + input [((NUM_OF_LANES*32)-1):0] tx_ip_data, + input [((NUM_OF_LANES* 4)-1):0] tx_ip_kchar, + input [((NUM_OF_LANES* 1)-1):0] tx_ip_elecidle, + input [((NUM_OF_LANES* 1)-1):0] tx_ip_lane_polarity, + input [((NUM_OF_LANES* 1)-1):0] tx_ip_lane_powerdown, + input tx_ip_bit_reversal, + input tx_ip_byte_reversal, + + // tx-mux interface + + input [ 2:0] tx_ip_s_0, + output [38:0] tx_ip_d_0, + output [ 2:0] tx_phy_s_0, + input [38:0] tx_phy_d_0, + + input [ 2:0] tx_ip_s_1, + output [38:0] tx_ip_d_1, + output [ 2:0] tx_phy_s_1, + input [38:0] tx_phy_d_1, + + input [ 2:0] tx_ip_s_2, + output [38:0] tx_ip_d_2, + output [ 2:0] tx_phy_s_2, + input [38:0] tx_phy_d_2, + + input [ 2:0] tx_ip_s_3, + output [38:0] tx_ip_d_3, + output [ 2:0] tx_phy_s_3, + input [38:0] tx_phy_d_3, + + input [ 2:0] tx_ip_s_4, + output [38:0] tx_ip_d_4, + output [ 2:0] tx_phy_s_4, + input [38:0] tx_phy_d_4, + + input [ 2:0] tx_ip_s_5, + output [38:0] tx_ip_d_5, + output [ 2:0] tx_phy_s_5, + input [38:0] tx_phy_d_5, + + input [ 2:0] tx_ip_s_6, + output [38:0] tx_ip_d_6, + output [ 2:0] tx_phy_s_6, + input [38:0] tx_phy_d_6, + + input [ 2:0] tx_ip_s_7, + output [38:0] tx_ip_d_7, + output [ 2:0] tx_phy_s_7, + input [38:0] tx_phy_d_7, + + // tx-phy interface + + input tx_phy_cal_busy_0, + input tx_phy_full_0, + input tx_phy_empty_0, + output [31:0] tx_phy_data_0, + output [ 3:0] tx_phy_kchar_0, + output tx_phy_elecidle_0, + output tx_phy_lane_polarity_0, + output tx_phy_lane_powerdown_0, + output tx_phy_bit_reversal_0, + output tx_phy_byte_reversal_0, + output tx_phy_analogreset_0, + output tx_phy_digitalreset_0, + + input tx_phy_cal_busy_1, + input tx_phy_full_1, + input tx_phy_empty_1, + output [31:0] tx_phy_data_1, + output [ 3:0] tx_phy_kchar_1, + output tx_phy_elecidle_1, + output tx_phy_lane_polarity_1, + output tx_phy_lane_powerdown_1, + output tx_phy_bit_reversal_1, + output tx_phy_byte_reversal_1, + output tx_phy_analogreset_1, + output tx_phy_digitalreset_1, + + input tx_phy_cal_busy_2, + input tx_phy_full_2, + input tx_phy_empty_2, + output [31:0] tx_phy_data_2, + output [ 3:0] tx_phy_kchar_2, + output tx_phy_elecidle_2, + output tx_phy_lane_polarity_2, + output tx_phy_lane_powerdown_2, + output tx_phy_bit_reversal_2, + output tx_phy_byte_reversal_2, + output tx_phy_analogreset_2, + output tx_phy_digitalreset_2, + + input tx_phy_cal_busy_3, + input tx_phy_full_3, + input tx_phy_empty_3, + output [31:0] tx_phy_data_3, + output [ 3:0] tx_phy_kchar_3, + output tx_phy_elecidle_3, + output tx_phy_lane_polarity_3, + output tx_phy_lane_powerdown_3, + output tx_phy_bit_reversal_3, + output tx_phy_byte_reversal_3, + output tx_phy_analogreset_3, + output tx_phy_digitalreset_3, + + input tx_phy_cal_busy_4, + input tx_phy_full_4, + input tx_phy_empty_4, + output [31:0] tx_phy_data_4, + output [ 3:0] tx_phy_kchar_4, + output tx_phy_elecidle_4, + output tx_phy_lane_polarity_4, + output tx_phy_lane_powerdown_4, + output tx_phy_bit_reversal_4, + output tx_phy_byte_reversal_4, + output tx_phy_analogreset_4, + output tx_phy_digitalreset_4, + + input tx_phy_cal_busy_5, + input tx_phy_full_5, + input tx_phy_empty_5, + output [31:0] tx_phy_data_5, + output [ 3:0] tx_phy_kchar_5, + output tx_phy_elecidle_5, + output tx_phy_lane_polarity_5, + output tx_phy_lane_powerdown_5, + output tx_phy_bit_reversal_5, + output tx_phy_byte_reversal_5, + output tx_phy_analogreset_5, + output tx_phy_digitalreset_5, + + input tx_phy_cal_busy_6, + input tx_phy_full_6, + input tx_phy_empty_6, + output [31:0] tx_phy_data_6, + output [ 3:0] tx_phy_kchar_6, + output tx_phy_elecidle_6, + output tx_phy_lane_polarity_6, + output tx_phy_lane_powerdown_6, + output tx_phy_bit_reversal_6, + output tx_phy_byte_reversal_6, + output tx_phy_analogreset_6, + output tx_phy_digitalreset_6, + + input tx_phy_cal_busy_7, + input tx_phy_full_7, + input tx_phy_empty_7, + output [31:0] tx_phy_data_7, + output [ 3:0] tx_phy_kchar_7, + output tx_phy_elecidle_7, + output tx_phy_lane_polarity_7, + output tx_phy_lane_powerdown_7, + output tx_phy_bit_reversal_7, + output tx_phy_byte_reversal_7, + output tx_phy_analogreset_7, + output tx_phy_digitalreset_7, + + // tx-core interface + + input [((NUM_OF_LANES* 1)-1):0] tx_core_analogreset, + input [((NUM_OF_LANES* 1)-1):0] tx_core_digitalreset, + output [((NUM_OF_LANES* 1)-1):0] tx_core_cal_busy); + + // rx assignments + + generate + if (NUM_OF_LANES > 0) begin + assign rx_core_locked[0] = rx_phy_locked_0; + assign rx_core_cal_busy[0] = rx_phy_cal_busy_0; + assign rx_ip_locked[0] = rx_phy_locked_0; + assign rx_ip_cal_busy[0] = rx_phy_cal_busy_0; + assign rx_ip_valid[0] = rx_phy_valid_0; + assign rx_ip_data[((32*1)-1):(32*0)] = rx_phy_data_0; + assign rx_ip_disperr[((4*1)-1):(4*0)] = rx_phy_disperr_0; + assign rx_ip_deterr[((4*1)-1):(4*0)] = rx_phy_deterr_0; + assign rx_ip_kchar[((4*1)-1):(4*0)] = rx_phy_kchar_0; + assign rx_ip_full[0] = rx_phy_full_0; + assign rx_ip_empty[0] = rx_phy_empty_0; + end + endgenerate + + generate + if (NUM_OF_LANES > 0) begin + assign rx_phy_align_en_0 = rx_ip_align_en[0]; + assign rx_phy_lane_polarity_0 = rx_ip_lane_polarity[0]; + assign rx_phy_lane_powerdown_0 = rx_ip_lane_powerdown[0]; + assign rx_phy_analogreset_0 = rx_core_analogreset[0]; + assign rx_phy_digitalreset_0 = rx_core_digitalreset[0]; + end else begin + assign rx_phy_align_en_0 = 1'd0; + assign rx_phy_lane_polarity_0 = 1'd0; + assign rx_phy_lane_powerdown_0 = 1'd0; + assign rx_phy_analogreset_0 = 1'd1; + assign rx_phy_digitalreset_0 = 1'd1; + end + endgenerate + + assign rx_phy_bit_reversal_0 = rx_ip_bit_reversal; + assign rx_phy_byte_reversal_0 = rx_ip_byte_reversal; + + generate + if (NUM_OF_LANES > 1) begin + assign rx_core_locked[1] = rx_phy_locked_1; + assign rx_core_cal_busy[1] = rx_phy_cal_busy_1; + assign rx_ip_locked[1] = rx_phy_locked_1; + assign rx_ip_cal_busy[1] = rx_phy_cal_busy_1; + assign rx_ip_valid[1] = rx_phy_valid_1; + assign rx_ip_data[((32*2)-1):(32*1)] = rx_phy_data_1; + assign rx_ip_disperr[((4*2)-1):(4*1)] = rx_phy_disperr_1; + assign rx_ip_deterr[((4*2)-1):(4*1)] = rx_phy_deterr_1; + assign rx_ip_kchar[((4*2)-1):(4*1)] = rx_phy_kchar_1; + assign rx_ip_full[1] = rx_phy_full_1; + assign rx_ip_empty[1] = rx_phy_empty_1; + end + endgenerate + + generate + if (NUM_OF_LANES > 1) begin + assign rx_phy_align_en_1 = rx_ip_align_en[1]; + assign rx_phy_lane_polarity_1 = rx_ip_lane_polarity[1]; + assign rx_phy_lane_powerdown_1 = rx_ip_lane_powerdown[1]; + assign rx_phy_analogreset_1 = rx_core_analogreset[1]; + assign rx_phy_digitalreset_1 = rx_core_digitalreset[1]; + end else begin + assign rx_phy_align_en_1 = 1'd0; + assign rx_phy_lane_polarity_1 = 1'd0; + assign rx_phy_lane_powerdown_1 = 1'd0; + assign rx_phy_analogreset_1 = 1'd1; + assign rx_phy_digitalreset_1 = 1'd1; + end + endgenerate + + assign rx_phy_bit_reversal_1 = rx_ip_bit_reversal; + assign rx_phy_byte_reversal_1 = rx_ip_byte_reversal; + + generate + if (NUM_OF_LANES > 2) begin + assign rx_core_locked[2] = rx_phy_locked_2; + assign rx_core_cal_busy[2] = rx_phy_cal_busy_2; + assign rx_ip_locked[2] = rx_phy_locked_2; + assign rx_ip_cal_busy[2] = rx_phy_cal_busy_2; + assign rx_ip_valid[2] = rx_phy_valid_2; + assign rx_ip_data[((32*3)-1):(32*2)] = rx_phy_data_2; + assign rx_ip_disperr[((4*3)-1):(4*2)] = rx_phy_disperr_2; + assign rx_ip_deterr[((4*3)-1):(4*2)] = rx_phy_deterr_2; + assign rx_ip_kchar[((4*3)-1):(4*2)] = rx_phy_kchar_2; + assign rx_ip_full[2] = rx_phy_full_2; + assign rx_ip_empty[2] = rx_phy_empty_2; + end + endgenerate + + generate + if (NUM_OF_LANES > 2) begin + assign rx_phy_align_en_2 = rx_ip_align_en[2]; + assign rx_phy_lane_polarity_2 = rx_ip_lane_polarity[2]; + assign rx_phy_lane_powerdown_2 = rx_ip_lane_powerdown[2]; + assign rx_phy_analogreset_2 = rx_core_analogreset[2]; + assign rx_phy_digitalreset_2 = rx_core_digitalreset[2]; + end else begin + assign rx_phy_align_en_2 = 1'd0; + assign rx_phy_lane_polarity_2 = 1'd0; + assign rx_phy_lane_powerdown_2 = 1'd0; + assign rx_phy_analogreset_2 = 1'd1; + assign rx_phy_digitalreset_2 = 1'd1; + end + endgenerate + + assign rx_phy_bit_reversal_2 = rx_ip_bit_reversal; + assign rx_phy_byte_reversal_2 = rx_ip_byte_reversal; + + generate + if (NUM_OF_LANES > 3) begin + assign rx_core_locked[3] = rx_phy_locked_3; + assign rx_core_cal_busy[3] = rx_phy_cal_busy_3; + assign rx_ip_locked[3] = rx_phy_locked_3; + assign rx_ip_cal_busy[3] = rx_phy_cal_busy_3; + assign rx_ip_valid[3] = rx_phy_valid_3; + assign rx_ip_data[((32*4)-1):(32*3)] = rx_phy_data_3; + assign rx_ip_disperr[((4*4)-1):(4*3)] = rx_phy_disperr_3; + assign rx_ip_deterr[((4*4)-1):(4*3)] = rx_phy_deterr_3; + assign rx_ip_kchar[((4*4)-1):(4*3)] = rx_phy_kchar_3; + assign rx_ip_full[3] = rx_phy_full_3; + assign rx_ip_empty[3] = rx_phy_empty_3; + end + endgenerate + + generate + if (NUM_OF_LANES > 3) begin + assign rx_phy_align_en_3 = rx_ip_align_en[3]; + assign rx_phy_lane_polarity_3 = rx_ip_lane_polarity[3]; + assign rx_phy_lane_powerdown_3 = rx_ip_lane_powerdown[3]; + assign rx_phy_analogreset_3 = rx_core_analogreset[3]; + assign rx_phy_digitalreset_3 = rx_core_digitalreset[3]; + end else begin + assign rx_phy_align_en_3 = 1'd0; + assign rx_phy_lane_polarity_3 = 1'd0; + assign rx_phy_lane_powerdown_3 = 1'd0; + assign rx_phy_analogreset_3 = 1'd1; + assign rx_phy_digitalreset_3 = 1'd1; + end + endgenerate + + assign rx_phy_bit_reversal_3 = rx_ip_bit_reversal; + assign rx_phy_byte_reversal_3 = rx_ip_byte_reversal; + + generate + if (NUM_OF_LANES > 4) begin + assign rx_core_locked[4] = rx_phy_locked_4; + assign rx_core_cal_busy[4] = rx_phy_cal_busy_4; + assign rx_ip_locked[4] = rx_phy_locked_4; + assign rx_ip_cal_busy[4] = rx_phy_cal_busy_4; + assign rx_ip_valid[4] = rx_phy_valid_4; + assign rx_ip_data[((32*5)-1):(32*4)] = rx_phy_data_4; + assign rx_ip_disperr[((4*5)-1):(4*4)] = rx_phy_disperr_4; + assign rx_ip_deterr[((4*5)-1):(4*4)] = rx_phy_deterr_4; + assign rx_ip_kchar[((4*5)-1):(4*4)] = rx_phy_kchar_4; + assign rx_ip_full[4] = rx_phy_full_4; + assign rx_ip_empty[4] = rx_phy_empty_4; + end + endgenerate + + generate + if (NUM_OF_LANES > 4) begin + assign rx_phy_align_en_4 = rx_ip_align_en[4]; + assign rx_phy_lane_polarity_4 = rx_ip_lane_polarity[4]; + assign rx_phy_lane_powerdown_4 = rx_ip_lane_powerdown[4]; + assign rx_phy_analogreset_4 = rx_core_analogreset[4]; + assign rx_phy_digitalreset_4 = rx_core_digitalreset[4]; + end else begin + assign rx_phy_align_en_4 = 1'd0; + assign rx_phy_lane_polarity_4 = 1'd0; + assign rx_phy_lane_powerdown_4 = 1'd0; + assign rx_phy_analogreset_4 = 1'd1; + assign rx_phy_digitalreset_4 = 1'd1; + end + endgenerate + + assign rx_phy_bit_reversal_4 = rx_ip_bit_reversal; + assign rx_phy_byte_reversal_4 = rx_ip_byte_reversal; + + generate + if (NUM_OF_LANES > 5) begin + assign rx_core_locked[5] = rx_phy_locked_5; + assign rx_core_cal_busy[5] = rx_phy_cal_busy_5; + assign rx_ip_locked[5] = rx_phy_locked_5; + assign rx_ip_cal_busy[5] = rx_phy_cal_busy_5; + assign rx_ip_valid[5] = rx_phy_valid_5; + assign rx_ip_data[((32*6)-1):(32*5)] = rx_phy_data_5; + assign rx_ip_disperr[((4*6)-1):(4*5)] = rx_phy_disperr_5; + assign rx_ip_deterr[((4*6)-1):(4*5)] = rx_phy_deterr_5; + assign rx_ip_kchar[((4*6)-1):(4*5)] = rx_phy_kchar_5; + assign rx_ip_full[5] = rx_phy_full_5; + assign rx_ip_empty[5] = rx_phy_empty_5; + end + endgenerate + + generate + if (NUM_OF_LANES > 5) begin + assign rx_phy_align_en_5 = rx_ip_align_en[5]; + assign rx_phy_lane_polarity_5 = rx_ip_lane_polarity[5]; + assign rx_phy_lane_powerdown_5 = rx_ip_lane_powerdown[5]; + assign rx_phy_analogreset_5 = rx_core_analogreset[5]; + assign rx_phy_digitalreset_5 = rx_core_digitalreset[5]; + end else begin + assign rx_phy_align_en_5 = 1'd0; + assign rx_phy_lane_polarity_5 = 1'd0; + assign rx_phy_lane_powerdown_5 = 1'd0; + assign rx_phy_analogreset_5 = 1'd1; + assign rx_phy_digitalreset_5 = 1'd1; + end + endgenerate + + assign rx_phy_bit_reversal_5 = rx_ip_bit_reversal; + assign rx_phy_byte_reversal_5 = rx_ip_byte_reversal; + + generate + if (NUM_OF_LANES > 6) begin + assign rx_core_locked[6] = rx_phy_locked_6; + assign rx_core_cal_busy[6] = rx_phy_cal_busy_6; + assign rx_ip_locked[6] = rx_phy_locked_6; + assign rx_ip_cal_busy[6] = rx_phy_cal_busy_6; + assign rx_ip_valid[6] = rx_phy_valid_6; + assign rx_ip_data[((32*7)-1):(32*6)] = rx_phy_data_6; + assign rx_ip_disperr[((4*7)-1):(4*6)] = rx_phy_disperr_6; + assign rx_ip_deterr[((4*7)-1):(4*6)] = rx_phy_deterr_6; + assign rx_ip_kchar[((4*7)-1):(4*6)] = rx_phy_kchar_6; + assign rx_ip_full[6] = rx_phy_full_6; + assign rx_ip_empty[6] = rx_phy_empty_6; + end + endgenerate + + generate + if (NUM_OF_LANES > 6) begin + assign rx_phy_align_en_6 = rx_ip_align_en[6]; + assign rx_phy_lane_polarity_6 = rx_ip_lane_polarity[6]; + assign rx_phy_lane_powerdown_6 = rx_ip_lane_powerdown[6]; + assign rx_phy_analogreset_6 = rx_core_analogreset[6]; + assign rx_phy_digitalreset_6 = rx_core_digitalreset[6]; + end else begin + assign rx_phy_align_en_6 = 1'd0; + assign rx_phy_lane_polarity_6 = 1'd0; + assign rx_phy_lane_powerdown_6 = 1'd0; + assign rx_phy_analogreset_6 = 1'd1; + assign rx_phy_digitalreset_6 = 1'd1; + end + endgenerate + + assign rx_phy_bit_reversal_6 = rx_ip_bit_reversal; + assign rx_phy_byte_reversal_6 = rx_ip_byte_reversal; + + generate + if (NUM_OF_LANES > 7) begin + assign rx_core_locked[7] = rx_phy_locked_7; + assign rx_core_cal_busy[7] = rx_phy_cal_busy_7; + assign rx_ip_locked[7] = rx_phy_locked_7; + assign rx_ip_cal_busy[7] = rx_phy_cal_busy_7; + assign rx_ip_valid[7] = rx_phy_valid_7; + assign rx_ip_data[((32*8)-1):(32*7)] = rx_phy_data_7; + assign rx_ip_disperr[((4*8)-1):(4*7)] = rx_phy_disperr_7; + assign rx_ip_deterr[((4*8)-1):(4*7)] = rx_phy_deterr_7; + assign rx_ip_kchar[((4*8)-1):(4*7)] = rx_phy_kchar_7; + assign rx_ip_full[7] = rx_phy_full_7; + assign rx_ip_empty[7] = rx_phy_empty_7; + end + endgenerate + + generate + if (NUM_OF_LANES > 7) begin + assign rx_phy_align_en_7 = rx_ip_align_en[7]; + assign rx_phy_lane_polarity_7 = rx_ip_lane_polarity[7]; + assign rx_phy_lane_powerdown_7 = rx_ip_lane_powerdown[7]; + assign rx_phy_analogreset_7 = rx_core_analogreset[7]; + assign rx_phy_digitalreset_7 = rx_core_digitalreset[7]; + end else begin + assign rx_phy_align_en_7 = 1'd0; + assign rx_phy_lane_polarity_7 = 1'd0; + assign rx_phy_lane_powerdown_7 = 1'd0; + assign rx_phy_analogreset_7 = 1'd1; + assign rx_phy_digitalreset_7 = 1'd1; + end + endgenerate + + assign rx_phy_bit_reversal_7 = rx_ip_bit_reversal; + assign rx_phy_byte_reversal_7 = rx_ip_byte_reversal; + + // tx assignments + + generate + if (NUM_OF_LANES > 0) begin + assign tx_core_cal_busy[0] = tx_ip_s_0[0]; + assign tx_ip_cal_busy[0] = tx_ip_s_0[0]; + assign tx_ip_full[0] = tx_ip_s_0[1]; + assign tx_ip_empty[0] = tx_ip_s_0[2]; + end + endgenerate + + generate + if (NUM_OF_LANES > 0) begin + assign tx_ip_d_0[31: 0] = tx_ip_data[((32*1)-1):(32*0)]; + assign tx_ip_d_0[35:32] = tx_ip_kchar[((4*1)-1):(4*0)]; + assign tx_ip_d_0[36:36] = tx_ip_elecidle[0]; + assign tx_ip_d_0[37:37] = tx_ip_lane_polarity[0]; + assign tx_ip_d_0[38:38] = tx_ip_lane_powerdown[0]; + end else begin + assign tx_ip_d_0[31: 0] = 32'd0; + assign tx_ip_d_0[35:32] = 4'd0; + assign tx_ip_d_0[36:36] = 1'd0; + assign tx_ip_d_0[37:37] = 1'd0; + assign tx_ip_d_0[38:38] = 1'd0; + end + endgenerate + + generate + if (NUM_OF_LANES > 0) begin + assign tx_phy_analogreset_0 = tx_core_analogreset[0]; + assign tx_phy_digitalreset_0 = tx_core_digitalreset[0]; + end else begin + assign tx_phy_analogreset_0 = 1'd1; + assign tx_phy_digitalreset_0 = 1'd1; + end + endgenerate + + assign tx_phy_s_0[0] = tx_phy_cal_busy_0; + assign tx_phy_s_0[1] = tx_phy_full_0; + assign tx_phy_s_0[2] = tx_phy_empty_0; + assign tx_phy_data_0 = tx_phy_d_0[31:0]; + assign tx_phy_kchar_0 = tx_phy_d_0[35:32]; + assign tx_phy_elecidle_0 = tx_phy_d_0[36]; + assign tx_phy_lane_polarity_0 = tx_phy_d_0[37]; + assign tx_phy_lane_powerdown_0 = tx_phy_d_0[38]; + assign tx_phy_bit_reversal_0 = tx_ip_bit_reversal; + assign tx_phy_byte_reversal_0 = tx_ip_byte_reversal; + + generate + if (NUM_OF_LANES > 1) begin + assign tx_core_cal_busy[1] = tx_ip_s_1[0]; + assign tx_ip_cal_busy[1] = tx_ip_s_1[0]; + assign tx_ip_full[1] = tx_ip_s_1[1]; + assign tx_ip_empty[1] = tx_ip_s_1[2]; + end + endgenerate + + generate + if (NUM_OF_LANES > 1) begin + assign tx_ip_d_1[31: 0] = tx_ip_data[((32*2)-1):(32*1)]; + assign tx_ip_d_1[35:32] = tx_ip_kchar[((4*2)-1):(4*1)]; + assign tx_ip_d_1[36:36] = tx_ip_elecidle[1]; + assign tx_ip_d_1[37:37] = tx_ip_lane_polarity[1]; + assign tx_ip_d_1[38:38] = tx_ip_lane_powerdown[1]; + end else begin + assign tx_ip_d_1[31: 0] = 32'd0; + assign tx_ip_d_1[35:32] = 4'd0; + assign tx_ip_d_1[36:36] = 1'd0; + assign tx_ip_d_1[37:37] = 1'd0; + assign tx_ip_d_1[38:38] = 1'd0; + end + endgenerate + + generate + if (NUM_OF_LANES > 1) begin + assign tx_phy_analogreset_1 = tx_core_analogreset[1]; + assign tx_phy_digitalreset_1 = tx_core_digitalreset[1]; + end else begin + assign tx_phy_analogreset_1 = 1'd1; + assign tx_phy_digitalreset_1 = 1'd1; + end + endgenerate + + assign tx_phy_s_1[0] = tx_phy_cal_busy_1; + assign tx_phy_s_1[1] = tx_phy_full_1; + assign tx_phy_s_1[2] = tx_phy_empty_1; + assign tx_phy_data_1 = tx_phy_d_1[31:0]; + assign tx_phy_kchar_1 = tx_phy_d_1[35:32]; + assign tx_phy_elecidle_1 = tx_phy_d_1[36]; + assign tx_phy_lane_polarity_1 = tx_phy_d_1[37]; + assign tx_phy_lane_powerdown_1 = tx_phy_d_1[38]; + assign tx_phy_bit_reversal_1 = tx_ip_bit_reversal; + assign tx_phy_byte_reversal_1 = tx_ip_byte_reversal; + + generate + if (NUM_OF_LANES > 2) begin + assign tx_core_cal_busy[2] = tx_ip_s_2[0]; + assign tx_ip_cal_busy[2] = tx_ip_s_2[0]; + assign tx_ip_full[2] = tx_ip_s_2[1]; + assign tx_ip_empty[2] = tx_ip_s_2[2]; + end + endgenerate + + generate + if (NUM_OF_LANES > 2) begin + assign tx_ip_d_2[31: 0] = tx_ip_data[((32*3)-1):(32*2)]; + assign tx_ip_d_2[35:32] = tx_ip_kchar[((4*3)-1):(4*2)]; + assign tx_ip_d_2[36:36] = tx_ip_elecidle[2]; + assign tx_ip_d_2[37:37] = tx_ip_lane_polarity[2]; + assign tx_ip_d_2[38:38] = tx_ip_lane_powerdown[2]; + end else begin + assign tx_ip_d_2[31: 0] = 32'd0; + assign tx_ip_d_2[35:32] = 4'd0; + assign tx_ip_d_2[36:36] = 1'd0; + assign tx_ip_d_2[37:37] = 1'd0; + assign tx_ip_d_2[38:38] = 1'd0; + end + endgenerate + + generate + if (NUM_OF_LANES > 2) begin + assign tx_phy_analogreset_2 = tx_core_analogreset[2]; + assign tx_phy_digitalreset_2 = tx_core_digitalreset[2]; + end else begin + assign tx_phy_analogreset_2 = 1'd1; + assign tx_phy_digitalreset_2 = 1'd1; + end + endgenerate + + assign tx_phy_s_2[0] = tx_phy_cal_busy_2; + assign tx_phy_s_2[1] = tx_phy_full_2; + assign tx_phy_s_2[2] = tx_phy_empty_2; + assign tx_phy_data_2 = tx_phy_d_2[31:0]; + assign tx_phy_kchar_2 = tx_phy_d_2[35:32]; + assign tx_phy_elecidle_2 = tx_phy_d_2[36]; + assign tx_phy_lane_polarity_2 = tx_phy_d_2[37]; + assign tx_phy_lane_powerdown_2 = tx_phy_d_2[38]; + assign tx_phy_bit_reversal_2 = tx_ip_bit_reversal; + assign tx_phy_byte_reversal_2 = tx_ip_byte_reversal; + + generate + if (NUM_OF_LANES > 3) begin + assign tx_core_cal_busy[3] = tx_ip_s_3[0]; + assign tx_ip_cal_busy[3] = tx_ip_s_3[0]; + assign tx_ip_full[3] = tx_ip_s_3[1]; + assign tx_ip_empty[3] = tx_ip_s_3[2]; + end + endgenerate + + generate + if (NUM_OF_LANES > 3) begin + assign tx_ip_d_3[31: 0] = tx_ip_data[((32*4)-1):(32*3)]; + assign tx_ip_d_3[35:32] = tx_ip_kchar[((4*4)-1):(4*3)]; + assign tx_ip_d_3[36:36] = tx_ip_elecidle[3]; + assign tx_ip_d_3[37:37] = tx_ip_lane_polarity[3]; + assign tx_ip_d_3[38:38] = tx_ip_lane_powerdown[3]; + end else begin + assign tx_ip_d_3[31: 0] = 32'd0; + assign tx_ip_d_3[35:32] = 4'd0; + assign tx_ip_d_3[36:36] = 1'd0; + assign tx_ip_d_3[37:37] = 1'd0; + assign tx_ip_d_3[38:38] = 1'd0; + end + endgenerate + + generate + if (NUM_OF_LANES > 3) begin + assign tx_phy_analogreset_3 = tx_core_analogreset[3]; + assign tx_phy_digitalreset_3 = tx_core_digitalreset[3]; + end else begin + assign tx_phy_analogreset_3 = 1'd1; + assign tx_phy_digitalreset_3 = 1'd1; + end + endgenerate + + assign tx_phy_s_3[0] = tx_phy_cal_busy_3; + assign tx_phy_s_3[1] = tx_phy_full_3; + assign tx_phy_s_3[2] = tx_phy_empty_3; + assign tx_phy_data_3 = tx_phy_d_3[31:0]; + assign tx_phy_kchar_3 = tx_phy_d_3[35:32]; + assign tx_phy_elecidle_3 = tx_phy_d_3[36]; + assign tx_phy_lane_polarity_3 = tx_phy_d_3[37]; + assign tx_phy_lane_powerdown_3 = tx_phy_d_3[38]; + assign tx_phy_bit_reversal_3 = tx_ip_bit_reversal; + assign tx_phy_byte_reversal_3 = tx_ip_byte_reversal; + + generate + if (NUM_OF_LANES > 4) begin + assign tx_core_cal_busy[4] = tx_ip_s_4[0]; + assign tx_ip_cal_busy[4] = tx_ip_s_4[0]; + assign tx_ip_full[4] = tx_ip_s_4[1]; + assign tx_ip_empty[4] = tx_ip_s_4[2]; + end + endgenerate + + generate + if (NUM_OF_LANES > 4) begin + assign tx_ip_d_4[31: 0] = tx_ip_data[((32*5)-1):(32*4)]; + assign tx_ip_d_4[35:32] = tx_ip_kchar[((4*5)-1):(4*4)]; + assign tx_ip_d_4[36:36] = tx_ip_elecidle[4]; + assign tx_ip_d_4[37:37] = tx_ip_lane_polarity[4]; + assign tx_ip_d_4[38:38] = tx_ip_lane_powerdown[4]; + end else begin + assign tx_ip_d_4[31: 0] = 32'd0; + assign tx_ip_d_4[35:32] = 4'd0; + assign tx_ip_d_4[36:36] = 1'd0; + assign tx_ip_d_4[37:37] = 1'd0; + assign tx_ip_d_4[38:38] = 1'd0; + end + endgenerate + + generate + if (NUM_OF_LANES > 4) begin + assign tx_phy_analogreset_4 = tx_core_analogreset[4]; + assign tx_phy_digitalreset_4 = tx_core_digitalreset[4]; + end else begin + assign tx_phy_analogreset_4 = 1'd1; + assign tx_phy_digitalreset_4 = 1'd1; + end + endgenerate + + assign tx_phy_s_4[0] = tx_phy_cal_busy_4; + assign tx_phy_s_4[1] = tx_phy_full_4; + assign tx_phy_s_4[2] = tx_phy_empty_4; + assign tx_phy_data_4 = tx_phy_d_4[31:0]; + assign tx_phy_kchar_4 = tx_phy_d_4[35:32]; + assign tx_phy_elecidle_4 = tx_phy_d_4[36]; + assign tx_phy_lane_polarity_4 = tx_phy_d_4[37]; + assign tx_phy_lane_powerdown_4 = tx_phy_d_4[38]; + assign tx_phy_bit_reversal_4 = tx_ip_bit_reversal; + assign tx_phy_byte_reversal_4 = tx_ip_byte_reversal; + + generate + if (NUM_OF_LANES > 5) begin + assign tx_core_cal_busy[5] = tx_ip_s_5[0]; + assign tx_ip_cal_busy[5] = tx_ip_s_5[0]; + assign tx_ip_full[5] = tx_ip_s_5[1]; + assign tx_ip_empty[5] = tx_ip_s_5[2]; + end + endgenerate + + generate + if (NUM_OF_LANES > 5) begin + assign tx_ip_d_5[31: 0] = tx_ip_data[((32*6)-1):(32*5)]; + assign tx_ip_d_5[35:32] = tx_ip_kchar[((4*6)-1):(4*5)]; + assign tx_ip_d_5[36:36] = tx_ip_elecidle[5]; + assign tx_ip_d_5[37:37] = tx_ip_lane_polarity[5]; + assign tx_ip_d_5[38:38] = tx_ip_lane_powerdown[5]; + end else begin + assign tx_ip_d_5[31: 0] = 32'd0; + assign tx_ip_d_5[35:32] = 4'd0; + assign tx_ip_d_5[36:36] = 1'd0; + assign tx_ip_d_5[37:37] = 1'd0; + assign tx_ip_d_5[38:38] = 1'd0; + end + endgenerate + + generate + if (NUM_OF_LANES > 5) begin + assign tx_phy_analogreset_5 = tx_core_analogreset[5]; + assign tx_phy_digitalreset_5 = tx_core_digitalreset[5]; + end else begin + assign tx_phy_analogreset_5 = 1'd1; + assign tx_phy_digitalreset_5 = 1'd1; + end + endgenerate + + assign tx_phy_s_5[0] = tx_phy_cal_busy_5; + assign tx_phy_s_5[1] = tx_phy_full_5; + assign tx_phy_s_5[2] = tx_phy_empty_5; + assign tx_phy_data_5 = tx_phy_d_5[31:0]; + assign tx_phy_kchar_5 = tx_phy_d_5[35:32]; + assign tx_phy_elecidle_5 = tx_phy_d_5[36]; + assign tx_phy_lane_polarity_5 = tx_phy_d_5[37]; + assign tx_phy_lane_powerdown_5 = tx_phy_d_5[38]; + assign tx_phy_bit_reversal_5 = tx_ip_bit_reversal; + assign tx_phy_byte_reversal_5 = tx_ip_byte_reversal; + + generate + if (NUM_OF_LANES > 6) begin + assign tx_core_cal_busy[6] = tx_ip_s_6[0]; + assign tx_ip_cal_busy[6] = tx_ip_s_6[0]; + assign tx_ip_full[6] = tx_ip_s_6[1]; + assign tx_ip_empty[6] = tx_ip_s_6[2]; + end + endgenerate + + generate + if (NUM_OF_LANES > 6) begin + assign tx_ip_d_6[31: 0] = tx_ip_data[((32*7)-1):(32*6)]; + assign tx_ip_d_6[35:32] = tx_ip_kchar[((4*7)-1):(4*6)]; + assign tx_ip_d_6[36:36] = tx_ip_elecidle[6]; + assign tx_ip_d_6[37:37] = tx_ip_lane_polarity[6]; + assign tx_ip_d_6[38:38] = tx_ip_lane_powerdown[6]; + end else begin + assign tx_ip_d_6[31: 0] = 32'd0; + assign tx_ip_d_6[35:32] = 4'd0; + assign tx_ip_d_6[36:36] = 1'd0; + assign tx_ip_d_6[37:37] = 1'd0; + assign tx_ip_d_6[38:38] = 1'd0; + end + endgenerate + + generate + if (NUM_OF_LANES > 6) begin + assign tx_phy_analogreset_6 = tx_core_analogreset[6]; + assign tx_phy_digitalreset_6 = tx_core_digitalreset[6]; + end else begin + assign tx_phy_analogreset_6 = 1'd1; + assign tx_phy_digitalreset_6 = 1'd1; + end + endgenerate + + assign tx_phy_s_6[0] = tx_phy_cal_busy_6; + assign tx_phy_s_6[1] = tx_phy_full_6; + assign tx_phy_s_6[2] = tx_phy_empty_6; + assign tx_phy_data_6 = tx_phy_d_6[31:0]; + assign tx_phy_kchar_6 = tx_phy_d_6[35:32]; + assign tx_phy_elecidle_6 = tx_phy_d_6[36]; + assign tx_phy_lane_polarity_6 = tx_phy_d_6[37]; + assign tx_phy_lane_powerdown_6 = tx_phy_d_6[38]; + assign tx_phy_bit_reversal_6 = tx_ip_bit_reversal; + assign tx_phy_byte_reversal_6 = tx_ip_byte_reversal; + + generate + if (NUM_OF_LANES > 7) begin + assign tx_core_cal_busy[7] = tx_ip_s_7[0]; + assign tx_ip_cal_busy[7] = tx_ip_s_7[0]; + assign tx_ip_full[7] = tx_ip_s_7[1]; + assign tx_ip_empty[7] = tx_ip_s_7[2]; + end + endgenerate + + generate + if (NUM_OF_LANES > 7) begin + assign tx_ip_d_7[31: 0] = tx_ip_data[((32*8)-1):(32*7)]; + assign tx_ip_d_7[35:32] = tx_ip_kchar[((4*8)-1):(4*7)]; + assign tx_ip_d_7[36:36] = tx_ip_elecidle[7]; + assign tx_ip_d_7[37:37] = tx_ip_lane_polarity[7]; + assign tx_ip_d_7[38:38] = tx_ip_lane_powerdown[7]; + end else begin + assign tx_ip_d_7[31: 0] = 32'd0; + assign tx_ip_d_7[35:32] = 4'd0; + assign tx_ip_d_7[36:36] = 1'd0; + assign tx_ip_d_7[37:37] = 1'd0; + assign tx_ip_d_7[38:38] = 1'd0; + end + endgenerate + + generate + if (NUM_OF_LANES > 7) begin + assign tx_phy_analogreset_7 = tx_core_analogreset[7]; + assign tx_phy_digitalreset_7 = tx_core_digitalreset[7]; + end else begin + assign tx_phy_analogreset_7 = 1'd1; + assign tx_phy_digitalreset_7 = 1'd1; + end + endgenerate + + assign tx_phy_s_7[0] = tx_phy_cal_busy_7; + assign tx_phy_s_7[1] = tx_phy_full_7; + assign tx_phy_s_7[2] = tx_phy_empty_7; + assign tx_phy_data_7 = tx_phy_d_7[31:0]; + assign tx_phy_kchar_7 = tx_phy_d_7[35:32]; + assign tx_phy_elecidle_7 = tx_phy_d_7[36]; + assign tx_phy_lane_polarity_7 = tx_phy_d_7[37]; + assign tx_phy_lane_powerdown_7 = tx_phy_d_7[38]; + assign tx_phy_bit_reversal_7 = tx_ip_bit_reversal; + assign tx_phy_byte_reversal_7 = tx_ip_byte_reversal; + +endmodule + +// *************************************************************************** +// *************************************************************************** + diff --git a/library/altera/avl_adxphy/avl_adxphy_hw.tcl b/library/altera/avl_adxphy/avl_adxphy_hw.tcl new file mode 100644 index 000000000..46fae17d4 --- /dev/null +++ b/library/altera/avl_adxphy/avl_adxphy_hw.tcl @@ -0,0 +1,122 @@ + +package require -exact qsys 14.0 + +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_alt.tcl + +set_module_property NAME avl_adxphy +set_module_property DESCRIPTION "Avalon ADXPHY Core" +set_module_property VERSION 1.0 +set_module_property GROUP "Analog Devices" +set_module_property DISPLAY_NAME avl_adxphy +set_module_property ELABORATION_CALLBACK p_avl_adxphy + +# files + +add_fileset quartus_synth QUARTUS_SYNTH "" "" +set_fileset_property quartus_synth TOP_LEVEL avl_adxphy +add_fileset_file avl_adxphy.v VERILOG PATH avl_adxphy.v TOP_LEVEL_FILE + +# parameters + +add_parameter TX_OR_RX_N INTEGER 0 +set_parameter_property TX_OR_RX_N DISPLAY_NAME TX_OR_RX_N +set_parameter_property TX_OR_RX_N TYPE INTEGER +set_parameter_property TX_OR_RX_N UNITS None +set_parameter_property TX_OR_RX_N HDL_PARAMETER false + +add_parameter NUM_OF_LANES INTEGER 4 +set_parameter_property NUM_OF_LANES DISPLAY_NAME NUM_OF_LANES +set_parameter_property NUM_OF_LANES TYPE INTEGER +set_parameter_property NUM_OF_LANES UNITS None +set_parameter_property NUM_OF_LANES HDL_PARAMETER true + +proc p_avl_adxphy {} { + + set m_tx_or_rx_n [get_parameter_value TX_OR_RX_N] + set m_num_of_lanes [get_parameter_value NUM_OF_LANES] + + if {$m_tx_or_rx_n == 1} { + + ad_conduit tx_core_analogreset tx_analogreset tx_core_analogreset input $m_num_of_lanes + ad_conduit tx_core_digitalreset tx_digitalreset tx_core_digitalreset input $m_num_of_lanes + ad_conduit tx_core_cal_busy tx_cal_busy tx_core_cal_busy output $m_num_of_lanes + + ad_conduit tx_ip_cal_busy tx_cal_busy tx_ip_cal_busy output $m_num_of_lanes + ad_conduit tx_ip_pcfifo_full export tx_ip_full output $m_num_of_lanes + ad_conduit tx_ip_pcfifo_empty export tx_ip_empty output $m_num_of_lanes + ad_conduit tx_ip_pcs_data export tx_ip_data input 32*$m_num_of_lanes + ad_conduit tx_ip_pcs_kchar_data export tx_ip_kchar input 4*$m_num_of_lanes + ad_conduit tx_ip_elecidle export tx_ip_elecidle input $m_num_of_lanes + ad_conduit tx_ip_csr_lane_polarity export tx_ip_lane_polarity input $m_num_of_lanes + ad_conduit tx_ip_csr_lane_powerdown export tx_ip_lane_powerdown input $m_num_of_lanes + ad_conduit tx_ip_csr_bit_reversal export rx_ip_bit_reversal input 1 + ad_conduit tx_ip_csr_byte_reversal export rx_ip_byte_reversal input 1 + + for {set n 0} {$n < $m_num_of_lanes} {incr n} { + + ad_conduit tx_ip_s_${n} export tx_ip_s_${n} input 3 + ad_conduit tx_ip_d_${n} export tx_ip_d_${n} output 39 + ad_conduit tx_phy_s_${n} export tx_phy_s_${n} output 3 + ad_conduit tx_phy_d_${n} export tx_phy_d_${n} input 39 + + ad_conduit tx_phy${n}_cal_busy tx_cal_busy tx_phy_cal_busy_${n} input 1 + ad_conduit tx_phy${n}_pcfifo_full export tx_phy_full_${n} input 1 + ad_conduit tx_phy${n}_pcfifo_empty export tx_phy_empty_${n} input 1 + ad_conduit tx_phy${n}_pcs_data export tx_phy_data_${n} output 32 + ad_conduit tx_phy${n}_pcs_kchar_data export tx_phy_kchar_${n} output 4 + ad_conduit tx_phy${n}_elecidle export tx_phy_elecidle_${n} output 1 + ad_conduit tx_phy${n}_csr_lane_polarity export tx_phy_lane_polarity_${n} output 1 + ad_conduit tx_phy${n}_csr_lane_powerdown export tx_phy_lane_powerdown_${n} output 1 + ad_conduit tx_phy${n}_csr_bit_reversal export tx_phy_bit_reversal_${n} output 1 + ad_conduit tx_phy${n}_csr_byte_reversal export tx_phy_byte_reversal_${n} output 1 + ad_conduit tx_phy${n}_analogreset tx_analogreset tx_phy_analogreset_${n} output 1 + ad_conduit tx_phy${n}_digitalreset tx_digitalreset tx_phy_digitalreset_${n} output 1 + } + } + + if {$m_tx_or_rx_n == 0} { + + ad_conduit rx_core_analogreset rx_analogreset rx_core_analogreset input $m_num_of_lanes + ad_conduit rx_core_digitalreset rx_digitalreset rx_core_digitalreset input $m_num_of_lanes + ad_conduit rx_core_is_lockedtodata rx_is_lockedtodata rx_core_locked output $m_num_of_lanes + ad_conduit rx_core_cal_busy rx_cal_busy rx_core_cal_busy output $m_num_of_lanes + + ad_conduit rx_ip_is_lockedtodata rx_is_lockedtodata rx_ip_locked output $m_num_of_lanes + ad_conduit rx_ip_cal_busy rx_cal_busy rx_ip_cal_busy output $m_num_of_lanes + ad_conduit rx_ip_pcs_data_valid export rx_ip_valid output $m_num_of_lanes + ad_conduit rx_ip_pcs_data export rx_ip_data output 32*$m_num_of_lanes + ad_conduit rx_ip_pcs_disperr export rx_ip_disperr output 4*$m_num_of_lanes + ad_conduit rx_ip_pcs_errdetect export rx_ip_deterr output 4*$m_num_of_lanes + ad_conduit rx_ip_pcs_kchar_data export rx_ip_kchar output 4*$m_num_of_lanes + ad_conduit rx_ip_pcfifo_full export rx_ip_full output $m_num_of_lanes + ad_conduit rx_ip_pcfifo_empty export rx_ip_empty output $m_num_of_lanes + ad_conduit rx_ip_patternalign_en export rx_ip_align_en input $m_num_of_lanes + ad_conduit rx_ip_csr_lane_polarity export rx_ip_lane_polarity input $m_num_of_lanes + ad_conduit rx_ip_csr_lane_powerdown export rx_ip_lane_powerdown input $m_num_of_lanes + ad_conduit rx_ip_csr_bit_reversal export rx_ip_bit_reversal input 1 + ad_conduit rx_ip_csr_byte_reversal export rx_ip_byte_reversal input 1 + + for {set n 0} {$n < $m_num_of_lanes} {incr n} { + + ad_conduit rx_phy${n}_is_lockedtodata rx_is_lockedtodata rx_phy_locked_${n} input 1 + ad_conduit rx_phy${n}_cal_busy rx_cal_busy rx_phy_cal_busy_${n} input 1 + ad_conduit rx_phy${n}_pcs_data_valid export rx_phy_valid_${n} input 1 + ad_conduit rx_phy${n}_pcs_data export rx_phy_data_${n} input 32 + ad_conduit rx_phy${n}_pcs_disperr export rx_phy_disperr_${n} input 4 + ad_conduit rx_phy${n}_pcs_errdetect export rx_phy_deterr_${n} input 4 + ad_conduit rx_phy${n}_pcs_kchar_data export rx_phy_kchar_${n} input 4 + ad_conduit rx_phy${n}_pcfifo_full export rx_phy_full_${n} input 1 + ad_conduit rx_phy${n}_pcfifo_empty export rx_phy_empty_${n} input 1 + ad_conduit rx_phy${n}_patternalign_en export rx_phy_align_en_${n} output 1 + ad_conduit rx_phy${n}_csr_lane_polarity export rx_phy_lane_polarity_${n} output 1 + ad_conduit rx_phy${n}_csr_lane_powerdown export rx_phy_lane_powerdown_${n} output 1 + ad_conduit rx_phy${n}_csr_bit_reversal export rx_phy_bit_reversal_${n} output 1 + ad_conduit rx_phy${n}_csr_byte_reversal export rx_phy_byte_reversal_${n} output 1 + ad_conduit rx_phy${n}_analogreset rx_analogreset rx_phy_analogreset_${n} output 1 + ad_conduit rx_phy${n}_digitalreset rx_digitalreset rx_phy_digitalreset_${n} output 1 + } + } +} + + diff --git a/library/altera/axi_adxcvr/axi_adxcvr.v b/library/altera/axi_adxcvr/axi_adxcvr.v new file mode 100644 index 000000000..c2d3b6ea0 --- /dev/null +++ b/library/altera/axi_adxcvr/axi_adxcvr.v @@ -0,0 +1,148 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/1ps + +module axi_adxcvr #( + + // parameters + + parameter integer ID = 0, + parameter integer TX_OR_RX_N = 0, + parameter integer NUM_OF_LANES = 4) ( + + // xcvr, lane-pll and ref-pll are shared + + output up_rst, + input up_pll_locked, + input [(NUM_OF_LANES-1):0] up_ready, + + input s_axi_aclk, + input s_axi_aresetn, + input s_axi_awvalid, + input [31:0] s_axi_awaddr, + input [ 2:0] s_axi_awprot, + output s_axi_awready, + input s_axi_wvalid, + input [31:0] s_axi_wdata, + input [ 3:0] s_axi_wstrb, + output s_axi_wready, + output s_axi_bvalid, + output [ 1:0] s_axi_bresp, + input s_axi_bready, + input s_axi_arvalid, + input [31:0] s_axi_araddr, + input [ 2:0] s_axi_arprot, + output s_axi_arready, + output s_axi_rvalid, + output [ 1:0] s_axi_rresp, + output [31:0] s_axi_rdata, + input s_axi_rready); + + // internal signals + + wire up_rstn; + wire up_clk; + wire up_wreq; + wire [ 9:0] up_waddr; + wire [31:0] up_wdata; + wire up_wack; + wire up_rreq; + wire [ 9:0] up_raddr; + wire [31:0] up_rdata; + wire up_rack; + + // clk & rst + + assign up_rstn = s_axi_aresetn; + assign up_clk = s_axi_aclk; + + // instantiations + + axi_adxcvr_up #( + .ID (ID), + .TX_OR_RX_N (TX_OR_RX_N), + .NUM_OF_LANES (NUM_OF_LANES)) + i_up ( + .up_rst (up_rst), + .up_pll_locked (up_pll_locked), + .up_ready (up_ready), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata), + .up_rack (up_rack)); + + up_axi #(.ADDRESS_WIDTH (10)) i_axi ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_axi_awvalid (s_axi_awvalid), + .up_axi_awaddr (s_axi_awaddr), + .up_axi_awready (s_axi_awready), + .up_axi_wvalid (s_axi_wvalid), + .up_axi_wdata (s_axi_wdata), + .up_axi_wstrb (s_axi_wstrb), + .up_axi_wready (s_axi_wready), + .up_axi_bvalid (s_axi_bvalid), + .up_axi_bresp (s_axi_bresp), + .up_axi_bready (s_axi_bready), + .up_axi_arvalid (s_axi_arvalid), + .up_axi_araddr (s_axi_araddr), + .up_axi_arready (s_axi_arready), + .up_axi_rvalid (s_axi_rvalid), + .up_axi_rresp (s_axi_rresp), + .up_axi_rdata (s_axi_rdata), + .up_axi_rready (s_axi_rready), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata), + .up_rack (up_rack)); + +endmodule + +// *************************************************************************** +// *************************************************************************** + diff --git a/library/altera/axi_adxcvr/axi_adxcvr_hw.tcl b/library/altera/axi_adxcvr/axi_adxcvr_hw.tcl new file mode 100644 index 000000000..cdb1834a1 --- /dev/null +++ b/library/altera/axi_adxcvr/axi_adxcvr_hw.tcl @@ -0,0 +1,99 @@ + +package require -exact qsys 14.0 + +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_alt.tcl + +set_module_property NAME axi_adxcvr +set_module_property DESCRIPTION "AXI ADXCVR Core" +set_module_property VERSION 1.0 +set_module_property GROUP "Analog Devices" +set_module_property DISPLAY_NAME axi_adxcvr +set_module_property ELABORATION_CALLBACK p_axi_adxcvr + +# files + +add_fileset quartus_synth QUARTUS_SYNTH "" "" +set_fileset_property quartus_synth TOP_LEVEL axi_adxcvr +add_fileset_file up_axi.v VERILOG PATH $ad_hdl_dir/library/common/up_axi.v +add_fileset_file axi_adxcvr_up.v VERILOG PATH axi_adxcvr_up.v +add_fileset_file axi_adxcvr.v VERILOG PATH axi_adxcvr.v TOP_LEVEL_FILE + +# parameters + +add_parameter ID INTEGER 0 +set_parameter_property ID DISPLAY_NAME ID +set_parameter_property ID TYPE INTEGER +set_parameter_property ID UNITS None +set_parameter_property ID HDL_PARAMETER true + +add_parameter TX_OR_RX_N INTEGER 0 +set_parameter_property TX_OR_RX_N DISPLAY_NAME TX_OR_RX_N +set_parameter_property TX_OR_RX_N TYPE INTEGER +set_parameter_property TX_OR_RX_N UNITS None +set_parameter_property TX_OR_RX_N HDL_PARAMETER true + +add_parameter NUM_OF_LANES INTEGER 4 +set_parameter_property NUM_OF_LANES DISPLAY_NAME NUM_OF_LANES +set_parameter_property NUM_OF_LANES TYPE INTEGER +set_parameter_property NUM_OF_LANES UNITS None +set_parameter_property NUM_OF_LANES HDL_PARAMETER true + +# axi4 slave interface + +add_interface s_axi_clock clock end +add_interface_port s_axi_clock s_axi_aclk clk Input 1 + +add_interface s_axi_reset reset end +set_interface_property s_axi_reset associatedClock s_axi_clock +add_interface_port s_axi_reset s_axi_aresetn reset_n Input 1 + +add_interface s_axi axi4lite end +set_interface_property s_axi associatedClock s_axi_clock +set_interface_property s_axi associatedReset s_axi_reset +add_interface_port s_axi s_axi_awvalid awvalid Input 1 +add_interface_port s_axi s_axi_awaddr awaddr Input 16 +add_interface_port s_axi s_axi_awprot awprot Input 3 +add_interface_port s_axi s_axi_awready awready Output 1 +add_interface_port s_axi s_axi_wvalid wvalid Input 1 +add_interface_port s_axi s_axi_wdata wdata Input 32 +add_interface_port s_axi s_axi_wstrb wstrb Input 4 +add_interface_port s_axi s_axi_wready wready Output 1 +add_interface_port s_axi s_axi_bvalid bvalid Output 1 +add_interface_port s_axi s_axi_bresp bresp Output 2 +add_interface_port s_axi s_axi_bready bready Input 1 +add_interface_port s_axi s_axi_arvalid arvalid Input 1 +add_interface_port s_axi s_axi_araddr araddr Input 16 +add_interface_port s_axi s_axi_arprot arprot Input 3 +add_interface_port s_axi s_axi_arready arready Output 1 +add_interface_port s_axi s_axi_rvalid rvalid Output 1 +add_interface_port s_axi s_axi_rresp rresp Output 2 +add_interface_port s_axi s_axi_rdata rdata Output 32 +add_interface_port s_axi s_axi_rready rready Input 1 + +# xcvr interface + +ad_alt_intf reset up_rst output 1 s_axi_clock +set_interface_property if_up_rst associatedResetSinks s_axi_reset + +add_interface core_pll_locked conduit end +add_interface_port core_pll_locked up_pll_locked export Input 1 + +# name changes + +proc p_axi_adxcvr {} { + + set m_tx_or_rx_n [get_parameter_value TX_OR_RX_N] + set m_num_of_lanes [get_parameter_value NUM_OF_LANES] + + if {$m_tx_or_rx_n == 1} { + add_interface ready conduit end + add_interface_port ready up_ready tx_ready input $m_num_of_lanes + } + + if {$m_tx_or_rx_n == 0} { + add_interface ready conduit end + add_interface_port ready up_ready rx_ready input $m_num_of_lanes + } +} + diff --git a/library/altera/axi_adxcvr/axi_adxcvr_up.v b/library/altera/axi_adxcvr/axi_adxcvr_up.v new file mode 100644 index 000000000..d09db1a5d --- /dev/null +++ b/library/altera/axi_adxcvr/axi_adxcvr_up.v @@ -0,0 +1,184 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_adxcvr_up #( + + // parameters + + parameter integer ID = 0, + parameter integer TX_OR_RX_N = 0, + parameter integer NUM_OF_LANES = 4) ( + + // xcvr, lane-pll and ref-pll are shared + + output up_rst, + input up_pll_locked, + input [(NUM_OF_LANES-1):0] up_ready, + + // bus interface + + input up_rstn, + input up_clk, + input up_wreq, + input [ 9:0] up_waddr, + input [31:0] up_wdata, + output up_wack, + input up_rreq, + input [ 9:0] up_raddr, + output [31:0] up_rdata, + output up_rack); + + // parameters + + localparam [31:0] VERSION = 32'h00100161; + + // internal registers + + reg up_wreq_d = 'd0; + reg [31:0] up_scratch = 'd0; + reg up_resetn = 'd0; + reg [ 3:0] up_rst_cnt = 'd8; + reg up_status_int = 'd0; + reg up_rreq_d = 'd0; + reg [31:0] up_rdata_d = 'd0; + + // internal signals + + wire up_ready_s; + wire [31:0] up_status_32_s; + wire [31:0] up_rparam_s; + + // defaults + + assign up_wack = up_wreq_d; + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_wreq_d <= 'd0; + up_scratch <= 'd0; + end else begin + up_wreq_d <= up_wreq; + if ((up_wreq == 1'b1) && (up_waddr == 10'h002)) begin + up_scratch <= up_wdata; + end + end + end + + // reset-controller + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_resetn <= 'd0; + end else begin + if ((up_wreq == 1'b1) && (up_waddr == 10'h004)) begin + up_resetn <= up_wdata[0]; + end + end + end + + assign up_rst = up_rst_cnt[3]; + assign up_ready_s = & up_status_32_s[NUM_OF_LANES:1]; + assign up_status_32_s[31:(NUM_OF_LANES+1)] = 'd0; + assign up_status_32_s[NUM_OF_LANES] = up_pll_locked; + assign up_status_32_s[(NUM_OF_LANES-1):0] = up_ready; + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_rst_cnt <= 4'h8; + up_status_int <= 1'b0; + end else begin + if (up_resetn == 1'b0) begin + up_rst_cnt <= 4'h8; + end else if (up_rst_cnt[3] == 1'b1) begin + up_rst_cnt <= up_rst_cnt + 1'b1; + end + if (up_resetn == 1'b0) begin + up_status_int <= 1'b0; + end else if (up_ready_s == 1'b1) begin + up_status_int <= 1'b1; + end + end + end + + // altera specific + + assign up_rparam_s[31:24] = 8'd0; + + // xilinx specific + + assign up_rparam_s[23:16] = 8'd0; + + // generic + + assign up_rparam_s[15: 9] = 7'd0; + assign up_rparam_s[ 8: 8] = (TX_OR_RX_N == 0) ? 1'b0 : 1'b1; + assign up_rparam_s[ 7: 0] = NUM_OF_LANES; + + // read interface + + assign up_rack = up_rreq_d; + assign up_rdata = up_rdata_d; + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_rreq_d <= 'd0; + up_rdata_d <= 'd0; + end else begin + up_rreq_d <= up_rreq; + if (up_rreq == 1'b1) begin + case (up_raddr) + 10'h000: up_rdata_d <= VERSION; + 10'h001: up_rdata_d <= ID; + 10'h002: up_rdata_d <= up_scratch; + 10'h004: up_rdata_d <= {31'd0, up_resetn}; + 10'h005: up_rdata_d <= {31'd0, up_status_int}; + 10'h006: up_rdata_d <= up_status_32_s; + 10'h009: up_rdata_d <= up_rparam_s; + default: up_rdata_d <= 32'd0; + endcase + end else begin + up_rdata_d <= 32'd0; + end + end + end + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/library/altera/common/ad_cmos_clk.v b/library/altera/common/ad_cmos_clk.v new file mode 100644 index 000000000..735b8fb01 --- /dev/null +++ b/library/altera/common/ad_cmos_clk.v @@ -0,0 +1,89 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2014(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module ad_cmos_clk ( + + rst, + locked, + + clk_in, + clk); + + parameter DEVICE_TYPE = 0; + + input rst; + output locked; + + input clk_in; + output clk; + + // instantiations + + generate + if (DEVICE_TYPE == 0) begin + alt_clk i_clk ( + .rst (rst), + .refclk (clk_in), + .outclk_0 (clk), + .locked (locked)); + end + endgenerate + + generate + if (DEVICE_TYPE == 1) begin + altera_pll #( + .reference_clock_frequency("250.0 MHz"), + .operation_mode("source synchronous"), + .number_of_clocks(1), + .output_clock_frequency0("0 MHz"), + .phase_shift0("0")) + i_clk ( + .rst (rst), + .refclk (clk_in), + .outclk (clk), + .fboutclk (), + .fbclk (1'b0), + .locked (locked)); + end + endgenerate + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/library/altera/common/ad_cmos_in.v b/library/altera/common/ad_cmos_in.v new file mode 100644 index 000000000..4860361ea --- /dev/null +++ b/library/altera/common/ad_cmos_in.v @@ -0,0 +1,138 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2014(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module ad_cmos_in ( + + // data interface + + rx_clk, + rx_data_in, + rx_data_p, + rx_data_n, + + // delay-data interface + + up_clk, + up_dld, + up_dwdata, + up_drdata, + + // delay-cntrl interface + + delay_clk, + delay_rst, + delay_locked); + + // parameters + + parameter SINGLE_ENDED = 0; + parameter DEVICE_TYPE = 0; + parameter IODELAY_CTRL = 0; + parameter IODELAY_GROUP = "dev_if_delay_group"; + + // data interface + + input rx_clk; + input rx_data_in; + output rx_data_p; + output rx_data_n; + + // delay-data interface + + input up_clk; + input up_dld; + input [ 4:0] up_dwdata; + output [ 4:0] up_drdata; + + // delay-cntrl interface + + input delay_clk; + input delay_rst; + output delay_locked; + + // internal registers + + reg rx_data_p = 'd0; + reg rx_data_n = 'd0; + + // internal signals + + wire rx_data_p_s; + wire rx_data_n_s; + + // defaults + + assign up_drdata = 5'd0; + assign delay_locked = 1'b1; + + // instantiations + + generate + if (DEVICE_TYPE == 0) begin + alt_ddio_in i_rx_data_iddr ( + .ck (rx_clk), + .pad_in (rx_data_in), + .dout ({rx_data_p_s, rx_data_n_s})); + end + endgenerate + + generate + if (DEVICE_TYPE == 1) begin + altddio_in #(.width (1), .lpm_hint("UNUSED")) i_rx_data_iddr ( + .inclock (rx_clk), + .datain (rx_data_in), + .dataout_h (rx_data_p_s), + .dataout_l (rx_data_n_s), + .inclocken (1'b1), + .aclr (1'b0), + .aset (1'b0), + .sclr (1'b0), + .sset (1'b0)); + end + endgenerate + + always @(posedge rx_clk) begin + rx_data_p <= rx_data_p_s; + rx_data_n <= rx_data_n_s; + end + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/library/altera/common/ad_cmos_out.v b/library/altera/common/ad_cmos_out.v new file mode 100644 index 000000000..cdec954dd --- /dev/null +++ b/library/altera/common/ad_cmos_out.v @@ -0,0 +1,101 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2014(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module __ad_cmos_out__ #( + + parameter DEVICE_TYPE = 0, + parameter SINGLE_ENDED = 0, + parameter IODELAY_ENABLE = 0, + parameter IODELAY_CTRL = 0, + parameter IODELAY_GROUP = "dev_if_delay_group") ( + + // data interface + + input tx_clk, + input tx_data_p, + input tx_data_n, + output tx_data_out, + + // delay-data interface + + input up_clk, + input up_dld, + input [ 4:0] up_dwdata, + output [ 4:0] up_drdata, + + // delay-cntrl interface + + input delay_clk, + input delay_rst, + output delay_locked); + + // local parameter + + localparam ARRIA10 = 0; + localparam CYCLONE5 = 1; + + // defaults + + assign up_drdata = 5'd0; + assign delay_locked = 1'b1; + + // instantiations + + generate + if (DEVICE_TYPE == ARRIA10) begin + __ad_cmos_out_1__ i_tx_data_oddr ( + .clk_export (tx_clk), + .din_export ({tx_data_p, tx_data_n}), + .pad_out_export (tx_data_out)); + end + endgenerate + + generate + if (DEVICE_TYPE == CYCLONE5) begin + ad_cmos_out_core_c5 i_tx_data_oddr ( + .clk (tx_clk), + .din ({tx_data_p, tx_data_n}), + .pad_out (tx_data_out)); + end + endgenerate + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/library/common/altera/ad_lvds_clk.v b/library/altera/common/ad_cmos_out_core_c5.v similarity index 84% rename from library/common/altera/ad_lvds_clk.v rename to library/altera/common/ad_cmos_out_core_c5.v index eab93e029..972362e25 100644 --- a/library/common/altera/ad_lvds_clk.v +++ b/library/altera/common/ad_cmos_out_core_c5.v @@ -34,26 +34,34 @@ // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // *************************************************************************** // *************************************************************************** -// *************************************************************************** -// *************************************************************************** -`timescale 1ns/100ps +`timescale 1ns/1ps -module ad_lvds_clk ( +module ad_cmos_out_core_c5 ( - clk_in_p, - clk_in_n, - clk); + // data interface - parameter DEVICE_TYPE = 0; - localparam SERIES7 = 0; - localparam VIRTEX6 = 1; + input clk, + input [ 1:0] din, + output pad_out); - input clk_in_p; - input clk_in_n; - output clk; - - assign clk = clk_in_p; + // instantiations + + altddio_out #( + .width (1), + .lpm_hint ("UNUSED")) + i_altddio_out ( + .outclock (clk), + .datain_h (din[1]), + .datain_l (din[0]), + .dataout (pad_out), + .outclocken (1'b1), + .oe_out (), + .oe (1'b1), + .aclr (1'b0), + .aset (1'b0), + .sclr (1'b0), + .sset (1'b0)); endmodule diff --git a/library/common/altera/ad_dcfilter_alt.v b/library/altera/common/ad_dcfilter.v old mode 100644 new mode 100755 similarity index 74% rename from library/common/altera/ad_dcfilter_alt.v rename to library/altera/common/ad_dcfilter.v index 457cbb38d..820ad731e --- a/library/common/altera/ad_dcfilter_alt.v +++ b/library/altera/common/ad_dcfilter.v @@ -1,9 +1,9 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014(c) Analog Devices, Inc. -// +// Copyright 2011(c) Analog Devices, Inc. +// // All rights reserved. -// +// // Redistribution and use in source and binary forms, with or without modification, // are permitted provided that the following conditions are met: // - Redistributions of source code must retain the above copyright @@ -34,41 +34,30 @@ // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // *************************************************************************** // *************************************************************************** -// *************************************************************************** -// *************************************************************************** // dc filter- y(n) = c*x(n) + (1-c)*y(n-1) +// NOT IMPLEMENTED `timescale 1ps/1ps -module ad_dcfilter ( +module ad_dcfilter #( + + // data path disable + + parameter DISABLE = 0) ( // data interface - clk, - valid, - data, - valid_out, - data_out, + input clk, + input valid, + input [15:0] data, + output reg valid_out, + output reg [15:0] data_out, // control interface - dcfilt_enb, - dcfilt_coeff, - dcfilt_offset); - - // data interface - - input clk; - input valid; - input [15:0] data; - output valid_out; - output [15:0] data_out; - - // control interface - - input dcfilt_enb; - input [15:0] dcfilt_coeff; - input [15:0] dcfilt_offset; + input dcfilt_enb, + input [15:0] dcfilt_coeff, + input [15:0] dcfilt_offset); // internal registers @@ -76,28 +65,20 @@ module ad_dcfilter ( reg [15:0] data_d = 'd0; reg valid_2d = 'd0; reg [15:0] data_2d = 'd0; - reg valid_out = 'd0; - reg [15:0] data_out = 'd0; + // internal signals - - // cancelling the dc offset + wire [47:0] dc_offset_s; always @(posedge clk) begin - dc_offset <= 16'h0; valid_d <= valid; if (valid == 1'b1) begin data_d <= data + dcfilt_offset; end valid_2d <= valid_d; - data_2d <= data_d - dc_offset; - if (dcfilt_enb == 1'b1) begin - valid_out <= valid_2d; - data_out <= data_d; // DC filter not implemented in this version - end else begin - valid_out <= valid_d; - data_out <= data_d; - end + data_2d <= data_d; + valid_out <= valid_2d; + data_out <= data_2d; end endmodule diff --git a/library/altera/common/ad_lvds_clk.v b/library/altera/common/ad_lvds_clk.v new file mode 100644 index 000000000..983a94723 --- /dev/null +++ b/library/altera/common/ad_lvds_clk.v @@ -0,0 +1,89 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2014(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module ad_lvds_clk ( + + rst, + locked, + + clk_in_p, + clk_in_n, + clk); + + parameter DEVICE_TYPE = 0; + + input rst; + output locked; + + input clk_in_p; + input clk_in_n; + output clk; + + // instantiations + + generate + if (DEVICE_TYPE == 0) begin + alt_clk i_clk ( + .rst (rst), + .refclk (clk_in_p), + .outclk_0 (clk), + .locked (locked)); + end + endgenerate + + generate + if (DEVICE_TYPE == 1) begin + altera_pll #( + .reference_clock_frequency("250.0 MHz"), + .operation_mode("lvds"), + .number_of_clocks(1), + .output_clock_frequency0("250.0 MHz"), + .phase_shift0("0")) + i_clk ( + .rst (rst), + .refclk (clk_in_p), + .outclk (clk), + .locked (locked)); + end + endgenerate + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/library/common/altera/ad_lvds_in.v b/library/altera/common/ad_lvds_in.v similarity index 76% rename from library/common/altera/ad_lvds_in.v rename to library/altera/common/ad_lvds_in.v index 7ab54045e..91774bdf1 100644 --- a/library/common/altera/ad_lvds_in.v +++ b/library/altera/common/ad_lvds_in.v @@ -34,8 +34,6 @@ // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // *************************************************************************** // *************************************************************************** -// *************************************************************************** -// *************************************************************************** `timescale 1ns/100ps @@ -49,22 +47,25 @@ module ad_lvds_in ( rx_data_p, rx_data_n, - // delay interface + // delay-data interface + + up_clk, + up_dld, + up_dwdata, + up_drdata, + + // delay-cntrl interface delay_clk, delay_rst, - delay_ld, - delay_wdata, - delay_rdata, delay_locked); // parameters + parameter SINGLE_ENDED = 0; parameter DEVICE_TYPE = 0; parameter IODELAY_CTRL = 0; parameter IODELAY_GROUP = "dev_if_delay_group"; - localparam SERIES7 = 0; - localparam VIRTEX6 = 1; // data interface @@ -74,38 +75,64 @@ module ad_lvds_in ( output rx_data_p; output rx_data_n; - // delay interface + // delay-data interface + + input up_clk; + input up_dld; + input [ 4:0] up_dwdata; + output [ 4:0] up_drdata; + + // delay-cntrl interface input delay_clk; input delay_rst; - input delay_ld; - input [ 4:0] delay_wdata; - output [ 4:0] delay_rdata; output delay_locked; + // internal registers + + reg rx_data_p = 'd0; + reg rx_data_n = 'd0; + + // internal signals + + wire rx_data_p_s; + wire rx_data_n_s; + // defaults - assign delay_rdata = 5'd0; + assign up_drdata = 5'd0; assign delay_locked = 1'b1; // instantiations - altddio_in #( - .invert_input_clocks("OFF"), - .lpm_hint("UNUSED"), - .lpm_type("altddio_in"), - .power_up_high("OFF"), - .width(1)) - i_rx_data_iddr ( + generate + if (DEVICE_TYPE == 0) begin + alt_ddio_in i_rx_data_iddr ( + .ck (rx_clk), + .pad_in (rx_data_in_p), + .dout ({rx_data_p_s, rx_data_n_s})); + end + endgenerate + + generate + if (DEVICE_TYPE == 1) begin + altddio_in #(.width (1), .lpm_hint("UNUSED")) i_rx_data_iddr ( + .inclock (rx_clk), + .datain (rx_data_in_p), + .dataout_h (rx_data_p_s), + .dataout_l (rx_data_n_s), + .inclocken (1'b1), .aclr (1'b0), .aset (1'b0), .sclr (1'b0), - .sset (1'b0), - .inclocken (1'b1), - .inclock (rx_clk), - .datain (rx_data_in_p), - .dataout_h (rx_data_p), - .dataout_l (rx_data_n)); + .sset (1'b0)); + end + endgenerate + + always @(posedge rx_clk) begin + rx_data_p <= rx_data_p_s; + rx_data_n <= rx_data_n_s; + end endmodule diff --git a/library/common/altera/ad_lvds_out.v b/library/altera/common/ad_lvds_out.v similarity index 75% rename from library/common/altera/ad_lvds_out.v rename to library/altera/common/ad_lvds_out.v index edc756114..9f8bf8cec 100644 --- a/library/common/altera/ad_lvds_out.v +++ b/library/altera/common/ad_lvds_out.v @@ -34,8 +34,6 @@ // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // *************************************************************************** // *************************************************************************** -// *************************************************************************** -// *************************************************************************** `timescale 1ns/100ps @@ -47,13 +45,28 @@ module ad_lvds_out ( tx_data_p, tx_data_n, tx_data_out_p, - tx_data_out_n); + tx_data_out_n, + + // delay-data interface + + up_clk, + up_dld, + up_dwdata, + up_drdata, + + // delay-cntrl interface + + delay_clk, + delay_rst, + delay_locked); // parameters parameter DEVICE_TYPE = 0; - localparam SERIES7 = 0; - localparam VIRTEX6 = 1; + parameter SINGLE_ENDED = 0; + parameter IODELAY_ENABLE = 0; + parameter IODELAY_CTRL = 0; + parameter IODELAY_GROUP = "dev_if_delay_group"; // data interface @@ -63,33 +76,51 @@ module ad_lvds_out ( output tx_data_out_p; output tx_data_out_n; + // delay-data interface + + input up_clk; + input up_dld; + input [ 4:0] up_dwdata; + output [ 4:0] up_drdata; + + // delay-cntrl interface + + input delay_clk; + input delay_rst; + output delay_locked; + // defaults - assign tx_data_out_n = 1'd0; + assign up_drdata = 5'd0; + assign delay_locked = 1'b1; // instantiations - altddio_out #( - .extend_oe_disable("OFF"), - .intended_device_family("Cyclone V"), - .invert_output("OFF"), - .lpm_hint("UNUSED"), - .lpm_type("altddio_out"), - .oe_reg("UNREGISTERED"), - .power_up_high("OFF"), - .width(1)) - i_tx_data_oddr ( - .aclr (1'b0), - .aset (1'b0), - .sclr (1'b0), - .sset (1'b0), - .oe (1'b1), - .oe_out (), - .outclocken (1'b1), + generate + if (DEVICE_TYPE == 0) begin + alt_ddio_out i_tx_data_oddr ( + .ck (tx_clk), + .din ({tx_data_p, tx_data_n}), + .pad_out (tx_data_out_p)); + end + endgenerate + + generate + if (DEVICE_TYPE == 1) begin + altddio_out #(.width (1), .lpm_hint ("UNUSED")) i_tx_data_oddr ( .outclock (tx_clk), .datain_h (tx_data_p), .datain_l (tx_data_n), - .dataout (tx_data_out_p)); + .dataout (tx_data_out_p), + .outclocken (1'b1), + .oe_out (), + .oe (1'b1), + .aclr (1'b0), + .aset (1'b0), + .sclr (1'b0), + .sset (1'b0)); + end + endgenerate endmodule diff --git a/library/common/ad_mul_u16.v b/library/altera/common/ad_mul.v similarity index 78% rename from library/common/ad_mul_u16.v rename to library/altera/common/ad_mul.v index eb4978dfb..896f9f185 100644 --- a/library/common/ad_mul_u16.v +++ b/library/altera/common/ad_mul.v @@ -1,9 +1,9 @@ // *************************************************************************** // *************************************************************************** // Copyright 2011(c) Analog Devices, Inc. -// +// // All rights reserved. -// +// // Redistribution and use in source and binary forms, with or without modification, // are permitted provided that the following conditions are met: // - Redistributions of source code must retain the above copyright @@ -21,27 +21,25 @@ // patent holders to use this software. // - Use of the software either in source or binary form, must be run // on or directly connected to an Analog Devices Inc. component. -// +// // THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, // INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A // PARTICULAR PURPOSE ARE DISCLAIMED. // // IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, // EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY -// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR // BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // *************************************************************************** // *************************************************************************** // *************************************************************************** // *************************************************************************** -// both inputs are considered unsigned 16 bits- -// ddata is delay matched generic data `timescale 1ps/1ps -module ad_mul_u16 ( +module ad_mul ( // data_p = data_a * data_b; @@ -58,29 +56,24 @@ module ad_mul_u16 ( // delayed data bus width parameter DELAY_DATA_WIDTH = 16; - localparam DW = DELAY_DATA_WIDTH - 1; // data_p = data_a * data_b; - input clk; - input [15:0] data_a; - input [15:0] data_b; - output [31:0] data_p; + input clk; + input [16:0] data_a; + input [16:0] data_b; + output [33:0] data_p; // delay interface - input [DW:0] ddata_in; - output [DW:0] ddata_out; + input [(DELAY_DATA_WIDTH-1):0] ddata_in; + output [(DELAY_DATA_WIDTH-1):0] ddata_out; // internal registers - reg [DW:0] p1_ddata = 'd0; - reg [DW:0] p2_ddata = 'd0; - reg [DW:0] ddata_out = 'd0; - - // internal signals - - wire [33:0] data_p_s; + reg [(DELAY_DATA_WIDTH-1):0] p1_ddata = 'd0; + reg [(DELAY_DATA_WIDTH-1):0] p2_ddata = 'd0; + reg [(DELAY_DATA_WIDTH-1):0] ddata_out = 'd0; // a/b reg, m-reg, p-reg delay match @@ -90,19 +83,21 @@ module ad_mul_u16 ( ddata_out <= p2_ddata; end - assign data_p = data_p_s[31:0]; - - MULT_MACRO #( - .LATENCY (3), - .A_DATA_WIDTH (17), - .B_DATA_WIDTH (17)) - i_mult_macro ( - .CE (1'b1), - .RST (1'b0), - .CLK (clk), - .A ({1'b0, data_a}), - .B ({1'b0, data_b}), - .P (data_p_s)); + lpm_mult #( + .lpm_type ("lpm_mult"), + .lpm_widtha (17), + .lpm_widthb (17), + .lpm_widthp (34), + .lpm_representation ("SIGNED"), + .lpm_pipeline (3)) + i_lpm_mult ( + .clken (1'b1), + .aclr (1'b0), + .sum (1'b0), + .clock (clk), + .dataa (data_a), + .datab (data_b), + .result (data_p)); endmodule diff --git a/library/altera/common/ad_serdes_clk.v b/library/altera/common/ad_serdes_clk.v new file mode 100644 index 000000000..e708404f2 --- /dev/null +++ b/library/altera/common/ad_serdes_clk.v @@ -0,0 +1,211 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +`timescale 1ps/1ps + +module __ad_serdes_clk__ #( + + // parameters + + parameter DEVICE_TYPE = 0, + parameter DDR_OR_SDR_N = 1, + parameter SERDES_FACTOR = 8, + parameter MMCM_OR_BUFR_N = 1, + parameter MMCM_CLKIN_PERIOD = 1.667, + parameter MMCM_VCO_DIV = 6, + parameter MMCM_VCO_MUL = 12.000, + parameter MMCM_CLK0_DIV = 2.000, + parameter MMCM_CLK1_DIV = 6) ( + + // clock and divided clock + + input rst, + input clk_in_p, + input clk_in_n, + output clk, + output div_clk, + output out_clk, + output loaden, + output [ 7:0] phase, + + // drp interface + + input up_clk, + input up_rstn, + input up_drp_sel, + input up_drp_wr, + input [11:0] up_drp_addr, + input [31:0] up_drp_wdata, + output [31:0] up_drp_rdata, + output up_drp_ready, + output up_drp_locked); + + // local parameter + + localparam ARRIA10 = 0; + localparam CYCLONE5 = 1; + + // internal registers + + reg up_drp_sel_int = 'd0; + reg up_drp_rd_int = 'd0; + reg up_drp_wr_int = 'd0; + reg [ 8:0] up_drp_addr_int = 'd0; + reg [31:0] up_drp_wdata_int = 'd0; + reg [31:0] up_drp_rdata_int = 'd0; + reg up_drp_ready_int = 'd0; + reg up_drp_locked_int_m = 'd0; + reg up_drp_locked_int = 'd0; + + // internal signals + + wire up_drp_reset; + wire [31:0] up_drp_rdata_int_s; + wire up_drp_busy_int_s; + wire up_drp_locked_int_s; + wire loaden_s; + wire clk_s; + + // defaults + + assign up_drp_reset = ~up_rstn; + assign out_clk = div_clk; + assign up_drp_rdata = up_drp_rdata_int; + assign up_drp_ready = up_drp_ready_int; + assign up_drp_locked = up_drp_locked_int; + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 1'b0) begin + up_drp_sel_int <= 1'b0; + up_drp_rd_int <= 1'b0; + up_drp_wr_int <= 1'b0; + up_drp_addr_int <= 9'd0; + up_drp_wdata_int <= 32'd0; + up_drp_rdata_int <= 32'd0; + up_drp_ready_int <= 1'b0; + up_drp_locked_int_m <= 1'd0; + up_drp_locked_int <= 1'd0; + end else begin + if (up_drp_sel_int == 1'b1) begin + if (up_drp_busy_int_s == 1'b0) begin + up_drp_sel_int <= 1'b0; + up_drp_rd_int <= 1'b0; + up_drp_wr_int <= 1'b0; + up_drp_addr_int <= 9'd0; + up_drp_wdata_int <= 32'd0; + up_drp_rdata_int <= up_drp_rdata_int_s; + up_drp_ready_int <= 1'b1; + end + end else if (up_drp_sel == 1'b1) begin + up_drp_sel_int <= 1'b1; + up_drp_rd_int <= ~up_drp_wr; + up_drp_wr_int <= up_drp_wr; + up_drp_addr_int <= up_drp_addr[8:0]; + up_drp_wdata_int <= up_drp_wdata; + up_drp_rdata_int <= 32'd0; + up_drp_ready_int <= 1'b0; + end else begin + up_drp_sel_int <= 1'b0; + up_drp_rd_int <= 1'b0; + up_drp_wr_int <= 1'b0; + up_drp_addr_int <= 9'd0; + up_drp_wdata_int <= 32'd0; + up_drp_rdata_int <= 32'd0; + up_drp_ready_int <= 1'b0; + end + up_drp_locked_int_m <= up_drp_locked_int_s; + up_drp_locked_int <= up_drp_locked_int_m; + end + end + + generate + if (DEVICE_TYPE == ARRIA10) begin + __ad_serdes_clk_1__ i_core ( + .rst_reset (rst), + .ref_clk_clk (clk_in_p), + .locked_export (up_drp_locked_int_s), + .hs_phase_phout (phase), + .hs_clk_lvds_clk (clk), + .loaden_loaden (loaden), + .ls_clk_clk (div_clk), + .drp_clk_clk (up_clk), + .drp_rst_reset (up_drp_reset), + .pll_reconfig_waitrequest (up_drp_busy_int_s), + .pll_reconfig_read (up_drp_rd_int), + .pll_reconfig_write (up_drp_wr_int), + .pll_reconfig_readdata (up_drp_rdata_int_s), + .pll_reconfig_address (up_drp_addr_int), + .pll_reconfig_writedata (up_drp_wdata_int)); + end + endgenerate + + generate + if (DEVICE_TYPE == CYCLONE5) begin + + assign phase = 8'd0; + + __ad_serdes_clk_1__ i_core ( + .rst_reset (rst), + .ref_clk_clk (clk_in_p), + .locked_export (up_drp_locked_int_s), + .hs_clk_clk (clk_s), + .loaden_clk (loaden_s), + .ls_clk_clk (div_clk), + .drp_clk_clk (up_clk), + .drp_rst_reset (up_drp_reset), + .pll_reconfig_waitrequest (up_drp_busy_int_s), + .pll_reconfig_read (up_drp_rd_int), + .pll_reconfig_write (up_drp_wr_int), + .pll_reconfig_readdata (up_drp_rdata_int_s), + .pll_reconfig_address (up_drp_addr_int[5:0]), + .pll_reconfig_writedata (up_drp_wdata_int)); + + cyclonev_pll_lvds_output #( + .pll_loaden_enable_disable ("true"), + .pll_lvdsclk_enable_disable ("true")) + i_clk_buf ( + .ccout ({loaden_s, clk_s}), + .loaden (loaden), + .lvdsclk (clk)); + + end + endgenerate + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/library/altera/common/ad_serdes_in.v b/library/altera/common/ad_serdes_in.v new file mode 100644 index 000000000..9b147d698 --- /dev/null +++ b/library/altera/common/ad_serdes_in.v @@ -0,0 +1,170 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR +// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR +// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE +// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +`timescale 1ps/1ps + +module __ad_serdes_in__ #( + + // parameters + + parameter DEVICE_TYPE = 0, + parameter DDR_OR_SDR_N = 0, + parameter SERDES_FACTOR = 8, + parameter DATA_WIDTH = 16, + parameter IODELAY_CTRL = 0, + parameter IODELAY_GROUP = "dev_if_delay_group") ( + + // reset and clocks + + input rst, + input clk, + input div_clk, + input loaden, + input [ 7:0] phase, + input locked, + + // data interface + + output [(DATA_WIDTH-1):0] data_s0, + output [(DATA_WIDTH-1):0] data_s1, + output [(DATA_WIDTH-1):0] data_s2, + output [(DATA_WIDTH-1):0] data_s3, + output [(DATA_WIDTH-1):0] data_s4, + output [(DATA_WIDTH-1):0] data_s5, + output [(DATA_WIDTH-1):0] data_s6, + output [(DATA_WIDTH-1):0] data_s7, + input [(DATA_WIDTH-1):0] data_in_p, + input [(DATA_WIDTH-1):0] data_in_n, + + // delay-data interface + + input up_clk, + input [(DATA_WIDTH-1):0] up_dld, + input [((DATA_WIDTH*5)-1):0] up_dwdata, + output [((DATA_WIDTH*5)-1):0] up_drdata, + + // delay-control interface + + input delay_clk, + input delay_rst, + output delay_locked); + + // local parameter + + localparam ARRIA10 = 0; + localparam CYCLONE5 = 1; + + // internal signals + + wire [(DATA_WIDTH-1):0] delay_locked_s; + wire [(DATA_WIDTH-1):0] data_samples_s[0:(SERDES_FACTOR-1)]; + wire [(SERDES_FACTOR-1):0] data_out_s[0:(DATA_WIDTH-1)]; + + // assignments + + assign up_drdata = 5'd0; + assign delay_locked = & delay_locked_s; + + // instantiations + + genvar n; + genvar i; + + generate + if (SERDES_FACTOR == 8) begin + assign data_s7 = data_samples_s[7]; + assign data_s6 = data_samples_s[6]; + assign data_s5 = data_samples_s[5]; + assign data_s4 = data_samples_s[4]; + end else begin + assign data_s7 = 'd0; + assign data_s6 = 'd0; + assign data_s5 = 'd0; + assign data_s4 = 'd0; + end + endgenerate + + assign data_s3 = data_samples_s[3]; + assign data_s2 = data_samples_s[2]; + assign data_s1 = data_samples_s[1]; + assign data_s0 = data_samples_s[0]; + + generate + for (i = 0; i < SERDES_FACTOR; i = i + 1) begin: g_samples + for (n = 0; n < DATA_WIDTH; n = n + 1) begin: g_swap + assign data_samples_s[i][n] = data_out_s[n][((SERDES_FACTOR-1)-i)]; + end + end + endgenerate + + generate + for (n = 0; n < DATA_WIDTH; n = n + 1) begin: g_data + + if (DEVICE_TYPE == CYCLONE5) begin + + assign delay_locked_s[n] = 1'b1; + + ad_serdes_in_core_c5 #( + .SERDES_FACTOR (SERDES_FACTOR)) + i_core ( + .clk (clk), + .div_clk (div_clk), + .enable (loaden), + .data_in (data_in_p[n]), + .data (data_out_s[n])); + end + + if (DEVICE_TYPE == ARRIA10) begin + __ad_serdes_in_1__ i_core ( + .clk_export (clk), + .div_clk_export (div_clk), + .hs_phase_export (phase), + .loaden_export (loaden), + .locked_export (locked), + .data_in_export (data_in_p[n]), + .data_s_export (data_out_s[n]), + .delay_locked_export (delay_locked_s[n])); + end + + end + endgenerate + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/library/altera/common/ad_serdes_in_core_c5.v b/library/altera/common/ad_serdes_in_core_c5.v new file mode 100644 index 000000000..05e34b8eb --- /dev/null +++ b/library/altera/common/ad_serdes_in_core_c5.v @@ -0,0 +1,146 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +`timescale 1ps/1ps + +module ad_serdes_in_core_c5 #( + + parameter SERDES_FACTOR = 8) ( + + input clk, + input div_clk, + input enable, + input data_in, + output [(SERDES_FACTOR-1):0] data); + + reg [(SERDES_FACTOR-1):0] data_int = 'd0; + wire [(SERDES_FACTOR-1):0] data_s; + + assign data = data_int; + + always @(posedge div_clk) begin + data_int <= data_s; + end + + altlvds_rx i_altlvds_rx ( + .rx_enable (enable), + .rx_in (data_in), + .rx_inclock (clk), + .rx_out (data_s), + .dpa_pll_cal_busy (), + .dpa_pll_recal (1'b0), + .pll_areset (1'b0), + .pll_phasecounterselect (), + .pll_phasedone (1'b1), + .pll_phasestep (), + .pll_phaseupdown (), + .pll_scanclk (), + .rx_cda_max (), + .rx_cda_reset (1'b0), + .rx_channel_data_align (1'b0), + .rx_coreclk (1'b1), + .rx_data_align (1'b0), + .rx_data_align_reset (1'b0), + .rx_data_reset (1'b0), + .rx_deskew (1'b0), + .rx_divfwdclk (), + .rx_dpa_lock_reset (1'b0), + .rx_dpa_locked (), + .rx_dpaclock (1'b0), + .rx_dpll_enable (1'b1), + .rx_dpll_hold (1'b0), + .rx_dpll_reset (1'b0), + .rx_fifo_reset (1'b0), + .rx_locked (), + .rx_outclock (), + .rx_pll_enable (1'b1), + .rx_readclock (1'b0), + .rx_reset (1'b0), + .rx_syncclock (1'b0)); + defparam + i_altlvds_rx.buffer_implementation = "RAM", + i_altlvds_rx.cds_mode = "UNUSED", + i_altlvds_rx.common_rx_tx_pll = "OFF", + i_altlvds_rx.data_align_rollover = 4, + i_altlvds_rx.data_rate = "800.0 Mbps", + i_altlvds_rx.deserialization_factor = SERDES_FACTOR, + i_altlvds_rx.dpa_initial_phase_value = 0, + i_altlvds_rx.dpll_lock_count = 0, + i_altlvds_rx.dpll_lock_window = 0, + i_altlvds_rx.enable_clock_pin_mode = "UNUSED", + i_altlvds_rx.enable_dpa_align_to_rising_edge_only = "OFF", + i_altlvds_rx.enable_dpa_calibration = "ON", + i_altlvds_rx.enable_dpa_fifo = "UNUSED", + i_altlvds_rx.enable_dpa_initial_phase_selection = "OFF", + i_altlvds_rx.enable_dpa_mode = "OFF", + i_altlvds_rx.enable_dpa_pll_calibration = "OFF", + i_altlvds_rx.enable_soft_cdr_mode = "OFF", + i_altlvds_rx.implement_in_les = "OFF", + i_altlvds_rx.inclock_boost = 0, + i_altlvds_rx.inclock_data_alignment = "EDGE_ALIGNED", + i_altlvds_rx.inclock_period = 50000, + i_altlvds_rx.inclock_phase_shift = 0, + i_altlvds_rx.input_data_rate = 800, + i_altlvds_rx.intended_device_family = "Cyclone V", + i_altlvds_rx.lose_lock_on_one_change = "UNUSED", + i_altlvds_rx.lpm_hint = "CBX_MODULE_PREFIX=ad_serdes_in_core_c5", + i_altlvds_rx.lpm_type = "altlvds_rx", + i_altlvds_rx.number_of_channels = 1, + i_altlvds_rx.outclock_resource = "Dual-Regional clock", + i_altlvds_rx.pll_operation_mode = "NORMAL", + i_altlvds_rx.pll_self_reset_on_loss_lock = "UNUSED", + i_altlvds_rx.port_rx_channel_data_align = "PORT_UNUSED", + i_altlvds_rx.port_rx_data_align = "PORT_UNUSED", + i_altlvds_rx.refclk_frequency = "20.000000 MHz", + i_altlvds_rx.registered_data_align_input = "UNUSED", + i_altlvds_rx.registered_output = "OFF", + i_altlvds_rx.reset_fifo_at_first_lock = "UNUSED", + i_altlvds_rx.rx_align_data_reg = "RISING_EDGE", + i_altlvds_rx.sim_dpa_is_negative_ppm_drift = "OFF", + i_altlvds_rx.sim_dpa_net_ppm_variation = 0, + i_altlvds_rx.sim_dpa_output_clock_phase_shift = 0, + i_altlvds_rx.use_coreclock_input = "OFF", + i_altlvds_rx.use_dpll_rawperror = "OFF", + i_altlvds_rx.use_external_pll = "ON", + i_altlvds_rx.use_no_phase_shift = "ON", + i_altlvds_rx.x_on_bitslip = "ON", + i_altlvds_rx.clk_src_is_pll = "off"; + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/library/altera/common/ad_serdes_out.v b/library/altera/common/ad_serdes_out.v new file mode 100644 index 000000000..8bca8ffd5 --- /dev/null +++ b/library/altera/common/ad_serdes_out.v @@ -0,0 +1,138 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +`timescale 1ps/1ps + +module __ad_serdes_out__ #( + + parameter DEVICE_TYPE = 0, + parameter DDR_OR_SDR_N = 1, + parameter SERDES_FACTOR = 8, + parameter DATA_WIDTH = 16) ( + + // reset and clocks + + input rst, + input clk, + input div_clk, + input loaden, + + // data interface + + input [(DATA_WIDTH-1):0] data_s0, + input [(DATA_WIDTH-1):0] data_s1, + input [(DATA_WIDTH-1):0] data_s2, + input [(DATA_WIDTH-1):0] data_s3, + input [(DATA_WIDTH-1):0] data_s4, + input [(DATA_WIDTH-1):0] data_s5, + input [(DATA_WIDTH-1):0] data_s6, + input [(DATA_WIDTH-1):0] data_s7, + output [(DATA_WIDTH-1):0] data_out_p, + output [(DATA_WIDTH-1):0] data_out_n); + + // local parameter + + localparam ARRIA10 = 0; + localparam CYCLONE5 = 1; + + // internal signals + + wire [(DATA_WIDTH-1):0] data_samples_s[0:(SERDES_FACTOR-1)]; + wire [(SERDES_FACTOR-1):0] data_in_s[0:(DATA_WIDTH-1)]; + + // defaults + + assign data_out_n = 'd0; + + // instantiations + + genvar n; + genvar i; + + generate + if (SERDES_FACTOR == 8) begin + assign data_samples_s[7] = data_s7; + assign data_samples_s[6] = data_s6; + assign data_samples_s[5] = data_s5; + assign data_samples_s[4] = data_s4; + end + endgenerate + + assign data_samples_s[3] = data_s3; + assign data_samples_s[2] = data_s2; + assign data_samples_s[1] = data_s1; + assign data_samples_s[0] = data_s0; + + generate + for (n = 0; n < DATA_WIDTH; n = n + 1) begin: g_swap + for (i = 0; i < SERDES_FACTOR; i = i + 1) begin: g_samples + assign data_in_s[n][((SERDES_FACTOR-1)-i)] = data_samples_s[i][n]; + end + end + endgenerate + + generate + for (n = 0; n < DATA_WIDTH; n = n + 1) begin: g_data + + if (DEVICE_TYPE == CYCLONE5) begin + ad_serdes_out_core_c5 #( + .SERDES_FACTOR (SERDES_FACTOR)) + i_core ( + .clk (clk), + .div_clk (div_clk), + .enable (loaden), + .data_out (data_out_p[n]), + .data (data_in_s[n])); + end + + if (DEVICE_TYPE == ARRIA10) begin + __ad_serdes_out_1__ i_core ( + .clk_export (clk), + .div_clk_export (div_clk), + .loaden_export (loaden), + .data_out_export (data_out_p[n]), + .data_s_export (data_in_s[n])); + end + + end + endgenerate + +endmodule + +// *************************************************************************** +// *************************************************************************** + diff --git a/library/altera/common/ad_serdes_out_core_c5.v b/library/altera/common/ad_serdes_out_core_c5.v new file mode 100644 index 000000000..07d627fe6 --- /dev/null +++ b/library/altera/common/ad_serdes_out_core_c5.v @@ -0,0 +1,107 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +`timescale 1ps/1ps + +module ad_serdes_out_core_c5 #( + + parameter SERDES_FACTOR = 8) ( + + input clk, + input div_clk, + input enable, + output data_out, + input [(SERDES_FACTOR-1):0] data); + + reg [(SERDES_FACTOR-1):0] data_int = 'd0; + + always @(posedge div_clk) begin + data_int <= data; + end + + altlvds_tx i_altlvds_tx ( + .tx_enable (enable), + .tx_in (data), + .tx_inclock (clk), + .tx_out (data_out), + .pll_areset (1'b0), + .sync_inclock (1'b0), + .tx_coreclock (), + .tx_data_reset (1'b0), + .tx_locked (), + .tx_outclock (), + .tx_pll_enable (1'b1), + .tx_syncclock (1'b0)); + defparam + i_altlvds_tx.center_align_msb = "UNUSED", + i_altlvds_tx.common_rx_tx_pll = "OFF", + i_altlvds_tx.coreclock_divide_by = 1, + i_altlvds_tx.data_rate = "800.0 Mbps", + i_altlvds_tx.deserialization_factor = SERDES_FACTOR, + i_altlvds_tx.differential_drive = 0, + i_altlvds_tx.enable_clock_pin_mode = "UNUSED", + i_altlvds_tx.implement_in_les = "OFF", + i_altlvds_tx.inclock_boost = 0, + i_altlvds_tx.inclock_data_alignment = "EDGE_ALIGNED", + i_altlvds_tx.inclock_period = 50000, + i_altlvds_tx.inclock_phase_shift = 0, + i_altlvds_tx.intended_device_family = "Cyclone V", + i_altlvds_tx.lpm_hint = "CBX_MODULE_PREFIX=ad_serdes_out_core_c5", + i_altlvds_tx.lpm_type = "altlvds_tx", + i_altlvds_tx.multi_clock = "OFF", + i_altlvds_tx.number_of_channels = 1, + i_altlvds_tx.outclock_alignment = "EDGE_ALIGNED", + i_altlvds_tx.outclock_divide_by = 1, + i_altlvds_tx.outclock_duty_cycle = 50, + i_altlvds_tx.outclock_multiply_by = 1, + i_altlvds_tx.outclock_phase_shift = 0, + i_altlvds_tx.outclock_resource = "Dual-Regional clock", + i_altlvds_tx.output_data_rate = 800, + i_altlvds_tx.pll_compensation_mode = "AUTO", + i_altlvds_tx.pll_self_reset_on_loss_lock = "OFF", + i_altlvds_tx.preemphasis_setting = 0, + i_altlvds_tx.refclk_frequency = "20.000000 MHz", + i_altlvds_tx.registered_input = "OFF", + i_altlvds_tx.use_external_pll = "ON", + i_altlvds_tx.use_no_phase_shift = "ON", + i_altlvds_tx.vod_setting = 0, + i_altlvds_tx.clk_src_is_pll = "off"; + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/library/axi_ad6676/Makefile b/library/axi_ad6676/Makefile index 126ec4e10..596eed550 100644 --- a/library/axi_ad6676/Makefile +++ b/library/axi_ad6676/Makefile @@ -5,23 +5,24 @@ #################################################################################### #################################################################################### -M_DEPS := axi_ad6676_ip.tcl -M_DEPS += ../scripts/adi_env.tcl -M_DEPS += ../scripts/adi_ip.tcl -M_DEPS += ../common/ad_rst.v +M_DEPS += ../common/ad_axi_ip_constr.xdc M_DEPS += ../common/ad_pnmon.v +M_DEPS += ../common/ad_rst.v +M_DEPS += ../common/ad_xcvr_rx_if.v +M_DEPS += ../common/up_adc_channel.v +M_DEPS += ../common/up_adc_common.v M_DEPS += ../common/up_axi.v +M_DEPS += ../common/up_clock_mon.v M_DEPS += ../common/up_xfer_cntrl.v M_DEPS += ../common/up_xfer_status.v -M_DEPS += ../common/up_clock_mon.v -M_DEPS += ../common/up_adc_common.v -M_DEPS += ../common/up_adc_channel.v -M_DEPS += ../common/ad_axi_ip_constr.xdc -M_DEPS += axi_ad6676_pnmon.v -M_DEPS += axi_ad6676_channel.v -M_DEPS += axi_ad6676_if.v -M_DEPS += axi_ad6676_constr.xdc +M_DEPS += ../scripts/adi_env.tcl +M_DEPS += ../scripts/adi_ip.tcl M_DEPS += axi_ad6676.v +M_DEPS += axi_ad6676_channel.v +M_DEPS += axi_ad6676_constr.xdc +M_DEPS += axi_ad6676_if.v +M_DEPS += axi_ad6676_ip.tcl +M_DEPS += axi_ad6676_pnmon.v M_VIVADO := vivado -mode batch -source @@ -32,6 +33,10 @@ M_FLIST += *.log M_FLIST += component.xml M_FLIST += *.jou M_FLIST += xgui +M_FLIST += *.ip_user_files +M_FLIST += *.srcs +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil @@ -48,7 +53,7 @@ clean-all: axi_ad6676.xpr: $(M_DEPS) - rm -rf $(M_FLIST) + -rm -rf $(M_FLIST) $(M_VIVADO) axi_ad6676_ip.tcl >> axi_ad6676_ip.log 2>&1 #################################################################################### diff --git a/library/axi_ad6676/axi_ad6676.v b/library/axi_ad6676/axi_ad6676.v index a55b8039d..4de586635 100755 --- a/library/axi_ad6676/axi_ad6676.v +++ b/library/axi_ad6676/axi_ad6676.v @@ -45,18 +45,21 @@ module axi_ad6676 ( // rx_clk is (line-rate/40) rx_clk, + rx_sof, + rx_valid, + rx_ready, rx_data, // dma interface adc_clk, adc_rst, - adc_valid_a, - adc_enable_a, - adc_data_a, - adc_valid_b, - adc_enable_b, - adc_data_b, + adc_valid_0, + adc_enable_0, + adc_data_0, + adc_valid_1, + adc_enable_1, + adc_data_1, adc_dovf, adc_dunf, @@ -80,7 +83,9 @@ module axi_ad6676 ( s_axi_rvalid, s_axi_rresp, s_axi_rdata, - s_axi_rready); + s_axi_rready, + s_axi_awprot, + s_axi_arprot); parameter ID = 0; parameter DEVICE_TYPE = 0; @@ -90,18 +95,21 @@ module axi_ad6676 ( // rx_clk is (line-rate/40) input rx_clk; + input [ 3:0] rx_sof; + input rx_valid; + output rx_ready; input [63:0] rx_data; // dma interface output adc_clk; output adc_rst; - output adc_valid_a; - output adc_enable_a; - output [31:0] adc_data_a; - output adc_valid_b; - output adc_enable_b; - output [31:0] adc_data_b; + output adc_valid_0; + output adc_enable_0; + output [31:0] adc_data_0; + output adc_valid_1; + output adc_enable_1; + output [31:0] adc_data_1; input adc_dovf; input adc_dunf; @@ -126,6 +134,9 @@ module axi_ad6676 ( output [ 1:0] s_axi_rresp; output [31:0] s_axi_rdata; input s_axi_rready; + input [ 2:0] s_axi_awprot; + input [ 2:0] s_axi_arprot; + // internal registers @@ -144,8 +155,8 @@ module axi_ad6676 ( // internal signals - wire [31:0] adc_data_a_s; - wire [31:0] adc_data_b_s; + wire [31:0] adc_data_0_s; + wire [31:0] adc_data_1_s; wire adc_or_a_s; wire adc_or_b_s; wire adc_status_s; @@ -166,6 +177,8 @@ module axi_ad6676 ( assign up_clk = s_axi_aclk; assign up_rstn = s_axi_aresetn; + assign rx_ready = 1'b1; + // processor read interface always @(negedge up_rstn or posedge up_clk) begin @@ -188,18 +201,19 @@ module axi_ad6676 ( // adc valid - assign adc_valid_a = 1'b1; - assign adc_valid_b = 1'b1; + assign adc_valid_0 = 1'b1; + assign adc_valid_1 = 1'b1; // main (device interface) - axi_ad6676_if i_if ( + axi_ad6676_if #(.DEVICE_TYPE (DEVICE_TYPE)) i_if ( .rx_clk (rx_clk), + .rx_sof (rx_sof), .rx_data (rx_data), .adc_clk (adc_clk), .adc_rst (adc_rst), - .adc_data_a (adc_data_a_s), - .adc_data_b (adc_data_b_s), + .adc_data_a (adc_data_0_s), + .adc_data_b (adc_data_1_s), .adc_or_a (adc_or_a_s), .adc_or_b (adc_or_b_s), .adc_status (adc_status_s)); @@ -209,10 +223,10 @@ module axi_ad6676 ( axi_ad6676_channel #(.Q_OR_I_N(0), .CHANNEL_ID(0)) i_channel_0 ( .adc_clk (adc_clk), .adc_rst (adc_rst), - .adc_data (adc_data_a_s), + .adc_data (adc_data_0_s), .adc_or (adc_or_a_s), - .adc_dfmt_data (adc_data_a), - .adc_enable (adc_enable_a), + .adc_dfmt_data (adc_data_0), + .adc_enable (adc_enable_0), .up_adc_pn_err (up_status_pn_err_s[0]), .up_adc_pn_oos (up_status_pn_oos_s[0]), .up_adc_or (up_status_or_s[0]), @@ -232,10 +246,10 @@ module axi_ad6676 ( axi_ad6676_channel #(.Q_OR_I_N(1), .CHANNEL_ID(1)) i_channel_1 ( .adc_clk (adc_clk), .adc_rst (adc_rst), - .adc_data (adc_data_b_s), + .adc_data (adc_data_1_s), .adc_or (adc_or_b_s), - .adc_dfmt_data (adc_data_b), - .adc_enable (adc_enable_b), + .adc_dfmt_data (adc_data_1), + .adc_enable (adc_enable_1), .up_adc_pn_err (up_status_pn_err_s[1]), .up_adc_pn_oos (up_status_pn_oos_s[1]), .up_adc_or (up_status_or_s[1]), @@ -273,7 +287,7 @@ module axi_ad6676 ( .up_drp_wr (), .up_drp_addr (), .up_drp_wdata (), - .up_drp_rdata (16'd0), + .up_drp_rdata (32'd0), .up_drp_ready (1'd0), .up_drp_locked (1'd1), .up_usr_chanmax (), diff --git a/library/axi_ad6676/axi_ad6676_channel.v b/library/axi_ad6676/axi_ad6676_channel.v index 69b4c273c..63299c6ff 100755 --- a/library/axi_ad6676/axi_ad6676_channel.v +++ b/library/axi_ad6676/axi_ad6676_channel.v @@ -120,7 +120,7 @@ module axi_ad6676_channel ( assign adc_dfmt_data = adc_data; - up_adc_channel #(.ADC_CHANNEL_ID(CHANNEL_ID)) i_up_adc_channel ( + up_adc_channel #(.CHANNEL_ID(CHANNEL_ID)) i_up_adc_channel ( .adc_clk (adc_clk), .adc_rst (adc_rst), .adc_enable (adc_enable), diff --git a/library/axi_ad6676/axi_ad6676_if.v b/library/axi_ad6676/axi_ad6676_if.v index dff2757fe..ecd68a454 100755 --- a/library/axi_ad6676/axi_ad6676_if.v +++ b/library/axi_ad6676/axi_ad6676_if.v @@ -1,9 +1,9 @@ // *************************************************************************** // *************************************************************************** // Copyright 2011(c) Analog Devices, Inc. -// +// // All rights reserved. -// +// // Redistribution and use in source and binary forms, with or without modification, // are permitted provided that the following conditions are met: // - Redistributions of source code must retain the above copyright @@ -21,31 +21,31 @@ // patent holders to use this software. // - Use of the software either in source or binary form, must be run // on or directly connected to an Analog Devices Inc. component. -// +// // THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, // INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A // PARTICULAR PURPOSE ARE DISCLAIMED. // // IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, // EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY -// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR // BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // *************************************************************************** // *************************************************************************** // *************************************************************************** // *************************************************************************** -// This is the LVDS/DDR interface `timescale 1ns/100ps module axi_ad6676_if ( - // jesd interface + // jesd interface // rx_clk is (line-rate/40) rx_clk, + rx_sof, rx_data, // adc data output @@ -58,10 +58,14 @@ module axi_ad6676_if ( adc_or_b, adc_status); - // jesd interface - // rx_clk is (line-rate/40) + // parameters + + parameter DEVICE_TYPE = 0; + + // jesd interface input rx_clk; + input [ 3:0] rx_sof; input [63:0] rx_data; // adc data output @@ -84,6 +88,7 @@ module axi_ad6676_if ( wire [15:0] adc_data_a_s0_s; wire [15:0] adc_data_b_s1_s; wire [15:0] adc_data_b_s0_s; + wire [63:0] rx_data_s; // adc clock is the reference clock @@ -100,7 +105,7 @@ module axi_ad6676_if ( assign adc_data_a_s1_s = {rx_data[23:16], rx_data[31:24]}; assign adc_data_a_s0_s = {rx_data[ 7: 0], rx_data[15: 8]}; - assign adc_data_b_s1_s = {rx_data[55:48], rx_data[63:56]}; + assign adc_data_b_s1_s = {rx_data[55:48], rx_data[63:56]}; assign adc_data_b_s0_s = {rx_data[39:32], rx_data[47:40]}; // status @@ -113,6 +118,21 @@ module axi_ad6676_if ( end end + // frame-alignment + + genvar n; + + generate + for (n = 0; n < 2; n = n + 1) begin: g_xcvr_if + ad_xcvr_rx_if #(.DEVICE_TYPE (DEVICE_TYPE)) i_xcvr_if ( + .rx_clk (rx_clk), + .rx_ip_sof (rx_sof), + .rx_ip_data (rx_data[((n*32)+31):(n*32)]), + .rx_sof (), + .rx_data (rx_data_s[((n*32)+31):(n*32)])); + end + endgenerate + endmodule // *************************************************************************** diff --git a/library/axi_ad6676/axi_ad6676_ip.tcl b/library/axi_ad6676/axi_ad6676_ip.tcl index 3480d7115..ec91fcdc6 100644 --- a/library/axi_ad6676/axi_ad6676_ip.tcl +++ b/library/axi_ad6676/axi_ad6676_ip.tcl @@ -13,6 +13,7 @@ adi_ip_files axi_ad6676 [list \ "$ad_hdl_dir/library/common/up_clock_mon.v" \ "$ad_hdl_dir/library/common/up_adc_common.v" \ "$ad_hdl_dir/library/common/up_adc_channel.v" \ + "$ad_hdl_dir/library/common/ad_xcvr_rx_if.v" \ "$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc" \ "axi_ad6676_pnmon.v" \ "axi_ad6676_channel.v" \ @@ -25,6 +26,7 @@ adi_ip_constraints axi_ad6676 [list \ "$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc" \ "axi_ad6676_constr.xdc" ] +set_property driver_value 0 [ipx::get_ports *rx_valid* -of_objects [ipx::current_core]] set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]] set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]] diff --git a/library/axi_ad7616/Makefile b/library/axi_ad7616/Makefile new file mode 100644 index 000000000..5189f10d2 --- /dev/null +++ b/library/axi_ad7616/Makefile @@ -0,0 +1,61 @@ +#################################################################################### +#################################################################################### +## Copyright 2011(c) Analog Devices, Inc. +## Auto-generated, do not modify! +#################################################################################### +#################################################################################### + +M_DEPS += ../common/ad_edge_detect.v +M_DEPS += ../common/up_axi.v +M_DEPS += ../scripts/adi_env.tcl +M_DEPS += ../scripts/adi_ip.tcl +M_DEPS += axi_ad7616.v +M_DEPS += axi_ad7616_control.v +M_DEPS += axi_ad7616_ip.tcl +M_DEPS += axi_ad7616_maxis2wrfifo.v +M_DEPS += axi_ad7616_pif.v + +M_DEPS += ../spi_engine/axi_spi_engine/axi_spi_engine.xpr +M_DEPS += ../spi_engine/spi_engine_execution/spi_engine_execution.xpr +M_DEPS += ../spi_engine/spi_engine_interconnect/spi_engine_interconnect.xpr +M_DEPS += ../spi_engine/spi_engine_offload/spi_engine_offload.xpr + +M_VIVADO := vivado -mode batch -source + +M_FLIST := *.cache +M_FLIST += *.data +M_FLIST += *.xpr +M_FLIST += *.log +M_FLIST += component.xml +M_FLIST += *.jou +M_FLIST += xgui +M_FLIST += *.ip_user_files +M_FLIST += *.srcs +M_FLIST += *.hw +M_FLIST += *.sim +M_FLIST += .Xil + + + +.PHONY: all dep clean clean-all +all: dep axi_ad7616.xpr + + +clean:clean-all + + +clean-all: + rm -rf $(M_FLIST) + + +axi_ad7616.xpr: $(M_DEPS) + -rm -rf $(M_FLIST) + $(M_VIVADO) axi_ad7616_ip.tcl >> axi_ad7616_ip.log 2>&1 + +dep: + make -C ../spi_engine/axi_spi_engine/ + make -C ../spi_engine/spi_engine_execution/ + make -C ../spi_engine/spi_engine_interconnect/ + make -C ../spi_engine/spi_engine_offload/ +#################################################################################### +#################################################################################### diff --git a/library/axi_ad7616/axi_ad7616.v b/library/axi_ad7616/axi_ad7616.v new file mode 100644 index 000000000..8027d41c5 --- /dev/null +++ b/library/axi_ad7616/axi_ad7616.v @@ -0,0 +1,521 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2013(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_ad7616 ( + + // physical data interface + + rx_sclk, + rx_cs_n, + rx_sdo, + rx_sdi_0, + rx_sdi_1, + + rx_db_o, + rx_db_i, + rx_db_t, + rx_rd_n, + rx_wr_n, + + // physical control interface + + rx_cnvst, + rx_busy, + + // AXI Slave Memory Map + + s_axi_aclk, + s_axi_aresetn, + s_axi_awvalid, + s_axi_awaddr, + s_axi_awprot, + s_axi_awready, + s_axi_wvalid, + s_axi_wdata, + s_axi_wstrb, + s_axi_wready, + s_axi_bvalid, + s_axi_bresp, + s_axi_bready, + s_axi_arvalid, + s_axi_araddr, + s_axi_arprot, + s_axi_arready, + s_axi_rvalid, + s_axi_rresp, + s_axi_rdata, + s_axi_rready, + + // Write FIFO interface + + adc_valid, + adc_data, + adc_sync, + + irq +); + + // parameters + + parameter ID = 0; + parameter IF_TYPE = 1; + + // local parameters + + localparam NUM_OF_SDI = 2; + localparam SERIAL = 0; + localparam PARALLEL = 1; + localparam NEG_EDGE = 1; + localparam UP_ADDRESS_WIDTH = 14; + + // IO definitions + + output rx_sclk; + output rx_cs_n; + output rx_sdo; + input rx_sdi_0; + input rx_sdi_1; + + output [15:0] rx_db_o; + input [15:0] rx_db_i; + output rx_db_t; + output rx_rd_n; + output rx_wr_n; + + output rx_cnvst; + input rx_busy; + + input s_axi_aclk; + input s_axi_aresetn; + input s_axi_awvalid; + input [31:0] s_axi_awaddr; + output s_axi_awready; + input s_axi_wvalid; + input [31:0] s_axi_wdata; + input [ 3:0] s_axi_wstrb; + output s_axi_wready; + output s_axi_bvalid; + output [ 1:0] s_axi_bresp; + input s_axi_bready; + input s_axi_arvalid; + input [31:0] s_axi_araddr; + output s_axi_arready; + output s_axi_rvalid; + output [ 1:0] s_axi_rresp; + output [31:0] s_axi_rdata; + input s_axi_rready; + input [ 2:0] s_axi_awprot; + input [ 2:0] s_axi_arprot; + + + output adc_valid; + output [15:0] adc_data; + output adc_sync; + + output irq; + + // internal registers + + reg up_wack = 1'b0; + reg up_rack = 1'b0; + reg [31:0] up_rdata = 32'b0; + + // internal signals + + wire up_clk; + wire up_rstn; + wire up_rst; + wire up_rreq_s; + wire [(UP_ADDRESS_WIDTH-1):0] up_raddr_s; + wire up_wreq_s; + wire [(UP_ADDRESS_WIDTH-1):0] up_waddr_s; + wire [31:0] up_wdata_s; + + wire up_wack_if_s; + wire up_rack_if_s; + wire [31:0] up_rdata_if_s; + wire up_wack_cntrl_s; + wire up_rack_cntrl_s; + wire [31:0] up_rdata_cntrl_s; + + wire trigger_s; + + wire rd_req_s; + wire wr_req_s; + wire [15:0] wr_data_s; + wire [15:0] rd_data_s; + wire rd_valid_s; + wire [ 4:0] burst_length_s; + wire m_axis_ready_s; + wire m_axis_valid_s; + wire [15:0] m_axis_data_s; + wire m_axis_xfer_req_s; + + // defaults + + assign up_clk = s_axi_aclk; + assign up_rstn = s_axi_aresetn; + assign up_rst = ~s_axi_aresetn; + + // processor read interface + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_wack <= 'd0; + up_rack <= 'd0; + up_rdata <= 'd0; + end else begin + up_wack <= up_wack_if_s | up_wack_cntrl_s; + up_rack <= up_rack_if_s | up_rack_cntrl_s; + up_rdata <= up_rdata_if_s | up_rdata_cntrl_s; + end + end + + generate if (IF_TYPE == SERIAL) begin + + // ground all parallel interface signals + + assign rx_db_o = 16'b0; + assign rx_rd_n = 1'b0; + assign rx_wr_n = 1'b0; + + // SPI Framework instances and logic + + wire spi_resetn_s; + wire s0_cmd_ready_s; + wire s0_cmd_valid_s; + wire [15:0] s0_cmd_data_s; + wire s0_sdo_data_ready_s; + wire s0_sdo_data_valid_s; + wire [ 7:0] s0_sdo_data_s; + wire s0_sdi_data_ready_s; + wire s0_sdi_data_valid_s; + wire [15:0] s0_sdi_data_s; + wire s0_sync_ready_s; + wire s0_sync_valid_s; + wire [ 7:0] s0_sync_s; + wire s1_cmd_ready_s; + wire s1_cmd_valid_s; + wire [15:0] s1_cmd_data_s; + wire s1_sdo_data_ready_s; + wire s1_sdo_data_valid_s; + wire [ 7:0] s1_sdo_data_s; + wire s1_sdi_data_ready_s; + wire s1_sdi_data_valid_s; + wire [15:0] s1_sdi_data_s; + wire s1_sync_ready_s; + wire s1_sync_valid_s; + wire [ 7:0] s1_sync_s; + wire m_cmd_ready_s; + wire m_cmd_valid_s; + wire [15:0] m_cmd_data_s; + wire m_sdo_data_ready_s; + wire m_sdo_data_valid_s; + wire [7:0] m_sdo_data_s; + wire m_sdi_data_ready_s; + wire m_sdi_data_valid_s; + wire [15:0] m_sdi_data_s; + wire m_sync_ready_s; + wire m_sync_valid_s; + wire [ 7:0] m_sync_s; + wire offload0_cmd_wr_en_s; + wire [15:0] offload0_cmd_wr_data_s; + wire offload0_sdo_wr_en_s; + wire [ 7:0] offload0_sdo_wr_data_s; + wire offload0_mem_reset_s; + wire offload0_enable_s; + wire offload0_enabled_s; + + axi_spi_engine #( + .DATA_WIDTH (8), + .NUM_OF_SDI (NUM_OF_SDI), + .NUM_OFFLOAD(1), + .MM_IF_TYPE(1), + .UP_ADDRESS_WIDTH (UP_ADDRESS_WIDTH) + ) i_axi_spi_engine ( + .up_clk (up_clk), + .up_rstn (up_rstn), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack_if_s), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata_if_s), + .up_rack (up_rack_if_s), + .irq (irq), + .spi_clk (up_clk), + .spi_resetn (spi_resetn_s), + .cmd_ready (s0_cmd_ready_s), + .cmd_valid (s0_cmd_valid_s), + .cmd_data (s0_cmd_data_s), + .sdo_data_ready (s0_sdo_data_ready_s), + .sdo_data_valid (s0_sdo_data_valid_s), + .sdo_data (s0_sdo_data_s), + .sdi_data_ready (s0_sdi_data_ready_s), + .sdi_data_valid (s0_sdi_data_valid_s), + .sdi_data (s0_sdi_data_s), + .sync_ready (s0_sync_ready_s), + .sync_valid (s0_sync_valid_s), + .sync_data (s0_sync_s), + .offload0_cmd_wr_en (offload0_cmd_wr_en_s), + .offload0_cmd_wr_data (offload0_cmd_wr_data_s), + .offload0_sdo_wr_en (offload0_sdo_wr_en_s), + .offload0_sdo_wr_data (offload0_sdo_wr_data_s), + .offload0_mem_reset (offload0_mem_reset_s), + .offload0_enable (offload0_enable_s), + .offload0_enabled(offload0_enabled_s)); + + spi_engine_offload #( + .DATA_WIDTH (8), + .NUM_OF_SDI (NUM_OF_SDI) + ) i_spi_engine_offload ( + .ctrl_clk (up_clk), + .ctrl_cmd_wr_en (offload0_cmd_wr_en_s), + .ctrl_cmd_wr_data (offload0_cmd_wr_data_s), + .ctrl_sdo_wr_en (offload0_sdo_wr_en_s), + .ctrl_sdo_wr_data (offload0_sdo_wr_data_s), + .ctrl_enable (offload0_enable_s), + .ctrl_enabled (offload0_enabled_s), + .ctrl_mem_reset (offload0_mem_reset_s), + .spi_clk (up_clk), + .spi_resetn (spi_resetn_s), + .trigger (trigger_s), + .cmd_valid (s1_cmd_valid_s), + .cmd_ready (s1_cmd_ready_s), + .cmd (s1_cmd_data_s), + .sdo_data_valid (s1_sdo_data_valid_s), + .sdo_data_ready (s1_sdo_data_ready_s), + .sdo_data (s1_sdo_data_s), + .sdi_data_valid (s1_sdi_data_valid_s), + .sdi_data_ready (s1_sdi_data_ready_s), + .sdi_data (s1_sdi_data_s), + .sync_valid (s1_sync_valid_s), + .sync_ready (s1_sync_ready_s), + .sync_data (s1_sync_s), + .offload_sdi_valid (m_axis_valid_s), + .offload_sdi_ready (m_axis_ready_s), + .offload_sdi_data (m_axis_data_s)); + + spi_engine_interconnect #( + .DATA_WIDTH (8), + .NUM_OF_SDI (NUM_OF_SDI) + ) i_spi_engine_interconnect ( + .clk (up_clk), + .resetn (spi_resetn_s), + .m_cmd_valid (m_cmd_valid_s), + .m_cmd_ready (m_cmd_ready_s), + .m_cmd_data (m_cmd_data_s), + .m_sdo_valid (m_sdo_data_valid_s), + .m_sdo_ready (m_sdo_data_ready_s), + .m_sdo_data (m_sdo_data_s), + .m_sdi_valid (m_sdi_data_valid_s), + .m_sdi_ready (m_sdi_data_ready_s), + .m_sdi_data (m_sdi_data_s), + .m_sync_valid (m_sync_valid_s), + .m_sync_ready (m_sync_ready_s), + .m_sync (m_sync_s), + .s0_cmd_valid (s0_cmd_valid_s), + .s0_cmd_ready (s0_cmd_ready_s), + .s0_cmd_data (s0_cmd_data_s), + .s0_sdo_valid (s0_sdo_data_valid_s), + .s0_sdo_ready (s0_sdo_data_ready_s), + .s0_sdo_data (s0_sdo_data_s), + .s0_sdi_valid (s0_sdi_data_valid_s), + .s0_sdi_ready (s0_sdi_data_ready_s), + .s0_sdi_data (s0_sdi_data_s), + .s0_sync_valid (s0_sync_valid_s), + .s0_sync_ready (s0_sync_ready_s), + .s0_sync (s0_sync_s), + .s1_cmd_valid (s1_cmd_valid_s), + .s1_cmd_ready (s1_cmd_ready_s), + .s1_cmd_data (s1_cmd_data_s), + .s1_sdo_valid (s1_sdo_data_valid_s), + .s1_sdo_ready (s1_sdo_data_ready_s), + .s1_sdo_data (s1_sdo_data_s), + .s1_sdi_valid (s1_sdi_data_valid_s), + .s1_sdi_ready (s1_sdi_data_ready_s), + .s1_sdi_data (s1_sdi_data_s), + .s1_sync_valid (s1_sync_valid_s), + .s1_sync_ready (s1_sync_ready_s), + .s1_sync (s1_sync_s)); + + spi_engine_execution #( + .DATA_WIDTH (8), + .NUM_OF_SDI (NUM_OF_SDI) + ) i_spi_engine_execution ( + .clk (up_clk), + .resetn (spi_resetn_s), + .active (), + .cmd_ready (m_cmd_ready_s), + .cmd_valid (m_cmd_valid_s), + .cmd (m_cmd_data_s), + .sdo_data_valid (m_sdo_data_valid_s), + .sdo_data_ready (m_sdo_data_ready_s), + .sdo_data (m_sdo_data_s), + .sdi_data_ready (m_sdi_data_ready_s), + .sdi_data_valid (m_sdi_data_valid_s), + .sdi_data (m_sdi_data_s), + .sync_ready (m_sync_ready_s), + .sync_valid (m_sync_valid_s), + .sync (m_sync_s), + .sclk (rx_sclk), + .sdo (rx_sdo), + .sdo_t (), + .sdi (rx_sdi_0), + .sdi_1 (rx_sdi_1), + .sdi_2 (1'b0), + .sdi_3 (1'b0), + .cs (rx_cs_n), + .three_wire ()); + + axi_ad7616_maxis2wrfifo #( + .DATA_WIDTH(16) + ) i_maxis2wrfifo ( + .clk(up_clk), + .rstn(up_rstn), + .sync_in(trigger_s), + .m_axis_data(m_axis_data_s), + .m_axis_ready(m_axis_ready_s), + .m_axis_valid(m_axis_valid_s), + .fifo_wr_en(adc_valid), + .fifo_wr_data(adc_data), + .fifo_wr_sync(adc_sync) + ); + + end + endgenerate + + generate if (IF_TYPE == PARALLEL) begin + + assign rx_sclk = 1'h0; + assign rx_sdo = 1'h0; + assign irq = 1'h0; + + assign up_wack_if_s = 1'h0; + assign up_rack_if_s = 1'h0; + assign up_rdata_if_s = 1'h0; + + axi_ad7616_pif i_ad7616_parallel_interface ( + .cs_n (rx_cs_n), + .db_o (rx_db_o), + .db_i (rx_db_i), + .db_t (rx_db_t), + .rd_n (rx_rd_n), + .wr_n (rx_wr_n), + .adc_data (adc_data), + .adc_valid (adc_valid), + .adc_sync (adc_sync), + .end_of_conv (trigger_s), + .burst_length(burst_length_s), + .clk (up_clk), + .rstn (up_rstn), + .rd_req (rd_req_s), + .wr_req (wr_req_s), + .wr_data (wr_data_s), + .rd_data (rd_data_s), + .rd_valid (rd_valid_s) + ); + + end + endgenerate + + axi_ad7616_control #( + .ID(ID), + .IF_TYPE(IF_TYPE) + ) i_ad7616_control ( + .cnvst (rx_cnvst), + .busy (rx_busy), + .up_burst_length (burst_length_s), + .up_read_data (rd_data_s), + .up_read_valid (rd_valid_s), + .up_write_data (wr_data_s), + .up_read_req (rd_req_s), + .up_write_req (wr_req_s), + .end_of_conv (trigger_s), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack_cntrl_s), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata_cntrl_s), + .up_rack (up_rack_cntrl_s)); + + // up bus interface + + up_axi #( + .ADDRESS_WIDTH (UP_ADDRESS_WIDTH) + ) i_up_axi ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_axi_awvalid (s_axi_awvalid), + .up_axi_awaddr (s_axi_awaddr), + .up_axi_awready (s_axi_awready), + .up_axi_wvalid (s_axi_wvalid), + .up_axi_wdata (s_axi_wdata), + .up_axi_wstrb (s_axi_wstrb), + .up_axi_wready (s_axi_wready), + .up_axi_bvalid (s_axi_bvalid), + .up_axi_bresp (s_axi_bresp), + .up_axi_bready (s_axi_bready), + .up_axi_arvalid (s_axi_arvalid), + .up_axi_araddr (s_axi_araddr), + .up_axi_arready (s_axi_arready), + .up_axi_rvalid (s_axi_rvalid), + .up_axi_rresp (s_axi_rresp), + .up_axi_rdata (s_axi_rdata), + .up_axi_rready (s_axi_rready), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata), + .up_rack (up_rack)); + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/library/axi_ad7616/axi_ad7616_control.v b/library/axi_ad7616/axi_ad7616_control.v new file mode 100644 index 000000000..af013aa96 --- /dev/null +++ b/library/axi_ad7616/axi_ad7616_control.v @@ -0,0 +1,251 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2015(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_ad7616_control ( + + // control signals + + cnvst, + busy, + + up_read_data, + up_read_valid, + up_write_data, + up_read_req, + up_write_req, + + up_burst_length, + end_of_conv, + + // bus interface + + up_rstn, + up_clk, + up_wreq, + up_waddr, + up_wdata, + up_wack, + up_rreq, + up_raddr, + up_rdata, + up_rack + +); + + parameter ID = 0; + parameter IF_TYPE = 0; + + localparam PCORE_VERSION = 'h0001001; + localparam POS_EDGE = 0; + localparam NEG_EDGE = 1; + localparam SERIAL = 0; + localparam PARALLEL = 1; + + output cnvst; + input busy; + + output end_of_conv; + output [ 4:0] up_burst_length; + + input [15:0] up_read_data; + input up_read_valid; + output [15:0] up_write_data; + output up_read_req; + output up_write_req; + + // bus interface + + input up_rstn; + input up_clk; + input up_wreq; + input [13:0] up_waddr; + input [31:0] up_wdata; + output up_wack; + input up_rreq; + input [13:0] up_raddr; + output [31:0] up_rdata; + output up_rack; + + // internal signals + + reg [31:0] up_scratch = 32'b0; + reg up_resetn = 1'b0; + reg up_cnvst_en = 1'b0; + reg up_wack = 1'b0; + reg up_rack = 1'b0; + reg [31:0] up_rdata = 32'b0; + reg [31:0] up_conv_rate = 32'b0; + reg [ 4:0] up_burst_length = 5'h0; + reg [15:0] up_write_data = 16'h0; + + reg [31:0] cnvst_counter = 32'b0; + reg [ 3:0] pulse_counter = 8'b0; + reg cnvst_buf = 1'b0; + reg cnvst_pulse = 1'b0; + reg [ 2:0] chsel_ff = 3'b0; + + wire up_rst; + wire up_rreq_s; + wire up_rack_s; + wire up_wreq_s; + + wire [31:0] up_read_data_s; + wire up_read_valid_s; + + // decode block select + + assign up_wreq_s = (up_waddr[13:8] == 6'h01) ? up_wreq : 1'b0; + assign up_rreq_s = (up_raddr[13:8] == 6'h01) ? up_rreq : 1'b0; + + // the up_[read/write]_data interfaces are valid just in parallel mode + + assign up_read_valid_s = (IF_TYPE == PARALLEL) ? up_read_valid : 1'b1; + assign up_read_data_s = (IF_TYPE == PARALLEL) ? {16'h0, up_read_data} : {2{16'hDEAD}}; + + // processor write interface + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_wack <= 1'h0; + up_scratch <= 32'b0; + up_resetn <= 1'b0; + up_cnvst_en <= 1'b0; + up_conv_rate <= 32'b0; + up_burst_length <= 5'h0; + up_write_data <= 16'h0; + end else begin + up_wack <= up_wreq_s; + if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h02)) begin + up_scratch <= up_wdata; + end + if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h10)) begin + up_resetn <= up_wdata[0]; + up_cnvst_en <= up_wdata[1]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h11)) begin + up_conv_rate <= up_wdata; + end + if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h12)) begin + up_burst_length <= up_wdata; + end + if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h14)) begin + up_write_data <= up_wdata; + end + end + end + + assign up_write_req = (up_waddr[7:0] == 8'h14) ? up_wreq_s : 1'h0; + + // processor read interface + + assign up_rack_s = (up_raddr[7:0] == 8'h13) ? up_read_valid_s : up_rreq_s; + assign up_read_req = (up_raddr[7:0] == 8'h13) ? up_rreq_s : 1'b0; + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_rack <= 1'b0; + up_rdata <= 32'b0; + end else begin + up_rack <= up_rack_s; + if (up_rack_s == 1'b1) begin + case (up_raddr[7:0]) + 8'h00 : up_rdata = PCORE_VERSION; + 8'h01 : up_rdata = ID; + 8'h02 : up_rdata = up_scratch; + 8'h03 : up_rdata = IF_TYPE; + 8'h10 : up_rdata = {29'b0, up_cnvst_en, up_resetn}; + 8'h11 : up_rdata = up_conv_rate; + 8'h12 : up_rdata = {27'b0, up_burst_length}; + 8'h13 : up_rdata = up_read_data_s; + endcase + end + end + end + + // instantiations + + assign up_rst = ~up_rstn; + + ad_edge_detect #( + .EDGE(NEG_EDGE) + ) i_ad_edge_detect ( + .clk (up_clk), + .rst (up_rst), + .in (busy), + .out (end_of_conv) + ); + + // convertion start generator + // NOTE: + The minimum convertion cycle is 1 us + // + The rate of the cnvst must be defined in a way, + // to not lose any data. cnvst_rate >= t_conversion + t_aquisition + // See the AD7616 datasheet for more information. + + always @(posedge up_clk) begin + if(up_resetn == 1'b0) begin + cnvst_counter <= 32'b0; + end else begin + cnvst_counter <= (cnvst_counter < up_conv_rate) ? cnvst_counter + 1 : 32'b0; + end + end + + always @(cnvst_counter, up_conv_rate) begin + cnvst_pulse <= (cnvst_counter == up_conv_rate) ? 1'b1 : 1'b0; + end + + always @(posedge up_clk) begin + if(up_resetn == 1'b0) begin + pulse_counter <= 3'b0; + cnvst_buf <= 1'b0; + end else begin + pulse_counter <= (cnvst == 1'b1) ? pulse_counter + 1 : 3'b0; + if(cnvst_pulse == 1'b1) begin + cnvst_buf <= 1'b1; + end else if (pulse_counter[2] == 1'b1) begin + cnvst_buf <= 1'b0; + end + end + end + + assign cnvst = (up_cnvst_en == 1'b1) ? cnvst_buf : 1'b0; + +endmodule + diff --git a/library/axi_ad7616/axi_ad7616_ip.tcl b/library/axi_ad7616/axi_ad7616_ip.tcl new file mode 100644 index 000000000..36e16530f --- /dev/null +++ b/library/axi_ad7616/axi_ad7616_ip.tcl @@ -0,0 +1,27 @@ +# ip + +source ../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip.tcl + +adi_ip_create axi_ad7616 +adi_ip_files axi_ad7616 [list \ + "$ad_hdl_dir/library/common/ad_edge_detect.v" \ + "$ad_hdl_dir/library/common/up_axi.v" \ + "axi_ad7616_control.v" \ + "axi_ad7616_pif.v" \ + "axi_ad7616_maxis2wrfifo.v" \ + "axi_ad7616.v" ] + +adi_ip_properties axi_ad7616 + +adi_ip_add_core_dependencies { \ + analog.com:user:spi_engine_execution:1.0 \ + analog.com:user:axi_spi_engine:1.0 \ + analog.com:user:spi_engine_offload:1.0 \ + analog.com:user:spi_engine_interconnect:1.0 \ +} + +set_property DRIVER_VALUE "0" [ipx::get_ports rx_db_i] + +ipx::save_core [ipx::current_core] + diff --git a/library/common/altera/ad_mul_u16_alt.v b/library/axi_ad7616/axi_ad7616_maxis2wrfifo.v similarity index 61% rename from library/common/altera/ad_mul_u16_alt.v rename to library/axi_ad7616/axi_ad7616_maxis2wrfifo.v index 923944a57..03448feed 100644 --- a/library/common/altera/ad_mul_u16_alt.v +++ b/library/axi_ad7616/axi_ad7616_maxis2wrfifo.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014(c) Analog Devices, Inc. +// Copyright 2013(c) Analog Devices, Inc. // // All rights reserved. // @@ -36,77 +36,72 @@ // *************************************************************************** // *************************************************************************** // *************************************************************************** -// both inputs are considered unsigned 16 bits- -// ddata is delay matched generic data -`timescale 1ps/1ps +`timescale 1ns/100ps -module ad_mul_u16 ( - - // data_p = data_a * data_b; +module axi_ad7616_maxis2wrfifo ( clk, - data_a, - data_b, - data_p, + rstn, + sync_in, - // delay interface + // m_axis interface - ddata_in, - ddata_out); + m_axis_data, + m_axis_ready, + m_axis_valid, + m_axis_xfer_req, - // delayed data bus width + // write fifo interface - parameter DELAY_DATA_WIDTH = 16; - localparam DW = DELAY_DATA_WIDTH - 1; + fifo_wr_en, + fifo_wr_data, + fifo_wr_sync, + fifo_wr_xfer_req - // data_p = data_a * data_b; +); - input clk; - input [15:0] data_a; - input [15:0] data_b; - output [31:0] data_p; + parameter DATA_WIDTH = 16; - // delay interface + input clk; + input rstn; + input sync_in; - input [DW:0] ddata_in; - output [DW:0] ddata_out; + input [DATA_WIDTH-1:0] m_axis_data; + output m_axis_ready; + input m_axis_valid; + output m_axis_xfer_req; - // internal registers + output fifo_wr_en; + output [DATA_WIDTH-1:0] fifo_wr_data; + output fifo_wr_sync; + input fifo_wr_xfer_req; - reg [DW:0] p1_ddata = 'd0; - reg [DW:0] p2_ddata = 'd0; - reg [DW:0] ddata_out = 'd0; - - // internal signals - - - // a/b reg, m-reg, p-reg delay match + reg m_axis_ready = 1'b0; + reg m_axis_xfer_req = 1'b0; + reg fifo_wr_en = 1'b0; + reg [DATA_WIDTH-1:0] fifo_wr_data = 'b0; + reg fifo_wr_sync = 1'b0; always @(posedge clk) begin - p1_ddata <= ddata_in; - p2_ddata <= p1_ddata; - ddata_out <= p2_ddata; + if (rstn == 1'b0) begin + m_axis_ready <= 1'b0; + m_axis_xfer_req <= 1'b0; + fifo_wr_data <= 'b0; + fifo_wr_en <= 1'b0; + fifo_wr_sync <= 1'b0; + end else begin + m_axis_ready <= 1'b1; + m_axis_xfer_req <= fifo_wr_xfer_req; + fifo_wr_data <= m_axis_data; + fifo_wr_en <= m_axis_valid; + if (sync_in == 1'b1) begin + fifo_wr_sync <= 1'b1; + end else if ((m_axis_valid == 1'b1) && + (fifo_wr_sync == 1'b1)) begin + fifo_wr_sync <= 1'b0; + end + end end - lpm_mult i_mult_macro ( - .clock (clk), - .dataa (data_a), - .datab (data_b), - .result (data_p), - .aclr (1'b0), - .clken (1'b1), - .sum (1'b0)); - defparam - lpm_mult_component.lpm_hint = "MAXIMIZE_SPEED=5", - lpm_mult_component.lpm_pipeline = 3, - lpm_mult_component.lpm_representation = "UNSIGNED", - lpm_mult_component.lpm_type = "LPM_MULT", - lpm_mult_component.lpm_widtha = 16, - lpm_mult_component.lpm_widthb = 16, - lpm_mult_component.lpm_widthp = 32; - endmodule - -// *************************************************************************** -// *************************************************************************** diff --git a/library/axi_ad7616/axi_ad7616_pif.v b/library/axi_ad7616/axi_ad7616_pif.v new file mode 100644 index 000000000..491222f30 --- /dev/null +++ b/library/axi_ad7616/axi_ad7616_pif.v @@ -0,0 +1,246 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2015(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_ad7616_pif ( + + // physical interface + + cs_n, + db_o, + db_i, + db_t, + rd_n, + wr_n, + + // FIFO interface + + adc_data, + adc_valid, + adc_sync, + + // end of convertion + + end_of_conv, + burst_length, + + // register access + + clk, + rstn, + rd_req, + wr_req, + wr_data, + rd_data, + rd_valid +); + + parameter UP_ADDRESS_WIDTH = 14; + + // IO definitions + + output cs_n; + output [15:0] db_o; + input [15:0] db_i; + output db_t; + output rd_n; + output wr_n; + + input end_of_conv; + input [ 4:0] burst_length; + + input clk; + input rstn; + input rd_req; + input wr_req; + input [15:0] wr_data; + output [15:0] rd_data; + output rd_valid; + + output [15:0] adc_data; + output adc_valid; + output adc_sync; + + // state registers + + localparam [ 2:0] IDLE = 3'h0, + CS_LOW = 3'h1, + CNTRL0_LOW = 3'h2, + CNTRL0_HIGH = 3'h3, + CNTRL1_LOW = 3'h4, + CNTRL1_HIGH = 3'h5, + CS_HIGH = 3'h6; + + // internal registers + + reg [ 2:0] transfer_state = 3'h0; + reg [ 2:0] transfer_state_next = 3'h0; + reg [ 1:0] width_counter = 2'h0; + reg [ 4:0] burst_counter = 5'h0; + + reg wr_req_d = 1'h0; + reg rd_req_d = 1'h0; + reg rd_conv_d = 1'h0; + + reg xfer_req_d = 1'h0; + + reg adc_sync = 1'h0; + reg rd_valid = 1'h0; + reg rd_valid_d = 1'h0; + reg [15:0] rd_data = 16'h0; + + // internal wires + + wire start_transfer_s; + wire rd_valid_s; + + // FSM state register + + always @(posedge clk) begin + if (rstn == 1'b0) begin + transfer_state <= 3'h0; + end else begin + transfer_state <= transfer_state_next; + end + end + + // counters to control the RD_N and WR_N lines + + assign start_transfer_s = end_of_conv | rd_req | wr_req; + + always @(posedge clk) begin + if (rstn == 1'b0) begin + width_counter <= 2'h0; + end else begin + if((transfer_state == CNTRL0_LOW) || (transfer_state == CNTRL0_HIGH) || + (transfer_state == CNTRL1_LOW) || (transfer_state == CNTRL1_HIGH)) + width_counter <= width_counter + 1; + else + width_counter <= 2'h0; + end + end + + always @(posedge clk) begin + if (rstn == 1'b0) begin + burst_counter <= 2'h0; + end else begin + if (transfer_state == CS_HIGH) + burst_counter <= burst_counter + 1; + else if (transfer_state == IDLE) + burst_counter <= 5'h0; + end + end + + always @(negedge clk) begin + if (transfer_state == IDLE) begin + wr_req_d <= wr_req; + rd_req_d <= rd_req; + rd_conv_d <= end_of_conv; + end + end + + // FSM next state logic + + always @(*) begin + case (transfer_state) + IDLE : begin + transfer_state_next <= (start_transfer_s == 1'b1) ? CS_LOW : IDLE; + end + CS_LOW : begin + transfer_state_next <= CNTRL0_LOW; + end + CNTRL0_LOW : begin + transfer_state_next <= (width_counter != 2'b11) ? CNTRL0_LOW : CNTRL0_HIGH; + end + CNTRL0_HIGH : begin + transfer_state_next <= (width_counter != 2'b11) ? CNTRL0_HIGH : + ((wr_req_d == 1'b1) || (rd_req_d == 1'b1)) ? CS_HIGH : CNTRL1_LOW; + end + CNTRL1_LOW : begin + transfer_state_next <= (width_counter != 2'b11) ? CNTRL1_LOW : CNTRL1_HIGH; + end + CNTRL1_HIGH : begin + transfer_state_next <= (width_counter != 2'b11) ? CNTRL1_HIGH : CS_HIGH; + end + CS_HIGH : begin + transfer_state_next <= (burst_length == burst_counter) ? IDLE : CNTRL0_LOW; + end + default : begin + transfer_state_next <= IDLE; + end + endcase + end + + // data valid for the register access and m_axis interface + + assign rd_valid_s = (((transfer_state == CNTRL0_HIGH) || (transfer_state == CNTRL1_HIGH)) && + ((rd_req_d == 1'b1) || (rd_conv_d == 1'b1))) ? 1'b1 : 1'b0; + + // FSM output logic + + assign db_o = wr_data; + + always @(posedge clk) begin + rd_data <= (rd_valid_s & ~rd_valid_d) ? db_i : rd_data; + rd_valid_d <= rd_valid_s; + rd_valid <= rd_valid_s & ~rd_valid_d; + end + + assign adc_valid = rd_valid; + assign adc_data = rd_data; + + assign cs_n = (transfer_state == IDLE) ? 1'b1 : 1'b0; + assign db_t = ~wr_req_d; + assign rd_n = (((transfer_state == CNTRL0_LOW) && ((rd_conv_d == 1'b1) || rd_req_d == 1'b1)) || + (transfer_state == CNTRL1_LOW)) ? 1'b0 : 1'b1; + assign wr_n = ((transfer_state == CNTRL0_LOW) && (wr_req_d == 1'b1)) ? 1'b0 : 1'b1; + + // sync will be asserted at the first valid data right after the convertion start + + always @(posedge clk) begin + if (end_of_conv == 1'b1) begin + adc_sync <= 1'b1; + end else if (rd_valid == 1'b1) begin + adc_sync <= 1'b0; + end + end + +endmodule + diff --git a/library/axi_ad9122/Makefile b/library/axi_ad9122/Makefile index c1ff2e4dd..8989cf8df 100644 --- a/library/axi_ad9122/Makefile +++ b/library/axi_ad9122/Makefile @@ -5,29 +5,29 @@ #################################################################################### #################################################################################### -M_DEPS := axi_ad9122_ip.tcl -M_DEPS += ../scripts/adi_env.tcl -M_DEPS += ../scripts/adi_ip.tcl -M_DEPS += ../common/ad_mul.v -M_DEPS += ../common/ad_dds_sine.v -M_DEPS += ../common/ad_dds_1.v +M_DEPS += ../common/ad_axi_ip_constr.xdc M_DEPS += ../common/ad_dds.v +M_DEPS += ../common/ad_dds_1.v +M_DEPS += ../common/ad_dds_sine.v M_DEPS += ../common/ad_rst.v -M_DEPS += ../common/ad_mmcm_drp.v -M_DEPS += ../common/ad_serdes_out.v -M_DEPS += ../common/ad_serdes_clk.v M_DEPS += ../common/up_axi.v +M_DEPS += ../common/up_clock_mon.v +M_DEPS += ../common/up_dac_channel.v +M_DEPS += ../common/up_dac_common.v M_DEPS += ../common/up_xfer_cntrl.v M_DEPS += ../common/up_xfer_status.v -M_DEPS += ../common/up_clock_mon.v -M_DEPS += ../common/up_dac_common.v -M_DEPS += ../common/up_dac_channel.v -M_DEPS += ../common/ad_axi_ip_constr.xdc +M_DEPS += ../scripts/adi_env.tcl +M_DEPS += ../scripts/adi_ip.tcl +M_DEPS += ../xilinx/common/ad_mmcm_drp.v +M_DEPS += ../xilinx/common/ad_mul.v +M_DEPS += ../xilinx/common/ad_serdes_clk.v +M_DEPS += ../xilinx/common/ad_serdes_out.v +M_DEPS += axi_ad9122.v M_DEPS += axi_ad9122_channel.v +M_DEPS += axi_ad9122_constr.xdc M_DEPS += axi_ad9122_core.v M_DEPS += axi_ad9122_if.v -M_DEPS += axi_ad9122_constr.xdc -M_DEPS += axi_ad9122.v +M_DEPS += axi_ad9122_ip.tcl M_VIVADO := vivado -mode batch -source @@ -38,6 +38,10 @@ M_FLIST += *.log M_FLIST += component.xml M_FLIST += *.jou M_FLIST += xgui +M_FLIST += *.ip_user_files +M_FLIST += *.srcs +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil @@ -54,7 +58,7 @@ clean-all: axi_ad9122.xpr: $(M_DEPS) - rm -rf $(M_FLIST) + -rm -rf $(M_FLIST) $(M_VIVADO) axi_ad9122_ip.tcl >> axi_ad9122_ip.log 2>&1 #################################################################################### diff --git a/library/axi_ad9122/axi_ad9122.v b/library/axi_ad9122/axi_ad9122.v index 4ac740ae0..c20ceeb8d 100644 --- a/library/axi_ad9122/axi_ad9122.v +++ b/library/axi_ad9122/axi_ad9122.v @@ -1,9 +1,9 @@ // *************************************************************************** // *************************************************************************** // Copyright 2011(c) Analog Devices, Inc. -// +// // All rights reserved. -// +// // Redistribution and use in source and binary forms, with or without modification, // are permitted provided that the following conditions are met: // - Redistributions of source code must retain the above copyright @@ -21,16 +21,16 @@ // patent holders to use this software. // - Use of the software either in source or binary form, must be run // on or directly connected to an Analog Devices Inc. component. -// +// // THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, // INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A // PARTICULAR PURPOSE ARE DISCLAIMED. // // IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, // EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY -// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR // BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // *************************************************************************** // *************************************************************************** @@ -87,7 +87,9 @@ module axi_ad9122 ( s_axi_rvalid, s_axi_rdata, s_axi_rresp, - s_axi_rready); + s_axi_rready, + s_axi_awprot, + s_axi_arprot); // parameters @@ -95,6 +97,11 @@ module axi_ad9122 ( parameter DEVICE_TYPE = 0; parameter SERDES_OR_DDR_N = 1; parameter MMCM_OR_BUFIO_N = 1; + parameter MMCM_CLKIN_PERIOD = 1.667; + parameter MMCM_VCO_DIV = 2; + parameter MMCM_VCO_MUL = 4; + parameter MMCM_CLK0_DIV = 2; + parameter MMCM_CLK1_DIV = 8; parameter DAC_DATAPATH_DISABLE = 0; parameter IO_DELAY_GROUP = "dev_if_delay_group"; @@ -147,6 +154,9 @@ module axi_ad9122 ( output [31:0] s_axi_rdata; output [ 1:0] s_axi_rresp; input s_axi_rready; + input [ 2:0] s_axi_awprot; + input [ 2:0] s_axi_arprot; + // internal clocks and resets @@ -177,8 +187,8 @@ module axi_ad9122 ( wire up_drp_sel_s; wire up_drp_wr_s; wire [11:0] up_drp_addr_s; - wire [15:0] up_drp_wdata_s; - wire [15:0] up_drp_rdata_s; + wire [31:0] up_drp_wdata_s; + wire [31:0] up_drp_rdata_s; wire up_drp_ready_s; wire up_drp_locked_s; wire up_wreq_s; @@ -200,7 +210,12 @@ module axi_ad9122 ( axi_ad9122_if #( .DEVICE_TYPE (DEVICE_TYPE), .SERDES_OR_DDR_N (SERDES_OR_DDR_N), - .MMCM_OR_BUFIO_N (MMCM_OR_BUFIO_N)) + .MMCM_OR_BUFIO_N (MMCM_OR_BUFIO_N), + .MMCM_CLKIN_PERIOD (MMCM_CLKIN_PERIOD), + .MMCM_VCO_DIV (MMCM_VCO_DIV), + .MMCM_VCO_MUL (MMCM_VCO_MUL), + .MMCM_CLK0_DIV (MMCM_CLK0_DIV), + .MMCM_CLK1_DIV (MMCM_CLK1_DIV)) i_if ( .dac_clk_in_p (dac_clk_in_p), .dac_clk_in_n (dac_clk_in_n), diff --git a/library/axi_ad9122/axi_ad9122_channel.v b/library/axi_ad9122/axi_ad9122_channel.v index 7b64d2d32..d936f9048 100644 --- a/library/axi_ad9122/axi_ad9122_channel.v +++ b/library/axi_ad9122/axi_ad9122_channel.v @@ -1,9 +1,9 @@ // *************************************************************************** // *************************************************************************** // Copyright 2011(c) Analog Devices, Inc. -// +// // All rights reserved. -// +// // Redistribution and use in source and binary forms, with or without modification, // are permitted provided that the following conditions are met: // - Redistributions of source code must retain the above copyright @@ -21,16 +21,16 @@ // patent holders to use this software. // - Use of the software either in source or binary form, must be run // on or directly connected to an Analog Devices Inc. component. -// +// // THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, // INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A // PARTICULAR PURPOSE ARE DISCLAIMED. // // IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, // EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY -// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR // BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // *************************************************************************** // *************************************************************************** @@ -141,8 +141,8 @@ module axi_ad9122_channel ( dac_enable <= (dac_data_sel_s == 4'h2) ? 1'b1 : 1'b0; case (dac_data_sel_s) 4'h2: dac_data <= dma_data; - 4'h1: dac_data <= { dac_pat_data_2_s, dac_pat_data_1_s, - dac_pat_data_2_s, dac_pat_data_1_s}; + 4'ha, 4'h1: dac_data <= {dac_pat_data_2_s, dac_pat_data_1_s, + dac_pat_data_2_s, dac_pat_data_1_s}; default: dac_data <= dac_dds_data; endcase if (dac_data_sel_s == 4'h1) begin @@ -197,7 +197,7 @@ module axi_ad9122_channel ( .dds_data (dac_dds_data_0_s)); end endgenerate - + generate if (DATAPATH_DISABLE == 1) begin assign dac_dds_data_1_s = 16'd0; @@ -212,7 +212,7 @@ module axi_ad9122_channel ( .dds_data (dac_dds_data_1_s)); end endgenerate - + generate if (DATAPATH_DISABLE == 1) begin assign dac_dds_data_2_s = 16'd0; @@ -227,7 +227,7 @@ module axi_ad9122_channel ( .dds_data (dac_dds_data_2_s)); end endgenerate - + generate if (DATAPATH_DISABLE == 1) begin assign dac_dds_data_3_s = 16'd0; @@ -242,10 +242,10 @@ module axi_ad9122_channel ( .dds_data (dac_dds_data_3_s)); end endgenerate - + // single channel processor - up_dac_channel #(.DAC_CHANNEL_ID(CHANNEL_ID)) i_up_dac_channel ( + up_dac_channel #(.CHANNEL_ID(CHANNEL_ID)) i_up_dac_channel ( .dac_clk (dac_div_clk), .dac_rst (dac_rst), .dac_dds_scale_1 (dac_dds_scale_1_s), @@ -257,6 +257,7 @@ module axi_ad9122_channel ( .dac_pat_data_1 (dac_pat_data_1_s), .dac_pat_data_2 (dac_pat_data_2_s), .dac_data_sel (dac_data_sel_s), + .dac_iq_mode (), .dac_iqcor_enb (), .dac_iqcor_coeff_1 (), .dac_iqcor_coeff_2 (), @@ -284,7 +285,7 @@ module axi_ad9122_channel ( .up_raddr (up_raddr), .up_rdata (up_rdata), .up_rack (up_rack)); - + endmodule // *************************************************************************** diff --git a/library/axi_ad9122/axi_ad9122_constr.sdc b/library/axi_ad9122/axi_ad9122_constr.sdc new file mode 100644 index 000000000..b562156b6 --- /dev/null +++ b/library/axi_ad9122/axi_ad9122_constr.sdc @@ -0,0 +1,3 @@ + +set_false_path -from [get_registers *up_drp_locked*] -to [get_registers *dac_status_m1*] + diff --git a/library/axi_ad9122/axi_ad9122_constr.xdc b/library/axi_ad9122/axi_ad9122_constr.xdc index a8b4a0c99..36143c266 100644 --- a/library/axi_ad9122/axi_ad9122_constr.xdc +++ b/library/axi_ad9122/axi_ad9122_constr.xdc @@ -1 +1,3 @@ -set_false_path -from [get_cells -hier -filter {name =~ *up_drp_locked_reg && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *dac_status_m1_reg && IS_SEQUENTIAL}] + +set_false_path -from [get_cells -hier -filter {name =~ *up_drp_locked_reg && IS_SEQUENTIAL}] \ + -to [get_cells -hier -filter {name =~ *dac_status_m1_reg && IS_SEQUENTIAL}] diff --git a/library/axi_ad9122/axi_ad9122_core.v b/library/axi_ad9122/axi_ad9122_core.v index e3c91a1e9..d3b79271c 100644 --- a/library/axi_ad9122/axi_ad9122_core.v +++ b/library/axi_ad9122/axi_ad9122_core.v @@ -156,8 +156,8 @@ module axi_ad9122_core ( output up_drp_sel; output up_drp_wr; output [11:0] up_drp_addr; - output [15:0] up_drp_wdata; - input [15:0] up_drp_rdata; + output [31:0] up_drp_wdata; + input [31:0] up_drp_rdata; input up_drp_ready; input up_drp_locked; @@ -278,6 +278,7 @@ module axi_ad9122_core ( .dac_rst (dac_rst), .dac_sync (dac_sync_out), .dac_frame (dac_frame_s), + .dac_clksel (), .dac_par_type (), .dac_par_enb (), .dac_r1_mode (), diff --git a/library/axi_ad9122/axi_ad9122_hw.tcl b/library/axi_ad9122/axi_ad9122_hw.tcl new file mode 100644 index 000000000..62ee04b0b --- /dev/null +++ b/library/axi_ad9122/axi_ad9122_hw.tcl @@ -0,0 +1,107 @@ + +package require -exact qsys 13.0 +source ../scripts/adi_env.tcl +source ../scripts/adi_ip_alt.tcl + +ad_ip_create axi_ad9122 {AXI AD9122 Interface} + +ad_ip_files axi_ad9122 [list \ + $ad_hdl_dir/library/common/ad_dds_sine.v \ + $ad_hdl_dir/library/common/ad_dds_1.v \ + $ad_hdl_dir/library/common/ad_dds.v \ + $ad_hdl_dir/library/altera/common/ad_mul.v \ + $ad_hdl_dir/library/common/ad_rst.v \ + $ad_hdl_dir/library/common/up_axi.v \ + $ad_hdl_dir/library/common/up_xfer_cntrl.v \ + $ad_hdl_dir/library/common/up_xfer_status.v \ + $ad_hdl_dir/library/common/up_clock_mon.v \ + $ad_hdl_dir/library/common/up_dac_common.v \ + $ad_hdl_dir/library/common/up_dac_channel.v \ + axi_ad9122_channel.v \ + axi_ad9122_core.v \ + axi_ad9122_if.v \ + axi_ad9122.v \ + $ad_hdl_dir/library/common/ad_axi_ip_constr.sdc \ + axi_ad9122_constr.sdc] \ + axi_ad9122_fileset + +# parameters + +add_parameter ID INTEGER 0 +set_parameter_property ID DEFAULT_VALUE 0 +set_parameter_property ID DISPLAY_NAME ID +set_parameter_property ID TYPE INTEGER +set_parameter_property ID UNITS None +set_parameter_property ID HDL_PARAMETER true + +add_parameter DEVICE_TYPE INTEGER 0 +set_parameter_property DEVICE_TYPE DEFAULT_VALUE 0 +set_parameter_property DEVICE_TYPE DISPLAY_NAME DEVICE_TYPE +set_parameter_property DEVICE_TYPE TYPE INTEGER +set_parameter_property DEVICE_TYPE UNITS None +set_parameter_property DEVICE_TYPE HDL_PARAMETER true + +# axi4 slave + +ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn + +# dac device interface + +add_interface device_if conduit end +set_interface_property device_if associatedClock none +set_interface_property device_if associatedReset none + +add_interface_port device_if dac_clk_in_p dac_clk_in_p Input 1 +add_interface_port device_if dac_clk_in_n dac_clk_in_n Input 1 +add_interface_port device_if dac_clk_out_p dac_clk_out_p Output 1 +add_interface_port device_if dac_clk_out_n dac_clk_out_n Output 1 +add_interface_port device_if dac_frame_out_p dac_frame_out_p Output 1 +add_interface_port device_if dac_frame_out_n dac_frame_out_n Output 1 +add_interface_port device_if dac_data_out_p dac_data_out_p Output 16 +add_interface_port device_if dac_data_out_n dac_data_out_n Output 16 + +add_interface_port device_if dac_sync_out dac_sync_out Output 1 +add_interface_port device_if dac_sync_in dac_sync_in Input 1 + +# dma interface + +ad_alt_intf clock dac_div_clk Output 1 + +add_interface dac_ch_0 conduit end +add_interface_port dac_ch_0 dac_valid_0 valid Output 1 +add_interface_port dac_ch_0 dac_enable_0 enable Output 1 +add_interface_port dac_ch_0 dac_ddata_0 data Input 64 +set_interface_property dac_ch_0 associatedClock if_dac_div_clk +set_interface_property dac_ch_0 associatedReset none + +add_interface dac_ch_1 conduit end +add_interface_port dac_ch_1 dac_valid_1 valid Output 1 +add_interface_port dac_ch_1 dac_enable_1 enable Output 1 +add_interface_port dac_ch_1 dac_ddata_1 data Input 64 +set_interface_property dac_ch_1 associatedClock if_dac_div_clk +set_interface_property dac_ch_1 associatedReset none + +ad_alt_intf signal dac_dovf input 1 ovf +ad_alt_intf signal dac_dunf input 1 unf + +# SERDES instances and configurations + +add_hdl_instance ad_serdes_clk_core_tx alt_serdes +set_instance_parameter_value ad_serdes_clk_core_tx {MODE} {CLK} +set_instance_parameter_value ad_serdes_clk_core_tx {DDR_OR_SDR_N} {1} +set_instance_parameter_value ad_serdes_clk_core_tx {SERDES_FACTOR} {8} +set_instance_parameter_value ad_serdes_clk_core_tx {CLKIN_FREQUENCY} {500.0} + +add_hdl_instance ad_serdes_out_core alt_serdes +set_instance_parameter_value ad_serdes_out_core {MODE} {OUT} +set_instance_parameter_value ad_serdes_out_core {DDR_OR_SDR_N} {1} +set_instance_parameter_value ad_serdes_out_core {SERDES_FACTOR} {8} +set_instance_parameter_value ad_serdes_out_core {CLKIN_FREQUENCY} {500.0} + +proc axi_ad9122_fileset { entityName } { + + ad_ip_modfile ad_serdes_out.v ad_serdes_out.v ad_serdes_out_core + ad_ip_modfile ad_serdes_clk.v ad_serdes_clk.v ad_serdes_clk_core_tx + +} + diff --git a/library/axi_ad9122/axi_ad9122_if.v b/library/axi_ad9122/axi_ad9122_if.v index cb7a437d7..4eb921561 100644 --- a/library/axi_ad9122/axi_ad9122_if.v +++ b/library/axi_ad9122/axi_ad9122_if.v @@ -1,9 +1,9 @@ // *************************************************************************** // *************************************************************************** // Copyright 2011(c) Analog Devices, Inc. -// +// // All rights reserved. -// +// // Redistribution and use in source and binary forms, with or without modification, // are permitted provided that the following conditions are met: // - Redistributions of source code must retain the above copyright @@ -21,16 +21,16 @@ // patent holders to use this software. // - Use of the software either in source or binary form, must be run // on or directly connected to an Analog Devices Inc. component. -// +// // THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, // INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A // PARTICULAR PURPOSE ARE DISCLAIMED. // // IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, // EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY -// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR // BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // *************************************************************************** // *************************************************************************** @@ -100,6 +100,11 @@ module axi_ad9122_if ( parameter DEVICE_TYPE = 0; parameter SERDES_OR_DDR_N = 1; parameter MMCM_OR_BUFIO_N = 1; + parameter MMCM_CLKIN_PERIOD = 1.667; + parameter MMCM_VCO_DIV = 6; + parameter MMCM_VCO_MUL = 12; + parameter MMCM_CLK0_DIV = 2; + parameter MMCM_CLK1_DIV = 8; parameter IO_DELAY_GROUP = "dac_if_delay_group"; // dac interface @@ -151,8 +156,8 @@ module axi_ad9122_if ( input up_drp_sel; input up_drp_wr; input [11:0] up_drp_addr; - input [15:0] up_drp_wdata; - output [15:0] up_drp_rdata; + input [31:0] up_drp_wdata; + output [31:0] up_drp_rdata; output up_drp_ready; output up_drp_locked; @@ -161,6 +166,11 @@ module axi_ad9122_if ( reg dac_status_m1 = 'd0; reg dac_status = 'd0; + // internal signals + + wire dac_out_clk; + wire loaden_s; + // dac status always @(posedge dac_div_clk) begin @@ -177,12 +187,13 @@ module axi_ad9122_if ( ad_serdes_out #( .DEVICE_TYPE (DEVICE_TYPE), - .SERDES_OR_DDR_N(SERDES_OR_DDR_N), - .DATA_WIDTH(16)) + .DDR_OR_SDR_N (SERDES_OR_DDR_N), + .DATA_WIDTH (16)) i_serdes_out_data ( .rst (dac_rst), .clk (dac_clk), .div_clk (dac_div_clk), + .loaden (loaden_s), .data_s0 (dac_data_i0), .data_s1 (dac_data_q0), .data_s2 (dac_data_i1), @@ -195,15 +206,16 @@ module axi_ad9122_if ( .data_out_n (dac_data_out_n)); // dac frame output serdes & buffer - + ad_serdes_out #( .DEVICE_TYPE (DEVICE_TYPE), - .SERDES_OR_DDR_N(SERDES_OR_DDR_N), - .DATA_WIDTH(1)) + .DDR_OR_SDR_N (SERDES_OR_DDR_N), + .DATA_WIDTH (1)) i_serdes_out_frame ( .rst (dac_rst), .clk (dac_clk), .div_clk (dac_div_clk), + .loaden (loaden_s), .data_s0 (dac_frame_i0), .data_s1 (dac_frame_q0), .data_s2 (dac_frame_i1), @@ -216,15 +228,16 @@ module axi_ad9122_if ( .data_out_n (dac_frame_out_n)); // dac clock output serdes & buffer - + ad_serdes_out #( .DEVICE_TYPE (DEVICE_TYPE), - .SERDES_OR_DDR_N(SERDES_OR_DDR_N), - .DATA_WIDTH(1)) + .DDR_OR_SDR_N (SERDES_OR_DDR_N), + .DATA_WIDTH (1)) i_serdes_out_clk ( .rst (dac_rst), .clk (dac_clk), .div_clk (dac_div_clk), + .loaden (loaden_s), .data_s0 (1'b1), .data_s1 (1'b0), .data_s2 (1'b1), @@ -239,20 +252,23 @@ module axi_ad9122_if ( // dac clock input buffers ad_serdes_clk #( - .SERDES_OR_DDR_N (SERDES_OR_DDR_N), + .DDR_OR_SDR_N (SERDES_OR_DDR_N), .MMCM_OR_BUFR_N (MMCM_OR_BUFIO_N), - .MMCM_DEVICE_TYPE (DEVICE_TYPE), - .MMCM_CLKIN_PERIOD (1.667), - .MMCM_VCO_DIV (6), - .MMCM_VCO_MUL (12), - .MMCM_CLK0_DIV (2), - .MMCM_CLK1_DIV (8)) + .DEVICE_TYPE (DEVICE_TYPE), + .MMCM_CLKIN_PERIOD (MMCM_CLKIN_PERIOD), + .MMCM_VCO_DIV (MMCM_VCO_DIV), + .MMCM_VCO_MUL (MMCM_VCO_MUL), + .MMCM_CLK0_DIV (MMCM_CLK0_DIV), + .MMCM_CLK1_DIV (MMCM_CLK1_DIV)) i_serdes_clk ( - .mmcm_rst (mmcm_rst), + .rst (mmcm_rst), .clk_in_p (dac_clk_in_p), .clk_in_n (dac_clk_in_n), .clk (dac_clk), .div_clk (dac_div_clk), + .out_clk (dac_out_clk), + .loaden (loaden_s), + .phase (), .up_clk (up_clk), .up_rstn (up_rstn), .up_drp_sel (up_drp_sel), diff --git a/library/axi_ad9122/axi_ad9122_ip.tcl b/library/axi_ad9122/axi_ad9122_ip.tcl index badf2c985..577439622 100644 --- a/library/axi_ad9122/axi_ad9122_ip.tcl +++ b/library/axi_ad9122/axi_ad9122_ip.tcl @@ -5,14 +5,14 @@ source $ad_hdl_dir/library/scripts/adi_ip.tcl adi_ip_create axi_ad9122 adi_ip_files axi_ad9122 [list \ - "$ad_hdl_dir/library/common/ad_mul.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_mul.v" \ "$ad_hdl_dir/library/common/ad_dds_sine.v" \ "$ad_hdl_dir/library/common/ad_dds_1.v" \ "$ad_hdl_dir/library/common/ad_dds.v" \ "$ad_hdl_dir/library/common/ad_rst.v" \ - "$ad_hdl_dir/library/common/ad_mmcm_drp.v" \ - "$ad_hdl_dir/library/common/ad_serdes_out.v" \ - "$ad_hdl_dir/library/common/ad_serdes_clk.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_mmcm_drp.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_serdes_out.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_serdes_clk.v" \ "$ad_hdl_dir/library/common/up_axi.v" \ "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ "$ad_hdl_dir/library/common/up_xfer_status.v" \ diff --git a/library/axi_ad9144/Makefile b/library/axi_ad9144/Makefile index 795b50715..12f3e8fb9 100644 --- a/library/axi_ad9144/Makefile +++ b/library/axi_ad9144/Makefile @@ -5,25 +5,25 @@ #################################################################################### #################################################################################### -M_DEPS := axi_ad9144_ip.tcl -M_DEPS += ../scripts/adi_env.tcl -M_DEPS += ../scripts/adi_ip.tcl M_DEPS += ../common/ad_axi_ip_constr.xdc -M_DEPS += ../common/ad_mul.v -M_DEPS += ../common/ad_dds_sine.v -M_DEPS += ../common/ad_dds_1.v M_DEPS += ../common/ad_dds.v +M_DEPS += ../common/ad_dds_1.v +M_DEPS += ../common/ad_dds_sine.v M_DEPS += ../common/ad_rst.v M_DEPS += ../common/up_axi.v +M_DEPS += ../common/up_clock_mon.v +M_DEPS += ../common/up_dac_channel.v +M_DEPS += ../common/up_dac_common.v M_DEPS += ../common/up_xfer_cntrl.v M_DEPS += ../common/up_xfer_status.v -M_DEPS += ../common/up_clock_mon.v -M_DEPS += ../common/up_dac_common.v -M_DEPS += ../common/up_dac_channel.v +M_DEPS += ../scripts/adi_env.tcl +M_DEPS += ../scripts/adi_ip.tcl +M_DEPS += ../xilinx/common/ad_mul.v +M_DEPS += axi_ad9144.v M_DEPS += axi_ad9144_channel.v M_DEPS += axi_ad9144_core.v M_DEPS += axi_ad9144_if.v -M_DEPS += axi_ad9144.v +M_DEPS += axi_ad9144_ip.tcl M_VIVADO := vivado -mode batch -source @@ -34,6 +34,10 @@ M_FLIST += *.log M_FLIST += component.xml M_FLIST += *.jou M_FLIST += xgui +M_FLIST += *.ip_user_files +M_FLIST += *.srcs +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil @@ -50,7 +54,7 @@ clean-all: axi_ad9144.xpr: $(M_DEPS) - rm -rf $(M_FLIST) + -rm -rf $(M_FLIST) $(M_VIVADO) axi_ad9144_ip.tcl >> axi_ad9144_ip.log 2>&1 #################################################################################### diff --git a/library/axi_ad9144/axi_ad9144.v b/library/axi_ad9144/axi_ad9144.v index aace45040..5aa391974 100644 --- a/library/axi_ad9144/axi_ad9144.v +++ b/library/axi_ad9144/axi_ad9144.v @@ -34,8 +34,6 @@ // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // *************************************************************************** // *************************************************************************** -// *************************************************************************** -// *************************************************************************** `timescale 1ns/100ps @@ -45,7 +43,9 @@ module axi_ad9144 ( // tx_clk is (line-rate/40) tx_clk, + tx_valid, tx_data, + tx_ready, // dma interface @@ -92,90 +92,93 @@ module axi_ad9144 ( // parameters parameter ID = 0; + parameter DEVICE_TYPE = 0; parameter QUAD_OR_DUAL_N = 1; parameter DAC_DATAPATH_DISABLE = 0; // jesd interface // tx_clk is (line-rate/40) - input tx_clk; - output [(128*QUAD_OR_DUAL_N)+127:0] tx_data; + input tx_clk; + output tx_valid; + output [(128*QUAD_OR_DUAL_N)+127:0] tx_data; + input tx_ready; // dma interface - output dac_clk; - output dac_valid_0; - output dac_enable_0; - input [63:0] dac_ddata_0; - output dac_valid_1; - output dac_enable_1; - input [63:0] dac_ddata_1; - output dac_valid_2; - output dac_enable_2; - input [63:0] dac_ddata_2; - output dac_valid_3; - output dac_enable_3; - input [63:0] dac_ddata_3; - input dac_dovf; - input dac_dunf; + output dac_clk; + output dac_valid_0; + output dac_enable_0; + input [63:0] dac_ddata_0; + output dac_valid_1; + output dac_enable_1; + input [63:0] dac_ddata_1; + output dac_valid_2; + output dac_enable_2; + input [63:0] dac_ddata_2; + output dac_valid_3; + output dac_enable_3; + input [63:0] dac_ddata_3; + input dac_dovf; + input dac_dunf; // axi interface - input s_axi_aclk; - input s_axi_aresetn; - input s_axi_awvalid; - input [ 31:0] s_axi_awaddr; - input [ 2:0] s_axi_awprot; - output s_axi_awready; - input s_axi_wvalid; - input [ 31:0] s_axi_wdata; - input [ 3:0] s_axi_wstrb; - output s_axi_wready; - output s_axi_bvalid; - output [ 1:0] s_axi_bresp; - input s_axi_bready; - input s_axi_arvalid; - input [ 31:0] s_axi_araddr; - input [ 2:0] s_axi_arprot; - output s_axi_arready; - output s_axi_rvalid; - output [ 31:0] s_axi_rdata; - output [ 1:0] s_axi_rresp; - input s_axi_rready; + input s_axi_aclk; + input s_axi_aresetn; + input s_axi_awvalid; + input [ 31:0] s_axi_awaddr; + input [ 2:0] s_axi_awprot; + output s_axi_awready; + input s_axi_wvalid; + input [ 31:0] s_axi_wdata; + input [ 3:0] s_axi_wstrb; + output s_axi_wready; + output s_axi_bvalid; + output [ 1:0] s_axi_bresp; + input s_axi_bready; + input s_axi_arvalid; + input [ 31:0] s_axi_araddr; + input [ 2:0] s_axi_arprot; + output s_axi_arready; + output s_axi_rvalid; + output [ 31:0] s_axi_rdata; + output [ 1:0] s_axi_rresp; + input s_axi_rready; // internal clocks and resets - wire dac_rst; - wire up_clk; - wire up_rstn; + wire dac_rst; + wire up_clk; + wire up_rstn; // internal signals - wire [255:0] tx_data_s; - wire [ 15:0] dac_data_0_0_s; - wire [ 15:0] dac_data_0_1_s; - wire [ 15:0] dac_data_0_2_s; - wire [ 15:0] dac_data_0_3_s; - wire [ 15:0] dac_data_1_0_s; - wire [ 15:0] dac_data_1_1_s; - wire [ 15:0] dac_data_1_2_s; - wire [ 15:0] dac_data_1_3_s; - wire [ 15:0] dac_data_2_0_s; - wire [ 15:0] dac_data_2_1_s; - wire [ 15:0] dac_data_2_2_s; - wire [ 15:0] dac_data_2_3_s; - wire [ 15:0] dac_data_3_0_s; - wire [ 15:0] dac_data_3_1_s; - wire [ 15:0] dac_data_3_2_s; - wire [ 15:0] dac_data_3_3_s; - wire up_wreq_s; - wire [ 13:0] up_waddr_s; - wire [ 31:0] up_wdata_s; - wire up_wack_s; - wire up_rreq_s; - wire [ 13:0] up_raddr_s; - wire [ 31:0] up_rdata_s; - wire up_rack_s; + wire [255:0] tx_data_s; + wire [ 15:0] dac_data_0_0_s; + wire [ 15:0] dac_data_0_1_s; + wire [ 15:0] dac_data_0_2_s; + wire [ 15:0] dac_data_0_3_s; + wire [ 15:0] dac_data_1_0_s; + wire [ 15:0] dac_data_1_1_s; + wire [ 15:0] dac_data_1_2_s; + wire [ 15:0] dac_data_1_3_s; + wire [ 15:0] dac_data_2_0_s; + wire [ 15:0] dac_data_2_1_s; + wire [ 15:0] dac_data_2_2_s; + wire [ 15:0] dac_data_2_3_s; + wire [ 15:0] dac_data_3_0_s; + wire [ 15:0] dac_data_3_1_s; + wire [ 15:0] dac_data_3_2_s; + wire [ 15:0] dac_data_3_3_s; + wire up_wreq_s; + wire [ 13:0] up_waddr_s; + wire [ 31:0] up_wdata_s; + wire up_wack_s; + wire up_rreq_s; + wire [ 13:0] up_raddr_s; + wire [ 31:0] up_rdata_s; + wire up_rack_s; // signal name changes @@ -184,11 +187,12 @@ module axi_ad9144 ( // dual/quad cores + assign tx_valid = 1'b1; assign tx_data = (QUAD_OR_DUAL_N == 1) ? tx_data_s : tx_data_s[127:0]; // device interface - axi_ad9144_if i_if ( + axi_ad9144_if #(.DEVICE_TYPE (DEVICE_TYPE)) i_if ( .tx_clk (tx_clk), .tx_data (tx_data_s), .dac_clk (dac_clk), diff --git a/library/axi_ad9144/axi_ad9144_channel.v b/library/axi_ad9144/axi_ad9144_channel.v index d079f0707..7794a4a5c 100644 --- a/library/axi_ad9144/axi_ad9144_channel.v +++ b/library/axi_ad9144/axi_ad9144_channel.v @@ -34,8 +34,6 @@ // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // *************************************************************************** // *************************************************************************** -// *************************************************************************** -// *************************************************************************** `timescale 1ns/100ps @@ -104,8 +102,6 @@ module axi_ad9144_channel ( reg [63:0] dac_data = 'd0; reg [63:0] dac_pn7_data = 'd0; reg [63:0] dac_pn15_data = 'd0; - reg [63:0] dac_pn23_data = 'd0; - reg [63:0] dac_pn31_data = 'd0; reg [15:0] dac_dds_phase_0_0 = 'd0; reg [15:0] dac_dds_phase_0_1 = 'd0; reg [15:0] dac_dds_phase_1_0 = 'd0; @@ -133,312 +129,174 @@ module axi_ad9144_channel ( wire [15:0] dac_pat_data_1_s; wire [15:0] dac_pat_data_2_s; wire [ 3:0] dac_data_sel_s; + wire [63:0] dac_pn7_data_i_s; + wire [63:0] dac_pn15_data_i_s; + wire [63:0] dac_pn7_data_s; + wire [63:0] dac_pn15_data_s; - // pn7 function + // PN7 function function [63:0] pn7; - input [63:0] din; + input [7:0] din; reg [63:0] dout; begin - dout[63] = din[ 7] ^ din[ 6]; - dout[62] = din[ 6] ^ din[ 5]; - dout[61] = din[ 5] ^ din[ 4]; - dout[60] = din[ 4] ^ din[ 3]; - dout[59] = din[ 3] ^ din[ 2]; - dout[58] = din[ 2] ^ din[ 1]; - dout[57] = din[ 1] ^ din[ 0]; - dout[56] = din[ 0] ^ din[ 7] ^ din[ 6]; - dout[55] = din[ 7] ^ din[ 5]; - dout[54] = din[ 6] ^ din[ 4]; - dout[53] = din[ 5] ^ din[ 3]; - dout[52] = din[ 4] ^ din[ 2]; - dout[51] = din[ 3] ^ din[ 1]; - dout[50] = din[ 2] ^ din[ 0]; - dout[49] = din[ 1] ^ din[ 7] ^ din[ 6]; - dout[48] = din[ 0] ^ din[ 6] ^ din[ 5]; - dout[47] = din[ 7] ^ din[ 5] ^ din[ 6] ^ din[ 4]; - dout[46] = din[ 6] ^ din[ 4] ^ din[ 5] ^ din[ 3]; - dout[45] = din[ 5] ^ din[ 3] ^ din[ 4] ^ din[ 2]; - dout[44] = din[ 4] ^ din[ 2] ^ din[ 3] ^ din[ 1]; - dout[43] = din[ 3] ^ din[ 1] ^ din[ 2] ^ din[ 0]; - dout[42] = din[ 2] ^ din[ 0] ^ din[ 1] ^ din[ 7] ^ din[ 6]; - dout[41] = din[ 1] ^ din[ 7] ^ din[ 0] ^ din[ 5]; - dout[40] = din[ 0] ^ din[ 7] ^ din[ 4]; - dout[39] = din[ 7] ^ din[ 3]; - dout[38] = din[ 6] ^ din[ 2]; - dout[37] = din[ 5] ^ din[ 1]; - dout[36] = din[ 4] ^ din[ 0]; - dout[35] = din[ 3] ^ din[ 7] ^ din[ 6]; - dout[34] = din[ 2] ^ din[ 6] ^ din[ 5]; - dout[33] = din[ 1] ^ din[ 5] ^ din[ 4]; - dout[32] = din[ 0] ^ din[ 4] ^ din[ 3]; - dout[31] = din[ 7] ^ din[ 3] ^ din[ 6] ^ din[ 2]; - dout[30] = din[ 6] ^ din[ 2] ^ din[ 5] ^ din[ 1]; - dout[29] = din[ 5] ^ din[ 1] ^ din[ 4] ^ din[ 0]; - dout[28] = din[ 4] ^ din[ 0] ^ din[ 3] ^ din[ 7] ^ din[ 6]; - dout[27] = din[ 3] ^ din[ 7] ^ din[ 2] ^ din[ 5]; - dout[26] = din[ 2] ^ din[ 6] ^ din[ 1] ^ din[ 4]; - dout[25] = din[ 1] ^ din[ 5] ^ din[ 0] ^ din[ 3]; - dout[24] = din[ 0] ^ din[ 4] ^ din[ 7] ^ din[ 6] ^ din[ 2]; - dout[23] = din[ 7] ^ din[ 3] ^ din[ 5] ^ din[ 1]; - dout[22] = din[ 6] ^ din[ 2] ^ din[ 4] ^ din[ 0]; - dout[21] = din[ 5] ^ din[ 1] ^ din[ 3] ^ din[ 7] ^ din[ 6]; - dout[20] = din[ 4] ^ din[ 0] ^ din[ 6] ^ din[ 2] ^ din[ 5]; - dout[19] = din[ 3] ^ din[ 7] ^ din[ 5] ^ din[ 6] ^ din[ 1] ^ din[ 4]; - dout[18] = din[ 2] ^ din[ 6] ^ din[ 4] ^ din[ 5] ^ din[ 0] ^ din[ 3]; - dout[17] = din[ 1] ^ din[ 5] ^ din[ 3] ^ din[ 4] ^ din[ 7] ^ din[ 6] ^ din[ 2]; - dout[16] = din[ 0] ^ din[ 4] ^ din[ 6] ^ din[ 2] ^ din[ 3] ^ din[ 5] ^ din[ 1]; - dout[15] = din[ 7] ^ din[ 3] ^ din[ 5] ^ din[ 1] ^ din[ 6] ^ din[ 2] ^ din[ 4] ^ din[ 0]; - dout[14] = din[ 2] ^ din[ 4] ^ din[ 0] ^ din[ 5] ^ din[ 1] ^ din[ 3] ^ din[ 7]; - dout[13] = din[ 1] ^ din[ 3] ^ din[ 7] ^ din[ 4] ^ din[ 0] ^ din[ 2]; - dout[12] = din[ 0] ^ din[ 2] ^ din[ 3] ^ din[ 7] ^ din[ 1]; - dout[11] = din[ 7] ^ din[ 1] ^ din[ 2] ^ din[ 0]; - dout[10] = din[ 0] ^ din[ 1] ^ din[ 7]; - dout[ 9] = din[ 7] ^ din[ 0]; - dout[ 8] = din[ 7]; - dout[ 7] = din[ 6]; - dout[ 6] = din[ 5]; - dout[ 5] = din[ 4]; - dout[ 4] = din[ 3]; - dout[ 3] = din[ 2]; - dout[ 2] = din[ 1]; - dout[ 1] = din[ 0]; - dout[ 0] = din[ 7] ^ din[ 6]; + dout[15] = din[ 6] ^ din[ 5]; + dout[14] = din[ 5] ^ din[ 4]; + dout[13] = din[ 4] ^ din[ 3]; + dout[12] = din[ 3] ^ din[ 2]; + dout[11] = din[ 2] ^ din[ 1]; + dout[10] = din[ 1] ^ din[ 0]; + dout[ 9] = din[ 0] ^ din[ 6] ^ din[ 5]; + dout[ 8] = din[ 6] ^ din[ 4]; + dout[ 7] = din[ 5] ^ din[ 3]; + dout[ 6] = din[ 4] ^ din[ 2]; + dout[ 5] = din[ 3] ^ din[ 1]; + dout[ 4] = din[ 2] ^ din[ 0]; + dout[ 3] = din[ 1] ^ din[ 6] ^ din[ 5]; + dout[ 2] = din[ 0] ^ din[ 5] ^ din[ 4]; + dout[ 1] = din[ 6] ^ din[ 4] ^ din[ 5] ^ din[ 3]; + dout[ 0] = din[ 5] ^ din[ 3] ^ din[ 4] ^ din[ 2]; + dout[31] = din[ 4] ^ din[ 2] ^ din[ 3] ^ din[ 1]; + dout[30] = din[ 3] ^ din[ 1] ^ din[ 2] ^ din[ 0]; + dout[29] = din[ 2] ^ din[ 0] ^ din[ 1] ^ din[ 6] ^ din[ 5]; + dout[28] = din[ 1] ^ din[ 6] ^ din[ 0] ^ din[ 4]; + dout[27] = din[ 0] ^ din[ 6] ^ din[ 3]; + dout[26] = din[ 6] ^ din[ 2]; + dout[25] = din[ 5] ^ din[ 1]; + dout[24] = din[ 4] ^ din[ 0]; + dout[23] = din[ 3] ^ din[ 6] ^ din[ 5]; + dout[22] = din[ 2] ^ din[ 5] ^ din[ 4]; + dout[21] = din[ 1] ^ din[ 4] ^ din[ 3]; + dout[20] = din[ 0] ^ din[ 3] ^ din[ 2]; + dout[19] = din[ 6] ^ din[ 2] ^ din[ 5] ^ din[ 1]; + dout[18] = din[ 5] ^ din[ 1] ^ din[ 4] ^ din[ 0]; + dout[17] = din[ 4] ^ din[ 0] ^ din[ 3] ^ din[ 6] ^ din[ 5]; + dout[16] = din[ 3] ^ din[ 6] ^ din[ 2] ^ din[ 4]; + dout[47] = din[ 2] ^ din[ 5] ^ din[ 1] ^ din[ 3]; + dout[46] = din[ 1] ^ din[ 4] ^ din[ 0] ^ din[ 2]; + dout[45] = din[ 0] ^ din[ 3] ^ din[ 6] ^ din[ 5] ^ din[ 1]; + dout[44] = din[ 6] ^ din[ 2] ^ din[ 4] ^ din[ 0]; + dout[43] = din[ 1] ^ din[ 3] ^ din[ 6]; + dout[42] = din[ 0] ^ din[ 5] ^ din[ 2]; + dout[41] = din[ 6] ^ din[ 4] ^ din[ 5] ^ din[ 1]; + dout[40] = din[ 5] ^ din[ 3] ^ din[ 4] ^ din[ 0]; + dout[39] = din[ 4] ^ din[ 2] ^ din[ 3] ^ din[ 6] ^ din[ 5]; + dout[38] = din[ 3] ^ din[ 5] ^ din[ 1] ^ din[ 2] ^ din[ 4]; + dout[37] = din[ 2] ^ din[ 4] ^ din[ 0] ^ din[ 1] ^ din[ 3]; + dout[36] = din[ 1] ^ din[ 3] ^ din[ 6] ^ din[ 0] ^ din[ 5] ^ din[ 2]; + dout[35] = din[ 0] ^ din[ 2] ^ din[ 6] ^ din[ 4] ^ din[ 1]; + dout[34] = din[ 6] ^ din[ 1] ^ din[ 3] ^ din[ 0]; + dout[33] = din[ 0] ^ din[ 2] ^ din[ 6]; + dout[32] = din[ 6] ^ din[ 1]; + dout[63] = din[ 5] ^ din[ 0]; + dout[62] = din[ 4] ^ din[ 6] ^ din[ 5]; + dout[61] = din[ 3] ^ din[ 5] ^ din[ 4]; + dout[60] = din[ 2] ^ din[ 4] ^ din[ 3]; + dout[59] = din[ 1] ^ din[ 3] ^ din[ 2]; + dout[58] = din[ 0] ^ din[ 2] ^ din[ 1]; + dout[57] = din[ 6] ^ din[ 1] ^ din[ 5] ^ din[ 0]; + dout[56] = din[ 0] ^ din[ 4] ^ din[ 6]; + dout[55] = din[ 6] ^ din[ 3]; + dout[54] = din[ 5] ^ din[ 2]; + dout[53] = din[ 4] ^ din[ 1]; + dout[52] = din[ 3] ^ din[ 0]; + dout[51] = din[ 2] ^ din[ 6] ^ din[ 5]; + dout[50] = din[ 1] ^ din[ 5] ^ din[ 4]; + dout[49] = din[ 0] ^ din[ 4] ^ din[ 3]; + dout[48] = din[ 6] ^ din[ 3] ^ din[ 5] ^ din[ 2]; pn7 = dout; end endfunction - - // pn15 function + + // PN15 function function [63:0] pn15; - input [63:0] din; + input [15:0] din; reg [63:0] dout; begin - dout[63] = din[15] ^ din[14]; - dout[62] = din[14] ^ din[13]; - dout[61] = din[13] ^ din[12]; - dout[60] = din[12] ^ din[11]; - dout[59] = din[11] ^ din[10]; - dout[58] = din[10] ^ din[ 9]; - dout[57] = din[ 9] ^ din[ 8]; - dout[56] = din[ 8] ^ din[ 7]; - dout[55] = din[ 7] ^ din[ 6]; - dout[54] = din[ 6] ^ din[ 5]; - dout[53] = din[ 5] ^ din[ 4]; - dout[52] = din[ 4] ^ din[ 3]; - dout[51] = din[ 3] ^ din[ 2]; - dout[50] = din[ 2] ^ din[ 1]; - dout[49] = din[ 1] ^ din[ 0]; - dout[48] = din[ 0] ^ din[15] ^ din[14]; - dout[47] = din[15] ^ din[13]; - dout[46] = din[14] ^ din[12]; - dout[45] = din[13] ^ din[11]; - dout[44] = din[12] ^ din[10]; - dout[43] = din[11] ^ din[ 9]; - dout[42] = din[10] ^ din[ 8]; - dout[41] = din[ 9] ^ din[ 7]; - dout[40] = din[ 8] ^ din[ 6]; - dout[39] = din[ 7] ^ din[ 5]; - dout[38] = din[ 6] ^ din[ 4]; - dout[37] = din[ 5] ^ din[ 3]; - dout[36] = din[ 4] ^ din[ 2]; - dout[35] = din[ 3] ^ din[ 1]; - dout[34] = din[ 2] ^ din[ 0]; - dout[33] = din[ 1] ^ din[15] ^ din[14]; - dout[32] = din[ 0] ^ din[14] ^ din[13]; - dout[31] = din[15] ^ din[13] ^ din[14] ^ din[12]; - dout[30] = din[14] ^ din[12] ^ din[13] ^ din[11]; - dout[29] = din[13] ^ din[11] ^ din[12] ^ din[10]; - dout[28] = din[12] ^ din[10] ^ din[11] ^ din[ 9]; - dout[27] = din[11] ^ din[ 9] ^ din[10] ^ din[ 8]; - dout[26] = din[10] ^ din[ 8] ^ din[ 9] ^ din[ 7]; - dout[25] = din[ 9] ^ din[ 7] ^ din[ 8] ^ din[ 6]; - dout[24] = din[ 8] ^ din[ 6] ^ din[ 7] ^ din[ 5]; - dout[23] = din[ 7] ^ din[ 5] ^ din[ 6] ^ din[ 4]; - dout[22] = din[ 6] ^ din[ 4] ^ din[ 5] ^ din[ 3]; - dout[21] = din[ 5] ^ din[ 3] ^ din[ 4] ^ din[ 2]; - dout[20] = din[ 4] ^ din[ 2] ^ din[ 3] ^ din[ 1]; - dout[19] = din[ 3] ^ din[ 1] ^ din[ 2] ^ din[ 0]; - dout[18] = din[ 2] ^ din[ 0] ^ din[ 1] ^ din[15] ^ din[14]; - dout[17] = din[ 1] ^ din[15] ^ din[ 0] ^ din[13]; - dout[16] = din[ 0] ^ din[15] ^ din[12]; - dout[15] = din[15] ^ din[11]; - dout[14] = din[14] ^ din[10]; - dout[13] = din[13] ^ din[ 9]; - dout[12] = din[12] ^ din[ 8]; - dout[11] = din[11] ^ din[ 7]; - dout[10] = din[10] ^ din[ 6]; - dout[ 9] = din[ 9] ^ din[ 5]; - dout[ 8] = din[ 8] ^ din[ 4]; - dout[ 7] = din[ 7] ^ din[ 3]; - dout[ 6] = din[ 6] ^ din[ 2]; - dout[ 5] = din[ 5] ^ din[ 1]; - dout[ 4] = din[ 4] ^ din[ 0]; - dout[ 3] = din[ 3] ^ din[15] ^ din[14]; - dout[ 2] = din[ 2] ^ din[14] ^ din[13]; - dout[ 1] = din[ 1] ^ din[13] ^ din[12]; - dout[ 0] = din[ 0] ^ din[12] ^ din[11]; + dout[15] = din[14] ^ din[13]; + dout[14] = din[13] ^ din[12]; + dout[13] = din[12] ^ din[11]; + dout[12] = din[11] ^ din[10]; + dout[11] = din[10] ^ din[ 9]; + dout[10] = din[ 9] ^ din[ 8]; + dout[ 9] = din[ 8] ^ din[ 7]; + dout[ 8] = din[ 7] ^ din[ 6]; + dout[ 7] = din[ 6] ^ din[ 5]; + dout[ 6] = din[ 5] ^ din[ 4]; + dout[ 5] = din[ 4] ^ din[ 3]; + dout[ 4] = din[ 3] ^ din[ 2]; + dout[ 3] = din[ 2] ^ din[ 1]; + dout[ 2] = din[ 1] ^ din[ 0]; + dout[ 1] = din[ 0] ^ din[14] ^ din[13]; + dout[ 0] = din[14] ^ din[12]; + dout[31] = din[13] ^ din[11]; + dout[30] = din[12] ^ din[10]; + dout[29] = din[11] ^ din[ 9]; + dout[28] = din[10] ^ din[ 8]; + dout[27] = din[ 9] ^ din[ 7]; + dout[26] = din[ 8] ^ din[ 6]; + dout[25] = din[ 7] ^ din[ 5]; + dout[24] = din[ 6] ^ din[ 4]; + dout[23] = din[ 5] ^ din[ 3]; + dout[22] = din[ 4] ^ din[ 2]; + dout[21] = din[ 3] ^ din[ 1]; + dout[20] = din[ 2] ^ din[ 0]; + dout[19] = din[ 1] ^ din[14] ^ din[13]; + dout[18] = din[ 0] ^ din[13] ^ din[12]; + dout[17] = din[14] ^ din[12] ^ din[13] ^ din[11]; + dout[16] = din[13] ^ din[11] ^ din[12] ^ din[10]; + dout[47] = din[12] ^ din[10] ^ din[11] ^ din[ 9]; + dout[46] = din[11] ^ din[ 9] ^ din[10] ^ din[ 8]; + dout[45] = din[10] ^ din[ 8] ^ din[ 9] ^ din[ 7]; + dout[44] = din[ 9] ^ din[ 7] ^ din[ 8] ^ din[ 6]; + dout[43] = din[ 8] ^ din[ 6] ^ din[ 7] ^ din[ 5]; + dout[42] = din[ 7] ^ din[ 5] ^ din[ 6] ^ din[ 4]; + dout[41] = din[ 6] ^ din[ 4] ^ din[ 5] ^ din[ 3]; + dout[40] = din[ 5] ^ din[ 3] ^ din[ 4] ^ din[ 2]; + dout[39] = din[ 4] ^ din[ 2] ^ din[ 3] ^ din[ 1]; + dout[38] = din[ 3] ^ din[ 1] ^ din[ 2] ^ din[ 0]; + dout[37] = din[ 2] ^ din[ 0] ^ din[ 1] ^ din[14] ^ din[13]; + dout[36] = din[ 1] ^ din[14] ^ din[ 0] ^ din[12]; + dout[35] = din[ 0] ^ din[14] ^ din[11]; + dout[34] = din[14] ^ din[10]; + dout[33] = din[13] ^ din[ 9]; + dout[32] = din[12] ^ din[ 8]; + dout[63] = din[11] ^ din[ 7]; + dout[62] = din[10] ^ din[ 6]; + dout[61] = din[ 9] ^ din[ 5]; + dout[60] = din[ 8] ^ din[ 4]; + dout[59] = din[ 7] ^ din[ 3]; + dout[58] = din[ 6] ^ din[ 2]; + dout[57] = din[ 5] ^ din[ 1]; + dout[56] = din[ 4] ^ din[ 0]; + dout[55] = din[ 3] ^ din[14] ^ din[13]; + dout[54] = din[ 2] ^ din[13] ^ din[12]; + dout[53] = din[ 1] ^ din[12] ^ din[11]; + dout[52] = din[ 0] ^ din[11] ^ din[10]; + dout[51] = din[14] ^ din[10] ^ din[13] ^ din[ 9]; + dout[50] = din[13] ^ din[ 9] ^ din[12] ^ din[ 8]; + dout[49] = din[12] ^ din[ 8] ^ din[11] ^ din[ 7]; + dout[48] = din[11] ^ din[ 7] ^ din[10] ^ din[ 6]; pn15 = dout; end endfunction - // pn23 function + assign dac_pn7_data_i_s = ~dac_pn7_data; + assign dac_pn15_data_i_s = ~dac_pn15_data; - function [63:0] pn23; - input [63:0] din; - reg [63:0] dout; - begin - dout[63] = din[23] ^ din[18]; - dout[62] = din[22] ^ din[17]; - dout[61] = din[21] ^ din[16]; - dout[60] = din[20] ^ din[15]; - dout[59] = din[19] ^ din[14]; - dout[58] = din[18] ^ din[13]; - dout[57] = din[17] ^ din[12]; - dout[56] = din[16] ^ din[11]; - dout[55] = din[15] ^ din[10]; - dout[54] = din[14] ^ din[ 9]; - dout[53] = din[13] ^ din[ 8]; - dout[52] = din[12] ^ din[ 7]; - dout[51] = din[11] ^ din[ 6]; - dout[50] = din[10] ^ din[ 5]; - dout[49] = din[ 9] ^ din[ 4]; - dout[48] = din[ 8] ^ din[ 3]; - dout[47] = din[ 7] ^ din[ 2]; - dout[46] = din[ 6] ^ din[ 1]; - dout[45] = din[ 5] ^ din[ 0]; - dout[44] = din[ 4] ^ din[23] ^ din[18]; - dout[43] = din[ 3] ^ din[22] ^ din[17]; - dout[42] = din[ 2] ^ din[21] ^ din[16]; - dout[41] = din[ 1] ^ din[20] ^ din[15]; - dout[40] = din[ 0] ^ din[19] ^ din[14]; - dout[39] = din[23] ^ din[13]; - dout[38] = din[22] ^ din[12]; - dout[37] = din[21] ^ din[11]; - dout[36] = din[20] ^ din[10]; - dout[35] = din[19] ^ din[ 9]; - dout[34] = din[18] ^ din[ 8]; - dout[33] = din[17] ^ din[ 7]; - dout[32] = din[16] ^ din[ 6]; - dout[31] = din[15] ^ din[ 5]; - dout[30] = din[14] ^ din[ 4]; - dout[29] = din[13] ^ din[ 3]; - dout[28] = din[12] ^ din[ 2]; - dout[27] = din[11] ^ din[ 1]; - dout[26] = din[10] ^ din[ 0]; - dout[25] = din[ 9] ^ din[23] ^ din[18]; - dout[24] = din[ 8] ^ din[22] ^ din[17]; - dout[23] = din[ 7] ^ din[21] ^ din[16]; - dout[22] = din[ 6] ^ din[20] ^ din[15]; - dout[21] = din[ 5] ^ din[19] ^ din[14]; - dout[20] = din[ 4] ^ din[18] ^ din[13]; - dout[19] = din[ 3] ^ din[17] ^ din[12]; - dout[18] = din[ 2] ^ din[16] ^ din[11]; - dout[17] = din[ 1] ^ din[15] ^ din[10]; - dout[16] = din[ 0] ^ din[14] ^ din[ 9]; - dout[15] = din[23] ^ din[13] ^ din[18] ^ din[ 8]; - dout[14] = din[22] ^ din[12] ^ din[17] ^ din[ 7]; - dout[13] = din[21] ^ din[11] ^ din[16] ^ din[ 6]; - dout[12] = din[20] ^ din[10] ^ din[15] ^ din[ 5]; - dout[11] = din[19] ^ din[ 9] ^ din[14] ^ din[ 4]; - dout[10] = din[18] ^ din[ 8] ^ din[13] ^ din[ 3]; - dout[ 9] = din[17] ^ din[ 7] ^ din[12] ^ din[ 2]; - dout[ 8] = din[16] ^ din[ 6] ^ din[11] ^ din[ 1]; - dout[ 7] = din[15] ^ din[ 5] ^ din[10] ^ din[ 0]; - dout[ 6] = din[14] ^ din[ 4] ^ din[ 9] ^ din[23] ^ din[18]; - dout[ 5] = din[13] ^ din[ 3] ^ din[ 8] ^ din[22] ^ din[17]; - dout[ 4] = din[12] ^ din[ 2] ^ din[ 7] ^ din[21] ^ din[16]; - dout[ 3] = din[11] ^ din[ 1] ^ din[ 6] ^ din[20] ^ din[15]; - dout[ 2] = din[10] ^ din[ 0] ^ din[ 5] ^ din[19] ^ din[14]; - dout[ 1] = din[ 9] ^ din[23] ^ din[ 4] ^ din[13]; - dout[ 0] = din[ 8] ^ din[22] ^ din[ 3] ^ din[12]; - pn23 = dout; - end - endfunction - - // pn31 function - - function [63:0] pn31; - input [63:0] din; - reg [63:0] dout; - begin - dout[63] = din[31] ^ din[28]; - dout[62] = din[30] ^ din[27]; - dout[61] = din[29] ^ din[26]; - dout[60] = din[28] ^ din[25]; - dout[59] = din[27] ^ din[24]; - dout[58] = din[26] ^ din[23]; - dout[57] = din[25] ^ din[22]; - dout[56] = din[24] ^ din[21]; - dout[55] = din[23] ^ din[20]; - dout[54] = din[22] ^ din[19]; - dout[53] = din[21] ^ din[18]; - dout[52] = din[20] ^ din[17]; - dout[51] = din[19] ^ din[16]; - dout[50] = din[18] ^ din[15]; - dout[49] = din[17] ^ din[14]; - dout[48] = din[16] ^ din[13]; - dout[47] = din[15] ^ din[12]; - dout[46] = din[14] ^ din[11]; - dout[45] = din[13] ^ din[10]; - dout[44] = din[12] ^ din[ 9]; - dout[43] = din[11] ^ din[ 8]; - dout[42] = din[10] ^ din[ 7]; - dout[41] = din[ 9] ^ din[ 6]; - dout[40] = din[ 8] ^ din[ 5]; - dout[39] = din[ 7] ^ din[ 4]; - dout[38] = din[ 6] ^ din[ 3]; - dout[37] = din[ 5] ^ din[ 2]; - dout[36] = din[ 4] ^ din[ 1]; - dout[35] = din[ 3] ^ din[ 0]; - dout[34] = din[ 2] ^ din[31] ^ din[28]; - dout[33] = din[ 1] ^ din[30] ^ din[27]; - dout[32] = din[ 0] ^ din[29] ^ din[26]; - dout[31] = din[31] ^ din[25]; - dout[30] = din[30] ^ din[24]; - dout[29] = din[29] ^ din[23]; - dout[28] = din[28] ^ din[22]; - dout[27] = din[27] ^ din[21]; - dout[26] = din[26] ^ din[20]; - dout[25] = din[25] ^ din[19]; - dout[24] = din[24] ^ din[18]; - dout[23] = din[23] ^ din[17]; - dout[22] = din[22] ^ din[16]; - dout[21] = din[21] ^ din[15]; - dout[20] = din[20] ^ din[14]; - dout[19] = din[19] ^ din[13]; - dout[18] = din[18] ^ din[12]; - dout[17] = din[17] ^ din[11]; - dout[16] = din[16] ^ din[10]; - dout[15] = din[15] ^ din[ 9]; - dout[14] = din[14] ^ din[ 8]; - dout[13] = din[13] ^ din[ 7]; - dout[12] = din[12] ^ din[ 6]; - dout[11] = din[11] ^ din[ 5]; - dout[10] = din[10] ^ din[ 4]; - dout[ 9] = din[ 9] ^ din[ 3]; - dout[ 8] = din[ 8] ^ din[ 2]; - dout[ 7] = din[ 7] ^ din[ 1]; - dout[ 6] = din[ 6] ^ din[ 0]; - dout[ 5] = din[ 5] ^ din[31] ^ din[28]; - dout[ 4] = din[ 4] ^ din[30] ^ din[27]; - dout[ 3] = din[ 3] ^ din[29] ^ din[26]; - dout[ 2] = din[ 2] ^ din[28] ^ din[25]; - dout[ 1] = din[ 1] ^ din[27] ^ din[24]; - dout[ 0] = din[ 0] ^ din[26] ^ din[23]; - pn31 = dout; - end - endfunction + assign dac_pn7_data_s = dac_pn7_data; + assign dac_pn15_data_s = dac_pn15_data; // dac data select always @(posedge dac_clk) begin dac_enable <= (dac_data_sel_s == 4'h2) ? 1'b1 : 1'b0; case (dac_data_sel_s) - 4'h7: dac_data <= dac_pn31_data; - 4'h6: dac_data <= dac_pn23_data; - 4'h5: dac_data <= dac_pn15_data; - 4'h4: dac_data <= dac_pn7_data; + 4'h7: dac_data <= dac_pn15_data_s; + 4'h6: dac_data <= dac_pn7_data_s; + 4'h5: dac_data <= dac_pn15_data_i_s; + 4'h4: dac_data <= dac_pn7_data_i_s; 4'h3: dac_data <= 64'd0; 4'h2: dac_data <= dma_data; 4'h1: dac_data <= { dac_pat_data_2_s, dac_pat_data_1_s, @@ -453,13 +311,9 @@ module axi_ad9144_channel ( if (dac_data_sync == 1'b1) begin dac_pn7_data <= {64{1'd1}}; dac_pn15_data <= {64{1'd1}}; - dac_pn23_data <= {64{1'd1}}; - dac_pn31_data <= {64{1'd1}}; end else begin - dac_pn7_data <= pn7(dac_pn7_data); - dac_pn15_data <= pn15(dac_pn15_data); - dac_pn23_data <= pn23(dac_pn23_data); - dac_pn31_data <= pn31(dac_pn31_data); + dac_pn7_data <= pn7(dac_pn7_data[55:48]); + dac_pn15_data <= pn15(dac_pn15_data[63:48]); end end @@ -556,7 +410,7 @@ module axi_ad9144_channel ( // single channel processor - up_dac_channel #(.DAC_CHANNEL_ID(CHANNEL_ID)) i_up_dac_channel ( + up_dac_channel #(.CHANNEL_ID(CHANNEL_ID)) i_up_dac_channel ( .dac_clk (dac_clk), .dac_rst (dac_rst), .dac_dds_scale_1 (dac_dds_scale_1_s), @@ -568,6 +422,7 @@ module axi_ad9144_channel ( .dac_pat_data_1 (dac_pat_data_1_s), .dac_pat_data_2 (dac_pat_data_2_s), .dac_data_sel (dac_data_sel_s), + .dac_iq_mode (), .dac_iqcor_enb (), .dac_iqcor_coeff_1 (), .dac_iqcor_coeff_2 (), @@ -600,3 +455,7 @@ endmodule // *************************************************************************** // *************************************************************************** + + + + diff --git a/library/axi_ad9144/axi_ad9144_core.v b/library/axi_ad9144/axi_ad9144_core.v index 9535c2764..8d4f9b0a1 100644 --- a/library/axi_ad9144/axi_ad9144_core.v +++ b/library/axi_ad9144/axi_ad9144_core.v @@ -287,6 +287,7 @@ module axi_ad9144_core ( .dac_rst (dac_rst), .dac_sync (dac_sync_s), .dac_frame (), + .dac_clksel (), .dac_par_type (), .dac_par_enb (), .dac_r1_mode (), @@ -300,7 +301,7 @@ module axi_ad9144_core ( .up_drp_wr (), .up_drp_addr (), .up_drp_wdata (), - .up_drp_rdata (16'd0), + .up_drp_rdata (32'd0), .up_drp_ready (1'd0), .up_drp_locked (1'd1), .up_usr_chanmax (), diff --git a/library/axi_ad9144/axi_ad9144_hw.tcl b/library/axi_ad9144/axi_ad9144_hw.tcl index b30788e08..a30d9aa5e 100755 --- a/library/axi_ad9144/axi_ad9144_hw.tcl +++ b/library/axi_ad9144/axi_ad9144_hw.tcl @@ -15,9 +15,7 @@ set_module_property ELABORATION_CALLBACK p_axi_ad9144 add_fileset quartus_synth QUARTUS_SYNTH "" "Quartus Synthesis" set_fileset_property quartus_synth TOP_LEVEL axi_ad9144 -add_fileset_file ad_rst.v VERILOG PATH $ad_hdl_dir/library/common/ad_rst.v -add_fileset_file MULT_MACRO.v VERILOG PATH $ad_hdl_dir/library/common/altera/MULT_MACRO.v -add_fileset_file ad_mul.v VERILOG PATH $ad_hdl_dir/library/common/ad_mul.v +add_fileset_file ad_mul.v VERILOG PATH $ad_hdl_dir/library/altera/common/ad_mul.v add_fileset_file ad_dds_sine.v VERILOG PATH $ad_hdl_dir/library/common/ad_dds_sine.v add_fileset_file ad_dds_1.v VERILOG PATH $ad_hdl_dir/library/common/ad_dds_1.v add_fileset_file ad_dds.v VERILOG PATH $ad_hdl_dir/library/common/ad_dds.v @@ -50,6 +48,13 @@ set_parameter_property QUAD_OR_DUAL_N TYPE INTEGER set_parameter_property QUAD_OR_DUAL_N UNITS None set_parameter_property QUAD_OR_DUAL_N HDL_PARAMETER true +add_parameter DEVICE_TYPE INTEGER 0 +set_parameter_property DEVICE_TYPE DEFAULT_VALUE 1 +set_parameter_property DEVICE_TYPE DISPLAY_NAME DEVICE_TYPE +set_parameter_property DEVICE_TYPE TYPE INTEGER +set_parameter_property DEVICE_TYPE UNITS None +set_parameter_property DEVICE_TYPE HDL_PARAMETER true + # axi4 slave add_interface s_axi_clock clock end @@ -85,24 +90,36 @@ add_interface_port s_axi s_axi_rready rready Input 1 # transceiver interface ad_alt_intf clock tx_clk input 1 -ad_alt_intf signal tx_data output 128*(QUAD_OR_DUAL_N+1) data + +add_interface if_tx_data avalon_streaming source +add_interface_port if_tx_data tx_data data output 128*(QUAD_OR_DUAL_N+1) +add_interface_port if_tx_data tx_valid valid output 1 +add_interface_port if_tx_data tx_ready ready input 1 +set_interface_property if_tx_data associatedClock if_tx_clk +set_interface_property if_tx_data dataBitsPerSymbol 128 # dma interface ad_alt_intf clock dac_clk output 1 -add_interface fifo_ch_0_out conduit end -add_interface_port fifo_ch_0_out dac_enable_0 enable Output 1 -add_interface_port fifo_ch_0_out dac_valid_0 valid Output 1 -add_interface_port fifo_ch_0_out dac_data_0 data Input 64 +add_interface dac_ch_0 conduit end +add_interface_port dac_ch_0 dac_enable_0 enable Output 1 +add_interface_port dac_ch_0 dac_valid_0 valid Output 1 +add_interface_port dac_ch_0 dac_ddata_0 data Input 64 -add_interface fifo_ch_1_out conduit end -add_interface_port fifo_ch_1_out dac_enable_1 enable Output 1 -add_interface_port fifo_ch_1_out dac_valid_1 valid Output 1 -add_interface_port fifo_ch_1_out dac_data_1 data Input 64 +set_interface_property dac_ch_0 associatedClock if_tx_clk +set_interface_property dac_ch_0 associatedReset none -ad_alt_intf signal dac_dovf input 1 -ad_alt_intf signal dac_dunf input 1 +add_interface dac_ch_1 conduit end +add_interface_port dac_ch_1 dac_enable_1 enable Output 1 +add_interface_port dac_ch_1 dac_valid_1 valid Output 1 +add_interface_port dac_ch_1 dac_ddata_1 data Input 64 + +set_interface_property dac_ch_1 associatedClock if_tx_clk +set_interface_property dac_ch_1 associatedReset none + +ad_alt_intf signal dac_dovf input 1 ovf +ad_alt_intf signal dac_dunf input 1 unf proc p_axi_ad9144 {} { @@ -110,15 +127,20 @@ proc p_axi_ad9144 {} { if {[get_parameter_value QUAD_OR_DUAL_N] == 1} { - add_interface fifo_ch_2_out conduit end - add_interface_port fifo_ch_2_out dac_enable_2 enable Output 1 - add_interface_port fifo_ch_2_out dac_valid_2 valid Output 1 - add_interface_port fifo_ch_2_out dac_data_2 data Input 64 + add_interface dac_ch_2 conduit end + add_interface_port dac_ch_2 dac_enable_2 enable Output 1 + add_interface_port dac_ch_2 dac_valid_2 valid Output 1 + add_interface_port dac_ch_2 dac_ddata_2 data Input 64 - add_interface fifo_ch_3_out conduit end - add_interface_port fifo_ch_3_out dac_enable_3 enable Output 1 - add_interface_port fifo_ch_3_out dac_valid_3 valid Output 1 - add_interface_port fifo_ch_3_out dac_data_3 data Input 64 + set_interface_property dac_ch_2 associatedClock if_tx_clk + set_interface_property dac_ch_2 associatedReset none + add_interface dac_ch_3 conduit end + add_interface_port dac_ch_3 dac_enable_3 enable Output 1 + add_interface_port dac_ch_3 dac_valid_3 valid Output 1 + add_interface_port dac_ch_3 dac_ddata_3 data Input 64 + + set_interface_property dac_ch_3 associatedClock if_tx_clk + set_interface_property dac_ch_3 associatedReset none } } diff --git a/library/axi_ad9144/axi_ad9144_if.v b/library/axi_ad9144/axi_ad9144_if.v index 09ee3b6fe..7d3836631 100644 --- a/library/axi_ad9144/axi_ad9144_if.v +++ b/library/axi_ad9144/axi_ad9144_if.v @@ -34,10 +34,6 @@ // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // *************************************************************************** // *************************************************************************** -// *************************************************************************** -// *************************************************************************** -// This is the dac physical interface (drives samples from the low speed clock to the -// dac clock domain. `timescale 1ns/100ps @@ -70,6 +66,10 @@ module axi_ad9144_if ( dac_data_3_2, dac_data_3_3); + // altera (0x1) or xilinx (0x0) + + parameter DEVICE_TYPE = 0; + // jesd interface // tx_clk is (line-rate/40) @@ -109,38 +109,38 @@ module axi_ad9144_if ( if (dac_rst == 1'b1) begin tx_data <= 256'd0; end else begin - tx_data[255:248] <= dac_data_3_3[ 7: 0]; - tx_data[247:240] <= dac_data_3_2[ 7: 0]; - tx_data[239:232] <= dac_data_3_1[ 7: 0]; - tx_data[231:224] <= dac_data_3_0[ 7: 0]; - tx_data[223:216] <= dac_data_3_3[15: 8]; - tx_data[215:208] <= dac_data_3_2[15: 8]; - tx_data[207:200] <= dac_data_3_1[15: 8]; - tx_data[199:192] <= dac_data_3_0[15: 8]; - tx_data[191:184] <= dac_data_2_3[ 7: 0]; - tx_data[183:176] <= dac_data_2_2[ 7: 0]; - tx_data[175:168] <= dac_data_2_1[ 7: 0]; - tx_data[167:160] <= dac_data_2_0[ 7: 0]; - tx_data[159:152] <= dac_data_2_3[15: 8]; - tx_data[151:144] <= dac_data_2_2[15: 8]; - tx_data[143:136] <= dac_data_2_1[15: 8]; - tx_data[135:128] <= dac_data_2_0[15: 8]; - tx_data[127:120] <= dac_data_1_3[ 7: 0]; - tx_data[119:112] <= dac_data_1_2[ 7: 0]; - tx_data[111:104] <= dac_data_1_1[ 7: 0]; - tx_data[103: 96] <= dac_data_1_0[ 7: 0]; - tx_data[ 95: 88] <= dac_data_1_3[15: 8]; - tx_data[ 87: 80] <= dac_data_1_2[15: 8]; - tx_data[ 79: 72] <= dac_data_1_1[15: 8]; - tx_data[ 71: 64] <= dac_data_1_0[15: 8]; - tx_data[ 63: 56] <= dac_data_0_3[ 7: 0]; - tx_data[ 55: 48] <= dac_data_0_2[ 7: 0]; - tx_data[ 47: 40] <= dac_data_0_1[ 7: 0]; - tx_data[ 39: 32] <= dac_data_0_0[ 7: 0]; - tx_data[ 31: 24] <= dac_data_0_3[15: 8]; - tx_data[ 23: 16] <= dac_data_0_2[15: 8]; - tx_data[ 15: 8] <= dac_data_0_1[15: 8]; - tx_data[ 7: 0] <= dac_data_0_0[15: 8]; + tx_data[255:248] <= (DEVICE_TYPE == 1) ? dac_data_3_0[ 7: 0] : dac_data_3_3[ 7: 0]; + tx_data[247:240] <= (DEVICE_TYPE == 1) ? dac_data_3_1[ 7: 0] : dac_data_3_2[ 7: 0]; + tx_data[239:232] <= (DEVICE_TYPE == 1) ? dac_data_3_2[ 7: 0] : dac_data_3_1[ 7: 0]; + tx_data[231:224] <= (DEVICE_TYPE == 1) ? dac_data_3_3[ 7: 0] : dac_data_3_0[ 7: 0]; + tx_data[223:216] <= (DEVICE_TYPE == 1) ? dac_data_3_0[15: 8] : dac_data_3_3[15: 8]; + tx_data[215:208] <= (DEVICE_TYPE == 1) ? dac_data_3_1[15: 8] : dac_data_3_2[15: 8]; + tx_data[207:200] <= (DEVICE_TYPE == 1) ? dac_data_3_2[15: 8] : dac_data_3_1[15: 8]; + tx_data[199:192] <= (DEVICE_TYPE == 1) ? dac_data_3_3[15: 8] : dac_data_3_0[15: 8]; + tx_data[191:184] <= (DEVICE_TYPE == 1) ? dac_data_2_0[ 7: 0] : dac_data_2_3[ 7: 0]; + tx_data[183:176] <= (DEVICE_TYPE == 1) ? dac_data_2_1[ 7: 0] : dac_data_2_2[ 7: 0]; + tx_data[175:168] <= (DEVICE_TYPE == 1) ? dac_data_2_2[ 7: 0] : dac_data_2_1[ 7: 0]; + tx_data[167:160] <= (DEVICE_TYPE == 1) ? dac_data_2_3[ 7: 0] : dac_data_2_0[ 7: 0]; + tx_data[159:152] <= (DEVICE_TYPE == 1) ? dac_data_2_0[15: 8] : dac_data_2_3[15: 8]; + tx_data[151:144] <= (DEVICE_TYPE == 1) ? dac_data_2_1[15: 8] : dac_data_2_2[15: 8]; + tx_data[143:136] <= (DEVICE_TYPE == 1) ? dac_data_2_2[15: 8] : dac_data_2_1[15: 8]; + tx_data[135:128] <= (DEVICE_TYPE == 1) ? dac_data_2_3[15: 8] : dac_data_2_0[15: 8]; + tx_data[127:120] <= (DEVICE_TYPE == 1) ? dac_data_1_0[ 7: 0] : dac_data_1_3[ 7: 0]; + tx_data[119:112] <= (DEVICE_TYPE == 1) ? dac_data_1_1[ 7: 0] : dac_data_1_2[ 7: 0]; + tx_data[111:104] <= (DEVICE_TYPE == 1) ? dac_data_1_2[ 7: 0] : dac_data_1_1[ 7: 0]; + tx_data[103: 96] <= (DEVICE_TYPE == 1) ? dac_data_1_3[ 7: 0] : dac_data_1_0[ 7: 0]; + tx_data[ 95: 88] <= (DEVICE_TYPE == 1) ? dac_data_1_0[15: 8] : dac_data_1_3[15: 8]; + tx_data[ 87: 80] <= (DEVICE_TYPE == 1) ? dac_data_1_1[15: 8] : dac_data_1_2[15: 8]; + tx_data[ 79: 72] <= (DEVICE_TYPE == 1) ? dac_data_1_2[15: 8] : dac_data_1_1[15: 8]; + tx_data[ 71: 64] <= (DEVICE_TYPE == 1) ? dac_data_1_3[15: 8] : dac_data_1_0[15: 8]; + tx_data[ 63: 56] <= (DEVICE_TYPE == 1) ? dac_data_0_0[ 7: 0] : dac_data_0_3[ 7: 0]; + tx_data[ 55: 48] <= (DEVICE_TYPE == 1) ? dac_data_0_1[ 7: 0] : dac_data_0_2[ 7: 0]; + tx_data[ 47: 40] <= (DEVICE_TYPE == 1) ? dac_data_0_2[ 7: 0] : dac_data_0_1[ 7: 0]; + tx_data[ 39: 32] <= (DEVICE_TYPE == 1) ? dac_data_0_3[ 7: 0] : dac_data_0_0[ 7: 0]; + tx_data[ 31: 24] <= (DEVICE_TYPE == 1) ? dac_data_0_0[15: 8] : dac_data_0_3[15: 8]; + tx_data[ 23: 16] <= (DEVICE_TYPE == 1) ? dac_data_0_1[15: 8] : dac_data_0_2[15: 8]; + tx_data[ 15: 8] <= (DEVICE_TYPE == 1) ? dac_data_0_2[15: 8] : dac_data_0_1[15: 8]; + tx_data[ 7: 0] <= (DEVICE_TYPE == 1) ? dac_data_0_3[15: 8] : dac_data_0_0[15: 8]; end end diff --git a/library/axi_ad9144/axi_ad9144_ip.tcl b/library/axi_ad9144/axi_ad9144_ip.tcl index dac97de77..7482746dd 100644 --- a/library/axi_ad9144/axi_ad9144_ip.tcl +++ b/library/axi_ad9144/axi_ad9144_ip.tcl @@ -6,7 +6,7 @@ source $ad_hdl_dir/library/scripts/adi_ip.tcl adi_ip_create axi_ad9144 adi_ip_files axi_ad9144 [list \ "$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc" \ - "$ad_hdl_dir/library/common/ad_mul.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_mul.v" \ "$ad_hdl_dir/library/common/ad_dds_sine.v" \ "$ad_hdl_dir/library/common/ad_dds_1.v" \ "$ad_hdl_dir/library/common/ad_dds.v" \ @@ -29,6 +29,7 @@ adi_ip_constraints axi_ad9144 [list \ set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]] set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]] +set_property driver_value 0 [ipx::get_ports *tx_ready* -of_objects [ipx::current_core]] ipx::save_core [ipx::current_core] diff --git a/library/axi_ad9152/Makefile b/library/axi_ad9152/Makefile index 55aaa7c77..1d43a55bc 100644 --- a/library/axi_ad9152/Makefile +++ b/library/axi_ad9152/Makefile @@ -5,25 +5,25 @@ #################################################################################### #################################################################################### -M_DEPS := axi_ad9152_ip.tcl -M_DEPS += ../scripts/adi_env.tcl -M_DEPS += ../scripts/adi_ip.tcl M_DEPS += ../common/ad_axi_ip_constr.xdc -M_DEPS += ../common/ad_mul.v -M_DEPS += ../common/ad_dds_sine.v -M_DEPS += ../common/ad_dds_1.v M_DEPS += ../common/ad_dds.v +M_DEPS += ../common/ad_dds_1.v +M_DEPS += ../common/ad_dds_sine.v M_DEPS += ../common/ad_rst.v M_DEPS += ../common/up_axi.v +M_DEPS += ../common/up_clock_mon.v +M_DEPS += ../common/up_dac_channel.v +M_DEPS += ../common/up_dac_common.v M_DEPS += ../common/up_xfer_cntrl.v M_DEPS += ../common/up_xfer_status.v -M_DEPS += ../common/up_clock_mon.v -M_DEPS += ../common/up_dac_common.v -M_DEPS += ../common/up_dac_channel.v +M_DEPS += ../scripts/adi_env.tcl +M_DEPS += ../scripts/adi_ip.tcl +M_DEPS += ../xilinx/common/ad_mul.v +M_DEPS += axi_ad9152.v M_DEPS += axi_ad9152_channel.v M_DEPS += axi_ad9152_core.v M_DEPS += axi_ad9152_if.v -M_DEPS += axi_ad9152.v +M_DEPS += axi_ad9152_ip.tcl M_VIVADO := vivado -mode batch -source @@ -34,6 +34,10 @@ M_FLIST += *.log M_FLIST += component.xml M_FLIST += *.jou M_FLIST += xgui +M_FLIST += *.ip_user_files +M_FLIST += *.srcs +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil @@ -50,7 +54,7 @@ clean-all: axi_ad9152.xpr: $(M_DEPS) - rm -rf $(M_FLIST) + -rm -rf $(M_FLIST) $(M_VIVADO) axi_ad9152_ip.tcl >> axi_ad9152_ip.log 2>&1 #################################################################################### diff --git a/library/axi_ad9152/axi_ad9152.v b/library/axi_ad9152/axi_ad9152.v index cc9c36e45..192c65a80 100644 --- a/library/axi_ad9152/axi_ad9152.v +++ b/library/axi_ad9152/axi_ad9152.v @@ -46,6 +46,8 @@ module axi_ad9152 ( tx_clk, tx_data, + tx_valid, + tx_ready, // dma interface @@ -87,12 +89,15 @@ module axi_ad9152 ( parameter ID = 0; parameter DAC_DATAPATH_DISABLE = 0; + parameter DEVICE_TYPE = 0; // jesd interface // tx_clk is (line-rate/40) input tx_clk; output [127:0] tx_data; + output tx_valid; + input tx_ready; // dma interface @@ -112,7 +117,7 @@ module axi_ad9152 ( input s_axi_aresetn; input s_axi_awvalid; input [ 31:0] s_axi_awaddr; - input [ 2:0] s_axi_awprot; + input [ 2:0] s_axi_awprot; output s_axi_awready; input s_axi_wvalid; input [ 31:0] s_axi_wdata; @@ -123,7 +128,7 @@ module axi_ad9152 ( input s_axi_bready; input s_axi_arvalid; input [ 31:0] s_axi_araddr; - input [ 2:0] s_axi_arprot; + input [ 2:0] s_axi_arprot; output s_axi_arready; output s_axi_rvalid; output [ 31:0] s_axi_rdata; @@ -159,10 +164,11 @@ module axi_ad9152 ( assign up_clk = s_axi_aclk; assign up_rstn = s_axi_aresetn; + assign tx_valid = 1'b1; // device interface - axi_ad9152_if i_if ( + axi_ad9152_if #(.DEVICE_TYPE (DEVICE_TYPE)) i_if ( .tx_clk (tx_clk), .tx_data (tx_data), .dac_clk (dac_clk), diff --git a/library/axi_ad9152/axi_ad9152_channel.v b/library/axi_ad9152/axi_ad9152_channel.v index dd5c0d1b0..56f599594 100644 --- a/library/axi_ad9152/axi_ad9152_channel.v +++ b/library/axi_ad9152/axi_ad9152_channel.v @@ -34,8 +34,6 @@ // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // *************************************************************************** // *************************************************************************** -// *************************************************************************** -// *************************************************************************** `timescale 1ns/100ps @@ -104,8 +102,6 @@ module axi_ad9152_channel ( reg [63:0] dac_data = 'd0; reg [63:0] dac_pn7_data = 'd0; reg [63:0] dac_pn15_data = 'd0; - reg [63:0] dac_pn23_data = 'd0; - reg [63:0] dac_pn31_data = 'd0; reg [15:0] dac_dds_phase_0_0 = 'd0; reg [15:0] dac_dds_phase_0_1 = 'd0; reg [15:0] dac_dds_phase_1_0 = 'd0; @@ -133,312 +129,174 @@ module axi_ad9152_channel ( wire [15:0] dac_pat_data_1_s; wire [15:0] dac_pat_data_2_s; wire [ 3:0] dac_data_sel_s; + wire [63:0] dac_pn7_data_i_s; + wire [63:0] dac_pn15_data_i_s; + wire [63:0] dac_pn7_data_s; + wire [63:0] dac_pn15_data_s; - // pn7 function + // PN7 function function [63:0] pn7; - input [63:0] din; + input [7:0] din; reg [63:0] dout; begin - dout[63] = din[ 7] ^ din[ 6]; - dout[62] = din[ 6] ^ din[ 5]; - dout[61] = din[ 5] ^ din[ 4]; - dout[60] = din[ 4] ^ din[ 3]; - dout[59] = din[ 3] ^ din[ 2]; - dout[58] = din[ 2] ^ din[ 1]; - dout[57] = din[ 1] ^ din[ 0]; - dout[56] = din[ 0] ^ din[ 7] ^ din[ 6]; - dout[55] = din[ 7] ^ din[ 5]; - dout[54] = din[ 6] ^ din[ 4]; - dout[53] = din[ 5] ^ din[ 3]; - dout[52] = din[ 4] ^ din[ 2]; - dout[51] = din[ 3] ^ din[ 1]; - dout[50] = din[ 2] ^ din[ 0]; - dout[49] = din[ 1] ^ din[ 7] ^ din[ 6]; - dout[48] = din[ 0] ^ din[ 6] ^ din[ 5]; - dout[47] = din[ 7] ^ din[ 5] ^ din[ 6] ^ din[ 4]; - dout[46] = din[ 6] ^ din[ 4] ^ din[ 5] ^ din[ 3]; - dout[45] = din[ 5] ^ din[ 3] ^ din[ 4] ^ din[ 2]; - dout[44] = din[ 4] ^ din[ 2] ^ din[ 3] ^ din[ 1]; - dout[43] = din[ 3] ^ din[ 1] ^ din[ 2] ^ din[ 0]; - dout[42] = din[ 2] ^ din[ 0] ^ din[ 1] ^ din[ 7] ^ din[ 6]; - dout[41] = din[ 1] ^ din[ 7] ^ din[ 0] ^ din[ 5]; - dout[40] = din[ 0] ^ din[ 7] ^ din[ 4]; - dout[39] = din[ 7] ^ din[ 3]; - dout[38] = din[ 6] ^ din[ 2]; - dout[37] = din[ 5] ^ din[ 1]; - dout[36] = din[ 4] ^ din[ 0]; - dout[35] = din[ 3] ^ din[ 7] ^ din[ 6]; - dout[34] = din[ 2] ^ din[ 6] ^ din[ 5]; - dout[33] = din[ 1] ^ din[ 5] ^ din[ 4]; - dout[32] = din[ 0] ^ din[ 4] ^ din[ 3]; - dout[31] = din[ 7] ^ din[ 3] ^ din[ 6] ^ din[ 2]; - dout[30] = din[ 6] ^ din[ 2] ^ din[ 5] ^ din[ 1]; - dout[29] = din[ 5] ^ din[ 1] ^ din[ 4] ^ din[ 0]; - dout[28] = din[ 4] ^ din[ 0] ^ din[ 3] ^ din[ 7] ^ din[ 6]; - dout[27] = din[ 3] ^ din[ 7] ^ din[ 2] ^ din[ 5]; - dout[26] = din[ 2] ^ din[ 6] ^ din[ 1] ^ din[ 4]; - dout[25] = din[ 1] ^ din[ 5] ^ din[ 0] ^ din[ 3]; - dout[24] = din[ 0] ^ din[ 4] ^ din[ 7] ^ din[ 6] ^ din[ 2]; - dout[23] = din[ 7] ^ din[ 3] ^ din[ 5] ^ din[ 1]; - dout[22] = din[ 6] ^ din[ 2] ^ din[ 4] ^ din[ 0]; - dout[21] = din[ 5] ^ din[ 1] ^ din[ 3] ^ din[ 7] ^ din[ 6]; - dout[20] = din[ 4] ^ din[ 0] ^ din[ 6] ^ din[ 2] ^ din[ 5]; - dout[19] = din[ 3] ^ din[ 7] ^ din[ 5] ^ din[ 6] ^ din[ 1] ^ din[ 4]; - dout[18] = din[ 2] ^ din[ 6] ^ din[ 4] ^ din[ 5] ^ din[ 0] ^ din[ 3]; - dout[17] = din[ 1] ^ din[ 5] ^ din[ 3] ^ din[ 4] ^ din[ 7] ^ din[ 6] ^ din[ 2]; - dout[16] = din[ 0] ^ din[ 4] ^ din[ 6] ^ din[ 2] ^ din[ 3] ^ din[ 5] ^ din[ 1]; - dout[15] = din[ 7] ^ din[ 3] ^ din[ 5] ^ din[ 1] ^ din[ 6] ^ din[ 2] ^ din[ 4] ^ din[ 0]; - dout[14] = din[ 2] ^ din[ 4] ^ din[ 0] ^ din[ 5] ^ din[ 1] ^ din[ 3] ^ din[ 7]; - dout[13] = din[ 1] ^ din[ 3] ^ din[ 7] ^ din[ 4] ^ din[ 0] ^ din[ 2]; - dout[12] = din[ 0] ^ din[ 2] ^ din[ 3] ^ din[ 7] ^ din[ 1]; - dout[11] = din[ 7] ^ din[ 1] ^ din[ 2] ^ din[ 0]; - dout[10] = din[ 0] ^ din[ 1] ^ din[ 7]; - dout[ 9] = din[ 7] ^ din[ 0]; - dout[ 8] = din[ 7]; - dout[ 7] = din[ 6]; - dout[ 6] = din[ 5]; - dout[ 5] = din[ 4]; - dout[ 4] = din[ 3]; - dout[ 3] = din[ 2]; - dout[ 2] = din[ 1]; - dout[ 1] = din[ 0]; - dout[ 0] = din[ 7] ^ din[ 6]; + dout[15] = din[ 6] ^ din[ 5]; + dout[14] = din[ 5] ^ din[ 4]; + dout[13] = din[ 4] ^ din[ 3]; + dout[12] = din[ 3] ^ din[ 2]; + dout[11] = din[ 2] ^ din[ 1]; + dout[10] = din[ 1] ^ din[ 0]; + dout[ 9] = din[ 0] ^ din[ 6] ^ din[ 5]; + dout[ 8] = din[ 6] ^ din[ 4]; + dout[ 7] = din[ 5] ^ din[ 3]; + dout[ 6] = din[ 4] ^ din[ 2]; + dout[ 5] = din[ 3] ^ din[ 1]; + dout[ 4] = din[ 2] ^ din[ 0]; + dout[ 3] = din[ 1] ^ din[ 6] ^ din[ 5]; + dout[ 2] = din[ 0] ^ din[ 5] ^ din[ 4]; + dout[ 1] = din[ 6] ^ din[ 4] ^ din[ 5] ^ din[ 3]; + dout[ 0] = din[ 5] ^ din[ 3] ^ din[ 4] ^ din[ 2]; + dout[31] = din[ 4] ^ din[ 2] ^ din[ 3] ^ din[ 1]; + dout[30] = din[ 3] ^ din[ 1] ^ din[ 2] ^ din[ 0]; + dout[29] = din[ 2] ^ din[ 0] ^ din[ 1] ^ din[ 6] ^ din[ 5]; + dout[28] = din[ 1] ^ din[ 6] ^ din[ 0] ^ din[ 4]; + dout[27] = din[ 0] ^ din[ 6] ^ din[ 3]; + dout[26] = din[ 6] ^ din[ 2]; + dout[25] = din[ 5] ^ din[ 1]; + dout[24] = din[ 4] ^ din[ 0]; + dout[23] = din[ 3] ^ din[ 6] ^ din[ 5]; + dout[22] = din[ 2] ^ din[ 5] ^ din[ 4]; + dout[21] = din[ 1] ^ din[ 4] ^ din[ 3]; + dout[20] = din[ 0] ^ din[ 3] ^ din[ 2]; + dout[19] = din[ 6] ^ din[ 2] ^ din[ 5] ^ din[ 1]; + dout[18] = din[ 5] ^ din[ 1] ^ din[ 4] ^ din[ 0]; + dout[17] = din[ 4] ^ din[ 0] ^ din[ 3] ^ din[ 6] ^ din[ 5]; + dout[16] = din[ 3] ^ din[ 6] ^ din[ 2] ^ din[ 4]; + dout[47] = din[ 2] ^ din[ 5] ^ din[ 1] ^ din[ 3]; + dout[46] = din[ 1] ^ din[ 4] ^ din[ 0] ^ din[ 2]; + dout[45] = din[ 0] ^ din[ 3] ^ din[ 6] ^ din[ 5] ^ din[ 1]; + dout[44] = din[ 6] ^ din[ 2] ^ din[ 4] ^ din[ 0]; + dout[43] = din[ 1] ^ din[ 3] ^ din[ 6]; + dout[42] = din[ 0] ^ din[ 5] ^ din[ 2]; + dout[41] = din[ 6] ^ din[ 4] ^ din[ 5] ^ din[ 1]; + dout[40] = din[ 5] ^ din[ 3] ^ din[ 4] ^ din[ 0]; + dout[39] = din[ 4] ^ din[ 2] ^ din[ 3] ^ din[ 6] ^ din[ 5]; + dout[38] = din[ 3] ^ din[ 5] ^ din[ 1] ^ din[ 2] ^ din[ 4]; + dout[37] = din[ 2] ^ din[ 4] ^ din[ 0] ^ din[ 1] ^ din[ 3]; + dout[36] = din[ 1] ^ din[ 3] ^ din[ 6] ^ din[ 0] ^ din[ 5] ^ din[ 2]; + dout[35] = din[ 0] ^ din[ 2] ^ din[ 6] ^ din[ 4] ^ din[ 1]; + dout[34] = din[ 6] ^ din[ 1] ^ din[ 3] ^ din[ 0]; + dout[33] = din[ 0] ^ din[ 2] ^ din[ 6]; + dout[32] = din[ 6] ^ din[ 1]; + dout[63] = din[ 5] ^ din[ 0]; + dout[62] = din[ 4] ^ din[ 6] ^ din[ 5]; + dout[61] = din[ 3] ^ din[ 5] ^ din[ 4]; + dout[60] = din[ 2] ^ din[ 4] ^ din[ 3]; + dout[59] = din[ 1] ^ din[ 3] ^ din[ 2]; + dout[58] = din[ 0] ^ din[ 2] ^ din[ 1]; + dout[57] = din[ 6] ^ din[ 1] ^ din[ 5] ^ din[ 0]; + dout[56] = din[ 0] ^ din[ 4] ^ din[ 6]; + dout[55] = din[ 6] ^ din[ 3]; + dout[54] = din[ 5] ^ din[ 2]; + dout[53] = din[ 4] ^ din[ 1]; + dout[52] = din[ 3] ^ din[ 0]; + dout[51] = din[ 2] ^ din[ 6] ^ din[ 5]; + dout[50] = din[ 1] ^ din[ 5] ^ din[ 4]; + dout[49] = din[ 0] ^ din[ 4] ^ din[ 3]; + dout[48] = din[ 6] ^ din[ 3] ^ din[ 5] ^ din[ 2]; pn7 = dout; end endfunction - // pn15 function + // PN15 function function [63:0] pn15; - input [63:0] din; + input [15:0] din; reg [63:0] dout; begin - dout[63] = din[15] ^ din[14]; - dout[62] = din[14] ^ din[13]; - dout[61] = din[13] ^ din[12]; - dout[60] = din[12] ^ din[11]; - dout[59] = din[11] ^ din[10]; - dout[58] = din[10] ^ din[ 9]; - dout[57] = din[ 9] ^ din[ 8]; - dout[56] = din[ 8] ^ din[ 7]; - dout[55] = din[ 7] ^ din[ 6]; - dout[54] = din[ 6] ^ din[ 5]; - dout[53] = din[ 5] ^ din[ 4]; - dout[52] = din[ 4] ^ din[ 3]; - dout[51] = din[ 3] ^ din[ 2]; - dout[50] = din[ 2] ^ din[ 1]; - dout[49] = din[ 1] ^ din[ 0]; - dout[48] = din[ 0] ^ din[15] ^ din[14]; - dout[47] = din[15] ^ din[13]; - dout[46] = din[14] ^ din[12]; - dout[45] = din[13] ^ din[11]; - dout[44] = din[12] ^ din[10]; - dout[43] = din[11] ^ din[ 9]; - dout[42] = din[10] ^ din[ 8]; - dout[41] = din[ 9] ^ din[ 7]; - dout[40] = din[ 8] ^ din[ 6]; - dout[39] = din[ 7] ^ din[ 5]; - dout[38] = din[ 6] ^ din[ 4]; - dout[37] = din[ 5] ^ din[ 3]; - dout[36] = din[ 4] ^ din[ 2]; - dout[35] = din[ 3] ^ din[ 1]; - dout[34] = din[ 2] ^ din[ 0]; - dout[33] = din[ 1] ^ din[15] ^ din[14]; - dout[32] = din[ 0] ^ din[14] ^ din[13]; - dout[31] = din[15] ^ din[13] ^ din[14] ^ din[12]; - dout[30] = din[14] ^ din[12] ^ din[13] ^ din[11]; - dout[29] = din[13] ^ din[11] ^ din[12] ^ din[10]; - dout[28] = din[12] ^ din[10] ^ din[11] ^ din[ 9]; - dout[27] = din[11] ^ din[ 9] ^ din[10] ^ din[ 8]; - dout[26] = din[10] ^ din[ 8] ^ din[ 9] ^ din[ 7]; - dout[25] = din[ 9] ^ din[ 7] ^ din[ 8] ^ din[ 6]; - dout[24] = din[ 8] ^ din[ 6] ^ din[ 7] ^ din[ 5]; - dout[23] = din[ 7] ^ din[ 5] ^ din[ 6] ^ din[ 4]; - dout[22] = din[ 6] ^ din[ 4] ^ din[ 5] ^ din[ 3]; - dout[21] = din[ 5] ^ din[ 3] ^ din[ 4] ^ din[ 2]; - dout[20] = din[ 4] ^ din[ 2] ^ din[ 3] ^ din[ 1]; - dout[19] = din[ 3] ^ din[ 1] ^ din[ 2] ^ din[ 0]; - dout[18] = din[ 2] ^ din[ 0] ^ din[ 1] ^ din[15] ^ din[14]; - dout[17] = din[ 1] ^ din[15] ^ din[ 0] ^ din[13]; - dout[16] = din[ 0] ^ din[15] ^ din[12]; - dout[15] = din[15] ^ din[11]; - dout[14] = din[14] ^ din[10]; - dout[13] = din[13] ^ din[ 9]; - dout[12] = din[12] ^ din[ 8]; - dout[11] = din[11] ^ din[ 7]; - dout[10] = din[10] ^ din[ 6]; - dout[ 9] = din[ 9] ^ din[ 5]; - dout[ 8] = din[ 8] ^ din[ 4]; - dout[ 7] = din[ 7] ^ din[ 3]; - dout[ 6] = din[ 6] ^ din[ 2]; - dout[ 5] = din[ 5] ^ din[ 1]; - dout[ 4] = din[ 4] ^ din[ 0]; - dout[ 3] = din[ 3] ^ din[15] ^ din[14]; - dout[ 2] = din[ 2] ^ din[14] ^ din[13]; - dout[ 1] = din[ 1] ^ din[13] ^ din[12]; - dout[ 0] = din[ 0] ^ din[12] ^ din[11]; + dout[15] = din[14] ^ din[13]; + dout[14] = din[13] ^ din[12]; + dout[13] = din[12] ^ din[11]; + dout[12] = din[11] ^ din[10]; + dout[11] = din[10] ^ din[ 9]; + dout[10] = din[ 9] ^ din[ 8]; + dout[ 9] = din[ 8] ^ din[ 7]; + dout[ 8] = din[ 7] ^ din[ 6]; + dout[ 7] = din[ 6] ^ din[ 5]; + dout[ 6] = din[ 5] ^ din[ 4]; + dout[ 5] = din[ 4] ^ din[ 3]; + dout[ 4] = din[ 3] ^ din[ 2]; + dout[ 3] = din[ 2] ^ din[ 1]; + dout[ 2] = din[ 1] ^ din[ 0]; + dout[ 1] = din[ 0] ^ din[14] ^ din[13]; + dout[ 0] = din[14] ^ din[12]; + dout[31] = din[13] ^ din[11]; + dout[30] = din[12] ^ din[10]; + dout[29] = din[11] ^ din[ 9]; + dout[28] = din[10] ^ din[ 8]; + dout[27] = din[ 9] ^ din[ 7]; + dout[26] = din[ 8] ^ din[ 6]; + dout[25] = din[ 7] ^ din[ 5]; + dout[24] = din[ 6] ^ din[ 4]; + dout[23] = din[ 5] ^ din[ 3]; + dout[22] = din[ 4] ^ din[ 2]; + dout[21] = din[ 3] ^ din[ 1]; + dout[20] = din[ 2] ^ din[ 0]; + dout[19] = din[ 1] ^ din[14] ^ din[13]; + dout[18] = din[ 0] ^ din[13] ^ din[12]; + dout[17] = din[14] ^ din[12] ^ din[13] ^ din[11]; + dout[16] = din[13] ^ din[11] ^ din[12] ^ din[10]; + dout[47] = din[12] ^ din[10] ^ din[11] ^ din[ 9]; + dout[46] = din[11] ^ din[ 9] ^ din[10] ^ din[ 8]; + dout[45] = din[10] ^ din[ 8] ^ din[ 9] ^ din[ 7]; + dout[44] = din[ 9] ^ din[ 7] ^ din[ 8] ^ din[ 6]; + dout[43] = din[ 8] ^ din[ 6] ^ din[ 7] ^ din[ 5]; + dout[42] = din[ 7] ^ din[ 5] ^ din[ 6] ^ din[ 4]; + dout[41] = din[ 6] ^ din[ 4] ^ din[ 5] ^ din[ 3]; + dout[40] = din[ 5] ^ din[ 3] ^ din[ 4] ^ din[ 2]; + dout[39] = din[ 4] ^ din[ 2] ^ din[ 3] ^ din[ 1]; + dout[38] = din[ 3] ^ din[ 1] ^ din[ 2] ^ din[ 0]; + dout[37] = din[ 2] ^ din[ 0] ^ din[ 1] ^ din[14] ^ din[13]; + dout[36] = din[ 1] ^ din[14] ^ din[ 0] ^ din[12]; + dout[35] = din[ 0] ^ din[14] ^ din[11]; + dout[34] = din[14] ^ din[10]; + dout[33] = din[13] ^ din[ 9]; + dout[32] = din[12] ^ din[ 8]; + dout[63] = din[11] ^ din[ 7]; + dout[62] = din[10] ^ din[ 6]; + dout[61] = din[ 9] ^ din[ 5]; + dout[60] = din[ 8] ^ din[ 4]; + dout[59] = din[ 7] ^ din[ 3]; + dout[58] = din[ 6] ^ din[ 2]; + dout[57] = din[ 5] ^ din[ 1]; + dout[56] = din[ 4] ^ din[ 0]; + dout[55] = din[ 3] ^ din[14] ^ din[13]; + dout[54] = din[ 2] ^ din[13] ^ din[12]; + dout[53] = din[ 1] ^ din[12] ^ din[11]; + dout[52] = din[ 0] ^ din[11] ^ din[10]; + dout[51] = din[14] ^ din[10] ^ din[13] ^ din[ 9]; + dout[50] = din[13] ^ din[ 9] ^ din[12] ^ din[ 8]; + dout[49] = din[12] ^ din[ 8] ^ din[11] ^ din[ 7]; + dout[48] = din[11] ^ din[ 7] ^ din[10] ^ din[ 6]; pn15 = dout; end endfunction - // pn23 function + assign dac_pn7_data_i_s = ~dac_pn7_data; + assign dac_pn15_data_i_s = ~dac_pn15_data; - function [63:0] pn23; - input [63:0] din; - reg [63:0] dout; - begin - dout[63] = din[23] ^ din[18]; - dout[62] = din[22] ^ din[17]; - dout[61] = din[21] ^ din[16]; - dout[60] = din[20] ^ din[15]; - dout[59] = din[19] ^ din[14]; - dout[58] = din[18] ^ din[13]; - dout[57] = din[17] ^ din[12]; - dout[56] = din[16] ^ din[11]; - dout[55] = din[15] ^ din[10]; - dout[54] = din[14] ^ din[ 9]; - dout[53] = din[13] ^ din[ 8]; - dout[52] = din[12] ^ din[ 7]; - dout[51] = din[11] ^ din[ 6]; - dout[50] = din[10] ^ din[ 5]; - dout[49] = din[ 9] ^ din[ 4]; - dout[48] = din[ 8] ^ din[ 3]; - dout[47] = din[ 7] ^ din[ 2]; - dout[46] = din[ 6] ^ din[ 1]; - dout[45] = din[ 5] ^ din[ 0]; - dout[44] = din[ 4] ^ din[23] ^ din[18]; - dout[43] = din[ 3] ^ din[22] ^ din[17]; - dout[42] = din[ 2] ^ din[21] ^ din[16]; - dout[41] = din[ 1] ^ din[20] ^ din[15]; - dout[40] = din[ 0] ^ din[19] ^ din[14]; - dout[39] = din[23] ^ din[13]; - dout[38] = din[22] ^ din[12]; - dout[37] = din[21] ^ din[11]; - dout[36] = din[20] ^ din[10]; - dout[35] = din[19] ^ din[ 9]; - dout[34] = din[18] ^ din[ 8]; - dout[33] = din[17] ^ din[ 7]; - dout[32] = din[16] ^ din[ 6]; - dout[31] = din[15] ^ din[ 5]; - dout[30] = din[14] ^ din[ 4]; - dout[29] = din[13] ^ din[ 3]; - dout[28] = din[12] ^ din[ 2]; - dout[27] = din[11] ^ din[ 1]; - dout[26] = din[10] ^ din[ 0]; - dout[25] = din[ 9] ^ din[23] ^ din[18]; - dout[24] = din[ 8] ^ din[22] ^ din[17]; - dout[23] = din[ 7] ^ din[21] ^ din[16]; - dout[22] = din[ 6] ^ din[20] ^ din[15]; - dout[21] = din[ 5] ^ din[19] ^ din[14]; - dout[20] = din[ 4] ^ din[18] ^ din[13]; - dout[19] = din[ 3] ^ din[17] ^ din[12]; - dout[18] = din[ 2] ^ din[16] ^ din[11]; - dout[17] = din[ 1] ^ din[15] ^ din[10]; - dout[16] = din[ 0] ^ din[14] ^ din[ 9]; - dout[15] = din[23] ^ din[13] ^ din[18] ^ din[ 8]; - dout[14] = din[22] ^ din[12] ^ din[17] ^ din[ 7]; - dout[13] = din[21] ^ din[11] ^ din[16] ^ din[ 6]; - dout[12] = din[20] ^ din[10] ^ din[15] ^ din[ 5]; - dout[11] = din[19] ^ din[ 9] ^ din[14] ^ din[ 4]; - dout[10] = din[18] ^ din[ 8] ^ din[13] ^ din[ 3]; - dout[ 9] = din[17] ^ din[ 7] ^ din[12] ^ din[ 2]; - dout[ 8] = din[16] ^ din[ 6] ^ din[11] ^ din[ 1]; - dout[ 7] = din[15] ^ din[ 5] ^ din[10] ^ din[ 0]; - dout[ 6] = din[14] ^ din[ 4] ^ din[ 9] ^ din[23] ^ din[18]; - dout[ 5] = din[13] ^ din[ 3] ^ din[ 8] ^ din[22] ^ din[17]; - dout[ 4] = din[12] ^ din[ 2] ^ din[ 7] ^ din[21] ^ din[16]; - dout[ 3] = din[11] ^ din[ 1] ^ din[ 6] ^ din[20] ^ din[15]; - dout[ 2] = din[10] ^ din[ 0] ^ din[ 5] ^ din[19] ^ din[14]; - dout[ 1] = din[ 9] ^ din[23] ^ din[ 4] ^ din[13]; - dout[ 0] = din[ 8] ^ din[22] ^ din[ 3] ^ din[12]; - pn23 = dout; - end - endfunction - - // pn31 function - - function [63:0] pn31; - input [63:0] din; - reg [63:0] dout; - begin - dout[63] = din[31] ^ din[28]; - dout[62] = din[30] ^ din[27]; - dout[61] = din[29] ^ din[26]; - dout[60] = din[28] ^ din[25]; - dout[59] = din[27] ^ din[24]; - dout[58] = din[26] ^ din[23]; - dout[57] = din[25] ^ din[22]; - dout[56] = din[24] ^ din[21]; - dout[55] = din[23] ^ din[20]; - dout[54] = din[22] ^ din[19]; - dout[53] = din[21] ^ din[18]; - dout[52] = din[20] ^ din[17]; - dout[51] = din[19] ^ din[16]; - dout[50] = din[18] ^ din[15]; - dout[49] = din[17] ^ din[14]; - dout[48] = din[16] ^ din[13]; - dout[47] = din[15] ^ din[12]; - dout[46] = din[14] ^ din[11]; - dout[45] = din[13] ^ din[10]; - dout[44] = din[12] ^ din[ 9]; - dout[43] = din[11] ^ din[ 8]; - dout[42] = din[10] ^ din[ 7]; - dout[41] = din[ 9] ^ din[ 6]; - dout[40] = din[ 8] ^ din[ 5]; - dout[39] = din[ 7] ^ din[ 4]; - dout[38] = din[ 6] ^ din[ 3]; - dout[37] = din[ 5] ^ din[ 2]; - dout[36] = din[ 4] ^ din[ 1]; - dout[35] = din[ 3] ^ din[ 0]; - dout[34] = din[ 2] ^ din[31] ^ din[28]; - dout[33] = din[ 1] ^ din[30] ^ din[27]; - dout[32] = din[ 0] ^ din[29] ^ din[26]; - dout[31] = din[31] ^ din[25]; - dout[30] = din[30] ^ din[24]; - dout[29] = din[29] ^ din[23]; - dout[28] = din[28] ^ din[22]; - dout[27] = din[27] ^ din[21]; - dout[26] = din[26] ^ din[20]; - dout[25] = din[25] ^ din[19]; - dout[24] = din[24] ^ din[18]; - dout[23] = din[23] ^ din[17]; - dout[22] = din[22] ^ din[16]; - dout[21] = din[21] ^ din[15]; - dout[20] = din[20] ^ din[14]; - dout[19] = din[19] ^ din[13]; - dout[18] = din[18] ^ din[12]; - dout[17] = din[17] ^ din[11]; - dout[16] = din[16] ^ din[10]; - dout[15] = din[15] ^ din[ 9]; - dout[14] = din[14] ^ din[ 8]; - dout[13] = din[13] ^ din[ 7]; - dout[12] = din[12] ^ din[ 6]; - dout[11] = din[11] ^ din[ 5]; - dout[10] = din[10] ^ din[ 4]; - dout[ 9] = din[ 9] ^ din[ 3]; - dout[ 8] = din[ 8] ^ din[ 2]; - dout[ 7] = din[ 7] ^ din[ 1]; - dout[ 6] = din[ 6] ^ din[ 0]; - dout[ 5] = din[ 5] ^ din[31] ^ din[28]; - dout[ 4] = din[ 4] ^ din[30] ^ din[27]; - dout[ 3] = din[ 3] ^ din[29] ^ din[26]; - dout[ 2] = din[ 2] ^ din[28] ^ din[25]; - dout[ 1] = din[ 1] ^ din[27] ^ din[24]; - dout[ 0] = din[ 0] ^ din[26] ^ din[23]; - pn31 = dout; - end - endfunction + assign dac_pn7_data_s = dac_pn7_data; + assign dac_pn15_data_s = dac_pn15_data; // dac data select always @(posedge dac_clk) begin dac_enable <= (dac_data_sel_s == 4'h2) ? 1'b1 : 1'b0; case (dac_data_sel_s) - 4'h7: dac_data <= dac_pn31_data; - 4'h6: dac_data <= dac_pn23_data; - 4'h5: dac_data <= dac_pn15_data; - 4'h4: dac_data <= dac_pn7_data; + 4'h7: dac_data <= dac_pn15_data_s; + 4'h6: dac_data <= dac_pn7_data_s; + 4'h5: dac_data <= dac_pn15_data_i_s; + 4'h4: dac_data <= dac_pn7_data_i_s; 4'h3: dac_data <= 64'd0; 4'h2: dac_data <= dma_data; 4'h1: dac_data <= { dac_pat_data_2_s, dac_pat_data_1_s, @@ -453,13 +311,9 @@ module axi_ad9152_channel ( if (dac_data_sync == 1'b1) begin dac_pn7_data <= {64{1'd1}}; dac_pn15_data <= {64{1'd1}}; - dac_pn23_data <= {64{1'd1}}; - dac_pn31_data <= {64{1'd1}}; end else begin - dac_pn7_data <= pn7(dac_pn7_data); - dac_pn15_data <= pn15(dac_pn15_data); - dac_pn23_data <= pn23(dac_pn23_data); - dac_pn31_data <= pn31(dac_pn31_data); + dac_pn7_data <= pn7(dac_pn7_data[55:48]); + dac_pn15_data <= pn15(dac_pn15_data[63:48]); end end @@ -556,7 +410,7 @@ module axi_ad9152_channel ( // single channel processor - up_dac_channel #(.DAC_CHANNEL_ID(CHANNEL_ID)) i_up_dac_channel ( + up_dac_channel #(.CHANNEL_ID(CHANNEL_ID)) i_up_dac_channel ( .dac_clk (dac_clk), .dac_rst (dac_rst), .dac_dds_scale_1 (dac_dds_scale_1_s), @@ -568,6 +422,7 @@ module axi_ad9152_channel ( .dac_pat_data_1 (dac_pat_data_1_s), .dac_pat_data_2 (dac_pat_data_2_s), .dac_data_sel (dac_data_sel_s), + .dac_iq_mode (), .dac_iqcor_enb (), .dac_iqcor_coeff_1 (), .dac_iqcor_coeff_2 (), diff --git a/library/axi_ad9152/axi_ad9152_core.v b/library/axi_ad9152/axi_ad9152_core.v index 93cb929ea..e61643f74 100644 --- a/library/axi_ad9152/axi_ad9152_core.v +++ b/library/axi_ad9152/axi_ad9152_core.v @@ -211,6 +211,7 @@ module axi_ad9152_core ( .dac_rst (dac_rst), .dac_sync (dac_sync_s), .dac_frame (), + .dac_clksel (), .dac_par_type (), .dac_par_enb (), .dac_r1_mode (), @@ -224,7 +225,7 @@ module axi_ad9152_core ( .up_drp_wr (), .up_drp_addr (), .up_drp_wdata (), - .up_drp_rdata (16'd0), + .up_drp_rdata (32'd0), .up_drp_ready (1'd0), .up_drp_locked (1'd1), .up_usr_chanmax (), diff --git a/library/axi_ad9152/axi_ad9152_hw.tcl b/library/axi_ad9152/axi_ad9152_hw.tcl index 27c96ffd0..4e86938d7 100755 --- a/library/axi_ad9152/axi_ad9152_hw.tcl +++ b/library/axi_ad9152/axi_ad9152_hw.tcl @@ -14,8 +14,7 @@ set_module_property DISPLAY_NAME axi_ad9152 add_fileset quartus_synth QUARTUS_SYNTH "" "Quartus Synthesis" set_fileset_property quartus_synth TOP_LEVEL axi_ad9152 -add_fileset_file MULT_MACRO.v VERILOG PATH $ad_hdl_dir/library/common/altera/MULT_MACRO.v -add_fileset_file ad_mul.v VERILOG PATH $ad_hdl_dir/library/common/ad_mul.v +add_fileset_file ad_mul.v VERILOG PATH $ad_hdl_dir/library/altera/common/ad_mul.v add_fileset_file ad_dds_sine.v VERILOG PATH $ad_hdl_dir/library/common/ad_dds_sine.v add_fileset_file ad_dds_1.v VERILOG PATH $ad_hdl_dir/library/common/ad_dds_1.v add_fileset_file ad_dds.v VERILOG PATH $ad_hdl_dir/library/common/ad_dds.v @@ -41,6 +40,13 @@ set_parameter_property ID TYPE INTEGER set_parameter_property ID UNITS None set_parameter_property ID HDL_PARAMETER true +add_parameter DEVICE_TYPE INTEGER 0 +set_parameter_property DEVICE_TYPE DEFAULT_VALUE 1 +set_parameter_property DEVICE_TYPE DISPLAY_NAME DEVICE_TYPE +set_parameter_property DEVICE_TYPE TYPE INTEGER +set_parameter_property DEVICE_TYPE UNITS None +set_parameter_property DEVICE_TYPE HDL_PARAMETER true + # axi4 slave add_interface s_axi_clock clock end @@ -76,21 +82,33 @@ add_interface_port s_axi s_axi_rready rready Input 1 # transceiver interface ad_alt_intf clock tx_clk input 1 -ad_alt_intf signal tx_data output 128 data + +add_interface if_tx_data avalon_streaming source +add_interface_port if_tx_data tx_data data output 128 +add_interface_port if_tx_data tx_valid valid output 1 +add_interface_port if_tx_data tx_ready ready input 1 +set_interface_property if_tx_data associatedClock if_tx_clk +set_interface_property if_tx_data dataBitsPerSymbol 128 # dma interface ad_alt_intf clock dac_clk output 1 -add_interface fifo_ch_0_out conduit end -add_interface_port fifo_ch_0_out dac_enable_0 enable Output 1 -add_interface_port fifo_ch_0_out dac_valid_0 valid Output 1 -add_interface_port fifo_ch_0_out dac_ddata_0 data Input 64 +add_interface dac_ch_0 conduit end +add_interface_port dac_ch_0 dac_enable_0 enable Output 1 +add_interface_port dac_ch_0 dac_valid_0 valid Output 1 +add_interface_port dac_ch_0 dac_ddata_0 data Input 64 -add_interface fifo_ch_1_out conduit end -add_interface_port fifo_ch_1_out dac_enable_1 enable Output 1 -add_interface_port fifo_ch_1_out dac_valid_1 valid Output 1 -add_interface_port fifo_ch_1_out dac_ddata_1 data Input 64 +set_interface_property dac_ch_0 associatedClock if_tx_clk +set_interface_property dac_ch_0 associatedReset none + +add_interface dac_ch_1 conduit end +add_interface_port dac_ch_1 dac_enable_1 enable Output 1 +add_interface_port dac_ch_1 dac_valid_1 valid Output 1 +add_interface_port dac_ch_1 dac_ddata_1 data Input 64 + +set_interface_property dac_ch_1 associatedClock if_tx_clk +set_interface_property dac_ch_1 associatedReset none ad_alt_intf signal dac_dovf input 1 ovf ad_alt_intf signal dac_dunf input 1 unf diff --git a/library/axi_ad9152/axi_ad9152_if.v b/library/axi_ad9152/axi_ad9152_if.v index 9275f809b..523888e03 100644 --- a/library/axi_ad9152/axi_ad9152_if.v +++ b/library/axi_ad9152/axi_ad9152_if.v @@ -41,49 +41,30 @@ `timescale 1ns/100ps -module axi_ad9152_if ( +module axi_ad9152_if #( + + // altera (0x1) or xilinx (0x0) + + parameter DEVICE_TYPE = 0)( // jesd interface // tx_clk is (line-rate/40) - tx_clk, - tx_data, + input tx_clk, + output reg [127:0] tx_data, // dac interface - dac_clk, - dac_rst, - dac_data_0_0, - dac_data_0_1, - dac_data_0_2, - dac_data_0_3, - dac_data_1_0, - dac_data_1_1, - dac_data_1_2, - dac_data_1_3); - - // jesd interface - // tx_clk is (line-rate/40) - - input tx_clk; - output [127:0] tx_data; - - // dac interface - - output dac_clk; - input dac_rst; - input [15:0] dac_data_0_0; - input [15:0] dac_data_0_1; - input [15:0] dac_data_0_2; - input [15:0] dac_data_0_3; - input [15:0] dac_data_1_0; - input [15:0] dac_data_1_1; - input [15:0] dac_data_1_2; - input [15:0] dac_data_1_3; - - // internal registers - - reg [127:0] tx_data = 'd0; + output dac_clk, + input dac_rst, + input [15:0] dac_data_0_0, + input [15:0] dac_data_0_1, + input [15:0] dac_data_0_2, + input [15:0] dac_data_0_3, + input [15:0] dac_data_1_0, + input [15:0] dac_data_1_1, + input [15:0] dac_data_1_2, + input [15:0] dac_data_1_3); // reorder data for the jesd links @@ -93,22 +74,22 @@ module axi_ad9152_if ( if (dac_rst == 1'b1) begin tx_data <= 128'd0; end else begin - tx_data[127:120] <= dac_data_1_3[ 7: 0]; - tx_data[119:112] <= dac_data_1_2[ 7: 0]; - tx_data[111:104] <= dac_data_1_1[ 7: 0]; - tx_data[103: 96] <= dac_data_1_0[ 7: 0]; - tx_data[ 95: 88] <= dac_data_1_3[15: 8]; - tx_data[ 87: 80] <= dac_data_1_2[15: 8]; - tx_data[ 79: 72] <= dac_data_1_1[15: 8]; - tx_data[ 71: 64] <= dac_data_1_0[15: 8]; - tx_data[ 63: 56] <= dac_data_0_3[ 7: 0]; - tx_data[ 55: 48] <= dac_data_0_2[ 7: 0]; - tx_data[ 47: 40] <= dac_data_0_1[ 7: 0]; - tx_data[ 39: 32] <= dac_data_0_0[ 7: 0]; - tx_data[ 31: 24] <= dac_data_0_3[15: 8]; - tx_data[ 23: 16] <= dac_data_0_2[15: 8]; - tx_data[ 15: 8] <= dac_data_0_1[15: 8]; - tx_data[ 7: 0] <= dac_data_0_0[15: 8]; + tx_data[127:120] <= (DEVICE_TYPE == 1) ? dac_data_1_0[ 7: 0] : dac_data_1_3[ 7: 0]; + tx_data[119:112] <= (DEVICE_TYPE == 1) ? dac_data_1_1[ 7: 0] : dac_data_1_2[ 7: 0]; + tx_data[111:104] <= (DEVICE_TYPE == 1) ? dac_data_1_2[ 7: 0] : dac_data_1_1[ 7: 0]; + tx_data[103: 96] <= (DEVICE_TYPE == 1) ? dac_data_1_3[ 7: 0] : dac_data_1_0[ 7: 0]; + tx_data[ 95: 88] <= (DEVICE_TYPE == 1) ? dac_data_1_0[15: 8] : dac_data_1_3[15: 8]; + tx_data[ 87: 80] <= (DEVICE_TYPE == 1) ? dac_data_1_1[15: 8] : dac_data_1_2[15: 8]; + tx_data[ 79: 72] <= (DEVICE_TYPE == 1) ? dac_data_1_2[15: 8] : dac_data_1_1[15: 8]; + tx_data[ 71: 64] <= (DEVICE_TYPE == 1) ? dac_data_1_3[15: 8] : dac_data_1_0[15: 8]; + tx_data[ 63: 56] <= (DEVICE_TYPE == 1) ? dac_data_0_0[ 7: 0] : dac_data_0_3[ 7: 0]; + tx_data[ 55: 48] <= (DEVICE_TYPE == 1) ? dac_data_0_1[ 7: 0] : dac_data_0_2[ 7: 0]; + tx_data[ 47: 40] <= (DEVICE_TYPE == 1) ? dac_data_0_2[ 7: 0] : dac_data_0_1[ 7: 0]; + tx_data[ 39: 32] <= (DEVICE_TYPE == 1) ? dac_data_0_3[ 7: 0] : dac_data_0_0[ 7: 0]; + tx_data[ 31: 24] <= (DEVICE_TYPE == 1) ? dac_data_0_0[15: 8] : dac_data_0_3[15: 8]; + tx_data[ 23: 16] <= (DEVICE_TYPE == 1) ? dac_data_0_1[15: 8] : dac_data_0_2[15: 8]; + tx_data[ 15: 8] <= (DEVICE_TYPE == 1) ? dac_data_0_2[15: 8] : dac_data_0_1[15: 8]; + tx_data[ 7: 0] <= (DEVICE_TYPE == 1) ? dac_data_0_3[15: 8] : dac_data_0_0[15: 8]; end end diff --git a/library/axi_ad9152/axi_ad9152_ip.tcl b/library/axi_ad9152/axi_ad9152_ip.tcl index 5f67222e0..9fb507c42 100644 --- a/library/axi_ad9152/axi_ad9152_ip.tcl +++ b/library/axi_ad9152/axi_ad9152_ip.tcl @@ -6,7 +6,7 @@ source $ad_hdl_dir/library/scripts/adi_ip.tcl adi_ip_create axi_ad9152 adi_ip_files axi_ad9152 [list \ "$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc" \ - "$ad_hdl_dir/library/common/ad_mul.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_mul.v" \ "$ad_hdl_dir/library/common/ad_dds_sine.v" \ "$ad_hdl_dir/library/common/ad_dds_1.v" \ "$ad_hdl_dir/library/common/ad_dds.v" \ @@ -29,6 +29,7 @@ adi_ip_constraints axi_ad9152 [list \ set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]] set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]] +set_property driver_value 0 [ipx::get_ports *tx_ready* -of_objects [ipx::current_core]] ipx::save_core [ipx::current_core] diff --git a/library/axi_ad9162/Makefile b/library/axi_ad9162/Makefile new file mode 100644 index 000000000..874689463 --- /dev/null +++ b/library/axi_ad9162/Makefile @@ -0,0 +1,61 @@ +#################################################################################### +#################################################################################### +## Copyright 2011(c) Analog Devices, Inc. +## Auto-generated, do not modify! +#################################################################################### +#################################################################################### + +M_DEPS += ../common/ad_axi_ip_constr.xdc +M_DEPS += ../common/ad_dds.v +M_DEPS += ../common/ad_dds_1.v +M_DEPS += ../common/ad_dds_sine.v +M_DEPS += ../common/ad_rst.v +M_DEPS += ../common/up_axi.v +M_DEPS += ../common/up_clock_mon.v +M_DEPS += ../common/up_dac_channel.v +M_DEPS += ../common/up_dac_common.v +M_DEPS += ../common/up_xfer_cntrl.v +M_DEPS += ../common/up_xfer_status.v +M_DEPS += ../scripts/adi_env.tcl +M_DEPS += ../scripts/adi_ip.tcl +M_DEPS += ../xilinx/common/ad_mul.v +M_DEPS += axi_ad9162.v +M_DEPS += axi_ad9162_channel.v +M_DEPS += axi_ad9162_core.v +M_DEPS += axi_ad9162_if.v +M_DEPS += axi_ad9162_ip.tcl + +M_VIVADO := vivado -mode batch -source + +M_FLIST := *.cache +M_FLIST += *.data +M_FLIST += *.xpr +M_FLIST += *.log +M_FLIST += component.xml +M_FLIST += *.jou +M_FLIST += xgui +M_FLIST += *.ip_user_files +M_FLIST += *.srcs +M_FLIST += *.hw +M_FLIST += *.sim +M_FLIST += .Xil + + + +.PHONY: all clean clean-all +all: axi_ad9162.xpr + + +clean:clean-all + + +clean-all: + rm -rf $(M_FLIST) + + +axi_ad9162.xpr: $(M_DEPS) + -rm -rf $(M_FLIST) + $(M_VIVADO) axi_ad9162_ip.tcl >> axi_ad9162_ip.log 2>&1 + +#################################################################################### +#################################################################################### diff --git a/library/axi_ad9162/axi_ad9162.v b/library/axi_ad9162/axi_ad9162.v new file mode 100644 index 000000000..0912cbc2d --- /dev/null +++ b/library/axi_ad9162/axi_ad9162.v @@ -0,0 +1,225 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns / 1ps + +module axi_ad9162 ( + + // jesd interface + // tx_clk is (line-rate/40) + + tx_clk, + tx_valid, + tx_data, + tx_ready, + + // dma interface + + dac_clk, + dac_valid, + dac_enable, + dac_ddata, + dac_dovf, + dac_dunf, + + // axi interface + + s_axi_aclk, + s_axi_aresetn, + s_axi_awvalid, + s_axi_awaddr, + s_axi_awprot, + s_axi_awready, + s_axi_wvalid, + s_axi_wdata, + s_axi_wstrb, + s_axi_wready, + s_axi_bvalid, + s_axi_bresp, + s_axi_bready, + s_axi_arvalid, + s_axi_araddr, + s_axi_arprot, + s_axi_arready, + s_axi_rvalid, + s_axi_rdata, + s_axi_rresp, + s_axi_rready); + + // parameters + + parameter ID = 0; + parameter DEVICE_TYPE = 0; + parameter DAC_DATAPATH_DISABLE = 0; + + // jesd interface + // tx_clk is (line-rate/40) + + input tx_clk; + output tx_valid; + output [255:0] tx_data; + input tx_ready; + + // dma interface + + output dac_clk; + output dac_valid; + output dac_enable; + input [255:0] dac_ddata; + input dac_dovf; + input dac_dunf; + + // axi interface + + input s_axi_aclk; + input s_axi_aresetn; + input s_axi_awvalid; + input [ 31:0] s_axi_awaddr; + input [ 2:0] s_axi_awprot; + output s_axi_awready; + input s_axi_wvalid; + input [ 31:0] s_axi_wdata; + input [ 3:0] s_axi_wstrb; + output s_axi_wready; + output s_axi_bvalid; + output [ 1:0] s_axi_bresp; + input s_axi_bready; + input s_axi_arvalid; + input [ 31:0] s_axi_araddr; + input [ 2:0] s_axi_arprot; + output s_axi_arready; + output s_axi_rvalid; + output [ 31:0] s_axi_rdata; + output [ 1:0] s_axi_rresp; + input s_axi_rready; + + // internal clocks and resets + + wire dac_rst; + wire up_clk; + wire up_rstn; + + // internal signals + + wire [255:0] dac_data_s; + wire up_wreq_s; + wire [ 13:0] up_waddr_s; + wire [ 31:0] up_wdata_s; + wire up_wack_s; + wire up_rreq_s; + wire [ 13:0] up_raddr_s; + wire [ 31:0] up_rdata_s; + wire up_rack_s; + + // signal name changes + + assign up_clk = s_axi_aclk; + assign up_rstn = s_axi_aresetn; + + // defaults + + assign tx_valid = 1'b1; + + // device interface + + axi_ad9162_if #(.DEVICE_TYPE (DEVICE_TYPE)) i_if ( + .tx_clk (tx_clk), + .tx_data (tx_data), + .dac_clk (dac_clk), + .dac_rst (dac_rst), + .dac_data (dac_data_s)); + + // core + + axi_ad9162_core #( + .ID (ID), + .DATAPATH_DISABLE (DAC_DATAPATH_DISABLE)) + i_core ( + .dac_clk (dac_clk), + .dac_rst (dac_rst), + .dac_data (dac_data_s), + .dac_valid (dac_valid), + .dac_enable (dac_enable), + .dac_ddata (dac_ddata), + .dac_dovf (dac_dovf), + .dac_dunf (dac_dunf), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack_s), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata_s), + .up_rack (up_rack_s)); + + // up bus interface + + up_axi i_up_axi ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_axi_awvalid (s_axi_awvalid), + .up_axi_awaddr (s_axi_awaddr), + .up_axi_awready (s_axi_awready), + .up_axi_wvalid (s_axi_wvalid), + .up_axi_wdata (s_axi_wdata), + .up_axi_wstrb (s_axi_wstrb), + .up_axi_wready (s_axi_wready), + .up_axi_bvalid (s_axi_bvalid), + .up_axi_bresp (s_axi_bresp), + .up_axi_bready (s_axi_bready), + .up_axi_arvalid (s_axi_arvalid), + .up_axi_araddr (s_axi_araddr), + .up_axi_arready (s_axi_arready), + .up_axi_rvalid (s_axi_rvalid), + .up_axi_rresp (s_axi_rresp), + .up_axi_rdata (s_axi_rdata), + .up_axi_rready (s_axi_rready), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack_s), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata_s), + .up_rack (up_rack_s)); + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/library/axi_ad9162/axi_ad9162_channel.v b/library/axi_ad9162/axi_ad9162_channel.v new file mode 100644 index 000000000..d13fd047e --- /dev/null +++ b/library/axi_ad9162/axi_ad9162_channel.v @@ -0,0 +1,502 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns / 1ps + +module axi_ad9162_channel ( + + // dac interface + + dac_clk, + dac_rst, + dac_enable, + dac_data, + dma_data, + + // processor interface + + dac_data_sync, + dac_dds_format, + + // bus interface + + up_rstn, + up_clk, + up_wreq, + up_waddr, + up_wdata, + up_wack, + up_rreq, + up_raddr, + up_rdata, + up_rack); + + // parameters + + parameter CHANNEL_ID = 32'h0; + parameter DATAPATH_DISABLE = 0; + + // dac interface + + input dac_clk; + input dac_rst; + output dac_enable; + output [255:0] dac_data; + input [255:0] dma_data; + + // processor interface + + input dac_data_sync; + input dac_dds_format; + + // bus interface + + input up_rstn; + input up_clk; + input up_wreq; + input [ 13:0] up_waddr; + input [ 31:0] up_wdata; + output up_wack; + input up_rreq; + input [ 13:0] up_raddr; + output [ 31:0] up_rdata; + output up_rack; + + // internal registers + + reg dac_enable = 'd0; + reg [255:0] dac_data = 'd0; + reg [255:0] dac_data_int = 'd0; + reg [ 15:0] dac_dds_phase_00_0 = 'd0; + reg [ 15:0] dac_dds_phase_00_1 = 'd0; + reg [ 15:0] dac_dds_phase_01_0 = 'd0; + reg [ 15:0] dac_dds_phase_01_1 = 'd0; + reg [ 15:0] dac_dds_phase_02_0 = 'd0; + reg [ 15:0] dac_dds_phase_02_1 = 'd0; + reg [ 15:0] dac_dds_phase_03_0 = 'd0; + reg [ 15:0] dac_dds_phase_03_1 = 'd0; + reg [ 15:0] dac_dds_phase_04_0 = 'd0; + reg [ 15:0] dac_dds_phase_04_1 = 'd0; + reg [ 15:0] dac_dds_phase_05_0 = 'd0; + reg [ 15:0] dac_dds_phase_05_1 = 'd0; + reg [ 15:0] dac_dds_phase_06_0 = 'd0; + reg [ 15:0] dac_dds_phase_06_1 = 'd0; + reg [ 15:0] dac_dds_phase_07_0 = 'd0; + reg [ 15:0] dac_dds_phase_07_1 = 'd0; + reg [ 15:0] dac_dds_phase_08_0 = 'd0; + reg [ 15:0] dac_dds_phase_08_1 = 'd0; + reg [ 15:0] dac_dds_phase_09_0 = 'd0; + reg [ 15:0] dac_dds_phase_09_1 = 'd0; + reg [ 15:0] dac_dds_phase_10_0 = 'd0; + reg [ 15:0] dac_dds_phase_10_1 = 'd0; + reg [ 15:0] dac_dds_phase_11_0 = 'd0; + reg [ 15:0] dac_dds_phase_11_1 = 'd0; + reg [ 15:0] dac_dds_phase_12_0 = 'd0; + reg [ 15:0] dac_dds_phase_12_1 = 'd0; + reg [ 15:0] dac_dds_phase_13_0 = 'd0; + reg [ 15:0] dac_dds_phase_13_1 = 'd0; + reg [ 15:0] dac_dds_phase_14_0 = 'd0; + reg [ 15:0] dac_dds_phase_14_1 = 'd0; + reg [ 15:0] dac_dds_phase_15_0 = 'd0; + reg [ 15:0] dac_dds_phase_15_1 = 'd0; + reg [ 15:0] dac_dds_incr_0 = 'd0; + reg [ 15:0] dac_dds_incr_1 = 'd0; + reg [255:0] dac_dds_data = 'd0; + + // internal signals + + wire [ 15:0] dac_dds_scale_1_s; + wire [ 15:0] dac_dds_init_1_s; + wire [ 15:0] dac_dds_incr_1_s; + wire [ 15:0] dac_dds_scale_2_s; + wire [ 15:0] dac_dds_init_2_s; + wire [ 15:0] dac_dds_incr_2_s; + wire [ 15:0] dac_pat_data_1_s; + wire [ 15:0] dac_pat_data_2_s; + wire [ 3:0] dac_data_sel_s; + wire dac_iq_mode_s; + wire [255:0] dac_pat_data_s; + wire [255:0] dac_dds_data_s; + + // dac sample mux + + always @(posedge dac_clk) begin + dac_data[255:240] <= (dac_iq_mode_s == 1'b1) ? dac_data_int[255:240] : dac_data_int[255:240]; + dac_data[239:224] <= (dac_iq_mode_s == 1'b1) ? dac_data_int[223:208] : dac_data_int[239:224]; + dac_data[223:208] <= (dac_iq_mode_s == 1'b1) ? dac_data_int[239:224] : dac_data_int[223:208]; + dac_data[207:192] <= (dac_iq_mode_s == 1'b1) ? dac_data_int[207:192] : dac_data_int[207:192]; + dac_data[191:176] <= (dac_iq_mode_s == 1'b1) ? dac_data_int[191:176] : dac_data_int[191:176]; + dac_data[175:160] <= (dac_iq_mode_s == 1'b1) ? dac_data_int[159:144] : dac_data_int[175:160]; + dac_data[159:144] <= (dac_iq_mode_s == 1'b1) ? dac_data_int[175:160] : dac_data_int[159:144]; + dac_data[143:128] <= (dac_iq_mode_s == 1'b1) ? dac_data_int[143:128] : dac_data_int[143:128]; + dac_data[127:112] <= (dac_iq_mode_s == 1'b1) ? dac_data_int[127:112] : dac_data_int[127:112]; + dac_data[111: 96] <= (dac_iq_mode_s == 1'b1) ? dac_data_int[ 95: 80] : dac_data_int[111: 96]; + dac_data[ 95: 80] <= (dac_iq_mode_s == 1'b1) ? dac_data_int[111: 96] : dac_data_int[ 95: 80]; + dac_data[ 79: 64] <= (dac_iq_mode_s == 1'b1) ? dac_data_int[ 79: 64] : dac_data_int[ 79: 64]; + dac_data[ 63: 48] <= (dac_iq_mode_s == 1'b1) ? dac_data_int[ 63: 48] : dac_data_int[ 63: 48]; + dac_data[ 47: 32] <= (dac_iq_mode_s == 1'b1) ? dac_data_int[ 31: 16] : dac_data_int[ 47: 32]; + dac_data[ 31: 16] <= (dac_iq_mode_s == 1'b1) ? dac_data_int[ 47: 32] : dac_data_int[ 31: 16]; + dac_data[ 15: 0] <= (dac_iq_mode_s == 1'b1) ? dac_data_int[ 15: 0] : dac_data_int[ 15: 0]; + end + + // dac pattern data + + genvar n; + generate + for (n = 0; n < 8; n = n + 1) begin: g_dac_pat_data + assign dac_pat_data_s[((32*n)+31):((32*n)+16)] = dac_pat_data_2_s; + assign dac_pat_data_s[((32*n)+15):((32*n)+ 0)] = dac_pat_data_1_s; + end + endgenerate + + // dac data select + + always @(posedge dac_clk) begin + dac_enable <= (dac_data_sel_s == 4'h2) ? 1'b1 : 1'b0; + case (dac_data_sel_s) + 4'h3: dac_data_int <= 256'd0; + 4'h2: dac_data_int <= dma_data; + 4'h1: dac_data_int <= dac_pat_data_s; + default: dac_data_int <= dac_dds_data; + endcase + end + + // dds + + always @(posedge dac_clk) begin + if (dac_data_sync == 1'b0) begin + dac_dds_phase_00_0 <= dac_dds_phase_00_0 + dac_dds_incr_0; + dac_dds_phase_00_1 <= dac_dds_phase_00_1 + dac_dds_incr_1; + dac_dds_phase_01_0 <= dac_dds_phase_01_0 + dac_dds_incr_0; + dac_dds_phase_01_1 <= dac_dds_phase_01_1 + dac_dds_incr_1; + dac_dds_phase_02_0 <= dac_dds_phase_02_0 + dac_dds_incr_0; + dac_dds_phase_02_1 <= dac_dds_phase_02_1 + dac_dds_incr_1; + dac_dds_phase_03_0 <= dac_dds_phase_03_0 + dac_dds_incr_0; + dac_dds_phase_03_1 <= dac_dds_phase_03_1 + dac_dds_incr_1; + dac_dds_phase_04_0 <= dac_dds_phase_04_0 + dac_dds_incr_0; + dac_dds_phase_04_1 <= dac_dds_phase_04_1 + dac_dds_incr_1; + dac_dds_phase_05_0 <= dac_dds_phase_05_0 + dac_dds_incr_0; + dac_dds_phase_05_1 <= dac_dds_phase_05_1 + dac_dds_incr_1; + dac_dds_phase_06_0 <= dac_dds_phase_06_0 + dac_dds_incr_0; + dac_dds_phase_06_1 <= dac_dds_phase_06_1 + dac_dds_incr_1; + dac_dds_phase_07_0 <= dac_dds_phase_07_0 + dac_dds_incr_0; + dac_dds_phase_07_1 <= dac_dds_phase_07_1 + dac_dds_incr_1; + dac_dds_phase_08_0 <= dac_dds_phase_08_0 + dac_dds_incr_0; + dac_dds_phase_08_1 <= dac_dds_phase_08_1 + dac_dds_incr_1; + dac_dds_phase_09_0 <= dac_dds_phase_09_0 + dac_dds_incr_0; + dac_dds_phase_09_1 <= dac_dds_phase_09_1 + dac_dds_incr_1; + dac_dds_phase_10_0 <= dac_dds_phase_10_0 + dac_dds_incr_0; + dac_dds_phase_10_1 <= dac_dds_phase_10_1 + dac_dds_incr_1; + dac_dds_phase_11_0 <= dac_dds_phase_11_0 + dac_dds_incr_0; + dac_dds_phase_11_1 <= dac_dds_phase_11_1 + dac_dds_incr_1; + dac_dds_phase_12_0 <= dac_dds_phase_12_0 + dac_dds_incr_0; + dac_dds_phase_12_1 <= dac_dds_phase_12_1 + dac_dds_incr_1; + dac_dds_phase_13_0 <= dac_dds_phase_13_0 + dac_dds_incr_0; + dac_dds_phase_13_1 <= dac_dds_phase_13_1 + dac_dds_incr_1; + dac_dds_phase_14_0 <= dac_dds_phase_14_0 + dac_dds_incr_0; + dac_dds_phase_14_1 <= dac_dds_phase_14_1 + dac_dds_incr_1; + dac_dds_phase_15_0 <= dac_dds_phase_15_0 + dac_dds_incr_0; + dac_dds_phase_15_1 <= dac_dds_phase_15_1 + dac_dds_incr_1; + dac_dds_incr_0 <= dac_dds_incr_0; + dac_dds_incr_1 <= dac_dds_incr_1; + dac_dds_data <= dac_dds_data_s; + end else if (dac_iq_mode_s == 1'b1) begin + dac_dds_phase_00_0 <= dac_dds_init_1_s; + dac_dds_phase_00_1 <= dac_dds_init_2_s; + dac_dds_phase_01_0 <= dac_dds_phase_00_0 + 16'h4000; + dac_dds_phase_01_1 <= dac_dds_phase_00_1 + 16'h4000; + dac_dds_phase_02_0 <= dac_dds_phase_00_0 + dac_dds_incr_1_s; + dac_dds_phase_02_1 <= dac_dds_phase_00_1 + dac_dds_incr_2_s; + dac_dds_phase_03_0 <= dac_dds_phase_02_0 + 16'h4000; + dac_dds_phase_03_1 <= dac_dds_phase_02_1 + 16'h4000; + dac_dds_phase_04_0 <= dac_dds_phase_02_0 + dac_dds_incr_1_s; + dac_dds_phase_04_1 <= dac_dds_phase_02_1 + dac_dds_incr_2_s; + dac_dds_phase_05_0 <= dac_dds_phase_04_0 + 16'h4000; + dac_dds_phase_05_1 <= dac_dds_phase_04_1 + 16'h4000; + dac_dds_phase_06_0 <= dac_dds_phase_04_0 + dac_dds_incr_1_s; + dac_dds_phase_06_1 <= dac_dds_phase_04_1 + dac_dds_incr_2_s; + dac_dds_phase_07_0 <= dac_dds_phase_06_0 + 16'h4000; + dac_dds_phase_07_1 <= dac_dds_phase_06_1 + 16'h4000; + dac_dds_phase_08_0 <= dac_dds_phase_06_0 + dac_dds_incr_1_s; + dac_dds_phase_08_1 <= dac_dds_phase_06_1 + dac_dds_incr_2_s; + dac_dds_phase_09_0 <= dac_dds_phase_08_0 + 16'h4000; + dac_dds_phase_09_1 <= dac_dds_phase_08_1 + 16'h4000; + dac_dds_phase_10_0 <= dac_dds_phase_08_0 + dac_dds_incr_1_s; + dac_dds_phase_10_1 <= dac_dds_phase_08_1 + dac_dds_incr_2_s; + dac_dds_phase_11_0 <= dac_dds_phase_10_0 + 16'h4000; + dac_dds_phase_11_1 <= dac_dds_phase_10_1 + 16'h4000; + dac_dds_phase_12_0 <= dac_dds_phase_10_0 + dac_dds_incr_1_s; + dac_dds_phase_12_1 <= dac_dds_phase_10_1 + dac_dds_incr_2_s; + dac_dds_phase_13_0 <= dac_dds_phase_12_0 + 16'h4000; + dac_dds_phase_13_1 <= dac_dds_phase_12_1 + 16'h4000; + dac_dds_phase_14_0 <= dac_dds_phase_12_0 + dac_dds_incr_1_s; + dac_dds_phase_14_1 <= dac_dds_phase_12_1 + dac_dds_incr_2_s; + dac_dds_phase_15_0 <= dac_dds_phase_14_0 + 16'h4000; + dac_dds_phase_15_1 <= dac_dds_phase_14_1 + 16'h4000; + dac_dds_incr_0 <= {dac_dds_incr_1_s[12:0], 3'd0}; + dac_dds_incr_1 <= {dac_dds_incr_2_s[12:0], 3'd0}; + dac_dds_data <= 256'd0; + end else begin + dac_dds_phase_00_0 <= dac_dds_init_1_s; + dac_dds_phase_00_1 <= dac_dds_init_2_s; + dac_dds_phase_01_0 <= dac_dds_phase_00_0 + dac_dds_incr_1_s; + dac_dds_phase_01_1 <= dac_dds_phase_00_1 + dac_dds_incr_2_s; + dac_dds_phase_02_0 <= dac_dds_phase_01_0 + dac_dds_incr_1_s; + dac_dds_phase_02_1 <= dac_dds_phase_01_1 + dac_dds_incr_2_s; + dac_dds_phase_03_0 <= dac_dds_phase_02_0 + dac_dds_incr_1_s; + dac_dds_phase_03_1 <= dac_dds_phase_02_1 + dac_dds_incr_2_s; + dac_dds_phase_04_0 <= dac_dds_phase_03_0 + dac_dds_incr_1_s; + dac_dds_phase_04_1 <= dac_dds_phase_03_1 + dac_dds_incr_2_s; + dac_dds_phase_05_0 <= dac_dds_phase_04_0 + dac_dds_incr_1_s; + dac_dds_phase_05_1 <= dac_dds_phase_04_1 + dac_dds_incr_2_s; + dac_dds_phase_06_0 <= dac_dds_phase_05_0 + dac_dds_incr_1_s; + dac_dds_phase_06_1 <= dac_dds_phase_05_1 + dac_dds_incr_2_s; + dac_dds_phase_07_0 <= dac_dds_phase_06_0 + dac_dds_incr_1_s; + dac_dds_phase_07_1 <= dac_dds_phase_06_1 + dac_dds_incr_2_s; + dac_dds_phase_08_0 <= dac_dds_phase_07_0 + dac_dds_incr_1_s; + dac_dds_phase_08_1 <= dac_dds_phase_07_1 + dac_dds_incr_2_s; + dac_dds_phase_09_0 <= dac_dds_phase_08_0 + dac_dds_incr_1_s; + dac_dds_phase_09_1 <= dac_dds_phase_08_1 + dac_dds_incr_2_s; + dac_dds_phase_10_0 <= dac_dds_phase_09_0 + dac_dds_incr_1_s; + dac_dds_phase_10_1 <= dac_dds_phase_09_1 + dac_dds_incr_2_s; + dac_dds_phase_11_0 <= dac_dds_phase_10_0 + dac_dds_incr_1_s; + dac_dds_phase_11_1 <= dac_dds_phase_10_1 + dac_dds_incr_2_s; + dac_dds_phase_12_0 <= dac_dds_phase_11_0 + dac_dds_incr_1_s; + dac_dds_phase_12_1 <= dac_dds_phase_11_1 + dac_dds_incr_2_s; + dac_dds_phase_13_0 <= dac_dds_phase_12_0 + dac_dds_incr_1_s; + dac_dds_phase_13_1 <= dac_dds_phase_12_1 + dac_dds_incr_2_s; + dac_dds_phase_14_0 <= dac_dds_phase_13_0 + dac_dds_incr_1_s; + dac_dds_phase_14_1 <= dac_dds_phase_13_1 + dac_dds_incr_2_s; + dac_dds_phase_15_0 <= dac_dds_phase_14_0 + dac_dds_incr_1_s; + dac_dds_phase_15_1 <= dac_dds_phase_14_1 + dac_dds_incr_2_s; + dac_dds_incr_0 <= {dac_dds_incr_1_s[11:0], 4'd0}; + dac_dds_incr_1 <= {dac_dds_incr_2_s[11:0], 4'd0}; + dac_dds_data <= 256'd0; + end + end + + ad_dds #(.DISABLE (DATAPATH_DISABLE)) i_dds_00 ( + .clk (dac_clk), + .dds_format (dac_dds_format), + .dds_phase_0 (dac_dds_phase_00_0), + .dds_scale_0 (dac_dds_scale_1_s), + .dds_phase_1 (dac_dds_phase_00_1), + .dds_scale_1 (dac_dds_scale_2_s), + .dds_data (dac_dds_data_s[15:0])); + + ad_dds #(.DISABLE (DATAPATH_DISABLE)) i_dds_01 ( + .clk (dac_clk), + .dds_format (dac_dds_format), + .dds_phase_0 (dac_dds_phase_01_0), + .dds_scale_0 (dac_dds_scale_1_s), + .dds_phase_1 (dac_dds_phase_01_1), + .dds_scale_1 (dac_dds_scale_2_s), + .dds_data (dac_dds_data_s[31:16])); + + ad_dds #(.DISABLE (DATAPATH_DISABLE)) i_dds_02 ( + .clk (dac_clk), + .dds_format (dac_dds_format), + .dds_phase_0 (dac_dds_phase_02_0), + .dds_scale_0 (dac_dds_scale_1_s), + .dds_phase_1 (dac_dds_phase_02_1), + .dds_scale_1 (dac_dds_scale_2_s), + .dds_data (dac_dds_data_s[47:32])); + + ad_dds #(.DISABLE (DATAPATH_DISABLE)) i_dds_03 ( + .clk (dac_clk), + .dds_format (dac_dds_format), + .dds_phase_0 (dac_dds_phase_03_0), + .dds_scale_0 (dac_dds_scale_1_s), + .dds_phase_1 (dac_dds_phase_03_1), + .dds_scale_1 (dac_dds_scale_2_s), + .dds_data (dac_dds_data_s[63:48])); + + ad_dds #(.DISABLE (DATAPATH_DISABLE)) i_dds_04 ( + .clk (dac_clk), + .dds_format (dac_dds_format), + .dds_phase_0 (dac_dds_phase_04_0), + .dds_scale_0 (dac_dds_scale_1_s), + .dds_phase_1 (dac_dds_phase_04_1), + .dds_scale_1 (dac_dds_scale_2_s), + .dds_data (dac_dds_data_s[79:64])); + + ad_dds #(.DISABLE (DATAPATH_DISABLE)) i_dds_05 ( + .clk (dac_clk), + .dds_format (dac_dds_format), + .dds_phase_0 (dac_dds_phase_05_0), + .dds_scale_0 (dac_dds_scale_1_s), + .dds_phase_1 (dac_dds_phase_05_1), + .dds_scale_1 (dac_dds_scale_2_s), + .dds_data (dac_dds_data_s[95:80])); + + ad_dds #(.DISABLE (DATAPATH_DISABLE)) i_dds_06 ( + .clk (dac_clk), + .dds_format (dac_dds_format), + .dds_phase_0 (dac_dds_phase_06_0), + .dds_scale_0 (dac_dds_scale_1_s), + .dds_phase_1 (dac_dds_phase_06_1), + .dds_scale_1 (dac_dds_scale_2_s), + .dds_data (dac_dds_data_s[111:96])); + + ad_dds #(.DISABLE (DATAPATH_DISABLE)) i_dds_07 ( + .clk (dac_clk), + .dds_format (dac_dds_format), + .dds_phase_0 (dac_dds_phase_07_0), + .dds_scale_0 (dac_dds_scale_1_s), + .dds_phase_1 (dac_dds_phase_07_1), + .dds_scale_1 (dac_dds_scale_2_s), + .dds_data (dac_dds_data_s[127:112])); + + ad_dds #(.DISABLE (DATAPATH_DISABLE)) i_dds_08 ( + .clk (dac_clk), + .dds_format (dac_dds_format), + .dds_phase_0 (dac_dds_phase_08_0), + .dds_scale_0 (dac_dds_scale_1_s), + .dds_phase_1 (dac_dds_phase_08_1), + .dds_scale_1 (dac_dds_scale_2_s), + .dds_data (dac_dds_data_s[143:128])); + + ad_dds #(.DISABLE (DATAPATH_DISABLE)) i_dds_09 ( + .clk (dac_clk), + .dds_format (dac_dds_format), + .dds_phase_0 (dac_dds_phase_09_0), + .dds_scale_0 (dac_dds_scale_1_s), + .dds_phase_1 (dac_dds_phase_09_1), + .dds_scale_1 (dac_dds_scale_2_s), + .dds_data (dac_dds_data_s[159:144])); + + ad_dds #(.DISABLE (DATAPATH_DISABLE)) i_dds_10 ( + .clk (dac_clk), + .dds_format (dac_dds_format), + .dds_phase_0 (dac_dds_phase_10_0), + .dds_scale_0 (dac_dds_scale_1_s), + .dds_phase_1 (dac_dds_phase_10_1), + .dds_scale_1 (dac_dds_scale_2_s), + .dds_data (dac_dds_data_s[175:160])); + + ad_dds #(.DISABLE (DATAPATH_DISABLE)) i_dds_11 ( + .clk (dac_clk), + .dds_format (dac_dds_format), + .dds_phase_0 (dac_dds_phase_11_0), + .dds_scale_0 (dac_dds_scale_1_s), + .dds_phase_1 (dac_dds_phase_11_1), + .dds_scale_1 (dac_dds_scale_2_s), + .dds_data (dac_dds_data_s[191:176])); + + ad_dds #(.DISABLE (DATAPATH_DISABLE)) i_dds_12 ( + .clk (dac_clk), + .dds_format (dac_dds_format), + .dds_phase_0 (dac_dds_phase_12_0), + .dds_scale_0 (dac_dds_scale_1_s), + .dds_phase_1 (dac_dds_phase_12_1), + .dds_scale_1 (dac_dds_scale_2_s), + .dds_data (dac_dds_data_s[207:192])); + + ad_dds #(.DISABLE (DATAPATH_DISABLE)) i_dds_13 ( + .clk (dac_clk), + .dds_format (dac_dds_format), + .dds_phase_0 (dac_dds_phase_13_0), + .dds_scale_0 (dac_dds_scale_1_s), + .dds_phase_1 (dac_dds_phase_13_1), + .dds_scale_1 (dac_dds_scale_2_s), + .dds_data (dac_dds_data_s[223:208])); + + ad_dds #(.DISABLE (DATAPATH_DISABLE)) i_dds_14 ( + .clk (dac_clk), + .dds_format (dac_dds_format), + .dds_phase_0 (dac_dds_phase_14_0), + .dds_scale_0 (dac_dds_scale_1_s), + .dds_phase_1 (dac_dds_phase_14_1), + .dds_scale_1 (dac_dds_scale_2_s), + .dds_data (dac_dds_data_s[239:224])); + + ad_dds #(.DISABLE (DATAPATH_DISABLE)) i_dds_15 ( + .clk (dac_clk), + .dds_format (dac_dds_format), + .dds_phase_0 (dac_dds_phase_15_0), + .dds_scale_0 (dac_dds_scale_1_s), + .dds_phase_1 (dac_dds_phase_15_1), + .dds_scale_1 (dac_dds_scale_2_s), + .dds_data (dac_dds_data_s[255:240])); + + // single channel processor + + up_dac_channel #(.CHANNEL_ID(CHANNEL_ID)) i_up_dac_channel ( + .dac_clk (dac_clk), + .dac_rst (dac_rst), + .dac_dds_scale_1 (dac_dds_scale_1_s), + .dac_dds_init_1 (dac_dds_init_1_s), + .dac_dds_incr_1 (dac_dds_incr_1_s), + .dac_dds_scale_2 (dac_dds_scale_2_s), + .dac_dds_init_2 (dac_dds_init_2_s), + .dac_dds_incr_2 (dac_dds_incr_2_s), + .dac_pat_data_1 (dac_pat_data_1_s), + .dac_pat_data_2 (dac_pat_data_2_s), + .dac_data_sel (dac_data_sel_s), + .dac_iq_mode (dac_iq_mode_s), + .dac_iqcor_enb (), + .dac_iqcor_coeff_1 (), + .dac_iqcor_coeff_2 (), + .up_usr_datatype_be (), + .up_usr_datatype_signed (), + .up_usr_datatype_shift (), + .up_usr_datatype_total_bits (), + .up_usr_datatype_bits (), + .up_usr_interpolation_m (), + .up_usr_interpolation_n (), + .dac_usr_datatype_be (1'b0), + .dac_usr_datatype_signed (1'b1), + .dac_usr_datatype_shift (8'd0), + .dac_usr_datatype_total_bits (8'd16), + .dac_usr_datatype_bits (8'd16), + .dac_usr_interpolation_m (16'd1), + .dac_usr_interpolation_n (16'd1), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata), + .up_rack (up_rack)); + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/library/axi_ad9162/axi_ad9162_core.v b/library/axi_ad9162/axi_ad9162_core.v new file mode 100644 index 000000000..8f8555716 --- /dev/null +++ b/library/axi_ad9162/axi_ad9162_core.v @@ -0,0 +1,204 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns / 1ps + +module axi_ad9162_core ( + + // dac interface + + dac_clk, + dac_rst, + dac_data, + + // dma interface + + dac_valid, + dac_enable, + dac_ddata, + dac_dovf, + dac_dunf, + + // processor interface + + up_rstn, + up_clk, + up_wreq, + up_waddr, + up_wdata, + up_wack, + up_rreq, + up_raddr, + up_rdata, + up_rack); + + // parameters + + parameter ID = 0; + parameter DATAPATH_DISABLE = 0; + + // dac interface + + input dac_clk; + output dac_rst; + output [255:0] dac_data; + + // dma interface + + output dac_valid; + output dac_enable; + input [255:0] dac_ddata; + input dac_dovf; + input dac_dunf; + + + // processor interface + + input up_rstn; + input up_clk; + input up_wreq; + input [ 13:0] up_waddr; + input [ 31:0] up_wdata; + output up_wack; + input up_rreq; + input [ 13:0] up_raddr; + output [ 31:0] up_rdata; + output up_rack; + + // internal registers + + reg [ 31:0] up_rdata = 'd0; + reg up_rack = 'd0; + reg up_wack = 'd0; + + // internal signals + + wire dac_sync_s; + wire dac_datafmt_s; + wire [ 31:0] up_rdata_0_s; + wire up_rack_0_s; + wire up_wack_0_s; + wire [ 31:0] up_rdata_s; + wire up_rack_s; + wire up_wack_s; + + // dac valid + + assign dac_valid = 1'b1; + + // processor read interface + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_rdata <= 'd0; + up_rack <= 'd0; + up_wack <= 'd0; + end else begin + up_rdata <= up_rdata_s | up_rdata_0_s; + up_rack <= up_rack_s | up_rack_0_s; + up_wack <= up_wack_s | up_wack_0_s; + end + end + + // dac channel + + axi_ad9162_channel #( + .CHANNEL_ID (0), + .DATAPATH_DISABLE (DATAPATH_DISABLE)) + i_channel_0 ( + .dac_clk (dac_clk), + .dac_rst (dac_rst), + .dac_enable (dac_enable), + .dac_data (dac_data), + .dma_data (dac_ddata), + .dac_data_sync (dac_sync_s), + .dac_dds_format (dac_datafmt_s), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack_0_s), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata_0_s), + .up_rack (up_rack_0_s)); + + // dac common processor interface + + up_dac_common #(.ID(ID)) i_up_dac_common ( + .mmcm_rst (), + .dac_clk (dac_clk), + .dac_rst (dac_rst), + .dac_sync (dac_sync_s), + .dac_frame (), + .dac_clksel (), + .dac_par_type (), + .dac_par_enb (), + .dac_r1_mode (), + .dac_datafmt (dac_datafmt_s), + .dac_datarate (), + .dac_status (1'b1), + .dac_status_ovf (dac_dovf), + .dac_status_unf (dac_dunf), + .dac_clk_ratio (32'd16), + .up_drp_sel (), + .up_drp_wr (), + .up_drp_addr (), + .up_drp_wdata (), + .up_drp_rdata (32'd0), + .up_drp_ready (1'd0), + .up_drp_locked (1'd1), + .up_usr_chanmax (), + .dac_usr_chanmax (8'd0), + .up_dac_gpio_in (32'd0), + .up_dac_gpio_out (), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack_s), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata_s), + .up_rack (up_rack_s)); + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/library/axi_ad9162/axi_ad9162_if.v b/library/axi_ad9162/axi_ad9162_if.v new file mode 100644 index 000000000..f114420a4 --- /dev/null +++ b/library/axi_ad9162/axi_ad9162_if.v @@ -0,0 +1,116 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns / 1ps + +module axi_ad9162_if ( + + // jesd interface + // tx_clk is (line-rate/40) + + tx_clk, + tx_data, + + // dac interface + + dac_clk, + dac_rst, + dac_data); + + // altera (0x1) or xilinx (0x0) + + parameter DEVICE_TYPE = 0; + + // jesd interface + // tx_clk is (line-rate/40) + + input tx_clk; + output [255:0] tx_data; + + // dac interface + + output dac_clk; + input dac_rst; + input [255:0] dac_data; + + // internal registers + + reg [255:0] tx_data = 'd0; + + // reorder data for the jesd links + + assign dac_clk = tx_clk; + + always @(posedge tx_clk) begin + tx_data[255:248] <= (DEVICE_TYPE == 1) ? dac_data[ 55: 48] : dac_data[247:240]; + tx_data[247:240] <= (DEVICE_TYPE == 1) ? dac_data[119:112] : dac_data[183:176]; + tx_data[239:232] <= (DEVICE_TYPE == 1) ? dac_data[183:176] : dac_data[119:112]; + tx_data[231:224] <= (DEVICE_TYPE == 1) ? dac_data[247:240] : dac_data[ 55: 48]; + tx_data[223:216] <= (DEVICE_TYPE == 1) ? dac_data[ 63: 56] : dac_data[255:248]; + tx_data[215:208] <= (DEVICE_TYPE == 1) ? dac_data[127:120] : dac_data[191:184]; + tx_data[207:200] <= (DEVICE_TYPE == 1) ? dac_data[191:184] : dac_data[127:120]; + tx_data[199:192] <= (DEVICE_TYPE == 1) ? dac_data[255:248] : dac_data[ 63: 56]; + tx_data[191:184] <= (DEVICE_TYPE == 1) ? dac_data[ 39: 32] : dac_data[231:224]; + tx_data[183:176] <= (DEVICE_TYPE == 1) ? dac_data[103: 96] : dac_data[167:160]; + tx_data[175:168] <= (DEVICE_TYPE == 1) ? dac_data[167:160] : dac_data[103: 96]; + tx_data[167:160] <= (DEVICE_TYPE == 1) ? dac_data[231:224] : dac_data[ 39: 32]; + tx_data[159:152] <= (DEVICE_TYPE == 1) ? dac_data[ 47: 40] : dac_data[239:232]; + tx_data[151:144] <= (DEVICE_TYPE == 1) ? dac_data[111:104] : dac_data[175:168]; + tx_data[143:136] <= (DEVICE_TYPE == 1) ? dac_data[175:168] : dac_data[111:104]; + tx_data[135:128] <= (DEVICE_TYPE == 1) ? dac_data[239:232] : dac_data[ 47: 40]; + tx_data[127:120] <= (DEVICE_TYPE == 1) ? dac_data[ 23: 16] : dac_data[215:208]; + tx_data[119:112] <= (DEVICE_TYPE == 1) ? dac_data[ 87: 80] : dac_data[151:144]; + tx_data[111:104] <= (DEVICE_TYPE == 1) ? dac_data[151:144] : dac_data[ 87: 80]; + tx_data[103: 96] <= (DEVICE_TYPE == 1) ? dac_data[215:208] : dac_data[ 23: 16]; + tx_data[ 95: 88] <= (DEVICE_TYPE == 1) ? dac_data[ 31: 24] : dac_data[223:216]; + tx_data[ 87: 80] <= (DEVICE_TYPE == 1) ? dac_data[ 95: 88] : dac_data[159:152]; + tx_data[ 79: 72] <= (DEVICE_TYPE == 1) ? dac_data[159:152] : dac_data[ 95: 88]; + tx_data[ 71: 64] <= (DEVICE_TYPE == 1) ? dac_data[223:216] : dac_data[ 31: 24]; + tx_data[ 63: 56] <= (DEVICE_TYPE == 1) ? dac_data[ 7: 0] : dac_data[199:192]; + tx_data[ 55: 48] <= (DEVICE_TYPE == 1) ? dac_data[ 71: 64] : dac_data[135:128]; + tx_data[ 47: 40] <= (DEVICE_TYPE == 1) ? dac_data[135:128] : dac_data[ 71: 64]; + tx_data[ 39: 32] <= (DEVICE_TYPE == 1) ? dac_data[199:192] : dac_data[ 7: 0]; + tx_data[ 31: 24] <= (DEVICE_TYPE == 1) ? dac_data[ 15: 8] : dac_data[207:200]; + tx_data[ 23: 16] <= (DEVICE_TYPE == 1) ? dac_data[ 79: 72] : dac_data[143:136]; + tx_data[ 15: 8] <= (DEVICE_TYPE == 1) ? dac_data[143:136] : dac_data[ 79: 72]; + tx_data[ 7: 0] <= (DEVICE_TYPE == 1) ? dac_data[207:200] : dac_data[ 15: 8]; + end + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/library/axi_ad9162/axi_ad9162_ip.tcl b/library/axi_ad9162/axi_ad9162_ip.tcl new file mode 100644 index 000000000..2439aebe4 --- /dev/null +++ b/library/axi_ad9162/axi_ad9162_ip.tcl @@ -0,0 +1,36 @@ +# ip + +source ../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip.tcl + +adi_ip_create axi_ad9162 +adi_ip_files axi_ad9162 [list \ + "$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc" \ + "$ad_hdl_dir/library/xilinx/common/ad_mul.v" \ + "$ad_hdl_dir/library/common/ad_dds_sine.v" \ + "$ad_hdl_dir/library/common/ad_dds_1.v" \ + "$ad_hdl_dir/library/common/ad_dds.v" \ + "$ad_hdl_dir/library/common/ad_rst.v" \ + "$ad_hdl_dir/library/common/up_axi.v" \ + "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ + "$ad_hdl_dir/library/common/up_xfer_status.v" \ + "$ad_hdl_dir/library/common/up_clock_mon.v" \ + "$ad_hdl_dir/library/common/up_dac_common.v" \ + "$ad_hdl_dir/library/common/up_dac_channel.v" \ + "axi_ad9162_channel.v" \ + "axi_ad9162_core.v" \ + "axi_ad9162_if.v" \ + "axi_ad9162.v" ] + +adi_ip_properties axi_ad9162 + +adi_ip_constraints axi_ad9162 [list \ + "$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc" ] + +set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]] +set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]] +set_property driver_value 0 [ipx::get_ports *tx_ready* -of_objects [ipx::current_core]] + +ipx::save_core [ipx::current_core] + + diff --git a/library/axi_ad9234/Makefile b/library/axi_ad9234/Makefile index d783795ac..ebcef7e79 100644 --- a/library/axi_ad9234/Makefile +++ b/library/axi_ad9234/Makefile @@ -5,22 +5,22 @@ #################################################################################### #################################################################################### -M_DEPS := axi_ad9234_ip.tcl -M_DEPS += ../scripts/adi_env.tcl -M_DEPS += ../scripts/adi_ip.tcl -M_DEPS += ../common/ad_rst.v M_DEPS += ../common/ad_pnmon.v +M_DEPS += ../common/ad_rst.v +M_DEPS += ../common/up_adc_channel.v +M_DEPS += ../common/up_adc_common.v M_DEPS += ../common/up_axi.v +M_DEPS += ../common/up_clock_mon.v M_DEPS += ../common/up_xfer_cntrl.v M_DEPS += ../common/up_xfer_status.v -M_DEPS += ../common/up_clock_mon.v -M_DEPS += ../common/up_adc_common.v -M_DEPS += ../common/up_adc_channel.v -M_DEPS += axi_ad9234_pnmon.v -M_DEPS += axi_ad9234_channel.v -M_DEPS += axi_ad9234_if.v +M_DEPS += ../scripts/adi_env.tcl +M_DEPS += ../scripts/adi_ip.tcl M_DEPS += axi_ad9234.v +M_DEPS += axi_ad9234_channel.v M_DEPS += axi_ad9234_constr.xdc +M_DEPS += axi_ad9234_if.v +M_DEPS += axi_ad9234_ip.tcl +M_DEPS += axi_ad9234_pnmon.v M_VIVADO := vivado -mode batch -source @@ -31,6 +31,10 @@ M_FLIST += *.log M_FLIST += component.xml M_FLIST += *.jou M_FLIST += xgui +M_FLIST += *.ip_user_files +M_FLIST += *.srcs +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil @@ -47,7 +51,7 @@ clean-all: axi_ad9234.xpr: $(M_DEPS) - rm -rf $(M_FLIST) + -rm -rf $(M_FLIST) $(M_VIVADO) axi_ad9234_ip.tcl >> axi_ad9234_ip.log 2>&1 #################################################################################### diff --git a/library/axi_ad9234/axi_ad9234.v b/library/axi_ad9234/axi_ad9234.v index 202909deb..d26b48102 100644 --- a/library/axi_ad9234/axi_ad9234.v +++ b/library/axi_ad9234/axi_ad9234.v @@ -79,7 +79,9 @@ module axi_ad9234 ( s_axi_rvalid, s_axi_rresp, s_axi_rdata, - s_axi_rready); + s_axi_rready, + s_axi_awprot, + s_axi_arprot); parameter ID = 0; parameter DEVICE_TYPE = 0; @@ -124,6 +126,9 @@ module axi_ad9234 ( output [ 1:0] s_axi_rresp; output [31:0] s_axi_rdata; input s_axi_rready; + input [ 2:0] s_axi_awprot; + input [ 2:0] s_axi_arprot; + // internal registers @@ -271,7 +276,7 @@ module axi_ad9234 ( .up_drp_wr (), .up_drp_addr (), .up_drp_wdata (), - .up_drp_rdata (16'd0), + .up_drp_rdata (32'd0), .up_drp_ready (1'd0), .up_drp_locked (1'd1), .up_usr_chanmax (), diff --git a/library/axi_ad9234/axi_ad9234_channel.v b/library/axi_ad9234/axi_ad9234_channel.v index 0c3878127..6bb5c98dd 100644 --- a/library/axi_ad9234/axi_ad9234_channel.v +++ b/library/axi_ad9234/axi_ad9234_channel.v @@ -120,7 +120,7 @@ module axi_ad9234_channel ( assign adc_dfmt_data = adc_data; - up_adc_channel #(.ADC_CHANNEL_ID(CHANNEL_ID)) i_up_adc_channel ( + up_adc_channel #(.CHANNEL_ID(CHANNEL_ID)) i_up_adc_channel ( .adc_clk (adc_clk), .adc_rst (adc_rst), .adc_enable (adc_enable), diff --git a/library/axi_ad9250/Makefile b/library/axi_ad9250/Makefile index d99cf1872..6d8901ff0 100644 --- a/library/axi_ad9250/Makefile +++ b/library/axi_ad9250/Makefile @@ -5,24 +5,25 @@ #################################################################################### #################################################################################### -M_DEPS := axi_ad9250_ip.tcl -M_DEPS += ../scripts/adi_env.tcl -M_DEPS += ../scripts/adi_ip.tcl -M_DEPS += ../common/ad_rst.v -M_DEPS += ../common/ad_pnmon.v +M_DEPS += ../common/ad_axi_ip_constr.xdc M_DEPS += ../common/ad_datafmt.v +M_DEPS += ../common/ad_pnmon.v +M_DEPS += ../common/ad_rst.v +M_DEPS += ../common/ad_xcvr_rx_if.v +M_DEPS += ../common/up_adc_channel.v +M_DEPS += ../common/up_adc_common.v M_DEPS += ../common/up_axi.v +M_DEPS += ../common/up_clock_mon.v M_DEPS += ../common/up_xfer_cntrl.v M_DEPS += ../common/up_xfer_status.v -M_DEPS += ../common/up_clock_mon.v -M_DEPS += ../common/up_adc_common.v -M_DEPS += ../common/up_adc_channel.v -M_DEPS += ../common/ad_axi_ip_constr.xdc -M_DEPS += axi_ad9250_pnmon.v -M_DEPS += axi_ad9250_channel.v -M_DEPS += axi_ad9250_if.v -M_DEPS += axi_ad9250_constr.xdc +M_DEPS += ../scripts/adi_env.tcl +M_DEPS += ../scripts/adi_ip.tcl M_DEPS += axi_ad9250.v +M_DEPS += axi_ad9250_channel.v +M_DEPS += axi_ad9250_constr.xdc +M_DEPS += axi_ad9250_if.v +M_DEPS += axi_ad9250_ip.tcl +M_DEPS += axi_ad9250_pnmon.v M_VIVADO := vivado -mode batch -source @@ -33,6 +34,10 @@ M_FLIST += *.log M_FLIST += component.xml M_FLIST += *.jou M_FLIST += xgui +M_FLIST += *.ip_user_files +M_FLIST += *.srcs +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil @@ -49,7 +54,7 @@ clean-all: axi_ad9250.xpr: $(M_DEPS) - rm -rf $(M_FLIST) + -rm -rf $(M_FLIST) $(M_VIVADO) axi_ad9250_ip.tcl >> axi_ad9250_ip.log 2>&1 #################################################################################### diff --git a/library/axi_ad9250/axi_ad9250.v b/library/axi_ad9250/axi_ad9250.v index 679c22af1..0367c7722 100644 --- a/library/axi_ad9250/axi_ad9250.v +++ b/library/axi_ad9250/axi_ad9250.v @@ -34,8 +34,6 @@ // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // *************************************************************************** // *************************************************************************** -// *************************************************************************** -// *************************************************************************** `timescale 1ns/100ps @@ -45,7 +43,10 @@ module axi_ad9250 ( // rx_clk is (line-rate/40) rx_clk, + rx_sof, + rx_valid, rx_data, + rx_ready, // dma interface @@ -86,13 +87,15 @@ module axi_ad9250 ( parameter ID = 0; parameter DEVICE_TYPE = 0; - parameter IO_DELAY_GROUP = "adc_if_delay_group"; // jesd interface // rx_clk is (line-rate/40) input rx_clk; + input [ 3:0] rx_sof; + input rx_valid; input [63:0] rx_data; + output rx_ready; // dma interface @@ -170,6 +173,10 @@ module axi_ad9250 ( assign up_clk = s_axi_aclk; assign up_rstn = s_axi_aresetn; + // defaults + + assign rx_ready = 1'b1; + // processor read interface always @(negedge up_rstn or posedge up_clk) begin @@ -197,8 +204,9 @@ module axi_ad9250 ( // main (device interface) - axi_ad9250_if i_if ( + axi_ad9250_if #(.DEVICE_TYPE (DEVICE_TYPE)) i_if ( .rx_clk (rx_clk), + .rx_sof (rx_sof), .rx_data (rx_data), .adc_clk (adc_clk), .adc_rst (adc_rst), @@ -277,7 +285,7 @@ module axi_ad9250 ( .up_drp_wr (), .up_drp_addr (), .up_drp_wdata (), - .up_drp_rdata (16'd0), + .up_drp_rdata (32'd0), .up_drp_ready (1'd0), .up_drp_locked (1'd1), .up_usr_chanmax (), diff --git a/library/axi_ad9250/axi_ad9250_channel.v b/library/axi_ad9250/axi_ad9250_channel.v index c5e6b2e6b..41c766ad9 100644 --- a/library/axi_ad9250/axi_ad9250_channel.v +++ b/library/axi_ad9250/axi_ad9250_channel.v @@ -136,7 +136,7 @@ module axi_ad9250_channel ( end endgenerate - up_adc_channel #(.ADC_CHANNEL_ID(CHANNEL_ID)) i_up_adc_channel ( + up_adc_channel #(.CHANNEL_ID(CHANNEL_ID)) i_up_adc_channel ( .adc_clk (adc_clk), .adc_rst (adc_rst), .adc_enable (adc_enable), diff --git a/library/axi_ad9250/axi_ad9250_hw.tcl b/library/axi_ad9250/axi_ad9250_hw.tcl index 6cbfe65f2..66ae542d7 100755 --- a/library/axi_ad9250/axi_ad9250_hw.tcl +++ b/library/axi_ad9250/axi_ad9250_hw.tcl @@ -24,6 +24,7 @@ add_fileset_file up_clock_mon.v VERILOG PATH $ad_hdl_dir/library/common/up add_fileset_file up_delay_cntrl.v VERILOG PATH $ad_hdl_dir/library/common/up_delay_cntrl.v add_fileset_file up_adc_common.v VERILOG PATH $ad_hdl_dir/library/common/up_adc_common.v add_fileset_file up_adc_channel.v VERILOG PATH $ad_hdl_dir/library/common/up_adc_channel.v +add_fileset_file ad_xcvr_rx_if.v VERILOG PATH $ad_hdl_dir/library/common/ad_xcvr_rx_if.v add_fileset_file axi_ad9250_pnmon.v VERILOG PATH axi_ad9250_pnmon.v add_fileset_file axi_ad9250_if.v VERILOG PATH axi_ad9250_if.v add_fileset_file axi_ad9250_channel.v VERILOG PATH axi_ad9250_channel.v @@ -40,7 +41,7 @@ set_parameter_property ID UNITS None set_parameter_property ID HDL_PARAMETER true add_parameter DEVICE_TYPE INTEGER 0 -set_parameter_property DEVICE_TYPE DEFAULT_VALUE 0 +set_parameter_property DEVICE_TYPE DEFAULT_VALUE 1 set_parameter_property DEVICE_TYPE DISPLAY_NAME DEVICE_TYPE set_parameter_property DEVICE_TYPE TYPE INTEGER set_parameter_property DEVICE_TYPE UNITS None @@ -81,24 +82,35 @@ add_interface_port s_axi s_axi_rready rready Input 1 # transceiver interface ad_alt_intf clock rx_clk input 1 -ad_alt_intf signal rx_data input 64 data +ad_alt_intf signal rx_sof input 4 export + +add_interface if_rx_data avalon_streaming sink +add_interface_port if_rx_data rx_data data input 64 +add_interface_port if_rx_data rx_valid valid input 1 +add_interface_port if_rx_data rx_ready ready output 1 +set_interface_property if_rx_data associatedClock if_rx_clk +set_interface_property if_rx_data dataBitsPerSymbol 64 # dma interface ad_alt_intf clock adc_clk output 1 ad_alt_intf reset adc_rst output 1 if_adc_clk -add_interface fifo_ch_0_in conduit end -#set_interface_property fifo_ch_0_in associatedClock if_adc_clk -add_interface_port fifo_ch_0_in adc_enable_a enable Output 1 -add_interface_port fifo_ch_0_in adc_valid_a valid Output 1 -add_interface_port fifo_ch_0_in adc_data_a data Output 32 +add_interface adc_ch_0 conduit end +add_interface_port adc_ch_0 adc_enable_a enable Output 1 +add_interface_port adc_ch_0 adc_valid_a valid Output 1 +add_interface_port adc_ch_0 adc_data_a data Output 32 -add_interface fifo_ch_1_in conduit end -#set_interface_property fifo_ch_1_in associatedClock if_adc_clk -add_interface_port fifo_ch_1_in adc_enable_b enable Output 1 -add_interface_port fifo_ch_1_in adc_valid_b valid Output 1 -add_interface_port fifo_ch_1_in adc_data_b data Output 32 +set_interface_property adc_ch_0 associatedClock if_rx_clk +set_interface_property adc_ch_0 associatedReset none + +add_interface adc_ch_1 conduit end +add_interface_port adc_ch_1 adc_enable_b enable Output 1 +add_interface_port adc_ch_1 adc_valid_b valid Output 1 +add_interface_port adc_ch_1 adc_data_b data Output 32 + +set_interface_property adc_ch_1 associatedClock if_rx_clk +set_interface_property adc_ch_1 associatedReset none ad_alt_intf signal adc_dovf input 1 ovf ad_alt_intf signal adc_dunf input 1 unf diff --git a/library/axi_ad9250/axi_ad9250_if.v b/library/axi_ad9250/axi_ad9250_if.v index b3274c275..0b8e603ff 100644 --- a/library/axi_ad9250/axi_ad9250_if.v +++ b/library/axi_ad9250/axi_ad9250_if.v @@ -34,9 +34,6 @@ // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // *************************************************************************** // *************************************************************************** -// *************************************************************************** -// *************************************************************************** -// This is the LVDS/DDR interface `timescale 1ns/100ps @@ -46,6 +43,7 @@ module axi_ad9250_if ( // rx_clk is (line-rate/40) rx_clk, + rx_sof, rx_data, // adc data output @@ -58,10 +56,15 @@ module axi_ad9250_if ( adc_or_b, adc_status); + // parameters + + parameter DEVICE_TYPE = 0; + // jesd interface // rx_clk is (line-rate/40) input rx_clk; + input [ 3:0] rx_sof; input [63:0] rx_data; // adc data output @@ -84,6 +87,7 @@ module axi_ad9250_if ( wire [15:0] adc_data_a_s0_s; wire [15:0] adc_data_b_s1_s; wire [15:0] adc_data_b_s0_s; + wire [63:0] rx_data_s; // adc clock is the reference clock @@ -98,10 +102,10 @@ module axi_ad9250_if ( // data multiplex - assign adc_data_a_s1_s = {rx_data[25:24], rx_data[23:16], rx_data[31:26]}; - assign adc_data_a_s0_s = {rx_data[ 9: 8], rx_data[ 7: 0], rx_data[15:10]}; - assign adc_data_b_s1_s = {rx_data[57:56], rx_data[55:48], rx_data[63:58]}; - assign adc_data_b_s0_s = {rx_data[41:40], rx_data[39:32], rx_data[47:42]}; + assign adc_data_a_s1_s = {rx_data_s[25:24], rx_data_s[23:16], rx_data_s[31:26]}; + assign adc_data_a_s0_s = {rx_data_s[ 9: 8], rx_data_s[ 7: 0], rx_data_s[15:10]}; + assign adc_data_b_s1_s = {rx_data_s[57:56], rx_data_s[55:48], rx_data_s[63:58]}; + assign adc_data_b_s0_s = {rx_data_s[41:40], rx_data_s[39:32], rx_data_s[47:42]}; // status @@ -113,6 +117,21 @@ module axi_ad9250_if ( end end + // frame-alignment + + genvar n; + + generate + for (n = 0; n < 2; n = n + 1) begin: g_xcvr_if + ad_xcvr_rx_if #(.DEVICE_TYPE (DEVICE_TYPE)) i_xcvr_if ( + .rx_clk (rx_clk), + .rx_ip_sof (rx_sof), + .rx_ip_data (rx_data[((n*32)+31):(n*32)]), + .rx_sof (), + .rx_data (rx_data_s[((n*32)+31):(n*32)])); + end + endgenerate + endmodule // *************************************************************************** diff --git a/library/axi_ad9250/axi_ad9250_ip.tcl b/library/axi_ad9250/axi_ad9250_ip.tcl index 390d75954..46055f829 100644 --- a/library/axi_ad9250/axi_ad9250_ip.tcl +++ b/library/axi_ad9250/axi_ad9250_ip.tcl @@ -14,6 +14,7 @@ adi_ip_files axi_ad9250 [list \ "$ad_hdl_dir/library/common/up_clock_mon.v" \ "$ad_hdl_dir/library/common/up_adc_common.v" \ "$ad_hdl_dir/library/common/up_adc_channel.v" \ + "$ad_hdl_dir/library/common/ad_xcvr_rx_if.v" \ "$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc" \ "axi_ad9250_pnmon.v" \ "axi_ad9250_channel.v" \ @@ -27,6 +28,7 @@ adi_ip_constraints axi_ad9250 [list \ "$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc" \ "axi_ad9250_constr.xdc" ] +set_property driver_value 0 [ipx::get_ports *rx_valid* -of_objects [ipx::current_core]] set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]] set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]] diff --git a/library/axi_ad9265/Makefile b/library/axi_ad9265/Makefile index ae440127f..d7beb31c9 100644 --- a/library/axi_ad9265/Makefile +++ b/library/axi_ad9265/Makefile @@ -5,28 +5,28 @@ #################################################################################### #################################################################################### -M_DEPS := axi_ad9265_ip.tcl -M_DEPS += ../scripts/adi_env.tcl -M_DEPS += ../scripts/adi_ip.tcl -M_DEPS += ../common/ad_rst.v -M_DEPS += ../common/ad_lvds_clk.v -M_DEPS += ../common/ad_lvds_in.v +M_DEPS += ../common/ad_axi_ip_constr.xdc M_DEPS += ../common/ad_datafmt.v M_DEPS += ../common/ad_dcfilter.v M_DEPS += ../common/ad_pnmon.v -M_DEPS += ../common/up_xfer_status.v -M_DEPS += ../common/up_xfer_cntrl.v +M_DEPS += ../common/ad_rst.v +M_DEPS += ../common/up_adc_channel.v +M_DEPS += ../common/up_adc_common.v +M_DEPS += ../common/up_axi.v M_DEPS += ../common/up_clock_mon.v M_DEPS += ../common/up_delay_cntrl.v -M_DEPS += ../common/up_adc_common.v -M_DEPS += ../common/up_adc_channel.v -M_DEPS += ../common/up_axi.v -M_DEPS += ../common/ad_axi_ip_constr.xdc -M_DEPS += axi_ad9265_pnmon.v -M_DEPS += axi_ad9265_if.v +M_DEPS += ../common/up_xfer_cntrl.v +M_DEPS += ../common/up_xfer_status.v +M_DEPS += ../scripts/adi_env.tcl +M_DEPS += ../scripts/adi_ip.tcl +M_DEPS += ../xilinx/common/ad_lvds_clk.v +M_DEPS += ../xilinx/common/ad_lvds_in.v +M_DEPS += axi_ad9265.v M_DEPS += axi_ad9265_channel.v M_DEPS += axi_ad9265_constr.xdc -M_DEPS += axi_ad9265.v +M_DEPS += axi_ad9265_if.v +M_DEPS += axi_ad9265_ip.tcl +M_DEPS += axi_ad9265_pnmon.v M_VIVADO := vivado -mode batch -source @@ -37,6 +37,10 @@ M_FLIST += *.log M_FLIST += component.xml M_FLIST += *.jou M_FLIST += xgui +M_FLIST += *.ip_user_files +M_FLIST += *.srcs +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil @@ -53,7 +57,7 @@ clean-all: axi_ad9265.xpr: $(M_DEPS) - rm -rf $(M_FLIST) + -rm -rf $(M_FLIST) $(M_VIVADO) axi_ad9265_ip.tcl >> axi_ad9265_ip.log 2>&1 #################################################################################### diff --git a/library/axi_ad9265/axi_ad9265.v b/library/axi_ad9265/axi_ad9265.v index 0e00ddbaa..0ed145d04 100644 --- a/library/axi_ad9265/axi_ad9265.v +++ b/library/axi_ad9265/axi_ad9265.v @@ -84,7 +84,9 @@ module axi_ad9265 ( s_axi_rvalid, s_axi_rresp, s_axi_rdata, - s_axi_rready); + s_axi_rready, + s_axi_awprot, + s_axi_arprot); // parameters @@ -137,6 +139,9 @@ module axi_ad9265 ( output [ 1:0] s_axi_rresp; output [31:0] s_axi_rdata; input s_axi_rready; + input [ 2:0] s_axi_awprot; + input [ 2:0] s_axi_arprot; + // internal registers @@ -294,7 +299,7 @@ module axi_ad9265 ( .up_drp_wr (), .up_drp_addr (), .up_drp_wdata (), - .up_drp_rdata (16'd0), + .up_drp_rdata (32'd0), .up_drp_ready (1'd0), .up_drp_locked (1'd1), .up_usr_chanmax (), diff --git a/library/axi_ad9265/axi_ad9265_channel.v b/library/axi_ad9265/axi_ad9265_channel.v index 7c4504b0f..cb5e76bca 100644 --- a/library/axi_ad9265/axi_ad9265_channel.v +++ b/library/axi_ad9265/axi_ad9265_channel.v @@ -159,7 +159,7 @@ module axi_ad9265_channel ( end endgenerate - up_adc_channel #(.ADC_CHANNEL_ID(CHANNEL_ID)) i_up_adc_channel ( + up_adc_channel #(.CHANNEL_ID(CHANNEL_ID)) i_up_adc_channel ( .adc_clk (adc_clk), .adc_rst (adc_rst), .adc_enable (adc_enable), diff --git a/library/axi_ad9265/axi_ad9265_if.v b/library/axi_ad9265/axi_ad9265_if.v index ad6d41025..4225fa9f8 100644 --- a/library/axi_ad9265/axi_ad9265_if.v +++ b/library/axi_ad9265/axi_ad9265_if.v @@ -175,6 +175,8 @@ module axi_ad9265_if ( ad_lvds_clk #( .DEVICE_TYPE (DEVICE_TYPE)) i_adc_clk ( + .rst (1'b0), + .locked (), .clk_in_p (adc_clk_in_p), .clk_in_n (adc_clk_in_n), .clk (adc_clk)); diff --git a/library/axi_ad9265/axi_ad9265_ip.tcl b/library/axi_ad9265/axi_ad9265_ip.tcl index b35aeebbd..2310f642a 100644 --- a/library/axi_ad9265/axi_ad9265_ip.tcl +++ b/library/axi_ad9265/axi_ad9265_ip.tcl @@ -6,8 +6,8 @@ source $ad_hdl_dir/library/scripts/adi_ip.tcl adi_ip_create axi_ad9265 adi_ip_files axi_ad9265 [list \ "$ad_hdl_dir/library/common/ad_rst.v" \ - "$ad_hdl_dir/library/common/ad_lvds_clk.v" \ - "$ad_hdl_dir/library/common/ad_lvds_in.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_lvds_clk.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_lvds_in.v" \ "$ad_hdl_dir/library/common/ad_datafmt.v" \ "$ad_hdl_dir/library/common/ad_dcfilter.v" \ "$ad_hdl_dir/library/common/ad_pnmon.v" \ diff --git a/library/axi_ad9361/Makefile b/library/axi_ad9361/Makefile index 702aba3f2..edf2c8ba0 100644 --- a/library/axi_ad9361/Makefile +++ b/library/axi_ad9361/Makefile @@ -5,44 +5,48 @@ #################################################################################### #################################################################################### -M_DEPS := axi_ad9361_ip.tcl -M_DEPS += ../scripts/adi_env.tcl -M_DEPS += ../scripts/adi_ip.tcl +M_DEPS += ../common/ad_addsub.v M_DEPS += ../common/ad_axi_ip_constr.xdc -M_DEPS += ../common/ad_rst.v -M_DEPS += ../common/ad_lvds_clk.v -M_DEPS += ../common/ad_lvds_in.v -M_DEPS += ../common/ad_lvds_out.v -M_DEPS += ../common/ad_mul.v -M_DEPS += ../common/ad_pnmon.v -M_DEPS += ../common/ad_dds_sine.v -M_DEPS += ../common/ad_dds_1.v -M_DEPS += ../common/ad_dds.v M_DEPS += ../common/ad_datafmt.v M_DEPS += ../common/ad_dcfilter.v +M_DEPS += ../common/ad_dds.v +M_DEPS += ../common/ad_dds_1.v +M_DEPS += ../common/ad_dds_sine.v M_DEPS += ../common/ad_iqcor.v -M_DEPS += ../common/ad_addsub.v +M_DEPS += ../common/ad_pnmon.v +M_DEPS += ../common/ad_rst.v M_DEPS += ../common/ad_tdd_control.v +M_DEPS += ../common/up_adc_channel.v +M_DEPS += ../common/up_adc_common.v M_DEPS += ../common/up_axi.v +M_DEPS += ../common/up_clock_mon.v +M_DEPS += ../common/up_dac_channel.v +M_DEPS += ../common/up_dac_common.v +M_DEPS += ../common/up_delay_cntrl.v +M_DEPS += ../common/up_tdd_cntrl.v M_DEPS += ../common/up_xfer_cntrl.v M_DEPS += ../common/up_xfer_status.v -M_DEPS += ../common/up_clock_mon.v -M_DEPS += ../common/up_delay_cntrl.v -M_DEPS += ../common/up_adc_common.v -M_DEPS += ../common/up_adc_channel.v -M_DEPS += ../common/up_dac_common.v -M_DEPS += ../common/up_dac_channel.v -M_DEPS += ../common/up_tdd_cntrl.v +M_DEPS += ../scripts/adi_env.tcl +M_DEPS += ../scripts/adi_ip.tcl +M_DEPS += ../xilinx/common/ad_cmos_clk.v +M_DEPS += ../xilinx/common/ad_cmos_in.v +M_DEPS += ../xilinx/common/ad_cmos_out.v +M_DEPS += ../xilinx/common/ad_lvds_clk.v +M_DEPS += ../xilinx/common/ad_lvds_in.v +M_DEPS += ../xilinx/common/ad_lvds_out.v +M_DEPS += ../xilinx/common/ad_mul.v +M_DEPS += axi_ad9361.v M_DEPS += axi_ad9361_constr.xdc -M_DEPS += axi_ad9361_dev_if.v -M_DEPS += axi_ad9361_rx_pnmon.v -M_DEPS += axi_ad9361_rx_channel.v +M_DEPS += axi_ad9361_ip.tcl M_DEPS += axi_ad9361_rx.v -M_DEPS += axi_ad9361_tx_channel.v -M_DEPS += axi_ad9361_tx.v +M_DEPS += axi_ad9361_rx_channel.v +M_DEPS += axi_ad9361_rx_pnmon.v M_DEPS += axi_ad9361_tdd.v M_DEPS += axi_ad9361_tdd_if.v -M_DEPS += axi_ad9361.v +M_DEPS += axi_ad9361_tx.v +M_DEPS += axi_ad9361_tx_channel.v +M_DEPS += xilinx/axi_ad9361_cmos_if.v +M_DEPS += xilinx/axi_ad9361_lvds_if.v M_VIVADO := vivado -mode batch -source @@ -53,6 +57,10 @@ M_FLIST += *.log M_FLIST += component.xml M_FLIST += *.jou M_FLIST += xgui +M_FLIST += *.ip_user_files +M_FLIST += *.srcs +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil @@ -69,7 +77,7 @@ clean-all: axi_ad9361.xpr: $(M_DEPS) - rm -rf $(M_FLIST) + -rm -rf $(M_FLIST) $(M_VIVADO) axi_ad9361_ip.tcl >> axi_ad9361_ip.log 2>&1 #################################################################################### diff --git a/library/axi_ad9361/axi_ad9361_alt_lvds_rx.v b/library/axi_ad9361/altera/axi_ad9361_alt_lvds_rx.v similarity index 100% rename from library/axi_ad9361/axi_ad9361_alt_lvds_rx.v rename to library/axi_ad9361/altera/axi_ad9361_alt_lvds_rx.v diff --git a/library/axi_ad9361/axi_ad9361_alt_lvds_tx.v b/library/axi_ad9361/altera/axi_ad9361_alt_lvds_tx.v similarity index 100% rename from library/axi_ad9361/axi_ad9361_alt_lvds_tx.v rename to library/axi_ad9361/altera/axi_ad9361_alt_lvds_tx.v diff --git a/library/axi_ad9361/altera/axi_ad9361_cmos_if.v b/library/axi_ad9361/altera/axi_ad9361_cmos_if.v new file mode 100644 index 000000000..0ce506d71 --- /dev/null +++ b/library/axi_ad9361/altera/axi_ad9361_cmos_if.v @@ -0,0 +1,583 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_ad9361_cmos_if ( + + // physical interface (receive) + + rx_clk_in, + rx_frame_in, + rx_data_in, + + // physical interface (transmit) + + tx_clk_out, + tx_frame_out, + tx_data_out, + + // ensm control + + enable, + txnrx, + + // clock (common to both receive and transmit) + + rst, + clk, + l_clk, + + // receive data path interface + + adc_valid, + adc_data, + adc_status, + adc_r1_mode, + adc_ddr_edgesel, + + // transmit data path interface + + dac_valid, + dac_data, + dac_clksel, + dac_r1_mode, + + // tdd interface + + tdd_enable, + tdd_txnrx, + tdd_mode, + + // delay interface + + mmcm_rst, + up_clk, + up_enable, + up_txnrx, + up_adc_dld, + up_adc_dwdata, + up_adc_drdata, + up_dac_dld, + up_dac_dwdata, + up_dac_drdata, + delay_clk, + delay_rst, + delay_locked); + + // this parameter controls the buffer type based on the target device. + + parameter DEVICE_TYPE = 0; + parameter DAC_IODELAY_ENABLE = 0; + parameter IO_DELAY_GROUP = "dev_if_delay_group"; + + // physical interface (receive) + + input rx_clk_in; + input rx_frame_in; + input [11:0] rx_data_in; + + // physical interface (transmit) + + output tx_clk_out; + output tx_frame_out; + output [11:0] tx_data_out; + + // ensm control + + output enable; + output txnrx; + + // clock (common to both receive and transmit) + + input rst; + input clk; + output l_clk; + + // receive data path interface + + output adc_valid; + output [47:0] adc_data; + output adc_status; + input adc_r1_mode; + input adc_ddr_edgesel; + + // transmit data path interface + + input dac_valid; + input [47:0] dac_data; + input dac_clksel; + input dac_r1_mode; + + // tdd interface + + input tdd_enable; + input tdd_txnrx; + input tdd_mode; + + // delay interface + + input mmcm_rst; + input up_clk; + input up_enable; + input up_txnrx; + input [12:0] up_adc_dld; + input [64:0] up_adc_dwdata; + output [64:0] up_adc_drdata; + input [15:0] up_dac_dld; + input [79:0] up_dac_dwdata; + output [79:0] up_dac_drdata; + input delay_clk; + input delay_rst; + output delay_locked; + + // internal registers + + reg [ 1:0] rx_frame = 0; + reg [11:0] rx_data_p = 0; + reg rx_error_r1 = 'd0; + reg rx_valid_r1 = 'd0; + reg [23:0] rx_data_r1 = 'd0; + reg rx_error_r2 = 'd0; + reg rx_valid_r2 = 'd0; + reg [47:0] rx_data_r2 = 'd0; + reg adc_p_valid = 'd0; + reg [47:0] adc_p_data = 'd0; + reg adc_p_status = 'd0; + reg adc_n_valid = 'd0; + reg [47:0] adc_n_data = 'd0; + reg adc_n_status = 'd0; + reg adc_valid_int = 'd0; + reg [47:0] adc_data_int = 'd0; + reg adc_status_int = 'd0; + reg adc_valid = 'd0; + reg [47:0] adc_data = 'd0; + reg adc_status = 'd0; + reg [ 1:0] tx_data_cnt = 'd0; + reg [47:0] tx_data = 'd0; + reg tx_frame_p = 'd0; + reg tx_frame_n = 'd0; + reg [11:0] tx_data_p = 'd0; + reg [11:0] tx_data_n = 'd0; + reg tx_n_frame_p = 'd0; + reg tx_n_frame_n = 'd0; + reg [11:0] tx_n_data_p = 'd0; + reg [11:0] tx_n_data_n = 'd0; + reg tx_p_frame_p = 'd0; + reg tx_p_frame_n = 'd0; + reg [11:0] tx_p_data_p = 'd0; + reg [11:0] tx_p_data_n = 'd0; + reg up_enable_int = 'd0; + reg up_txnrx_int = 'd0; + reg enable_up_m1 = 'd0; + reg txnrx_up_m1 = 'd0; + reg enable_up = 'd0; + reg txnrx_up = 'd0; + reg enable_int = 'd0; + reg txnrx_int = 'd0; + reg enable_n_int = 'd0; + reg txnrx_n_int = 'd0; + reg enable_p_int = 'd0; + reg txnrx_p_int = 'd0; + reg dac_clkdata_p = 'd0; + reg dac_clkdata_n = 'd0; + reg locked_m1 = 'd0; + reg locked = 'd0; + + // internal signals + + wire [ 1:0] rx_frame_s; + wire [ 3:0] rx_frame_4_s; + wire [ 2:0] tx_data_sel_s; + wire [11:0] rx_data_p_s; + wire [11:0] rx_data_n_s; + wire rx_frame_p_s; + wire rx_frame_n_s; + wire locked_s; + + genvar l_inst; + + // receive data path interface + + assign rx_frame_s = {rx_frame_p_s, rx_frame_n_s}; + assign rx_frame_4_s = {rx_frame_s, rx_frame}; + + always @(posedge l_clk) begin + rx_frame <= rx_frame_s; + rx_data_p <= rx_data_p_s; + end + + // receive data path for single rf, frame is expected to qualify i only + + always @(posedge l_clk) begin + rx_error_r1 <= ~^ rx_frame_s; + rx_valid_r1 <= ^ rx_frame_s; + case (rx_frame_s) + 2'b01: rx_data_r1 <= {rx_data_p_s, rx_data_n_s}; + 2'b10: rx_data_r1 <= {rx_data_n_s, rx_data_p}; + default: rx_data_r1 <= 24'd0; + endcase + end + + // receive data path for dual rf, frame is expected to qualify iq for rf-1 only + + always @(posedge l_clk) begin + rx_error_r2 <= ((rx_frame_4_s == 4'b0011) || (rx_frame_4_s == 4'b1100) || + (rx_frame_4_s == 4'b1001) || (rx_frame_4_s == 4'b0110)) ? 1'b0 : 1'b1; + rx_valid_r2 <= ((rx_frame_4_s == 4'b0011) || + (rx_frame_4_s == 4'b1001)) ? 1'b1 : 1'b0; + case (rx_frame_s) + 2'b11: rx_data_r2[23: 0] <= {rx_data_p_s, rx_data_n_s}; + 2'b01: rx_data_r2[23: 0] <= {rx_data_n_s, rx_data_p}; + default: rx_data_r2[23: 0] <= rx_data_r2[23: 0]; + endcase + case (rx_frame_s) + 2'b00: rx_data_r2[47:24] <= {rx_data_p_s, rx_data_n_s}; + 2'b10: rx_data_r2[47:24] <= {rx_data_n_s, rx_data_p}; + default: rx_data_r2[47:24] <= rx_data_r2[47:24]; + endcase + end + + // receive data path mux + + always @(posedge l_clk) begin + if (adc_r1_mode == 1'b1) begin + adc_p_valid <= rx_valid_r1; + adc_p_data <= {24'd0, rx_data_r1}; + adc_p_status <= ~rx_error_r1; + end else begin + adc_p_valid <= rx_valid_r2; + adc_p_data <= rx_data_r2; + adc_p_status <= ~rx_error_r2; + end + end + + // transfer to a synchronous common clock + + always @(negedge l_clk) begin + adc_n_valid <= adc_p_valid; + adc_n_data <= adc_p_data; + adc_n_status <= adc_p_status; + end + + always @(posedge clk) begin + adc_valid_int <= adc_n_valid; + adc_data_int <= adc_n_data; + adc_status_int <= adc_n_status; + adc_valid <= adc_valid_int; + if (adc_valid_int == 1'b1) begin + adc_data <= adc_data_int; + end + adc_status <= adc_status_int & locked; + end + + // transmit data path mux (reverse of what receive does above) + // the count simply selets the data muxing on the ddr outputs + + assign tx_data_sel_s = {tx_data_cnt[1], dac_r1_mode, tx_data_cnt[0]}; + + always @(posedge clk) begin + if (dac_valid == 1'b1) begin + tx_data_cnt <= 2'b10; + end else if (tx_data_cnt[1] == 1'b1) begin + tx_data_cnt <= tx_data_cnt + 1'b1; + end + if (dac_valid == 1'b1) begin + tx_data <= dac_data; + end + case (tx_data_sel_s) + 3'b101: begin + tx_frame_p <= 1'b0; + tx_frame_n <= 1'b0; + tx_data_p <= tx_data[35:24]; + tx_data_n <= tx_data[47:36]; + end + 3'b100: begin + tx_frame_p <= 1'b1; + tx_frame_n <= 1'b1; + tx_data_p <= tx_data[11: 0]; + tx_data_n <= tx_data[23:12]; + end + 3'b110: begin + tx_frame_p <= 1'b1; + tx_frame_n <= 1'b0; + tx_data_p <= tx_data[11: 0]; + tx_data_n <= tx_data[23:12]; + end + default: begin + tx_frame_p <= 1'd0; + tx_frame_n <= 1'd0; + tx_data_p <= 12'd0; + tx_data_n <= 12'd0; + end + endcase + end + + // transfer data from a synchronous clock (skew less than 2ns) + + always @(negedge clk) begin + tx_n_frame_p <= tx_frame_p; + tx_n_frame_n <= tx_frame_n; + tx_n_data_p <= tx_data_p; + tx_n_data_n <= tx_data_n; + end + + always @(posedge l_clk) begin + tx_p_frame_p <= tx_n_frame_p; + tx_p_frame_n <= tx_n_frame_n; + tx_p_data_p <= tx_n_data_p; + tx_p_data_n <= tx_n_data_n; + end + + // tdd/ensm control + + always @(posedge up_clk) begin + up_enable_int <= up_enable; + up_txnrx_int <= up_txnrx; + end + + always @(posedge clk or posedge rst) begin + if (rst == 1'b1) begin + enable_up_m1 <= 1'b0; + txnrx_up_m1 <= 1'b0; + enable_up <= 1'b0; + txnrx_up <= 1'b0; + end else begin + enable_up_m1 <= up_enable_int; + txnrx_up_m1 <= up_txnrx_int; + enable_up <= enable_up_m1; + txnrx_up <= txnrx_up_m1; + end + end + + always @(posedge clk) begin + if (tdd_mode == 1'b1) begin + enable_int <= tdd_enable; + txnrx_int <= tdd_txnrx; + end else begin + enable_int <= enable_up; + txnrx_int <= txnrx_up; + end + end + + always @(negedge clk) begin + enable_n_int <= enable_int; + txnrx_n_int <= txnrx_int; + end + + always @(posedge l_clk) begin + enable_p_int <= enable_n_int; + txnrx_p_int <= txnrx_n_int; + end + + always @(posedge l_clk) begin + dac_clkdata_p <= dac_clksel; + dac_clkdata_n <= ~dac_clksel; + end + + // receive data interface, ibuf -> idelay -> iddr + + generate + for (l_inst = 0; l_inst <= 11; l_inst = l_inst + 1) begin: g_rx_data + ad_cmos_in #( + .SINGLE_ENDED (1), + .DEVICE_TYPE (DEVICE_TYPE), + .IODELAY_CTRL (0), + .IODELAY_GROUP (IO_DELAY_GROUP)) + i_rx_data ( + .rx_clk (l_clk), + .rx_data_in (rx_data_in[l_inst]), + .rx_data_p (rx_data_p_s[l_inst]), + .rx_data_n (rx_data_n_s[l_inst]), + .up_clk (up_clk), + .up_dld (up_adc_dld[l_inst]), + .up_dwdata (up_adc_dwdata[((l_inst*5)+4):(l_inst*5)]), + .up_drdata (up_adc_drdata[((l_inst*5)+4):(l_inst*5)]), + .delay_clk (delay_clk), + .delay_rst (delay_rst), + .delay_locked ()); + end + endgenerate + + // receive frame interface, ibuf -> idelay -> iddr + + ad_cmos_in #( + .SINGLE_ENDED (1), + .DEVICE_TYPE (DEVICE_TYPE), + .IODELAY_CTRL (1), + .IODELAY_GROUP (IO_DELAY_GROUP)) + i_rx_frame ( + .rx_clk (l_clk), + .rx_data_in (rx_frame_in), + .rx_data_p (rx_frame_p_s), + .rx_data_n (rx_frame_n_s), + .up_clk (up_clk), + .up_dld (up_adc_dld[12]), + .up_dwdata (up_adc_dwdata[64:60]), + .up_drdata (up_adc_drdata[64:60]), + .delay_clk (delay_clk), + .delay_rst (delay_rst), + .delay_locked (delay_locked)); + + // transmit data interface, oddr -> obuf + + generate + for (l_inst = 0; l_inst <= 11; l_inst = l_inst + 1) begin: g_tx_data + ad_cmos_out #( + .DEVICE_TYPE (DEVICE_TYPE), + .SINGLE_ENDED (1), + .IODELAY_ENABLE (DAC_IODELAY_ENABLE), + .IODELAY_CTRL (0), + .IODELAY_GROUP (IO_DELAY_GROUP)) + i_tx_data ( + .tx_clk (l_clk), + .tx_data_p (tx_p_data_p[l_inst]), + .tx_data_n (tx_p_data_n[l_inst]), + .tx_data_out (tx_data_out[l_inst]), + .up_clk (up_clk), + .up_dld (up_dac_dld[l_inst]), + .up_dwdata (up_dac_dwdata[((l_inst*5)+4):(l_inst*5)]), + .up_drdata (up_dac_drdata[((l_inst*5)+4):(l_inst*5)]), + .delay_clk (delay_clk), + .delay_rst (delay_rst), + .delay_locked ()); + end + endgenerate + + // transmit frame interface, oddr -> obuf + + ad_cmos_out #( + .DEVICE_TYPE (DEVICE_TYPE), + .SINGLE_ENDED (1), + .IODELAY_ENABLE (DAC_IODELAY_ENABLE), + .IODELAY_CTRL (0), + .IODELAY_GROUP (IO_DELAY_GROUP)) + i_tx_frame ( + .tx_clk (l_clk), + .tx_data_p (tx_p_frame_p), + .tx_data_n (tx_p_frame_n), + .tx_data_out (tx_frame_out), + .up_clk (up_clk), + .up_dld (up_dac_dld[12]), + .up_dwdata (up_dac_dwdata[64:60]), + .up_drdata (up_dac_drdata[64:60]), + .delay_clk (delay_clk), + .delay_rst (delay_rst), + .delay_locked ()); + + // transmit clock interface, oddr -> obuf + + ad_cmos_out #( + .DEVICE_TYPE (DEVICE_TYPE), + .SINGLE_ENDED (1), + .IODELAY_ENABLE (DAC_IODELAY_ENABLE), + .IODELAY_CTRL (0), + .IODELAY_GROUP (IO_DELAY_GROUP)) + i_tx_clk ( + .tx_clk (l_clk), + .tx_data_p (dac_clkdata_p), + .tx_data_n (dac_clkdata_n), + .tx_data_out (tx_clk_out), + .up_clk (up_clk), + .up_dld (up_dac_dld[13]), + .up_dwdata (up_dac_dwdata[69:65]), + .up_drdata (up_dac_drdata[69:65]), + .delay_clk (delay_clk), + .delay_rst (delay_rst), + .delay_locked ()); + + // enable, oddr -> obuf + + ad_cmos_out #( + .DEVICE_TYPE (DEVICE_TYPE), + .SINGLE_ENDED (1), + .IODELAY_ENABLE (DAC_IODELAY_ENABLE), + .IODELAY_CTRL (0), + .IODELAY_GROUP (IO_DELAY_GROUP)) + i_enable ( + .tx_clk (l_clk), + .tx_data_p (enable_p_int), + .tx_data_n (enable_p_int), + .tx_data_out (enable), + .up_clk (up_clk), + .up_dld (up_dac_dld[14]), + .up_dwdata (up_dac_dwdata[74:70]), + .up_drdata (up_dac_drdata[74:70]), + .delay_clk (delay_clk), + .delay_rst (delay_rst), + .delay_locked ()); + + // txnrx, oddr -> obuf + + ad_cmos_out #( + .DEVICE_TYPE (DEVICE_TYPE), + .SINGLE_ENDED (1), + .IODELAY_ENABLE (DAC_IODELAY_ENABLE), + .IODELAY_CTRL (0), + .IODELAY_GROUP (IO_DELAY_GROUP)) + i_txnrx ( + .tx_clk (l_clk), + .tx_data_p (txnrx_p_int), + .tx_data_n (txnrx_p_int), + .tx_data_out (txnrx), + .up_clk (up_clk), + .up_dld (up_dac_dld[15]), + .up_dwdata (up_dac_dwdata[79:75]), + .up_drdata (up_dac_drdata[79:75]), + .delay_clk (delay_clk), + .delay_rst (delay_rst), + .delay_locked ()); + + // device clock interface (receive clock) + + always @(posedge clk) begin + locked_m1 <= locked_s; + locked <= locked_m1; + end + + ad_cmos_clk #( + .DEVICE_TYPE (DEVICE_TYPE)) + i_clk ( + .rst (mmcm_rst), + .locked (locked_s), + .clk_in (rx_clk_in), + .clk (l_clk)); + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/library/axi_ad9361/axi_ad9361_dev_if_alt.v b/library/axi_ad9361/altera/axi_ad9361_lvds_if.v similarity index 54% rename from library/axi_ad9361/axi_ad9361_dev_if_alt.v rename to library/axi_ad9361/altera/axi_ad9361_lvds_if.v index fd91e4dd1..67461e8db 100644 --- a/library/axi_ad9361/axi_ad9361_dev_if_alt.v +++ b/library/axi_ad9361/altera/axi_ad9361_lvds_if.v @@ -1,179 +1,122 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2011(c) Analog Devices, Inc. -// -// All rights reserved. -// -// Redistribution and use in source and binary forms, with or without modification, -// are permitted provided that the following conditions are met: -// - Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// - Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in -// the documentation and/or other materials provided with the -// distribution. -// - Neither the name of Analog Devices, Inc. nor the names of its -// contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// - The use of this software may or may not infringe the patent rights -// of one or more patent holders. This license does not release you -// from the requirement that you obtain separate licenses from these -// patent holders to use this software. -// - Use of the software either in source or binary form, must be run -// on or directly connected to an Analog Devices Inc. component. -// -// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, -// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A -// PARTICULAR PURPOSE ARE DISCLAIMED. +// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsabilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. // -// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY -// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF -// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // *************************************************************************** // *************************************************************************** -// This interface includes both the transmit and receive components - -// They both uses the same clock (sourced from the receiving side). `timescale 1ns/100ps -module axi_ad9361_dev_if ( +module axi_ad9361_lvds_if #( + + parameter DEVICE_TYPE = 0, + parameter DAC_IODELAY_ENABLE = 0, + parameter IO_DELAY_GROUP = "dev_if_delay_group") ( // physical interface (receive) - rx_clk_in_p, - rx_clk_in_n, - rx_frame_in_p, - rx_frame_in_n, - rx_data_in_p, - rx_data_in_n, + input rx_clk_in_p, + input rx_clk_in_n, + input rx_frame_in_p, + input rx_frame_in_n, + input [ 5:0] rx_data_in_p, + input [ 5:0] rx_data_in_n, // physical interface (transmit) - tx_clk_out_p, - tx_clk_out_n, - tx_frame_out_p, - tx_frame_out_n, - tx_data_out_p, - tx_data_out_n, + output tx_clk_out_p, + output tx_clk_out_n, + output tx_frame_out_p, + output tx_frame_out_n, + output [ 5:0] tx_data_out_p, + output [ 5:0] tx_data_out_n, // ensm control - enable, - txnrx, + output enable, + output txnrx, // clock (common to both receive and transmit) - rst, - clk, - l_clk, + input rst, + input clk, + output l_clk, // receive data path interface - adc_valid, - adc_data, - adc_status, - adc_r1_mode, - adc_ddr_edgesel, + output reg adc_valid, + output reg [47:0] adc_data, + output reg adc_status, + input adc_r1_mode, + input adc_ddr_edgesel, // transmit data path interface - dac_valid, - dac_data, - dac_r1_mode, + input dac_valid, + input [47:0] dac_data, + input dac_clksel, + input dac_r1_mode, // tdd interface - tdd_enable, - tdd_txnrx, - tdd_mode, + input tdd_enable, + input tdd_txnrx, + input tdd_mode, // delay interface - up_clk, - up_enable, - up_txnrx, - up_adc_dld, - up_adc_dwdata, - up_adc_drdata, - up_dac_dld, - up_dac_dwdata, - up_dac_drdata, - delay_clk, - delay_rst, - delay_locked); + input mmcm_rst, + input up_clk, + input up_rstn, + input up_enable, + input up_txnrx, + input [ 6:0] up_adc_dld, + input [34:0] up_adc_dwdata, + output [34:0] up_adc_drdata, + input [ 9:0] up_dac_dld, + input [49:0] up_dac_dwdata, + output [49:0] up_dac_drdata, + input delay_clk, + input delay_rst, + output delay_locked, - // this parameter controls the buffer type based on the target device. + // drp interface - parameter DEVICE_TYPE = 0; - parameter DAC_IODELAY_ENABLE = 0; - parameter IO_DELAY_GROUP = "dev_if_delay_group"; - - // physical interface (receive) - - input rx_clk_in_p; - input rx_clk_in_n; - input rx_frame_in_p; - input rx_frame_in_n; - input [ 5:0] rx_data_in_p; - input [ 5:0] rx_data_in_n; - - // physical interface (transmit) - - output tx_clk_out_p; - output tx_clk_out_n; - output tx_frame_out_p; - output tx_frame_out_n; - output [ 5:0] tx_data_out_p; - output [ 5:0] tx_data_out_n; - - // ensm control - - output enable; - output txnrx; - - // clock (common to both receive and transmit) - - input rst; - input clk; - output l_clk; - - // receive data path interface - - output adc_valid; - output [47:0] adc_data; - output adc_status; - input adc_r1_mode; - input adc_ddr_edgesel; - - // transmit data path interface - - input dac_valid; - input [47:0] dac_data; - input dac_r1_mode; - - // tdd interface - - input tdd_enable; - input tdd_txnrx; - input tdd_mode; - - // delay interface - - input up_clk; - input up_enable; - input up_txnrx; - input [ 6:0] up_adc_dld; - input [34:0] up_adc_dwdata; - output [34:0] up_adc_drdata; - input [ 9:0] up_dac_dld; - input [49:0] up_dac_dwdata; - output [49:0] up_dac_drdata; - input delay_clk; - input delay_rst; - output delay_locked; + input up_drp_sel, + input up_drp_wr, + input [11:0] up_drp_addr, + input [31:0] up_drp_wdata, + output [31:0] up_drp_rdata, + output up_drp_ready, + output up_drp_locked); // internal registers @@ -185,9 +128,6 @@ module axi_ad9361_dev_if ( reg rx_error_r2 = 'd0; reg rx_valid_r2 = 'd0; reg [23:0] rx_data_r2 = 'd0; - reg adc_valid = 'd0; - reg [47:0] adc_data = 'd0; - reg adc_status = 'd0; reg tx_data_sel = 'd0; reg [47:0] tx_data = 'd0; reg [ 3:0] tx_frame = 'd0; diff --git a/library/axi_ad9361/axi_ad9361.v b/library/axi_ad9361/axi_ad9361.v index 4351f22b7..7324d28d6 100644 --- a/library/axi_ad9361/axi_ad9361.v +++ b/library/axi_ad9361/axi_ad9361.v @@ -37,249 +37,174 @@ `timescale 1ns/100ps -module axi_ad9361 ( - - // physical interface (receive) - - rx_clk_in_p, - rx_clk_in_n, - rx_frame_in_p, - rx_frame_in_n, - rx_data_in_p, - rx_data_in_n, - - // physical interface (transmit) - - tx_clk_out_p, - tx_clk_out_n, - tx_frame_out_p, - tx_frame_out_n, - tx_data_out_p, - tx_data_out_n, - - // ensm control - - enable, - txnrx, - - // transmit master/slave - - dac_sync_in, - dac_sync_out, - - // tdd sync (1s pulse) - - tdd_sync, - tdd_sync_en, - tdd_terminal_type, - - // delay clock - - delay_clk, - - // master interface - - l_clk, - clk, - rst, - - // dma interface - - adc_enable_i0, - adc_valid_i0, - adc_data_i0, - adc_enable_q0, - adc_valid_q0, - adc_data_q0, - adc_enable_i1, - adc_valid_i1, - adc_data_i1, - adc_enable_q1, - adc_valid_q1, - adc_data_q1, - adc_dovf, - adc_dunf, - adc_r1_mode, - - dac_enable_i0, - dac_valid_i0, - dac_data_i0, - dac_enable_q0, - dac_valid_q0, - dac_data_q0, - dac_enable_i1, - dac_valid_i1, - dac_data_i1, - dac_enable_q1, - dac_valid_q1, - dac_data_q1, - dac_dovf, - dac_dunf, - dac_r1_mode, - - // axi interface - - s_axi_aclk, - s_axi_aresetn, - s_axi_awvalid, - s_axi_awaddr, - s_axi_awprot, - s_axi_awready, - s_axi_wvalid, - s_axi_wdata, - s_axi_wstrb, - s_axi_wready, - s_axi_bvalid, - s_axi_bresp, - s_axi_bready, - s_axi_arvalid, - s_axi_araddr, - s_axi_arprot, - s_axi_arready, - s_axi_rvalid, - s_axi_rdata, - s_axi_rresp, - s_axi_rready, - - // gpio - - up_enable, - up_txnrx, - up_dac_gpio_in, - up_dac_gpio_out, - up_adc_gpio_in, - up_adc_gpio_out, - - // chipscope signals - - tdd_dbg); +module axi_ad9361 #( // parameters - parameter ID = 0; - parameter DEVICE_TYPE = 0; - parameter DAC_IODELAY_ENABLE = 0; - parameter IO_DELAY_GROUP = "dev_if_delay_group"; - parameter DAC_DATAPATH_DISABLE = 0; - parameter ADC_DATAPATH_DISABLE = 0; + parameter ID = 0, + parameter MODE_1R1T = 0, + parameter DEVICE_TYPE = 0, + parameter TDD_DISABLE = 0, + parameter CMOS_OR_LVDS_N = 0, + parameter ADC_DATAPATH_DISABLE = 0, + parameter ADC_USERPORTS_DISABLE = 0, + parameter ADC_DATAFORMAT_DISABLE = 0, + parameter ADC_DCFILTER_DISABLE = 0, + parameter ADC_IQCORRECTION_DISABLE = 0, + parameter DAC_IODELAY_ENABLE = 0, + parameter DAC_DATAPATH_DISABLE = 0, + parameter DAC_DDS_DISABLE = 0, + parameter DAC_USERPORTS_DISABLE = 0, + parameter DAC_IQCORRECTION_DISABLE = 0, + parameter IO_DELAY_GROUP = "dev_if_delay_group") ( - // physical interface (receive) + // physical interface (receive-lvds) - input rx_clk_in_p; - input rx_clk_in_n; - input rx_frame_in_p; - input rx_frame_in_n; - input [ 5:0] rx_data_in_p; - input [ 5:0] rx_data_in_n; + input rx_clk_in_p, + input rx_clk_in_n, + input rx_frame_in_p, + input rx_frame_in_n, + input [ 5:0] rx_data_in_p, + input [ 5:0] rx_data_in_n, - // physical interface (transmit) + // physical interface (receive-cmos) - output tx_clk_out_p; - output tx_clk_out_n; - output tx_frame_out_p; - output tx_frame_out_n; - output [ 5:0] tx_data_out_p; - output [ 5:0] tx_data_out_n; + input rx_clk_in, + input rx_frame_in, + input [11:0] rx_data_in, + + // physical interface (transmit-lvds) + + output tx_clk_out_p, + output tx_clk_out_n, + output tx_frame_out_p, + output tx_frame_out_n, + output [ 5:0] tx_data_out_p, + output [ 5:0] tx_data_out_n, + + // physical interface (transmit-cmos) + + output tx_clk_out, + output tx_frame_out, + output [11:0] tx_data_out, // ensm control - output enable; - output txnrx; + output enable, + output txnrx, // transmit master/slave - input dac_sync_in; - output dac_sync_out; + input dac_sync_in, + output dac_sync_out, // tdd sync - input tdd_sync; - output tdd_sync_en; - output tdd_terminal_type; + input tdd_sync, + output tdd_sync_cntr, // delay clock - input delay_clk; + input delay_clk, // master interface - output l_clk; - input clk; - output rst; + output l_clk, + input clk, + output rst, // dma interface - output adc_enable_i0; - output adc_valid_i0; - output [15:0] adc_data_i0; - output adc_enable_q0; - output adc_valid_q0; - output [15:0] adc_data_q0; - output adc_enable_i1; - output adc_valid_i1; - output [15:0] adc_data_i1; - output adc_enable_q1; - output adc_valid_q1; - output [15:0] adc_data_q1; - input adc_dovf; - input adc_dunf; - output adc_r1_mode; + output adc_enable_i0, + output adc_valid_i0, + output [15:0] adc_data_i0, + output adc_enable_q0, + output adc_valid_q0, + output [15:0] adc_data_q0, + output adc_enable_i1, + output adc_valid_i1, + output [15:0] adc_data_i1, + output adc_enable_q1, + output adc_valid_q1, + output [15:0] adc_data_q1, + input adc_dovf, + input adc_dunf, + output adc_r1_mode, - output dac_enable_i0; - output dac_valid_i0; - input [15:0] dac_data_i0; - output dac_enable_q0; - output dac_valid_q0; - input [15:0] dac_data_q0; - output dac_enable_i1; - output dac_valid_i1; - input [15:0] dac_data_i1; - output dac_enable_q1; - output dac_valid_q1; - input [15:0] dac_data_q1; - input dac_dovf; - input dac_dunf; - output dac_r1_mode; + output dac_enable_i0, + output dac_valid_i0, + input [15:0] dac_data_i0, + output dac_enable_q0, + output dac_valid_q0, + input [15:0] dac_data_q0, + output dac_enable_i1, + output dac_valid_i1, + input [15:0] dac_data_i1, + output dac_enable_q1, + output dac_valid_q1, + input [15:0] dac_data_q1, + input dac_dovf, + input dac_dunf, + output dac_r1_mode, // axi interface - input s_axi_aclk; - input s_axi_aresetn; - input s_axi_awvalid; - input [31:0] s_axi_awaddr; - input [ 2:0] s_axi_awprot; - output s_axi_awready; - input s_axi_wvalid; - input [31:0] s_axi_wdata; - input [ 3:0] s_axi_wstrb; - output s_axi_wready; - output s_axi_bvalid; - output [ 1:0] s_axi_bresp; - input s_axi_bready; - input s_axi_arvalid; - input [31:0] s_axi_araddr; - input [ 2:0] s_axi_arprot; - output s_axi_arready; - output s_axi_rvalid; - output [31:0] s_axi_rdata; - output [ 1:0] s_axi_rresp; - input s_axi_rready; + input s_axi_aclk, + input s_axi_aresetn, + input s_axi_awvalid, + input [31:0] s_axi_awaddr, + input [ 2:0] s_axi_awprot, + output s_axi_awready, + input s_axi_wvalid, + input [31:0] s_axi_wdata, + input [ 3:0] s_axi_wstrb, + output s_axi_wready, + output s_axi_bvalid, + output [ 1:0] s_axi_bresp, + input s_axi_bready, + input s_axi_arvalid, + input [31:0] s_axi_araddr, + input [ 2:0] s_axi_arprot, + output s_axi_arready, + output s_axi_rvalid, + output [31:0] s_axi_rdata, + output [ 1:0] s_axi_rresp, + input s_axi_rready, // gpio - input up_enable; - input up_txnrx; - input [31:0] up_dac_gpio_in; - output [31:0] up_dac_gpio_out; - input [31:0] up_adc_gpio_in; - output [31:0] up_adc_gpio_out; + input up_enable, + input up_txnrx, + input [31:0] up_dac_gpio_in, + output [31:0] up_dac_gpio_out, + input [31:0] up_adc_gpio_in, + output [31:0] up_adc_gpio_out); - // chipscope signals + // derived parameters - output [41:0] tdd_dbg; + localparam ADC_USERPORTS_DISABLE_INT = (ADC_DATAPATH_DISABLE == 1) ? 1 : ADC_USERPORTS_DISABLE; + localparam ADC_DATAFORMAT_DISABLE_INT = (ADC_DATAPATH_DISABLE == 1) ? 1 : ADC_DATAFORMAT_DISABLE; + localparam ADC_DCFILTER_DISABLE_INT = (ADC_DATAPATH_DISABLE == 1) ? 1 : ADC_DCFILTER_DISABLE; + localparam ADC_IQCORRECTION_DISABLE_INT = (ADC_DATAPATH_DISABLE == 1) ? 1 : ADC_IQCORRECTION_DISABLE; + localparam DAC_DDS_DISABLE_INT = (DAC_DATAPATH_DISABLE == 1) ? 1 : DAC_DDS_DISABLE; + localparam DAC_USERPORTS_DISABLE_INT = (DAC_DATAPATH_DISABLE == 1) ? 1 : DAC_USERPORTS_DISABLE; + localparam DAC_DELAYCNTRL_DISABLE_INT = (DAC_IODELAY_ENABLE == 1) ? 0 : 1; + localparam DAC_IQCORRECTION_DISABLE_INT = (DAC_DATAPATH_DISABLE == 1) ? 1 : DAC_IQCORRECTION_DISABLE; // internal registers + reg adc_valid_i0_int = 'd0; + reg adc_valid_q0_int = 'd0; + reg adc_valid_i1_int = 'd0; + reg adc_valid_q1_int = 'd0; + reg [15:0] adc_data_i0_int = 'd0; + reg [15:0] adc_data_q0_int = 'd0; + reg [15:0] adc_data_i1_int = 'd0; + reg [15:0] adc_data_q1_int = 'd0; + reg dac_valid_i0_int = 'd0; + reg dac_valid_q0_int = 'd0; + reg dac_valid_i1_int = 'd0; + reg dac_valid_q1_int = 'd0; reg up_wack = 'd0; reg up_rack = 'd0; reg [31:0] up_rdata = 'd0; @@ -288,26 +213,40 @@ module axi_ad9361 ( wire up_clk; wire up_rstn; + wire mmcm_rst; wire delay_rst; // internal signals - wire adc_ddr_edgesel; + wire adc_ddr_edgesel_s; wire adc_valid_s; + wire adc_valid_i0_s; + wire adc_valid_q0_s; + wire adc_valid_i1_s; + wire adc_valid_q1_s; + wire [15:0] adc_data_i0_s; + wire [15:0] adc_data_q0_s; + wire [15:0] adc_data_i1_s; + wire [15:0] adc_data_q1_s; wire [47:0] adc_data_s; wire adc_status_s; + wire dac_clksel_s; wire dac_valid_s; wire [47:0] dac_data_s; wire dac_valid_i0_s; wire dac_valid_q0_s; wire dac_valid_i1_s; wire dac_valid_q1_s; - wire [ 6:0] up_adc_dld_s; - wire [34:0] up_adc_dwdata_s; - wire [34:0] up_adc_drdata_s; - wire [ 9:0] up_dac_dld_s; - wire [49:0] up_dac_dwdata_s; - wire [49:0] up_dac_drdata_s; + wire dac_data_i0_s; + wire dac_data_q0_s; + wire dac_data_i1_s; + wire dac_data_q1_s; + wire [12:0] up_adc_dld_s; + wire [64:0] up_adc_dwdata_s; + wire [64:0] up_adc_drdata_s; + wire [15:0] up_dac_dld_s; + wire [79:0] up_dac_dwdata_s; + wire [79:0] up_dac_drdata_s; wire delay_locked_s; wire up_wreq_s; wire [13:0] up_waddr_s; @@ -323,16 +262,23 @@ module axi_ad9361 ( wire up_wack_tdd_s; wire up_rack_tdd_s; wire [31:0] up_rdata_tdd_s; - wire tdd_tx_dp_en_s; + wire tdd_enable_s; + wire tdd_txnrx_s; + wire tdd_mode_s; + wire tdd_tx_valid_s; + wire tdd_rx_valid_s; wire tdd_rx_vco_en_s; wire tdd_tx_vco_en_s; wire tdd_rx_rf_en_s; wire tdd_tx_rf_en_s; wire [ 7:0] tdd_status_s; - wire tdd_enable_s; - wire tdd_txnrx_s; - wire tdd_mode_s; - + wire up_drp_sel; + wire up_drp_wr; + wire [11:0] up_drp_addr; + wire [31:0] up_drp_wdata; + wire [31:0] up_drp_rdata; + wire up_drp_ready; + wire up_drp_locked; // signal name changes @@ -355,7 +301,74 @@ module axi_ad9361 ( // device interface - axi_ad9361_dev_if #( + generate + if (CMOS_OR_LVDS_N == 1) begin + + assign tx_clk_out_p = 1'd0; + assign tx_clk_out_n = 1'd1; + assign tx_frame_out_p = 1'd0; + assign tx_frame_out_n = 1'd0; + assign tx_data_out_p = 6'h00; + assign tx_data_out_n = 6'h3f; + + assign up_drp_rdata = 32'd0; + assign up_drp_ready = 1'd0; + assign up_drp_locked = 1'd1; + + axi_ad9361_cmos_if #( + .DEVICE_TYPE (DEVICE_TYPE), + .DAC_IODELAY_ENABLE (DAC_IODELAY_ENABLE), + .IO_DELAY_GROUP (IO_DELAY_GROUP)) + i_dev_if ( + .rx_clk_in (rx_clk_in), + .rx_frame_in (rx_frame_in), + .rx_data_in (rx_data_in), + .tx_clk_out (tx_clk_out), + .tx_frame_out (tx_frame_out), + .tx_data_out (tx_data_out), + .enable (enable), + .txnrx (txnrx), + .rst (rst), + .clk (clk), + .l_clk (l_clk), + .adc_valid (adc_valid_s), + .adc_data (adc_data_s), + .adc_status (adc_status_s), + .adc_r1_mode (adc_r1_mode), + .adc_ddr_edgesel (adc_ddr_edgesel_s), + .dac_valid (dac_valid_s), + .dac_data (dac_data_s), + .dac_clksel (dac_clksel_s), + .dac_r1_mode (dac_r1_mode), + .tdd_enable (tdd_enable_s), + .tdd_txnrx (tdd_txnrx_s), + .tdd_mode (tdd_mode_s), + .mmcm_rst (mmcm_rst), + .up_clk (up_clk), + .up_enable (up_enable), + .up_txnrx (up_txnrx), + .up_adc_dld (up_adc_dld_s), + .up_adc_dwdata (up_adc_dwdata_s), + .up_adc_drdata (up_adc_drdata_s), + .up_dac_dld (up_dac_dld_s), + .up_dac_dwdata (up_dac_dwdata_s), + .up_dac_drdata (up_dac_drdata_s), + .delay_clk (delay_clk), + .delay_rst (delay_rst), + .delay_locked (delay_locked_s)); + end + endgenerate + + generate + if (CMOS_OR_LVDS_N == 0) begin + + assign tx_clk_out = 1'd0; + assign tx_frame_out = 1'd0; + assign tx_data_out = 12'd0; + assign up_adc_drdata_s[64:35] = 30'd0; + assign up_dac_drdata_s[79:50] = 30'd0; + + axi_ad9361_lvds_if #( .DEVICE_TYPE (DEVICE_TYPE), .DAC_IODELAY_ENABLE (DAC_IODELAY_ENABLE), .IO_DELAY_GROUP (IO_DELAY_GROUP)) @@ -381,28 +394,97 @@ module axi_ad9361 ( .adc_data (adc_data_s), .adc_status (adc_status_s), .adc_r1_mode (adc_r1_mode), - .adc_ddr_edgesel (adc_ddr_edgesel), + .adc_ddr_edgesel (adc_ddr_edgesel_s), .dac_valid (dac_valid_s), .dac_data (dac_data_s), + .dac_clksel (dac_clksel_s), .dac_r1_mode (dac_r1_mode), .tdd_enable (tdd_enable_s), .tdd_txnrx (tdd_txnrx_s), .tdd_mode (tdd_mode_s), + .mmcm_rst (mmcm_rst), .up_clk (up_clk), .up_enable (up_enable), .up_txnrx (up_txnrx), - .up_adc_dld (up_adc_dld_s), - .up_adc_dwdata (up_adc_dwdata_s), - .up_adc_drdata (up_adc_drdata_s), - .up_dac_dld (up_dac_dld_s), - .up_dac_dwdata (up_dac_dwdata_s), - .up_dac_drdata (up_dac_drdata_s), + .up_adc_dld (up_adc_dld_s[6:0]), + .up_adc_dwdata (up_adc_dwdata_s[34:0]), + .up_adc_drdata (up_adc_drdata_s[34:0]), + .up_dac_dld (up_dac_dld_s[9:0]), + .up_dac_dwdata (up_dac_dwdata_s[49:0]), + .up_dac_drdata (up_dac_drdata_s[49:0]), .delay_clk (delay_clk), .delay_rst (delay_rst), - .delay_locked (delay_locked_s)); + .delay_locked (delay_locked_s), + .up_drp_sel (up_drp_sel), + .up_drp_wr (up_drp_wr), + .up_drp_addr (up_drp_addr), + .up_drp_wdata (up_drp_wdata), + .up_drp_rdata (up_drp_rdata), + .up_drp_ready (up_drp_ready), + .up_drp_locked(up_drp_locked)); + end + endgenerate - // TDD interface + assign adc_valid_i0 = adc_valid_i0_int; + assign adc_valid_q0 = adc_valid_q0_int; + assign adc_valid_i1 = adc_valid_i1_int; + assign adc_valid_q1 = adc_valid_q1_int; + always @(posedge clk) begin + adc_valid_i0_int <= tdd_rx_valid_s & adc_valid_i0_s; + adc_valid_q0_int <= tdd_rx_valid_s & adc_valid_q0_s; + adc_valid_i1_int <= tdd_rx_valid_s & adc_valid_i1_s; + adc_valid_q1_int <= tdd_rx_valid_s & adc_valid_q1_s; + end + + assign adc_data_i0 = adc_data_i0_int; + assign adc_data_q0 = adc_data_q0_int; + assign adc_data_i1 = adc_data_i1_int; + assign adc_data_q1 = adc_data_q1_int; + + always @(posedge clk) begin + adc_data_i0_int <= adc_data_i0_s; + adc_data_q0_int <= adc_data_q0_s; + adc_data_i1_int <= adc_data_i1_s; + adc_data_q1_int <= adc_data_q1_s; + end + + assign dac_valid_i0 = dac_valid_i0_int; + assign dac_valid_q0 = dac_valid_q0_int; + assign dac_valid_i1 = dac_valid_i1_int; + assign dac_valid_q1 = dac_valid_q1_int; + + always @(posedge clk) begin + dac_valid_i0_int <= tdd_tx_valid_s & dac_valid_i0_s; + dac_valid_q0_int <= tdd_tx_valid_s & dac_valid_q0_s; + dac_valid_i1_int <= tdd_tx_valid_s & dac_valid_i1_s; + dac_valid_q1_int <= tdd_tx_valid_s & dac_valid_q1_s; + end + + // tdd + + generate + if (TDD_DISABLE == 1) begin + assign tdd_enable_s = 1'b0; + assign tdd_txnrx_s = 1'b0; + assign tdd_txnrx_s = 1'b0; + assign tdd_mode_s = 1'b0; + assign tdd_rx_vco_en_s = 1'b0; + assign tdd_tx_vco_en_s = 1'b0; + assign tdd_rx_rf_en_s = 1'b0; + assign tdd_tx_rf_en_s = 1'b0; + assign tdd_status_s = 8'd0; + assign tdd_sync_cntr = 1'b0; + assign tdd_tx_valid_s = 1'b1; + assign tdd_rx_valid_s = 1'b1; + assign up_wack_tdd_s = 1'b0; + assign up_rack_tdd_s = 1'b0; + assign up_rdata_tdd_s = 32'b0; + end + endgenerate + + generate + if (TDD_DISABLE == 0) begin axi_ad9361_tdd_if #(.LEVEL_OR_PULSE_N(1)) i_tdd_if ( .clk (clk), .rst (rst), @@ -414,8 +496,6 @@ module axi_ad9361 ( .ad9361_enable (tdd_enable_s), .ad9361_tdd_status (tdd_status_s)); - // TDD control - axi_ad9361_tdd i_tdd ( .clk (clk), .rst (rst), @@ -426,24 +506,9 @@ module axi_ad9361 ( .tdd_enabled (tdd_mode_s), .tdd_status (tdd_status_s), .tdd_sync (tdd_sync), - .tdd_sync_en (tdd_sync_en), - .tdd_terminal_type (tdd_terminal_type), - .tx_valid_i0 (dac_valid_i0_s), - .tx_valid_q0 (dac_valid_q0_s), - .tx_valid_i1 (dac_valid_i1_s), - .tx_valid_q1 (dac_valid_q1_s), - .tdd_tx_valid_i0 (dac_valid_i0), - .tdd_tx_valid_q0 (dac_valid_q0), - .tdd_tx_valid_i1 (dac_valid_i1), - .tdd_tx_valid_q1 (dac_valid_q1), - .rx_valid_i0 (adc_valid_i0_s), - .rx_valid_q0 (adc_valid_q0_s), - .rx_valid_i1 (adc_valid_i1_s), - .rx_valid_q1 (adc_valid_q1_s), - .tdd_rx_valid_i0 (adc_valid_i0), - .tdd_rx_valid_q0 (adc_valid_q0), - .tdd_rx_valid_i1 (adc_valid_i1), - .tdd_rx_valid_q1 (adc_valid_q1), + .tdd_sync_cntr (tdd_sync_cntr), + .tdd_tx_valid (tdd_tx_valid_s), + .tdd_rx_valid (tdd_rx_valid_s), .up_rstn (up_rstn), .up_clk (up_clk), .up_wreq (up_wreq_s), @@ -453,22 +518,28 @@ module axi_ad9361 ( .up_rreq (up_rreq_s), .up_raddr (up_raddr_s), .up_rdata (up_rdata_tdd_s), - .up_rack (up_rack_tdd_s), - .tdd_dbg (tdd_dbg)); + .up_rack (up_rack_tdd_s)); + end + endgenerate // receive axi_ad9361_rx #( .ID (ID), - .DATAPATH_DISABLE (ADC_DATAPATH_DISABLE)) + .MODE_1R1T (MODE_1R1T), + .USERPORTS_DISABLE (ADC_USERPORTS_DISABLE_INT), + .DATAFORMAT_DISABLE (ADC_DATAFORMAT_DISABLE_INT), + .DCFILTER_DISABLE (ADC_DCFILTER_DISABLE_INT), + .IQCORRECTION_DISABLE (ADC_IQCORRECTION_DISABLE_INT)) i_rx ( + .mmcm_rst (mmcm_rst), .adc_rst (rst), .adc_clk (clk), .adc_valid (adc_valid_s), .adc_data (adc_data_s), .adc_status (adc_status_s), .adc_r1_mode (adc_r1_mode), - .adc_ddr_edgesel (adc_ddr_edgesel), + .adc_ddr_edgesel (adc_ddr_edgesel_s), .dac_data (dac_data_s), .up_dld (up_adc_dld_s), .up_dwdata (up_adc_dwdata_s), @@ -478,16 +549,16 @@ module axi_ad9361 ( .delay_locked (delay_locked_s), .adc_enable_i0 (adc_enable_i0), .adc_valid_i0 (adc_valid_i0_s), - .adc_data_i0 (adc_data_i0), + .adc_data_i0 (adc_data_i0_s), .adc_enable_q0 (adc_enable_q0), .adc_valid_q0 (adc_valid_q0_s), - .adc_data_q0 (adc_data_q0), + .adc_data_q0 (adc_data_q0_s), .adc_enable_i1 (adc_enable_i1), .adc_valid_i1 (adc_valid_i1_s), - .adc_data_i1 (adc_data_i1), + .adc_data_i1 (adc_data_i1_s), .adc_enable_q1 (adc_enable_q1), .adc_valid_q1 (adc_valid_q1_s), - .adc_data_q1 (adc_data_q1), + .adc_data_q1 (adc_data_q1_s), .adc_dovf (adc_dovf), .adc_dunf (adc_dunf), .up_adc_gpio_in (up_adc_gpio_in), @@ -501,17 +572,29 @@ module axi_ad9361 ( .up_rreq (up_rreq_s), .up_raddr (up_raddr_s), .up_rdata (up_rdata_rx_s), - .up_rack (up_rack_rx_s)); + .up_rack (up_rack_rx_s), + .up_drp_sel (up_drp_sel), + .up_drp_wr (up_drp_wr), + .up_drp_addr (up_drp_addr), + .up_drp_wdata (up_drp_wdata), + .up_drp_rdata (up_drp_rdata), + .up_drp_ready (up_drp_ready), + .up_drp_locked(up_drp_locked)); // transmit axi_ad9361_tx #( .ID (ID), - .DATAPATH_DISABLE (DAC_DATAPATH_DISABLE)) + .MODE_1R1T (MODE_1R1T), + .DDS_DISABLE (DAC_DDS_DISABLE_INT), + .USERPORTS_DISABLE (DAC_USERPORTS_DISABLE_INT), + .DELAYCNTRL_DISABLE (DAC_DELAYCNTRL_DISABLE_INT), + .IQCORRECTION_DISABLE (DAC_IQCORRECTION_DISABLE_INT)) i_tx ( .dac_clk (clk), .dac_valid (dac_valid_s), .dac_data (dac_data_s), + .dac_clksel (dac_clksel_s), .dac_r1_mode (dac_r1_mode), .adc_data (adc_data_s), .up_dld (up_dac_dld_s), diff --git a/library/axi_ad9361/axi_ad9361_constr.sdc b/library/axi_ad9361/axi_ad9361_constr.sdc new file mode 100644 index 000000000..5c47199cc --- /dev/null +++ b/library/axi_ad9361/axi_ad9361_constr.sdc @@ -0,0 +1,7 @@ + +set_false_path -from [get_registers *i_dev_if|up_enable_int*] -to [get_registers *i_dev_if|enable_up_m1*] +set_false_path -from [get_registers *i_dev_if|up_txnrx_int*] -to [get_registers *i_dev_if|txnrx_up_m1*] +set_false_path -from [get_registers *up_xfer_cntrl:i_xfer_tdd_control|d_xfer_toggle*] -to [get_registers *up_xfer_cntrl:i_xfer_tdd_control|up_xfer_state_m1*] +set_false_path -from [get_registers *up_xfer_cntrl:i_xfer_tdd_control|up_xfer_toggle*] -to [get_registers *up_xfer_cntrl:i_xfer_tdd_control|d_xfer_toggle_m1*] +set_false_path -from [get_registers *up_xfer_cntrl:i_xfer_tdd_control|up_xfer_data*] -to [get_registers *up_xfer_cntrl:i_xfer_tdd_control|d_data_cntrl*] + diff --git a/library/axi_ad9361/axi_ad9361_hw.tcl b/library/axi_ad9361/axi_ad9361_hw.tcl index 5d22fc708..3f8e62b56 100644 --- a/library/axi_ad9361/axi_ad9361_hw.tcl +++ b/library/axi_ad9361/axi_ad9361_hw.tcl @@ -1,185 +1,234 @@ - package require -exact qsys 13.0 source ../scripts/adi_env.tcl source ../scripts/adi_ip_alt.tcl -set_module_property NAME axi_ad9361 -set_module_property DESCRIPTION "AXI AD9361 Interface" -set_module_property VERSION 1.0 -set_module_property GROUP "Analog Devices" -set_module_property DISPLAY_NAME axi_ad9361 - -# files - -add_fileset quartus_synth QUARTUS_SYNTH "" "Quartus Synthesis" -set_fileset_property quartus_synth TOP_LEVEL axi_ad9361 -add_fileset_file ad_rst.v VERILOG PATH $ad_hdl_dir/library/common/ad_rst.v -add_fileset_file ad_lvds_clk.v VERILOG PATH $ad_hdl_dir/library/common/altera/ad_lvds_clk.v -add_fileset_file ad_lvds_in.v VERILOG PATH $ad_hdl_dir/library/common/altera/ad_lvds_in.v -add_fileset_file ad_lvds_out.v VERILOG PATH $ad_hdl_dir/library/common/altera/ad_lvds_out.v -add_fileset_file MULT_MACRO.v VERILOG PATH $ad_hdl_dir/library/common/altera/MULT_MACRO.v -add_fileset_file DSP48E1.v VERILOG PATH $ad_hdl_dir/library/common/altera/DSP48E1.v -add_fileset_file ad_mul.v VERILOG PATH $ad_hdl_dir/library/common/ad_mul.v -add_fileset_file ad_pnmon.v VERILOG PATH $ad_hdl_dir/library/common/ad_pnmon.v -add_fileset_file ad_dds_sine.v VERILOG PATH $ad_hdl_dir/library/common/ad_dds_sine.v -add_fileset_file ad_dds_1.v VERILOG PATH $ad_hdl_dir/library/common/ad_dds_1.v -add_fileset_file ad_dds.v VERILOG PATH $ad_hdl_dir/library/common/ad_dds.v -add_fileset_file ad_datafmt.v VERILOG PATH $ad_hdl_dir/library/common/ad_datafmt.v -add_fileset_file ad_dcfilter.v VERILOG PATH $ad_hdl_dir/library/common/ad_dcfilter.v -add_fileset_file ad_iqcor.v VERILOG PATH $ad_hdl_dir/library/common/ad_iqcor.v -add_fileset_file up_axi.v VERILOG PATH $ad_hdl_dir/library/common/up_axi.v -add_fileset_file up_xfer_cntrl.v VERILOG PATH $ad_hdl_dir/library/common/up_xfer_cntrl.v -add_fileset_file up_xfer_status.v VERILOG PATH $ad_hdl_dir/library/common/up_xfer_status.v -add_fileset_file up_clock_mon.v VERILOG PATH $ad_hdl_dir/library/common/up_clock_mon.v -add_fileset_file up_delay_cntrl.v VERILOG PATH $ad_hdl_dir/library/common/up_delay_cntrl.v -add_fileset_file up_adc_common.v VERILOG PATH $ad_hdl_dir/library/common/up_adc_common.v -add_fileset_file up_adc_channel.v VERILOG PATH $ad_hdl_dir/library/common/up_adc_channel.v -add_fileset_file up_dac_common.v VERILOG PATH $ad_hdl_dir/library/common/up_dac_common.v -add_fileset_file up_dac_channel.v VERILOG PATH $ad_hdl_dir/library/common/up_dac_channel.v -add_fileset_file up_tdd_cntrl.v VERILOG PATH $ad_hdl_dir/library/common/up_tdd_cntrl.v -add_fileset_file ad_tdd_control.v VERILOG PATH $ad_hdl_dir/library/common/ad_tdd_control.v -add_fileset_file ad_addsub.v VERILOG PATH $ad_hdl_dir/library/common/ad_addsub.v -add_fileset_file axi_ad9361_alt_lvds_tx.v VERILOG PATH axi_ad9361_alt_lvds_tx.v -add_fileset_file axi_ad9361_alt_lvds_rx.v VERILOG PATH axi_ad9361_alt_lvds_rx.v -add_fileset_file axi_ad9361_dev_if_alt.v VERILOG PATH axi_ad9361_dev_if_alt.v -add_fileset_file axi_ad9361_rx_pnmon.v VERILOG PATH axi_ad9361_rx_pnmon.v -add_fileset_file axi_ad9361_rx_channel.v VERILOG PATH axi_ad9361_rx_channel.v -add_fileset_file axi_ad9361_rx.v VERILOG PATH axi_ad9361_rx.v -add_fileset_file axi_ad9361_tx_channel.v VERILOG PATH axi_ad9361_tx_channel.v -add_fileset_file axi_ad9361_tx.v VERILOG PATH axi_ad9361_tx.v -add_fileset_file axi_ad9361_tdd.v VERILOG PATH axi_ad9361_tdd.v -add_fileset_file axi_ad9361_tdd_if.v VERILOG PATH axi_ad9361_tdd_if.v -add_fileset_file axi_ad9361.v VERILOG PATH axi_ad9361.v TOP_LEVEL_FILE +ad_ip_create axi_ad9361 {AXI AD9361 Interface} axi_ad9361_elab +ad_ip_files axi_ad9361 [list\ + $ad_hdl_dir/library/altera/common/ad_lvds_clk.v \ + $ad_hdl_dir/library/altera/common/ad_lvds_in.v \ + $ad_hdl_dir/library/altera/common/ad_lvds_out.v \ + $ad_hdl_dir/library/altera/common/ad_mul.v \ + $ad_hdl_dir/library/altera/common/ad_dcfilter.v \ + $ad_hdl_dir/library/common/ad_rst.v \ + $ad_hdl_dir/library/common/ad_pnmon.v \ + $ad_hdl_dir/library/common/ad_dds_sine.v \ + $ad_hdl_dir/library/common/ad_dds_1.v \ + $ad_hdl_dir/library/common/ad_dds.v \ + $ad_hdl_dir/library/common/ad_datafmt.v \ + $ad_hdl_dir/library/common/ad_iqcor.v \ + $ad_hdl_dir/library/common/ad_addsub.v \ + $ad_hdl_dir/library/common/ad_tdd_control.v \ + $ad_hdl_dir/library/common/up_axi.v \ + $ad_hdl_dir/library/common/up_xfer_cntrl.v \ + $ad_hdl_dir/library/common/up_xfer_status.v \ + $ad_hdl_dir/library/common/up_clock_mon.v \ + $ad_hdl_dir/library/common/up_delay_cntrl.v \ + $ad_hdl_dir/library/common/up_adc_common.v \ + $ad_hdl_dir/library/common/up_adc_channel.v \ + $ad_hdl_dir/library/common/up_dac_common.v \ + $ad_hdl_dir/library/common/up_dac_channel.v \ + $ad_hdl_dir/library/common/up_tdd_cntrl.v \ + altera/axi_ad9361_alt_lvds_tx.v \ + altera/axi_ad9361_alt_lvds_rx.v \ + altera/axi_ad9361_lvds_if.v \ + axi_ad9361_rx_pnmon.v \ + axi_ad9361_rx_channel.v \ + axi_ad9361_rx.v \ + axi_ad9361_tx_channel.v \ + axi_ad9361_tx.v \ + axi_ad9361_tdd.v \ + axi_ad9361_tdd_if.v \ + axi_ad9361.v \ + $ad_hdl_dir/library/common/ad_axi_ip_constr.sdc \ + axi_ad9361_constr.sdc] # parameters -add_parameter ID INTEGER 0 -set_parameter_property ID DEFAULT_VALUE 0 -set_parameter_property ID DISPLAY_NAME ID -set_parameter_property ID TYPE INTEGER -set_parameter_property ID UNITS None -set_parameter_property ID HDL_PARAMETER true +ad_ip_parameter DEVICE_FAMILY STRING {Arria 10} +ad_ip_parameter ID INTEGER 0 +ad_ip_parameter MODE_1R1T INTEGER 0 +ad_ip_parameter DEVICE_TYPE INTEGER 0 +ad_ip_parameter TDD_DISABLE INTEGER 0 +ad_ip_parameter CMOS_OR_LVDS_N INTEGER 0 +ad_ip_parameter ADC_DATAPATH_DISABLE INTEGER 0 +ad_ip_parameter ADC_USERPORTS_DISABLE INTEGER 0 +ad_ip_parameter ADC_DATAFORMAT_DISABLE INTEGER 0 +ad_ip_parameter ADC_DCFILTER_DISABLE INTEGER 0 +ad_ip_parameter ADC_IQCORRECTION_DISABLE INTEGER 0 +ad_ip_parameter DAC_IODELAY_ENABLE INTEGER 0 +ad_ip_parameter DAC_DATAPATH_DISABLE INTEGER 0 +ad_ip_parameter DAC_DDS_DISABLE INTEGER 0 +ad_ip_parameter DAC_USERPORTS_DISABLE INTEGER 0 +ad_ip_parameter DAC_IQCORRECTION_DISABLE INTEGER 0 +ad_ip_parameter IO_DELAY_GROUP STRING {dev_if_delay_group} -add_parameter DEVICE_TYPE INTEGER 0 -set_parameter_property DEVICE_TYPE DEFAULT_VALUE 0 -set_parameter_property DEVICE_TYPE DISPLAY_NAME DEVICE_TYPE -set_parameter_property DEVICE_TYPE TYPE INTEGER -set_parameter_property DEVICE_TYPE UNITS None -set_parameter_property DEVICE_TYPE HDL_PARAMETER true +# interfaces -# axi4 slave +ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn + +ad_alt_intf signal dac_sync_in input 1 +ad_alt_intf signal dac_sync_out output 1 +ad_alt_intf signal tdd_sync input 1 +ad_alt_intf signal tdd_sync_cntr output 1 -add_interface s_axi_clock clock end -add_interface_port s_axi_clock s_axi_aclk clk Input 1 +ad_alt_intf clock delay_clk input 1 +ad_alt_intf clock l_clk output 1 +ad_alt_intf clock clk input 1 -add_interface s_axi_reset reset end -set_interface_property s_axi_reset associatedClock s_axi_clock -add_interface_port s_axi_reset s_axi_aresetn reset_n Input 1 +ad_alt_intf reset rst output 1 if_clk +set_interface_property if_rst associatedResetSinks s_axi_reset -add_interface s_axi axi4lite end -set_interface_property s_axi associatedClock s_axi_clock -set_interface_property s_axi associatedReset s_axi_reset -add_interface_port s_axi s_axi_awvalid awvalid Input 1 -add_interface_port s_axi s_axi_awaddr awaddr Input 16 -add_interface_port s_axi s_axi_awprot awprot Input 3 -add_interface_port s_axi s_axi_awready awready Output 1 -add_interface_port s_axi s_axi_wvalid wvalid Input 1 -add_interface_port s_axi s_axi_wdata wdata Input 32 -add_interface_port s_axi s_axi_wstrb wstrb Input 4 -add_interface_port s_axi s_axi_wready wready Output 1 -add_interface_port s_axi s_axi_bvalid bvalid Output 1 -add_interface_port s_axi s_axi_bresp bresp Output 2 -add_interface_port s_axi s_axi_bready bready Input 1 -add_interface_port s_axi s_axi_arvalid arvalid Input 1 -add_interface_port s_axi s_axi_araddr araddr Input 16 -add_interface_port s_axi s_axi_arprot arprot Input 3 -add_interface_port s_axi s_axi_arready arready Output 1 -add_interface_port s_axi s_axi_rvalid rvalid Output 1 -add_interface_port s_axi s_axi_rresp rresp Output 2 -add_interface_port s_axi s_axi_rdata rdata Output 32 -add_interface_port s_axi s_axi_rready rready Input 1 +add_interface adc_ch_0 conduit end +add_interface_port adc_ch_0 adc_enable_i0 enable Output 1 +add_interface_port adc_ch_0 adc_valid_i0 valid Output 1 +add_interface_port adc_ch_0 adc_data_i0 data Output 16 -# device interface +set_interface_property adc_ch_0 associatedClock if_clk +set_interface_property adc_ch_0 associatedReset none -add_interface device_clock clock end -add_interface_port device_clock clk clk Input 1 +add_interface adc_ch_1 conduit end +add_interface_port adc_ch_1 adc_enable_q0 enable Output 1 +add_interface_port adc_ch_1 adc_valid_q0 valid Output 1 +add_interface_port adc_ch_1 adc_data_q0 data Output 16 -add_interface device_if conduit end -set_interface_property device_if associatedClock device_clock -add_interface_port device_if rx_clk_in_p rx_clk_in_p Input 1 -add_interface_port device_if rx_clk_in_n rx_clk_in_n Input 1 -add_interface_port device_if rx_frame_in_p rx_frame_in_p Input 1 -add_interface_port device_if rx_frame_in_n rx_frame_in_n Input 1 -add_interface_port device_if rx_data_in_p rx_data_in_p Input 6 -add_interface_port device_if rx_data_in_n rx_data_in_n Input 6 -add_interface_port device_if tx_clk_out_p tx_clk_out_p Output 1 -add_interface_port device_if tx_clk_out_n tx_clk_out_n Output 1 -add_interface_port device_if tx_frame_out_p tx_frame_out_p Output 1 -add_interface_port device_if tx_frame_out_n tx_frame_out_n Output 1 -add_interface_port device_if tx_data_out_p tx_data_out_p Output 6 -add_interface_port device_if tx_data_out_n tx_data_out_n Output 6 +set_interface_property adc_ch_1 associatedClock if_clk +set_interface_property adc_ch_1 associatedReset none -ad_alt_intf signal dac_sync_in input 1 sync -ad_alt_intf signal dac_sync_out output 1 sync +add_interface adc_ch_2 conduit end +add_interface_port adc_ch_2 adc_enable_i1 enable Output 1 +add_interface_port adc_ch_2 adc_valid_i1 valid Output 1 +add_interface_port adc_ch_2 adc_data_i1 data Output 16 -ad_alt_intf clock l_clk output 1 -ad_alt_intf reset rst output 1 if_l_clk +set_interface_property adc_ch_2 associatedClock if_clk +set_interface_property adc_ch_2 associatedReset none -add_interface fifo_ch_0_in conduit end -#set_interface_property fifo_ch_0_in associatedClock if_l_clk -add_interface_port fifo_ch_0_in adc_enable_i0 enable Output 1 -add_interface_port fifo_ch_0_in adc_valid_i0 valid Output 1 -add_interface_port fifo_ch_0_in adc_data_i0 data Output 16 +add_interface adc_ch_3 conduit end +add_interface_port adc_ch_3 adc_enable_q1 enable Output 1 +add_interface_port adc_ch_3 adc_valid_q1 valid Output 1 +add_interface_port adc_ch_3 adc_data_q1 data Output 16 -add_interface fifo_ch_1_in conduit end -#set_interface_property fifo_ch_1_in associatedClock if_l_clk -add_interface_port fifo_ch_1_in adc_enable_q0 enable Output 1 -add_interface_port fifo_ch_1_in adc_valid_q0 valid Output 1 -add_interface_port fifo_ch_1_in adc_data_q0 data Output 16 +set_interface_property adc_ch_3 associatedClock if_clk +set_interface_property adc_ch_3 associatedReset none -add_interface fifo_ch_2_in conduit end -#set_interface_property fifo_ch_2_in associatedClock if_l_clk -add_interface_port fifo_ch_2_in adc_enable_i1 enable Output 1 -add_interface_port fifo_ch_2_in adc_valid_i1 valid Output 1 -add_interface_port fifo_ch_2_in adc_data_i1 data Output 16 +ad_alt_intf signal adc_dovf input 1 ovf +ad_alt_intf signal adc_dunf input 1 unf +ad_alt_intf signal adc_r1_mode output 1 r1_mode -add_interface fifo_ch_3_in conduit end -#set_interface_property fifo_ch_3_in associatedClock if_l_clk -add_interface_port fifo_ch_3_in adc_enable_q1 enable Output 1 -add_interface_port fifo_ch_3_in adc_valid_q1 valid Output 1 -add_interface_port fifo_ch_3_in adc_data_q1 data Output 16 +add_interface dac_ch_0 conduit end +add_interface_port dac_ch_0 dac_enable_i0 enable Output 1 +add_interface_port dac_ch_0 dac_valid_i0 valid Output 1 +add_interface_port dac_ch_0 dac_data_i0 data Input 16 -ad_alt_intf signal adc_dovf input 1 ovf -ad_alt_intf signal adc_dunf input 1 unf +set_interface_property dac_ch_0 associatedClock if_clk +set_interface_property dac_ch_0 associatedReset none -add_interface fifo_ch_0_out conduit end -#set_interface_property fifo_ch_0_out associatedClock if_l_clk -add_interface_port fifo_ch_0_out dac_enable_i0 enable Output 1 -add_interface_port fifo_ch_0_out dac_valid_i0 valid Output 1 -add_interface_port fifo_ch_0_out dac_data_i0 data Input 16 +add_interface dac_ch_1 conduit end +add_interface_port dac_ch_1 dac_enable_q0 enable Output 1 +add_interface_port dac_ch_1 dac_valid_q0 valid Output 1 +add_interface_port dac_ch_1 dac_data_q0 data Input 16 -add_interface fifo_ch_1_out conduit end -#set_interface_property fifo_ch_1_out associatedClock if_l_clk -add_interface_port fifo_ch_1_out dac_enable_q0 enable Output 1 -add_interface_port fifo_ch_1_out dac_valid_q0 valid Output 1 -add_interface_port fifo_ch_1_out dac_data_q0 data Input 16 +set_interface_property dac_ch_1 associatedClock if_clk +set_interface_property dac_ch_1 associatedReset none -add_interface fifo_ch_2_out conduit end -#set_interface_property fifo_ch_2_out associatedClock if_l_clk -add_interface_port fifo_ch_2_out dac_enable_i1 enable Output 1 -add_interface_port fifo_ch_2_out dac_valid_i1 valid Output 1 -add_interface_port fifo_ch_2_out dac_data_i1 data Input 16 +add_interface dac_ch_2 conduit end +add_interface_port dac_ch_2 dac_enable_i1 enable Output 1 +add_interface_port dac_ch_2 dac_valid_i1 valid Output 1 +add_interface_port dac_ch_2 dac_data_i1 data Input 16 -add_interface fifo_ch_3_out conduit end -#set_interface_property fifo_ch_3_out associatedClock if_l_clk -add_interface_port fifo_ch_3_out dac_enable_q1 enable Output 1 -add_interface_port fifo_ch_3_out dac_valid_q1 valid Output 1 -add_interface_port fifo_ch_3_out dac_data_q1 data Input 16 +set_interface_property dac_ch_2 associatedClock if_clk +set_interface_property dac_ch_2 associatedReset none -ad_alt_intf signal dac_dovf input 1 ovf -ad_alt_intf signal dac_dunf input 1 unf +add_interface dac_ch_3 conduit end +add_interface_port dac_ch_3 dac_enable_q1 enable Output 1 +add_interface_port dac_ch_3 dac_valid_q1 valid Output 1 +add_interface_port dac_ch_3 dac_data_q1 data Input 16 -add_interface delay_clock clock end -add_interface_port delay_clock delay_clk clk Input 1 +set_interface_property dac_ch_3 associatedClock if_clk +set_interface_property dac_ch_3 associatedReset none + +ad_alt_intf signal dac_dovf input 1 ovf +ad_alt_intf signal dac_dunf input 1 unf +ad_alt_intf signal dac_r1_mode output 1 r1_mode + +ad_alt_intf signal up_enable input 1 +ad_alt_intf signal up_txnrx input 1 +ad_alt_intf signal up_dac_gpio_in input 32 +ad_alt_intf signal up_dac_gpio_out output 32 +ad_alt_intf signal up_adc_gpio_in input 32 +ad_alt_intf signal up_adc_gpio_out output 32 + +# generated cores + +add_hdl_instance ad_serdes_clk_core alt_serdes +set_instance_parameter_value ad_serdes_clk_core {MODE} {CLK} +set_instance_parameter_value ad_serdes_clk_core {DDR_OR_SDR_N} {1} +set_instance_parameter_value ad_serdes_clk_core {SERDES_FACTOR} {4} +set_instance_parameter_value ad_serdes_clk_core {CLKIN_FREQUENCY} {250.0} + +add_hdl_instance ad_serdes_in_core_a10 alt_serdes +set_instance_parameter_value ad_serdes_in_core_a10 {MODE} {IN} +set_instance_parameter_value ad_serdes_in_core_a10 {DDR_OR_SDR_N} {1} +set_instance_parameter_value ad_serdes_in_core_a10 {SERDES_FACTOR} {4} +set_instance_parameter_value ad_serdes_in_core_a10 {CLKIN_FREQUENCY} {250.0} + +add_hdl_instance ad_serdes_out_core_a10 alt_serdes +set_instance_parameter_value ad_serdes_out_core_a10 {MODE} {OUT} +set_instance_parameter_value ad_serdes_out_core_a10 {DDR_OR_SDR_N} {1} +set_instance_parameter_value ad_serdes_out_core_a10 {SERDES_FACTOR} {4} +set_instance_parameter_value ad_serdes_out_core_a10 {CLKIN_FREQUENCY} {250.0} + +add_hdl_instance ad_cmos_out_core_a10 alt_serdes +set_instance_parameter_value ad_cmos_out_core_a10 {MODE} {OUT} +set_instance_parameter_value ad_cmos_out_core_a10 {DDR_OR_SDR_N} {1} +set_instance_parameter_value ad_cmos_out_core_a10 {SERDES_FACTOR} {2} +set_instance_parameter_value ad_cmos_out_core_a10 {CLKIN_FREQUENCY} {250.0} + +# updates + +proc axi_ad9361_elab {} { + + set m_cmos_or_lvds_n [get_parameter_value CMOS_OR_LVDS_N] + + add_interface device_if conduit end + set_interface_property device_if associatedClock none + set_interface_property device_if associatedReset none + + if {$m_cmos_or_lvds_n == 1} { + + add_interface_port device_if rx_clk_in rx_clk_in Input 1 + add_interface_port device_if rx_frame_in rx_frame_in Input 1 + add_interface_port device_if rx_data_in rx_data_in Input 12 + add_interface_port device_if tx_clk_out tx_clk_out Output 1 + add_interface_port device_if tx_frame_out tx_frame_out Output 1 + add_interface_port device_if tx_data_out tx_data_out Output 12 + } + + if {$m_cmos_or_lvds_n == 0} { + + add_interface_port device_if rx_clk_in_p rx_clk_in_p Input 1 + add_interface_port device_if rx_clk_in_n rx_clk_in_n Input 1 + add_interface_port device_if rx_frame_in_p rx_frame_in_p Input 1 + add_interface_port device_if rx_frame_in_n rx_frame_in_n Input 1 + add_interface_port device_if rx_data_in_p rx_data_in_p Input 6 + add_interface_port device_if rx_data_in_n rx_data_in_n Input 6 + add_interface_port device_if tx_clk_out_p tx_clk_out_p Output 1 + add_interface_port device_if tx_clk_out_n tx_clk_out_n Output 1 + add_interface_port device_if tx_frame_out_p tx_frame_out_p Output 1 + add_interface_port device_if tx_frame_out_n tx_frame_out_n Output 1 + add_interface_port device_if tx_data_out_p tx_data_out_p Output 6 + add_interface_port device_if tx_data_out_n tx_data_out_n Output 6 + } + + add_interface_port device_if enable enable Output 1 + add_interface_port device_if txnrx txnrx Output 1 +} + +proc axi_ad9361_fileset {entityName} { + + ad_ip_modfile ad_cmos_out.v ad_cmos_out.v ad_cmos_out_core_a10 + ad_ip_modfile ad_serdes_in.v ad_serdes_in.v ad_serdes_in_core_a10 + ad_ip_modfile ad_serdes_out.v ad_serdes_out.v ad_serdes_out_core_a10 + ad_ip_modfile ad_serdes_clk.v ad_serdes_clk.v ad_serdes_clk_core +} diff --git a/library/axi_ad9361/axi_ad9361_ip.tcl b/library/axi_ad9361/axi_ad9361_ip.tcl index 72f0c8e60..e70ad8387 100755 --- a/library/axi_ad9361/axi_ad9361_ip.tcl +++ b/library/axi_ad9361/axi_ad9361_ip.tcl @@ -7,10 +7,13 @@ adi_ip_create axi_ad9361 adi_ip_files axi_ad9361 [list \ "$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc" \ "$ad_hdl_dir/library/common/ad_rst.v" \ - "$ad_hdl_dir/library/common/ad_lvds_clk.v" \ - "$ad_hdl_dir/library/common/ad_lvds_in.v" \ - "$ad_hdl_dir/library/common/ad_lvds_out.v" \ - "$ad_hdl_dir/library/common/ad_mul.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_lvds_clk.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_lvds_in.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_lvds_out.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_cmos_clk.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_cmos_in.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_cmos_out.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_mul.v" \ "$ad_hdl_dir/library/common/ad_pnmon.v" \ "$ad_hdl_dir/library/common/ad_dds_sine.v" \ "$ad_hdl_dir/library/common/ad_dds_1.v" \ @@ -31,7 +34,8 @@ adi_ip_files axi_ad9361 [list \ "$ad_hdl_dir/library/common/up_dac_channel.v" \ "$ad_hdl_dir/library/common/up_tdd_cntrl.v" \ "axi_ad9361_constr.xdc" \ - "axi_ad9361_dev_if.v" \ + "xilinx/axi_ad9361_lvds_if.v" \ + "xilinx/axi_ad9361_cmos_if.v" \ "axi_ad9361_rx_pnmon.v" \ "axi_ad9361_rx_channel.v" \ "axi_ad9361_rx.v" \ @@ -46,11 +50,36 @@ adi_ip_constraints axi_ad9361 [list \ "axi_ad9361_constr.xdc" \ "$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc" ] +set_property driver_value 0 [ipx::get_ports *rx_clk_in* -of_objects [ipx::current_core]] +set_property driver_value 0 [ipx::get_ports *rx_frame_in* -of_objects [ipx::current_core]] +set_property driver_value 0 [ipx::get_ports *rx_data_in* -of_objects [ipx::current_core]] set_property driver_value 0 [ipx::get_ports *dac_sync_in* -of_objects [ipx::current_core]] set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]] set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]] set_property driver_value 0 [ipx::get_ports *gpio_in* -of_objects [ipx::current_core]] +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.CMOS_OR_LVDS_N')) == 0} \ + [ipx::get_ports rx_clk_in_p -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_clk_in_n -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_frame_in_p -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_frame_in_n -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_data_in_p -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_data_in_n -of_objects [ipx::current_core]] \ + [ipx::get_ports tx_clk_out_p -of_objects [ipx::current_core]] \ + [ipx::get_ports tx_clk_out_n -of_objects [ipx::current_core]] \ + [ipx::get_ports tx_frame_out_p -of_objects [ipx::current_core]] \ + [ipx::get_ports tx_frame_out_n -of_objects [ipx::current_core]] \ + [ipx::get_ports tx_data_out_p -of_objects [ipx::current_core]] \ + [ipx::get_ports tx_data_out_n -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.CMOS_OR_LVDS_N')) == 1} \ + [ipx::get_ports rx_clk_in -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_frame_in -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_data_in -of_objects [ipx::current_core]] \ + [ipx::get_ports tx_clk_out -of_objects [ipx::current_core]] \ + [ipx::get_ports tx_frame_out -of_objects [ipx::current_core]] \ + [ipx::get_ports tx_data_out -of_objects [ipx::current_core]] + ipx::remove_bus_interface rst [ipx::current_core] ipx::remove_bus_interface clk [ipx::current_core] ipx::remove_bus_interface l_clk [ipx::current_core] diff --git a/library/axi_ad9361/axi_ad9361_rx.v b/library/axi_ad9361/axi_ad9361_rx.v index e28ee0978..589c9b648 100644 --- a/library/axi_ad9361/axi_ad9361_rx.v +++ b/library/axi_ad9361/axi_ad9361_rx.v @@ -34,137 +34,106 @@ // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // *************************************************************************** // *************************************************************************** -// *************************************************************************** -// *************************************************************************** // ADC channel-need to work on dual mode for pn sequence `timescale 1ns/100ps -module axi_ad9361_rx ( - - // adc interface - - adc_rst, - adc_clk, - adc_valid, - adc_data, - adc_status, - adc_r1_mode, - adc_ddr_edgesel, - dac_data, - - // delay interface - - up_dld, - up_dwdata, - up_drdata, - delay_clk, - delay_rst, - delay_locked, - - // dma interface - - adc_enable_i0, - adc_valid_i0, - adc_data_i0, - adc_enable_q0, - adc_valid_q0, - adc_data_q0, - adc_enable_i1, - adc_valid_i1, - adc_data_i1, - adc_enable_q1, - adc_valid_q1, - adc_data_q1, - adc_dovf, - adc_dunf, - - // gpio - - up_adc_gpio_in, - up_adc_gpio_out, - - // processor interface - - up_rstn, - up_clk, - up_wreq, - up_waddr, - up_wdata, - up_wack, - up_rreq, - up_raddr, - up_rdata, - up_rack); +module axi_ad9361_rx #( // parameters - parameter DATAPATH_DISABLE = 0; - parameter ID = 0; + parameter ID = 0, + parameter MODE_1R1T = 0, + parameter USERPORTS_DISABLE = 0, + parameter DATAFORMAT_DISABLE = 0, + parameter DCFILTER_DISABLE = 0, + parameter IQCORRECTION_DISABLE = 0) ( + + // common + + output mmcm_rst, // adc interface - output adc_rst; - input adc_clk; - input adc_valid; - input [47:0] adc_data; - input adc_status; - output adc_r1_mode; - output adc_ddr_edgesel; - input [47:0] dac_data; + output adc_rst, + input adc_clk, + input adc_valid, + input [47:0] adc_data, + input adc_status, + output adc_r1_mode, + output adc_ddr_edgesel, + input [47:0] dac_data, // delay interface - output [ 6:0] up_dld; - output [34:0] up_dwdata; - input [34:0] up_drdata; - input delay_clk; - output delay_rst; - input delay_locked; + output [12:0] up_dld, + output [64:0] up_dwdata, + input [64:0] up_drdata, + input delay_clk, + output delay_rst, + input delay_locked, // dma interface - output adc_enable_i0; - output adc_valid_i0; - output [15:0] adc_data_i0; - output adc_enable_q0; - output adc_valid_q0; - output [15:0] adc_data_q0; - output adc_enable_i1; - output adc_valid_i1; - output [15:0] adc_data_i1; - output adc_enable_q1; - output adc_valid_q1; - output [15:0] adc_data_q1; - input adc_dovf; - input adc_dunf; + output adc_enable_i0, + output adc_valid_i0, + output [15:0] adc_data_i0, + output adc_enable_q0, + output adc_valid_q0, + output [15:0] adc_data_q0, + output adc_enable_i1, + output adc_valid_i1, + output [15:0] adc_data_i1, + output adc_enable_q1, + output adc_valid_q1, + output [15:0] adc_data_q1, + input adc_dovf, + input adc_dunf, // gpio - input [31:0] up_adc_gpio_in; - output [31:0] up_adc_gpio_out; + input [31:0] up_adc_gpio_in, + output [31:0] up_adc_gpio_out, // processor interface - input up_rstn; - input up_clk; - input up_wreq; - input [13:0] up_waddr; - input [31:0] up_wdata; - output up_wack; - input up_rreq; - input [13:0] up_raddr; - output [31:0] up_rdata; - output up_rack; + input up_rstn, + input up_clk, + input up_wreq, + input [13:0] up_waddr, + input [31:0] up_wdata, + output up_wack, + input up_rreq, + input [13:0] up_raddr, + output [31:0] up_rdata, + output up_rack, + + // drp interface + + output up_drp_sel, + output up_drp_wr, + output [11:0] up_drp_addr, + output [31:0] up_drp_wdata, + input [31:0] up_drp_rdata, + input up_drp_ready, + input up_drp_locked); + + // configuration settings + + localparam CONFIG = (MODE_1R1T * 16) + + (USERPORTS_DISABLE * 8) + + (DATAFORMAT_DISABLE * 4) + + (DCFILTER_DISABLE * 2) + + (IQCORRECTION_DISABLE * 1); // internal registers reg up_status_pn_err = 'd0; reg up_status_pn_oos = 'd0; reg up_status_or = 'd0; - reg [31:0] up_rdata = 'd0; - reg up_rack = 'd0; - reg up_wack = 'd0; + reg [31:0] up_rdata_int = 'd0; + reg up_rack_int = 'd0; + reg up_wack_int = 'd0; // internal signals @@ -176,38 +145,44 @@ module axi_ad9361_rx ( wire [ 3:0] up_adc_pn_oos_s; wire [ 3:0] up_adc_or_s; wire [31:0] up_rdata_s[0:5]; - wire up_rack_s[0:5]; - wire up_wack_s[0:5]; + wire [ 5:0] up_rack_s; + wire [ 5:0] up_wack_s; // processor read interface + assign up_wack = up_wack_int; + assign up_rack = up_rack_int; + assign up_rdata = up_rdata_int; + always @(negedge up_rstn or posedge up_clk) begin if (up_rstn == 0) begin up_status_pn_err <= 'd0; up_status_pn_oos <= 'd0; up_status_or <= 'd0; - up_rdata <= 'd0; - up_rack <= 'd0; - up_wack <= 'd0; + up_rdata_int <= 'd0; + up_rack_int <= 'd0; + up_wack_int <= 'd0; end else begin up_status_pn_err <= | up_adc_pn_err_s; up_status_pn_oos <= | up_adc_pn_oos_s; up_status_or <= | up_adc_or_s; - up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2] | - up_rdata_s[3] | up_rdata_s[4] | up_rdata_s[5]; - up_rack <= up_rack_s[0] | up_rack_s[1] | up_rack_s[2] | - up_rack_s[3] | up_rack_s[4] | up_rack_s[5]; - up_wack <= up_wack_s[0] | up_wack_s[1] | up_wack_s[2] | - up_wack_s[3] | up_wack_s[4] | up_wack_s[5]; + up_rdata_int <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2] | + up_rdata_s[3] | up_rdata_s[4] | up_rdata_s[5]; + up_rack_int <= | up_rack_s; + up_wack_int <= | up_wack_s; end end // channel 0 (i) axi_ad9361_rx_channel #( - .Q_OR_I_N(0), - .CHANNEL_ID(0), - .DATAPATH_DISABLE (DATAPATH_DISABLE)) + .Q_OR_I_N (0), + .CHANNEL_ID (0), + .DISABLE (0), + .USERPORTS_DISABLE (USERPORTS_DISABLE), + .DATAFORMAT_DISABLE (DATAFORMAT_DISABLE), + .DCFILTER_DISABLE (DCFILTER_DISABLE), + .IQCORRECTION_DISABLE (IQCORRECTION_DISABLE)) i_rx_channel_0 ( .adc_clk (adc_clk), .adc_rst (adc_rst), @@ -238,9 +213,13 @@ module axi_ad9361_rx ( // channel 1 (q) axi_ad9361_rx_channel #( - .Q_OR_I_N(1), - .CHANNEL_ID(1), - .DATAPATH_DISABLE (DATAPATH_DISABLE)) + .Q_OR_I_N (1), + .CHANNEL_ID (1), + .DISABLE (0), + .USERPORTS_DISABLE (USERPORTS_DISABLE), + .DATAFORMAT_DISABLE (DATAFORMAT_DISABLE), + .DCFILTER_DISABLE (DCFILTER_DISABLE), + .IQCORRECTION_DISABLE (IQCORRECTION_DISABLE)) i_rx_channel_1 ( .adc_clk (adc_clk), .adc_rst (adc_rst), @@ -271,9 +250,13 @@ module axi_ad9361_rx ( // channel 2 (i) axi_ad9361_rx_channel #( - .Q_OR_I_N(0), - .CHANNEL_ID(2), - .DATAPATH_DISABLE (DATAPATH_DISABLE)) + .Q_OR_I_N (0), + .CHANNEL_ID (2), + .DISABLE (MODE_1R1T), + .USERPORTS_DISABLE (USERPORTS_DISABLE), + .DATAFORMAT_DISABLE (DATAFORMAT_DISABLE), + .DCFILTER_DISABLE (DCFILTER_DISABLE), + .IQCORRECTION_DISABLE (IQCORRECTION_DISABLE)) i_rx_channel_2 ( .adc_clk (adc_clk), .adc_rst (adc_rst), @@ -304,9 +287,13 @@ module axi_ad9361_rx ( // channel 3 (q) axi_ad9361_rx_channel #( - .Q_OR_I_N(1), - .CHANNEL_ID(3), - .DATAPATH_DISABLE (DATAPATH_DISABLE)) + .Q_OR_I_N (1), + .CHANNEL_ID (3), + .DISABLE (MODE_1R1T), + .USERPORTS_DISABLE (USERPORTS_DISABLE), + .DATAFORMAT_DISABLE (DATAFORMAT_DISABLE), + .DCFILTER_DISABLE (DCFILTER_DISABLE), + .IQCORRECTION_DISABLE (IQCORRECTION_DISABLE)) i_rx_channel_3 ( .adc_clk (adc_clk), .adc_rst (adc_rst), @@ -336,8 +323,13 @@ module axi_ad9361_rx ( // common processor control - up_adc_common #(.ID (ID)) i_up_adc_common ( - .mmcm_rst (), + up_adc_common #( + .ID (ID), + .CONFIG (CONFIG), + .DRP_DISABLE (1), + .USERPORTS_DISABLE (USERPORTS_DISABLE)) + i_up_adc_common ( + .mmcm_rst (mmcm_rst), .adc_clk (adc_clk), .adc_rst (adc_rst), .adc_r1_mode (adc_r1_mode), @@ -353,13 +345,13 @@ module axi_ad9361_rx ( .up_status_pn_err (up_status_pn_err), .up_status_pn_oos (up_status_pn_oos), .up_status_or (up_status_or), - .up_drp_sel (), - .up_drp_wr (), - .up_drp_addr (), - .up_drp_wdata (), - .up_drp_rdata (16'd0), - .up_drp_ready (1'd0), - .up_drp_locked (1'd1), + .up_drp_sel (up_drp_sel), + .up_drp_wr (up_drp_wr), + .up_drp_addr (up_drp_addr), + .up_drp_wdata (up_drp_wdata), + .up_drp_rdata (up_drp_rdata), + .up_drp_ready (up_drp_ready), + .up_drp_locked (up_drp_locked), .up_usr_chanmax (), .adc_usr_chanmax (8'd3), .up_adc_gpio_in (up_adc_gpio_in), @@ -377,7 +369,10 @@ module axi_ad9361_rx ( // adc delay control - up_delay_cntrl #(.DATA_WIDTH(7), .BASE_ADDRESS(6'h02)) i_delay_cntrl ( + up_delay_cntrl #( + .DATA_WIDTH (13), + .BASE_ADDRESS (6'h02)) + i_delay_cntrl ( .delay_clk (delay_clk), .delay_rst (delay_rst), .delay_locked (delay_locked), diff --git a/library/axi_ad9361/axi_ad9361_rx_channel.v b/library/axi_ad9361/axi_ad9361_rx_channel.v index 558ea2a80..1f63e1617 100644 --- a/library/axi_ad9361/axi_ad9361_rx_channel.v +++ b/library/axi_ad9361/axi_ad9361_rx_channel.v @@ -34,87 +34,54 @@ // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // *************************************************************************** // *************************************************************************** -// *************************************************************************** -// *************************************************************************** -// ADC channel-need to work on dual mode for pn sequence `timescale 1ns/100ps -module axi_ad9361_rx_channel ( - - // adc interface - - adc_clk, - adc_rst, - adc_valid, - adc_data, - adc_data_q, - adc_or, - dac_data, - - // channel interface - - adc_dcfilter_data_out, - adc_dcfilter_data_in, - adc_iqcor_valid, - adc_iqcor_data, - adc_enable, - up_adc_pn_err, - up_adc_pn_oos, - up_adc_or, - - // processor interface - - up_rstn, - up_clk, - up_wreq, - up_waddr, - up_wdata, - up_wack, - up_rreq, - up_raddr, - up_rdata, - up_rack); +module axi_ad9361_rx_channel #( // parameters - parameter Q_OR_I_N = 0; - parameter CHANNEL_ID = 0; - parameter DATAPATH_DISABLE = 0; + parameter Q_OR_I_N = 0, + parameter CHANNEL_ID = 0, + parameter DISABLE = 0, + parameter USERPORTS_DISABLE = 0, + parameter DATAFORMAT_DISABLE = 0, + parameter DCFILTER_DISABLE = 0, + parameter IQCORRECTION_DISABLE = 0) ( // adc interface - input adc_clk; - input adc_rst; - input adc_valid; - input [11:0] adc_data; - input [11:0] adc_data_q; - input adc_or; - input [11:0] dac_data; + input adc_clk, + input adc_rst, + input adc_valid, + input [11:0] adc_data, + input [11:0] adc_data_q, + input adc_or, + input [11:0] dac_data, // channel interface - output [15:0] adc_dcfilter_data_out; - input [15:0] adc_dcfilter_data_in; - output adc_iqcor_valid; - output [15:0] adc_iqcor_data; - output adc_enable; - output up_adc_pn_err; - output up_adc_pn_oos; - output up_adc_or; + output [15:0] adc_dcfilter_data_out, + input [15:0] adc_dcfilter_data_in, + output adc_iqcor_valid, + output [15:0] adc_iqcor_data, + output adc_enable, + output up_adc_pn_err, + output up_adc_pn_oos, + output up_adc_or, // processor interface - input up_rstn; - input up_clk; - input up_wreq; - input [13:0] up_waddr; - input [31:0] up_wdata; - output up_wack; - input up_rreq; - input [13:0] up_raddr; - output [31:0] up_rdata; - output up_rack; + input up_rstn, + input up_clk, + input up_wreq, + input [13:0] up_waddr, + input [31:0] up_wdata, + output up_wack, + input up_rreq, + input [13:0] up_raddr, + output [31:0] up_rdata, + output up_rack); // internal signals @@ -137,12 +104,35 @@ module axi_ad9361_rx_channel ( wire adc_pn_err_s; wire adc_pn_oos_s; + // data-path disable + + generate + if (DISABLE == 1) begin + assign adc_dcfilter_data_out = 16'd0; + assign adc_iqcor_valid = 1'd0; + assign adc_iqcor_data = 16'd0; + assign adc_enable = 1'd0; + assign up_adc_pn_err = 1'd0; + assign up_adc_pn_oos = 1'd0; + assign up_adc_or = 1'd0; + assign up_wack = 1'd0; + assign up_rdata = 32'd0; + assign up_rack = 1'd0; + end + endgenerate + + generate + if (DISABLE == 0) begin + // iq correction inputs assign adc_data_s = (adc_data_sel_s == 4'h0) ? adc_data : dac_data; assign adc_dcfilter_data_out = adc_dcfilter_data_s; - axi_ad9361_rx_pnmon #(.Q_OR_I_N (Q_OR_I_N), .PRBS_SEL (CHANNEL_ID)) i_rx_pnmon ( + axi_ad9361_rx_pnmon #( + .Q_OR_I_N (Q_OR_I_N), + .PRBS_SEL (CHANNEL_ID)) + i_rx_pnmon ( .adc_clk (adc_clk), .adc_valid (adc_valid), .adc_data_i (adc_data), @@ -151,12 +141,10 @@ module axi_ad9361_rx_channel ( .adc_pn_oos (adc_pn_oos_s), .adc_pn_err (adc_pn_err_s)); - generate - if (DATAPATH_DISABLE == 1) begin - assign adc_dfmt_valid_s = adc_valid; - assign adc_dfmt_data_s = {4'd0, adc_data_s}; - end else begin - ad_datafmt #(.DATA_WIDTH (12)) i_ad_datafmt ( + ad_datafmt #( + .DATA_WIDTH (12), + .DISABLE (DATAFORMAT_DISABLE)) + i_ad_datafmt ( .clk (adc_clk), .valid (adc_valid), .data (adc_data_s), @@ -165,15 +153,10 @@ module axi_ad9361_rx_channel ( .dfmt_enable (adc_dfmt_enable_s), .dfmt_type (adc_dfmt_type_s), .dfmt_se (adc_dfmt_se_s)); - end - endgenerate - generate - if (DATAPATH_DISABLE == 1) begin - assign adc_dcfilter_valid_s = adc_dfmt_valid_s; - assign adc_dcfilter_data_s = adc_dfmt_data_s; - end else begin - ad_dcfilter i_ad_dcfilter ( + ad_dcfilter #( + .DISABLE (DCFILTER_DISABLE)) + i_ad_dcfilter ( .clk (adc_clk), .valid (adc_dfmt_valid_s), .data (adc_dfmt_data_s), @@ -182,15 +165,11 @@ module axi_ad9361_rx_channel ( .dcfilt_enb (adc_dcfilt_enb_s), .dcfilt_coeff (adc_dcfilt_coeff_s), .dcfilt_offset (adc_dcfilt_offset_s)); - end - endgenerate - generate - if (DATAPATH_DISABLE == 1) begin - assign adc_iqcor_valid = adc_dcfilter_valid_s; - assign adc_iqcor_data = adc_dcfilter_data_s; - end else begin - ad_iqcor #(.Q_OR_I_N (Q_OR_I_N)) i_ad_iqcor ( + ad_iqcor #( + .Q_OR_I_N (Q_OR_I_N), + .DISABLE (IQCORRECTION_DISABLE)) + i_ad_iqcor ( .clk (adc_clk), .valid (adc_dcfilter_valid_s), .data_in (adc_dcfilter_data_s), @@ -200,10 +179,14 @@ module axi_ad9361_rx_channel ( .iqcor_enable (adc_iqcor_enb_s), .iqcor_coeff_1 (adc_iqcor_coeff_1_s), .iqcor_coeff_2 (adc_iqcor_coeff_2_s)); - end - endgenerate - up_adc_channel #(.ADC_CHANNEL_ID (CHANNEL_ID)) i_up_adc_channel ( + up_adc_channel #( + .CHANNEL_ID (CHANNEL_ID), + .USERPORTS_DISABLE (USERPORTS_DISABLE), + .DATAFORMAT_DISABLE (DATAFORMAT_DISABLE), + .DCFILTER_DISABLE (DCFILTER_DISABLE), + .IQCORRECTION_DISABLE (IQCORRECTION_DISABLE)) + i_up_adc_channel ( .adc_clk (adc_clk), .adc_rst (adc_rst), .adc_enable (adc_enable), @@ -249,6 +232,9 @@ module axi_ad9361_rx_channel ( .up_rdata (up_rdata), .up_rack (up_rack)); + end + endgenerate + endmodule // *************************************************************************** diff --git a/library/axi_ad9361/axi_ad9361_tdd.v b/library/axi_ad9361/axi_ad9361_tdd.v index 914ad1f6d..d0955817f 100644 --- a/library/axi_ad9361/axi_ad9361_tdd.v +++ b/library/axi_ad9361/axi_ad9361_tdd.v @@ -61,30 +61,12 @@ module axi_ad9361_tdd ( // sync signal tdd_sync, - tdd_sync_en, - tdd_terminal_type, + tdd_sync_cntr, // tx/rx data flow control - tx_valid_i0, - tx_valid_q0, - tx_valid_i1, - tx_valid_q1, - - tdd_tx_valid_i0, - tdd_tx_valid_q0, - tdd_tx_valid_i1, - tdd_tx_valid_q1, - - rx_valid_i0, - rx_valid_q0, - rx_valid_i1, - rx_valid_q1, - - tdd_rx_valid_i0, - tdd_rx_valid_q0, - tdd_rx_valid_i1, - tdd_rx_valid_q1, + tdd_tx_valid, + tdd_rx_valid, // bus interface @@ -97,10 +79,7 @@ module axi_ad9361_tdd ( up_rreq, up_raddr, up_rdata, - up_rack, - - tdd_dbg -); + up_rack); input clk; input rst; @@ -116,32 +95,12 @@ module axi_ad9361_tdd ( input [ 7:0] tdd_status; input tdd_sync; - output tdd_sync_en; - output tdd_terminal_type; + output tdd_sync_cntr; - // tx data flow control + // data flow control - input tx_valid_i0; - input tx_valid_q0; - input tx_valid_i1; - input tx_valid_q1; - - output tdd_tx_valid_i0; - output tdd_tx_valid_q0; - output tdd_tx_valid_i1; - output tdd_tx_valid_q1; - - // rx data flow control - - input rx_valid_i0; - input rx_valid_q0; - input rx_valid_i1; - input rx_valid_q1; - - output tdd_rx_valid_i0; - output tdd_rx_valid_q0; - output tdd_rx_valid_i1; - output tdd_rx_valid_q1; + output tdd_tx_valid; + output tdd_rx_valid; // bus interface @@ -156,15 +115,13 @@ module axi_ad9361_tdd ( output [31:0] up_rdata; output up_rack; - output [41:0] tdd_dbg; - - reg tdd_slave_synced = 1'b0; + reg tdd_tx_valid = 1'b0; + reg tdd_rx_valid = 1'b0; // internal signals wire rst; wire tdd_enable_s; - wire tdd_enable_synced_s; wire tdd_secondary_s; wire [ 7:0] tdd_burst_count_s; wire tdd_rx_only_s; @@ -181,6 +138,8 @@ module axi_ad9361_tdd ( wire [23:0] tdd_vco_tx_off_1_s; wire [23:0] tdd_rx_on_1_s; wire [23:0] tdd_rx_off_1_s; + wire [23:0] tdd_rx_dp_on_1_s; + wire [23:0] tdd_rx_dp_off_1_s; wire [23:0] tdd_tx_on_1_s; wire [23:0] tdd_tx_off_1_s; wire [23:0] tdd_tx_dp_on_1_s; @@ -191,6 +150,8 @@ module axi_ad9361_tdd ( wire [23:0] tdd_vco_tx_off_2_s; wire [23:0] tdd_rx_on_2_s; wire [23:0] tdd_rx_off_2_s; + wire [23:0] tdd_rx_dp_on_2_s; + wire [23:0] tdd_rx_dp_off_2_s; wire [23:0] tdd_tx_on_2_s; wire [23:0] tdd_tx_off_2_s; wire [23:0] tdd_tx_dp_on_2_s; @@ -198,33 +159,29 @@ module axi_ad9361_tdd ( wire [23:0] tdd_counter_status; + wire tdd_rx_dp_en_s; wire tdd_tx_dp_en_s; - assign tdd_dbg = {tdd_counter_status, tdd_enable_s, tdd_sync, tdd_tx_dp_en_s, - tdd_rx_vco_en, tdd_tx_vco_en, tdd_rx_rf_en, tdd_tx_rf_en}; + assign tdd_enabled = tdd_enable_s; + assign tdd_sync_cntr = ~(tdd_enable_s & tdd_terminal_type_s); // tx/rx data flow control - assign tdd_tx_valid_i0 = ((tdd_enable_synced_s & tdd_gated_tx_dmapath_s) == 1'b1) ? - (tx_valid_i0 & tdd_tx_dp_en_s) : tx_valid_i0; - assign tdd_tx_valid_q0 = ((tdd_enable_synced_s & tdd_gated_tx_dmapath_s) == 1'b1) ? - (tx_valid_q0 & tdd_tx_dp_en_s) : tx_valid_q0; - assign tdd_tx_valid_i1 = ((tdd_enable_synced_s & tdd_gated_tx_dmapath_s) == 1'b1) ? - (tx_valid_i1 & tdd_tx_dp_en_s) : tx_valid_i1; - assign tdd_tx_valid_q1 = ((tdd_enable_synced_s & tdd_gated_tx_dmapath_s) == 1'b1) ? - (tx_valid_q1 & tdd_tx_dp_en_s) : tx_valid_q1; + always @(posedge clk) begin + if((tdd_enable_s == 1) && (tdd_gated_tx_dmapath_s == 1)) begin + tdd_tx_valid <= tdd_tx_dp_en_s; + end else begin + tdd_tx_valid <= 1'b1; + end + end - assign tdd_rx_valid_i0 = ((tdd_enable_synced_s & tdd_gated_rx_dmapath_s) == 1'b1) ? - (rx_valid_i0 & tdd_rx_rf_en) : rx_valid_i0; - assign tdd_rx_valid_q0 = ((tdd_enable_synced_s & tdd_gated_rx_dmapath_s) == 1'b1) ? - (rx_valid_q0 & tdd_rx_rf_en) : rx_valid_q0; - assign tdd_rx_valid_i1 = ((tdd_enable_synced_s & tdd_gated_rx_dmapath_s) == 1'b1) ? - (rx_valid_i1 & tdd_rx_rf_en) : rx_valid_i1; - assign tdd_rx_valid_q1 = ((tdd_enable_synced_s & tdd_gated_rx_dmapath_s) == 1'b1) ? - (rx_valid_q1 & tdd_rx_rf_en) : rx_valid_q1; - - assign tdd_enabled = tdd_enable_synced_s; - assign tdd_terminal_type = ~tdd_terminal_type_s; + always @(posedge clk) begin + if((tdd_enable_s == 1) && (tdd_gated_tx_dmapath_s == 1)) begin + tdd_rx_valid <= tdd_rx_dp_en_s; + end else begin + tdd_rx_valid <= 1'b1; + end + end // instantiations @@ -241,13 +198,14 @@ module axi_ad9361_tdd ( .tdd_counter_init(tdd_counter_init_s), .tdd_frame_length(tdd_frame_length_s), .tdd_terminal_type(tdd_terminal_type_s), - .tdd_sync_enable(tdd_sync_enable_s), .tdd_vco_rx_on_1(tdd_vco_rx_on_1_s), .tdd_vco_rx_off_1(tdd_vco_rx_off_1_s), .tdd_vco_tx_on_1(tdd_vco_tx_on_1_s), .tdd_vco_tx_off_1(tdd_vco_tx_off_1_s), .tdd_rx_on_1(tdd_rx_on_1_s), .tdd_rx_off_1(tdd_rx_off_1_s), + .tdd_rx_dp_on_1(tdd_rx_dp_on_1_s), + .tdd_rx_dp_off_1(tdd_rx_dp_off_1_s), .tdd_tx_on_1(tdd_tx_on_1_s), .tdd_tx_off_1(tdd_tx_off_1_s), .tdd_tx_dp_on_1(tdd_tx_dp_on_1_s), @@ -258,6 +216,8 @@ module axi_ad9361_tdd ( .tdd_vco_tx_off_2(tdd_vco_tx_off_2_s), .tdd_rx_on_2(tdd_rx_on_2_s), .tdd_rx_off_2(tdd_rx_off_2_s), + .tdd_rx_dp_on_2(tdd_rx_dp_on_2_s), + .tdd_rx_dp_off_2(tdd_rx_dp_off_2_s), .tdd_tx_on_2(tdd_tx_on_2_s), .tdd_tx_off_2(tdd_tx_off_2_s), .tdd_tx_dp_on_2(tdd_tx_dp_on_2_s), @@ -278,13 +238,12 @@ module axi_ad9361_tdd ( // for the axi_ad9361 core ad_tdd_control #( - .TX_DATA_PATH_DELAY(14), - .CONTROL_PATH_DELAY(3)) + .TX_DATA_PATH_DELAY(), + .CONTROL_PATH_DELAY()) i_tdd_control( .clk(clk), .rst(rst), .tdd_enable(tdd_enable_s), - .tdd_enable_synced (tdd_enable_synced_s), .tdd_secondary(tdd_secondary_s), .tdd_counter_init(tdd_counter_init_s), .tdd_frame_length(tdd_frame_length_s), @@ -292,13 +251,14 @@ module axi_ad9361_tdd ( .tdd_rx_only(tdd_rx_only_s), .tdd_tx_only(tdd_tx_only_s), .tdd_sync (tdd_sync), - .tdd_sync_en (tdd_sync_en), .tdd_vco_rx_on_1(tdd_vco_rx_on_1_s), .tdd_vco_rx_off_1(tdd_vco_rx_off_1_s), .tdd_vco_tx_on_1(tdd_vco_tx_on_1_s), .tdd_vco_tx_off_1(tdd_vco_tx_off_1_s), .tdd_rx_on_1(tdd_rx_on_1_s), .tdd_rx_off_1(tdd_rx_off_1_s), + .tdd_rx_dp_on_1(tdd_rx_dp_on_1_s), + .tdd_rx_dp_off_1(tdd_rx_dp_off_1_s), .tdd_tx_on_1(tdd_tx_on_1_s), .tdd_tx_off_1(tdd_tx_off_1_s), .tdd_tx_dp_on_1(tdd_tx_dp_on_1_s), @@ -309,10 +269,13 @@ module axi_ad9361_tdd ( .tdd_vco_tx_off_2(tdd_vco_tx_off_2_s), .tdd_rx_on_2(tdd_rx_on_2_s), .tdd_rx_off_2(tdd_rx_off_2_s), + .tdd_rx_dp_on_2(tdd_rx_dp_on_2_s), + .tdd_rx_dp_off_2(tdd_rx_dp_off_2_s), .tdd_tx_on_2(tdd_tx_on_2_s), .tdd_tx_off_2(tdd_tx_off_2_s), .tdd_tx_dp_on_2(tdd_tx_dp_on_2_s), .tdd_tx_dp_off_2(tdd_tx_dp_off_2_s), + .tdd_rx_dp_en(tdd_rx_dp_en_s), .tdd_tx_dp_en(tdd_tx_dp_en_s), .tdd_rx_vco_en(tdd_rx_vco_en), .tdd_tx_vco_en(tdd_tx_vco_en), diff --git a/library/axi_ad9361/axi_ad9361_tx.v b/library/axi_ad9361/axi_ad9361_tx.v index 6c36e28b6..c6484a5e6 100644 --- a/library/axi_ad9361/axi_ad9361_tx.v +++ b/library/axi_ad9361/axi_ad9361_tx.v @@ -1,9 +1,9 @@ // *************************************************************************** // *************************************************************************** // Copyright 2011(c) Analog Devices, Inc. -// +// // All rights reserved. -// +// // Redistribution and use in source and binary forms, with or without modification, // are permitted provided that the following conditions are met: // - Redistributions of source code must retain the above copyright @@ -21,155 +21,111 @@ // patent holders to use this software. // - Use of the software either in source or binary form, must be run // on or directly connected to an Analog Devices Inc. component. -// +// // THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, // INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A // PARTICULAR PURPOSE ARE DISCLAIMED. // // IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, // EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY -// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR // BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // *************************************************************************** // *************************************************************************** `timescale 1ns/100ps -module axi_ad9361_tx ( - - // dac interface - - dac_clk, - dac_valid, - dac_data, - dac_r1_mode, - adc_data, - - // delay interface - - up_dld, - up_dwdata, - up_drdata, - delay_clk, - delay_rst, - delay_locked, - - // master/slave - - dac_sync_in, - dac_sync_out, - - // dma interface - - dac_enable_i0, - dac_valid_i0, - dac_data_i0, - dac_enable_q0, - dac_valid_q0, - dac_data_q0, - dac_enable_i1, - dac_valid_i1, - dac_data_i1, - dac_enable_q1, - dac_valid_q1, - dac_data_q1, - dac_dovf, - dac_dunf, - - // gpio - - up_dac_gpio_in, - up_dac_gpio_out, - - // processor interface - - up_rstn, - up_clk, - up_wreq, - up_waddr, - up_wdata, - up_wack, - up_rreq, - up_raddr, - up_rdata, - up_rack); +module axi_ad9361_tx #( // parameters - parameter DATAPATH_DISABLE = 0; - parameter ID = 0; + parameter ID = 0, + parameter MODE_1R1T = 0, + parameter DDS_DISABLE = 0, + parameter USERPORTS_DISABLE = 0, + parameter DELAYCNTRL_DISABLE = 0, + parameter IQCORRECTION_DISABLE = 0) ( // dac interface - input dac_clk; - output dac_valid; - output [47:0] dac_data; - output dac_r1_mode; - input [47:0] adc_data; - + input dac_clk, + output dac_valid, + output [47:0] dac_data, + output dac_clksel, + output dac_r1_mode, + input [47:0] adc_data, + // delay interface - output [ 9:0] up_dld; - output [49:0] up_dwdata; - input [49:0] up_drdata; - input delay_clk; - output delay_rst; - input delay_locked; + output [15:0] up_dld, + output [79:0] up_dwdata, + input [79:0] up_drdata, + input delay_clk, + output delay_rst, + input delay_locked, // master/slave - input dac_sync_in; - output dac_sync_out; + input dac_sync_in, + output dac_sync_out, // dma interface - output dac_enable_i0; - output dac_valid_i0; - input [15:0] dac_data_i0; - output dac_enable_q0; - output dac_valid_q0; - input [15:0] dac_data_q0; - output dac_enable_i1; - output dac_valid_i1; - input [15:0] dac_data_i1; - output dac_enable_q1; - output dac_valid_q1; - input [15:0] dac_data_q1; - input dac_dovf; - input dac_dunf; + output dac_enable_i0, + output dac_valid_i0, + input [15:0] dac_data_i0, + output dac_enable_q0, + output dac_valid_q0, + input [15:0] dac_data_q0, + output dac_enable_i1, + output dac_valid_i1, + input [15:0] dac_data_i1, + output dac_enable_q1, + output dac_valid_q1, + input [15:0] dac_data_q1, + input dac_dovf, + input dac_dunf, // gpio - input [31:0] up_dac_gpio_in; - output [31:0] up_dac_gpio_out; + input [31:0] up_dac_gpio_in, + output [31:0] up_dac_gpio_out, // processor interface - input up_rstn; - input up_clk; - input up_wreq; - input [13:0] up_waddr; - input [31:0] up_wdata; - output up_wack; - input up_rreq; - input [13:0] up_raddr; - output [31:0] up_rdata; - output up_rack; + input up_rstn, + input up_clk, + input up_wreq, + input [13:0] up_waddr, + input [31:0] up_wdata, + output up_wack, + input up_rreq, + input [13:0] up_raddr, + output [31:0] up_rdata, + output up_rack); + + // configuration settings + + localparam CONFIG = (DDS_DISABLE * 64) + + (DELAYCNTRL_DISABLE * 32) + + (MODE_1R1T * 16) + + (USERPORTS_DISABLE * 8) + + (IQCORRECTION_DISABLE * 1); // internal registers reg dac_data_sync = 'd0; reg [ 7:0] dac_rate_cnt = 'd0; - reg dac_valid = 'd0; - reg dac_valid_i0 = 'd0; - reg dac_valid_q0 = 'd0; - reg dac_valid_i1 = 'd0; - reg dac_valid_q1 = 'd0; - reg [31:0] up_rdata = 'd0; - reg up_rack = 'd0; - reg up_wack = 'd0; + reg dac_valid_int = 'd0; + reg dac_valid_i0_int = 'd0; + reg dac_valid_q0_int = 'd0; + reg dac_valid_i1_int = 'd0; + reg dac_valid_q1_int = 'd0; + reg up_wack_int = 'd0; + reg up_rack_int = 'd0; + reg [31:0] up_rdata_int = 'd0; // internal clock and resets @@ -181,9 +137,9 @@ module axi_ad9361_tx ( wire dac_dds_format_s; wire [ 7:0] dac_datarate_s; wire [47:0] dac_data_int_s; + wire [ 5:0] up_wack_s; + wire [ 5:0] up_rack_s; wire [31:0] up_rdata_s[0:5]; - wire up_rack_s[0:5]; - wire up_wack_s[0:5]; // master/slave @@ -205,41 +161,52 @@ module axi_ad9361_tx ( // dma interface + assign dac_valid = dac_valid_int; + assign dac_valid_i0 = dac_valid_i0_int; + assign dac_valid_q0 = dac_valid_q0_int; + assign dac_valid_i1 = dac_valid_i1_int; + assign dac_valid_q1 = dac_valid_q1_int; + always @(posedge dac_clk) begin - dac_valid <= (dac_rate_cnt == 8'd0) ? 1'b1 : 1'b0; - dac_valid_i0 <= dac_valid; - dac_valid_q0 <= dac_valid; - dac_valid_i1 <= dac_valid & ~dac_r1_mode; - dac_valid_q1 <= dac_valid & ~dac_r1_mode; + dac_valid_int <= (dac_rate_cnt == 8'd0) ? 1'b1 : 1'b0; + dac_valid_i0_int <= dac_valid_int; + dac_valid_q0_int <= dac_valid_int; + dac_valid_i1_int <= dac_valid_int & ~dac_r1_mode; + dac_valid_q1_int <= dac_valid_int & ~dac_r1_mode; end // processor read interface + assign up_wack = up_wack_int; + assign up_rack = up_rack_int; + assign up_rdata = up_rdata_int; + always @(negedge up_rstn or posedge up_clk) begin if (up_rstn == 0) begin - up_rdata <= 'd0; - up_rack <= 'd0; - up_wack <= 'd0; + up_wack_int <= 'd0; + up_rack_int <= 'd0; + up_rdata_int <= 'd0; end else begin - up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2] | - up_rdata_s[3] | up_rdata_s[4] | up_rdata_s[5]; - up_rack <= up_rack_s[0] | up_rack_s[1] | up_rack_s[2] | - up_rack_s[3] | up_rack_s[4] | up_rack_s[5]; - up_wack <= up_wack_s[0] | up_wack_s[1] | up_wack_s[2] | - up_wack_s[3] | up_wack_s[4] | up_wack_s[5]; + up_wack_int <= | up_wack_s; + up_rack_int <= | up_rack_s; + up_rdata_int <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2] | + up_rdata_s[3] | up_rdata_s[4] | up_rdata_s[5]; end end // dac channel - + axi_ad9361_tx_channel #( .CHANNEL_ID (0), .Q_OR_I_N (0), - .DATAPATH_DISABLE (DATAPATH_DISABLE)) + .DISABLE (0), + .DDS_DISABLE (DDS_DISABLE), + .USERPORTS_DISABLE (USERPORTS_DISABLE), + .IQCORRECTION_DISABLE (IQCORRECTION_DISABLE)) i_tx_channel_0 ( .dac_clk (dac_clk), .dac_rst (dac_rst), - .dac_valid (dac_valid), + .dac_valid (dac_valid_int), .dma_data (dac_data_i0), .adc_data (adc_data[11:0]), .dac_data (dac_data[11:0]), @@ -260,15 +227,18 @@ module axi_ad9361_tx ( .up_rack (up_rack_s[0])); // dac channel - + axi_ad9361_tx_channel #( .CHANNEL_ID (1), .Q_OR_I_N (1), - .DATAPATH_DISABLE (DATAPATH_DISABLE)) + .DISABLE (0), + .DDS_DISABLE (DDS_DISABLE), + .USERPORTS_DISABLE (USERPORTS_DISABLE), + .IQCORRECTION_DISABLE (IQCORRECTION_DISABLE)) i_tx_channel_1 ( .dac_clk (dac_clk), .dac_rst (dac_rst), - .dac_valid (dac_valid), + .dac_valid (dac_valid_int), .dma_data (dac_data_q0), .adc_data (adc_data[23:12]), .dac_data (dac_data[23:12]), @@ -289,15 +259,18 @@ module axi_ad9361_tx ( .up_rack (up_rack_s[1])); // dac channel - + axi_ad9361_tx_channel #( .CHANNEL_ID (2), .Q_OR_I_N (0), - .DATAPATH_DISABLE (DATAPATH_DISABLE)) + .DISABLE (MODE_1R1T), + .DDS_DISABLE (DDS_DISABLE), + .USERPORTS_DISABLE (USERPORTS_DISABLE), + .IQCORRECTION_DISABLE (IQCORRECTION_DISABLE)) i_tx_channel_2 ( .dac_clk (dac_clk), .dac_rst (dac_rst), - .dac_valid (dac_valid), + .dac_valid (dac_valid_int), .dma_data (dac_data_i1), .adc_data (adc_data[35:24]), .dac_data (dac_data[35:24]), @@ -318,15 +291,18 @@ module axi_ad9361_tx ( .up_rack (up_rack_s[2])); // dac channel - + axi_ad9361_tx_channel #( .CHANNEL_ID (3), .Q_OR_I_N (1), - .DATAPATH_DISABLE (DATAPATH_DISABLE)) + .DISABLE (MODE_1R1T), + .DDS_DISABLE (DDS_DISABLE), + .USERPORTS_DISABLE (USERPORTS_DISABLE), + .IQCORRECTION_DISABLE (IQCORRECTION_DISABLE)) i_tx_channel_3 ( .dac_clk (dac_clk), .dac_rst (dac_rst), - .dac_valid (dac_valid), + .dac_valid (dac_valid_int), .dma_data (dac_data_q1), .adc_data (adc_data[47:36]), .dac_data (dac_data[47:36]), @@ -348,12 +324,18 @@ module axi_ad9361_tx ( // dac common processor interface - up_dac_common #(.ID (ID)) i_up_dac_common ( + up_dac_common #( + .ID (ID), + .CONFIG (CONFIG), + .DRP_DISABLE (1), + .USERPORTS_DISABLE (USERPORTS_DISABLE)) + i_up_dac_common ( .mmcm_rst (), .dac_clk (dac_clk), .dac_rst (dac_rst), .dac_sync (dac_sync_out), .dac_frame (), + .dac_clksel (dac_clksel), .dac_par_type (), .dac_par_enb (), .dac_r1_mode (dac_r1_mode), @@ -367,7 +349,7 @@ module axi_ad9361_tx ( .up_drp_wr (), .up_drp_addr (), .up_drp_wdata (), - .up_drp_rdata (16'd0), + .up_drp_rdata (32'd0), .up_drp_ready (1'd0), .up_drp_locked (1'd1), .up_usr_chanmax (), @@ -384,10 +366,14 @@ module axi_ad9361_tx ( .up_raddr (up_raddr), .up_rdata (up_rdata_s[4]), .up_rack (up_rack_s[4])); - + // dac delay control - up_delay_cntrl #(.DATA_WIDTH(10), .BASE_ADDRESS(6'h12)) i_delay_cntrl ( + up_delay_cntrl #( + .DISABLE (DELAYCNTRL_DISABLE), + .DATA_WIDTH(16), + .BASE_ADDRESS(6'h12)) + i_delay_cntrl ( .delay_clk (delay_clk), .delay_rst (delay_rst), .delay_locked (delay_locked), diff --git a/library/axi_ad9361/axi_ad9361_tx_channel.v b/library/axi_ad9361/axi_ad9361_tx_channel.v index f64859640..f69ea52f9 100644 --- a/library/axi_ad9361/axi_ad9361_tx_channel.v +++ b/library/axi_ad9361/axi_ad9361_tx_channel.v @@ -34,90 +34,64 @@ // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // *************************************************************************** // *************************************************************************** -// *************************************************************************** -// *************************************************************************** `timescale 1ns/100ps -module axi_ad9361_tx_channel ( - - // dac interface - - dac_clk, - dac_rst, - dac_valid, - dma_data, - adc_data, - dac_data, - dac_data_out, - dac_data_in, - - // processor interface - - dac_enable, - dac_data_sync, - dac_dds_format, - - // bus interface - - up_rstn, - up_clk, - up_wreq, - up_waddr, - up_wdata, - up_wack, - up_rreq, - up_raddr, - up_rdata, - up_rack); +module axi_ad9361_tx_channel #( + + // parameters + + parameter Q_OR_I_N = 0, + parameter CHANNEL_ID = 32'h0, + parameter DISABLE = 0, + parameter DDS_DISABLE = 0, + parameter USERPORTS_DISABLE = 0, + parameter IQCORRECTION_DISABLE = 0) ( + + // dac interface + + input dac_clk, + input dac_rst, + input dac_valid, + input [15:0] dma_data, + input [11:0] adc_data, + output [11:0] dac_data, + output [11:0] dac_data_out, + input [11:0] dac_data_in, + + // processor interface + + output dac_enable, + input dac_data_sync, + input dac_dds_format, + + // bus interface + + input up_rstn, + input up_clk, + input up_wreq, + input [13:0] up_waddr, + input [31:0] up_wdata, + output up_wack, + input up_rreq, + input [13:0] up_raddr, + output [31:0] up_rdata, + output up_rack); // parameters - parameter CHANNEL_ID = 32'h0; - parameter Q_OR_I_N = 0; - parameter DATAPATH_DISABLE = 0; localparam PRBS_SEL = CHANNEL_ID; localparam PRBS_P09 = 0; localparam PRBS_P11 = 1; localparam PRBS_P15 = 2; localparam PRBS_P20 = 3; - // dac interface - - input dac_clk; - input dac_rst; - input dac_valid; - input [15:0] dma_data; - input [11:0] adc_data; - output [11:0] dac_data; - output [11:0] dac_data_out; - input [11:0] dac_data_in; - - // processor interface - - output dac_enable; - input dac_data_sync; - input dac_dds_format; - - // bus interface - - input up_rstn; - input up_clk; - input up_wreq; - input [13:0] up_waddr; - input [31:0] up_wdata; - output up_wack; - input up_rreq; - input [13:0] up_raddr; - output [31:0] up_rdata; - output up_rack; - // internal registers reg dac_valid_sel = 'd0; - reg dac_enable = 'd0; - reg [11:0] dac_data = 'd0; - reg [11:0] dac_data_out = 'd0; + reg dac_enable_int = 'd0; + reg [11:0] dac_data_int = 'd0; + reg [11:0] dac_data_out_int = 'd0; reg [23:0] dac_pn_seq = 'd0; reg [11:0] dac_pn_data = 'd0; reg [15:0] dac_pat_data = 'd0; @@ -144,6 +118,9 @@ module axi_ad9361_tx_channel ( wire dac_iqcor_enb_s; wire [15:0] dac_iqcor_coeff_1_s; wire [15:0] dac_iqcor_coeff_2_s; + wire up_wack_s; + wire up_rack_s; + wire [31:0] up_rdata_s; // standard prbs functions @@ -273,41 +250,42 @@ module axi_ad9361_tx_channel ( // dac iq correction + assign dac_enable = (DISABLE == 1) ? 'd0 : dac_enable_int; + assign dac_data = (DISABLE == 1) ? 'd0 : dac_data_int; + always @(posedge dac_clk) begin - dac_enable <= (dac_data_sel_s == 4'h2) ? 1'b1 : 1'b0; + dac_enable_int <= (dac_data_sel_s == 4'h2) ? 1'b1 : 1'b0; if (dac_iqcor_valid_s == 1'b1) begin - dac_data <= dac_iqcor_data_s[15:4]; + dac_data_int <= dac_iqcor_data_s[15:4]; end end - generate - if (DATAPATH_DISABLE == 1) begin - assign dac_iqcor_valid_s = dac_valid; - assign dac_iqcor_data_s = {dac_data_out, 4'd0}; - end else begin - ad_iqcor #(.Q_OR_I_N (Q_OR_I_N)) i_ad_iqcor ( + ad_iqcor #( + .Q_OR_I_N (Q_OR_I_N), + .DISABLE (IQCORRECTION_DISABLE)) + i_ad_iqcor ( .clk (dac_clk), .valid (dac_valid), - .data_in ({dac_data_out, 4'd0}), + .data_in ({dac_data_out_int, 4'd0}), .data_iq ({dac_data_in, 4'd0}), .valid_out (dac_iqcor_valid_s), .data_out (dac_iqcor_data_s), .iqcor_enable (dac_iqcor_enb_s), .iqcor_coeff_1 (dac_iqcor_coeff_1_s), .iqcor_coeff_2 (dac_iqcor_coeff_2_s)); - end - endgenerate // dac mux + assign dac_data_out = (DISABLE == 1) ? 'd0 : dac_data_out_int; + always @(posedge dac_clk) begin case (dac_data_sel_s) - 4'h9: dac_data_out <= dac_pn_data; - 4'h8: dac_data_out <= adc_data; - 4'h3: dac_data_out <= 12'd0; - 4'h2: dac_data_out <= dma_data[15:4]; - 4'h1: dac_data_out <= dac_pat_data[15:4]; - default: dac_data_out <= dac_dds_data[15:4]; + 4'h9: dac_data_out_int <= dac_pn_data; + 4'h8: dac_data_out_int <= adc_data; + 4'h3: dac_data_out_int <= 12'd0; + 4'h2: dac_data_out_int <= dma_data[15:4]; + 4'h1: dac_data_out_int <= dac_pat_data[15:4]; + default: dac_data_out_int <= dac_dds_data[15:4]; endcase end @@ -360,11 +338,9 @@ module axi_ad9361_tx_channel ( // dds - generate - if (DATAPATH_DISABLE == 1) begin - assign dac_dds_data_s = 16'd0; - end else begin - ad_dds i_dds ( + ad_dds #( + .DISABLE (DDS_DISABLE)) + i_dds ( .clk (dac_clk), .dds_format (dac_dds_format), .dds_phase_0 (dac_dds_phase_0), @@ -372,12 +348,19 @@ module axi_ad9361_tx_channel ( .dds_phase_1 (dac_dds_phase_1), .dds_scale_1 (dac_dds_scale_2_s), .dds_data (dac_dds_data_s)); - end - endgenerate // single channel processor - up_dac_channel #(.DAC_CHANNEL_ID(CHANNEL_ID)) i_up_dac_channel ( + assign up_wack = (DISABLE == 1) ? 'd0 : up_wack_s; + assign up_rack = (DISABLE == 1) ? 'd0 : up_rack_s; + assign up_rdata = (DISABLE == 1) ? 'd0 : up_rdata_s; + + up_dac_channel #( + .CHANNEL_ID (CHANNEL_ID), + .DDS_DISABLE (DDS_DISABLE), + .USERPORTS_DISABLE (USERPORTS_DISABLE), + .IQCORRECTION_DISABLE (IQCORRECTION_DISABLE)) + i_up_dac_channel ( .dac_clk (dac_clk), .dac_rst (dac_rst), .dac_dds_scale_1 (dac_dds_scale_1_s), @@ -389,6 +372,7 @@ module axi_ad9361_tx_channel ( .dac_pat_data_1 (dac_pat_data_1_s), .dac_pat_data_2 (dac_pat_data_2_s), .dac_data_sel (dac_data_sel_s), + .dac_iq_mode (), .dac_iqcor_enb (dac_iqcor_enb_s), .dac_iqcor_coeff_1 (dac_iqcor_coeff_1_s), .dac_iqcor_coeff_2 (dac_iqcor_coeff_2_s), @@ -411,11 +395,11 @@ module axi_ad9361_tx_channel ( .up_wreq (up_wreq), .up_waddr (up_waddr), .up_wdata (up_wdata), - .up_wack (up_wack), + .up_wack (up_wack_s), .up_rreq (up_rreq), .up_raddr (up_raddr), - .up_rdata (up_rdata), - .up_rack (up_rack)); + .up_rdata (up_rdata_s), + .up_rack (up_rack_s)); endmodule diff --git a/library/axi_ad9361/xilinx/axi_ad9361_cmos_if.v b/library/axi_ad9361/xilinx/axi_ad9361_cmos_if.v new file mode 100644 index 000000000..0ce506d71 --- /dev/null +++ b/library/axi_ad9361/xilinx/axi_ad9361_cmos_if.v @@ -0,0 +1,583 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_ad9361_cmos_if ( + + // physical interface (receive) + + rx_clk_in, + rx_frame_in, + rx_data_in, + + // physical interface (transmit) + + tx_clk_out, + tx_frame_out, + tx_data_out, + + // ensm control + + enable, + txnrx, + + // clock (common to both receive and transmit) + + rst, + clk, + l_clk, + + // receive data path interface + + adc_valid, + adc_data, + adc_status, + adc_r1_mode, + adc_ddr_edgesel, + + // transmit data path interface + + dac_valid, + dac_data, + dac_clksel, + dac_r1_mode, + + // tdd interface + + tdd_enable, + tdd_txnrx, + tdd_mode, + + // delay interface + + mmcm_rst, + up_clk, + up_enable, + up_txnrx, + up_adc_dld, + up_adc_dwdata, + up_adc_drdata, + up_dac_dld, + up_dac_dwdata, + up_dac_drdata, + delay_clk, + delay_rst, + delay_locked); + + // this parameter controls the buffer type based on the target device. + + parameter DEVICE_TYPE = 0; + parameter DAC_IODELAY_ENABLE = 0; + parameter IO_DELAY_GROUP = "dev_if_delay_group"; + + // physical interface (receive) + + input rx_clk_in; + input rx_frame_in; + input [11:0] rx_data_in; + + // physical interface (transmit) + + output tx_clk_out; + output tx_frame_out; + output [11:0] tx_data_out; + + // ensm control + + output enable; + output txnrx; + + // clock (common to both receive and transmit) + + input rst; + input clk; + output l_clk; + + // receive data path interface + + output adc_valid; + output [47:0] adc_data; + output adc_status; + input adc_r1_mode; + input adc_ddr_edgesel; + + // transmit data path interface + + input dac_valid; + input [47:0] dac_data; + input dac_clksel; + input dac_r1_mode; + + // tdd interface + + input tdd_enable; + input tdd_txnrx; + input tdd_mode; + + // delay interface + + input mmcm_rst; + input up_clk; + input up_enable; + input up_txnrx; + input [12:0] up_adc_dld; + input [64:0] up_adc_dwdata; + output [64:0] up_adc_drdata; + input [15:0] up_dac_dld; + input [79:0] up_dac_dwdata; + output [79:0] up_dac_drdata; + input delay_clk; + input delay_rst; + output delay_locked; + + // internal registers + + reg [ 1:0] rx_frame = 0; + reg [11:0] rx_data_p = 0; + reg rx_error_r1 = 'd0; + reg rx_valid_r1 = 'd0; + reg [23:0] rx_data_r1 = 'd0; + reg rx_error_r2 = 'd0; + reg rx_valid_r2 = 'd0; + reg [47:0] rx_data_r2 = 'd0; + reg adc_p_valid = 'd0; + reg [47:0] adc_p_data = 'd0; + reg adc_p_status = 'd0; + reg adc_n_valid = 'd0; + reg [47:0] adc_n_data = 'd0; + reg adc_n_status = 'd0; + reg adc_valid_int = 'd0; + reg [47:0] adc_data_int = 'd0; + reg adc_status_int = 'd0; + reg adc_valid = 'd0; + reg [47:0] adc_data = 'd0; + reg adc_status = 'd0; + reg [ 1:0] tx_data_cnt = 'd0; + reg [47:0] tx_data = 'd0; + reg tx_frame_p = 'd0; + reg tx_frame_n = 'd0; + reg [11:0] tx_data_p = 'd0; + reg [11:0] tx_data_n = 'd0; + reg tx_n_frame_p = 'd0; + reg tx_n_frame_n = 'd0; + reg [11:0] tx_n_data_p = 'd0; + reg [11:0] tx_n_data_n = 'd0; + reg tx_p_frame_p = 'd0; + reg tx_p_frame_n = 'd0; + reg [11:0] tx_p_data_p = 'd0; + reg [11:0] tx_p_data_n = 'd0; + reg up_enable_int = 'd0; + reg up_txnrx_int = 'd0; + reg enable_up_m1 = 'd0; + reg txnrx_up_m1 = 'd0; + reg enable_up = 'd0; + reg txnrx_up = 'd0; + reg enable_int = 'd0; + reg txnrx_int = 'd0; + reg enable_n_int = 'd0; + reg txnrx_n_int = 'd0; + reg enable_p_int = 'd0; + reg txnrx_p_int = 'd0; + reg dac_clkdata_p = 'd0; + reg dac_clkdata_n = 'd0; + reg locked_m1 = 'd0; + reg locked = 'd0; + + // internal signals + + wire [ 1:0] rx_frame_s; + wire [ 3:0] rx_frame_4_s; + wire [ 2:0] tx_data_sel_s; + wire [11:0] rx_data_p_s; + wire [11:0] rx_data_n_s; + wire rx_frame_p_s; + wire rx_frame_n_s; + wire locked_s; + + genvar l_inst; + + // receive data path interface + + assign rx_frame_s = {rx_frame_p_s, rx_frame_n_s}; + assign rx_frame_4_s = {rx_frame_s, rx_frame}; + + always @(posedge l_clk) begin + rx_frame <= rx_frame_s; + rx_data_p <= rx_data_p_s; + end + + // receive data path for single rf, frame is expected to qualify i only + + always @(posedge l_clk) begin + rx_error_r1 <= ~^ rx_frame_s; + rx_valid_r1 <= ^ rx_frame_s; + case (rx_frame_s) + 2'b01: rx_data_r1 <= {rx_data_p_s, rx_data_n_s}; + 2'b10: rx_data_r1 <= {rx_data_n_s, rx_data_p}; + default: rx_data_r1 <= 24'd0; + endcase + end + + // receive data path for dual rf, frame is expected to qualify iq for rf-1 only + + always @(posedge l_clk) begin + rx_error_r2 <= ((rx_frame_4_s == 4'b0011) || (rx_frame_4_s == 4'b1100) || + (rx_frame_4_s == 4'b1001) || (rx_frame_4_s == 4'b0110)) ? 1'b0 : 1'b1; + rx_valid_r2 <= ((rx_frame_4_s == 4'b0011) || + (rx_frame_4_s == 4'b1001)) ? 1'b1 : 1'b0; + case (rx_frame_s) + 2'b11: rx_data_r2[23: 0] <= {rx_data_p_s, rx_data_n_s}; + 2'b01: rx_data_r2[23: 0] <= {rx_data_n_s, rx_data_p}; + default: rx_data_r2[23: 0] <= rx_data_r2[23: 0]; + endcase + case (rx_frame_s) + 2'b00: rx_data_r2[47:24] <= {rx_data_p_s, rx_data_n_s}; + 2'b10: rx_data_r2[47:24] <= {rx_data_n_s, rx_data_p}; + default: rx_data_r2[47:24] <= rx_data_r2[47:24]; + endcase + end + + // receive data path mux + + always @(posedge l_clk) begin + if (adc_r1_mode == 1'b1) begin + adc_p_valid <= rx_valid_r1; + adc_p_data <= {24'd0, rx_data_r1}; + adc_p_status <= ~rx_error_r1; + end else begin + adc_p_valid <= rx_valid_r2; + adc_p_data <= rx_data_r2; + adc_p_status <= ~rx_error_r2; + end + end + + // transfer to a synchronous common clock + + always @(negedge l_clk) begin + adc_n_valid <= adc_p_valid; + adc_n_data <= adc_p_data; + adc_n_status <= adc_p_status; + end + + always @(posedge clk) begin + adc_valid_int <= adc_n_valid; + adc_data_int <= adc_n_data; + adc_status_int <= adc_n_status; + adc_valid <= adc_valid_int; + if (adc_valid_int == 1'b1) begin + adc_data <= adc_data_int; + end + adc_status <= adc_status_int & locked; + end + + // transmit data path mux (reverse of what receive does above) + // the count simply selets the data muxing on the ddr outputs + + assign tx_data_sel_s = {tx_data_cnt[1], dac_r1_mode, tx_data_cnt[0]}; + + always @(posedge clk) begin + if (dac_valid == 1'b1) begin + tx_data_cnt <= 2'b10; + end else if (tx_data_cnt[1] == 1'b1) begin + tx_data_cnt <= tx_data_cnt + 1'b1; + end + if (dac_valid == 1'b1) begin + tx_data <= dac_data; + end + case (tx_data_sel_s) + 3'b101: begin + tx_frame_p <= 1'b0; + tx_frame_n <= 1'b0; + tx_data_p <= tx_data[35:24]; + tx_data_n <= tx_data[47:36]; + end + 3'b100: begin + tx_frame_p <= 1'b1; + tx_frame_n <= 1'b1; + tx_data_p <= tx_data[11: 0]; + tx_data_n <= tx_data[23:12]; + end + 3'b110: begin + tx_frame_p <= 1'b1; + tx_frame_n <= 1'b0; + tx_data_p <= tx_data[11: 0]; + tx_data_n <= tx_data[23:12]; + end + default: begin + tx_frame_p <= 1'd0; + tx_frame_n <= 1'd0; + tx_data_p <= 12'd0; + tx_data_n <= 12'd0; + end + endcase + end + + // transfer data from a synchronous clock (skew less than 2ns) + + always @(negedge clk) begin + tx_n_frame_p <= tx_frame_p; + tx_n_frame_n <= tx_frame_n; + tx_n_data_p <= tx_data_p; + tx_n_data_n <= tx_data_n; + end + + always @(posedge l_clk) begin + tx_p_frame_p <= tx_n_frame_p; + tx_p_frame_n <= tx_n_frame_n; + tx_p_data_p <= tx_n_data_p; + tx_p_data_n <= tx_n_data_n; + end + + // tdd/ensm control + + always @(posedge up_clk) begin + up_enable_int <= up_enable; + up_txnrx_int <= up_txnrx; + end + + always @(posedge clk or posedge rst) begin + if (rst == 1'b1) begin + enable_up_m1 <= 1'b0; + txnrx_up_m1 <= 1'b0; + enable_up <= 1'b0; + txnrx_up <= 1'b0; + end else begin + enable_up_m1 <= up_enable_int; + txnrx_up_m1 <= up_txnrx_int; + enable_up <= enable_up_m1; + txnrx_up <= txnrx_up_m1; + end + end + + always @(posedge clk) begin + if (tdd_mode == 1'b1) begin + enable_int <= tdd_enable; + txnrx_int <= tdd_txnrx; + end else begin + enable_int <= enable_up; + txnrx_int <= txnrx_up; + end + end + + always @(negedge clk) begin + enable_n_int <= enable_int; + txnrx_n_int <= txnrx_int; + end + + always @(posedge l_clk) begin + enable_p_int <= enable_n_int; + txnrx_p_int <= txnrx_n_int; + end + + always @(posedge l_clk) begin + dac_clkdata_p <= dac_clksel; + dac_clkdata_n <= ~dac_clksel; + end + + // receive data interface, ibuf -> idelay -> iddr + + generate + for (l_inst = 0; l_inst <= 11; l_inst = l_inst + 1) begin: g_rx_data + ad_cmos_in #( + .SINGLE_ENDED (1), + .DEVICE_TYPE (DEVICE_TYPE), + .IODELAY_CTRL (0), + .IODELAY_GROUP (IO_DELAY_GROUP)) + i_rx_data ( + .rx_clk (l_clk), + .rx_data_in (rx_data_in[l_inst]), + .rx_data_p (rx_data_p_s[l_inst]), + .rx_data_n (rx_data_n_s[l_inst]), + .up_clk (up_clk), + .up_dld (up_adc_dld[l_inst]), + .up_dwdata (up_adc_dwdata[((l_inst*5)+4):(l_inst*5)]), + .up_drdata (up_adc_drdata[((l_inst*5)+4):(l_inst*5)]), + .delay_clk (delay_clk), + .delay_rst (delay_rst), + .delay_locked ()); + end + endgenerate + + // receive frame interface, ibuf -> idelay -> iddr + + ad_cmos_in #( + .SINGLE_ENDED (1), + .DEVICE_TYPE (DEVICE_TYPE), + .IODELAY_CTRL (1), + .IODELAY_GROUP (IO_DELAY_GROUP)) + i_rx_frame ( + .rx_clk (l_clk), + .rx_data_in (rx_frame_in), + .rx_data_p (rx_frame_p_s), + .rx_data_n (rx_frame_n_s), + .up_clk (up_clk), + .up_dld (up_adc_dld[12]), + .up_dwdata (up_adc_dwdata[64:60]), + .up_drdata (up_adc_drdata[64:60]), + .delay_clk (delay_clk), + .delay_rst (delay_rst), + .delay_locked (delay_locked)); + + // transmit data interface, oddr -> obuf + + generate + for (l_inst = 0; l_inst <= 11; l_inst = l_inst + 1) begin: g_tx_data + ad_cmos_out #( + .DEVICE_TYPE (DEVICE_TYPE), + .SINGLE_ENDED (1), + .IODELAY_ENABLE (DAC_IODELAY_ENABLE), + .IODELAY_CTRL (0), + .IODELAY_GROUP (IO_DELAY_GROUP)) + i_tx_data ( + .tx_clk (l_clk), + .tx_data_p (tx_p_data_p[l_inst]), + .tx_data_n (tx_p_data_n[l_inst]), + .tx_data_out (tx_data_out[l_inst]), + .up_clk (up_clk), + .up_dld (up_dac_dld[l_inst]), + .up_dwdata (up_dac_dwdata[((l_inst*5)+4):(l_inst*5)]), + .up_drdata (up_dac_drdata[((l_inst*5)+4):(l_inst*5)]), + .delay_clk (delay_clk), + .delay_rst (delay_rst), + .delay_locked ()); + end + endgenerate + + // transmit frame interface, oddr -> obuf + + ad_cmos_out #( + .DEVICE_TYPE (DEVICE_TYPE), + .SINGLE_ENDED (1), + .IODELAY_ENABLE (DAC_IODELAY_ENABLE), + .IODELAY_CTRL (0), + .IODELAY_GROUP (IO_DELAY_GROUP)) + i_tx_frame ( + .tx_clk (l_clk), + .tx_data_p (tx_p_frame_p), + .tx_data_n (tx_p_frame_n), + .tx_data_out (tx_frame_out), + .up_clk (up_clk), + .up_dld (up_dac_dld[12]), + .up_dwdata (up_dac_dwdata[64:60]), + .up_drdata (up_dac_drdata[64:60]), + .delay_clk (delay_clk), + .delay_rst (delay_rst), + .delay_locked ()); + + // transmit clock interface, oddr -> obuf + + ad_cmos_out #( + .DEVICE_TYPE (DEVICE_TYPE), + .SINGLE_ENDED (1), + .IODELAY_ENABLE (DAC_IODELAY_ENABLE), + .IODELAY_CTRL (0), + .IODELAY_GROUP (IO_DELAY_GROUP)) + i_tx_clk ( + .tx_clk (l_clk), + .tx_data_p (dac_clkdata_p), + .tx_data_n (dac_clkdata_n), + .tx_data_out (tx_clk_out), + .up_clk (up_clk), + .up_dld (up_dac_dld[13]), + .up_dwdata (up_dac_dwdata[69:65]), + .up_drdata (up_dac_drdata[69:65]), + .delay_clk (delay_clk), + .delay_rst (delay_rst), + .delay_locked ()); + + // enable, oddr -> obuf + + ad_cmos_out #( + .DEVICE_TYPE (DEVICE_TYPE), + .SINGLE_ENDED (1), + .IODELAY_ENABLE (DAC_IODELAY_ENABLE), + .IODELAY_CTRL (0), + .IODELAY_GROUP (IO_DELAY_GROUP)) + i_enable ( + .tx_clk (l_clk), + .tx_data_p (enable_p_int), + .tx_data_n (enable_p_int), + .tx_data_out (enable), + .up_clk (up_clk), + .up_dld (up_dac_dld[14]), + .up_dwdata (up_dac_dwdata[74:70]), + .up_drdata (up_dac_drdata[74:70]), + .delay_clk (delay_clk), + .delay_rst (delay_rst), + .delay_locked ()); + + // txnrx, oddr -> obuf + + ad_cmos_out #( + .DEVICE_TYPE (DEVICE_TYPE), + .SINGLE_ENDED (1), + .IODELAY_ENABLE (DAC_IODELAY_ENABLE), + .IODELAY_CTRL (0), + .IODELAY_GROUP (IO_DELAY_GROUP)) + i_txnrx ( + .tx_clk (l_clk), + .tx_data_p (txnrx_p_int), + .tx_data_n (txnrx_p_int), + .tx_data_out (txnrx), + .up_clk (up_clk), + .up_dld (up_dac_dld[15]), + .up_dwdata (up_dac_dwdata[79:75]), + .up_drdata (up_dac_drdata[79:75]), + .delay_clk (delay_clk), + .delay_rst (delay_rst), + .delay_locked ()); + + // device clock interface (receive clock) + + always @(posedge clk) begin + locked_m1 <= locked_s; + locked <= locked_m1; + end + + ad_cmos_clk #( + .DEVICE_TYPE (DEVICE_TYPE)) + i_clk ( + .rst (mmcm_rst), + .locked (locked_s), + .clk_in (rx_clk_in), + .clk (l_clk)); + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/library/axi_ad9361/axi_ad9361_dev_if.v b/library/axi_ad9361/xilinx/axi_ad9361_lvds_if.v similarity index 92% rename from library/axi_ad9361/axi_ad9361_dev_if.v rename to library/axi_ad9361/xilinx/axi_ad9361_lvds_if.v index d5b416fc9..77a974b5e 100644 --- a/library/axi_ad9361/axi_ad9361_dev_if.v +++ b/library/axi_ad9361/xilinx/axi_ad9361_lvds_if.v @@ -1,9 +1,9 @@ // *************************************************************************** // *************************************************************************** // Copyright 2011(c) Analog Devices, Inc. -// +// // All rights reserved. -// +// // Redistribution and use in source and binary forms, with or without modification, // are permitted provided that the following conditions are met: // - Redistributions of source code must retain the above copyright @@ -21,25 +21,23 @@ // patent holders to use this software. // - Use of the software either in source or binary form, must be run // on or directly connected to an Analog Devices Inc. component. -// +// // THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, // INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A // PARTICULAR PURPOSE ARE DISCLAIMED. // // IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, // EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY -// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR // BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // *************************************************************************** // *************************************************************************** -// This interface includes both the transmit and receive components - -// They both uses the same clock (sourced from the receiving side). `timescale 1ns/100ps -module axi_ad9361_dev_if ( +module axi_ad9361_lvds_if ( // physical interface (receive) @@ -82,6 +80,7 @@ module axi_ad9361_dev_if ( dac_valid, dac_data, + dac_clksel, dac_r1_mode, // tdd interface @@ -92,6 +91,7 @@ module axi_ad9361_dev_if ( // delay interface + mmcm_rst, up_clk, up_enable, up_txnrx, @@ -103,7 +103,17 @@ module axi_ad9361_dev_if ( up_dac_drdata, delay_clk, delay_rst, - delay_locked); + delay_locked, + + //drp interface + + up_drp_sel, + up_drp_wr, + up_drp_addr, + up_drp_wdata, + up_drp_rdata, + up_drp_ready, + up_drp_locked); // this parameter controls the buffer type based on the target device. @@ -152,6 +162,7 @@ module axi_ad9361_dev_if ( input dac_valid; input [47:0] dac_data; + input dac_clksel; input dac_r1_mode; // tdd interface @@ -162,6 +173,7 @@ module axi_ad9361_dev_if ( // delay interface + input mmcm_rst; input up_clk; input up_enable; input up_txnrx; @@ -175,6 +187,16 @@ module axi_ad9361_dev_if ( input delay_rst; output delay_locked; + //drp interface + + input up_drp_sel; + input up_drp_wr; + input [11:0] up_drp_addr; + input [31:0] up_drp_wdata; + output [31:0] up_drp_rdata; + output up_drp_ready; + output up_drp_locked; + // internal registers reg [ 5:0] rx_data_p = 0; @@ -227,6 +249,10 @@ module axi_ad9361_dev_if ( reg txnrx_n_int = 'd0; reg enable_p_int = 'd0; reg txnrx_p_int = 'd0; + reg dac_clkdata_p = 'd0; + reg dac_clkdata_n = 'd0; + reg locked_m1 = 'd0; + reg locked = 'd0; // internal signals @@ -237,6 +263,13 @@ module axi_ad9361_dev_if ( wire [ 5:0] rx_data_n_s; wire rx_frame_p_s; wire rx_frame_n_s; + wire locked_s; + + // drp interface signals + + assign up_drp_rdata = 32'd0; + assign up_drp_ready = 1'd0; + assign up_drp_locked = 1'd1; genvar l_inst; @@ -328,7 +361,7 @@ module axi_ad9361_dev_if ( if (adc_valid_int == 1'b1) begin adc_data <= adc_data_int; end - adc_status <= adc_status_int; + adc_status <= adc_status_int & locked; end // transmit data path mux (reverse of what receive does above) @@ -449,6 +482,11 @@ module axi_ad9361_dev_if ( txnrx_p_int <= txnrx_n_int; end + always @(posedge l_clk) begin + dac_clkdata_p <= dac_clksel; + dac_clkdata_n <= ~dac_clksel; + end + // receive data interface, ibuf -> idelay -> iddr generate @@ -551,8 +589,8 @@ module axi_ad9361_dev_if ( .IODELAY_GROUP (IO_DELAY_GROUP)) i_tx_clk ( .tx_clk (l_clk), - .tx_data_p (1'b0), - .tx_data_n (1'b1), + .tx_data_p (dac_clkdata_p), + .tx_data_n (dac_clkdata_n), .tx_data_out_p (tx_clk_out_p), .tx_data_out_n (tx_clk_out_n), .up_clk (up_clk), @@ -565,7 +603,7 @@ module axi_ad9361_dev_if ( // enable, oddr -> obuf - ad_lvds_out #( + ad_cmos_out #( .DEVICE_TYPE (DEVICE_TYPE), .SINGLE_ENDED (1), .IODELAY_ENABLE (DAC_IODELAY_ENABLE), @@ -575,8 +613,7 @@ module axi_ad9361_dev_if ( .tx_clk (l_clk), .tx_data_p (enable_p_int), .tx_data_n (enable_p_int), - .tx_data_out_p (enable), - .tx_data_out_n (), + .tx_data_out (enable), .up_clk (up_clk), .up_dld (up_dac_dld[8]), .up_dwdata (up_dac_dwdata[44:40]), @@ -587,7 +624,7 @@ module axi_ad9361_dev_if ( // txnrx, oddr -> obuf - ad_lvds_out #( + ad_cmos_out #( .DEVICE_TYPE (DEVICE_TYPE), .SINGLE_ENDED (1), .IODELAY_ENABLE (DAC_IODELAY_ENABLE), @@ -597,8 +634,7 @@ module axi_ad9361_dev_if ( .tx_clk (l_clk), .tx_data_p (txnrx_p_int), .tx_data_n (txnrx_p_int), - .tx_data_out_p (txnrx), - .tx_data_out_n (), + .tx_data_out (txnrx), .up_clk (up_clk), .up_dld (up_dac_dld[9]), .up_dwdata (up_dac_dwdata[49:45]), @@ -609,9 +645,16 @@ module axi_ad9361_dev_if ( // device clock interface (receive clock) + always @(posedge clk) begin + locked_m1 <= locked_s; + locked <= locked_m1; + end + ad_lvds_clk #( .DEVICE_TYPE (DEVICE_TYPE)) i_clk ( + .rst (mmcm_rst), + .locked (locked_s), .clk_in_p (rx_clk_in_p), .clk_in_n (rx_clk_in_n), .clk (l_clk)); diff --git a/library/axi_ad9371/Makefile b/library/axi_ad9371/Makefile new file mode 100644 index 000000000..1b512eb5a --- /dev/null +++ b/library/axi_ad9371/Makefile @@ -0,0 +1,70 @@ +#################################################################################### +#################################################################################### +## Copyright 2011(c) Analog Devices, Inc. +## Auto-generated, do not modify! +#################################################################################### +#################################################################################### + +M_DEPS += ../common/ad_axi_ip_constr.xdc +M_DEPS += ../common/ad_datafmt.v +M_DEPS += ../common/ad_dcfilter.v +M_DEPS += ../common/ad_dds.v +M_DEPS += ../common/ad_dds_1.v +M_DEPS += ../common/ad_dds_sine.v +M_DEPS += ../common/ad_iqcor.v +M_DEPS += ../common/ad_rst.v +M_DEPS += ../common/ad_xcvr_rx_if.v +M_DEPS += ../common/up_adc_channel.v +M_DEPS += ../common/up_adc_common.v +M_DEPS += ../common/up_axi.v +M_DEPS += ../common/up_clock_mon.v +M_DEPS += ../common/up_dac_channel.v +M_DEPS += ../common/up_dac_common.v +M_DEPS += ../common/up_xfer_cntrl.v +M_DEPS += ../common/up_xfer_status.v +M_DEPS += ../scripts/adi_env.tcl +M_DEPS += ../scripts/adi_ip.tcl +M_DEPS += ../xilinx/common/ad_mul.v +M_DEPS += axi_ad9371.v +M_DEPS += axi_ad9371_if.v +M_DEPS += axi_ad9371_ip.tcl +M_DEPS += axi_ad9371_rx.v +M_DEPS += axi_ad9371_rx_channel.v +M_DEPS += axi_ad9371_rx_os.v +M_DEPS += axi_ad9371_tx.v +M_DEPS += axi_ad9371_tx_channel.v + +M_VIVADO := vivado -mode batch -source + +M_FLIST := *.cache +M_FLIST += *.data +M_FLIST += *.xpr +M_FLIST += *.log +M_FLIST += component.xml +M_FLIST += *.jou +M_FLIST += xgui +M_FLIST += *.ip_user_files +M_FLIST += *.srcs +M_FLIST += *.hw +M_FLIST += *.sim +M_FLIST += .Xil + + + +.PHONY: all clean clean-all +all: axi_ad9371.xpr + + +clean:clean-all + + +clean-all: + rm -rf $(M_FLIST) + + +axi_ad9371.xpr: $(M_DEPS) + -rm -rf $(M_FLIST) + $(M_VIVADO) axi_ad9371_ip.tcl >> axi_ad9371_ip.log 2>&1 + +#################################################################################### +#################################################################################### diff --git a/library/axi_ad9371/axi_ad9371.v b/library/axi_ad9371/axi_ad9371.v new file mode 100644 index 000000000..2d82d45c8 --- /dev/null +++ b/library/axi_ad9371/axi_ad9371.v @@ -0,0 +1,428 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_ad9371 ( + + // receive + + adc_clk, + adc_rx_valid, + adc_rx_sof, + adc_rx_data, + adc_rx_ready, + adc_os_clk, + adc_rx_os_valid, + adc_rx_os_sof, + adc_rx_os_data, + adc_rx_os_ready, + + // transmit + + dac_clk, + dac_tx_valid, + dac_tx_data, + dac_tx_ready, + + // master/slave + + dac_sync_in, + dac_sync_out, + + // dma interface + + adc_enable_i0, + adc_valid_i0, + adc_data_i0, + adc_enable_q0, + adc_valid_q0, + adc_data_q0, + adc_enable_i1, + adc_valid_i1, + adc_data_i1, + adc_enable_q1, + adc_valid_q1, + adc_data_q1, + adc_dovf, + adc_dunf, + + adc_os_enable_i0, + adc_os_valid_i0, + adc_os_data_i0, + adc_os_enable_q0, + adc_os_valid_q0, + adc_os_data_q0, + adc_os_dovf, + adc_os_dunf, + + dac_enable_i0, + dac_valid_i0, + dac_data_i0, + dac_enable_q0, + dac_valid_q0, + dac_data_q0, + dac_enable_i1, + dac_valid_i1, + dac_data_i1, + dac_enable_q1, + dac_valid_q1, + dac_data_q1, + dac_dovf, + dac_dunf, + + // axi interface + + s_axi_aclk, + s_axi_aresetn, + s_axi_awvalid, + s_axi_awaddr, + s_axi_awprot, + s_axi_awready, + s_axi_wvalid, + s_axi_wdata, + s_axi_wstrb, + s_axi_wready, + s_axi_bvalid, + s_axi_bresp, + s_axi_bready, + s_axi_arvalid, + s_axi_araddr, + s_axi_arprot, + s_axi_arready, + s_axi_rvalid, + s_axi_rdata, + s_axi_rresp, + s_axi_rready); + + // parameters + + parameter ID = 0; + parameter DEVICE_TYPE = 0; + parameter DAC_DATAPATH_DISABLE = 0; + parameter ADC_DATAPATH_DISABLE = 0; + + // receive + + input adc_clk; + input adc_rx_valid; + input [ 3:0] adc_rx_sof; + input [ 63:0] adc_rx_data; + output adc_rx_ready; + input adc_os_clk; + input adc_rx_os_valid; + input [ 3:0] adc_rx_os_sof; + input [ 63:0] adc_rx_os_data; + output adc_rx_os_ready; + + // transmit + + input dac_clk; + output dac_tx_valid; + output [127:0] dac_tx_data; + input dac_tx_ready; + + // master/slave + + input dac_sync_in; + output dac_sync_out; + + // dma interface + + output adc_enable_i0; + output adc_valid_i0; + output [ 15:0] adc_data_i0; + output adc_enable_q0; + output adc_valid_q0; + output [ 15:0] adc_data_q0; + output adc_enable_i1; + output adc_valid_i1; + output [ 15:0] adc_data_i1; + output adc_enable_q1; + output adc_valid_q1; + output [ 15:0] adc_data_q1; + input adc_dovf; + input adc_dunf; + + output adc_os_enable_i0; + output adc_os_valid_i0; + output [ 31:0] adc_os_data_i0; + output adc_os_enable_q0; + output adc_os_valid_q0; + output [ 31:0] adc_os_data_q0; + input adc_os_dovf; + input adc_os_dunf; + + output dac_enable_i0; + output dac_valid_i0; + input [ 31:0] dac_data_i0; + output dac_enable_q0; + output dac_valid_q0; + input [ 31:0] dac_data_q0; + output dac_enable_i1; + output dac_valid_i1; + input [ 31:0] dac_data_i1; + output dac_enable_q1; + output dac_valid_q1; + input [ 31:0] dac_data_q1; + input dac_dovf; + input dac_dunf; + + // axi interface + + input s_axi_aclk; + input s_axi_aresetn; + input s_axi_awvalid; + input [ 31:0] s_axi_awaddr; + input [ 2:0] s_axi_awprot; + output s_axi_awready; + input s_axi_wvalid; + input [ 31:0] s_axi_wdata; + input [ 3:0] s_axi_wstrb; + output s_axi_wready; + output s_axi_bvalid; + output [ 1:0] s_axi_bresp; + input s_axi_bready; + input s_axi_arvalid; + input [ 31:0] s_axi_araddr; + input [ 2:0] s_axi_arprot; + output s_axi_arready; + output s_axi_rvalid; + output [ 31:0] s_axi_rdata; + output [ 1:0] s_axi_rresp; + input s_axi_rready; + + // internal registers + + reg up_wack = 'd0; + reg up_rack = 'd0; + reg [ 31:0] up_rdata = 'd0; + + // internal signals + + wire up_clk; + wire up_rstn; + wire [ 63:0] adc_data_s; + wire adc_os_valid_s; + wire [ 63:0] adc_os_data_s; + wire [127:0] dac_data_s; + wire up_wreq_s; + wire [ 13:0] up_waddr_s; + wire [ 31:0] up_wdata_s; + wire [ 2:0] up_wack_s; + wire up_rreq_s; + wire [ 13:0] up_raddr_s; + wire [ 31:0] up_rdata_s[0:2]; + wire [ 2:0] up_rack_s; + + // signal name changes + + assign up_clk = s_axi_aclk; + assign up_rstn = s_axi_aresetn; + + // defaults + + assign dac_tx_valid = 1'b1; + assign adc_rx_ready = 1'b1; + assign adc_rx_os_ready = 1'b1; + + // processor read interface + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_wack <= 'd0; + up_rack <= 'd0; + up_rdata <= 'd0; + end else begin + up_wack <= | up_wack_s; + up_rack <= | up_rack_s; + up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2]; + end + end + + // device interface + + axi_ad9371_if #( + .DEVICE_TYPE (DEVICE_TYPE)) + i_if ( + .adc_clk (adc_clk), + .adc_rx_sof (adc_rx_sof), + .adc_rx_data (adc_rx_data), + .adc_os_clk (adc_os_clk), + .adc_rx_os_sof (adc_rx_os_sof), + .adc_rx_os_data (adc_rx_os_data), + .adc_data (adc_data_s), + .adc_os_valid (adc_os_valid_s), + .adc_os_data (adc_os_data_s), + .dac_clk (dac_clk), + .dac_tx_data (dac_tx_data), + .dac_data (dac_data_s)); + + // receive + + axi_ad9371_rx #( + .ID (ID), + .DATAPATH_DISABLE (ADC_DATAPATH_DISABLE)) + i_rx ( + .adc_rst (adc_rst), + .adc_clk (adc_clk), + .adc_data (adc_data_s), + .adc_enable_i0 (adc_enable_i0), + .adc_valid_i0 (adc_valid_i0), + .adc_data_i0 (adc_data_i0), + .adc_enable_q0 (adc_enable_q0), + .adc_valid_q0 (adc_valid_q0), + .adc_data_q0 (adc_data_q0), + .adc_enable_i1 (adc_enable_i1), + .adc_valid_i1 (adc_valid_i1), + .adc_data_i1 (adc_data_i1), + .adc_enable_q1 (adc_enable_q1), + .adc_valid_q1 (adc_valid_q1), + .adc_data_q1 (adc_data_q1), + .adc_dovf (adc_dovf), + .adc_dunf (adc_dunf), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack_s[0]), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata_s[0]), + .up_rack (up_rack_s[0])); + + // receive (o/s) + + axi_ad9371_rx_os #( + .ID (ID), + .DATAPATH_DISABLE (ADC_DATAPATH_DISABLE)) + i_rx_os ( + .adc_os_rst (adc_os_rst), + .adc_os_clk (adc_os_clk), + .adc_os_valid (adc_os_valid_s), + .adc_os_data (adc_os_data_s), + .adc_os_enable_i0 (adc_os_enable_i0), + .adc_os_valid_i0 (adc_os_valid_i0), + .adc_os_data_i0 (adc_os_data_i0), + .adc_os_enable_q0 (adc_os_enable_q0), + .adc_os_valid_q0 (adc_os_valid_q0), + .adc_os_data_q0 (adc_os_data_q0), + .adc_os_dovf (adc_os_dovf), + .adc_os_dunf (adc_os_dunf), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack_s[1]), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata_s[1]), + .up_rack (up_rack_s[1])); + + // transmit + + axi_ad9371_tx #( + .ID (ID), + .DATAPATH_DISABLE (DAC_DATAPATH_DISABLE)) + i_tx ( + .dac_rst (dac_rst), + .dac_clk (dac_clk), + .dac_data (dac_data_s), + .dac_sync_in (dac_sync_in), + .dac_sync_out (dac_sync_out), + .dac_enable_i0 (dac_enable_i0), + .dac_valid_i0 (dac_valid_i0), + .dac_data_i0 (dac_data_i0), + .dac_enable_q0 (dac_enable_q0), + .dac_valid_q0 (dac_valid_q0), + .dac_data_q0 (dac_data_q0), + .dac_enable_i1 (dac_enable_i1), + .dac_valid_i1 (dac_valid_i1), + .dac_data_i1 (dac_data_i1), + .dac_enable_q1 (dac_enable_q1), + .dac_valid_q1 (dac_valid_q1), + .dac_data_q1 (dac_data_q1), + .dac_dovf(dac_dovf), + .dac_dunf(dac_dunf), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack_s[2]), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata_s[2]), + .up_rack (up_rack_s[2])); + + // axi interface + + up_axi i_up_axi ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_axi_awvalid (s_axi_awvalid), + .up_axi_awaddr (s_axi_awaddr), + .up_axi_awready (s_axi_awready), + .up_axi_wvalid (s_axi_wvalid), + .up_axi_wdata (s_axi_wdata), + .up_axi_wstrb (s_axi_wstrb), + .up_axi_wready (s_axi_wready), + .up_axi_bvalid (s_axi_bvalid), + .up_axi_bresp (s_axi_bresp), + .up_axi_bready (s_axi_bready), + .up_axi_arvalid (s_axi_arvalid), + .up_axi_araddr (s_axi_araddr), + .up_axi_arready (s_axi_arready), + .up_axi_rvalid (s_axi_rvalid), + .up_axi_rresp (s_axi_rresp), + .up_axi_rdata (s_axi_rdata), + .up_axi_rready (s_axi_rready), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata), + .up_rack (up_rack)); + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/library/axi_ad9371/axi_ad9371_hw.tcl b/library/axi_ad9371/axi_ad9371_hw.tcl new file mode 100755 index 000000000..cf1e4ca6b --- /dev/null +++ b/library/axi_ad9371/axi_ad9371_hw.tcl @@ -0,0 +1,232 @@ + + +package require -exact qsys 13.0 +source ../scripts/adi_env.tcl +source ../scripts/adi_ip_alt.tcl + +set_module_property NAME axi_ad9371 +set_module_property DESCRIPTION "AXI AD9371 Interface" +set_module_property VERSION 1.0 +set_module_property GROUP "Analog Devices" +set_module_property DISPLAY_NAME axi_ad9371 + +# files + +add_fileset quartus_synth QUARTUS_SYNTH "" "Quartus Synthesis" +set_fileset_property quartus_synth TOP_LEVEL axi_ad9371 +add_fileset_file ad_rst.v VERILOG PATH $ad_hdl_dir/library/common/ad_rst.v +add_fileset_file ad_mul.v VERILOG PATH $ad_hdl_dir/library/altera/common/ad_mul.v +add_fileset_file ad_dds_sine.v VERILOG PATH $ad_hdl_dir/library/common/ad_dds_sine.v +add_fileset_file ad_dds_1.v VERILOG PATH $ad_hdl_dir/library/common/ad_dds_1.v +add_fileset_file ad_dds.v VERILOG PATH $ad_hdl_dir/library/common/ad_dds.v +add_fileset_file ad_datafmt.v VERILOG PATH $ad_hdl_dir/library/common/ad_datafmt.v +add_fileset_file ad_dcfilter.v VERILOG PATH $ad_hdl_dir/library/altera/common/ad_dcfilter.v +add_fileset_file ad_iqcor.v VERILOG PATH $ad_hdl_dir/library/common/ad_iqcor.v +add_fileset_file up_axi.v VERILOG PATH $ad_hdl_dir/library/common/up_axi.v +add_fileset_file up_xfer_cntrl.v VERILOG PATH $ad_hdl_dir/library/common/up_xfer_cntrl.v +add_fileset_file up_xfer_status.v VERILOG PATH $ad_hdl_dir/library/common/up_xfer_status.v +add_fileset_file up_clock_mon.v VERILOG PATH $ad_hdl_dir/library/common/up_clock_mon.v +add_fileset_file up_adc_common.v VERILOG PATH $ad_hdl_dir/library/common/up_adc_common.v +add_fileset_file up_adc_channel.v VERILOG PATH $ad_hdl_dir/library/common/up_adc_channel.v +add_fileset_file up_dac_common.v VERILOG PATH $ad_hdl_dir/library/common/up_dac_common.v +add_fileset_file up_dac_channel.v VERILOG PATH $ad_hdl_dir/library/common/up_dac_channel.v +add_fileset_file ad_xcvr_rx_if.v VERILOG PATH $ad_hdl_dir/library/common/ad_xcvr_rx_if.v +add_fileset_file axi_ad9371_if.v VERILOG PATH axi_ad9371_if.v +add_fileset_file axi_ad9371_rx_channel.v VERILOG PATH axi_ad9371_rx_channel.v +add_fileset_file axi_ad9371_rx.v VERILOG PATH axi_ad9371_rx.v +add_fileset_file axi_ad9371_rx_os.v VERILOG PATH axi_ad9371_rx_os.v +add_fileset_file axi_ad9371_tx_channel.v VERILOG PATH axi_ad9371_tx_channel.v +add_fileset_file axi_ad9371_tx.v VERILOG PATH axi_ad9371_tx.v +add_fileset_file axi_ad9371.v VERILOG PATH axi_ad9371.v TOP_LEVEL_FILE +add_fileset_file ad_axi_ip_constr.sdc SDC PATH $ad_hdl_dir/library/common/ad_axi_ip_constr.sdc + +# parameters + +add_parameter ID INTEGER 0 +set_parameter_property ID DEFAULT_VALUE 0 +set_parameter_property ID DISPLAY_NAME ID +set_parameter_property ID TYPE INTEGER +set_parameter_property ID UNITS None +set_parameter_property ID HDL_PARAMETER true + +add_parameter DEVICE_TYPE INTEGER 0 +set_parameter_property DEVICE_TYPE DEFAULT_VALUE 1 +set_parameter_property DEVICE_TYPE DISPLAY_NAME DEVICE_TYPE +set_parameter_property DEVICE_TYPE TYPE INTEGER +set_parameter_property DEVICE_TYPE UNITS None +set_parameter_property DEVICE_TYPE HDL_PARAMETER true + +add_parameter DAC_DATAPATH_DISABLE INTEGER 0 +set_parameter_property DAC_DATAPATH_DISABLE DEFAULT_VALUE 0 +set_parameter_property DAC_DATAPATH_DISABLE DISPLAY_NAME DAC_DATAPATH_DISABLE +set_parameter_property DAC_DATAPATH_DISABLE TYPE INTEGER +set_parameter_property DAC_DATAPATH_DISABLE UNITS None +set_parameter_property DAC_DATAPATH_DISABLE HDL_PARAMETER true + +add_parameter ADC_DATAPATH_DISABLE INTEGER 0 +set_parameter_property ADC_DATAPATH_DISABLE DEFAULT_VALUE 0 +set_parameter_property ADC_DATAPATH_DISABLE DISPLAY_NAME ADC_DATAPATH_DISABLE +set_parameter_property ADC_DATAPATH_DISABLE TYPE INTEGER +set_parameter_property ADC_DATAPATH_DISABLE UNITS None +set_parameter_property ADC_DATAPATH_DISABLE HDL_PARAMETER true + +# axi4 slave + +add_interface s_axi_clock clock end +add_interface_port s_axi_clock s_axi_aclk clk Input 1 + +add_interface s_axi_reset reset end +set_interface_property s_axi_reset associatedClock s_axi_clock +add_interface_port s_axi_reset s_axi_aresetn reset_n Input 1 + +add_interface s_axi axi4lite end +set_interface_property s_axi associatedClock s_axi_clock +set_interface_property s_axi associatedReset s_axi_reset +add_interface_port s_axi s_axi_awvalid awvalid Input 1 +add_interface_port s_axi s_axi_awaddr awaddr Input 16 +add_interface_port s_axi s_axi_awprot awprot Input 3 +add_interface_port s_axi s_axi_awready awready Output 1 +add_interface_port s_axi s_axi_wvalid wvalid Input 1 +add_interface_port s_axi s_axi_wdata wdata Input 32 +add_interface_port s_axi s_axi_wstrb wstrb Input 4 +add_interface_port s_axi s_axi_wready wready Output 1 +add_interface_port s_axi s_axi_bvalid bvalid Output 1 +add_interface_port s_axi s_axi_bresp bresp Output 2 +add_interface_port s_axi s_axi_bready bready Input 1 +add_interface_port s_axi s_axi_arvalid arvalid Input 1 +add_interface_port s_axi s_axi_araddr araddr Input 16 +add_interface_port s_axi s_axi_arprot arprot Input 3 +add_interface_port s_axi s_axi_arready arready Output 1 +add_interface_port s_axi s_axi_rvalid rvalid Output 1 +add_interface_port s_axi s_axi_rresp rresp Output 2 +add_interface_port s_axi s_axi_rdata rdata Output 32 +add_interface_port s_axi s_axi_rready rready Input 1 + +# transceiver interface + +ad_alt_intf clock adc_clk input 1 +ad_alt_intf signal adc_rx_sof input 4 export +add_interface if_adc_rx_data avalon_streaming sink +add_interface_port if_adc_rx_data adc_rx_data data input 64 +add_interface_port if_adc_rx_data adc_rx_valid valid input 1 +add_interface_port if_adc_rx_data adc_rx_ready ready output 1 +set_interface_property if_adc_rx_data associatedClock if_adc_clk +set_interface_property if_adc_rx_data dataBitsPerSymbol 64 + +ad_alt_intf clock adc_os_clk input 1 +ad_alt_intf signal adc_rx_os_sof input 4 export +add_interface if_adc_rx_os_data avalon_streaming sink +add_interface_port if_adc_rx_os_data adc_rx_os_data data input 64 +add_interface_port if_adc_rx_os_data adc_rx_os_valid valid input 1 +add_interface_port if_adc_rx_os_data adc_rx_os_ready ready output 1 +set_interface_property if_adc_rx_os_data associatedClock if_adc_os_clk +set_interface_property if_adc_rx_os_data dataBitsPerSymbol 64 + +ad_alt_intf clock dac_clk input 1 +add_interface if_dac_tx_data avalon_streaming source +add_interface_port if_dac_tx_data dac_tx_data data output 128 +add_interface_port if_dac_tx_data dac_tx_valid valid output 1 +add_interface_port if_dac_tx_data dac_tx_ready ready input 1 +set_interface_property if_dac_tx_data associatedClock if_dac_clk +set_interface_property if_dac_tx_data dataBitsPerSymbol 128 + +# master/slave + +ad_alt_intf signal dac_sync_in input 1 +ad_alt_intf signal dac_sync_out output 1 + +# adc-channel interface + +add_interface adc_ch_0 conduit end +add_interface_port adc_ch_0 adc_enable_i0 enable Output 1 +add_interface_port adc_ch_0 adc_valid_i0 valid Output 1 +add_interface_port adc_ch_0 adc_data_i0 data Output 16 + +set_interface_property adc_ch_0 associatedClock if_adc_clk +set_interface_property adc_ch_0 associatedReset none + +add_interface adc_ch_1 conduit end +add_interface_port adc_ch_1 adc_enable_q0 enable Output 1 +add_interface_port adc_ch_1 adc_valid_q0 valid Output 1 +add_interface_port adc_ch_1 adc_data_q0 data Output 16 + +set_interface_property adc_ch_1 associatedClock if_adc_clk +set_interface_property adc_ch_1 associatedReset none + +add_interface adc_ch_2 conduit end +add_interface_port adc_ch_2 adc_enable_i1 enable Output 1 +add_interface_port adc_ch_2 adc_valid_i1 valid Output 1 +add_interface_port adc_ch_2 adc_data_i1 data Output 16 + +set_interface_property adc_ch_2 associatedClock if_adc_clk +set_interface_property adc_ch_2 associatedReset none + +add_interface adc_ch_3 conduit end +add_interface_port adc_ch_3 adc_enable_q1 enable Output 1 +add_interface_port adc_ch_3 adc_valid_q1 valid Output 1 +add_interface_port adc_ch_3 adc_data_q1 data Output 16 + +set_interface_property adc_ch_3 associatedClock if_adc_clk +set_interface_property adc_ch_3 associatedReset none + +ad_alt_intf signal adc_dovf input 1 ovf +ad_alt_intf signal adc_dunf input 1 unf + +# adc-os-channel interface + +add_interface adc_os_ch_0 conduit end +add_interface_port adc_os_ch_0 adc_os_enable_i0 enable Output 1 +add_interface_port adc_os_ch_0 adc_os_valid_i0 valid Output 1 +add_interface_port adc_os_ch_0 adc_os_data_i0 data Output 32 + +set_interface_property adc_os_ch_0 associatedClock if_adc_os_clk +set_interface_property adc_os_ch_0 associatedReset none + +add_interface adc_os_ch_1 conduit end +add_interface_port adc_os_ch_1 adc_os_enable_q0 enable Output 1 +add_interface_port adc_os_ch_1 adc_os_valid_q0 valid Output 1 +add_interface_port adc_os_ch_1 adc_os_data_q0 data Output 32 + +set_interface_property adc_os_ch_1 associatedClock if_adc_os_clk +set_interface_property adc_os_ch_1 associatedReset none + +ad_alt_intf signal adc_os_dovf input 1 ovf +ad_alt_intf signal adc_os_dunf input 1 unf + +# dac-channel interface + +add_interface dac_ch_0 conduit end +add_interface_port dac_ch_0 dac_enable_i0 enable Output 1 +add_interface_port dac_ch_0 dac_valid_i0 valid Output 1 +add_interface_port dac_ch_0 dac_data_i0 data Input 32 + +set_interface_property dac_ch_0 associatedClock if_dac_clk +set_interface_property dac_ch_0 associatedReset none + +add_interface dac_ch_1 conduit end +add_interface_port dac_ch_1 dac_enable_q0 enable Output 1 +add_interface_port dac_ch_1 dac_valid_q0 valid Output 1 +add_interface_port dac_ch_1 dac_data_q0 data Input 32 + +set_interface_property dac_ch_1 associatedClock if_dac_clk +set_interface_property dac_ch_1 associatedReset none + +add_interface dac_ch_2 conduit end +add_interface_port dac_ch_2 dac_enable_i1 enable Output 1 +add_interface_port dac_ch_2 dac_valid_i1 valid Output 1 +add_interface_port dac_ch_2 dac_data_i1 data Input 32 + +set_interface_property dac_ch_2 associatedClock if_dac_clk +set_interface_property dac_ch_2 associatedReset none + +add_interface dac_ch_3 conduit end +add_interface_port dac_ch_3 dac_enable_q1 enable Output 1 +add_interface_port dac_ch_3 dac_valid_q1 valid Output 1 +add_interface_port dac_ch_3 dac_data_q1 data Input 32 + +set_interface_property dac_ch_3 associatedClock if_dac_clk +set_interface_property dac_ch_3 associatedReset none + +ad_alt_intf signal dac_dovf input 1 ovf +ad_alt_intf signal dac_dunf input 1 unf + diff --git a/library/axi_ad9371/axi_ad9371_if.v b/library/axi_ad9371/axi_ad9371_if.v new file mode 100644 index 000000000..476c08012 --- /dev/null +++ b/library/axi_ad9371/axi_ad9371_if.v @@ -0,0 +1,153 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_ad9371_if ( + + // receive + + adc_clk, + adc_rx_sof, + adc_rx_data, + adc_os_clk, + adc_rx_os_sof, + adc_rx_os_data, + + adc_data, + adc_os_valid, + adc_os_data, + + // transmit + + dac_clk, + dac_tx_data, + + dac_data); + + // parameters + + parameter DEVICE_TYPE = 0; + + // receive + + input adc_clk; + input [ 3:0] adc_rx_sof; + input [ 63:0] adc_rx_data; + input adc_os_clk; + input [ 3:0] adc_rx_os_sof; + input [ 63:0] adc_rx_os_data; + output [ 63:0] adc_data; + output adc_os_valid; + output [ 63:0] adc_os_data; + + // transmit + + input dac_clk; + output [127:0] dac_tx_data; + input [127:0] dac_data; + + // internal signals + + wire [ 63:0] adc_rx_data_s; + wire [ 63:0] adc_rx_os_data_s; + + // delineating + + assign adc_data[((8* 7)+7):(8* 7)] = adc_rx_data_s[((8* 6)+7):(8* 6)]; + assign adc_data[((8* 6)+7):(8* 6)] = adc_rx_data_s[((8* 7)+7):(8* 7)]; + assign adc_data[((8* 5)+7):(8* 5)] = adc_rx_data_s[((8* 4)+7):(8* 4)]; + assign adc_data[((8* 4)+7):(8* 4)] = adc_rx_data_s[((8* 5)+7):(8* 5)]; + assign adc_data[((8* 3)+7):(8* 3)] = adc_rx_data_s[((8* 2)+7):(8* 2)]; + assign adc_data[((8* 2)+7):(8* 2)] = adc_rx_data_s[((8* 3)+7):(8* 3)]; + assign adc_data[((8* 1)+7):(8* 1)] = adc_rx_data_s[((8* 0)+7):(8* 0)]; + assign adc_data[((8* 0)+7):(8* 0)] = adc_rx_data_s[((8* 1)+7):(8* 1)]; + + assign adc_os_valid = 'd1; + assign adc_os_data[((8* 7)+7):(8* 7)] = adc_rx_os_data_s[((8* 6)+7):(8* 6)]; + assign adc_os_data[((8* 6)+7):(8* 6)] = adc_rx_os_data_s[((8* 7)+7):(8* 7)]; + assign adc_os_data[((8* 5)+7):(8* 5)] = adc_rx_os_data_s[((8* 4)+7):(8* 4)]; + assign adc_os_data[((8* 4)+7):(8* 4)] = adc_rx_os_data_s[((8* 5)+7):(8* 5)]; + assign adc_os_data[((8* 3)+7):(8* 3)] = adc_rx_os_data_s[((8* 2)+7):(8* 2)]; + assign adc_os_data[((8* 2)+7):(8* 2)] = adc_rx_os_data_s[((8* 3)+7):(8* 3)]; + assign adc_os_data[((8* 1)+7):(8* 1)] = adc_rx_os_data_s[((8* 0)+7):(8* 0)]; + assign adc_os_data[((8* 0)+7):(8* 0)] = adc_rx_os_data_s[((8* 1)+7):(8* 1)]; + + assign dac_tx_data[((8*15)+7):(8*15)] = (DEVICE_TYPE == 1) ? dac_data[((8*13)+7):(8*13)] : dac_data[((8*14)+7):(8*14)]; + assign dac_tx_data[((8*14)+7):(8*14)] = (DEVICE_TYPE == 1) ? dac_data[((8*12)+7):(8*12)] : dac_data[((8*15)+7):(8*15)]; + assign dac_tx_data[((8*13)+7):(8*13)] = (DEVICE_TYPE == 1) ? dac_data[((8*15)+7):(8*15)] : dac_data[((8*12)+7):(8*12)]; + assign dac_tx_data[((8*12)+7):(8*12)] = (DEVICE_TYPE == 1) ? dac_data[((8*14)+7):(8*14)] : dac_data[((8*13)+7):(8*13)]; + assign dac_tx_data[((8*11)+7):(8*11)] = (DEVICE_TYPE == 1) ? dac_data[((8* 9)+7):(8* 9)] : dac_data[((8*10)+7):(8*10)]; + assign dac_tx_data[((8*10)+7):(8*10)] = (DEVICE_TYPE == 1) ? dac_data[((8* 8)+7):(8* 8)] : dac_data[((8*11)+7):(8*11)]; + assign dac_tx_data[((8* 9)+7):(8* 9)] = (DEVICE_TYPE == 1) ? dac_data[((8*11)+7):(8*11)] : dac_data[((8* 8)+7):(8* 8)]; + assign dac_tx_data[((8* 8)+7):(8* 8)] = (DEVICE_TYPE == 1) ? dac_data[((8*10)+7):(8*10)] : dac_data[((8* 9)+7):(8* 9)]; + assign dac_tx_data[((8* 7)+7):(8* 7)] = (DEVICE_TYPE == 1) ? dac_data[((8* 5)+7):(8* 5)] : dac_data[((8* 6)+7):(8* 6)]; + assign dac_tx_data[((8* 6)+7):(8* 6)] = (DEVICE_TYPE == 1) ? dac_data[((8* 4)+7):(8* 4)] : dac_data[((8* 7)+7):(8* 7)]; + assign dac_tx_data[((8* 5)+7):(8* 5)] = (DEVICE_TYPE == 1) ? dac_data[((8* 7)+7):(8* 7)] : dac_data[((8* 4)+7):(8* 4)]; + assign dac_tx_data[((8* 4)+7):(8* 4)] = (DEVICE_TYPE == 1) ? dac_data[((8* 6)+7):(8* 6)] : dac_data[((8* 5)+7):(8* 5)]; + assign dac_tx_data[((8* 3)+7):(8* 3)] = (DEVICE_TYPE == 1) ? dac_data[((8* 1)+7):(8* 1)] : dac_data[((8* 2)+7):(8* 2)]; + assign dac_tx_data[((8* 2)+7):(8* 2)] = (DEVICE_TYPE == 1) ? dac_data[((8* 0)+7):(8* 0)] : dac_data[((8* 3)+7):(8* 3)]; + assign dac_tx_data[((8* 1)+7):(8* 1)] = (DEVICE_TYPE == 1) ? dac_data[((8* 3)+7):(8* 3)] : dac_data[((8* 0)+7):(8* 0)]; + assign dac_tx_data[((8* 0)+7):(8* 0)] = (DEVICE_TYPE == 1) ? dac_data[((8* 2)+7):(8* 2)] : dac_data[((8* 1)+7):(8* 1)]; + + // instantiations + + genvar n; + + generate + for (n = 0; n < 2; n = n + 1) begin: g_xcvr_if + + ad_xcvr_rx_if #(.DEVICE_TYPE (DEVICE_TYPE)) i_xcvr_rx_if ( + .rx_clk (adc_clk), + .rx_ip_sof (adc_rx_sof), + .rx_ip_data (adc_rx_data[((n*32)+31):(n*32)]), + .rx_sof (), + .rx_data (adc_rx_data_s[((n*32)+31):(n*32)])); + + ad_xcvr_rx_if #(.DEVICE_TYPE (DEVICE_TYPE)) i_xcvr_rx_os_if ( + .rx_clk (adc_os_clk), + .rx_ip_sof (adc_rx_os_sof), + .rx_ip_data (adc_rx_os_data[((n*32)+31):(n*32)]), + .rx_sof (), + .rx_data (adc_rx_os_data_s[((n*32)+31):(n*32)])); + end + endgenerate + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/library/axi_ad9371/axi_ad9371_ip.tcl b/library/axi_ad9371/axi_ad9371_ip.tcl new file mode 100755 index 000000000..551e3289a --- /dev/null +++ b/library/axi_ad9371/axi_ad9371_ip.tcl @@ -0,0 +1,47 @@ +# ip + +source ../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip.tcl + +adi_ip_create axi_ad9371 +adi_ip_files axi_ad9371 [list \ + "$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc" \ + "$ad_hdl_dir/library/common/ad_rst.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_mul.v" \ + "$ad_hdl_dir/library/common/ad_dds_sine.v" \ + "$ad_hdl_dir/library/common/ad_dds_1.v" \ + "$ad_hdl_dir/library/common/ad_dds.v" \ + "$ad_hdl_dir/library/common/ad_datafmt.v" \ + "$ad_hdl_dir/library/common/ad_dcfilter.v" \ + "$ad_hdl_dir/library/common/ad_iqcor.v" \ + "$ad_hdl_dir/library/common/up_axi.v" \ + "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ + "$ad_hdl_dir/library/common/up_xfer_status.v" \ + "$ad_hdl_dir/library/common/up_clock_mon.v" \ + "$ad_hdl_dir/library/common/up_adc_common.v" \ + "$ad_hdl_dir/library/common/up_adc_channel.v" \ + "$ad_hdl_dir/library/common/up_dac_common.v" \ + "$ad_hdl_dir/library/common/up_dac_channel.v" \ + "$ad_hdl_dir/library/common/ad_xcvr_rx_if.v" \ + "axi_ad9371_if.v" \ + "axi_ad9371_rx_channel.v" \ + "axi_ad9371_rx.v" \ + "axi_ad9371_rx_os.v" \ + "axi_ad9371_tx_channel.v" \ + "axi_ad9371_tx.v" \ + "axi_ad9371.v" ] + +adi_ip_properties axi_ad9371 + +adi_ip_constraints axi_jesd_gt [list \ + "$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc" ] + +set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]] +set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]] +set_property driver_value 0 [ipx::get_ports *dac_sync_in* -of_objects [ipx::current_core]] +set_property driver_value 0 [ipx::get_ports *dac_tx_ready* -of_objects [ipx::current_core]] +set_property driver_value 0 [ipx::get_ports *adc_rx_valid* -of_objects [ipx::current_core]] +set_property driver_value 0 [ipx::get_ports *adc_rx_os_valid* -of_objects [ipx::current_core]] + +ipx::save_core [ipx::current_core] + diff --git a/library/axi_ad9371/axi_ad9371_rx.v b/library/axi_ad9371/axi_ad9371_rx.v new file mode 100644 index 000000000..6d37e9577 --- /dev/null +++ b/library/axi_ad9371/axi_ad9371_rx.v @@ -0,0 +1,344 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_ad9371_rx ( + + // adc interface + + adc_rst, + adc_clk, + adc_data, + + // dma interface + + adc_enable_i0, + adc_valid_i0, + adc_data_i0, + adc_enable_q0, + adc_valid_q0, + adc_data_q0, + adc_enable_i1, + adc_valid_i1, + adc_data_i1, + adc_enable_q1, + adc_valid_q1, + adc_data_q1, + adc_dovf, + adc_dunf, + + // processor interface + + up_rstn, + up_clk, + up_wreq, + up_waddr, + up_wdata, + up_wack, + up_rreq, + up_raddr, + up_rdata, + up_rack); + + // parameters + + parameter DATAPATH_DISABLE = 0; + parameter ID = 0; + + // adc interface + + output adc_rst; + input adc_clk; + input [ 63:0] adc_data; + + // dma interface + + output adc_enable_i0; + output adc_valid_i0; + output [ 15:0] adc_data_i0; + output adc_enable_q0; + output adc_valid_q0; + output [ 15:0] adc_data_q0; + output adc_enable_i1; + output adc_valid_i1; + output [ 15:0] adc_data_i1; + output adc_enable_q1; + output adc_valid_q1; + output [ 15:0] adc_data_q1; + input adc_dovf; + input adc_dunf; + + // processor interface + + input up_rstn; + input up_clk; + input up_wreq; + input [ 13:0] up_waddr; + input [ 31:0] up_wdata; + output up_wack; + input up_rreq; + input [ 13:0] up_raddr; + output [ 31:0] up_rdata; + output up_rack; + + // internal registers + + reg up_status_pn_err = 'd0; + reg up_status_pn_oos = 'd0; + reg up_status_or = 'd0; + reg up_wack = 'd0; + reg up_rack = 'd0; + reg [ 31:0] up_rdata = 'd0; + + // internal signals + + wire [ 15:0] adc_data_iq_i0_s; + wire [ 15:0] adc_data_iq_q0_s; + wire [ 15:0] adc_data_iq_i1_s; + wire [ 15:0] adc_data_iq_q1_s; + wire [ 3:0] up_adc_pn_err_s; + wire [ 3:0] up_adc_pn_oos_s; + wire [ 3:0] up_adc_or_s; + wire [ 4:0] up_wack_s; + wire [ 4:0] up_rack_s; + wire [ 31:0] up_rdata_s[0:4]; + + // processor read interface + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_status_pn_err <= 'd0; + up_status_pn_oos <= 'd0; + up_status_or <= 'd0; + up_wack <= 'd0; + up_rack <= 'd0; + up_rdata <= 'd0; + end else begin + up_status_pn_err <= | up_adc_pn_err_s; + up_status_pn_oos <= | up_adc_pn_oos_s; + up_status_or <= | up_adc_or_s; + up_wack <= | up_wack_s; + up_rack <= | up_rack_s; + up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2] | up_rdata_s[3] | up_rdata_s[4]; + end + end + + // channel width is 32 bits + + assign adc_valid_i0 = 1'b1; + assign adc_valid_q0 = 1'b1; + assign adc_valid_i1 = 1'b1; + assign adc_valid_q1 = 1'b1; + + // channel 0 (i) + + axi_ad9371_rx_channel #( + .Q_OR_I_N (0), + .COMMON_ID ('h01), + .CHANNEL_ID (0), + .DATAPATH_DISABLE (DATAPATH_DISABLE), + .DATA_WIDTH (16)) + i_rx_channel_0 ( + .adc_clk (adc_clk), + .adc_rst (adc_rst), + .adc_valid_in (1'b1), + .adc_data_in (adc_data[15:0]), + .adc_valid_out (), + .adc_data_out (adc_data_i0), + .adc_data_iq_in (adc_data_iq_q0_s), + .adc_data_iq_out (adc_data_iq_i0_s), + .adc_enable (adc_enable_i0), + .up_adc_pn_err (up_adc_pn_err_s[0]), + .up_adc_pn_oos (up_adc_pn_oos_s[0]), + .up_adc_or (up_adc_or_s[0]), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack_s[0]), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata_s[0]), + .up_rack (up_rack_s[0])); + + // channel 1 (q) + + axi_ad9371_rx_channel #( + .Q_OR_I_N (1), + .COMMON_ID ('h01), + .CHANNEL_ID (1), + .DATAPATH_DISABLE (DATAPATH_DISABLE), + .DATA_WIDTH (16)) + i_rx_channel_1 ( + .adc_clk (adc_clk), + .adc_rst (adc_rst), + .adc_valid_in (1'b1), + .adc_data_in (adc_data[31:16]), + .adc_valid_out (), + .adc_data_out (adc_data_q0), + .adc_data_iq_in (adc_data_iq_i0_s), + .adc_data_iq_out (adc_data_iq_q0_s), + .adc_enable (adc_enable_q0), + .up_adc_pn_err (up_adc_pn_err_s[1]), + .up_adc_pn_oos (up_adc_pn_oos_s[1]), + .up_adc_or (up_adc_or_s[1]), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack_s[1]), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata_s[1]), + .up_rack (up_rack_s[1])); + + // channel 2 (i) + + axi_ad9371_rx_channel #( + .Q_OR_I_N (0), + .COMMON_ID ('h01), + .CHANNEL_ID (2), + .DATAPATH_DISABLE (DATAPATH_DISABLE), + .DATA_WIDTH (16)) + i_rx_channel_2 ( + .adc_clk (adc_clk), + .adc_rst (adc_rst), + .adc_valid_in (1'b1), + .adc_data_in (adc_data[47:32]), + .adc_valid_out (), + .adc_data_out (adc_data_i1), + .adc_data_iq_in (adc_data_iq_q1_s), + .adc_data_iq_out (adc_data_iq_i1_s), + .adc_enable (adc_enable_i1), + .up_adc_pn_err (up_adc_pn_err_s[2]), + .up_adc_pn_oos (up_adc_pn_oos_s[2]), + .up_adc_or (up_adc_or_s[2]), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack_s[2]), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata_s[2]), + .up_rack (up_rack_s[2])); + + // channel 3 (q) + + axi_ad9371_rx_channel #( + .Q_OR_I_N (1), + .COMMON_ID ('h01), + .CHANNEL_ID (3), + .DATAPATH_DISABLE (DATAPATH_DISABLE), + .DATA_WIDTH (16)) + i_rx_channel_3 ( + .adc_clk (adc_clk), + .adc_rst (adc_rst), + .adc_valid_in (1'b1), + .adc_data_in (adc_data[63:48]), + .adc_valid_out (), + .adc_data_out (adc_data_q1), + .adc_data_iq_in (adc_data_iq_i1_s), + .adc_data_iq_out (adc_data_iq_q1_s), + .adc_enable (adc_enable_q1), + .up_adc_pn_err (up_adc_pn_err_s[3]), + .up_adc_pn_oos (up_adc_pn_oos_s[3]), + .up_adc_or (up_adc_or_s[3]), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack_s[3]), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata_s[3]), + .up_rack (up_rack_s[3])); + + // common processor control + + up_adc_common #( + .COMMON_ID ('h00), + .ID (ID)) + i_up_adc_common ( + .mmcm_rst (), + .adc_clk (adc_clk), + .adc_rst (adc_rst), + .adc_r1_mode (), + .adc_ddr_edgesel (), + .adc_pin_mode (), + .adc_status (1'b1), + .adc_sync_status (1'd0), + .adc_status_ovf (adc_dovf), + .adc_status_unf (adc_dunf), + .adc_clk_ratio (32'd1), + .adc_start_code (), + .adc_sync (), + .up_status_pn_err (up_status_pn_err), + .up_status_pn_oos (up_status_pn_oos), + .up_status_or (up_status_or), + .up_drp_sel (), + .up_drp_wr (), + .up_drp_addr (), + .up_drp_wdata (), + .up_drp_rdata (32'd0), + .up_drp_ready (1'd0), + .up_drp_locked (1'd1), + .up_usr_chanmax (), + .adc_usr_chanmax (8'd3), + .up_adc_gpio_in (32'd0), + .up_adc_gpio_out (), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack_s[4]), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata_s[4]), + .up_rack (up_rack_s[4])); + +endmodule + +// *************************************************************************** +// *************************************************************************** + diff --git a/library/axi_ad9371/axi_ad9371_rx_channel.v b/library/axi_ad9371/axi_ad9371_rx_channel.v new file mode 100644 index 000000000..040a6180c --- /dev/null +++ b/library/axi_ad9371/axi_ad9371_rx_channel.v @@ -0,0 +1,256 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_ad9371_rx_channel ( + + // adc interface + + adc_clk, + adc_rst, + adc_valid_in, + adc_data_in, + adc_valid_out, + adc_data_out, + adc_data_iq_in, + adc_data_iq_out, + adc_enable, + + // channel interface + + up_adc_pn_err, + up_adc_pn_oos, + up_adc_or, + + // processor interface + + up_rstn, + up_clk, + up_wreq, + up_waddr, + up_wdata, + up_wack, + up_rreq, + up_raddr, + up_rdata, + up_rack); + + // parameters + + parameter Q_OR_I_N = 0; + parameter COMMON_ID = 0; + parameter CHANNEL_ID = 0; + parameter DATAPATH_DISABLE = 0; + parameter DATA_WIDTH = 32; + + localparam NUM_OF_SAMPLES = DATA_WIDTH/16; + + // adc interface + + input adc_clk; + input adc_rst; + input adc_valid_in; + input [(DATA_WIDTH-1):0] adc_data_in; + output adc_valid_out; + output [(DATA_WIDTH-1):0] adc_data_out; + input [(DATA_WIDTH-1):0] adc_data_iq_in; + output [(DATA_WIDTH-1):0] adc_data_iq_out; + output adc_enable; + + // channel interface + + output up_adc_pn_err; + output up_adc_pn_oos; + output up_adc_or; + + // processor interface + + input up_rstn; + input up_clk; + input up_wreq; + input [13:0] up_waddr; + input [31:0] up_wdata; + output up_wack; + input up_rreq; + input [13:0] up_raddr; + output [31:0] up_rdata; + output up_rack; + + // internal signals + + wire [(NUM_OF_SAMPLES-1):0] adc_dfmt_valid_s; + wire [(DATA_WIDTH-1):0] adc_dfmt_data_s; + wire [(NUM_OF_SAMPLES-1):0] adc_dcfilter_valid_s; + wire [(DATA_WIDTH-1):0] adc_dcfilter_data_s; + wire [(NUM_OF_SAMPLES-1):0] adc_valid_out_s; + wire adc_pn_err_s; + wire adc_pn_oos_s; + wire adc_dfmt_se_s; + wire adc_dfmt_type_s; + wire adc_dfmt_enable_s; + wire adc_dcfilt_enb_s; + wire [15:0] adc_dcfilt_offset_s; + wire [15:0] adc_dcfilt_coeff_s; + wire adc_iqcor_enb_s; + wire [15:0] adc_iqcor_coeff_1_s; + wire [15:0] adc_iqcor_coeff_2_s; + + // variables + + genvar n; + + // iq correction inputs + + assign adc_pn_oos_s = 1'b1; + assign adc_pn_err_s = 1'b0; + + generate + for (n = 0; n < NUM_OF_SAMPLES; n = n + 1) begin: g_datafmt + if (DATAPATH_DISABLE == 1) begin + assign adc_dfmt_valid_s[n] = adc_valid_in; + assign adc_dfmt_data_s[((16*n)+15):(16*n)] = adc_data_in[((16*n)+15):(16*n)]; + end else begin + ad_datafmt #(.DATA_WIDTH (16)) i_ad_datafmt ( + .clk (adc_clk), + .valid (adc_valid_in), + .data (adc_data_in[((16*n)+15):(16*n)]), + .valid_out (adc_dfmt_valid_s[n]), + .data_out (adc_dfmt_data_s[((16*n)+15):(16*n)]), + .dfmt_enable (adc_dfmt_enable_s), + .dfmt_type (adc_dfmt_type_s), + .dfmt_se (adc_dfmt_se_s)); + end + end + endgenerate + + generate + for (n = 0; n < NUM_OF_SAMPLES; n = n + 1) begin: g_dcfilter + if (DATAPATH_DISABLE == 1) begin + assign adc_dcfilter_valid_s[n] = adc_dfmt_valid_s[n]; + assign adc_dcfilter_data_s[((16*n)+15):(16*n)] = adc_dfmt_data_s[((16*n)+15):(16*n)]; + end else begin + ad_dcfilter i_ad_dcfilter ( + .clk (adc_clk), + .valid (adc_dfmt_valid_s[n]), + .data (adc_dfmt_data_s[((16*n)+15):(16*n)]), + .valid_out (adc_dcfilter_valid_s[n]), + .data_out (adc_dcfilter_data_s[((16*n)+15):(16*n)]), + .dcfilt_enb (adc_dcfilt_enb_s), + .dcfilt_coeff (adc_dcfilt_coeff_s), + .dcfilt_offset (adc_dcfilt_offset_s)); + end + end + endgenerate + + assign adc_valid_out = adc_valid_out_s[0]; + assign adc_data_iq_out = adc_dcfilter_data_s; + + generate + for (n = 0; n < NUM_OF_SAMPLES; n = n + 1) begin: g_iqcor + if (DATAPATH_DISABLE == 1) begin + assign adc_valid_out_s[n] = adc_dcfilter_valid_s[n]; + assign adc_data_out[((16*n)+15):(16*n)] = adc_dcfilter_data_s[((16*n)+15):(16*n)]; + end else begin + ad_iqcor #(.Q_OR_I_N (Q_OR_I_N)) i_ad_iqcor ( + .clk (adc_clk), + .valid (adc_dcfilter_valid_s[n]), + .data_in (adc_dcfilter_data_s[((16*n)+15):(16*n)]), + .data_iq (adc_data_iq_in[((16*n)+15):(16*n)]), + .valid_out (adc_valid_out_s[n]), + .data_out (adc_data_out[((16*n)+15):(16*n)]), + .iqcor_enable (adc_iqcor_enb_s), + .iqcor_coeff_1 (adc_iqcor_coeff_1_s), + .iqcor_coeff_2 (adc_iqcor_coeff_2_s)); + end + end + endgenerate + + up_adc_channel #( + .COMMON_ID (COMMON_ID), + .CHANNEL_ID (CHANNEL_ID)) + i_up_adc_channel ( + .adc_clk (adc_clk), + .adc_rst (adc_rst), + .adc_enable (adc_enable), + .adc_iqcor_enb (adc_iqcor_enb_s), + .adc_dcfilt_enb (adc_dcfilt_enb_s), + .adc_dfmt_se (adc_dfmt_se_s), + .adc_dfmt_type (adc_dfmt_type_s), + .adc_dfmt_enable (adc_dfmt_enable_s), + .adc_dcfilt_offset (adc_dcfilt_offset_s), + .adc_dcfilt_coeff (adc_dcfilt_coeff_s), + .adc_iqcor_coeff_1 (adc_iqcor_coeff_1_s), + .adc_iqcor_coeff_2 (adc_iqcor_coeff_2_s), + .adc_pnseq_sel (), + .adc_data_sel (), + .adc_pn_err (adc_pn_err_s), + .adc_pn_oos (adc_pn_oos_s), + .adc_or (1'd0), + .up_adc_pn_err (up_adc_pn_err), + .up_adc_pn_oos (up_adc_pn_oos), + .up_adc_or (up_adc_or), + .up_usr_datatype_be (), + .up_usr_datatype_signed (), + .up_usr_datatype_shift (), + .up_usr_datatype_total_bits (), + .up_usr_datatype_bits (), + .up_usr_decimation_m (), + .up_usr_decimation_n (), + .adc_usr_datatype_be (1'b0), + .adc_usr_datatype_signed (1'b1), + .adc_usr_datatype_shift (8'd0), + .adc_usr_datatype_total_bits (8'd16), + .adc_usr_datatype_bits (8'd16), + .adc_usr_decimation_m (16'd1), + .adc_usr_decimation_n (16'd1), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata), + .up_rack (up_rack)); + +endmodule + +// *************************************************************************** +// *************************************************************************** + diff --git a/library/axi_ad9371/axi_ad9371_rx_os.v b/library/axi_ad9371/axi_ad9371_rx_os.v new file mode 100644 index 000000000..81304a5c5 --- /dev/null +++ b/library/axi_ad9371/axi_ad9371_rx_os.v @@ -0,0 +1,261 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_ad9371_rx_os ( + + // adc interface + + adc_os_rst, + adc_os_clk, + adc_os_valid, + adc_os_data, + + // dma interface + + adc_os_enable_i0, + adc_os_valid_i0, + adc_os_data_i0, + adc_os_enable_q0, + adc_os_valid_q0, + adc_os_data_q0, + adc_os_dovf, + adc_os_dunf, + + // processor interface + + up_rstn, + up_clk, + up_wreq, + up_waddr, + up_wdata, + up_wack, + up_rreq, + up_raddr, + up_rdata, + up_rack); + + // parameters + + parameter DATAPATH_DISABLE = 0; + parameter ID = 0; + + // adc interface + + output adc_os_rst; + input adc_os_clk; + input adc_os_valid; + input [ 63:0] adc_os_data; + + // dma interface + + output adc_os_enable_i0; + output adc_os_valid_i0; + output [ 31:0] adc_os_data_i0; + output adc_os_enable_q0; + output adc_os_valid_q0; + output [ 31:0] adc_os_data_q0; + input adc_os_dovf; + input adc_os_dunf; + + // processor interface + + input up_rstn; + input up_clk; + input up_wreq; + input [ 13:0] up_waddr; + input [ 31:0] up_wdata; + output up_wack; + input up_rreq; + input [ 13:0] up_raddr; + output [ 31:0] up_rdata; + output up_rack; + + // internal registers + + reg up_status_pn_err = 'd0; + reg up_status_pn_oos = 'd0; + reg up_status_or = 'd0; + reg up_wack = 'd0; + reg up_rack = 'd0; + reg [ 31:0] up_rdata = 'd0; + + // internal signals + + wire [ 31:0] adc_os_data_iq_i0_s; + wire [ 31:0] adc_os_data_iq_q0_s; + wire [ 1:0] up_adc_pn_err_s; + wire [ 1:0] up_adc_pn_oos_s; + wire [ 1:0] up_adc_or_s; + wire [ 2:0] up_wack_s; + wire [ 2:0] up_rack_s; + wire [ 31:0] up_rdata_s[0:2]; + + // processor read interface + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_status_pn_err <= 'd0; + up_status_pn_oos <= 'd0; + up_status_or <= 'd0; + up_wack <= 'd0; + up_rack <= 'd0; + up_rdata <= 'd0; + end else begin + up_status_pn_err <= | up_adc_pn_err_s; + up_status_pn_oos <= | up_adc_pn_oos_s; + up_status_or <= | up_adc_or_s; + up_wack <= | up_wack_s; + up_rack <= | up_rack_s; + up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2]; + end + end + + // channel o/s (i) + + axi_ad9371_rx_channel #( + .Q_OR_I_N (0), + .COMMON_ID ('h21), + .CHANNEL_ID (0), + .DATAPATH_DISABLE (DATAPATH_DISABLE), + .DATA_WIDTH (32)) + i_rx_os_channel_0 ( + .adc_clk (adc_os_clk), + .adc_rst (adc_os_rst), + .adc_valid_in (adc_os_valid), + .adc_data_in (adc_os_data[31:0]), + .adc_valid_out (adc_os_valid_i0), + .adc_data_out (adc_os_data_i0), + .adc_data_iq_in (adc_os_data_iq_q0_s), + .adc_data_iq_out (adc_os_data_iq_i0_s), + .adc_enable (adc_os_enable_i0), + .up_adc_pn_err (up_adc_pn_err_s[0]), + .up_adc_pn_oos (up_adc_pn_oos_s[0]), + .up_adc_or (up_adc_or_s[0]), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack_s[0]), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata_s[0]), + .up_rack (up_rack_s[0])); + + // channel o/s (q) + + axi_ad9371_rx_channel #( + .Q_OR_I_N (1), + .COMMON_ID ('h21), + .CHANNEL_ID (1), + .DATAPATH_DISABLE (DATAPATH_DISABLE), + .DATA_WIDTH (32)) + i_rx_os_channel_1 ( + .adc_clk (adc_os_clk), + .adc_rst (adc_os_rst), + .adc_valid_in (adc_os_valid), + .adc_data_in (adc_os_data[63:32]), + .adc_valid_out (adc_os_valid_q0), + .adc_data_out (adc_os_data_q0), + .adc_data_iq_in (adc_os_data_iq_i0_s), + .adc_data_iq_out (adc_os_data_iq_q0_s), + .adc_enable (adc_os_enable_q0), + .up_adc_pn_err (up_adc_pn_err_s[1]), + .up_adc_pn_oos (up_adc_pn_oos_s[1]), + .up_adc_or (up_adc_or_s[1]), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack_s[1]), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata_s[1]), + .up_rack (up_rack_s[1])); + + // common processor control + + up_adc_common #( + .COMMON_ID ('h20), + .ID (ID)) + i_up_adc_common ( + .mmcm_rst (), + .adc_clk (adc_os_clk), + .adc_rst (adc_os_rst), + .adc_r1_mode (), + .adc_ddr_edgesel (), + .adc_pin_mode (), + .adc_status (1'b1), + .adc_sync_status (1'd0), + .adc_status_ovf (adc_os_dovf), + .adc_status_unf (adc_os_dunf), + .adc_clk_ratio (32'd1), + .adc_start_code (), + .adc_sync (), + .up_status_pn_err (up_status_pn_err), + .up_status_pn_oos (up_status_pn_oos), + .up_status_or (up_status_or), + .up_drp_sel (), + .up_drp_wr (), + .up_drp_addr (), + .up_drp_wdata (), + .up_drp_rdata (32'd0), + .up_drp_ready (1'd0), + .up_drp_locked (1'd1), + .up_usr_chanmax (), + .adc_usr_chanmax (8'd3), + .up_adc_gpio_in (32'd0), + .up_adc_gpio_out (), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack_s[2]), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata_s[2]), + .up_rack (up_rack_s[2])); + +endmodule + +// *************************************************************************** +// *************************************************************************** + diff --git a/library/axi_ad9371/axi_ad9371_tx.v b/library/axi_ad9371/axi_ad9371_tx.v new file mode 100644 index 000000000..853b4fec4 --- /dev/null +++ b/library/axi_ad9371/axi_ad9371_tx.v @@ -0,0 +1,330 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_ad9371_tx ( + + // dac interface + + dac_rst, + dac_clk, + dac_data, + + // master/slave + + dac_sync_in, + dac_sync_out, + + // dma interface + + dac_enable_i0, + dac_valid_i0, + dac_data_i0, + dac_enable_q0, + dac_valid_q0, + dac_data_q0, + dac_enable_i1, + dac_valid_i1, + dac_data_i1, + dac_enable_q1, + dac_valid_q1, + dac_data_q1, + dac_dovf, + dac_dunf, + + // processor interface + + up_rstn, + up_clk, + up_wreq, + up_waddr, + up_wdata, + up_wack, + up_rreq, + up_raddr, + up_rdata, + up_rack); + + // parameters + + parameter DATAPATH_DISABLE = 0; + parameter ID = 0; + + // dac interface + + output dac_rst; + input dac_clk; + output [127:0] dac_data; + + // master/slave + + input dac_sync_in; + output dac_sync_out; + + // dma interface + + output dac_enable_i0; + output dac_valid_i0; + input [ 31:0] dac_data_i0; + output dac_enable_q0; + output dac_valid_q0; + input [ 31:0] dac_data_q0; + output dac_enable_i1; + output dac_valid_i1; + input [ 31:0] dac_data_i1; + output dac_enable_q1; + output dac_valid_q1; + input [ 31:0] dac_data_q1; + input dac_dovf; + input dac_dunf; + + // processor interface + + input up_rstn; + input up_clk; + input up_wreq; + input [ 13:0] up_waddr; + input [ 31:0] up_wdata; + output up_wack; + input up_rreq; + input [ 13:0] up_raddr; + output [ 31:0] up_rdata; + output up_rack; + + // internal registers + + reg dac_data_sync = 'd0; + reg up_wack = 'd0; + reg up_rack = 'd0; + reg [ 31:0] up_rdata = 'd0; + + // internal signals + + wire dac_data_sync_s; + wire [ 31:0] dac_data_iq_i0_s; + wire [ 31:0] dac_data_iq_q0_s; + wire [ 31:0] dac_data_iq_i1_s; + wire [ 31:0] dac_data_iq_q1_s; + wire dac_dds_format_s; + wire [ 4:0] up_wack_s; + wire [ 4:0] up_rack_s; + wire [ 31:0] up_rdata_s[0:4]; + + // master/slave + + assign dac_data_sync_s = (ID == 0) ? dac_sync_out : dac_sync_in; + + always @(posedge dac_clk) begin + dac_data_sync <= dac_data_sync_s; + end + + // processor read interface + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_wack <= 'd0; + up_rack <= 'd0; + up_rdata <= 'd0; + end else begin + up_wack <= | up_wack_s; + up_rack <= | up_rack_s; + up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2] | + up_rdata_s[3] | up_rdata_s[4]; + end + end + + // dac channel + + assign dac_valid_i0 = 1'b1; + + axi_ad9371_tx_channel #( + .CHANNEL_ID (0), + .Q_OR_I_N (0), + .DATAPATH_DISABLE (DATAPATH_DISABLE)) + i_tx_channel_0 ( + .dac_clk (dac_clk), + .dac_rst (dac_rst), + .dac_data_in (dac_data_i0), + .dac_data_out (dac_data[31:0]), + .dac_data_iq_in (dac_data_iq_q0_s), + .dac_data_iq_out (dac_data_iq_i0_s), + .dac_enable (dac_enable_i0), + .dac_data_sync (dac_data_sync), + .dac_dds_format (dac_dds_format_s), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack_s[0]), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata_s[0]), + .up_rack (up_rack_s[0])); + + // dac channel + + assign dac_valid_q0 = 1'b1; + + axi_ad9371_tx_channel #( + .CHANNEL_ID (1), + .Q_OR_I_N (1), + .DATAPATH_DISABLE (DATAPATH_DISABLE)) + i_tx_channel_1 ( + .dac_clk (dac_clk), + .dac_rst (dac_rst), + .dac_data_in (dac_data_q0), + .dac_data_out (dac_data[63:32]), + .dac_data_iq_in (dac_data_iq_i0_s), + .dac_data_iq_out (dac_data_iq_q0_s), + .dac_enable (dac_enable_q0), + .dac_data_sync (dac_data_sync), + .dac_dds_format (dac_dds_format_s), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack_s[1]), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata_s[1]), + .up_rack (up_rack_s[1])); + + // dac channel + + assign dac_valid_i1 = 1'b1; + + axi_ad9371_tx_channel #( + .CHANNEL_ID (2), + .Q_OR_I_N (0), + .DATAPATH_DISABLE (DATAPATH_DISABLE)) + i_tx_channel_2 ( + .dac_clk (dac_clk), + .dac_rst (dac_rst), + .dac_data_in (dac_data_i1), + .dac_data_out (dac_data[95:64]), + .dac_data_iq_in (dac_data_iq_q1_s), + .dac_data_iq_out (dac_data_iq_i1_s), + .dac_enable (dac_enable_i1), + .dac_data_sync (dac_data_sync), + .dac_dds_format (dac_dds_format_s), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack_s[2]), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata_s[2]), + .up_rack (up_rack_s[2])); + + // dac channel + + assign dac_valid_q1 = 1'b1; + + axi_ad9371_tx_channel #( + .CHANNEL_ID (3), + .Q_OR_I_N (1), + .DATAPATH_DISABLE (DATAPATH_DISABLE)) + i_tx_channel_3 ( + .dac_clk (dac_clk), + .dac_rst (dac_rst), + .dac_data_in (dac_data_q1), + .dac_data_out (dac_data[127:96]), + .dac_data_iq_in (dac_data_iq_i1_s), + .dac_data_iq_out (dac_data_iq_q1_s), + .dac_enable (dac_enable_q1), + .dac_data_sync (dac_data_sync), + .dac_dds_format (dac_dds_format_s), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack_s[3]), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata_s[3]), + .up_rack (up_rack_s[3])); + + // dac common processor interface + + up_dac_common #(.ID (ID)) i_up_dac_common ( + .mmcm_rst (), + .dac_clk (dac_clk), + .dac_rst (dac_rst), + .dac_sync (dac_sync_out), + .dac_frame (), + .dac_clksel (), + .dac_par_type (), + .dac_par_enb (), + .dac_r1_mode (), + .dac_datafmt (dac_dds_format_s), + .dac_datarate (), + .dac_status (1'b1), + .dac_status_ovf (dac_dovf), + .dac_status_unf (dac_dunf), + .dac_clk_ratio (32'd2), + .up_drp_sel (), + .up_drp_wr (), + .up_drp_addr (), + .up_drp_wdata (), + .up_drp_rdata (32'd0), + .up_drp_ready (1'd0), + .up_drp_locked (1'd1), + .up_usr_chanmax (), + .dac_usr_chanmax (8'd3), + .up_dac_gpio_in (32'd0), + .up_dac_gpio_out (), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack_s[4]), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata_s[4]), + .up_rack (up_rack_s[4])); + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/library/axi_ad9371/axi_ad9371_tx_channel.v b/library/axi_ad9371/axi_ad9371_tx_channel.v new file mode 100644 index 000000000..6755ee133 --- /dev/null +++ b/library/axi_ad9371/axi_ad9371_tx_channel.v @@ -0,0 +1,284 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_ad9371_tx_channel ( + + // dac interface + + dac_clk, + dac_rst, + dac_data_in, + dac_data_out, + dac_data_iq_in, + dac_data_iq_out, + + // processor interface + + dac_enable, + dac_data_sync, + dac_dds_format, + + // bus interface + + up_rstn, + up_clk, + up_wreq, + up_waddr, + up_wdata, + up_wack, + up_rreq, + up_raddr, + up_rdata, + up_rack); + + // parameters + + parameter CHANNEL_ID = 32'h0; + parameter Q_OR_I_N = 0; + parameter DATAPATH_DISABLE = 0; + + // dac interface + + input dac_clk; + input dac_rst; + input [31:0] dac_data_in; + output [31:0] dac_data_out; + input [31:0] dac_data_iq_in; + output [31:0] dac_data_iq_out; + + // processor interface + + output dac_enable; + input dac_data_sync; + input dac_dds_format; + + // bus interface + + input up_rstn; + input up_clk; + input up_wreq; + input [13:0] up_waddr; + input [31:0] up_wdata; + output up_wack; + input up_rreq; + input [13:0] up_raddr; + output [31:0] up_rdata; + output up_rack; + + // internal registers + + reg dac_enable = 'd0; + reg [31:0] dac_data_iq_out = 'd0; + reg [31:0] dac_pat_data = 'd0; + reg [15:0] dac_dds_phase_0_0 = 'd0; + reg [15:0] dac_dds_phase_0_1 = 'd0; + reg [15:0] dac_dds_phase_1_0 = 'd0; + reg [15:0] dac_dds_phase_1_1 = 'd0; + reg [15:0] dac_dds_incr_0 = 'd0; + reg [15:0] dac_dds_incr_1 = 'd0; + reg [31:0] dac_dds_data = 'd0; + + // internal signals + + wire [15:0] dac_dds_data_0_s; + wire [15:0] dac_dds_data_1_s; + wire [15:0] dac_dds_scale_1_s; + wire [15:0] dac_dds_init_1_s; + wire [15:0] dac_dds_incr_1_s; + wire [15:0] dac_dds_scale_2_s; + wire [15:0] dac_dds_init_2_s; + wire [15:0] dac_dds_incr_2_s; + wire [15:0] dac_pat_data_1_s; + wire [15:0] dac_pat_data_2_s; + wire [ 3:0] dac_data_sel_s; + wire dac_iqcor_enb_s; + wire [15:0] dac_iqcor_coeff_1_s; + wire [15:0] dac_iqcor_coeff_2_s; + + // dac iq correction + + generate + if (DATAPATH_DISABLE == 1) begin + + assign dac_data_out = dac_data_iq_out; + + end else begin + + ad_iqcor #(.Q_OR_I_N (Q_OR_I_N)) i_ad_iqcor_1 ( + .clk (dac_clk), + .valid (1'b1), + .data_in (dac_data_iq_out[31:16]), + .data_iq (dac_data_iq_in[31:16]), + .valid_out (), + .data_out (dac_data_out[31:16]), + .iqcor_enable (dac_iqcor_enb_s), + .iqcor_coeff_1 (dac_iqcor_coeff_1_s), + .iqcor_coeff_2 (dac_iqcor_coeff_2_s)); + + ad_iqcor #(.Q_OR_I_N (Q_OR_I_N)) i_ad_iqcor_0 ( + .clk (dac_clk), + .valid (1'b1), + .data_in (dac_data_iq_out[15:0]), + .data_iq (dac_data_iq_in[15:0]), + .valid_out (), + .data_out (dac_data_out[15:0]), + .iqcor_enable (dac_iqcor_enb_s), + .iqcor_coeff_1 (dac_iqcor_coeff_1_s), + .iqcor_coeff_2 (dac_iqcor_coeff_2_s)); + end + endgenerate + + // dac mux + + always @(posedge dac_clk) begin + dac_enable <= (dac_data_sel_s == 4'h2) ? 1'b1 : 1'b0; + case (dac_data_sel_s) + 4'h3: dac_data_iq_out <= 32'd0; + 4'h2: dac_data_iq_out <= dac_data_in; + 4'h1: dac_data_iq_out <= dac_pat_data; + default: dac_data_iq_out <= dac_dds_data; + endcase + end + + // pattern + + always @(posedge dac_clk) begin + dac_pat_data <= {dac_pat_data_2_s, dac_pat_data_1_s}; + end + + // dds + + always @(posedge dac_clk) begin + if (dac_data_sync == 1'b1) begin + dac_dds_phase_0_0 <= dac_dds_init_1_s; + dac_dds_phase_0_1 <= dac_dds_init_2_s; + dac_dds_phase_1_0 <= dac_dds_phase_0_0 + dac_dds_incr_1_s; + dac_dds_phase_1_1 <= dac_dds_phase_0_1 + dac_dds_incr_2_s; + dac_dds_incr_0 <= {dac_dds_incr_1_s[14:0], 1'd0}; + dac_dds_incr_1 <= {dac_dds_incr_2_s[14:0], 1'd0}; + dac_dds_data <= 32'd0; + end else begin + dac_dds_phase_0_0 <= dac_dds_phase_0_0 + dac_dds_incr_0; + dac_dds_phase_0_1 <= dac_dds_phase_0_1 + dac_dds_incr_1; + dac_dds_phase_1_0 <= dac_dds_phase_1_0 + dac_dds_incr_0; + dac_dds_phase_1_1 <= dac_dds_phase_1_1 + dac_dds_incr_1; + dac_dds_incr_0 <= dac_dds_incr_0; + dac_dds_incr_1 <= dac_dds_incr_1; + dac_dds_data <= {dac_dds_data_1_s, dac_dds_data_0_s}; + end + end + + // dds + + generate + if (DATAPATH_DISABLE == 1) begin + + assign dac_dds_data_0_s = 16'd0; + assign dac_dds_data_1_s = 16'd0; + + end else begin + + ad_dds i_dds_0 ( + .clk (dac_clk), + .dds_format (dac_dds_format), + .dds_phase_0 (dac_dds_phase_0_0), + .dds_scale_0 (dac_dds_scale_1_s), + .dds_phase_1 (dac_dds_phase_0_1), + .dds_scale_1 (dac_dds_scale_2_s), + .dds_data (dac_dds_data_0_s)); + + ad_dds i_dds_1 ( + .clk (dac_clk), + .dds_format (dac_dds_format), + .dds_phase_0 (dac_dds_phase_1_0), + .dds_scale_0 (dac_dds_scale_1_s), + .dds_phase_1 (dac_dds_phase_1_1), + .dds_scale_1 (dac_dds_scale_2_s), + .dds_data (dac_dds_data_1_s)); + + end + endgenerate + + // single channel processor + + up_dac_channel #(.CHANNEL_ID (CHANNEL_ID)) i_up_dac_channel ( + .dac_clk (dac_clk), + .dac_rst (dac_rst), + .dac_dds_scale_1 (dac_dds_scale_1_s), + .dac_dds_init_1 (dac_dds_init_1_s), + .dac_dds_incr_1 (dac_dds_incr_1_s), + .dac_dds_scale_2 (dac_dds_scale_2_s), + .dac_dds_init_2 (dac_dds_init_2_s), + .dac_dds_incr_2 (dac_dds_incr_2_s), + .dac_pat_data_1 (dac_pat_data_1_s), + .dac_pat_data_2 (dac_pat_data_2_s), + .dac_data_sel (dac_data_sel_s), + .dac_iq_mode (), + .dac_iqcor_enb (dac_iqcor_enb_s), + .dac_iqcor_coeff_1 (dac_iqcor_coeff_1_s), + .dac_iqcor_coeff_2 (dac_iqcor_coeff_2_s), + .up_usr_datatype_be (), + .up_usr_datatype_signed (), + .up_usr_datatype_shift (), + .up_usr_datatype_total_bits (), + .up_usr_datatype_bits (), + .up_usr_interpolation_m (), + .up_usr_interpolation_n (), + .dac_usr_datatype_be (1'b0), + .dac_usr_datatype_signed (1'b1), + .dac_usr_datatype_shift (8'd0), + .dac_usr_datatype_total_bits (8'd16), + .dac_usr_datatype_bits (8'd16), + .dac_usr_interpolation_m (16'd1), + .dac_usr_interpolation_n (16'd1), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata), + .up_rack (up_rack)); + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/library/axi_ad9434/Makefile b/library/axi_ad9434/Makefile index f8841cd1f..f950dc456 100644 --- a/library/axi_ad9434/Makefile +++ b/library/axi_ad9434/Makefile @@ -5,28 +5,28 @@ #################################################################################### #################################################################################### -M_DEPS := axi_ad9434_ip.tcl -M_DEPS += ../scripts/adi_env.tcl -M_DEPS += ../scripts/adi_ip.tcl -M_DEPS += ../common/ad_serdes_clk.v -M_DEPS += ../common/ad_mmcm_drp.v -M_DEPS += ../common/ad_serdes_in.v +M_DEPS += ../common/ad_axi_ip_constr.xdc M_DEPS += ../common/ad_datafmt.v +M_DEPS += ../common/ad_pnmon.v M_DEPS += ../common/ad_rst.v -M_DEPS += ../common/up_xfer_cntrl.v -M_DEPS += ../common/up_xfer_status.v +M_DEPS += ../common/up_adc_channel.v +M_DEPS += ../common/up_adc_common.v +M_DEPS += ../common/up_axi.v M_DEPS += ../common/up_clock_mon.v M_DEPS += ../common/up_delay_cntrl.v -M_DEPS += ../common/up_adc_common.v -M_DEPS += ../common/up_adc_channel.v -M_DEPS += ../common/ad_pnmon.v -M_DEPS += ../common/up_axi.v -M_DEPS += ../common/ad_axi_ip_constr.xdc -M_DEPS += axi_ad9434_if.v -M_DEPS += axi_ad9434_pnmon.v -M_DEPS += axi_ad9434_core.v -M_DEPS += axi_ad9434_constr.xdc +M_DEPS += ../common/up_xfer_cntrl.v +M_DEPS += ../common/up_xfer_status.v +M_DEPS += ../scripts/adi_env.tcl +M_DEPS += ../scripts/adi_ip.tcl +M_DEPS += ../xilinx/common/ad_mmcm_drp.v +M_DEPS += ../xilinx/common/ad_serdes_clk.v +M_DEPS += ../xilinx/common/ad_serdes_in.v M_DEPS += axi_ad9434.v +M_DEPS += axi_ad9434_constr.xdc +M_DEPS += axi_ad9434_core.v +M_DEPS += axi_ad9434_if.v +M_DEPS += axi_ad9434_ip.tcl +M_DEPS += axi_ad9434_pnmon.v M_VIVADO := vivado -mode batch -source @@ -37,6 +37,10 @@ M_FLIST += *.log M_FLIST += component.xml M_FLIST += *.jou M_FLIST += xgui +M_FLIST += *.ip_user_files +M_FLIST += *.srcs +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil @@ -53,7 +57,7 @@ clean-all: axi_ad9434.xpr: $(M_DEPS) - rm -rf $(M_FLIST) + -rm -rf $(M_FLIST) $(M_VIVADO) axi_ad9434_ip.tcl >> axi_ad9434_ip.log 2>&1 #################################################################################### diff --git a/library/axi_ad9434/axi_ad9434.v b/library/axi_ad9434/axi_ad9434.v index 2a226e5e9..83e32fa8c 100644 --- a/library/axi_ad9434/axi_ad9434.v +++ b/library/axi_ad9434/axi_ad9434.v @@ -79,7 +79,9 @@ module axi_ad9434 ( s_axi_rvalid, s_axi_rresp, s_axi_rdata, - s_axi_rready); + s_axi_rready, + s_axi_awprot, + s_axi_arprot); // parameters @@ -128,6 +130,9 @@ module axi_ad9434 ( output [ 1:0] s_axi_rresp; output [31:0] s_axi_rdata; input s_axi_rready; + input [ 2:0] s_axi_awprot; + input [ 2:0] s_axi_arprot; + // internal clocks & resets wire adc_rst; @@ -162,8 +167,8 @@ module axi_ad9434 ( wire up_drp_sel_s; wire up_drp_wr_s; wire [11:0] up_drp_addr_s; - wire [15:0] up_drp_wdata_s; - wire [15:0] up_drp_rdata_s; + wire [31:0] up_drp_wdata_s; + wire [31:0] up_drp_rdata_s; wire up_drp_ready_s; wire up_drp_locked_s; diff --git a/library/axi_ad9434/axi_ad9434_constr.xdc b/library/axi_ad9434/axi_ad9434_constr.xdc index 8b1378917..eb8b7d9e3 100644 --- a/library/axi_ad9434/axi_ad9434_constr.xdc +++ b/library/axi_ad9434/axi_ad9434_constr.xdc @@ -1 +1,2 @@ - +set_false_path -from [get_cells -hier -filter {name =~ *up_drp_locked_reg && IS_SEQUENTIAL}] -to \ +[get_cells -hier -filter {name =~ *adc_status_m1_reg && IS_SEQUENTIAL}] diff --git a/library/axi_ad9434/axi_ad9434_core.v b/library/axi_ad9434/axi_ad9434_core.v index a0d94d6af..84d6c2203 100644 --- a/library/axi_ad9434/axi_ad9434_core.v +++ b/library/axi_ad9434/axi_ad9434_core.v @@ -109,8 +109,8 @@ module axi_ad9434_core ( output up_drp_sel; output up_drp_wr; output [11:0] up_drp_addr; - output [15:0] up_drp_wdata; - input [15:0] up_drp_rdata; + output [31:0] up_drp_wdata; + input [31:0] up_drp_rdata; input up_drp_ready; input up_drp_locked; @@ -246,7 +246,7 @@ module axi_ad9434_core ( .up_rack (up_rack_s[0])); up_adc_channel #( - .ADC_CHANNEL_ID(0)) + .CHANNEL_ID(0)) i_adc_channel( .adc_clk (adc_clk), .adc_rst (adc_rst), diff --git a/library/axi_ad9434/axi_ad9434_if.v b/library/axi_ad9434/axi_ad9434_if.v index ccfa4b86e..1d30a232c 100644 --- a/library/axi_ad9434/axi_ad9434_if.v +++ b/library/axi_ad9434/axi_ad9434_if.v @@ -124,8 +124,8 @@ module axi_ad9434_if ( input up_drp_sel; input up_drp_wr; input [11:0] up_drp_addr; - input [15:0] up_drp_wdata; - output [15:0] up_drp_rdata; + input [31:0] up_drp_wdata; + output [31:0] up_drp_rdata; output up_drp_ready; output up_drp_locked; @@ -147,37 +147,37 @@ module axi_ad9434_if ( assign adc_clk = adc_div_clk; // data interface - generate - for (l_inst = 0; l_inst <= 11; l_inst = l_inst + 1) begin : g_adc_if - ad_serdes_in #( - .DEVICE_TYPE(DEVICE_TYPE), - .IODELAY_CTRL(0), - .IODELAY_GROUP(IO_DELAY_GROUP), - .DDR_OR_SDR_N(SDR), - .DATA_WIDTH(4)) - i_adc_data ( - .rst(adc_rst), - .clk(adc_clk_in), - .div_clk(adc_div_clk), - .data_s0(adc_data[(3*12)+l_inst]), - .data_s1(adc_data[(2*12)+l_inst]), - .data_s2(adc_data[(1*12)+l_inst]), - .data_s3(adc_data[(0*12)+l_inst]), - .data_s4(), - .data_s5(), - .data_s6(), - .data_s7(), - .data_in_p(adc_data_in_p[l_inst]), - .data_in_n(adc_data_in_n[l_inst]), - .up_clk (up_clk), - .up_dld (up_adc_dld[l_inst]), - .up_dwdata (up_adc_dwdata[((l_inst*5)+4):(l_inst*5)]), - .up_drdata (up_adc_drdata[((l_inst*5)+4):(l_inst*5)]), - .delay_clk(delay_clk), - .delay_rst(delay_rst), - .delay_locked()); - end - endgenerate + ad_serdes_in #( + .DEVICE_TYPE(DEVICE_TYPE), + .IODELAY_CTRL(0), + .IODELAY_GROUP(IO_DELAY_GROUP), + .DDR_OR_SDR_N(SDR), + .DATA_WIDTH(12), + .SERDES_FACTOR(4)) + i_adc_data ( + .rst(adc_rst), + .clk(adc_clk_in), + .div_clk(adc_div_clk), + .loaden(1'b0), + .phase(8'b0), + .locked(1'b0), + .data_s0(adc_data[47:36]), + .data_s1(adc_data[35:24]), + .data_s2(adc_data[23:12]), + .data_s3(adc_data[11: 0]), + .data_s4(), + .data_s5(), + .data_s6(), + .data_s7(), + .data_in_p(adc_data_in_p), + .data_in_n(adc_data_in_n), + .up_clk (up_clk), + .up_dld (up_adc_dld[11:0]), + .up_dwdata (up_adc_dwdata[59:0]), + .up_drdata (up_adc_drdata[59:0]), + .delay_clk(delay_clk), + .delay_rst(delay_rst), + .delay_locked()); // over-range interface ad_serdes_in #( @@ -185,15 +185,19 @@ module axi_ad9434_if ( .IODELAY_CTRL(1), .IODELAY_GROUP(IO_DELAY_GROUP), .DDR_OR_SDR_N(SDR), - .DATA_WIDTH(4)) - i_adc_data ( + .DATA_WIDTH(1), + .SERDES_FACTOR(4)) + i_adc_or ( .rst(adc_rst), .clk(adc_clk_in), .div_clk(adc_div_clk), - .data_s0(adc_or_s[0]), - .data_s1(adc_or_s[1]), - .data_s2(adc_or_s[2]), - .data_s3(adc_or_s[3]), + .loaden(1'b0), + .phase(8'b0), + .locked(1'b0), + .data_s0(adc_or_s[3]), + .data_s1(adc_or_s[2]), + .data_s2(adc_or_s[1]), + .data_s3(adc_or_s[0]), .data_s4(), .data_s5(), .data_s6(), @@ -210,18 +214,22 @@ module axi_ad9434_if ( // clock input buffers and MMCM_OR_BUFR_N ad_serdes_clk #( - .MMCM_DEVICE_TYPE (DEVICE_TYPE), + .DEVICE_TYPE (DEVICE_TYPE), .MMCM_CLKIN_PERIOD (2), .MMCM_VCO_DIV (6), .MMCM_VCO_MUL (12), .MMCM_CLK0_DIV (2), - .MMCM_CLK1_DIV (8)) + .MMCM_CLK1_DIV (8), + .SERDES_FACTOR(4)) i_serdes_clk ( - .mmcm_rst (mmcm_rst), + .rst (mmcm_rst), .clk_in_p (adc_clk_in_p), .clk_in_n (adc_clk_in_n), .clk (adc_clk_in), .div_clk (adc_div_clk), + .out_clk (), + .loaden (), + .phase (), .up_clk (up_clk), .up_rstn (up_rstn), .up_drp_sel (up_drp_sel), @@ -232,7 +240,7 @@ module axi_ad9434_if ( .up_drp_ready (up_drp_ready), .up_drp_locked (up_drp_locked)); - // adc overange + // adc over range assign adc_or = adc_or_s[0] | adc_or_s[1] | adc_or_s[2] | adc_or_s[3]; // adc status: adc is up, if both the MMCM_OR_BUFR_N and DELAY blocks are up @@ -242,6 +250,7 @@ module axi_ad9434_if ( adc_status <= 1'b0; end else begin adc_status_m1 <= up_drp_locked & delay_locked; + adc_status <= adc_status_m1; end end diff --git a/library/axi_ad9434/axi_ad9434_ip.tcl b/library/axi_ad9434/axi_ad9434_ip.tcl index d13a1bbd6..7e9f4cb4f 100644 --- a/library/axi_ad9434/axi_ad9434_ip.tcl +++ b/library/axi_ad9434/axi_ad9434_ip.tcl @@ -5,9 +5,9 @@ source $ad_hdl_dir/library/scripts/adi_ip.tcl adi_ip_create axi_ad9434 adi_ip_files axi_ad9434 [list \ - "$ad_hdl_dir/library/common/ad_serdes_clk.v" \ - "$ad_hdl_dir/library/common/ad_mmcm_drp.v" \ - "$ad_hdl_dir/library/common/ad_serdes_in.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_serdes_clk.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_mmcm_drp.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_serdes_in.v" \ "$ad_hdl_dir/library/common/ad_datafmt.v" \ "$ad_hdl_dir/library/common/ad_rst.v" \ "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ diff --git a/library/axi_ad9467/Makefile b/library/axi_ad9467/Makefile index 1bd3c4919..56e03068e 100644 --- a/library/axi_ad9467/Makefile +++ b/library/axi_ad9467/Makefile @@ -5,27 +5,27 @@ #################################################################################### #################################################################################### -M_DEPS := axi_ad9467_ip.tcl -M_DEPS += ../scripts/adi_env.tcl -M_DEPS += ../scripts/adi_ip.tcl -M_DEPS += ../common/ad_rst.v -M_DEPS += ../common/ad_lvds_clk.v -M_DEPS += ../common/ad_lvds_in.v +M_DEPS += ../common/ad_axi_ip_constr.xdc M_DEPS += ../common/ad_datafmt.v M_DEPS += ../common/ad_pnmon.v -M_DEPS += ../common/up_xfer_status.v -M_DEPS += ../common/up_xfer_cntrl.v +M_DEPS += ../common/ad_rst.v +M_DEPS += ../common/up_adc_channel.v +M_DEPS += ../common/up_adc_common.v +M_DEPS += ../common/up_axi.v M_DEPS += ../common/up_clock_mon.v M_DEPS += ../common/up_delay_cntrl.v -M_DEPS += ../common/up_adc_common.v -M_DEPS += ../common/up_adc_channel.v -M_DEPS += ../common/up_axi.v -M_DEPS += ../common/ad_axi_ip_constr.xdc -M_DEPS += axi_ad9467_pnmon.v -M_DEPS += axi_ad9467_if.v +M_DEPS += ../common/up_xfer_cntrl.v +M_DEPS += ../common/up_xfer_status.v +M_DEPS += ../scripts/adi_env.tcl +M_DEPS += ../scripts/adi_ip.tcl +M_DEPS += ../xilinx/common/ad_lvds_clk.v +M_DEPS += ../xilinx/common/ad_lvds_in.v +M_DEPS += axi_ad9467.v M_DEPS += axi_ad9467_channel.v M_DEPS += axi_ad9467_constr.xdc -M_DEPS += axi_ad9467.v +M_DEPS += axi_ad9467_if.v +M_DEPS += axi_ad9467_ip.tcl +M_DEPS += axi_ad9467_pnmon.v M_VIVADO := vivado -mode batch -source @@ -36,6 +36,10 @@ M_FLIST += *.log M_FLIST += component.xml M_FLIST += *.jou M_FLIST += xgui +M_FLIST += *.ip_user_files +M_FLIST += *.srcs +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil @@ -52,7 +56,7 @@ clean-all: axi_ad9467.xpr: $(M_DEPS) - rm -rf $(M_FLIST) + -rm -rf $(M_FLIST) $(M_VIVADO) axi_ad9467_ip.tcl >> axi_ad9467_ip.log 2>&1 #################################################################################### diff --git a/library/axi_ad9467/axi_ad9467.v b/library/axi_ad9467/axi_ad9467.v index 63b1d4cbc..3d549a15c 100644 --- a/library/axi_ad9467/axi_ad9467.v +++ b/library/axi_ad9467/axi_ad9467.v @@ -69,6 +69,7 @@ module axi_ad9467( s_axi_aresetn, s_axi_awvalid, s_axi_awaddr, + s_axi_awprot, s_axi_awready, s_axi_wvalid, s_axi_wdata, @@ -79,6 +80,7 @@ module axi_ad9467( s_axi_bready, s_axi_arvalid, s_axi_araddr, + s_axi_arprot, s_axi_arready, s_axi_rvalid, s_axi_rresp, @@ -134,6 +136,9 @@ module axi_ad9467( output [ 1:0] s_axi_rresp; output [31:0] s_axi_rdata; input s_axi_rready; + input [ 2:0] s_axi_awprot; + input [ 2:0] s_axi_arprot; + // internal registers diff --git a/library/axi_ad9467/axi_ad9467_channel.v b/library/axi_ad9467/axi_ad9467_channel.v index 75eb42672..4ecb883f0 100644 --- a/library/axi_ad9467/axi_ad9467_channel.v +++ b/library/axi_ad9467/axi_ad9467_channel.v @@ -127,7 +127,7 @@ module axi_ad9467_channel( .dfmt_type(adc_dfmt_type_s), .dfmt_se(adc_dfmt_se_s)); - up_adc_channel #(.ADC_CHANNEL_ID(0)) i_up_adc_channel ( + up_adc_channel #(.CHANNEL_ID(0)) i_up_adc_channel ( .adc_clk (adc_clk), .adc_rst (adc_rst), .adc_enable (adc_enable), diff --git a/library/axi_ad9467/axi_ad9467_if.v b/library/axi_ad9467/axi_ad9467_if.v index d4379eb3c..0886dc693 100644 --- a/library/axi_ad9467/axi_ad9467_if.v +++ b/library/axi_ad9467/axi_ad9467_if.v @@ -209,6 +209,8 @@ module axi_ad9467_if ( ad_lvds_clk #( .DEVICE_TYPE (DEVICE_TYPE)) i_adc_clk ( + .rst (1'b0), + .locked (), .clk_in_p (adc_clk_in_p), .clk_in_n (adc_clk_in_n), .clk (adc_clk)); diff --git a/library/axi_ad9467/axi_ad9467_ip.tcl b/library/axi_ad9467/axi_ad9467_ip.tcl index 127effe37..1c61b680e 100644 --- a/library/axi_ad9467/axi_ad9467_ip.tcl +++ b/library/axi_ad9467/axi_ad9467_ip.tcl @@ -6,8 +6,8 @@ source $ad_hdl_dir/library/scripts/adi_ip.tcl adi_ip_create axi_ad9467 adi_ip_files axi_ad9467 [list \ "$ad_hdl_dir/library/common/ad_rst.v" \ - "$ad_hdl_dir/library/common/ad_lvds_clk.v" \ - "$ad_hdl_dir/library/common/ad_lvds_in.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_lvds_clk.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_lvds_in.v" \ "$ad_hdl_dir/library/common/ad_datafmt.v" \ "$ad_hdl_dir/library/common/ad_pnmon.v" \ "$ad_hdl_dir/library/common/up_xfer_status.v" \ diff --git a/library/axi_ad9625/Makefile b/library/axi_ad9625/Makefile index 23f0a474b..e7c9115e4 100644 --- a/library/axi_ad9625/Makefile +++ b/library/axi_ad9625/Makefile @@ -5,25 +5,26 @@ #################################################################################### #################################################################################### -M_DEPS := axi_ad9625_ip.tcl -M_DEPS += ../scripts/adi_env.tcl -M_DEPS += ../scripts/adi_ip.tcl -M_DEPS += ../common/ad_rst.v +M_DEPS += ../common/ad_axi_ip_constr.xdc +M_DEPS += ../common/ad_datafmt.v M_DEPS += ../common/ad_mem.v M_DEPS += ../common/ad_pnmon.v -M_DEPS += ../common/ad_datafmt.v +M_DEPS += ../common/ad_rst.v +M_DEPS += ../common/ad_xcvr_rx_if.v +M_DEPS += ../common/up_adc_channel.v +M_DEPS += ../common/up_adc_common.v M_DEPS += ../common/up_axi.v +M_DEPS += ../common/up_clock_mon.v M_DEPS += ../common/up_xfer_cntrl.v M_DEPS += ../common/up_xfer_status.v -M_DEPS += ../common/up_clock_mon.v -M_DEPS += ../common/up_adc_common.v -M_DEPS += ../common/up_adc_channel.v -M_DEPS += ../common/ad_axi_ip_constr.xdc -M_DEPS += axi_ad9625_pnmon.v -M_DEPS += axi_ad9625_channel.v -M_DEPS += axi_ad9625_if.v +M_DEPS += ../scripts/adi_env.tcl +M_DEPS += ../scripts/adi_ip.tcl M_DEPS += axi_ad9625.v +M_DEPS += axi_ad9625_channel.v M_DEPS += axi_ad9625_constr.xdc +M_DEPS += axi_ad9625_if.v +M_DEPS += axi_ad9625_ip.tcl +M_DEPS += axi_ad9625_pnmon.v M_VIVADO := vivado -mode batch -source @@ -34,6 +35,10 @@ M_FLIST += *.log M_FLIST += component.xml M_FLIST += *.jou M_FLIST += xgui +M_FLIST += *.ip_user_files +M_FLIST += *.srcs +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil @@ -50,7 +55,7 @@ clean-all: axi_ad9625.xpr: $(M_DEPS) - rm -rf $(M_FLIST) + -rm -rf $(M_FLIST) $(M_VIVADO) axi_ad9625_ip.tcl >> axi_ad9625_ip.log 2>&1 #################################################################################### diff --git a/library/axi_ad9625/axi_ad9625.v b/library/axi_ad9625/axi_ad9625.v index 9f7be37ba..59bdaa00b 100644 --- a/library/axi_ad9625/axi_ad9625.v +++ b/library/axi_ad9625/axi_ad9625.v @@ -34,8 +34,6 @@ // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // *************************************************************************** // *************************************************************************** -// *************************************************************************** -// *************************************************************************** `timescale 1ns/100ps @@ -45,7 +43,10 @@ module axi_ad9625 ( // rx_clk is (line-rate/40) rx_clk, + rx_sof, + rx_valid, rx_data, + rx_ready, // dma interface @@ -80,7 +81,9 @@ module axi_ad9625 ( s_axi_rvalid, s_axi_rresp, s_axi_rdata, - s_axi_rready); + s_axi_rready, + s_axi_awprot, + s_axi_arprot); parameter ID = 0; parameter DEVICE_TYPE = 0; @@ -90,7 +93,10 @@ module axi_ad9625 ( // rx_clk is (line-rate/40) input rx_clk; + input [ 3:0] rx_sof; + input rx_valid; input [255:0] rx_data; + output rx_ready; // dma interface @@ -126,6 +132,9 @@ module axi_ad9625 ( output [ 1:0] s_axi_rresp; output [ 31:0] s_axi_rdata; input s_axi_rready; + input [ 2:0] s_axi_awprot; + input [ 2:0] s_axi_arprot; + // internal registers @@ -161,6 +170,10 @@ module axi_ad9625 ( assign up_clk = s_axi_aclk; assign up_rstn = s_axi_aresetn; + // defaults + + assign rx_ready = 1'b1; + // processor read interface always @(negedge up_rstn or posedge up_clk) begin @@ -179,8 +192,12 @@ module axi_ad9625 ( assign adc_valid = 1'b1; - axi_ad9625_if #(.ID(ID)) i_if ( + axi_ad9625_if #( + .ID (ID), + .DEVICE_TYPE (DEVICE_TYPE)) + i_if ( .rx_clk (rx_clk), + .rx_sof (rx_sof), .rx_data (rx_data), .adc_clk (adc_clk), .adc_rst (adc_rst), @@ -227,7 +244,7 @@ module axi_ad9625 ( .adc_sync_status (1'd0), .adc_status_ovf (adc_dovf), .adc_status_unf (adc_dunf), - .adc_clk_ratio (32'd1), + .adc_clk_ratio (32'd16), .adc_start_code (), .adc_sync (), .up_status_pn_err (up_adc_pn_err_s), @@ -237,7 +254,7 @@ module axi_ad9625 ( .up_drp_wr (), .up_drp_addr (), .up_drp_wdata (), - .up_drp_rdata (16'd0), + .up_drp_rdata (32'd0), .up_drp_ready (1'd0), .up_drp_locked (1'd1), .up_usr_chanmax (), diff --git a/library/axi_ad9625/axi_ad9625_channel.v b/library/axi_ad9625/axi_ad9625_channel.v index 1b9c38960..e2f8460fc 100644 --- a/library/axi_ad9625/axi_ad9625_channel.v +++ b/library/axi_ad9625/axi_ad9625_channel.v @@ -131,7 +131,7 @@ module axi_ad9625_channel ( end endgenerate - up_adc_channel #(.ADC_CHANNEL_ID(0)) i_up_adc_channel ( + up_adc_channel #(.CHANNEL_ID(0)) i_up_adc_channel ( .adc_clk (adc_clk), .adc_rst (adc_rst), .adc_enable (adc_enable), diff --git a/library/axi_ad9625/axi_ad9625_if.v b/library/axi_ad9625/axi_ad9625_if.v index 51d2827ac..2e0f78f18 100644 --- a/library/axi_ad9625/axi_ad9625_if.v +++ b/library/axi_ad9625/axi_ad9625_if.v @@ -34,9 +34,6 @@ // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // *************************************************************************** // *************************************************************************** -// *************************************************************************** -// *************************************************************************** -// This is the LVDS/DDR interface `timescale 1ns/100ps @@ -46,6 +43,7 @@ module axi_ad9625_if ( // rx_clk is (line-rate/40) rx_clk, + rx_sof, rx_data, // adc data output @@ -59,12 +57,16 @@ module axi_ad9625_if ( adc_raddr_in, adc_raddr_out); + // parameters + parameter ID = 0; + parameter DEVICE_TYPE = 0; // jesd interface // rx_clk is ref_clk/4 input rx_clk; + input [ 3:0] rx_sof; input [255:0] rx_data; // adc data output @@ -119,6 +121,7 @@ module axi_ad9625_if ( wire [ 31:0] rx_data5_s; wire [ 31:0] rx_data6_s; wire [ 31:0] rx_data7_s; + wire [255:0] rx_data_s; // nothing much to do on clock & over-range @@ -198,14 +201,14 @@ module axi_ad9625_if ( assign adc_data_s01_s = {rx_data3_s[ 3: 0], rx_data2_s[ 7: 0], rx_data3_s[ 7: 4]}; assign adc_data_s00_s = {rx_data1_s[ 3: 0], rx_data0_s[ 7: 0], rx_data1_s[ 7: 4]}; - assign rx_data0_s = rx_data[ 31: 0]; - assign rx_data1_s = rx_data[ 63: 32]; - assign rx_data2_s = rx_data[ 95: 64]; - assign rx_data3_s = rx_data[127: 96]; - assign rx_data4_s = rx_data[159:128]; - assign rx_data5_s = rx_data[191:160]; - assign rx_data6_s = rx_data[223:192]; - assign rx_data7_s = rx_data[255:224]; + assign rx_data0_s = rx_data_s[ 31: 0]; + assign rx_data1_s = rx_data_s[ 63: 32]; + assign rx_data2_s = rx_data_s[ 95: 64]; + assign rx_data3_s = rx_data_s[127: 96]; + assign rx_data4_s = rx_data_s[159:128]; + assign rx_data5_s = rx_data_s[191:160]; + assign rx_data6_s = rx_data_s[223:192]; + assign rx_data7_s = rx_data_s[255:224]; // status @@ -228,6 +231,21 @@ module axi_ad9625_if ( .addrb (adc_raddr_s), .doutb (adc_rdata_s)); + // frame-alignment + + genvar n; + + generate + for (n = 0; n < 8; n = n + 1) begin: g_xcvr_if + ad_xcvr_rx_if #(.DEVICE_TYPE (DEVICE_TYPE)) i_xcvr_if ( + .rx_clk (rx_clk), + .rx_ip_sof (rx_sof), + .rx_ip_data (rx_data[((n*32)+31):(n*32)]), + .rx_sof (), + .rx_data (rx_data_s[((n*32)+31):(n*32)])); + end + endgenerate + endmodule // *************************************************************************** diff --git a/library/axi_ad9625/axi_ad9625_ip.tcl b/library/axi_ad9625/axi_ad9625_ip.tcl index c046b62ba..5500260f1 100644 --- a/library/axi_ad9625/axi_ad9625_ip.tcl +++ b/library/axi_ad9625/axi_ad9625_ip.tcl @@ -16,6 +16,7 @@ adi_ip_files axi_ad9625 [list \ "$ad_hdl_dir/library/common/up_adc_common.v" \ "$ad_hdl_dir/library/common/up_adc_channel.v" \ "$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc" \ + "$ad_hdl_dir/library/common/ad_xcvr_rx_if.v" \ "axi_ad9625_pnmon.v" \ "axi_ad9625_channel.v" \ "axi_ad9625_if.v" \ @@ -31,6 +32,7 @@ adi_ip_constraints axi_ad9625 [list \ set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]] set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]] set_property driver_value 0 [ipx::get_ports *raddr_in* -of_objects [ipx::current_core]] +set_property driver_value 0 [ipx::get_ports *rx_valid* -of_objects [ipx::current_core]] ipx::save_core [ipx::current_core] diff --git a/library/axi_ad9643/Makefile b/library/axi_ad9643/Makefile index f556924d4..a2cc20274 100644 --- a/library/axi_ad9643/Makefile +++ b/library/axi_ad9643/Makefile @@ -5,30 +5,30 @@ #################################################################################### #################################################################################### -M_DEPS := axi_ad9643_ip.tcl -M_DEPS += ../scripts/adi_env.tcl -M_DEPS += ../scripts/adi_ip.tcl -M_DEPS += ../common/ad_rst.v -M_DEPS += ../common/ad_mul.v -M_DEPS += ../common/ad_lvds_clk.v -M_DEPS += ../common/ad_lvds_in.v -M_DEPS += ../common/ad_pnmon.v +M_DEPS += ../common/ad_axi_ip_constr.xdc M_DEPS += ../common/ad_datafmt.v M_DEPS += ../common/ad_dcfilter.v M_DEPS += ../common/ad_iqcor.v +M_DEPS += ../common/ad_pnmon.v +M_DEPS += ../common/ad_rst.v +M_DEPS += ../common/up_adc_channel.v +M_DEPS += ../common/up_adc_common.v M_DEPS += ../common/up_axi.v -M_DEPS += ../common/up_xfer_cntrl.v -M_DEPS += ../common/up_xfer_status.v M_DEPS += ../common/up_clock_mon.v M_DEPS += ../common/up_delay_cntrl.v -M_DEPS += ../common/up_adc_common.v -M_DEPS += ../common/up_adc_channel.v -M_DEPS += ../common/ad_axi_ip_constr.xdc -M_DEPS += axi_ad9643_pnmon.v -M_DEPS += axi_ad9643_channel.v -M_DEPS += axi_ad9643_if.v -M_DEPS += axi_ad9643_constr.xdc +M_DEPS += ../common/up_xfer_cntrl.v +M_DEPS += ../common/up_xfer_status.v +M_DEPS += ../scripts/adi_env.tcl +M_DEPS += ../scripts/adi_ip.tcl +M_DEPS += ../xilinx/common/ad_lvds_clk.v +M_DEPS += ../xilinx/common/ad_lvds_in.v +M_DEPS += ../xilinx/common/ad_mul.v M_DEPS += axi_ad9643.v +M_DEPS += axi_ad9643_channel.v +M_DEPS += axi_ad9643_constr.xdc +M_DEPS += axi_ad9643_if.v +M_DEPS += axi_ad9643_ip.tcl +M_DEPS += axi_ad9643_pnmon.v M_VIVADO := vivado -mode batch -source @@ -39,6 +39,10 @@ M_FLIST += *.log M_FLIST += component.xml M_FLIST += *.jou M_FLIST += xgui +M_FLIST += *.ip_user_files +M_FLIST += *.srcs +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil @@ -55,7 +59,7 @@ clean-all: axi_ad9643.xpr: $(M_DEPS) - rm -rf $(M_FLIST) + -rm -rf $(M_FLIST) $(M_VIVADO) axi_ad9643_ip.tcl >> axi_ad9643_ip.log 2>&1 #################################################################################### diff --git a/library/axi_ad9643/axi_ad9643.v b/library/axi_ad9643/axi_ad9643.v index 58aba5e54..4fbb67a54 100644 --- a/library/axi_ad9643/axi_ad9643.v +++ b/library/axi_ad9643/axi_ad9643.v @@ -87,7 +87,9 @@ module axi_ad9643 ( s_axi_rvalid, s_axi_rresp, s_axi_rdata, - s_axi_rready); + s_axi_rready, + s_axi_awprot, + s_axi_arprot); // parameters @@ -145,6 +147,9 @@ module axi_ad9643 ( output [ 1:0] s_axi_rresp; output [31:0] s_axi_rdata; input s_axi_rready; + input [ 2:0] s_axi_awprot; + input [ 2:0] s_axi_arprot; + // internal registers @@ -330,7 +335,7 @@ module axi_ad9643 ( .up_drp_wr (), .up_drp_addr (), .up_drp_wdata (), - .up_drp_rdata (16'd0), + .up_drp_rdata (32'd0), .up_drp_ready (1'd0), .up_drp_locked (1'd1), .up_usr_chanmax (), diff --git a/library/axi_ad9643/axi_ad9643_channel.v b/library/axi_ad9643/axi_ad9643_channel.v index 093e05da1..78072d2ad 100644 --- a/library/axi_ad9643/axi_ad9643_channel.v +++ b/library/axi_ad9643/axi_ad9643_channel.v @@ -183,7 +183,7 @@ module axi_ad9643_channel ( end endgenerate - up_adc_channel #(.ADC_CHANNEL_ID(CHANNEL_ID)) i_up_adc_channel ( + up_adc_channel #(.CHANNEL_ID(CHANNEL_ID)) i_up_adc_channel ( .adc_clk (adc_clk), .adc_rst (adc_rst), .adc_enable (adc_enable), diff --git a/library/axi_ad9643/axi_ad9643_if.v b/library/axi_ad9643/axi_ad9643_if.v index fd6600489..b46678775 100644 --- a/library/axi_ad9643/axi_ad9643_if.v +++ b/library/axi_ad9643/axi_ad9643_if.v @@ -245,6 +245,8 @@ module axi_ad9643_if ( ad_lvds_clk #( .DEVICE_TYPE (DEVICE_TYPE)) i_adc_clk ( + .rst (1'b0), + .locked (), .clk_in_p (adc_clk_in_p), .clk_in_n (adc_clk_in_n), .clk (adc_clk)); diff --git a/library/axi_ad9643/axi_ad9643_ip.tcl b/library/axi_ad9643/axi_ad9643_ip.tcl index 51781ca0c..cbb5e2a9d 100644 --- a/library/axi_ad9643/axi_ad9643_ip.tcl +++ b/library/axi_ad9643/axi_ad9643_ip.tcl @@ -6,9 +6,9 @@ source $ad_hdl_dir/library/scripts/adi_ip.tcl adi_ip_create axi_ad9643 adi_ip_files axi_ad9643 [list \ "$ad_hdl_dir/library/common/ad_rst.v" \ - "$ad_hdl_dir/library/common/ad_mul.v" \ - "$ad_hdl_dir/library/common/ad_lvds_clk.v" \ - "$ad_hdl_dir/library/common/ad_lvds_in.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_mul.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_lvds_clk.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_lvds_in.v" \ "$ad_hdl_dir/library/common/ad_pnmon.v" \ "$ad_hdl_dir/library/common/ad_datafmt.v" \ "$ad_hdl_dir/library/common/ad_dcfilter.v" \ diff --git a/library/axi_ad9652/Makefile b/library/axi_ad9652/Makefile index 67cd73faf..baa78f217 100644 --- a/library/axi_ad9652/Makefile +++ b/library/axi_ad9652/Makefile @@ -5,29 +5,29 @@ #################################################################################### #################################################################################### -M_DEPS := axi_ad9652_ip.tcl -M_DEPS += ../scripts/adi_env.tcl -M_DEPS += ../scripts/adi_ip.tcl -M_DEPS += ../common/ad_rst.v -M_DEPS += ../common/ad_mul.v -M_DEPS += ../common/ad_lvds_clk.v -M_DEPS += ../common/ad_lvds_in.v -M_DEPS += ../common/ad_pnmon.v +M_DEPS += ../common/ad_axi_ip_constr.xdc M_DEPS += ../common/ad_dcfilter.v M_DEPS += ../common/ad_iqcor.v +M_DEPS += ../common/ad_pnmon.v +M_DEPS += ../common/ad_rst.v +M_DEPS += ../common/up_adc_channel.v +M_DEPS += ../common/up_adc_common.v M_DEPS += ../common/up_axi.v -M_DEPS += ../common/up_xfer_cntrl.v -M_DEPS += ../common/up_xfer_status.v M_DEPS += ../common/up_clock_mon.v M_DEPS += ../common/up_delay_cntrl.v -M_DEPS += ../common/up_adc_common.v -M_DEPS += ../common/up_adc_channel.v -M_DEPS += ../common/ad_axi_ip_constr.xdc -M_DEPS += axi_ad9652_pnmon.v -M_DEPS += axi_ad9652_channel.v -M_DEPS += axi_ad9652_if.v -M_DEPS += axi_ad9652_constr.xdc +M_DEPS += ../common/up_xfer_cntrl.v +M_DEPS += ../common/up_xfer_status.v +M_DEPS += ../scripts/adi_env.tcl +M_DEPS += ../scripts/adi_ip.tcl +M_DEPS += ../xilinx/common/ad_lvds_clk.v +M_DEPS += ../xilinx/common/ad_lvds_in.v +M_DEPS += ../xilinx/common/ad_mul.v M_DEPS += axi_ad9652.v +M_DEPS += axi_ad9652_channel.v +M_DEPS += axi_ad9652_constr.xdc +M_DEPS += axi_ad9652_if.v +M_DEPS += axi_ad9652_ip.tcl +M_DEPS += axi_ad9652_pnmon.v M_VIVADO := vivado -mode batch -source @@ -38,6 +38,10 @@ M_FLIST += *.log M_FLIST += component.xml M_FLIST += *.jou M_FLIST += xgui +M_FLIST += *.ip_user_files +M_FLIST += *.srcs +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil @@ -54,7 +58,7 @@ clean-all: axi_ad9652.xpr: $(M_DEPS) - rm -rf $(M_FLIST) + -rm -rf $(M_FLIST) $(M_VIVADO) axi_ad9652_ip.tcl >> axi_ad9652_ip.log 2>&1 #################################################################################### diff --git a/library/axi_ad9652/axi_ad9652.v b/library/axi_ad9652/axi_ad9652.v index 750c3c32a..4b51be6ea 100644 --- a/library/axi_ad9652/axi_ad9652.v +++ b/library/axi_ad9652/axi_ad9652.v @@ -87,7 +87,9 @@ module axi_ad9652 ( s_axi_rvalid, s_axi_rresp, s_axi_rdata, - s_axi_rready); + s_axi_rready, + s_axi_awprot, + s_axi_arprot); // parameters @@ -145,6 +147,9 @@ module axi_ad9652 ( output [ 1:0] s_axi_rresp; output [31:0] s_axi_rdata; input s_axi_rready; + input [ 2:0] s_axi_awprot; + input [ 2:0] s_axi_arprot; + // internal registers @@ -328,7 +333,7 @@ module axi_ad9652 ( .up_drp_wr (), .up_drp_addr (), .up_drp_wdata (), - .up_drp_rdata (16'd0), + .up_drp_rdata (32'd0), .up_drp_ready (1'd0), .up_drp_locked (1'd1), .up_usr_chanmax (), diff --git a/library/axi_ad9652/axi_ad9652_channel.v b/library/axi_ad9652/axi_ad9652_channel.v index 1c3f5adb5..63747b9de 100644 --- a/library/axi_ad9652/axi_ad9652_channel.v +++ b/library/axi_ad9652/axi_ad9652_channel.v @@ -165,7 +165,7 @@ module axi_ad9652_channel ( end endgenerate - up_adc_channel #(.ADC_CHANNEL_ID(CHANNEL_ID)) i_up_adc_channel ( + up_adc_channel #(.CHANNEL_ID(CHANNEL_ID)) i_up_adc_channel ( .adc_clk (adc_clk), .adc_rst (adc_rst), .adc_enable (adc_enable), diff --git a/library/axi_ad9652/axi_ad9652_if.v b/library/axi_ad9652/axi_ad9652_if.v index 86075ddd6..ad422c0d7 100644 --- a/library/axi_ad9652/axi_ad9652_if.v +++ b/library/axi_ad9652/axi_ad9652_if.v @@ -214,6 +214,8 @@ module axi_ad9652_if ( ad_lvds_clk #( .DEVICE_TYPE (DEVICE_TYPE)) i_adc_clk ( + .rst (1'b0), + .locked (), .clk_in_p (adc_clk_in_p), .clk_in_n (adc_clk_in_n), .clk (adc_clk)); diff --git a/library/axi_ad9652/axi_ad9652_ip.tcl b/library/axi_ad9652/axi_ad9652_ip.tcl index 5033b8b03..99bb266b9 100644 --- a/library/axi_ad9652/axi_ad9652_ip.tcl +++ b/library/axi_ad9652/axi_ad9652_ip.tcl @@ -6,9 +6,9 @@ source $ad_hdl_dir/library/scripts/adi_ip.tcl adi_ip_create axi_ad9652 adi_ip_files axi_ad9652 [list \ "$ad_hdl_dir/library/common/ad_rst.v" \ - "$ad_hdl_dir/library/common/ad_mul.v" \ - "$ad_hdl_dir/library/common/ad_lvds_clk.v" \ - "$ad_hdl_dir/library/common/ad_lvds_in.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_mul.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_lvds_clk.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_lvds_in.v" \ "$ad_hdl_dir/library/common/ad_pnmon.v" \ "$ad_hdl_dir/library/common/ad_dcfilter.v" \ "$ad_hdl_dir/library/common/ad_iqcor.v" \ diff --git a/library/axi_ad9671/Makefile b/library/axi_ad9671/Makefile index 954b0313f..f5424efcc 100644 --- a/library/axi_ad9671/Makefile +++ b/library/axi_ad9671/Makefile @@ -5,25 +5,26 @@ #################################################################################### #################################################################################### -M_DEPS := axi_ad9671_ip.tcl -M_DEPS += ../scripts/adi_env.tcl -M_DEPS += ../scripts/adi_ip.tcl -M_DEPS += ../common/ad_rst.v -M_DEPS += ../common/ad_pnmon.v +M_DEPS += ../common/ad_axi_ip_constr.xdc M_DEPS += ../common/ad_datafmt.v +M_DEPS += ../common/ad_mem.v +M_DEPS += ../common/ad_pnmon.v +M_DEPS += ../common/ad_rst.v +M_DEPS += ../common/ad_xcvr_rx_if.v +M_DEPS += ../common/up_adc_channel.v +M_DEPS += ../common/up_adc_common.v M_DEPS += ../common/up_axi.v +M_DEPS += ../common/up_clock_mon.v M_DEPS += ../common/up_xfer_cntrl.v M_DEPS += ../common/up_xfer_status.v -M_DEPS += ../common/up_clock_mon.v -M_DEPS += ../common/up_adc_common.v -M_DEPS += ../common/up_adc_channel.v -M_DEPS += ../common/ad_mem.v -M_DEPS += ../common/ad_axi_ip_constr.xdc -M_DEPS += axi_ad9671_pnmon.v -M_DEPS += axi_ad9671_channel.v -M_DEPS += axi_ad9671_if.v -M_DEPS += axi_ad9671_constr.xdc +M_DEPS += ../scripts/adi_env.tcl +M_DEPS += ../scripts/adi_ip.tcl M_DEPS += axi_ad9671.v +M_DEPS += axi_ad9671_channel.v +M_DEPS += axi_ad9671_constr.xdc +M_DEPS += axi_ad9671_if.v +M_DEPS += axi_ad9671_ip.tcl +M_DEPS += axi_ad9671_pnmon.v M_VIVADO := vivado -mode batch -source @@ -34,6 +35,10 @@ M_FLIST += *.log M_FLIST += component.xml M_FLIST += *.jou M_FLIST += xgui +M_FLIST += *.ip_user_files +M_FLIST += *.srcs +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil @@ -50,7 +55,7 @@ clean-all: axi_ad9671.xpr: $(M_DEPS) - rm -rf $(M_FLIST) + -rm -rf $(M_FLIST) $(M_VIVADO) axi_ad9671_ip.tcl >> axi_ad9671_ip.log 2>&1 #################################################################################### diff --git a/library/axi_ad9671/axi_ad9671.v b/library/axi_ad9671/axi_ad9671.v index 46406cfab..442476e08 100644 --- a/library/axi_ad9671/axi_ad9671.v +++ b/library/axi_ad9671/axi_ad9671.v @@ -34,8 +34,6 @@ // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // *************************************************************************** // *************************************************************************** -// *************************************************************************** -// *************************************************************************** `timescale 1ns/100ps @@ -45,8 +43,10 @@ module axi_ad9671 ( // rx_clk is (line-rate/40) rx_clk, - rx_data, rx_sof, + rx_valid, + rx_data, + rx_ready, // dma interface @@ -88,14 +88,15 @@ module axi_ad9671 ( parameter ID = 0; parameter DEVICE_TYPE = 0; parameter QUAD_OR_DUAL_N = 1; - parameter IO_DELAY_GROUP = "adc_if_delay_group"; // jesd interface // rx_clk is the jesd clock (ref_clk/2) input rx_clk; - input [(64*QUAD_OR_DUAL_N)+63:0] rx_data; - input rx_sof; + input [ 3:0] rx_sof; + input rx_valid; + input [(64*QUAD_OR_DUAL_N)+63:0] rx_data; + output rx_ready; // dma interface @@ -172,6 +173,7 @@ module axi_ad9671 ( // signal name changes + assign rx_ready = 1'b1; assign up_clk = s_axi_aclk; assign up_rstn = s_axi_aresetn; @@ -201,9 +203,10 @@ module axi_ad9671 ( // main (device interface) axi_ad9671_if #( - .QUAD_OR_DUAL_N(QUAD_OR_DUAL_N), - .ID(ID) - ) i_if ( + .QUAD_OR_DUAL_N (QUAD_OR_DUAL_N), + .ID (ID), + .DEVICE_TYPE (DEVICE_TYPE)) + i_if ( .rx_clk (rx_clk), .rx_data (rx_data), .rx_sof (rx_sof), @@ -232,8 +235,8 @@ module axi_ad9671 ( .adc_sync_out (adc_sync_out), .adc_sync_status (adc_sync_status_s), .adc_status (adc_status_s), - .adc_raddr_in(adc_raddr_in), - .adc_raddr_out(adc_raddr_out)); + .adc_raddr_in (adc_raddr_in), + .adc_raddr_out (adc_raddr_out)); // channels @@ -267,9 +270,7 @@ module axi_ad9671 ( // common processor control - up_adc_common #( - .ID(ID) - ) i_up_adc_common ( + up_adc_common #(.ID (ID)) i_up_adc_common ( .mmcm_rst (), .adc_clk (adc_clk), .adc_rst (adc_rst), @@ -290,7 +291,7 @@ module axi_ad9671 ( .up_drp_wr (), .up_drp_addr (), .up_drp_wdata (), - .up_drp_rdata (16'd0), + .up_drp_rdata (32'd0), .up_drp_ready (1'd0), .up_drp_locked (1'd1), .up_usr_chanmax (), @@ -310,9 +311,7 @@ module axi_ad9671 ( // up bus interface - up_axi #( - .ADDRESS_WIDTH (14) - ) i_up_axi ( + up_axi i_up_axi ( .up_rstn (up_rstn), .up_clk (up_clk), .up_axi_awvalid (s_axi_awvalid), diff --git a/library/axi_ad9671/axi_ad9671_channel.v b/library/axi_ad9671/axi_ad9671_channel.v index 939fe8cdf..68bd4778f 100644 --- a/library/axi_ad9671/axi_ad9671_channel.v +++ b/library/axi_ad9671/axi_ad9671_channel.v @@ -135,7 +135,7 @@ module axi_ad9671_channel ( .dfmt_type (adc_dfmt_type_s), .dfmt_se (adc_dfmt_se_s)); - up_adc_channel #(.ADC_CHANNEL_ID(CHANNEL_ID)) i_up_adc_channel ( + up_adc_channel #(.CHANNEL_ID(CHANNEL_ID)) i_up_adc_channel ( .adc_clk (adc_clk), .adc_rst (adc_rst), .adc_enable (adc_enable), diff --git a/library/axi_ad9671/axi_ad9671_hw.tcl b/library/axi_ad9671/axi_ad9671_hw.tcl index 4d03ba575..ea7c1995b 100644 --- a/library/axi_ad9671/axi_ad9671_hw.tcl +++ b/library/axi_ad9671/axi_ad9671_hw.tcl @@ -2,6 +2,7 @@ package require -exact qsys 14.0 source ../scripts/adi_env.tcl +source ../scripts/adi_ip_alt.tcl set_module_property NAME axi_ad9671 set_module_property DESCRIPTION "AXI AD9671 Interface" @@ -23,11 +24,13 @@ add_fileset_file up_clock_mon.v VERILOG PATH $ad_hdl_dir/library/common/up add_fileset_file up_delay_cntrl.v VERILOG PATH $ad_hdl_dir/library/common/up_delay_cntrl.v add_fileset_file up_adc_common.v VERILOG PATH $ad_hdl_dir/library/common/up_adc_common.v add_fileset_file up_adc_channel.v VERILOG PATH $ad_hdl_dir/library/common/up_adc_channel.v +add_fileset_file ad_xcvr_rx_if.v VERILOG PATH $ad_hdl_dir/library/common/ad_xcvr_rx_if.v add_fileset_file ad_mem.v VERILOG PATH $ad_hdl_dir/library/common/ad_mem.v add_fileset_file axi_ad9671_pnmon.v VERILOG PATH axi_ad9671_pnmon.v add_fileset_file axi_ad9671_if.v VERILOG PATH axi_ad9671_if.v add_fileset_file axi_ad9671_channel.v VERILOG PATH axi_ad9671_channel.v add_fileset_file axi_ad9671.v VERILOG PATH axi_ad9671.v TOP_LEVEL_FILE +add_fileset_file ad_axi_ip_constr.sdc SDC PATH $ad_hdl_dir/library/common/ad_axi_ip_constr.sdc # parameters @@ -65,7 +68,7 @@ add_interface s_axi axi4lite end set_interface_property s_axi associatedClock s_axi_clock set_interface_property s_axi associatedReset s_axi_reset add_interface_port s_axi s_axi_awvalid awvalid Input 1 -add_interface_port s_axi s_axi_awaddr awaddr Input 14 +add_interface_port s_axi s_axi_awaddr awaddr Input 16 add_interface_port s_axi s_axi_awprot awprot Input 3 add_interface_port s_axi s_axi_awready awready Output 1 add_interface_port s_axi s_axi_wvalid wvalid Input 1 @@ -76,7 +79,7 @@ add_interface_port s_axi s_axi_bvalid bvalid Output 1 add_interface_port s_axi s_axi_bresp bresp Output 2 add_interface_port s_axi s_axi_bready bready Input 1 add_interface_port s_axi s_axi_arvalid arvalid Input 1 -add_interface_port s_axi s_axi_araddr araddr Input 14 +add_interface_port s_axi s_axi_araddr araddr Input 16 add_interface_port s_axi s_axi_arprot arprot Input 3 add_interface_port s_axi s_axi_arready arready Output 1 add_interface_port s_axi s_axi_rvalid rvalid Output 1 @@ -86,31 +89,36 @@ add_interface_port s_axi s_axi_rready rready Input 1 # transceiver interface -add_interface xcvr_clk clock end -add_interface_port xcvr_clk rx_clk clk Input 1 +ad_alt_intf clock rx_clk input 1 +ad_alt_intf signal rx_sof input 4 export -add_interface xcvr_data conduit end -set_interface_property xcvr_data associatedClock xcvr_clk -add_interface_port xcvr_data rx_data data Input 64*QUAD_OR_DUAL_N+64 -add_interface_port xcvr_data rx_sof data_sof Input 1 +add_interface if_rx_data avalon_streaming sink +add_interface_port if_rx_data rx_data data input 64*QUAD_OR_DUAL_N+64 +add_interface_port if_rx_data rx_valid valid input 1 +add_interface_port if_rx_data rx_ready ready output 1 +set_interface_property if_rx_data associatedClock if_rx_clk +set_interface_property if_rx_data dataBitsPerSymbol 64 -add_interface xcvr_sync conduit end -set_interface_property xcvr_sync associatedClock xcvr_clk -add_interface_port xcvr_sync adc_sync_in sync_in Input 1 -add_interface_port xcvr_sync adc_sync_out sync_out Output 1 -add_interface_port xcvr_sync adc_raddr_in raddr_in Input 4 -add_interface_port xcvr_sync adc_raddr_out raddr_out Output 4 +add_interface if_sync conduit end +set_interface_property if_sync associatedClock if_clk +add_interface_port if_sync adc_sync_in sync_in Input 1 +add_interface_port if_sync adc_sync_out sync_out Output 1 +add_interface_port if_sync adc_raddr_in raddr_in Input 4 +add_interface_port if_sync adc_raddr_out raddr_out Output 4 # dma interface -add_interface adc_clock clock start -add_interface_port adc_clock adc_clk clk Output 1 +ad_alt_intf clock adc_clk output 1 +ad_alt_intf reset adc_rst output 1 if_adc_clk -add_interface adc_dma_if conduit end -set_interface_property adc_dma_if associatedClock adc_clock -add_interface_port adc_dma_if adc_valid valid Output 8 -add_interface_port adc_dma_if adc_enable enable Output 8 -add_interface_port adc_dma_if adc_data data Output 128 -add_interface_port adc_dma_if adc_dovf dovf Input 1 -add_interface_port adc_dma_if adc_dunf dunf Input 1 +add_interface adc_ch conduit end +add_interface_port adc_ch adc_enable enable Output 8 +add_interface_port adc_ch adc_valid valid Output 8 +add_interface_port adc_ch adc_data data Output 128 + +set_interface_property adc_ch associatedClock if_rx_clk +set_interface_property adc_ch associatedReset none + +ad_alt_intf signal adc_dovf input 1 ovf +ad_alt_intf signal adc_dunf input 1 unf diff --git a/library/axi_ad9671/axi_ad9671_if.v b/library/axi_ad9671/axi_ad9671_if.v index 4e838487f..9b8eaabb6 100644 --- a/library/axi_ad9671/axi_ad9671_if.v +++ b/library/axi_ad9671/axi_ad9671_if.v @@ -34,8 +34,6 @@ // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // *************************************************************************** // *************************************************************************** -// *************************************************************************** -// *************************************************************************** `timescale 1ns/100ps @@ -81,14 +79,15 @@ module axi_ad9671_if ( // parameters parameter QUAD_OR_DUAL_N = 1; + parameter DEVICE_TYPE = 0; parameter ID = 0; // jesd interface // rx_clk is (line-rate/40) input rx_clk; - input rx_sof; - input [(64*QUAD_OR_DUAL_N)+63:0] rx_data; + input [ 3:0] rx_sof; + input [(64*QUAD_OR_DUAL_N)+63:0] rx_data; // adc data output @@ -122,6 +121,8 @@ module axi_ad9671_if ( // internal wires + wire [(2*QUAD_OR_DUAL_N)+1:0] rx_sof_s; + wire [(64*QUAD_OR_DUAL_N)+63:0] rx_data_s; wire [127:0] adc_wdata; wire [127:0] adc_rdata; wire [ 15:0] adc_data_a_s; @@ -142,17 +143,16 @@ module axi_ad9671_if ( reg adc_status = 'd0; reg adc_sync_status = 'd0; reg rx_sof_d = 'd0; - reg [ 3:0] adc_waddr = 'd0; reg [ 3:0] adc_raddr_out = 'd0; - reg [ 15:0] adc_data_a; - reg [ 15:0] adc_data_b; - reg [ 15:0] adc_data_c; - reg [ 15:0] adc_data_d; - reg [ 15:0] adc_data_e; - reg [ 15:0] adc_data_f; - reg [ 15:0] adc_data_g; - reg [ 15:0] adc_data_h; + reg [ 15:0] adc_data_a = 'd0; + reg [ 15:0] adc_data_b = 'd0; + reg [ 15:0] adc_data_c = 'd0; + reg [ 15:0] adc_data_d = 'd0; + reg [ 15:0] adc_data_e = 'd0; + reg [ 15:0] adc_data_f = 'd0; + reg [ 15:0] adc_data_g = 'd0; + reg [ 15:0] adc_data_h = 'd0; // adc clock & valid @@ -219,12 +219,12 @@ module axi_ad9671_if ( always @(posedge rx_clk) begin if (QUAD_OR_DUAL_N == 1'b1) begin int_valid <= 1'b1; - int_data <= rx_data; + int_data <= rx_data_s; end else begin - rx_sof_d <= rx_sof; + rx_sof_d <= &rx_sof_s; int_valid <= rx_sof_d; - int_data[63:0] <= {rx_data[31:0], int_data[63:32]}; - int_data[127:64] <= {rx_data[63:32], int_data[127:96]}; + int_data[63:0] <= {rx_data_s[31: 0], int_data[ 63:32]}; + int_data[127:64] <= {rx_data_s[63:32], int_data[127:96]}; end end @@ -245,6 +245,21 @@ module axi_ad9671_if ( .addrb(adc_raddr_s), .doutb(adc_rdata)); + // frame-alignment + + genvar n; + + generate + for (n = 0; n < ((2*QUAD_OR_DUAL_N)+2); n = n + 1) begin: g_xcvr_if + ad_xcvr_rx_if #(.DEVICE_TYPE (DEVICE_TYPE)) i_xcvr_if ( + .rx_clk (rx_clk), + .rx_ip_sof (rx_sof), + .rx_ip_data (rx_data[((n*32)+31):(n*32)]), + .rx_sof (rx_sof_s[n]), + .rx_data (rx_data_s[((n*32)+31):(n*32)])); + end + endgenerate + endmodule // *************************************************************************** diff --git a/library/axi_ad9671/axi_ad9671_ip.tcl b/library/axi_ad9671/axi_ad9671_ip.tcl index a51cccfc9..f7ccf834b 100644 --- a/library/axi_ad9671/axi_ad9671_ip.tcl +++ b/library/axi_ad9671/axi_ad9671_ip.tcl @@ -15,6 +15,7 @@ adi_ip_files axi_ad9671 [list \ "$ad_hdl_dir/library/common/up_adc_common.v" \ "$ad_hdl_dir/library/common/up_adc_channel.v" \ "$ad_hdl_dir/library/common/ad_mem.v" \ + "$ad_hdl_dir/library/common/ad_xcvr_rx_if.v" \ "$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc" \ "axi_ad9671_pnmon.v" \ "axi_ad9671_channel.v" \ @@ -28,6 +29,7 @@ adi_ip_constraints axi_ad9671 [list \ "$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc" \ "axi_ad9671_constr.xdc" ] +set_property driver_value 0 [ipx::get_ports *rx_valid* -of_objects [ipx::current_core]] set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]] set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]] set_property driver_value 0 [ipx::get_ports *sync_in* -of_objects [ipx::current_core]] diff --git a/library/axi_ad9680/Makefile b/library/axi_ad9680/Makefile index 7eac51c70..6bf938799 100644 --- a/library/axi_ad9680/Makefile +++ b/library/axi_ad9680/Makefile @@ -5,23 +5,24 @@ #################################################################################### #################################################################################### -M_DEPS := axi_ad9680_ip.tcl -M_DEPS += ../scripts/adi_env.tcl -M_DEPS += ../scripts/adi_ip.tcl -M_DEPS += ../common/ad_rst.v -M_DEPS += ../common/ad_pnmon.v +M_DEPS += ../common/ad_axi_ip_constr.xdc M_DEPS += ../common/ad_datafmt.v +M_DEPS += ../common/ad_pnmon.v +M_DEPS += ../common/ad_rst.v +M_DEPS += ../common/ad_xcvr_rx_if.v +M_DEPS += ../common/up_adc_channel.v +M_DEPS += ../common/up_adc_common.v M_DEPS += ../common/up_axi.v +M_DEPS += ../common/up_clock_mon.v M_DEPS += ../common/up_xfer_cntrl.v M_DEPS += ../common/up_xfer_status.v -M_DEPS += ../common/up_clock_mon.v -M_DEPS += ../common/up_adc_common.v -M_DEPS += ../common/up_adc_channel.v -M_DEPS += axi_ad9680_pnmon.v +M_DEPS += ../scripts/adi_env.tcl +M_DEPS += ../scripts/adi_ip.tcl +M_DEPS += axi_ad9680.v M_DEPS += axi_ad9680_channel.v M_DEPS += axi_ad9680_if.v -M_DEPS += axi_ad9680.v -M_DEPS += ../common/ad_axi_ip_constr.xdc +M_DEPS += axi_ad9680_ip.tcl +M_DEPS += axi_ad9680_pnmon.v M_VIVADO := vivado -mode batch -source @@ -32,6 +33,10 @@ M_FLIST += *.log M_FLIST += component.xml M_FLIST += *.jou M_FLIST += xgui +M_FLIST += *.ip_user_files +M_FLIST += *.srcs +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil @@ -48,7 +53,7 @@ clean-all: axi_ad9680.xpr: $(M_DEPS) - rm -rf $(M_FLIST) + -rm -rf $(M_FLIST) $(M_VIVADO) axi_ad9680_ip.tcl >> axi_ad9680_ip.log 2>&1 #################################################################################### diff --git a/library/axi_ad9680/axi_ad9680.v b/library/axi_ad9680/axi_ad9680.v index 0e8b5125b..0f404143c 100644 --- a/library/axi_ad9680/axi_ad9680.v +++ b/library/axi_ad9680/axi_ad9680.v @@ -43,7 +43,10 @@ module axi_ad9680 ( // rx_clk is (line-rate/40) rx_clk, + rx_sof, + rx_valid, rx_data, + rx_ready, // dma interface @@ -89,7 +92,10 @@ module axi_ad9680 ( // rx_clk is (line-rate/40) input rx_clk; + input [ 3:0] rx_sof; + input rx_valid; input [127:0] rx_data; + output rx_ready; // dma interface @@ -170,6 +176,7 @@ module axi_ad9680 ( assign adc_valid_0 = 1'b1; assign adc_valid_1 = 1'b1; + assign rx_ready = 1'b1; // processor read interface @@ -193,8 +200,9 @@ module axi_ad9680 ( // main (device interface) - axi_ad9680_if i_if ( + axi_ad9680_if #(.DEVICE_TYPE (DEVICE_TYPE)) i_if ( .rx_clk (rx_clk), + .rx_sof (rx_sof), .rx_data (rx_data), .adc_clk (adc_clk), .adc_rst (adc_rst), @@ -206,7 +214,7 @@ module axi_ad9680 ( // channel - axi_ad9680_channel #(.Q_OR_I_N(0), .CHANNEL_ID(0)) i_channel_0 ( + axi_ad9680_channel #(.CHANNEL_ID(0)) i_channel_0 ( .adc_clk (adc_clk), .adc_rst (adc_rst), .adc_data (adc_data_a_s), @@ -229,7 +237,7 @@ module axi_ad9680 ( // channel - axi_ad9680_channel #(.Q_OR_I_N(1), .CHANNEL_ID(1)) i_channel_1 ( + axi_ad9680_channel #(.CHANNEL_ID(1)) i_channel_1 ( .adc_clk (adc_clk), .adc_rst (adc_rst), .adc_data (adc_data_b_s), @@ -273,7 +281,7 @@ module axi_ad9680 ( .up_drp_wr (), .up_drp_addr (), .up_drp_wdata (), - .up_drp_rdata (16'd0), + .up_drp_rdata (32'd0), .up_drp_ready (1'd0), .up_drp_locked (1'd1), .up_usr_chanmax (), diff --git a/library/axi_ad9680/axi_ad9680_channel.v b/library/axi_ad9680/axi_ad9680_channel.v index 0192f7e61..56b2dbe18 100644 --- a/library/axi_ad9680/axi_ad9680_channel.v +++ b/library/axi_ad9680/axi_ad9680_channel.v @@ -72,7 +72,6 @@ module axi_ad9680_channel ( // parameters - parameter Q_OR_I_N = 0; parameter CHANNEL_ID = 0; // adc interface @@ -136,7 +135,7 @@ module axi_ad9680_channel ( end endgenerate - up_adc_channel #(.ADC_CHANNEL_ID(CHANNEL_ID)) i_up_adc_channel ( + up_adc_channel #(.CHANNEL_ID(CHANNEL_ID)) i_up_adc_channel ( .adc_clk (adc_clk), .adc_rst (adc_rst), .adc_enable (adc_enable), diff --git a/library/axi_ad9680/axi_ad9680_hw.tcl b/library/axi_ad9680/axi_ad9680_hw.tcl index 4a91fa68c..3d91a4ecc 100755 --- a/library/axi_ad9680/axi_ad9680_hw.tcl +++ b/library/axi_ad9680/axi_ad9680_hw.tcl @@ -24,6 +24,7 @@ add_fileset_file up_clock_mon.v VERILOG PATH $ad_hdl_dir/library/common/up add_fileset_file up_delay_cntrl.v VERILOG PATH $ad_hdl_dir/library/common/up_delay_cntrl.v add_fileset_file up_adc_common.v VERILOG PATH $ad_hdl_dir/library/common/up_adc_common.v add_fileset_file up_adc_channel.v VERILOG PATH $ad_hdl_dir/library/common/up_adc_channel.v +add_fileset_file ad_xcvr_rx_if.v VERILOG PATH $ad_hdl_dir/library/common/ad_xcvr_rx_if.v add_fileset_file axi_ad9680_pnmon.v VERILOG PATH axi_ad9680_pnmon.v add_fileset_file axi_ad9680_channel.v VERILOG PATH axi_ad9680_channel.v add_fileset_file axi_ad9680_if.v VERILOG PATH axi_ad9680_if.v @@ -39,6 +40,13 @@ set_parameter_property ID TYPE INTEGER set_parameter_property ID UNITS None set_parameter_property ID HDL_PARAMETER true +add_parameter DEVICE_TYPE INTEGER 0 +set_parameter_property DEVICE_TYPE DEFAULT_VALUE 1 +set_parameter_property DEVICE_TYPE DISPLAY_NAME DEVICE_TYPE +set_parameter_property DEVICE_TYPE TYPE INTEGER +set_parameter_property DEVICE_TYPE UNITS None +set_parameter_property DEVICE_TYPE HDL_PARAMETER true + # axi4 slave add_interface s_axi_clock clock end @@ -74,22 +82,35 @@ add_interface_port s_axi s_axi_rready rready Input 1 # transceiver interface ad_alt_intf clock rx_clk input 1 -ad_alt_intf signal rx_data input 128 data +ad_alt_intf signal rx_sof input 4 export + +add_interface if_rx_data avalon_streaming sink +add_interface_port if_rx_data rx_data data input 128 +add_interface_port if_rx_data rx_valid valid input 1 +add_interface_port if_rx_data rx_ready ready output 1 +set_interface_property if_rx_data associatedClock if_rx_clk +set_interface_property if_rx_data dataBitsPerSymbol 128 # dma interface ad_alt_intf clock adc_clock output 1 -add_interface fifo_ch_0 conduit end -add_interface_port fifo_ch_0 adc_enable_0 enable Output 1 -add_interface_port fifo_ch_0 adc_valid_0 valid Output 1 -add_interface_port fifo_ch_0 adc_data_0 data Output 64 +add_interface adc_ch_0 conduit end +add_interface_port adc_ch_0 adc_enable_0 enable Output 1 +add_interface_port adc_ch_0 adc_valid_0 valid Output 1 +add_interface_port adc_ch_0 adc_data_0 data Output 64 -add_interface fifo_ch_1 conduit end -add_interface_port fifo_ch_1 adc_enable_1 enable Output 1 -add_interface_port fifo_ch_1 adc_valid_1 valid Output 1 -add_interface_port fifo_ch_1 adc_data_1 data Output 64 +set_interface_property adc_ch_0 associatedClock if_rx_clk +set_interface_property adc_ch_0 associatedReset none -ad_alt_intf signal adc_dovf input 1 -ad_alt_intf signal adc_dunf input 1 +add_interface adc_ch_1 conduit end +add_interface_port adc_ch_1 adc_enable_1 enable Output 1 +add_interface_port adc_ch_1 adc_valid_1 valid Output 1 +add_interface_port adc_ch_1 adc_data_1 data Output 64 + +set_interface_property adc_ch_1 associatedClock if_rx_clk +set_interface_property adc_ch_1 associatedReset none + +ad_alt_intf signal adc_dovf input 1 ovf +ad_alt_intf signal adc_dunf input 1 unf diff --git a/library/axi_ad9680/axi_ad9680_if.v b/library/axi_ad9680/axi_ad9680_if.v index d7309858d..14c71068e 100644 --- a/library/axi_ad9680/axi_ad9680_if.v +++ b/library/axi_ad9680/axi_ad9680_if.v @@ -34,9 +34,6 @@ // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // *************************************************************************** // *************************************************************************** -// *************************************************************************** -// *************************************************************************** -// This is the LVDS/DDR interface `timescale 1ns/100ps @@ -46,6 +43,7 @@ module axi_ad9680_if ( // rx_clk is (line-rate/40) rx_clk, + rx_sof, rx_data, // adc data output @@ -58,10 +56,15 @@ module axi_ad9680_if ( adc_or_b, adc_status); + // parameters + + parameter DEVICE_TYPE = 0; + // jesd interface // rx_clk is (line-rate/40) input rx_clk; + input [ 3:0] rx_sof; input [127:0] rx_data; // adc data output @@ -88,6 +91,7 @@ module axi_ad9680_if ( wire [15:0] adc_data_b_s2_s; wire [15:0] adc_data_b_s1_s; wire [15:0] adc_data_b_s0_s; + wire [127:0] rx_data_s; // adc clock is the reference clock @@ -105,15 +109,15 @@ module axi_ad9680_if ( // data multiplex - assign adc_data_a_s3_s = {rx_data[ 57: 56], rx_data[ 31: 24], rx_data[ 63: 58]}; - assign adc_data_a_s2_s = {rx_data[ 49: 48], rx_data[ 23: 16], rx_data[ 55: 50]}; - assign adc_data_a_s1_s = {rx_data[ 41: 40], rx_data[ 15: 8], rx_data[ 47: 42]}; - assign adc_data_a_s0_s = {rx_data[ 33: 32], rx_data[ 7: 0], rx_data[ 39: 34]}; + assign adc_data_a_s3_s = {rx_data_s[ 57: 56], rx_data_s[ 31: 24], rx_data_s[ 63: 58]}; + assign adc_data_a_s2_s = {rx_data_s[ 49: 48], rx_data_s[ 23: 16], rx_data_s[ 55: 50]}; + assign adc_data_a_s1_s = {rx_data_s[ 41: 40], rx_data_s[ 15: 8], rx_data_s[ 47: 42]}; + assign adc_data_a_s0_s = {rx_data_s[ 33: 32], rx_data_s[ 7: 0], rx_data_s[ 39: 34]}; - assign adc_data_b_s3_s = {rx_data[121:120], rx_data[ 95: 88], rx_data[127:122]}; - assign adc_data_b_s2_s = {rx_data[113:112], rx_data[ 87: 80], rx_data[119:114]}; - assign adc_data_b_s1_s = {rx_data[105:104], rx_data[ 79: 72], rx_data[111:106]}; - assign adc_data_b_s0_s = {rx_data[ 97: 96], rx_data[ 71: 64], rx_data[103: 98]}; + assign adc_data_b_s3_s = {rx_data_s[121:120], rx_data_s[ 95: 88], rx_data_s[127:122]}; + assign adc_data_b_s2_s = {rx_data_s[113:112], rx_data_s[ 87: 80], rx_data_s[119:114]}; + assign adc_data_b_s1_s = {rx_data_s[105:104], rx_data_s[ 79: 72], rx_data_s[111:106]}; + assign adc_data_b_s0_s = {rx_data_s[ 97: 96], rx_data_s[ 71: 64], rx_data_s[103: 98]}; // status @@ -125,6 +129,21 @@ module axi_ad9680_if ( end end + // frame-alignment + + genvar n; + + generate + for (n = 0; n < 4; n = n + 1) begin: g_xcvr_if + ad_xcvr_rx_if #(.DEVICE_TYPE (DEVICE_TYPE)) i_xcvr_if ( + .rx_clk (rx_clk), + .rx_ip_sof (rx_sof), + .rx_ip_data (rx_data[((n*32)+31):(n*32)]), + .rx_sof (), + .rx_data (rx_data_s[((n*32)+31):(n*32)])); + end + endgenerate + endmodule // *************************************************************************** diff --git a/library/axi_ad9680/axi_ad9680_ip.tcl b/library/axi_ad9680/axi_ad9680_ip.tcl index 7a045961e..29891e34d 100644 --- a/library/axi_ad9680/axi_ad9680_ip.tcl +++ b/library/axi_ad9680/axi_ad9680_ip.tcl @@ -14,6 +14,7 @@ adi_ip_files axi_ad9680 [list \ "$ad_hdl_dir/library/common/up_clock_mon.v" \ "$ad_hdl_dir/library/common/up_adc_common.v" \ "$ad_hdl_dir/library/common/up_adc_channel.v" \ + "$ad_hdl_dir/library/common/ad_xcvr_rx_if.v" \ "axi_ad9680_pnmon.v" \ "axi_ad9680_channel.v" \ "axi_ad9680_if.v" \ @@ -25,6 +26,7 @@ adi_ip_properties axi_ad9680 adi_ip_constraints axi_ad9680 [list \ "$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc" ] +set_property driver_value 0 [ipx::get_ports *rx_valid* -of_objects [ipx::current_core]] set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]] set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]] diff --git a/library/axi_ad9684/Makefile b/library/axi_ad9684/Makefile new file mode 100644 index 000000000..2a198b631 --- /dev/null +++ b/library/axi_ad9684/Makefile @@ -0,0 +1,64 @@ +#################################################################################### +#################################################################################### +## Copyright 2011(c) Analog Devices, Inc. +## Auto-generated, do not modify! +#################################################################################### +#################################################################################### + +M_DEPS += ../common/ad_axi_ip_constr.xdc +M_DEPS += ../common/ad_datafmt.v +M_DEPS += ../common/ad_pnmon.v +M_DEPS += ../common/ad_rst.v +M_DEPS += ../common/up_adc_channel.v +M_DEPS += ../common/up_adc_common.v +M_DEPS += ../common/up_axi.v +M_DEPS += ../common/up_clock_mon.v +M_DEPS += ../common/up_delay_cntrl.v +M_DEPS += ../common/up_xfer_cntrl.v +M_DEPS += ../common/up_xfer_status.v +M_DEPS += ../scripts/adi_env.tcl +M_DEPS += ../scripts/adi_ip.tcl +M_DEPS += ../xilinx/common/ad_mmcm_drp.v +M_DEPS += ../xilinx/common/ad_serdes_clk.v +M_DEPS += ../xilinx/common/ad_serdes_in.v +M_DEPS += axi_ad9684.v +M_DEPS += axi_ad9684_channel.v +M_DEPS += axi_ad9684_constr.xdc +M_DEPS += axi_ad9684_if.v +M_DEPS += axi_ad9684_ip.tcl +M_DEPS += axi_ad9684_pnmon.v + +M_VIVADO := vivado -mode batch -source + +M_FLIST := *.cache +M_FLIST += *.data +M_FLIST += *.xpr +M_FLIST += *.log +M_FLIST += component.xml +M_FLIST += *.jou +M_FLIST += xgui +M_FLIST += *.ip_user_files +M_FLIST += *.srcs +M_FLIST += *.hw +M_FLIST += *.sim +M_FLIST += .Xil + + + +.PHONY: all clean clean-all +all: axi_ad9684.xpr + + +clean:clean-all + + +clean-all: + rm -rf $(M_FLIST) + + +axi_ad9684.xpr: $(M_DEPS) + -rm -rf $(M_FLIST) + $(M_VIVADO) axi_ad9684_ip.tcl >> axi_ad9684_ip.log 2>&1 + +#################################################################################### +#################################################################################### diff --git a/library/axi_ad9684/axi_ad9684.v b/library/axi_ad9684/axi_ad9684.v new file mode 100644 index 000000000..b878bec4d --- /dev/null +++ b/library/axi_ad9684/axi_ad9684.v @@ -0,0 +1,409 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2015(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR +// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR +// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE +// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_ad9684 ( + + // device interface ports + + adc_clk_in_p, + adc_clk_in_n, + adc_data_in_p, + adc_data_in_n, + adc_data_or_p, + adc_data_or_n, + + // dma interface ports + + adc_clk, + adc_rst, + adc_valid_0, + adc_enable_0, + adc_data_0, + adc_valid_1, + adc_enable_1, + adc_data_1, + adc_dovf, + adc_dunf, + + // delay clock ports + + delay_clk, + + // axi slave interface ports + + s_axi_aclk, + s_axi_aresetn, + s_axi_awvalid, + s_axi_awaddr, + s_axi_awprot, + s_axi_awready, + s_axi_wvalid, + s_axi_wdata, + s_axi_wstrb, + s_axi_wready, + s_axi_bvalid, + s_axi_bresp, + s_axi_bready, + s_axi_arvalid, + s_axi_araddr, + s_axi_arprot, + s_axi_arready, + s_axi_rvalid, + s_axi_rresp, + s_axi_rdata, + s_axi_rready +); + + // parameters + + parameter ID = 0; + parameter DEVICE_TYPE = 0; + parameter IO_DELAY_GROUP = "dev_if_delay_group"; + parameter OR_STATUS = 1; + + // IO definitions + + input adc_clk_in_p; + input adc_clk_in_n; + input [13:0] adc_data_in_p; + input [13:0] adc_data_in_n; + input adc_data_or_p; + input adc_data_or_n; + + output adc_clk; + output adc_rst; + output adc_valid_0; + output adc_enable_0; + output [31:0] adc_data_0; + output adc_valid_1; + output adc_enable_1; + output [31:0] adc_data_1; + input adc_dovf; + input adc_dunf; + + input delay_clk; + + input s_axi_aclk; + input s_axi_aresetn; + input s_axi_awvalid; + input [31:0] s_axi_awaddr; + output s_axi_awready; + input s_axi_wvalid; + input [31:0] s_axi_wdata; + input [ 3:0] s_axi_wstrb; + output s_axi_wready; + output s_axi_bvalid; + output [ 1:0] s_axi_bresp; + input s_axi_bready; + input s_axi_arvalid; + input [31:0] s_axi_araddr; + output s_axi_arready; + output s_axi_rvalid; + output [ 1:0] s_axi_rresp; + output [31:0] s_axi_rdata; + input s_axi_rready; + input [ 2:0] s_axi_awprot; + input [ 2:0] s_axi_arprot; + + + // internal registers + + reg up_wack = 1'b0; + reg [31:0] up_rdata = 32'b0; + reg up_rack = 1'b0; + + // internal clocks & resets + + wire up_clk; + wire up_rstn; + wire delay_rst; + + // internal signals + + wire [55:0] adc_rawdata_s; + wire [27:0] adc_rawdata_0_s; + wire [27:0] adc_rawdata_1_s; + wire adc_or_0_s; + wire adc_or_1_s; + wire adc_status_s; + wire adc_or_s; + wire [14:0] up_dld_s; + wire [74:0] up_dwdata_s; + wire [74:0] up_drdata_s; + wire delay_locked_s; + wire up_status_pn_err_s; + wire up_status_pn_oos_s; + wire up_status_or_s; + wire [ 1:0] up_adc_pn_err_s; + wire [ 1:0] up_adc_pn_oos_s; + wire [ 1:0] up_adc_or_s; + wire up_rreq_s; + wire [13:0] up_raddr_s; + wire [31:0] up_rdata_s[0:3]; + wire up_rack_s[0:3]; + wire up_wack_s[0:3]; + wire up_wreq_s; + wire [13:0] up_waddr_s; + wire [31:0] up_wdata_s; + wire up_drp_sel_s; + wire up_drp_wr_s; + wire [11:0] up_drp_addr_s; + wire [31:0] up_drp_wdata_s; + wire [31:0] up_drp_rdata_s; + wire up_drp_ready_s; + wire up_drp_locked_s; + wire rst_s; + + //defaults + + assign up_clk = s_axi_aclk; + assign up_rstn = s_axi_aresetn; + assign adc_valid = 1'b1; + + // processor read interface + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_rdata <= 32'd0; + up_rack <= 1'd0; + up_wack <= 1'd0; + end else begin + up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2] | up_rdata_s[3]; + up_rack <= up_rack_s[0] | up_rack_s[1] | up_rack_s[2] | up_rack_s[3]; + up_wack <= up_wack_s[0] | up_wack_s[1] | up_wack_s[2] | up_wack_s[3]; + end + end + + // device interface instance + + axi_ad9684_if #( + .DEVICE_TYPE(DEVICE_TYPE), + .IO_DELAY_GROUP(IO_DELAY_GROUP), + .OR_STATUS (OR_STATUS)) + i_ad9684_if ( + .adc_clk_in_p (adc_clk_in_p), + .adc_clk_in_n (adc_clk_in_n), + .adc_data_in_p (adc_data_in_p), + .adc_data_in_n (adc_data_in_n), + .adc_data_or_p (adc_data_or_p), + .adc_data_or_n (adc_data_or_n), + .adc_clk (adc_clk), + .adc_rst (adc_rst), + .adc_data_a (adc_rawdata_0_s), + .adc_or_a (adc_or_0_s), + .adc_data_b (adc_rawdata_1_s), + .adc_or_b (adc_or_1_s), + .adc_status (adc_status_s), + .delay_clk (delay_clk), + .delay_rst (delay_rst), + .delay_dload (up_dld_s), + .delay_wdata (up_dwdata_s), + .delay_rdata (up_drdata_s), + .delay_locked (delay_locked_s), + .rst (rst_s), + .up_clk (up_clk), + .up_rstn (up_rstn), + .up_drp_sel (up_drp_sel_s), + .up_drp_wr (up_drp_wr_s), + .up_drp_addr (up_drp_addr_s), + .up_drp_wdata (up_drp_wdata_s), + .up_drp_rdata (up_drp_rdata_s), + .up_drp_ready (up_drp_ready_s), + .up_drp_locked (up_drp_locked_s)); + + // common processor control instance + + assign up_status_pn_err_s = up_adc_pn_err_s[0] | up_adc_pn_err_s[1]; + assign up_status_pn_oos_s = up_adc_pn_oos_s[0] | up_adc_pn_oos_s[1]; + assign up_status_or_s = up_adc_or_s[0] | up_adc_or_s[1]; + + up_adc_common #( + .ID(ID)) + i_up_adc_common ( + .mmcm_rst (rst_s), + .adc_clk (adc_clk), + .adc_rst (adc_rst), + .adc_r1_mode (), + .adc_ddr_edgesel (), + .adc_pin_mode (), + .adc_status (adc_status_s), + .adc_sync_status (1'd0), + .adc_status_ovf (adc_dovf), + .adc_status_unf (adc_dunf), + .adc_clk_ratio (32'b1), + .adc_start_code (), + .adc_sync (), + .up_status_pn_err (up_status_pn_err_s), + .up_status_pn_oos (up_status_pn_oos_s), + .up_status_or (up_status_or_s), + .up_drp_sel (up_drp_sel_s), + .up_drp_wr (up_drp_wr_s), + .up_drp_addr (up_drp_addr_s), + .up_drp_wdata (up_drp_wdata_s), + .up_drp_rdata (up_drp_rdata_s), + .up_drp_ready (up_drp_ready_s), + .up_drp_locked (up_drp_locked_s), + .up_usr_chanmax (), + .adc_usr_chanmax (8'd1), + .up_adc_gpio_in (32'd0), + .up_adc_gpio_out (), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack_s[0]), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata_s[0]), + .up_rack (up_rack_s[0])); + + // adc channel 0 instance + + axi_ad9684_channel #( + .CHANNEL_ID (0), + .Q_OR_I_N (0)) + i_channel_0 ( + .adc_clk (adc_clk), + .adc_rst (adc_rst), + .adc_data (adc_rawdata_0_s), + .adc_data_q (adc_rawdata_1_s), + .adc_or (adc_or_0_s), + .adc_dfmt_data (adc_data_0), + .adc_valid (adc_valid_0), + .adc_enable (adc_enable_0), + .up_adc_pn_err (up_adc_pn_err_s[0]), + .up_adc_pn_oos (up_adc_pn_oos_s[0]), + .up_adc_or (up_adc_or_s[0]), + .up_clk (up_clk), + .up_rstn (up_rstn), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack_s[1]), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata_s[1]), + .up_rack (up_rack_s[1])); + + // adc channel 1 instance + + axi_ad9684_channel #( + .CHANNEL_ID (1), + .Q_OR_I_N (1)) + i_channel_1 ( + .adc_clk (adc_clk), + .adc_rst (adc_rst), + .adc_data (adc_rawdata_1_s), + .adc_data_q (adc_rawdata_0_s), + .adc_or (adc_or_1_s), + .adc_dfmt_data (adc_data_1), + .adc_valid (adc_valid_1), + .adc_enable (adc_enable_1), + .up_adc_pn_err (up_adc_pn_err_s[1]), + .up_adc_pn_oos (up_adc_pn_oos_s[1]), + .up_adc_or (up_adc_or_s[1] ), + .up_clk (up_clk), + .up_rstn (up_rstn), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack_s[2]), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata_s[2]), + .up_rack (up_rack_s[2])); + + // adc delay control instance + + up_delay_cntrl #( + .DATA_WIDTH(15)) + i_delay_cntrl ( + .delay_clk (delay_clk), + .delay_rst (delay_rst), + .delay_locked (delay_locked_s), + .up_dld (up_dld_s), + .up_dwdata (up_dwdata_s), + .up_drdata (up_drdata_s), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack_s[3]), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata_s[3]), + .up_rack (up_rack_s[3])); + + // uP bus interface instance + + up_axi i_up_axi ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_axi_awvalid (s_axi_awvalid), + .up_axi_awaddr (s_axi_awaddr), + .up_axi_awready (s_axi_awready), + .up_axi_wvalid (s_axi_wvalid), + .up_axi_wdata (s_axi_wdata), + .up_axi_wstrb (s_axi_wstrb), + .up_axi_wready (s_axi_wready), + .up_axi_bvalid (s_axi_bvalid), + .up_axi_bresp (s_axi_bresp), + .up_axi_bready (s_axi_bready), + .up_axi_arvalid (s_axi_arvalid), + .up_axi_araddr (s_axi_araddr), + .up_axi_arready (s_axi_arready), + .up_axi_rvalid (s_axi_rvalid), + .up_axi_rresp (s_axi_rresp), + .up_axi_rdata (s_axi_rdata), + .up_axi_rready (s_axi_rready), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata), + .up_rack (up_rack)); + +endmodule diff --git a/library/axi_ad9684/axi_ad9684_channel.v b/library/axi_ad9684/axi_ad9684_channel.v new file mode 100644 index 000000000..04b99873c --- /dev/null +++ b/library/axi_ad9684/axi_ad9684_channel.v @@ -0,0 +1,191 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2015(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR +// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR +// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE +// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_ad9684_channel ( + + // adc data interface + + adc_clk, + adc_rst, + adc_data, + adc_data_q, + adc_or, + + // channel interface + + adc_dfmt_data, + adc_valid, + adc_enable, + up_adc_pn_err, + up_adc_pn_oos, + up_adc_or, + + // up interface + + up_clk, + up_rstn, + up_wreq, + up_waddr, + up_wdata, + up_wack, + up_rreq, + up_raddr, + up_rdata, + up_rack +); + + // parameters + + parameter Q_OR_I_N = 0; + parameter CHANNEL_ID = 0; + parameter DATAPATH_DISABLE = 0; + + // IO definitions + + input adc_clk; + input adc_rst; + input [27:0] adc_data; + input [27:0] adc_data_q; + input adc_or; + + output [31:0] adc_dfmt_data; + output adc_enable; + output adc_valid; + output up_adc_pn_err; + output up_adc_pn_oos; + output up_adc_or; + + input up_clk; + input up_rstn; + input up_wreq; + input [13:0] up_waddr; + input [31:0] up_wdata; + output up_wack; + input up_rreq; + input [13:0] up_raddr; + output [31:0] up_rdata; + output up_rack; + + // internal signals + + wire adc_pn_oos_s; + wire adc_pn_err_s; + wire adc_dfmt_enable_s; + wire adc_dfmt_type_s; + wire adc_dfmt_se_s; + wire [ 1:0] adc_dfmt_valid_s; + wire [ 3:0] adc_pnseq_sel_s; + + // instantiations + + axi_ad9684_pnmon i_pnmon ( + .adc_clk (adc_clk), + .adc_data (adc_data), + .adc_pn_oos (adc_pn_oos_s), + .adc_pn_err (adc_pn_err_s), + .adc_pnseq_sel (adc_pnseq_sel_s)); + + genvar n; + generate + for (n = 0; n < 2; n = n + 1) begin: g_ad_datafmt_1 + ad_datafmt #(.DATA_WIDTH(14)) i_ad_datafmt ( + .clk (adc_clk), + .valid (1'b1), + .data (adc_data[n*14+13:n*14]), + .valid_out (adc_dfmt_valid_s[n]), + .data_out (adc_dfmt_data[n*16+15:n*16]), + .dfmt_enable (adc_dfmt_enable_s), + .dfmt_type (adc_dfmt_type_s), + .dfmt_se (adc_dfmt_se_s)); + end + endgenerate + + assign adc_valid = adc_dfmt_valid_s[0] | adc_dfmt_valid_s[1]; + + up_adc_channel #(.CHANNEL_ID(CHANNEL_ID)) i_up_adc_channel ( + .adc_clk (adc_clk), + .adc_rst (adc_rst), + .adc_enable (adc_enable), + .adc_iqcor_enb (), + .adc_dcfilt_enb (), + .adc_dfmt_se (adc_dfmt_se_s), + .adc_dfmt_type (adc_dfmt_type_s), + .adc_dfmt_enable (adc_dfmt_enable_s), + .adc_dcfilt_offset (), + .adc_dcfilt_coeff (), + .adc_iqcor_coeff_1 (), + .adc_iqcor_coeff_2 (), + .adc_pnseq_sel (adc_pnseq_sel_s), + .adc_data_sel (), + .adc_pn_err (adc_pn_err_s), + .adc_pn_oos (adc_pn_oos_s), + .adc_or (adc_or), + .up_adc_pn_err (up_adc_pn_err), + .up_adc_pn_oos (up_adc_pn_oos), + .up_adc_or (up_adc_or), + .up_usr_datatype_be (), + .up_usr_datatype_signed (), + .up_usr_datatype_shift (), + .up_usr_datatype_total_bits (), + .up_usr_datatype_bits (), + .up_usr_decimation_m (), + .up_usr_decimation_n (), + .adc_usr_datatype_be (1'b0), + .adc_usr_datatype_signed (1'b1), + .adc_usr_datatype_shift (8'd0), + .adc_usr_datatype_total_bits (8'd16), + .adc_usr_datatype_bits (8'd16), + .adc_usr_decimation_m (16'd1), + .adc_usr_decimation_n (16'd1), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata), + .up_rack (up_rack)); + +endmodule + diff --git a/library/axi_ad9684/axi_ad9684_constr.sdc b/library/axi_ad9684/axi_ad9684_constr.sdc new file mode 100644 index 000000000..e69de29bb diff --git a/library/axi_ad9684/axi_ad9684_constr.xdc b/library/axi_ad9684/axi_ad9684_constr.xdc new file mode 100644 index 000000000..fa9ce5ae5 --- /dev/null +++ b/library/axi_ad9684/axi_ad9684_constr.xdc @@ -0,0 +1 @@ +set_false_path -from [get_cells -hier -filter {name =~ *up_drp_locked_reg && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *adc_status_m1_reg && IS_SEQUENTIAL}] diff --git a/library/axi_ad9684/axi_ad9684_hw.tcl b/library/axi_ad9684/axi_ad9684_hw.tcl new file mode 100644 index 000000000..a6ffcedd5 --- /dev/null +++ b/library/axi_ad9684/axi_ad9684_hw.tcl @@ -0,0 +1,119 @@ + +package require -exact qsys 13.0 +source ../scripts/adi_env.tcl +source ../scripts/adi_ip_alt.tcl + +ad_ip_create axi_ad9684 {AXI AD9684 Interface} axi_ad9684_elab +ad_ip_files axi_ad9684 [list \ + $ad_hdl_dir/library/common/ad_rst.v \ + $ad_hdl_dir/library/common/ad_datafmt.v \ + $ad_hdl_dir/library/common/ad_pnmon.v \ + $ad_hdl_dir/library/common/up_xfer_status.v \ + $ad_hdl_dir/library/common/up_xfer_cntrl.v \ + $ad_hdl_dir/library/common/up_clock_mon.v \ + $ad_hdl_dir/library/common/up_delay_cntrl.v \ + $ad_hdl_dir/library/common/up_adc_common.v \ + $ad_hdl_dir/library/common/up_adc_channel.v \ + $ad_hdl_dir/library/common/up_axi.v \ + axi_ad9684_pnmon.v \ + axi_ad9684_if.v \ + axi_ad9684_channel.v \ + axi_ad9684.v \ + $ad_hdl_dir/library/common/ad_axi_ip_constr.sdc \ + axi_ad9684_constr.sdc] \ + axi_ad9684_fileset + +# parameters + +add_parameter ID INTEGER 0 +set_parameter_property ID DEFAULT_VALUE 0 +set_parameter_property ID DISPLAY_NAME ID +set_parameter_property ID TYPE INTEGER +set_parameter_property ID DESCRIPTION "Instance ID" +set_parameter_property ID UNITS None +set_parameter_property ID HDL_PARAMETER true + +add_parameter DEVICE_TYPE INTEGER 0 +set_parameter_property DEVICE_TYPE DEFAULT_VALUE 0 +set_parameter_property DEVICE_TYPE DISPLAY_NAME DEVICE_TYPE +set_parameter_property DEVICE_TYPE TYPE INTEGER +set_parameter_property DEVICE_TYPE DESCRIPTION "Specify the FPGA device type" +set_parameter_property DEVICE_TYPE UNITS None +set_parameter_property DEVICE_TYPE HDL_PARAMETER true + +add_parameter OR_STATUS INTEGER 1 +set_parameter_property OR_STATUS DEFAULT_VALUE 1 +set_parameter_property OR_STATUS DISPLAY_NAME OR_STATUS +set_parameter_property OR_STATUS TYPE INTEGER +set_parameter_property OR_STATUS DESCRIPTION "This parameter enables the OVER RANGE line at the physical interface" +set_parameter_property OR_STATUS UNITS None +set_parameter_property OR_STATUS HDL_PARAMETER true + +# axi4 slave + +ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn + +# adc device interface + +add_interface device_if conduit end +set_interface_property device_if associatedClock none +set_interface_property device_if associatedReset none + +add_interface_port device_if adc_clk_in_p adc_clk_in_p Input 1 +add_interface_port device_if adc_clk_in_n adc_clk_in_n Input 1 +add_interface_port device_if adc_data_in_p adc_data_in_p Input 14 +add_interface_port device_if adc_data_in_n adc_data_in_n Input 14 + +# dma interface + +ad_alt_intf clock adc_clk output 1 +ad_alt_intf reset adc_rst output 1 if_adc_clk + +add_interface adc_ch_0 conduit end +add_interface_port adc_ch_0 adc_valid_0 valid Output 1 +add_interface_port adc_ch_0 adc_enable_0 enable Output 1 +add_interface_port adc_ch_0 adc_data_0 data Output 32 +set_interface_property adc_ch_0 associatedClock if_adc_clk +set_interface_property adc_ch_0 associatedReset none + +add_interface adc_ch_1 conduit end +add_interface_port adc_ch_1 adc_valid_1 valid Output 1 +add_interface_port adc_ch_1 adc_enable_1 enable Output 1 +add_interface_port adc_ch_1 adc_data_1 data Output 32 +set_interface_property adc_ch_1 associatedClock if_adc_clk +set_interface_property adc_ch_1 associatedReset none + +ad_alt_intf signal adc_dovf input 1 ovf +ad_alt_intf signal adc_dunf input 1 unf + +# SERDES instances and configurations + +add_hdl_instance ad_serdes_clk_core_rx alt_serdes +set_instance_parameter_value ad_serdes_clk_core_rx {MODE} {CLK} +set_instance_parameter_value ad_serdes_clk_core_rx {DDR_OR_SDR_N} {1} +set_instance_parameter_value ad_serdes_clk_core_rx {SERDES_FACTOR} {4} +set_instance_parameter_value ad_serdes_clk_core_rx {CLKIN_FREQUENCY} {500.0} + +add_hdl_instance ad_serdes_in_core alt_serdes +set_instance_parameter_value ad_serdes_in_core {MODE} {IN} +set_instance_parameter_value ad_serdes_in_core {DDR_OR_SDR_N} {1} +set_instance_parameter_value ad_serdes_in_core {SERDES_FACTOR} {4} +set_instance_parameter_value ad_serdes_in_core {CLKIN_FREQUENCY} {500.0} + +proc axi_ad9684_elab {} { + + set or_status [get_parameter_value OR_STATUS] + + if {$or_status == 1} { + add_interface_port device_if adc_data_or_p adc_data_or_p Input 1 + add_interface_port device_if adc_data_or_n adc_data_or_n Input 1 + } +} + +proc axi_ad9684_fileset { entityName } { + + ad_ip_modfile ad_serdes_in.v ad_serdes_in.v ad_serdes_in_core + ad_ip_modfile ad_serdes_clk.v ad_serdes_clk.v ad_serdes_clk_core_rx + +} + diff --git a/library/axi_ad9684/axi_ad9684_if.v b/library/axi_ad9684/axi_ad9684_if.v new file mode 100644 index 000000000..58e91058c --- /dev/null +++ b/library/axi_ad9684/axi_ad9684_if.v @@ -0,0 +1,267 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2015(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR +// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR +// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE +// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_ad9684_if ( + + // device interface + adc_clk_in_p, + adc_clk_in_n, + adc_data_in_p, + adc_data_in_n, + adc_data_or_p, + adc_data_or_n, + + // data interface + adc_clk, + adc_rst, + adc_data_a, + adc_or_a, + adc_data_b, + adc_or_b, + adc_status, + + // delay interface + delay_clk, + delay_rst, + delay_dload, + delay_wdata, + delay_rdata, + delay_locked, + + // reset + rst, + + // drp interface + up_clk, + up_rstn, + up_drp_sel, + up_drp_wr, + up_drp_addr, + up_drp_wdata, + up_drp_rdata, + up_drp_ready, + up_drp_locked +); + + // parameters + parameter DEVICE_TYPE = 0; // 0 - 7Series / 1 - 6Series + parameter IO_DELAY_GROUP = "dev_if_delay_group"; + parameter OR_STATUS = 0; + + // buffer type based on the target device + localparam DDR_OR_SDR_N = 1; + + // IO definitions + + input adc_clk_in_p; + input adc_clk_in_n; + input [13:0] adc_data_in_p; + input [13:0] adc_data_in_n; + input adc_data_or_p; + input adc_data_or_n; + + output adc_clk; + input adc_rst; + output [27:0] adc_data_a; + output adc_or_a; + output [27:0] adc_data_b; + output adc_or_b; + output adc_status; + + input delay_clk; + input delay_rst; + input [14:0] delay_dload; + input [74:0] delay_wdata; + output [74:0] delay_rdata; + output delay_locked; + + input rst; + + input up_clk; + input up_rstn; + input up_drp_sel; + input up_drp_wr; + input [11:0] up_drp_addr; + input [31:0] up_drp_wdata; + output [31:0] up_drp_rdata; + output up_drp_ready; + output up_drp_locked; + + // internal registers + + reg adc_status = 'd0; + reg adc_status_m1 = 'd0; + + // internal signals + + wire adc_clk_in; + wire adc_div_clk; + wire [ 1:0] adc_data_or_a_s; + wire [ 1:0] adc_data_or_b_s; + wire loaden_s; + wire [ 7:0] phase_s; + + + genvar l_inst; + + // adc_clk is 1:2 of the sampling clock + // f_max = 250 MHz + + assign adc_clk = adc_div_clk; + + // data interface + + ad_serdes_in #( + .DEVICE_TYPE(DEVICE_TYPE), + .IODELAY_CTRL(1), + .IODELAY_GROUP(IO_DELAY_GROUP), + .DDR_OR_SDR_N(DDR_OR_SDR_N), + .DATA_WIDTH(14)) + i_adc_data ( + .rst(adc_rst), + .clk(adc_clk_in), + .div_clk(adc_div_clk), + .loaden(loaden_s), + .phase(phase_s), + .locked(1'b0), + .data_s0(adc_data_b[27:14]), + .data_s1(adc_data_a[27:14]), + .data_s2(adc_data_b[13: 0]), + .data_s3(adc_data_a[13: 0]), + .data_s4(), + .data_s5(), + .data_s6(), + .data_s7(), + .data_in_p(adc_data_in_p[13:0]), + .data_in_n(adc_data_in_n[13:0]), + .up_clk (up_clk), + .up_dld (delay_dload[13:0]), + .up_dwdata (delay_wdata[69:0]), + .up_drdata (delay_rdata[69:0]), + .delay_clk(delay_clk), + .delay_rst(delay_rst), + .delay_locked(delay_locked)); + + generate if (OR_STATUS == 1) begin + + ad_serdes_in #( + .DEVICE_TYPE(DEVICE_TYPE), + .IODELAY_CTRL(0), + .IODELAY_GROUP(IO_DELAY_GROUP), + .DDR_OR_SDR_N(DDR_OR_SDR_N), + .DATA_WIDTH(1)) + i_adc_or ( + .rst(adc_rst), + .clk(adc_clk_in), + .div_clk(adc_div_clk), + .loaden(loaden_s), + .phase(phase_s), + .locked(1'b0), + .data_s0(adc_data_or_b_s[1]), + .data_s1(adc_data_or_a_s[1]), + .data_s2(adc_data_or_b_s[0]), + .data_s3(adc_data_or_a_s[0]), + .data_s4(), + .data_s5(), + .data_s6(), + .data_s7(), + .data_in_p(adc_data_or_p), + .data_in_n(adc_data_or_n), + .up_clk (up_clk), + .up_dld (delay_dload[14]), + .up_dwdata (delay_wdata[74:70]), + .up_drdata (delay_rdata[74:70]), + .delay_clk(delay_clk), + .delay_rst(delay_rst), + .delay_locked()); + + assign adc_or_a = adc_data_or_a_s[0] | adc_data_or_a_s[1]; + assign adc_or_b = adc_data_or_b_s[0] | adc_data_or_b_s[1]; + + end else begin + + assign adc_or_a = 1'b0; + assign adc_or_b = 1'b0; + + end + endgenerate + + // clock input buffers and MMCM_OR_BUFR_N + + ad_serdes_clk #( + .DEVICE_TYPE (DEVICE_TYPE), + .MMCM_CLKIN_PERIOD (2), + .MMCM_VCO_DIV (6), + .MMCM_VCO_MUL (12), + .MMCM_CLK0_DIV (2), + .MMCM_CLK1_DIV (4)) + i_serdes_clk ( + .rst (rst), + .clk_in_p (adc_clk_in_p), + .clk_in_n (adc_clk_in_n), + .clk (adc_clk_in), + .div_clk (adc_div_clk), + .out_clk (), + .loaden (loaden_s), + .phase (phase_s), + .up_clk (up_clk), + .up_rstn (up_rstn), + .up_drp_sel (up_drp_sel), + .up_drp_wr (up_drp_wr), + .up_drp_addr (up_drp_addr), + .up_drp_wdata (up_drp_wdata), + .up_drp_rdata (up_drp_rdata), + .up_drp_ready (up_drp_ready), + .up_drp_locked (up_drp_locked)); + + // adc status: adc is up, if both the MMCM_OR_BUFR_N and DELAY blocks are up + always @(posedge adc_div_clk) begin + if(adc_rst == 1'b1) begin + adc_status_m1 <= 1'b0; + adc_status <= 1'b0; + end else begin + adc_status_m1 <= up_drp_locked; + adc_status <= adc_status_m1; + end + end + +endmodule diff --git a/library/axi_ad9684/axi_ad9684_ip.tcl b/library/axi_ad9684/axi_ad9684_ip.tcl new file mode 100644 index 000000000..3ad31474e --- /dev/null +++ b/library/axi_ad9684/axi_ad9684_ip.tcl @@ -0,0 +1,38 @@ + +# ip + +source ../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip.tcl + +adi_ip_create axi_ad9684 +adi_ip_files axi_ad9684 [list \ + "$ad_hdl_dir/library/common/ad_rst.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_serdes_in.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_serdes_clk.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_mmcm_drp.v" \ + "$ad_hdl_dir/library/common/ad_datafmt.v" \ + "$ad_hdl_dir/library/common/ad_pnmon.v" \ + "$ad_hdl_dir/library/common/up_xfer_status.v" \ + "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ + "$ad_hdl_dir/library/common/up_clock_mon.v" \ + "$ad_hdl_dir/library/common/up_delay_cntrl.v" \ + "$ad_hdl_dir/library/common/up_adc_common.v" \ + "$ad_hdl_dir/library/common/up_adc_channel.v" \ + "$ad_hdl_dir/library/common/up_axi.v" \ + "$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc" \ + "axi_ad9684_pnmon.v" \ + "axi_ad9684_if.v" \ + "axi_ad9684_channel.v" \ + "axi_ad9684_constr.xdc" \ + "axi_ad9684.v"] + +adi_ip_properties axi_ad9684 + +adi_ip_constraints axi_ad9684 [list \ + "axi_ad9684_constr.xdc" \ + "$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc"] + +set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]] +set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]] + +ipx::save_core [ipx::current_core] diff --git a/library/axi_ad9684/axi_ad9684_pnmon.v b/library/axi_ad9684/axi_ad9684_pnmon.v new file mode 100644 index 000000000..e57102e9d --- /dev/null +++ b/library/axi_ad9684/axi_ad9684_pnmon.v @@ -0,0 +1,192 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2015(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// PN monitors + +`timescale 1ns/100ps + +module axi_ad9684_pnmon ( + + // adc interface + + adc_clk, + adc_data, + + // pn out of sync and error + + adc_pn_oos, + adc_pn_err, + + // processor interface PN9 (0x0), PN23 (0x1) + + adc_pnseq_sel); + + // adc interface + + input adc_clk; + input [27:0] adc_data; + + // pn out of sync and error + + output adc_pn_oos; + output adc_pn_err; + + // processor interface PN9 (0x0), PN23 (0x1) + + input [ 3:0] adc_pnseq_sel; + + // internal registers + + reg [27:0] adc_pn_data_in = 'd0; + reg [27:0] adc_pn_data_pn = 'd0; + + // internal signals + + wire [27:0] adc_pn_data_pn_s; + wire [31:0] adc_pn_data_pn9_s; + + // PN23 function + + function [27:0] pn23; + input [27:0] din; + reg [27:0] dout; + begin + dout[27] = din[22] ^ din[17]; + dout[26] = din[21] ^ din[16]; + dout[25] = din[20] ^ din[15]; + dout[24] = din[19] ^ din[14]; + dout[23] = din[18] ^ din[13]; + dout[22] = din[17] ^ din[12]; + dout[21] = din[16] ^ din[11]; + dout[20] = din[15] ^ din[10]; + dout[19] = din[14] ^ din[ 9]; + dout[18] = din[13] ^ din[ 8]; + dout[17] = din[12] ^ din[ 7]; + dout[16] = din[11] ^ din[ 6]; + dout[15] = din[10] ^ din[ 5]; + dout[14] = din[ 9] ^ din[ 4]; + dout[13] = din[ 8] ^ din[ 3]; + dout[12] = din[ 7] ^ din[ 2]; + dout[11] = din[ 6] ^ din[ 1]; + dout[10] = din[ 5] ^ din[ 0]; + dout[ 9] = din[ 4] ^ din[22] ^ din[17]; + dout[ 8] = din[ 3] ^ din[21] ^ din[16]; + dout[ 7] = din[ 2] ^ din[20] ^ din[15]; + dout[ 6] = din[ 1] ^ din[19] ^ din[14]; + dout[ 5] = din[ 0] ^ din[18] ^ din[13]; + dout[ 4] = din[22] ^ din[12]; + dout[ 3] = din[21] ^ din[11]; + dout[ 2] = din[20] ^ din[10]; + dout[ 1] = din[19] ^ din[ 9]; + dout[ 0] = din[18] ^ din[ 8]; + pn23 = dout; + end + endfunction + + // PN9 function + + function [31:0] pn9; + input [27:0] din; + reg [31:0] dout; + begin + dout[31] = din[ 8] ^ din[ 4]; + dout[30] = din[ 7] ^ din[ 3]; + dout[29] = din[ 6] ^ din[ 2]; + dout[28] = din[ 5] ^ din[ 1]; + dout[27] = din[ 4] ^ din[ 0]; + dout[26] = din[ 3] ^ din[ 8] ^ din[ 4]; + dout[25] = din[ 2] ^ din[ 7] ^ din[ 3]; + dout[24] = din[ 1] ^ din[ 6] ^ din[ 2]; + dout[23] = din[ 0] ^ din[ 5] ^ din[ 1]; + dout[22] = din[ 8] ^ din[ 0]; + dout[21] = din[ 7] ^ din[ 8] ^ din[ 4]; + dout[20] = din[ 6] ^ din[ 7] ^ din[ 3]; + dout[19] = din[ 5] ^ din[ 6] ^ din[ 2]; + dout[18] = din[ 4] ^ din[ 5] ^ din[ 1]; + dout[17] = din[ 3] ^ din[ 4] ^ din[ 0]; + dout[16] = din[ 2] ^ din[ 3] ^ din[ 8] ^ din[ 4]; + dout[15] = din[ 1] ^ din[ 2] ^ din[ 7] ^ din[ 3]; + dout[14] = din[ 0] ^ din[ 1] ^ din[ 6] ^ din[ 2]; + dout[13] = din[ 8] ^ din[ 0] ^ din[ 5] ^ din[ 1] ^ din[ 4]; + dout[12] = din[ 7] ^ din[ 8] ^ din[ 3] ^ din[ 0]; + dout[11] = din[ 6] ^ din[ 7] ^ din[ 2] ^ din[ 8] ^ din[ 4]; + dout[10] = din[ 5] ^ din[ 6] ^ din[ 1] ^ din[ 7] ^ din[ 3]; + dout[ 9] = din[ 4] ^ din[ 5] ^ din[ 0] ^ din[ 6] ^ din[ 2]; + dout[ 8] = din[ 3] ^ din[ 8] ^ din[ 5] ^ din[ 1]; + dout[ 7] = din[ 2] ^ din[ 4] ^ din[ 7] ^ din[ 0]; + dout[ 6] = din[ 1] ^ din[ 3] ^ din[ 6] ^ din[ 8] ^ din[ 4]; + dout[ 5] = din[ 0] ^ din[ 2] ^ din[ 5] ^ din[ 7] ^ din[ 3]; + dout[ 4] = din[ 8] ^ din[ 1] ^ din[ 6] ^ din[ 2]; + dout[ 3] = din[ 7] ^ din[ 0] ^ din[ 5] ^ din[ 1]; + dout[ 2] = din[ 6] ^ din[ 8] ^ din[ 0]; + dout[ 1] = din[ 5] ^ din[ 7] ^ din[ 8] ^ din[ 4]; + dout[ 0] = din[ 4] ^ din[ 6] ^ din[ 7] ^ din[ 3]; + pn9 = dout; + end + endfunction + + // pn sequence select + + assign adc_pn_data_pn_s = (adc_pn_oos == 1'b1) ? adc_pn_data_in : adc_pn_data_pn; + assign adc_pn_data_pn9_s = pn9(adc_pn_data_pn_s); + + always @(posedge adc_clk) begin + adc_pn_data_in <= { ~adc_data[13], adc_data[12: 0], + ~adc_data[27], adc_data[26:14]}; + if (adc_pnseq_sel == 4'd0) begin + adc_pn_data_pn <= {adc_pn_data_pn9_s[29:16], adc_pn_data_pn9_s[13:0]}; + end else begin + adc_pn_data_pn <= pn23(adc_pn_data_pn_s); + end + end + + // pn oos & pn err + + ad_pnmon #(.DATA_WIDTH(28)) i_pnmon ( + .adc_clk (adc_clk), + .adc_valid_in (1'b1), + .adc_data_in (adc_pn_data_in), + .adc_data_pn (adc_pn_data_pn), + .adc_pn_oos (adc_pn_oos), + .adc_pn_err (adc_pn_err)); + +endmodule + +// *************************************************************************** +// *************************************************************************** + diff --git a/library/axi_ad9739a/Makefile b/library/axi_ad9739a/Makefile index 0068469d5..1fa25b7e9 100644 --- a/library/axi_ad9739a/Makefile +++ b/library/axi_ad9739a/Makefile @@ -5,27 +5,27 @@ #################################################################################### #################################################################################### -M_DEPS := axi_ad9739a_ip.tcl -M_DEPS += ../scripts/adi_env.tcl -M_DEPS += ../scripts/adi_ip.tcl -M_DEPS += ../common/ad_mul.v -M_DEPS += ../common/ad_dds_sine.v -M_DEPS += ../common/ad_dds_1.v +M_DEPS += ../common/ad_axi_ip_constr.xdc M_DEPS += ../common/ad_dds.v +M_DEPS += ../common/ad_dds_1.v +M_DEPS += ../common/ad_dds_sine.v M_DEPS += ../common/ad_rst.v -M_DEPS += ../common/ad_serdes_out.v M_DEPS += ../common/up_axi.v +M_DEPS += ../common/up_clock_mon.v +M_DEPS += ../common/up_dac_channel.v +M_DEPS += ../common/up_dac_common.v M_DEPS += ../common/up_xfer_cntrl.v M_DEPS += ../common/up_xfer_status.v -M_DEPS += ../common/up_clock_mon.v -M_DEPS += ../common/up_dac_common.v -M_DEPS += ../common/up_dac_channel.v -M_DEPS += ../common/ad_axi_ip_constr.xdc +M_DEPS += ../scripts/adi_env.tcl +M_DEPS += ../scripts/adi_ip.tcl +M_DEPS += ../xilinx/common/ad_mul.v +M_DEPS += ../xilinx/common/ad_serdes_out.v +M_DEPS += axi_ad9739a.v M_DEPS += axi_ad9739a_channel.v +M_DEPS += axi_ad9739a_constr.xdc M_DEPS += axi_ad9739a_core.v M_DEPS += axi_ad9739a_if.v -M_DEPS += axi_ad9739a_constr.xdc -M_DEPS += axi_ad9739a.v +M_DEPS += axi_ad9739a_ip.tcl M_VIVADO := vivado -mode batch -source @@ -36,6 +36,10 @@ M_FLIST += *.log M_FLIST += component.xml M_FLIST += *.jou M_FLIST += xgui +M_FLIST += *.ip_user_files +M_FLIST += *.srcs +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil @@ -52,7 +56,7 @@ clean-all: axi_ad9739a.xpr: $(M_DEPS) - rm -rf $(M_FLIST) + -rm -rf $(M_FLIST) $(M_VIVADO) axi_ad9739a_ip.tcl >> axi_ad9739a_ip.log 2>&1 #################################################################################### diff --git a/library/axi_ad9739a/axi_ad9739a.v b/library/axi_ad9739a/axi_ad9739a.v index e357648a5..c7e2beead 100644 --- a/library/axi_ad9739a/axi_ad9739a.v +++ b/library/axi_ad9739a/axi_ad9739a.v @@ -81,7 +81,9 @@ module axi_ad9739a ( s_axi_rvalid, s_axi_rdata, s_axi_rresp, - s_axi_rready); + s_axi_rready, + s_axi_awprot, + s_axi_arprot); // parameters @@ -133,6 +135,9 @@ module axi_ad9739a ( output [ 31:0] s_axi_rdata; output [ 1:0] s_axi_rresp; input s_axi_rready; + input [ 2:0] s_axi_awprot; + input [ 2:0] s_axi_arprot; + // internal clocks and resets diff --git a/library/axi_ad9739a/axi_ad9739a_channel.v b/library/axi_ad9739a/axi_ad9739a_channel.v index 3e8605054..37b99bf45 100644 --- a/library/axi_ad9739a/axi_ad9739a_channel.v +++ b/library/axi_ad9739a/axi_ad9739a_channel.v @@ -638,7 +638,7 @@ module axi_ad9739a_channel ( // single channel processor - up_dac_channel #(.DAC_CHANNEL_ID(CHANNEL_ID)) i_up_dac_channel ( + up_dac_channel #(.CHANNEL_ID(CHANNEL_ID)) i_up_dac_channel ( .dac_clk (dac_div_clk), .dac_rst (dac_rst), .dac_dds_scale_1 (dac_dds_scale_1_s), @@ -650,6 +650,7 @@ module axi_ad9739a_channel ( .dac_pat_data_1 (dac_pat_data_1_s), .dac_pat_data_2 (dac_pat_data_2_s), .dac_data_sel (dac_data_sel_s), + .dac_iq_mode (), .dac_iqcor_enb (), .dac_iqcor_coeff_1 (), .dac_iqcor_coeff_2 (), diff --git a/library/axi_ad9739a/axi_ad9739a_core.v b/library/axi_ad9739a/axi_ad9739a_core.v index 12a2a34bc..f23524a60 100644 --- a/library/axi_ad9739a/axi_ad9739a_core.v +++ b/library/axi_ad9739a/axi_ad9739a_core.v @@ -214,6 +214,7 @@ module axi_ad9739a_core ( .dac_rst (dac_rst), .dac_sync (dac_sync_s), .dac_frame (), + .dac_clksel (), .dac_par_type (), .dac_par_enb (), .dac_r1_mode (), @@ -222,12 +223,12 @@ module axi_ad9739a_core ( .dac_status (dac_status), .dac_status_ovf (dac_dovf), .dac_status_unf (dac_dunf), - .dac_clk_ratio (32'd4), + .dac_clk_ratio (32'd16), .up_drp_sel (), .up_drp_wr (), .up_drp_addr (), .up_drp_wdata (), - .up_drp_rdata (16'd0), + .up_drp_rdata (32'd0), .up_drp_ready (1'd1), .up_drp_locked (1'd1), .up_usr_chanmax (), diff --git a/library/axi_ad9739a/axi_ad9739a_if.v b/library/axi_ad9739a/axi_ad9739a_if.v index f84187f69..c333ca06f 100644 --- a/library/axi_ad9739a/axi_ad9739a_if.v +++ b/library/axi_ad9739a/axi_ad9739a_if.v @@ -1,9 +1,9 @@ // *************************************************************************** // *************************************************************************** // Copyright 2011(c) Analog Devices, Inc. -// +// // All rights reserved. -// +// // Redistribution and use in source and binary forms, with or without modification, // are permitted provided that the following conditions are met: // - Redistributions of source code must retain the above copyright @@ -21,16 +21,16 @@ // patent holders to use this software. // - Use of the software either in source or binary form, must be run // on or directly connected to an Analog Devices Inc. component. -// +// // THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, // INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A // PARTICULAR PURPOSE ARE DISCLAIMED. // // IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, // EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY -// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR // BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // *************************************************************************** // *************************************************************************** @@ -143,13 +143,14 @@ module axi_ad9739a_if ( // dac data output serdes(s) & buffers ad_serdes_out #( - .SERDES_OR_DDR_N(1), + .DDR_OR_SDR_N(1), .DATA_WIDTH(14), .DEVICE_TYPE (DEVICE_TYPE)) i_serdes_out_data_a ( .rst (dac_rst), .clk (dac_clk), .div_clk (dac_div_clk), + .loaden (1'b0), .data_s0 (dac_data_00[15:2]), .data_s1 (dac_data_02[15:2]), .data_s2 (dac_data_04[15:2]), @@ -162,15 +163,16 @@ module axi_ad9739a_if ( .data_out_n (dac_data_out_a_n)); // dac data output serdes(s) & buffers - + ad_serdes_out #( - .SERDES_OR_DDR_N(1), + .DDR_OR_SDR_N(1), .DATA_WIDTH(14), .DEVICE_TYPE (DEVICE_TYPE)) i_serdes_out_data_b ( .rst (dac_rst), .clk (dac_clk), .div_clk (dac_div_clk), + .loaden (1'b0), .data_s0 (dac_data_01[15:2]), .data_s1 (dac_data_03[15:2]), .data_s2 (dac_data_05[15:2]), @@ -183,15 +185,16 @@ module axi_ad9739a_if ( .data_out_n (dac_data_out_b_n)); // dac clock output serdes & buffer - + ad_serdes_out #( - .SERDES_OR_DDR_N(1), + .DDR_OR_SDR_N(1), .DATA_WIDTH(1), .DEVICE_TYPE (DEVICE_TYPE)) i_serdes_out_clk ( .rst (dac_rst), .clk (dac_clk), .div_clk (dac_div_clk), + .loaden (1'b0), .data_s0 (1'b1), .data_s1 (1'b0), .data_s2 (1'b1), diff --git a/library/axi_ad9739a/axi_ad9739a_ip.tcl b/library/axi_ad9739a/axi_ad9739a_ip.tcl index 49134339c..3c152248d 100644 --- a/library/axi_ad9739a/axi_ad9739a_ip.tcl +++ b/library/axi_ad9739a/axi_ad9739a_ip.tcl @@ -5,12 +5,12 @@ source $ad_hdl_dir/library/scripts/adi_ip.tcl adi_ip_create axi_ad9739a adi_ip_files axi_ad9739a [list \ - "$ad_hdl_dir/library/common/ad_mul.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_mul.v" \ "$ad_hdl_dir/library/common/ad_dds_sine.v" \ "$ad_hdl_dir/library/common/ad_dds_1.v" \ "$ad_hdl_dir/library/common/ad_dds.v" \ "$ad_hdl_dir/library/common/ad_rst.v" \ - "$ad_hdl_dir/library/common/ad_serdes_out.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_serdes_out.v" \ "$ad_hdl_dir/library/common/up_axi.v" \ "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ "$ad_hdl_dir/library/common/up_xfer_status.v" \ diff --git a/library/axi_ad9963/Makefile b/library/axi_ad9963/Makefile new file mode 100644 index 000000000..4c5b88c2a --- /dev/null +++ b/library/axi_ad9963/Makefile @@ -0,0 +1,73 @@ +#################################################################################### +#################################################################################### +## Copyright 2011(c) Analog Devices, Inc. +## Auto-generated, do not modify! +#################################################################################### +#################################################################################### + +M_DEPS += ../common/ad_axi_ip_constr.xdc +M_DEPS += ../common/ad_datafmt.v +M_DEPS += ../common/ad_dcfilter.v +M_DEPS += ../common/ad_dds.v +M_DEPS += ../common/ad_dds_1.v +M_DEPS += ../common/ad_dds_sine.v +M_DEPS += ../common/ad_iqcor.v +M_DEPS += ../common/ad_pnmon.v +M_DEPS += ../common/ad_rst.v +M_DEPS += ../common/up_adc_channel.v +M_DEPS += ../common/up_adc_common.v +M_DEPS += ../common/up_axi.v +M_DEPS += ../common/up_clock_mon.v +M_DEPS += ../common/up_dac_channel.v +M_DEPS += ../common/up_dac_common.v +M_DEPS += ../common/up_delay_cntrl.v +M_DEPS += ../common/up_xfer_cntrl.v +M_DEPS += ../common/up_xfer_status.v +M_DEPS += ../scripts/adi_env.tcl +M_DEPS += ../scripts/adi_ip.tcl +M_DEPS += ../xilinx/common/ad_lvds_in.v +M_DEPS += ../xilinx/common/ad_lvds_out.v +M_DEPS += ../xilinx/common/ad_mul.v +M_DEPS += axi_ad9963.v +M_DEPS += axi_ad9963_if.v +M_DEPS += axi_ad9963_ip.tcl +M_DEPS += axi_ad9963_rx.v +M_DEPS += axi_ad9963_rx_channel.v +M_DEPS += axi_ad9963_rx_pnmon.v +M_DEPS += axi_ad9963_tx.v +M_DEPS += axi_ad9963_tx_channel.v + +M_VIVADO := vivado -mode batch -source + +M_FLIST := *.cache +M_FLIST += *.data +M_FLIST += *.xpr +M_FLIST += *.log +M_FLIST += component.xml +M_FLIST += *.jou +M_FLIST += xgui +M_FLIST += *.ip_user_files +M_FLIST += *.srcs +M_FLIST += *.hw +M_FLIST += *.sim +M_FLIST += .Xil + + + +.PHONY: all clean clean-all +all: axi_ad9963.xpr + + +clean:clean-all + + +clean-all: + rm -rf $(M_FLIST) + + +axi_ad9963.xpr: $(M_DEPS) + -rm -rf $(M_FLIST) + $(M_VIVADO) axi_ad9963_ip.tcl >> axi_ad9963_ip.log 2>&1 + +#################################################################################### +#################################################################################### diff --git a/library/axi_ad9963/axi_ad9963.v b/library/axi_ad9963/axi_ad9963.v new file mode 100644 index 000000000..1bed35e21 --- /dev/null +++ b/library/axi_ad9963/axi_ad9963.v @@ -0,0 +1,322 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_ad9963 #( + + // parameters + + parameter ID = 0, + parameter DEVICE_TYPE = 0, + parameter DAC_IODELAY_ENABLE = 0, + parameter IO_DELAY_GROUP = "dev_if_delay_group", + parameter DAC_DATAPATH_DISABLE = 0, + parameter ADC_DATAPATH_DISABLE = 0 ) ( + + // physical interface (receive) + + input trx_clk, + input trx_iq, + input [11:0] trx_data, + + // physical interface (transmit) + + output tx_clk, + output tx_iq, + output [11:0] tx_data, + + // transmit master/slave + + input dac_sync_in, + output dac_sync_out, + + // delay clock + + input delay_clk, + + // master interface + + output l_clk, + output dac_clk, + output rst, + + // dma interface + + output adc_enable_i, + output adc_valid_i, + output [15:0] adc_data_i, + output adc_enable_q, + output adc_valid_q, + output [15:0] adc_data_q, + input adc_dovf, + input adc_dunf, + + output dac_enable_i, + output dac_valid_i, + input [15:0] dac_data_i, + output dac_enable_q, + output dac_valid_q, + input [15:0] dac_data_q, + input dac_dovf, + input dac_dunf, + + // axi interface + + input s_axi_aclk, + input s_axi_aresetn, + input s_axi_awvalid, + input [31:0] s_axi_awaddr, + input [ 2:0] s_axi_awprot, + output s_axi_awready, + input s_axi_wvalid, + input [31:0] s_axi_wdata, + input [ 3:0] s_axi_wstrb, + output s_axi_wready, + output s_axi_bvalid, + output [ 1:0] s_axi_bresp, + input s_axi_bready, + input s_axi_arvalid, + input [31:0] s_axi_araddr, + input [ 2:0] s_axi_arprot, + output s_axi_arready, + output s_axi_rvalid, + output [31:0] s_axi_rdata, + output [ 1:0] s_axi_rresp, + input s_axi_rready); + + // internal registers + + reg up_wack = 'd0; + reg up_rack = 'd0; + reg [31:0] up_rdata = 'd0; + + // internal clocks and resets + + wire up_clk; + wire up_rstn; + wire delay_rst; + + // internal signals + + wire adc_valid_s; + wire [23:0] adc_data_s; + wire adc_status_s; + wire dac_valid_s; + wire [23:0] dac_data_s; + wire dac_valid_i0_s; + wire dac_valid_q0_s; + wire dac_valid_i1_s; + wire dac_valid_q1_s; + wire [12:0] up_adc_dld_s; + wire [64:0] up_adc_dwdata_s; + wire [64:0] up_adc_drdata_s; + wire [13:0] up_dac_dld_s; + wire [69:0] up_dac_dwdata_s; + wire [69:0] up_dac_drdata_s; + wire delay_locked_s; + wire up_wreq_s; + wire [13:0] up_waddr_s; + wire [31:0] up_wdata_s; + wire up_wack_rx_s; + wire up_wack_tx_s; + wire up_rreq_s; + wire [13:0] up_raddr_s; + wire [31:0] up_rdata_rx_s; + wire up_rack_rx_s; + wire [31:0] up_rdata_tx_s; + wire up_rack_tx_s; + + // signal name changes + + assign up_clk = s_axi_aclk; + assign up_rstn = s_axi_aresetn; + + // processor read interface + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_wack <= 'd0; + up_rack <= 'd0; + up_rdata <= 'd0; + end else begin + up_wack <= up_wack_rx_s | up_wack_tx_s ; + up_rack <= up_rack_rx_s | up_rack_tx_s ; + up_rdata <= up_rdata_rx_s | up_rdata_tx_s ; + end + end + + // device interface + + axi_ad9963_if #( + .DEVICE_TYPE (DEVICE_TYPE), + .DAC_IODELAY_ENABLE (DAC_IODELAY_ENABLE), + .IO_DELAY_GROUP (IO_DELAY_GROUP)) + i_dev_if ( + .trx_clk (trx_clk), + .trx_iq (trx_iq), + .trx_data (trx_data), + .tx_clk (tx_clk), + .tx_iq (tx_iq), + .tx_data (tx_data), + .rst (rst), + .l_clk (l_clk), + .dac_clk (dac_clk), + .adc_valid (adc_valid_s), + .adc_data (adc_data_s), + .adc_status (adc_status_s), + .dac_valid (dac_valid_s), + .dac_data (dac_data_s), + .up_clk (up_clk), + .up_adc_dld (up_adc_dld_s), + .up_adc_dwdata (up_adc_dwdata_s), + .up_adc_drdata (up_adc_drdata_s), + .up_dac_dld (up_dac_dld_s), + .up_dac_dwdata (up_dac_dwdata_s), + .up_dac_drdata (up_dac_drdata_s), + .delay_clk (delay_clk), + .delay_rst (delay_rst), + .delay_locked (delay_locked_s)); + + // receive + + axi_ad9963_rx #( + .ID (ID), + .DATAPATH_DISABLE (ADC_DATAPATH_DISABLE)) + i_rx ( + .adc_rst (rst), + .adc_clk (l_clk), + .adc_valid (adc_valid_s), + .adc_data (adc_data_s), + .adc_status (adc_status_s), + .up_dld (up_adc_dld_s), + .up_dwdata (up_adc_dwdata_s), + .up_drdata (up_adc_drdata_s), + .delay_clk (delay_clk), + .delay_rst (delay_rst), + .delay_locked (delay_locked_s), + .adc_enable_i (adc_enable_i), + .adc_valid_i (adc_valid_i), + .adc_data_i (adc_data_i), + .adc_enable_q (adc_enable_q), + .adc_valid_q (adc_valid_q), + .adc_data_q (adc_data_q), + .adc_dovf (adc_dovf), + .adc_dunf (adc_dunf), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack_rx_s), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata_rx_s), + .up_rack (up_rack_rx_s)); + + // transmit + + axi_ad9963_tx #( + .ID (ID), + .DATAPATH_DISABLE (DAC_DATAPATH_DISABLE)) + i_tx ( + .dac_clk (dac_clk), + .dac_valid (dac_valid_s), + .dac_data (dac_data_s), + .adc_data (adc_data_s), + .up_dld (up_dac_dld_s), + .up_dwdata (up_dac_dwdata_s), + .up_drdata (up_dac_drdata_s), + .delay_clk (delay_clk), + .delay_rst (), + .delay_locked (delay_locked_s), + .dac_sync_in (dac_sync_in), + .dac_sync_out (dac_sync_out), + .dac_enable_i (dac_enable_i), + .dac_valid_i (dac_valid_i), + .dac_data_i (dac_data_i), + .dac_enable_q (dac_enable_q), + .dac_valid_q (dac_valid_q), + .dac_data_q (dac_data_q), + .dac_dovf(dac_dovf), + .dac_dunf(dac_dunf), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack_tx_s), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata_tx_s), + .up_rack (up_rack_tx_s)); + + // axi interface + + up_axi i_up_axi ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_axi_awvalid (s_axi_awvalid), + .up_axi_awaddr (s_axi_awaddr), + .up_axi_awready (s_axi_awready), + .up_axi_wvalid (s_axi_wvalid), + .up_axi_wdata (s_axi_wdata), + .up_axi_wstrb (s_axi_wstrb), + .up_axi_wready (s_axi_wready), + .up_axi_bvalid (s_axi_bvalid), + .up_axi_bresp (s_axi_bresp), + .up_axi_bready (s_axi_bready), + .up_axi_arvalid (s_axi_arvalid), + .up_axi_araddr (s_axi_araddr), + .up_axi_arready (s_axi_arready), + .up_axi_rvalid (s_axi_rvalid), + .up_axi_rresp (s_axi_rresp), + .up_axi_rdata (s_axi_rdata), + .up_axi_rready (s_axi_rready), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata), + .up_rack (up_rack)); + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/library/axi_ad9963/axi_ad9963_if.v b/library/axi_ad9963/axi_ad9963_if.v new file mode 100644 index 000000000..d87467530 --- /dev/null +++ b/library/axi_ad9963/axi_ad9963_if.v @@ -0,0 +1,297 @@ +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// This interface includes both the transmit and receive components - +// They both uses the same clock (sourced from the receiving side). +// assumes RX_IQ is 1 for I and 0 for Q (RX_IFIRST = 1 , RXIQ_HILO = 1) + +`timescale 1ns/100ps + +module axi_ad9963_if #( + + // this parameter controls the buffer type based on the target device. + + parameter DEVICE_TYPE = 0, + parameter DAC_IODELAY_ENABLE = 0, + parameter IO_DELAY_GROUP = "dev_if_delay_group") ( + + // physical interface (receive) + + input trx_clk, + input trx_iq, + input [11:0] trx_data, + + // physical interface (transmit) + + output tx_clk, + output tx_iq, + output [11:0] tx_data, + + // clock (common to both receive and transmit) + + input rst, + output l_clk, + output dac_clk, + + // receive data path interface + + output reg adc_valid, + output reg [23:0] adc_data, + output reg adc_status, + + // transmit data path interface + + input dac_valid, + input [23:0] dac_data, + + // delay interface + + input up_clk, + input [12:0] up_adc_dld, + input [64:0] up_adc_dwdata, + output [64:0] up_adc_drdata, + input [13:0] up_dac_dld, + input [69:0] up_dac_dwdata, + output [69:0] up_dac_drdata, + input delay_clk, + input delay_rst, + output delay_locked); + + // internal registers + + reg [11:0] rx_data_p = 0; + reg [11:0] tx_data_p = 'd0; + reg [11:0] tx_data_n = 'd0; + reg tx_n_iq = 'd0; + reg tx_p_iq = 'd0; + + // internal signals + + wire [11:0] rx_data_p_s; + wire [11:0] rx_data_n_s; + wire rx_iq_p_s; + wire rx_iq_n_s; + + wire feedback_clk; + wire tx_clk_pll; + + genvar l_inst; + + always @(posedge l_clk) begin + if( rx_iq_p_s == 1'b1) begin + adc_data <= {rx_data_n_s, rx_data_p_s} ; // data[11:00] I + adc_valid <= 1'b1; // data[23:12] Q + end else begin + rx_data_p <= rx_data_p_s; // if this happens it means that risedge data is sampled on falledge + adc_data <= {rx_data_p, rx_data_n_s} ; // so we take current N data with previous P data + adc_valid <= 1'b1; // in order to have data sampled at the same instance sent to the DMA + end + end + + always @(posedge dac_clk) begin + if(dac_valid == 1'b1) begin + tx_data_p <= dac_data[11:0] ; + tx_data_n <= dac_data[23:12]; + tx_p_iq <= 1'b1; + tx_n_iq <= 1'b0; + end + end + + always @(posedge l_clk) begin + if (rst == 1'b1) begin + adc_status <= 1'b0; + end else begin + adc_status <= 1'b1; + end + end + + // device clock interface (receive clock) + + BUFG i_clk_gbuf ( + .I (trx_clk), + .O (l_clk)); + + // receive data interface, ibuf -> idelay -> iddr + + generate + for (l_inst = 0; l_inst <= 11; l_inst = l_inst + 1) begin: g_rx_data + ad_lvds_in #( + .SINGLE_ENDED (1), + .DEVICE_TYPE (DEVICE_TYPE), + .IODELAY_CTRL (0), + .IODELAY_GROUP (IO_DELAY_GROUP)) + i_rx_data ( + .rx_clk (l_clk), + .rx_data_in_p (trx_data[l_inst]), + .rx_data_in_n (1'b0), + .rx_data_p (rx_data_p_s[l_inst]), + .rx_data_n (rx_data_n_s[l_inst]), + .up_clk (up_clk), + .up_dld (up_adc_dld[l_inst]), + .up_dwdata (up_adc_dwdata[((l_inst*5)+4):(l_inst*5)]), + .up_drdata (up_adc_drdata[((l_inst*5)+4):(l_inst*5)]), + .delay_clk (delay_clk), + .delay_rst (delay_rst), + .delay_locked ()); + end + endgenerate + + // receive iq interface, ibuf -> idelay -> iddr + + ad_lvds_in #( + .SINGLE_ENDED (1), + .DEVICE_TYPE (DEVICE_TYPE), + .IODELAY_CTRL (1), + .IODELAY_GROUP (IO_DELAY_GROUP)) + i_rx_iq ( + .rx_clk (l_clk), + .rx_data_in_p (trx_iq), + .rx_data_in_n (1'b0), + .rx_data_p (rx_iq_p_s), + .rx_data_n (rx_iq_n_s), + .up_clk (up_clk), + .up_dld (up_adc_dld[12]), + .up_dwdata (up_adc_dwdata[64:60]), + .up_drdata (up_adc_drdata[64:60]), + .delay_clk (delay_clk), + .delay_rst (delay_rst), + .delay_locked (delay_locked)); + + // transmit data interface, oddr -> obuf + + generate + for (l_inst = 0; l_inst <= 11; l_inst = l_inst + 1) begin: g_tx_data + ad_lvds_out #( + .DEVICE_TYPE (DEVICE_TYPE), + .SINGLE_ENDED (1), + .IODELAY_ENABLE (DAC_IODELAY_ENABLE), + .IODELAY_CTRL (0), + .IODELAY_GROUP (IO_DELAY_GROUP)) + i_tx_data ( + .tx_clk (dac_clk), + .tx_data_p (tx_data_p[l_inst]), + .tx_data_n (tx_data_n[l_inst]), + .tx_data_out_p (tx_data[l_inst]), + .tx_data_out_n (), + .up_clk (up_clk), + .up_dld (up_dac_dld[l_inst]), + .up_dwdata (up_dac_dwdata[((l_inst*5)+4):(l_inst*5)]), + .up_drdata (up_dac_drdata[((l_inst*5)+4):(l_inst*5)]), + .delay_clk (delay_clk), + .delay_rst (delay_rst), + .delay_locked ()); + end + endgenerate + + // transmit iq interface, oddr -> obuf + + ad_lvds_out #( + .DEVICE_TYPE (DEVICE_TYPE), + .SINGLE_ENDED (1), + .IODELAY_ENABLE (DAC_IODELAY_ENABLE), + .IODELAY_CTRL (0), + .IODELAY_GROUP (IO_DELAY_GROUP)) + i_tx_iq ( + .tx_clk (dac_clk), + .tx_data_p (tx_p_iq), + .tx_data_n (tx_n_iq), + .tx_data_out_p (tx_iq), + .tx_data_out_n (), + .up_clk (up_clk), + .up_dld (up_dac_dld[12]), + .up_dwdata (up_dac_dwdata[64:60]), + .up_drdata (up_dac_drdata[64:60]), + .delay_clk (delay_clk), + .delay_rst (delay_rst), + .delay_locked ()); + + // transmit clock interface, oddr -> obuf + PLLE2_BASE #( + .BANDWIDTH("OPTIMIZED"), // OPTIMIZED, HIGH, LOW + .CLKFBOUT_MULT(15), // Multiply value for all CLKOUT, (2-64) + .CLKFBOUT_PHASE(0.0), // Phase offset in degrees of CLKFB, (-360.000-360.000). + .CLKIN1_PERIOD(10.0), // Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz). + // CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: Divide amount for each CLKOUT (1-128) + .CLKOUT0_DIVIDE(20), + .CLKOUT1_DIVIDE(20), + .CLKOUT2_DIVIDE(1), + .CLKOUT3_DIVIDE(1), + .CLKOUT4_DIVIDE(1), + .CLKOUT5_DIVIDE(1), + // CLKOUT0_DUTY_CYCLE - CLKOUT5_DUTY_CYCLE: Duty cycle for each CLKOUT (0.001-0.999). + .CLKOUT0_DUTY_CYCLE(0.5), + .CLKOUT1_DUTY_CYCLE(0.5), + .CLKOUT2_DUTY_CYCLE(0.5), + .CLKOUT3_DUTY_CYCLE(0.5), + .CLKOUT4_DUTY_CYCLE(0.5), + .CLKOUT5_DUTY_CYCLE(0.5), + // CLKOUT0_PHASE - CLKOUT5_PHASE: Phase offset for each CLKOUT (-360.000-360.000). + .CLKOUT0_PHASE(90.0), + .CLKOUT1_PHASE(0.0), + .CLKOUT2_PHASE(0.0), + .CLKOUT3_PHASE(0.0), + .CLKOUT4_PHASE(0.0), + .CLKOUT5_PHASE(0.0), + .DIVCLK_DIVIDE(1), // Master division value, (1-56) + .REF_JITTER1(0.0), // Reference input jitter in UI, (0.000-0.999). + .STARTUP_WAIT("FALSE") // Delay DONE until PLL Locks, ("TRUE"/"FALSE") + ) + PLLE2_BASE_inst ( + // Clock Outputs: 1-bit (each) output: User configurable clock outputs + .CLKOUT0(tx_clk_pll), // 1-bit output: CLKOUT0 + .CLKOUT1(dac_clk), // 1-bit output: CLKOUT1 + .CLKOUT2(), // 1-bit output: CLKOUT2 + .CLKOUT3(), // 1-bit output: CLKOUT3 + .CLKOUT4(), // 1-bit output: CLKOUT4 + .CLKOUT5(), // 1-bit output: CLKOUT5 + // Feedback Clocks: 1-bit (each) output: Clock feedback ports + .CLKFBOUT(feedback_clk), // 1-bit output: Feedback clock + .LOCKED(), // 1-bit output: LOCK + .CLKIN1(l_clk), // 1-bit input: Input clock + // Control Ports: 1-bit (each) input: PLL control ports + .PWRDWN(1'b0), // 1-bit input: Power-down + .RST(rst), // 1-bit input: Reset + // Feedback Clocks: 1-bit (each) input: Clock feedback ports + .CLKFBIN(feedback_clk) // 1-bit input: Feedback clock + ); + + ODDR #( + .DDR_CLK_EDGE ("SAME_EDGE"), + .INIT (1'b0), + .SRTYPE ("ASYNC")) + i_tx_clk_oddr( + .CE (1'b1), + .R (1'b0), + .S (1'b0), + .C (tx_clk_pll), + .D1 (1'b1), + .D2 (1'b0), + .Q (tx_clk)); + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/library/axi_ad9963/axi_ad9963_ip.tcl b/library/axi_ad9963/axi_ad9963_ip.tcl new file mode 100644 index 000000000..860878395 --- /dev/null +++ b/library/axi_ad9963/axi_ad9963_ip.tcl @@ -0,0 +1,57 @@ +# ip + +source ../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip.tcl + +adi_ip_create axi_ad9963 +adi_ip_files axi_ad9963 [list \ + "$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc" \ + "$ad_hdl_dir/library/common/ad_rst.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_lvds_in.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_lvds_out.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_mul.v" \ + "$ad_hdl_dir/library/common/ad_pnmon.v" \ + "$ad_hdl_dir/library/common/ad_dds_sine.v" \ + "$ad_hdl_dir/library/common/ad_dds_1.v" \ + "$ad_hdl_dir/library/common/ad_dds.v" \ + "$ad_hdl_dir/library/common/ad_datafmt.v" \ + "$ad_hdl_dir/library/common/ad_dcfilter.v" \ + "$ad_hdl_dir/library/common/ad_iqcor.v" \ + "$ad_hdl_dir/library/common/up_axi.v" \ + "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ + "$ad_hdl_dir/library/common/up_xfer_status.v" \ + "$ad_hdl_dir/library/common/up_clock_mon.v" \ + "$ad_hdl_dir/library/common/up_delay_cntrl.v" \ + "$ad_hdl_dir/library/common/up_adc_common.v" \ + "$ad_hdl_dir/library/common/up_adc_channel.v" \ + "$ad_hdl_dir/library/common/up_dac_common.v" \ + "$ad_hdl_dir/library/common/up_dac_channel.v" \ + "axi_ad9963_if.v" \ + "axi_ad9963_rx_pnmon.v" \ + "axi_ad9963_rx_channel.v" \ + "axi_ad9963_rx.v" \ + "axi_ad9963_tx_channel.v" \ + "axi_ad9963_tx.v" \ + "axi_ad9963.v" ] + +adi_ip_properties axi_ad9963 +adi_ip_constraints axi_ad9963 [list \ + "$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc" ] + +set_property driver_value 0 [ipx::get_ports *dac_sync_in* -of_objects [ipx::current_core]] +set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]] +set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]] + +ipx::remove_bus_interface rst [ipx::current_core] +ipx::remove_bus_interface clk [ipx::current_core] +ipx::remove_bus_interface l_clk [ipx::current_core] +ipx::remove_bus_interface delay_clk [ipx::current_core] + +ipx::add_bus_parameter ASSOCIATED_BUSIF [ipx::get_bus_interfaces s_axi_aclk \ + -of_objects [ipx::current_core]] +set_property value s_axi [ipx::get_bus_parameters ASSOCIATED_BUSIF \ + -of_objects [ipx::get_bus_interfaces s_axi_aclk \ + -of_objects [ipx::current_core]]] + +ipx::save_core [ipx::current_core] + diff --git a/library/axi_ad9963/axi_ad9963_rx.v b/library/axi_ad9963/axi_ad9963_rx.v new file mode 100644 index 000000000..29fea5f15 --- /dev/null +++ b/library/axi_ad9963/axi_ad9963_rx.v @@ -0,0 +1,252 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_ad9963_rx #( + + // parameters + + parameter DATAPATH_DISABLE = 0, + parameter ID = 0) ( + + // adc interface + + output adc_rst, + input adc_clk, + input adc_valid, + input [23:0] adc_data, + input adc_status, + + // delay interface + + output [12:0] up_dld, + output [64:0] up_dwdata, + input [64:0] up_drdata, + input delay_clk, + output delay_rst, + input delay_locked, + + // dma interface + + output adc_enable_i, + output adc_valid_i, + output [15:0] adc_data_i, + output adc_enable_q, + output adc_valid_q, + output [15:0] adc_data_q, + input adc_dovf, + input adc_dunf, + + // processor interface + + input up_rstn, + input up_clk, + input up_wreq, + input [13:0] up_waddr, + input [31:0] up_wdata, + output reg up_wack, + input up_rreq, + input [13:0] up_raddr, + output reg [31:0] up_rdata, + output reg up_rack); + + // internal registers + + reg up_status_pn_err = 'd0; + reg up_status_pn_oos = 'd0; + reg up_status_or = 'd0; + + // internal signals + + wire [15:0] adc_dcfilter_data_out_0_s; + wire [15:0] adc_dcfilter_data_out_1_s; + wire [ 1:0] up_adc_pn_err_s; + wire [ 1:0] up_adc_pn_oos_s; + wire [ 1:0] up_adc_or_s; + wire [31:0] up_rdata_s[0:3]; + wire up_rack_s[0:3]; + wire up_wack_s[0:3]; + + // processor read interface + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_status_pn_err <= 'd0; + up_status_pn_oos <= 'd0; + up_status_or <= 'd0; + up_rdata <= 'd0; + up_rack <= 'd0; + up_wack <= 'd0; + end else begin + up_status_pn_err <= | up_adc_pn_err_s; + up_status_pn_oos <= | up_adc_pn_oos_s; + up_status_or <= | up_adc_or_s; + up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2] | up_rdata_s[3]; + up_rack <= up_rack_s[0] | up_rack_s[1] | up_rack_s[2] | up_rack_s[3]; + up_wack <= up_wack_s[0] | up_wack_s[1] | up_wack_s[2] | up_wack_s[3]; + end + end + + // channel 0 (i) + + axi_ad9963_rx_channel #( + .Q_OR_I_N(0), + .CHANNEL_ID(0), + .DATAPATH_DISABLE (DATAPATH_DISABLE)) + i_rx_channel_0 ( + .adc_clk (adc_clk), + .adc_rst (adc_rst), + .adc_valid (adc_valid), + .adc_data (adc_data[11:0]), + .adc_or (1'b0), + .adc_dcfilter_data_out (adc_dcfilter_data_out_0_s), + .adc_dcfilter_data_in (adc_dcfilter_data_out_1_s), + .adc_iqcor_valid (adc_valid_i), + .adc_iqcor_data (adc_data_i), + .adc_enable (adc_enable_i), + .up_adc_pn_err (up_adc_pn_err_s[0]), + .up_adc_pn_oos (up_adc_pn_oos_s[0]), + .up_adc_or (up_adc_or_s[0]), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack_s[0]), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata_s[0]), + .up_rack (up_rack_s[0])); + + // channel 1 (q) + + axi_ad9963_rx_channel #( + .Q_OR_I_N(1), + .CHANNEL_ID(1), + .DATAPATH_DISABLE (DATAPATH_DISABLE)) + i_rx_channel_1 ( + .adc_clk (adc_clk), + .adc_rst (adc_rst), + .adc_valid (adc_valid), + .adc_data (adc_data[23:12]), + .adc_or (1'b0), + .adc_dcfilter_data_out (adc_dcfilter_data_out_1_s), + .adc_dcfilter_data_in (adc_dcfilter_data_out_0_s), + .adc_iqcor_valid (adc_valid_q), + .adc_iqcor_data (adc_data_q), + .adc_enable (adc_enable_q), + .up_adc_pn_err (up_adc_pn_err_s[1]), + .up_adc_pn_oos (up_adc_pn_oos_s[1]), + .up_adc_or (up_adc_or_s[1]), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack_s[1]), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata_s[1]), + .up_rack (up_rack_s[1])); + + // common processor control + + up_adc_common #(.ID (ID)) i_up_adc_common ( + .mmcm_rst (), + .adc_clk (adc_clk), + .adc_rst (adc_rst), + .adc_r1_mode (), + .adc_ddr_edgesel (), + .adc_pin_mode (), + .adc_status (adc_status), + .adc_sync_status (1'd0), + .adc_status_ovf (adc_dovf), + .adc_status_unf (adc_dunf), + .adc_clk_ratio (32'd1), + .adc_start_code (), + .adc_sync (), + .up_status_pn_err (up_status_pn_err), + .up_status_pn_oos (up_status_pn_oos), + .up_status_or (up_status_or), + .up_drp_sel (), + .up_drp_wr (), + .up_drp_addr (), + .up_drp_wdata (), + .up_drp_rdata (16'd0), + .up_drp_ready (1'd0), + .up_drp_locked (1'd1), + .up_usr_chanmax (), + .adc_usr_chanmax (8'd1), + .up_adc_gpio_in (32'h0), + .up_adc_gpio_out (), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack_s[2]), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata_s[2]), + .up_rack (up_rack_s[2])); + + // adc delay control + + up_delay_cntrl #(.DATA_WIDTH(13), .BASE_ADDRESS(6'h02)) i_delay_cntrl ( + .delay_clk (delay_clk), + .delay_rst (delay_rst), + .delay_locked (delay_locked), + .up_dld (up_dld), + .up_dwdata (up_dwdata), + .up_drdata (up_drdata), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack_s[3]), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata_s[3]), + .up_rack (up_rack_s[3])); + +endmodule + +// *************************************************************************** +// *************************************************************************** + diff --git a/library/axi_ad9963/axi_ad9963_rx_channel.v b/library/axi_ad9963/axi_ad9963_rx_channel.v new file mode 100644 index 000000000..9c26e04fe --- /dev/null +++ b/library/axi_ad9963/axi_ad9963_rx_channel.v @@ -0,0 +1,214 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_ad9963_rx_channel #( + + // parameters + + parameter Q_OR_I_N = 0, + parameter CHANNEL_ID = 0, + parameter DATAPATH_DISABLE = 0) ( + + // adc interface + + input adc_clk, + input adc_rst, + input adc_valid, + input [11:0] adc_data, + input adc_or, + + // channel interface + + output [15:0] adc_dcfilter_data_out, + input [15:0] adc_dcfilter_data_in, + output adc_iqcor_valid, + output [15:0] adc_iqcor_data, + output adc_enable, + output up_adc_pn_err, + output up_adc_pn_oos, + output up_adc_or, + + // processor interface + + input up_rstn, + input up_clk, + input up_wreq, + input [13:0] up_waddr, + input [31:0] up_wdata, + output up_wack, + input up_rreq, + input [13:0] up_raddr, + output [31:0] up_rdata, + output up_rack); + + // internal signals + + wire adc_dfmt_valid_s; + wire [15:0] adc_dfmt_data_s; + wire adc_dcfilter_valid_s; + wire [15:0] adc_dcfilter_data_s; + wire adc_iqcor_enb_s; + wire adc_dcfilt_enb_s; + wire adc_dfmt_se_s; + wire adc_dfmt_type_s; + wire adc_dfmt_enable_s; + wire [15:0] adc_dcfilt_offset_s; + wire [15:0] adc_dcfilt_coeff_s; + wire [15:0] adc_iqcor_coeff_1_s; + wire [15:0] adc_iqcor_coeff_2_s; + wire [ 3:0] adc_pnseq_sel_s; + wire [ 3:0] adc_data_sel_s; + wire adc_pn_err_s; + wire adc_pn_oos_s; + + // iq correction inputs + + assign adc_dcfilter_data_out = adc_dcfilter_data_s; + + axi_ad9963_rx_pnmon i_rx_pnmon ( + .adc_clk (adc_clk), + .adc_valid (adc_valid), + .adc_data (adc_data), + .adc_pnseq_sel (adc_pnseq_sel_s), + .adc_pn_oos (adc_pn_oos_s), + .adc_pn_err (adc_pn_err_s)); + + generate + if (DATAPATH_DISABLE == 1) begin + assign adc_dfmt_valid_s = adc_valid; + assign adc_dfmt_data_s = {4'd0, adc_data}; + end else begin + ad_datafmt #(.DATA_WIDTH (12)) i_ad_datafmt ( + .clk (adc_clk), + .valid (adc_valid), + .data (adc_data), + .valid_out (adc_dfmt_valid_s), + .data_out (adc_dfmt_data_s), + .dfmt_enable (adc_dfmt_enable_s), + .dfmt_type (adc_dfmt_type_s), + .dfmt_se (adc_dfmt_se_s)); + end + endgenerate + + generate + if (DATAPATH_DISABLE == 1) begin + assign adc_dcfilter_valid_s = adc_dfmt_valid_s; + assign adc_dcfilter_data_s = adc_dfmt_data_s; + end else begin + ad_dcfilter i_ad_dcfilter ( + .clk (adc_clk), + .valid (adc_dfmt_valid_s), + .data (adc_dfmt_data_s), + .valid_out (adc_dcfilter_valid_s), + .data_out (adc_dcfilter_data_s), + .dcfilt_enb (adc_dcfilt_enb_s), + .dcfilt_coeff (adc_dcfilt_coeff_s), + .dcfilt_offset (adc_dcfilt_offset_s)); + end + endgenerate + + generate + if (DATAPATH_DISABLE == 1) begin + assign adc_iqcor_valid = adc_dcfilter_valid_s; + assign adc_iqcor_data = adc_dcfilter_data_s; + end else begin + ad_iqcor #(.Q_OR_I_N (Q_OR_I_N)) i_ad_iqcor ( + .clk (adc_clk), + .valid (adc_dcfilter_valid_s), + .data_in (adc_dcfilter_data_s), + .data_iq (adc_dcfilter_data_in), + .valid_out (adc_iqcor_valid), + .data_out (adc_iqcor_data), + .iqcor_enable (adc_iqcor_enb_s), + .iqcor_coeff_1 (adc_iqcor_coeff_1_s), + .iqcor_coeff_2 (adc_iqcor_coeff_2_s)); + end + endgenerate + + up_adc_channel #(.CHANNEL_ID (CHANNEL_ID)) i_up_adc_channel ( + .adc_clk (adc_clk), + .adc_rst (adc_rst), + .adc_enable (adc_enable), + .adc_iqcor_enb (adc_iqcor_enb_s), + .adc_dcfilt_enb (adc_dcfilt_enb_s), + .adc_dfmt_se (adc_dfmt_se_s), + .adc_dfmt_type (adc_dfmt_type_s), + .adc_dfmt_enable (adc_dfmt_enable_s), + .adc_dcfilt_offset (adc_dcfilt_offset_s), + .adc_dcfilt_coeff (adc_dcfilt_coeff_s), + .adc_iqcor_coeff_1 (adc_iqcor_coeff_1_s), + .adc_iqcor_coeff_2 (adc_iqcor_coeff_2_s), + .adc_pnseq_sel (adc_pnseq_sel_s), + .adc_data_sel (adc_data_sel_s), + .adc_pn_err (adc_pn_err_s), + .adc_pn_oos (adc_pn_oos_s), + .adc_or (adc_or), + .up_adc_pn_err (up_adc_pn_err), + .up_adc_pn_oos (up_adc_pn_oos), + .up_adc_or (up_adc_or), + .up_usr_datatype_be (), + .up_usr_datatype_signed (), + .up_usr_datatype_shift (), + .up_usr_datatype_total_bits (), + .up_usr_datatype_bits (), + .up_usr_decimation_m (), + .up_usr_decimation_n (), + .adc_usr_datatype_be (1'b0), + .adc_usr_datatype_signed (1'b1), + .adc_usr_datatype_shift (8'd0), + .adc_usr_datatype_total_bits (8'd16), + .adc_usr_datatype_bits (8'd16), + .adc_usr_decimation_m (16'd1), + .adc_usr_decimation_n (16'd1), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata), + .up_rack (up_rack)); + +endmodule + +// *************************************************************************** +// *************************************************************************** + diff --git a/library/axi_ad9963/axi_ad9963_rx_pnmon.v b/library/axi_ad9963/axi_ad9963_rx_pnmon.v new file mode 100644 index 000000000..6a38eb0f4 --- /dev/null +++ b/library/axi_ad9963/axi_ad9963_rx_pnmon.v @@ -0,0 +1,121 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// PN monitors + +`timescale 1ns/100ps + +module axi_ad9963_rx_pnmon ( + + // adc interface + + input adc_clk, + input adc_valid, + input [11:0] adc_data, + + // pn out of sync and error + + input [ 3:0] adc_pnseq_sel, + output adc_pn_oos, + output adc_pn_err); + + // internal registers + + reg [23:0] adc_pn_data_in = 'd0; + reg [23:0] adc_pn_data_pn = 'd0; + + // internal signals + + wire [31:0] adc_pn_data_pn_s; + + // bit reversal function + + function [11:0] brfn; + input [11:0] din; + reg [11:0] dout; + begin + dout[11] = din[ 0]; + dout[10] = din[ 1]; + dout[ 9] = din[ 2]; + dout[ 8] = din[ 3]; + dout[ 7] = din[ 4]; + dout[ 6] = din[ 5]; + dout[ 5] = din[ 6]; + dout[ 4] = din[ 7]; + dout[ 3] = din[ 8]; + dout[ 2] = din[ 9]; + dout[ 1] = din[10]; + dout[ 0] = din[11]; + brfn = dout; + end + endfunction + + // standard prbs functions + + function [23:0] pn23; + input [23:0] din; + reg [23:0] dout; + begin + dout = {din[22:0], din[22] ^ din[17]}; + pn23 = dout; + end + endfunction + + // standard, runs on 24bit + + assign adc_pn_data_pn_s = (adc_pn_oos == 1'b1) ? adc_pn_data_in : adc_pn_data_pn; + + always @(posedge adc_clk) begin + if(adc_valid == 1'b1) begin + adc_pn_data_in <= {adc_pn_data_in[22:11], adc_data}; + adc_pn_data_pn <= pn23(adc_pn_data_pn_s); + end + end + + // pn oos & pn err + + ad_pnmon #(.DATA_WIDTH(24)) i_pnmon ( + .adc_clk (adc_clk), + .adc_valid_in (adc_valid), + .adc_data_in (adc_pn_data_in), + .adc_data_pn (adc_pn_data_pn), + .adc_pn_oos (adc_pn_oos), + .adc_pn_err (adc_pn_err)); + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/library/axi_ad9963/axi_ad9963_tx.v b/library/axi_ad9963/axi_ad9963_tx.v new file mode 100644 index 000000000..f8ab3eb25 --- /dev/null +++ b/library/axi_ad9963/axi_ad9963_tx.v @@ -0,0 +1,272 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_ad9963_tx #( + + // parameters + + parameter DATAPATH_DISABLE = 0, + parameter ID = 0) ( + + // dac interface + + input dac_clk, + output reg dac_valid, + output [23:0] dac_data, + input [23:0] adc_data, + + // delay interface + + output [13:0] up_dld, + output [69:0] up_dwdata, + input [69:0] up_drdata, + input delay_clk, + output delay_rst, + input delay_locked, + + // master/slave + + input dac_sync_in, + output dac_sync_out, + + // dma interface + + output dac_enable_i, + output reg dac_valid_i, + input [15:0] dac_data_i, + output dac_enable_q, + output reg dac_valid_q, + input [15:0] dac_data_q, + input dac_dovf, + input dac_dunf, + + // processor interface + + input up_rstn, + input up_clk, + input up_wreq, + input [13:0] up_waddr, + input [31:0] up_wdata, + output reg up_wack, + input up_rreq, + input [13:0] up_raddr, + output reg [31:0] up_rdata, + output reg up_rack); + + // internal registers + + reg dac_data_sync = 'd0; + reg [ 7:0] dac_rate_cnt = 'd0; + + // internal clock and resets + + wire dac_rst; + + // internal signals + + wire dac_data_sync_s; + wire dac_dds_format_s; + wire [ 7:0] dac_datarate_s; + wire [23:0] dac_data_int_s; + wire [31:0] up_rdata_s[0:3]; + wire up_rack_s[0:3]; + wire up_wack_s[0:3]; + + // master/slave + + assign dac_data_sync_s = (ID == 0) ? dac_sync_out : dac_sync_in; + + always @(posedge dac_clk) begin + dac_data_sync <= dac_data_sync_s; + end + + // rate counters and data sync signals + + always @(posedge dac_clk) begin + if ((dac_data_sync == 1'b1) || (dac_rate_cnt == 8'd0)) begin + dac_rate_cnt <= dac_datarate_s; + end else begin + dac_rate_cnt <= dac_rate_cnt - 1'b1; + end + end + + // dma interface + + always @(posedge dac_clk) begin + dac_valid <= (dac_rate_cnt == 8'd0) ? 1'b1 : 1'b0; + dac_valid_i <= dac_valid; + dac_valid_q <= dac_valid; + end + + // processor read interface + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_rdata <= 'd0; + up_rack <= 'd0; + up_wack <= 'd0; + end else begin + up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2] | up_rdata_s[3]; + up_rack <= up_rack_s[0] | up_rack_s[1] | up_rack_s[2] | up_rack_s[3]; + up_wack <= up_wack_s[0] | up_wack_s[1] | up_wack_s[2] | up_wack_s[3]; + end + end + + // dac channel + + axi_ad9963_tx_channel #( + .CHANNEL_ID (0), + .Q_OR_I_N (0), + .DATAPATH_DISABLE (DATAPATH_DISABLE)) + i_tx_channel_0 ( + .dac_clk (dac_clk), + .dac_rst (dac_rst), + .dac_valid (dac_valid), + .dma_data (dac_data_i), + .adc_data (adc_data[11:0]), + .dac_data (dac_data[11:0]), + .dac_data_out (dac_data_int_s[11:0]), + .dac_data_in (dac_data_int_s[23:12]), + .dac_enable (dac_enable_i), + .dac_data_sync (dac_data_sync), + .dac_dds_format (dac_dds_format_s), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack_s[0]), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata_s[0]), + .up_rack (up_rack_s[0])); + + // dac channel + + axi_ad9963_tx_channel #( + .CHANNEL_ID (1), + .Q_OR_I_N (1), + .DATAPATH_DISABLE (DATAPATH_DISABLE)) + i_tx_channel_1 ( + .dac_clk (dac_clk), + .dac_rst (dac_rst), + .dac_valid (dac_valid), + .dma_data (dac_data_q), + .adc_data (adc_data[23:12]), + .dac_data (dac_data[23:12]), + .dac_data_out (dac_data_int_s[23:12]), + .dac_data_in (dac_data_int_s[11:0]), + .dac_enable (dac_enable_q), + .dac_data_sync (dac_data_sync), + .dac_dds_format (dac_dds_format_s), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack_s[1]), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata_s[1]), + .up_rack (up_rack_s[1])); + + // dac common processor interface + + up_dac_common #(.ID (ID)) i_up_dac_common ( + .mmcm_rst (), + .dac_clk (dac_clk), + .dac_rst (dac_rst), + .dac_sync (dac_sync_out), + .dac_frame (), + .dac_clksel(), + .dac_par_type (), + .dac_par_enb (), + .dac_r1_mode (), + .dac_datafmt (dac_dds_format_s), + .dac_datarate (dac_datarate_s), + .dac_status (1'b1), + .dac_status_ovf (dac_dovf), + .dac_status_unf (dac_dunf), + .dac_clk_ratio (32'd1), + .up_drp_sel (), + .up_drp_wr (), + .up_drp_addr (), + .up_drp_wdata (), + .up_drp_rdata (16'd0), + .up_drp_ready (1'd0), + .up_drp_locked (1'd1), + .up_usr_chanmax (), + .dac_usr_chanmax (8'd2), + .up_dac_gpio_in (32'h0), + .up_dac_gpio_out (), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack_s[2]), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata_s[2]), + .up_rack (up_rack_s[2])); + + // dac delay control + + up_delay_cntrl #(.DATA_WIDTH(14), .BASE_ADDRESS(6'h12)) i_delay_cntrl ( + .delay_clk (delay_clk), + .delay_rst (delay_rst), + .delay_locked (delay_locked), + .up_dld (up_dld), + .up_dwdata (up_dwdata), + .up_drdata (up_drdata), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack_s[3]), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata_s[3]), + .up_rack (up_rack_s[3])); + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/library/axi_ad9963/axi_ad9963_tx_channel.v b/library/axi_ad9963/axi_ad9963_tx_channel.v new file mode 100644 index 000000000..707843659 --- /dev/null +++ b/library/axi_ad9963/axi_ad9963_tx_channel.v @@ -0,0 +1,415 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_ad9963_tx_channel #( + + // parameters + + parameter CHANNEL_ID = 32'h0, + parameter Q_OR_I_N = 0, + parameter DATAPATH_DISABLE = 0, + localparam PRBS_SEL = CHANNEL_ID, + localparam PRBS_P09 = 0, + localparam PRBS_P11 = 1, + localparam PRBS_P15 = 2, + localparam PRBS_P20 = 3) ( + + // dac interface + + input dac_clk, + input dac_rst, + input dac_valid, + input [15:0] dma_data, + input [11:0] adc_data, + output reg [11:0] dac_data, + output reg [11:0] dac_data_out, + input [11:0] dac_data_in, + + // processor interface + + output reg dac_enable, + input dac_data_sync, + input dac_dds_format, + + // bus interface + + input up_rstn, + input up_clk, + input up_wreq, + input [13:0] up_waddr, + input [31:0] up_wdata, + output up_wack, + input up_rreq, + input [13:0] up_raddr, + output [31:0] up_rdata, + output up_rack); + + // internal registers + + reg dac_valid_sel = 'd0; + reg [23:0] dac_test_data = 'd0; + reg [15:0] dac_test_counter = 'd0; + reg [23:0] dac_pn_seq = 'd0; + reg [11:0] dac_pn_data = 'd0; + reg [15:0] dac_pat_data = 'd0; + reg [15:0] dac_dds_phase_0 = 'd0; + reg [15:0] dac_dds_phase_1 = 'd0; + reg [15:0] dac_dds_incr_0 = 'd0; + reg [15:0] dac_dds_incr_1 = 'd0; + reg [15:0] dac_dds_data = 'd0; + + // internal signals + + wire dac_iqcor_valid_s; + wire [15:0] dac_iqcor_data_s; + wire [15:0] dac_dds_data_s; + wire [15:0] dac_dds_scale_1_s; + wire [15:0] dac_dds_init_1_s; + wire [15:0] dac_dds_incr_1_s; + wire [15:0] dac_dds_scale_2_s; + wire [15:0] dac_dds_init_2_s; + wire [15:0] dac_dds_incr_2_s; + wire [15:0] dac_pat_data_1_s; + wire [15:0] dac_pat_data_2_s; + wire [ 3:0] dac_data_sel_s; + wire dac_iqcor_enb_s; + wire [15:0] dac_iqcor_coeff_1_s; + wire [15:0] dac_iqcor_coeff_2_s; + + // standard prbs functions + + function [23:0] pn1fn; + input [23:0] din; + reg [23:0] dout; + begin + case (PRBS_SEL) + PRBS_P09: begin + dout[23] = din[ 8] ^ din[ 4]; + dout[22] = din[ 7] ^ din[ 3]; + dout[21] = din[ 6] ^ din[ 2]; + dout[20] = din[ 5] ^ din[ 1]; + dout[19] = din[ 4] ^ din[ 0]; + dout[18] = din[ 3] ^ din[ 8] ^ din[ 4]; + dout[17] = din[ 2] ^ din[ 7] ^ din[ 3]; + dout[16] = din[ 1] ^ din[ 6] ^ din[ 2]; + dout[15] = din[ 0] ^ din[ 5] ^ din[ 1]; + dout[14] = din[ 8] ^ din[ 0]; + dout[13] = din[ 7] ^ din[ 8] ^ din[ 4]; + dout[12] = din[ 6] ^ din[ 7] ^ din[ 3]; + dout[11] = din[ 5] ^ din[ 6] ^ din[ 2]; + dout[10] = din[ 4] ^ din[ 5] ^ din[ 1]; + dout[ 9] = din[ 3] ^ din[ 4] ^ din[ 0]; + dout[ 8] = din[ 2] ^ din[ 3] ^ din[ 8] ^ din[ 4]; + dout[ 7] = din[ 1] ^ din[ 2] ^ din[ 7] ^ din[ 3]; + dout[ 6] = din[ 0] ^ din[ 1] ^ din[ 6] ^ din[ 2]; + dout[ 5] = din[ 8] ^ din[ 0] ^ din[ 4] ^ din[ 5] ^ din[ 1]; + dout[ 4] = din[ 7] ^ din[ 8] ^ din[ 3] ^ din[ 0]; + dout[ 3] = din[ 6] ^ din[ 7] ^ din[ 2] ^ din[ 8] ^ din[ 4]; + dout[ 2] = din[ 5] ^ din[ 6] ^ din[ 1] ^ din[ 7] ^ din[ 3]; + dout[ 1] = din[ 4] ^ din[ 5] ^ din[ 0] ^ din[ 6] ^ din[ 2]; + dout[ 0] = din[ 3] ^ din[ 8] ^ din[ 5] ^ din[ 1]; + end + PRBS_P11: begin + dout[23] = din[10] ^ din[ 8]; + dout[22] = din[ 9] ^ din[ 7]; + dout[21] = din[ 8] ^ din[ 6]; + dout[20] = din[ 7] ^ din[ 5]; + dout[19] = din[ 6] ^ din[ 4]; + dout[18] = din[ 5] ^ din[ 3]; + dout[17] = din[ 4] ^ din[ 2]; + dout[16] = din[ 3] ^ din[ 1]; + dout[15] = din[ 2] ^ din[ 0]; + dout[14] = din[ 1] ^ din[10] ^ din[ 8]; + dout[13] = din[ 0] ^ din[ 9] ^ din[ 7]; + dout[12] = din[10] ^ din[ 6]; + dout[11] = din[ 9] ^ din[ 5]; + dout[10] = din[ 8] ^ din[ 4]; + dout[ 9] = din[ 7] ^ din[ 3]; + dout[ 8] = din[ 6] ^ din[ 2]; + dout[ 7] = din[ 5] ^ din[ 1]; + dout[ 6] = din[ 4] ^ din[ 0]; + dout[ 5] = din[ 3] ^ din[10] ^ din[ 8]; + dout[ 4] = din[ 2] ^ din[ 9] ^ din[ 7]; + dout[ 3] = din[ 1] ^ din[ 8] ^ din[ 6]; + dout[ 2] = din[ 0] ^ din[ 7] ^ din[ 5]; + dout[ 1] = din[10] ^ din[ 6] ^ din[ 8] ^ din[ 4]; + dout[ 0] = din[ 9] ^ din[ 5] ^ din[ 7] ^ din[ 3]; + end + PRBS_P15: begin + dout[23] = din[14] ^ din[13]; + dout[22] = din[13] ^ din[12]; + dout[21] = din[12] ^ din[11]; + dout[20] = din[11] ^ din[10]; + dout[19] = din[10] ^ din[ 9]; + dout[18] = din[ 9] ^ din[ 8]; + dout[17] = din[ 8] ^ din[ 7]; + dout[16] = din[ 7] ^ din[ 6]; + dout[15] = din[ 6] ^ din[ 5]; + dout[14] = din[ 5] ^ din[ 4]; + dout[13] = din[ 4] ^ din[ 3]; + dout[12] = din[ 3] ^ din[ 2]; + dout[11] = din[ 2] ^ din[ 1]; + dout[10] = din[ 1] ^ din[ 0]; + dout[ 9] = din[ 0] ^ din[14] ^ din[13]; + dout[ 8] = din[14] ^ din[12]; + dout[ 7] = din[13] ^ din[11]; + dout[ 6] = din[12] ^ din[10]; + dout[ 5] = din[11] ^ din[ 9]; + dout[ 4] = din[10] ^ din[ 8]; + dout[ 3] = din[ 9] ^ din[ 7]; + dout[ 2] = din[ 8] ^ din[ 6]; + dout[ 1] = din[ 7] ^ din[ 5]; + dout[ 0] = din[ 6] ^ din[ 4]; + end + PRBS_P20: begin + dout[23] = din[19] ^ din[ 2]; + dout[22] = din[18] ^ din[ 1]; + dout[21] = din[17] ^ din[ 0]; + dout[20] = din[16] ^ din[19] ^ din[ 2]; + dout[19] = din[15] ^ din[18] ^ din[ 1]; + dout[18] = din[14] ^ din[17] ^ din[ 0]; + dout[17] = din[13] ^ din[16] ^ din[19] ^ din[ 2]; + dout[16] = din[12] ^ din[15] ^ din[18] ^ din[ 1]; + dout[15] = din[11] ^ din[14] ^ din[17] ^ din[ 0]; + dout[14] = din[10] ^ din[13] ^ din[16] ^ din[19] ^ din[ 2]; + dout[13] = din[ 9] ^ din[12] ^ din[15] ^ din[18] ^ din[ 1]; + dout[12] = din[ 8] ^ din[11] ^ din[14] ^ din[17] ^ din[ 0]; + dout[11] = din[ 7] ^ din[10] ^ din[13] ^ din[16] ^ din[19] ^ din[ 2]; + dout[10] = din[ 6] ^ din[ 9] ^ din[12] ^ din[15] ^ din[18] ^ din[ 1]; + dout[ 9] = din[ 5] ^ din[ 8] ^ din[11] ^ din[14] ^ din[17] ^ din[ 0]; + dout[ 8] = din[ 4] ^ din[ 7] ^ din[10] ^ din[13] ^ din[16] ^ din[19] ^ din[ 2]; + dout[ 7] = din[ 3] ^ din[ 6] ^ din[ 9] ^ din[12] ^ din[15] ^ din[18] ^ din[ 1]; + dout[ 6] = din[ 2] ^ din[ 5] ^ din[ 8] ^ din[11] ^ din[14] ^ din[17] ^ din[ 0]; + dout[ 5] = din[ 1] ^ din[ 4] ^ din[ 7] ^ din[10] ^ din[13] ^ din[16] ^ din[19] ^ din[ 2]; + dout[ 4] = din[ 0] ^ din[ 3] ^ din[ 6] ^ din[ 9] ^ din[12] ^ din[15] ^ din[18] ^ din[ 1]; + dout[ 3] = din[19] ^ din[ 5] ^ din[ 8] ^ din[11] ^ din[14] ^ din[17] ^ din[ 0]; + dout[ 2] = din[18] ^ din[ 4] ^ din[ 7] ^ din[10] ^ din[13] ^ din[16] ^ din[19] ^ din[ 2]; + dout[ 1] = din[17] ^ din[ 3] ^ din[ 6] ^ din[ 9] ^ din[12] ^ din[15] ^ din[18] ^ din[ 1]; + dout[ 0] = din[16] ^ din[ 2] ^ din[ 5] ^ din[ 8] ^ din[11] ^ din[14] ^ din[17] ^ din[ 0]; + end + endcase + pn1fn = dout; + end + endfunction + + // global toggle + + always @(posedge dac_clk) begin + if (dac_data_sync == 1'b1) begin + dac_valid_sel <= 1'b0; + end else if (dac_valid == 1'b1) begin + dac_valid_sel <= ~dac_valid_sel; + end + end + + // dac iq correction + + always @(posedge dac_clk) begin + dac_enable <= (dac_data_sel_s == 4'h2) ? 1'b1 : 1'b0; + if (dac_iqcor_valid_s == 1'b1) begin + dac_data <= dac_iqcor_data_s[15:4]; + end + end + + generate + if (DATAPATH_DISABLE == 1) begin + assign dac_iqcor_valid_s = dac_valid; + assign dac_iqcor_data_s = {dac_data_out, 4'd0}; + end else begin + ad_iqcor #(.Q_OR_I_N (Q_OR_I_N)) i_ad_iqcor ( + .clk (dac_clk), + .valid (dac_valid), + .data_in ({dac_data_out, 4'd0}), + .data_iq ({dac_data_in, 4'd0}), + .valid_out (dac_iqcor_valid_s), + .data_out (dac_iqcor_data_s), + .iqcor_enable (dac_iqcor_enb_s), + .iqcor_coeff_1 (dac_iqcor_coeff_1_s), + .iqcor_coeff_2 (dac_iqcor_coeff_2_s)); + end + endgenerate + + // dac mux + + always @(posedge dac_clk) begin + case (dac_data_sel_s) + 4'h9: dac_data_out <= dac_pn_data; + 4'h8: dac_data_out <= 16'h0; + 4'h6: dac_data_out <= dac_test_data[11:0]; + 4'h5: dac_data_out <= dac_data_out-1; + 4'h4: dac_data_out <= dac_data_out+1; + 4'h3: dac_data_out <= 12'd0; + 4'h2: dac_data_out <= dma_data[15:4]; + 4'h1: dac_data_out <= dac_pat_data[15:4]; + default: dac_data_out <= dac_dds_data[15:4]; + endcase + end + + function [23:0] pn23; + input [23:0] din; + reg [23:0] dout; + begin + dout = {din[22:0], din[22] ^ din[17]}; + pn23 = dout; + end + endfunction + + always @(posedge dac_clk) begin + if(dac_data_sel_s != 6) begin + dac_test_data <= 24'hffffff; + dac_test_counter <= 16'h0; + end else if (dac_test_counter == 1024) begin + dac_test_data <= 24'h0; + end else begin + dac_test_data <= pn23(dac_test_data); + dac_test_counter <= dac_test_counter + 1; + end + end + + // prbs sequences + + always @(posedge dac_clk) begin + if (dac_data_sync == 1'b1) begin + dac_pn_seq <= 24'hffffff; + dac_pn_data <= 12'd0; + end else if (dac_valid == 1'b1) begin + if (dac_valid_sel == 1'b1) begin + dac_pn_seq <= pn1fn(dac_pn_seq); + dac_pn_data <= dac_pn_seq[11: 0]; + end else begin + dac_pn_seq <= dac_pn_seq; + dac_pn_data <= dac_pn_seq[23:12]; + end + end + end + + // pattern + + always @(posedge dac_clk) begin + if (dac_valid == 1'b1) begin + if (dac_valid_sel == 1'b0) begin + dac_pat_data <= dac_pat_data_1_s; + end else begin + dac_pat_data <= dac_pat_data_2_s; + end + end + end + + // dds + + always @(posedge dac_clk) begin + if (dac_data_sync == 1'b1) begin + dac_dds_phase_0 <= dac_dds_init_1_s; + dac_dds_phase_1 <= dac_dds_init_2_s; + dac_dds_incr_0 <= dac_dds_incr_1_s; + dac_dds_incr_1 <= dac_dds_incr_2_s; + dac_dds_data <= 16'd0; + end else if (dac_valid == 1'b1) begin + dac_dds_phase_0 <= dac_dds_phase_0 + dac_dds_incr_0; + dac_dds_phase_1 <= dac_dds_phase_1 + dac_dds_incr_1; + dac_dds_incr_0 <= dac_dds_incr_0; + dac_dds_incr_1 <= dac_dds_incr_1; + dac_dds_data <= dac_dds_data_s; + end + end + + // dds + + generate + if (DATAPATH_DISABLE == 1) begin + assign dac_dds_data_s = 16'd0; + end else begin + ad_dds i_dds ( + .clk (dac_clk), + .dds_format (dac_dds_format), + .dds_phase_0 (dac_dds_phase_0), + .dds_scale_0 (dac_dds_scale_1_s), + .dds_phase_1 (dac_dds_phase_1), + .dds_scale_1 (dac_dds_scale_2_s), + .dds_data (dac_dds_data_s)); + end + endgenerate + + // single channel processor + + up_dac_channel #(.CHANNEL_ID(CHANNEL_ID)) i_up_dac_channel ( + .dac_clk (dac_clk), + .dac_rst (dac_rst), + .dac_dds_scale_1 (dac_dds_scale_1_s), + .dac_dds_init_1 (dac_dds_init_1_s), + .dac_dds_incr_1 (dac_dds_incr_1_s), + .dac_dds_scale_2 (dac_dds_scale_2_s), + .dac_dds_init_2 (dac_dds_init_2_s), + .dac_dds_incr_2 (dac_dds_incr_2_s), + .dac_pat_data_1 (dac_pat_data_1_s), + .dac_pat_data_2 (dac_pat_data_2_s), + .dac_iq_mode(), + .dac_data_sel (dac_data_sel_s), + .dac_iqcor_enb (dac_iqcor_enb_s), + .dac_iqcor_coeff_1 (dac_iqcor_coeff_1_s), + .dac_iqcor_coeff_2 (dac_iqcor_coeff_2_s), + .up_usr_datatype_be (), + .up_usr_datatype_signed (), + .up_usr_datatype_shift (), + .up_usr_datatype_total_bits (), + .up_usr_datatype_bits (), + .up_usr_interpolation_m (), + .up_usr_interpolation_n (), + .dac_usr_datatype_be (1'b0), + .dac_usr_datatype_signed (1'b1), + .dac_usr_datatype_shift (8'd0), + .dac_usr_datatype_total_bits (8'd16), + .dac_usr_datatype_bits (8'd16), + .dac_usr_interpolation_m (16'd1), + .dac_usr_interpolation_n (16'd1), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata), + .up_rack (up_rack)); + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/library/axi_adc_decimate/Makefile b/library/axi_adc_decimate/Makefile new file mode 100644 index 000000000..19396d233 --- /dev/null +++ b/library/axi_adc_decimate/Makefile @@ -0,0 +1,53 @@ +#################################################################################### +#################################################################################### +## Copyright 2011(c) Analog Devices, Inc. +## Auto-generated, do not modify! +#################################################################################### +#################################################################################### + +M_DEPS += ../common/ad_rst.v +M_DEPS += ../common/up_axi.v +M_DEPS += ../common/up_xfer_cntrl.v +M_DEPS += ../scripts/adi_env.tcl +M_DEPS += ../scripts/adi_ip.tcl +M_DEPS += axi_adc_decimate.v +M_DEPS += axi_adc_decimate_constr.xdc +M_DEPS += axi_adc_decimate_ip.tcl +M_DEPS += axi_adc_decimate_reg.v +M_DEPS += cic_decim.v +M_DEPS += fir_decim.v + +M_VIVADO := vivado -mode batch -source + +M_FLIST := *.cache +M_FLIST += *.data +M_FLIST += *.xpr +M_FLIST += *.log +M_FLIST += component.xml +M_FLIST += *.jou +M_FLIST += xgui +M_FLIST += *.ip_user_files +M_FLIST += *.srcs +M_FLIST += *.hw +M_FLIST += *.sim +M_FLIST += .Xil + + + +.PHONY: all clean clean-all +all: axi_adc_decimate.xpr + + +clean:clean-all + + +clean-all: + rm -rf $(M_FLIST) + + +axi_adc_decimate.xpr: $(M_DEPS) + -rm -rf $(M_FLIST) + $(M_VIVADO) axi_adc_decimate_ip.tcl >> axi_adc_decimate_ip.log 2>&1 + +#################################################################################### +#################################################################################### diff --git a/library/axi_adc_decimate/axi_adc_decimate.v b/library/axi_adc_decimate/axi_adc_decimate.v new file mode 100644 index 000000000..03908a42d --- /dev/null +++ b/library/axi_adc_decimate/axi_adc_decimate.v @@ -0,0 +1,272 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_adc_decimate( + + input adc_clk, + + input [15:0] adc_data_a, + input [15:0] adc_data_b, + input adc_valid_a, + input adc_valid_b, + + output reg [15:0] adc_dec_data_a, + output reg [15:0] adc_dec_data_b, + output reg adc_dec_valid_a, + output reg adc_dec_valid_b, + + // axi interface + + input s_axi_aclk, + input s_axi_aresetn, + input s_axi_awvalid, + input [31:0] s_axi_awaddr, + input [ 2:0] s_axi_awprot, + output s_axi_awready, + input s_axi_wvalid, + input [31:0] s_axi_wdata, + input [ 3:0] s_axi_wstrb, + output s_axi_wready, + output s_axi_bvalid, + output [ 1:0] s_axi_bresp, + input s_axi_bready, + input s_axi_arvalid, + input [31:0] s_axi_araddr, + input [ 2:0] s_axi_arprot, + output s_axi_arready, + output s_axi_rvalid, + output [31:0] s_axi_rdata, + output [ 1:0] s_axi_rresp, + input s_axi_rready); + + // internal signals + + wire up_clk; + wire up_rstn; + wire [13:0] up_waddr; + wire [31:0] up_wdata; + wire up_wack; + wire up_wreq; + wire up_rack; + wire [31:0] up_rdata; + wire up_rreq; + wire [13:0] up_raddr; + + wire [31:0] decimation_ratio; + wire [31:0] filter_mask; + + wire [105:0] adc_cic_data_a; + wire adc_cic_valid_a; + wire [105:0] adc_cic_data_b; + wire adc_cic_valid_b; + + wire [25:0] adc_fir_data_a; + wire adc_fir_valid_a; + wire [25:0] adc_fir_data_b; + wire adc_fir_valid_b; + + reg adc_dec_valid_a_filter; + reg adc_dec_valid_b_filter; + + reg [31:0] decimation_counter; + reg [15:0] decim_rate_cic; + + // signal name changes + + assign up_clk = s_axi_aclk; + assign up_rstn = s_axi_aresetn; + + cic_decim cic_decimation_a ( + .clk(adc_clk), + .clk_enable(adc_valid_a), + .reset(adc_rst), + .filter_in(adc_data_a[11:0]), + .rate(decim_rate_cic), + .load_rate(1'b0), + .filter_out(adc_cic_data_a), + .ce_out(adc_cic_valid_a)); + + cic_decim cic_decimation_b ( + .clk(adc_clk), + .clk_enable(adc_valid_b), + .reset(adc_rst), + .filter_in(adc_data_b[11:0]), + .rate(decim_rate_cic), + .load_rate(1'b0), + .filter_out(adc_cic_data_b), + .ce_out(adc_cic_valid_b)); + + fir_decim fir_decimation_a ( + .clk(adc_clk), + .clk_enable(adc_cic_valid_a), + .reset(adc_rst), + .filter_in(adc_cic_data_a[11:0]), + .filter_out(adc_fir_data_a), + .ce_out(adc_fir_valid_a)); + + fir_decim fir_decimation_b ( + .clk(adc_clk), + .clk_enable(adc_cic_valid_b), + .reset(adc_rst), + .filter_in(adc_cic_data_b[11:0]), + .filter_out(adc_fir_data_b), + .ce_out(adc_fir_valid_b)); + + always @(*) begin + case (filter_mask) + 16'h1: adc_dec_data_a = {adc_fir_data_a[25], adc_fir_data_a[25:11]}; + 16'h2: adc_dec_data_a = {adc_fir_data_a[25], adc_fir_data_a[25:11]}; + 16'h3: adc_dec_data_a = {adc_fir_data_a[25], adc_fir_data_a[25:11]}; + 16'h6: adc_dec_data_a = {adc_fir_data_a[25], adc_fir_data_a[25:11]}; + 16'h7: adc_dec_data_a = {adc_fir_data_a[25], adc_fir_data_a[25:11]}; + default: adc_dec_data_a = adc_data_a; + endcase + + case (filter_mask) + 16'h1: adc_dec_valid_a_filter = adc_fir_valid_a; + 16'h2: adc_dec_valid_a_filter = adc_fir_valid_a; + 16'h3: adc_dec_valid_a_filter = adc_fir_valid_a; + 16'h6: adc_dec_valid_a_filter = adc_fir_valid_a; + 16'h7: adc_dec_valid_a_filter = adc_fir_valid_a; + default: adc_dec_valid_a_filter = adc_valid_a; + endcase + + case (filter_mask) + 16'h1: adc_dec_data_b = {adc_fir_data_b[25], adc_fir_data_b[25:11]}; + 16'h2: adc_dec_data_b = {adc_fir_data_b[25], adc_fir_data_b[25:11]}; + 16'h3: adc_dec_data_b = {adc_fir_data_b[25], adc_fir_data_b[25:11]}; + 16'h6: adc_dec_data_b = {adc_fir_data_b[25], adc_fir_data_b[25:11]}; + 16'h7: adc_dec_data_b = {adc_fir_data_b[25], adc_fir_data_b[25:11]}; + default: adc_dec_data_b = adc_data_b; + endcase + + case (filter_mask) + 16'h1: adc_dec_valid_b_filter = adc_fir_valid_b; + 16'h2: adc_dec_valid_b_filter = adc_fir_valid_b; + 16'h3: adc_dec_valid_b_filter = adc_fir_valid_b; + 16'h6: adc_dec_valid_b_filter = adc_fir_valid_b; + 16'h7: adc_dec_valid_b_filter = adc_fir_valid_b; + default: adc_dec_valid_b_filter = adc_valid_b; + endcase + + case (filter_mask) + 16'h1: decim_rate_cic = 16'd5; + 16'h2: decim_rate_cic = 16'd50; + 16'h3: decim_rate_cic = 16'd500; + 16'h6: decim_rate_cic = 16'd5000; + 16'h7: decim_rate_cic = 16'd50000; + default: decim_rate_cic = 16'd1; + endcase + end + + always @(posedge adc_clk) begin + if (adc_rst == 1'b1) begin + decimation_counter <= 32'b0; + adc_dec_valid_a <= 1'b0; + adc_dec_valid_b <= 1'b0; + end else begin + if (adc_dec_valid_a_filter == 1'b1) begin + if (decimation_counter < decimation_ratio) begin + decimation_counter <= decimation_counter + 1; + adc_dec_valid_a <= 1'b0; + adc_dec_valid_b <= 1'b0; + end else begin + decimation_counter <= 0; + adc_dec_valid_a <= 1'b1; + adc_dec_valid_b <= 1'b1; + end + end else begin + adc_dec_valid_a <= 1'b0; + adc_dec_valid_b <= 1'b0; + end + end + end + + axi_adc_decimate_reg axi_adc_decimate_reg ( + + .clk (adc_clk), + .adc_rst (adc_rst), + + .adc_decimation_ratio (decimation_ratio), + .adc_filter_mask (filter_mask), + + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata), + .up_rack (up_rack)); + + up_axi i_up_axi ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_axi_awvalid (s_axi_awvalid), + .up_axi_awaddr (s_axi_awaddr), + .up_axi_awready (s_axi_awready), + .up_axi_wvalid (s_axi_wvalid), + .up_axi_wdata (s_axi_wdata), + .up_axi_wstrb (s_axi_wstrb), + .up_axi_wready (s_axi_wready), + .up_axi_bvalid (s_axi_bvalid), + .up_axi_bresp (s_axi_bresp), + .up_axi_bready (s_axi_bready), + .up_axi_arvalid (s_axi_arvalid), + .up_axi_araddr (s_axi_araddr), + .up_axi_arready (s_axi_arready), + .up_axi_rvalid (s_axi_rvalid), + .up_axi_rresp (s_axi_rresp), + .up_axi_rdata (s_axi_rdata), + .up_axi_rready (s_axi_rready), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata), + .up_rack (up_rack)); + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/library/axi_adc_decimate/axi_adc_decimate_constr.xdc b/library/axi_adc_decimate/axi_adc_decimate_constr.xdc new file mode 100644 index 000000000..3f786eb5d --- /dev/null +++ b/library/axi_adc_decimate/axi_adc_decimate_constr.xdc @@ -0,0 +1,8 @@ +set_property shreg_extract no [get_cells -hier -filter {name =~ *up_xfer_state*}] +set_property shreg_extract no [get_cells -hier -filter {name =~ *d_xfer_toggle*}] +set_property shreg_extract no [get_cells -hier -filter {name =~ *up_xfer_toggle*}] +set_property shreg_extract no [get_cells -hier -filter {name =~ *ad_rst_sync*}] + +set_false_path -from [get_cells -hier -filter {name =~ *d_xfer_toggle_reg && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *up_xfer_state_m1_reg && IS_SEQUENTIAL}] +set_false_path -from [get_cells -hier -filter {name =~ *up_xfer_toggle_reg && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *d_xfer_toggle_m1_reg && IS_SEQUENTIAL}] +set_false_path -from [get_cells -hier -filter {name =~ *up_xfer_data* && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *d_data_cntrl* && IS_SEQUENTIAL}] diff --git a/library/axi_adc_decimate/axi_adc_decimate_ip.tcl b/library/axi_adc_decimate/axi_adc_decimate_ip.tcl new file mode 100644 index 000000000..42173905f --- /dev/null +++ b/library/axi_adc_decimate/axi_adc_decimate_ip.tcl @@ -0,0 +1,25 @@ +# ip + +source ../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip.tcl + +adi_ip_create axi_adc_decimate +adi_ip_files axi_adc_decimate [list \ + "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ + "$ad_hdl_dir/library/common/ad_rst.v" \ + "$ad_hdl_dir/library/common/up_axi.v" \ + "axi_adc_decimate_constr.xdc" \ + "fir_decim.v" \ + "cic_decim.v" \ + "axi_adc_decimate_reg.v" \ + "axi_adc_decimate.v" ] + +adi_ip_properties axi_adc_decimate +adi_ip_constraints axi_adc_decimate [list \ + "axi_adc_decimate_constr.xdc" ] + +ipx::remove_bus_interface {clk} [ipx::current_core] +ipx::associate_bus_interfaces -busif s_axi -clock s_axi_aclk [ipx::current_core] + +ipx::save_core [ipx::current_core] + diff --git a/library/axi_adc_decimate/axi_adc_decimate_reg.v b/library/axi_adc_decimate/axi_adc_decimate_reg.v new file mode 100644 index 000000000..47b4b6ab1 --- /dev/null +++ b/library/axi_adc_decimate/axi_adc_decimate_reg.v @@ -0,0 +1,137 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_adc_decimate_reg( + + input clk, + output adc_rst, + + output [31:0] adc_decimation_ratio, + output [31:0] adc_filter_mask, + + // bus interface + + input up_rstn, + input up_clk, + input up_wreq, + input [13:0] up_waddr, + input [31:0] up_wdata, + output reg up_wack, + input up_rreq, + input [13:0] up_raddr, + output reg [31:0] up_rdata, + output reg up_rack); + + // internal signals + + wire up_wreq_s; + wire up_rreq_s; + + // internal registers + + reg [31:0] up_version = 32'h00010000; + reg [31:0] up_scratch = 32'h0; + + reg [31:0] up_decimation_ratio = 32'h0; + reg [31:0] up_filter_mask = 32'h0; + + assign up_wreq_s = ((up_waddr[13:5] == 6'h00)) ? up_wreq : 1'b0; + assign up_rreq_s = ((up_raddr[13:5] == 6'h00)) ? up_rreq : 1'b0; + + ad_rst i_core_rst_reg (.preset(~up_rstn), .clk(clk), .rst(adc_rst)); + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_wack <= 'd0; + up_scratch <= 'd0; + up_decimation_ratio <= 'd0; + up_filter_mask <= 'd0; + end else begin + up_wack <= up_wreq_s; + if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h1)) begin + up_scratch <= up_wdata; + end + if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h10)) begin + up_decimation_ratio <= up_wdata; + end + if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h11)) begin + up_filter_mask <= up_wdata; + end + end + end + + // processor read interface + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_rack <= 'd0; + up_rdata <= 'd0; + end else begin + up_rack <= up_rreq_s; + if (up_rreq_s == 1'b1) begin + case (up_raddr[4:0]) + 5'h0: up_rdata <= up_version; + 5'h1: up_rdata <= up_scratch; + 5'h10: up_rdata <= up_decimation_ratio; + 5'h11: up_rdata <= up_filter_mask; + default: up_rdata <= 0; + endcase + end else begin + up_rdata <= 32'd0; + end + end + end + + up_xfer_cntrl #(.DATA_WIDTH(64)) i_xfer_cntrl ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_data_cntrl ({ up_decimation_ratio, // 32 + up_filter_mask}), // 32 + + .up_xfer_done (), + .d_rst (1'b0), + .d_clk (clk), + .d_data_cntrl ({ adc_decimation_ratio, // 32 + adc_filter_mask})); // 32 + +endmodule + +// *************************************************************************** +// *************************************************************************** + diff --git a/library/axi_adc_decimate/cic_decim.v b/library/axi_adc_decimate/cic_decim.v new file mode 100644 index 000000000..bbe15e9b6 --- /dev/null +++ b/library/axi_adc_decimate/cic_decim.v @@ -0,0 +1,610 @@ +// ------------------------------------------------------------- +// +// Module: cic_decim +// Generated by MATLAB(R) 9.0 and the Filter Design HDL Coder 3.0. +// Generated on: 2016-07-05 15:46:18 +// ------------------------------------------------------------- + +// ------------------------------------------------------------- +// HDL Code Generation Options: +// +// OptimizeForHDL: on +// EDAScriptGeneration: off +// AddPipelineRegisters: on +// Name: cic_decim +// AddRatePort: on +// InputDataType: numerictype(1,12,11) +// TargetLanguage: Verilog +// TestBenchName: cicdecimfilt_copy_tb +// TestBenchStimulus: step ramp chirp noise +// GenerateHDLTestBench: off + +// ------------------------------------------------------------- +// HDL Implementation : Fully parallel +// ------------------------------------------------------------- +// Filter Settings: +// +// Discrete-Time FIR Multirate Filter (real) +// ----------------------------------------- +// Filter Structure : Cascaded Integrator-Comb Decimator +// Decimation Factor : 50000 +// Differential Delay : 1 +// Number of Sections : 6 +// Stable : Yes +// Linear Phase : No +// +// ------------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module cic_decim + ( + clk, + clk_enable, + reset, + filter_in, + rate, + load_rate, + filter_out, + ce_out + ); + + input clk; + input clk_enable; + input reset; + input signed [11:0] filter_in; //sfix12_En11 + input [15:0] rate; //ufix16 + input load_rate; + output signed [105:0] filter_out; //sfix106_En11 + output ce_out; + +//////////////////////////////////////////////////////////////// +//Module Architecture: cic_decim +//////////////////////////////////////////////////////////////// + // Local Functions + // Type Definitions + // Constants + // Signals + reg [15:0] rate_register; // ufix16 + reg [15:0] cur_count; // ufix16 + wire phase_1; // boolean + wire ce_delayline; // boolean + reg int_delay_pipe [0:4] ; // boolean + wire ce_gated; // boolean + reg ce_out_reg; // boolean + // + reg signed [11:0] input_register; // sfix12_En11 + // -- Section 1 Signals + wire signed [11:0] section_in1; // sfix12_En11 + wire signed [105:0] section_cast1; // sfix106_En11 + wire signed [105:0] sum1; // sfix106_En11 + reg signed [105:0] section_out1; // sfix106_En11 + wire signed [105:0] add_cast; // sfix106_En11 + wire signed [105:0] add_cast_1; // sfix106_En11 + wire signed [106:0] add_temp; // sfix107_En11 + // -- Section 2 Signals + wire signed [105:0] section_in2; // sfix106_En11 + wire signed [105:0] sum2; // sfix106_En11 + reg signed [105:0] section_out2; // sfix106_En11 + wire signed [105:0] add_cast_2; // sfix106_En11 + wire signed [105:0] add_cast_3; // sfix106_En11 + wire signed [106:0] add_temp_1; // sfix107_En11 + // -- Section 3 Signals + wire signed [105:0] section_in3; // sfix106_En11 + wire signed [105:0] sum3; // sfix106_En11 + reg signed [105:0] section_out3; // sfix106_En11 + wire signed [105:0] add_cast_4; // sfix106_En11 + wire signed [105:0] add_cast_5; // sfix106_En11 + wire signed [106:0] add_temp_2; // sfix107_En11 + // -- Section 4 Signals + wire signed [105:0] section_in4; // sfix106_En11 + wire signed [105:0] sum4; // sfix106_En11 + reg signed [105:0] section_out4; // sfix106_En11 + wire signed [105:0] add_cast_6; // sfix106_En11 + wire signed [105:0] add_cast_7; // sfix106_En11 + wire signed [106:0] add_temp_3; // sfix107_En11 + // -- Section 5 Signals + wire signed [105:0] section_in5; // sfix106_En11 + wire signed [105:0] sum5; // sfix106_En11 + reg signed [105:0] section_out5; // sfix106_En11 + wire signed [105:0] add_cast_8; // sfix106_En11 + wire signed [105:0] add_cast_9; // sfix106_En11 + wire signed [106:0] add_temp_4; // sfix107_En11 + // -- Section 6 Signals + wire signed [105:0] section_in6; // sfix106_En11 + wire signed [105:0] sum6; // sfix106_En11 + reg signed [105:0] section_out6; // sfix106_En11 + wire signed [105:0] add_cast_10; // sfix106_En11 + wire signed [105:0] add_cast_11; // sfix106_En11 + wire signed [106:0] add_temp_5; // sfix107_En11 + // -- Section 7 Signals + wire signed [105:0] section_in7; // sfix106_En11 + reg signed [105:0] diff1; // sfix106_En11 + wire signed [105:0] section_out7; // sfix106_En11 + wire signed [105:0] sub_cast; // sfix106_En11 + wire signed [105:0] sub_cast_1; // sfix106_En11 + wire signed [106:0] sub_temp; // sfix107_En11 + reg signed [105:0] cic_pipeline7; // sfix106_En11 + // -- Section 8 Signals + wire signed [105:0] section_in8; // sfix106_En11 + reg signed [105:0] diff2; // sfix106_En11 + wire signed [105:0] section_out8; // sfix106_En11 + wire signed [105:0] sub_cast_2; // sfix106_En11 + wire signed [105:0] sub_cast_3; // sfix106_En11 + wire signed [106:0] sub_temp_1; // sfix107_En11 + reg signed [105:0] cic_pipeline8; // sfix106_En11 + // -- Section 9 Signals + wire signed [105:0] section_in9; // sfix106_En11 + reg signed [105:0] diff3; // sfix106_En11 + wire signed [105:0] section_out9; // sfix106_En11 + wire signed [105:0] sub_cast_4; // sfix106_En11 + wire signed [105:0] sub_cast_5; // sfix106_En11 + wire signed [106:0] sub_temp_2; // sfix107_En11 + reg signed [105:0] cic_pipeline9; // sfix106_En11 + // -- Section 10 Signals + wire signed [105:0] section_in10; // sfix106_En11 + reg signed [105:0] diff4; // sfix106_En11 + wire signed [105:0] section_out10; // sfix106_En11 + wire signed [105:0] sub_cast_6; // sfix106_En11 + wire signed [105:0] sub_cast_7; // sfix106_En11 + wire signed [106:0] sub_temp_3; // sfix107_En11 + reg signed [105:0] cic_pipeline10; // sfix106_En11 + // -- Section 11 Signals + wire signed [105:0] section_in11; // sfix106_En11 + reg signed [105:0] diff5; // sfix106_En11 + wire signed [105:0] section_out11; // sfix106_En11 + wire signed [105:0] sub_cast_8; // sfix106_En11 + wire signed [105:0] sub_cast_9; // sfix106_En11 + wire signed [106:0] sub_temp_4; // sfix107_En11 + reg signed [105:0] cic_pipeline11; // sfix106_En11 + // -- Section 12 Signals + wire signed [105:0] section_in12; // sfix106_En11 + reg signed [105:0] diff6; // sfix106_En11 + wire signed [105:0] section_out12; // sfix106_En11 + wire signed [105:0] sub_cast_10; // sfix106_En11 + wire signed [105:0] sub_cast_11; // sfix106_En11 + wire signed [106:0] sub_temp_5; // sfix107_En11 + reg [6:0] bitgain; // ufix7 + wire signed [105:0] output_typeconvert; // sfix106_En11 + wire signed [105:0] muxinput_14; // sfix106_E3 + wire signed [105:0] muxinput_34; // sfix106_E23 + wire signed [105:0] muxinput_54; // sfix106_E43 + wire signed [105:0] muxinput_74; // sfix106_E63 + wire signed [105:0] muxinput_94; // sfix106_E83 + // + reg signed [105:0] output_register; // sfix106_En11 + + // Block Statements + // ------------------ CE Output Generation ------------------ + + always @ (posedge clk or posedge reset) + begin: ce_output + if (reset == 1'b1) begin + cur_count <= 16'b0000000000000000; + end + else begin + if (clk_enable == 1'b1) begin + if (load_rate == 1'b1) begin + cur_count <= 16'b0000000000000001; + end + else if (cur_count == rate_register - 1) begin + cur_count <= 16'b0000000000000000; + end + else begin + cur_count <= cur_count + 1; + end + end + end + end // ce_output + + assign phase_1 = (cur_count == 16'b0000000000000001 && clk_enable == 1'b1)? 1 : 0; + + always @ (posedge clk or posedge reset) + begin: ce_delay + if (reset == 1'b1) begin + int_delay_pipe[0] <= 1'b0; + int_delay_pipe[1] <= 1'b0; + int_delay_pipe[2] <= 1'b0; + int_delay_pipe[3] <= 1'b0; + int_delay_pipe[4] <= 1'b0; + end + else begin + if (phase_1 == 1'b1) begin + int_delay_pipe[1] <= int_delay_pipe[0]; + int_delay_pipe[2] <= int_delay_pipe[1]; + int_delay_pipe[3] <= int_delay_pipe[2]; + int_delay_pipe[4] <= int_delay_pipe[3]; + int_delay_pipe[0] <= clk_enable; + end + end + end // ce_delay + assign ce_delayline = int_delay_pipe[4]; + + assign ce_gated = ce_delayline & phase_1; + + // ------------------ CE Output Register ------------------ + + always @ (posedge clk or posedge reset) + begin: ce_output_register + if (reset == 1'b1) begin + ce_out_reg <= 1'b0; + end + else begin + ce_out_reg <= ce_gated; + end + end // ce_output_register + + // ------------------ Input Register ------------------ + + always @ (posedge clk or posedge reset) + begin: input_reg_process + if (reset == 1'b1) begin + input_register <= 0; + rate_register <= 0; + end + else begin + if (clk_enable == 1'b1) begin + input_register <= filter_in; + rate_register <= rate; + end + end + end // input_reg_process + + // ------------------ Section # 1 : Integrator ------------------ + + assign section_in1 = input_register; + + assign section_cast1 = $signed({{94{section_in1[11]}}, section_in1}); + + assign add_cast = section_cast1; + assign add_cast_1 = section_out1; + assign add_temp = add_cast + add_cast_1; + assign sum1 = add_temp[105:0]; + + always @ (posedge clk or posedge reset) + begin: integrator_delay_section1 + if (reset == 1'b1) begin + section_out1 <= 0; + end + else begin + if (clk_enable == 1'b1) begin + section_out1 <= sum1; + end + end + end // integrator_delay_section1 + + // ------------------ Section # 2 : Integrator ------------------ + + assign section_in2 = section_out1; + + assign add_cast_2 = section_in2; + assign add_cast_3 = section_out2; + assign add_temp_1 = add_cast_2 + add_cast_3; + assign sum2 = add_temp_1[105:0]; + + always @ (posedge clk or posedge reset) + begin: integrator_delay_section2 + if (reset == 1'b1) begin + section_out2 <= 0; + end + else begin + if (clk_enable == 1'b1) begin + section_out2 <= sum2; + end + end + end // integrator_delay_section2 + + // ------------------ Section # 3 : Integrator ------------------ + + assign section_in3 = section_out2; + + assign add_cast_4 = section_in3; + assign add_cast_5 = section_out3; + assign add_temp_2 = add_cast_4 + add_cast_5; + assign sum3 = add_temp_2[105:0]; + + always @ (posedge clk or posedge reset) + begin: integrator_delay_section3 + if (reset == 1'b1) begin + section_out3 <= 0; + end + else begin + if (clk_enable == 1'b1) begin + section_out3 <= sum3; + end + end + end // integrator_delay_section3 + + // ------------------ Section # 4 : Integrator ------------------ + + assign section_in4 = section_out3; + + assign add_cast_6 = section_in4; + assign add_cast_7 = section_out4; + assign add_temp_3 = add_cast_6 + add_cast_7; + assign sum4 = add_temp_3[105:0]; + + always @ (posedge clk or posedge reset) + begin: integrator_delay_section4 + if (reset == 1'b1) begin + section_out4 <= 0; + end + else begin + if (clk_enable == 1'b1) begin + section_out4 <= sum4; + end + end + end // integrator_delay_section4 + + // ------------------ Section # 5 : Integrator ------------------ + + assign section_in5 = section_out4; + + assign add_cast_8 = section_in5; + assign add_cast_9 = section_out5; + assign add_temp_4 = add_cast_8 + add_cast_9; + assign sum5 = add_temp_4[105:0]; + + always @ (posedge clk or posedge reset) + begin: integrator_delay_section5 + if (reset == 1'b1) begin + section_out5 <= 0; + end + else begin + if (clk_enable == 1'b1) begin + section_out5 <= sum5; + end + end + end // integrator_delay_section5 + + // ------------------ Section # 6 : Integrator ------------------ + + assign section_in6 = section_out5; + + assign add_cast_10 = section_in6; + assign add_cast_11 = section_out6; + assign add_temp_5 = add_cast_10 + add_cast_11; + assign sum6 = add_temp_5[105:0]; + + always @ (posedge clk or posedge reset) + begin: integrator_delay_section6 + if (reset == 1'b1) begin + section_out6 <= 0; + end + else begin + if (clk_enable == 1'b1) begin + section_out6 <= sum6; + end + end + end // integrator_delay_section6 + + // ------------------ Section # 7 : Comb ------------------ + + assign section_in7 = section_out6; + + assign sub_cast = section_in7; + assign sub_cast_1 = diff1; + assign sub_temp = sub_cast - sub_cast_1; + assign section_out7 = sub_temp[105:0]; + + always @ (posedge clk or posedge reset) + begin: comb_delay_section7 + if (reset == 1'b1) begin + diff1 <= 0; + end + else begin + if (phase_1 == 1'b1) begin + diff1 <= section_in7; + end + end + end // comb_delay_section7 + + always @ (posedge clk or posedge reset) + begin: cic_pipeline_process_section7 + if (reset == 1'b1) begin + cic_pipeline7 <= 0; + end + else begin + if (phase_1 == 1'b1) begin + cic_pipeline7 <= section_out7; + end + end + end // cic_pipeline_process_section7 + + // ------------------ Section # 8 : Comb ------------------ + + assign section_in8 = cic_pipeline7; + + assign sub_cast_2 = section_in8; + assign sub_cast_3 = diff2; + assign sub_temp_1 = sub_cast_2 - sub_cast_3; + assign section_out8 = sub_temp_1[105:0]; + + always @ (posedge clk or posedge reset) + begin: comb_delay_section8 + if (reset == 1'b1) begin + diff2 <= 0; + end + else begin + if (phase_1 == 1'b1) begin + diff2 <= section_in8; + end + end + end // comb_delay_section8 + + always @ (posedge clk or posedge reset) + begin: cic_pipeline_process_section8 + if (reset == 1'b1) begin + cic_pipeline8 <= 0; + end + else begin + if (phase_1 == 1'b1) begin + cic_pipeline8 <= section_out8; + end + end + end // cic_pipeline_process_section8 + + // ------------------ Section # 9 : Comb ------------------ + + assign section_in9 = cic_pipeline8; + + assign sub_cast_4 = section_in9; + assign sub_cast_5 = diff3; + assign sub_temp_2 = sub_cast_4 - sub_cast_5; + assign section_out9 = sub_temp_2[105:0]; + + always @ (posedge clk or posedge reset) + begin: comb_delay_section9 + if (reset == 1'b1) begin + diff3 <= 0; + end + else begin + if (phase_1 == 1'b1) begin + diff3 <= section_in9; + end + end + end // comb_delay_section9 + + always @ (posedge clk or posedge reset) + begin: cic_pipeline_process_section9 + if (reset == 1'b1) begin + cic_pipeline9 <= 0; + end + else begin + if (phase_1 == 1'b1) begin + cic_pipeline9 <= section_out9; + end + end + end // cic_pipeline_process_section9 + + // ------------------ Section # 10 : Comb ------------------ + + assign section_in10 = cic_pipeline9; + + assign sub_cast_6 = section_in10; + assign sub_cast_7 = diff4; + assign sub_temp_3 = sub_cast_6 - sub_cast_7; + assign section_out10 = sub_temp_3[105:0]; + + always @ (posedge clk or posedge reset) + begin: comb_delay_section10 + if (reset == 1'b1) begin + diff4 <= 0; + end + else begin + if (phase_1 == 1'b1) begin + diff4 <= section_in10; + end + end + end // comb_delay_section10 + + always @ (posedge clk or posedge reset) + begin: cic_pipeline_process_section10 + if (reset == 1'b1) begin + cic_pipeline10 <= 0; + end + else begin + if (phase_1 == 1'b1) begin + cic_pipeline10 <= section_out10; + end + end + end // cic_pipeline_process_section10 + + // ------------------ Section # 11 : Comb ------------------ + + assign section_in11 = cic_pipeline10; + + assign sub_cast_8 = section_in11; + assign sub_cast_9 = diff5; + assign sub_temp_4 = sub_cast_8 - sub_cast_9; + assign section_out11 = sub_temp_4[105:0]; + + always @ (posedge clk or posedge reset) + begin: comb_delay_section11 + if (reset == 1'b1) begin + diff5 <= 0; + end + else begin + if (phase_1 == 1'b1) begin + diff5 <= section_in11; + end + end + end // comb_delay_section11 + + always @ (posedge clk or posedge reset) + begin: cic_pipeline_process_section11 + if (reset == 1'b1) begin + cic_pipeline11 <= 0; + end + else begin + if (phase_1 == 1'b1) begin + cic_pipeline11 <= section_out11; + end + end + end // cic_pipeline_process_section11 + + // ------------------ Section # 12 : Comb ------------------ + + assign section_in12 = cic_pipeline11; + + assign sub_cast_10 = section_in12; + assign sub_cast_11 = diff6; + assign sub_temp_5 = sub_cast_10 - sub_cast_11; + assign section_out12 = sub_temp_5[105:0]; + + always @ (posedge clk or posedge reset) + begin: comb_delay_section12 + if (reset == 1'b1) begin + diff6 <= 0; + end + else begin + if (phase_1 == 1'b1) begin + diff6 <= section_in12; + end + end + end // comb_delay_section12 + + always @(rate_register) + begin + case(rate_register) + 16'b0000000000000101 : bitgain = 7'b0001110; + 16'b0000000000110010 : bitgain = 7'b0100010; + 16'b0000000111110100 : bitgain = 7'b0110110; + 16'b0001001110001000 : bitgain = 7'b1001010; + default : bitgain = 7'b1011110; + endcase + end + + assign muxinput_14 = $signed({{14{section_out12[105]}}, section_out12[105:14]}); + + assign muxinput_34 = $signed({{34{section_out12[105]}}, section_out12[105:34]}); + + assign muxinput_54 = $signed({{54{section_out12[105]}}, section_out12[105:54]}); + + assign muxinput_74 = $signed({{74{section_out12[105]}}, section_out12[105:74]}); + + assign muxinput_94 = $signed({{94{section_out12[105]}}, section_out12[105:94]}); + + assign output_typeconvert = (bitgain == 7'b0001110) ? muxinput_14 : + (bitgain == 7'b0100010) ? muxinput_34 : + (bitgain == 7'b0110110) ? muxinput_54 : + (bitgain == 7'b1001010) ? muxinput_74 : + muxinput_94; + // ------------------ Output Register ------------------ + + always @ (posedge clk or posedge reset) + begin: output_reg_process + if (reset == 1'b1) begin + output_register <= 0; + end + else begin + if (phase_1 == 1'b1) begin + output_register <= output_typeconvert; + end + end + end // output_reg_process + + // Assignment Statements + assign ce_out = ce_out_reg; + assign filter_out = output_register; +endmodule // cic_decim diff --git a/library/axi_adc_decimate/fir_decim.v b/library/axi_adc_decimate/fir_decim.v new file mode 100644 index 000000000..ef23f6924 --- /dev/null +++ b/library/axi_adc_decimate/fir_decim.v @@ -0,0 +1,331 @@ +// ------------------------------------------------------------- +// +// Module: fir_decim +// Generated by MATLAB(R) 9.0 and the Filter Design HDL Coder 3.0. +// Generated on: 2016-07-05 15:45:22 +// ------------------------------------------------------------- + +// ------------------------------------------------------------- +// HDL Code Generation Options: +// +// FIRAdderStyle: tree +// OptimizeForHDL: on +// EDAScriptGeneration: off +// AddPipelineRegisters: on +// Name: fir_decim +// TargetLanguage: Verilog +// TestBenchName: fo_copy_tb +// TestBenchStimulus: step ramp chirp noise +// GenerateHDLTestBench: off + +// ------------------------------------------------------------- +// HDL Implementation : Fully parallel +// Multipliers : 6 +// Folding Factor : 1 +// ------------------------------------------------------------- +// Filter Settings: +// +// Discrete-Time FIR Multirate Filter (real) +// ----------------------------------------- +// Filter Structure : Direct-Form FIR Polyphase Decimator +// Decimation Factor : 2 +// Polyphase Length : 3 +// Filter Length : 6 +// Stable : Yes +// Linear Phase : Yes (Type 2) +// +// Arithmetic : fixed +// Numerator : s12,11 -> [-1 1) +// ------------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module fir_decim + ( + clk, + clk_enable, + reset, + filter_in, + filter_out, + ce_out + ); + + input clk; + input clk_enable; + input reset; + input signed [11:0] filter_in; //sfix12_En11 + output signed [25:0] filter_out; //sfix26_En22 + output ce_out; + +//////////////////////////////////////////////////////////////// +//Module Architecture: fir_decim +//////////////////////////////////////////////////////////////// + // Local Functions + // Type Definitions + // Constants + parameter signed [11:0] coeffphase1_1 = 12'b000011010101; //sfix12_En11 + parameter signed [11:0] coeffphase1_2 = 12'b011011110010; //sfix12_En11 + parameter signed [11:0] coeffphase1_3 = 12'b110000111110; //sfix12_En11 + parameter signed [11:0] coeffphase2_1 = 12'b110000111110; //sfix12_En11 + parameter signed [11:0] coeffphase2_2 = 12'b011011110010; //sfix12_En11 + parameter signed [11:0] coeffphase2_3 = 12'b000011010101; //sfix12_En11 + + // Signals + reg [1:0] ring_count; // ufix2 + wire phase_0; // boolean + wire phase_1; // boolean + reg ce_out_reg; // boolean + reg signed [11:0] input_register; // sfix12_En11 + reg signed [11:0] input_pipeline_phase0 [0:1] ; // sfix12_En11 + reg signed [11:0] input_pipeline_phase1 [0:2] ; // sfix12_En11 + wire signed [23:0] product_phase0_1; // sfix24_En22 + wire signed [23:0] product_phase0_2; // sfix24_En22 + wire signed [23:0] product_phase0_3; // sfix24_En22 + wire signed [23:0] product_phase1_1; // sfix24_En22 + wire signed [23:0] product_phase1_2; // sfix24_En22 + wire signed [23:0] product_phase1_3; // sfix24_En22 + reg signed [23:0] product_pipeline_phase0_1; // sfix24_En22 + reg signed [23:0] product_pipeline_phase0_2; // sfix24_En22 + reg signed [23:0] product_pipeline_phase0_3; // sfix24_En22 + reg signed [23:0] product_pipeline_phase1_1; // sfix24_En22 + reg signed [23:0] product_pipeline_phase1_2; // sfix24_En22 + reg signed [23:0] product_pipeline_phase1_3; // sfix24_En22 + wire signed [25:0] sumvector1 [0:2] ; // sfix26_En22 + wire signed [23:0] add_signext; // sfix24_En22 + wire signed [23:0] add_signext_1; // sfix24_En22 + wire signed [24:0] add_temp; // sfix25_En22 + wire signed [23:0] add_signext_2; // sfix24_En22 + wire signed [23:0] add_signext_3; // sfix24_En22 + wire signed [24:0] add_temp_1; // sfix25_En22 + wire signed [23:0] add_signext_4; // sfix24_En22 + wire signed [23:0] add_signext_5; // sfix24_En22 + wire signed [24:0] add_temp_2; // sfix25_En22 + reg signed [25:0] sumdelay_pipeline1 [0:2] ; // sfix26_En22 + wire signed [25:0] sumvector2 [0:1] ; // sfix26_En22 + wire signed [25:0] add_signext_6; // sfix26_En22 + wire signed [25:0] add_signext_7; // sfix26_En22 + wire signed [26:0] add_temp_3; // sfix27_En22 + reg signed [25:0] sumdelay_pipeline2 [0:1] ; // sfix26_En22 + wire signed [25:0] sum3; // sfix26_En22 + wire signed [25:0] add_signext_8; // sfix26_En22 + wire signed [25:0] add_signext_9; // sfix26_En22 + wire signed [26:0] add_temp_4; // sfix27_En22 + reg ce_delayline1; // boolean + reg ce_delayline2; // boolean + reg ce_delayline3; // boolean + reg ce_delayline4; // boolean + reg ce_delayline5; // boolean + reg ce_delayline6; // boolean + reg ce_delayline7; // boolean + reg ce_delayline8; // boolean + wire ce_gated; // boolean + reg signed [25:0] output_register; // sfix26_En22 + + // Block Statements + always @ (posedge clk or posedge reset) + begin: ce_output + if (reset == 1'b1) begin + ring_count <= 1; + end + else begin + if (clk_enable == 1'b1) begin + ring_count <= {ring_count[0], ring_count[1]}; + end + end + end // ce_output + + assign phase_0 = ring_count[0] && clk_enable; + + assign phase_1 = ring_count[1] && clk_enable; + + // ------------------ CE Output Register ------------------ + + always @ (posedge clk or posedge reset) + begin: ce_output_register + if (reset == 1'b1) begin + ce_out_reg <= 1'b0; + end + else begin + ce_out_reg <= phase_1; + end + end // ce_output_register + + always @ (posedge clk or posedge reset) + begin: input_reg_process + if (reset == 1'b1) begin + input_register <= 0; + end + else begin + if (clk_enable == 1'b1) begin + input_register <= filter_in; + end + end + end // input_reg_process + + always @( posedge clk or posedge reset) + begin: Delay_Pipeline_Phase0_process + if (reset == 1'b1) begin + input_pipeline_phase0[0] <= 0; + input_pipeline_phase0[1] <= 0; + end + else begin + if (phase_1 == 1'b1) begin + input_pipeline_phase0[0] <= input_register; + input_pipeline_phase0[1] <= input_pipeline_phase0[0]; + end + end + end // Delay_Pipeline_Phase0_process + + + always @( posedge clk or posedge reset) + begin: Delay_Pipeline_Phase1_process + if (reset == 1'b1) begin + input_pipeline_phase1[0] <= 0; + input_pipeline_phase1[1] <= 0; + input_pipeline_phase1[2] <= 0; + end + else begin + if (phase_0 == 1'b1) begin + input_pipeline_phase1[0] <= input_register; + input_pipeline_phase1[1] <= input_pipeline_phase1[0]; + input_pipeline_phase1[2] <= input_pipeline_phase1[1]; + end + end + end // Delay_Pipeline_Phase1_process + + + assign product_phase0_1 = input_register * coeffphase1_1; + + assign product_phase0_2 = input_pipeline_phase0[0] * coeffphase1_2; + + assign product_phase0_3 = input_pipeline_phase0[1] * coeffphase1_3; + + assign product_phase1_1 = input_pipeline_phase1[0] * coeffphase2_1; + + assign product_phase1_2 = input_pipeline_phase1[1] * coeffphase2_2; + + assign product_phase1_3 = input_pipeline_phase1[2] * coeffphase2_3; + + always @ (posedge clk or posedge reset) + begin: product_pipeline_process1 + if (reset == 1'b1) begin + product_pipeline_phase0_1 <= 0; + product_pipeline_phase1_1 <= 0; + product_pipeline_phase0_2 <= 0; + product_pipeline_phase1_2 <= 0; + product_pipeline_phase0_3 <= 0; + product_pipeline_phase1_3 <= 0; + end + else begin + if (phase_1 == 1'b1) begin + product_pipeline_phase0_1 <= product_phase0_1; + product_pipeline_phase1_1 <= product_phase1_1; + product_pipeline_phase0_2 <= product_phase0_2; + product_pipeline_phase1_2 <= product_phase1_2; + product_pipeline_phase0_3 <= product_phase0_3; + product_pipeline_phase1_3 <= product_phase1_3; + end + end + end // product_pipeline_process1 + + assign add_signext = product_pipeline_phase1_1; + assign add_signext_1 = product_pipeline_phase1_2; + assign add_temp = add_signext + add_signext_1; + assign sumvector1[0] = $signed({{1{add_temp[24]}}, add_temp}); + + assign add_signext_2 = product_pipeline_phase1_3; + assign add_signext_3 = product_pipeline_phase0_1; + assign add_temp_1 = add_signext_2 + add_signext_3; + assign sumvector1[1] = $signed({{1{add_temp_1[24]}}, add_temp_1}); + + assign add_signext_4 = product_pipeline_phase0_2; + assign add_signext_5 = product_pipeline_phase0_3; + assign add_temp_2 = add_signext_4 + add_signext_5; + assign sumvector1[2] = $signed({{1{add_temp_2[24]}}, add_temp_2}); + + always @ (posedge clk or posedge reset) + begin: sumdelay_pipeline_process1 + if (reset == 1'b1) begin + sumdelay_pipeline1[0] <= 0; + sumdelay_pipeline1[1] <= 0; + sumdelay_pipeline1[2] <= 0; + end + else begin + if (phase_1 == 1'b1) begin + sumdelay_pipeline1[0] <= sumvector1[0]; + sumdelay_pipeline1[1] <= sumvector1[1]; + sumdelay_pipeline1[2] <= sumvector1[2]; + end + end + end // sumdelay_pipeline_process1 + + assign add_signext_6 = sumdelay_pipeline1[0]; + assign add_signext_7 = sumdelay_pipeline1[1]; + assign add_temp_3 = add_signext_6 + add_signext_7; + assign sumvector2[0] = add_temp_3[25:0]; + + assign sumvector2[1] = sumdelay_pipeline1[2]; + + always @ (posedge clk or posedge reset) + begin: sumdelay_pipeline_process2 + if (reset == 1'b1) begin + sumdelay_pipeline2[0] <= 0; + sumdelay_pipeline2[1] <= 0; + end + else begin + if (phase_1 == 1'b1) begin + sumdelay_pipeline2[0] <= sumvector2[0]; + sumdelay_pipeline2[1] <= sumvector2[1]; + end + end + end // sumdelay_pipeline_process2 + + assign add_signext_8 = sumdelay_pipeline2[0]; + assign add_signext_9 = sumdelay_pipeline2[1]; + assign add_temp_4 = add_signext_8 + add_signext_9; + assign sum3 = add_temp_4[25:0]; + + always @ (posedge clk or posedge reset) + begin: ce_delay + if (reset == 1'b1) begin + ce_delayline1 <= 1'b0; + ce_delayline2 <= 1'b0; + ce_delayline3 <= 1'b0; + ce_delayline4 <= 1'b0; + ce_delayline5 <= 1'b0; + ce_delayline6 <= 1'b0; + ce_delayline7 <= 1'b0; + ce_delayline8 <= 1'b0; + end + else begin + if (clk_enable == 1'b1) begin + ce_delayline1 <= clk_enable; + ce_delayline2 <= ce_delayline1; + ce_delayline3 <= ce_delayline2; + ce_delayline4 <= ce_delayline3; + ce_delayline5 <= ce_delayline4; + ce_delayline6 <= ce_delayline5; + ce_delayline7 <= ce_delayline6; + ce_delayline8 <= ce_delayline7; + end + end + end // ce_delay + + assign ce_gated = ce_delayline8 & ce_out_reg; + + always @ (posedge clk or posedge reset) + begin: output_register_process + if (reset == 1'b1) begin + output_register <= 0; + end + else begin + if (phase_1 == 1'b1) begin + output_register <= sum3; + end + end + end // output_register_process + + // Assignment Statements + assign ce_out = ce_gated; + assign filter_out = output_register; +endmodule // fir_decim diff --git a/library/axi_adc_trigger/Makefile b/library/axi_adc_trigger/Makefile new file mode 100644 index 000000000..c2ab354f1 --- /dev/null +++ b/library/axi_adc_trigger/Makefile @@ -0,0 +1,50 @@ +#################################################################################### +#################################################################################### +## Copyright 2011(c) Analog Devices, Inc. +## Auto-generated, do not modify! +#################################################################################### +#################################################################################### + +M_DEPS += ../common/up_axi.v +M_DEPS += ../common/up_xfer_cntrl.v +M_DEPS += ../scripts/adi_env.tcl +M_DEPS += ../scripts/adi_ip.tcl +M_DEPS += axi_adc_trigger.v +M_DEPS += axi_adc_trigger_constr.xdc +M_DEPS += axi_adc_trigger_ip.tcl +M_DEPS += axi_adc_trigger_reg.v + +M_VIVADO := vivado -mode batch -source + +M_FLIST := *.cache +M_FLIST += *.data +M_FLIST += *.xpr +M_FLIST += *.log +M_FLIST += component.xml +M_FLIST += *.jou +M_FLIST += xgui +M_FLIST += *.ip_user_files +M_FLIST += *.srcs +M_FLIST += *.hw +M_FLIST += *.sim +M_FLIST += .Xil + + + +.PHONY: all clean clean-all +all: axi_adc_trigger.xpr + + +clean:clean-all + + +clean-all: + rm -rf $(M_FLIST) + + +axi_adc_trigger.xpr: $(M_DEPS) + -rm -rf $(M_FLIST) + $(M_VIVADO) axi_adc_trigger_ip.tcl >> axi_adc_trigger_ip.log 2>&1 + +#################################################################################### +#################################################################################### diff --git a/library/axi_adc_trigger/axi_adc_trigger.v b/library/axi_adc_trigger/axi_adc_trigger.v new file mode 100644 index 000000000..dde4990bc --- /dev/null +++ b/library/axi_adc_trigger/axi_adc_trigger.v @@ -0,0 +1,413 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_adc_trigger( + + input clk, + + input [ 1:0] trigger_i, + output [ 1:0] trigger_o, + output [ 1:0] trigger_t, + + input [15:0] data_a, + input [15:0] data_b, + input data_valid_a, + input data_valid_b, + + output [15:0] data_a_trig, + output [15:0] data_b_trig, + output data_valid_a_trig, + output data_valid_b_trig, + + output [31:0] trigger_offset, + + // axi interface + + input s_axi_aclk, + input s_axi_aresetn, + input s_axi_awvalid, + input [31:0] s_axi_awaddr, + input [ 2:0] s_axi_awprot, + output s_axi_awready, + input s_axi_wvalid, + input [31:0] s_axi_wdata, + input [ 3:0] s_axi_wstrb, + output s_axi_wready, + output s_axi_bvalid, + output [ 1:0] s_axi_bresp, + input s_axi_bready, + input s_axi_arvalid, + input [31:0] s_axi_araddr, + input [ 2:0] s_axi_arprot, + output s_axi_arready, + output s_axi_rvalid, + output [31:0] s_axi_rdata, + output [ 1:0] s_axi_rresp, + input s_axi_rready); + + // internal signals + + wire up_clk; + wire up_rstn; + wire [13:0] up_waddr; + wire [31:0] up_wdata; + wire up_wack; + wire up_wreq; + wire up_rack; + wire [31:0] up_rdata; + wire up_rreq; + wire [13:0] up_raddr; + + wire [ 1:0] io_selection; + + wire [ 1:0] low_level; + wire [ 1:0] high_level; + wire [ 1:0] any_edge; + wire [ 1:0] rise_edge; + wire [ 1:0] fall_edge; + + wire [15:0] limit_a; + wire [ 1:0] function_a; + wire [31:0] hysteresis_a; + wire [ 3:0] trigger_l_mix_a; + + wire [15:0] limit_b; + wire [ 1:0] function_b; + wire [31:0] hysteresis_b; + wire [ 3:0] trigger_l_mix_b; + + wire [ 2:0] trigger_out_mix; + wire [31:0] delay_trigger; + + wire [15:0] data_a_cmp; + wire [15:0] data_b_cmp; + wire [15:0] limit_a_cmp; + wire [15:0] limit_b_cmp; + + wire trigger_a_fall_edge; + wire trigger_a_rise_edge; + wire trigger_b_fall_edge; + wire trigger_b_rise_edge; + wire trigger_a_any_edge; + wire trigger_b_any_edge; + wire trigger_out_a; + wire trigger_out_b; + + reg trigger_a_d1; // synchronization flip flop + reg trigger_a_d2; // synchronization flip flop + reg trigger_a_d3; + reg trigger_b_d1; // synchronization flip flop + reg trigger_b_d2; // synchronization flip flop + reg trigger_b_d3; + reg passthrough_high_a; // trigger when rising through the limit + reg passthrough_low_a; // trigger when fallingh thorugh the limit + reg low_a; // signal was under the limit, so if it goes through, assert rising + reg high_a; // signal was over the limit, so if it passes through, assert falling + reg comp_high_a; // signal is over the limit + reg comp_low_a; // signal is under the limit + reg passthrough_high_b; // trigger when rising through the limit + reg passthrough_low_b; // trigger when fallingh thorugh the limit + reg low_b; // signal was under the limit, so if it goes through, assert rising + reg high_b; // signal was over the limit, so if it passes through, assert falling + reg comp_high_b; // signal is over the limit + reg comp_low_b; // signal is under the limit + + reg trigger_pin_a; + reg trigger_pin_b; + + reg trigger_adc_a; + reg trigger_adc_b; + + reg trigger_a; + reg trigger_b; + + reg trigger_out_mixed; + + reg [15:0] data_a_r; + reg [15:0] data_b_r; + reg data_valid_a_r; + reg data_valid_b_r; + + // signal name changes + + assign up_clk = s_axi_aclk; + assign up_rstn = s_axi_aresetn; + + assign trigger_offset = delay_trigger; + + assign trigger_t = io_selection; + + assign trigger_a_fall_edge = (trigger_a_d2 == 1'b0 && trigger_a_d3 == 1'b1) ? 1'b1: 1'b0; + assign trigger_a_rise_edge = (trigger_a_d2 == 1'b1 && trigger_a_d3 == 1'b0) ? 1'b1: 1'b0; + assign trigger_a_any_edge = trigger_a_rise_edge | trigger_a_fall_edge; + assign trigger_b_fall_edge = (trigger_b_d2 == 1'b0 && trigger_b_d3 == 1'b1) ? 1'b1: 1'b0; + assign trigger_b_rise_edge = (trigger_b_d2 == 1'b1 && trigger_b_d3 == 1'b0) ? 1'b1: 1'b0; + assign trigger_b_any_edge = trigger_b_rise_edge | trigger_b_fall_edge; + + assign data_a_cmp = {!data_a[15],data_a[14:0]}; + assign data_b_cmp = {!data_b[15],data_b[14:0]}; + assign limit_a_cmp = {!limit_a[15],limit_a[14:0]}; + assign limit_b_cmp = {!limit_b[15],limit_b[14:0]}; + + assign data_a_trig = {trigger_out_mixed, data_a_r[14:0]}; + assign data_b_trig = {trigger_out_mixed, data_b_r[14:0]};; + assign data_valid_a_trig = data_valid_a_r; + assign data_valid_b_trig = data_valid_b_r; + + always @(posedge clk) begin + data_a_r <= data_a; + data_valid_a_r <= data_valid_a; + data_b_r <= data_b; + data_valid_b_r <= data_valid_b; + end + + always @(*) begin + case(trigger_l_mix_a) + 4'h0: trigger_a = 1'b1; + 4'h1: trigger_a = trigger_pin_a; + 4'h2: trigger_a = trigger_adc_a; + 4'h4: trigger_a = trigger_pin_a | trigger_adc_a ; + 4'h5: trigger_a = trigger_pin_a & trigger_adc_a ; + 4'h6: trigger_a = trigger_pin_a ^ trigger_adc_a ; + 4'h7: trigger_a = !(trigger_pin_a | trigger_adc_a) ; + 4'h8: trigger_a = !(trigger_pin_a & trigger_adc_a) ; + 4'h9: trigger_a = !(trigger_pin_a ^ trigger_adc_a) ; + default: trigger_a = 1'b1; + endcase + end + + always @(*) begin + case(trigger_l_mix_b) + 4'h0: trigger_b = 1'b1; + 4'h1: trigger_b = trigger_pin_b; + 4'h2: trigger_b = trigger_adc_b; + 4'h4: trigger_b = trigger_pin_b | trigger_adc_b ; + 4'h5: trigger_b = trigger_pin_b & trigger_adc_b ; + 4'h6: trigger_b = trigger_pin_b ^ trigger_adc_b ; + 4'h7: trigger_b = !(trigger_pin_b | trigger_adc_b) ; + 4'h8: trigger_b = !(trigger_pin_b & trigger_adc_b) ; + 4'h9: trigger_b = !(trigger_pin_b ^ trigger_adc_b) ; + default: trigger_b = 1'b1; + endcase + end + + always @(*) begin + case(function_a) + 2'h0: trigger_adc_a = comp_low_a; + 2'h1: trigger_adc_a = comp_high_a; + 2'h2: trigger_adc_a = passthrough_high_a; + 2'h3: trigger_adc_a = passthrough_low_a; + default: trigger_adc_a = comp_low_a; + endcase + end + + always @(*) begin + case(function_b) + 2'h0: trigger_adc_b = comp_low_b; + 2'h1: trigger_adc_b = comp_high_b; + 2'h2: trigger_adc_b = passthrough_high_b; + 2'h3: trigger_adc_b = passthrough_low_b; + default: trigger_adc_b = comp_low_b; + endcase + end + + always @(posedge clk) begin + trigger_a_d1 <= trigger_i[0]; + trigger_a_d2 <= trigger_a_d1; + trigger_a_d3 <= trigger_a_d2; + trigger_b_d1 <= trigger_i[1]; + trigger_b_d2 <= trigger_b_d1; + trigger_b_d3 <= trigger_b_d2; + end + + always @(*) begin + trigger_pin_a = ((!trigger_a_d3 & low_level[0]) | + (trigger_a_d3 & high_level[0]) | + (trigger_a_fall_edge & fall_edge[0]) | + (trigger_a_rise_edge & rise_edge[0]) | + (trigger_a_any_edge & any_edge[0])); + end + + always @(*) begin + trigger_pin_b = ((!trigger_b_d3 & low_level[1]) | + (trigger_b_d3 & high_level[1]) | + (trigger_b_fall_edge & fall_edge[1]) | + (trigger_b_rise_edge & rise_edge[1]) | + (trigger_b_any_edge & any_edge[1])); + end + + always @(*) begin + case(trigger_out_mix) + 3'h0: trigger_out_mixed = trigger_a; + 3'h1: trigger_out_mixed = trigger_b; + 3'h2: trigger_out_mixed = trigger_a | trigger_b; + 3'h3: trigger_out_mixed = trigger_a & trigger_b; + 3'h4: trigger_out_mixed = trigger_a ^ trigger_b; + default: trigger_out_mixed = trigger_a; + endcase + end + + always @(posedge clk) begin + if (data_valid_a == 1'b1) begin + if (data_a_cmp > limit_a_cmp) begin + comp_high_a <= 1'b1; + passthrough_high_a <= low_a; + end else begin + comp_high_a <= 1'b0; + passthrough_high_a <= 1'b0; + end + if (data_a_cmp < limit_a_cmp) begin + comp_low_a <= 1'b1; + passthrough_low_a <= high_a; + end else begin + comp_low_a <= 1'b0; + passthrough_low_a <= 1'b0; + end + if (passthrough_high_a == 1'b1) begin + low_a <= 1'b0; + end else if (data_a_cmp < limit_a_cmp - hysteresis_a) begin + low_a <= 1'b1; + end + if (passthrough_low_a == 1'b1) begin + high_a <= 1'b0; + end else if (data_a_cmp > limit_a_cmp + hysteresis_a) begin + high_a <= 1'b1; + end + end + end + + always @(posedge clk) begin + if (data_valid_b == 1'b1) begin + if (data_b_cmp > limit_b_cmp) begin + comp_high_b <= 1'b1; + passthrough_high_b <= low_b; + end else begin + comp_high_b <= 1'b0; + passthrough_high_b <= 1'b0; + end + if (data_b_cmp < limit_b_cmp) begin + comp_low_b <= 1'b1; + passthrough_low_b <= high_b; + end else begin + comp_low_b <= 1'b0; + passthrough_low_b <= 1'b0; + end + if (trigger_b == 1'b1) begin + low_b <= 1'b0; + high_b <= 1'b0; + end else if (data_b_cmp < limit_b_cmp - hysteresis_b) begin + low_b <= 1'b1; + end else if (data_b_cmp > limit_b_cmp + hysteresis_b) begin + high_b <= 1'b1; + end + end + end + + axi_adc_trigger_reg adc_trigger_registers ( + + .clk(clk), + + .io_selection(io_selection), + .trigger_o(trigger_o), + + .low_level(low_level), + .high_level(high_level), + .any_edge(any_edge), + .rise_edge(rise_edge), + .fall_edge(fall_edge), + + .limit_a(limit_a), + .function_a(function_a), + .hysteresis_a(hysteresis_a), + .trigger_l_mix_a(trigger_l_mix_a), + + .limit_b(limit_b), + .function_b(function_b), + .hysteresis_b(hysteresis_b), + .trigger_l_mix_b(trigger_l_mix_b), + + .trigger_out_mix(trigger_out_mix), + .delay_trigger(delay_trigger), + + // bus interface + + .up_rstn(up_rstn), + .up_clk(up_clk), + .up_wreq(up_wreq), + .up_waddr(up_waddr), + .up_wdata(up_wdata), + .up_wack(up_wack), + .up_rreq(up_rreq), + .up_raddr(up_raddr), + .up_rdata(up_rdata), + .up_rack(up_rack)); + + up_axi i_up_axi ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_axi_awvalid (s_axi_awvalid), + .up_axi_awaddr (s_axi_awaddr), + .up_axi_awready (s_axi_awready), + .up_axi_wvalid (s_axi_wvalid), + .up_axi_wdata (s_axi_wdata), + .up_axi_wstrb (s_axi_wstrb), + .up_axi_wready (s_axi_wready), + .up_axi_bvalid (s_axi_bvalid), + .up_axi_bresp (s_axi_bresp), + .up_axi_bready (s_axi_bready), + .up_axi_arvalid (s_axi_arvalid), + .up_axi_araddr (s_axi_araddr), + .up_axi_arready (s_axi_arready), + .up_axi_rvalid (s_axi_rvalid), + .up_axi_rresp (s_axi_rresp), + .up_axi_rdata (s_axi_rdata), + .up_axi_rready (s_axi_rready), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata), + .up_rack (up_rack)); + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/library/axi_adc_trigger/axi_adc_trigger_constr.xdc b/library/axi_adc_trigger/axi_adc_trigger_constr.xdc new file mode 100644 index 000000000..d8c0c576e --- /dev/null +++ b/library/axi_adc_trigger/axi_adc_trigger_constr.xdc @@ -0,0 +1,12 @@ +set_property shreg_extract no [get_cells -hier -filter {name =~ *up_xfer_state*}] +set_property shreg_extract no [get_cells -hier -filter {name =~ *d_xfer_toggle*}] +set_property shreg_extract no [get_cells -hier -filter {name =~ *up_xfer_toggle*}] +set_property shreg_extract no [get_cells -hier -filter {name =~ *trigger_a_d*}] +set_property shreg_extract no [get_cells -hier -filter {name =~ *trigger_b_d*}] + +set_false_path -from [get_cells -hier -filter {name =~ *d_xfer_toggle_reg && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *up_xfer_state_m1_reg && IS_SEQUENTIAL}] +set_false_path -from [get_cells -hier -filter {name =~ *up_xfer_toggle_reg && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *d_xfer_toggle_m1_reg && IS_SEQUENTIAL}] +set_false_path -from [get_cells -hier -filter {name =~ *up_xfer_data* && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *d_data_cntrl* && IS_SEQUENTIAL}] +set_false_path -to [get_cells -hier -filter {name =~ *trigger_a_d1_reg* && IS_SEQUENTIAL}] +set_false_path -to [get_cells -hier -filter {name =~ *trigger_b_d1_reg* && IS_SEQUENTIAL}] + diff --git a/library/axi_adc_trigger/axi_adc_trigger_ip.tcl b/library/axi_adc_trigger/axi_adc_trigger_ip.tcl new file mode 100644 index 000000000..1cefb23be --- /dev/null +++ b/library/axi_adc_trigger/axi_adc_trigger_ip.tcl @@ -0,0 +1,22 @@ +# ip + +source ../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip.tcl + +adi_ip_create axi_adc_trigger +adi_ip_files axi_adc_trigger [list \ + "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ + "$ad_hdl_dir/library/common/up_axi.v" \ + "axi_adc_trigger_constr.xdc" \ + "axi_adc_trigger_reg.v" \ + "axi_adc_trigger.v" ] + +adi_ip_properties axi_adc_trigger +adi_ip_constraints axi_adc_trigger [list \ + "axi_adc_trigger_constr.xdc" ] + +ipx::remove_bus_interface {clk} [ipx::current_core] +ipx::associate_bus_interfaces -busif s_axi -clock s_axi_aclk [ipx::current_core] + +ipx::save_core [ipx::current_core] + diff --git a/library/axi_adc_trigger/axi_adc_trigger_reg.v b/library/axi_adc_trigger/axi_adc_trigger_reg.v new file mode 100644 index 000000000..62d530553 --- /dev/null +++ b/library/axi_adc_trigger/axi_adc_trigger_reg.v @@ -0,0 +1,241 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_adc_trigger_reg ( + + input clk, + + output reg [ 1:0] io_selection, + output reg [ 1:0] trigger_o, + + output [ 1:0] low_level, + output [ 1:0] high_level, + output [ 1:0] any_edge, + output [ 1:0] rise_edge, + output [ 1:0] fall_edge, + + output [15:0] limit_a, + output [ 1:0] function_a, + output [31:0] hysteresis_a, + output [ 3:0] trigger_l_mix_a, + + output [15:0] limit_b, + output [ 1:0] function_b, + output [31:0] hysteresis_b, + output [ 3:0] trigger_l_mix_b, + + output [ 2:0] trigger_out_mix, + output [31:0] delay_trigger, + + // bus interface + + input up_rstn, + input up_clk, + input up_wreq, + input [13:0] up_waddr, + input [31:0] up_wdata, + output reg up_wack, + input up_rreq, + input [13:0] up_raddr, + output reg [31:0] up_rdata, + output reg up_rack); + + // internal signals + + wire up_wreq_s; + wire up_rreq_s; + wire [ 9:0] config_trigger; + + // internal registers + + reg [31:0] up_version = 32'h00010000; + reg [31:0] up_scratch = 32'h0; + reg [ 9:0] up_config_trigger = 10'h0; + reg [15:0] up_limit_a = 16'h0; + reg [ 1:0] up_function_a = 2'h0; + reg [31:0] up_hysteresis_a = 32'h0; + reg [ 3:0] up_trigger_l_mix_a = 32'h0; + reg [15:0] up_limit_b = 16'h0; + reg [ 1:0] up_function_b = 2'h0; + reg [31:0] up_hysteresis_b = 32'h0; + reg [ 3:0] up_trigger_l_mix_b = 32'h0; + reg [ 2:0] up_trigger_out_mix = 32'h0; + reg [31:0] up_delay_trigger= 32'h0; + + assign up_wreq_s = ((up_waddr[13:5] == 6'h00)) ? up_wreq : 1'b0; + assign up_rreq_s = ((up_raddr[13:5] == 6'h00)) ? up_rreq : 1'b0; + + assign low_level = config_trigger[1:0]; + assign high_level = config_trigger[3:2]; + assign any_edge = config_trigger[5:4]; + assign rise_edge = config_trigger[7:6]; + assign fall_edge = config_trigger[9:8]; + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_wack <= 'd0; + up_scratch <= 'd0; + io_selection <= 'd3; + trigger_o <= 'd0; + up_config_trigger <= 'd0; + up_limit_a <= 'd0; + up_function_a <= 'd0; + up_hysteresis_a <= 'd0; + up_limit_b <= 'd0; + up_function_b <= 'd0; + up_hysteresis_b <= 'd0; + up_delay_trigger <= 'd0; + up_trigger_l_mix_a <= 'd0; + up_trigger_l_mix_b <= 'd0; + up_trigger_out_mix <= 'd0; + end else begin + up_wack <= up_wreq_s; + if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h1)) begin + up_scratch <= up_wdata; + end + if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h2)) begin + trigger_o <= up_wdata[1:0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h3)) begin + io_selection <= up_wdata[1:0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h4)) begin + up_config_trigger <= up_wdata[9:0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h5)) begin + up_limit_a <= up_wdata[15:0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h6)) begin + up_function_a <= up_wdata[1:0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h7)) begin + up_hysteresis_a <= up_wdata; + end + if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h8)) begin + up_trigger_l_mix_a <= up_wdata[3:0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h9)) begin + up_limit_b <= up_wdata[15:0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'ha)) begin + up_function_b <= up_wdata[1:0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'hb)) begin + up_hysteresis_b <= up_wdata; + end + if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'hc)) begin + up_trigger_l_mix_b <= up_wdata[3:0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'hd)) begin + up_trigger_out_mix <= up_wdata[2:0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'he)) begin + up_delay_trigger <= up_wdata; + end + end + end + + // processor read interface + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_rack <= 'd0; + up_rdata <= 'd0; + end else begin + up_rack <= up_rreq_s; + if (up_rreq_s == 1'b1) begin + case (up_raddr[4:0]) + 5'h0: up_rdata <= up_version; + 5'h1: up_rdata <= up_scratch; + 5'h2: up_rdata <= {30'h0,trigger_o}; + 5'h3: up_rdata <= {30'h0,io_selection}; + 5'h4: up_rdata <= {22'h0,up_config_trigger}; + 5'h5: up_rdata <= {16'h0,up_limit_a}; + 5'h6: up_rdata <= {30'h0,up_function_a}; + 5'h7: up_rdata <= up_hysteresis_a; + 5'h8: up_rdata <= {28'h0,up_trigger_l_mix_a}; + 5'h9: up_rdata <= {16'h0,up_limit_b}; + 5'ha: up_rdata <= {30'h0,up_function_b}; + 5'hb: up_rdata <= up_hysteresis_b; + 5'hc: up_rdata <= {28'h0,up_trigger_l_mix_b}; + 5'hd: up_rdata <= {29'h0,up_trigger_out_mix}; + 5'he: up_rdata <= up_delay_trigger; + default: up_rdata <= 0; + endcase + end else begin + up_rdata <= 32'd0; + end + end + end + + up_xfer_cntrl #(.DATA_WIDTH(153)) i_xfer_cntrl ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_data_cntrl ({ up_config_trigger, // 10 + up_limit_a, // 16 + up_function_a, // 2 + up_hysteresis_a, // 32 + up_trigger_l_mix_a, // 4 + up_limit_b, // 16 + up_function_b, // 2 + up_hysteresis_b, // 32 + up_trigger_l_mix_b, // 4 + up_trigger_out_mix, // 3 + up_delay_trigger}), // 32 + + .up_xfer_done (), + .d_rst (1'b0), + .d_clk (clk), + .d_data_cntrl ({ config_trigger, // 10 + limit_a, // 16 + function_a, // 2 + hysteresis_a, // 32 + trigger_l_mix_a, // 4 + limit_b, // 16 + function_b, // 2 + hysteresis_b, // 32 + trigger_l_mix_b, // 4 + trigger_out_mix, // 3 + delay_trigger})); // 32 + +endmodule + +// *************************************************************************** +// *************************************************************************** + diff --git a/library/axi_adcfifo/axi_adcfifo_ip.tcl b/library/axi_adcfifo/axi_adcfifo_ip.tcl deleted file mode 100644 index 3b3fecd9c..000000000 --- a/library/axi_adcfifo/axi_adcfifo_ip.tcl +++ /dev/null @@ -1,26 +0,0 @@ -# ip - -source ../scripts/adi_env.tcl -source $ad_hdl_dir/library/scripts/adi_ip.tcl - -adi_ip_create axi_adcfifo -adi_ip_files axi_adcfifo [list \ - "$ad_hdl_dir/library/common/ad_mem.v" \ - "$ad_hdl_dir/library/common/ad_mem_asym.v" \ - "$ad_hdl_dir/library/common/up_xfer_status.v" \ - "$ad_hdl_dir/library/common/ad_axis_inf_rx.v" \ - "axi_adcfifo_adc.v" \ - "axi_adcfifo_dma.v" \ - "axi_adcfifo_wr.v" \ - "axi_adcfifo_rd.v" \ - "axi_adcfifo.v" \ - "axi_adcfifo_constr.xdc" ] - -adi_ip_properties_lite axi_adcfifo -adi_ip_constraints axi_adcfifo [list \ - "axi_adcfifo_constr.xdc" ] - -ipx::infer_bus_interfaces {{xilinx.com:interface:aximm:1.0}} [ipx::current_core] - -ipx::save_core [ipx::current_core] - diff --git a/library/axi_clkgen/Makefile b/library/axi_clkgen/Makefile index 790233395..785af8fd6 100644 --- a/library/axi_clkgen/Makefile +++ b/library/axi_clkgen/Makefile @@ -5,15 +5,15 @@ #################################################################################### #################################################################################### -M_DEPS := axi_clkgen_ip.tcl -M_DEPS += ../scripts/adi_env.tcl -M_DEPS += ../scripts/adi_ip.tcl M_DEPS += ../common/ad_rst.v -M_DEPS += ../common/ad_mmcm_drp.v M_DEPS += ../common/up_axi.v M_DEPS += ../common/up_clkgen.v -M_DEPS += axi_clkgen_constr.xdc +M_DEPS += ../scripts/adi_env.tcl +M_DEPS += ../scripts/adi_ip.tcl +M_DEPS += ../xilinx/common/ad_mmcm_drp.v M_DEPS += axi_clkgen.v +M_DEPS += axi_clkgen_constr.xdc +M_DEPS += axi_clkgen_ip.tcl M_VIVADO := vivado -mode batch -source @@ -24,6 +24,10 @@ M_FLIST += *.log M_FLIST += component.xml M_FLIST += *.jou M_FLIST += xgui +M_FLIST += *.ip_user_files +M_FLIST += *.srcs +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil @@ -40,7 +44,7 @@ clean-all: axi_clkgen.xpr: $(M_DEPS) - rm -rf $(M_FLIST) + -rm -rf $(M_FLIST) $(M_VIVADO) axi_clkgen_ip.tcl >> axi_clkgen_ip.log 2>&1 #################################################################################### diff --git a/library/axi_clkgen/axi_clkgen.v b/library/axi_clkgen/axi_clkgen.v index eabe5564e..2a5586983 100644 --- a/library/axi_clkgen/axi_clkgen.v +++ b/library/axi_clkgen/axi_clkgen.v @@ -65,7 +65,9 @@ module axi_clkgen ( s_axi_rvalid, s_axi_rdata, s_axi_rresp, - s_axi_rready); + s_axi_rready, + s_axi_awprot, + s_axi_arprot); // parameters @@ -76,7 +78,11 @@ module axi_clkgen ( parameter VCO_DIV = 11; parameter VCO_MUL = 49; parameter CLK0_DIV = 6; + parameter CLK0_PHASE = 0.000; parameter CLK1_DIV = 6; + parameter CLK1_PHASE = 0.000; + parameter CLK2_DIV = 6; + parameter CLK2_PHASE = 0.000; // clocks @@ -106,6 +112,10 @@ module axi_clkgen ( output [31:0] s_axi_rdata; output [ 1:0] s_axi_rresp; input s_axi_rready; + input [ 2:0] s_axi_awprot; + input [ 2:0] s_axi_arprot; + + // reset and clocks @@ -200,14 +210,17 @@ module axi_clkgen ( .MMCM_VCO_DIV (VCO_DIV), .MMCM_VCO_MUL (VCO_MUL), .MMCM_CLK0_DIV (CLK0_DIV), - .MMCM_CLK1_DIV (CLK1_DIV)) + .MMCM_CLK0_PHASE (CLK0_PHASE), + .MMCM_CLK1_DIV (CLK1_DIV), + .MMCM_CLK1_PHASE (CLK1_PHASE)) i_mmcm_drp ( .clk (clk), .clk2 (clk2), - .mmcm_rst (mmcm_rst), .clk_sel(clk_sel), + .mmcm_rst (mmcm_rst), .mmcm_clk_0 (clk_0), .mmcm_clk_1 (clk_1), + .mmcm_clk_2 (), .up_clk (up_clk), .up_rstn (up_rstn), .up_drp_sel (up_drp_sel_s), diff --git a/library/axi_clkgen/axi_clkgen_ip.tcl b/library/axi_clkgen/axi_clkgen_ip.tcl index 0a472245e..4f041d954 100644 --- a/library/axi_clkgen/axi_clkgen_ip.tcl +++ b/library/axi_clkgen/axi_clkgen_ip.tcl @@ -6,7 +6,7 @@ source $ad_hdl_dir/library/scripts/adi_ip.tcl adi_ip_create axi_clkgen adi_ip_files axi_clkgen [list \ "$ad_hdl_dir/library/common/ad_rst.v" \ - "$ad_hdl_dir/library/common/ad_mmcm_drp.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_mmcm_drp.v" \ "$ad_hdl_dir/library/common/up_axi.v" \ "$ad_hdl_dir/library/common/up_clkgen.v" \ "axi_clkgen_constr.xdc" \ diff --git a/library/axi_dac_interpolate/Makefile b/library/axi_dac_interpolate/Makefile new file mode 100644 index 000000000..b080bf3f2 --- /dev/null +++ b/library/axi_dac_interpolate/Makefile @@ -0,0 +1,53 @@ +#################################################################################### +#################################################################################### +## Copyright 2011(c) Analog Devices, Inc. +## Auto-generated, do not modify! +#################################################################################### +#################################################################################### + +M_DEPS += ../common/ad_rst.v +M_DEPS += ../common/up_axi.v +M_DEPS += ../common/up_xfer_cntrl.v +M_DEPS += ../scripts/adi_env.tcl +M_DEPS += ../scripts/adi_ip.tcl +M_DEPS += axi_dac_interpolate.v +M_DEPS += axi_dac_interpolate_constr.xdc +M_DEPS += axi_dac_interpolate_ip.tcl +M_DEPS += axi_dac_interpolate_reg.v +M_DEPS += cic_interp.v +M_DEPS += fir_interp.v + +M_VIVADO := vivado -mode batch -source + +M_FLIST := *.cache +M_FLIST += *.data +M_FLIST += *.xpr +M_FLIST += *.log +M_FLIST += component.xml +M_FLIST += *.jou +M_FLIST += xgui +M_FLIST += *.ip_user_files +M_FLIST += *.srcs +M_FLIST += *.hw +M_FLIST += *.sim +M_FLIST += .Xil + + + +.PHONY: all clean clean-all +all: axi_dac_interpolate.xpr + + +clean:clean-all + + +clean-all: + rm -rf $(M_FLIST) + + +axi_dac_interpolate.xpr: $(M_DEPS) + -rm -rf $(M_FLIST) + $(M_VIVADO) axi_dac_interpolate_ip.tcl >> axi_dac_interpolate_ip.log 2>&1 + +#################################################################################### +#################################################################################### diff --git a/library/axi_dac_interpolate/axi_dac_interpolate.v b/library/axi_dac_interpolate/axi_dac_interpolate.v new file mode 100644 index 000000000..f6541ac4d --- /dev/null +++ b/library/axi_dac_interpolate/axi_dac_interpolate.v @@ -0,0 +1,323 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_dac_interpolate( + + input dac_clk, + + input [15:0] dac_data_a, + input [15:0] dac_data_b, + input dac_valid_a, + input dac_valid_b, + + output reg [15:0] dac_int_data_a, + output reg [15:0] dac_int_data_b, + output reg dac_int_valid_a, + output reg dac_int_valid_b, + + // axi interface + + input s_axi_aclk, + input s_axi_aresetn, + input s_axi_awvalid, + input [31:0] s_axi_awaddr, + input [ 2:0] s_axi_awprot, + output s_axi_awready, + input s_axi_wvalid, + input [31:0] s_axi_wdata, + input [ 3:0] s_axi_wstrb, + output s_axi_wready, + output s_axi_bvalid, + output [ 1:0] s_axi_bresp, + input s_axi_bready, + input s_axi_arvalid, + input [31:0] s_axi_araddr, + input [ 2:0] s_axi_arprot, + output s_axi_arready, + output s_axi_rvalid, + output [31:0] s_axi_rdata, + output [ 1:0] s_axi_rresp, + input s_axi_rready); + + // internal signals + + wire up_clk; + wire up_rstn; + wire [13:0] up_waddr; + wire [31:0] up_wdata; + wire up_wack; + wire up_wreq; + wire up_rack; + wire [31:0] up_rdata; + wire up_rreq; + wire [13:0] up_raddr; + + wire [31:0] interpolation_ratio_a; + wire [31:0] interpolation_ratio_b; + wire [31:0] filter_mask_a; + wire [31:0] filter_mask_b; + + wire dac_fir_valid_a; + wire [35:0] dac_fir_data_a; + wire dac_fir_valid_b; + wire [35:0] dac_fir_data_b; + + wire dac_cic_valid_a; + wire [109:0] dac_cic_data_a; + wire dac_cic_valid_b; + wire [109:0] dac_cic_data_b; + + wire dma_transfer_suspend; + + reg dac_filt_int_valid_a; + reg dac_filt_int_valid_b; + reg [15:0] interp_rate_cic_a; + reg [15:0] interp_rate_cic_b; + reg [31:0] filter_mask_a_d1; + reg [31:0] filter_mask_b_d1; + reg cic_change_rate_a; + reg cic_change_rate_b; + reg [31:0] interpolation_counter_a; + reg [31:0] interpolation_counter_b; + + // signal name changes + + assign up_clk = s_axi_aclk; + assign up_rstn = s_axi_aresetn; + + ad_rst i_core_rst_reg (.preset(~up_rstn), .clk(dac_clk), .rst(dac_rst)); + + fir_interp fir_interpolation_a ( + .clk (dac_clk), + .clk_enable (dac_cic_valid_a), + .reset (dac_rst | dma_transfer_suspend), + .filter_in (dac_data_a), + .filter_out (dac_fir_data_a), + .ce_out (dac_fir_valid_a)); + + fir_interp fir_interpolation_b ( + .clk (dac_clk), + .clk_enable (dac_cic_valid_b), + .reset (dac_rst | dma_transfer_suspend), + .filter_in (dac_data_b), + .filter_out (dac_fir_data_b), + .ce_out (dac_fir_valid_b)); + + cic_interp cic_interpolation_a ( + .clk (dac_clk), + .clk_enable (dac_valid_a), + .reset (dac_rst | cic_change_rate_a | dma_transfer_suspend), + .rate (interp_rate_cic_a), + .load_rate (1'b0), + .filter_in (dac_fir_data_a[30:0]), + .filter_out (dac_cic_data_a), + .ce_out (dac_cic_valid_a)); + + cic_interp cic_interpolation_b ( + .clk (dac_clk), + .clk_enable (dac_valid_b), + .reset (dac_rst | cic_change_rate_b | dma_transfer_suspend), + .rate (interp_rate_cic_b), + .load_rate (1'b0), + .filter_in (dac_fir_data_b[30:0]), + .filter_out (dac_cic_data_b), + .ce_out (dac_cic_valid_b)); + + always @(posedge dac_clk) begin + filter_mask_a_d1 <= filter_mask_a; + filter_mask_b_d1 <= filter_mask_b; + if (filter_mask_a_d1 != filter_mask_a) begin + cic_change_rate_a <= 1'b1; + end else begin + cic_change_rate_a <= 1'b0; + end + if (filter_mask_b_d1 != filter_mask_b) begin + cic_change_rate_b <= 1'b1; + end else begin + cic_change_rate_b <= 1'b0; + end + end + + always @(posedge dac_clk) begin + if (interpolation_ratio_a == 0 || interpolation_ratio_a == 1) begin + dac_int_valid_a <= dac_filt_int_valid_a; + end else begin + if (dac_filt_int_valid_a == 1'b1) begin + if (interpolation_counter_a < interpolation_ratio_a) begin + interpolation_counter_a <= interpolation_counter_a + 1; + dac_int_valid_a <= 1'b0; + end else begin + interpolation_counter_a <= 0; + dac_int_valid_a <= 1'b1; + end + end else begin + dac_int_valid_a <= 1'b0; + end + end + end + + always @(posedge dac_clk) begin + if (interpolation_ratio_b == 0 || interpolation_ratio_b == 1) begin + dac_int_valid_b <= dac_filt_int_valid_b; + end else begin + if (dac_filt_int_valid_b == 1'b1) begin + if (interpolation_counter_b < interpolation_ratio_b) begin + interpolation_counter_b <= interpolation_counter_b + 1; + dac_int_valid_b <= 1'b0; + end else begin + interpolation_counter_b <= 0; + dac_int_valid_b <= 1'b1; + end + end else begin + dac_int_valid_b <= 1'b0; + end + end + end + + always @(*) begin + case (filter_mask_a) + 16'h1: dac_int_data_a = dac_cic_data_a[31:16]; + 16'h2: dac_int_data_a = dac_cic_data_a[31:16]; + 16'h3: dac_int_data_a = dac_cic_data_a[31:16]; + 16'h6: dac_int_data_a = dac_cic_data_a[31:16]; + 16'h7: dac_int_data_a = dac_cic_data_a[31:16]; + default: dac_int_data_a = dac_data_a; + endcase + + case (filter_mask_a) + 16'h1: dac_filt_int_valid_a = dac_fir_valid_a; + 16'h2: dac_filt_int_valid_a = dac_fir_valid_a; + 16'h3: dac_filt_int_valid_a = dac_fir_valid_a; + 16'h6: dac_filt_int_valid_a = dac_fir_valid_a; + 16'h7: dac_filt_int_valid_a = dac_fir_valid_a; + default: dac_filt_int_valid_a = dac_valid_a & !dma_transfer_suspend; + endcase + + case (filter_mask_b) + 16'h1: dac_int_data_b = dac_cic_data_b[31:16]; + 16'h2: dac_int_data_b = dac_cic_data_b[31:16]; + 16'h3: dac_int_data_b = dac_cic_data_b[31:16]; + 16'h6: dac_int_data_b = dac_cic_data_b[31:16]; + 16'h7: dac_int_data_b = dac_cic_data_b[31:16]; + default: dac_int_data_b = dac_data_b; + endcase + + case (filter_mask_b) + 16'h1: dac_filt_int_valid_b = dac_fir_valid_b; + 16'h2: dac_filt_int_valid_b = dac_fir_valid_b; + 16'h3: dac_filt_int_valid_b = dac_fir_valid_b; + 16'h6: dac_filt_int_valid_b = dac_fir_valid_b; + 16'h7: dac_filt_int_valid_b = dac_fir_valid_b; + default: dac_filt_int_valid_b = dac_valid_b & !dma_transfer_suspend; + endcase + + case (filter_mask_a) + 16'h1: interp_rate_cic_a = 16'd5; + 16'h2: interp_rate_cic_a = 16'd50; + 16'h3: interp_rate_cic_a = 16'd500; + 16'h6: interp_rate_cic_a = 16'd5000; + 16'h7: interp_rate_cic_a = 16'd50000; + default: interp_rate_cic_a = 16'd1; + endcase + + case (filter_mask_b) + 16'h1: interp_rate_cic_b = 16'd5; + 16'h2: interp_rate_cic_b = 16'd50; + 16'h3: interp_rate_cic_b = 16'd500; + 16'h6: interp_rate_cic_b = 16'd5000; + 16'h7: interp_rate_cic_b = 16'd50000; + default: interp_rate_cic_b = 16'd1; + endcase + end + + axi_dac_interpolate_reg axi_dac_interpolate_reg_inst ( + + .clk (dac_clk), + + .dac_interpolation_ratio_a (interpolation_ratio_a), + .dac_filter_mask_a (filter_mask_a), + .dac_interpolation_ratio_b (interpolation_ratio_b), + .dac_filter_mask_b (filter_mask_b), + + .dma_transfer_suspend (dma_transfer_suspend), + + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata), + .up_rack (up_rack)); + + up_axi i_up_axi ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_axi_awvalid (s_axi_awvalid), + .up_axi_awaddr (s_axi_awaddr), + .up_axi_awready (s_axi_awready), + .up_axi_wvalid (s_axi_wvalid), + .up_axi_wdata (s_axi_wdata), + .up_axi_wstrb (s_axi_wstrb), + .up_axi_wready (s_axi_wready), + .up_axi_bvalid (s_axi_bvalid), + .up_axi_bresp (s_axi_bresp), + .up_axi_bready (s_axi_bready), + .up_axi_arvalid (s_axi_arvalid), + .up_axi_araddr (s_axi_araddr), + .up_axi_arready (s_axi_arready), + .up_axi_rvalid (s_axi_rvalid), + .up_axi_rresp (s_axi_rresp), + .up_axi_rdata (s_axi_rdata), + .up_axi_rready (s_axi_rready), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata), + .up_rack (up_rack)); + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/library/axi_dac_interpolate/axi_dac_interpolate_constr.xdc b/library/axi_dac_interpolate/axi_dac_interpolate_constr.xdc new file mode 100644 index 000000000..52097cb82 --- /dev/null +++ b/library/axi_dac_interpolate/axi_dac_interpolate_constr.xdc @@ -0,0 +1,11 @@ + +set_property shreg_extract no [get_cells -hier -filter {name =~ *up_xfer_state*}] +set_property shreg_extract no [get_cells -hier -filter {name =~ *d_xfer_toggle*}] +set_property shreg_extract no [get_cells -hier -filter {name =~ *up_xfer_toggle*}] +set_property shreg_extract no [get_cells -hier -filter {name =~ *ad_rst_sync*}] + +set_false_path -from [get_cells -hier -filter {name =~ *d_xfer_toggle_reg && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *up_xfer_state_m1_reg && IS_SEQUENTIAL}] +set_false_path -from [get_cells -hier -filter {name =~ *up_xfer_toggle_reg && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *d_xfer_toggle_m1_reg && IS_SEQUENTIAL}] +set_false_path -from [get_cells -hier -filter {name =~ *up_xfer_data* && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *d_data_cntrl* && IS_SEQUENTIAL}] +set_false_path -to [get_cells -hier -filter {name =~ *ad_rst_sync_m1_reg && IS_SEQUENTIAL}] + diff --git a/library/axi_dac_interpolate/axi_dac_interpolate_ip.tcl b/library/axi_dac_interpolate/axi_dac_interpolate_ip.tcl new file mode 100644 index 000000000..effd1ce25 --- /dev/null +++ b/library/axi_dac_interpolate/axi_dac_interpolate_ip.tcl @@ -0,0 +1,25 @@ +# ip + +source ../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip.tcl + +adi_ip_create axi_dac_interpolate +adi_ip_files axi_dac_interpolate [list \ + "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ + "$ad_hdl_dir/library/common/ad_rst.v" \ + "$ad_hdl_dir/library/common/up_axi.v" \ + "axi_dac_interpolate_constr.xdc" \ + "cic_interp.v" \ + "fir_interp.v" \ + "axi_dac_interpolate_reg.v" \ + "axi_dac_interpolate.v" ] + +adi_ip_properties axi_dac_interpolate +adi_ip_constraints axi_dac_interpolate [list \ + "axi_dac_interpolate_constr.xdc" ] + +ipx::remove_bus_interface {clk} [ipx::current_core] +ipx::associate_bus_interfaces -busif s_axi -clock s_axi_aclk [ipx::current_core] + +ipx::save_core [ipx::current_core] + diff --git a/library/axi_dac_interpolate/axi_dac_interpolate_reg.v b/library/axi_dac_interpolate/axi_dac_interpolate_reg.v new file mode 100644 index 000000000..ad33beb63 --- /dev/null +++ b/library/axi_dac_interpolate/axi_dac_interpolate_reg.v @@ -0,0 +1,161 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_dac_interpolate_reg( + + input clk, + + output [31:0] dac_interpolation_ratio_a, + output [31:0] dac_filter_mask_a, + output [31:0] dac_interpolation_ratio_b, + output [31:0] dac_filter_mask_b, + output dma_transfer_suspend, + + // bus interface + + input up_rstn, + input up_clk, + input up_wreq, + input [13:0] up_waddr, + input [31:0] up_wdata, + output reg up_wack, + input up_rreq, + input [13:0] up_raddr, + output reg [31:0] up_rdata, + output reg up_rack); + + // internal signals + + wire up_wreq_s; + wire up_rreq_s; + + // internal registers + + reg [31:0] up_version = 32'h00020000; + reg [31:0] up_scratch = 32'h0; + + reg [31:0] up_interpolation_ratio_a = 32'h0; + reg [31:0] up_filter_mask_a = 32'h0; + reg [31:0] up_interpolation_ratio_b = 32'h0; + reg [31:0] up_filter_mask_b = 32'h0; + reg [31:0] up_flags = 32'h0; + + assign up_wreq_s = ((up_waddr[13:5] == 6'h00)) ? up_wreq : 1'b0; + assign up_rreq_s = ((up_raddr[13:5] == 6'h00)) ? up_rreq : 1'b0; + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_wack <= 'd0; + up_scratch <= 'd0; + up_interpolation_ratio_a <= 'd0; + up_filter_mask_a <= 'd0; + up_interpolation_ratio_b <= 'd0; + up_filter_mask_b <= 'd0; + up_flags <= 'd0; + end else begin + up_wack <= up_wreq_s; + if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h1)) begin + up_scratch <= up_wdata; + end + if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h10)) begin + up_interpolation_ratio_a <= up_wdata; + end + if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h11)) begin + up_filter_mask_a <= up_wdata; + end + if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h12)) begin + up_interpolation_ratio_b <= up_wdata; + end + if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h13)) begin + up_filter_mask_b <= up_wdata; + end + if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h14)) begin + up_flags <= up_wdata; + end + end + end + + // processor read interface + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_rack <= 'd0; + up_rdata <= 'd0; + end else begin + up_rack <= up_rreq_s; + if (up_rreq_s == 1'b1) begin + case (up_raddr[4:0]) + 5'h0: up_rdata <= up_version; + 5'h1: up_rdata <= up_scratch; + 5'h10: up_rdata <= up_interpolation_ratio_a; + 5'h11: up_rdata <= up_filter_mask_a; + 5'h12: up_rdata <= up_interpolation_ratio_b; + 5'h13: up_rdata <= up_filter_mask_b; + 5'h14: up_rdata <= up_flags; + default: up_rdata <= 0; + endcase + end else begin + up_rdata <= 32'd0; + end + end + end + + up_xfer_cntrl #(.DATA_WIDTH(129)) i_xfer_cntrl ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_data_cntrl ({ up_flags[0], // 1 + up_interpolation_ratio_b, // 32 + up_interpolation_ratio_a, // 32 + up_filter_mask_b, // 32 + up_filter_mask_a}), // 32 + + .up_xfer_done (), + .d_rst (1'b0), + .d_clk (clk), + .d_data_cntrl ({ dma_transfer_suspend, // 1 + dac_interpolation_ratio_b, // 32 + dac_interpolation_ratio_a, // 32 + dac_filter_mask_b, // 32 + dac_filter_mask_a})); // 32 + +endmodule + +// *************************************************************************** +// *************************************************************************** + diff --git a/library/axi_dac_interpolate/cic_interp.v b/library/axi_dac_interpolate/cic_interp.v new file mode 100644 index 000000000..5b0d3e493 --- /dev/null +++ b/library/axi_dac_interpolate/cic_interp.v @@ -0,0 +1,614 @@ +// ------------------------------------------------------------- +// +// Module: cic_interp +// Generated by MATLAB(R) 9.0 and the Filter Design HDL Coder 3.0. +// Generated on: 2016-07-05 11:08:04 +// ------------------------------------------------------------- + +// ------------------------------------------------------------- +// HDL Code Generation Options: +// +// OptimizeForHDL: on +// EDAScriptGeneration: off +// AddPipelineRegisters: on +// Name: cic_interp +// AddRatePort: on +// InputDataType: numerictype(1,31,30) +// TargetLanguage: Verilog +// TestBenchName: cicinterpfilt_copy_tb +// TestBenchStimulus: step ramp chirp noise +// GenerateHDLTestBench: off + +// ------------------------------------------------------------- +// HDL Implementation : Fully parallel +// ------------------------------------------------------------- +// Filter Settings: +// +// Discrete-Time FIR Multirate Filter (real) +// ----------------------------------------- +// Filter Structure : Cascaded Integrator-Comb Interpolator +// Interpolation Factor : 50000 +// Differential Delay : 1 +// Number of Sections : 6 +// Stable : Yes +// Linear Phase : No +// +// ------------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module cic_interp + ( + clk, + clk_enable, + reset, + filter_in, + rate, + load_rate, + filter_out, + ce_out + ); + + input clk; + input clk_enable; + input reset; + input signed [30:0] filter_in; //sfix31_En30 + input [15:0] rate; //ufix16 + input load_rate; + output signed [109:0] filter_out; //sfix110_En30 + output ce_out; + +//////////////////////////////////////////////////////////////// +//Module Architecture: cic_interp +//////////////////////////////////////////////////////////////// + // Local Functions + // Type Definitions + // Constants + parameter signed [35:0] zeroconst = 36'h000000000; //sfix36_En30 + // Signals + wire [15:0] rate_unsigned; // ufix16 + reg [15:0] cur_count = 0; // ufix16 + wire phase_0; // boolean + // + reg signed [30:0] input_register = 0; // sfix31_En30 + // -- Section 1 Signals + wire signed [30:0] section_in1; // sfix31_En30 + wire signed [31:0] section_cast1; // sfix32_En30 + reg signed [31:0] diff1 = 0; // sfix32_En30 + wire signed [31:0] section_out1; // sfix32_En30 + wire signed [31:0] sub_cast; // sfix32_En30 + wire signed [31:0] sub_cast_1; // sfix32_En30 + wire signed [32:0] sub_temp; // sfix33_En30 + reg signed [31:0] cic_pipeline1 = 0; // sfix32_En30 + // -- Section 2 Signals + wire signed [31:0] section_in2; // sfix32_En30 + wire signed [32:0] section_cast2; // sfix33_En30 + reg signed [32:0] diff2 = 0; // sfix33_En30 + wire signed [32:0] section_out2; // sfix33_En30 + wire signed [32:0] sub_cast_2; // sfix33_En30 + wire signed [32:0] sub_cast_3; // sfix33_En30 + wire signed [33:0] sub_temp_1; // sfix34_En30 + reg signed [32:0] cic_pipeline2 = 0; // sfix33_En30 + // -- Section 3 Signals + wire signed [32:0] section_in3; // sfix33_En30 + wire signed [33:0] section_cast3; // sfix34_En30 + reg signed [33:0] diff3 = 0; // sfix34_En30 + wire signed [33:0] section_out3; // sfix34_En30 + wire signed [33:0] sub_cast_4; // sfix34_En30 + wire signed [33:0] sub_cast_5; // sfix34_En30 + wire signed [34:0] sub_temp_2; // sfix35_En30 + reg signed [33:0] cic_pipeline3 = 0; // sfix34_En30 + // -- Section 4 Signals + wire signed [33:0] section_in4; // sfix34_En30 + wire signed [34:0] section_cast4; // sfix35_En30 + reg signed [34:0] diff4 = 0; // sfix35_En30 + wire signed [34:0] section_out4; // sfix35_En30 + wire signed [34:0] sub_cast_6; // sfix35_En30 + wire signed [34:0] sub_cast_7; // sfix35_En30 + wire signed [35:0] sub_temp_3; // sfix36_En30 + reg signed [34:0] cic_pipeline4 = 0; // sfix35_En30 + // -- Section 5 Signals + wire signed [34:0] section_in5; // sfix35_En30 + wire signed [35:0] section_cast5; // sfix36_En30 + reg signed [35:0] diff5 = 0; // sfix36_En30 + wire signed [35:0] section_out5; // sfix36_En30 + wire signed [35:0] sub_cast_8; // sfix36_En30 + wire signed [35:0] sub_cast_9; // sfix36_En30 + wire signed [36:0] sub_temp_4; // sfix37_En30 + reg signed [35:0] cic_pipeline5 = 0; // sfix36_En30 + // -- Section 6 Signals + wire signed [35:0] section_in6; // sfix36_En30 + reg signed [35:0] diff6 = 0; // sfix36_En30 + wire signed [35:0] section_out6; // sfix36_En30 + wire signed [35:0] sub_cast_10; // sfix36_En30 + wire signed [35:0] sub_cast_11; // sfix36_En30 + wire signed [36:0] sub_temp_5; // sfix37_En30 + reg signed [35:0] cic_pipeline6 = 0; // sfix36_En30 + wire signed [35:0] upsampling; // sfix36_En30 + // -- Section 7 Signals + wire signed [35:0] section_in7; // sfix36_En30 + wire signed [35:0] sum1; // sfix36_En30 + reg signed [35:0] section_out7 = 0; // sfix36_En30 + wire signed [35:0] add_cast; // sfix36_En30 + wire signed [35:0] add_cast_1; // sfix36_En30 + wire signed [36:0] add_temp; // sfix37_En30 + // -- Section 8 Signals + wire signed [35:0] section_in8; // sfix36_En30 + wire signed [50:0] section_cast8; // sfix51_En30 + wire signed [50:0] sum2; // sfix51_En30 + reg signed [50:0] section_out8 = 0; // sfix51_En30 + wire signed [50:0] add_cast_2; // sfix51_En30 + wire signed [50:0] add_cast_3; // sfix51_En30 + wire signed [51:0] add_temp_1; // sfix52_En30 + // -- Section 9 Signals + wire signed [50:0] section_in9; // sfix51_En30 + wire signed [65:0] section_cast9; // sfix66_En30 + wire signed [65:0] sum3; // sfix66_En30 + reg signed [65:0] section_out9 = 0; // sfix66_En30 + wire signed [65:0] add_cast_4; // sfix66_En30 + wire signed [65:0] add_cast_5; // sfix66_En30 + wire signed [66:0] add_temp_2; // sfix67_En30 + // -- Section 10 Signals + wire signed [65:0] section_in10; // sfix66_En30 + wire signed [79:0] section_cast10; // sfix80_En30 + wire signed [79:0] sum4; // sfix80_En30 + reg signed [79:0] section_out10 = 0; // sfix80_En30 + wire signed [79:0] add_cast_6; // sfix80_En30 + wire signed [79:0] add_cast_7; // sfix80_En30 + wire signed [80:0] add_temp_3; // sfix81_En30 + // -- Section 11 Signals + wire signed [79:0] section_in11; // sfix80_En30 + wire signed [94:0] section_cast11; // sfix95_En30 + wire signed [94:0] sum5; // sfix95_En30 + reg signed [94:0] section_out11 = 0; // sfix95_En30 + wire signed [94:0] add_cast_8; // sfix95_En30 + wire signed [94:0] add_cast_9; // sfix95_En30 + wire signed [95:0] add_temp_4; // sfix96_En30 + // -- Section 12 Signals + wire signed [94:0] section_in12; // sfix95_En30 + wire signed [109:0] section_cast12; // sfix110_En30 + wire signed [109:0] sum6; // sfix110_En30 + reg signed [109:0] section_out12 = 0; // sfix110_En30 + wire signed [109:0] add_cast_10; // sfix110_En30 + wire signed [109:0] add_cast_11; // sfix110_En30 + wire signed [110:0] add_temp_5; // sfix111_En30 + reg [6:0] bitgain = 0; // ufix7 + wire signed [109:0] output_typeconvert; // sfix110_En30 + wire signed [109:0] muxinput_14; // sfix110_En16 + wire signed [109:0] muxinput_34; // sfix110_E4 + wire signed [109:0] muxinput_54; // sfix110_E24 + wire signed [109:0] muxinput_74; // sfix110_E44 + wire signed [109:0] muxinput_94; // sfix110_E64 + // + reg signed [109:0] output_register = 0; // sfix110_En30 + + // Block Statements + assign rate_unsigned = rate; + + always @ (posedge clk or posedge reset) + begin: ce_output + if (reset == 1'b1) begin + cur_count <= 16'b0000000000000000; + end + else begin + if (clk_enable == 1'b1) begin + if (load_rate == 1'b1) begin + cur_count <= 16'b0000000000000001; + end + else if (cur_count == rate_unsigned - 1) begin + cur_count <= 16'b0000000000000000; + end + else begin + cur_count <= cur_count + 1; + end + end + end + end // ce_output + + assign phase_0 = (cur_count == 16'b0000000000000000 && clk_enable == 1'b1)? 1 : 0; + + // ------------------ Input Register ------------------ + + always @ (posedge clk or posedge reset) + begin: input_reg_process + if (reset == 1'b1) begin + input_register <= 0; + end + else begin + if (phase_0 == 1'b1) begin + input_register <= filter_in; + end + end + end // input_reg_process + + // ------------------ Section # 1 : Comb ------------------ + + assign section_in1 = input_register; + + assign section_cast1 = $signed({{1{section_in1[30]}}, section_in1}); + + assign sub_cast = section_cast1; + assign sub_cast_1 = diff1; + assign sub_temp = sub_cast - sub_cast_1; + assign section_out1 = sub_temp[31:0]; + + always @ (posedge clk or posedge reset) + begin: comb_delay_section1 + if (reset == 1'b1) begin + diff1 <= 0; + end + else begin + if (phase_0 == 1'b1) begin + diff1 <= section_cast1; + end + end + end // comb_delay_section1 + + always @ (posedge clk or posedge reset) + begin: cic_pipeline_process_section1 + if (reset == 1'b1) begin + cic_pipeline1 <= 0; + end + else begin + if (phase_0 == 1'b1) begin + cic_pipeline1 <= section_out1; + end + end + end // cic_pipeline_process_section1 + + // ------------------ Section # 2 : Comb ------------------ + + assign section_in2 = cic_pipeline1; + + assign section_cast2 = $signed({{1{section_in2[31]}}, section_in2}); + + assign sub_cast_2 = section_cast2; + assign sub_cast_3 = diff2; + assign sub_temp_1 = sub_cast_2 - sub_cast_3; + assign section_out2 = sub_temp_1[32:0]; + + always @ (posedge clk or posedge reset) + begin: comb_delay_section2 + if (reset == 1'b1) begin + diff2 <= 0; + end + else begin + if (phase_0 == 1'b1) begin + diff2 <= section_cast2; + end + end + end // comb_delay_section2 + + always @ (posedge clk or posedge reset) + begin: cic_pipeline_process_section2 + if (reset == 1'b1) begin + cic_pipeline2 <= 0; + end + else begin + if (phase_0 == 1'b1) begin + cic_pipeline2 <= section_out2; + end + end + end // cic_pipeline_process_section2 + + // ------------------ Section # 3 : Comb ------------------ + + assign section_in3 = cic_pipeline2; + + assign section_cast3 = $signed({{1{section_in3[32]}}, section_in3}); + + assign sub_cast_4 = section_cast3; + assign sub_cast_5 = diff3; + assign sub_temp_2 = sub_cast_4 - sub_cast_5; + assign section_out3 = sub_temp_2[33:0]; + + always @ (posedge clk or posedge reset) + begin: comb_delay_section3 + if (reset == 1'b1) begin + diff3 <= 0; + end + else begin + if (phase_0 == 1'b1) begin + diff3 <= section_cast3; + end + end + end // comb_delay_section3 + + always @ (posedge clk or posedge reset) + begin: cic_pipeline_process_section3 + if (reset == 1'b1) begin + cic_pipeline3 <= 0; + end + else begin + if (phase_0 == 1'b1) begin + cic_pipeline3 <= section_out3; + end + end + end // cic_pipeline_process_section3 + + // ------------------ Section # 4 : Comb ------------------ + + assign section_in4 = cic_pipeline3; + + assign section_cast4 = $signed({{1{section_in4[33]}}, section_in4}); + + assign sub_cast_6 = section_cast4; + assign sub_cast_7 = diff4; + assign sub_temp_3 = sub_cast_6 - sub_cast_7; + assign section_out4 = sub_temp_3[34:0]; + + always @ (posedge clk or posedge reset) + begin: comb_delay_section4 + if (reset == 1'b1) begin + diff4 <= 0; + end + else begin + if (phase_0 == 1'b1) begin + diff4 <= section_cast4; + end + end + end // comb_delay_section4 + + always @ (posedge clk or posedge reset) + begin: cic_pipeline_process_section4 + if (reset == 1'b1) begin + cic_pipeline4 <= 0; + end + else begin + if (phase_0 == 1'b1) begin + cic_pipeline4 <= section_out4; + end + end + end // cic_pipeline_process_section4 + + // ------------------ Section # 5 : Comb ------------------ + + assign section_in5 = cic_pipeline4; + + assign section_cast5 = $signed({{1{section_in5[34]}}, section_in5}); + + assign sub_cast_8 = section_cast5; + assign sub_cast_9 = diff5; + assign sub_temp_4 = sub_cast_8 - sub_cast_9; + assign section_out5 = sub_temp_4[35:0]; + + always @ (posedge clk or posedge reset) + begin: comb_delay_section5 + if (reset == 1'b1) begin + diff5 <= 0; + end + else begin + if (phase_0 == 1'b1) begin + diff5 <= section_cast5; + end + end + end // comb_delay_section5 + + always @ (posedge clk or posedge reset) + begin: cic_pipeline_process_section5 + if (reset == 1'b1) begin + cic_pipeline5 <= 0; + end + else begin + if (phase_0 == 1'b1) begin + cic_pipeline5 <= section_out5; + end + end + end // cic_pipeline_process_section5 + + // ------------------ Section # 6 : Comb ------------------ + + assign section_in6 = cic_pipeline5; + + assign sub_cast_10 = section_in6; + assign sub_cast_11 = diff6; + assign sub_temp_5 = sub_cast_10 - sub_cast_11; + assign section_out6 = sub_temp_5[35:0]; + + always @ (posedge clk or posedge reset) + begin: comb_delay_section6 + if (reset == 1'b1) begin + diff6 <= 0; + end + else begin + if (phase_0 == 1'b1) begin + diff6 <= section_in6; + end + end + end // comb_delay_section6 + + always @ (posedge clk or posedge reset) + begin: cic_pipeline_process_section6 + if (reset == 1'b1) begin + cic_pipeline6 <= 0; + end + else begin + if (phase_0 == 1'b1) begin + cic_pipeline6 <= section_out6; + end + end + end // cic_pipeline_process_section6 + + assign upsampling = (phase_0 == 1'b1) ? cic_pipeline6 : + zeroconst; + // ------------------ Section # 7 : Integrator ------------------ + + assign section_in7 = upsampling; + + assign add_cast = section_in7; + assign add_cast_1 = section_out7; + assign add_temp = add_cast + add_cast_1; + assign sum1 = add_temp[35:0]; + + always @ (posedge clk or posedge reset) + begin: integrator_delay_section7 + if (reset == 1'b1) begin + section_out7 <= 0; + end + else begin + if (clk_enable == 1'b1) begin + section_out7 <= sum1; + end + end + end // integrator_delay_section7 + + // ------------------ Section # 8 : Integrator ------------------ + + assign section_in8 = section_out7; + + assign section_cast8 = $signed({{15{section_in8[35]}}, section_in8}); + + assign add_cast_2 = section_cast8; + assign add_cast_3 = section_out8; + assign add_temp_1 = add_cast_2 + add_cast_3; + assign sum2 = add_temp_1[50:0]; + + always @ (posedge clk or posedge reset) + begin: integrator_delay_section8 + if (reset == 1'b1) begin + section_out8 <= 0; + end + else begin + if (clk_enable == 1'b1) begin + section_out8 <= sum2; + end + end + end // integrator_delay_section8 + + // ------------------ Section # 9 : Integrator ------------------ + + assign section_in9 = section_out8; + + assign section_cast9 = $signed({{15{section_in9[50]}}, section_in9}); + + assign add_cast_4 = section_cast9; + assign add_cast_5 = section_out9; + assign add_temp_2 = add_cast_4 + add_cast_5; + assign sum3 = add_temp_2[65:0]; + + always @ (posedge clk or posedge reset) + begin: integrator_delay_section9 + if (reset == 1'b1) begin + section_out9 <= 0; + end + else begin + if (clk_enable == 1'b1) begin + section_out9 <= sum3; + end + end + end // integrator_delay_section9 + + // ------------------ Section # 10 : Integrator ------------------ + + assign section_in10 = section_out9; + + assign section_cast10 = $signed({{14{section_in10[65]}}, section_in10}); + + assign add_cast_6 = section_cast10; + assign add_cast_7 = section_out10; + assign add_temp_3 = add_cast_6 + add_cast_7; + assign sum4 = add_temp_3[79:0]; + + always @ (posedge clk or posedge reset) + begin: integrator_delay_section10 + if (reset == 1'b1) begin + section_out10 <= 0; + end + else begin + if (clk_enable == 1'b1) begin + section_out10 <= sum4; + end + end + end // integrator_delay_section10 + + // ------------------ Section # 11 : Integrator ------------------ + + assign section_in11 = section_out10; + + assign section_cast11 = $signed({{15{section_in11[79]}}, section_in11}); + + assign add_cast_8 = section_cast11; + assign add_cast_9 = section_out11; + assign add_temp_4 = add_cast_8 + add_cast_9; + assign sum5 = add_temp_4[94:0]; + + always @ (posedge clk or posedge reset) + begin: integrator_delay_section11 + if (reset == 1'b1) begin + section_out11 <= 0; + end + else begin + if (clk_enable == 1'b1) begin + section_out11 <= sum5; + end + end + end // integrator_delay_section11 + + // ------------------ Section # 12 : Integrator ------------------ + + assign section_in12 = section_out11; + + assign section_cast12 = $signed({{15{section_in12[94]}}, section_in12}); + + assign add_cast_10 = section_cast12; + assign add_cast_11 = section_out12; + assign add_temp_5 = add_cast_10 + add_cast_11; + assign sum6 = add_temp_5[109:0]; + + always @ (posedge clk or posedge reset) + begin: integrator_delay_section12 + if (reset == 1'b1) begin + section_out12 <= 0; + end + else begin + if (clk_enable == 1'b1) begin + section_out12 <= sum6; + end + end + end // integrator_delay_section12 + + always @(rate_unsigned) + begin + case(rate_unsigned) + 16'b0000000000000101 : bitgain = 7'b0001110; + 16'b0000000000110010 : bitgain = 7'b0100010; + 16'b0000000111110100 : bitgain = 7'b0110110; + 16'b0001001110001000 : bitgain = 7'b1001010; + 16'b1100001101010000 : bitgain = 7'b1011110; + default : bitgain = 7'b1011110; + endcase + end + + assign muxinput_14 = $signed({{10{section_out12[109]}}, section_out12[109:10]}); + + assign muxinput_34 = $signed({{27{section_out12[109]}}, section_out12[109:27]}); + + assign muxinput_54 = $signed({{43{section_out12[109]}}, section_out12[109:43]}); + + assign muxinput_74 = $signed({{60{section_out12[109]}}, section_out12[109:60]}); + + assign muxinput_94 = $signed({{77{section_out12[109]}}, section_out12[109:77]}); + + assign output_typeconvert = (bitgain == 7'b0001110) ? muxinput_14 : + (bitgain == 7'b0100010) ? muxinput_34 : + (bitgain == 7'b0110110) ? muxinput_54 : + (bitgain == 7'b1001010) ? muxinput_74 : + muxinput_94; + // ------------------ Output Register ------------------ + + always @ (posedge clk or posedge reset) + begin: output_reg_process + if (reset == 1'b1) begin + output_register <= 0; + end + else begin + if (clk_enable == 1'b1) begin + output_register <= output_typeconvert; + end + end + end // output_reg_process + + // Assignment Statements + assign ce_out = phase_0; + assign filter_out = output_register; +endmodule // cic_interp diff --git a/library/axi_dac_interpolate/fir_interp.v b/library/axi_dac_interpolate/fir_interp.v new file mode 100644 index 000000000..4d6fd69ba --- /dev/null +++ b/library/axi_dac_interpolate/fir_interp.v @@ -0,0 +1,390 @@ +// ------------------------------------------------------------- +// +// Module: fir_interp +// Generated by MATLAB(R) 9.0 and the Filter Design HDL Coder 3.0. +// Generated on: 2016-07-05 15:54:12 +// ------------------------------------------------------------- + +// ------------------------------------------------------------- +// HDL Code Generation Options: +// +// FIRAdderStyle: tree +// OptimizeForHDL: on +// EDAScriptGeneration: off +// AddPipelineRegisters: on +// Name: fir_interp +// TargetLanguage: Verilog +// TestBenchName: fo_copy_tb +// TestBenchStimulus: step ramp chirp noise +// GenerateHDLTestBench: off + +// ------------------------------------------------------------- +// HDL Implementation : Fully parallel +// Multipliers : 12 +// Folding Factor : 1 +// ------------------------------------------------------------- +// Filter Settings: +// +// Discrete-Time FIR Multirate Filter (real) +// ----------------------------------------- +// Filter Structure : Direct-Form FIR Polyphase Interpolator +// Interpolation Factor : 2 +// Polyphase Length : 12 +// Filter Length : 24 +// Stable : Yes +// Linear Phase : Yes (Type 2) +// +// Arithmetic : fixed +// Numerator : s16,15 -> [-1 1) +// ------------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module fir_interp + ( + clk, + clk_enable, + reset, + filter_in, + filter_out, + ce_out + ); + + input clk; + input clk_enable; + input reset; + input signed [15:0] filter_in; //sfix16_En15 + output signed [35:0] filter_out; //sfix36_En30 + output ce_out; + +//////////////////////////////////////////////////////////////// +//Module Architecture: fir_interp +//////////////////////////////////////////////////////////////// + // Local Functions + // Type Definitions + // Constants + parameter signed [15:0] coeffphase1_1 = 16'b1111111110101001; //sfix16_En15 + parameter signed [15:0] coeffphase1_2 = 16'b1111111101111010; //sfix16_En15 + parameter signed [15:0] coeffphase1_3 = 16'b0000010011111111; //sfix16_En15 + parameter signed [15:0] coeffphase1_4 = 16'b1111101010101110; //sfix16_En15 + parameter signed [15:0] coeffphase1_5 = 16'b1111001001101000; //sfix16_En15 + parameter signed [15:0] coeffphase1_6 = 16'b0011011010110011; //sfix16_En15 + parameter signed [15:0] coeffphase1_7 = 16'b0101011100111111; //sfix16_En15 + parameter signed [15:0] coeffphase1_8 = 16'b0000110010011010; //sfix16_En15 + parameter signed [15:0] coeffphase1_9 = 16'b1111000000000010; //sfix16_En15 + parameter signed [15:0] coeffphase1_10 = 16'b0000001110101000; //sfix16_En15 + parameter signed [15:0] coeffphase1_11 = 16'b0000000111110010; //sfix16_En15 + parameter signed [15:0] coeffphase1_12 = 16'b1111111100011100; //sfix16_En15 + parameter signed [15:0] coeffphase2_1 = 16'b1111111100011100; //sfix16_En15 + parameter signed [15:0] coeffphase2_2 = 16'b0000000111110010; //sfix16_En15 + parameter signed [15:0] coeffphase2_3 = 16'b0000001110101000; //sfix16_En15 + parameter signed [15:0] coeffphase2_4 = 16'b1111000000000010; //sfix16_En15 + parameter signed [15:0] coeffphase2_5 = 16'b0000110010011010; //sfix16_En15 + parameter signed [15:0] coeffphase2_6 = 16'b0101011100111111; //sfix16_En15 + parameter signed [15:0] coeffphase2_7 = 16'b0011011010110011; //sfix16_En15 + parameter signed [15:0] coeffphase2_8 = 16'b1111001001101000; //sfix16_En15 + parameter signed [15:0] coeffphase2_9 = 16'b1111101010101110; //sfix16_En15 + parameter signed [15:0] coeffphase2_10 = 16'b0000010011111111; //sfix16_En15 + parameter signed [15:0] coeffphase2_11 = 16'b1111111101111010; //sfix16_En15 + parameter signed [15:0] coeffphase2_12 = 16'b1111111110101001; //sfix16_En15 + + // Signals + reg [1:0] cur_count = 0; // ufix2 + wire phase_1; // boolean + reg signed [15:0] delay_pipeline [0:11]; // sfix16_En15 + wire signed [31:0] product; // sfix32_En30 + wire signed [15:0] product_mux; // sfix16_En15 + wire signed [31:0] product_1; // sfix32_En30 + wire signed [15:0] product_mux_1; // sfix16_En15 + wire signed [31:0] product_2; // sfix32_En30 + wire signed [15:0] product_mux_2; // sfix16_En15 + wire signed [31:0] product_3; // sfix32_En30 + wire signed [15:0] product_mux_3; // sfix16_En15 + wire signed [31:0] product_4; // sfix32_En30 + wire signed [15:0] product_mux_4; // sfix16_En15 + wire signed [31:0] product_5; // sfix32_En30 + wire signed [15:0] product_mux_5; // sfix16_En15 + wire signed [31:0] product_6; // sfix32_En30 + wire signed [15:0] product_mux_6; // sfix16_En15 + wire signed [31:0] product_7; // sfix32_En30 + wire signed [15:0] product_mux_7; // sfix16_En15 + wire signed [31:0] product_8; // sfix32_En30 + wire signed [15:0] product_mux_8; // sfix16_En15 + wire signed [31:0] product_9; // sfix32_En30 + wire signed [15:0] product_mux_9; // sfix16_En15 + wire signed [31:0] product_10; // sfix32_En30 + wire signed [15:0] product_mux_10; // sfix16_En15 + wire signed [31:0] product_11; // sfix32_En30 + wire signed [15:0] product_mux_11; // sfix16_En15 + wire signed [35:0] sumvector1 [0:5] ; // sfix36_En30 + wire signed [31:0] add_signext; // sfix32_En30 + wire signed [31:0] add_signext_1; // sfix32_En30 + wire signed [32:0] add_temp; // sfix33_En30 + wire signed [31:0] add_signext_2; // sfix32_En30 + wire signed [31:0] add_signext_3; // sfix32_En30 + wire signed [32:0] add_temp_1; // sfix33_En30 + wire signed [31:0] add_signext_4; // sfix32_En30 + wire signed [31:0] add_signext_5; // sfix32_En30 + wire signed [32:0] add_temp_2; // sfix33_En30 + wire signed [31:0] add_signext_6; // sfix32_En30 + wire signed [31:0] add_signext_7; // sfix32_En30 + wire signed [32:0] add_temp_3; // sfix33_En30 + wire signed [31:0] add_signext_8; // sfix32_En30 + wire signed [31:0] add_signext_9; // sfix32_En30 + wire signed [32:0] add_temp_4; // sfix33_En30 + wire signed [31:0] add_signext_10; // sfix32_En30 + wire signed [31:0] add_signext_11; // sfix32_En30 + wire signed [32:0] add_temp_5; // sfix33_En30 + reg signed [35:0] sumdelay_pipeline1 [0:5]; // sfix36_En30 + wire signed [35:0] sumvector2 [0:2] ; // sfix36_En30 + wire signed [35:0] add_signext_12; // sfix36_En30 + wire signed [35:0] add_signext_13; // sfix36_En30 + wire signed [36:0] add_temp_6; // sfix37_En30 + wire signed [35:0] add_signext_14; // sfix36_En30 + wire signed [35:0] add_signext_15; // sfix36_En30 + wire signed [36:0] add_temp_7; // sfix37_En30 + wire signed [35:0] add_signext_16; // sfix36_En30 + wire signed [35:0] add_signext_17; // sfix36_En30 + wire signed [36:0] add_temp_8; // sfix37_En30 + reg signed [35:0] sumdelay_pipeline2 [0:2]; // sfix36_En30 + wire signed [35:0] sumvector3 [0:1] ; // sfix36_En30 + wire signed [35:0] add_signext_18; // sfix36_En30 + wire signed [35:0] add_signext_19; // sfix36_En30 + wire signed [36:0] add_temp_9; // sfix37_En30 + reg signed [35:0] sumdelay_pipeline3 [0:1]; // sfix36_En30 + wire signed [35:0] sum4; // sfix36_En30 + wire signed [35:0] add_signext_20; // sfix36_En30 + wire signed [35:0] add_signext_21; // sfix36_En30 + wire signed [36:0] add_temp_10; // sfix37_En30 + reg signed [35:0] output_register = 0; // sfix36_En30 + + // Block Statements + always @ (posedge clk or posedge reset) + begin: ce_output + if (reset == 1'b1) begin + cur_count <= 2'b00; + end + else begin + if (clk_enable == 1'b1) begin + if (cur_count == 2'b01) begin + cur_count <= 2'b00; + end + else begin + cur_count <= cur_count + 1; + end + end + end + end // ce_output + + assign phase_1 = (cur_count == 2'b01 && clk_enable == 1'b1)? 1 : 0; + + // ---------------- Delay Registers ---------------- + + always @( posedge clk or posedge reset) + begin: Delay_Pipeline_process + if (reset == 1'b1) begin + delay_pipeline[0] <= 0; + delay_pipeline[1] <= 0; + delay_pipeline[2] <= 0; + delay_pipeline[3] <= 0; + delay_pipeline[4] <= 0; + delay_pipeline[5] <= 0; + delay_pipeline[6] <= 0; + delay_pipeline[7] <= 0; + delay_pipeline[8] <= 0; + delay_pipeline[9] <= 0; + delay_pipeline[10] <= 0; + delay_pipeline[11] <= 0; + end + else begin + if (phase_1 == 1'b1) begin + delay_pipeline[0] <= filter_in; + delay_pipeline[1] <= delay_pipeline[0]; + delay_pipeline[2] <= delay_pipeline[1]; + delay_pipeline[3] <= delay_pipeline[2]; + delay_pipeline[4] <= delay_pipeline[3]; + delay_pipeline[5] <= delay_pipeline[4]; + delay_pipeline[6] <= delay_pipeline[5]; + delay_pipeline[7] <= delay_pipeline[6]; + delay_pipeline[8] <= delay_pipeline[7]; + delay_pipeline[9] <= delay_pipeline[8]; + delay_pipeline[10] <= delay_pipeline[9]; + delay_pipeline[11] <= delay_pipeline[10]; + end + end + end // Delay_Pipeline_process + + + assign product_mux = (cur_count == 2'b00) ? coeffphase1_12 : + coeffphase2_12; + assign product = delay_pipeline[11] * product_mux; + + assign product_mux_1 = (cur_count == 2'b00) ? coeffphase1_11 : + coeffphase2_11; + assign product_1 = delay_pipeline[10] * product_mux_1; + + assign product_mux_2 = (cur_count == 2'b00) ? coeffphase1_10 : + coeffphase2_10; + assign product_2 = delay_pipeline[9] * product_mux_2; + + assign product_mux_3 = (cur_count == 2'b00) ? coeffphase1_9 : + coeffphase2_9; + assign product_3 = delay_pipeline[8] * product_mux_3; + + assign product_mux_4 = (cur_count == 2'b00) ? coeffphase1_8 : + coeffphase2_8; + assign product_4 = delay_pipeline[7] * product_mux_4; + + assign product_mux_5 = (cur_count == 2'b00) ? coeffphase1_7 : + coeffphase2_7; + assign product_5 = delay_pipeline[6] * product_mux_5; + + assign product_mux_6 = (cur_count == 2'b00) ? coeffphase1_6 : + coeffphase2_6; + assign product_6 = delay_pipeline[5] * product_mux_6; + + assign product_mux_7 = (cur_count == 2'b00) ? coeffphase1_5 : + coeffphase2_5; + assign product_7 = delay_pipeline[4] * product_mux_7; + + assign product_mux_8 = (cur_count == 2'b00) ? coeffphase1_4 : + coeffphase2_4; + assign product_8 = delay_pipeline[3] * product_mux_8; + + assign product_mux_9 = (cur_count == 2'b00) ? coeffphase1_3 : + coeffphase2_3; + assign product_9 = delay_pipeline[2] * product_mux_9; + + assign product_mux_10 = (cur_count == 2'b00) ? coeffphase1_2 : + coeffphase2_2; + assign product_10 = delay_pipeline[1] * product_mux_10; + + assign product_mux_11 = (cur_count == 2'b00) ? coeffphase1_1 : + coeffphase2_1; + assign product_11 = delay_pipeline[0] * product_mux_11; + + assign add_signext = product; + assign add_signext_1 = product_1; + assign add_temp = add_signext + add_signext_1; + assign sumvector1[0] = $signed({{3{add_temp[32]}}, add_temp}); + + assign add_signext_2 = product_2; + assign add_signext_3 = product_3; + assign add_temp_1 = add_signext_2 + add_signext_3; + assign sumvector1[1] = $signed({{3{add_temp_1[32]}}, add_temp_1}); + + assign add_signext_4 = product_4; + assign add_signext_5 = product_5; + assign add_temp_2 = add_signext_4 + add_signext_5; + assign sumvector1[2] = $signed({{3{add_temp_2[32]}}, add_temp_2}); + + assign add_signext_6 = product_6; + assign add_signext_7 = product_7; + assign add_temp_3 = add_signext_6 + add_signext_7; + assign sumvector1[3] = $signed({{3{add_temp_3[32]}}, add_temp_3}); + + assign add_signext_8 = product_8; + assign add_signext_9 = product_9; + assign add_temp_4 = add_signext_8 + add_signext_9; + assign sumvector1[4] = $signed({{3{add_temp_4[32]}}, add_temp_4}); + + assign add_signext_10 = product_10; + assign add_signext_11 = product_11; + assign add_temp_5 = add_signext_10 + add_signext_11; + assign sumvector1[5] = $signed({{3{add_temp_5[32]}}, add_temp_5}); + + always @ (posedge clk or posedge reset) + begin: sumdelay_pipeline_process1 + if (reset == 1'b1) begin + sumdelay_pipeline1[0] <= 0; + sumdelay_pipeline1[1] <= 0; + sumdelay_pipeline1[2] <= 0; + sumdelay_pipeline1[3] <= 0; + sumdelay_pipeline1[4] <= 0; + sumdelay_pipeline1[5] <= 0; + end + else begin + if (clk_enable == 1'b1) begin + sumdelay_pipeline1[0] <= sumvector1[0]; + sumdelay_pipeline1[1] <= sumvector1[1]; + sumdelay_pipeline1[2] <= sumvector1[2]; + sumdelay_pipeline1[3] <= sumvector1[3]; + sumdelay_pipeline1[4] <= sumvector1[4]; + sumdelay_pipeline1[5] <= sumvector1[5]; + end + end + end // sumdelay_pipeline_process1 + + assign add_signext_12 = sumdelay_pipeline1[0]; + assign add_signext_13 = sumdelay_pipeline1[1]; + assign add_temp_6 = add_signext_12 + add_signext_13; + assign sumvector2[0] = add_temp_6[35:0]; + + assign add_signext_14 = sumdelay_pipeline1[2]; + assign add_signext_15 = sumdelay_pipeline1[3]; + assign add_temp_7 = add_signext_14 + add_signext_15; + assign sumvector2[1] = add_temp_7[35:0]; + + assign add_signext_16 = sumdelay_pipeline1[4]; + assign add_signext_17 = sumdelay_pipeline1[5]; + assign add_temp_8 = add_signext_16 + add_signext_17; + assign sumvector2[2] = add_temp_8[35:0]; + + always @ (posedge clk or posedge reset) + begin: sumdelay_pipeline_process2 + if (reset == 1'b1) begin + sumdelay_pipeline2[0] <= 0; + sumdelay_pipeline2[1] <= 0; + sumdelay_pipeline2[2] <= 0; + end + else begin + if (clk_enable == 1'b1) begin + sumdelay_pipeline2[0] <= sumvector2[0]; + sumdelay_pipeline2[1] <= sumvector2[1]; + sumdelay_pipeline2[2] <= sumvector2[2]; + end + end + end // sumdelay_pipeline_process2 + + assign add_signext_18 = sumdelay_pipeline2[0]; + assign add_signext_19 = sumdelay_pipeline2[1]; + assign add_temp_9 = add_signext_18 + add_signext_19; + assign sumvector3[0] = add_temp_9[35:0]; + + assign sumvector3[1] = sumdelay_pipeline2[2]; + + always @ (posedge clk or posedge reset) + begin: sumdelay_pipeline_process3 + if (reset == 1'b1) begin + sumdelay_pipeline3[0] <= 0; + sumdelay_pipeline3[1] <= 0; + end + else begin + if (clk_enable == 1'b1) begin + sumdelay_pipeline3[0] <= sumvector3[0]; + sumdelay_pipeline3[1] <= sumvector3[1]; + end + end + end // sumdelay_pipeline_process3 + + assign add_signext_20 = sumdelay_pipeline3[0]; + assign add_signext_21 = sumdelay_pipeline3[1]; + assign add_temp_10 = add_signext_20 + add_signext_21; + assign sum4 = add_temp_10[35:0]; + + always @ (posedge clk or posedge reset) + begin: Output_Register_process + if (reset == 1'b1) begin + output_register <= 0; + end + else begin + if (clk_enable == 1'b1) begin + output_register <= sum4; + end + end + end // Output_Register_process + + // Assignment Statements + assign ce_out = phase_1; + assign filter_out = output_register; +endmodule // fir_interp diff --git a/library/axi_dmac/2d_transfer.v b/library/axi_dmac/2d_transfer.v index 6f9c25549..13f4e2dff 100644 --- a/library/axi_dmac/2d_transfer.v +++ b/library/axi_dmac/2d_transfer.v @@ -37,28 +37,28 @@ // *************************************************************************** module dmac_2d_transfer ( - input req_aclk, - input req_aresetn, + input req_aclk, + input req_aresetn, - input req_valid, - output reg req_ready, + input req_valid, + output reg req_ready, - input [31:BYTES_PER_BEAT_WIDTH_DEST] req_dest_address, - input [31:BYTES_PER_BEAT_WIDTH_SRC] req_src_address, - input [DMA_LENGTH_WIDTH-1:0] req_x_length, - input [DMA_LENGTH_WIDTH-1:0] req_y_length, - input [DMA_LENGTH_WIDTH-1:0] req_dest_stride, - input [DMA_LENGTH_WIDTH-1:0] req_src_stride, - input req_sync_transfer_start, - output reg req_eot, - - output reg out_req_valid, - input out_req_ready, - output [31:BYTES_PER_BEAT_WIDTH_DEST] out_req_dest_address, - output [31:BYTES_PER_BEAT_WIDTH_SRC] out_req_src_address, - output [DMA_LENGTH_WIDTH-1:0] out_req_length, - output reg out_req_sync_transfer_start, - input out_eot + input [31:BYTES_PER_BEAT_WIDTH_DEST] req_dest_address, + input [31:BYTES_PER_BEAT_WIDTH_SRC] req_src_address, + input [DMA_LENGTH_WIDTH-1:0] req_x_length, + input [DMA_LENGTH_WIDTH-1:0] req_y_length, + input [DMA_LENGTH_WIDTH-1:0] req_dest_stride, + input [DMA_LENGTH_WIDTH-1:0] req_src_stride, + input req_sync_transfer_start, + output reg req_eot, + + output reg out_req_valid, + input out_req_ready, + output [31:BYTES_PER_BEAT_WIDTH_DEST] out_req_dest_address, + output [31:BYTES_PER_BEAT_WIDTH_SRC] out_req_src_address, + output [DMA_LENGTH_WIDTH-1:0] out_req_length, + output reg out_req_sync_transfer_start, + input out_eot ); parameter DMA_LENGTH_WIDTH = 24; @@ -82,61 +82,61 @@ assign out_req_length = x_length; always @(posedge req_aclk) begin - if (req_aresetn == 1'b0) begin - req_id <= 2'b0; - eot_id <= 2'b0; - req_eot <= 1'b0; - end else begin - if (out_req_valid && out_req_ready) begin - req_id <= req_id + 1'b1; - last_req[req_id] <= y_length == 0; - end - req_eot <= 1'b0; - if (out_eot) begin - eot_id <= eot_id + 1'b1; - req_eot <= last_req[eot_id]; - end - end + if (req_aresetn == 1'b0) begin + req_id <= 2'b0; + eot_id <= 2'b0; + req_eot <= 1'b0; + end else begin + if (out_req_valid && out_req_ready) begin + req_id <= req_id + 1'b1; + last_req[req_id] <= y_length == 0; + end + req_eot <= 1'b0; + if (out_eot) begin + eot_id <= eot_id + 1'b1; + req_eot <= last_req[eot_id]; + end + end end always @(posedge req_aclk) begin - if (req_aresetn == 1'b0) begin - dest_address <= 'h00; - src_address <= 'h00; - x_length <= 'h00; - y_length <= 'h00; - dest_stride <= 'h00; - src_stride <= 'h00; - req_ready <= 1'b1; - out_req_valid <= 1'b0; - out_req_sync_transfer_start <= 1'b0; - end else begin - if (req_ready) begin - if (req_valid) begin - dest_address <= req_dest_address; - src_address <= req_src_address; - x_length <= req_x_length; - y_length <= req_y_length; - dest_stride <= req_dest_stride; - src_stride <= req_src_stride; - out_req_sync_transfer_start <= req_sync_transfer_start; - req_ready <= 1'b0; - out_req_valid <= 1'b1; - end - end else begin - if (out_req_valid && out_req_ready) begin - dest_address <= dest_address + dest_stride[DMA_LENGTH_WIDTH-1:BYTES_PER_BEAT_WIDTH_DEST]; - src_address <= src_address + src_stride[DMA_LENGTH_WIDTH-1:BYTES_PER_BEAT_WIDTH_SRC]; - y_length <= y_length - 1'b1; - out_req_sync_transfer_start <= 1'b0; - if (y_length == 0) begin - out_req_valid <= 1'b0; - req_ready <= 1'b1; - end - end - end - end + if (req_aresetn == 1'b0) begin + dest_address <= 'h00; + src_address <= 'h00; + x_length <= 'h00; + y_length <= 'h00; + dest_stride <= 'h00; + src_stride <= 'h00; + req_ready <= 1'b1; + out_req_valid <= 1'b0; + out_req_sync_transfer_start <= 1'b0; + end else begin + if (req_ready) begin + if (req_valid) begin + dest_address <= req_dest_address; + src_address <= req_src_address; + x_length <= req_x_length; + y_length <= req_y_length; + dest_stride <= req_dest_stride; + src_stride <= req_src_stride; + out_req_sync_transfer_start <= req_sync_transfer_start; + req_ready <= 1'b0; + out_req_valid <= 1'b1; + end + end else begin + if (out_req_valid && out_req_ready) begin + dest_address <= dest_address + dest_stride[DMA_LENGTH_WIDTH-1:BYTES_PER_BEAT_WIDTH_DEST]; + src_address <= src_address + src_stride[DMA_LENGTH_WIDTH-1:BYTES_PER_BEAT_WIDTH_SRC]; + y_length <= y_length - 1'b1; + out_req_sync_transfer_start <= 1'b0; + if (y_length == 0) begin + out_req_valid <= 1'b0; + req_ready <= 1'b1; + end + end + end + end end endmodule diff --git a/library/axi_dmac/Makefile b/library/axi_dmac/Makefile index 7c9e6bc4a..cebb500d9 100644 --- a/library/axi_dmac/Makefile +++ b/library/axi_dmac/Makefile @@ -5,31 +5,35 @@ #################################################################################### #################################################################################### -M_DEPS := axi_dmac_ip.tcl -M_DEPS += ../scripts/adi_env.tcl -M_DEPS += ../scripts/adi_ip.tcl M_DEPS += ../common/sync_bits.v M_DEPS += ../common/up_axi.v -M_DEPS += address_generator.v -M_DEPS += data_mover.v -M_DEPS += request_arb.v -M_DEPS += request_generator.v -M_DEPS += response_handler.v -M_DEPS += axi_register_slice.v +M_DEPS += ../scripts/adi_env.tcl +M_DEPS += ../scripts/adi_ip.tcl M_DEPS += 2d_transfer.v +M_DEPS += address_generator.v +M_DEPS += axi_dmac.v +M_DEPS += axi_dmac_ip.tcl +M_DEPS += axi_register_slice.v +M_DEPS += data_mover.v M_DEPS += dest_axi_mm.v M_DEPS += dest_axi_stream.v M_DEPS += dest_fifo_inf.v +M_DEPS += request_arb.v +M_DEPS += request_generator.v +M_DEPS += response_generator.v +M_DEPS += response_handler.v +M_DEPS += splitter.v M_DEPS += src_axi_mm.v M_DEPS += src_axi_stream.v M_DEPS += src_fifo_inf.v -M_DEPS += splitter.v -M_DEPS += response_generator.v -M_DEPS += axi_dmac.v -M_DEPS += axi_dmac_constr.ttcl -M_DEPS += bd/bd.tcl -M_DEPS += ../util_axis_resize/util_axis_resize.xpr + M_DEPS += ../util_axis_fifo/util_axis_fifo.xpr +M_DEPS += ../util_axis_resize/util_axis_resize.xpr + +M_DEPS += ../interfaces/fifo_rd.xml +M_DEPS += ../interfaces/fifo_rd_rtl.xml +M_DEPS += ../interfaces/fifo_wr.xml +M_DEPS += ../interfaces/fifo_wr_rtl.xml M_VIVADO := vivado -mode batch -source @@ -40,6 +44,10 @@ M_FLIST += *.log M_FLIST += component.xml M_FLIST += *.jou M_FLIST += xgui +M_FLIST += *.ip_user_files +M_FLIST += *.srcs +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil @@ -56,11 +64,11 @@ clean-all: axi_dmac.xpr: $(M_DEPS) - rm -rf $(M_FLIST) + -rm -rf $(M_FLIST) $(M_VIVADO) axi_dmac_ip.tcl >> axi_dmac_ip.log 2>&1 dep: - make -C ../util_axis_resize - make -C ../util_axis_fifo + make -C ../util_axis_fifo/ + make -C ../util_axis_resize/ #################################################################################### #################################################################################### diff --git a/library/axi_dmac/address_generator.v b/library/axi_dmac/address_generator.v index 56320b605..8e38486d5 100644 --- a/library/axi_dmac/address_generator.v +++ b/library/axi_dmac/address_generator.v @@ -36,32 +36,32 @@ // *************************************************************************** module dmac_address_generator ( - input clk, - input resetn, + input clk, + input resetn, - input req_valid, - output reg req_ready, - input [31:BYTES_PER_BEAT_WIDTH] req_address, - input [BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length, + input req_valid, + output reg req_ready, + input [31:BYTES_PER_BEAT_WIDTH] req_address, + input [BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length, - output reg [ID_WIDTH-1:0] id, - input [ID_WIDTH-1:0] request_id, - input sync_id, + output reg [ID_WIDTH-1:0] id, + input [ID_WIDTH-1:0] request_id, + input sync_id, - input eot, + input eot, - input enable, - input pause, - output reg enabled, + input enable, + input pause, + output reg enabled, - input addr_ready, - output reg addr_valid, - output [31:0] addr, - output [ 7:0] len, - output [ 2:0] size, - output [ 1:0] burst, - output [ 2:0] prot, - output [ 3:0] cache + input addr_ready, + output reg addr_valid, + output [31:0] addr, + output [ 7:0] len, + output [ 2:0] size, + output [ 1:0] burst, + output [ 2:0] prot, + output [ 3:0] cache ); @@ -110,52 +110,52 @@ always @(posedge clk) begin end always @(posedge clk) begin - if (resetn == 1'b0) begin - last <= 1'b0; - end else if (addr_valid == 1'b0) begin - last <= eot; - end + if (resetn == 1'b0) begin + last <= 1'b0; + end else if (addr_valid == 1'b0) begin + last <= eot; + end end always @(posedge clk) begin - if (resetn == 1'b0) begin - address <= 'h00; - last_burst_len <= 'h00; - req_ready <= 1'b1; - addr_valid <= 1'b0; - end else begin - if (~enabled) begin - req_ready <= 1'b1; - end else if (req_ready) begin - if (req_valid && enable) begin - address <= req_address; - req_ready <= 1'b0; - last_burst_len <= req_last_burst_length; - end - end else begin - if (addr_valid && addr_ready) begin - address <= address + MAX_BEATS_PER_BURST; - addr_valid <= 1'b0; - if (last) - req_ready <= 1'b1; - end else if (id != request_id && enable) begin - addr_valid <= 1'b1; - end - end - end + if (resetn == 1'b0) begin + address <= 'h00; + last_burst_len <= 'h00; + req_ready <= 1'b1; + addr_valid <= 1'b0; + end else begin + if (~enabled) begin + req_ready <= 1'b1; + end else if (req_ready) begin + if (req_valid && enable) begin + address <= req_address; + req_ready <= 1'b0; + last_burst_len <= req_last_burst_length; + end + end else begin + if (addr_valid && addr_ready) begin + address <= address + MAX_BEATS_PER_BURST; + addr_valid <= 1'b0; + if (last) + req_ready <= 1'b1; + end else if (id != request_id && enable) begin + addr_valid <= 1'b1; + end + end + end end always @(posedge clk) begin - if (resetn == 1'b0) begin - id <='h0; + if (resetn == 1'b0) begin + id <='h0; addr_valid_d1 <= 1'b0; - end else begin + end else begin addr_valid_d1 <= addr_valid; if ((addr_valid && ~addr_valid_d1) || - (sync_id && id != request_id)) - id <= inc_id(id); + (sync_id && id != request_id)) + id <= inc_id(id); - end + end end endmodule diff --git a/library/axi_dmac/axi_dmac.v b/library/axi_dmac/axi_dmac.v index b2503d91c..ba4611412 100644 --- a/library/axi_dmac/axi_dmac.v +++ b/library/axi_dmac/axi_dmac.v @@ -37,141 +37,141 @@ // *************************************************************************** module axi_dmac ( - // Slave AXI interface - input s_axi_aclk, - input s_axi_aresetn, + // Slave AXI interface + input s_axi_aclk, + input s_axi_aresetn, - input s_axi_awvalid, - input [13:0] s_axi_awaddr, - output s_axi_awready, - input [2:0] s_axi_awprot, - input s_axi_wvalid, - input [31:0] s_axi_wdata, - input [ 3:0] s_axi_wstrb, - output s_axi_wready, - output s_axi_bvalid, - output [ 1:0] s_axi_bresp, - input s_axi_bready, - input s_axi_arvalid, - input [13:0] s_axi_araddr, - output s_axi_arready, - input [2:0] s_axi_arprot, - output s_axi_rvalid, - input s_axi_rready, - output [ 1:0] s_axi_rresp, - output [31:0] s_axi_rdata, + input s_axi_awvalid, + input [31:0] s_axi_awaddr, + output s_axi_awready, + input [2:0] s_axi_awprot, + input s_axi_wvalid, + input [31:0] s_axi_wdata, + input [ 3:0] s_axi_wstrb, + output s_axi_wready, + output s_axi_bvalid, + output [ 1:0] s_axi_bresp, + input s_axi_bready, + input s_axi_arvalid, + input [31:0] s_axi_araddr, + output s_axi_arready, + input [2:0] s_axi_arprot, + output s_axi_rvalid, + input s_axi_rready, + output [ 1:0] s_axi_rresp, + output [31:0] s_axi_rdata, - // Interrupt - output reg irq, + // Interrupt + output reg irq, - // Master AXI interface - input m_dest_axi_aclk, - input m_dest_axi_aresetn, + // Master AXI interface + input m_dest_axi_aclk, + input m_dest_axi_aresetn, - // Write address - output [31:0] m_dest_axi_awaddr, - output [7-(4*DMA_AXI_PROTOCOL_DEST):0] m_dest_axi_awlen, - output [ 2:0] m_dest_axi_awsize, - output [ 1:0] m_dest_axi_awburst, - output [ 2:0] m_dest_axi_awprot, - output [ 3:0] m_dest_axi_awcache, - output m_dest_axi_awvalid, - input m_dest_axi_awready, + // Write address + output [31:0] m_dest_axi_awaddr, + output [7-(4*DMA_AXI_PROTOCOL_DEST):0] m_dest_axi_awlen, + output [ 2:0] m_dest_axi_awsize, + output [ 1:0] m_dest_axi_awburst, + output [ 2:0] m_dest_axi_awprot, + output [ 3:0] m_dest_axi_awcache, + output m_dest_axi_awvalid, + input m_dest_axi_awready, - // Write data - output [DMA_DATA_WIDTH_DEST-1:0] m_dest_axi_wdata, - output [(DMA_DATA_WIDTH_DEST/8)-1:0] m_dest_axi_wstrb, - input m_dest_axi_wready, - output m_dest_axi_wvalid, - output m_dest_axi_wlast, + // Write data + output [DMA_DATA_WIDTH_DEST-1:0] m_dest_axi_wdata, + output [(DMA_DATA_WIDTH_DEST/8)-1:0] m_dest_axi_wstrb, + input m_dest_axi_wready, + output m_dest_axi_wvalid, + output m_dest_axi_wlast, - // Write response - input m_dest_axi_bvalid, - input [ 1:0] m_dest_axi_bresp, - output m_dest_axi_bready, + // Write response + input m_dest_axi_bvalid, + input [ 1:0] m_dest_axi_bresp, + output m_dest_axi_bready, - // Unused read interface - output m_dest_axi_arvalid, - output [31:0] m_dest_axi_araddr, - output [7-(4*DMA_AXI_PROTOCOL_DEST):0] m_dest_axi_arlen, - output [ 2:0] m_dest_axi_arsize, - output [ 1:0] m_dest_axi_arburst, - output [ 3:0] m_dest_axi_arcache, - output [ 2:0] m_dest_axi_arprot, - input m_dest_axi_arready, - input m_dest_axi_rvalid, - input [ 1:0] m_dest_axi_rresp, - input [DMA_DATA_WIDTH_DEST-1:0] m_dest_axi_rdata, - output m_dest_axi_rready, + // Unused read interface + output m_dest_axi_arvalid, + output [31:0] m_dest_axi_araddr, + output [7-(4*DMA_AXI_PROTOCOL_DEST):0] m_dest_axi_arlen, + output [ 2:0] m_dest_axi_arsize, + output [ 1:0] m_dest_axi_arburst, + output [ 3:0] m_dest_axi_arcache, + output [ 2:0] m_dest_axi_arprot, + input m_dest_axi_arready, + input m_dest_axi_rvalid, + input [ 1:0] m_dest_axi_rresp, + input [DMA_DATA_WIDTH_DEST-1:0] m_dest_axi_rdata, + output m_dest_axi_rready, - // Master AXI interface - input m_src_axi_aclk, - input m_src_axi_aresetn, + // Master AXI interface + input m_src_axi_aclk, + input m_src_axi_aresetn, - // Read address - input m_src_axi_arready, - output m_src_axi_arvalid, - output [31:0] m_src_axi_araddr, - output [7-(4*DMA_AXI_PROTOCOL_SRC):0] m_src_axi_arlen, - output [ 2:0] m_src_axi_arsize, - output [ 1:0] m_src_axi_arburst, - output [ 2:0] m_src_axi_arprot, - output [ 3:0] m_src_axi_arcache, + // Read address + input m_src_axi_arready, + output m_src_axi_arvalid, + output [31:0] m_src_axi_araddr, + output [7-(4*DMA_AXI_PROTOCOL_SRC):0] m_src_axi_arlen, + output [ 2:0] m_src_axi_arsize, + output [ 1:0] m_src_axi_arburst, + output [ 2:0] m_src_axi_arprot, + output [ 3:0] m_src_axi_arcache, - // Read data and response - input [DMA_DATA_WIDTH_SRC-1:0] m_src_axi_rdata, - output m_src_axi_rready, - input m_src_axi_rvalid, - input [ 1:0] m_src_axi_rresp, + // Read data and response + input [DMA_DATA_WIDTH_SRC-1:0] m_src_axi_rdata, + output m_src_axi_rready, + input m_src_axi_rvalid, + input [ 1:0] m_src_axi_rresp, - // Unused write interface - output m_src_axi_awvalid, - output [31:0] m_src_axi_awaddr, - output [7-(4*DMA_AXI_PROTOCOL_SRC):0] m_src_axi_awlen, - output [ 2:0] m_src_axi_awsize, - output [ 1:0] m_src_axi_awburst, - output [ 3:0] m_src_axi_awcache, - output [ 2:0] m_src_axi_awprot, - input m_src_axi_awready, - output m_src_axi_wvalid, - output [DMA_DATA_WIDTH_SRC-1:0] m_src_axi_wdata, - output [(DMA_DATA_WIDTH_SRC/8)-1:0] m_src_axi_wstrb, - output m_src_axi_wlast, - input m_src_axi_wready, - input m_src_axi_bvalid, - input [ 1:0] m_src_axi_bresp, - output m_src_axi_bready, + // Unused write interface + output m_src_axi_awvalid, + output [31:0] m_src_axi_awaddr, + output [7-(4*DMA_AXI_PROTOCOL_SRC):0] m_src_axi_awlen, + output [ 2:0] m_src_axi_awsize, + output [ 1:0] m_src_axi_awburst, + output [ 3:0] m_src_axi_awcache, + output [ 2:0] m_src_axi_awprot, + input m_src_axi_awready, + output m_src_axi_wvalid, + output [DMA_DATA_WIDTH_SRC-1:0] m_src_axi_wdata, + output [(DMA_DATA_WIDTH_SRC/8)-1:0] m_src_axi_wstrb, + output m_src_axi_wlast, + input m_src_axi_wready, + input m_src_axi_bvalid, + input [ 1:0] m_src_axi_bresp, + output m_src_axi_bready, - // Slave streaming AXI interface - input s_axis_aclk, - output s_axis_ready, - input s_axis_valid, - input [DMA_DATA_WIDTH_SRC-1:0] s_axis_data, - input [0:0] s_axis_user, - output s_axis_xfer_req, + // Slave streaming AXI interface + input s_axis_aclk, + output s_axis_ready, + input s_axis_valid, + input [DMA_DATA_WIDTH_SRC-1:0] s_axis_data, + input [0:0] s_axis_user, + output s_axis_xfer_req, - // Master streaming AXI interface - input m_axis_aclk, - input m_axis_ready, - output m_axis_valid, - output [DMA_DATA_WIDTH_DEST-1:0] m_axis_data, + // Master streaming AXI interface + input m_axis_aclk, + input m_axis_ready, + output m_axis_valid, + output [DMA_DATA_WIDTH_DEST-1:0] m_axis_data, output m_axis_last, output m_axis_xfer_req, - // Input FIFO interface - input fifo_wr_clk, - input fifo_wr_en, - input [DMA_DATA_WIDTH_SRC-1:0] fifo_wr_din, - output fifo_wr_overflow, - input fifo_wr_sync, - output fifo_wr_xfer_req, + // Input FIFO interface + input fifo_wr_clk, + input fifo_wr_en, + input [DMA_DATA_WIDTH_SRC-1:0] fifo_wr_din, + output fifo_wr_overflow, + input fifo_wr_sync, + output fifo_wr_xfer_req, - // Input FIFO interface - input fifo_rd_clk, - input fifo_rd_en, - output fifo_rd_valid, - output [DMA_DATA_WIDTH_DEST-1:0] fifo_rd_dout, - output fifo_rd_underflow, + // Input FIFO interface + input fifo_rd_clk, + input fifo_rd_en, + output fifo_rd_valid, + output [DMA_DATA_WIDTH_DEST-1:0] fifo_rd_dout, + output fifo_rd_underflow, output fifo_rd_xfer_req ); @@ -210,21 +210,28 @@ localparam HAS_SRC_ADDR = DMA_TYPE_SRC == DMA_TYPE_AXI_MM; // Argh... "[Synth 8-2722] system function call clog2 is not allowed here" localparam BYTES_PER_BEAT_WIDTH_DEST = DMA_DATA_WIDTH_DEST > 1024 ? 8 : - DMA_DATA_WIDTH_DEST > 512 ? 7 : - DMA_DATA_WIDTH_DEST > 256 ? 6 : - DMA_DATA_WIDTH_DEST > 128 ? 5 : - DMA_DATA_WIDTH_DEST > 64 ? 4 : - DMA_DATA_WIDTH_DEST > 32 ? 3 : - DMA_DATA_WIDTH_DEST > 16 ? 2 : - DMA_DATA_WIDTH_DEST > 8 ? 1 : 0; + DMA_DATA_WIDTH_DEST > 512 ? 7 : + DMA_DATA_WIDTH_DEST > 256 ? 6 : + DMA_DATA_WIDTH_DEST > 128 ? 5 : + DMA_DATA_WIDTH_DEST > 64 ? 4 : + DMA_DATA_WIDTH_DEST > 32 ? 3 : + DMA_DATA_WIDTH_DEST > 16 ? 2 : + DMA_DATA_WIDTH_DEST > 8 ? 1 : 0; localparam BYTES_PER_BEAT_WIDTH_SRC = DMA_DATA_WIDTH_SRC > 1024 ? 8 : - DMA_DATA_WIDTH_SRC > 512 ? 7 : - DMA_DATA_WIDTH_SRC > 256 ? 6 : - DMA_DATA_WIDTH_SRC > 128 ? 5 : - DMA_DATA_WIDTH_SRC > 64 ? 4 : - DMA_DATA_WIDTH_SRC > 32 ? 3 : - DMA_DATA_WIDTH_SRC > 16 ? 2 : - DMA_DATA_WIDTH_SRC > 8 ? 1 : 0; + DMA_DATA_WIDTH_SRC > 512 ? 7 : + DMA_DATA_WIDTH_SRC > 256 ? 6 : + DMA_DATA_WIDTH_SRC > 128 ? 5 : + DMA_DATA_WIDTH_SRC > 64 ? 4 : + DMA_DATA_WIDTH_SRC > 32 ? 3 : + DMA_DATA_WIDTH_SRC > 16 ? 2 : + DMA_DATA_WIDTH_SRC > 8 ? 1 : 0; +localparam ID_WIDTH = (FIFO_SIZE) > 64 ? 8 : + (FIFO_SIZE) > 32 ? 7 : + (FIFO_SIZE) > 16 ? 6 : + (FIFO_SIZE) > 8 ? 5 : + (FIFO_SIZE) > 4 ? 4 : + (FIFO_SIZE) > 2 ? 3 : + (FIFO_SIZE) > 1 ? 2 : 1; // Register interface signals reg [31:0] up_rdata = 'd0; @@ -273,14 +280,14 @@ reg up_dma_cyclic = CYCLIC; wire up_dma_sync_transfer_start = SYNC_TRANSFER_START ? 1'b1 : 1'b0; // ID signals from the DMAC, just for debugging -wire [2:0] dest_request_id; -wire [2:0] dest_data_id; -wire [2:0] dest_address_id; -wire [2:0] dest_response_id; -wire [2:0] src_request_id; -wire [2:0] src_data_id; -wire [2:0] src_address_id; -wire [2:0] src_response_id; +wire [ID_WIDTH-1:0] dest_request_id; +wire [ID_WIDTH-1:0] dest_data_id; +wire [ID_WIDTH-1:0] dest_address_id; +wire [ID_WIDTH-1:0] dest_response_id; +wire [ID_WIDTH-1:0] src_request_id; +wire [ID_WIDTH-1:0] src_data_id; +wire [ID_WIDTH-1:0] src_address_id; +wire [ID_WIDTH-1:0] src_response_id; wire [7:0] dbg_status; assign m_dest_axi_araddr = 'd0; @@ -300,35 +307,35 @@ assign m_src_axi_wstrb = 'd0; assign m_src_axi_wlast = 'd0; up_axi #( - .ADDRESS_WIDTH (12) + .ADDRESS_WIDTH (12) ) i_up_axi ( - .up_rstn(s_axi_aresetn), - .up_clk(s_axi_aclk), - .up_axi_awvalid(s_axi_awvalid), - .up_axi_awaddr(s_axi_awaddr), - .up_axi_awready(s_axi_awready), - .up_axi_wvalid(s_axi_wvalid), - .up_axi_wdata(s_axi_wdata), - .up_axi_wstrb(s_axi_wstrb), - .up_axi_wready(s_axi_wready), - .up_axi_bvalid(s_axi_bvalid), - .up_axi_bresp(s_axi_bresp), - .up_axi_bready(s_axi_bready), - .up_axi_arvalid(s_axi_arvalid), - .up_axi_araddr(s_axi_araddr), - .up_axi_arready(s_axi_arready), - .up_axi_rvalid(s_axi_rvalid), - .up_axi_rresp(s_axi_rresp), - .up_axi_rdata(s_axi_rdata), - .up_axi_rready(s_axi_rready), - .up_wreq(up_wreq), - .up_waddr(up_waddr), - .up_wdata(up_wdata), - .up_wack(up_wack), - .up_rreq(up_rreq), - .up_raddr(up_raddr), - .up_rdata(up_rdata), - .up_rack(up_rack) + .up_rstn(s_axi_aresetn), + .up_clk(s_axi_aclk), + .up_axi_awvalid(s_axi_awvalid), + .up_axi_awaddr(s_axi_awaddr), + .up_axi_awready(s_axi_awready), + .up_axi_wvalid(s_axi_wvalid), + .up_axi_wdata(s_axi_wdata), + .up_axi_wstrb(s_axi_wstrb), + .up_axi_wready(s_axi_wready), + .up_axi_bvalid(s_axi_bvalid), + .up_axi_bresp(s_axi_bresp), + .up_axi_bready(s_axi_bready), + .up_axi_arvalid(s_axi_arvalid), + .up_axi_araddr(s_axi_araddr), + .up_axi_arready(s_axi_arready), + .up_axi_rvalid(s_axi_rvalid), + .up_axi_rresp(s_axi_rresp), + .up_axi_rdata(s_axi_rdata), + .up_axi_rready(s_axi_rready), + .up_wreq(up_wreq), + .up_waddr(up_waddr), + .up_wdata(up_wdata), + .up_wack(up_wack), + .up_rreq(up_rreq), + .up_raddr(up_raddr), + .up_rdata(up_rdata), + .up_rack(up_rack) ); // IRQ handling @@ -338,124 +345,125 @@ assign up_irq_source_clear = (up_wreq == 1'b1 && up_waddr == 12'h021) ? up_wdata always @(posedge s_axi_aclk) begin - if (s_axi_aresetn == 1'b0) - irq <= 1'b0; - else - irq <= |up_irq_pending; + if (s_axi_aresetn == 1'b0) + irq <= 1'b0; + else + irq <= |up_irq_pending; end always @(posedge s_axi_aclk) begin - if (s_axi_aresetn == 1'b0) begin - up_irq_source <= 2'b00; - end else begin - up_irq_source <= up_irq_trigger | (up_irq_source & ~up_irq_source_clear); - end + if (s_axi_aresetn == 1'b0) begin + up_irq_source <= 2'b00; + end else begin + up_irq_source <= up_irq_trigger | (up_irq_source & ~up_irq_source_clear); + end end // Register Interface always @(posedge s_axi_aclk) begin - if (s_axi_aresetn == 1'b0) begin - up_enable <= 'h00; - up_pause <= 'h00; - up_dma_src_address <= 'h00; - up_dma_dest_address <= 'h00; - up_dma_y_length <= 'h00; - up_dma_x_length <= 'h00; - up_dma_dest_stride <= 'h00; - up_dma_src_stride <= 'h00; - up_irq_mask <= 3'b11; - up_dma_req_valid <= 1'b0; - up_scratch <= 'h00; - up_wack <= 1'b0; - end else begin - up_wack <= up_wreq; - if (up_enable == 1'b1) begin - if (up_wreq && up_waddr == 12'h102) begin - up_dma_req_valid <= up_dma_req_valid | up_wdata[0]; - end else if (up_sot) begin - up_dma_req_valid <= 1'b0; - end - end else begin - up_dma_req_valid <= 1'b0; - end + if (s_axi_aresetn == 1'b0) begin + up_enable <= 'h00; + up_pause <= 'h00; + up_dma_src_address <= 'h00; + up_dma_dest_address <= 'h00; + up_dma_y_length <= 'h00; + up_dma_x_length <= 'h00; + up_dma_dest_stride <= 'h00; + up_dma_src_stride <= 'h00; + up_irq_mask <= 3'b11; + up_dma_req_valid <= 1'b0; + up_scratch <= 'h00; + up_wack <= 1'b0; + end else begin + up_wack <= up_wreq; + if (up_enable == 1'b1) begin + if (up_wreq && up_waddr == 12'h102) begin + up_dma_req_valid <= up_dma_req_valid | up_wdata[0]; + end else if (up_sot) begin + up_dma_req_valid <= 1'b0; + end + end else begin + up_dma_req_valid <= 1'b0; + end - if (up_wreq) begin - case (up_waddr) - 12'h002: up_scratch <= up_wdata; - 12'h020: up_irq_mask <= up_wdata; - 12'h100: {up_pause, up_enable} <= up_wdata[1:0]; + if (up_wreq) begin + case (up_waddr) + 12'h002: up_scratch <= up_wdata; + 12'h020: up_irq_mask <= up_wdata; + 12'h100: {up_pause, up_enable} <= up_wdata[1:0]; 12'h103: begin if (CYCLIC) up_dma_cyclic <= up_wdata[0]; up_axis_xlast <= up_wdata[1]; end - 12'h104: up_dma_dest_address <= up_wdata[31:BYTES_PER_BEAT_WIDTH_DEST]; - 12'h105: up_dma_src_address <= up_wdata[31:BYTES_PER_BEAT_WIDTH_SRC]; - 12'h106: up_dma_x_length <= up_wdata[DMA_LENGTH_WIDTH-1:0]; - 12'h107: up_dma_y_length <= up_wdata[DMA_LENGTH_WIDTH-1:0]; - 12'h108: up_dma_dest_stride <= up_wdata[DMA_LENGTH_WIDTH-1:0]; - 12'h109: up_dma_src_stride <= up_wdata[DMA_LENGTH_WIDTH-1:0]; - endcase - end - end + 12'h104: up_dma_dest_address <= up_wdata[31:BYTES_PER_BEAT_WIDTH_DEST]; + 12'h105: up_dma_src_address <= up_wdata[31:BYTES_PER_BEAT_WIDTH_SRC]; + 12'h106: up_dma_x_length <= up_wdata[DMA_LENGTH_WIDTH-1:0]; + 12'h107: up_dma_y_length <= up_wdata[DMA_LENGTH_WIDTH-1:0]; + 12'h108: up_dma_dest_stride <= up_wdata[DMA_LENGTH_WIDTH-1:0]; + 12'h109: up_dma_src_stride <= up_wdata[DMA_LENGTH_WIDTH-1:0]; + endcase + end + end end always @(posedge s_axi_aclk) begin - if (s_axi_aresetn == 1'b0) begin + if (s_axi_aresetn == 1'b0) begin up_rack <= 'd0; - up_rdata <= 'h00; - end else begin + up_rdata <= 'h00; + end else begin up_rack <= up_rreq; - case (up_raddr) - 12'h000: up_rdata <= PCORE_VERSION; - 12'h001: up_rdata <= ID; - 12'h002: up_rdata <= up_scratch; - 12'h020: up_rdata <= up_irq_mask; - 12'h021: up_rdata <= up_irq_pending; - 12'h022: up_rdata <= up_irq_source; - 12'h100: up_rdata <= {up_pause, up_enable}; - 12'h101: up_rdata <= up_transfer_id; - 12'h102: up_rdata <= up_dma_req_valid; - 12'h103: up_rdata <= {30'h00, up_axis_xlast, up_dma_cyclic}; // Flags - 12'h104: up_rdata <= HAS_DEST_ADDR ? {up_dma_dest_address,{BYTES_PER_BEAT_WIDTH_DEST{1'b0}}} : 'h00; - 12'h105: up_rdata <= HAS_SRC_ADDR ? {up_dma_src_address,{BYTES_PER_BEAT_WIDTH_SRC{1'b0}}} : 'h00; - 12'h106: up_rdata <= up_dma_x_length; - 12'h107: up_rdata <= DMA_2D_TRANSFER ? up_dma_y_length : 'h00; - 12'h108: up_rdata <= DMA_2D_TRANSFER ? up_dma_dest_stride : 'h00; - 12'h109: up_rdata <= DMA_2D_TRANSFER ? up_dma_src_stride : 'h00; - 12'h10a: up_rdata <= up_transfer_done_bitmap; - 12'h10b: up_rdata <= up_transfer_id_eot; - 12'h10c: up_rdata <= 'h00; // Status - 12'h10d: up_rdata <= m_dest_axi_awaddr; //HAS_DEST_ADDR ? 'h00 : 'h00; // Current dest address - 12'h10e: up_rdata <= m_src_axi_araddr; //HAS_SRC_ADDR ? 'h00 : 'h00; // Current src address - 12'h10f: up_rdata <= {src_response_id, 1'b0, src_data_id, 1'b0, src_address_id, 1'b0, src_request_id, - 1'b0, dest_response_id, 1'b0, dest_data_id, 1'b0, dest_address_id, 1'b0, dest_request_id}; - 12'h110: up_rdata <= dbg_status; - default: up_rdata <= 'h00; - endcase - end + case (up_raddr) + 12'h000: up_rdata <= PCORE_VERSION; + 12'h001: up_rdata <= ID; + 12'h002: up_rdata <= up_scratch; + 12'h003: up_rdata <= 32'h444d4143; // "DMAC" + 12'h020: up_rdata <= up_irq_mask; + 12'h021: up_rdata <= up_irq_pending; + 12'h022: up_rdata <= up_irq_source; + 12'h100: up_rdata <= {up_pause, up_enable}; + 12'h101: up_rdata <= up_transfer_id; + 12'h102: up_rdata <= up_dma_req_valid; + 12'h103: up_rdata <= {30'h00, up_axis_xlast, up_dma_cyclic}; // Flags + 12'h104: up_rdata <= HAS_DEST_ADDR ? {up_dma_dest_address,{BYTES_PER_BEAT_WIDTH_DEST{1'b0}}} : 'h00; + 12'h105: up_rdata <= HAS_SRC_ADDR ? {up_dma_src_address,{BYTES_PER_BEAT_WIDTH_SRC{1'b0}}} : 'h00; + 12'h106: up_rdata <= up_dma_x_length; + 12'h107: up_rdata <= DMA_2D_TRANSFER ? up_dma_y_length : 'h00; + 12'h108: up_rdata <= DMA_2D_TRANSFER ? up_dma_dest_stride : 'h00; + 12'h109: up_rdata <= DMA_2D_TRANSFER ? up_dma_src_stride : 'h00; + 12'h10a: up_rdata <= up_transfer_done_bitmap; + 12'h10b: up_rdata <= up_transfer_id_eot; + 12'h10c: up_rdata <= 'h00; // Status + 12'h10d: up_rdata <= m_dest_axi_awaddr; //HAS_DEST_ADDR ? 'h00 : 'h00; // Current dest address + 12'h10e: up_rdata <= m_src_axi_araddr; //HAS_SRC_ADDR ? 'h00 : 'h00; // Current src address + 12'h10f: up_rdata <= {src_response_id, 1'b0, src_data_id, 1'b0, src_address_id, 1'b0, src_request_id, + 1'b0, dest_response_id, 1'b0, dest_data_id, 1'b0, dest_address_id, 1'b0, dest_request_id}; + 12'h110: up_rdata <= dbg_status; + default: up_rdata <= 'h00; + endcase + end end // Request ID and Request done bitmap handling always @(posedge s_axi_aclk) begin - if (s_axi_aresetn == 1'b0 || up_enable == 1'b0) begin - up_transfer_id <= 'h0; - up_transfer_id_eot <= 'h0; - up_transfer_done_bitmap <= 'h0; - end begin - if (up_dma_req_valid == 1'b1 && up_dma_req_ready == 1'b1) begin - up_transfer_id <= up_transfer_id + 1'b1; - up_transfer_done_bitmap[up_transfer_id] <= 1'b0; - end - if (up_eot == 1'b1) begin - up_transfer_done_bitmap[up_transfer_id_eot] <= 1'b1; - up_transfer_id_eot <= up_transfer_id_eot + 1'b1; - end - end + if (s_axi_aresetn == 1'b0 || up_enable == 1'b0) begin + up_transfer_id <= 'h0; + up_transfer_id_eot <= 'h0; + up_transfer_done_bitmap <= 'h0; + end begin + if (up_dma_req_valid == 1'b1 && up_dma_req_ready == 1'b1) begin + up_transfer_id <= up_transfer_id + 1'b1; + up_transfer_done_bitmap[up_transfer_id] <= 1'b0; + end + if (up_eot == 1'b1) begin + up_transfer_done_bitmap[up_transfer_id_eot] <= 1'b1; + up_transfer_id_eot <= up_transfer_id_eot + 1'b1; + end + end end wire dma_req_valid; @@ -474,32 +482,32 @@ assign up_eot = up_dma_cyclic ? 1'b0 : up_req_eot; generate if (DMA_2D_TRANSFER == 1) begin dmac_2d_transfer #( - .DMA_LENGTH_WIDTH(DMA_LENGTH_WIDTH), - .BYTES_PER_BEAT_WIDTH_DEST(BYTES_PER_BEAT_WIDTH_DEST), - .BYTES_PER_BEAT_WIDTH_SRC(BYTES_PER_BEAT_WIDTH_SRC) + .DMA_LENGTH_WIDTH(DMA_LENGTH_WIDTH), + .BYTES_PER_BEAT_WIDTH_DEST(BYTES_PER_BEAT_WIDTH_DEST), + .BYTES_PER_BEAT_WIDTH_SRC(BYTES_PER_BEAT_WIDTH_SRC) ) i_2d_transfer ( - .req_aclk(s_axi_aclk), - .req_aresetn(s_axi_aresetn), + .req_aclk(s_axi_aclk), + .req_aresetn(s_axi_aresetn), - .req_eot(up_req_eot), + .req_eot(up_req_eot), - .req_valid(up_dma_req_valid), - .req_ready(up_dma_req_ready), - .req_dest_address(up_dma_dest_address), - .req_src_address(up_dma_src_address), - .req_x_length(up_dma_x_length), - .req_y_length(up_dma_y_length), - .req_dest_stride(up_dma_dest_stride), - .req_src_stride(up_dma_src_stride), - .req_sync_transfer_start(up_dma_sync_transfer_start), + .req_valid(up_dma_req_valid), + .req_ready(up_dma_req_ready), + .req_dest_address(up_dma_dest_address), + .req_src_address(up_dma_src_address), + .req_x_length(up_dma_x_length), + .req_y_length(up_dma_y_length), + .req_dest_stride(up_dma_dest_stride), + .req_src_stride(up_dma_src_stride), + .req_sync_transfer_start(up_dma_sync_transfer_start), - .out_req_valid(dma_req_valid), - .out_req_ready(dma_req_ready), - .out_req_dest_address(dma_req_dest_address), - .out_req_src_address(dma_req_src_address), - .out_req_length(dma_req_length), - .out_req_sync_transfer_start(dma_req_sync_transfer_start), - .out_eot(dma_req_eot) + .out_req_valid(dma_req_valid), + .out_req_ready(dma_req_ready), + .out_req_dest_address(dma_req_dest_address), + .out_req_src_address(dma_req_src_address), + .out_req_length(dma_req_length), + .out_req_sync_transfer_start(dma_req_sync_transfer_start), + .out_eot(dma_req_eot) ); end else begin @@ -515,123 +523,124 @@ assign up_req_eot = dma_req_eot; end endgenerate dmac_request_arb #( - .DMA_DATA_WIDTH_SRC(DMA_DATA_WIDTH_SRC), - .DMA_DATA_WIDTH_DEST(DMA_DATA_WIDTH_DEST), - .DMA_LENGTH_WIDTH(DMA_LENGTH_WIDTH), - .BYTES_PER_BEAT_WIDTH_DEST(BYTES_PER_BEAT_WIDTH_DEST), - .BYTES_PER_BEAT_WIDTH_SRC(BYTES_PER_BEAT_WIDTH_SRC), - .DMA_TYPE_DEST(DMA_TYPE_DEST), - .DMA_TYPE_SRC(DMA_TYPE_SRC), - .ASYNC_CLK_REQ_SRC(ASYNC_CLK_REQ_SRC), - .ASYNC_CLK_SRC_DEST(ASYNC_CLK_SRC_DEST), - .ASYNC_CLK_DEST_REQ(ASYNC_CLK_DEST_REQ), - .AXI_SLICE_DEST(AXI_SLICE_DEST), - .AXI_SLICE_SRC(AXI_SLICE_SRC), - .MAX_BYTES_PER_BURST(MAX_BYTES_PER_BURST), - .FIFO_SIZE(FIFO_SIZE) + .DMA_DATA_WIDTH_SRC(DMA_DATA_WIDTH_SRC), + .DMA_DATA_WIDTH_DEST(DMA_DATA_WIDTH_DEST), + .DMA_LENGTH_WIDTH(DMA_LENGTH_WIDTH), + .BYTES_PER_BEAT_WIDTH_DEST(BYTES_PER_BEAT_WIDTH_DEST), + .BYTES_PER_BEAT_WIDTH_SRC(BYTES_PER_BEAT_WIDTH_SRC), + .DMA_TYPE_DEST(DMA_TYPE_DEST), + .DMA_TYPE_SRC(DMA_TYPE_SRC), + .ASYNC_CLK_REQ_SRC(ASYNC_CLK_REQ_SRC), + .ASYNC_CLK_SRC_DEST(ASYNC_CLK_SRC_DEST), + .ASYNC_CLK_DEST_REQ(ASYNC_CLK_DEST_REQ), + .AXI_SLICE_DEST(AXI_SLICE_DEST), + .AXI_SLICE_SRC(AXI_SLICE_SRC), + .MAX_BYTES_PER_BURST(MAX_BYTES_PER_BURST), + .FIFO_SIZE(FIFO_SIZE), + .ID_WIDTH(ID_WIDTH) ) i_request_arb ( - .req_aclk(s_axi_aclk), - .req_aresetn(s_axi_aresetn), + .req_aclk(s_axi_aclk), + .req_aresetn(s_axi_aresetn), - .enable(up_enable), - .pause(up_pause), + .enable(up_enable), + .pause(up_pause), - .req_valid(dma_req_valid), - .req_ready(dma_req_ready), - .req_dest_address(dma_req_dest_address), - .req_src_address(dma_req_src_address), - .req_length(dma_req_length), + .req_valid(dma_req_valid), + .req_ready(dma_req_ready), + .req_dest_address(dma_req_dest_address), + .req_src_address(dma_req_src_address), + .req_length(dma_req_length), .req_xlast(up_axis_xlast), - .req_sync_transfer_start(dma_req_sync_transfer_start), + .req_sync_transfer_start(dma_req_sync_transfer_start), - .eot(dma_req_eot), + .eot(dma_req_eot), - .m_dest_axi_aclk(m_dest_axi_aclk), - .m_dest_axi_aresetn(m_dest_axi_aresetn), - .m_src_axi_aclk(m_src_axi_aclk), - .m_src_axi_aresetn(m_src_axi_aresetn), + .m_dest_axi_aclk(m_dest_axi_aclk), + .m_dest_axi_aresetn(m_dest_axi_aresetn), + .m_src_axi_aclk(m_src_axi_aclk), + .m_src_axi_aresetn(m_src_axi_aresetn), - .m_axi_awaddr(m_dest_axi_awaddr), - .m_axi_awlen(m_dest_axi_awlen), - .m_axi_awsize(m_dest_axi_awsize), - .m_axi_awburst(m_dest_axi_awburst), - .m_axi_awprot(m_dest_axi_awprot), - .m_axi_awcache(m_dest_axi_awcache), - .m_axi_awvalid(m_dest_axi_awvalid), - .m_axi_awready(m_dest_axi_awready), + .m_axi_awaddr(m_dest_axi_awaddr), + .m_axi_awlen(m_dest_axi_awlen), + .m_axi_awsize(m_dest_axi_awsize), + .m_axi_awburst(m_dest_axi_awburst), + .m_axi_awprot(m_dest_axi_awprot), + .m_axi_awcache(m_dest_axi_awcache), + .m_axi_awvalid(m_dest_axi_awvalid), + .m_axi_awready(m_dest_axi_awready), - .m_axi_wdata(m_dest_axi_wdata), - .m_axi_wstrb(m_dest_axi_wstrb), - .m_axi_wready(m_dest_axi_wready), - .m_axi_wvalid(m_dest_axi_wvalid), - .m_axi_wlast(m_dest_axi_wlast), + .m_axi_wdata(m_dest_axi_wdata), + .m_axi_wstrb(m_dest_axi_wstrb), + .m_axi_wready(m_dest_axi_wready), + .m_axi_wvalid(m_dest_axi_wvalid), + .m_axi_wlast(m_dest_axi_wlast), - .m_axi_bvalid(m_dest_axi_bvalid), - .m_axi_bresp(m_dest_axi_bresp), - .m_axi_bready(m_dest_axi_bready), + .m_axi_bvalid(m_dest_axi_bvalid), + .m_axi_bresp(m_dest_axi_bresp), + .m_axi_bready(m_dest_axi_bready), - .m_axi_arready(m_src_axi_arready), - .m_axi_arvalid(m_src_axi_arvalid), - .m_axi_araddr(m_src_axi_araddr), - .m_axi_arlen(m_src_axi_arlen), - .m_axi_arsize(m_src_axi_arsize), - .m_axi_arburst(m_src_axi_arburst), - .m_axi_arprot(m_src_axi_arprot), - .m_axi_arcache(m_src_axi_arcache), + .m_axi_arready(m_src_axi_arready), + .m_axi_arvalid(m_src_axi_arvalid), + .m_axi_araddr(m_src_axi_araddr), + .m_axi_arlen(m_src_axi_arlen), + .m_axi_arsize(m_src_axi_arsize), + .m_axi_arburst(m_src_axi_arburst), + .m_axi_arprot(m_src_axi_arprot), + .m_axi_arcache(m_src_axi_arcache), - .m_axi_rdata(m_src_axi_rdata), - .m_axi_rready(m_src_axi_rready), - .m_axi_rvalid(m_src_axi_rvalid), - .m_axi_rresp(m_src_axi_rresp), + .m_axi_rdata(m_src_axi_rdata), + .m_axi_rready(m_src_axi_rready), + .m_axi_rvalid(m_src_axi_rvalid), + .m_axi_rresp(m_src_axi_rresp), - .s_axis_aclk(s_axis_aclk), - .s_axis_ready(s_axis_ready), - .s_axis_valid(s_axis_valid), - .s_axis_data(s_axis_data), - .s_axis_user(s_axis_user), - .s_axis_xfer_req(s_axis_xfer_req), + .s_axis_aclk(s_axis_aclk), + .s_axis_ready(s_axis_ready), + .s_axis_valid(s_axis_valid), + .s_axis_data(s_axis_data), + .s_axis_user(s_axis_user), + .s_axis_xfer_req(s_axis_xfer_req), - .m_axis_aclk(m_axis_aclk), - .m_axis_ready(m_axis_ready), - .m_axis_valid(m_axis_valid), - .m_axis_data(m_axis_data), + .m_axis_aclk(m_axis_aclk), + .m_axis_ready(m_axis_ready), + .m_axis_valid(m_axis_valid), + .m_axis_data(m_axis_data), .m_axis_last(m_axis_last), .m_axis_xfer_req(m_axis_xfer_req), - .fifo_wr_clk(fifo_wr_clk), - .fifo_wr_en(fifo_wr_en), - .fifo_wr_din(fifo_wr_din), - .fifo_wr_overflow(fifo_wr_overflow), - .fifo_wr_sync(fifo_wr_sync), - .fifo_wr_xfer_req(fifo_wr_xfer_req), + .fifo_wr_clk(fifo_wr_clk), + .fifo_wr_en(fifo_wr_en), + .fifo_wr_din(fifo_wr_din), + .fifo_wr_overflow(fifo_wr_overflow), + .fifo_wr_sync(fifo_wr_sync), + .fifo_wr_xfer_req(fifo_wr_xfer_req), - .fifo_rd_clk(fifo_rd_clk), - .fifo_rd_en(fifo_rd_en), - .fifo_rd_valid(fifo_rd_valid), - .fifo_rd_dout(fifo_rd_dout), - .fifo_rd_underflow(fifo_rd_underflow), + .fifo_rd_clk(fifo_rd_clk), + .fifo_rd_en(fifo_rd_en), + .fifo_rd_valid(fifo_rd_valid), + .fifo_rd_dout(fifo_rd_dout), + .fifo_rd_underflow(fifo_rd_underflow), .fifo_rd_xfer_req(fifo_rd_xfer_req), - // DBG - .dbg_dest_request_id(dest_request_id), - .dbg_dest_address_id(dest_address_id), - .dbg_dest_data_id(dest_data_id), - .dbg_dest_response_id(dest_response_id), - .dbg_src_request_id(src_request_id), - .dbg_src_address_id(src_address_id), - .dbg_src_data_id(src_data_id), - .dbg_src_response_id(src_response_id), - .dbg_status(dbg_status) + // DBG + .dbg_dest_request_id(dest_request_id), + .dbg_dest_address_id(dest_address_id), + .dbg_dest_data_id(dest_data_id), + .dbg_dest_response_id(dest_response_id), + .dbg_src_request_id(src_request_id), + .dbg_src_address_id(src_address_id), + .dbg_src_data_id(src_data_id), + .dbg_src_response_id(src_response_id), + .dbg_status(dbg_status) ); assign m_dest_axi_arvalid = 1'b0; diff --git a/library/axi_dmac/axi_dmac_constr.ttcl b/library/axi_dmac/axi_dmac_constr.ttcl index 2ca055ecf..a2cabf55f 100644 --- a/library/axi_dmac/axi_dmac_constr.ttcl +++ b/library/axi_dmac/axi_dmac_constr.ttcl @@ -21,40 +21,40 @@ set_property ASYNC_REG TRUE \ set_max_delay -quiet -datapath_only \ -from $req_clk \ -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ - -filter {NAME =~ *i_sync_src_request_id* && PRIMITIVE_SUBGROUP == flop}] \ + -filter {NAME =~ *i_sync_src_request_id* && IS_SEQUENTIAL}] \ [get_property -min PERIOD $req_clk] set_false_path -quiet \ -from $src_clk \ -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ - -filter {NAME =~ *i_sync_status_src* && PRIMITIVE_SUBGROUP == flop}] + -filter {NAME =~ *i_sync_status_src* && IS_SEQUENTIAL}] set_false_path -quiet \ -from $req_clk \ -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ - -filter {NAME =~ *i_sync_control_src* && PRIMITIVE_SUBGROUP == flop}] + -filter {NAME =~ *i_sync_control_src* && IS_SEQUENTIAL}] set_max_delay -quiet -datapath_only \ -from $req_clk \ -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ - -filter {NAME =~ *i_src_req_fifo/i_waddr_sync* && PRIMITIVE_SUBGROUP == flop}] \ + -filter {NAME =~ *i_src_req_fifo/i_waddr_sync* && IS_SEQUENTIAL}] \ [get_property -min PERIOD $req_clk] set_max_delay -quiet -datapath_only \ -from $src_clk \ -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ - -filter {NAME =~ *i_src_req_fifo/i_raddr_sync* && PRIMITIVE_SUBGROUP == flop}] \ + -filter {NAME =~ *i_src_req_fifo/i_raddr_sync* && IS_SEQUENTIAL}] \ [get_property -min PERIOD $src_clk] set_max_delay -quiet -datapath_only \ -from [get_cells -quiet -hier *cdc_sync_fifo_ram_reg* \ - -filter {NAME =~ *i_src_req_fifo* && PRIMITIVE_SUBGROUP == flop}] \ + -filter {NAME =~ *i_src_req_fifo* && IS_SEQUENTIAL}] \ -to $src_clk \ [get_property -min PERIOD $src_clk] set_max_delay -quiet -datapath_only \ -from [get_cells -quiet -hier *eot_mem_reg* \ - -filter {NAME =~ *i_request_arb* && PRIMITIVE_SUBGROUP == flop}] \ + -filter {NAME =~ *i_request_arb* && IS_SEQUENTIAL}] \ -to $src_clk \ [get_property -min PERIOD $src_clk] @@ -63,57 +63,57 @@ set_max_delay -quiet -datapath_only \ set_max_delay -quiet -datapath_only \ -from $dest_clk \ -to [get_cells -hier *cdc_sync_stage1_reg* \ - -filter {NAME =~ *i_sync_req_response_id* && PRIMITIVE_SUBGROUP == flop}] \ + -filter {NAME =~ *i_sync_req_response_id* && IS_SEQUENTIAL}] \ [get_property -min PERIOD $dest_clk] set_false_path -quiet \ -from $dest_clk \ -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ - -filter {NAME =~ *i_sync_status_dest* && PRIMITIVE_SUBGROUP == flop}] + -filter {NAME =~ *i_sync_status_dest* && IS_SEQUENTIAL}] set_false_path -quiet \ -from $req_clk \ -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ - -filter {NAME =~ *i_sync_control_dest* && PRIMITIVE_SUBGROUP == flop}] + -filter {NAME =~ *i_sync_control_dest* && IS_SEQUENTIAL}] set_max_delay -quiet -datapath_only \ -from $req_clk \ -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ - -filter {NAME =~ *i_dest_req_fifo/i_waddr_sync* && PRIMITIVE_SUBGROUP == flop}] \ + -filter {NAME =~ *i_dest_req_fifo/i_waddr_sync* && IS_SEQUENTIAL}] \ [get_property -min PERIOD $req_clk] set_max_delay -quiet -datapath_only \ -from $dest_clk \ -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ - -filter {NAME =~ *i_dest_req_fifo/i_raddr_sync* && PRIMITIVE_SUBGROUP == flop}] \ + -filter {NAME =~ *i_dest_req_fifo/i_raddr_sync* && IS_SEQUENTIAL}] \ [get_property -min PERIOD $dest_clk] set_max_delay -quiet -datapath_only \ -from [get_cells -quiet -hier *cdc_sync_fifo_ram_reg* \ - -filter {NAME =~ *i_dest_req_fifo* && PRIMITIVE_SUBGROUP == flop}] \ + -filter {NAME =~ *i_dest_req_fifo* && IS_SEQUENTIAL}] \ -to $dest_clk \ [get_property -min PERIOD $dest_clk] set_max_delay -quiet -datapath_only \ -from $dest_clk \ -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ - -filter {NAME =~ *i_dest_response_fifo/i_waddr_sync* && PRIMITIVE_SUBGROUP == flop}] \ + -filter {NAME =~ *i_dest_response_fifo/i_waddr_sync* && IS_SEQUENTIAL}] \ [get_property -min PERIOD $dest_clk] set_max_delay -quiet -datapath_only \ -from $req_clk \ -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ - -filter {NAME =~ *i_dest_response_fifo/i_raddr_sync* && PRIMITIVE_SUBGROUP == flop}] \ + -filter {NAME =~ *i_dest_response_fifo/i_raddr_sync* && IS_SEQUENTIAL}] \ [get_property -min PERIOD $req_clk] set_max_delay -quiet -datapath_only \ -from [get_cells -quiet -hier *cdc_sync_fifo_ram_reg* \ - -filter {NAME =~ *i_dest_response_fifo* && PRIMITIVE_SUBGROUP == flop}] \ + -filter {NAME =~ *i_dest_response_fifo* && IS_SEQUENTIAL}] \ -to $req_clk \ [get_property -min PERIOD $req_clk] set_max_delay -quiet -datapath_only \ -from [get_cells -quiet -hier *eot_mem_reg* \ - -filter {NAME =~ *i_request_arb* && PRIMITIVE_SUBGROUP == flop}] \ + -filter {NAME =~ *i_request_arb* && IS_SEQUENTIAL}] \ -to $dest_clk \ [get_property -min PERIOD $dest_clk] @@ -122,19 +122,19 @@ set_max_delay -quiet -datapath_only \ set_max_delay -quiet -datapath_only \ -from $src_clk \ -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ - -filter {NAME =~ *i_sync_dest_request_id* && PRIMITIVE_SUBGROUP == flop}] \ + -filter {NAME =~ *i_sync_dest_request_id* && IS_SEQUENTIAL}] \ [get_property -min PERIOD $src_clk] set_max_delay -quiet -datapath_only \ -from $src_clk \ -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ - -filter {NAME =~ *i_fifo/i_address_gray/i_waddr_sync* && PRIMITIVE_SUBGROUP == flop}] \ + -filter {NAME =~ *i_fifo/i_address_gray/i_waddr_sync* && IS_SEQUENTIAL}] \ [get_property -min PERIOD $src_clk] set_max_delay -quiet -datapath_only \ -from $dest_clk \ -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ - -filter {NAME =~ *i_fifo/i_address_gray/i_raddr_sync* && PRIMITIVE_SUBGROUP == flop}] \ + -filter {NAME =~ *i_fifo/i_address_gray/i_raddr_sync* && IS_SEQUENTIAL}] \ [get_property -min PERIOD $dest_clk] # In SDP mode REGCEB should not be connected. When inferring the BRAM the tools @@ -153,15 +153,15 @@ set_false_path -quiet \ # Ignore timing for debug signals to register map set_false_path -quiet \ -from [get_cells -quiet -hier *cdc_sync_stage2_reg* \ - -filter {name =~ *i_sync_src_request_id* && primitive_subgroup == flop}] \ - -to [get_cells -quiet -hier *up_rdata_reg* -filter {primitive_subgroup == flop}] + -filter {name =~ *i_sync_src_request_id* && IS_SEQUENTIAL}] \ + -to [get_cells -quiet -hier *up_rdata_reg* -filter {IS_SEQUENTIAL}] set_false_path -quiet \ -from [get_cells -quiet -hier *cdc_sync_stage2_reg* \ - -filter {name =~ *i_sync_dest_request_id* && primitive_subgroup == flop}] \ - -to [get_cells -quiet -hier *up_rdata_reg* -filter {primitive_subgroup == flop}] + -filter {name =~ *i_sync_dest_request_id* && IS_SEQUENTIAL}] \ + -to [get_cells -quiet -hier *up_rdata_reg* -filter {IS_SEQUENTIAL}] set_false_path -quiet \ - -from [get_cells -quiet -hier *id_reg* -filter {name =~ *i_request_arb* && primitive_subgroup == flop}] \ - -to [get_cells -quiet -hier *up_rdata_reg* -filter {primitive_subgroup == flop}] + -from [get_cells -quiet -hier *id_reg* -filter {name =~ *i_request_arb* && IS_SEQUENTIAL}] \ + -to [get_cells -quiet -hier *up_rdata_reg* -filter {IS_SEQUENTIAL}] set_false_path -quiet \ - -from [get_cells -quiet -hier *address_reg* -filter {name =~ *i_addr_gen* && primitive_subgroup == flop}] \ - -to [get_cells -quiet -hier *up_rdata_reg* -filter {primitive_subgroup == flop}] + -from [get_cells -quiet -hier *address_reg* -filter {name =~ *i_addr_gen* && IS_SEQUENTIAL}] \ + -to [get_cells -quiet -hier *up_rdata_reg* -filter {IS_SEQUENTIAL}] diff --git a/library/axi_dmac/axi_dmac_ip.tcl b/library/axi_dmac/axi_dmac_ip.tcl index d6a6668d0..c32d0434b 100644 --- a/library/axi_dmac/axi_dmac_ip.tcl +++ b/library/axi_dmac/axi_dmac_ip.tcl @@ -27,6 +27,7 @@ adi_ip_files axi_dmac [list \ "bd/bd.tcl" ] adi_ip_properties axi_dmac +adi_ip_infer_mm_interfaces axi_dmac adi_ip_ttcl axi_dmac "axi_dmac_constr.ttcl" adi_ip_bd axi_dmac "bd/bd.tcl" @@ -35,6 +36,9 @@ adi_ip_add_core_dependencies { \ analog.com:user:util_axis_fifo:1.0 \ } +set_property display_name "ADI AXI DMA Controller" [ipx::current_core] +set_property description "ADI AXI DMA Controller" [ipx::current_core] + adi_add_bus "s_axis" "slave" \ "xilinx.com:interface:axis_rtl:1.0" \ "xilinx.com:interface:axis:1.0" \ @@ -103,6 +107,13 @@ foreach p $dummy_axi_ports { adi_set_ports_dependency $p "0" } +set_property master_address_space_ref m_dest_axi \ + [ipx::get_bus_interfaces m_dest_axi \ + -of_objects [ipx::current_core]] +set_property master_address_space_ref m_src_axi \ + [ipx::get_bus_interfaces m_src_axi \ + -of_objects [ipx::current_core]] + adi_add_bus "fifo_wr" "slave" \ "analog.com:interface:fifo_wr_rtl:1.0" \ "analog.com:interface:fifo_wr:1.0" \ diff --git a/library/axi_dmac/axi_register_slice.v b/library/axi_dmac/axi_register_slice.v index d685b8db6..159f0d0fe 100644 --- a/library/axi_dmac/axi_register_slice.v +++ b/library/axi_dmac/axi_register_slice.v @@ -36,16 +36,16 @@ // *************************************************************************** module axi_register_slice ( - input clk, - input resetn, + input clk, + input resetn, - input s_axi_valid, - output s_axi_ready, - input [DATA_WIDTH-1:0] s_axi_data, + input s_axi_valid, + output s_axi_ready, + input [DATA_WIDTH-1:0] s_axi_data, - output m_axi_valid, - input m_axi_ready, - output [DATA_WIDTH-1:0] m_axi_data + output m_axi_valid, + input m_axi_ready, + output [DATA_WIDTH-1:0] m_axi_data ); parameter DATA_WIDTH = 32; @@ -79,19 +79,19 @@ assign fwd_valid_s = fwd_valid; assign fwd_data_s = fwd_data; always @(posedge clk) begin - if (~fwd_valid | m_axi_ready) - fwd_data <= bwd_data_s; + if (~fwd_valid | m_axi_ready) + fwd_data <= bwd_data_s; end always @(posedge clk) begin - if (resetn == 1'b0) begin - fwd_valid <= 1'b0; - end else begin - if (bwd_valid_s) - fwd_valid <= 1'b1; - else if (m_axi_ready) - fwd_valid <= 1'b0; - end + if (resetn == 1'b0) begin + fwd_valid <= 1'b0; + end else begin + if (bwd_valid_s) + fwd_valid <= 1'b1; + else if (m_axi_ready) + fwd_valid <= 1'b0; + end end end else begin @@ -111,19 +111,19 @@ assign bwd_data_s = bwd_ready ? s_axi_data : bwd_data; assign bwd_ready_s = bwd_ready; always @(posedge clk) begin - if (bwd_ready) - bwd_data <= s_axi_data; + if (bwd_ready) + bwd_data <= s_axi_data; end always @(posedge clk) begin - if (resetn == 1'b0) begin - bwd_ready <= 1'b1; - end else begin - if (fwd_ready_s) - bwd_ready <= 1'b1; - else if (s_axi_valid) - bwd_ready <= 1'b0; - end + if (resetn == 1'b0) begin + bwd_ready <= 1'b1; + end else begin + if (fwd_ready_s) + bwd_ready <= 1'b1; + else if (s_axi_valid) + bwd_ready <= 1'b0; + end end end else begin diff --git a/library/axi_dmac/data_mover.v b/library/axi_dmac/data_mover.v index 714e28cb2..1f1b9dc04 100644 --- a/library/axi_dmac/data_mover.v +++ b/library/axi_dmac/data_mover.v @@ -37,31 +37,31 @@ // *************************************************************************** module dmac_data_mover ( - input clk, - input resetn, + input clk, + input resetn, - input [ID_WIDTH-1:0] request_id, - output [ID_WIDTH-1:0] response_id, - input sync_id, - input eot, + input [ID_WIDTH-1:0] request_id, + output [ID_WIDTH-1:0] response_id, + input sync_id, + input eot, - input enable, - output reg enabled, + input enable, + output reg enabled, - output xfer_req, + output xfer_req, - output s_axi_ready, - input s_axi_valid, - input [DATA_WIDTH-1:0] s_axi_data, + output s_axi_ready, + input s_axi_valid, + input [DATA_WIDTH-1:0] s_axi_data, - input m_axi_ready, - output m_axi_valid, - output [DATA_WIDTH-1:0] m_axi_data, - output m_axi_last, + input m_axi_ready, + output m_axi_valid, + output [DATA_WIDTH-1:0] m_axi_data, + output m_axi_last, - input req_valid, - output req_ready, - input [BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length + input req_valid, + output req_ready, + input [BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length ); parameter ID_WIDTH = 3; @@ -104,73 +104,73 @@ assign last_load = s_axi_ready && s_axi_valid && last_eot && eot; assign req_ready = last_load || ~active; always @(posedge clk) begin - if (resetn == 1'b0) begin - enabled <= 1'b0; - end else begin - if (enable) begin - enabled <= 1'b1; - end else begin - if (DISABLE_WAIT_FOR_ID == 0) begin - // We are not allowed to just deassert valid, so wait until the - // current beat has been accepted - if (~s_axi_valid || m_axi_ready) - enabled <= 1'b0; - end else begin - // For memory mapped AXI busses we have to complete all pending - // burst requests before we can disable the data mover. - if (response_id == request_id) - enabled <= 1'b0; - end - end - end + if (resetn == 1'b0) begin + enabled <= 1'b0; + end else begin + if (enable) begin + enabled <= 1'b1; + end else begin + if (DISABLE_WAIT_FOR_ID == 0) begin + // We are not allowed to just deassert valid, so wait until the + // current beat has been accepted + if (~s_axi_valid || m_axi_ready) + enabled <= 1'b0; + end else begin + // For memory mapped AXI busses we have to complete all pending + // burst requests before we can disable the data mover. + if (response_id == request_id) + enabled <= 1'b0; + end + end + end end always @(posedge clk) begin - if (req_ready) begin - last_eot <= req_last_burst_length == 'h0; - last_non_eot <= 1'b0; - beat_counter <= 'h1; - end else if (s_axi_ready && s_axi_valid) begin - last_eot <= beat_counter == last_burst_length; - last_non_eot <= beat_counter == MAX_BEATS_PER_BURST - 1; - beat_counter <= beat_counter + 1; - end + if (req_ready) begin + last_eot <= req_last_burst_length == 'h0; + last_non_eot <= 1'b0; + beat_counter <= 'h1; + end else if (s_axi_ready && s_axi_valid) begin + last_eot <= beat_counter == last_burst_length; + last_non_eot <= beat_counter == MAX_BEATS_PER_BURST - 1; + beat_counter <= beat_counter + 1; + end end always @(posedge clk) begin - if (req_ready) - last_burst_length <= req_last_burst_length; + if (req_ready) + last_burst_length <= req_last_burst_length; end always @(posedge clk) begin - if (enabled == 1'b0 || resetn == 1'b0) begin - active <= 1'b0; - end else if (req_valid) begin - active <= 1'b1; - end else if (last_load) begin - active <= 1'b0; - end + if (enabled == 1'b0 || resetn == 1'b0) begin + active <= 1'b0; + end else if (req_valid) begin + active <= 1'b1; + end else if (last_load) begin + active <= 1'b0; + end end always @(*) begin - if ((s_axi_ready && s_axi_valid && last) || - (sync_id && pending_burst)) - id_next <= inc_id(id); - else - id_next <= id; + if ((s_axi_ready && s_axi_valid && last) || + (sync_id && pending_burst)) + id_next <= inc_id(id); + else + id_next <= id; end always @(posedge clk) begin - if (resetn == 1'b0) begin - id <= 'h0; - end else begin - id <= id_next; - end + if (resetn == 1'b0) begin + id <= 'h0; + end else begin + id <= id_next; + end end always @(posedge clk) begin - pending_burst <= id_next != request_id; + pending_burst <= id_next != request_id; end endmodule diff --git a/library/axi_dmac/dest_axi_mm.v b/library/axi_dmac/dest_axi_mm.v index ddf995c93..93f351e3f 100644 --- a/library/axi_dmac/dest_axi_mm.v +++ b/library/axi_dmac/dest_axi_mm.v @@ -37,60 +37,60 @@ // *************************************************************************** module dmac_dest_mm_axi ( - input m_axi_aclk, - input m_axi_aresetn, + input m_axi_aclk, + input m_axi_aresetn, - input req_valid, - output req_ready, - input [31:BYTES_PER_BEAT_WIDTH] req_address, - input [BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length, - input [BYTES_PER_BEAT_WIDTH-1:0] req_last_beat_bytes, + input req_valid, + output req_ready, + input [31:BYTES_PER_BEAT_WIDTH] req_address, + input [BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length, + input [BYTES_PER_BEAT_WIDTH-1:0] req_last_beat_bytes, - input enable, - output enabled, - input pause, - input sync_id, - output sync_id_ret, + input enable, + output enabled, + input pause, + input sync_id, + output sync_id_ret, - output response_valid, - input response_ready, - output [1:0] response_resp, - output response_resp_eot, + output response_valid, + input response_ready, + output [1:0] response_resp, + output response_resp_eot, - input [ID_WIDTH-1:0] request_id, - output [ID_WIDTH-1:0] response_id, + input [ID_WIDTH-1:0] request_id, + output [ID_WIDTH-1:0] response_id, - output [ID_WIDTH-1:0] data_id, - output [ID_WIDTH-1:0] address_id, - input data_eot, - input address_eot, - input response_eot, + output [ID_WIDTH-1:0] data_id, + output [ID_WIDTH-1:0] address_id, + input data_eot, + input address_eot, + input response_eot, - input fifo_valid, - output fifo_ready, - input [DMA_DATA_WIDTH-1:0] fifo_data, + input fifo_valid, + output fifo_ready, + input [DMA_DATA_WIDTH-1:0] fifo_data, - // Write address - input m_axi_awready, - output m_axi_awvalid, - output [31:0] m_axi_awaddr, - output [ 7:0] m_axi_awlen, - output [ 2:0] m_axi_awsize, - output [ 1:0] m_axi_awburst, - output [ 2:0] m_axi_awprot, - output [ 3:0] m_axi_awcache, + // Write address + input m_axi_awready, + output m_axi_awvalid, + output [31:0] m_axi_awaddr, + output [ 7:0] m_axi_awlen, + output [ 2:0] m_axi_awsize, + output [ 1:0] m_axi_awburst, + output [ 2:0] m_axi_awprot, + output [ 3:0] m_axi_awcache, - // Write data - output [DMA_DATA_WIDTH-1:0] m_axi_wdata, - output [(DMA_DATA_WIDTH/8)-1:0] m_axi_wstrb, - input m_axi_wready, - output m_axi_wvalid, - output m_axi_wlast, + // Write data + output [DMA_DATA_WIDTH-1:0] m_axi_wdata, + output [(DMA_DATA_WIDTH/8)-1:0] m_axi_wstrb, + input m_axi_wready, + output m_axi_wvalid, + output m_axi_wlast, - // Write response - input m_axi_bvalid, - input [ 1:0] m_axi_bresp, - output m_axi_bready + // Write response + input m_axi_bvalid, + input [ 1:0] m_axi_bresp, + output m_axi_bready ); parameter ID_WIDTH = 3; @@ -113,120 +113,120 @@ wire _fifo_ready; assign fifo_ready = _fifo_ready | ~enabled; splitter #( - .NUM_M(2) + .NUM_M(2) ) i_req_splitter ( - .clk(m_axi_aclk), - .resetn(m_axi_aresetn), - .s_valid(req_valid), - .s_ready(req_ready), - .m_valid({ - address_req_valid, - data_req_valid - }), - .m_ready({ - address_req_ready, - data_req_ready - }) + .clk(m_axi_aclk), + .resetn(m_axi_aresetn), + .s_valid(req_valid), + .s_ready(req_ready), + .m_valid({ + address_req_valid, + data_req_valid + }), + .m_ready({ + address_req_ready, + data_req_ready + }) ); dmac_address_generator #( - .ID_WIDTH(ID_WIDTH), - .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH), - .BYTES_PER_BEAT_WIDTH(BYTES_PER_BEAT_WIDTH), - .DMA_DATA_WIDTH(DMA_DATA_WIDTH) + .ID_WIDTH(ID_WIDTH), + .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH), + .BYTES_PER_BEAT_WIDTH(BYTES_PER_BEAT_WIDTH), + .DMA_DATA_WIDTH(DMA_DATA_WIDTH) ) i_addr_gen ( - .clk(m_axi_aclk), - .resetn(m_axi_aresetn), + .clk(m_axi_aclk), + .resetn(m_axi_aresetn), - .enable(enable), - .enabled(address_enabled), - .pause(pause), + .enable(enable), + .enabled(address_enabled), + .pause(pause), - .id(address_id), - .request_id(request_id), - .sync_id(sync_id), + .id(address_id), + .request_id(request_id), + .sync_id(sync_id), - .req_valid(address_req_valid), - .req_ready(address_req_ready), - .req_address(req_address), - .req_last_burst_length(req_last_burst_length), + .req_valid(address_req_valid), + .req_ready(address_req_ready), + .req_address(req_address), + .req_last_burst_length(req_last_burst_length), - .eot(address_eot), + .eot(address_eot), - .addr_ready(m_axi_awready), - .addr_valid(m_axi_awvalid), - .addr(m_axi_awaddr), - .len(m_axi_awlen), - .size(m_axi_awsize), - .burst(m_axi_awburst), - .prot(m_axi_awprot), - .cache(m_axi_awcache) + .addr_ready(m_axi_awready), + .addr_valid(m_axi_awvalid), + .addr(m_axi_awaddr), + .len(m_axi_awlen), + .size(m_axi_awsize), + .burst(m_axi_awburst), + .prot(m_axi_awprot), + .cache(m_axi_awcache) ); dmac_data_mover # ( - .ID_WIDTH(ID_WIDTH), - .DATA_WIDTH(DMA_DATA_WIDTH), - .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH) + .ID_WIDTH(ID_WIDTH), + .DATA_WIDTH(DMA_DATA_WIDTH), + .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH) ) i_data_mover ( - .clk(m_axi_aclk), - .resetn(m_axi_aresetn), + .clk(m_axi_aclk), + .resetn(m_axi_aresetn), - .enable(address_enabled), - .enabled(data_enabled), + .enable(address_enabled), + .enabled(data_enabled), - .xfer_req(), + .xfer_req(), - .request_id(address_id), - .response_id(data_id), - .sync_id(sync_id), - .eot(data_eot), + .request_id(address_id), + .response_id(data_id), + .sync_id(sync_id), + .eot(data_eot), - .req_valid(data_req_valid), - .req_ready(data_req_ready), - .req_last_burst_length(req_last_burst_length), + .req_valid(data_req_valid), + .req_ready(data_req_ready), + .req_last_burst_length(req_last_burst_length), - .s_axi_valid(fifo_valid), - .s_axi_ready(_fifo_ready), - .s_axi_data(fifo_data), - .m_axi_valid(m_axi_wvalid), - .m_axi_ready(m_axi_wready), - .m_axi_data(m_axi_wdata), - .m_axi_last(m_axi_wlast) + .s_axi_valid(fifo_valid), + .s_axi_ready(_fifo_ready), + .s_axi_data(fifo_data), + .m_axi_valid(m_axi_wvalid), + .m_axi_ready(m_axi_wready), + .m_axi_data(m_axi_wdata), + .m_axi_last(m_axi_wlast) ); always @(*) begin - if (data_eot & m_axi_wlast) begin - wstrb <= (1 << (req_last_beat_bytes + 1)) - 1; - end else begin - wstrb <= {(DMA_DATA_WIDTH/8){1'b1}}; - end + if (data_eot & m_axi_wlast) begin + wstrb <= (1 << (req_last_beat_bytes + 1)) - 1; + end else begin + wstrb <= {(DMA_DATA_WIDTH/8){1'b1}}; + end end assign m_axi_wstrb = wstrb; dmac_response_handler #( - .ID_WIDTH(ID_WIDTH) + .ID_WIDTH(ID_WIDTH) ) i_response_handler ( - .clk(m_axi_aclk), - .resetn(m_axi_aresetn), - .bvalid(m_axi_bvalid), - .bready(m_axi_bready), - .bresp(m_axi_bresp), + .clk(m_axi_aclk), + .resetn(m_axi_aresetn), + .bvalid(m_axi_bvalid), + .bready(m_axi_bready), + .bresp(m_axi_bresp), - .enable(data_enabled), - .enabled(enabled), + .enable(data_enabled), + .enabled(enabled), - .id(response_id), - .request_id(data_id), - .sync_id(sync_id), + .id(response_id), + .request_id(data_id), + .sync_id(sync_id), - .eot(response_eot), + .eot(response_eot), - .resp_valid(response_valid), - .resp_ready(response_ready), - .resp_resp(response_resp), - .resp_eot(response_resp_eot) + .resp_valid(response_valid), + .resp_ready(response_ready), + .resp_resp(response_resp), + .resp_eot(response_resp_eot) ); endmodule diff --git a/library/axi_dmac/dest_axi_stream.v b/library/axi_dmac/dest_axi_stream.v index 48c5dea55..3b3da3397 100644 --- a/library/axi_dmac/dest_axi_stream.v +++ b/library/axi_dmac/dest_axi_stream.v @@ -37,39 +37,39 @@ // *************************************************************************** module dmac_dest_axi_stream ( - input s_axis_aclk, - input s_axis_aresetn, + input s_axis_aclk, + input s_axis_aresetn, - input enable, - output enabled, - input sync_id, - output sync_id_ret, + input enable, + output enabled, + input sync_id, + output sync_id_ret, output xfer_req, - input [ID_WIDTH-1:0] request_id, - output [ID_WIDTH-1:0] response_id, - output [ID_WIDTH-1:0] data_id, - input data_eot, - input response_eot, + input [ID_WIDTH-1:0] request_id, + output [ID_WIDTH-1:0] response_id, + output [ID_WIDTH-1:0] data_id, + input data_eot, + input response_eot, - input m_axis_ready, - output m_axis_valid, - output [S_AXIS_DATA_WIDTH-1:0] m_axis_data, + input m_axis_ready, + output m_axis_valid, + output [S_AXIS_DATA_WIDTH-1:0] m_axis_data, output m_axis_last, - output fifo_ready, - input fifo_valid, - input [S_AXIS_DATA_WIDTH-1:0] fifo_data, + output fifo_ready, + input fifo_valid, + input [S_AXIS_DATA_WIDTH-1:0] fifo_data, - input req_valid, - output req_ready, - input [BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length, + input req_valid, + output req_ready, + input [BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length, input req_xlast, - output response_valid, - input response_ready, - output response_resp_eot, - output [1:0] response_resp + output response_valid, + input response_ready, + output response_resp_eot, + output [1:0] response_resp ); parameter ID_WIDTH = 3; @@ -97,56 +97,56 @@ end assign m_axis_last = (req_xlast_d == 1'b1) ? m_axis_last_s : 1'b0; dmac_data_mover # ( - .ID_WIDTH(ID_WIDTH), - .DATA_WIDTH(S_AXIS_DATA_WIDTH), - .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH), - .DISABLE_WAIT_FOR_ID(0), - .LAST(1) + .ID_WIDTH(ID_WIDTH), + .DATA_WIDTH(S_AXIS_DATA_WIDTH), + .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH), + .DISABLE_WAIT_FOR_ID(0), + .LAST(1) ) i_data_mover ( - .clk(s_axis_aclk), - .resetn(s_axis_aresetn), + .clk(s_axis_aclk), + .resetn(s_axis_aresetn), - .enable(enable), - .enabled(data_enabled), - .sync_id(sync_id), + .enable(enable), + .enabled(data_enabled), + .sync_id(sync_id), .xfer_req(xfer_req), - .request_id(request_id), - .response_id(data_id), - .eot(data_eot), + .request_id(request_id), + .response_id(data_id), + .eot(data_eot), - .req_valid(req_valid), - .req_ready(req_ready), - .req_last_burst_length(req_last_burst_length), + .req_valid(req_valid), + .req_ready(req_ready), + .req_last_burst_length(req_last_burst_length), - .m_axi_ready(m_axis_ready), - .m_axi_valid(m_axis_valid), - .m_axi_data(m_axis_data), + .m_axi_ready(m_axis_ready), + .m_axi_valid(m_axis_valid), + .m_axi_data(m_axis_data), .m_axi_last(m_axis_last_s), - .s_axi_ready(_fifo_ready), - .s_axi_valid(fifo_valid), - .s_axi_data(fifo_data) + .s_axi_ready(_fifo_ready), + .s_axi_valid(fifo_valid), + .s_axi_data(fifo_data) ); dmac_response_generator # ( - .ID_WIDTH(ID_WIDTH) + .ID_WIDTH(ID_WIDTH) ) i_response_generator ( - .clk(s_axis_aclk), - .resetn(s_axis_aresetn), + .clk(s_axis_aclk), + .resetn(s_axis_aresetn), - .enable(data_enabled), - .enabled(enabled), - .sync_id(sync_id), + .enable(data_enabled), + .enabled(enabled), + .sync_id(sync_id), - .request_id(data_id), - .response_id(response_id), + .request_id(data_id), + .response_id(response_id), - .eot(response_eot), + .eot(response_eot), - .resp_valid(response_valid), - .resp_ready(response_ready), - .resp_eot(response_resp_eot), - .resp_resp(response_resp) + .resp_valid(response_valid), + .resp_ready(response_ready), + .resp_eot(response_resp_eot), + .resp_resp(response_resp) ); assign fifo_ready = _fifo_ready | ~enabled; diff --git a/library/axi_dmac/dest_fifo_inf.v b/library/axi_dmac/dest_fifo_inf.v index 3e5c1d0eb..fccac5d7a 100644 --- a/library/axi_dmac/dest_fifo_inf.v +++ b/library/axi_dmac/dest_fifo_inf.v @@ -37,39 +37,39 @@ // *************************************************************************** module dmac_dest_fifo_inf ( - input clk, - input resetn, + input clk, + input resetn, - input enable, - output enabled, - input sync_id, - output sync_id_ret, + input enable, + output enabled, + input sync_id, + output sync_id_ret, - input [ID_WIDTH-1:0] request_id, - output [ID_WIDTH-1:0] response_id, - output [ID_WIDTH-1:0] data_id, - input data_eot, - input response_eot, + input [ID_WIDTH-1:0] request_id, + output [ID_WIDTH-1:0] response_id, + output [ID_WIDTH-1:0] data_id, + input data_eot, + input response_eot, - input en, - output [DATA_WIDTH-1:0] dout, - output valid, - output underflow, + input en, + output [DATA_WIDTH-1:0] dout, + output valid, + output underflow, output xfer_req, - output fifo_ready, - input fifo_valid, - input [DATA_WIDTH-1:0] fifo_data, + output fifo_ready, + input fifo_valid, + input [DATA_WIDTH-1:0] fifo_data, - input req_valid, - output req_ready, - input [BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length, + input req_valid, + output req_ready, + input [BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length, - output response_valid, - input response_ready, - output response_resp_eot, - output [1:0] response_resp + output response_valid, + input response_ready, + output response_resp_eot, + output [1:0] response_resp ); parameter ID_WIDTH = 3; @@ -88,11 +88,11 @@ wire data_valid; always @(posedge clk) begin - if (resetn == 1'b0) begin - en_d1 <= 1'b0; - end else begin - en_d1 <= en; - end + if (resetn == 1'b0) begin + en_d1 <= 1'b0; + end else begin + en_d1 <= en; + end end assign underflow = en_d1 & (~data_valid | ~enable); @@ -100,55 +100,55 @@ assign data_ready = en_d1 & (data_valid | ~enable); assign valid = en_d1 & data_valid & enable; dmac_data_mover # ( - .ID_WIDTH(ID_WIDTH), - .DATA_WIDTH(DATA_WIDTH), - .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH), - .DISABLE_WAIT_FOR_ID(0) + .ID_WIDTH(ID_WIDTH), + .DATA_WIDTH(DATA_WIDTH), + .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH), + .DISABLE_WAIT_FOR_ID(0) ) i_data_mover ( - .clk(clk), - .resetn(resetn), + .clk(clk), + .resetn(resetn), - .enable(enable), - .enabled(data_enabled), - .sync_id(sync_id), + .enable(enable), + .enabled(data_enabled), + .sync_id(sync_id), .xfer_req(xfer_req), - .request_id(request_id), - .response_id(data_id), - .eot(data_eot), - - .req_valid(req_valid), - .req_ready(req_ready), - .req_last_burst_length(req_last_burst_length), + .request_id(request_id), + .response_id(data_id), + .eot(data_eot), + + .req_valid(req_valid), + .req_ready(req_ready), + .req_last_burst_length(req_last_burst_length), - .s_axi_ready(_fifo_ready), - .s_axi_valid(fifo_valid), - .s_axi_data(fifo_data), - .m_axi_ready(data_ready), - .m_axi_valid(data_valid), - .m_axi_data(dout), - .m_axi_last() + .s_axi_ready(_fifo_ready), + .s_axi_valid(fifo_valid), + .s_axi_data(fifo_data), + .m_axi_ready(data_ready), + .m_axi_valid(data_valid), + .m_axi_data(dout), + .m_axi_last() ); dmac_response_generator # ( - .ID_WIDTH(ID_WIDTH) + .ID_WIDTH(ID_WIDTH) ) i_response_generator ( - .clk(clk), - .resetn(resetn), + .clk(clk), + .resetn(resetn), - .enable(data_enabled), - .enabled(enabled), - .sync_id(sync_id), + .enable(data_enabled), + .enabled(enabled), + .sync_id(sync_id), - .request_id(data_id), - .response_id(response_id), + .request_id(data_id), + .response_id(response_id), - .eot(response_eot), + .eot(response_eot), - .resp_valid(response_valid), - .resp_ready(response_ready), - .resp_eot(response_resp_eot), - .resp_resp(response_resp) + .resp_valid(response_valid), + .resp_ready(response_ready), + .resp_eot(response_resp_eot), + .resp_resp(response_resp) ); endmodule diff --git a/library/axi_dmac/request_arb.v b/library/axi_dmac/request_arb.v index 2e622403a..706d2cedc 100644 --- a/library/axi_dmac/request_arb.v +++ b/library/axi_dmac/request_arb.v @@ -37,107 +37,107 @@ // *************************************************************************** module dmac_request_arb ( - input req_aclk, - input req_aresetn, + input req_aclk, + input req_aresetn, - input req_valid, - output req_ready, - input [31:BYTES_PER_BEAT_WIDTH_DEST] req_dest_address, - input [31:BYTES_PER_BEAT_WIDTH_SRC] req_src_address, - input [DMA_LENGTH_WIDTH-1:0] req_length, + input req_valid, + output req_ready, + input [31:BYTES_PER_BEAT_WIDTH_DEST] req_dest_address, + input [31:BYTES_PER_BEAT_WIDTH_SRC] req_src_address, + input [DMA_LENGTH_WIDTH-1:0] req_length, input req_xlast, - input req_sync_transfer_start, + input req_sync_transfer_start, - output reg eot, + output reg eot, - input enable, - input pause, + input enable, + input pause, - // Master AXI interface - input m_dest_axi_aclk, - input m_dest_axi_aresetn, - input m_src_axi_aclk, - input m_src_axi_aresetn, + // Master AXI interface + input m_dest_axi_aclk, + input m_dest_axi_aresetn, + input m_src_axi_aclk, + input m_src_axi_aresetn, - // Write address - output [31:0] m_axi_awaddr, - output [ 7:0] m_axi_awlen, - output [ 2:0] m_axi_awsize, - output [ 1:0] m_axi_awburst, - output [ 2:0] m_axi_awprot, - output [ 3:0] m_axi_awcache, - output m_axi_awvalid, - input m_axi_awready, + // Write address + output [31:0] m_axi_awaddr, + output [ 7:0] m_axi_awlen, + output [ 2:0] m_axi_awsize, + output [ 1:0] m_axi_awburst, + output [ 2:0] m_axi_awprot, + output [ 3:0] m_axi_awcache, + output m_axi_awvalid, + input m_axi_awready, - // Write data - output [DMA_DATA_WIDTH_DEST-1:0] m_axi_wdata, - output [(DMA_DATA_WIDTH_DEST/8)-1:0] m_axi_wstrb, - input m_axi_wready, - output m_axi_wvalid, - output m_axi_wlast, + // Write data + output [DMA_DATA_WIDTH_DEST-1:0] m_axi_wdata, + output [(DMA_DATA_WIDTH_DEST/8)-1:0] m_axi_wstrb, + input m_axi_wready, + output m_axi_wvalid, + output m_axi_wlast, - // Write response - input m_axi_bvalid, - input [ 1:0] m_axi_bresp, - output m_axi_bready, + // Write response + input m_axi_bvalid, + input [ 1:0] m_axi_bresp, + output m_axi_bready, - // Read address - input m_axi_arready, - output m_axi_arvalid, - output [31:0] m_axi_araddr, - output [ 7:0] m_axi_arlen, - output [ 2:0] m_axi_arsize, - output [ 1:0] m_axi_arburst, - output [ 2:0] m_axi_arprot, - output [ 3:0] m_axi_arcache, + // Read address + input m_axi_arready, + output m_axi_arvalid, + output [31:0] m_axi_araddr, + output [ 7:0] m_axi_arlen, + output [ 2:0] m_axi_arsize, + output [ 1:0] m_axi_arburst, + output [ 2:0] m_axi_arprot, + output [ 3:0] m_axi_arcache, - // Read data and response - input [DMA_DATA_WIDTH_SRC-1:0] m_axi_rdata, - output m_axi_rready, - input m_axi_rvalid, - input [ 1:0] m_axi_rresp, + // Read data and response + input [DMA_DATA_WIDTH_SRC-1:0] m_axi_rdata, + output m_axi_rready, + input m_axi_rvalid, + input [ 1:0] m_axi_rresp, - // Slave streaming AXI interface - input s_axis_aclk, - output s_axis_ready, - input s_axis_valid, - input [DMA_DATA_WIDTH_SRC-1:0] s_axis_data, - input [0:0] s_axis_user, - output s_axis_xfer_req, + // Slave streaming AXI interface + input s_axis_aclk, + output s_axis_ready, + input s_axis_valid, + input [DMA_DATA_WIDTH_SRC-1:0] s_axis_data, + input [0:0] s_axis_user, + output s_axis_xfer_req, - // Master streaming AXI interface - input m_axis_aclk, - input m_axis_ready, - output m_axis_valid, - output [DMA_DATA_WIDTH_DEST-1:0] m_axis_data, + // Master streaming AXI interface + input m_axis_aclk, + input m_axis_ready, + output m_axis_valid, + output [DMA_DATA_WIDTH_DEST-1:0] m_axis_data, output m_axis_last, output m_axis_xfer_req, - // Input FIFO interface - input fifo_wr_clk, - input fifo_wr_en, - input [DMA_DATA_WIDTH_SRC-1:0] fifo_wr_din, - output fifo_wr_overflow, - input fifo_wr_sync, - output fifo_wr_xfer_req, + // Input FIFO interface + input fifo_wr_clk, + input fifo_wr_en, + input [DMA_DATA_WIDTH_SRC-1:0] fifo_wr_din, + output fifo_wr_overflow, + input fifo_wr_sync, + output fifo_wr_xfer_req, - // Input FIFO interface - input fifo_rd_clk, - input fifo_rd_en, - output fifo_rd_valid, - output [DMA_DATA_WIDTH_DEST-1:0] fifo_rd_dout, - output fifo_rd_underflow, + // Input FIFO interface + input fifo_rd_clk, + input fifo_rd_en, + output fifo_rd_valid, + output [DMA_DATA_WIDTH_DEST-1:0] fifo_rd_dout, + output fifo_rd_underflow, output fifo_rd_xfer_req, - output [ID_WIDTH-1:0] dbg_dest_request_id, - output [ID_WIDTH-1:0] dbg_dest_address_id, - output [ID_WIDTH-1:0] dbg_dest_data_id, - output [ID_WIDTH-1:0] dbg_dest_response_id, - output [ID_WIDTH-1:0] dbg_src_request_id, - output [ID_WIDTH-1:0] dbg_src_address_id, - output [ID_WIDTH-1:0] dbg_src_data_id, - output [ID_WIDTH-1:0] dbg_src_response_id, - output [7:0] dbg_status + output [ID_WIDTH-1:0] dbg_dest_request_id, + output [ID_WIDTH-1:0] dbg_dest_address_id, + output [ID_WIDTH-1:0] dbg_dest_data_id, + output [ID_WIDTH-1:0] dbg_dest_response_id, + output [ID_WIDTH-1:0] dbg_src_request_id, + output [ID_WIDTH-1:0] dbg_src_address_id, + output [ID_WIDTH-1:0] dbg_src_data_id, + output [ID_WIDTH-1:0] dbg_src_response_id, + output [7:0] dbg_status ); parameter DMA_DATA_WIDTH_SRC = 64; @@ -170,7 +170,7 @@ localparam DMA_ADDRESS_WIDTH_DEST = 32 - BYTES_PER_BEAT_WIDTH_DEST; localparam DMA_ADDRESS_WIDTH_SRC = 32 - BYTES_PER_BEAT_WIDTH_SRC; localparam DMA_DATA_WIDTH = DMA_DATA_WIDTH_SRC < DMA_DATA_WIDTH_DEST ? - DMA_DATA_WIDTH_DEST : DMA_DATA_WIDTH_SRC; + DMA_DATA_WIDTH_DEST : DMA_DATA_WIDTH_SRC; @@ -294,49 +294,49 @@ reg do_enable; // Enable src and dest if we are in sync always @(posedge req_aclk) begin - if (req_aresetn == 1'b0) begin - do_enable <= 1'b0; - end else begin - if (enable) begin - // First make sure we are fully disabled - if (~sync_id_ret_dest && ~sync_id_ret_src && - response_id == request_id && ~enabled_dest && ~enabled_src && - req_dest_empty && req_src_empty && fifo_empty) - do_enable <= 1'b1; - end else begin - do_enable <= 1'b0; - end - end + if (req_aresetn == 1'b0) begin + do_enable <= 1'b0; + end else begin + if (enable) begin + // First make sure we are fully disabled + if (~sync_id_ret_dest && ~sync_id_ret_src && + response_id == request_id && ~enabled_dest && ~enabled_src && + req_dest_empty && req_src_empty && fifo_empty) + do_enable <= 1'b1; + end else begin + do_enable <= 1'b0; + end + end end // Flag enabled once both src and dest are enabled always @(posedge req_aclk) begin - if (req_aresetn == 1'b0) begin - enabled <= 1'b0; - end else begin - if (do_enable == 1'b0) - enabled <= 1'b0; - else if (enabled_dest && enabled_src) - enabled <= 1'b1; - end + if (req_aresetn == 1'b0) begin + enabled <= 1'b0; + end else begin + if (do_enable == 1'b0) + enabled <= 1'b0; + else if (enabled_dest && enabled_src) + enabled <= 1'b1; + end end assign dbg_status = {do_enable, enabled, enabled_dest, enabled_src, fifo_empty, - sync_id, sync_id_ret_dest, sync_id_ret_src}; + sync_id, sync_id_ret_dest, sync_id_ret_src}; always @(posedge req_aclk) begin - eot_mem[request_id] <= request_eot; + eot_mem[request_id] <= request_eot; end always @(posedge req_aclk) begin - if (req_aresetn == 1'b0) begin - eot <= 1'b0; - end else begin - eot <= response_dest_valid & response_dest_ready & response_dest_resp_eot; - end + if (req_aresetn == 1'b0) begin + eot <= 1'b0; + end else begin + eot <= response_dest_valid & response_dest_ready & response_dest_resp_eot; + end end generate if (ASYNC_CLK_REQ_SRC) begin @@ -353,10 +353,10 @@ reg [2:0] src_reset_shift = 3'b111; assign src_resetn = ~src_reset_shift[2]; always @(negedge src_async_resetn_source or posedge src_clk) begin - if (src_async_resetn_source == 1'b0) - src_reset_shift <= 3'b111; - else - src_reset_shift <= {src_reset_shift[1:0], 1'b0}; + if (src_async_resetn_source == 1'b0) + src_reset_shift <= 3'b111; + else + src_reset_shift <= {src_reset_shift[1:0], 1'b0}; end end else begin @@ -376,10 +376,10 @@ reg [2:0] dest_reset_shift = 3'b111; assign dest_resetn = ~dest_reset_shift[2]; always @(negedge dest_async_resetn_source or posedge dest_clk) begin - if (dest_async_resetn_source == 1'b0) - dest_reset_shift <= 3'b111; - else - dest_reset_shift <= {dest_reset_shift[1:0], 1'b0}; + if (dest_async_resetn_source == 1'b0) + dest_reset_shift <= 3'b111; + else + dest_reset_shift <= {dest_reset_shift[1:0], 1'b0}; end end else begin @@ -400,62 +400,62 @@ assign dbg_dest_address_id = dest_address_id; assign dbg_dest_data_id = dest_data_id; dmac_dest_mm_axi #( - .ID_WIDTH(ID_WIDTH), - .DMA_DATA_WIDTH(DMA_DATA_WIDTH_DEST), - .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH_DEST), - .BYTES_PER_BEAT_WIDTH(BYTES_PER_BEAT_WIDTH_DEST) + .ID_WIDTH(ID_WIDTH), + .DMA_DATA_WIDTH(DMA_DATA_WIDTH_DEST), + .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH_DEST), + .BYTES_PER_BEAT_WIDTH(BYTES_PER_BEAT_WIDTH_DEST) ) i_dest_dma_mm ( - .m_axi_aclk(m_dest_axi_aclk), - .m_axi_aresetn(dest_resetn), + .m_axi_aclk(m_dest_axi_aclk), + .m_axi_aresetn(dest_resetn), - .enable(dest_enable), - .enabled(dest_enabled), - .pause(dest_pause), + .enable(dest_enable), + .enabled(dest_enabled), + .pause(dest_pause), - .req_valid(dest_req_valid), - .req_ready(dest_req_ready), - .req_address(dest_req_address), - .req_last_burst_length(dest_req_last_burst_length), - .req_last_beat_bytes(dest_req_last_beat_bytes), + .req_valid(dest_req_valid), + .req_ready(dest_req_ready), + .req_address(dest_req_address), + .req_last_burst_length(dest_req_last_burst_length), + .req_last_beat_bytes(dest_req_last_beat_bytes), - .response_valid(dest_response_valid), - .response_ready(dest_response_ready), - .response_resp(dest_response_resp), - .response_resp_eot(dest_response_resp_eot), + .response_valid(dest_response_valid), + .response_ready(dest_response_ready), + .response_resp(dest_response_resp), + .response_resp_eot(dest_response_resp_eot), - .request_id(dest_request_id), - .response_id(dest_response_id), - .sync_id(dest_sync_id), - .sync_id_ret(dest_sync_id_ret), + .request_id(dest_request_id), + .response_id(dest_response_id), + .sync_id(dest_sync_id), + .sync_id_ret(dest_sync_id_ret), - .data_id(dest_data_id), - .address_id(dest_address_id), + .data_id(dest_data_id), + .address_id(dest_address_id), - .address_eot(dest_address_eot), - .data_eot(dest_data_eot), - .response_eot(dest_response_eot), + .address_eot(dest_address_eot), + .data_eot(dest_data_eot), + .response_eot(dest_response_eot), - .fifo_valid(dest_valid), - .fifo_ready(dest_ready), - .fifo_data(dest_data), + .fifo_valid(dest_valid), + .fifo_ready(dest_ready), + .fifo_data(dest_data), - .m_axi_awready(m_axi_awready), - .m_axi_awvalid(m_axi_awvalid), - .m_axi_awaddr(m_axi_awaddr), - .m_axi_awlen(m_axi_awlen), - .m_axi_awsize(m_axi_awsize), - .m_axi_awburst(m_axi_awburst), - .m_axi_awprot(m_axi_awprot), - .m_axi_awcache(m_axi_awcache), - .m_axi_wready(m_axi_wready), - .m_axi_wvalid(m_axi_wvalid), - .m_axi_wdata(m_axi_wdata), - .m_axi_wstrb(m_axi_wstrb), - .m_axi_wlast(m_axi_wlast), + .m_axi_awready(m_axi_awready), + .m_axi_awvalid(m_axi_awvalid), + .m_axi_awaddr(m_axi_awaddr), + .m_axi_awlen(m_axi_awlen), + .m_axi_awsize(m_axi_awsize), + .m_axi_awburst(m_axi_awburst), + .m_axi_awprot(m_axi_awprot), + .m_axi_awcache(m_axi_awcache), + .m_axi_wready(m_axi_wready), + .m_axi_wvalid(m_axi_wvalid), + .m_axi_wdata(m_axi_wdata), + .m_axi_wstrb(m_axi_wstrb), + .m_axi_wlast(m_axi_wlast), - .m_axi_bvalid(m_axi_bvalid), - .m_axi_bresp(m_axi_bresp), - .m_axi_bready(m_axi_bready) + .m_axi_bvalid(m_axi_bvalid), + .m_axi_bresp(m_axi_bresp), + .m_axi_bready(m_axi_bready) ); end else begin @@ -490,43 +490,43 @@ assign dbg_dest_address_id = 'h00; assign dbg_dest_data_id = data_id; dmac_dest_axi_stream #( - .ID_WIDTH(ID_WIDTH), - .S_AXIS_DATA_WIDTH(DMA_DATA_WIDTH_DEST), - .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH_DEST) + .ID_WIDTH(ID_WIDTH), + .S_AXIS_DATA_WIDTH(DMA_DATA_WIDTH_DEST), + .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH_DEST) ) i_dest_dma_stream ( - .s_axis_aclk(m_axis_aclk), - .s_axis_aresetn(dest_resetn), + .s_axis_aclk(m_axis_aclk), + .s_axis_aresetn(dest_resetn), - .enable(dest_enable), - .enabled(dest_enabled), + .enable(dest_enable), + .enabled(dest_enabled), - .req_valid(dest_req_valid), - .req_ready(dest_req_ready), - .req_last_burst_length(dest_req_last_burst_length), + .req_valid(dest_req_valid), + .req_ready(dest_req_ready), + .req_last_burst_length(dest_req_last_burst_length), .req_xlast(dest_req_xlast), - .response_valid(dest_response_valid), - .response_ready(dest_response_ready), - .response_resp(dest_response_resp), - .response_resp_eot(dest_response_resp_eot), + .response_valid(dest_response_valid), + .response_ready(dest_response_ready), + .response_resp(dest_response_resp), + .response_resp_eot(dest_response_resp_eot), - .request_id(dest_request_id), - .response_id(dest_response_id), - .data_id(data_id), - .sync_id(dest_sync_id), - .sync_id_ret(dest_sync_id_ret), + .request_id(dest_request_id), + .response_id(dest_response_id), + .data_id(data_id), + .sync_id(dest_sync_id), + .sync_id_ret(dest_sync_id_ret), .xfer_req(m_axis_xfer_req), - .data_eot(data_eot), - .response_eot(response_eot), + .data_eot(data_eot), + .response_eot(response_eot), - .fifo_valid(dest_valid), - .fifo_ready(dest_ready), - .fifo_data(dest_data), + .fifo_valid(dest_valid), + .fifo_ready(dest_ready), + .fifo_data(dest_data), - .m_axis_valid(m_axis_valid), - .m_axis_ready(m_axis_ready), - .m_axis_data(m_axis_data), + .m_axis_valid(m_axis_valid), + .m_axis_ready(m_axis_ready), + .m_axis_data(m_axis_data), .m_axis_last(m_axis_last) ); @@ -552,42 +552,42 @@ assign dbg_dest_address_id = 'h00; assign dbg_dest_data_id = data_id; dmac_dest_fifo_inf #( - .ID_WIDTH(ID_WIDTH), - .DATA_WIDTH(DMA_DATA_WIDTH_DEST), - .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH_DEST) + .ID_WIDTH(ID_WIDTH), + .DATA_WIDTH(DMA_DATA_WIDTH_DEST), + .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH_DEST) ) i_dest_dma_fifo ( - .clk(fifo_rd_clk), - .resetn(dest_resetn), + .clk(fifo_rd_clk), + .resetn(dest_resetn), - .enable(dest_enable), - .enabled(dest_enabled), + .enable(dest_enable), + .enabled(dest_enabled), - .req_valid(dest_req_valid), - .req_ready(dest_req_ready), - .req_last_burst_length(dest_req_last_burst_length), + .req_valid(dest_req_valid), + .req_ready(dest_req_ready), + .req_last_burst_length(dest_req_last_burst_length), - .response_valid(dest_response_valid), - .response_ready(dest_response_ready), - .response_resp(dest_response_resp), - .response_resp_eot(dest_response_resp_eot), + .response_valid(dest_response_valid), + .response_ready(dest_response_ready), + .response_resp(dest_response_resp), + .response_resp_eot(dest_response_resp_eot), - .request_id(dest_request_id), - .response_id(dest_response_id), - .data_id(data_id), - .sync_id(dest_sync_id), - .sync_id_ret(dest_sync_id_ret), + .request_id(dest_request_id), + .response_id(dest_response_id), + .data_id(data_id), + .sync_id(dest_sync_id), + .sync_id_ret(dest_sync_id_ret), - .data_eot(data_eot), - .response_eot(response_eot), + .data_eot(data_eot), + .response_eot(response_eot), - .fifo_valid(dest_valid), - .fifo_ready(dest_ready), - .fifo_data(dest_data), + .fifo_valid(dest_valid), + .fifo_ready(dest_ready), + .fifo_data(dest_data), - .en(fifo_rd_en), - .valid(fifo_rd_valid), - .dout(fifo_rd_dout), - .underflow(fifo_rd_underflow), + .en(fifo_rd_en), + .valid(fifo_rd_valid), + .dout(fifo_rd_dout), + .underflow(fifo_rd_underflow), .xfer_req(fifo_rd_xfer_req) ); @@ -613,54 +613,54 @@ assign dbg_src_address_id = src_address_id; assign dbg_src_data_id = src_data_id; dmac_src_mm_axi #( - .ID_WIDTH(ID_WIDTH), - .DMA_DATA_WIDTH(DMA_DATA_WIDTH_SRC), - .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH_SRC), - .BYTES_PER_BEAT_WIDTH(BYTES_PER_BEAT_WIDTH_SRC) + .ID_WIDTH(ID_WIDTH), + .DMA_DATA_WIDTH(DMA_DATA_WIDTH_SRC), + .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH_SRC), + .BYTES_PER_BEAT_WIDTH(BYTES_PER_BEAT_WIDTH_SRC) ) i_src_dma_mm ( - .m_axi_aclk(m_src_axi_aclk), - .m_axi_aresetn(src_resetn), + .m_axi_aclk(m_src_axi_aclk), + .m_axi_aresetn(src_resetn), - .pause(src_pause), - .enable(src_enable), - .enabled(src_enabled), - .sync_id(src_sync_id), - .sync_id_ret(src_sync_id_ret), + .pause(src_pause), + .enable(src_enable), + .enabled(src_enabled), + .sync_id(src_sync_id), + .sync_id_ret(src_sync_id_ret), - .req_valid(src_req_valid), - .req_ready(src_req_ready), - .req_address(src_req_address), - .req_last_burst_length(src_req_last_burst_length), + .req_valid(src_req_valid), + .req_ready(src_req_ready), + .req_address(src_req_address), + .req_last_burst_length(src_req_last_burst_length), - .response_valid(src_response_valid), - .response_ready(src_response_ready), - .response_resp(src_response_resp), + .response_valid(src_response_valid), + .response_ready(src_response_ready), + .response_resp(src_response_resp), - .request_id(src_request_id), - .response_id(src_response_id), - .address_id(src_address_id), - .data_id(src_data_id), + .request_id(src_request_id), + .response_id(src_response_id), + .address_id(src_address_id), + .data_id(src_data_id), - .address_eot(src_address_eot), - .data_eot(src_data_eot), + .address_eot(src_address_eot), + .data_eot(src_data_eot), - .fifo_valid(src_valid), - .fifo_ready(src_ready), - .fifo_data(src_data), + .fifo_valid(src_valid), + .fifo_ready(src_ready), + .fifo_data(src_data), - .m_axi_arready(m_axi_arready), - .m_axi_arvalid(m_axi_arvalid), - .m_axi_araddr(m_axi_araddr), - .m_axi_arlen(m_axi_arlen), - .m_axi_arsize(m_axi_arsize), - .m_axi_arburst(m_axi_arburst), - .m_axi_arprot(m_axi_arprot), - .m_axi_arcache(m_axi_arcache), + .m_axi_arready(m_axi_arready), + .m_axi_arvalid(m_axi_arvalid), + .m_axi_araddr(m_axi_araddr), + .m_axi_arlen(m_axi_arlen), + .m_axi_arsize(m_axi_arsize), + .m_axi_arburst(m_axi_arburst), + .m_axi_arprot(m_axi_arprot), + .m_axi_arcache(m_axi_arcache), - .m_axi_rready(m_axi_rready), - .m_axi_rvalid(m_axi_rvalid), - .m_axi_rdata(m_axi_rdata), - .m_axi_rresp(m_axi_rresp) + .m_axi_rready(m_axi_rready), + .m_axi_rvalid(m_axi_rvalid), + .m_axi_rdata(m_axi_rdata), + .m_axi_rresp(m_axi_rresp) ); end else begin @@ -690,37 +690,37 @@ assign src_response_valid = 1'b0; assign src_response_resp = 2'b0; dmac_src_axi_stream #( - .ID_WIDTH(ID_WIDTH), - .S_AXIS_DATA_WIDTH(DMA_DATA_WIDTH_SRC), - .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH_SRC) + .ID_WIDTH(ID_WIDTH), + .S_AXIS_DATA_WIDTH(DMA_DATA_WIDTH_SRC), + .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH_SRC) ) i_src_dma_stream ( - .s_axis_aclk(s_axis_aclk), - .s_axis_aresetn(src_resetn), + .s_axis_aclk(s_axis_aclk), + .s_axis_aresetn(src_resetn), - .enable(src_enable), - .enabled(src_enabled), - .sync_id(src_sync_id), - .sync_id_ret(src_sync_id_ret), + .enable(src_enable), + .enabled(src_enabled), + .sync_id(src_sync_id), + .sync_id_ret(src_sync_id_ret), - .req_valid(src_req_valid), - .req_ready(src_req_ready), - .req_last_burst_length(src_req_last_burst_length), - .req_sync_transfer_start(src_req_sync_transfer_start), + .req_valid(src_req_valid), + .req_ready(src_req_ready), + .req_last_burst_length(src_req_last_burst_length), + .req_sync_transfer_start(src_req_sync_transfer_start), - .request_id(src_request_id), - .response_id(src_response_id), + .request_id(src_request_id), + .response_id(src_response_id), - .eot(src_eot), + .eot(src_eot), - .fifo_valid(src_valid), - .fifo_ready(src_ready), - .fifo_data(src_data), + .fifo_valid(src_valid), + .fifo_ready(src_ready), + .fifo_data(src_data), - .s_axis_valid(s_axis_valid), - .s_axis_ready(s_axis_ready), - .s_axis_data(s_axis_data), - .s_axis_user(s_axis_user), - .s_axis_xfer_req(s_axis_xfer_req) + .s_axis_valid(s_axis_valid), + .s_axis_ready(s_axis_ready), + .s_axis_data(s_axis_data), + .s_axis_user(s_axis_user), + .s_axis_xfer_req(s_axis_xfer_req) ); end else begin @@ -744,37 +744,37 @@ assign src_response_valid = 1'b0; assign src_response_resp = 2'b0; dmac_src_fifo_inf #( - .ID_WIDTH(ID_WIDTH), - .DATA_WIDTH(DMA_DATA_WIDTH_SRC), - .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH_SRC) + .ID_WIDTH(ID_WIDTH), + .DATA_WIDTH(DMA_DATA_WIDTH_SRC), + .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH_SRC) ) i_src_dma_fifo ( - .clk(fifo_wr_clk), - .resetn(src_resetn), + .clk(fifo_wr_clk), + .resetn(src_resetn), - .enable(src_enable), - .enabled(src_enabled), - .sync_id(src_sync_id), - .sync_id_ret(src_sync_id_ret), + .enable(src_enable), + .enabled(src_enabled), + .sync_id(src_sync_id), + .sync_id_ret(src_sync_id_ret), - .req_valid(src_req_valid), - .req_ready(src_req_ready), - .req_last_burst_length(src_req_last_burst_length), - .req_sync_transfer_start(src_req_sync_transfer_start), + .req_valid(src_req_valid), + .req_ready(src_req_ready), + .req_last_burst_length(src_req_last_burst_length), + .req_sync_transfer_start(src_req_sync_transfer_start), - .request_id(src_request_id), - .response_id(src_response_id), + .request_id(src_request_id), + .response_id(src_response_id), - .eot(src_eot), + .eot(src_eot), - .fifo_valid(src_valid), - .fifo_ready(src_ready), - .fifo_data(src_data), + .fifo_valid(src_valid), + .fifo_ready(src_ready), + .fifo_data(src_data), - .en(fifo_wr_en), - .din(fifo_wr_din), - .overflow(fifo_wr_overflow), - .sync(fifo_wr_sync), - .xfer_req(fifo_wr_xfer_req) + .en(fifo_wr_en), + .din(fifo_wr_din), + .overflow(fifo_wr_overflow), + .sync(fifo_wr_sync), + .xfer_req(fifo_wr_xfer_req) ); end else begin @@ -785,97 +785,97 @@ assign fifo_wr_xfer_req = 1'b0; end endgenerate sync_bits #( - .NUM_OF_BITS(ID_WIDTH), - .ASYNC_CLK(ASYNC_CLK_REQ_SRC) + .NUM_OF_BITS(ID_WIDTH), + .ASYNC_CLK(ASYNC_CLK_REQ_SRC) ) i_sync_src_request_id ( - .out_clk(src_clk), - .out_resetn(src_resetn), - .in(request_id), - .out(src_request_id) + .out_clk(src_clk), + .out_resetn(src_resetn), + .in(request_id), + .out(src_request_id) ); sync_bits #( - .NUM_OF_BITS(ID_WIDTH), - .ASYNC_CLK(ASYNC_CLK_SRC_DEST) + .NUM_OF_BITS(ID_WIDTH), + .ASYNC_CLK(ASYNC_CLK_SRC_DEST) ) i_sync_dest_request_id ( - .out_clk(dest_clk), - .out_resetn(dest_resetn), - .in(src_response_id), - .out(dest_request_id) + .out_clk(dest_clk), + .out_resetn(dest_resetn), + .in(src_response_id), + .out(dest_request_id) ); sync_bits #( - .NUM_OF_BITS(ID_WIDTH), - .ASYNC_CLK(ASYNC_CLK_DEST_REQ) + .NUM_OF_BITS(ID_WIDTH), + .ASYNC_CLK(ASYNC_CLK_DEST_REQ) ) i_sync_req_response_id ( - .out_clk(req_aclk), - .out_resetn(req_aresetn), - .in(dest_response_id), - .out(response_id) + .out_clk(req_aclk), + .out_resetn(req_aresetn), + .in(dest_response_id), + .out(response_id) ); axi_register_slice #( - .DATA_WIDTH(DMA_DATA_WIDTH_SRC), - .FORWARD_REGISTERED(AXI_SLICE_SRC), - .BACKWARD_REGISTERED(AXI_SLICE_SRC) + .DATA_WIDTH(DMA_DATA_WIDTH_SRC), + .FORWARD_REGISTERED(AXI_SLICE_SRC), + .BACKWARD_REGISTERED(AXI_SLICE_SRC) ) i_src_slice ( - .clk(src_clk), - .resetn(src_resetn), - .s_axi_valid(src_valid), - .s_axi_ready(src_ready), - .s_axi_data(src_data), - .m_axi_valid(src_fifo_valid), - .m_axi_ready(src_fifo_ready), - .m_axi_data(src_fifo_data) + .clk(src_clk), + .resetn(src_resetn), + .s_axi_valid(src_valid), + .s_axi_ready(src_ready), + .s_axi_data(src_data), + .m_axi_valid(src_fifo_valid), + .m_axi_ready(src_fifo_ready), + .m_axi_data(src_fifo_data) ); util_axis_resize #( - .SLAVE_DATA_WIDTH(DMA_DATA_WIDTH_SRC), - .MASTER_DATA_WIDTH(DMA_DATA_WIDTH) + .SLAVE_DATA_WIDTH(DMA_DATA_WIDTH_SRC), + .MASTER_DATA_WIDTH(DMA_DATA_WIDTH) ) i_src_repack ( - .clk(src_clk), - .resetn(src_resetn & src_enable), - .s_valid(src_fifo_valid), - .s_ready(src_fifo_ready), - .s_data(src_fifo_data), - .m_valid(src_fifo_repacked_valid), - .m_ready(src_fifo_repacked_ready), - .m_data(src_fifo_repacked_data) + .clk(src_clk), + .resetn(src_resetn & src_enable), + .s_valid(src_fifo_valid), + .s_ready(src_fifo_ready), + .s_data(src_fifo_data), + .m_valid(src_fifo_repacked_valid), + .m_ready(src_fifo_repacked_ready), + .m_data(src_fifo_repacked_data) ); util_axis_fifo #( - .DATA_WIDTH(DMA_DATA_WIDTH), - .ADDRESS_WIDTH($clog2(MAX_BYTES_PER_BURST / (DMA_DATA_WIDTH / 8) * FIFO_SIZE)), - .ASYNC_CLK(ASYNC_CLK_SRC_DEST) + .DATA_WIDTH(DMA_DATA_WIDTH), + .ADDRESS_WIDTH($clog2(MAX_BYTES_PER_BURST / (DMA_DATA_WIDTH / 8) * FIFO_SIZE)), + .ASYNC_CLK(ASYNC_CLK_SRC_DEST) ) i_fifo ( - .s_axis_aclk(src_clk), - .s_axis_aresetn(src_resetn), - .s_axis_valid(src_fifo_repacked_valid), - .s_axis_ready(src_fifo_repacked_ready), - .s_axis_data(src_fifo_repacked_data), - .s_axis_empty(src_fifo_empty), - .s_axis_room(), + .s_axis_aclk(src_clk), + .s_axis_aresetn(src_resetn), + .s_axis_valid(src_fifo_repacked_valid), + .s_axis_ready(src_fifo_repacked_ready), + .s_axis_data(src_fifo_repacked_data), + .s_axis_empty(src_fifo_empty), + .s_axis_room(), - .m_axis_aclk(dest_clk), - .m_axis_aresetn(dest_resetn), - .m_axis_valid(dest_fifo_valid), - .m_axis_ready(dest_fifo_ready), - .m_axis_data(dest_fifo_data), - .m_axis_level() + .m_axis_aclk(dest_clk), + .m_axis_aresetn(dest_resetn), + .m_axis_valid(dest_fifo_valid), + .m_axis_ready(dest_fifo_ready), + .m_axis_data(dest_fifo_data), + .m_axis_level() ); util_axis_resize #( - .SLAVE_DATA_WIDTH(DMA_DATA_WIDTH), - .MASTER_DATA_WIDTH(DMA_DATA_WIDTH_DEST) + .SLAVE_DATA_WIDTH(DMA_DATA_WIDTH), + .MASTER_DATA_WIDTH(DMA_DATA_WIDTH_DEST) ) i_dest_repack ( - .clk(dest_clk), - .resetn(dest_resetn & dest_enable), - .s_valid(dest_fifo_valid), - .s_ready(dest_fifo_ready), - .s_data(dest_fifo_data), - .m_valid(dest_fifo_repacked_valid), - .m_ready(dest_fifo_repacked_ready), - .m_data(dest_fifo_repacked_data) + .clk(dest_clk), + .resetn(dest_resetn & dest_enable), + .s_valid(dest_fifo_valid), + .s_ready(dest_fifo_ready), + .s_data(dest_fifo_data), + .m_valid(dest_fifo_repacked_valid), + .m_ready(dest_fifo_repacked_ready), + .m_data(dest_fifo_repacked_data) ); wire _dest_valid; @@ -883,32 +883,32 @@ wire _dest_ready; wire [DMA_DATA_WIDTH_DEST-1:0] _dest_data; axi_register_slice #( - .DATA_WIDTH(DMA_DATA_WIDTH_DEST), - .FORWARD_REGISTERED(AXI_SLICE_DEST) + .DATA_WIDTH(DMA_DATA_WIDTH_DEST), + .FORWARD_REGISTERED(AXI_SLICE_DEST) ) i_dest_slice2 ( - .clk(dest_clk), - .resetn(dest_resetn), - .s_axi_valid(dest_fifo_repacked_valid), - .s_axi_ready(dest_fifo_repacked_ready), - .s_axi_data(dest_fifo_repacked_data), - .m_axi_valid(_dest_valid), - .m_axi_ready(_dest_ready), - .m_axi_data(_dest_data) + .clk(dest_clk), + .resetn(dest_resetn), + .s_axi_valid(dest_fifo_repacked_valid), + .s_axi_ready(dest_fifo_repacked_ready), + .s_axi_data(dest_fifo_repacked_data), + .m_axi_valid(_dest_valid), + .m_axi_ready(_dest_ready), + .m_axi_data(_dest_data) ); axi_register_slice #( - .DATA_WIDTH(DMA_DATA_WIDTH_DEST), - .FORWARD_REGISTERED(AXI_SLICE_DEST), - .BACKWARD_REGISTERED(AXI_SLICE_DEST) + .DATA_WIDTH(DMA_DATA_WIDTH_DEST), + .FORWARD_REGISTERED(AXI_SLICE_DEST), + .BACKWARD_REGISTERED(AXI_SLICE_DEST) ) i_dest_slice ( - .clk(dest_clk), - .resetn(dest_resetn), - .s_axi_valid(_dest_valid), - .s_axi_ready(_dest_ready), - .s_axi_data(_dest_data), - .m_axi_valid(dest_valid), - .m_axi_ready(dest_ready), - .m_axi_data(dest_data) + .clk(dest_clk), + .resetn(dest_resetn), + .s_axi_valid(_dest_valid), + .s_axi_ready(_dest_ready), + .s_axi_data(_dest_data), + .m_axi_valid(dest_valid), + .m_axi_ready(dest_ready), + .m_axi_data(dest_data) ); @@ -918,198 +918,198 @@ wire _req_ready; always @(posedge req_aclk) begin - if (req_aresetn == 1'b0) begin - _req_valid <= 1'b0; - end else begin - if (_req_valid == 1'b1 && _req_ready == 1'b1) begin - _req_valid <= 1'b0; - end else if (req_valid == 1'b1 && enabled == 1'b1) begin - _req_valid <= 1'b1; - end - end + if (req_aresetn == 1'b0) begin + _req_valid <= 1'b0; + end else begin + if (_req_valid == 1'b1 && _req_ready == 1'b1) begin + _req_valid <= 1'b0; + end else if (req_valid == 1'b1 && enabled == 1'b1) begin + _req_valid <= 1'b1; + end + end end assign req_ready = _req_ready & _req_valid & enable; splitter #( - .NUM_M(3) + .NUM_M(3) ) i_req_splitter ( - .clk(req_aclk), - .resetn(req_aresetn), - .s_valid(_req_valid), - .s_ready(_req_ready), - .m_valid({ - req_gen_valid, - req_dest_valid, - req_src_valid - }), - .m_ready({ - req_gen_ready, - req_dest_ready, - req_src_ready - }) + .clk(req_aclk), + .resetn(req_aresetn), + .s_valid(_req_valid), + .s_ready(_req_ready), + .m_valid({ + req_gen_valid, + req_dest_valid, + req_src_valid + }), + .m_ready({ + req_gen_ready, + req_dest_ready, + req_src_ready + }) ); util_axis_fifo #( - .DATA_WIDTH(DMA_ADDRESS_WIDTH_DEST + BEATS_PER_BURST_WIDTH_DEST + BYTES_PER_BEAT_WIDTH_DEST + 1), - .ADDRESS_WIDTH(0), - .ASYNC_CLK(ASYNC_CLK_DEST_REQ) + .DATA_WIDTH(DMA_ADDRESS_WIDTH_DEST + BEATS_PER_BURST_WIDTH_DEST + BYTES_PER_BEAT_WIDTH_DEST + 1), + .ADDRESS_WIDTH(0), + .ASYNC_CLK(ASYNC_CLK_DEST_REQ) ) i_dest_req_fifo ( - .s_axis_aclk(req_aclk), - .s_axis_aresetn(req_aresetn), - .s_axis_valid(req_dest_valid), - .s_axis_ready(req_dest_ready), - .s_axis_empty(req_dest_empty), - .s_axis_data({ - req_dest_address, - req_length[BYTES_PER_BURST_WIDTH-1:BYTES_PER_BEAT_WIDTH_DEST], - req_length[BYTES_PER_BEAT_WIDTH_DEST-1:0], + .s_axis_aclk(req_aclk), + .s_axis_aresetn(req_aresetn), + .s_axis_valid(req_dest_valid), + .s_axis_ready(req_dest_ready), + .s_axis_empty(req_dest_empty), + .s_axis_data({ + req_dest_address, + req_length[BYTES_PER_BURST_WIDTH-1:BYTES_PER_BEAT_WIDTH_DEST], + req_length[BYTES_PER_BEAT_WIDTH_DEST-1:0], req_xlast - }), - .s_axis_room(), + }), + .s_axis_room(), - .m_axis_aclk(dest_clk), - .m_axis_aresetn(dest_resetn), - .m_axis_valid(dest_req_valid), - .m_axis_ready(dest_req_ready), - .m_axis_data({ - dest_req_address, - dest_req_last_burst_length, - dest_req_last_beat_bytes, + .m_axis_aclk(dest_clk), + .m_axis_aresetn(dest_resetn), + .m_axis_valid(dest_req_valid), + .m_axis_ready(dest_req_ready), + .m_axis_data({ + dest_req_address, + dest_req_last_burst_length, + dest_req_last_beat_bytes, dest_req_xlast - }), - .m_axis_level() + }), + .m_axis_level() ); util_axis_fifo #( - .DATA_WIDTH(DMA_ADDRESS_WIDTH_SRC + BEATS_PER_BURST_WIDTH_SRC + 1), - .ADDRESS_WIDTH(0), - .ASYNC_CLK(ASYNC_CLK_REQ_SRC) + .DATA_WIDTH(DMA_ADDRESS_WIDTH_SRC + BEATS_PER_BURST_WIDTH_SRC + 1), + .ADDRESS_WIDTH(0), + .ASYNC_CLK(ASYNC_CLK_REQ_SRC) ) i_src_req_fifo ( - .s_axis_aclk(req_aclk), - .s_axis_aresetn(req_aresetn), - .s_axis_valid(req_src_valid), - .s_axis_ready(req_src_ready), - .s_axis_empty(req_src_empty), - .s_axis_data({ - req_src_address, - req_length[BYTES_PER_BURST_WIDTH-1:BYTES_PER_BEAT_WIDTH_SRC], - req_sync_transfer_start - }), - .s_axis_room(), + .s_axis_aclk(req_aclk), + .s_axis_aresetn(req_aresetn), + .s_axis_valid(req_src_valid), + .s_axis_ready(req_src_ready), + .s_axis_empty(req_src_empty), + .s_axis_data({ + req_src_address, + req_length[BYTES_PER_BURST_WIDTH-1:BYTES_PER_BEAT_WIDTH_SRC], + req_sync_transfer_start + }), + .s_axis_room(), - .m_axis_aclk(src_clk), - .m_axis_aresetn(src_resetn), - .m_axis_valid(src_req_valid), - .m_axis_ready(src_req_ready), - .m_axis_data({ - src_req_address, - src_req_last_burst_length, - src_req_sync_transfer_start - }), - .m_axis_level() + .m_axis_aclk(src_clk), + .m_axis_aresetn(src_resetn), + .m_axis_valid(src_req_valid), + .m_axis_ready(src_req_ready), + .m_axis_data({ + src_req_address, + src_req_last_burst_length, + src_req_sync_transfer_start + }), + .m_axis_level() ); util_axis_fifo #( - .DATA_WIDTH(1), - .ADDRESS_WIDTH(0), - .ASYNC_CLK(ASYNC_CLK_DEST_REQ) + .DATA_WIDTH(1), + .ADDRESS_WIDTH(0), + .ASYNC_CLK(ASYNC_CLK_DEST_REQ) ) i_dest_response_fifo ( - .s_axis_aclk(dest_clk), - .s_axis_aresetn(dest_resetn), - .s_axis_valid(dest_response_valid), - .s_axis_ready(dest_response_ready), - .s_axis_empty(dest_response_empty), - .s_axis_data(dest_response_resp_eot), - .s_axis_room(), + .s_axis_aclk(dest_clk), + .s_axis_aresetn(dest_resetn), + .s_axis_valid(dest_response_valid), + .s_axis_ready(dest_response_ready), + .s_axis_empty(dest_response_empty), + .s_axis_data(dest_response_resp_eot), + .s_axis_room(), - .m_axis_aclk(req_aclk), - .m_axis_aresetn(req_aresetn), - .m_axis_valid(response_dest_valid), - .m_axis_ready(response_dest_ready), - .m_axis_data(response_dest_resp_eot), - .m_axis_level() + .m_axis_aclk(req_aclk), + .m_axis_aresetn(req_aresetn), + .m_axis_valid(response_dest_valid), + .m_axis_ready(response_dest_ready), + .m_axis_data(response_dest_resp_eot), + .m_axis_level() ); /* Unused for now util_axis_fifo #( - .DATA_WIDTH(2), - .ADDRESS_WIDTH(0), - .ASYNC_CLK(ASYNC_CLK_REQ_SRC) + .DATA_WIDTH(2), + .ADDRESS_WIDTH(0), + .ASYNC_CLK(ASYNC_CLK_REQ_SRC) ) i_src_response_fifo ( - .s_axis_aclk(src_clk), - .s_axis_aresetn(src_resetn), - .s_axis_valid(src_response_valid), - .s_axis_ready(src_response_ready), - .s_axis_empty(src_response_empty), - .s_axis_data(src_response_resp), - .m_axis_aclk(req_aclk), - .m_axis_aresetn(req_aresetn), - .m_axis_valid(response_src_valid), - .m_axis_ready(response_src_ready), - .m_axis_data(response_src_resp) + .s_axis_aclk(src_clk), + .s_axis_aresetn(src_resetn), + .s_axis_valid(src_response_valid), + .s_axis_ready(src_response_ready), + .s_axis_empty(src_response_empty), + .s_axis_data(src_response_resp), + .m_axis_aclk(req_aclk), + .m_axis_aresetn(req_aresetn), + .m_axis_valid(response_src_valid), + .m_axis_ready(response_src_ready), + .m_axis_data(response_src_resp) );*/ assign src_response_empty = 1'b1; assign src_response_ready = 1'b1; dmac_request_generator #( - .ID_WIDTH(ID_WIDTH), - .BURSTS_PER_TRANSFER_WIDTH(BURSTS_PER_TRANSFER_WIDTH) + .ID_WIDTH(ID_WIDTH), + .BURSTS_PER_TRANSFER_WIDTH(BURSTS_PER_TRANSFER_WIDTH) ) i_req_gen ( - .req_aclk(req_aclk), - .req_aresetn(req_aresetn), + .req_aclk(req_aclk), + .req_aresetn(req_aresetn), - .request_id(request_id), - .response_id(response_id), + .request_id(request_id), + .response_id(response_id), - .req_valid(req_gen_valid), - .req_ready(req_gen_ready), - .req_burst_count(req_length[DMA_LENGTH_WIDTH-1:BYTES_PER_BURST_WIDTH]), + .req_valid(req_gen_valid), + .req_ready(req_gen_ready), + .req_burst_count(req_length[DMA_LENGTH_WIDTH-1:BYTES_PER_BURST_WIDTH]), - .enable(do_enable), - .pause(pause), + .enable(do_enable), + .pause(pause), - .eot(request_eot) + .eot(request_eot) ); sync_bits #( - .NUM_OF_BITS(3), - .ASYNC_CLK(ASYNC_CLK_DEST_REQ) + .NUM_OF_BITS(3), + .ASYNC_CLK(ASYNC_CLK_DEST_REQ) ) i_sync_control_dest ( - .out_clk(dest_clk), - .out_resetn(dest_resetn), - .in({do_enable, pause, sync_id}), - .out({dest_enable, dest_pause, dest_sync_id}) + .out_clk(dest_clk), + .out_resetn(dest_resetn), + .in({do_enable, pause, sync_id}), + .out({dest_enable, dest_pause, dest_sync_id}) ); sync_bits #( - .NUM_OF_BITS(2), - .ASYNC_CLK(ASYNC_CLK_DEST_REQ) + .NUM_OF_BITS(2), + .ASYNC_CLK(ASYNC_CLK_DEST_REQ) ) i_sync_status_dest ( - .out_clk(req_aclk), - .out_resetn(req_aresetn), - .in({dest_enabled | ~dest_response_empty, dest_sync_id_ret}), - .out({enabled_dest, sync_id_ret_dest}) + .out_clk(req_aclk), + .out_resetn(req_aresetn), + .in({dest_enabled | ~dest_response_empty, dest_sync_id_ret}), + .out({enabled_dest, sync_id_ret_dest}) ); sync_bits #( - .NUM_OF_BITS(3), - .ASYNC_CLK(ASYNC_CLK_REQ_SRC) + .NUM_OF_BITS(3), + .ASYNC_CLK(ASYNC_CLK_REQ_SRC) ) i_sync_control_src ( - .out_clk(src_clk), - .out_resetn(src_resetn), - .in({do_enable, pause, sync_id}), - .out({src_enable, src_pause, src_sync_id}) + .out_clk(src_clk), + .out_resetn(src_resetn), + .in({do_enable, pause, sync_id}), + .out({src_enable, src_pause, src_sync_id}) ); sync_bits #( - .NUM_OF_BITS(3), - .ASYNC_CLK(ASYNC_CLK_REQ_SRC) + .NUM_OF_BITS(3), + .ASYNC_CLK(ASYNC_CLK_REQ_SRC) ) i_sync_status_src ( - .out_clk(req_aclk), - .out_resetn(req_aresetn), - .in({src_enabled | ~src_response_empty, src_sync_id_ret, src_fifo_empty}), - .out({enabled_src, sync_id_ret_src, fifo_empty}) + .out_clk(req_aclk), + .out_resetn(req_aresetn), + .in({src_enabled | ~src_response_empty, src_sync_id_ret, src_fifo_empty}), + .out({enabled_src, sync_id_ret_src, fifo_empty}) ); endmodule diff --git a/library/axi_dmac/request_generator.v b/library/axi_dmac/request_generator.v index 7a6df253d..d56a5e8c5 100644 --- a/library/axi_dmac/request_generator.v +++ b/library/axi_dmac/request_generator.v @@ -37,20 +37,20 @@ // *************************************************************************** module dmac_request_generator ( - input req_aclk, - input req_aresetn, + input req_aclk, + input req_aresetn, - output [ID_WIDTH-1:0] request_id, - input [ID_WIDTH-1:0] response_id, + output [ID_WIDTH-1:0] request_id, + input [ID_WIDTH-1:0] response_id, - input req_valid, - output reg req_ready, - input [BURSTS_PER_TRANSFER_WIDTH-1:0] req_burst_count, + input req_valid, + output reg req_ready, + input [BURSTS_PER_TRANSFER_WIDTH-1:0] req_burst_count, - input enable, - input pause, + input enable, + input pause, - output eot + output eot ); parameter ID_WIDTH = 3; @@ -74,25 +74,25 @@ assign request_id = id; always @(posedge req_aclk) begin - if (req_aresetn == 1'b0) begin - burst_count <= 'h00; - id <= 'h0; - req_ready <= 1'b1; - end else if (enable == 1'b0) begin - req_ready <= 1'b1; - end else begin - if (req_ready) begin - if (req_valid && enable) begin - burst_count <= req_burst_count; - req_ready <= 1'b0; - end - end else if (response_id != id_next && ~pause) begin - if (eot) - req_ready <= 1'b1; - burst_count <= burst_count - 1'b1; - id <= id_next; - end - end + if (req_aresetn == 1'b0) begin + burst_count <= 'h00; + id <= 'h0; + req_ready <= 1'b1; + end else if (enable == 1'b0) begin + req_ready <= 1'b1; + end else begin + if (req_ready) begin + if (req_valid && enable) begin + burst_count <= req_burst_count; + req_ready <= 1'b0; + end + end else if (response_id != id_next && ~pause) begin + if (eot) + req_ready <= 1'b1; + burst_count <= burst_count - 1'b1; + id <= id_next; + end + end end endmodule diff --git a/library/axi_dmac/response_generator.v b/library/axi_dmac/response_generator.v index 1ed4aae02..61104d36f 100644 --- a/library/axi_dmac/response_generator.v +++ b/library/axi_dmac/response_generator.v @@ -37,22 +37,22 @@ // *************************************************************************** module dmac_response_generator ( - input clk, - input resetn, + input clk, + input resetn, - input enable, - output reg enabled, + input enable, + output reg enabled, - input [ID_WIDTH-1:0] request_id, - output reg [ID_WIDTH-1:0] response_id, - input sync_id, + input [ID_WIDTH-1:0] request_id, + output reg [ID_WIDTH-1:0] response_id, + input sync_id, - input eot, + input eot, - output resp_valid, - input resp_ready, - output resp_eot, - output [1:0] resp_resp + output resp_valid, + input resp_ready, + output resp_eot, + output [1:0] resp_resp ); parameter ID_WIDTH = 3; @@ -67,24 +67,24 @@ assign resp_valid = request_id != response_id && enabled; // We have to wait for all responses before we can disable the response handler always @(posedge clk) begin - if (resetn == 1'b0) begin - enabled <= 1'b0; - end else begin - if (enable) - enabled <= 1'b1; - else if (request_id == response_id) - enabled <= 1'b0; - end + if (resetn == 1'b0) begin + enabled <= 1'b0; + end else begin + if (enable) + enabled <= 1'b1; + else if (request_id == response_id) + enabled <= 1'b0; + end end always @(posedge clk) begin - if (resetn == 1'b0) begin - response_id <= 'h0; - end else begin - if ((resp_valid && resp_ready) || - (sync_id && response_id != request_id)) - response_id <= inc_id(response_id); - end + if (resetn == 1'b0) begin + response_id <= 'h0; + end else begin + if ((resp_valid && resp_ready) || + (sync_id && response_id != request_id)) + response_id <= inc_id(response_id); + end end endmodule diff --git a/library/axi_dmac/response_handler.v b/library/axi_dmac/response_handler.v index 3c62915f6..cd64ba7e7 100644 --- a/library/axi_dmac/response_handler.v +++ b/library/axi_dmac/response_handler.v @@ -37,26 +37,26 @@ // *************************************************************************** module dmac_response_handler ( - input clk, - input resetn, + input clk, + input resetn, - input bvalid, - output bready, - input [1:0] bresp, + input bvalid, + output bready, + input [1:0] bresp, - output reg [ID_WIDTH-1:0] id, - input [ID_WIDTH-1:0] request_id, - input sync_id, + output reg [ID_WIDTH-1:0] id, + input [ID_WIDTH-1:0] request_id, + input sync_id, - input enable, - output reg enabled, + input enable, + output reg enabled, - input eot, + input eot, - output resp_valid, - input resp_ready, - output resp_eot, - output [1:0] resp_resp + output resp_valid, + input resp_ready, + output resp_eot, + output [1:0] resp_resp ); parameter ID_WIDTH = 3; @@ -74,24 +74,24 @@ assign resp_valid = active && bvalid; // We have to wait for all responses before we can disable the response handler always @(posedge clk) begin - if (resetn == 1'b0) begin - enabled <= 1'b0; - end else begin - if (enable) - enabled <= 1'b1; - else if (request_id == id) - enabled <= 1'b0; - end + if (resetn == 1'b0) begin + enabled <= 1'b0; + end else begin + if (enable) + enabled <= 1'b1; + else if (request_id == id) + enabled <= 1'b0; + end end always @(posedge clk) begin - if (resetn == 1'b0) begin - id <= 'h0; - end else begin - if ((bready && bvalid) || - (sync_id && id != request_id)) - id <= inc_id(id); - end + if (resetn == 1'b0) begin + id <= 'h0; + end else begin + if ((bready && bvalid) || + (sync_id && id != request_id)) + id <= inc_id(id); + end end endmodule diff --git a/library/axi_dmac/splitter.v b/library/axi_dmac/splitter.v index 3d262c54e..4fee19f95 100644 --- a/library/axi_dmac/splitter.v +++ b/library/axi_dmac/splitter.v @@ -37,14 +37,14 @@ module splitter ( - input clk, - input resetn, + input clk, + input resetn, - input s_valid, - output s_ready, + input s_valid, + output s_ready, - output [NUM_M-1:0] m_valid, - input [NUM_M-1:0] m_ready + output [NUM_M-1:0] m_valid, + input [NUM_M-1:0] m_ready ); parameter NUM_M = 2; @@ -56,14 +56,14 @@ assign m_valid = s_valid ? ~acked : {NUM_M{1'b0}}; always @(posedge clk) begin - if (resetn == 1'b0) begin - acked <= {NUM_M{1'b0}}; - end else begin - if (s_valid & s_ready) - acked <= {NUM_M{1'b0}}; - else - acked <= acked | (m_ready & m_valid); - end + if (resetn == 1'b0) begin + acked <= {NUM_M{1'b0}}; + end else begin + if (s_valid & s_ready) + acked <= {NUM_M{1'b0}}; + else + acked <= acked | (m_ready & m_valid); + end end endmodule diff --git a/library/axi_dmac/src_axi_mm.v b/library/axi_dmac/src_axi_mm.v index 4fb149fb1..c1a06b0d8 100644 --- a/library/axi_dmac/src_axi_mm.v +++ b/library/axi_dmac/src_axi_mm.v @@ -37,51 +37,51 @@ // *************************************************************************** module dmac_src_mm_axi ( - input m_axi_aclk, - input m_axi_aresetn, + input m_axi_aclk, + input m_axi_aresetn, - input req_valid, - output req_ready, - input [31:BYTES_PER_BEAT_WIDTH] req_address, - input [BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length, + input req_valid, + output req_ready, + input [31:BYTES_PER_BEAT_WIDTH] req_address, + input [BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length, - input enable, - output enabled, - input pause, - input sync_id, - output sync_id_ret, + input enable, + output enabled, + input pause, + input sync_id, + output sync_id_ret, - output response_valid, - input response_ready, - output [1:0] response_resp, + output response_valid, + input response_ready, + output [1:0] response_resp, - input [ID_WIDTH-1:0] request_id, - output [ID_WIDTH-1:0] response_id, + input [ID_WIDTH-1:0] request_id, + output [ID_WIDTH-1:0] response_id, - output [ID_WIDTH-1:0] data_id, - output [ID_WIDTH-1:0] address_id, - input data_eot, - input address_eot, + output [ID_WIDTH-1:0] data_id, + output [ID_WIDTH-1:0] address_id, + input data_eot, + input address_eot, - output fifo_valid, - input fifo_ready, - output [DMA_DATA_WIDTH-1:0] fifo_data, + output fifo_valid, + input fifo_ready, + output [DMA_DATA_WIDTH-1:0] fifo_data, - // Read address - input m_axi_arready, - output m_axi_arvalid, - output [31:0] m_axi_araddr, - output [ 7:0] m_axi_arlen, - output [ 2:0] m_axi_arsize, - output [ 1:0] m_axi_arburst, - output [ 2:0] m_axi_arprot, - output [ 3:0] m_axi_arcache, + // Read address + input m_axi_arready, + output m_axi_arvalid, + output [31:0] m_axi_araddr, + output [ 7:0] m_axi_arlen, + output [ 2:0] m_axi_arsize, + output [ 1:0] m_axi_arburst, + output [ 2:0] m_axi_arprot, + output [ 3:0] m_axi_arcache, - // Read data and response - input [DMA_DATA_WIDTH-1:0] m_axi_rdata, - output m_axi_rready, - input m_axi_rvalid, - input [ 1:0] m_axi_rresp + // Read data and response + input [DMA_DATA_WIDTH-1:0] m_axi_rdata, + output m_axi_rready, + input m_axi_rvalid, + input [ 1:0] m_axi_rresp ); parameter ID_WIDTH = 3; @@ -105,95 +105,95 @@ assign response_valid = 1'b0; assign response_resp = RESP_OKAY; splitter #( - .NUM_M(2) + .NUM_M(2) ) i_req_splitter ( - .clk(m_axi_aclk), - .resetn(m_axi_aresetn), - .s_valid(req_valid), - .s_ready(req_ready), - .m_valid({ - address_req_valid, - data_req_valid - }), - .m_ready({ - address_req_ready, - data_req_ready - }) + .clk(m_axi_aclk), + .resetn(m_axi_aresetn), + .s_valid(req_valid), + .s_ready(req_ready), + .m_valid({ + address_req_valid, + data_req_valid + }), + .m_ready({ + address_req_ready, + data_req_ready + }) ); dmac_address_generator #( - .ID_WIDTH(ID_WIDTH), - .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH), - .BYTES_PER_BEAT_WIDTH(BYTES_PER_BEAT_WIDTH), - .DMA_DATA_WIDTH(DMA_DATA_WIDTH) + .ID_WIDTH(ID_WIDTH), + .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH), + .BYTES_PER_BEAT_WIDTH(BYTES_PER_BEAT_WIDTH), + .DMA_DATA_WIDTH(DMA_DATA_WIDTH) ) i_addr_gen ( - .clk(m_axi_aclk), - .resetn(m_axi_aresetn), + .clk(m_axi_aclk), + .resetn(m_axi_aresetn), - .enable(enable), - .enabled(address_enabled), - .pause(pause), - .sync_id(sync_id), + .enable(enable), + .enabled(address_enabled), + .pause(pause), + .sync_id(sync_id), - .request_id(request_id), - .id(address_id), + .request_id(request_id), + .id(address_id), - .req_valid(address_req_valid), - .req_ready(address_req_ready), - .req_address(req_address), - .req_last_burst_length(req_last_burst_length), + .req_valid(address_req_valid), + .req_ready(address_req_ready), + .req_address(req_address), + .req_last_burst_length(req_last_burst_length), - .eot(address_eot), + .eot(address_eot), - .addr_ready(m_axi_arready), - .addr_valid(m_axi_arvalid), - .addr(m_axi_araddr), - .len(m_axi_arlen), - .size(m_axi_arsize), - .burst(m_axi_arburst), - .prot(m_axi_arprot), - .cache(m_axi_arcache) + .addr_ready(m_axi_arready), + .addr_valid(m_axi_arvalid), + .addr(m_axi_araddr), + .len(m_axi_arlen), + .size(m_axi_arsize), + .burst(m_axi_arburst), + .prot(m_axi_arprot), + .cache(m_axi_arcache) ); dmac_data_mover # ( - .ID_WIDTH(ID_WIDTH), - .DATA_WIDTH(DMA_DATA_WIDTH), - .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH) + .ID_WIDTH(ID_WIDTH), + .DATA_WIDTH(DMA_DATA_WIDTH), + .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH) ) i_data_mover ( - .clk(m_axi_aclk), - .resetn(m_axi_aresetn), + .clk(m_axi_aclk), + .resetn(m_axi_aresetn), - .enable(address_enabled), - .enabled(enabled), - .sync_id(sync_id), + .enable(address_enabled), + .enabled(enabled), + .sync_id(sync_id), - .xfer_req(), + .xfer_req(), - .request_id(address_id), - .response_id(data_id), - .eot(data_eot), + .request_id(address_id), + .response_id(data_id), + .eot(data_eot), - .req_valid(data_req_valid), - .req_ready(data_req_ready), - .req_last_burst_length(req_last_burst_length), + .req_valid(data_req_valid), + .req_ready(data_req_ready), + .req_last_burst_length(req_last_burst_length), - .s_axi_valid(m_axi_rvalid), - .s_axi_ready(m_axi_rready), - .s_axi_data(m_axi_rdata), - .m_axi_valid(fifo_valid), - .m_axi_ready(fifo_ready), - .m_axi_data(fifo_data), - .m_axi_last() + .s_axi_valid(m_axi_rvalid), + .s_axi_ready(m_axi_rready), + .s_axi_data(m_axi_rdata), + .m_axi_valid(fifo_valid), + .m_axi_ready(fifo_ready), + .m_axi_data(fifo_data), + .m_axi_last() ); reg [1:0] rresp; always @(posedge m_axi_aclk) begin - if (m_axi_rvalid && m_axi_rready) begin - if (m_axi_rresp != 2'b0) - rresp <= m_axi_rresp; - end + if (m_axi_rvalid && m_axi_rready) begin + if (m_axi_rresp != 2'b0) + rresp <= m_axi_rresp; + end end endmodule diff --git a/library/axi_dmac/src_axi_stream.v b/library/axi_dmac/src_axi_stream.v index 4d281f7e1..a2c41a928 100644 --- a/library/axi_dmac/src_axi_stream.v +++ b/library/axi_dmac/src_axi_stream.v @@ -37,32 +37,32 @@ // *************************************************************************** module dmac_src_axi_stream ( - input s_axis_aclk, - input s_axis_aresetn, + input s_axis_aclk, + input s_axis_aresetn, - input enable, - output enabled, - input sync_id, - output sync_id_ret, + input enable, + output enabled, + input sync_id, + output sync_id_ret, - input [ID_WIDTH-1:0] request_id, - output [ID_WIDTH-1:0] response_id, - input eot, + input [ID_WIDTH-1:0] request_id, + output [ID_WIDTH-1:0] response_id, + input eot, - output s_axis_ready, - input s_axis_valid, - input [S_AXIS_DATA_WIDTH-1:0] s_axis_data, - input [0:0] s_axis_user, - output s_axis_xfer_req, + output s_axis_ready, + input s_axis_valid, + input [S_AXIS_DATA_WIDTH-1:0] s_axis_data, + input [0:0] s_axis_user, + output s_axis_xfer_req, - input fifo_ready, - output fifo_valid, - output [S_AXIS_DATA_WIDTH-1:0] fifo_data, + input fifo_ready, + output fifo_valid, + output [S_AXIS_DATA_WIDTH-1:0] fifo_data, - input req_valid, - output req_ready, - input [BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length, - input req_sync_transfer_start + input req_valid, + output req_ready, + input [BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length, + input req_sync_transfer_start ); parameter ID_WIDTH = 3; @@ -78,46 +78,46 @@ assign sync_id_ret = sync_id; always @(posedge s_axis_aclk) begin - if (s_axis_aresetn == 1'b0) begin - needs_sync <= 1'b0; - end else begin - if (s_axis_valid && s_axis_ready && sync) begin - needs_sync <= 1'b0; - end else if (req_valid && req_ready) begin - needs_sync <= req_sync_transfer_start; - end - end + if (s_axis_aresetn == 1'b0) begin + needs_sync <= 1'b0; + end else begin + if (s_axis_valid && s_axis_ready && sync) begin + needs_sync <= 1'b0; + end else if (req_valid && req_ready) begin + needs_sync <= req_sync_transfer_start; + end + end end dmac_data_mover # ( - .ID_WIDTH(ID_WIDTH), - .DATA_WIDTH(S_AXIS_DATA_WIDTH), - .DISABLE_WAIT_FOR_ID(0), - .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH) + .ID_WIDTH(ID_WIDTH), + .DATA_WIDTH(S_AXIS_DATA_WIDTH), + .DISABLE_WAIT_FOR_ID(0), + .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH) ) i_data_mover ( - .clk(s_axis_aclk), - .resetn(s_axis_aresetn), + .clk(s_axis_aclk), + .resetn(s_axis_aresetn), - .enable(enable), - .enabled(enabled), - .sync_id(sync_id), + .enable(enable), + .enabled(enabled), + .sync_id(sync_id), - .xfer_req(s_axis_xfer_req), + .xfer_req(s_axis_xfer_req), - .request_id(request_id), - .response_id(response_id), - .eot(eot), - - .req_valid(req_valid), - .req_ready(req_ready), - .req_last_burst_length(req_last_burst_length), + .request_id(request_id), + .response_id(response_id), + .eot(eot), + + .req_valid(req_valid), + .req_ready(req_ready), + .req_last_burst_length(req_last_burst_length), - .s_axi_ready(s_axis_ready), - .s_axi_valid(sync_valid), - .s_axi_data(s_axis_data), - .m_axi_ready(fifo_ready), - .m_axi_valid(fifo_valid), - .m_axi_data(fifo_data) + .s_axi_ready(s_axis_ready), + .s_axi_valid(sync_valid), + .s_axi_data(s_axis_data), + .m_axi_ready(fifo_ready), + .m_axi_valid(fifo_valid), + .m_axi_data(fifo_data) ); endmodule diff --git a/library/axi_dmac/src_fifo_inf.v b/library/axi_dmac/src_fifo_inf.v index bb28ce421..633cc1ab4 100644 --- a/library/axi_dmac/src_fifo_inf.v +++ b/library/axi_dmac/src_fifo_inf.v @@ -37,32 +37,32 @@ // *************************************************************************** module dmac_src_fifo_inf ( - input clk, - input resetn, + input clk, + input resetn, - input enable, - output enabled, - input sync_id, - output sync_id_ret, + input enable, + output enabled, + input sync_id, + output sync_id_ret, - input [ID_WIDTH-1:0] request_id, - output [ID_WIDTH-1:0] response_id, - input eot, + input [ID_WIDTH-1:0] request_id, + output [ID_WIDTH-1:0] response_id, + input eot, - input en, - input [DATA_WIDTH-1:0] din, - output reg overflow, - input sync, - output xfer_req, + input en, + input [DATA_WIDTH-1:0] din, + output reg overflow, + input sync, + output xfer_req, - input fifo_ready, - output fifo_valid, - output [DATA_WIDTH-1:0] fifo_data, + input fifo_ready, + output fifo_valid, + output [DATA_WIDTH-1:0] fifo_data, - input req_valid, - output req_ready, - input [BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length, - input req_sync_transfer_start + input req_valid, + output req_ready, + input [BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length, + input req_sync_transfer_start ); parameter ID_WIDTH = 3; @@ -77,62 +77,62 @@ wire sync_valid = en & ready & has_sync; always @(posedge clk) begin - if (resetn == 1'b0) begin - needs_sync <= 1'b0; - end else begin - if (ready && en && sync) begin - needs_sync <= 1'b0; - end else if (req_valid && req_ready) begin - needs_sync <= req_sync_transfer_start; - end - end + if (resetn == 1'b0) begin + needs_sync <= 1'b0; + end else begin + if (ready && en && sync) begin + needs_sync <= 1'b0; + end else if (req_valid && req_ready) begin + needs_sync <= req_sync_transfer_start; + end + end end always @(posedge clk) begin - if (resetn == 1'b0) begin - overflow <= 1'b0; - end else begin - if (enable) begin - overflow <= en & ~ready; - end else begin - overflow <= en; - end - end + if (resetn == 1'b0) begin + overflow <= 1'b0; + end else begin + if (enable) begin + overflow <= en & ~ready; + end else begin + overflow <= en; + end + end end assign sync_id_ret = sync_id; dmac_data_mover # ( - .ID_WIDTH(ID_WIDTH), - .DATA_WIDTH(DATA_WIDTH), - .DISABLE_WAIT_FOR_ID(0), - .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH) + .ID_WIDTH(ID_WIDTH), + .DATA_WIDTH(DATA_WIDTH), + .DISABLE_WAIT_FOR_ID(0), + .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH) ) i_data_mover ( - .clk(clk), - .resetn(resetn), + .clk(clk), + .resetn(resetn), - .enable(enable), - .enabled(enabled), - .sync_id(sync_id), + .enable(enable), + .enabled(enabled), + .sync_id(sync_id), - .xfer_req(xfer_req), + .xfer_req(xfer_req), - .request_id(request_id), - .response_id(response_id), - .eot(eot), - - .req_valid(req_valid), - .req_ready(req_ready), - .req_last_burst_length(req_last_burst_length), + .request_id(request_id), + .response_id(response_id), + .eot(eot), + + .req_valid(req_valid), + .req_ready(req_ready), + .req_last_burst_length(req_last_burst_length), - .s_axi_ready(ready), - .s_axi_valid(sync_valid), - .s_axi_data(din), - .m_axi_ready(fifo_ready), - .m_axi_valid(fifo_valid), - .m_axi_data(fifo_data), - .m_axi_last() + .s_axi_ready(ready), + .s_axi_valid(sync_valid), + .s_axi_data(din), + .m_axi_ready(fifo_ready), + .m_axi_valid(fifo_valid), + .m_axi_data(fifo_data), + .m_axi_last() ); endmodule diff --git a/library/axi_generic_adc/Makefile b/library/axi_generic_adc/Makefile index ef3361cc4..2efbcfbf7 100644 --- a/library/axi_generic_adc/Makefile +++ b/library/axi_generic_adc/Makefile @@ -5,18 +5,18 @@ #################################################################################### #################################################################################### -M_DEPS := axi_generic_adc_ip.tcl -M_DEPS += ../scripts/adi_env.tcl -M_DEPS += ../scripts/adi_ip.tcl M_DEPS += ../common/ad_rst.v +M_DEPS += ../common/up_adc_channel.v +M_DEPS += ../common/up_adc_common.v M_DEPS += ../common/up_axi.v +M_DEPS += ../common/up_clock_mon.v M_DEPS += ../common/up_delay_cntrl.v M_DEPS += ../common/up_xfer_cntrl.v M_DEPS += ../common/up_xfer_status.v -M_DEPS += ../common/up_clock_mon.v -M_DEPS += ../common/up_adc_channel.v -M_DEPS += ../common/up_adc_common.v +M_DEPS += ../scripts/adi_env.tcl +M_DEPS += ../scripts/adi_ip.tcl M_DEPS += axi_generic_adc.v +M_DEPS += axi_generic_adc_ip.tcl M_VIVADO := vivado -mode batch -source @@ -27,6 +27,10 @@ M_FLIST += *.log M_FLIST += component.xml M_FLIST += *.jou M_FLIST += xgui +M_FLIST += *.ip_user_files +M_FLIST += *.srcs +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil @@ -43,7 +47,7 @@ clean-all: axi_generic_adc.xpr: $(M_DEPS) - rm -rf $(M_FLIST) + -rm -rf $(M_FLIST) $(M_VIVADO) axi_generic_adc_ip.tcl >> axi_generic_adc_ip.log 2>&1 #################################################################################### diff --git a/library/axi_generic_adc/axi_generic_adc.v b/library/axi_generic_adc/axi_generic_adc.v index 7e747eb04..f2acc457f 100644 --- a/library/axi_generic_adc/axi_generic_adc.v +++ b/library/axi_generic_adc/axi_generic_adc.v @@ -1,33 +1,36 @@ module axi_generic_adc ( - input adc_clk, - output [NUM_OF_CHANNELS-1:0] adc_enable, - input adc_dovf, + input adc_clk, + output [NUM_OF_CHANNELS-1:0] adc_enable, + input adc_dovf, + + input s_axi_aclk, + input s_axi_aresetn, + input s_axi_awvalid, + input [31:0] s_axi_awaddr, + output s_axi_awready, + input s_axi_wvalid, + input [31:0] s_axi_wdata, + input [ 3:0] s_axi_wstrb, + output s_axi_wready, + output s_axi_bvalid, + output [ 1:0] s_axi_bresp, + input s_axi_bready, + input s_axi_arvalid, + input [31:0] s_axi_araddr, + output s_axi_arready, + output s_axi_rvalid, + output [ 1:0] s_axi_rresp, + output [31:0] s_axi_rdata, + input s_axi_rready, + input [ 2:0] s_axi_awprot, + input [ 2:0] s_axi_arprot - input s_axi_aclk, - input s_axi_aresetn, - input s_axi_awvalid, - input [31:0] s_axi_awaddr, - output s_axi_awready, - input s_axi_wvalid, - input [31:0] s_axi_wdata, - input [ 3:0] s_axi_wstrb, - output s_axi_wready, - output s_axi_bvalid, - output [ 1:0] s_axi_bresp, - input s_axi_bready, - input s_axi_arvalid, - input [31:0] s_axi_araddr, - output s_axi_arready, - output s_axi_rvalid, - output [ 1:0] s_axi_rresp, - output [31:0] s_axi_rdata, - input s_axi_rready ); parameter NUM_OF_CHANNELS = 2; parameter ID = 0; -reg [31:0] up_rdata = 'd0; +reg [31:0] up_rdata = 'd0; reg up_rack = 'd0; reg up_wack = 'd0; @@ -57,145 +60,148 @@ assign up_rstn = s_axi_aresetn; integer j; always @(*) begin - up_rdata_r = 'h00; - up_rack_r = 'h00; - up_wack_r = 'h00; - for (j = 0; j <= NUM_OF_CHANNELS; j=j+1) begin - up_rack_r = up_rack_r | up_rack_s[j]; - up_wack_r = up_wack_r | up_wack_s[j]; - up_rdata_r = up_rdata_r | up_rdata_s[j]; - end + up_rdata_r = 'h00; + up_rack_r = 'h00; + up_wack_r = 'h00; + for (j = 0; j <= NUM_OF_CHANNELS; j=j+1) begin + up_rack_r = up_rack_r | up_rack_s[j]; + up_wack_r = up_wack_r | up_wack_s[j]; + up_rdata_r = up_rdata_r | up_rdata_s[j]; + end end always @(negedge up_rstn or posedge up_clk) begin - if (up_rstn == 0) begin - up_rdata <= 'd0; - up_rack <= 'd0; - up_wack <= 'd0; - end else begin - up_rdata <= up_rdata_r; - up_rack <= up_rack_r; - up_wack <= up_wack_r; - end + if (up_rstn == 0) begin + up_rdata <= 'd0; + up_rack <= 'd0; + up_wack <= 'd0; + end else begin + up_rdata <= up_rdata_r; + up_rack <= up_rack_r; + up_wack <= up_wack_r; + end end up_adc_common #(.ID(ID)) i_up_adc_common ( - .mmcm_rst (), - .adc_clk (adc_clk), - .adc_rst (adc_rst), - .adc_r1_mode (), - .adc_ddr_edgesel (), - .adc_pin_mode (), - .adc_status ('h00), - .adc_status_ovf (adc_dovf), - .adc_status_unf (1'b0), - .adc_clk_ratio (32'd1), + .mmcm_rst (), + .adc_clk (adc_clk), + .adc_rst (adc_rst), + .adc_r1_mode (), + .adc_ddr_edgesel (), + .adc_pin_mode (), + .adc_status ('h00), + .adc_sync_status (1'b1), + .adc_status_ovf (adc_dovf), + .adc_status_unf (1'b0), + .adc_clk_ratio (32'd1), + .adc_start_code (), + .adc_sync (), - .up_status_pn_err (1'b0), - .up_status_pn_oos (1'b0), - .up_status_or (1'b0), - .up_drp_sel (), - .up_drp_wr (), - .up_drp_addr (), - .up_drp_wdata (), - .up_drp_rdata (16'd0), - .up_drp_ready (1'd0), - .up_drp_locked (1'd1), - .up_usr_chanmax (), - .adc_usr_chanmax (8'd0), - .up_adc_gpio_in (), - .up_adc_gpio_out (), - .up_rstn (up_rstn), - .up_clk (up_clk), - .up_wreq (up_wreq_s), - .up_waddr (up_waddr_s), - .up_wdata (up_wdata_s), - .up_wack (up_wack_s[NUM_OF_CHANNELS]), - .up_rreq (up_rreq_s), - .up_raddr (up_raddr_s), - .up_rdata (up_rdata_s[NUM_OF_CHANNELS]), - .up_rack (up_rack_s[NUM_OF_CHANNELS])); + .up_status_pn_err (1'b0), + .up_status_pn_oos (1'b0), + .up_status_or (1'b0), + .up_drp_sel (), + .up_drp_wr (), + .up_drp_addr (), + .up_drp_wdata (), + .up_drp_rdata (32'd0), + .up_drp_ready (1'd0), + .up_drp_locked (1'd1), + .up_usr_chanmax (), + .adc_usr_chanmax (8'd0), + .up_adc_gpio_in (), + .up_adc_gpio_out (), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack_s[NUM_OF_CHANNELS]), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata_s[NUM_OF_CHANNELS]), + .up_rack (up_rack_s[NUM_OF_CHANNELS])); // up bus interface up_axi i_up_axi ( - .up_rstn (up_rstn), - .up_clk (up_clk), - .up_axi_awvalid (s_axi_awvalid), - .up_axi_awaddr (s_axi_awaddr), - .up_axi_awready (s_axi_awready), - .up_axi_wvalid (s_axi_wvalid), - .up_axi_wdata (s_axi_wdata), - .up_axi_wstrb (s_axi_wstrb), - .up_axi_wready (s_axi_wready), - .up_axi_bvalid (s_axi_bvalid), - .up_axi_bresp (s_axi_bresp), - .up_axi_bready (s_axi_bready), - .up_axi_arvalid (s_axi_arvalid), - .up_axi_araddr (s_axi_araddr), - .up_axi_arready (s_axi_arready), - .up_axi_rvalid (s_axi_rvalid), - .up_axi_rresp (s_axi_rresp), - .up_axi_rdata (s_axi_rdata), - .up_axi_rready (s_axi_rready), - .up_wreq (up_wreq_s), - .up_waddr (up_waddr_s), - .up_wdata (up_wdata_s), - .up_wack (up_wack), - .up_rreq (up_rreq_s), - .up_raddr (up_raddr_s), - .up_rdata (up_rdata), - .up_rack (up_rack)); + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_axi_awvalid (s_axi_awvalid), + .up_axi_awaddr (s_axi_awaddr), + .up_axi_awready (s_axi_awready), + .up_axi_wvalid (s_axi_wvalid), + .up_axi_wdata (s_axi_wdata), + .up_axi_wstrb (s_axi_wstrb), + .up_axi_wready (s_axi_wready), + .up_axi_bvalid (s_axi_bvalid), + .up_axi_bresp (s_axi_bresp), + .up_axi_bready (s_axi_bready), + .up_axi_arvalid (s_axi_arvalid), + .up_axi_araddr (s_axi_araddr), + .up_axi_arready (s_axi_arready), + .up_axi_rvalid (s_axi_rvalid), + .up_axi_rresp (s_axi_rresp), + .up_axi_rdata (s_axi_rdata), + .up_axi_rready (s_axi_rready), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata), + .up_rack (up_rack)); generate genvar i; for (i = 0; i < NUM_OF_CHANNELS; i=i+1) begin - up_adc_channel #(.ADC_CHANNEL_ID(i)) i_up_adc_channel ( - .adc_clk (adc_clk), - .adc_rst (adc_rst), - .adc_enable (adc_enable[i]), - .adc_iqcor_enb (), - .adc_dcfilt_enb (), - .adc_dfmt_se (), - .adc_dfmt_type (), - .adc_dfmt_enable (), - .adc_dcfilt_offset (), - .adc_dcfilt_coeff (), - .adc_iqcor_coeff_1 (), - .adc_iqcor_coeff_2 (), - .adc_pnseq_sel (), - .adc_data_sel (), - .adc_pn_err (), - .adc_pn_oos (), - .adc_or (), - .up_adc_pn_err (), - .up_adc_pn_oos (), - .up_adc_or (), - .up_usr_datatype_be (), - .up_usr_datatype_signed (), - .up_usr_datatype_shift (), - .up_usr_datatype_total_bits (), - .up_usr_datatype_bits (), - .up_usr_decimation_m (), - .up_usr_decimation_n (), - .adc_usr_datatype_be (1'b0), - .adc_usr_datatype_signed (1'b1), - .adc_usr_datatype_shift (8'd0), - .adc_usr_datatype_total_bits (8'd32), - .adc_usr_datatype_bits (8'd32), - .adc_usr_decimation_m (16'd1), - .adc_usr_decimation_n (16'd1), - .up_rstn (up_rstn), - .up_clk (up_clk), - .up_wreq (up_wreq_s), - .up_waddr (up_waddr_s), - .up_wdata (up_wdata_s), - .up_wack (up_wack_s[i]), - .up_rreq (up_rreq_s), - .up_raddr (up_raddr_s), - .up_rdata (up_rdata_s[i]), - .up_rack (up_rack_s[i])); + up_adc_channel #(.CHANNEL_ID(i)) i_up_adc_channel ( + .adc_clk (adc_clk), + .adc_rst (adc_rst), + .adc_enable (adc_enable[i]), + .adc_iqcor_enb (), + .adc_dcfilt_enb (), + .adc_dfmt_se (), + .adc_dfmt_type (), + .adc_dfmt_enable (), + .adc_dcfilt_offset (), + .adc_dcfilt_coeff (), + .adc_iqcor_coeff_1 (), + .adc_iqcor_coeff_2 (), + .adc_pnseq_sel (), + .adc_data_sel (), + .adc_pn_err (), + .adc_pn_oos (), + .adc_or (), + .up_adc_pn_err (), + .up_adc_pn_oos (), + .up_adc_or (), + .up_usr_datatype_be (), + .up_usr_datatype_signed (), + .up_usr_datatype_shift (), + .up_usr_datatype_total_bits (), + .up_usr_datatype_bits (), + .up_usr_decimation_m (), + .up_usr_decimation_n (), + .adc_usr_datatype_be (1'b0), + .adc_usr_datatype_signed (1'b1), + .adc_usr_datatype_shift (8'd0), + .adc_usr_datatype_total_bits (8'd32), + .adc_usr_datatype_bits (8'd32), + .adc_usr_decimation_m (16'd1), + .adc_usr_decimation_n (16'd1), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack_s[i]), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata_s[i]), + .up_rack (up_rack_s[i])); end endgenerate diff --git a/library/axi_gpreg/Makefile b/library/axi_gpreg/Makefile index f8a659395..1b61f384d 100644 --- a/library/axi_gpreg/Makefile +++ b/library/axi_gpreg/Makefile @@ -5,16 +5,16 @@ #################################################################################### #################################################################################### -M_DEPS := axi_gpreg_ip.tcl +M_DEPS += ../common/ad_rst.v +M_DEPS += ../common/up_axi.v +M_DEPS += ../common/up_clock_mon.v M_DEPS += ../scripts/adi_env.tcl M_DEPS += ../scripts/adi_ip.tcl -M_DEPS += ../common/ad_rst.v -M_DEPS += ../common/up_clock_mon.v -M_DEPS += ../common/up_axi.v +M_DEPS += axi_gpreg.v +M_DEPS += axi_gpreg_clock_mon.v M_DEPS += axi_gpreg_constr.xdc M_DEPS += axi_gpreg_io.v -M_DEPS += axi_gpreg_clock_mon.v -M_DEPS += axi_gpreg.v +M_DEPS += axi_gpreg_ip.tcl M_VIVADO := vivado -mode batch -source @@ -25,6 +25,10 @@ M_FLIST += *.log M_FLIST += component.xml M_FLIST += *.jou M_FLIST += xgui +M_FLIST += *.ip_user_files +M_FLIST += *.srcs +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil @@ -41,7 +45,7 @@ clean-all: axi_gpreg.xpr: $(M_DEPS) - rm -rf $(M_FLIST) + -rm -rf $(M_FLIST) $(M_VIVADO) axi_gpreg_ip.tcl >> axi_gpreg_ip.log 2>&1 #################################################################################### diff --git a/library/axi_gpreg/axi_gpreg.v b/library/axi_gpreg/axi_gpreg.v index 8b5d5852e..30a8471a3 100644 --- a/library/axi_gpreg/axi_gpreg.v +++ b/library/axi_gpreg/axi_gpreg.v @@ -111,7 +111,10 @@ module axi_gpreg #( output s_axi_rvalid, output [ 31:0] s_axi_rdata, output [ 1:0] s_axi_rresp, - input s_axi_rready); + input s_axi_rready, + input [ 2:0] s_axi_awprot, + input [ 2:0] s_axi_arprot); + // version diff --git a/library/axi_hdmi_rx/Makefile b/library/axi_hdmi_rx/Makefile index d08123f0f..370f3d528 100644 --- a/library/axi_hdmi_rx/Makefile +++ b/library/axi_hdmi_rx/Makefile @@ -5,26 +5,26 @@ #################################################################################### #################################################################################### -M_DEPS := axi_hdmi_rx_ip.tcl -M_DEPS += ../scripts/adi_env.tcl -M_DEPS += ../scripts/adi_ip.tcl M_DEPS += ../common/ad_axi_ip_constr.xdc -M_DEPS += ../common/ad_rst.v M_DEPS += ../common/ad_csc_1.v -M_DEPS += ../common/ad_csc_1_mul.v M_DEPS += ../common/ad_csc_1_add.v -M_DEPS += ../common/ad_ss_422to444.v +M_DEPS += ../common/ad_csc_1_mul.v M_DEPS += ../common/ad_csc_CrYCb2RGB.v +M_DEPS += ../common/ad_rst.v +M_DEPS += ../common/ad_ss_422to444.v M_DEPS += ../common/up_axi.v M_DEPS += ../common/up_clock_mon.v -M_DEPS += ../common/up_xfer_status.v -M_DEPS += ../common/up_xfer_cntrl.v M_DEPS += ../common/up_hdmi_rx.v +M_DEPS += ../common/up_xfer_cntrl.v +M_DEPS += ../common/up_xfer_status.v +M_DEPS += ../scripts/adi_env.tcl +M_DEPS += ../scripts/adi_ip.tcl M_DEPS += axi_hdmi_rx.v -M_DEPS += axi_hdmi_rx_es.v -M_DEPS += axi_hdmi_rx_tpm.v M_DEPS += axi_hdmi_rx_constr.xdc M_DEPS += axi_hdmi_rx_core.v +M_DEPS += axi_hdmi_rx_es.v +M_DEPS += axi_hdmi_rx_ip.tcl +M_DEPS += axi_hdmi_rx_tpm.v M_VIVADO := vivado -mode batch -source @@ -35,6 +35,10 @@ M_FLIST += *.log M_FLIST += component.xml M_FLIST += *.jou M_FLIST += xgui +M_FLIST += *.ip_user_files +M_FLIST += *.srcs +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil @@ -51,7 +55,7 @@ clean-all: axi_hdmi_rx.xpr: $(M_DEPS) - rm -rf $(M_FLIST) + -rm -rf $(M_FLIST) $(M_VIVADO) axi_hdmi_rx_ip.tcl >> axi_hdmi_rx_ip.log 2>&1 #################################################################################### diff --git a/library/axi_hdmi_rx/axi_hdmi_rx.v b/library/axi_hdmi_rx/axi_hdmi_rx.v index afc20774e..3b6523f82 100644 --- a/library/axi_hdmi_rx/axi_hdmi_rx.v +++ b/library/axi_hdmi_rx/axi_hdmi_rx.v @@ -73,7 +73,9 @@ module axi_hdmi_rx ( s_axi_rvalid, s_axi_rresp, s_axi_rdata, - s_axi_rready); + s_axi_rready, + s_axi_awprot, + s_axi_arprot); // parameters @@ -114,6 +116,9 @@ module axi_hdmi_rx ( output [ 1:0] s_axi_rresp; output [31:0] s_axi_rdata; input s_axi_rready; + input [ 2:0] s_axi_awprot; + input [ 2:0] s_axi_arprot; + // internal signals diff --git a/library/axi_hdmi_rx/axi_hdmi_rx_core.v b/library/axi_hdmi_rx/axi_hdmi_rx_core.v index c1df3ab67..dc9e277cb 100644 --- a/library/axi_hdmi_rx/axi_hdmi_rx_core.v +++ b/library/axi_hdmi_rx/axi_hdmi_rx_core.v @@ -347,7 +347,7 @@ module axi_hdmi_rx_core ( .hdmi_hs_de (hdmi_hs_de_s), .hdmi_data_de (hdmi_data_de_s)); - // test patttern matcher + // test pattern matcher axi_hdmi_rx_tpm i_tpm ( .hdmi_clk (hdmi_clk), diff --git a/library/axi_hdmi_tx/Makefile b/library/axi_hdmi_tx/Makefile index 39f79bd36..4bb5e3319 100644 --- a/library/axi_hdmi_tx/Makefile +++ b/library/axi_hdmi_tx/Makefile @@ -5,27 +5,27 @@ #################################################################################### #################################################################################### -M_DEPS := axi_hdmi_tx_ip.tcl -M_DEPS += ../scripts/adi_env.tcl -M_DEPS += ../scripts/adi_ip.tcl M_DEPS += ../common/ad_axi_ip_constr.xdc +M_DEPS += ../common/ad_csc_1.v +M_DEPS += ../common/ad_csc_1_add.v +M_DEPS += ../common/ad_csc_1_mul.v +M_DEPS += ../common/ad_csc_RGB2CrYCb.v M_DEPS += ../common/ad_mem.v M_DEPS += ../common/ad_rst.v -M_DEPS += ../common/ad_csc_1_mul.v -M_DEPS += ../common/ad_csc_1_add.v -M_DEPS += ../common/ad_csc_1.v -M_DEPS += ../common/ad_csc_RGB2CrYCb.v M_DEPS += ../common/ad_ss_444to422.v M_DEPS += ../common/up_axi.v -M_DEPS += ../common/up_xfer_cntrl.v -M_DEPS += ../common/up_xfer_status.v M_DEPS += ../common/up_clock_mon.v M_DEPS += ../common/up_hdmi_tx.v -M_DEPS += axi_hdmi_tx_constr.xdc -M_DEPS += axi_hdmi_tx_vdma.v -M_DEPS += axi_hdmi_tx_es.v -M_DEPS += axi_hdmi_tx_core.v +M_DEPS += ../common/up_xfer_cntrl.v +M_DEPS += ../common/up_xfer_status.v +M_DEPS += ../scripts/adi_env.tcl +M_DEPS += ../scripts/adi_ip.tcl M_DEPS += axi_hdmi_tx.v +M_DEPS += axi_hdmi_tx_constr.xdc +M_DEPS += axi_hdmi_tx_core.v +M_DEPS += axi_hdmi_tx_es.v +M_DEPS += axi_hdmi_tx_ip.tcl +M_DEPS += axi_hdmi_tx_vdma.v M_VIVADO := vivado -mode batch -source @@ -36,6 +36,10 @@ M_FLIST += *.log M_FLIST += component.xml M_FLIST += *.jou M_FLIST += xgui +M_FLIST += *.ip_user_files +M_FLIST += *.srcs +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil @@ -52,7 +56,7 @@ clean-all: axi_hdmi_tx.xpr: $(M_DEPS) - rm -rf $(M_FLIST) + -rm -rf $(M_FLIST) $(M_VIVADO) axi_hdmi_tx_ip.tcl >> axi_hdmi_tx_ip.log 2>&1 #################################################################################### diff --git a/library/axi_hdmi_tx/axi_hdmi_tx.v b/library/axi_hdmi_tx/axi_hdmi_tx.v index 056eb2fb3..b0b08b758 100644 --- a/library/axi_hdmi_tx/axi_hdmi_tx.v +++ b/library/axi_hdmi_tx/axi_hdmi_tx.v @@ -187,7 +187,6 @@ module axi_hdmi_tx ( wire [13:0] up_raddr_s; wire [31:0] up_rdata_s; wire up_rack_s; - wire hdmi_full_range_s; wire hdmi_csc_bypass_s; wire hdmi_ss_bypass_s; wire [ 1:0] hdmi_srcsel_s; @@ -202,8 +201,8 @@ module axi_hdmi_tx ( wire [15:0] hdmi_vs_width_s; wire [15:0] hdmi_ve_max_s; wire [15:0] hdmi_ve_min_s; - wire [31:0] hdmi_clip_max_s; - wire [31:0] hdmi_clip_min_s; + wire [23:0] hdmi_clip_max_s; + wire [23:0] hdmi_clip_min_s; wire hdmi_fs_toggle_s; wire [ 8:0] hdmi_raddr_g_s; wire hdmi_tpm_oos_s; @@ -258,7 +257,6 @@ module axi_hdmi_tx ( up_hdmi_tx i_up ( .hdmi_clk (hdmi_clk), .hdmi_rst (hdmi_rst), - .hdmi_full_range (hdmi_full_range_s), .hdmi_csc_bypass (hdmi_csc_bypass_s), .hdmi_ss_bypass (hdmi_ss_bypass_s), .hdmi_srcsel (hdmi_srcsel_s), @@ -346,7 +344,6 @@ module axi_hdmi_tx ( .vdma_wdata (vdma_wdata_s), .vdma_fs_ret_toggle (vdma_fs_ret_toggle_s), .vdma_fs_waddr (vdma_fs_waddr_s), - .hdmi_full_range (hdmi_full_range_s), .hdmi_csc_bypass (hdmi_csc_bypass_s), .hdmi_ss_bypass (hdmi_ss_bypass_s), .hdmi_srcsel (hdmi_srcsel_s), diff --git a/library/axi_hdmi_tx/axi_hdmi_tx_core.v b/library/axi_hdmi_tx/axi_hdmi_tx_core.v index fd1ccf12c..4f50cdb36 100644 --- a/library/axi_hdmi_tx/axi_hdmi_tx_core.v +++ b/library/axi_hdmi_tx/axi_hdmi_tx_core.v @@ -1,9 +1,9 @@ // *************************************************************************** // *************************************************************************** // Copyright 2011(c) Analog Devices, Inc. -// +// // All rights reserved. -// +// // Redistribution and use in source and binary forms, with or without modification, // are permitted provided that the following conditions are met: // - Redistributions of source code must retain the above copyright @@ -21,16 +21,16 @@ // patent holders to use this software. // - Use of the software either in source or binary form, must be run // on or directly connected to an Analog Devices Inc. component. -// +// // THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, // INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A // PARTICULAR PURPOSE ARE DISCLAIMED. // // IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, // EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY -// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR // BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // *************************************************************************** // *************************************************************************** @@ -83,7 +83,6 @@ module axi_hdmi_tx_core ( // processor interface - hdmi_full_range, hdmi_csc_bypass, hdmi_ss_bypass, hdmi_srcsel, @@ -151,7 +150,6 @@ module axi_hdmi_tx_core ( // processor interface - input hdmi_full_range; input hdmi_csc_bypass; input hdmi_ss_bypass; input [ 1:0] hdmi_srcsel; @@ -203,6 +201,10 @@ module axi_hdmi_tx_core ( reg [47:0] hdmi_data_2d = 'd0; reg [23:0] hdmi_tpm_data = 'd0; reg hdmi_tpm_oos = 'd0; + reg hdmi_36_hsync = 'd0; + reg hdmi_36_vsync = 'd0; + reg hdmi_36_data_e = 'd0; + reg [35:0] hdmi_36_data = 'd0; reg hdmi_hsync = 'd0; reg hdmi_vsync = 'd0; reg hdmi_hsync_data_e = 'd0; @@ -221,21 +223,22 @@ module axi_hdmi_tx_core ( reg hdmi_24_vsync_data_e = 'd0; reg hdmi_24_data_e = 'd0; reg [23:0] hdmi_24_data = 'd0; - reg hdmi_24_hsync_ss = 'd0; - reg hdmi_24_vsync_ss = 'd0; - reg hdmi_24_hsync_data_e_ss = 'd0; - reg hdmi_24_vsync_data_e_ss = 'd0; - reg hdmi_24_data_e_ss = 'd0; - reg [23:0] hdmi_24_data_ss = 'd0; reg hdmi_16_hsync = 'd0; reg hdmi_16_vsync = 'd0; reg hdmi_16_hsync_data_e = 'd0; reg hdmi_16_vsync_data_e = 'd0; + reg hdmi_16_hsync_d = 'd0; + reg hdmi_16_vsync_d = 'd0; + reg hdmi_16_hsync_data_e_d = 'd0; + reg hdmi_16_vsync_data_e_d = 'd0; + reg hdmi_16_data_e_d = 'd0; + reg [15:0] hdmi_16_data_d = 'd0; reg hdmi_16_data_e = 'd0; reg [15:0] hdmi_16_data = 'd0; reg hdmi_es_hs_de = 'd0; reg hdmi_es_vs_de = 'd0; reg [15:0] hdmi_es_data = 'd0; + reg [15:0] hdmi_16_es_data = 'd0; reg [23:0] hdmi_clip_data = 'd0; reg hdmi_clip_hs_de_d = 'd0; reg hdmi_clip_vs_de_d = 'd0; @@ -267,15 +270,9 @@ module axi_hdmi_tx_core ( wire hdmi_ss_vsync_data_e_s; wire hdmi_ss_data_e_s; wire [15:0] hdmi_ss_data_s; - wire hdmi_clip_hs_de_s; - wire hdmi_clip_vs_de_s; - wire hdmi_clip_de_s; - wire [23:0] hdmi_clip_data_s; - wire hdmi_es_hs_de_s; - wire hdmi_es_vs_de_s; - wire hdmi_es_de_s; wire [15:0] hdmi_es_data_s; + // binary to grey conversion function [8:0] b2g; @@ -501,8 +498,6 @@ module axi_hdmi_tx_core ( // hdmi clipping - assign hdmi_clip_data_s = hdmi_24_csc_data; - always @(posedge hdmi_clk) begin hdmi_clip_hs_d <= hdmi_24_csc_hsync; hdmi_clip_vs_d <= hdmi_24_csc_vsync; @@ -512,46 +507,46 @@ module axi_hdmi_tx_core ( // Cr (red-diff) / red - if (hdmi_clip_data_s[23:16] > hdmi_clip_max[23:16]) begin + if (hdmi_24_csc_data[23:16] > hdmi_clip_max[23:16]) begin hdmi_clip_data[23:16] <= hdmi_clip_max[23:16]; - end else if (hdmi_clip_data_s[23:16] < hdmi_clip_min[23:16]) begin + end else if (hdmi_24_csc_data[23:16] < hdmi_clip_min[23:16]) begin hdmi_clip_data[23:16] <= hdmi_clip_min[23:16]; end else begin - hdmi_clip_data[23:16] <= hdmi_clip_data_s[23:16]; + hdmi_clip_data[23:16] <= hdmi_24_csc_data[23:16]; end // Y (luma) / green - if (hdmi_clip_data_s[15:8] > hdmi_clip_max[15:8]) begin + if (hdmi_24_csc_data[15:8] > hdmi_clip_max[15:8]) begin hdmi_clip_data[15:8] <= hdmi_clip_max[15:8]; - end else if (hdmi_clip_data_s[15:8] < hdmi_clip_min[15:8]) begin + end else if (hdmi_24_csc_data[15:8] < hdmi_clip_min[15:8]) begin hdmi_clip_data[15:8] <= hdmi_clip_min[15:8]; end else begin - hdmi_clip_data[15:8] <= hdmi_clip_data_s[15:8]; + hdmi_clip_data[15:8] <= hdmi_24_csc_data[15:8]; end // Cb (blue-diff) / blue - if (hdmi_clip_data_s[7:0] > hdmi_clip_max[7:0]) begin + if (hdmi_24_csc_data[7:0] > hdmi_clip_max[7:0]) begin hdmi_clip_data[7:0] <= hdmi_clip_max[7:0]; - end else if (hdmi_clip_data_s[7:0] < hdmi_clip_min[7:0]) begin + end else if (hdmi_24_csc_data[7:0] < hdmi_clip_min[7:0]) begin hdmi_clip_data[7:0] <= hdmi_clip_min[7:0]; end else begin - hdmi_clip_data[7:0] <= hdmi_clip_data_s[7:0]; + hdmi_clip_data[7:0] <= hdmi_24_csc_data[7:0]; end end // hdmi csc 16, 24 and 36 outputs - assign hdmi_36_hsync = hdmi_24_hsync; - assign hdmi_36_vsync = hdmi_24_vsync; - assign hdmi_36_data_e = hdmi_24_data_e; - assign hdmi_36_data[35:24] = {hdmi_24_data[23:16], hdmi_24_data[23:20]}; - assign hdmi_36_data[23:12] = {hdmi_24_data[15: 8], hdmi_24_data[15:12]}; - assign hdmi_36_data[11: 0] = {hdmi_24_data[ 7: 0], hdmi_24_data[ 7: 4]}; - always @(posedge hdmi_clk) begin + hdmi_36_hsync <= hdmi_clip_hs_d; + hdmi_36_vsync <= hdmi_clip_vs_d; + hdmi_36_data_e <= hdmi_clip_de_d; + hdmi_36_data[35:24] <= {hdmi_clip_data[23:16], hdmi_clip_data[23:20]}; + hdmi_36_data[23:12] <= {hdmi_clip_data[15: 8], hdmi_clip_data[15:12]}; + hdmi_36_data[11: 0] <= {hdmi_clip_data[ 7: 0], hdmi_clip_data[ 7: 4]}; + hdmi_24_hsync <= hdmi_clip_hs_d; hdmi_24_vsync <= hdmi_clip_vs_d; hdmi_24_hsync_data_e <= hdmi_clip_hs_de_d; @@ -559,42 +554,45 @@ module axi_hdmi_tx_core ( hdmi_24_data_e <= hdmi_clip_de_d; hdmi_24_data <= hdmi_clip_data; + hdmi_16_hsync <= hdmi_16_hsync_d; + hdmi_16_vsync <= hdmi_16_vsync_d; + hdmi_16_hsync_data_e <= hdmi_16_hsync_data_e_d; + hdmi_16_vsync_data_e <= hdmi_16_vsync_data_e_d; + hdmi_16_data_e <= hdmi_16_data_e_d; + hdmi_16_data <= hdmi_16_data_d; + hdmi_16_es_data <= hdmi_es_data_s; + if (hdmi_ss_bypass == 1'b1) begin - hdmi_16_hsync <= hdmi_24_hsync; - hdmi_16_vsync <= hdmi_24_vsync; - hdmi_16_hsync_data_e <= hdmi_24_hsync_data_e; - hdmi_16_vsync_data_e <= hdmi_24_vsync_data_e; - hdmi_16_data_e <= hdmi_24_data_e; - hdmi_16_data <= hdmi_24_data[15:0]; // Ignore the upper 8 bit + hdmi_16_hsync_d <= hdmi_clip_hs_d; + hdmi_16_vsync_d <= hdmi_clip_vs_d; + hdmi_16_hsync_data_e_d <= hdmi_clip_hs_de_d; + hdmi_16_vsync_data_e_d <= hdmi_clip_vs_de_d; + hdmi_16_data_e_d <= hdmi_clip_de_d; + hdmi_16_data_d <= hdmi_clip_data[15:0]; // Ignore the upper 8 bit end else begin - hdmi_16_hsync <= hdmi_ss_hsync_s; - hdmi_16_vsync <= hdmi_ss_vsync_s; - hdmi_16_hsync_data_e <= hdmi_ss_hsync_data_e_s; - hdmi_16_vsync_data_e <= hdmi_ss_vsync_data_e_s; - hdmi_16_data_e <= hdmi_ss_data_e_s; - hdmi_16_data <= hdmi_ss_data_s; + hdmi_16_hsync_d <= hdmi_ss_hsync_s; + hdmi_16_vsync_d <= hdmi_ss_vsync_s; + hdmi_16_hsync_data_e_d <= hdmi_ss_hsync_data_e_s; + hdmi_16_vsync_data_e_d <= hdmi_ss_vsync_data_e_s; + hdmi_16_data_e_d <= hdmi_ss_data_e_s; + hdmi_16_data_d <= hdmi_ss_data_s; end end // hdmi embedded sync - assign hdmi_es_hs_de_s = hdmi_16_hsync_data_e; - assign hdmi_es_vs_de_s = hdmi_16_vsync_data_e; - assign hdmi_es_de_s = hdmi_16_data_e; - assign hdmi_es_data_s = hdmi_16_data; - always @(posedge hdmi_clk) begin - hdmi_es_hs_de <= hdmi_es_hs_de_s; - hdmi_es_vs_de <= hdmi_es_vs_de_s; - if (hdmi_es_de_s == 1'b0) begin + hdmi_es_hs_de <= hdmi_16_hsync_data_e_d; + hdmi_es_vs_de <= hdmi_16_vsync_data_e_d; + if (hdmi_16_data_e_d == 1'b0) begin hdmi_es_data[15:8] <= 8'h80; end else begin - hdmi_es_data[15:8] <= hdmi_es_data_s[15:8]; + hdmi_es_data[15:8] <= hdmi_16_data_d[15:8]; end - if (hdmi_es_de_s == 1'b0) begin + if (hdmi_16_data_e_d == 1'b0) begin hdmi_es_data[7:0] <= 8'h80; end else begin - hdmi_es_data[7:0] <= hdmi_es_data_s[7:0]; + hdmi_es_data[7:0] <= hdmi_16_data_d[7:0]; end end @@ -651,7 +649,7 @@ module axi_hdmi_tx_core ( .hdmi_hs_de (hdmi_es_hs_de), .hdmi_vs_de (hdmi_es_vs_de), .hdmi_data_de (hdmi_es_data), - .hdmi_data (hdmi_16_es_data)); + .hdmi_data (hdmi_es_data_s)); endmodule diff --git a/library/axi_hdmi_tx/axi_hdmi_tx_hw.tcl b/library/axi_hdmi_tx/axi_hdmi_tx_hw.tcl index 8492d8cc1..9ee79219e 100755 --- a/library/axi_hdmi_tx/axi_hdmi_tx_hw.tcl +++ b/library/axi_hdmi_tx/axi_hdmi_tx_hw.tcl @@ -14,7 +14,6 @@ set_module_property DISPLAY_NAME axi_hdmi_tx add_fileset quartus_synth QUARTUS_SYNTH "" "Quartus Synthesis" set_fileset_property quartus_synth TOP_LEVEL axi_hdmi_tx -add_fileset_file MULT_MACRO.v VERILOG PATH $ad_hdl_dir/library/common/altera/MULT_MACRO.v add_fileset_file ad_mem.v VERILOG PATH $ad_hdl_dir/library/common/ad_mem.v add_fileset_file ad_rst.v VERILOG PATH $ad_hdl_dir/library/common/ad_rst.v add_fileset_file ad_csc_1_mul.v VERILOG PATH $ad_hdl_dir/library/common/ad_csc_1_mul.v diff --git a/library/axi_i2s_adi/Makefile b/library/axi_i2s_adi/Makefile index 04e05795e..1294ce309 100644 --- a/library/axi_i2s_adi/Makefile +++ b/library/axi_i2s_adi/Makefile @@ -5,21 +5,24 @@ #################################################################################### #################################################################################### -M_DEPS := axi_i2s_adi_ip.tcl +M_DEPS += ../common/axi_ctrlif.vhd +M_DEPS += ../common/axi_streaming_dma_rx_fifo.vhd +M_DEPS += ../common/axi_streaming_dma_tx_fifo.vhd +M_DEPS += ../common/dma_fifo.vhd +M_DEPS += ../common/pl330_dma_fifo.vhd M_DEPS += ../scripts/adi_env.tcl M_DEPS += ../scripts/adi_ip.tcl -M_DEPS += ../common/axi_ctrlif.vhd -M_DEPS += ../common/axi_streaming_dma_tx_fifo.vhd -M_DEPS += ../common/axi_streaming_dma_rx_fifo.vhd -M_DEPS += ../common/pl330_dma_fifo.vhd -M_DEPS += ../common/dma_fifo.vhd +M_DEPS += axi_i2s_adi.vhd +M_DEPS += axi_i2s_adi_constr.xdc +M_DEPS += axi_i2s_adi_ip.tcl +M_DEPS += fifo_synchronizer.vhd +M_DEPS += i2s_clkgen.vhd M_DEPS += i2s_controller.vhd M_DEPS += i2s_rx.vhd M_DEPS += i2s_tx.vhd -M_DEPS += i2s_clkgen.vhd -M_DEPS += fifo_synchronizer.vhd -M_DEPS += axi_i2s_adi.vhd -M_DEPS += axi_i2s_adi_constr.xdc + +M_DEPS += ../axi_i2s_adi/i2s.xml +M_DEPS += ../axi_i2s_adi/i2s_rtl.xml M_VIVADO := vivado -mode batch -source @@ -30,6 +33,10 @@ M_FLIST += *.log M_FLIST += component.xml M_FLIST += *.jou M_FLIST += xgui +M_FLIST += *.ip_user_files +M_FLIST += *.srcs +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil @@ -46,7 +53,7 @@ clean-all: axi_i2s_adi.xpr: $(M_DEPS) - rm -rf $(M_FLIST) + -rm -rf $(M_FLIST) $(M_VIVADO) axi_i2s_adi_ip.tcl >> axi_i2s_adi_ip.log 2>&1 #################################################################################### diff --git a/library/axi_i2s_adi/axi_i2s_adi.vhd b/library/axi_i2s_adi/axi_i2s_adi.vhd index 265cea358..90703fc3c 100644 --- a/library/axi_i2s_adi/axi_i2s_adi.vhd +++ b/library/axi_i2s_adi/axi_i2s_adi.vhd @@ -101,7 +101,10 @@ entity axi_i2s_adi is S_AXI_WREADY : out std_logic; S_AXI_BRESP : out std_logic_vector(1 downto 0); S_AXI_BVALID : out std_logic; - S_AXI_AWREADY : out std_logic + S_AXI_AWREADY : out std_logic; + S_AXI_AWPROT : in std_logic_vector(2 downto 0); + S_AXI_ARPROT : in std_logic_vector(2 downto 0) + ); end entity axi_i2s_adi; diff --git a/library/axi_i2s_adi/axi_i2s_adi_ip.tcl b/library/axi_i2s_adi/axi_i2s_adi_ip.tcl index d30ec0834..c5b1ae36c 100644 --- a/library/axi_i2s_adi/axi_i2s_adi_ip.tcl +++ b/library/axi_i2s_adi/axi_i2s_adi_ip.tcl @@ -20,6 +20,7 @@ adi_ip_files axi_i2s_adi [list \ ] adi_ip_properties axi_i2s_adi +adi_ip_infer_streaming_interfaces axi_i2s_adi adi_ip_constraints axi_spdif_tx axi_i2s_adi_constr.xdc late adi_add_bus "DMA_ACK_RX" "slave" \ @@ -97,8 +98,16 @@ adi_set_ports_dependency "DMA_REQ_RX_RSTN" \ "(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 1)" ipx::associate_bus_interfaces -clock s_axi_aclk -reset S_AXI_ARESETN [ipx::current_core] -ipx::associate_bus_interfaces -busif I2S -clock i2s_signal_clock [ipx::current_core] ipx::associate_bus_interfaces -clock s_axi_aclk -reset S_AXIS_ARESETN -clear [ipx::current_core] +# Tie-off optional inputs to 0 +set_property driver_value 0 [ipx::get_ports -filter "direction==in && enablement_dependency!={}" -of_objects [ipx::current_core]] + +# Incorrectly inferred interfaces +ipx::remove_bus_interface DMA_REQ_TX_RSTN [ipx::current_core] +ipx::remove_bus_interface DMA_REQ_RX_RSTN [ipx::current_core] +ipx::remove_bus_interface DMA_REQ_TX_ACLK [ipx::current_core] +ipx::remove_bus_interface DMA_REQ_RX_ACLK [ipx::current_core] + ipx::save_core [ipx::current_core] diff --git a/library/axi_intr_monitor/Makefile b/library/axi_intr_monitor/Makefile new file mode 100644 index 000000000..5a6d5cc98 --- /dev/null +++ b/library/axi_intr_monitor/Makefile @@ -0,0 +1,47 @@ +#################################################################################### +#################################################################################### +## Copyright 2011(c) Analog Devices, Inc. +## Auto-generated, do not modify! +#################################################################################### +#################################################################################### + +M_DEPS += ../common/up_axi.v +M_DEPS += ../scripts/adi_env.tcl +M_DEPS += ../scripts/adi_ip.tcl +M_DEPS += axi_intr_monitor.v +M_DEPS += axi_intr_monitor_ip.tcl + +M_VIVADO := vivado -mode batch -source + +M_FLIST := *.cache +M_FLIST += *.data +M_FLIST += *.xpr +M_FLIST += *.log +M_FLIST += component.xml +M_FLIST += *.jou +M_FLIST += xgui +M_FLIST += *.ip_user_files +M_FLIST += *.srcs +M_FLIST += *.hw +M_FLIST += *.sim +M_FLIST += .Xil + + + +.PHONY: all clean clean-all +all: axi_intr_monitor.xpr + + +clean:clean-all + + +clean-all: + rm -rf $(M_FLIST) + + +axi_intr_monitor.xpr: $(M_DEPS) + -rm -rf $(M_FLIST) + $(M_VIVADO) axi_intr_monitor_ip.tcl >> axi_intr_monitor_ip.log 2>&1 + +#################################################################################### +#################################################################################### diff --git a/library/axi_intr_monitor/axi_intr_monitor.v b/library/axi_intr_monitor/axi_intr_monitor.v new file mode 100644 index 000000000..c2ae7309f --- /dev/null +++ b/library/axi_intr_monitor/axi_intr_monitor.v @@ -0,0 +1,243 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2014(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// IP used to monitor interrupt handling latency for a system. +// Control register, bit 0 enables the core. If it's set to 0, the interrupt +// won't be activated and all counters will be reset to 0 +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_intr_monitor +( + output irq, + +// axi interface + + input s_axi_aclk, + input s_axi_aresetn, + input s_axi_awvalid, + input [31:0] s_axi_awaddr, + output s_axi_awready, + input s_axi_wvalid, + input [31:0] s_axi_wdata, + input [3:0] s_axi_wstrb, + output s_axi_wready, + output s_axi_bvalid, + output [1:0] s_axi_bresp, + input s_axi_bready, + input s_axi_arvalid, + input [31:0] s_axi_araddr, + output s_axi_arready, + output s_axi_rvalid, + output [1:0] s_axi_rresp, + output [31:0] s_axi_rdata, + input s_axi_rready, + input [ 2:0] s_axi_awprot, + input [ 2:0] s_axi_arprot + +); + +parameter VERSION = 32'h00010000; + +//------------------------------------------------------------------------------ +//----------- Registers Declarations ------------------------------------------- +//------------------------------------------------------------------------------ + +reg [31:0] up_rdata = 'd0; +reg up_wack = 'd0; +reg up_rack = 'd0; +reg pwm_gen_clk = 'd0; +reg [31:0] scratch = 'd0; +reg [31:0] control = 'd0; +reg interrupt = 'd0; +reg [31:0] counter_to_interrupt = 'd0; +reg [31:0] counter_to_interrupt_cnt = 'd0; +reg [31:0] counter_from_interrupt = 'd0; +reg [31:0] counter_interrupt_handling = 'd0; +reg [31:0] min_interrupt_handling = 'd0; +reg [31:0] max_interrupt_handling = 'd0; +reg interrupt_d1 = 'd0; +reg arm_counter = 'd0; +reg counter_active = 'd0; + +//------------------------------------------------------------------------------ +//----------- Wires Declarations ----------------------------------------------- +//------------------------------------------------------------------------------ + +wire up_rreq_s; +wire up_wreq_s; +wire [13:0] up_raddr_s; +wire [13:0] up_waddr_s; +wire [31:0] up_wdata_s; + +//------------------------------------------------------------------------------ +//----------- Assign/Always Blocks --------------------------------------------- +//------------------------------------------------------------------------------ + +assign irq = interrupt; + +always @(negedge s_axi_aresetn or posedge s_axi_aclk) begin + if (s_axi_aresetn == 1'b0 || control[0] == 1'b0) begin + counter_to_interrupt_cnt <= 0; + counter_interrupt_handling <= 'd0; + counter_from_interrupt <= 32'h0; + min_interrupt_handling <= 'd0; + max_interrupt_handling <= 'd0; + interrupt_d1 <= 0; + counter_active <= 1'b0; + end else begin + interrupt_d1 <= irq; + + if (arm_counter == 1'b1) begin + counter_to_interrupt_cnt <= counter_to_interrupt; + counter_active <= 1'b1; + end else if (counter_to_interrupt_cnt > 0) begin + counter_to_interrupt_cnt <= counter_to_interrupt_cnt - 1; + end else begin + counter_active <= 1'b0; + end + + if (irq == 1'b1 && interrupt_d1 == 1'b0) begin + counter_from_interrupt <= 32'h0; + end else begin + counter_from_interrupt <= counter_from_interrupt + 1; + end + + if (irq == 1'b0 && interrupt_d1 == 1'b1) begin + counter_interrupt_handling <= counter_from_interrupt; + if (min_interrupt_handling > counter_from_interrupt) begin + min_interrupt_handling <= counter_from_interrupt; + end + if (max_interrupt_handling < counter_from_interrupt) begin + max_interrupt_handling <= counter_from_interrupt; + end + end + end +end + +always @(negedge s_axi_aresetn or posedge s_axi_aclk) begin + if (s_axi_aresetn == 0) begin + up_wack <= 1'b0; + scratch <= 'd0; + control <= 'd0; + interrupt <= 'd0; + counter_to_interrupt <= 'd0; + arm_counter <= 'd0; + end else begin + up_wack <= up_wreq_s; + arm_counter <= 1'b0; + if ((up_wreq_s == 1'b1) && (up_waddr_s[3:0] == 4'h1)) begin + scratch <= up_wdata_s; + end + if ((up_wreq_s == 1'b1) && (up_waddr_s[3:0] == 4'h2)) begin + control <= up_wdata_s; + end + if (control[0] == 1'b0) begin + interrupt <= 1'b0; + end else if ((up_wreq_s == 1'b1) && (up_waddr_s[3:0] == 4'h3)) begin + interrupt <= interrupt & ~up_wdata_s[0]; + end else begin + if (counter_to_interrupt_cnt == 32'h0 && counter_active == 1'b1) begin + interrupt <= 1'b1; + end + end + if ((up_wreq_s == 1'b1) && (up_waddr_s[3:0] == 4'h4)) begin + counter_to_interrupt <= up_wdata_s; + arm_counter <= 1'b1; + end + end +end + +always @(negedge s_axi_aresetn or posedge s_axi_aclk) begin + if (s_axi_aresetn == 0) begin + up_rack <= 'd0; + up_rdata <= 'd0; + end else begin + up_rack <= up_rreq_s; + if (up_rreq_s == 1'b1) begin + case (up_raddr_s[3:0]) + 4'h0: up_rdata <= VERSION; + 4'h1: up_rdata <= scratch; + 4'h2: up_rdata <= control; + 4'h3: up_rdata <= {31'h0,interrupt}; + 4'h4: up_rdata <= counter_to_interrupt; + 4'h5: up_rdata <= counter_from_interrupt; + 4'h6: up_rdata <= counter_interrupt_handling; + 4'h7: up_rdata <= min_interrupt_handling; + 4'h8: up_rdata <= max_interrupt_handling; + default: up_rdata <= 0; + endcase + end else begin + up_rdata <= 32'd0; + end + end +end + +// up bus interface + +up_axi i_up_axi( + .up_rstn(s_axi_aresetn), + .up_clk(s_axi_aclk), + .up_axi_awvalid(s_axi_awvalid), + .up_axi_awaddr(s_axi_awaddr), + .up_axi_awready(s_axi_awready), + .up_axi_wvalid(s_axi_wvalid), + .up_axi_wdata(s_axi_wdata), + .up_axi_wstrb(s_axi_wstrb), + .up_axi_wready(s_axi_wready), + .up_axi_bvalid(s_axi_bvalid), + .up_axi_bresp(s_axi_bresp), + .up_axi_bready(s_axi_bready), + .up_axi_arvalid(s_axi_arvalid), + .up_axi_araddr(s_axi_araddr), + .up_axi_arready(s_axi_arready), + .up_axi_rvalid(s_axi_rvalid), + .up_axi_rresp(s_axi_rresp), + .up_axi_rdata(s_axi_rdata), + .up_axi_rready(s_axi_rready), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata), + .up_rack (up_rack)); + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/library/axi_intr_monitor/axi_intr_monitor_ip.tcl b/library/axi_intr_monitor/axi_intr_monitor_ip.tcl new file mode 100644 index 000000000..6352801ed --- /dev/null +++ b/library/axi_intr_monitor/axi_intr_monitor_ip.tcl @@ -0,0 +1,17 @@ +# ip + +source ../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip.tcl + +adi_ip_create axi_intr_monitor +adi_ip_files axi_intr_monitor [list \ + "$ad_hdl_dir/library/common/up_axi.v" \ + "axi_intr_monitor.v" ] + +adi_ip_properties axi_intr_monitor + +ipx::infer_bus_interface irq xilinx.com:signal:interrupt_rtl:1.0 [ipx::current_core] + +ipx::save_core [ipx::current_core] + + diff --git a/library/axi_jesd_gt/Makefile b/library/axi_jesd_gt/Makefile deleted file mode 100644 index e8fdc5069..000000000 --- a/library/axi_jesd_gt/Makefile +++ /dev/null @@ -1,66 +0,0 @@ -#################################################################################### -#################################################################################### -## Copyright 2011(c) Analog Devices, Inc. -## Auto-generated, do not modify! -#################################################################################### -#################################################################################### - -M_DEPS := axi_jesd_gt_ip.tcl -M_DEPS += ../scripts/adi_env.tcl -M_DEPS += ../scripts/adi_ip.tcl -M_DEPS += ../common/ad_rst.v -M_DEPS += ../common/ad_gt_channel.v -M_DEPS += ../common/ad_gt_common.v -M_DEPS += ../common/ad_gt_es.v -M_DEPS += ../common/ad_gt_es_axi.v -M_DEPS += ../common/ad_gt_channel_1.v -M_DEPS += ../common/ad_gt_common_1.v -M_DEPS += ../common/ad_jesd_align.v -M_DEPS += ../common/up_axi.v -M_DEPS += ../common/up_gt_channel.v -M_DEPS += ../common/up_gt.v -M_DEPS += axi_jesd_gt_constr.xdc -M_DEPS += axi_jesd_gt.v -M_DEPS += ../interfaces/if_gt_qpll.xml -M_DEPS += ../interfaces/if_gt_qpll_rtl.xml -M_DEPS += ../interfaces/if_gt_pll.xml -M_DEPS += ../interfaces/if_gt_pll_rtl.xml -M_DEPS += ../interfaces/if_gt_rx.xml -M_DEPS += ../interfaces/if_gt_rx_rtl.xml -M_DEPS += ../interfaces/if_gt_rx_ksig.xml -M_DEPS += ../interfaces/if_gt_rx_ksig_rtl.xml -M_DEPS += ../interfaces/if_gt_tx.xml -M_DEPS += ../interfaces/if_gt_tx_rtl.xml - -M_VIVADO := vivado -mode batch -source - -M_FLIST := *.cache -M_FLIST += *.data -M_FLIST += *.xpr -M_FLIST += *.log -M_FLIST += component.xml -M_FLIST += *.jou -M_FLIST += xgui -M_FLIST += .Xil - - - -.PHONY: all dep clean clean-all -all: dep axi_jesd_gt.xpr - - -clean:clean-all - - -clean-all: - rm -rf $(M_FLIST) - - -axi_jesd_gt.xpr: $(M_DEPS) - rm -rf $(M_FLIST) - $(M_VIVADO) axi_jesd_gt_ip.tcl >> axi_jesd_gt_ip.log 2>&1 - -dep: - make -C ../interfaces -#################################################################################### -#################################################################################### diff --git a/library/axi_jesd_gt/axi_jesd_gt.v b/library/axi_jesd_gt/axi_jesd_gt.v deleted file mode 100644 index 0612f9e6b..000000000 --- a/library/axi_jesd_gt/axi_jesd_gt.v +++ /dev/null @@ -1,1687 +0,0 @@ -// *************************************************************************** -// *************************************************************************** -// Copyright 2011(c) Analog Devices, Inc. -// -// All rights reserved. -// -// Redistribution and use in source and binary forms, with or without modification, -// are permitted provided that the following conditions are met: -// - Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// - Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in -// the documentation and/or other materials provided with the -// distribution. -// - Neither the name of Analog Devices, Inc. nor the names of its -// contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// - The use of this software may or may not infringe the patent rights -// of one or more patent holders. This license does not release you -// from the requirement that you obtain separate licenses from these -// patent holders to use this software. -// - Use of the software either in source or binary form, must be run -// on or directly connected to an Analog Devices Inc. component. -// -// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, -// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A -// PARTICULAR PURPOSE ARE DISCLAIMED. -// -// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY -// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF -// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// *************************************************************************** -// *************************************************************************** - -`timescale 1ns/100ps - -module axi_jesd_gt #( - - parameter integer ID = 0, - parameter integer NUM_OF_LANES = 8, - parameter integer GTH_OR_GTX_N = 0, - parameter integer QPLL0_ENABLE = 1, - parameter integer QPLL0_REFCLK_DIV = 1, - parameter [26:0] QPLL0_CFG = 27'h0680181, - parameter integer QPLL0_FBDIV_RATIO = 1'b1, - parameter [ 9:0] QPLL0_FBDIV = 10'b0000110000, - parameter integer QPLL1_ENABLE = 1, - parameter integer QPLL1_REFCLK_DIV = 1, - parameter [26:0] QPLL1_CFG = 27'h0680181, - parameter integer QPLL1_FBDIV_RATIO = 1'b1, - parameter [ 9:0] QPLL1_FBDIV = 10'b0000110000, - - parameter [31:0] PMA_RSV_0 = 32'h001E7080, - parameter integer CPLL_FBDIV_0 = 2, - parameter [31:0] PMA_RSV_1 = 32'h001E7080, - parameter integer CPLL_FBDIV_1 = 2, - parameter [31:0] PMA_RSV_2 = 32'h001E7080, - parameter integer CPLL_FBDIV_2 = 2, - parameter [31:0] PMA_RSV_3 = 32'h001E7080, - parameter integer CPLL_FBDIV_3 = 2, - parameter [31:0] PMA_RSV_4 = 32'h001E7080, - parameter integer CPLL_FBDIV_4 = 2, - parameter [31:0] PMA_RSV_5 = 32'h001E7080, - parameter integer CPLL_FBDIV_5 = 2, - parameter [31:0] PMA_RSV_6 = 32'h001E7080, - parameter integer CPLL_FBDIV_6 = 2, - parameter [31:0] PMA_RSV_7 = 32'h001E7080, - parameter integer CPLL_FBDIV_7 = 2, - - parameter integer RX_NUM_OF_LANES = 8, - parameter integer RX_OUT_DIV_0 = 1, - parameter integer RX_CLK25_DIV_0 = 20, - parameter integer RX_CLKBUF_ENABLE_0 = 1, - parameter [71:0] RX_CDR_CFG_0 = 72'h0b000023ff10400020, - parameter integer RX_OUT_DIV_1 = 1, - parameter integer RX_CLK25_DIV_1 = 20, - parameter integer RX_CLKBUF_ENABLE_1 = 1, - parameter [71:0] RX_CDR_CFG_1 = 72'h0b000023ff10400020, - parameter integer RX_OUT_DIV_2 = 1, - parameter integer RX_CLK25_DIV_2 = 20, - parameter integer RX_CLKBUF_ENABLE_2 = 1, - parameter [71:0] RX_CDR_CFG_2 = 72'h0b000023ff10400020, - parameter integer RX_OUT_DIV_3 = 1, - parameter integer RX_CLK25_DIV_3 = 20, - parameter integer RX_CLKBUF_ENABLE_3 = 1, - parameter [71:0] RX_CDR_CFG_3 = 72'h0b000023ff10400020, - parameter integer RX_OUT_DIV_4 = 1, - parameter integer RX_CLK25_DIV_4 = 20, - parameter integer RX_CLKBUF_ENABLE_4 = 1, - parameter [71:0] RX_CDR_CFG_4 = 72'h0b000023ff10400020, - parameter integer RX_OUT_DIV_5 = 1, - parameter integer RX_CLK25_DIV_5 = 20, - parameter integer RX_CLKBUF_ENABLE_5 = 1, - parameter [71:0] RX_CDR_CFG_5 = 72'h0b000023ff10400020, - parameter integer RX_OUT_DIV_6 = 1, - parameter integer RX_CLK25_DIV_6 = 20, - parameter integer RX_CLKBUF_ENABLE_6 = 1, - parameter [71:0] RX_CDR_CFG_6 = 72'h0b000023ff10400020, - parameter integer RX_OUT_DIV_7 = 1, - parameter integer RX_CLK25_DIV_7 = 20, - parameter integer RX_CLKBUF_ENABLE_7 = 1, - parameter [71:0] RX_CDR_CFG_7 = 72'h0b000023ff10400020, - - parameter integer TX_NUM_OF_LANES = 8, - parameter integer TX_OUT_DIV_0 = 1, - parameter integer TX_CLK25_DIV_0 = 20, - parameter integer TX_CLKBUF_ENABLE_0 = 1, - parameter integer TX_DATA_SEL_0 = 0, - parameter integer TX_OUT_DIV_1 = 1, - parameter integer TX_CLK25_DIV_1 = 20, - parameter integer TX_CLKBUF_ENABLE_1 = 1, - parameter integer TX_DATA_SEL_1 = 1, - parameter integer TX_OUT_DIV_2 = 1, - parameter integer TX_CLK25_DIV_2 = 20, - parameter integer TX_CLKBUF_ENABLE_2 = 1, - parameter integer TX_DATA_SEL_2 = 2, - parameter integer TX_OUT_DIV_3 = 1, - parameter integer TX_CLK25_DIV_3 = 20, - parameter integer TX_CLKBUF_ENABLE_3 = 1, - parameter integer TX_DATA_SEL_3 = 3, - parameter integer TX_OUT_DIV_4 = 1, - parameter integer TX_CLK25_DIV_4 = 20, - parameter integer TX_CLKBUF_ENABLE_4 = 1, - parameter integer TX_DATA_SEL_4 = 4, - parameter integer TX_OUT_DIV_5 = 1, - parameter integer TX_CLK25_DIV_5 = 20, - parameter integer TX_CLKBUF_ENABLE_5 = 1, - parameter integer TX_DATA_SEL_5 = 5, - parameter integer TX_OUT_DIV_6 = 1, - parameter integer TX_CLK25_DIV_6 = 20, - parameter integer TX_CLKBUF_ENABLE_6 = 1, - parameter integer TX_DATA_SEL_6 = 6, - parameter integer TX_OUT_DIV_7 = 1, - parameter integer TX_CLK25_DIV_7 = 20, - parameter integer TX_CLKBUF_ENABLE_7 = 1, - parameter integer TX_DATA_SEL_7 = 7) - - ( - - // pll clocks - - input qpll0_rst, - input qpll0_ref_clk_in, - input qpll1_rst, - input qpll1_ref_clk_in, - - // pll resets - - input cpll_rst_m_0, - input cpll_ref_clk_in_0, - input cpll_rst_m_1, - input cpll_ref_clk_in_1, - input cpll_rst_m_2, - input cpll_ref_clk_in_2, - input cpll_rst_m_3, - input cpll_ref_clk_in_3, - input cpll_rst_m_4, - input cpll_ref_clk_in_4, - input cpll_rst_m_5, - input cpll_ref_clk_in_5, - input cpll_rst_m_6, - input cpll_ref_clk_in_6, - input cpll_rst_m_7, - input cpll_ref_clk_in_7, - - // channel interface (rx) - - input rx_0_p, - input rx_0_n, - output rx_rst_0, - input rx_rst_m_0, - output rx_pll_rst_0, - output rx_gt_rst_0, - input rx_gt_rst_m_0, - output rx_pll_locked_0, - input rx_pll_locked_m_0, - output rx_user_ready_0, - input rx_user_ready_m_0, - output rx_rst_done_0, - input rx_rst_done_m_0, - output rx_out_clk_0, - input rx_clk_0, - input rx_sysref_0, - output rx_sync_0, - output rx_sof_0, - output [31:0] rx_data_0, - output [ 3:0] rx_gt_charisk_0, - output [ 3:0] rx_gt_disperr_0, - output [ 3:0] rx_gt_notintable_0, - output [31:0] rx_gt_data_0, - input rx_gt_comma_align_enb_0, - output [ 3:0] rx_gt_ilas_f_0, - output [ 3:0] rx_gt_ilas_q_0, - output [ 3:0] rx_gt_ilas_a_0, - output [ 3:0] rx_gt_ilas_r_0, - output [ 3:0] rx_gt_cgs_k_0, - output rx_ip_rst_0, - input [ 3:0] rx_ip_sof_0, - input [31:0] rx_ip_data_0, - output rx_ip_sysref_0, - input rx_ip_sync_0, - output rx_ip_rst_done_0, - - input rx_1_p, - input rx_1_n, - output rx_rst_1, - input rx_rst_m_1, - output rx_pll_rst_1, - output rx_gt_rst_1, - input rx_gt_rst_m_1, - output rx_pll_locked_1, - input rx_pll_locked_m_1, - output rx_user_ready_1, - input rx_user_ready_m_1, - output rx_rst_done_1, - input rx_rst_done_m_1, - output rx_out_clk_1, - input rx_clk_1, - input rx_sysref_1, - output rx_sync_1, - output rx_sof_1, - output [31:0] rx_data_1, - output [ 3:0] rx_gt_charisk_1, - output [ 3:0] rx_gt_disperr_1, - output [ 3:0] rx_gt_notintable_1, - output [31:0] rx_gt_data_1, - input rx_gt_comma_align_enb_1, - output [ 3:0] rx_gt_ilas_f_1, - output [ 3:0] rx_gt_ilas_q_1, - output [ 3:0] rx_gt_ilas_a_1, - output [ 3:0] rx_gt_ilas_r_1, - output [ 3:0] rx_gt_cgs_k_1, - output rx_ip_rst_1, - input [ 3:0] rx_ip_sof_1, - input [31:0] rx_ip_data_1, - output rx_ip_sysref_1, - input rx_ip_sync_1, - output rx_ip_rst_done_1, - - input rx_2_p, - input rx_2_n, - output rx_rst_2, - input rx_rst_m_2, - output rx_pll_rst_2, - output rx_gt_rst_2, - input rx_gt_rst_m_2, - output rx_pll_locked_2, - input rx_pll_locked_m_2, - output rx_user_ready_2, - input rx_user_ready_m_2, - output rx_rst_done_2, - input rx_rst_done_m_2, - output rx_out_clk_2, - input rx_clk_2, - input rx_sysref_2, - output rx_sync_2, - output rx_sof_2, - output [31:0] rx_data_2, - output [ 3:0] rx_gt_charisk_2, - output [ 3:0] rx_gt_disperr_2, - output [ 3:0] rx_gt_notintable_2, - output [31:0] rx_gt_data_2, - input rx_gt_comma_align_enb_2, - output [ 3:0] rx_gt_ilas_f_2, - output [ 3:0] rx_gt_ilas_q_2, - output [ 3:0] rx_gt_ilas_a_2, - output [ 3:0] rx_gt_ilas_r_2, - output [ 3:0] rx_gt_cgs_k_2, - output rx_ip_rst_2, - input [ 3:0] rx_ip_sof_2, - input [31:0] rx_ip_data_2, - output rx_ip_sysref_2, - input rx_ip_sync_2, - output rx_ip_rst_done_2, - - input rx_3_p, - input rx_3_n, - output rx_rst_3, - input rx_rst_m_3, - output rx_pll_rst_3, - output rx_gt_rst_3, - input rx_gt_rst_m_3, - output rx_pll_locked_3, - input rx_pll_locked_m_3, - output rx_user_ready_3, - input rx_user_ready_m_3, - output rx_rst_done_3, - input rx_rst_done_m_3, - output rx_out_clk_3, - input rx_clk_3, - input rx_sysref_3, - output rx_sync_3, - output rx_sof_3, - output [31:0] rx_data_3, - output [ 3:0] rx_gt_charisk_3, - output [ 3:0] rx_gt_disperr_3, - output [ 3:0] rx_gt_notintable_3, - output [31:0] rx_gt_data_3, - input rx_gt_comma_align_enb_3, - output [ 3:0] rx_gt_ilas_f_3, - output [ 3:0] rx_gt_ilas_q_3, - output [ 3:0] rx_gt_ilas_a_3, - output [ 3:0] rx_gt_ilas_r_3, - output [ 3:0] rx_gt_cgs_k_3, - output rx_ip_rst_3, - input [ 3:0] rx_ip_sof_3, - input [31:0] rx_ip_data_3, - output rx_ip_sysref_3, - input rx_ip_sync_3, - output rx_ip_rst_done_3, - - input rx_4_p, - input rx_4_n, - output rx_rst_4, - input rx_rst_m_4, - output rx_pll_rst_4, - output rx_gt_rst_4, - input rx_gt_rst_m_4, - output rx_pll_locked_4, - input rx_pll_locked_m_4, - output rx_user_ready_4, - input rx_user_ready_m_4, - output rx_rst_done_4, - input rx_rst_done_m_4, - output rx_out_clk_4, - input rx_clk_4, - input rx_sysref_4, - output rx_sync_4, - output rx_sof_4, - output [31:0] rx_data_4, - output [ 3:0] rx_gt_charisk_4, - output [ 3:0] rx_gt_disperr_4, - output [ 3:0] rx_gt_notintable_4, - output [31:0] rx_gt_data_4, - input rx_gt_comma_align_enb_4, - output [ 3:0] rx_gt_ilas_f_4, - output [ 3:0] rx_gt_ilas_q_4, - output [ 3:0] rx_gt_ilas_a_4, - output [ 3:0] rx_gt_ilas_r_4, - output [ 3:0] rx_gt_cgs_k_4, - output rx_ip_rst_4, - input [ 3:0] rx_ip_sof_4, - input [31:0] rx_ip_data_4, - output rx_ip_sysref_4, - input rx_ip_sync_4, - output rx_ip_rst_done_4, - - input rx_5_p, - input rx_5_n, - output rx_rst_5, - input rx_rst_m_5, - output rx_pll_rst_5, - output rx_gt_rst_5, - input rx_gt_rst_m_5, - output rx_pll_locked_5, - input rx_pll_locked_m_5, - output rx_user_ready_5, - input rx_user_ready_m_5, - output rx_rst_done_5, - input rx_rst_done_m_5, - output rx_out_clk_5, - input rx_clk_5, - input rx_sysref_5, - output rx_sync_5, - output rx_sof_5, - output [31:0] rx_data_5, - output [ 3:0] rx_gt_charisk_5, - output [ 3:0] rx_gt_disperr_5, - output [ 3:0] rx_gt_notintable_5, - output [31:0] rx_gt_data_5, - input rx_gt_comma_align_enb_5, - output [ 3:0] rx_gt_ilas_f_5, - output [ 3:0] rx_gt_ilas_q_5, - output [ 3:0] rx_gt_ilas_a_5, - output [ 3:0] rx_gt_ilas_r_5, - output [ 3:0] rx_gt_cgs_k_5, - output rx_ip_rst_5, - input [ 3:0] rx_ip_sof_5, - input [31:0] rx_ip_data_5, - output rx_ip_sysref_5, - input rx_ip_sync_5, - output rx_ip_rst_done_5, - - input rx_6_p, - input rx_6_n, - output rx_rst_6, - input rx_rst_m_6, - output rx_pll_rst_6, - output rx_gt_rst_6, - input rx_gt_rst_m_6, - output rx_pll_locked_6, - input rx_pll_locked_m_6, - output rx_user_ready_6, - input rx_user_ready_m_6, - output rx_rst_done_6, - input rx_rst_done_m_6, - output rx_out_clk_6, - input rx_clk_6, - input rx_sysref_6, - output rx_sync_6, - output rx_sof_6, - output [31:0] rx_data_6, - output [ 3:0] rx_gt_charisk_6, - output [ 3:0] rx_gt_disperr_6, - output [ 3:0] rx_gt_notintable_6, - output [31:0] rx_gt_data_6, - input rx_gt_comma_align_enb_6, - output [ 3:0] rx_gt_ilas_f_6, - output [ 3:0] rx_gt_ilas_q_6, - output [ 3:0] rx_gt_ilas_a_6, - output [ 3:0] rx_gt_ilas_r_6, - output [ 3:0] rx_gt_cgs_k_6, - output rx_ip_rst_6, - input [ 3:0] rx_ip_sof_6, - input [31:0] rx_ip_data_6, - output rx_ip_sysref_6, - input rx_ip_sync_6, - output rx_ip_rst_done_6, - - input rx_7_p, - input rx_7_n, - output rx_rst_7, - input rx_rst_m_7, - output rx_pll_rst_7, - output rx_gt_rst_7, - input rx_gt_rst_m_7, - output rx_pll_locked_7, - input rx_pll_locked_m_7, - output rx_user_ready_7, - input rx_user_ready_m_7, - output rx_rst_done_7, - input rx_rst_done_m_7, - output rx_out_clk_7, - input rx_clk_7, - input rx_sysref_7, - output rx_sync_7, - output rx_sof_7, - output [31:0] rx_data_7, - output [ 3:0] rx_gt_charisk_7, - output [ 3:0] rx_gt_disperr_7, - output [ 3:0] rx_gt_notintable_7, - output [31:0] rx_gt_data_7, - input rx_gt_comma_align_enb_7, - output [ 3:0] rx_gt_ilas_f_7, - output [ 3:0] rx_gt_ilas_q_7, - output [ 3:0] rx_gt_ilas_a_7, - output [ 3:0] rx_gt_ilas_r_7, - output [ 3:0] rx_gt_cgs_k_7, - output rx_ip_rst_7, - input [ 3:0] rx_ip_sof_7, - input [31:0] rx_ip_data_7, - output rx_ip_sysref_7, - input rx_ip_sync_7, - output rx_ip_rst_done_7, - - // channel interface (tx) - - output tx_0_p, - output tx_0_n, - output tx_rst_0, - input tx_rst_m_0, - output tx_pll_rst_0, - output tx_gt_rst_0, - input tx_gt_rst_m_0, - output tx_pll_locked_0, - input tx_pll_locked_m_0, - output tx_user_ready_0, - input tx_user_ready_m_0, - output tx_rst_done_0, - input tx_rst_done_m_0, - output tx_out_clk_0, - input tx_clk_0, - input tx_sysref_0, - input tx_sync_0, - input [31:0] tx_data_0, - input [ 3:0] tx_gt_charisk_0, - input [31:0] tx_gt_data_0, - output tx_ip_rst_0, - output [31:0] tx_ip_data_0, - output tx_ip_sysref_0, - output tx_ip_sync_0, - output tx_ip_rst_done_0, - - output tx_1_p, - output tx_1_n, - output tx_rst_1, - input tx_rst_m_1, - output tx_pll_rst_1, - output tx_gt_rst_1, - input tx_gt_rst_m_1, - output tx_pll_locked_1, - input tx_pll_locked_m_1, - output tx_user_ready_1, - input tx_user_ready_m_1, - output tx_rst_done_1, - input tx_rst_done_m_1, - output tx_out_clk_1, - input tx_clk_1, - input tx_sysref_1, - input tx_sync_1, - input [31:0] tx_data_1, - input [ 3:0] tx_gt_charisk_1, - input [31:0] tx_gt_data_1, - output tx_ip_rst_1, - output [31:0] tx_ip_data_1, - output tx_ip_sysref_1, - output tx_ip_sync_1, - output tx_ip_rst_done_1, - - output tx_2_p, - output tx_2_n, - output tx_rst_2, - input tx_rst_m_2, - output tx_pll_rst_2, - output tx_gt_rst_2, - input tx_gt_rst_m_2, - output tx_pll_locked_2, - input tx_pll_locked_m_2, - output tx_user_ready_2, - input tx_user_ready_m_2, - output tx_rst_done_2, - input tx_rst_done_m_2, - output tx_out_clk_2, - input tx_clk_2, - input tx_sysref_2, - input tx_sync_2, - input [31:0] tx_data_2, - input [ 3:0] tx_gt_charisk_2, - input [31:0] tx_gt_data_2, - output tx_ip_rst_2, - output [31:0] tx_ip_data_2, - output tx_ip_sysref_2, - output tx_ip_sync_2, - output tx_ip_rst_done_2, - - output tx_3_p, - output tx_3_n, - output tx_rst_3, - input tx_rst_m_3, - output tx_pll_rst_3, - output tx_gt_rst_3, - input tx_gt_rst_m_3, - output tx_pll_locked_3, - input tx_pll_locked_m_3, - output tx_user_ready_3, - input tx_user_ready_m_3, - output tx_rst_done_3, - input tx_rst_done_m_3, - output tx_out_clk_3, - input tx_clk_3, - input tx_sysref_3, - input tx_sync_3, - input [31:0] tx_data_3, - input [ 3:0] tx_gt_charisk_3, - input [31:0] tx_gt_data_3, - output tx_ip_rst_3, - output [31:0] tx_ip_data_3, - output tx_ip_sysref_3, - output tx_ip_sync_3, - output tx_ip_rst_done_3, - - output tx_4_p, - output tx_4_n, - output tx_rst_4, - input tx_rst_m_4, - output tx_pll_rst_4, - output tx_gt_rst_4, - input tx_gt_rst_m_4, - output tx_pll_locked_4, - input tx_pll_locked_m_4, - output tx_user_ready_4, - input tx_user_ready_m_4, - output tx_rst_done_4, - input tx_rst_done_m_4, - output tx_out_clk_4, - input tx_clk_4, - input tx_sysref_4, - input tx_sync_4, - input [31:0] tx_data_4, - input [ 3:0] tx_gt_charisk_4, - input [31:0] tx_gt_data_4, - output tx_ip_rst_4, - output [31:0] tx_ip_data_4, - output tx_ip_sysref_4, - output tx_ip_sync_4, - output tx_ip_rst_done_4, - - output tx_5_p, - output tx_5_n, - output tx_rst_5, - input tx_rst_m_5, - output tx_pll_rst_5, - output tx_gt_rst_5, - input tx_gt_rst_m_5, - output tx_pll_locked_5, - input tx_pll_locked_m_5, - output tx_user_ready_5, - input tx_user_ready_m_5, - output tx_rst_done_5, - input tx_rst_done_m_5, - output tx_out_clk_5, - input tx_clk_5, - input tx_sysref_5, - input tx_sync_5, - input [31:0] tx_data_5, - input [ 3:0] tx_gt_charisk_5, - input [31:0] tx_gt_data_5, - output tx_ip_rst_5, - output [31:0] tx_ip_data_5, - output tx_ip_sysref_5, - output tx_ip_sync_5, - output tx_ip_rst_done_5, - - output tx_6_p, - output tx_6_n, - output tx_rst_6, - input tx_rst_m_6, - output tx_pll_rst_6, - output tx_gt_rst_6, - input tx_gt_rst_m_6, - output tx_pll_locked_6, - input tx_pll_locked_m_6, - output tx_user_ready_6, - input tx_user_ready_m_6, - output tx_rst_done_6, - input tx_rst_done_m_6, - output tx_out_clk_6, - input tx_clk_6, - input tx_sysref_6, - input tx_sync_6, - input [31:0] tx_data_6, - input [ 3:0] tx_gt_charisk_6, - input [31:0] tx_gt_data_6, - output tx_ip_rst_6, - output [31:0] tx_ip_data_6, - output tx_ip_sysref_6, - output tx_ip_sync_6, - output tx_ip_rst_done_6, - - output tx_7_p, - output tx_7_n, - output tx_rst_7, - input tx_rst_m_7, - output tx_pll_rst_7, - output tx_gt_rst_7, - input tx_gt_rst_m_7, - output tx_pll_locked_7, - input tx_pll_locked_m_7, - output tx_user_ready_7, - input tx_user_ready_m_7, - output tx_rst_done_7, - input tx_rst_done_m_7, - output tx_out_clk_7, - input tx_clk_7, - input tx_sysref_7, - input tx_sync_7, - input [31:0] tx_data_7, - input [ 3:0] tx_gt_charisk_7, - input [31:0] tx_gt_data_7, - output tx_ip_rst_7, - output [31:0] tx_ip_data_7, - output tx_ip_sysref_7, - output tx_ip_sync_7, - output tx_ip_rst_done_7, - - // axi - clock & reset - - input s_axi_aclk, - input s_axi_aresetn, - - // axi interface - - input s_axi_awvalid, - input [ 31:0] s_axi_awaddr, - output s_axi_awready, - input s_axi_wvalid, - input [ 31:0] s_axi_wdata, - input [ 3:0] s_axi_wstrb, - output s_axi_wready, - output s_axi_bvalid, - output [ 1:0] s_axi_bresp, - input s_axi_bready, - input s_axi_arvalid, - input [ 31:0] s_axi_araddr, - output s_axi_arready, - output s_axi_rvalid, - output [ 31:0] s_axi_rdata, - output [ 1:0] s_axi_rresp, - input s_axi_rready, - - // master interface - - output m_axi_awvalid, - output [ 31:0] m_axi_awaddr, - output [ 2:0] m_axi_awprot, - input m_axi_awready, - output m_axi_wvalid, - output [ 31:0] m_axi_wdata, - output [ 3:0] m_axi_wstrb, - input m_axi_wready, - input m_axi_bvalid, - input [ 1:0] m_axi_bresp, - output m_axi_bready, - output m_axi_arvalid, - output [ 31:0] m_axi_araddr, - output [ 2:0] m_axi_arprot, - input m_axi_arready, - input m_axi_rvalid, - input [ 31:0] m_axi_rdata, - input [ 1:0] m_axi_rresp, - output m_axi_rready); - - // post-processing - - localparam [31:0] PMA_RSV[7:0] = {PMA_RSV_7, PMA_RSV_6, PMA_RSV_5, PMA_RSV_4, - PMA_RSV_3, PMA_RSV_2, PMA_RSV_1, PMA_RSV_0}; - localparam integer CPLL_FBDIV[7:0] = {CPLL_FBDIV_7, CPLL_FBDIV_6, CPLL_FBDIV_5, CPLL_FBDIV_4, - CPLL_FBDIV_3, CPLL_FBDIV_2, CPLL_FBDIV_1, CPLL_FBDIV_0}; - - localparam integer RX_OUT_DIV[7:0] = {RX_OUT_DIV_7, RX_OUT_DIV_6, RX_OUT_DIV_5, - RX_OUT_DIV_4, RX_OUT_DIV_3, RX_OUT_DIV_2, RX_OUT_DIV_1, RX_OUT_DIV_0}; - localparam integer RX_CLK25_DIV[7:0] = {RX_CLK25_DIV_7, RX_CLK25_DIV_6, RX_CLK25_DIV_5, - RX_CLK25_DIV_4, RX_CLK25_DIV_3, RX_CLK25_DIV_2, RX_CLK25_DIV_1, RX_CLK25_DIV_0}; - localparam integer RX_CLKBUF_ENABLE[7:0] = {RX_CLKBUF_ENABLE_7, RX_CLKBUF_ENABLE_6, - RX_CLKBUF_ENABLE_5, RX_CLKBUF_ENABLE_4, RX_CLKBUF_ENABLE_3, - RX_CLKBUF_ENABLE_2, RX_CLKBUF_ENABLE_1, RX_CLKBUF_ENABLE_0}; - localparam [71:0] RX_CDR_CFG[7:0] = {RX_CDR_CFG_7, RX_CDR_CFG_6, RX_CDR_CFG_5, - RX_CDR_CFG_4, RX_CDR_CFG_3, RX_CDR_CFG_2, RX_CDR_CFG_1, RX_CDR_CFG_0}; - - localparam integer TX_OUT_DIV[7:0] = {TX_OUT_DIV_7, TX_OUT_DIV_6, TX_OUT_DIV_5, - TX_OUT_DIV_4, TX_OUT_DIV_3, TX_OUT_DIV_2, TX_OUT_DIV_1, TX_OUT_DIV_0}; - localparam integer TX_CLK25_DIV[7:0] = {TX_CLK25_DIV_7, TX_CLK25_DIV_6, TX_CLK25_DIV_5, - TX_CLK25_DIV_4, TX_CLK25_DIV_3, TX_CLK25_DIV_2, TX_CLK25_DIV_1, TX_CLK25_DIV_0}; - localparam integer TX_CLKBUF_ENABLE[7:0] = {TX_CLKBUF_ENABLE_7, TX_CLKBUF_ENABLE_6, - TX_CLKBUF_ENABLE_5, TX_CLKBUF_ENABLE_4, TX_CLKBUF_ENABLE_3, - TX_CLKBUF_ENABLE_2, TX_CLKBUF_ENABLE_1, TX_CLKBUF_ENABLE_0}; - localparam integer TX_DATA_SEL[7:0] = {TX_DATA_SEL_7, TX_DATA_SEL_6, TX_DATA_SEL_5, - TX_DATA_SEL_4, TX_DATA_SEL_3, TX_DATA_SEL_2, TX_DATA_SEL_1, TX_DATA_SEL_0}; - - // internal registers - - reg up_wack_d = 'd0; - reg up_rack_d = 'd0; - reg [ 31:0] up_rdata_d = 'd0; - - // internal signals - - wire [(( 1*8)-1):0] qpll_clk; - wire [(( 1*8)-1):0] qpll_ref_clk; - wire [(( 1*8)-1):0] qpll_locked; - wire [(( 1*8)-1):0] cpll_rst_m; - wire [(( 1*8)-1):0] cpll_ref_clk_in; - wire [(( 1*8)-1):0] rx_p; - wire [(( 1*8)-1):0] rx_n; - wire [(( 1*8)-1):0] rx_out_clk; - wire [(( 1*8)-1):0] rx_clk; - wire [(( 1*8)-1):0] rx_rst; - wire [(( 1*8)-1):0] rx_sof; - wire [((32*8)-1):0] rx_data; - wire [(( 1*8)-1):0] rx_sysref; - wire [(( 1*8)-1):0] rx_sync; - wire [(( 4*8)-1):0] rx_gt_charisk; - wire [(( 4*8)-1):0] rx_gt_disperr; - wire [(( 4*8)-1):0] rx_gt_notintable; - wire [((32*8)-1):0] rx_gt_data; - wire [(( 1*8)-1):0] rx_gt_comma_align_enb; - wire [(( 4*8)-1):0] rx_gt_ilas_f; - wire [(( 4*8)-1):0] rx_gt_ilas_q; - wire [(( 4*8)-1):0] rx_gt_ilas_a; - wire [(( 4*8)-1):0] rx_gt_ilas_r; - wire [(( 4*8)-1):0] rx_gt_cgs_k; - wire [(( 1*8)-1):0] rx_ip_rst; - wire [(( 4*8)-1):0] rx_ip_sof; - wire [((32*8)-1):0] rx_ip_data; - wire [(( 1*8)-1):0] rx_ip_sysref; - wire [(( 1*8)-1):0] rx_ip_sync; - wire [(( 1*8)-1):0] rx_ip_rst_done; - wire [(( 1*8)-1):0] rx_rst_m; - wire [(( 1*8)-1):0] rx_pll_rst; - wire [(( 1*8)-1):0] rx_gt_rst; - wire [(( 1*8)-1):0] rx_gt_rst_m; - wire [(( 1*8)-1):0] rx_user_ready; - wire [(( 1*8)-1):0] rx_rst_done_m; - wire [(( 1*8)-1):0] rx_pll_locked_m; - wire [(( 1*8)-1):0] rx_user_ready_m; - wire [(( 1*8)-1):0] rx_rst_done; - wire [(( 1*8)-1):0] rx_pll_locked; - wire [(( 1*8)-1):0] tx_p; - wire [(( 1*8)-1):0] tx_n; - wire [(( 1*8)-1):0] tx_out_clk; - wire [(( 1*8)-1):0] tx_clk; - wire [(( 1*8)-1):0] tx_rst; - wire [((32*8)-1):0] tx_data; - wire [(( 1*8)-1):0] tx_sysref; - wire [(( 1*8)-1):0] tx_sync; - wire [(( 4*8)-1):0] tx_gt_charisk; - wire [((32*8)-1):0] tx_gt_data; - wire [(( 1*8)-1):0] tx_ip_rst; - wire [((32*8)-1):0] tx_ip_data; - wire [(( 1*8)-1):0] tx_ip_sysref; - wire [(( 1*8)-1):0] tx_ip_sync; - wire [(( 1*8)-1):0] tx_ip_rst_done; - wire [(( 1*8)-1):0] tx_rst_m; - wire [(( 1*8)-1):0] tx_pll_rst; - wire [(( 1*8)-1):0] tx_gt_rst; - wire [(( 1*8)-1):0] tx_gt_rst_m; - wire [(( 1*8)-1):0] tx_user_ready; - wire [(( 1*8)-1):0] tx_rst_done_m; - wire [(( 1*8)-1):0] tx_pll_locked_m; - wire [(( 1*8)-1):0] tx_user_ready_m; - wire [(( 1*8)-1):0] tx_rst_done; - wire [(( 1*8)-1):0] tx_pll_locked; - wire up_rstn; - wire up_clk; - wire up_wreq; - wire [((14*1)-1):0] up_waddr; - wire [((32*1)-1):0] up_wdata; - wire [(( 1*9)-1):0] up_wack; - wire up_rreq; - wire [((14*1)-1):0] up_raddr; - wire [((32*9)-1):0] up_rdata; - wire [(( 1*9)-1):0] up_rack; - wire [(( 1*8)-1):0] up_es_dma_req; - wire [((32*8)-1):0] up_es_dma_addr; - wire [((32*8)-1):0] up_es_dma_data; - wire [(( 1*8)-1):0] up_es_dma_ack; - wire [(( 1*8)-1):0] up_es_dma_err; - - // signal name changes - - assign up_rstn = s_axi_aresetn; - assign up_clk = s_axi_aclk; - - // pll - - assign cpll_rst_m[0] = cpll_rst_m_0; - assign cpll_ref_clk_in[0] = cpll_ref_clk_in_0; - - assign cpll_rst_m[1] = cpll_rst_m_1; - assign cpll_ref_clk_in[1] = cpll_ref_clk_in_1; - - assign cpll_rst_m[2] = cpll_rst_m_2; - assign cpll_ref_clk_in[2] = cpll_ref_clk_in_2; - - assign cpll_rst_m[3] = cpll_rst_m_3; - assign cpll_ref_clk_in[3] = cpll_ref_clk_in_3; - - assign cpll_rst_m[4] = cpll_rst_m_4; - assign cpll_ref_clk_in[4] = cpll_ref_clk_in_4; - - assign cpll_rst_m[5] = cpll_rst_m_5; - assign cpll_ref_clk_in[5] = cpll_ref_clk_in_5; - - assign cpll_rst_m[6] = cpll_rst_m_6; - assign cpll_ref_clk_in[6] = cpll_ref_clk_in_6; - - assign cpll_rst_m[7] = cpll_rst_m_7; - assign cpll_ref_clk_in[7] = cpll_ref_clk_in_7; - - // split-up interfaces - - assign rx_out_clk_0 = rx_out_clk[0]; - assign rx_rst_0 = rx_rst[0]; - assign rx_sof_0 = rx_sof[0]; - assign rx_data_0 = rx_data[((32*0)+31):(32*0)]; - assign rx_sync_0 = rx_sync[0]; - assign rx_gt_charisk_0 = rx_gt_charisk[((4*0)+3):(4*0)]; - assign rx_gt_disperr_0 = rx_gt_disperr[((4*0)+3):(4*0)]; - assign rx_gt_notintable_0 = rx_gt_notintable[((4*0)+3):(4*0)]; - assign rx_gt_data_0 = rx_gt_data[((32*0)+31):(32*0)]; - assign rx_gt_ilas_f_0 = rx_gt_ilas_f[((4*0)+3):(4*0)]; - assign rx_gt_ilas_q_0 = rx_gt_ilas_q[((4*0)+3):(4*0)]; - assign rx_gt_ilas_a_0 = rx_gt_ilas_a[((4*0)+3):(4*0)]; - assign rx_gt_ilas_r_0 = rx_gt_ilas_r[((4*0)+3):(4*0)]; - assign rx_gt_cgs_k_0 = rx_gt_cgs_k[((4*0)+3):(4*0)]; - assign rx_ip_rst_0 = rx_ip_rst[0]; - assign rx_ip_sysref_0 = rx_ip_sysref[0]; - assign rx_ip_rst_done_0 = rx_ip_rst_done[0]; - assign rx_rst_0 = rx_rst[0]; - assign rx_pll_rst_0 = rx_pll_rst[0]; - assign rx_gt_rst_0 = rx_gt_rst[0]; - assign rx_pll_locked_0 = rx_pll_locked[0]; - assign rx_user_ready_0 = rx_user_ready[0]; - assign rx_rst_done_0 = rx_rst_done[0]; - - assign rx_p[0] = rx_0_p; - assign rx_n[0] = rx_0_n; - assign rx_clk[0] = rx_clk_0; - assign rx_sysref[0] = rx_sysref_0; - assign rx_gt_comma_align_enb[0] = rx_gt_comma_align_enb_0; - assign rx_ip_sof[((4*0)+3):(4*0)] = rx_ip_sof_0; - assign rx_ip_data[((32*0)+31):(32*0)] = rx_ip_data_0; - assign rx_ip_sync[0] = rx_ip_sync_0; - assign rx_rst_m[0] = rx_rst_m_0; - assign rx_gt_rst_m[0] = rx_gt_rst_m_0; - assign rx_pll_locked_m[0] = rx_pll_locked_m_0; - assign rx_user_ready_m[0] = rx_user_ready_m_0; - assign rx_rst_done_m[0] = rx_rst_done_m_0; - - assign rx_out_clk_1 = rx_out_clk[1]; - assign rx_rst_1 = rx_rst[1]; - assign rx_sof_1 = rx_sof[1]; - assign rx_data_1 = rx_data[((32*1)+31):(32*1)]; - assign rx_sync_1 = rx_sync[1]; - assign rx_gt_charisk_1 = rx_gt_charisk[((4*1)+3):(4*1)]; - assign rx_gt_disperr_1 = rx_gt_disperr[((4*1)+3):(4*1)]; - assign rx_gt_notintable_1 = rx_gt_notintable[((4*1)+3):(4*1)]; - assign rx_gt_data_1 = rx_gt_data[((32*1)+31):(32*1)]; - assign rx_gt_ilas_f_1 = rx_gt_ilas_f[((4*1)+3):(4*1)]; - assign rx_gt_ilas_q_1 = rx_gt_ilas_q[((4*1)+3):(4*1)]; - assign rx_gt_ilas_a_1 = rx_gt_ilas_a[((4*1)+3):(4*1)]; - assign rx_gt_ilas_r_1 = rx_gt_ilas_r[((4*1)+3):(4*1)]; - assign rx_gt_cgs_k_1 = rx_gt_cgs_k[((4*1)+3):(4*1)]; - assign rx_ip_rst_1 = rx_ip_rst[1]; - assign rx_ip_sysref_1 = rx_ip_sysref[1]; - assign rx_ip_rst_done_1 = rx_ip_rst_done[1]; - assign rx_rst_1 = rx_rst[1]; - assign rx_pll_rst_1 = rx_pll_rst[1]; - assign rx_gt_rst_1 = rx_gt_rst[1]; - assign rx_pll_locked_1 = rx_pll_locked[1]; - assign rx_user_ready_1 = rx_user_ready[1]; - assign rx_rst_done_1 = rx_rst_done[1]; - - assign rx_p[1] = rx_1_p; - assign rx_n[1] = rx_1_n; - assign rx_clk[1] = rx_clk_1; - assign rx_sysref[1] = rx_sysref_1; - assign rx_gt_comma_align_enb[1] = rx_gt_comma_align_enb_1; - assign rx_ip_sof[((4*1)+3):(4*1)] = rx_ip_sof_1; - assign rx_ip_data[((32*1)+31):(32*1)] = rx_ip_data_1; - assign rx_ip_sync[1] = rx_ip_sync_1; - assign rx_rst_m[1] = rx_rst_m_1; - assign rx_gt_rst_m[1] = rx_gt_rst_m_1; - assign rx_pll_locked_m[1] = rx_pll_locked_m_1; - assign rx_user_ready_m[1] = rx_user_ready_m_1; - assign rx_rst_done_m[1] = rx_rst_done_m_1; - - assign rx_out_clk_2 = rx_out_clk[2]; - assign rx_rst_2 = rx_rst[2]; - assign rx_sof_2 = rx_sof[2]; - assign rx_data_2 = rx_data[((32*2)+31):(32*2)]; - assign rx_sync_2 = rx_sync[2]; - assign rx_gt_charisk_2 = rx_gt_charisk[((4*2)+3):(4*2)]; - assign rx_gt_disperr_2 = rx_gt_disperr[((4*2)+3):(4*2)]; - assign rx_gt_notintable_2 = rx_gt_notintable[((4*2)+3):(4*2)]; - assign rx_gt_data_2 = rx_gt_data[((32*2)+31):(32*2)]; - assign rx_gt_ilas_f_2 = rx_gt_ilas_f[((4*2)+3):(4*2)]; - assign rx_gt_ilas_q_2 = rx_gt_ilas_q[((4*2)+3):(4*2)]; - assign rx_gt_ilas_a_2 = rx_gt_ilas_a[((4*2)+3):(4*2)]; - assign rx_gt_ilas_r_2 = rx_gt_ilas_r[((4*2)+3):(4*2)]; - assign rx_gt_cgs_k_2 = rx_gt_cgs_k[((4*2)+3):(4*2)]; - assign rx_ip_rst_2 = rx_ip_rst[2]; - assign rx_ip_sysref_2 = rx_ip_sysref[2]; - assign rx_ip_rst_done_2 = rx_ip_rst_done[2]; - assign rx_rst_2 = rx_rst[2]; - assign rx_pll_rst_2 = rx_pll_rst[2]; - assign rx_gt_rst_2 = rx_gt_rst[2]; - assign rx_pll_locked_2 = rx_pll_locked[2]; - assign rx_user_ready_2 = rx_user_ready[2]; - assign rx_rst_done_2 = rx_rst_done[2]; - - assign rx_p[2] = rx_2_p; - assign rx_n[2] = rx_2_n; - assign rx_clk[2] = rx_clk_2; - assign rx_sysref[2] = rx_sysref_2; - assign rx_gt_comma_align_enb[2] = rx_gt_comma_align_enb_2; - assign rx_ip_sof[((4*2)+3):(4*2)] = rx_ip_sof_2; - assign rx_ip_data[((32*2)+31):(32*2)] = rx_ip_data_2; - assign rx_ip_sync[2] = rx_ip_sync_2; - assign rx_rst_m[2] = rx_rst_m_2; - assign rx_gt_rst_m[2] = rx_gt_rst_m_2; - assign rx_pll_locked_m[2] = rx_pll_locked_m_2; - assign rx_user_ready_m[2] = rx_user_ready_m_2; - assign rx_rst_done_m[2] = rx_rst_done_m_2; - - assign rx_out_clk_3 = rx_out_clk[3]; - assign rx_rst_3 = rx_rst[3]; - assign rx_sof_3 = rx_sof[3]; - assign rx_data_3 = rx_data[((32*3)+31):(32*3)]; - assign rx_sync_3 = rx_sync[3]; - assign rx_gt_charisk_3 = rx_gt_charisk[((4*3)+3):(4*3)]; - assign rx_gt_disperr_3 = rx_gt_disperr[((4*3)+3):(4*3)]; - assign rx_gt_notintable_3 = rx_gt_notintable[((4*3)+3):(4*3)]; - assign rx_gt_data_3 = rx_gt_data[((32*3)+31):(32*3)]; - assign rx_gt_ilas_f_3 = rx_gt_ilas_f[((4*3)+3):(4*3)]; - assign rx_gt_ilas_q_3 = rx_gt_ilas_q[((4*3)+3):(4*3)]; - assign rx_gt_ilas_a_3 = rx_gt_ilas_a[((4*3)+3):(4*3)]; - assign rx_gt_ilas_r_3 = rx_gt_ilas_r[((4*3)+3):(4*3)]; - assign rx_gt_cgs_k_3 = rx_gt_cgs_k[((4*3)+3):(4*3)]; - assign rx_ip_rst_3 = rx_ip_rst[3]; - assign rx_ip_sysref_3 = rx_ip_sysref[3]; - assign rx_ip_rst_done_3 = rx_ip_rst_done[3]; - assign rx_rst_3 = rx_rst[3]; - assign rx_pll_rst_3 = rx_pll_rst[3]; - assign rx_gt_rst_3 = rx_gt_rst[3]; - assign rx_pll_locked_3 = rx_pll_locked[3]; - assign rx_user_ready_3 = rx_user_ready[3]; - assign rx_rst_done_3 = rx_rst_done[3]; - - assign rx_p[3] = rx_3_p; - assign rx_n[3] = rx_3_n; - assign rx_clk[3] = rx_clk_3; - assign rx_sysref[3] = rx_sysref_3; - assign rx_gt_comma_align_enb[3] = rx_gt_comma_align_enb_3; - assign rx_ip_sof[((4*3)+3):(4*3)] = rx_ip_sof_3; - assign rx_ip_data[((32*3)+31):(32*3)] = rx_ip_data_3; - assign rx_ip_sync[3] = rx_ip_sync_3; - assign rx_rst_m[3] = rx_rst_m_3; - assign rx_gt_rst_m[3] = rx_gt_rst_m_3; - assign rx_pll_locked_m[3] = rx_pll_locked_m_3; - assign rx_user_ready_m[3] = rx_user_ready_m_3; - assign rx_rst_done_m[3] = rx_rst_done_m_3; - - assign rx_out_clk_4 = rx_out_clk[4]; - assign rx_rst_4 = rx_rst[4]; - assign rx_sof_4 = rx_sof[4]; - assign rx_data_4 = rx_data[((32*4)+31):(32*4)]; - assign rx_sync_4 = rx_sync[4]; - assign rx_gt_charisk_4 = rx_gt_charisk[((4*4)+3):(4*4)]; - assign rx_gt_disperr_4 = rx_gt_disperr[((4*4)+3):(4*4)]; - assign rx_gt_notintable_4 = rx_gt_notintable[((4*4)+3):(4*4)]; - assign rx_gt_data_4 = rx_gt_data[((32*4)+31):(32*4)]; - assign rx_gt_ilas_f_4 = rx_gt_ilas_f[((4*4)+3):(4*4)]; - assign rx_gt_ilas_q_4 = rx_gt_ilas_q[((4*4)+3):(4*4)]; - assign rx_gt_ilas_a_4 = rx_gt_ilas_a[((4*4)+3):(4*4)]; - assign rx_gt_ilas_r_4 = rx_gt_ilas_r[((4*4)+3):(4*4)]; - assign rx_gt_cgs_k_4 = rx_gt_cgs_k[((4*4)+3):(4*4)]; - assign rx_ip_rst_4 = rx_ip_rst[4]; - assign rx_ip_sysref_4 = rx_ip_sysref[4]; - assign rx_ip_rst_done_4 = rx_ip_rst_done[4]; - assign rx_rst_4 = rx_rst[4]; - assign rx_pll_rst_4 = rx_pll_rst[4]; - assign rx_gt_rst_4 = rx_gt_rst[4]; - assign rx_pll_locked_4 = rx_pll_locked[4]; - assign rx_user_ready_4 = rx_user_ready[4]; - assign rx_rst_done_4 = rx_rst_done[4]; - - assign rx_p[4] = rx_4_p; - assign rx_n[4] = rx_4_n; - assign rx_clk[4] = rx_clk_4; - assign rx_sysref[4] = rx_sysref_4; - assign rx_gt_comma_align_enb[4] = rx_gt_comma_align_enb_4; - assign rx_ip_sof[((4*4)+3):(4*4)] = rx_ip_sof_4; - assign rx_ip_data[((32*4)+31):(32*4)] = rx_ip_data_4; - assign rx_ip_sync[4] = rx_ip_sync_4; - assign rx_rst_m[4] = rx_rst_m_4; - assign rx_gt_rst_m[4] = rx_gt_rst_m_4; - assign rx_pll_locked_m[4] = rx_pll_locked_m_4; - assign rx_user_ready_m[4] = rx_user_ready_m_4; - assign rx_rst_done_m[4] = rx_rst_done_m_4; - - assign rx_out_clk_5 = rx_out_clk[5]; - assign rx_rst_5 = rx_rst[5]; - assign rx_sof_5 = rx_sof[5]; - assign rx_data_5 = rx_data[((32*5)+31):(32*5)]; - assign rx_sync_5 = rx_sync[5]; - assign rx_gt_charisk_5 = rx_gt_charisk[((4*5)+3):(4*5)]; - assign rx_gt_disperr_5 = rx_gt_disperr[((4*5)+3):(4*5)]; - assign rx_gt_notintable_5 = rx_gt_notintable[((4*5)+3):(4*5)]; - assign rx_gt_data_5 = rx_gt_data[((32*5)+31):(32*5)]; - assign rx_gt_ilas_f_5 = rx_gt_ilas_f[((4*5)+3):(4*5)]; - assign rx_gt_ilas_q_5 = rx_gt_ilas_q[((4*5)+3):(4*5)]; - assign rx_gt_ilas_a_5 = rx_gt_ilas_a[((4*5)+3):(4*5)]; - assign rx_gt_ilas_r_5 = rx_gt_ilas_r[((4*5)+3):(4*5)]; - assign rx_gt_cgs_k_5 = rx_gt_cgs_k[((4*5)+3):(4*5)]; - assign rx_ip_rst_5 = rx_ip_rst[5]; - assign rx_ip_sysref_5 = rx_ip_sysref[5]; - assign rx_ip_rst_done_5 = rx_ip_rst_done[5]; - assign rx_rst_5 = rx_rst[5]; - assign rx_pll_rst_5 = rx_pll_rst[5]; - assign rx_gt_rst_5 = rx_gt_rst[5]; - assign rx_pll_locked_5 = rx_pll_locked[5]; - assign rx_user_ready_5 = rx_user_ready[5]; - assign rx_rst_done_5 = rx_rst_done[5]; - - assign rx_p[5] = rx_5_p; - assign rx_n[5] = rx_5_n; - assign rx_clk[5] = rx_clk_5; - assign rx_sysref[5] = rx_sysref_5; - assign rx_gt_comma_align_enb[5] = rx_gt_comma_align_enb_5; - assign rx_ip_sof[((4*5)+3):(4*5)] = rx_ip_sof_5; - assign rx_ip_data[((32*5)+31):(32*5)] = rx_ip_data_5; - assign rx_ip_sync[5] = rx_ip_sync_5; - assign rx_rst_m[5] = rx_rst_m_5; - assign rx_gt_rst_m[5] = rx_gt_rst_m_5; - assign rx_pll_locked_m[5] = rx_pll_locked_m_5; - assign rx_user_ready_m[5] = rx_user_ready_m_5; - assign rx_rst_done_m[5] = rx_rst_done_m_5; - - assign rx_out_clk_6 = rx_out_clk[6]; - assign rx_rst_6 = rx_rst[6]; - assign rx_sof_6 = rx_sof[6]; - assign rx_data_6 = rx_data[((32*6)+31):(32*6)]; - assign rx_sync_6 = rx_sync[6]; - assign rx_gt_charisk_6 = rx_gt_charisk[((4*6)+3):(4*6)]; - assign rx_gt_disperr_6 = rx_gt_disperr[((4*6)+3):(4*6)]; - assign rx_gt_notintable_6 = rx_gt_notintable[((4*6)+3):(4*6)]; - assign rx_gt_data_6 = rx_gt_data[((32*6)+31):(32*6)]; - assign rx_gt_ilas_f_6 = rx_gt_ilas_f[((4*6)+3):(4*6)]; - assign rx_gt_ilas_q_6 = rx_gt_ilas_q[((4*6)+3):(4*6)]; - assign rx_gt_ilas_a_6 = rx_gt_ilas_a[((4*6)+3):(4*6)]; - assign rx_gt_ilas_r_6 = rx_gt_ilas_r[((4*6)+3):(4*6)]; - assign rx_gt_cgs_k_6 = rx_gt_cgs_k[((4*6)+3):(4*6)]; - assign rx_ip_rst_6 = rx_ip_rst[6]; - assign rx_ip_sysref_6 = rx_ip_sysref[6]; - assign rx_ip_rst_done_6 = rx_ip_rst_done[6]; - assign rx_rst_6 = rx_rst[6]; - assign rx_pll_rst_6 = rx_pll_rst[6]; - assign rx_gt_rst_6 = rx_gt_rst[6]; - assign rx_pll_locked_6 = rx_pll_locked[6]; - assign rx_user_ready_6 = rx_user_ready[6]; - assign rx_rst_done_6 = rx_rst_done[6]; - - assign rx_p[6] = rx_6_p; - assign rx_n[6] = rx_6_n; - assign rx_clk[6] = rx_clk_6; - assign rx_sysref[6] = rx_sysref_6; - assign rx_gt_comma_align_enb[6] = rx_gt_comma_align_enb_6; - assign rx_ip_sof[((4*6)+3):(4*6)] = rx_ip_sof_6; - assign rx_ip_data[((32*6)+31):(32*6)] = rx_ip_data_6; - assign rx_ip_sync[6] = rx_ip_sync_6; - assign rx_rst_m[6] = rx_rst_m_6; - assign rx_gt_rst_m[6] = rx_gt_rst_m_6; - assign rx_pll_locked_m[6] = rx_pll_locked_m_6; - assign rx_user_ready_m[6] = rx_user_ready_m_6; - assign rx_rst_done_m[6] = rx_rst_done_m_6; - - assign rx_out_clk_7 = rx_out_clk[7]; - assign rx_rst_7 = rx_rst[7]; - assign rx_sof_7 = rx_sof[7]; - assign rx_data_7 = rx_data[((32*7)+31):(32*7)]; - assign rx_sync_7 = rx_sync[7]; - assign rx_gt_charisk_7 = rx_gt_charisk[((4*7)+3):(4*7)]; - assign rx_gt_disperr_7 = rx_gt_disperr[((4*7)+3):(4*7)]; - assign rx_gt_notintable_7 = rx_gt_notintable[((4*7)+3):(4*7)]; - assign rx_gt_data_7 = rx_gt_data[((32*7)+31):(32*7)]; - assign rx_gt_ilas_f_7 = rx_gt_ilas_f[((4*7)+3):(4*7)]; - assign rx_gt_ilas_q_7 = rx_gt_ilas_q[((4*7)+3):(4*7)]; - assign rx_gt_ilas_a_7 = rx_gt_ilas_a[((4*7)+3):(4*7)]; - assign rx_gt_ilas_r_7 = rx_gt_ilas_r[((4*7)+3):(4*7)]; - assign rx_gt_cgs_k_7 = rx_gt_cgs_k[((4*7)+3):(4*7)]; - assign rx_ip_rst_7 = rx_ip_rst[7]; - assign rx_ip_sysref_7 = rx_ip_sysref[7]; - assign rx_ip_rst_done_7 = rx_ip_rst_done[7]; - assign rx_rst_7 = rx_rst[7]; - assign rx_pll_rst_7 = rx_pll_rst[7]; - assign rx_gt_rst_7 = rx_gt_rst[7]; - assign rx_pll_locked_7 = rx_pll_locked[7]; - assign rx_user_ready_7 = rx_user_ready[7]; - assign rx_rst_done_7 = rx_rst_done[7]; - - assign rx_p[7] = rx_7_p; - assign rx_n[7] = rx_7_n; - assign rx_clk[7] = rx_clk_7; - assign rx_sysref[7] = rx_sysref_7; - assign rx_gt_comma_align_enb[7] = rx_gt_comma_align_enb_7; - assign rx_ip_sof[((4*7)+3):(4*7)] = rx_ip_sof_7; - assign rx_ip_data[((32*7)+31):(32*7)] = rx_ip_data_7; - assign rx_ip_sync[7] = rx_ip_sync_7; - assign rx_rst_m[7] = rx_rst_m_7; - assign rx_gt_rst_m[7] = rx_gt_rst_m_7; - assign rx_pll_locked_m[7] = rx_pll_locked_m_7; - assign rx_user_ready_m[7] = rx_user_ready_m_7; - assign rx_rst_done_m[7] = rx_rst_done_m_7; - - assign tx_0_p = tx_p[0]; - assign tx_0_n = tx_n[0]; - assign tx_out_clk_0 = tx_out_clk[0]; - assign tx_rst_0 = tx_rst[0]; - assign tx_ip_rst_0 = tx_ip_rst[0]; - assign tx_ip_data_0 = tx_ip_data[((32*0)+31):(32*0)]; - assign tx_ip_sysref_0 = tx_ip_sysref[0]; - assign tx_ip_sync_0 = tx_ip_sync[0]; - assign tx_ip_rst_done_0 = tx_ip_rst_done[0]; - assign tx_rst_0 = tx_rst[0]; - assign tx_pll_rst_0 = tx_pll_rst[0]; - assign tx_gt_rst_0 = tx_gt_rst[0]; - assign tx_pll_locked_0 = tx_pll_locked[0]; - assign tx_user_ready_0 = tx_user_ready[0]; - assign tx_rst_done_0 = tx_rst_done[0]; - - assign tx_clk[0] = tx_clk_0; - assign tx_data[((32*0)+31):(32*0)] = tx_data_0; - assign tx_sysref[0] = tx_sysref_0; - assign tx_sync[0] = tx_sync_0; - assign tx_gt_charisk[((4*0)+3):(4*0)] = tx_gt_charisk_0; - assign tx_gt_data[((32*0)+31):(32*0)] = tx_gt_data_0; - assign tx_rst_m[0] = tx_rst_m_0; - assign tx_gt_rst_m[0] = tx_gt_rst_m_0; - assign tx_pll_locked_m[0] = tx_pll_locked_m_0; - assign tx_user_ready_m[0] = tx_user_ready_m_0; - assign tx_rst_done_m[0] = tx_rst_done_m_0; - - assign tx_1_p = tx_p[1]; - assign tx_1_n = tx_n[1]; - assign tx_out_clk_1 = tx_out_clk[1]; - assign tx_rst_1 = tx_rst[1]; - assign tx_ip_rst_1 = tx_ip_rst[1]; - assign tx_ip_data_1 = tx_ip_data[((32*1)+31):(32*1)]; - assign tx_ip_sysref_1 = tx_ip_sysref[1]; - assign tx_ip_sync_1 = tx_ip_sync[1]; - assign tx_ip_rst_done_1 = tx_ip_rst_done[1]; - assign tx_rst_1 = tx_rst[1]; - assign tx_pll_rst_1 = tx_pll_rst[1]; - assign tx_gt_rst_1 = tx_gt_rst[1]; - assign tx_pll_locked_1 = tx_pll_locked[1]; - assign tx_user_ready_1 = tx_user_ready[1]; - assign tx_rst_done_1 = tx_rst_done[1]; - - assign tx_clk[1] = tx_clk_1; - assign tx_data[((32*1)+31):(32*1)] = tx_data_1; - assign tx_sysref[1] = tx_sysref_1; - assign tx_sync[1] = tx_sync_1; - assign tx_gt_charisk[((4*1)+3):(4*1)] = tx_gt_charisk_1; - assign tx_gt_data[((32*1)+31):(32*1)] = tx_gt_data_1; - assign tx_rst_m[1] = tx_rst_m_1; - assign tx_gt_rst_m[1] = tx_gt_rst_m_1; - assign tx_pll_locked_m[1] = tx_pll_locked_m_1; - assign tx_user_ready_m[1] = tx_user_ready_m_1; - assign tx_rst_done_m[1] = tx_rst_done_m_1; - - assign tx_2_p = tx_p[2]; - assign tx_2_n = tx_n[2]; - assign tx_out_clk_2 = tx_out_clk[2]; - assign tx_rst_2 = tx_rst[2]; - assign tx_ip_rst_2 = tx_ip_rst[2]; - assign tx_ip_data_2 = tx_ip_data[((32*2)+31):(32*2)]; - assign tx_ip_sysref_2 = tx_ip_sysref[2]; - assign tx_ip_sync_2 = tx_ip_sync[2]; - assign tx_ip_rst_done_2 = tx_ip_rst_done[2]; - assign tx_rst_2 = tx_rst[2]; - assign tx_pll_rst_2 = tx_pll_rst[2]; - assign tx_gt_rst_2 = tx_gt_rst[2]; - assign tx_pll_locked_2 = tx_pll_locked[2]; - assign tx_user_ready_2 = tx_user_ready[2]; - assign tx_rst_done_2 = tx_rst_done[2]; - - assign tx_clk[2] = tx_clk_2; - assign tx_data[((32*2)+31):(32*2)] = tx_data_2; - assign tx_sysref[2] = tx_sysref_2; - assign tx_sync[2] = tx_sync_2; - assign tx_gt_charisk[((4*2)+3):(4*2)] = tx_gt_charisk_2; - assign tx_gt_data[((32*2)+31):(32*2)] = tx_gt_data_2; - assign tx_rst_m[2] = tx_rst_m_2; - assign tx_gt_rst_m[2] = tx_gt_rst_m_2; - assign tx_pll_locked_m[2] = tx_pll_locked_m_2; - assign tx_user_ready_m[2] = tx_user_ready_m_2; - assign tx_rst_done_m[2] = tx_rst_done_m_2; - - assign tx_3_p = tx_p[3]; - assign tx_3_n = tx_n[3]; - assign tx_out_clk_3 = tx_out_clk[3]; - assign tx_rst_3 = tx_rst[3]; - assign tx_ip_rst_3 = tx_ip_rst[3]; - assign tx_ip_data_3 = tx_ip_data[((32*3)+31):(32*3)]; - assign tx_ip_sysref_3 = tx_ip_sysref[3]; - assign tx_ip_sync_3 = tx_ip_sync[3]; - assign tx_ip_rst_done_3 = tx_ip_rst_done[3]; - assign tx_rst_3 = tx_rst[3]; - assign tx_pll_rst_3 = tx_pll_rst[3]; - assign tx_gt_rst_3 = tx_gt_rst[3]; - assign tx_pll_locked_3 = tx_pll_locked[3]; - assign tx_user_ready_3 = tx_user_ready[3]; - assign tx_rst_done_3 = tx_rst_done[3]; - - assign tx_clk[3] = tx_clk_3; - assign tx_data[((32*3)+31):(32*3)] = tx_data_3; - assign tx_sysref[3] = tx_sysref_3; - assign tx_sync[3] = tx_sync_3; - assign tx_gt_charisk[((4*3)+3):(4*3)] = tx_gt_charisk_3; - assign tx_gt_data[((32*3)+31):(32*3)] = tx_gt_data_3; - assign tx_rst_m[3] = tx_rst_m_3; - assign tx_gt_rst_m[3] = tx_gt_rst_m_3; - assign tx_pll_locked_m[3] = tx_pll_locked_m_3; - assign tx_user_ready_m[3] = tx_user_ready_m_3; - assign tx_rst_done_m[3] = tx_rst_done_m_3; - - assign tx_4_p = tx_p[4]; - assign tx_4_n = tx_n[4]; - assign tx_out_clk_4 = tx_out_clk[4]; - assign tx_rst_4 = tx_rst[4]; - assign tx_ip_rst_4 = tx_ip_rst[4]; - assign tx_ip_data_4 = tx_ip_data[((32*4)+31):(32*4)]; - assign tx_ip_sysref_4 = tx_ip_sysref[4]; - assign tx_ip_sync_4 = tx_ip_sync[4]; - assign tx_ip_rst_done_4 = tx_ip_rst_done[4]; - assign tx_rst_4 = tx_rst[4]; - assign tx_pll_rst_4 = tx_pll_rst[4]; - assign tx_gt_rst_4 = tx_gt_rst[4]; - assign tx_pll_locked_4 = tx_pll_locked[4]; - assign tx_user_ready_4 = tx_user_ready[4]; - assign tx_rst_done_4 = tx_rst_done[4]; - - assign tx_clk[4] = tx_clk_4; - assign tx_data[((32*4)+31):(32*4)] = tx_data_4; - assign tx_sysref[4] = tx_sysref_4; - assign tx_sync[4] = tx_sync_4; - assign tx_gt_charisk[((4*4)+3):(4*4)] = tx_gt_charisk_4; - assign tx_gt_data[((32*4)+31):(32*4)] = tx_gt_data_4; - assign tx_rst_m[4] = tx_rst_m_4; - assign tx_gt_rst_m[4] = tx_gt_rst_m_4; - assign tx_pll_locked_m[4] = tx_pll_locked_m_4; - assign tx_user_ready_m[4] = tx_user_ready_m_4; - assign tx_rst_done_m[4] = tx_rst_done_m_4; - - assign tx_5_p = tx_p[5]; - assign tx_5_n = tx_n[5]; - assign tx_out_clk_5 = tx_out_clk[5]; - assign tx_rst_5 = tx_rst[5]; - assign tx_ip_rst_5 = tx_ip_rst[5]; - assign tx_ip_data_5 = tx_ip_data[((32*5)+31):(32*5)]; - assign tx_ip_sysref_5 = tx_ip_sysref[5]; - assign tx_ip_sync_5 = tx_ip_sync[5]; - assign tx_ip_rst_done_5 = tx_ip_rst_done[5]; - assign tx_rst_5 = tx_rst[5]; - assign tx_pll_rst_5 = tx_pll_rst[5]; - assign tx_gt_rst_5 = tx_gt_rst[5]; - assign tx_pll_locked_5 = tx_pll_locked[5]; - assign tx_user_ready_5 = tx_user_ready[5]; - assign tx_rst_done_5 = tx_rst_done[5]; - - assign tx_clk[5] = tx_clk_5; - assign tx_data[((32*5)+31):(32*5)] = tx_data_5; - assign tx_sysref[5] = tx_sysref_5; - assign tx_sync[5] = tx_sync_5; - assign tx_gt_charisk[((4*5)+3):(4*5)] = tx_gt_charisk_5; - assign tx_gt_data[((32*5)+31):(32*5)] = tx_gt_data_5; - assign tx_rst_m[5] = tx_rst_m_5; - assign tx_gt_rst_m[5] = tx_gt_rst_m_5; - assign tx_pll_locked_m[5] = tx_pll_locked_m_5; - assign tx_user_ready_m[5] = tx_user_ready_m_5; - assign tx_rst_done_m[5] = tx_rst_done_m_5; - - assign tx_6_p = tx_p[6]; - assign tx_6_n = tx_n[6]; - assign tx_out_clk_6 = tx_out_clk[6]; - assign tx_rst_6 = tx_rst[6]; - assign tx_ip_rst_6 = tx_ip_rst[6]; - assign tx_ip_data_6 = tx_ip_data[((32*6)+31):(32*6)]; - assign tx_ip_sysref_6 = tx_ip_sysref[6]; - assign tx_ip_sync_6 = tx_ip_sync[6]; - assign tx_ip_rst_done_6 = tx_ip_rst_done[6]; - assign tx_rst_6 = tx_rst[6]; - assign tx_pll_rst_6 = tx_pll_rst[6]; - assign tx_gt_rst_6 = tx_gt_rst[6]; - assign tx_pll_locked_6 = tx_pll_locked[6]; - assign tx_user_ready_6 = tx_user_ready[6]; - assign tx_rst_done_6 = tx_rst_done[6]; - - assign tx_clk[6] = tx_clk_6; - assign tx_data[((32*6)+31):(32*6)] = tx_data_6; - assign tx_sysref[6] = tx_sysref_6; - assign tx_sync[6] = tx_sync_6; - assign tx_gt_charisk[((4*6)+3):(4*6)] = tx_gt_charisk_6; - assign tx_gt_data[((32*6)+31):(32*6)] = tx_gt_data_6; - assign tx_rst_m[6] = tx_rst_m_6; - assign tx_gt_rst_m[6] = tx_gt_rst_m_6; - assign tx_pll_locked_m[6] = tx_pll_locked_m_6; - assign tx_user_ready_m[6] = tx_user_ready_m_6; - assign tx_rst_done_m[6] = tx_rst_done_m_6; - - assign tx_7_p = tx_p[7]; - assign tx_7_n = tx_n[7]; - assign tx_out_clk_7 = tx_out_clk[7]; - assign tx_rst_7 = tx_rst[7]; - assign tx_ip_rst_7 = tx_ip_rst[7]; - assign tx_ip_data_7 = tx_ip_data[((32*7)+31):(32*7)]; - assign tx_ip_sysref_7 = tx_ip_sysref[7]; - assign tx_ip_sync_7 = tx_ip_sync[7]; - assign tx_ip_rst_done_7 = tx_ip_rst_done[7]; - assign tx_rst_7 = tx_rst[7]; - assign tx_pll_rst_7 = tx_pll_rst[7]; - assign tx_gt_rst_7 = tx_gt_rst[7]; - assign tx_pll_locked_7 = tx_pll_locked[7]; - assign tx_user_ready_7 = tx_user_ready[7]; - assign tx_rst_done_7 = tx_rst_done[7]; - - assign tx_clk[7] = tx_clk_7; - assign tx_data[((32*7)+31):(32*7)] = tx_data_7; - assign tx_sysref[7] = tx_sysref_7; - assign tx_sync[7] = tx_sync_7; - assign tx_gt_charisk[((4*7)+3):(4*7)] = tx_gt_charisk_7; - assign tx_gt_data[((32*7)+31):(32*7)] = tx_gt_data_7; - assign tx_rst_m[7] = tx_rst_m_7; - assign tx_gt_rst_m[7] = tx_gt_rst_m_7; - assign tx_pll_locked_m[7] = tx_pll_locked_m_7; - assign tx_user_ready_m[7] = tx_user_ready_m_7; - assign tx_rst_done_m[7] = tx_rst_done_m_7; - - // up signals - - always @(posedge up_clk or negedge up_rstn) begin - if (up_rstn == 1'b0) begin - up_wack_d <= 1'd0; - up_rack_d <= 1'd0; - up_rdata_d <= 32'd0; - end else begin - up_wack_d <= | up_wack; - up_rack_d <= | up_rack; - up_rdata_d <= up_rdata[((32*0)+31):(32*0)] | - up_rdata[((32*1)+31):(32*1)] | - up_rdata[((32*2)+31):(32*2)] | - up_rdata[((32*3)+31):(32*3)] | - up_rdata[((32*4)+31):(32*4)] | - up_rdata[((32*5)+31):(32*5)] | - up_rdata[((32*6)+31):(32*6)] | - up_rdata[((32*7)+31):(32*7)] | - up_rdata[((32*8)+31):(32*8)]; - end - end - - // instantiations - - genvar n; - generate - - if (NUM_OF_LANES < 8) begin - for (n = NUM_OF_LANES; n < 8; n = n + 1) begin: g_unused_1 - assign rx_rst[n] = 1'd0; - assign rx_pll_rst[n] = 1'd0; - assign rx_gt_rst[n] = 1'd0; - assign rx_pll_locked[n] = 1'd0; - assign rx_user_ready[n] = 1'd0; - assign rx_rst_done[n] = 1'd0; - assign rx_out_clk[n] = 1'd0; - assign rx_rst[n] = 1'd0; - assign rx_sync[n] = 1'd0; - assign rx_sof[n] = 1'd0; - assign rx_data[((32*n)+31):(32*n)] = 32'd0; - assign rx_gt_charisk[((4*n)+3):(4*n)] = 4'd0; - assign rx_gt_disperr[((4*n)+3):(4*n)] = 4'd0; - assign rx_gt_notintable[((4*n)+3):(4*n)] = 4'd0; - assign rx_gt_data[((32*n)+31):(32*n)] = 32'd0; - assign rx_gt_ilas_f[((4*n)+3):(4*n)] = 4'd0; - assign rx_gt_ilas_q[((4*n)+3):(4*n)] = 4'd0; - assign rx_gt_ilas_a[((4*n)+3):(4*n)] = 4'd0; - assign rx_gt_ilas_r[((4*n)+3):(4*n)] = 4'd0; - assign rx_gt_cgs_k[((4*n)+3):(4*n)] = 4'd0; - assign rx_ip_rst[n] = 1'd0; - assign rx_ip_sysref[n] = 1'd0; - assign rx_ip_rst_done[n] = 1'd0; - assign tx_p[n] = 1'd0; - assign tx_n[n] = 1'd1; - assign tx_rst[n] = 1'd0; - assign tx_pll_rst[n] = 1'd0; - assign tx_gt_rst[n] = 1'd0; - assign tx_pll_locked[n] = 1'd0; - assign tx_user_ready[n] = 1'd0; - assign tx_rst_done[n] = 1'd0; - assign tx_out_clk[n] = 1'd0; - assign tx_rst[n] = 1'd0; - assign tx_ip_rst[n] = 1'd0; - assign tx_ip_data[((32*n)+31):(32*n)] = 32'd0; - assign tx_ip_sysref[n] = 1'd0; - assign tx_ip_sync[n] = 1'd0; - assign tx_ip_rst_done[n] = 1'd0; - end - end - - for (n = 0; n < NUM_OF_LANES; n = n + 1) begin: g_lane_1 - ad_gt_channel_1 #( - .ID (n), - .GTH_OR_GTX_N (GTH_OR_GTX_N), - .PMA_RSV (PMA_RSV[n]), - .CPLL_FBDIV (CPLL_FBDIV[n]), - .RX_OUT_DIV (RX_OUT_DIV[n]), - .RX_CLK25_DIV (RX_CLK25_DIV[n]), - .RX_CLKBUF_ENABLE (RX_CLKBUF_ENABLE[n]), - .RX_CDR_CFG (RX_CDR_CFG[n]), - .TX_OUT_DIV (TX_OUT_DIV[n]), - .TX_CLK25_DIV (TX_CLK25_DIV[n]), - .TX_CLKBUF_ENABLE (TX_CLKBUF_ENABLE[n])) - i_channel ( - .cpll_rst_m (cpll_rst_m[n]), - .cpll_ref_clk_in (cpll_ref_clk_in[n]), - .qpll_ref_clk (qpll_ref_clk[n]), - .qpll_locked (qpll_locked[n]), - .qpll_clk (qpll_clk[n]), - .rx_p (rx_p[n]), - .rx_n (rx_n[n]), - .rx_out_clk (rx_out_clk[n]), - .rx_clk (rx_clk[n]), - .rx_rst (rx_rst[n]), - .rx_rst_m (rx_rst_m[n]), - .rx_sof (rx_sof[n]), - .rx_data (rx_data[((32*n)+31):(32*n)]), - .rx_sysref (rx_sysref[n]), - .rx_sync (rx_sync[n]), - .rx_pll_rst (rx_pll_rst[n]), - .rx_gt_rst (rx_gt_rst[n]), - .rx_gt_rst_m (rx_gt_rst_m[n]), - .rx_gt_charisk (rx_gt_charisk[((4*n)+3):(4*n)]), - .rx_gt_disperr (rx_gt_disperr[((4*n)+3):(4*n)]), - .rx_gt_notintable (rx_gt_notintable[((4*n)+3):(4*n)]), - .rx_gt_data (rx_gt_data[((32*n)+31):(32*n)]), - .rx_gt_comma_align_enb (rx_gt_comma_align_enb[n]), - .rx_gt_ilas_f (rx_gt_ilas_f[((4*n)+3):(4*n)]), - .rx_gt_ilas_q (rx_gt_ilas_q[((4*n)+3):(4*n)]), - .rx_gt_ilas_a (rx_gt_ilas_a[((4*n)+3):(4*n)]), - .rx_gt_ilas_r (rx_gt_ilas_r[((4*n)+3):(4*n)]), - .rx_gt_cgs_k (rx_gt_cgs_k[((4*n)+3):(4*n)]), - .rx_ip_rst (rx_ip_rst[n]), - .rx_ip_sof (rx_ip_sof[((4*n)+3):(4*n)]), - .rx_ip_data (rx_ip_data[((32*n)+31):(32*n)]), - .rx_ip_sysref (rx_ip_sysref[n]), - .rx_ip_sync (rx_ip_sync[n]), - .rx_ip_rst_done (rx_ip_rst_done[n]), - .rx_pll_locked (rx_pll_locked[n]), - .rx_user_ready (rx_user_ready[n]), - .rx_rst_done (rx_rst_done[n]), - .rx_pll_locked_m (rx_pll_locked_m[n]), - .rx_user_ready_m (rx_user_ready_m[n]), - .rx_rst_done_m (rx_rst_done_m[n]), - .tx_p (tx_p[n]), - .tx_n (tx_n[n]), - .tx_out_clk (tx_out_clk[n]), - .tx_clk (tx_clk[n]), - .tx_rst (tx_rst[n]), - .tx_rst_m (tx_rst_m[n]), - .tx_data (tx_data[((32*n)+31):(32*n)]), - .tx_sysref (tx_sysref[n]), - .tx_sync (tx_sync[n]), - .tx_pll_rst (tx_pll_rst[n]), - .tx_gt_rst (tx_gt_rst[n]), - .tx_gt_rst_m (tx_gt_rst_m[n]), - .tx_gt_charisk (tx_gt_charisk[((4*TX_DATA_SEL[n])+3):(4*TX_DATA_SEL[n])]), - .tx_gt_data (tx_gt_data[((32*TX_DATA_SEL[n])+31):(32*TX_DATA_SEL[n])]), - .tx_ip_rst (tx_ip_rst[n]), - .tx_ip_data (tx_ip_data[((32*n)+31):(32*n)]), - .tx_ip_sysref (tx_ip_sysref[n]), - .tx_ip_sync (tx_ip_sync[n]), - .tx_ip_rst_done (tx_ip_rst_done[n]), - .tx_pll_locked (tx_pll_locked[n]), - .tx_user_ready (tx_user_ready[n]), - .tx_rst_done (tx_rst_done[n]), - .tx_pll_locked_m (tx_pll_locked_m[n]), - .tx_user_ready_m (tx_user_ready_m[n]), - .tx_rst_done_m (tx_rst_done_m[n]), - .up_es_dma_req (up_es_dma_req[n]), - .up_es_dma_addr (up_es_dma_addr[((32*n)+31):(32*n)]), - .up_es_dma_data (up_es_dma_data[((32*n)+31):(32*n)]), - .up_es_dma_ack (up_es_dma_ack[n]), - .up_es_dma_err (up_es_dma_err[n]), - .up_rstn (up_rstn), - .up_clk (up_clk), - .up_wreq (up_wreq), - .up_waddr (up_waddr), - .up_wdata (up_wdata), - .up_wack (up_wack[n]), - .up_rreq (up_rreq), - .up_raddr (up_raddr), - .up_rdata (up_rdata[((32*n)+31):(32*n)]), - .up_rack (up_rack[n])); - end - endgenerate - - ad_gt_common_1 #( - .ID (0), - .GTH_OR_GTX_N (GTH_OR_GTX_N), - .QPLL0_ENABLE (QPLL0_ENABLE), - .QPLL0_REFCLK_DIV (QPLL0_REFCLK_DIV), - .QPLL0_CFG (QPLL0_CFG), - .QPLL0_FBDIV_RATIO (QPLL0_FBDIV_RATIO), - .QPLL0_FBDIV (QPLL0_FBDIV), - .QPLL1_ENABLE (QPLL1_ENABLE), - .QPLL1_REFCLK_DIV (QPLL1_REFCLK_DIV), - .QPLL1_CFG (QPLL1_CFG), - .QPLL1_FBDIV_RATIO (QPLL1_FBDIV_RATIO), - .QPLL1_FBDIV (QPLL1_FBDIV)) - i_common ( - .qpll0_rst (qpll0_rst), - .qpll0_ref_clk_in (qpll0_ref_clk_in), - .qpll1_rst (qpll1_rst), - .qpll1_ref_clk_in (qpll1_ref_clk_in), - .qpll_clk (qpll_clk), - .qpll_ref_clk (qpll_ref_clk), - .qpll_locked (qpll_locked), - .up_rstn (up_rstn), - .up_clk (up_clk), - .up_wreq (up_wreq), - .up_waddr (up_waddr), - .up_wdata (up_wdata), - .up_wack (up_wack[8]), - .up_rreq (up_rreq), - .up_raddr (up_raddr), - .up_rdata (up_rdata[((32*8)+31):(32*8)]), - .up_rack (up_rack[8])); - - ad_gt_es_axi i_es_axi ( - .up_rstn (up_rstn), - .up_clk (up_clk), - .up_es_dma_req_0 (up_es_dma_req[0]), - .up_es_dma_addr_0 (up_es_dma_addr[((32*0)+31):(32*0)]), - .up_es_dma_data_0 (up_es_dma_data[((32*0)+31):(32*0)]), - .up_es_dma_ack_0 (up_es_dma_ack[0]), - .up_es_dma_err_0 (up_es_dma_err[0]), - .up_es_dma_req_1 (up_es_dma_req[1]), - .up_es_dma_addr_1 (up_es_dma_addr[((32*1)+31):(32*1)]), - .up_es_dma_data_1 (up_es_dma_data[((32*1)+31):(32*1)]), - .up_es_dma_ack_1 (up_es_dma_ack[1]), - .up_es_dma_err_1 (up_es_dma_err[1]), - .up_es_dma_req_2 (up_es_dma_req[2]), - .up_es_dma_addr_2 (up_es_dma_addr[((32*2)+31):(32*2)]), - .up_es_dma_data_2 (up_es_dma_data[((32*2)+31):(32*2)]), - .up_es_dma_ack_2 (up_es_dma_ack[2]), - .up_es_dma_err_2 (up_es_dma_err[2]), - .up_es_dma_req_3 (up_es_dma_req[3]), - .up_es_dma_addr_3 (up_es_dma_addr[((32*3)+31):(32*3)]), - .up_es_dma_data_3 (up_es_dma_data[((32*3)+31):(32*3)]), - .up_es_dma_ack_3 (up_es_dma_ack[3]), - .up_es_dma_err_3 (up_es_dma_err[3]), - .up_es_dma_req_4 (up_es_dma_req[4]), - .up_es_dma_addr_4 (up_es_dma_addr[((32*4)+31):(32*4)]), - .up_es_dma_data_4 (up_es_dma_data[((32*4)+31):(32*4)]), - .up_es_dma_ack_4 (up_es_dma_ack[4]), - .up_es_dma_err_4 (up_es_dma_err[4]), - .up_es_dma_req_5 (up_es_dma_req[5]), - .up_es_dma_addr_5 (up_es_dma_addr[((32*5)+31):(32*5)]), - .up_es_dma_data_5 (up_es_dma_data[((32*5)+31):(32*5)]), - .up_es_dma_ack_5 (up_es_dma_ack[5]), - .up_es_dma_err_5 (up_es_dma_err[5]), - .up_es_dma_req_6 (up_es_dma_req[6]), - .up_es_dma_addr_6 (up_es_dma_addr[((32*6)+31):(32*6)]), - .up_es_dma_data_6 (up_es_dma_data[((32*6)+31):(32*6)]), - .up_es_dma_ack_6 (up_es_dma_ack[6]), - .up_es_dma_err_6 (up_es_dma_err[6]), - .up_es_dma_req_7 (up_es_dma_req[7]), - .up_es_dma_addr_7 (up_es_dma_addr[((32*7)+31):(32*7)]), - .up_es_dma_data_7 (up_es_dma_data[((32*7)+31):(32*7)]), - .up_es_dma_ack_7 (up_es_dma_ack[7]), - .up_es_dma_err_7 (up_es_dma_err[7]), - .axi_awvalid (m_axi_awvalid), - .axi_awaddr (m_axi_awaddr), - .axi_awprot (m_axi_awprot), - .axi_awready (m_axi_awready), - .axi_wvalid (m_axi_wvalid), - .axi_wdata (m_axi_wdata), - .axi_wstrb (m_axi_wstrb), - .axi_wready (m_axi_wready), - .axi_bvalid (m_axi_bvalid), - .axi_bresp (m_axi_bresp), - .axi_bready (m_axi_bready), - .axi_arvalid (m_axi_arvalid), - .axi_araddr (m_axi_araddr), - .axi_arprot (m_axi_arprot), - .axi_arready (m_axi_arready), - .axi_rvalid (m_axi_rvalid), - .axi_rresp (m_axi_rresp), - .axi_rdata (m_axi_rdata), - .axi_rready (m_axi_rready)); - - up_axi i_up_axi ( - .up_rstn (up_rstn), - .up_clk (up_clk), - .up_axi_awvalid (s_axi_awvalid), - .up_axi_awaddr (s_axi_awaddr), - .up_axi_awready (s_axi_awready), - .up_axi_wvalid (s_axi_wvalid), - .up_axi_wdata (s_axi_wdata), - .up_axi_wstrb (s_axi_wstrb), - .up_axi_wready (s_axi_wready), - .up_axi_bvalid (s_axi_bvalid), - .up_axi_bresp (s_axi_bresp), - .up_axi_bready (s_axi_bready), - .up_axi_arvalid (s_axi_arvalid), - .up_axi_araddr (s_axi_araddr), - .up_axi_arready (s_axi_arready), - .up_axi_rvalid (s_axi_rvalid), - .up_axi_rresp (s_axi_rresp), - .up_axi_rdata (s_axi_rdata), - .up_axi_rready (s_axi_rready), - .up_wreq (up_wreq), - .up_waddr (up_waddr), - .up_wdata (up_wdata), - .up_wack (up_wack_d), - .up_rreq (up_rreq), - .up_raddr (up_raddr), - .up_rdata (up_rdata_d), - .up_rack (up_rack_d)); - -endmodule - -// *************************************************************************** -// *************************************************************************** diff --git a/library/axi_jesd_gt/axi_jesd_gt_constr.xdc b/library/axi_jesd_gt/axi_jesd_gt_constr.xdc deleted file mode 100644 index 65112d6ce..000000000 --- a/library/axi_jesd_gt/axi_jesd_gt_constr.xdc +++ /dev/null @@ -1,35 +0,0 @@ - -set_property shreg_extract no [get_cells -hier -filter {name =~ *i_channel/i_up/up_rx_rst_done*}] -set_property shreg_extract no [get_cells -hier -filter {name =~ *i_channel/i_up/up_rx_pll_locked*}] -set_property shreg_extract no [get_cells -hier -filter {name =~ *i_channel/i_up/up_rx_status*}] -set_property shreg_extract no [get_cells -hier -filter {name =~ *i_channel/i_up/up_tx_rst_done*}] -set_property shreg_extract no [get_cells -hier -filter {name =~ *i_channel/i_up/up_tx_pll_locked*}] -set_property shreg_extract no [get_cells -hier -filter {name =~ *i_channel/i_up/up_tx_status*}] -set_property shreg_extract no [get_cells -hier -filter {name =~ *i_channel/i_up/rx_sysref_sel*}] -set_property shreg_extract no [get_cells -hier -filter {name =~ *i_channel/i_up/rx_up_sysref*}] -set_property shreg_extract no [get_cells -hier -filter {name =~ *i_channel/i_up/rx_up_sync*}] -set_property shreg_extract no [get_cells -hier -filter {name =~ *i_channel/i_up/tx_sysref_sel*}] -set_property shreg_extract no [get_cells -hier -filter {name =~ *i_channel/i_up/tx_up_sysref*}] -set_property shreg_extract no [get_cells -hier -filter {name =~ *i_channel/i_up/tx_up_sync*}] -set_property shreg_extract no [get_cells -hier -filter {name =~ *ad_rst_sync*}] - -set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/up_rx_rst_done_m1_reg && IS_SEQUENTIAL}] -set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/up_rx_rst_done_m_m1_reg && IS_SEQUENTIAL}] -set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/up_rx_pll_locked_m1_reg && IS_SEQUENTIAL}] -set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/up_rx_pll_locked_m_m1_reg && IS_SEQUENTIAL}] -set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/up_rx_status_m1_reg && IS_SEQUENTIAL}] -set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/up_tx_rst_done_m1_reg && IS_SEQUENTIAL}] -set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/up_tx_rst_done_m_m1_reg && IS_SEQUENTIAL}] -set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/up_tx_pll_locked_m1_reg && IS_SEQUENTIAL}] -set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/up_tx_pll_locked_m_m1_reg && IS_SEQUENTIAL}] -set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/up_tx_status_m1_reg && IS_SEQUENTIAL}] -set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/rx_sysref_sel_m1_reg && IS_SEQUENTIAL}] -set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/rx_up_sysref_m1_reg && IS_SEQUENTIAL}] -set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/rx_up_sync_m1_reg && IS_SEQUENTIAL}] -set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/tx_sysref_sel_m1_reg && IS_SEQUENTIAL}] -set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/tx_up_sysref_m1_reg && IS_SEQUENTIAL}] -set_false_path -to [get_cells -hier -filter {name =~ *i_channel/i_up/tx_up_sync_m1_reg && IS_SEQUENTIAL}] - -set_false_path -from [get_cells -hier -filter {name =~ *up_rx_preset_reg && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *ad_rst_sync_m1_reg && IS_SEQUENTIAL}] -set_false_path -from [get_cells -hier -filter {name =~ *up_tx_preset_reg && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *ad_rst_sync_m1_reg && IS_SEQUENTIAL}] - diff --git a/library/axi_jesd_gt/axi_jesd_gt_ip.tcl b/library/axi_jesd_gt/axi_jesd_gt_ip.tcl deleted file mode 100644 index 79688653b..000000000 --- a/library/axi_jesd_gt/axi_jesd_gt_ip.tcl +++ /dev/null @@ -1,189 +0,0 @@ -# ip - -source ../scripts/adi_env.tcl -source $ad_hdl_dir/library/scripts/adi_ip.tcl - -adi_ip_create axi_jesd_gt -adi_ip_files axi_jesd_gt [list \ - "$ad_hdl_dir/library/common/ad_rst.v" \ - "$ad_hdl_dir/library/common/ad_gt_channel.v" \ - "$ad_hdl_dir/library/common/ad_gt_common.v" \ - "$ad_hdl_dir/library/common/ad_gt_es.v" \ - "$ad_hdl_dir/library/common/ad_gt_es_axi.v" \ - "$ad_hdl_dir/library/common/ad_gt_channel_1.v" \ - "$ad_hdl_dir/library/common/ad_gt_common_1.v" \ - "$ad_hdl_dir/library/common/ad_jesd_align.v" \ - "$ad_hdl_dir/library/common/up_axi.v" \ - "$ad_hdl_dir/library/common/up_gt_channel.v" \ - "$ad_hdl_dir/library/common/up_gt.v" \ - "axi_jesd_gt_constr.xdc" \ - "axi_jesd_gt.v" ] - -adi_ip_properties axi_jesd_gt - -adi_ip_constraints axi_jesd_gt [list \ - "axi_jesd_gt_constr.xdc" ] - -ipx::associate_bus_interfaces -busif m_axi -clock s_axi_aclk [ipx::current_core] - -adi_if_infer_bus ADI:user:if_gt_qpll slave gt_qpll_0 [list \ - "qpll_rst qpll0_rst "\ - "qpll_ref_clk qpll0_ref_clk_in "] - -adi_if_infer_bus ADI:user:if_gt_qpll slave gt_qpll_1 [list \ - "qpll_rst qpll1_rst "\ - "qpll_ref_clk qpll1_ref_clk_in "] - -for {set n 0} {$n < 8} {incr n} { - - adi_if_infer_bus ADI:user:if_gt_pll slave gt_pll_${n} [list \ - "cpll_rst_m cpll_rst_m_${n} "\ - "cpll_ref_clk_in cpll_ref_clk_in_${n} "] - - adi_if_infer_bus ADI:user:if_gt_rx slave gt_rx_${n} [list \ - "rx_p rx_${n}_p "\ - "rx_n rx_${n}_n "\ - "rx_rst rx_rst_${n} "\ - "rx_rst_m rx_rst_m_${n} "\ - "rx_pll_rst rx_pll_rst_${n} "\ - "rx_gt_rst rx_gt_rst_${n} "\ - "rx_gt_rst_m rx_gt_rst_m_${n} "\ - "rx_pll_locked rx_pll_locked_${n} "\ - "rx_pll_locked_m rx_pll_locked_m_${n} "\ - "rx_user_ready rx_user_ready_${n} "\ - "rx_user_ready_m rx_user_ready_m_${n} "\ - "rx_rst_done rx_rst_done_${n} "\ - "rx_rst_done_m rx_rst_done_m_${n} "\ - "rx_out_clk rx_out_clk_${n} "\ - "rx_clk rx_clk_${n} "\ - "rx_sysref rx_sysref_${n} "\ - "rx_sync rx_sync_${n} "\ - "rx_sof rx_sof_${n} "\ - "rx_data rx_data_${n} "\ - "rx_ip_rst rx_ip_rst_${n} "\ - "rx_ip_sof rx_ip_sof_${n} "\ - "rx_ip_data rx_ip_data_${n} "\ - "rx_ip_sysref rx_ip_sysref_${n} "\ - "rx_ip_sync rx_ip_sync_${n} "\ - "rx_ip_rst_done rx_ip_rst_done_${n} "] - - adi_if_infer_bus xilinx.com:display_jesd204:jesd204_rx_bus master gt_rx_ip_${n} [list \ - "rxcharisk rx_gt_charisk_${n} "\ - "rxdisperr rx_gt_disperr_${n} "\ - "rxnotintable rx_gt_notintable_${n} "\ - "rxdata rx_gt_data_${n} "] - - adi_if_infer_bus ADI:user:if_gt_rx_ksig master gt_rx_ksig_${n} [list \ - "rx_gt_ilas_f rx_gt_ilas_f_${n} "\ - "rx_gt_ilas_q rx_gt_ilas_q_${n} "\ - "rx_gt_ilas_a rx_gt_ilas_a_${n} "\ - "rx_gt_ilas_r rx_gt_ilas_r_${n} "\ - "rx_gt_cgs_k rx_gt_cgs_k_${n} "] - - adi_if_infer_bus ADI:user:if_gt_tx slave gt_tx_${n} [list \ - "tx_p tx_${n}_p "\ - "tx_n tx_${n}_n "\ - "tx_rst tx_rst_${n} "\ - "tx_rst_m tx_rst_m_${n} "\ - "tx_pll_rst tx_pll_rst_${n} "\ - "tx_gt_rst tx_gt_rst_${n} "\ - "tx_gt_rst_m tx_gt_rst_m_${n} "\ - "tx_pll_locked tx_pll_locked_${n} "\ - "tx_pll_locked_m tx_pll_locked_m_${n} "\ - "tx_user_ready tx_user_ready_${n} "\ - "tx_user_ready_m tx_user_ready_m_${n} "\ - "tx_rst_done tx_rst_done_${n} "\ - "tx_rst_done_m tx_rst_done_m_${n} "\ - "tx_out_clk tx_out_clk_${n} "\ - "tx_clk tx_clk_${n} "\ - "tx_sysref tx_sysref_${n} "\ - "tx_sync tx_sync_${n} "\ - "tx_data tx_data_${n} "\ - "tx_ip_rst tx_ip_rst_${n} "\ - "tx_ip_data tx_ip_data_${n} "\ - "tx_ip_sysref tx_ip_sysref_${n} "\ - "tx_ip_sync tx_ip_sync_${n} "\ - "tx_ip_rst_done tx_ip_rst_done_${n} "] - - adi_if_infer_bus xilinx.com:display_jesd204:jesd204_tx_bus slave gt_tx_ip_${n} [list \ - "txcharisk tx_gt_charisk_${n} "\ - "txdata tx_gt_data_${n} "] -} - -set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.QPLL0_ENABLE')) == 1} \ - [ipx::get_bus_interfaces gt_qpll_0 -of_objects [ipx::current_core]] -set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.QPLL1_ENABLE')) == 1} \ - [ipx::get_bus_interfaces gt_qpll_1 -of_objects [ipx::current_core]] - -set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 0} \ - [ipx::get_bus_interfaces gt_pll_0 -of_objects [ipx::current_core]] -set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 1} \ - [ipx::get_bus_interfaces gt_pll_1 -of_objects [ipx::current_core]] -set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 2} \ - [ipx::get_bus_interfaces gt_pll_2 -of_objects [ipx::current_core]] -set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 3} \ - [ipx::get_bus_interfaces gt_pll_3 -of_objects [ipx::current_core]] -set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 4} \ - [ipx::get_bus_interfaces gt_pll_4 -of_objects [ipx::current_core]] -set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 5} \ - [ipx::get_bus_interfaces gt_pll_5 -of_objects [ipx::current_core]] -set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 6} \ - [ipx::get_bus_interfaces gt_pll_6 -of_objects [ipx::current_core]] -set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 7} \ - [ipx::get_bus_interfaces gt_pll_7 -of_objects [ipx::current_core]] - -set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 0} \ - [ipx::get_bus_interfaces gt_rx_*0 -of_objects [ipx::current_core]] -set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 1} \ - [ipx::get_bus_interfaces gt_rx_*1 -of_objects [ipx::current_core]] -set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 2} \ - [ipx::get_bus_interfaces gt_rx_*2 -of_objects [ipx::current_core]] -set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 3} \ - [ipx::get_bus_interfaces gt_rx_*3 -of_objects [ipx::current_core]] -set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 4} \ - [ipx::get_bus_interfaces gt_rx_*4 -of_objects [ipx::current_core]] -set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 5} \ - [ipx::get_bus_interfaces gt_rx_*5 -of_objects [ipx::current_core]] -set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 6} \ - [ipx::get_bus_interfaces gt_rx_*6 -of_objects [ipx::current_core]] -set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 7} \ - [ipx::get_bus_interfaces gt_rx_*7 -of_objects [ipx::current_core]] - -set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 0} \ - [ipx::get_bus_interfaces gt_tx_*0 -of_objects [ipx::current_core]] -set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 1} \ - [ipx::get_bus_interfaces gt_tx_*1 -of_objects [ipx::current_core]] -set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 2} \ - [ipx::get_bus_interfaces gt_tx_*2 -of_objects [ipx::current_core]] -set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 3} \ - [ipx::get_bus_interfaces gt_tx_*3 -of_objects [ipx::current_core]] -set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 4} \ - [ipx::get_bus_interfaces gt_tx_*4 -of_objects [ipx::current_core]] -set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 5} \ - [ipx::get_bus_interfaces gt_tx_*5 -of_objects [ipx::current_core]] -set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 6} \ - [ipx::get_bus_interfaces gt_tx_*6 -of_objects [ipx::current_core]] -set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 7} \ - [ipx::get_bus_interfaces gt_tx_*7 -of_objects [ipx::current_core]] - -set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 0} \ - [ipx::get_ports *rx_*0* -of_objects [ipx::current_core]] -set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 1} \ - [ipx::get_ports *rx_*1* -of_objects [ipx::current_core]] -set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 2} \ - [ipx::get_ports *rx_*2* -of_objects [ipx::current_core]] -set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 3} \ - [ipx::get_ports *rx_*3* -of_objects [ipx::current_core]] -set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 4} \ - [ipx::get_ports *rx_*4* -of_objects [ipx::current_core]] -set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 5} \ - [ipx::get_ports *rx_*5* -of_objects [ipx::current_core]] -set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 6} \ - [ipx::get_ports *rx_*6* -of_objects [ipx::current_core]] -set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 7} \ - [ipx::get_ports *rx_*7* -of_objects [ipx::current_core]] - -set_property driver_value 0 [ipx::get_ports -filter "direction==in" -of_objects [ipx::current_core]] - -ipx::save_core [ipx::current_core] - diff --git a/library/axi_jesd_xcvr/axi_jesd_xcvr.v b/library/axi_jesd_xcvr/axi_jesd_xcvr.v deleted file mode 100644 index 149af54b9..000000000 --- a/library/axi_jesd_xcvr/axi_jesd_xcvr.v +++ /dev/null @@ -1,315 +0,0 @@ -// *************************************************************************** -// *************************************************************************** -// Copyright 2011(c) Analog Devices, Inc. -// -// All rights reserved. -// -// Redistribution and use in source and binary forms, with or without modification, -// are permitted provided that the following conditions are met: -// - Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// - Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in -// the documentation and/or other materials provided with the -// distribution. -// - Neither the name of Analog Devices, Inc. nor the names of its -// contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// - The use of this software may or may not infringe the patent rights -// of one or more patent holders. This license does not release you -// from the requirement that you obtain separate licenses from these -// patent holders to use this software. -// - Use of the software either in source or binary form, must be run -// on or directly connected to an Analog Devices Inc. component. -// -// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, -// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A -// PARTICULAR PURPOSE ARE DISCLAIMED. -// -// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY -// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF -// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// *************************************************************************** -// *************************************************************************** - -`timescale 1ns/100ps - -module axi_jesd_xcvr ( - - rst, - - // receive interface - - rx_clk, - rx_rstn, - rx_ext_sysref_in, - rx_ext_sysref_out, - rx_sync, - rx_sof, - rx_data, - rx_ready, - rx_ip_sysref, - rx_ip_sync, - rx_ip_sof, - rx_ip_valid, - rx_ip_data, - rx_ip_ready, - - // transmit interface - - tx_clk, - tx_rstn, - tx_ext_sysref_in, - tx_ext_sysref_out, - tx_sync, - tx_data, - tx_ready, - tx_ip_sysref, - tx_ip_sync, - tx_ip_valid, - tx_ip_data, - tx_ip_ready, - - // axi-lite (slave) - - s_axi_aclk, - s_axi_aresetn, - s_axi_awvalid, - s_axi_awaddr, - s_axi_awprot, - s_axi_awready, - s_axi_wvalid, - s_axi_wdata, - s_axi_wstrb, - s_axi_wready, - s_axi_bvalid, - s_axi_bresp, - s_axi_bready, - s_axi_arvalid, - s_axi_araddr, - s_axi_arprot, - s_axi_arready, - s_axi_rvalid, - s_axi_rdata, - s_axi_rresp, - s_axi_rready); - - parameter ID = 0; - parameter DEVICE_TYPE = 0; - parameter TX_NUM_OF_LANES = 4; - parameter RX_NUM_OF_LANES = 4; - - output rst; - - // receive interface - - input rx_clk; - output rx_rstn; - input rx_ext_sysref_in; - output rx_ext_sysref_out; - output rx_sync; - output [((RX_NUM_OF_LANES* 1)-1):0] rx_sof; - output [((RX_NUM_OF_LANES*32)-1):0] rx_data; - input [((RX_NUM_OF_LANES* 1)-1):0] rx_ready; - output rx_ip_sysref; - input rx_ip_sync; - input [ 3:0] rx_ip_sof; - input rx_ip_valid; - input [((RX_NUM_OF_LANES*32)-1):0] rx_ip_data; - output rx_ip_ready; - - // transmit interface - - input tx_clk; - output tx_rstn; - input tx_ext_sysref_in; - output tx_ext_sysref_out; - input tx_sync; - input [((TX_NUM_OF_LANES*32)-1):0] tx_data; - input [((RX_NUM_OF_LANES* 1)-1):0] tx_ready; - output tx_ip_sysref; - output tx_ip_sync; - output tx_ip_valid; - output [((RX_NUM_OF_LANES*32)-1):0] tx_ip_data; - input tx_ip_ready; - - // axi interface - - input s_axi_aclk; - input s_axi_aresetn; - input s_axi_awvalid; - input [ 31:0] s_axi_awaddr; - input [ 2:0] s_axi_awprot; - output s_axi_awready; - input s_axi_wvalid; - input [ 31:0] s_axi_wdata; - input [ 3:0] s_axi_wstrb; - output s_axi_wready; - output s_axi_bvalid; - output [ 1:0] s_axi_bresp; - input s_axi_bready; - input s_axi_arvalid; - input [ 31:0] s_axi_araddr; - input [ 2:0] s_axi_arprot; - output s_axi_arready; - output s_axi_rvalid; - output [ 31:0] s_axi_rdata; - output [ 1:0] s_axi_rresp; - input s_axi_rready; - - // internal signals - - wire up_rstn; - wire up_clk; - wire [ 7:0] status_s; - wire [ 3:0] rx_ip_sof_s; - wire [((RX_NUM_OF_LANES*32)-1):0] rx_ip_data_s; - wire [ 7:0] rx_status_s; - wire [ 7:0] tx_status_s; - wire up_wreq_s; - wire [ 13:0] up_waddr_s; - wire [ 31:0] up_wdata_s; - wire up_wack_s; - wire up_rreq_s; - wire [ 13:0] up_raddr_s; - wire [ 31:0] up_rdata_s; - wire up_rack_s; - - // variables - - genvar n; - - // assignments - - assign status_s = 8'hff; - assign up_rstn = s_axi_aresetn; - assign up_clk = s_axi_aclk; - - assign rx_ip_ready = 1'b1; - assign rx_ip_sysref = rx_ext_sysref_out; - - assign rx_ip_sof_s[3] = rx_ip_sof[0]; - assign rx_ip_sof_s[2] = rx_ip_sof[1]; - assign rx_ip_sof_s[1] = rx_ip_sof[2]; - assign rx_ip_sof_s[0] = rx_ip_sof[3]; - - generate - for (n = 0; n < RX_NUM_OF_LANES; n = n + 1) begin: g_rx_swap - assign rx_ip_data_s[((n*32) + 31):((n*32) + 24)] = rx_ip_data[((n*32) + 7):((n*32) + 0)]; - assign rx_ip_data_s[((n*32) + 23):((n*32) + 16)] = rx_ip_data[((n*32) + 15):((n*32) + 8)]; - assign rx_ip_data_s[((n*32) + 15):((n*32) + 8)] = rx_ip_data[((n*32) + 23):((n*32) + 16)]; - assign rx_ip_data_s[((n*32) + 7):((n*32) + 0)] = rx_ip_data[((n*32) + 31):((n*32) + 24)]; - end - endgenerate - - generate - if (RX_NUM_OF_LANES < 8) begin - assign rx_status_s[7:RX_NUM_OF_LANES] = status_s[7:RX_NUM_OF_LANES]; - assign rx_status_s[(RX_NUM_OF_LANES-1):0] = rx_ready; - end else begin - assign rx_status_s = rx_ready[7:0]; - end - endgenerate - - generate - for (n = 0; n < RX_NUM_OF_LANES; n = n + 1) begin: g_rx_align - ad_jesd_align i_jesd_align ( - .rx_clk (rx_clk), - .rx_ip_sof (rx_ip_sof_s), - .rx_ip_data (rx_ip_data_s[n*32+31:n*32]), - .rx_sof (rx_sof[n]), - .rx_data (rx_data[n*32+31:n*32])); - end - endgenerate - - assign tx_ip_valid = 1'b1; - assign tx_ip_sysref = tx_ext_sysref_out; - - generate - for (n = 0; n < TX_NUM_OF_LANES; n = n + 1) begin: g_tx_swap - assign tx_ip_data[((n*32) + 31):((n*32) + 24)] = tx_data[((n*32) + 7):((n*32) + 0)]; - assign tx_ip_data[((n*32) + 23):((n*32) + 16)] = tx_data[((n*32) + 15):((n*32) + 8)]; - assign tx_ip_data[((n*32) + 15):((n*32) + 8)] = tx_data[((n*32) + 23):((n*32) + 16)]; - assign tx_ip_data[((n*32) + 7):((n*32) + 0)] = tx_data[((n*32) + 31):((n*32) + 24)]; - end - endgenerate - - generate - if (TX_NUM_OF_LANES < 8) begin - assign tx_status_s[7:TX_NUM_OF_LANES] = status_s[7:TX_NUM_OF_LANES]; - assign tx_status_s[(TX_NUM_OF_LANES-1):0] = tx_ready; - end else begin - assign tx_status_s = tx_ready[7:0]; - end - endgenerate - - // processor - - up_xcvr #( - .ID(ID), - .DEVICE_TYPE(DEVICE_TYPE)) - i_up_xcvr ( - .rst (rst), - .rx_clk (rx_clk), - .rx_rstn (rx_rstn), - .rx_ext_sysref (rx_ext_sysref_in), - .rx_sysref (rx_ext_sysref_out), - .rx_ip_sync (rx_ip_sync), - .rx_sync (rx_sync), - .rx_status (rx_status_s), - .tx_clk (tx_clk), - .tx_rstn (tx_rstn), - .tx_ext_sysref (tx_ext_sysref_in), - .tx_sysref (tx_ext_sysref_out), - .tx_sync (tx_sync), - .tx_ip_sync (tx_ip_sync), - .tx_status (tx_status_s), - .up_rstn (up_rstn), - .up_clk (up_clk), - .up_wreq (up_wreq_s), - .up_waddr (up_waddr_s), - .up_wdata (up_wdata_s), - .up_wack (up_wack_s), - .up_rreq (up_rreq_s), - .up_raddr (up_raddr_s), - .up_rdata (up_rdata_s), - .up_rack (up_rack_s)); - - // axi interface - - up_axi i_up_axi ( - .up_rstn (up_rstn), - .up_clk (up_clk), - .up_axi_awvalid (s_axi_awvalid), - .up_axi_awaddr (s_axi_awaddr), - .up_axi_awready (s_axi_awready), - .up_axi_wvalid (s_axi_wvalid), - .up_axi_wdata (s_axi_wdata), - .up_axi_wstrb (s_axi_wstrb), - .up_axi_wready (s_axi_wready), - .up_axi_bvalid (s_axi_bvalid), - .up_axi_bresp (s_axi_bresp), - .up_axi_bready (s_axi_bready), - .up_axi_arvalid (s_axi_arvalid), - .up_axi_araddr (s_axi_araddr), - .up_axi_arready (s_axi_arready), - .up_axi_rvalid (s_axi_rvalid), - .up_axi_rresp (s_axi_rresp), - .up_axi_rdata (s_axi_rdata), - .up_axi_rready (s_axi_rready), - .up_wreq (up_wreq_s), - .up_waddr (up_waddr_s), - .up_wdata (up_wdata_s), - .up_wack (up_wack_s), - .up_rreq (up_rreq_s), - .up_raddr (up_raddr_s), - .up_rdata (up_rdata_s), - .up_rack (up_rack_s)); - -endmodule - -// *************************************************************************** -// *************************************************************************** diff --git a/library/axi_jesd_xcvr/axi_jesd_xcvr_constr.sdc b/library/axi_jesd_xcvr/axi_jesd_xcvr_constr.sdc deleted file mode 100644 index 6f0442c15..000000000 --- a/library/axi_jesd_xcvr/axi_jesd_xcvr_constr.sdc +++ /dev/null @@ -1,12 +0,0 @@ - -set_false_path -from [get_registers *up_xcvr:i_up_xcvr|up_rx_sysref_sel*] -to [get_registers *up_xcvr:i_up_xcvr|rx_sysref_sel_m1*] -set_false_path -from [get_registers *up_xcvr:i_up_xcvr|up_rx_sysref*] -to [get_registers *up_xcvr:i_up_xcvr|rx_up_sysref_m1*] -set_false_path -from [get_registers *up_xcvr:i_up_xcvr|up_rx_sync*] -to [get_registers *up_xcvr:i_up_xcvr|rx_up_sync_m1*] -set_false_path -from [get_registers *up_xcvr:i_up_xcvr|up_tx_sysref_sel*] -to [get_registers *up_xcvr:i_up_xcvr|tx_sysref_sel_m1*] -set_false_path -from [get_registers *up_xcvr:i_up_xcvr|up_tx_sysref*] -to [get_registers *up_xcvr:i_up_xcvr|tx_up_sysref_m1*] -set_false_path -from [get_registers *up_xcvr:i_up_xcvr|up_tx_sync*] -to [get_registers *up_xcvr:i_up_xcvr|tx_up_sync_m1*] -set_false_path -from [get_registers *up_xcvr:i_up_xcvr|rx_sync*] -to [get_registers *up_xcvr:i_up_xcvr|up_rx_status_m1*] -set_false_path -from [get_registers *up_xcvr:i_up_xcvr|tx_ip_sync*] -to [get_registers *up_xcvr:i_up_xcvr|up_tx_status_m1*] -set_false_path -from [get_registers *up_xcvr:i_up_xcvr|up_rx_reset*] -to [get_registers *up_xcvr:i_up_xcvr|ad_rst:i_rx_rst_reg|ad_rst_sync_m1*] -set_false_path -from [get_registers *up_xcvr:i_up_xcvr|up_tx_reset*] -to [get_registers *up_xcvr:i_up_xcvr|ad_rst:i_tx_rst_reg|ad_rst_sync_m1*] - diff --git a/library/axi_jesd_xcvr/axi_jesd_xcvr_hw.tcl b/library/axi_jesd_xcvr/axi_jesd_xcvr_hw.tcl deleted file mode 100755 index 40ed2e55c..000000000 --- a/library/axi_jesd_xcvr/axi_jesd_xcvr_hw.tcl +++ /dev/null @@ -1,136 +0,0 @@ - - -package require -exact qsys 13.0 -source ../scripts/adi_env.tcl -source ../scripts/adi_ip_alt.tcl - -set_module_property NAME axi_jesd_xcvr -set_module_property DESCRIPTION "AXI JESD XCVR Interface" -set_module_property VERSION 1.0 -set_module_property GROUP "Analog Devices" -set_module_property DISPLAY_NAME axi_jesd_xcvr -set_module_property ELABORATION_CALLBACK p_axi_jesd_xcvr - -# files - -add_fileset quartus_synth QUARTUS_SYNTH "" "Quartus Synthesis" -set_fileset_property quartus_synth TOP_LEVEL axi_jesd_xcvr -add_fileset_file ad_rst.v VERILOG PATH $ad_hdl_dir/library/common/ad_rst.v -add_fileset_file ad_jesd_align.v VERILOG PATH $ad_hdl_dir/library/common/ad_jesd_align.v -add_fileset_file up_axi.v VERILOG PATH $ad_hdl_dir/library/common/up_axi.v -add_fileset_file up_xcvr.v VERILOG PATH $ad_hdl_dir/library/common/up_xcvr.v -add_fileset_file axi_jesd_xcvr.v VERILOG PATH axi_jesd_xcvr.v TOP_LEVEL_FILE -add_fileset_file axi_jesd_xcvr_constr.sdc SDC PATH axi_jesd_xcvr_constr.sdc - -# parameters - -add_parameter ID INTEGER 0 -set_parameter_property ID DEFAULT_VALUE 0 -set_parameter_property ID DISPLAY_NAME ID -set_parameter_property ID TYPE INTEGER -set_parameter_property ID UNITS None -set_parameter_property ID HDL_PARAMETER true - -add_parameter DEVICE_TYPE INTEGER 0 -set_parameter_property DEVICE_TYPE DEFAULT_VALUE 0 -set_parameter_property DEVICE_TYPE DISPLAY_NAME DEVICE_TYPE -set_parameter_property DEVICE_TYPE TYPE INTEGER -set_parameter_property DEVICE_TYPE UNITS None -set_parameter_property DEVICE_TYPE HDL_PARAMETER true - -add_parameter TX_NUM_OF_LANES INTEGER 0 -set_parameter_property TX_NUM_OF_LANES DEFAULT_VALUE 4 -set_parameter_property TX_NUM_OF_LANES DISPLAY_NAME TX_NUM_OF_LANES -set_parameter_property TX_NUM_OF_LANES TYPE INTEGER -set_parameter_property TX_NUM_OF_LANES UNITS None -set_parameter_property TX_NUM_OF_LANES HDL_PARAMETER true - -add_parameter RX_NUM_OF_LANES INTEGER 0 -set_parameter_property RX_NUM_OF_LANES DEFAULT_VALUE 4 -set_parameter_property RX_NUM_OF_LANES DISPLAY_NAME RX_NUM_OF_LANES -set_parameter_property RX_NUM_OF_LANES TYPE INTEGER -set_parameter_property RX_NUM_OF_LANES UNITS None -set_parameter_property RX_NUM_OF_LANES HDL_PARAMETER true - -# axi4 slave - -add_interface s_axi_clock clock end -add_interface_port s_axi_clock s_axi_aclk clk Input 1 - -add_interface s_axi_reset reset end -set_interface_property s_axi_reset associatedClock s_axi_clock -add_interface_port s_axi_reset s_axi_aresetn reset_n Input 1 - -add_interface s_axi axi4lite end -set_interface_property s_axi associatedClock s_axi_clock -set_interface_property s_axi associatedReset s_axi_reset -add_interface_port s_axi s_axi_awvalid awvalid Input 1 -add_interface_port s_axi s_axi_awaddr awaddr Input 16 -add_interface_port s_axi s_axi_awprot awprot Input 3 -add_interface_port s_axi s_axi_awready awready Output 1 -add_interface_port s_axi s_axi_wvalid wvalid Input 1 -add_interface_port s_axi s_axi_wdata wdata Input 32 -add_interface_port s_axi s_axi_wstrb wstrb Input 4 -add_interface_port s_axi s_axi_wready wready Output 1 -add_interface_port s_axi s_axi_bvalid bvalid Output 1 -add_interface_port s_axi s_axi_bresp bresp Output 2 -add_interface_port s_axi s_axi_bready bready Input 1 -add_interface_port s_axi s_axi_arvalid arvalid Input 1 -add_interface_port s_axi s_axi_araddr araddr Input 16 -add_interface_port s_axi s_axi_arprot arprot Input 3 -add_interface_port s_axi s_axi_arready arready Output 1 -add_interface_port s_axi s_axi_rvalid rvalid Output 1 -add_interface_port s_axi s_axi_rresp rresp Output 2 -add_interface_port s_axi s_axi_rdata rdata Output 32 -add_interface_port s_axi s_axi_rready rready Input 1 - -# transceiver interface - -ad_alt_intf reset rst output 1 s_axi_clock s_axi_reset - -ad_alt_intf clock rx_clk input 1 -ad_alt_intf reset-n rx_rstn output 1 if_rx_clk s_axi_reset -ad_alt_intf signal rx_ext_sysref_in input 1 -ad_alt_intf signal rx_ext_sysref_out output 1 -ad_alt_intf signal rx_sync output 1 -ad_alt_intf signal rx_sof output RX_NUM_OF_LANES -ad_alt_intf signal rx_data output RX_NUM_OF_LANES*32 data -ad_alt_intf signal rx_ready input RX_NUM_OF_LANES rx_ready -ad_alt_intf signal rx_ip_sysref output 1 export -ad_alt_intf signal rx_ip_sync input 1 export -ad_alt_intf signal rx_ip_sof input 4 export - -add_interface if_rx_ip_avl avalon_streaming sink -add_interface_port if_rx_ip_avl rx_ip_data data input RX_NUM_OF_LANES*32 -add_interface_port if_rx_ip_avl rx_ip_valid valid input 1 -add_interface_port if_rx_ip_avl rx_ip_ready ready output 1 - -ad_alt_intf clock tx_clk input 1 -ad_alt_intf reset-n tx_rstn output 1 if_tx_clk s_axi_reset -ad_alt_intf signal tx_ext_sysref_in input 1 -ad_alt_intf signal tx_ext_sysref_out output 1 -ad_alt_intf signal tx_sync input 1 -ad_alt_intf signal tx_data input TX_NUM_OF_LANES*32 data -ad_alt_intf signal tx_ready input TX_NUM_OF_LANES tx_ready -ad_alt_intf signal tx_ip_sysref output 1 export -ad_alt_intf signal tx_ip_sync output 1 export - -add_interface if_tx_ip_avl avalon_streaming source -add_interface_port if_tx_ip_avl tx_ip_data data output TX_NUM_OF_LANES*32 -add_interface_port if_tx_ip_avl tx_ip_valid valid output 1 -add_interface_port if_tx_ip_avl tx_ip_ready ready input 1 - -proc p_axi_jesd_xcvr {} { - - set p_num_of_rx_lanes [get_parameter_value "RX_NUM_OF_LANES"] - set p_num_of_tx_lanes [get_parameter_value "TX_NUM_OF_LANES"] - - set_interface_property if_rx_ip_avl associatedClock if_rx_clk - set_interface_property if_rx_ip_avl associatedReset if_rx_rstn - set_interface_property if_rx_ip_avl dataBitsPerSymbol [expr ($p_num_of_rx_lanes*32)] - - set_interface_property if_tx_ip_avl associatedClock if_tx_clk - set_interface_property if_tx_ip_avl associatedReset if_tx_rstn - set_interface_property if_tx_ip_avl dataBitsPerSymbol [expr ($p_num_of_tx_lanes*32)] -} - diff --git a/library/axi_jesd_xcvr/Makefile b/library/axi_logic_analyzer/Makefile similarity index 71% rename from library/axi_jesd_xcvr/Makefile rename to library/axi_logic_analyzer/Makefile index 3cd8bf682..f538e037e 100644 --- a/library/axi_jesd_xcvr/Makefile +++ b/library/axi_logic_analyzer/Makefile @@ -5,21 +5,17 @@ #################################################################################### #################################################################################### -M_DEPS := axi_jesd_gt_ip.tcl -M_DEPS += ../scripts/adi_env.tcl -M_DEPS += ../scripts/adi_ip.tcl -M_DEPS += ../common/ad_gt_common_1.v -M_DEPS += ../common/ad_gt_channel_1.v -M_DEPS += ../common/ad_gt_es.v -M_DEPS += ../common/ad_jesd_align.v M_DEPS += ../common/ad_rst.v M_DEPS += ../common/up_axi.v M_DEPS += ../common/up_xfer_cntrl.v M_DEPS += ../common/up_xfer_status.v -M_DEPS += ../common/up_drp_cntrl.v -M_DEPS += ../common/up_gt.v -M_DEPS += axi_jesd_gt.v -M_DEPS += axi_jesd_gt_constr.xdc +M_DEPS += ../scripts/adi_env.tcl +M_DEPS += ../scripts/adi_ip.tcl +M_DEPS += axi_logic_analyzer.v +M_DEPS += axi_logic_analyzer_constr.xdc +M_DEPS += axi_logic_analyzer_ip.tcl +M_DEPS += axi_logic_analyzer_reg.v +M_DEPS += axi_logic_analyzer_trigger.v M_VIVADO := vivado -mode batch -source @@ -30,12 +26,16 @@ M_FLIST += *.log M_FLIST += component.xml M_FLIST += *.jou M_FLIST += xgui +M_FLIST += *.ip_user_files +M_FLIST += *.srcs +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil .PHONY: all clean clean-all -all: axi_jesd_gt.xpr +all: axi_logic_analyzer.xpr clean:clean-all @@ -45,9 +45,9 @@ clean-all: rm -rf $(M_FLIST) -axi_jesd_gt.xpr: $(M_DEPS) - rm -rf $(M_FLIST) - $(M_VIVADO) axi_jesd_gt_ip.tcl >> axi_jesd_gt_ip.log 2>&1 +axi_logic_analyzer.xpr: $(M_DEPS) + -rm -rf $(M_FLIST) + $(M_VIVADO) axi_logic_analyzer_ip.tcl >> axi_logic_analyzer_ip.log 2>&1 #################################################################################### #################################################################################### diff --git a/library/axi_logic_analyzer/axi_logic_analyzer.v b/library/axi_logic_analyzer/axi_logic_analyzer.v new file mode 100644 index 000000000..e00a7920c --- /dev/null +++ b/library/axi_logic_analyzer/axi_logic_analyzer.v @@ -0,0 +1,297 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_logic_analyzer ( + + input clk, + output clk_out, + + input [15:0] data_i, + output reg [15:0] data_o, + output [15:0] data_t, + input [ 1:0] trigger_i, + + output reg adc_valid, + output reg [15:0] adc_data, + + input [15:0] dac_data, + input dac_valid, + output reg dac_read, + + output trigger_out, + output [31:0] trigger_offset, + + // axi interface + + input s_axi_aclk, + input s_axi_aresetn, + input s_axi_awvalid, + input [31:0] s_axi_awaddr, + input [ 2:0] s_axi_awprot, + output s_axi_awready, + input s_axi_wvalid, + input [31:0] s_axi_wdata, + input [ 3:0] s_axi_wstrb, + output s_axi_wready, + output s_axi_bvalid, + output [ 1:0] s_axi_bresp, + input s_axi_bready, + input s_axi_arvalid, + input [31:0] s_axi_araddr, + input [ 2:0] s_axi_arprot, + output s_axi_arready, + output s_axi_rvalid, + output [31:0] s_axi_rdata, + output [ 1:0] s_axi_rresp, + input s_axi_rready); + + // internal registers + + reg [15:0] data_m1 = 'd0; + reg [15:0] data_r = 'd0; + reg [ 1:0] trigger_m1 = 'd0; + reg [ 1:0] trigger_m2 = 'd0; + reg [31:0] downsampler_counter_la = 'd0; + reg [31:0] upsampler_counter_pg = 'd0; + + reg sample_valid_la = 'd0; + reg adc_valid_d1 = 'd0; + reg adc_valid_d2 = 'd0; + + // internal signals + + wire up_clk; + wire up_rstn; + wire [13:0] up_waddr; + wire [31:0] up_wdata; + wire up_wack; + wire up_wreq; + wire up_rack; + wire [31:0] up_rdata; + wire up_rreq; + wire [13:0] up_raddr; + + wire [31:0] divider_counter_la; + wire [31:0] divider_counter_pg; + + wire [17:0] edge_detect_enable; + wire [17:0] rise_edge_enable; + wire [17:0] fall_edge_enable; + wire [17:0] low_level_enable; + wire [17:0] high_level_enable; + wire [31:0] trigger_delay; + wire trigger_logic; // 0-OR,1-AND,2-XOR,3-NOR,4-NAND,5-NXOR + wire clock_select; + wire [15:0] overwrite_enable; + wire [15:0] overwrite_data; + + wire [15:0] io_selection; + wire [15:0] od_pp_n; // 0 - push/pull, 1 - open drain + + genvar i; + + // signal name changes + + assign up_clk = s_axi_aclk; + assign up_rstn = s_axi_aresetn; + + assign trigger_offset = trigger_delay; + + generate + for (i = 0 ; i < 16; i = i + 1) begin + assign data_t[i] = od_pp_n[i] ? io_selection[i] & !data_o[i] : io_selection[i]; + always @(posedge clk) begin + data_o[i] <= overwrite_enable[i] ? overwrite_data[i] : data_r[i]; + end + end + endgenerate + + BUFGMUX BUFGMUX_inst ( + .O (clk_out), + .I0 (data_i[0]), + .I1 (trigger_i[0]), + .S (clock_select)); + + // synchronization + + always @(posedge clk) begin + data_m1 <= data_i; + trigger_m1 <= trigger_i; + trigger_m2 <= trigger_m1; + end + + // transfer data at clock frequency + // if capture is enabled + + always @(posedge clk) begin + adc_valid_d1 <= adc_valid_d2; + adc_valid <= adc_valid_d1; + if (sample_valid_la == 1'b1) begin + adc_data <= data_m1; + adc_valid_d2 <= 1'b1; + end else begin + adc_valid_d2 <= 1'b0; + end + end + + // downsampler logic analyzer + + always @(posedge clk) begin + if (reset == 1'b1) begin + sample_valid_la <= 1'b0; + downsampler_counter_la <= 32'h0; + end else begin + if (downsampler_counter_la < divider_counter_la ) begin + downsampler_counter_la <= downsampler_counter_la + 1; + sample_valid_la <= 1'b0; + end else begin + downsampler_counter_la <= 32'h0; + sample_valid_la <= 1'b1; + end + end + end + + // upsampler pattern generator + + always @(posedge clk) begin + if (reset == 1'b1) begin + upsampler_counter_pg <= 32'h0; + dac_read <= 1'b0; + end else begin + dac_read <= 1'b0; + if (upsampler_counter_pg < divider_counter_pg) begin + upsampler_counter_pg <= upsampler_counter_pg + 1; + end else begin + upsampler_counter_pg <= 32'h0; + dac_read <= 1'b1; + end + end + end + + always @(posedge clk) begin + if (dac_valid == 1'b1) begin + data_r <= dac_data; + end + end + + axi_logic_analyzer_trigger i_trigger ( + .clk (clk), + .reset (reset), + + .data (adc_data), + .trigger (trigger_m2), + + .edge_detect_enable (edge_detect_enable), + .rise_edge_enable (rise_edge_enable), + .fall_edge_enable (fall_edge_enable), + .low_level_enable (low_level_enable), + .high_level_enable (high_level_enable), + .trigger_logic (trigger_logic), + .trigger_out (trigger_out)); + + axi_logic_analyzer_reg i_registers ( + + .clk (clk), + .reset (reset), + + .divider_counter_la (divider_counter_la), + .divider_counter_pg (divider_counter_pg), + .io_selection (io_selection), + + .edge_detect_enable (edge_detect_enable), + .rise_edge_enable (rise_edge_enable), + .fall_edge_enable (fall_edge_enable), + .low_level_enable (low_level_enable), + .high_level_enable (high_level_enable), + .trigger_delay (trigger_delay), + .trigger_logic (trigger_logic), + .clock_select (clock_select), + .overwrite_enable (overwrite_enable), + .overwrite_data (overwrite_data), + .input_data (adc_data), + .od_pp_n (od_pp_n), + + // bus interface + + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata), + .up_rack (up_rack)); + + // axi interface + + up_axi i_up_axi ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_axi_awvalid (s_axi_awvalid), + .up_axi_awaddr (s_axi_awaddr), + .up_axi_awready (s_axi_awready), + .up_axi_wvalid (s_axi_wvalid), + .up_axi_wdata (s_axi_wdata), + .up_axi_wstrb (s_axi_wstrb), + .up_axi_wready (s_axi_wready), + .up_axi_bvalid (s_axi_bvalid), + .up_axi_bresp (s_axi_bresp), + .up_axi_bready (s_axi_bready), + .up_axi_arvalid (s_axi_arvalid), + .up_axi_araddr (s_axi_araddr), + .up_axi_arready (s_axi_arready), + .up_axi_rvalid (s_axi_rvalid), + .up_axi_rresp (s_axi_rresp), + .up_axi_rdata (s_axi_rdata), + .up_axi_rready (s_axi_rready), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata), + .up_rack (up_rack)); + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/library/axi_logic_analyzer/axi_logic_analyzer_constr.xdc b/library/axi_logic_analyzer/axi_logic_analyzer_constr.xdc new file mode 100644 index 000000000..794a7cae0 --- /dev/null +++ b/library/axi_logic_analyzer/axi_logic_analyzer_constr.xdc @@ -0,0 +1,30 @@ +set_property shreg_extract no [get_cells -hier -filter {name =~ *up_xfer_state*}] +set_property shreg_extract no [get_cells -hier -filter {name =~ *d_xfer_toggle*}] +set_property shreg_extract no [get_cells -hier -filter {name =~ *d_xfer_state*}] +set_property shreg_extract no [get_cells -hier -filter {name =~ *up_xfer_toggle*}] +set_property shreg_extract no [get_cells -hier -filter {name =~ *ad_rst_sync*}] + +set_false_path -from [get_cells -hier -filter {name =~ *d_xfer_toggle_reg* && IS_SEQUENTIAL}] \ + -to [get_cells -hier -filter {name =~ *up_xfer_toggle_m1_reg* && IS_SEQUENTIAL}] +set_false_path -from [get_cells -hier -filter {name =~ *up_xfer_toggle_reg* && IS_SEQUENTIAL}] \ + -to [get_cells -hier -filter {name =~ *d_xfer_toggle_m1_reg* && IS_SEQUENTIAL}] +set_false_path -from [get_cells -hier -filter {name =~ *up_xfer_data* && IS_SEQUENTIAL}] \ + -to [get_cells -hier -filter {name =~ *d_data_cntrl* && IS_SEQUENTIAL}] + +set_false_path -from [get_cells -hier -filter {name =~ *d_data_cntrl* && IS_SEQUENTIAL}] \ + -to [get_cells -hier -filter {name =~ *downsampler_counter_* && IS_SEQUENTIAL}] +set_false_path -from [get_cells -hier -filter {name =~ *d_data_cntrl* && IS_SEQUENTIAL}] \ + -to [get_cells -hier -filter {name =~ *data_r_reg* && IS_SEQUENTIAL}] +set_false_path -from [get_cells -hier -filter {name =~ *d_data_cntrl* && IS_SEQUENTIAL}] \ + -to [get_cells -hier -filter {name =~ *dac_read_reg* && IS_SEQUENTIAL}] + +set_false_path -from [get_cells -hier -filter {name =~ *d_xfer_data* && IS_SEQUENTIAL}] \ + -to [get_cells -hier -filter {name =~ *up_data_status* && IS_SEQUENTIAL}] +set_false_path -from [get_cells -hier -filter {name =~ *d_xfer_toggle_reg && IS_SEQUENTIAL}] \ + -to [get_cells -hier -filter {name =~ *up_xfer_state_m1_reg* && IS_SEQUENTIAL}] +set_false_path -from [get_cells -hier -filter {name =~ *up_xfer_toggle_reg* && IS_SEQUENTIAL}] \ + -to [get_cells -hier -filter {name =~ *d_xfer_state_m1_reg* && IS_SEQUENTIAL}] + +set_false_path -to [get_cells -hier -filter {name =~ *trigger_m1_reg* && IS_SEQUENTIAL}] + +set_false_path -to [get_cells -hier -filter {name =~ *ad_rst_sync_m1_reg* && IS_SEQUENTIAL}] diff --git a/library/axi_logic_analyzer/axi_logic_analyzer_ip.tcl b/library/axi_logic_analyzer/axi_logic_analyzer_ip.tcl new file mode 100644 index 000000000..5732ab21d --- /dev/null +++ b/library/axi_logic_analyzer/axi_logic_analyzer_ip.tcl @@ -0,0 +1,25 @@ +# ip + +source ../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip.tcl + +adi_ip_create axi_logic_analyzer +adi_ip_files axi_logic_analyzer [list \ + "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ + "$ad_hdl_dir/library/common/up_xfer_status.v" \ + "$ad_hdl_dir/library/common/ad_rst.v" \ + "$ad_hdl_dir/library/common/up_axi.v" \ + "axi_logic_analyzer_constr.xdc" \ + "axi_logic_analyzer_reg.v" \ + "axi_logic_analyzer_trigger.v" \ + "axi_logic_analyzer.v" ] + +adi_ip_properties axi_logic_analyzer +adi_ip_constraints axi_logic_analyzer [list \ + "axi_logic_analyzer_constr.xdc" ] + +ipx::remove_bus_interface {clk} [ipx::current_core] +ipx::associate_bus_interfaces -busif s_axi -clock s_axi_aclk [ipx::current_core] + +ipx::save_core [ipx::current_core] + diff --git a/library/axi_logic_analyzer/axi_logic_analyzer_reg.v b/library/axi_logic_analyzer/axi_logic_analyzer_reg.v new file mode 100644 index 000000000..3de67b7ea --- /dev/null +++ b/library/axi_logic_analyzer/axi_logic_analyzer_reg.v @@ -0,0 +1,264 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_logic_analyzer_reg ( + + input clk, + output reset, + + output [31:0] divider_counter_la, + output [31:0] divider_counter_pg, + output [15:0] io_selection, + + output [17:0] edge_detect_enable, + output [17:0] rise_edge_enable, + output [17:0] fall_edge_enable, + output [17:0] low_level_enable, + output [17:0] high_level_enable, + output [31:0] trigger_delay, + output trigger_logic, + output clock_select, + output [15:0] overwrite_enable, + output [15:0] overwrite_data, + input [15:0] input_data, + output [15:0] od_pp_n, + + // bus interface + + input up_rstn, + input up_clk, + input up_wreq, + input [13:0] up_waddr, + input [31:0] up_wdata, + output reg up_wack, + input up_rreq, + input [13:0] up_raddr, + output reg [31:0] up_rdata, + output reg up_rack); + + // internal signals + + wire up_wreq_s; + wire up_rreq_s; + + // internal registers + + reg [31:0] up_version = 32'h00010000; + reg [31:0] up_scratch = 0; + reg [31:0] up_divider_counter_la = 0; + reg [31:0] up_divider_counter_pg = 0; + reg [15:0] up_io_selection = 16'h0; + + reg [17:0] up_edge_detect_enable = 0; + reg [17:0] up_rise_edge_enable = 0; + reg [17:0] up_fall_edge_enable = 0; + reg [17:0] up_low_level_enable = 0; + reg [17:0] up_high_level_enable = 0; + reg [31:0] up_trigger_delay = 0; + reg up_trigger_logic = 0; + reg up_clock_select = 0; + reg [15:0] up_overwrite_enable = 0; + reg [15:0] up_overwrite_data = 0; + reg [15:0] up_od_pp_n = 0; + + wire [15:0] up_input_data; + + assign up_wreq_s = ((up_waddr[13:5] == 6'h00)) ? up_wreq : 1'b0; + assign up_rreq_s = ((up_raddr[13:5] == 6'h00)) ? up_rreq : 1'b0; + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_wack <= 'd0; + up_scratch <= 'd0; + up_divider_counter_la <= 'd0; + up_divider_counter_pg <= 'd0; + up_edge_detect_enable <= 'd0; + up_rise_edge_enable <= 'd0; + up_fall_edge_enable <= 'd0; + up_low_level_enable <= 'd0; + up_high_level_enable <= 'd0; + up_trigger_delay <= 'd0; + up_trigger_logic <= 'd0; + up_clock_select <= 'd0; + up_overwrite_enable <= 'd0; + up_overwrite_data <= 'd0; + up_io_selection <= 16'h0; + up_od_pp_n <= 16'h0; + end else begin + up_wack <= up_wreq_s; + if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h1)) begin + up_scratch <= up_wdata; + end + if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h2)) begin + up_divider_counter_la <= up_wdata; + end + if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h3)) begin + up_divider_counter_pg <= up_wdata; + end + if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h4)) begin + up_io_selection <= up_wdata[15:0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h5)) begin + up_edge_detect_enable <= up_wdata[17:0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h6)) begin + up_rise_edge_enable <= up_wdata[17:0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h7)) begin + up_fall_edge_enable <= up_wdata[17:0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h8)) begin + up_low_level_enable <= up_wdata[17:0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h9)) begin + up_high_level_enable <= up_wdata[17:0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'ha)) begin + up_trigger_delay <= up_wdata; + end + if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'hb)) begin + up_trigger_logic <= up_wdata[0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'hc)) begin + up_clock_select <= up_wdata[0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'hd)) begin + up_overwrite_enable <= up_wdata[15:0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'he)) begin + up_overwrite_data <= up_wdata[15:0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h10)) begin + up_od_pp_n <= up_wdata[15:0]; + end + end + end + + // processor read interface + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_rack <= 'd0; + up_rdata <= 'd0; + end else begin + up_rack <= up_rreq_s; + if (up_rreq_s == 1'b1) begin + case (up_raddr[4:0]) + 5'h0: up_rdata <= up_version; + 5'h1: up_rdata <= up_scratch; + 5'h2: up_rdata <= up_divider_counter_la; + 5'h3: up_rdata <= up_divider_counter_pg; + 5'h4: up_rdata <= {16'h0,up_io_selection}; + 5'h5: up_rdata <= {14'h0,up_edge_detect_enable}; + 5'h6: up_rdata <= {14'h0,up_rise_edge_enable}; + 5'h7: up_rdata <= {14'h0,up_fall_edge_enable}; + 5'h8: up_rdata <= {14'h0,up_low_level_enable}; + 5'h9: up_rdata <= {14'h0,up_high_level_enable}; + 5'ha: up_rdata <= up_trigger_delay; + 5'hb: up_rdata <= {31'h0,up_trigger_logic}; + 5'hc: up_rdata <= {31'h0,up_clock_select}; + 5'hd: up_rdata <= {16'h0,up_overwrite_enable}; + 5'he: up_rdata <= {16'h0,up_overwrite_data}; + 5'hf: up_rdata <= {16'h0,up_input_data}; + 5'h10: up_rdata <= {16'h0,up_od_pp_n}; + default: up_rdata <= 0; + endcase + end else begin + up_rdata <= 32'd0; + end + end + end + + ad_rst i_core_rst_reg (.preset(!up_rstn), .clk(clk), .rst(reset)); + + up_xfer_cntrl #(.DATA_WIDTH(252)) i_xfer_cntrl ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_data_cntrl ({ up_od_pp_n, // 16 + up_overwrite_data, // 16 + up_overwrite_enable, // 16 + up_clock_select, // 1 + up_trigger_logic, // 1 + up_trigger_delay, // 32 + up_high_level_enable, // 18 + up_low_level_enable, // 18 + up_fall_edge_enable, // 18 + up_rise_edge_enable, // 18 + up_edge_detect_enable, // 18 + up_io_selection, // 16 + up_divider_counter_pg, // 32 + up_divider_counter_la}), // 32 + + .up_xfer_done (), + .d_rst (1'b0), + .d_clk (clk), + .d_data_cntrl ({ od_pp_n, // 16 + overwrite_data, // 16 + overwrite_enable, // 16 + clock_select, // 1 + trigger_logic, // 1 + trigger_delay, // 32 + high_level_enable, // 18 + low_level_enable, // 18 + fall_edge_enable, // 18 + rise_edge_enable, // 18 + edge_detect_enable, // 18 + io_selection, // 16 + divider_counter_pg, // 32 + divider_counter_la})); // 32 + + up_xfer_status #(.DATA_WIDTH(16)) i_xfer_status ( + + // up interface + + .up_rstn(up_rstn), + .up_clk(up_clk), + .up_data_status(up_input_data), + + // device interface + + .d_rst(1'd0), + .d_clk(clk), + .d_data_status(input_data)); + +endmodule + +// *************************************************************************** +// *************************************************************************** + diff --git a/library/axi_logic_analyzer/axi_logic_analyzer_trigger.v b/library/axi_logic_analyzer/axi_logic_analyzer_trigger.v new file mode 100644 index 000000000..b634a1f45 --- /dev/null +++ b/library/axi_logic_analyzer/axi_logic_analyzer_trigger.v @@ -0,0 +1,114 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_logic_analyzer_trigger ( + + input clk, + input reset, + + input [15:0] data, + input [ 1:0] trigger, + + input [17:0] edge_detect_enable, + input [17:0] rise_edge_enable, + input [17:0] fall_edge_enable, + input [17:0] low_level_enable, + input [17:0] high_level_enable, + + input trigger_logic, + + output trigger_out); + + reg [ 17:0] data_m1 = 'd0; + reg [ 17:0] low_level = 'd0; + reg [ 17:0] high_level = 'd0; + reg [ 17:0] edge_detect = 'd0; + reg [ 17:0] rise_edge = 'd0; + reg [ 17:0] fall_edge = 'd0; + reg [ 31:0] delay_count = 'd0; + + reg trigger_active; + + assign trigger_out = trigger_active; + + // trigger logic: + // 0 OR + // 1 AND + + always @(*) begin + case (trigger_logic) + 0: trigger_active = | ((edge_detect & edge_detect_enable) | + (rise_edge & rise_edge_enable) | + (fall_edge & fall_edge_enable) | + (low_level & low_level_enable) | + (high_level & high_level_enable)); + 1: trigger_active = | (((edge_detect & edge_detect_enable) | !(|edge_detect_enable)) & + ((rise_edge & rise_edge_enable) | !(|rise_edge_enable)) & + ((fall_edge & fall_edge_enable) | !(|fall_edge_enable)) & + ((low_level & low_level_enable) | !(|low_level_enable)) & + ((high_level & high_level_enable) | !(|high_level_enable))); + default: trigger_active = 1'b1; + endcase + end + + // internal signals + + always @(posedge clk) begin + if (reset == 1'b1) begin + data_m1 <= 'd0; + edge_detect <= 'd0; + rise_edge <= 'd0; + fall_edge <= 'd0; + low_level <= 'd0; + high_level <= 'd0; + end else begin + data_m1 <= {trigger, data} ; + edge_detect <= data_m1 ^ {trigger, data}; + rise_edge <= (data_m1 ^ {trigger, data} ) & {trigger, data}; + fall_edge <= (data_m1 ^ {trigger, data}) & ~{trigger, data}; + low_level <= ~{trigger, data}; + high_level <= {trigger, data}; + end + end + + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/library/axi_mc_controller/Makefile b/library/axi_mc_controller/Makefile index d1e1e455a..0b0937a3d 100644 --- a/library/axi_mc_controller/Makefile +++ b/library/axi_mc_controller/Makefile @@ -5,23 +5,22 @@ #################################################################################### #################################################################################### -M_DEPS := axi_mc_controller_ip.tcl -M_DEPS += ../scripts/adi_env.tcl -M_DEPS += ../scripts/adi_ip.tcl -M_DEPS += ../common/up_axi.v M_DEPS += ../common/ad_rst.v +M_DEPS += ../common/up_adc_channel.v +M_DEPS += ../common/up_adc_common.v +M_DEPS += ../common/up_axi.v +M_DEPS += ../common/up_clock_mon.v M_DEPS += ../common/up_delay_cntrl.v M_DEPS += ../common/up_xfer_cntrl.v M_DEPS += ../common/up_xfer_status.v -M_DEPS += ../common/up_clock_mon.v -M_DEPS += ../common/up_delay_cntrl.v -M_DEPS += ../common/up_adc_common.v -M_DEPS += ../common/up_adc_channel.v -M_DEPS += motor_driver.v -M_DEPS += delay.v -M_DEPS += control_registers.v -M_DEPS += axi_mc_controller_constr.xdc +M_DEPS += ../scripts/adi_env.tcl +M_DEPS += ../scripts/adi_ip.tcl M_DEPS += axi_mc_controller.v +M_DEPS += axi_mc_controller_constr.xdc +M_DEPS += axi_mc_controller_ip.tcl +M_DEPS += control_registers.v +M_DEPS += delay.v +M_DEPS += motor_driver.v M_VIVADO := vivado -mode batch -source @@ -32,6 +31,10 @@ M_FLIST += *.log M_FLIST += component.xml M_FLIST += *.jou M_FLIST += xgui +M_FLIST += *.ip_user_files +M_FLIST += *.srcs +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil @@ -48,7 +51,7 @@ clean-all: axi_mc_controller.xpr: $(M_DEPS) - rm -rf $(M_FLIST) + -rm -rf $(M_FLIST) $(M_VIVADO) axi_mc_controller_ip.tcl >> axi_mc_controller_ip.log 2>&1 #################################################################################### diff --git a/library/axi_mc_controller/axi_mc_controller.v b/library/axi_mc_controller/axi_mc_controller.v index e802feef8..2f7d79688 100644 --- a/library/axi_mc_controller/axi_mc_controller.v +++ b/library/axi_mc_controller/axi_mc_controller.v @@ -84,7 +84,10 @@ module axi_mc_controller output s_axi_rvalid, output [1:0] s_axi_rresp, output [31:0] s_axi_rdata, - input s_axi_rready + input s_axi_rready, + input [ 2:0] s_axi_awprot, + input [ 2:0] s_axi_arprot + ); //------------------------------------------------------------------------------ diff --git a/library/axi_mc_controller/control_registers.v b/library/axi_mc_controller/control_registers.v index 589234e97..ed72e73dc 100644 --- a/library/axi_mc_controller/control_registers.v +++ b/library/axi_mc_controller/control_registers.v @@ -130,6 +130,7 @@ always @(negedge up_rstn or posedge up_clk) begin if (up_rstn == 0) begin + reserved_r1 <= 'd0; up_wack <= 1'b0; control_r <= 'h0; reference_speed_r <= 'd1000; diff --git a/library/axi_mc_current_monitor/Makefile b/library/axi_mc_current_monitor/Makefile index 5df04372d..08e2ba4c3 100644 --- a/library/axi_mc_current_monitor/Makefile +++ b/library/axi_mc_current_monitor/Makefile @@ -5,21 +5,21 @@ #################################################################################### #################################################################################### -M_DEPS := axi_mc_current_monitor_ip.tcl -M_DEPS += ../scripts/adi_env.tcl -M_DEPS += ../scripts/adi_ip.tcl M_DEPS += ../common/ad_rst.v +M_DEPS += ../common/up_adc_channel.v +M_DEPS += ../common/up_adc_common.v M_DEPS += ../common/up_axi.v +M_DEPS += ../common/up_clock_mon.v M_DEPS += ../common/up_delay_cntrl.v M_DEPS += ../common/up_xfer_cntrl.v M_DEPS += ../common/up_xfer_status.v -M_DEPS += ../common/up_clock_mon.v -M_DEPS += ../common/up_adc_common.v -M_DEPS += ../common/up_adc_channel.v -M_DEPS += dec256sinc24b.v +M_DEPS += ../scripts/adi_env.tcl +M_DEPS += ../scripts/adi_ip.tcl M_DEPS += ad7401.v -M_DEPS += axi_mc_current_monitor_constr.xdc M_DEPS += axi_mc_current_monitor.v +M_DEPS += axi_mc_current_monitor_constr.xdc +M_DEPS += axi_mc_current_monitor_ip.tcl +M_DEPS += dec256sinc24b.v M_VIVADO := vivado -mode batch -source @@ -30,6 +30,10 @@ M_FLIST += *.log M_FLIST += component.xml M_FLIST += *.jou M_FLIST += xgui +M_FLIST += *.ip_user_files +M_FLIST += *.srcs +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil @@ -46,7 +50,7 @@ clean-all: axi_mc_current_monitor.xpr: $(M_DEPS) - rm -rf $(M_FLIST) + -rm -rf $(M_FLIST) $(M_VIVADO) axi_mc_current_monitor_ip.tcl >> axi_mc_current_monitor_ip.log 2>&1 #################################################################################### diff --git a/library/axi_mc_current_monitor/axi_mc_current_monitor.v b/library/axi_mc_current_monitor/axi_mc_current_monitor.v index 71585d809..89ededd6b 100644 --- a/library/axi_mc_current_monitor/axi_mc_current_monitor.v +++ b/library/axi_mc_current_monitor/axi_mc_current_monitor.v @@ -77,7 +77,10 @@ module axi_mc_current_monitor ( output s_axi_rvalid, output [1:0] s_axi_rresp, output [31:0] s_axi_rdata, - input s_axi_rready + input s_axi_rready, + input [ 2:0] s_axi_awprot, + input [ 2:0] s_axi_arprot + ); //------------------------------------------------------------------------------ @@ -193,7 +196,7 @@ ad7401 vbus_if( .data_rd_ready_o(), .adc_mdata_i(adc_vbus_dat_i)); -up_adc_channel #(.ADC_CHANNEL_ID(0)) i_up_adc_channel_ia( +up_adc_channel #(.CHANNEL_ID(0)) i_up_adc_channel_ia( .adc_clk(adc_clk_o), .adc_rst(adc_rst), .adc_enable(adc_enable_ia), @@ -239,7 +242,7 @@ up_adc_channel #(.ADC_CHANNEL_ID(0)) i_up_adc_channel_ia( .up_rdata (up_rdata_0_s), .up_rack (up_rack_0_s)); -up_adc_channel #(.ADC_CHANNEL_ID(1)) i_up_adc_channel_ib( +up_adc_channel #(.CHANNEL_ID(1)) i_up_adc_channel_ib( .adc_clk(adc_clk_o), .adc_rst(adc_rst), .adc_enable(adc_enable_ib), @@ -285,7 +288,7 @@ up_adc_channel #(.ADC_CHANNEL_ID(1)) i_up_adc_channel_ib( .up_rdata (up_rdata_1_s), .up_rack (up_rack_1_s)); -up_adc_channel #(.ADC_CHANNEL_ID(2)) i_up_adc_channel_vbus( +up_adc_channel #(.CHANNEL_ID(2)) i_up_adc_channel_vbus( .adc_clk(adc_clk_o), .adc_rst(adc_rst), .adc_enable(adc_enable_vbus), @@ -401,6 +404,7 @@ up_axi i_up_axi( .up_wreq (up_wreq_s), .up_waddr (up_waddr_s), .up_wdata (up_wdata_s), + .up_wack (up_wack), .up_rreq (up_rreq_s), .up_raddr (up_raddr_s), .up_rdata (up_rdata), diff --git a/library/axi_mc_speed/Makefile b/library/axi_mc_speed/Makefile index 53fa8b598..50a3910b5 100644 --- a/library/axi_mc_speed/Makefile +++ b/library/axi_mc_speed/Makefile @@ -5,22 +5,22 @@ #################################################################################### #################################################################################### -M_DEPS := axi_mc_speed_ip.tcl -M_DEPS += ../scripts/adi_env.tcl -M_DEPS += ../scripts/adi_ip.tcl M_DEPS += ../common/ad_rst.v +M_DEPS += ../common/up_adc_channel.v +M_DEPS += ../common/up_adc_common.v M_DEPS += ../common/up_axi.v -M_DEPS += ../common/up_delay_cntrl.v M_DEPS += ../common/up_clock_mon.v +M_DEPS += ../common/up_delay_cntrl.v M_DEPS += ../common/up_xfer_cntrl.v M_DEPS += ../common/up_xfer_status.v -M_DEPS += ../common/up_adc_common.v -M_DEPS += ../common/up_adc_channel.v -M_DEPS += debouncer.v -M_DEPS += speed_detector.v -M_DEPS += delay_30_degrees.v -M_DEPS += axi_mc_speed_constr.xdc +M_DEPS += ../scripts/adi_env.tcl +M_DEPS += ../scripts/adi_ip.tcl M_DEPS += axi_mc_speed.v +M_DEPS += axi_mc_speed_constr.xdc +M_DEPS += axi_mc_speed_ip.tcl +M_DEPS += debouncer.v +M_DEPS += delay_30_degrees.v +M_DEPS += speed_detector.v M_VIVADO := vivado -mode batch -source @@ -31,6 +31,10 @@ M_FLIST += *.log M_FLIST += component.xml M_FLIST += *.jou M_FLIST += xgui +M_FLIST += *.ip_user_files +M_FLIST += *.srcs +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil @@ -47,7 +51,7 @@ clean-all: axi_mc_speed.xpr: $(M_DEPS) - rm -rf $(M_FLIST) + -rm -rf $(M_FLIST) $(M_VIVADO) axi_mc_speed_ip.tcl >> axi_mc_speed_ip.log 2>&1 #################################################################################### diff --git a/library/axi_mc_speed/axi_mc_speed.v b/library/axi_mc_speed/axi_mc_speed.v index eae590835..4bd6cb0b9 100644 --- a/library/axi_mc_speed/axi_mc_speed.v +++ b/library/axi_mc_speed/axi_mc_speed.v @@ -68,7 +68,10 @@ module axi_mc_speed output s_axi_rvalid, output [ 1:0] s_axi_rresp, output [31:0] s_axi_rdata, - input s_axi_rready); + input s_axi_rready, + input [ 2:0] s_axi_awprot, + input [ 2:0] s_axi_arprot +); //------------------------------------------------------------------------------ //----------- Registers Declarations ------------------------------------------- diff --git a/library/axi_spdif_rx/Makefile b/library/axi_spdif_rx/Makefile index d56a4b265..1504dd869 100644 --- a/library/axi_spdif_rx/Makefile +++ b/library/axi_spdif_rx/Makefile @@ -5,19 +5,19 @@ #################################################################################### #################################################################################### -M_DEPS := axi_spdif_rx_ip.tcl -M_DEPS += ../scripts/adi_env.tcl -M_DEPS += ../scripts/adi_ip.tcl M_DEPS += ../common/axi_ctrlif.vhd M_DEPS += ../common/axi_streaming_dma_rx_fifo.vhd -M_DEPS += ../common/pl330_dma_fifo.vhd M_DEPS += ../common/dma_fifo.vhd -M_DEPS += rx_phase_det.vhd -M_DEPS += rx_package.vhd -M_DEPS += rx_decode.vhd -M_DEPS += rx_status_reg.vhd +M_DEPS += ../common/pl330_dma_fifo.vhd +M_DEPS += ../scripts/adi_env.tcl +M_DEPS += ../scripts/adi_ip.tcl M_DEPS += axi_spdif_rx.vhd M_DEPS += axi_spdif_rx_constr.xdc +M_DEPS += axi_spdif_rx_ip.tcl +M_DEPS += rx_decode.vhd +M_DEPS += rx_package.vhd +M_DEPS += rx_phase_det.vhd +M_DEPS += rx_status_reg.vhd M_VIVADO := vivado -mode batch -source @@ -28,6 +28,10 @@ M_FLIST += *.log M_FLIST += component.xml M_FLIST += *.jou M_FLIST += xgui +M_FLIST += *.ip_user_files +M_FLIST += *.srcs +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil @@ -44,7 +48,7 @@ clean-all: axi_spdif_rx.xpr: $(M_DEPS) - rm -rf $(M_FLIST) + -rm -rf $(M_FLIST) $(M_VIVADO) axi_spdif_rx_ip.tcl >> axi_spdif_rx_ip.log 2>&1 #################################################################################### diff --git a/library/axi_spdif_rx/axi_spdif_rx.vhd b/library/axi_spdif_rx/axi_spdif_rx.vhd index 881f02470..88975beba 100644 --- a/library/axi_spdif_rx/axi_spdif_rx.vhd +++ b/library/axi_spdif_rx/axi_spdif_rx.vhd @@ -84,6 +84,9 @@ entity axi_spdif_rx is S_AXI_BRESP : out std_logic_vector(1 downto 0); S_AXI_BVALID : out std_logic; S_AXI_AWREADY : out std_logic; + S_AXI_AWPROT : in std_logic_vector(2 downto 0); + S_AXI_ARPROT : in std_logic_vector(2 downto 0); + --AXI STREAM interface M_AXIS_ACLK : in std_logic; @@ -408,7 +411,6 @@ begin begin if rising_edge(S_AXI_ACLK) then if S_AXI_ARESETN = '0' then - version_reg <= (others => '0'); control_reg <= (others => '0'); else if wr_stb = '1' then @@ -421,7 +423,7 @@ begin end if; end process; - process (rd_addr, version_reg, control_reg, chstatus_reg) + process (rd_addr, version_reg, control_reg, chstatus_reg, sampled_data) begin case rd_addr is when 0 => rd_data <= version_reg; diff --git a/library/axi_spdif_rx/axi_spdif_rx_ip.tcl b/library/axi_spdif_rx/axi_spdif_rx_ip.tcl index 9b22be7d6..c82d1ae97 100644 --- a/library/axi_spdif_rx/axi_spdif_rx_ip.tcl +++ b/library/axi_spdif_rx/axi_spdif_rx_ip.tcl @@ -17,6 +17,7 @@ adi_ip_files axi_spdif_rx [list \ "axi_spdif_rx_constr.xdc"] adi_ip_properties axi_spdif_rx +adi_ip_infer_streaming_interfaces axi_spdif_rx adi_ip_constraints axi_spdif_tx axi_spdif_rx_constr.xdc adi_add_bus "DMA_ACK" "slave" \ diff --git a/library/axi_spdif_tx/Makefile b/library/axi_spdif_tx/Makefile index bf7a33117..4e933fff4 100644 --- a/library/axi_spdif_tx/Makefile +++ b/library/axi_spdif_tx/Makefile @@ -5,17 +5,17 @@ #################################################################################### #################################################################################### -M_DEPS := axi_spdif_tx_ip.tcl -M_DEPS += ../scripts/adi_env.tcl -M_DEPS += ../scripts/adi_ip.tcl M_DEPS += ../common/axi_ctrlif.vhd M_DEPS += ../common/axi_streaming_dma_tx_fifo.vhd -M_DEPS += ../common/pl330_dma_fifo.vhd M_DEPS += ../common/dma_fifo.vhd -M_DEPS += tx_package.vhd -M_DEPS += tx_encoder.vhd +M_DEPS += ../common/pl330_dma_fifo.vhd +M_DEPS += ../scripts/adi_env.tcl +M_DEPS += ../scripts/adi_ip.tcl M_DEPS += axi_spdif_tx.vhd M_DEPS += axi_spdif_tx_constr.xdc +M_DEPS += axi_spdif_tx_ip.tcl +M_DEPS += tx_encoder.vhd +M_DEPS += tx_package.vhd M_VIVADO := vivado -mode batch -source @@ -26,6 +26,10 @@ M_FLIST += *.log M_FLIST += component.xml M_FLIST += *.jou M_FLIST += xgui +M_FLIST += *.ip_user_files +M_FLIST += *.srcs +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil @@ -42,7 +46,7 @@ clean-all: axi_spdif_tx.xpr: $(M_DEPS) - rm -rf $(M_FLIST) + -rm -rf $(M_FLIST) $(M_VIVADO) axi_spdif_tx_ip.tcl >> axi_spdif_tx_ip.log 2>&1 #################################################################################### diff --git a/library/axi_spdif_tx/axi_spdif_tx.vhd b/library/axi_spdif_tx/axi_spdif_tx.vhd index 2a0d1d2d5..eedf3ca9e 100644 --- a/library/axi_spdif_tx/axi_spdif_tx.vhd +++ b/library/axi_spdif_tx/axi_spdif_tx.vhd @@ -63,12 +63,14 @@ entity axi_spdif_tx is S_AXI_ACLK : in std_logic; S_AXI_ARESETN : in std_logic; S_AXI_AWADDR : in std_logic_vector(S_AXI_ADDRESS_WIDTH-1 downto 0); + S_AXI_AWPROT : in std_logic_vector(2 downto 0); S_AXI_AWVALID : in std_logic; S_AXI_WDATA : in std_logic_vector(S_AXI_DATA_WIDTH-1 downto 0); S_AXI_WSTRB : in std_logic_vector((S_AXI_DATA_WIDTH/8)-1 downto 0); S_AXI_WVALID : in std_logic; S_AXI_BREADY : in std_logic; S_AXI_ARADDR : in std_logic_vector(S_AXI_ADDRESS_WIDTH-1 downto 0); + S_AXI_ARPROT : in std_logic_vector(2 downto 0); S_AXI_ARVALID : in std_logic; S_AXI_RREADY : in std_logic; S_AXI_ARREADY : out std_logic; diff --git a/library/axi_spdif_tx/axi_spdif_tx_ip.tcl b/library/axi_spdif_tx/axi_spdif_tx_ip.tcl index fdc4c38c3..6f87d0d5f 100644 --- a/library/axi_spdif_tx/axi_spdif_tx_ip.tcl +++ b/library/axi_spdif_tx/axi_spdif_tx_ip.tcl @@ -15,6 +15,7 @@ adi_ip_files axi_spdif_tx [list \ "axi_spdif_tx_constr.xdc" ] adi_ip_properties axi_spdif_tx +adi_ip_infer_streaming_interfaces axi_spdif_tx adi_ip_constraints axi_spdif_tx axi_spdif_tx_constr.xdc adi_add_bus "DMA_ACK" "slave" \ diff --git a/library/axi_usb_fx3/Makefile b/library/axi_usb_fx3/Makefile index 54123fcfc..904d9deb6 100644 --- a/library/axi_usb_fx3/Makefile +++ b/library/axi_usb_fx3/Makefile @@ -5,14 +5,14 @@ #################################################################################### #################################################################################### -M_DEPS := axi_usb_fx3_ip.tcl +M_DEPS += ../common/up_axi.v M_DEPS += ../scripts/adi_env.tcl M_DEPS += ../scripts/adi_ip.tcl -M_DEPS += ../common/up_axi.v +M_DEPS += axi_usb_fx3.v M_DEPS += axi_usb_fx3_core.v M_DEPS += axi_usb_fx3_if.v +M_DEPS += axi_usb_fx3_ip.tcl M_DEPS += axi_usb_fx3_reg.v -M_DEPS += axi_usb_fx3.v M_VIVADO := vivado -mode batch -source @@ -23,6 +23,10 @@ M_FLIST += *.log M_FLIST += component.xml M_FLIST += *.jou M_FLIST += xgui +M_FLIST += *.ip_user_files +M_FLIST += *.srcs +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil @@ -39,7 +43,7 @@ clean-all: axi_usb_fx3.xpr: $(M_DEPS) - rm -rf $(M_FLIST) + -rm -rf $(M_FLIST) $(M_VIVADO) axi_usb_fx3_ip.tcl >> axi_usb_fx3_ip.log 2>&1 #################################################################################### diff --git a/library/axi_usb_fx3/axi_usb_fx3.v b/library/axi_usb_fx3/axi_usb_fx3.v index f6e19cbdf..4478990d2 100644 --- a/library/axi_usb_fx3/axi_usb_fx3.v +++ b/library/axi_usb_fx3/axi_usb_fx3.v @@ -65,6 +65,7 @@ module axi_usb_fx3 ( irq, // DEBUG + debug_fx32dma, debug_dma2fx3, debug_status, @@ -91,6 +92,7 @@ module axi_usb_fx3 ( s_axi_aresetn, s_axi_awvalid, s_axi_awaddr, + s_axi_awprot, s_axi_awready, s_axi_wvalid, s_axi_wdata, @@ -101,6 +103,7 @@ module axi_usb_fx3 ( s_axi_bready, s_axi_arvalid, s_axi_araddr, + s_axi_arprot, s_axi_arready, s_axi_rvalid, s_axi_rresp, @@ -112,12 +115,12 @@ module axi_usb_fx3 ( input dma_rdy; input dma_wmk; - input [10:0] fifo_rdy; + input [ 3:0] fifo_rdy; output pclk; - output [31:0] data; - output [4:0] addr; + inout [31:0] data; + output [ 1:0] addr; output slcs_n; output slrd_n; @@ -127,8 +130,9 @@ module axi_usb_fx3 ( output epswitch_n; // DEBUG - output [35:0] debug_fx32dma; - output [34:0] debug_dma2fx3; + + output [74:0] debug_fx32dma; + output [73:0] debug_dma2fx3; output [14:0] debug_status; // irq @@ -157,6 +161,7 @@ module axi_usb_fx3 ( input s_axi_aresetn; input s_axi_awvalid; input [31:0] s_axi_awaddr; + input [ 2:0] s_axi_awprot; output s_axi_awready; input s_axi_wvalid; input [31:0] s_axi_wdata; @@ -167,6 +172,7 @@ module axi_usb_fx3 ( input s_axi_bready; input s_axi_arvalid; input [31:0] s_axi_araddr; + input [ 2:0] s_axi_arprot; output s_axi_arready; output s_axi_rvalid; output [ 1:0] s_axi_rresp; @@ -223,6 +229,7 @@ module axi_usb_fx3 ( wire fifo8_direction; wire fifo9_direction; wire fifoa_direction; + wire [10:0] fifo_direction; wire fx32dma_valid; wire fx32dma_ready; @@ -245,17 +252,25 @@ module axi_usb_fx3 ( wire [ 4:0] fifo_num; wire [10:0] fifo_ready; + wire [31:0] length_fx32dma; + wire [31:0] length_dma2fx3; + + wire trig; + wire zlp; + // signal name changes assign up_clk = s_axi_aclk; assign pclk = s_axi_aclk; assign up_rstn = s_axi_aresetn; + assign fifo_direction = {fifo9_direction, fifo8_direction, fifo7_direction, fifo6_direction, fifo5_direction, fifo4_direction, fifo3_direction, fifo2_direction, fifo1_direction, fifo0_direction}; + // DEBUG - assign debug_dma2fx3 = {dma2fx3_ready, dma2fx3_valid, dma2fx3_data, dma2fx3_eop}; - assign debug_fx32dma = {fx32dma_eop,fx32dma_ready, fx32dma_valid, fx32dma_data, fx32dma_sop}; - assign debug_status = {irq, error, monitor_error, test_mode_tpg, test_mode_tpm, trig, fifo_num}; + assign debug_dma2fx3 = {s_axis_tdata, dma2fx3_data, s_axis_tkeep, s_axis_tlast, s_axis_tvalid, s_axis_tready, dma2fx3_ready, dma2fx3_valid, dma2fx3_eop}; + assign debug_fx32dma = {fx32dma_eop, m_axis_tdata, fx32dma_data, m_axis_tkeep, m_axis_tlast, m_axis_tvalid, m_axis_tready, fx32dma_ready, fx32dma_valid, fx32dma_sop}; + assign debug_status = {irq, error, monitor_error, test_mode_tpg, test_mode_tpm, trig, fifo_num}; // packetizer, TPM/TPG and DMA interface @@ -298,6 +313,9 @@ module axi_usb_fx3 ( .fifoa_header_size(fifoa_header_size), .fifoa_buffer_size(fifoa_buffer_size), + .length_fx32dma(length_fx32dma), + .length_dma2fx3(length_dma2fx3), + .fx32dma_valid(fx32dma_valid), .fx32dma_ready(fx32dma_ready), .fx32dma_data(fx32dma_data), @@ -317,6 +335,8 @@ module axi_usb_fx3 ( .test_mode_tpg(test_mode_tpg), .monitor_error(monitor_error), + .zlp(zlp), + .fifo_num(fifo_num)); // register map @@ -328,6 +348,7 @@ module axi_usb_fx3 ( .eot_fx32dma(eot_fx32dma), .eot_dma2fx3(eot_dma2fx3), .trig(trig), + .zlp(zlp), .fifo_num(fifo_num), .error(error), @@ -382,6 +403,9 @@ module axi_usb_fx3 ( .fifoa_header_size(fifoa_header_size), .fifoa_buffer_size(fifoa_buffer_size), + .length_fx32dma(length_fx32dma), + .length_dma2fx3(length_dma2fx3), + .up_rstn(up_rstn), .up_clk(up_clk), .up_wreq(up_wreq), @@ -397,10 +421,12 @@ module axi_usb_fx3 ( axi_usb_fx3_if fx3_if( + .pclk(pclk), //output clk 100 Mhz and 180 phase shift + .reset_n(up_rstn), + .dma_rdy(dma_rdy), .dma_wmk(dma_wmk), .fifo_rdy(fifo_rdy), - .pclk(pclk), //output clk 100 Mhz and 180 phase shift .data(data), .addr(addr), //output fifo address .slcs_n(slcs_n), //output chip select @@ -409,16 +435,19 @@ module axi_usb_fx3 ( .slwr_n(slwr_n), //output write select .pktend_n(pktend_n), //output pkt end .epswitch_n(epswitch_n), //output pkt end - .fifo_num(fifo_num), - .trig(trig), - .test_mode_tpm(test_mode_tpm), + .fifo_ready(fifo_ready), + .fifo_num(fifo_num), + .fifo_direction(fifo_direction), + .trig(trig), + .fx32dma_valid(fx32dma_valid), .fx32dma_ready(fx32dma_ready), .fx32dma_data(fx32dma_data), .fx32dma_sop(fx32dma_sop), .fx32dma_eop(fx32dma_eop), + .eot_fx32dma(eot_fx32dma), .dma2fx3_ready(dma2fx3_ready), .dma2fx3_valid(dma2fx3_valid), diff --git a/library/axi_usb_fx3/axi_usb_fx3_core.v b/library/axi_usb_fx3/axi_usb_fx3_core.v index e0ed6114e..943354361 100644 --- a/library/axi_usb_fx3/axi_usb_fx3_core.v +++ b/library/axi_usb_fx3/axi_usb_fx3_core.v @@ -35,8 +35,6 @@ // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // *************************************************************************** // *************************************************************************** -// *************************************************************************** -// *************************************************************************** `timescale 1ns/100ps @@ -111,6 +109,9 @@ module axi_usb_fx3_core ( fifof_header_size, fifof_buffer_size, + length_fx32dma, + length_dma2fx3, + // fx3 interface // IN -> TO HOST / FX3 // OUT -> FROM HOST / FX3 @@ -134,6 +135,8 @@ module axi_usb_fx3_core ( test_mode_tpg, monitor_error, + zlp, + fifo_num); input clk; @@ -205,6 +208,9 @@ module axi_usb_fx3_core ( input [ 7:0] fifof_header_size; input [15:0] fifof_buffer_size; + output [31:0] length_fx32dma; + output [31:0] length_dma2fx3; + // FX3 interface // IN -> ZYNQ TO HOST / FX3 // OUT -> ZYNQ FROM HOST / FX3 @@ -213,7 +219,7 @@ module axi_usb_fx3_core ( output fx32dma_ready; input [31:0] fx32dma_data; input fx32dma_sop; - input fx32dma_eop; + output fx32dma_eop; input dma2fx3_ready; output dma2fx3_valid; @@ -228,6 +234,8 @@ module axi_usb_fx3_core ( input [ 2:0] test_mode_tpg; output monitor_error; + input zlp; + input [ 4:0] fifo_num; // internal parameters @@ -244,7 +252,7 @@ module axi_usb_fx3_core ( // internal registers - reg [31:0] data_size_transaction = 32'h0; + reg [31:0] data_size_transaction = 32'hffffffff; reg [15:0] buffer_size_current = 16'h0; reg [ 7:0] header_size_current = 8'h0; @@ -268,18 +276,24 @@ module axi_usb_fx3_core ( reg [ 7:0] header_pointer = 8'h0; reg header_read = 1'b0; - reg [31:0] dma2fx3_counter = 1'b0; - reg [31:0] footer_pointer = 1'b0; + reg [31:0] dma2fx3_counter = 32'h0; + reg [ 7:0] footer_pointer = 8'h0; reg s_axis_tready = 1'b0; reg dma2fx3_valid = 1'b0; reg [31:0] dma2fx3_data = 32'h0; + reg [31:0] dma2fx3_data_reg = 32'h0; reg dma2fx3_eop = 1'b0; reg [31:0] expected_data = 32'h0; reg monitor_error = 1'b0; reg first_transfer = 1'b0; + reg [31:0] length_fx32dma = 0; + reg [31:0] length_dma2fx3 = 0; + + reg fx32dma_eop = 1'b0; + function [31:0] pn23; input [31:0] din; reg [31:0] dout; @@ -369,132 +383,6 @@ module axi_usb_fx3_core ( assign fx32dma_ready = m_axis_tready; - // state machine - - always @(posedge clk) begin - if (reset == 1'b1 || error_fx32dma == 1'b1) begin - state_fx32dma <= IDLE; - end else begin - state_fx32dma <= next_state_fx32dma; - end - end - - always @(*) begin - case(state_fx32dma) - IDLE: - if(fx32dma_sop == 1'b1) begin - next_state_fx32dma = READ_HEADER; - end else begin - next_state_fx32dma = state_fx32dma; - end - READ_HEADER: - if(header_read == 1'b1) begin - next_state_fx32dma = READ_DATA; - end else begin - next_state_fx32dma = state_fx32dma; - end - READ_DATA: - if(data_size_transaction <= 4) begin - next_state_fx32dma = IDLE; - end else begin - next_state_fx32dma = state_fx32dma; - end - default: next_state_fx32dma = IDLE; - endcase - end - - always @(posedge clk) begin - case(state_fx32dma) - IDLE: begin - m_axis_tvalid <= 1'b0; - m_axis_tkeep <= 4'h0; - m_axis_tlast <= 1'b0; - error_fx32dma <= 1'b0; - eot_fx32dma <= 1'b0; - header_read <= 1'b0; - header_pointer <= 8'h4; - first_transfer <= 1'b1; - monitor_error <= 1'b0; - if (fx32dma_sop == 1'b1) begin - if(fx32dma_valid == 1'b1) begin - if(fx32dma_data != 32'hf00ff00f) begin - error_fx32dma <= 1'b1; - end else begin - error_fx32dma <= 1'b0; - end - end - end - case (test_mode_tpm) - 4'h1: expected_data <= 32'haaaaaaaa; - default: expected_data <= 32'hffffffff; - endcase - end - READ_HEADER: begin - m_axis_tvalid <= 1'b0; - m_axis_tkeep <= 4'h0; - m_axis_tlast <= 1'b0; - error_fx32dma <= 1'b0; - eot_fx32dma <= 1'b0; - first_transfer <= 1'b1; - monitor_error <= 1'b0; - if( fx32dma_valid == 1'b1) begin - if(header_pointer < header_size_current - 8) begin - header_pointer <= header_pointer + 4; - end else begin - header_read <= 1'b1; - end - if (header_pointer == 4) begin - data_size_transaction <= fx32dma_data; - if (fx32dma_data > buffer_size_current) begin - error_fx32dma <= 1'b1; - end - end - end - end - READ_DATA: begin - m_axis_tvalid <= fx32dma_valid; - m_axis_tdata <= fx32dma_data; - if (fx32dma_valid == 1'b1) begin - first_transfer <= 1'b0; - if (data_size_transaction > 4) begin - m_axis_tkeep <= 4'hf; - m_axis_tlast <= 1'b0; - data_size_transaction <= data_size_transaction - 4; - end else begin - m_axis_tlast <= 1'b1; - eot_fx32dma <= 1'b1; - case (data_size_transaction) - 1: m_axis_tkeep <= 4'h1; - 2: m_axis_tkeep <= 4'h3; - 3: m_axis_tkeep <= 4'h7; - default: m_axis_tkeep <= 4'hf; - endcase - end - end - // monitor - if (test_mode_active_tpm == 1'b1) begin - if (first_transfer == 1) begin - expected_data <= fx32dma_data; - end else begin - case (test_mode_tpm) - 4'h1: expected_data <= ~expected_data; - 4'h2: expected_data <= ~expected_data; - 4'h3: expected_data <= pn9(expected_data); - 4'h4: expected_data <= pn23(expected_data); - 4'h7: expected_data <= expected_data + 1; - default: expected_data <= 0; - endcase - if (expected_data != m_axis_tdata) begin - monitor_error <= 1'b1; - end else begin - monitor_error <= 1'b0; - end - end - end - end - endcase - end - always @(*) begin case (fifo_num) 5'h0: buffer_size_current = fifo0_buffer_size; @@ -536,6 +424,161 @@ module axi_usb_fx3_core ( endcase end + // state machine + + always @(posedge clk) begin + if (reset == 1'b1 || error_fx32dma == 1'b1) begin + state_fx32dma <= IDLE; + end else begin + state_fx32dma <= next_state_fx32dma; + end + end + + always @(*) begin + case(state_fx32dma) + IDLE: + if(fx32dma_sop == 1'b1) begin + next_state_fx32dma = READ_HEADER; + end else begin + next_state_fx32dma = state_fx32dma; + end + READ_HEADER: + if(header_read == 1'b1) begin + next_state_fx32dma = READ_DATA; + end else begin + next_state_fx32dma = state_fx32dma; + end + READ_DATA: + if(data_size_transaction <= 4) begin + next_state_fx32dma = IDLE; + end else begin + next_state_fx32dma = state_fx32dma; + end + default: next_state_fx32dma = IDLE; + endcase + end + + always @(*) begin + m_axis_tdata = fx32dma_data; + fx32dma_eop = 1'b0; + m_axis_tlast = 1'b0; + case(state_fx32dma) + IDLE: begin + m_axis_tvalid = 1'b0; + m_axis_tkeep = 4'h0; + eot_fx32dma = 1'b0; + end + READ_HEADER: begin + m_axis_tvalid = 1'b0; + m_axis_tkeep = 4'h0; + m_axis_tlast = 1'b0; + eot_fx32dma = 1'b0; + end + READ_DATA: begin + m_axis_tvalid = fx32dma_valid; + if (fx32dma_valid == 1'b1) begin + if (data_size_transaction > 12 ) begin + fx32dma_eop = 1'b0; + end else begin + fx32dma_eop = 1'b1; + end + if (data_size_transaction > 4) begin + m_axis_tlast = 1'b0; + m_axis_tkeep = 4'hf; + eot_fx32dma = 1'b0; + end else begin + m_axis_tlast = 1'b1; + eot_fx32dma = 1'b1; + m_axis_tlast = 1'b1; + case (data_size_transaction) + 1: m_axis_tkeep = 4'h1; + 2: m_axis_tkeep = 4'h3; + 3: m_axis_tkeep = 4'h7; + default: m_axis_tkeep = 4'hf; + endcase + end + end else begin + m_axis_tkeep = 4'h0; + eot_fx32dma = 1'b0; + end + end + default: begin + m_axis_tvalid = 1'b0; + m_axis_tkeep = 4'h0; + m_axis_tlast = 1'b0; + eot_fx32dma = 1'b0; + end + endcase + end + + always @(posedge clk) begin + header_read <= 1'b0; + if (state_fx32dma == IDLE) begin + if (fx32dma_sop == 1'b1) begin + header_pointer <= 8'h4; + if (fx32dma_data != 32'h0ff00ff0) begin + error_fx32dma <= 1'b1; + end else begin + error_fx32dma <= 1'b0; + end + end + case (test_mode_tpm) + 4'h1: expected_data <= 32'haaaaaaaa; + default: expected_data <= 32'hffffffff; + endcase + end + if (state_fx32dma == READ_HEADER) begin + if (fx32dma_valid == 1'b1) begin + if (m_axis_tready == 1'b0) begin + error_fx32dma <= 1'b1; + end + if(header_pointer < header_size_current - 4) begin + header_pointer <= header_pointer + 8; + end else begin + header_read <= 1'b1; + end + if (header_pointer == 4) begin + data_size_transaction <= fx32dma_data; + length_fx32dma <= fx32dma_data; + if (fx32dma_data > buffer_size_current) begin + error_fx32dma <= 1'b1; + end + end + end + end + if (state_fx32dma == READ_DATA) begin + first_transfer <= 1'b1; + if (fx32dma_valid == 1'b1) begin + first_transfer <= 1'b0; + if (data_size_transaction > 4) begin + data_size_transaction <= data_size_transaction - 4; + end + end + + // monitor + + if (test_mode_active_tpm == 1'b1) begin + if (first_transfer == 1) begin + expected_data <= fx32dma_data; + end else begin + case (test_mode_tpm) + 4'h1: expected_data <= ~expected_data; + 4'h2: expected_data <= ~expected_data; + 4'h3: expected_data <= pn9(expected_data); + 4'h4: expected_data <= pn23(expected_data); + 4'h7: expected_data <= expected_data + 1; + default: expected_data <= 0; + endcase + if (expected_data != m_axis_tdata) begin + monitor_error <= 1'b1; + end else begin + monitor_error <= 1'b0; + end + end + end + end + end + // dma2fx3 always @(posedge clk) begin @@ -550,94 +593,129 @@ module axi_usb_fx3_core ( case(state_dma2fx3) IDLE: if(dma2fx3_ready == 1'b1) begin - next_state_dma2fx3 = READ_DATA; + if (zlp == 1'b1) begin + next_state_dma2fx3 = ADD_FOOTER; + end else begin + next_state_dma2fx3 = READ_DATA; + end end else begin - next_state_dma2fx3 = state_dma2fx3; + next_state_dma2fx3 = IDLE; end READ_DATA: if(s_axis_tlast == 1'b1 || dma2fx3_counter >= buffer_size_current - 4) begin next_state_dma2fx3 = ADD_FOOTER; end else begin - next_state_dma2fx3 = state_dma2fx3; + next_state_dma2fx3 = READ_DATA; end ADD_FOOTER: if(dma2fx3_eop == 1'b1) begin next_state_dma2fx3 = IDLE; end else begin - next_state_dma2fx3 = state_dma2fx3; + next_state_dma2fx3 = ADD_FOOTER; end - default: next_state_dma2fx3 = IDLE; + default: next_state_dma2fx3 = IDLE; + endcase + end + + always @(*) begin + case(state_dma2fx3) + IDLE: begin + s_axis_tready = 1'b0; + dma2fx3_valid = 1'b0; + eot_dma2fx3 = 1'b0; + dma2fx3_eop = 1'b0; + dma2fx3_data = dma2fx3_data_reg; + end + READ_DATA: begin + eot_dma2fx3 = 1'b0; + if (test_mode_active_tpg == 1'b1) begin + s_axis_tready = 1'b0; + dma2fx3_valid = 1'b1; + end else begin + dma2fx3_valid = s_axis_tvalid & s_axis_tready; + s_axis_tready = dma2fx3_ready; + end + dma2fx3_eop = 1'b0; + if (test_mode_active_tpg == 1'b1) begin + dma2fx3_data = dma2fx3_data_reg; + end else begin + dma2fx3_data = s_axis_tdata; + end + end + ADD_FOOTER: begin + s_axis_tready = 1'b0; + dma2fx3_valid = 1'b1; + if (footer_pointer == header_size_current) begin + dma2fx3_eop = 1'b1; + eot_dma2fx3 = 1'b1; + end else begin + dma2fx3_eop = 1'b0; + eot_dma2fx3 = 1'b0; + end + dma2fx3_data = dma2fx3_data_reg; + end + default: begin + s_axis_tready = 1'b0; + dma2fx3_valid = 1'b0; + eot_dma2fx3 = 1'b0; + dma2fx3_eop = 1'b0; + dma2fx3_data = dma2fx3_data_reg; + end endcase end always @(posedge clk) begin - case(state_dma2fx3) - IDLE: begin - dma2fx3_eop <= 1'b0; - eot_dma2fx3 <= 1'b0; - s_axis_tready <= 1'b0; - footer_pointer <= 0; - dma2fx3_counter <= 0; - dma2fx3_valid <= 1'b0; - case (test_mode_tpg) - 4'h1: dma2fx3_data <= 32'haaaaaaaa; - default: dma2fx3_data <= 32'hffffffff; - endcase + if(state_dma2fx3 == IDLE) begin + footer_pointer <= 4; + dma2fx3_counter <= 0; + case (test_mode_tpg) + 4'h1: dma2fx3_data_reg <= 32'haaaaaaaa; + default: dma2fx3_data_reg <= 32'hffffffff; + endcase + if (zlp == 1'b1) begin + dma2fx3_data_reg <= 32'h0ff00ff0; end - READ_DATA: begin - dma2fx3_eop <= 1'b0; - eot_dma2fx3 <= 1'b0; - footer_pointer <= 0; - if (test_mode_active_tpg == 1'b1) begin - s_axis_tready <= 1'b0; - dma2fx3_valid <= 1'b1; - if (dma2fx3_ready == 1'b1) begin - dma2fx3_counter <= dma2fx3_counter + 4; - case (test_mode_tpg) - 4'h1: dma2fx3_data <= ~dma2fx3_data; - 4'h2: dma2fx3_data <= ~dma2fx3_data; - 4'h3: dma2fx3_data <= pn9(dma2fx3_data); - 4'h4: dma2fx3_data <= pn23(dma2fx3_data); - 4'h7: dma2fx3_data <= dma2fx3_data + 1; - default: dma2fx3_data <= 0; - endcase - end - end else begin - dma2fx3_data <= s_axis_tdata; - if (s_axis_tlast == 1'b0) begin - s_axis_tready <= dma2fx3_ready; + end + + if(state_dma2fx3 == READ_DATA) begin + if (test_mode_active_tpg == 1'b1) begin + if (dma2fx3_ready == 1'b1) begin + dma2fx3_counter <= dma2fx3_counter + 4; + if (dma2fx3_counter >= buffer_size_current - 4) begin + dma2fx3_data_reg <= 32'h0ff00ff0; end else begin - s_axis_tready <= 1'b0; - end - dma2fx3_valid <= s_axis_tvalid & s_axis_tready; - if (s_axis_tvalid== 1'b1 && s_axis_tready == 1'b1) begin - case (s_axis_tkeep) - 1: dma2fx3_counter <= dma2fx3_counter + 1; - 3: dma2fx3_counter <= dma2fx3_counter + 2; - 7: dma2fx3_counter <= dma2fx3_counter + 3; - default: dma2fx3_counter <= dma2fx3_counter + 4; + case (test_mode_tpg) + 4'h1: dma2fx3_data_reg <= ~dma2fx3_data_reg; + 4'h2: dma2fx3_data_reg <= ~dma2fx3_data_reg; + 4'h3: dma2fx3_data_reg <= pn9(dma2fx3_data_reg); + 4'h4: dma2fx3_data_reg <= pn23(dma2fx3_data_reg); + 4'h7: dma2fx3_data_reg <= dma2fx3_data_reg + 1; + default: dma2fx3_data_reg <= 0; endcase end end - end - ADD_FOOTER: begin - dma2fx3_valid <= ~eot_dma2fx3; - dma2fx3_eop <= 1'b0; - eot_dma2fx3 <= 1'b0; - s_axis_tready <= 1'b0; - footer_pointer <= footer_pointer + 4; - case(footer_pointer) - 32'h0: dma2fx3_data <= 32'hf00ff00f; - 32'h4: dma2fx3_data <= dma2fx3_counter; - 32'h8: dma2fx3_data <= 32'h0; - default: dma2fx3_data <= 32'h0; - endcase - if (footer_pointer == header_size_current - 4) begin - dma2fx3_eop <= 1'b1; - eot_dma2fx3 <= 1'b1; + end else begin + dma2fx3_data_reg <= 32'h0ff00ff0; + if (s_axis_tvalid== 1'b1 && s_axis_tready == 1'b1) begin + case (s_axis_tkeep) + 1: dma2fx3_counter <= dma2fx3_counter + 1; + 3: dma2fx3_counter <= dma2fx3_counter + 2; + 7: dma2fx3_counter <= dma2fx3_counter + 3; + default: dma2fx3_counter <= dma2fx3_counter + 4; + endcase end end - endcase + end + + if(state_dma2fx3 == ADD_FOOTER) begin + footer_pointer <= footer_pointer + 4; + length_dma2fx3 <= dma2fx3_counter; + case(footer_pointer) + 32'h4: dma2fx3_data_reg <= dma2fx3_counter; + 32'h8: dma2fx3_data_reg <= 32'h0; + default: dma2fx3_data_reg <= 32'h0; + endcase + end end endmodule diff --git a/library/axi_usb_fx3/axi_usb_fx3_if.v b/library/axi_usb_fx3/axi_usb_fx3_if.v index 7e1a1f6aa..2a0a387ba 100644 --- a/library/axi_usb_fx3/axi_usb_fx3_if.v +++ b/library/axi_usb_fx3/axi_usb_fx3_if.v @@ -45,6 +45,7 @@ module axi_usb_fx3_if ( fifo_rdy, pclk, //output clk 100 Mhz and 180 phase shift + reset_n, data, addr, //output fifo address @@ -57,31 +58,32 @@ module axi_usb_fx3_if ( epswitch_n, //output pkt end fifo_num, + fifo_direction, trig, fifo_ready, - test_mode_tpm, - fx32dma_valid, fx32dma_ready, fx32dma_data, fx32dma_sop, fx32dma_eop, + eot_fx32dma, dma2fx3_ready, dma2fx3_valid, dma2fx3_data, dma2fx3_eop); + input pclk; + input reset_n; + input dma_rdy; input dma_wmk; - input [10:0] fifo_rdy; + input [ 3:0] fifo_rdy; - input pclk; - - output [31:0] data; - output [4:0] addr; + inout [31:0] data; + output [ 1:0] addr; output slcs_n; output slrd_n; @@ -92,199 +94,226 @@ module axi_usb_fx3_if ( output [10:0] fifo_ready; - input [ 2:0] test_mode_tpm; - - input [4:0] fifo_num; + input [ 4:0] fifo_num; + input [10:0] fifo_direction; input trig; output fx32dma_valid; input fx32dma_ready; output [31:0] fx32dma_data; output fx32dma_sop; - output fx32dma_eop; + input fx32dma_eop; + input eot_fx32dma; input dma2fx3_valid; output dma2fx3_ready; input [31:0] dma2fx3_data; input dma2fx3_eop; - // internal wires - - wire fx32dma_sop; - // internal registers - wire fx32dma_valid; + reg [10:0] fifo_ready = 0; - reg [10:0] fifo_ready; + reg [31:0] fx32dma_data = 0; - reg internal_trig = 0; - reg trig_d = 0; - reg [31:0] internal_counter = 0; - reg [ 2:0] packet_number = 0; - reg [31:0] data_size = 0; - reg [31:0] fx32dma_data = 0; - reg [31:0] generated_data = 0; - reg fx32dma_eop; + reg [ 3:0] state_gpif_ii = 4'h0; + reg [ 3:0] next_state_gpif_ii = 4'h0; - reg transaction_in_progress = 0; + reg current_direction = 0; + reg current_fifo = 0; + reg slcs_n = 0; + reg slcs_n_d1 = 0; + reg slcs_n_d2 = 0; + reg slcs_n_d3 = 0; + reg slcs_n_d4 = 0; + reg slrd_n = 0; + reg slrd_n_d1 = 0; + reg slrd_n_d2 = 0; + reg slrd_n_d3 = 0; + reg sloe_n = 0; + reg [ 1:0] addr = 0; + reg sloe_n_d1 = 0; + reg slwr_n = 0; + reg fx32dma_valid = 0; + reg dma2fx3_ready = 0; + reg fx32dma_sop = 0; + reg pktend_n = 0; + reg pip = 0; - assign fx32dma_sop = internal_trig ; - assign fx32dma_valid = transaction_in_progress; - function [31:0] pn23; - input [31:0] din; - reg [31:0] dout; - begin - dout[31] = din[22] ^ din[17]; - dout[30] = din[21] ^ din[16]; - dout[29] = din[20] ^ din[15]; - dout[28] = din[19] ^ din[14]; - dout[27] = din[18] ^ din[13]; - dout[26] = din[17] ^ din[12]; - dout[25] = din[16] ^ din[11]; - dout[24] = din[15] ^ din[10]; - dout[23] = din[14] ^ din[ 9]; - dout[22] = din[13] ^ din[ 8]; - dout[21] = din[12] ^ din[ 7]; - dout[20] = din[11] ^ din[ 6]; - dout[19] = din[10] ^ din[ 5]; - dout[18] = din[ 9] ^ din[ 4]; - dout[17] = din[ 8] ^ din[ 3]; - dout[16] = din[ 7] ^ din[ 2]; - dout[15] = din[ 6] ^ din[ 1]; - dout[14] = din[ 5] ^ din[ 0]; - dout[13] = din[ 4] ^ din[22] ^ din[17]; - dout[12] = din[ 3] ^ din[21] ^ din[16]; - dout[11] = din[ 2] ^ din[20] ^ din[15]; - dout[10] = din[ 1] ^ din[19] ^ din[14]; - dout[ 9] = din[ 0] ^ din[18] ^ din[13]; - dout[ 8] = din[22] ^ din[12]; - dout[ 7] = din[21] ^ din[11]; - dout[ 6] = din[20] ^ din[10]; - dout[ 5] = din[19] ^ din[ 9]; - dout[ 4] = din[18] ^ din[ 8]; - dout[ 3] = din[17] ^ din[ 7]; - dout[ 2] = din[16] ^ din[ 6]; - dout[ 1] = din[15] ^ din[ 5]; - dout[ 0] = din[14] ^ din[ 4]; - pn23 = dout; - end - endfunction + localparam IDLE = 4'b0001; + localparam READ_START = 4'b0010; + localparam READ_DATA = 4'b0100; + localparam WRITE_DATA = 4'b1000; - function [31:0] pn9; - input [31:0] din; - reg [31:0] dout; - begin - dout[31] = din[ 8] ^ din[ 4]; - dout[30] = din[ 7] ^ din[ 3]; - dout[29] = din[ 6] ^ din[ 2]; - dout[28] = din[ 5] ^ din[ 1]; - dout[27] = din[ 4] ^ din[ 0]; - dout[26] = din[ 3] ^ din[ 8] ^ din[ 4]; - dout[25] = din[ 2] ^ din[ 7] ^ din[ 3]; - dout[24] = din[ 1] ^ din[ 6] ^ din[ 2]; - dout[23] = din[ 0] ^ din[ 5] ^ din[ 1]; - dout[22] = din[ 8] ^ din[ 0]; - dout[21] = din[ 7] ^ din[ 8] ^ din[ 4]; - dout[20] = din[ 6] ^ din[ 7] ^ din[ 3]; - dout[19] = din[ 5] ^ din[ 6] ^ din[ 2]; - dout[18] = din[ 4] ^ din[ 5] ^ din[ 1]; - dout[17] = din[ 3] ^ din[ 4] ^ din[ 0]; - dout[16] = din[ 2] ^ din[ 3] ^ din[ 8] ^ din[ 4]; - dout[15] = din[ 1] ^ din[ 2] ^ din[ 7] ^ din[ 3]; - dout[14] = din[ 0] ^ din[ 1] ^ din[ 6] ^ din[ 2]; - dout[13] = din[ 8] ^ din[ 0] ^ din[ 4] ^ din[ 5] ^ din[ 1]; - dout[12] = din[ 7] ^ din[ 8] ^ din[ 3] ^ din[ 0]; - dout[11] = din[ 6] ^ din[ 7] ^ din[ 2] ^ din[ 8] ^ din[ 4]; - dout[10] = din[ 5] ^ din[ 6] ^ din[ 1] ^ din[ 7] ^ din[ 3]; - dout[ 9] = din[ 4] ^ din[ 5] ^ din[ 0] ^ din[ 6] ^ din[ 2]; - dout[ 8] = din[ 3] ^ din[ 8] ^ din[ 5] ^ din[ 1]; - dout[ 7] = din[ 2] ^ din[ 4] ^ din[ 7] ^ din[ 0]; - dout[ 6] = din[ 1] ^ din[ 3] ^ din[ 6] ^ din[ 8] ^ din[ 4]; - dout[ 5] = din[ 0] ^ din[ 2] ^ din[ 5] ^ din[ 7] ^ din[ 3]; - dout[ 4] = din[ 8] ^ din[ 1] ^ din[ 6] ^ din[ 2]; - dout[ 3] = din[ 7] ^ din[ 0] ^ din[ 5] ^ din[ 1]; - dout[ 2] = din[ 6] ^ din[ 8] ^ din[ 0]; - dout[ 1] = din[5] ^ din[7] ^ din[8] ^ din[4]; - dout[ 0] = din[4] ^ din[6] ^ din[7] ^ din[3]; - pn9 = dout; - end - endfunction + assign data = (state_gpif_ii == WRITE_DATA && dma2fx3_valid && current_fifo) ? dma2fx3_data : 32'hz; + assign epswitch_n = 1'b1; - always @(posedge pclk) begin - trig_d <= trig; - fx32dma_eop <= 1'b0; - internal_trig <= trig & ~trig_d; - if (transaction_in_progress == 1'b0) begin - transaction_in_progress <= trig & ~trig_d; - end else begin - if (internal_counter >= data_size + 12) begin - transaction_in_progress = 1'b0; - fx32dma_eop <= 1'b1; + always @(fifo_num, fifo_rdy, fifo_direction) begin + case(fifo_num) + 5'h0: begin + current_direction = fifo_direction[0]; + current_fifo = fifo_rdy[0]; + end + 5'h1: begin + current_direction = fifo_direction[1]; + current_fifo = fifo_rdy[1]; + end + 5'h2: begin + current_direction = fifo_direction[2]; + current_fifo = fifo_rdy[2]; + end + 5'h3: begin + current_direction = fifo_direction[3]; + current_fifo = fifo_rdy[3]; + end + 5'h4: begin + current_direction = fifo_direction[4]; + current_fifo = fifo_rdy[0]; + end + 5'h5: begin + current_direction = fifo_direction[5]; + current_fifo = fifo_rdy[0]; + end + 5'h6: begin + current_direction = fifo_direction[6]; + current_fifo = fifo_rdy[0]; + end + 5'h7: begin + current_direction = fifo_direction[7]; + current_fifo = fifo_rdy[0]; + end + 5'h8: begin + current_direction = fifo_direction[8]; + current_fifo = fifo_rdy[0]; + end + 5'h9: begin + current_direction = fifo_direction[9]; + current_fifo = fifo_rdy[0]; + end + default: begin + current_direction = 0; + current_fifo = fifo_rdy[0]; end - end - end - - always @(posedge pclk) begin - if (internal_trig == 1'b1 )begin - internal_counter <= 4; - packet_number <= packet_number + 1; - end else if (transaction_in_progress == 1'b1) begin - internal_counter <= internal_counter + 4; - end else begin - internal_counter <= 0; - end - end - - always @(packet_number) begin - case (packet_number) - 0: data_size = 1; - 1: data_size = 2; - 2: data_size = 3; - 3: data_size = 4; - 4: data_size = 512; - 5: data_size = 1024; - 6: data_size = 32767; - 7: data_size = 32768; - default: data_size = 16; endcase end - always@(internal_counter, data_size, internal_counter, generated_data) begin - case (internal_counter) - 5'h0: fx32dma_data <= 32'hf00ff00f; - 5'h4: fx32dma_data <= data_size; - 5'h8: fx32dma_data <= 0; - 5'hc: fx32dma_data <= 32'hffffffff; - default: fx32dma_data <= generated_data; + // STATE MACHINE GPIF II + always @(posedge pclk) begin + if (reset_n == 1'b0 || trig == 1'b0 ) begin + state_gpif_ii <= IDLE; + end else begin + state_gpif_ii <= next_state_gpif_ii; + end + end + + always @(*) begin + case(state_gpif_ii) + IDLE: + if(trig == 1'b1 && current_fifo == 1'b1) begin + if (current_direction == 0) begin + next_state_gpif_ii = READ_START; + end else begin + next_state_gpif_ii = WRITE_DATA; + end + end else begin + next_state_gpif_ii = IDLE; + end + READ_START: + next_state_gpif_ii = READ_DATA; + READ_DATA: + if (eot_fx32dma == 1'b1) begin + next_state_gpif_ii = IDLE; + end else begin + next_state_gpif_ii = READ_DATA; + end + WRITE_DATA: + if(dma2fx3_eop == 1'b1) begin + next_state_gpif_ii = IDLE; + end else begin + next_state_gpif_ii = WRITE_DATA; + end + default: next_state_gpif_ii = IDLE; + endcase + end + + always @(*) begin + case(state_gpif_ii) + IDLE: begin + slcs_n = 1'b1; + sloe_n = 1'b1; + slrd_n = 1'b1; + fx32dma_valid = 1'b0; + fx32dma_sop = 1'b0; + fx32dma_data = 32'h0; + slwr_n = 1'b1; + pktend_n = 1'b1; + dma2fx3_ready = 1'b0; + end + READ_START: begin + slcs_n = 1'b0; + sloe_n = 1'b0; + slrd_n = 1'b1; + fx32dma_valid = 1'b0; + fx32dma_sop = 1'b0; + fx32dma_data = 32'h0; + slwr_n = 1'b1; + pktend_n = 1'b1; + dma2fx3_ready = 1'b0; + end + READ_DATA: begin + slcs_n = 1'b0; + sloe_n = 1'b0; + slrd_n = !fx32dma_ready | fx32dma_eop; + fx32dma_valid = !slcs_n_d4 & !slrd_n_d3; + fx32dma_sop = !slcs_n_d4 & !slrd_n_d3 & pip; + fx32dma_data = data; + slwr_n = 1'b1; + pktend_n = 1'b1; + dma2fx3_ready = 1'b0; + end + WRITE_DATA: begin + slcs_n = 1'b0; + sloe_n = 1'b1; + slrd_n = 1'b1; + fx32dma_valid = 1'b0; + fx32dma_sop = 1'b0; + fx32dma_data = 32'h0; + slwr_n = !dma2fx3_valid | !current_fifo; + dma2fx3_ready = current_fifo; + pktend_n = !dma2fx3_eop; + end + default: begin + slcs_n = 1'b1; + sloe_n = 1'b1; + slrd_n = 1'b1; + fx32dma_valid = 1'b0; + fx32dma_sop = 1'b0; + fx32dma_data = 32'h0; + slwr_n = 1'b1; + pktend_n = 1'b1; + dma2fx3_ready = 1'b0; + end endcase end always @(posedge pclk) begin - if (fx32dma_sop == 1'b1) begin - if (test_mode_tpm == 3'h1) begin - generated_data <= 32'haaaaaaaa; - end else begin - generated_data <= 32'hffffffff; - end + fifo_ready <= {7'h0,fifo_rdy}; + slrd_n_d1 <= slrd_n; + slrd_n_d2 <= slrd_n_d1; + slrd_n_d3 <= slrd_n_d2; + slcs_n_d1 <= slcs_n; + slcs_n_d2 <= slcs_n_d1; + slcs_n_d3 <= slcs_n_d2; + slcs_n_d4 <= slcs_n_d3; + addr <= fifo_num[1:0]; + if (state_gpif_ii == IDLE) begin + pip <= 1'b1; end else begin - case(test_mode_tpm) - 4'h0: generated_data <= generated_data + 32'h10; - 4'h1: generated_data <= ~generated_data; - 4'h2: generated_data <= ~generated_data; - 4'h3: generated_data <= pn9(generated_data); - 4'h4: generated_data <= pn23(generated_data); - 4'h7: generated_data <= generated_data + 1; - default: generated_data <= generated_data + 32'h10; - endcase + if (fx32dma_sop == 1'b1) begin + pip <= 1'b0; + end end end - // dma2fx3 - - assign dma2fx3_ready = 1'b1; - assign data = dma2fx3_data; - assign pktend_n = ~dma2fx3_eop; - assign slwr_n = ~dma2fx3_valid; endmodule diff --git a/library/axi_usb_fx3/axi_usb_fx3_ip.tcl b/library/axi_usb_fx3/axi_usb_fx3_ip.tcl index fc62ff2c6..cd4a33526 100644 --- a/library/axi_usb_fx3/axi_usb_fx3_ip.tcl +++ b/library/axi_usb_fx3/axi_usb_fx3_ip.tcl @@ -13,24 +13,9 @@ adi_ip_files axi_usb_fx3 [list \ adi_ip_properties axi_usb_fx3 -ipx::remove_bus_interface rst [ipx::current_core] -ipx::remove_bus_interface clk [ipx::current_core] -ipx::remove_bus_interface l_clk [ipx::current_core] -ipx::remove_bus_interface delay_clk [ipx::current_core] +adi_ip_infer_streaming_interfaces axi_usb_fx3 -adi_add_bus_clock "s_axi_aclk" "s_axis" -adi_add_bus_clock "s_axi_aclk" "m_axis" - -ipx::add_bus_parameter ASSOCIATED_BUSIF [ipx::get_bus_interfaces s_axi_aclk \ - -of_objects [ipx::current_core]] -set_property value s_axi [ipx::get_bus_parameters ASSOCIATED_BUSIF \ - -of_objects [ipx::get_bus_interfaces s_axi_aclk \ - -of_objects [ipx::current_core]]] - -#adi_ip_constraints axi_usb_fx3 [list \ -# "axi_usb_fx3_constr.xdc" ] - -#set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]] -#set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]] +ipx::associate_bus_interfaces -busif m_axis -clock s_axi_aclk [ipx::current_core] +ipx::associate_bus_interfaces -busif s_axis -clock s_axi_aclk [ipx::current_core] ipx::save_core [ipx::current_core] diff --git a/library/axi_usb_fx3/axi_usb_fx3_reg.v b/library/axi_usb_fx3/axi_usb_fx3_reg.v index 3d9c6e750..2bf33d20a 100644 --- a/library/axi_usb_fx3/axi_usb_fx3_reg.v +++ b/library/axi_usb_fx3/axi_usb_fx3_reg.v @@ -48,6 +48,7 @@ module axi_usb_fx3_reg ( eot_fx32dma, eot_dma2fx3, trig, + zlp, fifo_num, error, @@ -102,6 +103,9 @@ module axi_usb_fx3_reg ( fifoa_header_size, fifoa_buffer_size, + length_fx32dma, + length_dma2fx3, + // bus interface up_rstn, @@ -122,6 +126,7 @@ module axi_usb_fx3_reg ( input eot_fx32dma; input eot_dma2fx3; output trig; + output zlp; output [ 4:0] fifo_num; input error; @@ -176,6 +181,9 @@ module axi_usb_fx3_reg ( output [ 7:0] fifoa_header_size; output [15:0] fifoa_buffer_size; + input [31:0] length_fx32dma; + input [31:0] length_dma2fx3; + // bus interface input up_rstn; @@ -235,6 +243,7 @@ module axi_usb_fx3_reg ( assign up_rreq_s = ((up_raddr[13:8] == 6'h00)) ? up_rreq : 1'b0; assign trig = transfer_config[31]; + assign zlp = transfer_config[30]; assign fifo_num = transfer_config[4:0]; assign test_mode_tpm = tpm_config[2:0]; @@ -325,6 +334,7 @@ module axi_usb_fx3_reg ( tpm_status <= 32'h0; tpg_config <= 32'h0; tpg_status <= 32'h0; + fifo_status <= 32'h0; end else begin up_wack <= up_wreq_s; if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h0)) begin @@ -366,6 +376,7 @@ module axi_usb_fx3_reg ( end if (eot_fx32dma == 1'b1 || eot_dma2fx3 == 1'b1 || error == 1'b1) begin transfer_config[31] <= 1'b0; + transfer_config[30] <= 1'b0; end else if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h12)) begin transfer_config <= up_wdata; end @@ -420,6 +431,8 @@ module axi_usb_fx3_reg ( 5'h15: up_rdata <= tpm_status; 5'h16: up_rdata <= tpg_config; 5'h17: up_rdata <= tpg_status; + 5'h18: up_rdata <= length_fx32dma; + 5'h19: up_rdata <= length_dma2fx3; default: up_rdata <= 0; endcase end else begin diff --git a/library/cn0363/cn0363_dma_sequencer/Makefile b/library/cn0363/cn0363_dma_sequencer/Makefile index 29972c388..82adb137b 100644 --- a/library/cn0363/cn0363_dma_sequencer/Makefile +++ b/library/cn0363/cn0363_dma_sequencer/Makefile @@ -5,10 +5,13 @@ #################################################################################### #################################################################################### -M_DEPS := cn0363_dma_sequencer_ip.tcl M_DEPS += ../../scripts/adi_env.tcl M_DEPS += ../../scripts/adi_ip.tcl M_DEPS += cn0363_dma_sequencer.v +M_DEPS += cn0363_dma_sequencer_ip.tcl + +M_DEPS += ../../interfaces/fifo_wr.xml +M_DEPS += ../../interfaces/fifo_wr_rtl.xml M_VIVADO := vivado -mode batch -source @@ -19,6 +22,10 @@ M_FLIST += *.log M_FLIST += component.xml M_FLIST += *.jou M_FLIST += xgui +M_FLIST += *.ip_user_files +M_FLIST += *.srcs +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil @@ -35,7 +42,7 @@ clean-all: cn0363_dma_sequencer.xpr: $(M_DEPS) - rm -rf $(M_FLIST) + -rm -rf $(M_FLIST) $(M_VIVADO) cn0363_dma_sequencer_ip.tcl >> cn0363_dma_sequencer_ip.log 2>&1 #################################################################################### diff --git a/library/cn0363/cn0363_dma_sequencer/cn0363_dma_sequencer.v b/library/cn0363/cn0363_dma_sequencer/cn0363_dma_sequencer.v index dac6814b8..9db2eb39d 100644 --- a/library/cn0363/cn0363_dma_sequencer/cn0363_dma_sequencer.v +++ b/library/cn0363/cn0363_dma_sequencer/cn0363_dma_sequencer.v @@ -1,38 +1,38 @@ module cn0363_dma_sequencer ( - input clk, - input resetn, + input clk, + input resetn, - input [31:0] phase, - input phase_valid, - output reg phase_ready, + input [31:0] phase, + input phase_valid, + output reg phase_ready, - input [23:0] data, - input data_valid, - output reg data_ready, + input [23:0] data, + input data_valid, + output reg data_ready, - input [31:0] data_filtered, - input data_filtered_valid, - output reg data_filtered_ready, + input [31:0] data_filtered, + input data_filtered_valid, + output reg data_filtered_ready, - input [31:0] i_q, - input i_q_valid, - output reg i_q_ready, + input [31:0] i_q, + input i_q_valid, + output reg i_q_ready, - input [31:0] i_q_filtered, - input i_q_filtered_valid, - output reg i_q_filtered_ready, + input [31:0] i_q_filtered, + input i_q_filtered_valid, + output reg i_q_filtered_ready, - output overflow, + output overflow, - output reg [31:0] dma_wr_data, - output reg dma_wr_en, - output reg dma_wr_sync, - input dma_wr_overflow, - input dma_wr_xfer_req, + output reg [31:0] dma_wr_data, + output reg dma_wr_en, + output reg dma_wr_sync, + input dma_wr_overflow, + input dma_wr_xfer_req, - input [13:0] channel_enable, + input [13:0] channel_enable, - output processing_resetn + output processing_resetn ); reg [3:0] count = 'h00; @@ -41,120 +41,120 @@ assign overflow = dma_wr_overflow; assign processing_resetn = dma_wr_xfer_req; always @(posedge clk) begin - if (processing_resetn == 1'b0) begin - count <= 'h0; - end else begin - case (count) - 'h0: if (phase_valid) count <= count + 1; - 'h1: if (data_valid) count <= count + 1; - 'h2: if (data_filtered_valid) count <= count + 1; - 'h3: if (i_q_valid) count <= count + 1; - 'h4: if (i_q_valid) count <= count + 1; - 'h5: if (i_q_filtered_valid) count <= count + 1; - 'h6: if (i_q_filtered_valid) count <= count + 1; - 'h7: if (phase_valid) count <= count + 1; - 'h8: if (data_valid) count <= count + 1; - 'h9: if (data_filtered_valid) count <= count + 1; - 'ha: if (i_q_valid) count <= count + 1; - 'hb: if (i_q_valid) count <= count + 1; - 'hc: if (i_q_filtered_valid) count <= count + 1; - 'hd: if (i_q_filtered_valid) count <= 'h00; - endcase - end + if (processing_resetn == 1'b0) begin + count <= 'h0; + end else begin + case (count) + 'h0: if (phase_valid) count <= count + 1; + 'h1: if (data_valid) count <= count + 1; + 'h2: if (data_filtered_valid) count <= count + 1; + 'h3: if (i_q_valid) count <= count + 1; + 'h4: if (i_q_valid) count <= count + 1; + 'h5: if (i_q_filtered_valid) count <= count + 1; + 'h6: if (i_q_filtered_valid) count <= count + 1; + 'h7: if (phase_valid) count <= count + 1; + 'h8: if (data_valid) count <= count + 1; + 'h9: if (data_filtered_valid) count <= count + 1; + 'ha: if (i_q_valid) count <= count + 1; + 'hb: if (i_q_valid) count <= count + 1; + 'hc: if (i_q_filtered_valid) count <= count + 1; + 'hd: if (i_q_filtered_valid) count <= 'h00; + endcase + end end always @(posedge clk) begin - case (count) - 'h0: dma_wr_data <= phase; - 'h1: dma_wr_data <= {8'h00,data[23:0]}; - 'h2: dma_wr_data <= data_filtered; - 'h3: dma_wr_data <= i_q; - 'h4: dma_wr_data <= i_q; - 'h5: dma_wr_data <= i_q_filtered; - 'h6: dma_wr_data <= i_q_filtered; - 'h7: dma_wr_data <= phase; - 'h8: dma_wr_data <= {8'h00,data[23:0]}; - 'h9: dma_wr_data <= data_filtered; - 'ha: dma_wr_data <= i_q; - 'hb: dma_wr_data <= i_q; - 'hc: dma_wr_data <= i_q_filtered; - 'hd: dma_wr_data <= i_q_filtered; - endcase + case (count) + 'h0: dma_wr_data <= phase; + 'h1: dma_wr_data <= {8'h00,data[23:0]}; + 'h2: dma_wr_data <= data_filtered; + 'h3: dma_wr_data <= i_q; + 'h4: dma_wr_data <= i_q; + 'h5: dma_wr_data <= i_q_filtered; + 'h6: dma_wr_data <= i_q_filtered; + 'h7: dma_wr_data <= phase; + 'h8: dma_wr_data <= {8'h00,data[23:0]}; + 'h9: dma_wr_data <= data_filtered; + 'ha: dma_wr_data <= i_q; + 'hb: dma_wr_data <= i_q; + 'hc: dma_wr_data <= i_q_filtered; + 'hd: dma_wr_data <= i_q_filtered; + endcase end always @(posedge clk) begin - if (processing_resetn == 1'b0 || channel_enable[count] == 1'b0) begin - dma_wr_en <= 1'b0; - end else begin - case (count) - 'h0: dma_wr_en <= phase_valid; - 'h1: dma_wr_en <= data_valid; - 'h2: dma_wr_en <= data_filtered_valid; - 'h3: dma_wr_en <= i_q_valid; - 'h4: dma_wr_en <= i_q_valid; - 'h5: dma_wr_en <= i_q_filtered_valid; - 'h6: dma_wr_en <= i_q_filtered_valid; - 'h7: dma_wr_en <= phase_valid; - 'h8: dma_wr_en <= data_valid; - 'h9: dma_wr_en <= data_filtered_valid; - 'ha: dma_wr_en <= i_q_valid; - 'hb: dma_wr_en <= i_q_valid; - 'hc: dma_wr_en <= i_q_filtered_valid; - 'hd: dma_wr_en <= i_q_filtered_valid; - endcase - end + if (processing_resetn == 1'b0 || channel_enable[count] == 1'b0) begin + dma_wr_en <= 1'b0; + end else begin + case (count) + 'h0: dma_wr_en <= phase_valid; + 'h1: dma_wr_en <= data_valid; + 'h2: dma_wr_en <= data_filtered_valid; + 'h3: dma_wr_en <= i_q_valid; + 'h4: dma_wr_en <= i_q_valid; + 'h5: dma_wr_en <= i_q_filtered_valid; + 'h6: dma_wr_en <= i_q_filtered_valid; + 'h7: dma_wr_en <= phase_valid; + 'h8: dma_wr_en <= data_valid; + 'h9: dma_wr_en <= data_filtered_valid; + 'ha: dma_wr_en <= i_q_valid; + 'hb: dma_wr_en <= i_q_valid; + 'hc: dma_wr_en <= i_q_filtered_valid; + 'hd: dma_wr_en <= i_q_filtered_valid; + endcase + end end always @(posedge clk) begin - if (count == 'h00) begin - dma_wr_sync <= 1'b1; - end else if (dma_wr_en == 1'b1) begin - dma_wr_sync = 1'b0; - end + if (count == 'h00) begin + dma_wr_sync <= 1'b1; + end else if (dma_wr_en == 1'b1) begin + dma_wr_sync = 1'b0; + end end always @(*) begin - case (count) - 'h0: phase_ready <= 1'b1; - 'h7: phase_ready <= 1'b1; - default: phase_ready <= 1'b0; - endcase + case (count) + 'h0: phase_ready <= 1'b1; + 'h7: phase_ready <= 1'b1; + default: phase_ready <= 1'b0; + endcase end always @(*) begin - case (count) - 'h1: data_ready <= 1'b1; - 'h8: data_ready <= 1'b1; - default: data_ready <= 1'b0; - endcase + case (count) + 'h1: data_ready <= 1'b1; + 'h8: data_ready <= 1'b1; + default: data_ready <= 1'b0; + endcase end always @(*) begin - case (count) - 'h2: data_filtered_ready <= 1'b1; - 'h9: data_filtered_ready <= 1'b1; - default: data_filtered_ready <= 1'b0; - endcase + case (count) + 'h2: data_filtered_ready <= 1'b1; + 'h9: data_filtered_ready <= 1'b1; + default: data_filtered_ready <= 1'b0; + endcase end always @(*) begin - case (count) - 'h3: i_q_ready <= 1'b1; - 'h4: i_q_ready <= 1'b1; - 'ha: i_q_ready <= 1'b1; - 'hb: i_q_ready <= 1'b1; - default: i_q_ready <= 1'b0; - endcase + case (count) + 'h3: i_q_ready <= 1'b1; + 'h4: i_q_ready <= 1'b1; + 'ha: i_q_ready <= 1'b1; + 'hb: i_q_ready <= 1'b1; + default: i_q_ready <= 1'b0; + endcase end always @(*) begin - case (count) - 'h5: i_q_filtered_ready <= 1'b1; - 'h6: i_q_filtered_ready <= 1'b1; - 'hc: i_q_filtered_ready <= 1'b1; - 'hd: i_q_filtered_ready <= 1'b1; - default: i_q_filtered_ready <= 1'b0; - endcase + case (count) + 'h5: i_q_filtered_ready <= 1'b1; + 'h6: i_q_filtered_ready <= 1'b1; + 'hc: i_q_filtered_ready <= 1'b1; + 'hd: i_q_filtered_ready <= 1'b1; + default: i_q_filtered_ready <= 1'b0; + endcase end endmodule diff --git a/library/cn0363/cn0363_dma_sequencer/cn0363_dma_sequencer_ip.tcl b/library/cn0363/cn0363_dma_sequencer/cn0363_dma_sequencer_ip.tcl index 77d41a487..4556af8ea 100644 --- a/library/cn0363/cn0363_dma_sequencer/cn0363_dma_sequencer_ip.tcl +++ b/library/cn0363/cn0363_dma_sequencer/cn0363_dma_sequencer_ip.tcl @@ -67,6 +67,6 @@ adi_add_bus "dma_wr" "master" \ } -adi_add_bus_clock "clk" "phase:data:data_filtered:i_q:i_q_filtered:dma_wr" "resetn:processing_resetn" +adi_add_bus_clock "clk" "phase:data:data_filtered:i_q:i_q_filtered:dma_wr" "processing_resetn" ipx::save_core [ipx::current_core] diff --git a/library/cn0363/cn0363_phase_data_sync/Makefile b/library/cn0363/cn0363_phase_data_sync/Makefile index 33cf98cdd..ff28d4943 100644 --- a/library/cn0363/cn0363_phase_data_sync/Makefile +++ b/library/cn0363/cn0363_phase_data_sync/Makefile @@ -5,10 +5,10 @@ #################################################################################### #################################################################################### -M_DEPS := cn0363_phase_data_sync_ip.tcl M_DEPS += ../../scripts/adi_env.tcl M_DEPS += ../../scripts/adi_ip.tcl M_DEPS += cn0363_phase_data_sync.v +M_DEPS += cn0363_phase_data_sync_ip.tcl M_VIVADO := vivado -mode batch -source @@ -19,6 +19,10 @@ M_FLIST += *.log M_FLIST += component.xml M_FLIST += *.jou M_FLIST += xgui +M_FLIST += *.ip_user_files +M_FLIST += *.srcs +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil @@ -35,7 +39,7 @@ clean-all: cn0363_phase_data_sync.xpr: $(M_DEPS) - rm -rf $(M_FLIST) + -rm -rf $(M_FLIST) $(M_VIVADO) cn0363_phase_data_sync_ip.tcl >> cn0363_phase_data_sync_ip.log 2>&1 #################################################################################### diff --git a/library/cn0363/cn0363_phase_data_sync/cn0363_phase_data_sync.v b/library/cn0363/cn0363_phase_data_sync/cn0363_phase_data_sync.v index c2bb1310b..d0e4baf58 100644 --- a/library/cn0363/cn0363_phase_data_sync/cn0363_phase_data_sync.v +++ b/library/cn0363/cn0363_phase_data_sync/cn0363_phase_data_sync.v @@ -1,29 +1,29 @@ module cn0363_phase_data_sync ( - input clk, - input resetn, + input clk, + input resetn, - input processing_resetn, + input processing_resetn, - output s_axis_sample_ready, - input s_axis_sample_valid, - input [7:0] s_axis_sample_data, + output s_axis_sample_ready, + input s_axis_sample_valid, + input [7:0] s_axis_sample_data, - input sample_has_stat, + input sample_has_stat, - input conv_done, - input [31:0] phase, + input conv_done, + input [31:0] phase, - output reg m_axis_sample_valid, - input m_axis_sample_ready, - output [23:0] m_axis_sample_data, + output reg m_axis_sample_valid, + input m_axis_sample_ready, + output [23:0] m_axis_sample_data, - output reg m_axis_phase_valid, - input m_axis_phase_ready, - output [31:0] m_axis_phase_data, + output reg m_axis_phase_valid, + input m_axis_phase_ready, + output [31:0] m_axis_phase_data, - output reg overflow + output reg overflow ); reg [1:0] data_counter = 'h00; @@ -46,38 +46,38 @@ assign m_axis_sample_data = {~sample_hold[23],sample_hold[22:0]}; assign m_axis_phase_data = phase_hold; always @(posedge clk) begin - if (conv_done_d1 == 1'b0 && conv_done == 1'b1) begin - // Is the processing pipeline ready to accept data? - if (m_axis_sample_valid | m_axis_phase_valid | ~processing_resetn) begin - overflow <= 1'b1; - end else begin - phase_hold <= phase; - overflow <= 1'b0; - end - end else begin - overflow <= 1'b0; - end - conv_done_d1 <= conv_done; + if (conv_done_d1 == 1'b0 && conv_done == 1'b1) begin + // Is the processing pipeline ready to accept data? + if (m_axis_sample_valid | m_axis_phase_valid | ~processing_resetn) begin + overflow <= 1'b1; + end else begin + phase_hold <= phase; + overflow <= 1'b0; + end + end else begin + overflow <= 1'b0; + end + conv_done_d1 <= conv_done; end always @(posedge clk) begin - if (processing_resetn == 1'b0) begin - m_axis_phase_valid <= 1'b0; - m_axis_sample_valid <= 1'b0; - end else begin - /* Data and phase become valid once we have both */ - if (sample_hold_valid == 1'b1) begin - m_axis_phase_valid <= 1'b1; - m_axis_sample_valid <= 1'b1; - end else begin - if (m_axis_phase_ready == 1'b1) begin - m_axis_phase_valid <= 1'b0; - end - if (m_axis_sample_ready == 1'b1) begin - m_axis_sample_valid <= 1'b0; - end - end - end + if (processing_resetn == 1'b0) begin + m_axis_phase_valid <= 1'b0; + m_axis_sample_valid <= 1'b0; + end else begin + /* Data and phase become valid once we have both */ + if (sample_hold_valid == 1'b1) begin + m_axis_phase_valid <= 1'b1; + m_axis_sample_valid <= 1'b1; + end else begin + if (m_axis_phase_ready == 1'b1) begin + m_axis_phase_valid <= 1'b0; + end + if (m_axis_sample_ready == 1'b1) begin + m_axis_sample_valid <= 1'b0; + end + end + end end /* If the STAT register is included in the sample we get 4 bytes per sample and @@ -87,45 +87,45 @@ end * channel */ always @(posedge clk) begin - sample_hold_valid <= 1'b0; - if (sample_has_stat == 1'b0) begin - if (s_axis_sample_valid == 1'b1 && data_counter == 2'h2) begin - sample_hold_valid <= 1'b1; - end - end else begin - if (s_axis_sample_valid == 1'b1 && data_counter == 2'h3 && - (sync == 1'b1 || synced == 1'b1)) begin - sample_hold_valid <= 1'b1; - end - end + sample_hold_valid <= 1'b0; + if (sample_has_stat == 1'b0) begin + if (s_axis_sample_valid == 1'b1 && data_counter == 2'h2) begin + sample_hold_valid <= 1'b1; + end + end else begin + if (s_axis_sample_valid == 1'b1 && data_counter == 2'h3 && + (sync == 1'b1 || synced == 1'b1)) begin + sample_hold_valid <= 1'b1; + end + end end always @(posedge clk) begin - if (s_axis_sample_valid == 1'b1 && data_counter != 2'h3) begin - sample_hold <= {sample_hold[15:0],s_axis_sample_data}; - end + if (s_axis_sample_valid == 1'b1 && data_counter != 2'h3) begin + sample_hold <= {sample_hold[15:0],s_axis_sample_data}; + end end always @(posedge clk) begin - if (s_axis_sample_valid == 1'b1) begin - if (data_counter == 2'h2 && sample_has_stat == 1'b0) begin - data_counter <= 2'h0; - end else begin - data_counter <= data_counter + 1'b1; - end - end + if (s_axis_sample_valid == 1'b1) begin + if (data_counter == 2'h2 && sample_has_stat == 1'b0) begin + data_counter <= 2'h0; + end else begin + data_counter <= data_counter + 1'b1; + end + end end assign sync = s_axis_sample_data[3:0] == 'h00 && data_counter == 'h3; always @(posedge clk) begin - if (processing_resetn == 1'b0) begin - synced <= ~sample_has_stat; - end else begin - if (s_axis_sample_valid == 1'b1 && sync == 1'b1) begin - synced <= 1'b1; - end - end + if (processing_resetn == 1'b0) begin + synced <= ~sample_has_stat; + end else begin + if (s_axis_sample_valid == 1'b1 && sync == 1'b1) begin + synced <= 1'b1; + end + end end endmodule diff --git a/library/common/ad_axi_ip_constr.sdc b/library/common/ad_axi_ip_constr.sdc index 4decbe86e..40c5058dc 100644 --- a/library/common/ad_axi_ip_constr.sdc +++ b/library/common/ad_axi_ip_constr.sdc @@ -8,5 +8,5 @@ set_false_path -from [get_registers *up_xfer_status:i_xfer_status|d_xfer_data*] set_false_path -from [get_registers *up_clock_mon:i_clock_mon|d_count_toggle*] -to [get_registers *up_clock_mon:i_clock_mon|up_count_toggle_m1*] set_false_path -from [get_registers *up_clock_mon:i_clock_mon|d_count_hold*] -to [get_registers *up_clock_mon:i_clock_mon|up_d_count*] set_false_path -from [get_registers *up_clock_mon:i_clock_mon|up_count_toggle*] -to [get_registers *up_clock_mon:i_clock_mon|d_count_toggle_m1*] -set_false_path -from [get_registers *up_core_preset*] -to [get_registers *ad_rst:i_core_rst_reg|ad_rst_sync_m1*] +set_false_path -from [get_registers *up_*preset*] -to [get_registers *ad_rst:i_core_rst_reg|ad_rst_sync_m1*] diff --git a/library/common/ad_axi_ip_constr.xdc b/library/common/ad_axi_ip_constr.xdc index f2a5eeac1..ee5cfc941 100644 --- a/library/common/ad_axi_ip_constr.xdc +++ b/library/common/ad_axi_ip_constr.xdc @@ -16,5 +16,5 @@ set_false_path -from [get_cells -hier -filter {name =~ *d_xfer_data* && I set_false_path -from [get_cells -hier -filter {name =~ *d_count_toggle_reg && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *up_count_toggle_m1_reg && IS_SEQUENTIAL}] set_false_path -from [get_cells -hier -filter {name =~ *d_count_hold* && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *up_d_count* && IS_SEQUENTIAL}] set_false_path -from [get_cells -hier -filter {name =~ *up_count_toggle_reg && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *d_count_toggle_m1_reg && IS_SEQUENTIAL}] -set_false_path -from [get_cells -hier -filter {name =~ *up_core_preset_reg && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *ad_rst_sync_m1_reg && IS_SEQUENTIAL}] +set_false_path -from [get_cells -hier -filter {name =~ *up_*preset_reg && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *ad_rst_sync_m1_reg && IS_SEQUENTIAL}] diff --git a/library/common/ad_axis_dma_rx.v b/library/common/ad_axis_dma_rx.v deleted file mode 100644 index 08c40b4e2..000000000 --- a/library/common/ad_axis_dma_rx.v +++ /dev/null @@ -1,330 +0,0 @@ -// *************************************************************************** -// *************************************************************************** -// Copyright 2011(c) Analog Devices, Inc. -// -// All rights reserved. -// -// Redistribution and use in source and binary forms, with or without modification, -// are permitted provided that the following conditions are met: -// - Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// - Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in -// the documentation and/or other materials provided with the -// distribution. -// - Neither the name of Analog Devices, Inc. nor the names of its -// contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// - The use of this software may or may not infringe the patent rights -// of one or more patent holders. This license does not release you -// from the requirement that you obtain separate licenses from these -// patent holders to use this software. -// - Use of the software either in source or binary form, must be run -// on or directly connected to an Analog Devices Inc. component. -// -// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, -// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A -// PARTICULAR PURPOSE ARE DISCLAIMED. -// -// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY -// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF -// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// *************************************************************************** -// *************************************************************************** -// *************************************************************************** -// *************************************************************************** - -`timescale 1ns/100ps - -module ad_axis_dma_rx ( - - // dma interface - - dma_clk, - dma_rst, - dma_valid, - dma_last, - dma_data, - dma_ready, - dma_ovf, - dma_unf, - dma_status, - dma_bw, - - // data interface - - adc_clk, - adc_rst, - adc_valid, - adc_data, - - // processor interface - - dma_start, - dma_stream, - dma_count); - - // parameters - - parameter DATA_WIDTH = 64; - localparam DW = DATA_WIDTH - 1; - localparam BUF_THRESHOLD_LO = 6'd3; - localparam BUF_THRESHOLD_HI = 6'd60; - localparam DATA_WIDTH_IN_BYTES = DATA_WIDTH/8; - - // dma interface - - input dma_clk; - input dma_rst; - output dma_valid; - output dma_last; - output [DW:0] dma_data; - input dma_ready; - output dma_ovf; - output dma_unf; - output dma_status; - output [31:0] dma_bw; - - // data interface - - input adc_clk; - input adc_rst; - input adc_valid; - input [DW:0] adc_data; - - // processor interface - - input dma_start; - input dma_stream; - input [31:0] dma_count; - - // internal registers - - reg dma_valid_int = 'd0; - reg dma_last_int = 'd0; - reg [DW:0] dma_data_int = 'd0; - reg dma_capture_enable = 'd0; - reg [31:0] dma_capture_count = 'd0; - reg dma_rd = 'd0; - reg [ 5:0] dma_raddr = 'd0; - reg dma_release_toggle_m1 = 'd0; - reg dma_release_toggle_m2 = 'd0; - reg dma_release_toggle_m3 = 'd0; - reg [ 5:0] dma_release_waddr = 'd0; - reg [ 5:0] dma_waddr_m1 = 'd0; - reg [ 5:0] dma_waddr_m2 = 'd0; - reg [ 5:0] dma_waddr = 'd0; - reg [ 5:0] dma_addr_diff = 'd0; - reg dma_almost_full = 'd0; - reg dma_almost_empty = 'd0; - reg dma_ovf = 'd0; - reg dma_unf = 'd0; - reg dma_resync = 'd0; - reg adc_wr = 'd0; - reg [ 5:0] adc_waddr = 'd0; - reg [ 5:0] adc_waddr_g = 'd0; - reg [ 3:0] adc_release_count = 'd0; - reg [DW:0] adc_wdata = 'd0; - reg adc_release_toggle = 'd0; - reg [ 5:0] adc_release_waddr = 'd0; - reg adc_resync_m1 = 'd0; - reg adc_resync_m2 = 'd0; - reg adc_resync = 'd0; - - // internal signals - - wire dma_rd_valid_s; - wire dma_last_s; - wire dma_ready_s; - wire dma_rd_s; - wire dma_release_s; - wire [ 6:0] dma_addr_diff_s; - wire dma_ovf_s; - wire dma_unf_s; - wire [DW:0] dma_rdata_s; - - // binary to grey conversion - - function [5:0] b2g; - input [5:0] b; - reg [5:0] g; - begin - g[5] = b[5]; - g[4] = b[5] ^ b[4]; - g[3] = b[4] ^ b[3]; - g[2] = b[3] ^ b[2]; - g[1] = b[2] ^ b[1]; - g[0] = b[1] ^ b[0]; - b2g = g; - end - endfunction - - // grey to binary conversion - - function [5:0] g2b; - input [5:0] g; - reg [5:0] b; - begin - b[5] = g[5]; - b[4] = b[5] ^ g[4]; - b[3] = b[4] ^ g[3]; - b[2] = b[3] ^ g[2]; - b[1] = b[2] ^ g[1]; - b[0] = b[1] ^ g[0]; - g2b = b; - end - endfunction - - // dma read- user interface - - assign dma_bw = DATA_WIDTH_IN_BYTES; - assign dma_status = dma_capture_enable; - - always @(posedge dma_clk) begin - dma_valid_int <= dma_rd_valid_s; - dma_last_int <= dma_last_s; - dma_data_int <= dma_rdata_s; - end - - // dma read- capture control signals - - assign dma_rd_valid_s = dma_capture_enable & dma_rd; - assign dma_last_s = (dma_capture_count == dma_count) ? dma_rd_valid_s : 1'b0; - - always @(posedge dma_clk) begin - if ((dma_stream == 1'b0) && (dma_last_s == 1'b1)) begin - dma_capture_enable <= 1'b0; - end else if (dma_start == 1'b1) begin - dma_capture_enable <= 1'b1; - end - if ((dma_capture_enable == 1'b0) || (dma_last_s == 1'b1)) begin - dma_capture_count <= dma_bw; - end else if (dma_rd == 1'b1) begin - dma_capture_count <= dma_capture_count + dma_bw; - end - end - - // dma read- read data always and pass it to the external memory - - assign dma_ready_s = (~dma_capture_enable) | dma_ready; - assign dma_rd_s = (dma_release_waddr == dma_raddr) ? 1'b0 : dma_ready_s; - - always @(posedge dma_clk) begin - dma_rd <= dma_rd_s; - if ((dma_resync == 1'b1) || (dma_rst == 1'b1)) begin - dma_raddr <= 6'd0; - end else if (dma_rd_s == 1'b1) begin - dma_raddr <= dma_raddr + 1'b1; - end - end - - // dma read- get bursts of adc data from the other side - - assign dma_release_s = dma_release_toggle_m3 ^ dma_release_toggle_m2; - - always @(posedge dma_clk) begin - if (dma_rst == 1'b1) begin - dma_release_toggle_m1 <= 'd0; - dma_release_toggle_m2 <= 'd0; - dma_release_toggle_m3 <= 'd0; - end else begin - dma_release_toggle_m1 <= adc_release_toggle; - dma_release_toggle_m2 <= dma_release_toggle_m1; - dma_release_toggle_m3 <= dma_release_toggle_m2; - end - if (dma_resync == 1'b1) begin - dma_release_waddr <= 6'd0; - end else if (dma_release_s == 1'b1) begin - dma_release_waddr <= adc_release_waddr; - end - end - - // dma read- get free running write address for ovf/unf checking - - assign dma_addr_diff_s = {1'b1, dma_waddr} - dma_raddr; - assign dma_ovf_s = (dma_addr_diff < BUF_THRESHOLD_LO) ? dma_almost_full : 1'b0; - assign dma_unf_s = (dma_addr_diff > BUF_THRESHOLD_HI) ? dma_almost_empty : 1'b0; - - always @(posedge dma_clk) begin - if (dma_rst == 1'b1) begin - dma_waddr_m1 <= 'd0; - dma_waddr_m2 <= 'd0; - end else begin - dma_waddr_m1 <= adc_waddr_g; - dma_waddr_m2 <= dma_waddr_m1; - end - dma_waddr <= g2b(dma_waddr_m2); - dma_addr_diff <= dma_addr_diff_s[5:0]; - if (dma_addr_diff > BUF_THRESHOLD_HI) begin - dma_almost_full <= 1'b1; - end else begin - dma_almost_full <= 1'b0; - end - if (dma_addr_diff < BUF_THRESHOLD_LO) begin - dma_almost_empty <= 1'b1; - end else begin - dma_almost_empty <= 1'b0; - end - dma_ovf <= dma_ovf_s; - dma_unf <= dma_unf_s; - dma_resync <= dma_ovf | dma_unf; - end - - // adc write- used here to simply transfer data to the dma side - // address is released with a free running counter - - always @(posedge adc_clk) begin - adc_wr <= adc_valid; - if ((adc_resync == 1'b1) || (adc_rst == 1'b1)) begin - adc_waddr <= 6'd0; - end else if (adc_wr == 1'b1) begin - adc_waddr <= adc_waddr + 1'b1; - end - adc_waddr_g <= b2g(adc_waddr); - adc_wdata <= adc_data; - adc_release_count <= adc_release_count + 1'b1; - if (adc_release_count == 4'hf) begin - adc_release_toggle <= ~adc_release_toggle; - adc_release_waddr <= adc_waddr; - end - if (adc_rst == 1'b1) begin - adc_resync_m1 <= 'd0; - adc_resync_m2 <= 'd0; - end else begin - adc_resync_m1 <= dma_resync; - adc_resync_m2 <= adc_resync_m1; - end - adc_resync <= adc_resync_m2; - end - - // interface handler for ready - - ad_axis_inf_rx #(.DATA_WIDTH(DATA_WIDTH)) i_axis_inf ( - .clk (dma_clk), - .rst (dma_rst), - .valid (dma_valid_int), - .last (dma_last_int), - .data (dma_data_int), - .inf_valid (dma_valid), - .inf_last (dma_last), - .inf_data (dma_data), - .inf_ready (dma_ready)); - - // buffer (mainly for clock domain transfer) - - ad_mem #(.DATA_WIDTH(DATA_WIDTH), .ADDRESS_WIDTH(6)) i_mem ( - .clka (adc_clk), - .wea (adc_wr), - .addra (adc_waddr), - .dina (adc_wdata), - .clkb (dma_clk), - .addrb (dma_raddr), - .doutb (dma_rdata_s)); - -endmodule - -// *************************************************************************** -// *************************************************************************** diff --git a/library/common/ad_axis_dma_tx.v b/library/common/ad_axis_dma_tx.v deleted file mode 100644 index d14f32c48..000000000 --- a/library/common/ad_axis_dma_tx.v +++ /dev/null @@ -1,281 +0,0 @@ -// *************************************************************************** -// *************************************************************************** -// Copyright 2011(c) Analog Devices, Inc. -// -// All rights reserved. -// -// Redistribution and use in source and binary forms, with or without modification, -// are permitted provided that the following conditions are met: -// - Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// - Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in -// the documentation and/or other materials provided with the -// distribution. -// - Neither the name of Analog Devices, Inc. nor the names of its -// contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// - The use of this software may or may not infringe the patent rights -// of one or more patent holders. This license does not release you -// from the requirement that you obtain separate licenses from these -// patent holders to use this software. -// - Use of the software either in source or binary form, must be run -// on or directly connected to an Analog Devices Inc. component. -// -// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, -// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A -// PARTICULAR PURPOSE ARE DISCLAIMED. -// -// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY -// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF -// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// *************************************************************************** -// *************************************************************************** -// *************************************************************************** -// *************************************************************************** -// dac vdma read - -module ad_axis_dma_tx ( - - // vdma interface - - dma_clk, - dma_rst, - dma_fs, - dma_valid, - dma_data, - dma_ready, - dma_ovf, - dma_unf, - - // dac interface - - dac_clk, - dac_rst, - dac_rd, - dac_valid, - dac_data, - - // processor interface - - dma_frmcnt); - - // parameters - - parameter DATA_WIDTH = 64; - localparam DW = DATA_WIDTH - 1; - localparam BUF_THRESHOLD_LO = 6'd3; - localparam BUF_THRESHOLD_HI = 6'd60; - localparam RDY_THRESHOLD_LO = 6'd40; - localparam RDY_THRESHOLD_HI = 6'd50; - - // vdma interface - - input dma_clk; - input dma_rst; - output dma_fs; - input dma_valid; - input [DW:0] dma_data; - output dma_ready; - output dma_ovf; - output dma_unf; - - // dac interface - - input dac_clk; - input dac_rst; - input dac_rd; - output dac_valid; - output [DW:0] dac_data; - - // processor interface - - input [31:0] dma_frmcnt; - - // internal registers - - reg dac_start_m1 = 'd0; - reg dac_start = 'd0; - reg dac_resync_m1 = 'd0; - reg dac_resync = 'd0; - reg [ 5:0] dac_raddr = 'd0; - reg [ 5:0] dac_raddr_g = 'd0; - reg dac_rd_d = 'd0; - reg dac_rd_2d = 'd0; - reg dac_valid = 'd0; - reg [DW:0] dac_data = 'd0; - reg [31:0] dma_clkcnt = 'd0; - reg dma_fs = 'd0; - reg [ 5:0] dma_raddr_g_m1 = 'd0; - reg [ 5:0] dma_raddr_g_m2 = 'd0; - reg [ 5:0] dma_raddr = 'd0; - reg [ 5:0] dma_addr_diff = 'd0; - reg dma_ready = 'd0; - reg dma_almost_full = 'd0; - reg dma_almost_empty = 'd0; - reg dma_ovf = 'd0; - reg dma_unf = 'd0; - reg dma_resync = 'd0; - reg dma_start = 'd0; - reg dma_wr = 'd0; - reg [ 5:0] dma_waddr = 'd0; - reg [DW:0] dma_wdata = 'd0; - - // internal signals - - wire dma_wr_s; - wire [ 6:0] dma_addr_diff_s; - wire dma_ovf_s; - wire dma_unf_s; - wire [DW:0] dac_rdata_s; - - // binary to grey coversion - - function [7:0] b2g; - input [7:0] b; - reg [7:0] g; - begin - g[7] = b[7]; - g[6] = b[7] ^ b[6]; - g[5] = b[6] ^ b[5]; - g[4] = b[5] ^ b[4]; - g[3] = b[4] ^ b[3]; - g[2] = b[3] ^ b[2]; - g[1] = b[2] ^ b[1]; - g[0] = b[1] ^ b[0]; - b2g = g; - end - endfunction - - // grey to binary conversion - - function [7:0] g2b; - input [7:0] g; - reg [7:0] b; - begin - b[7] = g[7]; - b[6] = b[7] ^ g[6]; - b[5] = b[6] ^ g[5]; - b[4] = b[5] ^ g[4]; - b[3] = b[4] ^ g[3]; - b[2] = b[3] ^ g[2]; - b[1] = b[2] ^ g[1]; - b[0] = b[1] ^ g[0]; - g2b = b; - end - endfunction - - // dac read interface - - always @(posedge dac_clk) begin - if (dac_rst == 1'b1) begin - dac_start_m1 <= 'd0; - dac_start <= 'd0; - dac_resync_m1 <= 'd0; - dac_resync <= 'd0; - end else begin - dac_start_m1 <= dma_start; - dac_start <= dac_start_m1; - dac_resync_m1 <= dma_resync; - dac_resync <= dac_resync_m1; - end - if ((dac_start == 1'b0) || (dac_resync == 1'b1) || (dac_rst == 1'b1)) begin - dac_raddr <= 6'd0; - end else if (dac_rd == 1'b1) begin - dac_raddr <= dac_raddr + 1'b1; - end - dac_raddr_g <= b2g(dac_raddr); - dac_rd_d <= dac_rd; - dac_rd_2d <= dac_rd_d; - dac_valid <= dac_rd_2d; - dac_data <= dac_rdata_s; - end - - // generate fsync - - always @(posedge dma_clk) begin - if ((dma_resync == 1'b1) || (dma_rst == 1'b1) || (dma_clkcnt >= dma_frmcnt)) begin - dma_clkcnt <= 16'd0; - end else begin - dma_clkcnt <= dma_clkcnt + 1'b1; - end - if (dma_clkcnt == 32'd1) begin - dma_fs <= 1'b1; - end else begin - dma_fs <= 1'b0; - end - end - - // overflow or underflow status - - assign dma_addr_diff_s = {1'b1, dma_waddr} - dma_raddr; - assign dma_ovf_s = (dma_addr_diff < BUF_THRESHOLD_LO) ? dma_almost_full : 1'b0; - assign dma_unf_s = (dma_addr_diff > BUF_THRESHOLD_HI) ? dma_almost_empty : 1'b0; - - always @(posedge dma_clk) begin - if (dma_rst == 1'b1) begin - dma_raddr_g_m1 <= 'd0; - dma_raddr_g_m2 <= 'd0; - end else begin - dma_raddr_g_m1 <= dac_raddr_g; - dma_raddr_g_m2 <= dma_raddr_g_m1; - end - dma_raddr <= g2b(dma_raddr_g_m2); - dma_addr_diff <= dma_addr_diff_s[5:0]; - if (dma_addr_diff >= RDY_THRESHOLD_HI) begin - dma_ready <= 1'b0; - end else if (dma_addr_diff <= RDY_THRESHOLD_LO) begin - dma_ready <= 1'b1; - end - if (dma_addr_diff > BUF_THRESHOLD_HI) begin - dma_almost_full <= 1'b1; - end else begin - dma_almost_full <= 1'b0; - end - if (dma_addr_diff < BUF_THRESHOLD_LO) begin - dma_almost_empty <= 1'b1; - end else begin - dma_almost_empty <= 1'b0; - end - dma_ovf <= dma_ovf_s; - dma_unf <= dma_unf_s; - dma_resync <= dma_ovf | dma_unf; - end - - // vdma write - - assign dma_wr_s = dma_valid & dma_ready; - - always @(posedge dma_clk) begin - if (dma_rst == 1'b1) begin - dma_start <= 1'b0; - end else if (dma_wr_s == 1'b1) begin - dma_start <= 1'b1; - end - dma_wr <= dma_wr_s; - if ((dma_resync == 1'b1) || (dma_rst == 1'b1)) begin - dma_waddr <= 6'd0; - end else if (dma_wr == 1'b1) begin - dma_waddr <= dma_waddr + 1'b1; - end - dma_wdata <= dma_data; - end - - // memory - - ad_mem #(.DATA_WIDTH(DATA_WIDTH), .ADDRESS_WIDTH(6)) i_mem ( - .clka (dma_clk), - .wea (dma_wr), - .addra (dma_waddr), - .dina (dma_wdata), - .clkb (dac_clk), - .addrb (dac_raddr), - .doutb (dac_rdata_s)); - -endmodule - -// *************************************************************************** -// *************************************************************************** diff --git a/library/common/ad_datafmt.v b/library/common/ad_datafmt.v index c92350f7c..28a5ee2cb 100644 --- a/library/common/ad_datafmt.v +++ b/library/common/ad_datafmt.v @@ -34,72 +34,73 @@ // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // *************************************************************************** // *************************************************************************** -// *************************************************************************** -// *************************************************************************** // data format (offset binary or 2's complement only) `timescale 1ps/1ps -module ad_datafmt ( +module ad_datafmt #( + + // data bus width + + parameter DATA_WIDTH = 16, + parameter DISABLE = 0) ( // data path - clk, - valid, - data, - valid_out, - data_out, + input clk, + input valid, + input [(DATA_WIDTH-1):0] data, + output valid_out, + output [15:0] data_out, // control signals - dfmt_enable, - dfmt_type, - dfmt_se); - - // delayed data bus width - - parameter DATA_WIDTH = 16; - localparam DW = DATA_WIDTH - 1; - - // data path - - input clk; - input valid; - input [DW:0] data; - output valid_out; - output [15:0] data_out; - - // control signals - - input dfmt_enable; - input dfmt_type; - input dfmt_se; + input dfmt_enable, + input dfmt_type, + input dfmt_se); // internal registers - reg valid_out = 'd0; - reg [15:0] data_out = 'd0; + reg valid_int = 'd0; + reg [15:0] data_int = 'd0; // internal signals - wire type_s; - wire signext_s; - wire [DW:0] data_s; - wire [23:0] sign_s; - wire [23:0] data_out_s; + wire type_s; + wire signext_s; + wire sign_s; + wire [15:0] data_out_s; + + // data-path disable + + generate + if (DISABLE == 1) begin + assign valid_out = valid; + assign data_out = data; + end else begin + assign valid_out = valid_int; + assign data_out = data_int; + end + endgenerate // if offset-binary convert to 2's complement first assign type_s = dfmt_enable & dfmt_type; assign signext_s = dfmt_enable & dfmt_se; + assign sign_s = signext_s & (type_s ^ data[(DATA_WIDTH-1)]); - assign data_s = (type_s == 1'b1) ? {~data[DW], data[(DW-1):0]} : data; - assign sign_s = (signext_s == 1'b1) ? {{24{data_s[DW]}}} : 24'd0; - assign data_out_s = {sign_s[23:(DW+1)], data_s}; + generate + if (DATA_WIDTH < 16) begin + assign data_out_s[15:DATA_WIDTH] = {(16-DATA_WIDTH){sign_s}}; + end + endgenerate + + assign data_out_s[(DATA_WIDTH-1)] = type_s ^ data[(DATA_WIDTH-1)]; + assign data_out_s[(DATA_WIDTH-2):0] = data[(DATA_WIDTH-2):0]; always @(posedge clk) begin - valid_out <= valid; - data_out <= data_out_s[15:0]; + valid_int <= valid; + data_int <= data_out_s[15:0]; end endmodule diff --git a/library/common/ad_dcfilter.v b/library/common/ad_dcfilter.v index 5ee1909ed..70795286c 100644 --- a/library/common/ad_dcfilter.v +++ b/library/common/ad_dcfilter.v @@ -34,44 +34,33 @@ // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // *************************************************************************** // *************************************************************************** -// *************************************************************************** -// *************************************************************************** // dc filter- y(n) = c*x(n) + (1-c)*y(n-1) `timescale 1ps/1ps -module ad_dcfilter ( +module ad_dcfilter #( + + // data path disable + + parameter DISABLE = 0) ( // data interface - clk, - valid, - data, - valid_out, - data_out, + input clk, + input valid, + input [15:0] data, + output valid_out, + output [15:0] data_out, // control interface - dcfilt_enb, - dcfilt_coeff, - dcfilt_offset); - - // data interface - - input clk; - input valid; - input [15:0] data; - output valid_out; - output [15:0] data_out; - - // control interface - - input dcfilt_enb; - input [15:0] dcfilt_coeff; - input [15:0] dcfilt_offset; + input dcfilt_enb, + input [15:0] dcfilt_coeff, + input [15:0] dcfilt_offset); // internal registers + reg [15:0] dcfilt_coeff_d = 'd0; reg [47:0] dc_offset = 'd0; reg [47:0] dc_offset_d = 'd0; reg valid_d = 'd0; @@ -79,21 +68,33 @@ module ad_dcfilter ( reg valid_2d = 'd0; reg [15:0] data_2d = 'd0; reg [15:0] data_dcfilt = 'd0; - reg valid_out = 'd0; - reg [15:0] data_out = 'd0; - reg [15:0] dcfilt_coeff_r; + reg valid_int = 'd0; + reg [15:0] data_int = 'd0; // internal signals wire [47:0] dc_offset_s; - // cancelling the dc offset + // data-path disable + + generate + if (DISABLE == 1) begin + assign valid_out = valid; + assign data_out = data; + end else begin + assign valid_out = valid_int; + assign data_out = data_int; + end + endgenerate // dcfilt_coeff is flopped so to remove warnings from vivado + always @(posedge clk) begin - dcfilt_coeff_r <= dcfilt_coeff; + dcfilt_coeff_d <= dcfilt_coeff; end + // removing dc offset + always @(posedge clk) begin dc_offset <= dc_offset_s; dc_offset_d <= dc_offset; @@ -105,11 +106,11 @@ module ad_dcfilter ( data_2d <= data_d; data_dcfilt <= data_d - dc_offset[32:17]; if (dcfilt_enb == 1'b1) begin - valid_out <= valid_2d; - data_out <= data_dcfilt; + valid_int <= valid_2d; + data_int <= data_dcfilt; end else begin - valid_out <= valid_2d; - data_out <= data_2d; + valid_int <= valid_2d; + data_int <= data_2d; end end @@ -144,7 +145,7 @@ module ad_dcfilter ( i_dsp48e1 ( .CLK (clk), .A ({{14{dc_offset_s[32]}}, dc_offset_s[32:17]}), - .B ({{2{dcfilt_coeff_r[15]}}, dcfilt_coeff_r}), + .B ({{2{dcfilt_coeff_d[15]}}, dcfilt_coeff_d}), .C (dc_offset_d), .D ({{9{data_d[15]}}, data_d}), .MULTSIGNIN (1'd0), diff --git a/library/common/ad_dds.v b/library/common/ad_dds.v index 3a09e6ec7..5a91a1143 100644 --- a/library/common/ad_dds.v +++ b/library/common/ad_dds.v @@ -34,63 +34,59 @@ // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // *************************************************************************** // *************************************************************************** -// *************************************************************************** -// *************************************************************************** `timescale 1ns/100ps -module ad_dds ( +module ad_dds #( + + // data path disable + + parameter DISABLE = 0) ( // interface - clk, - dds_format, - dds_phase_0, - dds_scale_0, - dds_phase_1, - dds_scale_1, - dds_data); - - // interface - - input clk; - input dds_format; - input [15:0] dds_phase_0; - input [15:0] dds_scale_0; - input [15:0] dds_phase_1; - input [15:0] dds_scale_1; - output [15:0] dds_data; + input clk, + input dds_format, + input [15:0] dds_phase_0, + input [15:0] dds_scale_0, + input [15:0] dds_phase_1, + input [15:0] dds_scale_1, + output [15:0] dds_data); // internal registers reg [15:0] dds_data_int = 'd0; - reg [15:0] dds_data = 'd0; + reg [15:0] dds_data_out = 'd0; + reg [15:0] dds_scale_0_d = 'd0; + reg [15:0] dds_scale_1_d = 'd0; - reg [15:0] dds_scale_0_r = 'd0; - reg [15:0] dds_scale_1_r = 'd0; // internal signals wire [15:0] dds_data_0_s; wire [15:0] dds_data_1_s; + // disable + + assign dds_data = (DISABLE == 1) ? 16'd0 : dds_data_out; + // dds channel output always @(posedge clk) begin dds_data_int <= dds_data_0_s + dds_data_1_s; - dds_data[15:15] <= dds_data_int[15] ^ dds_format; - dds_data[14: 0] <= dds_data_int[14:0]; + dds_data_out[15:15] <= dds_data_int[15] ^ dds_format; + dds_data_out[14: 0] <= dds_data_int[14:0]; end always @(posedge clk) begin - dds_scale_0_r <= dds_scale_0; - dds_scale_1_r <= dds_scale_1; + dds_scale_0_d <= dds_scale_0; + dds_scale_1_d <= dds_scale_1; end // dds-1 ad_dds_1 i_dds_1_0 ( .clk (clk), .angle (dds_phase_0), - .scale (dds_scale_0_r), + .scale (dds_scale_0_d), .dds_data (dds_data_0_s)); // dds-2 @@ -98,7 +94,7 @@ module ad_dds ( ad_dds_1 i_dds_1_1 ( .clk (clk), .angle (dds_phase_1), - .scale (dds_scale_1_r), + .scale (dds_scale_1_d), .dds_data (dds_data_1_s)); endmodule diff --git a/library/common/ad_edge_detect.v b/library/common/ad_edge_detect.v new file mode 100644 index 000000000..6c15454b4 --- /dev/null +++ b/library/common/ad_edge_detect.v @@ -0,0 +1,95 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2013(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** + +// A simple edge detector circuit + +`timescale 1ns/100ps + +module ad_edge_detect ( + + clk, + rst, + + in, + out +); + + parameter EDGE = 0; + + localparam POS_EDGE = 0; + localparam NEG_EDGE = 1; + localparam ANY_EDGE = 2; + + input clk; + input rst; + + input in; + output out; + + reg ff_m1 = 0; + reg ff_m2 = 0; + + reg out = 0; + + always @(posedge clk) begin + if (rst == 1) begin + ff_m1 <= 0; + ff_m2 <= 0; + end else begin + ff_m1 <= in; + ff_m2 <= ff_m1; + end + end + + always @(posedge clk) begin + if (rst == 1) begin + out <= 1'b0; + end else begin + if (EDGE == POS_EDGE) begin + out <= ff_m1 & ~ff_m2; + end else if (EDGE == NEG_EDGE) begin + out <= ~ff_m1 & ff_m2; + end else begin + out <= ff_m1 ^ ff_m2; + end + end + end + +endmodule + diff --git a/library/common/ad_iqcor.v b/library/common/ad_iqcor.v index 5d78a9aad..d8543e972 100644 --- a/library/common/ad_iqcor.v +++ b/library/common/ad_iqcor.v @@ -38,41 +38,27 @@ `timescale 1ns/100ps -module ad_iqcor ( - - // data interface - - clk, - valid, - data_in, - data_iq, - valid_out, - data_out, - - // control interface - - iqcor_enable, - iqcor_coeff_1, - iqcor_coeff_2); +module ad_iqcor #( // select i/q if disabled - parameter Q_OR_I_N = 0; + parameter Q_OR_I_N = 0, + parameter DISABLE = 0) ( // data interface - input clk; - input valid; - input [15:0] data_in; - input [15:0] data_iq; - output valid_out; - output [15:0] data_out; + input clk, + input valid, + input [15:0] data_in, + input [15:0] data_iq, + output valid_out, + output [15:0] data_out, // control interface - input iqcor_enable; - input [15:0] iqcor_coeff_1; - input [15:0] iqcor_coeff_2; + input iqcor_enable, + input [15:0] iqcor_coeff_1, + input [15:0] iqcor_coeff_2); // internal registers @@ -80,8 +66,8 @@ module ad_iqcor ( reg [15:0] p1_data_i = 'd0; reg [15:0] p1_data_q = 'd0; reg [33:0] p1_data_p = 'd0; - reg valid_out = 'd0; - reg [15:0] data_out = 'd0; + reg valid_int = 'd0; + reg [15:0] data_int = 'd0; reg [15:0] iqcor_coeff_1_r = 'd0; reg [15:0] iqcor_coeff_2_r = 'd0; @@ -95,6 +81,18 @@ module ad_iqcor ( wire [33:0] p1_data_p_q_s; wire [15:0] p1_data_q_s; + // data-path disable + + generate + if (DISABLE == 1) begin + assign valid_out = valid; + assign data_out = data_in; + end else begin + assign valid_out = valid_int; + assign data_out = data_int; + end + endgenerate + // swap i & q assign data_i_s = (Q_OR_I_N == 1) ? data_iq : data_in; @@ -139,13 +137,13 @@ module ad_iqcor ( // output registers always @(posedge clk) begin - valid_out <= p1_valid; + valid_int <= p1_valid; if (iqcor_enable == 1'b1) begin - data_out <= p1_data_p[29:14]; + data_int <= p1_data_p[29:14]; end else if (Q_OR_I_N == 1) begin - data_out <= p1_data_q; + data_int <= p1_data_q; end else begin - data_out <= p1_data_i; + data_int <= p1_data_i; end end diff --git a/library/common/ad_mem.v b/library/common/ad_mem.v index 412e17f8f..a06be19b3 100644 --- a/library/common/ad_mem.v +++ b/library/common/ad_mem.v @@ -1,9 +1,9 @@ // *************************************************************************** // *************************************************************************** // Copyright 2011(c) Analog Devices, Inc. -// +// // All rights reserved. -// +// // Redistribution and use in source and binary forms, with or without modification, // are permitted provided that the following conditions are met: // - Redistributions of source code must retain the above copyright @@ -21,16 +21,16 @@ // patent holders to use this software. // - Use of the software either in source or binary form, must be run // on or directly connected to an Analog Devices Inc. component. -// +// // THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, // INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A // PARTICULAR PURPOSE ARE DISCLAIMED. // // IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, // EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY -// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR // BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // *************************************************************************** // *************************************************************************** @@ -64,6 +64,7 @@ module ad_mem ( input [AW:0] addrb; output [DW:0] doutb; + (* ram_style = "block" *) reg [DW:0] m_ram[0:((2**ADDRESS_WIDTH)-1)]; reg [DW:0] doutb; diff --git a/library/common/ad_mem_asym.v b/library/common/ad_mem_asym.v index c4fec8ee6..eb86ab21c 100644 --- a/library/common/ad_mem_asym.v +++ b/library/common/ad_mem_asym.v @@ -1,9 +1,9 @@ // *************************************************************************** // *************************************************************************** // Copyright 2011(c) Analog Devices, Inc. -// +// // All rights reserved. -// +// // Redistribution and use in source and binary forms, with or without modification, // are permitted provided that the following conditions are met: // - Redistributions of source code must retain the above copyright @@ -21,22 +21,25 @@ // patent holders to use this software. // - Use of the software either in source or binary form, must be run // on or directly connected to an Analog Devices Inc. component. -// +// // THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, // INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A // PARTICULAR PURPOSE ARE DISCLAIMED. // // IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, // EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY -// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR // BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // *************************************************************************** // *************************************************************************** // *************************************************************************** // *************************************************************************** +// A simple asymetric memory. The write and read memory space must have the same size. +// 2^A_ADDRESS_WIDTH * A_DATA_WIDTH == 2^B_ADDRESS_WIDTH * B_DATA_WIDTH + `timescale 1ns/100ps module ad_mem_asym ( @@ -50,86 +53,125 @@ module ad_mem_asym ( addrb, doutb); - parameter A_ADDRESS_WIDTH = 10; + parameter A_ADDRESS_WIDTH = 8; parameter A_DATA_WIDTH = 256; - parameter B_ADDRESS_WIDTH = 8; + parameter B_ADDRESS_WIDTH = 10; parameter B_DATA_WIDTH = 64; - localparam MEM_SIZE_A = 2**A_ADDRESS_WIDTH; - localparam MEM_SIZE_B = 2**B_ADDRESS_WIDTH; - localparam MEM_SIZE = (MEM_SIZE_A > MEM_SIZE_B) ? MEM_SIZE_A : MEM_SIZE_B; - localparam MEM_RATIO = A_DATA_WIDTH/B_DATA_WIDTH; + localparam MEM_ADDRESS_WIDTH = (A_ADDRESS_WIDTH > B_ADDRESS_WIDTH) ? A_ADDRESS_WIDTH : B_ADDRESS_WIDTH; + localparam MEM_DATA_WIDTH = (A_DATA_WIDTH > B_DATA_WIDTH) ? B_DATA_WIDTH : A_DATA_WIDTH; + localparam MEM_SIZE = 2 ** MEM_ADDRESS_WIDTH; + // suported ratios: 1:1 / 1:2 / 1:4 / 1:8 / 2:1 / 4:1 / 8:1 + localparam MEM_RATIO = (A_DATA_WIDTH > B_DATA_WIDTH) ? A_DATA_WIDTH/B_DATA_WIDTH : B_DATA_WIDTH/A_DATA_WIDTH; + localparam MEM_IO_COMP = (A_DATA_WIDTH > B_DATA_WIDTH) ? 1'b1 : 1'b0; // write interface - input clka; - input wea; - input [A_ADDRESS_WIDTH-1:0] addra; - input [A_DATA_WIDTH-1:0] dina; + input clka; + input wea; + input [A_ADDRESS_WIDTH-1:0] addra; + input [A_DATA_WIDTH-1:0] dina; // read interface - input clkb; - input [B_ADDRESS_WIDTH-1:0] addrb; - output [B_DATA_WIDTH-1:0] doutb; + input clkb; + input [B_ADDRESS_WIDTH-1:0] addrb; + output [B_DATA_WIDTH-1:0] doutb; // internal registers - reg [B_DATA_WIDTH-1:0] m_ram[0:MEM_SIZE-1]; - reg [B_DATA_WIDTH-1:0] doutb; + reg [MEM_DATA_WIDTH-1:0] m_ram[0:MEM_SIZE-1]; + reg [B_DATA_WIDTH-1:0] doutb; - // write interface + // write interface options - generate - if (MEM_RATIO == 1) begin - always @(posedge clka) begin - if (wea == 1'b1) begin - m_ram[addra] <= dina; + generate if (MEM_IO_COMP == 0) begin + always @(posedge clka) begin + if (wea == 1'b1) begin + m_ram[addra] <= dina; + end end end - end - - if (MEM_RATIO == 2) begin - always @(posedge clka) begin - if (wea == 1'b1) begin - m_ram[{addra, 1'd0}] <= dina[((1*B_DATA_WIDTH)-1):(B_DATA_WIDTH*0)]; - m_ram[{addra, 1'd1}] <= dina[((2*B_DATA_WIDTH)-1):(B_DATA_WIDTH*1)]; - end - end - end - - if (MEM_RATIO == 4) begin - always @(posedge clka) begin - if (wea == 1'b1) begin - m_ram[{addra, 2'd0}] <= dina[((1*B_DATA_WIDTH)-1):(B_DATA_WIDTH*0)]; - m_ram[{addra, 2'd1}] <= dina[((2*B_DATA_WIDTH)-1):(B_DATA_WIDTH*1)]; - m_ram[{addra, 2'd2}] <= dina[((3*B_DATA_WIDTH)-1):(B_DATA_WIDTH*2)]; - m_ram[{addra, 2'd3}] <= dina[((4*B_DATA_WIDTH)-1):(B_DATA_WIDTH*3)]; - end - end - end - - if (MEM_RATIO == 8) begin - always @(posedge clka) begin - if (wea == 1'b1) begin - m_ram[{addra, 3'd0}] <= dina[((1*B_DATA_WIDTH)-1):(B_DATA_WIDTH*0)]; - m_ram[{addra, 3'd1}] <= dina[((2*B_DATA_WIDTH)-1):(B_DATA_WIDTH*1)]; - m_ram[{addra, 3'd2}] <= dina[((3*B_DATA_WIDTH)-1):(B_DATA_WIDTH*2)]; - m_ram[{addra, 3'd3}] <= dina[((4*B_DATA_WIDTH)-1):(B_DATA_WIDTH*3)]; - m_ram[{addra, 3'd4}] <= dina[((5*B_DATA_WIDTH)-1):(B_DATA_WIDTH*4)]; - m_ram[{addra, 3'd5}] <= dina[((6*B_DATA_WIDTH)-1):(B_DATA_WIDTH*5)]; - m_ram[{addra, 3'd6}] <= dina[((7*B_DATA_WIDTH)-1):(B_DATA_WIDTH*6)]; - m_ram[{addra, 3'd7}] <= dina[((8*B_DATA_WIDTH)-1):(B_DATA_WIDTH*7)]; - end - end - end endgenerate - // read interface - - always @(posedge clkb) begin - doutb <= m_ram[addrb]; + generate if ((MEM_IO_COMP == 1) && (MEM_RATIO == 2)) begin + always @(posedge clka) begin + if (wea == 1'b1) begin + m_ram[{addra, 1'd0}] <= dina[((1*B_DATA_WIDTH)-1):(B_DATA_WIDTH*0)]; + m_ram[{addra, 1'd1}] <= dina[((2*B_DATA_WIDTH)-1):(B_DATA_WIDTH*1)]; + end + end end + endgenerate + + generate if ((MEM_IO_COMP == 1) && (MEM_RATIO == 4)) begin + always @(posedge clka) begin + if (wea == 1'b1) begin + m_ram[{addra, 2'd0}] <= dina[((1*B_DATA_WIDTH)-1):(B_DATA_WIDTH*0)]; + m_ram[{addra, 2'd1}] <= dina[((2*B_DATA_WIDTH)-1):(B_DATA_WIDTH*1)]; + m_ram[{addra, 2'd2}] <= dina[((3*B_DATA_WIDTH)-1):(B_DATA_WIDTH*2)]; + m_ram[{addra, 2'd3}] <= dina[((4*B_DATA_WIDTH)-1):(B_DATA_WIDTH*3)]; + end + end + end + endgenerate + + generate if ((MEM_IO_COMP == 1) && (MEM_RATIO == 8)) begin + always @(posedge clka) begin + if (wea == 1'b1) begin + m_ram[{addra, 3'd0}] <= dina[((1*B_DATA_WIDTH)-1):(B_DATA_WIDTH*0)]; + m_ram[{addra, 3'd1}] <= dina[((2*B_DATA_WIDTH)-1):(B_DATA_WIDTH*1)]; + m_ram[{addra, 3'd2}] <= dina[((3*B_DATA_WIDTH)-1):(B_DATA_WIDTH*2)]; + m_ram[{addra, 3'd3}] <= dina[((4*B_DATA_WIDTH)-1):(B_DATA_WIDTH*3)]; + m_ram[{addra, 3'd4}] <= dina[((5*B_DATA_WIDTH)-1):(B_DATA_WIDTH*4)]; + m_ram[{addra, 3'd5}] <= dina[((6*B_DATA_WIDTH)-1):(B_DATA_WIDTH*5)]; + m_ram[{addra, 3'd6}] <= dina[((7*B_DATA_WIDTH)-1):(B_DATA_WIDTH*6)]; + m_ram[{addra, 3'd7}] <= dina[((8*B_DATA_WIDTH)-1):(B_DATA_WIDTH*7)]; + end + end + end + endgenerate + + // read interface options + + generate if ((MEM_IO_COMP == 1) || (MEM_RATIO == 1)) begin + always @(posedge clkb) begin + doutb <= m_ram[addrb]; + end + end + endgenerate + + generate if ((MEM_IO_COMP == 0) && (MEM_RATIO == 2)) begin + always @(posedge clkb) begin + doutb <= {m_ram[{addrb, 1'd1}], + m_ram[{addrb, 1'd0}]}; + end + end + endgenerate + + generate if ((MEM_IO_COMP == 0) && (MEM_RATIO == 4)) begin + always @(posedge clkb) begin + doutb <= {m_ram[{addrb, 2'd3}], + m_ram[{addrb, 2'd2}], + m_ram[{addrb, 2'd1}], + m_ram[{addrb, 2'd0}]}; + end + end + endgenerate + + generate if ((MEM_IO_COMP == 0) && (MEM_RATIO == 8)) begin + always @(posedge clkb) begin + doutb <= {m_ram[{addrb, 3'd7}], + m_ram[{addrb, 3'd6}], + m_ram[{addrb, 3'd5}], + m_ram[{addrb, 3'd4}], + m_ram[{addrb, 3'd3}], + m_ram[{addrb, 3'd2}], + m_ram[{addrb, 3'd1}], + m_ram[{addrb, 3'd0}]}; + end + end + endgenerate endmodule diff --git a/library/common/ad_serdes_in.v b/library/common/ad_serdes_in.v deleted file mode 100644 index b4d8f0d36..000000000 --- a/library/common/ad_serdes_in.v +++ /dev/null @@ -1,398 +0,0 @@ -// *************************************************************************** -// *************************************************************************** -// Copyright 2011(c) Analog Devices, Inc. -// -// All rights reserved. -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are met: -// - Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// - Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in -// the documentation and/or other materials provided with the -// distribution. -// - Neither the name of Analog Devices, Inc. nor the names of its -// contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// - The use of this software may or may not infringe the patent rights -// of one or more patent holders. This license does not release you -// from the requirement that you obtain separate licenses from these -// patent holders to use this software. -// - Use of the software either in source or binary form, must be run -// on or directly connected to an Analog Devices Inc. component. -// -// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR -// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -// -// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, -// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR -// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE -// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// *************************************************************************** -// *************************************************************************** -// *************************************************************************** -// *************************************************************************** -`timescale 1ps/1ps - -module ad_serdes_in ( - - // reset and clocks - - rst, - clk, - div_clk, - - // data interface - - data_s0, - data_s1, - data_s2, - data_s3, - data_s4, - data_s5, - data_s6, - data_s7, - data_in_p, - data_in_n, - - // delay-data interface - - up_clk, - up_dld, - up_dwdata, - up_drdata, - - // delay-control interface - - delay_clk, - delay_rst, - delay_locked); - - // parameters - - parameter DEVICE_TYPE = 0; - parameter IODELAY_CTRL = 0; - parameter IODELAY_GROUP = "dev_if_delay_group"; - // SDR = 0 / DDR = 1 - parameter DDR_OR_SDR_N = 0; - // serialization factor - parameter DATA_WIDTH = 8; - - localparam DEVICE_6SERIES = 1; - localparam DEVICE_7SERIES = 0; - localparam SDR = 0; - localparam DDR = 1; - - // reset and clocks - - input rst; - input clk; - input div_clk; - - // data interface - - output data_s0; - output data_s1; - output data_s2; - output data_s3; - output data_s4; - output data_s5; - output data_s6; - output data_s7; - input data_in_p; - input data_in_n; - - // delay-data interface - - input up_clk; - input up_dld; - input [ 4:0] up_dwdata; - output [ 4:0] up_drdata; - - // delay-control interface - input delay_clk; - input delay_rst; - output delay_locked; - - // internal signals - - wire data_in_ibuf_s; - wire data_in_idelay_s; - wire data_shift1_s; - wire data_shift2_s; - - // delay controller - - generate - if (IODELAY_CTRL == 1) begin - (* IODELAY_GROUP = IODELAY_GROUP *) - IDELAYCTRL i_delay_ctrl ( - .RST (delay_rst), - .REFCLK (delay_clk), - .RDY (delay_locked)); - end else begin - assign delay_locked = 1'b1; - end - endgenerate - - // received data interface: ibuf -> idelay -> iserdes - - IBUFDS i_ibuf ( - .O(data_in_ibuf_s), - .I(data_in_p), - .IB(data_in_n) - ); - - if(DEVICE_TYPE == DEVICE_7SERIES) begin - (* IODELAY_GROUP = IODELAY_GROUP *) - - IDELAYE2 #( - .CINVCTRL_SEL ("FALSE"), - .DELAY_SRC ("IDATAIN"), - .HIGH_PERFORMANCE_MODE ("FALSE"), - .IDELAY_TYPE ("VAR_LOAD"), - .IDELAY_VALUE (0), - .REFCLK_FREQUENCY (200.0), - .PIPE_SEL ("FALSE"), - .SIGNAL_PATTERN ("DATA")) - i_rx_data_idelay ( - .CE (1'b0), - .INC (1'b0), - .DATAIN (1'b0), - .LDPIPEEN (1'b0), - .CINVCTRL (1'b0), - .REGRST (1'b0), - .C (up_clk), - .IDATAIN (data_in_ibuf_s), - .DATAOUT (data_in_idelay_s), - .LD (up_dld), - .CNTVALUEIN (up_dwdata), - .CNTVALUEOUT (up_drdata)); - - // Note: The first sample in time will be data_s7, the last data_s0! - if(DDR_OR_SDR_N == SDR) begin - ISERDESE2 #( - .DATA_RATE("SDR"), - .DATA_WIDTH(DATA_WIDTH), - .DYN_CLKDIV_INV_EN("FALSE"), - .DYN_CLK_INV_EN("FALSE"), - .INIT_Q1(1'b0), - .INIT_Q2(1'b0), - .INIT_Q3(1'b0), - .INIT_Q4(1'b0), - .INTERFACE_TYPE("NETWORKING"), - .IOBDELAY("IFD"), - .NUM_CE(2), - .OFB_USED("FALSE"), - .SERDES_MODE("MASTER"), - .SRVAL_Q1(1'b0), - .SRVAL_Q2(1'b0), - .SRVAL_Q3(1'b0), - .SRVAL_Q4(1'b0)) - ISERDESE2_inst ( - .O(), - .Q1(data_s0), - .Q2(data_s1), - .Q3(data_s2), - .Q4(data_s3), - .Q5(data_s4), - .Q6(data_s5), - .Q7(data_s6), - .Q8(data_s7), - .SHIFTOUT1(), - .SHIFTOUT2(), - .BITSLIP(1'b0), - .CE1(1'b1), - .CE2(1'b1), - .CLKDIVP(1'b0), - .CLK(clk), - .CLKB(~clk), - .CLKDIV(div_clk), - .OCLK(1'b0), - .DYNCLKDIVSEL(1'b0), - .DYNCLKSEL(1'b0), - .D(1'b0), - .DDLY(data_in_idelay_s), - .OFB(1'b0), - .OCLKB(1'b0), - .RST(rst), - .SHIFTIN1(1'b0), - .SHIFTIN2(1'b0) - ); - end else begin - - ISERDESE2 #( - .DATA_RATE("DDR"), - .DATA_WIDTH(DATA_WIDTH), - .DYN_CLKDIV_INV_EN("FALSE"), - .DYN_CLK_INV_EN("FALSE"), - .INIT_Q1(1'b0), - .INIT_Q2(1'b0), - .INIT_Q3(1'b0), - .INIT_Q4(1'b0), - .INTERFACE_TYPE("NETWORKING"), - .IOBDELAY("IFD"), - .NUM_CE(2), - .OFB_USED("FALSE"), - .SERDES_MODE("MASTER"), - .SRVAL_Q1(1'b0), - .SRVAL_Q2(1'b0), - .SRVAL_Q3(1'b0), - .SRVAL_Q4(1'b0)) - ISERDESE2_inst ( - .O(), - .Q1(data_s0), - .Q2(data_s1), - .Q3(data_s2), - .Q4(data_s3), - .Q5(data_s4), - .Q6(data_s5), - .Q7(data_s6), - .Q8(data_s7), - .SHIFTOUT1(), - .SHIFTOUT2(), - .BITSLIP(1'b0), - .CE1(1'b1), - .CE2(1'b1), - .CLKDIVP(1'b0), - .CLK(clk), - .CLKB(~clk), - .CLKDIV(div_clk), - .OCLK(1'b0), - .DYNCLKDIVSEL(1'b0), - .DYNCLKSEL(1'b0), - .D(1'b0), - .DDLY(data_in_idelay_s), - .OFB(1'b0), - .OCLKB(1'b0), - .RST(rst), - .SHIFTIN1(1'b0), - .SHIFTIN2(1'b0) - ); - end - end - - if(DEVICE_TYPE == DEVICE_6SERIES) begin - (* IODELAY_GROUP = IODELAY_GROUP *) - IODELAYE1 #( - .CINVCTRL_SEL ("FALSE"), - .DELAY_SRC ("I"), - .HIGH_PERFORMANCE_MODE ("TRUE"), - .IDELAY_TYPE ("VAR_LOADABLE"), - .IDELAY_VALUE (0), - .ODELAY_TYPE ("FIXED"), - .ODELAY_VALUE (0), - .REFCLK_FREQUENCY (200.0), - .SIGNAL_PATTERN ("DATA")) - i_rx_data_idelay ( - .T (1'b1), - .CE (1'b0), - .INC (1'b0), - .CLKIN (1'b0), - .DATAIN (1'b0), - .ODATAIN (1'b0), - .CINVCTRL (1'b0), - .C (up_clk), - .IDATAIN (data_in_ibuf_s), - .DATAOUT (data_in_idelay_s), - .RST (up_dld), - .CNTVALUEIN (up_dwdata), - .CNTVALUEOUT (up_drdata)); - - ISERDESE1 #( - .DATA_RATE("DDR"), - .DATA_WIDTH(DATA_WIDTH), - .DYN_CLKDIV_INV_EN("FALSE"), - .DYN_CLK_INV_EN("FALSE"), - .INIT_Q1(1'b0), - .INIT_Q2(1'b0), - .INIT_Q3(1'b0), - .INIT_Q4(1'b0), - .INTERFACE_TYPE("NETWORKING"), - .IOBDELAY("NONE"), - .NUM_CE(1), - .OFB_USED("FALSE"), - .SERDES_MODE("MASTER"), - .SRVAL_Q1(1'b0), - .SRVAL_Q2(1'b0), - .SRVAL_Q3(1'b0), - .SRVAL_Q4(1'b0)) - i_serdes_m ( - .O(), - .Q1(data_s0), - .Q2(data_s1), - .Q3(data_s2), - .Q4(data_s3), - .Q5(data_s4), - .Q6(data_s5), - .SHIFTOUT1(data_shift1_s), - .SHIFTOUT2(data_shift2_s), - .BITSLIP(1'b0), - .CE1(1'b1), - .CE2(1'b1), - .CLK(clk), - .CLKB(1'b0), - .CLKDIV(div_clk), - .OCLK(1'b0), - .DYNCLKDIVSEL(1'b0), - .DYNCLKSEL(1'b0), - .D(data_in_idelay_s), - .DDLY(1'b0), - .OFB(1'b0), - .RST(rst), - .SHIFTIN1(1'b0), - .SHIFTIN2(1'b0) - ); - - ISERDESE1 #( - .DATA_RATE("DDR"), - .DATA_WIDTH(DATA_WIDTH), - .DYN_CLKDIV_INV_EN("FALSE"), - .DYN_CLK_INV_EN("FALSE"), - .INIT_Q1(1'b0), - .INIT_Q2(1'b0), - .INIT_Q3(1'b0), - .INIT_Q4(1'b0), - .INTERFACE_TYPE("NETWORKING"), - .IOBDELAY("NONE"), - .NUM_CE(1), - .OFB_USED("FALSE"), - .SERDES_MODE("SLAVE"), - .SRVAL_Q1(1'b0), - .SRVAL_Q2(1'b0), - .SRVAL_Q3(1'b0), - .SRVAL_Q4(1'b0)) - i_serdes_s ( - .O(), - .Q1(), - .Q2(), - .Q3(data_s6), - .Q4(data_s7), - .Q5(), - .Q6(), - .SHIFTOUT1(), - .SHIFTOUT2(), - .BITSLIP(1'b0), - .CE1(1'b1), - .CE2(1'b1), - .CLK(clk), - .CLKB(1'b0), - .CLKDIV(div_clk), - .OCLK(1'b0), - .DYNCLKDIVSEL(1'b0), - .DYNCLKSEL(1'b0), - .D(1'b0), - .DDLY(1'b0), - .OFB(1'b0), - .RST(rst), - .SHIFTIN1(data_shift1_s), - .SHIFTIN2(data_shift2_s)); - end - -endmodule - diff --git a/library/common/ad_serdes_out.v b/library/common/ad_serdes_out.v deleted file mode 100644 index 334785720..000000000 --- a/library/common/ad_serdes_out.v +++ /dev/null @@ -1,246 +0,0 @@ -// *************************************************************************** -// *************************************************************************** -// Copyright 2011(c) Analog Devices, Inc. -// -// All rights reserved. -// -// Redistribution and use in source and binary forms, with or without modification, -// are permitted provided that the following conditions are met: -// - Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// - Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in -// the documentation and/or other materials provided with the -// distribution. -// - Neither the name of Analog Devices, Inc. nor the names of its -// contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// - The use of this software may or may not infringe the patent rights -// of one or more patent holders. This license does not release you -// from the requirement that you obtain separate licenses from these -// patent holders to use this software. -// - Use of the software either in source or binary form, must be run -// on or directly connected to an Analog Devices Inc. component. -// -// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, -// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A -// PARTICULAR PURPOSE ARE DISCLAIMED. -// -// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY -// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF -// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// *************************************************************************** -// *************************************************************************** -// *************************************************************************** -// *************************************************************************** -// serial data output interface: serdes(x8) or oddr(x2) output module - -`timescale 1ps/1ps - -module ad_serdes_out ( - - // reset and clocks - - rst, - clk, - div_clk, - - // data interface - - data_s0, - data_s1, - data_s2, - data_s3, - data_s4, - data_s5, - data_s6, - data_s7, - data_out_p, - data_out_n); - - // parameters - - parameter DEVICE_TYPE = 0; - parameter SERDES_OR_DDR_N = 1; - parameter DATA_WIDTH = 16; - - - localparam DEVICE_6SERIES = 1; - localparam DEVICE_7SERIES = 0; - localparam DW = DATA_WIDTH - 1; - - // reset and clocks - - input rst; - input clk; - input div_clk; - - // data interface - - input [DW:0] data_s0; - input [DW:0] data_s1; - input [DW:0] data_s2; - input [DW:0] data_s3; - input [DW:0] data_s4; - input [DW:0] data_s5; - input [DW:0] data_s6; - input [DW:0] data_s7; - output [DW:0] data_out_p; - output [DW:0] data_out_n; - - // internal signals - - wire [DW:0] data_out_s; - wire [DW:0] serdes_shift1_s; - wire [DW:0] serdes_shift2_s; - - // instantiations - - genvar l_inst; - generate - for (l_inst = 0; l_inst <= DW; l_inst = l_inst + 1) begin: g_data - - if (SERDES_OR_DDR_N == 0) begin - ODDR #( - .DDR_CLK_EDGE ("SAME_EDGE"), - .INIT (1'b0), - .SRTYPE ("ASYNC")) - i_oddr ( - .S (1'b0), - .CE (1'b1), - .R (rst), - .C (clk), - .D1 (data_s0[l_inst]), - .D2 (data_s1[l_inst]), - .Q (data_out_s[l_inst])); - end - - if ((SERDES_OR_DDR_N == 1) && (DEVICE_TYPE == DEVICE_7SERIES)) begin - OSERDESE2 #( - .DATA_RATE_OQ ("DDR"), - .DATA_RATE_TQ ("SDR"), - .DATA_WIDTH (8), - .TRISTATE_WIDTH (1), - .SERDES_MODE ("MASTER")) - i_serdes ( - .D1 (data_s0[l_inst]), - .D2 (data_s1[l_inst]), - .D3 (data_s2[l_inst]), - .D4 (data_s3[l_inst]), - .D5 (data_s4[l_inst]), - .D6 (data_s5[l_inst]), - .D7 (data_s6[l_inst]), - .D8 (data_s7[l_inst]), - .T1 (1'b0), - .T2 (1'b0), - .T3 (1'b0), - .T4 (1'b0), - .SHIFTIN1 (1'b0), - .SHIFTIN2 (1'b0), - .SHIFTOUT1 (), - .SHIFTOUT2 (), - .OCE (1'b1), - .CLK (clk), - .CLKDIV (div_clk), - .OQ (data_out_s[l_inst]), - .TQ (), - .OFB (), - .TFB (), - .TBYTEIN (1'b0), - .TBYTEOUT (), - .TCE (1'b0), - .RST (rst)); - end - - if ((SERDES_OR_DDR_N == 1) && (DEVICE_TYPE == DEVICE_6SERIES)) begin - OSERDESE1 #( - .DATA_RATE_OQ ("DDR"), - .DATA_RATE_TQ ("SDR"), - .DATA_WIDTH (8), - .INTERFACE_TYPE ("DEFAULT"), - .TRISTATE_WIDTH (1), - .SERDES_MODE ("MASTER")) - i_serdes_m ( - .D1 (data_s0[l_inst]), - .D2 (data_s1[l_inst]), - .D3 (data_s2[l_inst]), - .D4 (data_s3[l_inst]), - .D5 (data_s4[l_inst]), - .D6 (data_s5[l_inst]), - .T1 (1'b0), - .T2 (1'b0), - .T3 (1'b0), - .T4 (1'b0), - .SHIFTIN1 (serdes_shift1_s[l_inst]), - .SHIFTIN2 (serdes_shift2_s[l_inst]), - .SHIFTOUT1 (), - .SHIFTOUT2 (), - .OCE (1'b1), - .CLK (clk), - .CLKDIV (div_clk), - .CLKPERF (1'b0), - .CLKPERFDELAY (1'b0), - .WC (1'b0), - .ODV (1'b0), - .OQ (data_out_s[l_inst]), - .TQ (), - .OCBEXTEND (), - .OFB (), - .TFB (), - .TCE (1'b0), - .RST (rst)); - - OSERDESE1 #( - .DATA_RATE_OQ ("DDR"), - .DATA_RATE_TQ ("SDR"), - .DATA_WIDTH (8), - .INTERFACE_TYPE ("DEFAULT"), - .TRISTATE_WIDTH (1), - .SERDES_MODE ("SLAVE")) - i_serdes_s ( - .D1 (1'b0), - .D2 (1'b0), - .D3 (data_s6[l_inst]), - .D4 (data_s7[l_inst]), - .D5 (1'b0), - .D6 (1'b0), - .T1 (1'b0), - .T2 (1'b0), - .T3 (1'b0), - .T4 (1'b0), - .SHIFTIN1 (1'b0), - .SHIFTIN2 (1'b0), - .SHIFTOUT1 (serdes_shift1_s[l_inst]), - .SHIFTOUT2 (serdes_shift2_s[l_inst]), - .OCE (1'b1), - .CLK (clk), - .CLKDIV (div_clk), - .CLKPERF (1'b0), - .CLKPERFDELAY (1'b0), - .WC (1'b0), - .ODV (1'b0), - .OQ (), - .TQ (), - .OCBEXTEND (), - .OFB (), - .TFB (), - .TCE (1'b0), - .RST (rst)); - end - - OBUFDS i_obuf ( - .I (data_out_s[l_inst]), - .O (data_out_p[l_inst]), - .OB (data_out_n[l_inst])); - - end - endgenerate - -endmodule - -// *************************************************************************** -// *************************************************************************** - diff --git a/library/common/ad_sysref_gen.v b/library/common/ad_sysref_gen.v new file mode 100644 index 000000000..61173acd1 --- /dev/null +++ b/library/common/ad_sysref_gen.v @@ -0,0 +1,89 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2016(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module ad_sysref_gen ( + + input core_clk, + + input sysref_en, + output reg sysref_out +); + + // SYSREF period is multiple of core_clk, and has a duty cycle of 50% + // NOTE: if SYSREF always on (this is a JESD204 IP configuration), + // the period must be a correct multiple of the multiframe period + parameter SYSREF_PERIOD = 128; + + localparam SYSREF_HALFPERIOD = SYSREF_PERIOD/2 - 1; + + reg [ 7:0] counter; + reg sysref_en_m1; + reg sysref_en_m2; + reg sysref_en_int; + + // bring the enable signal to JESD core clock domain + always @(posedge core_clk) begin + sysref_en_m1 <= sysref_en; + sysref_en_m2 <= sysref_en_m1; + sysref_en_int <= sysref_en_m2; + end + + // free running counter for periodic SYSREF generation + always @(posedge core_clk) begin + if (sysref_en_int) begin + counter <= (counter < SYSREF_HALFPERIOD) ? counter + 1 : 0; + end else begin + counter <= 0; + end + end + + // generate SYSREF + always @(posedge core_clk) begin + if (sysref_en_int) begin + if (counter == SYSREF_HALFPERIOD) begin + sysref_out <= ~sysref_out; + end + end else begin + sysref_out <= 1'b0; + end + end + +endmodule diff --git a/library/common/ad_tdd_control.v b/library/common/ad_tdd_control.v index 328c9c6b0..151a3edeb 100644 --- a/library/common/ad_tdd_control.v +++ b/library/common/ad_tdd_control.v @@ -49,7 +49,6 @@ module ad_tdd_control( // TDD timming signals tdd_enable, - tdd_enable_synced, tdd_secondary, tdd_tx_only, tdd_rx_only, @@ -62,6 +61,8 @@ module ad_tdd_control( tdd_vco_tx_off_1, tdd_rx_on_1, tdd_rx_off_1, + tdd_rx_dp_on_1, + tdd_rx_dp_off_1, tdd_tx_on_1, tdd_tx_off_1, tdd_tx_dp_on_1, @@ -72,16 +73,18 @@ module ad_tdd_control( tdd_vco_tx_off_2, tdd_rx_on_2, tdd_rx_off_2, + tdd_rx_dp_on_2, + tdd_rx_dp_off_2, tdd_tx_on_2, tdd_tx_off_2, tdd_tx_dp_on_2, tdd_tx_dp_off_2, tdd_sync, - tdd_sync_en, // TDD control signals tdd_tx_dp_en, + tdd_rx_dp_en, tdd_rx_vco_en, tdd_tx_vco_en, tdd_rx_rf_en, @@ -103,7 +106,6 @@ module ad_tdd_control( input rst; input tdd_enable; - output tdd_enable_synced; input tdd_secondary; input tdd_tx_only; input tdd_rx_only; @@ -116,6 +118,8 @@ module ad_tdd_control( input [23:0] tdd_vco_tx_off_1; input [23:0] tdd_rx_on_1; input [23:0] tdd_rx_off_1; + input [23:0] tdd_rx_dp_on_1; + input [23:0] tdd_rx_dp_off_1; input [23:0] tdd_tx_on_1; input [23:0] tdd_tx_off_1; input [23:0] tdd_tx_dp_on_1; @@ -126,25 +130,28 @@ module ad_tdd_control( input [23:0] tdd_vco_tx_off_2; input [23:0] tdd_rx_on_2; input [23:0] tdd_rx_off_2; + input [23:0] tdd_rx_dp_on_2; + input [23:0] tdd_rx_dp_off_2; input [23:0] tdd_tx_on_2; input [23:0] tdd_tx_off_2; input [23:0] tdd_tx_dp_on_2; input [23:0] tdd_tx_dp_off_2; input tdd_sync; - output tdd_sync_en; - output tdd_tx_dp_en; // initiate vco tx2rx switch - output tdd_rx_vco_en; // initiate vco rx2tx switch - output tdd_tx_vco_en; // power up RF Rx - output tdd_rx_rf_en; // power up RF Tx - output tdd_tx_rf_en; // enable Tx datapath + output tdd_rx_vco_en; // initiate vco tx2rx switch + output tdd_tx_vco_en; // initiate vco rx2tx switch + output tdd_rx_rf_en; // power up RF Rx + output tdd_tx_rf_en; // power up RF Tx + output tdd_tx_dp_en; // enable Tx datapath + output tdd_rx_dp_en; // enable Rx datapath output [23:0] tdd_counter_status; // tdd control related reg tdd_tx_dp_en = 1'b0; + reg tdd_rx_dp_en = 1'b0; reg tdd_rx_vco_en = 1'b0; reg tdd_tx_vco_en = 1'b0; reg tdd_rx_rf_en = 1'b0; @@ -164,6 +171,8 @@ module ad_tdd_control( reg counter_at_tdd_vco_tx_off_1 = 1'b0; reg counter_at_tdd_rx_on_1 = 1'b0; reg counter_at_tdd_rx_off_1 = 1'b0; + reg counter_at_tdd_rx_dp_on_1 = 1'b0; + reg counter_at_tdd_rx_dp_off_1 = 1'b0; reg counter_at_tdd_tx_on_1 = 1'b0; reg counter_at_tdd_tx_off_1 = 1'b0; reg counter_at_tdd_tx_dp_on_1 = 1'b0; @@ -174,20 +183,19 @@ module ad_tdd_control( reg counter_at_tdd_vco_tx_off_2 = 1'b0; reg counter_at_tdd_rx_on_2 = 1'b0; reg counter_at_tdd_rx_off_2 = 1'b0; + reg counter_at_tdd_rx_dp_on_2 = 1'b0; + reg counter_at_tdd_rx_dp_off_2 = 1'b0; reg counter_at_tdd_tx_on_2 = 1'b0; reg counter_at_tdd_tx_off_2 = 1'b0; reg counter_at_tdd_tx_dp_on_2 = 1'b0; reg counter_at_tdd_tx_dp_off_2 = 1'b0; - reg tdd_enable_synced = 1'h0; reg tdd_last_burst = 1'b0; reg tdd_sync_d1 = 1'b0; reg tdd_sync_d2 = 1'b0; reg tdd_sync_d3 = 1'b0; - reg tdd_sync_en = 1'b0; - // internal signals wire [23:0] tdd_vco_rx_on_1_s; @@ -220,26 +228,16 @@ module ad_tdd_control( // synchronization of tdd_sync always @(posedge clk) begin if (rst == 1'b1) begin - tdd_sync_en <= 1'b0; tdd_sync_d1 <= 1'b0; tdd_sync_d2 <= 1'b0; tdd_sync_d3 <= 1'b0; end else begin - tdd_sync_en <= tdd_enable; tdd_sync_d1 <= tdd_sync; tdd_sync_d2 <= tdd_sync_d1; tdd_sync_d3 <= tdd_sync_d2; end end - always @(posedge clk) begin - if (rst == 1'b1) begin - tdd_enable_synced <= 1'b0; - end else begin - tdd_enable_synced <= ((~tdd_sync_d3 & tdd_sync_d2) == 1'b1) ? tdd_enable : tdd_enable_synced; - end - end - // *************************************************************************** // tdd counter (state machine) // *************************************************************************** @@ -516,6 +514,48 @@ module ad_tdd_control( end end + // start/stop rx data path + always @(posedge clk) begin + if(rst == 1'b1) begin + counter_at_tdd_rx_dp_on_1 <= 1'b0; + end else if(tdd_counter == tdd_rx_dp_on_1) begin + counter_at_tdd_rx_dp_on_1 <= 1'b1; + end else begin + counter_at_tdd_rx_dp_on_1 <= 1'b0; + end + end + + always @(posedge clk) begin + if(rst == 1'b1) begin + counter_at_tdd_rx_dp_on_2 <= 1'b0; + end else if((tdd_secondary == 1'b1) && (tdd_counter == tdd_rx_dp_on_2)) begin + counter_at_tdd_rx_dp_on_2 <= 1'b1; + end else begin + counter_at_tdd_rx_dp_on_2 <= 1'b0; + end + end + + always @(posedge clk) begin + if(rst == 1'b1) begin + counter_at_tdd_rx_dp_off_1 <= 1'b0; + end else if(tdd_counter == tdd_rx_dp_off_1) begin + counter_at_tdd_rx_dp_off_1 <= 1'b1; + end else begin + counter_at_tdd_rx_dp_off_1 <= 1'b0; + end + end + + always @(posedge clk) begin + if(rst == 1'b1) begin + counter_at_tdd_rx_dp_off_2 <= 1'b0; + end else if((tdd_secondary == 1'b1) && (tdd_counter == tdd_rx_dp_off_2)) begin + counter_at_tdd_rx_dp_off_2 <= 1'b1; + end else begin + counter_at_tdd_rx_dp_off_2 <= 1'b0; + end + end + + // control-path delay compensation ad_addsub #( @@ -834,5 +874,19 @@ module ad_tdd_control( end end + always @(posedge clk) begin + if(rst == 1'b1) begin + tdd_rx_dp_en <= 1'b0; + end else if((tdd_cstate == OFF) || (counter_at_tdd_rx_dp_off_1 == 1'b1) || (counter_at_tdd_rx_dp_off_2 == 1'b1)) begin + tdd_rx_dp_en <= 1'b0; + end else if((tdd_cstate == ON) && ((counter_at_tdd_rx_dp_on_1 == 1'b1) || (counter_at_tdd_rx_dp_on_2 == 1'b1))) begin + tdd_rx_dp_en <= 1'b1; + end else if((tdd_cstate == ON) && (tdd_txrx_only_en_s == 1'b1)) begin + tdd_rx_dp_en <= tdd_rx_only; + end else begin + tdd_rx_dp_en <= tdd_rx_dp_en; + end + end + endmodule diff --git a/library/common/ad_xcvr_rx_if.v b/library/common/ad_xcvr_rx_if.v new file mode 100644 index 000000000..a53052706 --- /dev/null +++ b/library/common/ad_xcvr_rx_if.v @@ -0,0 +1,127 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module ad_xcvr_rx_if ( + + // jesd interface + + rx_clk, + rx_ip_sof, + rx_ip_data, + rx_sof, + rx_data); + + // parameter + + parameter DEVICE_TYPE = 0; + + // jesd interface + + input rx_clk; + input [ 3:0] rx_ip_sof; + input [31:0] rx_ip_data; + + // aligned data + + output rx_sof; + output [31:0] rx_data; + + // internal registers + + reg [31:0] rx_ip_data_d = 'd0; + reg [ 3:0] rx_ip_sof_hold = 'd0; + reg rx_sof = 'd0; + reg rx_ip_sof_d = 'd0; + reg [31:0] rx_data = 'd0; + + // internal signals + + wire [ 3:0] rx_ip_sof_s; + wire [31:0] rx_ip_data_s; + + // altera/xilinx + + generate + if (DEVICE_TYPE == 1) begin + assign rx_ip_sof_s[3] = rx_ip_sof[0]; + assign rx_ip_sof_s[2] = rx_ip_sof[1]; + assign rx_ip_sof_s[1] = rx_ip_sof[2]; + assign rx_ip_sof_s[0] = rx_ip_sof[3]; + assign rx_ip_data_s[31:24] = rx_ip_data[ 7: 0]; + assign rx_ip_data_s[23:16] = rx_ip_data[15: 8]; + assign rx_ip_data_s[15: 8] = rx_ip_data[23:16]; + assign rx_ip_data_s[ 7: 0] = rx_ip_data[31:24]; + end else begin + assign rx_ip_sof_s[3] = rx_ip_sof[3]; + assign rx_ip_sof_s[2] = rx_ip_sof[2]; + assign rx_ip_sof_s[1] = rx_ip_sof[1]; + assign rx_ip_sof_s[0] = rx_ip_sof[0]; + assign rx_ip_data_s[31:24] = rx_ip_data[31:24]; + assign rx_ip_data_s[23:16] = rx_ip_data[23:16]; + assign rx_ip_data_s[15: 8] = rx_ip_data[15: 8]; + assign rx_ip_data_s[ 7: 0] = rx_ip_data[ 7: 0]; + end + endgenerate + + // dword may contain more than one frame per clock + + always @(posedge rx_clk) begin + rx_ip_data_d <= rx_ip_data_s; + rx_ip_sof_d <= rx_ip_sof_s; + if (rx_ip_sof_s != 4'h0) begin + rx_ip_sof_hold <= rx_ip_sof_s; + end + rx_sof <= |rx_ip_sof_d; + if (rx_ip_sof_hold[0] == 1'b1) begin + rx_data <= rx_ip_data_s; + end else if (rx_ip_sof_hold[1] == 1'b1) begin + rx_data <= {rx_ip_data_s[ 7:0], rx_ip_data_d[31: 8]}; + end else if (rx_ip_sof_hold[2] == 1'b1) begin + rx_data <= {rx_ip_data_s[15:0], rx_ip_data_d[31:16]}; + end else if (rx_ip_sof_hold[3] == 1'b1) begin + rx_data <= {rx_ip_data_s[23:0], rx_ip_data_d[31:24]}; + end else begin + rx_data <= 32'd0; + end + end + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/library/common/altera/DSP48E1.v b/library/common/altera/DSP48E1.v deleted file mode 100644 index cdf993f86..000000000 --- a/library/common/altera/DSP48E1.v +++ /dev/null @@ -1,186 +0,0 @@ -// *************************************************************************** -// *************************************************************************** -// Copyright 2011(c) Analog Devices, Inc. -// -// All rights reserved. -// -// Redistribution and use in source and binary forms, with or without modification, -// are permitted provided that the following conditions are met: -// - Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// - Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in -// the documentation and/or other materials provided with the -// distribution. -// - Neither the name of Analog Devices, Inc. nor the names of its -// contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// - The use of this software may or may not infringe the patent rights -// of one or more patent holders. This license does not release you -// from the requirement that you obtain separate licenses from these -// patent holders to use this software. -// - Use of the software either in source or binary form, must be run -// on or directly connected to an Analog Devices Inc. component. -// -// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, -// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A -// PARTICULAR PURPOSE ARE DISCLAIMED. -// -// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY -// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF -// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// *************************************************************************** -// *************************************************************************** -// *************************************************************************** -// *************************************************************************** -// dc filter- y(n) = c*x(n) + (1-c)*y(n-1) - -`timescale 1ps/1ps - -module DSP48E1 ( - - ACOUT, - BCOUT, - CARRYCASCOUT, - CARRYOUT, - MULTSIGNOUT, - OVERFLOW, - P, - PATTERNBDETECT, - PATTERNDETECT, - PCOUT, - UNDERFLOW, - A, - ACIN, - ALUMODE, - B, - BCIN, - C, - CARRYCASCIN, - CARRYIN, - CARRYINSEL, - CEA1, - CEA2, - CEAD, - CEALUMODE, - CEB1, - CEB2, - CEC, - CECARRYIN, - CECTRL, - CED, - CEINMODE, - CEM, - CEP, - CLK, - D, - INMODE, - MULTSIGNIN, - OPMODE, - PCIN, - RSTA, - RSTALLCARRYIN, - RSTALUMODE, - RSTB, - RSTC, - RSTCTRL, - RSTD, - RSTINMODE, - RSTM, - RSTP); - - parameter ACASCREG = 1; - parameter ADREG = 1; - parameter ALUMODEREG = 1; - parameter AREG = 1; - parameter AUTORESET_PATDET = "NO_RESET"; - parameter A_INPUT = "DIRECT"; - parameter BCASCREG = 1; - parameter BREG = 1; - parameter B_INPUT = "DIRECT"; - parameter CARRYINREG = 1; - parameter CARRYINSELREG = 1; - parameter CREG = 1; - parameter DREG = 1; - parameter INMODEREG = 1; - parameter MASK = 'h3fffffffffff; - parameter MREG = 1; - parameter OPMODEREG = 1; - parameter PATTERN = 0; - parameter PREG = 1; - parameter SEL_MASK = "MASK"; - parameter SEL_PATTERN = "PATTERN"; - parameter USE_DPORT = 0; - parameter USE_MULT = "MULTIPLY"; - parameter USE_PATTERN_DETECT = "NO_PATDET"; - parameter USE_SIMD = "ONE48"; - - output [29:0] ACOUT; - output [17:0] BCOUT; - output CARRYCASCOUT; - output [ 3:0] CARRYOUT; - output MULTSIGNOUT; - output OVERFLOW; - output [47:0] P; - output PATTERNBDETECT; - output PATTERNDETECT; - output [47:0] PCOUT; - output UNDERFLOW; - input [29:0] A; - input [29:0] ACIN; - input [ 3:0] ALUMODE; - input [17:0] B; - input [17:0] BCIN; - input [47:0] C; - input CARRYCASCIN; - input CARRYIN; - input [ 2:0] CARRYINSEL; - input CEA1; - input CEA2; - input CEAD; - input CEALUMODE; - input CEB1; - input CEB2; - input CEC; - input CECARRYIN; - input CECTRL; - input CED; - input CEINMODE; - input CEM; - input CEP; - input CLK; - input [24:0] D; - input [ 4:0] INMODE; - input MULTSIGNIN; - input [ 6:0] OPMODE; - input [47:0] PCIN; - input RSTA; - input RSTALLCARRYIN; - input RSTALUMODE; - input RSTB; - input RSTC; - input RSTCTRL; - input RSTD; - input RSTINMODE; - input RSTM; - input RSTP; - - assign ACOUT = 30'd0; - assign BCOUT = 18'd0; - assign CARRYCASCOUT = 1'd0; - assign CARRYOUT = 4'd0; - assign MULTSIGNOUT = 1'd0; - assign OVERFLOW = 1'd0; - assign P = 48'd0; - assign PATTERNBDETECT = 1'd0; - assign PATTERNDETECT = 1'd0; - assign PCOUT = 48'd0; - assign UNDERFLOW = 1'd0; - -endmodule - -// *************************************************************************** -// *************************************************************************** diff --git a/library/common/sync_bits.v b/library/common/sync_bits.v index cec9f09ec..2530f047b 100644 --- a/library/common/sync_bits.v +++ b/library/common/sync_bits.v @@ -45,10 +45,10 @@ */ module sync_bits ( - input [NUM_OF_BITS-1:0] in, - input out_resetn, - input out_clk, - output [NUM_OF_BITS-1:0] out + input [NUM_OF_BITS-1:0] in, + input out_resetn, + input out_clk, + output [NUM_OF_BITS-1:0] out ); // Number of bits to synchronize @@ -62,13 +62,13 @@ reg [NUM_OF_BITS-1:0] cdc_sync_stage2 = 'h0; always @(posedge out_clk) begin - if (out_resetn == 1'b0) begin - cdc_sync_stage1 <= 'b0; - cdc_sync_stage2 <= 'b0; - end else begin - cdc_sync_stage1 <= in; - cdc_sync_stage2 <= cdc_sync_stage1; - end + if (out_resetn == 1'b0) begin + cdc_sync_stage1 <= 'b0; + cdc_sync_stage2 <= 'b0; + end else begin + cdc_sync_stage1 <= in; + cdc_sync_stage2 <= cdc_sync_stage1; + end end assign out = ASYNC_CLK ? cdc_sync_stage2 : in; diff --git a/library/common/sync_gray.v b/library/common/sync_gray.v index 701dfe37c..2b67e1266 100644 --- a/library/common/sync_gray.v +++ b/library/common/sync_gray.v @@ -43,12 +43,12 @@ * change by either -1, 0 or +1. */ module sync_gray ( - input in_clk, - input in_resetn, - input [DATA_WIDTH-1:0] in_count, - input out_resetn, - input out_clk, - output [DATA_WIDTH-1:0] out_count + input in_clk, + input in_resetn, + input [DATA_WIDTH-1:0] in_count, + input out_resetn, + input out_clk, + output [DATA_WIDTH-1:0] out_count ); // Bit-width of the counter @@ -63,47 +63,47 @@ reg [DATA_WIDTH-1:0] cdc_sync_stage2 = 'h0; reg [DATA_WIDTH-1:0] out_count_m = 'h0; function [DATA_WIDTH-1:0] g2b; - input [DATA_WIDTH-1:0] g; - reg [DATA_WIDTH-1:0] b; - integer i; - begin - b[DATA_WIDTH-1] = g[DATA_WIDTH-1]; - for (i = DATA_WIDTH - 2; i >= 0; i = i - 1) - b[i] = b[i + 1] ^ g[i]; - g2b = b; - end + input [DATA_WIDTH-1:0] g; + reg [DATA_WIDTH-1:0] b; + integer i; + begin + b[DATA_WIDTH-1] = g[DATA_WIDTH-1]; + for (i = DATA_WIDTH - 2; i >= 0; i = i - 1) + b[i] = b[i + 1] ^ g[i]; + g2b = b; + end endfunction function [DATA_WIDTH-1:0] b2g; - input [DATA_WIDTH-1:0] b; - reg [DATA_WIDTH-1:0] g; - integer i; - begin - g[DATA_WIDTH-1] = b[DATA_WIDTH-1]; - for (i = DATA_WIDTH - 2; i >= 0; i = i -1) - g[i] = b[i + 1] ^ b[i]; - b2g = g; - end + input [DATA_WIDTH-1:0] b; + reg [DATA_WIDTH-1:0] g; + integer i; + begin + g[DATA_WIDTH-1] = b[DATA_WIDTH-1]; + for (i = DATA_WIDTH - 2; i >= 0; i = i -1) + g[i] = b[i + 1] ^ b[i]; + b2g = g; + end endfunction always @(posedge in_clk) begin - if (in_resetn == 1'b0) begin - cdc_sync_stage0 <= 'h00; - end else begin - cdc_sync_stage0 <= b2g(in_count); - end + if (in_resetn == 1'b0) begin + cdc_sync_stage0 <= 'h00; + end else begin + cdc_sync_stage0 <= b2g(in_count); + end end always @(posedge out_clk) begin - if (out_resetn == 1'b0) begin - cdc_sync_stage1 <= 'h00; - cdc_sync_stage2 <= 'h00; - out_count_m <= 'h00; - end else begin - cdc_sync_stage1 <= cdc_sync_stage0; - cdc_sync_stage2 <= cdc_sync_stage1; - out_count_m <= g2b(cdc_sync_stage2); - end + if (out_resetn == 1'b0) begin + cdc_sync_stage1 <= 'h00; + cdc_sync_stage2 <= 'h00; + out_count_m <= 'h00; + end else begin + cdc_sync_stage1 <= cdc_sync_stage0; + cdc_sync_stage2 <= cdc_sync_stage1; + out_count_m <= g2b(cdc_sync_stage2); + end end assign out_count = ASYNC_CLK ? out_count_m : in_count; diff --git a/library/common/up_adc_channel.v b/library/common/up_adc_channel.v index b6d85dfd4..06004bc98 100644 --- a/library/common/up_adc_channel.v +++ b/library/common/up_adc_channel.v @@ -34,126 +34,76 @@ // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // *************************************************************************** // *************************************************************************** -// *************************************************************************** -// *************************************************************************** `timescale 1ns/100ps -module up_adc_channel ( - - // adc interface - - adc_clk, - adc_rst, - adc_enable, - adc_iqcor_enb, - adc_dcfilt_enb, - adc_dfmt_se, - adc_dfmt_type, - adc_dfmt_enable, - adc_dcfilt_offset, - adc_dcfilt_coeff, - adc_iqcor_coeff_1, - adc_iqcor_coeff_2, - adc_pnseq_sel, - adc_data_sel, - adc_pn_err, - adc_pn_oos, - adc_or, - up_adc_pn_err, - up_adc_pn_oos, - up_adc_or, - - // user controls - - up_usr_datatype_be, - up_usr_datatype_signed, - up_usr_datatype_shift, - up_usr_datatype_total_bits, - up_usr_datatype_bits, - up_usr_decimation_m, - up_usr_decimation_n, - adc_usr_datatype_be, - adc_usr_datatype_signed, - adc_usr_datatype_shift, - adc_usr_datatype_total_bits, - adc_usr_datatype_bits, - adc_usr_decimation_m, - adc_usr_decimation_n, - - // bus interface - - up_rstn, - up_clk, - up_wreq, - up_waddr, - up_wdata, - up_wack, - up_rreq, - up_raddr, - up_rdata, - up_rack); +module up_adc_channel #( // parameters - parameter ADC_CHANNEL_ID = 4'h0; + parameter COMMON_ID = 6'h01, + parameter CHANNEL_ID = 4'h0, + parameter USERPORTS_DISABLE = 0, + parameter DATAFORMAT_DISABLE = 0, + parameter DCFILTER_DISABLE = 0, + parameter IQCORRECTION_DISABLE = 0) ( // adc interface - input adc_clk; - input adc_rst; - output adc_enable; - output adc_iqcor_enb; - output adc_dcfilt_enb; - output adc_dfmt_se; - output adc_dfmt_type; - output adc_dfmt_enable; - output [15:0] adc_dcfilt_offset; - output [15:0] adc_dcfilt_coeff; - output [15:0] adc_iqcor_coeff_1; - output [15:0] adc_iqcor_coeff_2; - output [ 3:0] adc_pnseq_sel; - output [ 3:0] adc_data_sel; - input adc_pn_err; - input adc_pn_oos; - input adc_or; - output up_adc_pn_err; - output up_adc_pn_oos; - output up_adc_or; + input adc_clk, + input adc_rst, + output adc_enable, + output adc_iqcor_enb, + output adc_dcfilt_enb, + output adc_dfmt_se, + output adc_dfmt_type, + output adc_dfmt_enable, + output [15:0] adc_dcfilt_offset, + output [15:0] adc_dcfilt_coeff, + output [15:0] adc_iqcor_coeff_1, + output [15:0] adc_iqcor_coeff_2, + output [ 3:0] adc_pnseq_sel, + output [ 3:0] adc_data_sel, + input adc_pn_err, + input adc_pn_oos, + input adc_or, + output up_adc_pn_err, + output up_adc_pn_oos, + output up_adc_or, // user controls - output up_usr_datatype_be; - output up_usr_datatype_signed; - output [ 7:0] up_usr_datatype_shift; - output [ 7:0] up_usr_datatype_total_bits; - output [ 7:0] up_usr_datatype_bits; - output [15:0] up_usr_decimation_m; - output [15:0] up_usr_decimation_n; - input adc_usr_datatype_be; - input adc_usr_datatype_signed; - input [ 7:0] adc_usr_datatype_shift; - input [ 7:0] adc_usr_datatype_total_bits; - input [ 7:0] adc_usr_datatype_bits; - input [15:0] adc_usr_decimation_m; - input [15:0] adc_usr_decimation_n; + output up_usr_datatype_be, + output up_usr_datatype_signed, + output [ 7:0] up_usr_datatype_shift, + output [ 7:0] up_usr_datatype_total_bits, + output [ 7:0] up_usr_datatype_bits, + output [15:0] up_usr_decimation_m, + output [15:0] up_usr_decimation_n, + input adc_usr_datatype_be, + input adc_usr_datatype_signed, + input [ 7:0] adc_usr_datatype_shift, + input [ 7:0] adc_usr_datatype_total_bits, + input [ 7:0] adc_usr_datatype_bits, + input [15:0] adc_usr_decimation_m, + input [15:0] adc_usr_decimation_n, // bus interface - input up_rstn; - input up_clk; - input up_wreq; - input [13:0] up_waddr; - input [31:0] up_wdata; - output up_wack; - input up_rreq; - input [13:0] up_raddr; - output [31:0] up_rdata; - output up_rack; + input up_rstn, + input up_clk, + input up_wreq, + input [13:0] up_waddr, + input [31:0] up_wdata, + output up_wack, + input up_rreq, + input [13:0] up_raddr, + output [31:0] up_rdata, + output up_rack); // internal registers - reg up_wack = 'd0; + reg up_wack_int = 'd0; reg up_adc_lb_enb = 'd0; reg up_adc_pn_sel = 'd0; reg up_adc_iqcor_enb = 'd0; @@ -163,24 +113,24 @@ module up_adc_channel ( reg up_adc_dfmt_enable = 'd0; reg up_adc_pn_type = 'd0; reg up_adc_enable = 'd0; - reg up_adc_pn_err = 'd0; - reg up_adc_pn_oos = 'd0; - reg up_adc_or = 'd0; + reg up_adc_pn_err_int = 'd0; + reg up_adc_pn_oos_int = 'd0; + reg up_adc_or_int = 'd0; reg [15:0] up_adc_dcfilt_offset = 'd0; reg [15:0] up_adc_dcfilt_coeff = 'd0; reg [15:0] up_adc_iqcor_coeff_1 = 'd0; reg [15:0] up_adc_iqcor_coeff_2 = 'd0; reg [ 3:0] up_adc_pnseq_sel = 'd0; reg [ 3:0] up_adc_data_sel = 'd0; - reg up_usr_datatype_be = 'd0; - reg up_usr_datatype_signed = 'd0; - reg [ 7:0] up_usr_datatype_shift = 'd0; - reg [ 7:0] up_usr_datatype_total_bits = 'd0; - reg [ 7:0] up_usr_datatype_bits = 'd0; - reg [15:0] up_usr_decimation_m = 'd0; - reg [15:0] up_usr_decimation_n = 'd0; - reg up_rack = 'd0; - reg [31:0] up_rdata = 'd0; + reg up_usr_datatype_be_int = 'd0; + reg up_usr_datatype_signed_int = 'd0; + reg [ 7:0] up_usr_datatype_shift_int = 'd0; + reg [ 7:0] up_usr_datatype_total_bits_int = 'd0; + reg [ 7:0] up_usr_datatype_bits_int = 'd0; + reg [15:0] up_usr_decimation_m_int = 'd0; + reg [15:0] up_usr_decimation_n_int = 'd0; + reg up_rack_int = 'd0; + reg [31:0] up_rdata_int = 'd0; reg [15:0] up_adc_iqcor_coeff_tc_1 = 'd0; reg [15:0] up_adc_iqcor_coeff_tc_2 = 'd0; reg [ 3:0] up_adc_pnseq_sel_m = 'd0; @@ -209,121 +159,253 @@ module up_adc_channel ( end endfunction + // up control/status + + assign up_adc_pn_err = up_adc_pn_err_int; + assign up_adc_pn_oos = up_adc_pn_oos_int; + assign up_adc_or = up_adc_or_int; + assign up_usr_datatype_be = up_usr_datatype_be_int; + assign up_usr_datatype_signed = up_usr_datatype_signed_int; + assign up_usr_datatype_shift = up_usr_datatype_shift_int; + assign up_usr_datatype_total_bits = up_usr_datatype_total_bits_int; + assign up_usr_datatype_bits = up_usr_datatype_bits_int; + assign up_usr_decimation_m = up_usr_decimation_m_int; + assign up_usr_decimation_n = up_usr_decimation_n_int; + // decode block select - assign up_wreq_s = ((up_waddr[13:8] == 6'h01) && (up_waddr[7:4] == ADC_CHANNEL_ID)) ? up_wreq : 1'b0; - assign up_rreq_s = ((up_raddr[13:8] == 6'h01) && (up_raddr[7:4] == ADC_CHANNEL_ID)) ? up_rreq : 1'b0; + assign up_wreq_s = ((up_waddr[13:8] == COMMON_ID) && (up_waddr[7:4] == CHANNEL_ID)) ? up_wreq : 1'b0; + assign up_rreq_s = ((up_raddr[13:8] == COMMON_ID) && (up_raddr[7:4] == CHANNEL_ID)) ? up_rreq : 1'b0; // processor write interface + assign up_wack = up_wack_int; + always @(negedge up_rstn or posedge up_clk) begin if (up_rstn == 0) begin - up_wack <= 'd0; + up_wack_int <= 'd0; up_adc_lb_enb <= 'd0; up_adc_pn_sel <= 'd0; - up_adc_iqcor_enb <= 'd0; - up_adc_dcfilt_enb <= 'd0; - up_adc_dfmt_se <= 'd0; - up_adc_dfmt_type <= 'd0; - up_adc_dfmt_enable <= 'd0; - up_adc_pn_type <= 'd0; - up_adc_enable <= 'd0; - up_adc_pn_err <= 'd0; - up_adc_pn_oos <= 'd0; - up_adc_or <= 'd0; - up_adc_dcfilt_offset <= 'd0; - up_adc_dcfilt_coeff <= 'd0; - up_adc_iqcor_coeff_1 <= 'd0; - up_adc_iqcor_coeff_2 <= 'd0; - up_adc_pnseq_sel <= 'd0; - up_adc_data_sel <= 'd0; - up_usr_datatype_be <= 'd0; - up_usr_datatype_signed <= 'd0; - up_usr_datatype_shift <= 'd0; - up_usr_datatype_total_bits <= 'd0; - up_usr_datatype_bits <= 'd0; - up_usr_decimation_m <= 'd0; - up_usr_decimation_n <= 'd0; end else begin - up_wack <= up_wreq_s; + up_wack_int <= up_wreq_s; if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h0)) begin up_adc_lb_enb <= up_wdata[11]; up_adc_pn_sel <= up_wdata[10]; - up_adc_iqcor_enb <= up_wdata[9]; - up_adc_dcfilt_enb <= up_wdata[8]; - up_adc_dfmt_se <= up_wdata[6]; - up_adc_dfmt_type <= up_wdata[5]; - up_adc_dfmt_enable <= up_wdata[4]; - up_adc_pn_type <= up_wdata[1]; - up_adc_enable <= up_wdata[0]; - end - if (up_adc_pn_err_s == 1'b1) begin - up_adc_pn_err <= 1'b1; - end else if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h1)) begin - up_adc_pn_err <= up_adc_pn_err & ~up_wdata[2]; - end - if (up_adc_pn_oos_s == 1'b1) begin - up_adc_pn_oos <= 1'b1; - end else if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h1)) begin - up_adc_pn_oos <= up_adc_pn_oos & ~up_wdata[1]; - end - if (up_adc_or_s == 1'b1) begin - up_adc_or <= 1'b1; - end else if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h1)) begin - up_adc_or <= up_adc_or & ~up_wdata[0]; - end - if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h4)) begin - up_adc_dcfilt_offset <= up_wdata[31:16]; - up_adc_dcfilt_coeff <= up_wdata[15:0]; - end - if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h5)) begin - up_adc_iqcor_coeff_1 <= up_wdata[31:16]; - up_adc_iqcor_coeff_2 <= up_wdata[15:0]; - end - if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h6)) begin - up_adc_pnseq_sel <= up_wdata[19:16]; - up_adc_data_sel <= up_wdata[3:0]; - end - if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h8)) begin - up_usr_datatype_be <= up_wdata[25]; - up_usr_datatype_signed <= up_wdata[24]; - up_usr_datatype_shift <= up_wdata[23:16]; - up_usr_datatype_total_bits <= up_wdata[15:8]; - up_usr_datatype_bits <= up_wdata[7:0]; - end - if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h9)) begin - up_usr_decimation_m <= up_wdata[31:16]; - up_usr_decimation_n <= up_wdata[15:0]; end end end - // processor read interface + generate + if (IQCORRECTION_DISABLE == 1) begin + always @(posedge up_clk) begin + up_adc_iqcor_enb <= 'd0; + end + end else begin + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_adc_iqcor_enb <= 'd0; + end else begin + if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h0)) begin + up_adc_iqcor_enb <= up_wdata[9]; + end + end + end + end + endgenerate + + generate + if (DCFILTER_DISABLE == 1) begin + always @(posedge up_clk) begin + up_adc_dcfilt_enb <= 'd0; + end + end else begin + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_adc_dcfilt_enb <= 'd0; + end else begin + if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h0)) begin + up_adc_dcfilt_enb <= up_wdata[8]; + end + end + end + end + endgenerate + + generate + if (DATAFORMAT_DISABLE == 1) begin + always @(posedge up_clk) begin + up_adc_dfmt_se <= 'd0; + up_adc_dfmt_type <= 'd0; + up_adc_dfmt_enable <= 'd0; + end + end else begin + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_adc_dfmt_se <= 'd0; + up_adc_dfmt_type <= 'd0; + up_adc_dfmt_enable <= 'd0; + end else begin + if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h0)) begin + up_adc_dfmt_se <= up_wdata[6]; + up_adc_dfmt_type <= up_wdata[5]; + up_adc_dfmt_enable <= up_wdata[4]; + end + end + end + end + endgenerate always @(negedge up_rstn or posedge up_clk) begin if (up_rstn == 0) begin - up_rack <= 'd0; - up_rdata <= 'd0; + up_adc_pn_type <= 'd0; + up_adc_enable <= 'd0; + up_adc_pn_err_int <= 'd0; + up_adc_pn_oos_int <= 'd0; + up_adc_or_int <= 'd0; end else begin - up_rack <= up_rreq_s; + if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h0)) begin + up_adc_pn_type <= up_wdata[1]; + up_adc_enable <= up_wdata[0]; + end + if (up_adc_pn_err_s == 1'b1) begin + up_adc_pn_err_int <= 1'b1; + end else if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h1)) begin + up_adc_pn_err_int <= up_adc_pn_err_int & ~up_wdata[2]; + end + if (up_adc_pn_oos_s == 1'b1) begin + up_adc_pn_oos_int <= 1'b1; + end else if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h1)) begin + up_adc_pn_oos_int <= up_adc_pn_oos_int & ~up_wdata[1]; + end + if (up_adc_or_s == 1'b1) begin + up_adc_or_int <= 1'b1; + end else if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h1)) begin + up_adc_or_int <= up_adc_or_int & ~up_wdata[0]; + end + end + end + + generate + if (DCFILTER_DISABLE == 1) begin + always @(posedge up_clk) begin + up_adc_dcfilt_offset <= 'd0; + up_adc_dcfilt_coeff <= 'd0; + end + end else begin + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_adc_dcfilt_offset <= 'd0; + up_adc_dcfilt_coeff <= 'd0; + end else begin + if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h4)) begin + up_adc_dcfilt_offset <= up_wdata[31:16]; + up_adc_dcfilt_coeff <= up_wdata[15:0]; + end + end + end + end + endgenerate + + generate + if (IQCORRECTION_DISABLE == 1) begin + always @(posedge up_clk) begin + up_adc_iqcor_coeff_1 <= 'd0; + up_adc_iqcor_coeff_2 <= 'd0; + end + end else begin + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_adc_iqcor_coeff_1 <= 'd0; + up_adc_iqcor_coeff_2 <= 'd0; + end else begin + if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h5)) begin + up_adc_iqcor_coeff_1 <= up_wdata[31:16]; + up_adc_iqcor_coeff_2 <= up_wdata[15:0]; + end + end + end + end + endgenerate + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_adc_pnseq_sel <= 'd0; + up_adc_data_sel <= 'd0; + end else begin + if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h6)) begin + up_adc_pnseq_sel <= up_wdata[19:16]; + up_adc_data_sel <= up_wdata[3:0]; + end + end + end + + generate + if (USERPORTS_DISABLE == 1) begin + always @(posedge up_clk) begin + up_usr_datatype_be_int <= 'd0; + up_usr_datatype_signed_int <= 'd0; + up_usr_datatype_shift_int <= 'd0; + up_usr_datatype_total_bits_int <= 'd0; + up_usr_datatype_bits_int <= 'd0; + up_usr_decimation_m_int <= 'd0; + up_usr_decimation_n_int <= 'd0; + end + end else begin + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_usr_datatype_be_int <= 'd0; + up_usr_datatype_signed_int <= 'd0; + up_usr_datatype_shift_int <= 'd0; + up_usr_datatype_total_bits_int <= 'd0; + up_usr_datatype_bits_int <= 'd0; + up_usr_decimation_m_int <= 'd0; + up_usr_decimation_n_int <= 'd0; + end else begin + if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h8)) begin + up_usr_datatype_be_int <= up_wdata[25]; + up_usr_datatype_signed_int <= up_wdata[24]; + up_usr_datatype_shift_int <= up_wdata[23:16]; + up_usr_datatype_total_bits_int <= up_wdata[15:8]; + up_usr_datatype_bits_int <= up_wdata[7:0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h9)) begin + up_usr_decimation_m_int <= up_wdata[31:16]; + up_usr_decimation_n_int <= up_wdata[15:0]; + end + end + end + end + endgenerate + + // processor read interface + + assign up_rack = up_rack_int; + assign up_rdata = up_rdata_int; + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_rack_int <= 'd0; + up_rdata_int <= 'd0; + end else begin + up_rack_int <= up_rreq_s; if (up_rreq_s == 1'b1) begin case (up_raddr[3:0]) - 4'h0: up_rdata <= {20'd0, up_adc_lb_enb, up_adc_pn_sel, - up_adc_iqcor_enb, up_adc_dcfilt_enb, - 1'd0, up_adc_dfmt_se, up_adc_dfmt_type, up_adc_dfmt_enable, - 2'd0, up_adc_pn_type, up_adc_enable}; - 4'h1: up_rdata <= {29'd0, up_adc_pn_err, up_adc_pn_oos, up_adc_or}; - 4'h4: up_rdata <= {up_adc_dcfilt_offset, up_adc_dcfilt_coeff}; - 4'h5: up_rdata <= {up_adc_iqcor_coeff_1, up_adc_iqcor_coeff_2}; - 4'h6: up_rdata <= {12'd0, up_adc_pnseq_sel, 12'd0, up_adc_data_sel}; - 4'h8: up_rdata <= {6'd0, adc_usr_datatype_be, adc_usr_datatype_signed, - adc_usr_datatype_shift, adc_usr_datatype_total_bits, - adc_usr_datatype_bits}; - 4'h9: up_rdata <= {adc_usr_decimation_m, adc_usr_decimation_n}; - default: up_rdata <= 0; + 4'h0: up_rdata_int <= { 20'd0, up_adc_lb_enb, up_adc_pn_sel, + up_adc_iqcor_enb, up_adc_dcfilt_enb, + 1'd0, up_adc_dfmt_se, up_adc_dfmt_type, up_adc_dfmt_enable, + 2'd0, up_adc_pn_type, up_adc_enable}; + 4'h1: up_rdata_int <= { 29'd0, up_adc_pn_err_int, up_adc_pn_oos_int, up_adc_or_int}; + 4'h4: up_rdata_int <= { up_adc_dcfilt_offset, up_adc_dcfilt_coeff}; + 4'h5: up_rdata_int <= { up_adc_iqcor_coeff_1, up_adc_iqcor_coeff_2}; + 4'h6: up_rdata_int <= { 12'd0, up_adc_pnseq_sel, 12'd0, up_adc_data_sel}; + 4'h8: up_rdata_int <= { 6'd0, adc_usr_datatype_be, adc_usr_datatype_signed, + adc_usr_datatype_shift, adc_usr_datatype_total_bits, + adc_usr_datatype_bits}; + 4'h9: up_rdata_int <= { adc_usr_decimation_m, adc_usr_decimation_n}; + default: up_rdata_int <= 0; endcase end else begin - up_rdata <= 32'd0; + up_rdata_int <= 32'd0; end end end diff --git a/library/common/up_adc_common.v b/library/common/up_adc_common.v index 29ccd571f..baefdb905 100644 --- a/library/common/up_adc_common.v +++ b/library/common/up_adc_common.v @@ -1,9 +1,9 @@ // *************************************************************************** // *************************************************************************** // Copyright 2011(c) Analog Devices, Inc. -// +// // All rights reserved. -// +// // Redistribution and use in source and binary forms, with or without modification, // are permitted provided that the following conditions are met: // - Redistributions of source code must retain the above copyright @@ -21,165 +21,117 @@ // patent holders to use this software. // - Use of the software either in source or binary form, must be run // on or directly connected to an Analog Devices Inc. component. -// +// // THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, // INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A // PARTICULAR PURPOSE ARE DISCLAIMED. // // IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, // EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY -// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR // BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // *************************************************************************** // *************************************************************************** `timescale 1ns/100ps -module up_adc_common ( - - // clock reset - - mmcm_rst, - - // adc interface - - adc_clk, - adc_rst, - adc_r1_mode, - adc_ddr_edgesel, - adc_pin_mode, - adc_status, - adc_sync_status, - adc_status_ovf, - adc_status_unf, - adc_clk_ratio, - adc_start_code, - adc_sync, - - // channel interface - - up_status_pn_err, - up_status_pn_oos, - up_status_or, - - // drp interface - - up_drp_sel, - up_drp_wr, - up_drp_addr, - up_drp_wdata, - up_drp_rdata, - up_drp_ready, - up_drp_locked, - - // user channel control - - up_usr_chanmax, - adc_usr_chanmax, - up_adc_gpio_in, - up_adc_gpio_out, - - // bus interface - - up_rstn, - up_clk, - up_wreq, - up_waddr, - up_wdata, - up_wack, - up_rreq, - up_raddr, - up_rdata, - up_rack); +module up_adc_common #( // parameters - localparam PCORE_VERSION = 32'h00090062; - parameter ID = 0; + parameter ID = 0, + parameter CONFIG = 0, + parameter COMMON_ID = 6'h00, + parameter DRP_DISABLE = 6'h00, + parameter USERPORTS_DISABLE = 0) ( // clock reset - output mmcm_rst; + output mmcm_rst, // adc interface - input adc_clk; - output adc_rst; - output adc_r1_mode; - output adc_ddr_edgesel; - output adc_pin_mode; - input adc_status; - input adc_sync_status; - input adc_status_ovf; - input adc_status_unf; - input [31:0] adc_clk_ratio; - output [31:0] adc_start_code; - output adc_sync; + input adc_clk, + output adc_rst, + output adc_r1_mode, + output adc_ddr_edgesel, + output adc_pin_mode, + input adc_status, + input adc_sync_status, + input adc_status_ovf, + input adc_status_unf, + input [31:0] adc_clk_ratio, + output [31:0] adc_start_code, + output adc_sync, // channel interface - input up_status_pn_err; - input up_status_pn_oos; - input up_status_or; + input up_status_pn_err, + input up_status_pn_oos, + input up_status_or, // drp interface - output up_drp_sel; - output up_drp_wr; - output [11:0] up_drp_addr; - output [15:0] up_drp_wdata; - input [15:0] up_drp_rdata; - input up_drp_ready; - input up_drp_locked; + output up_drp_sel, + output up_drp_wr, + output [11:0] up_drp_addr, + output [31:0] up_drp_wdata, + input [31:0] up_drp_rdata, + input up_drp_ready, + input up_drp_locked, // user channel control - output [ 7:0] up_usr_chanmax; - input [ 7:0] adc_usr_chanmax; - input [31:0] up_adc_gpio_in; - output [31:0] up_adc_gpio_out; + output [ 7:0] up_usr_chanmax, + input [ 7:0] adc_usr_chanmax, + input [31:0] up_adc_gpio_in, + output [31:0] up_adc_gpio_out, // bus interface - input up_rstn; - input up_clk; - input up_wreq; - input [13:0] up_waddr; - input [31:0] up_wdata; - output up_wack; - input up_rreq; - input [13:0] up_raddr; - output [31:0] up_rdata; - output up_rack; + input up_rstn, + input up_clk, + input up_wreq, + input [13:0] up_waddr, + input [31:0] up_wdata, + output up_wack, + input up_rreq, + input [13:0] up_raddr, + output [31:0] up_rdata, + output up_rack); + + // parameters + + localparam VERSION = 32'h000a0062; // internal registers - - reg up_core_preset = 'd0; - reg up_mmcm_preset = 'd0; - reg up_wack = 'd0; + + reg up_core_preset = 'd1; + reg up_mmcm_preset = 'd1; + reg up_wack_int = 'd0; reg [31:0] up_scratch = 'd0; reg up_mmcm_resetn = 'd0; reg up_resetn = 'd0; + reg up_adc_sync = 'd0; reg up_adc_r1_mode = 'd0; reg up_adc_ddr_edgesel = 'd0; reg up_adc_pin_mode = 'd0; - reg up_drp_sel = 'd0; - reg up_drp_wr = 'd0; + reg up_drp_sel_int = 'd0; + reg up_drp_wr_int = 'd0; reg up_drp_status = 'd0; reg up_drp_rwn = 'd0; - reg [11:0] up_drp_addr = 'd0; - reg [15:0] up_drp_wdata = 'd0; - reg [15:0] up_drp_rdata_hold = 'd0; + reg [11:0] up_drp_addr_int = 'd0; + reg [31:0] up_drp_wdata_int = 'd0; + reg [31:0] up_drp_rdata_hold = 'd0; reg up_status_ovf = 'd0; reg up_status_unf = 'd0; - reg [ 7:0] up_usr_chanmax = 'd0; - reg [31:0] up_adc_gpio_out = 'd0; + reg [ 7:0] up_usr_chanmax_int = 'd0; reg [31:0] up_adc_start_code = 'd0; - reg up_adc_sync = 'd0; - reg up_rack = 'd0; - reg [31:0] up_rdata = 'd0; + reg [31:0] up_adc_gpio_out_int = 'd0; + reg up_rack_int = 'd0; + reg [31:0] up_rdata_int = 'd0; // internal signals @@ -189,43 +141,34 @@ module up_adc_common ( wire up_sync_status_s; wire up_status_ovf_s; wire up_status_unf_s; - wire up_cntrl_xfer_done; + wire up_cntrl_xfer_done_s; wire [31:0] up_adc_clk_count_s; // decode block select - assign up_wreq_s = (up_waddr[13:8] == 6'h00) ? up_wreq : 1'b0; - assign up_rreq_s = (up_raddr[13:8] == 6'h00) ? up_rreq : 1'b0; + assign up_wreq_s = (up_waddr[13:8] == COMMON_ID) ? up_wreq : 1'b0; + assign up_rreq_s = (up_raddr[13:8] == COMMON_ID) ? up_rreq : 1'b0; // processor write interface + assign up_wack = up_wack_int; + always @(negedge up_rstn or posedge up_clk) begin if (up_rstn == 0) begin up_core_preset <= 1'd1; up_mmcm_preset <= 1'd1; - up_wack <= 'd0; + up_wack_int <= 'd0; up_scratch <= 'd0; up_mmcm_resetn <= 'd0; up_resetn <= 'd0; + up_adc_sync <= 'd0; up_adc_r1_mode <= 'd0; up_adc_ddr_edgesel <= 'd0; up_adc_pin_mode <= 'd0; - up_drp_sel <= 'd0; - up_drp_wr <= 'd0; - up_drp_status <= 'd0; - up_drp_rwn <= 'd0; - up_drp_addr <= 'd0; - up_drp_wdata <= 'd0; - up_drp_rdata_hold <= 'd0; - up_status_ovf <= 'd0; - up_status_unf <= 'd0; - up_usr_chanmax <= 'd0; - up_adc_gpio_out <= 'd0; - up_adc_start_code <= 'd0; end else begin up_core_preset <= ~up_resetn; up_mmcm_preset <= ~up_mmcm_resetn; - up_wack <= up_wreq_s; + up_wack_int <= up_wreq_s; if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h02)) begin up_scratch <= up_wdata; end @@ -234,7 +177,7 @@ module up_adc_common ( up_resetn <= up_wdata[0]; end if (up_adc_sync == 1'b1) begin - if (up_cntrl_xfer_done == 1'b1) begin + if (up_cntrl_xfer_done_s == 1'b1) begin up_adc_sync <= 1'b0; end end else if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h11)) begin @@ -245,12 +188,42 @@ module up_adc_common ( up_adc_ddr_edgesel <= up_wdata[1]; up_adc_pin_mode <= up_wdata[0]; end + end + end + + assign up_drp_sel = up_drp_sel_int; + assign up_drp_wr = up_drp_wr_int; + assign up_drp_addr = up_drp_addr_int; + assign up_drp_wdata = up_drp_wdata_int; + + generate + if (DRP_DISABLE == 1) begin + always @(posedge up_clk) begin + up_drp_sel_int <= 'd0; + up_drp_wr_int <= 'd0; + up_drp_status <= 'd0; + up_drp_rwn <= 'd0; + up_drp_addr_int <= 'd0; + up_drp_wdata_int <= 'd0; + up_drp_rdata_hold <= 'd0; + end + end else begin + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_drp_sel_int <= 'd0; + up_drp_wr_int <= 'd0; + up_drp_status <= 'd0; + up_drp_rwn <= 'd0; + up_drp_addr_int <= 'd0; + up_drp_wdata_int <= 'd0; + up_drp_rdata_hold <= 'd0; + end else begin if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h1c)) begin - up_drp_sel <= 1'b1; - up_drp_wr <= ~up_wdata[28]; + up_drp_sel_int <= 1'b1; + up_drp_wr_int <= ~up_wdata[28]; end else begin - up_drp_sel <= 1'b0; - up_drp_wr <= 1'b0; + up_drp_sel_int <= 1'b0; + up_drp_wr_int <= 1'b0; end if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h1c)) begin up_drp_status <= 1'b1; @@ -259,12 +232,24 @@ module up_adc_common ( end if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h1c)) begin up_drp_rwn <= up_wdata[28]; - up_drp_addr <= up_wdata[27:16]; - up_drp_wdata <= up_wdata[15:0]; + up_drp_addr_int <= up_wdata[27:16]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h1e)) begin + up_drp_wdata_int <= up_wdata; end if (up_drp_ready == 1'b1) begin up_drp_rdata_hold <= up_drp_rdata; end + end + end + end + endgenerate + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_status_ovf <= 'd0; + up_status_unf <= 'd0; + end else begin if (up_status_ovf_s == 1'b1) begin up_status_ovf <= 1'b1; end else if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h22)) begin @@ -275,49 +260,82 @@ module up_adc_common ( end else if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h22)) begin up_status_unf <= up_status_unf & ~up_wdata[1]; end + end + end + + assign up_usr_chanmax = up_usr_chanmax_int; + + generate + if (USERPORTS_DISABLE == 1) begin + always @(posedge up_clk) begin + up_usr_chanmax_int <= 'd0; + end + end else begin + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_usr_chanmax_int <= 'd0; + end else begin if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h28)) begin - up_usr_chanmax <= up_wdata[7:0]; + up_usr_chanmax_int <= up_wdata[7:0]; end + end + end + end + endgenerate + + assign up_adc_gpio_out = up_adc_gpio_out_int; + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_adc_start_code <= 'd0; + up_adc_gpio_out_int <= 'd0; + end else begin if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h29)) begin up_adc_start_code <= up_wdata[31:0]; end if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h2f)) begin - up_adc_gpio_out <= up_wdata; + up_adc_gpio_out_int <= up_wdata; end end end // processor read interface + assign up_rack = up_rack_int; + assign up_rdata = up_rdata_int; + always @(negedge up_rstn or posedge up_clk) begin if (up_rstn == 0) begin - up_rack <= 'd0; - up_rdata <= 'd0; + up_rack_int <= 'd0; + up_rdata_int <= 'd0; end else begin - up_rack <= up_rreq_s; + up_rack_int <= up_rreq_s; if (up_rreq_s == 1'b1) begin case (up_raddr[7:0]) - 8'h00: up_rdata <= PCORE_VERSION; - 8'h01: up_rdata <= ID; - 8'h02: up_rdata <= up_scratch; - 8'h10: up_rdata <= {30'd0, up_mmcm_resetn, up_resetn}; - 8'h11: up_rdata <= {28'd0, up_adc_sync, up_adc_r1_mode, up_adc_ddr_edgesel, up_adc_pin_mode}; - 8'h15: up_rdata <= up_adc_clk_count_s; - 8'h16: up_rdata <= adc_clk_ratio; - 8'h17: up_rdata <= {28'd0, up_status_pn_err, up_status_pn_oos, up_status_or, up_status_s}; - 8'h1a: up_rdata <= {31'd0, up_sync_status_s}; - 8'h1c: up_rdata <= {3'd0, up_drp_rwn, up_drp_addr, up_drp_wdata}; - 8'h1d: up_rdata <= {14'd0, up_drp_locked, up_drp_status, up_drp_rdata_hold}; - 8'h22: up_rdata <= {29'd0, up_status_ovf, up_status_unf, 1'b0}; - 8'h23: up_rdata <= 32'd8; - 8'h28: up_rdata <= {24'd0, adc_usr_chanmax}; - 8'h29: up_rdata <= up_adc_start_code; - 8'h2e: up_rdata <= up_adc_gpio_in; - 8'h2f: up_rdata <= up_adc_gpio_out; - default: up_rdata <= 0; + 8'h00: up_rdata_int <= VERSION; + 8'h01: up_rdata_int <= ID; + 8'h02: up_rdata_int <= up_scratch; + 8'h03: up_rdata_int <= CONFIG; + 8'h10: up_rdata_int <= {30'd0, up_mmcm_resetn, up_resetn}; + 8'h11: up_rdata_int <= {28'd0, up_adc_sync, up_adc_r1_mode, up_adc_ddr_edgesel, up_adc_pin_mode}; + 8'h15: up_rdata_int <= up_adc_clk_count_s; + 8'h16: up_rdata_int <= adc_clk_ratio; + 8'h17: up_rdata_int <= {28'd0, up_status_pn_err, up_status_pn_oos, up_status_or, up_status_s}; + 8'h1a: up_rdata_int <= {31'd0, up_sync_status_s}; + 8'h1c: up_rdata_int <= {3'd0, up_drp_rwn, up_drp_addr_int, 16'b0}; + 8'h1d: up_rdata_int <= {14'd0, up_drp_locked, up_drp_status, 16'b0}; + 8'h1e: up_rdata_int <= up_drp_wdata_int; + 8'h1f: up_rdata_int <= up_drp_rdata_hold; + 8'h22: up_rdata_int <= {29'd0, up_status_ovf, up_status_unf, 1'b0}; + 8'h23: up_rdata_int <= 32'd8; + 8'h28: up_rdata_int <= {24'd0, adc_usr_chanmax}; + 8'h29: up_rdata_int <= up_adc_start_code; + 8'h2e: up_rdata_int <= up_adc_gpio_in; + 8'h2f: up_rdata_int <= up_adc_gpio_out_int; + default: up_rdata_int <= 0; endcase end else begin - up_rdata <= 32'd0; + up_rdata_int <= 32'd0; end end end @@ -337,7 +355,7 @@ module up_adc_common ( up_adc_r1_mode, up_adc_ddr_edgesel, up_adc_pin_mode}), - .up_xfer_done (up_cntrl_xfer_done), + .up_xfer_done (up_cntrl_xfer_done_s), .d_rst (adc_rst), .d_clk (adc_clk), .d_data_cntrl ({ adc_sync, diff --git a/library/common/up_axis_dma_rx.v b/library/common/up_axis_dma_rx.v deleted file mode 100644 index 71494cf80..000000000 --- a/library/common/up_axis_dma_rx.v +++ /dev/null @@ -1,249 +0,0 @@ -// *************************************************************************** -// *************************************************************************** -// Copyright 2011(c) Analog Devices, Inc. -// -// All rights reserved. -// -// Redistribution and use in source and binary forms, with or without modification, -// are permitted provided that the following conditions are met: -// - Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// - Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in -// the documentation and/or other materials provided with the -// distribution. -// - Neither the name of Analog Devices, Inc. nor the names of its -// contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// - The use of this software may or may not infringe the patent rights -// of one or more patent holders. This license does not release you -// from the requirement that you obtain separate licenses from these -// patent holders to use this software. -// - Use of the software either in source or binary form, must be run -// on or directly connected to an Analog Devices Inc. component. -// -// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, -// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A -// PARTICULAR PURPOSE ARE DISCLAIMED. -// -// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY -// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF -// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// *************************************************************************** -// *************************************************************************** -// *************************************************************************** -// *************************************************************************** - -`timescale 1ns/100ps - -module up_axis_dma_rx ( - - // adc interface - - adc_clk, - adc_rst, - - // dma interface - - dma_clk, - dma_rst, - dma_start, - dma_stream, - dma_count, - dma_ovf, - dma_unf, - dma_status, - dma_bw, - - // bus interface - - up_rstn, - up_clk, - up_wreq, - up_waddr, - up_wdata, - up_wack, - up_rreq, - up_raddr, - up_rdata, - up_rack); - - // parameters - - localparam PCORE_VERSION = 32'h00050063; - parameter ID = 0; - - // adc interface - - input adc_clk; - output adc_rst; - - // dma interface - - input dma_clk; - output dma_rst; - output dma_start; - output dma_stream; - output [31:0] dma_count; - input dma_ovf; - input dma_unf; - input dma_status; - input [31:0] dma_bw; - - // bus interface - - input up_rstn; - input up_clk; - input up_wreq; - input [13:0] up_waddr; - input [31:0] up_wdata; - output up_wack; - input up_rreq; - input [13:0] up_raddr; - output [31:0] up_rdata; - output up_rack; - - // internal registers - - reg up_preset = 'd0; - reg up_wack = 'd0; - reg [31:0] up_scratch = 'd0; - reg up_resetn = 'd0; - reg up_dma_stream = 'd0; - reg up_dma_start = 'd0; - reg [31:0] up_dma_count = 'd0; - reg up_dma_ovf = 'd0; - reg up_dma_unf = 'd0; - reg up_rack = 'd0; - reg [31:0] up_rdata = 'd0; - reg dma_start_d = 'd0; - reg dma_start_2d = 'd0; - reg dma_start = 'd0; - - // internal signals - - wire up_wreq_s; - wire up_rreq_s; - wire up_dma_ovf_s; - wire up_dma_unf_s; - wire up_dma_status_s; - - // decode block select - - assign up_wreq_s = (up_waddr[13:8] == 6'h00) ? up_wreq : 1'b0; - assign up_rreq_s = (up_waddr[13:8] == 6'h00) ? up_rreq : 1'b0; - - // processor write interface - - always @(negedge up_rstn or posedge up_clk) begin - if (up_rstn == 0) begin - up_preset <= 1'd1; - up_wack <= 'd0; - up_scratch <= 'd0; - up_resetn <= 'd0; - up_dma_stream <= 'd0; - up_dma_start <= 'd0; - up_dma_count <= 'd0; - up_dma_ovf <= 'd0; - up_dma_unf <= 'd0; - end else begin - up_preset <= 1'd0; - up_wack <= up_wreq_s; - if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h02)) begin - up_scratch <= up_wdata; - end - if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h10)) begin - up_resetn <= up_wdata[0]; - end - if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h20)) begin - up_dma_stream <= up_wdata[1]; - up_dma_start <= up_wdata[0]; - end - if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h21)) begin - up_dma_count <= up_wdata; - end - if (up_dma_ovf_s == 1'b1) begin - up_dma_ovf <= 1'b1; - end else if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h22)) begin - up_dma_ovf <= up_dma_ovf & ~up_wdata[2]; - end - if (up_dma_unf_s == 1'b1) begin - up_dma_unf <= 1'b1; - end else if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h22)) begin - up_dma_unf <= up_dma_unf & ~up_wdata[1]; - end - end - end - - // processor read interface - - always @(negedge up_rstn or posedge up_clk) begin - if (up_rstn == 0) begin - up_rack <= 'd0; - up_rdata <= 'd0; - end else begin - up_rack <= up_rreq_s; - if (up_rreq_s == 1'b1) begin - case (up_raddr[7:0]) - 8'h00: up_rdata <= PCORE_VERSION; - 8'h01: up_rdata <= ID; - 8'h02: up_rdata <= up_scratch; - 8'h10: up_rdata <= {31'd0, up_resetn}; - 8'h20: up_rdata <= {30'd0, up_dma_stream, up_dma_start}; - 8'h21: up_rdata <= up_dma_count; - 8'h22: up_rdata <= {29'd0, up_dma_ovf, up_dma_unf, up_dma_status_s}; - 8'h23: up_rdata <= dma_bw; - default: up_rdata <= 0; - endcase - end else begin - up_rdata <= 32'd0; - end - end - end - - // resets - - ad_rst i_adc_rst_reg (.preset(up_preset), .clk(adc_clk), .rst(adc_rst)); - ad_rst i_dma_rst_reg (.preset(up_preset), .clk(dma_clk), .rst(dma_rst)); - - // dma control & status - - up_xfer_cntrl #(.DATA_WIDTH(34)) i_dma_xfer_cntrl ( - .up_rstn (up_rstn), - .up_clk (up_clk), - .up_data_cntrl ({ up_dma_start, - up_dma_stream, - up_dma_count}), - .d_rst (dma_rst), - .d_clk (dma_clk), - .d_data_cntrl ({ dma_start_s, - dma_stream, - dma_count})); - - up_xfer_status #(.DATA_WIDTH(3)) i_dma_xfer_status ( - .up_rstn (up_rstn), - .up_clk (up_clk), - .up_data_status ({up_dma_ovf_s, - up_dma_unf_s, - up_dma_status_s}), - .d_rst (dma_rst), - .d_clk (dma_clk), - .d_data_status ({ dma_ovf, - dma_unf, - dma_status})); - - // start needs to be a pulse - - always @(posedge dma_clk) begin - dma_start_d <= dma_start_s; - dma_start_2d <= dma_start_d; - dma_start <= dma_start_d & ~dma_start_2d; - end - -endmodule - -// *************************************************************************** -// *************************************************************************** diff --git a/library/common/up_axis_dma_tx.v b/library/common/up_axis_dma_tx.v deleted file mode 100644 index 454ed9f37..000000000 --- a/library/common/up_axis_dma_tx.v +++ /dev/null @@ -1,213 +0,0 @@ -// *************************************************************************** -// *************************************************************************** -// Copyright 2011(c) Analog Devices, Inc. -// -// All rights reserved. -// -// Redistribution and use in source and binary forms, with or without modification, -// are permitted provided that the following conditions are met: -// - Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// - Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in -// the documentation and/or other materials provided with the -// distribution. -// - Neither the name of Analog Devices, Inc. nor the names of its -// contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// - The use of this software may or may not infringe the patent rights -// of one or more patent holders. This license does not release you -// from the requirement that you obtain separate licenses from these -// patent holders to use this software. -// - Use of the software either in source or binary form, must be run -// on or directly connected to an Analog Devices Inc. component. -// -// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, -// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A -// PARTICULAR PURPOSE ARE DISCLAIMED. -// -// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY -// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF -// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// *************************************************************************** -// *************************************************************************** -// *************************************************************************** -// *************************************************************************** - -`timescale 1ns/100ps - -module up_axis_dma_tx ( - - // dac interface - - dac_clk, - dac_rst, - - // dma interface - - dma_clk, - dma_rst, - dma_frmcnt, - dma_ovf, - dma_unf, - - // bus interface - - up_rstn, - up_clk, - up_wreq, - up_waddr, - up_wdata, - up_wack, - up_rreq, - up_raddr, - up_rdata, - up_rack); - - // parameters - - localparam PCORE_VERSION = 32'h00050062; - parameter ID = 0; - - // dac interface - - input dac_clk; - output dac_rst; - - // dma interface - - input dma_clk; - output dma_rst; - output [31:0] dma_frmcnt; - input dma_ovf; - input dma_unf; - - // bus interface - - input up_rstn; - input up_clk; - input up_wreq; - input [13:0] up_waddr; - input [31:0] up_wdata; - output up_wack; - input up_rreq; - input [13:0] up_raddr; - output [31:0] up_rdata; - output up_rack; - - // internal registers - - reg up_preset = 'd0; - reg up_wack = 'd0; - reg [31:0] up_scratch = 'd0; - reg up_resetn = 'd0; - reg [31:0] up_dma_frmcnt = 'd0; - reg up_dma_ovf = 'd0; - reg up_dma_unf = 'd0; - reg up_rack = 'd0; - reg [31:0] up_rdata = 'd0; - - // internal signals - - wire up_wreq_s; - wire up_rreq_s; - wire up_dma_ovf_s; - wire up_dma_unf_s; - - // decode block select - - assign up_wreq_s = (up_waddr[13:8] == 6'h10) ? up_wreq : 1'b0; - assign up_rreq_s = (up_raddr[13:8] == 6'h10) ? up_rreq : 1'b0; - - // processor write interface - - always @(negedge up_rstn or posedge up_clk) begin - if (up_rstn == 0) begin - up_preset <= 1'd1; - up_wack <= 'd0; - up_scratch <= 'd0; - up_resetn <= 'd0; - up_dma_frmcnt <= 'd0; - up_dma_ovf <= 'd0; - up_dma_unf <= 'd0; - end else begin - up_preset <= 1'd0; - up_wack <= up_wreq_s; - if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h02)) begin - up_scratch <= up_wdata; - end - if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h10)) begin - up_resetn <= up_wdata[0]; - end - if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h21)) begin - up_dma_frmcnt <= up_wdata; - end - if (up_dma_ovf_s == 1'b1) begin - up_dma_ovf <= 1'b1; - end else if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h22)) begin - up_dma_ovf <= up_dma_ovf & ~up_wdata[1]; - end - if (up_dma_unf_s == 1'b1) begin - up_dma_unf <= 1'b1; - end else if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h22)) begin - up_dma_unf <= up_dma_unf & ~up_wdata[0]; - end - end - end - - // processor read interface - - always @(negedge up_rstn or posedge up_clk) begin - if (up_rstn == 0) begin - up_rack <= 'd0; - up_rdata <= 'd0; - end else begin - up_rack <= up_rreq_s; - if (up_rreq_s == 1'b1) begin - case (up_raddr[7:0]) - 8'h00: up_rdata <= PCORE_VERSION; - 8'h01: up_rdata <= ID; - 8'h02: up_rdata <= up_scratch; - 8'h10: up_rdata <= {31'd0, up_resetn}; - 8'h21: up_rdata <= up_dma_frmcnt; - 8'h22: up_rdata <= {30'd0, up_dma_ovf, up_dma_unf}; - default: up_rdata <= 0; - endcase - end else begin - up_rdata <= 32'd0; - end - end - end - - // resets - - ad_rst i_dac_rst_reg (.preset(up_preset), .clk(dac_clk), .rst(dac_rst)); - ad_rst i_dma_rst_reg (.preset(up_preset), .clk(dma_clk), .rst(dma_rst)); - - // dma control & status - - up_xfer_cntrl #(.DATA_WIDTH(32)) i_dma_xfer_cntrl ( - .up_rstn (up_rstn), - .up_clk (up_clk), - .up_data_cntrl ( up_dma_frmcnt), - .d_rst (dma_rst), - .d_clk (dma_clk), - .d_data_cntrl ( dma_frmcnt)); - - up_xfer_status #(.DATA_WIDTH(2)) i_dma_xfer_status ( - .up_rstn (up_rstn), - .up_clk (up_clk), - .up_data_status ({up_dma_ovf_s, - up_dma_unf_s}), - .d_rst (dma_rst), - .d_clk (dma_clk), - .d_data_status ({ dma_ovf, - dma_unf})); - -endmodule - -// *************************************************************************** -// *************************************************************************** diff --git a/library/common/up_dac_channel.v b/library/common/up_dac_channel.v index 24e9437e7..700458f4e 100644 --- a/library/common/up_dac_channel.v +++ b/library/common/up_dac_channel.v @@ -34,114 +34,70 @@ // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // *************************************************************************** // *************************************************************************** -// *************************************************************************** -// *************************************************************************** `timescale 1ns/100ps -module up_dac_channel ( - - // dac interface - - dac_clk, - dac_rst, - dac_dds_scale_1, - dac_dds_init_1, - dac_dds_incr_1, - dac_dds_scale_2, - dac_dds_init_2, - dac_dds_incr_2, - dac_pat_data_1, - dac_pat_data_2, - dac_data_sel, - dac_iqcor_enb, - dac_iqcor_coeff_1, - dac_iqcor_coeff_2, - - // user controls - - up_usr_datatype_be, - up_usr_datatype_signed, - up_usr_datatype_shift, - up_usr_datatype_total_bits, - up_usr_datatype_bits, - up_usr_interpolation_m, - up_usr_interpolation_n, - dac_usr_datatype_be, - dac_usr_datatype_signed, - dac_usr_datatype_shift, - dac_usr_datatype_total_bits, - dac_usr_datatype_bits, - dac_usr_interpolation_m, - dac_usr_interpolation_n, - - // bus interface - - up_rstn, - up_clk, - up_wreq, - up_waddr, - up_wdata, - up_wack, - up_rreq, - up_raddr, - up_rdata, - up_rack); +module up_dac_channel #( // parameters - parameter DAC_CHANNEL_ID = 4'h0; + parameter COMMON_ID = 6'h11, + parameter CHANNEL_ID = 4'h0, + parameter DDS_DISABLE = 0, + parameter USERPORTS_DISABLE = 0, + parameter IQCORRECTION_DISABLE = 0) ( // dac interface - input dac_clk; - input dac_rst; - output [15:0] dac_dds_scale_1; - output [15:0] dac_dds_init_1; - output [15:0] dac_dds_incr_1; - output [15:0] dac_dds_scale_2; - output [15:0] dac_dds_init_2; - output [15:0] dac_dds_incr_2; - output [15:0] dac_pat_data_1; - output [15:0] dac_pat_data_2; - output [ 3:0] dac_data_sel; - output dac_iqcor_enb; - output [15:0] dac_iqcor_coeff_1; - output [15:0] dac_iqcor_coeff_2; + input dac_clk, + input dac_rst, + output [15:0] dac_dds_scale_1, + output [15:0] dac_dds_init_1, + output [15:0] dac_dds_incr_1, + output [15:0] dac_dds_scale_2, + output [15:0] dac_dds_init_2, + output [15:0] dac_dds_incr_2, + output [15:0] dac_pat_data_1, + output [15:0] dac_pat_data_2, + output [ 3:0] dac_data_sel, + output dac_iq_mode, + output dac_iqcor_enb, + output [15:0] dac_iqcor_coeff_1, + output [15:0] dac_iqcor_coeff_2, // user controls - output up_usr_datatype_be; - output up_usr_datatype_signed; - output [ 7:0] up_usr_datatype_shift; - output [ 7:0] up_usr_datatype_total_bits; - output [ 7:0] up_usr_datatype_bits; - output [15:0] up_usr_interpolation_m; - output [15:0] up_usr_interpolation_n; - input dac_usr_datatype_be; - input dac_usr_datatype_signed; - input [ 7:0] dac_usr_datatype_shift; - input [ 7:0] dac_usr_datatype_total_bits; - input [ 7:0] dac_usr_datatype_bits; - input [15:0] dac_usr_interpolation_m; - input [15:0] dac_usr_interpolation_n; + output up_usr_datatype_be, + output up_usr_datatype_signed, + output [ 7:0] up_usr_datatype_shift, + output [ 7:0] up_usr_datatype_total_bits, + output [ 7:0] up_usr_datatype_bits, + output [15:0] up_usr_interpolation_m, + output [15:0] up_usr_interpolation_n, + input dac_usr_datatype_be, + input dac_usr_datatype_signed, + input [ 7:0] dac_usr_datatype_shift, + input [ 7:0] dac_usr_datatype_total_bits, + input [ 7:0] dac_usr_datatype_bits, + input [15:0] dac_usr_interpolation_m, + input [15:0] dac_usr_interpolation_n, // bus interface - input up_rstn; - input up_clk; - input up_wreq; - input [13:0] up_waddr; - input [31:0] up_wdata; - output up_wack; - input up_rreq; - input [13:0] up_raddr; - output [31:0] up_rdata; - output up_rack; + input up_rstn, + input up_clk, + input up_wreq, + input [13:0] up_waddr, + input [31:0] up_wdata, + output up_wack, + input up_rreq, + input [13:0] up_raddr, + output [31:0] up_rdata, + output up_rack); // internal registers - reg up_wack = 'd0; + reg up_wack_int = 'd0; reg [15:0] up_dac_dds_scale_1 = 'd0; reg [15:0] up_dac_dds_init_1 = 'd0; reg [15:0] up_dac_dds_incr_1 = 'd0; @@ -156,15 +112,16 @@ module up_dac_channel ( reg [ 3:0] up_dac_data_sel = 'd0; reg [15:0] up_dac_iqcor_coeff_1 = 'd0; reg [15:0] up_dac_iqcor_coeff_2 = 'd0; - reg up_usr_datatype_be = 'd0; - reg up_usr_datatype_signed = 'd0; - reg [ 7:0] up_usr_datatype_shift = 'd0; - reg [ 7:0] up_usr_datatype_total_bits = 'd0; - reg [ 7:0] up_usr_datatype_bits = 'd0; - reg [15:0] up_usr_interpolation_m = 'd0; - reg [15:0] up_usr_interpolation_n = 'd0; - reg up_rack = 'd0; - reg [31:0] up_rdata = 'd0; + reg up_usr_datatype_be_int = 'd0; + reg up_usr_datatype_signed_int = 'd0; + reg [ 7:0] up_usr_datatype_shift_int = 'd0; + reg [ 7:0] up_usr_datatype_total_bits_int = 'd0; + reg [ 7:0] up_usr_datatype_bits_int = 'd0; + reg [15:0] up_usr_interpolation_m_int = 'd0; + reg [15:0] up_usr_interpolation_n_int = 'd0; + reg up_dac_iq_mode = 'd0; + reg up_rack_int = 'd0; + reg [31:0] up_rdata_int = 'd0; reg [15:0] up_dac_dds_scale_tc_1 = 'd0; reg [15:0] up_dac_dds_scale_tc_2 = 'd0; reg [15:0] up_dac_iqcor_coeff_tc_1 = 'd0; @@ -193,37 +150,41 @@ module up_dac_channel ( // decode block select - assign up_wreq_s = ((up_waddr[13:8] == 6'h11) && (up_waddr[7:4] == DAC_CHANNEL_ID)) ? up_wreq : 1'b0; - assign up_rreq_s = ((up_raddr[13:8] == 6'h11) && (up_raddr[7:4] == DAC_CHANNEL_ID)) ? up_rreq : 1'b0; + assign up_wreq_s = ((up_waddr[13:8] == COMMON_ID) && (up_waddr[7:4] == CHANNEL_ID)) ? up_wreq : 1'b0; + assign up_rreq_s = ((up_raddr[13:8] == COMMON_ID) && (up_raddr[7:4] == CHANNEL_ID)) ? up_rreq : 1'b0; // processor write interface + assign up_wack = up_wack_int; + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_wack_int <= 'd0; + end else begin + up_wack_int <= up_wreq_s; + end + end + + generate + if (DDS_DISABLE == 1) begin + always @(posedge up_clk) begin + up_dac_dds_scale_1 <= 'd0; + up_dac_dds_init_1 <= 'd0; + up_dac_dds_incr_1 <= 'd0; + up_dac_dds_scale_2 <= 'd0; + up_dac_dds_init_2 <= 'd0; + up_dac_dds_incr_2 <= 'd0; + end + end else begin always @(negedge up_rstn or posedge up_clk) begin if (up_rstn == 0) begin - up_wack <= 'd0; up_dac_dds_scale_1 <= 'd0; up_dac_dds_init_1 <= 'd0; up_dac_dds_incr_1 <= 'd0; up_dac_dds_scale_2 <= 'd0; up_dac_dds_init_2 <= 'd0; up_dac_dds_incr_2 <= 'd0; - up_dac_pat_data_2 <= 'd0; - up_dac_pat_data_1 <= 'd0; - up_dac_iqcor_enb <= 'd0; - up_dac_lb_enb <= 'd0; - up_dac_pn_enb <= 'd0; - up_dac_data_sel <= 'd0; - up_dac_iqcor_coeff_1 <= 'd0; - up_dac_iqcor_coeff_2 <= 'd0; - up_usr_datatype_be <= 'd0; - up_usr_datatype_signed <= 'd0; - up_usr_datatype_shift <= 'd0; - up_usr_datatype_total_bits <= 'd0; - up_usr_datatype_bits <= 'd0; - up_usr_interpolation_m <= 'd0; - up_usr_interpolation_n <= 'd0; end else begin - up_wack <= up_wreq_s; if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h0)) begin up_dac_dds_scale_1 <= up_wdata[15:0]; end @@ -238,62 +199,164 @@ module up_dac_channel ( up_dac_dds_init_2 <= up_wdata[31:16]; up_dac_dds_incr_2 <= up_wdata[15:0]; end + end + end + end + endgenerate + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_dac_pat_data_2 <= 'd0; + up_dac_pat_data_1 <= 'd0; + end else begin if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h4)) begin up_dac_pat_data_2 <= up_wdata[31:16]; up_dac_pat_data_1 <= up_wdata[15:0]; end + end + end + + generate + if (IQCORRECTION_DISABLE == 1) begin + always @(posedge up_clk) begin + up_dac_iqcor_enb <= 'd0; + end + end else begin + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_dac_iqcor_enb <= 'd0; + end else begin if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h5)) begin up_dac_iqcor_enb <= up_wdata[2]; + end + end + end + end + endgenerate + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_dac_lb_enb <= 'd0; + up_dac_pn_enb <= 'd0; + up_dac_data_sel <= 'd0; + end else begin + if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h5)) begin up_dac_lb_enb <= up_wdata[1]; up_dac_pn_enb <= up_wdata[0]; end if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h6)) begin up_dac_data_sel <= up_wdata[3:0]; end + end + end + + generate + if (IQCORRECTION_DISABLE == 1) begin + always @(posedge up_clk) begin + up_dac_iqcor_coeff_1 <= 'd0; + up_dac_iqcor_coeff_2 <= 'd0; + end + end else begin + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_dac_iqcor_coeff_1 <= 'd0; + up_dac_iqcor_coeff_2 <= 'd0; + end else begin if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h7)) begin up_dac_iqcor_coeff_1 <= up_wdata[31:16]; up_dac_iqcor_coeff_2 <= up_wdata[15:0]; end + end + end + end + endgenerate + + assign up_usr_datatype_be = up_usr_datatype_be_int; + assign up_usr_datatype_signed = up_usr_datatype_signed_int; + assign up_usr_datatype_shift = up_usr_datatype_shift_int; + assign up_usr_datatype_total_bits = up_usr_datatype_total_bits_int; + assign up_usr_datatype_bits = up_usr_datatype_bits_int; + assign up_usr_interpolation_m = up_usr_interpolation_m_int; + assign up_usr_interpolation_n = up_usr_interpolation_n_int; + + generate + if (USERPORTS_DISABLE == 1) begin + always @(posedge up_clk) begin + up_usr_datatype_be_int <= 'd0; + up_usr_datatype_signed_int <= 'd0; + up_usr_datatype_shift_int <= 'd0; + up_usr_datatype_total_bits_int <= 'd0; + up_usr_datatype_bits_int <= 'd0; + up_usr_interpolation_m_int <= 'd0; + up_usr_interpolation_n_int <= 'd0; + end + end else begin + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_usr_datatype_be_int <= 'd0; + up_usr_datatype_signed_int <= 'd0; + up_usr_datatype_shift_int <= 'd0; + up_usr_datatype_total_bits_int <= 'd0; + up_usr_datatype_bits_int <= 'd0; + up_usr_interpolation_m_int <= 'd0; + up_usr_interpolation_n_int <= 'd0; + end else begin if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h8)) begin - up_usr_datatype_be <= up_wdata[25]; - up_usr_datatype_signed <= up_wdata[24]; - up_usr_datatype_shift <= up_wdata[23:16]; - up_usr_datatype_total_bits <= up_wdata[15:8]; - up_usr_datatype_bits <= up_wdata[7:0]; + up_usr_datatype_be_int <= up_wdata[25]; + up_usr_datatype_signed_int <= up_wdata[24]; + up_usr_datatype_shift_int <= up_wdata[23:16]; + up_usr_datatype_total_bits_int <= up_wdata[15:8]; + up_usr_datatype_bits_int <= up_wdata[7:0]; end if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h9)) begin - up_usr_interpolation_m <= up_wdata[31:16]; - up_usr_interpolation_n <= up_wdata[15:0]; + up_usr_interpolation_m_int <= up_wdata[31:16]; + up_usr_interpolation_n_int <= up_wdata[15:0]; + end + end + end + end + endgenerate + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_dac_iq_mode <= 'd0; + end else begin + if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'ha)) begin + up_dac_iq_mode <= up_wdata[0]; end end end // processor read interface + assign up_rack = up_rack_int; + assign up_rdata = up_rdata_int; + always @(negedge up_rstn or posedge up_clk) begin if (up_rstn == 0) begin - up_rack <= 'd0; - up_rdata <= 'd0; + up_rack_int <= 'd0; + up_rdata_int <= 'd0; end else begin - up_rack <= up_rreq_s; + up_rack_int <= up_rreq_s; if (up_rreq_s == 1'b1) begin case (up_raddr[3:0]) - 4'h0: up_rdata <= {16'd0, up_dac_dds_scale_1}; - 4'h1: up_rdata <= {up_dac_dds_init_1, up_dac_dds_incr_1}; - 4'h2: up_rdata <= {16'd0, up_dac_dds_scale_2}; - 4'h3: up_rdata <= {up_dac_dds_init_2, up_dac_dds_incr_2}; - 4'h4: up_rdata <= {up_dac_pat_data_2, up_dac_pat_data_1}; - 4'h5: up_rdata <= {29'd0, up_dac_iqcor_enb, up_dac_lb_enb, up_dac_pn_enb}; - 4'h6: up_rdata <= {28'd0, up_dac_data_sel_m}; - 4'h7: up_rdata <= {up_dac_iqcor_coeff_1, up_dac_iqcor_coeff_2}; - 4'h8: up_rdata <= {6'd0, dac_usr_datatype_be, dac_usr_datatype_signed, - dac_usr_datatype_shift, dac_usr_datatype_total_bits, - dac_usr_datatype_bits}; - 4'h9: up_rdata <= {dac_usr_interpolation_m, dac_usr_interpolation_n}; - default: up_rdata <= 0; + 4'h0: up_rdata_int <= { 16'd0, up_dac_dds_scale_1}; + 4'h1: up_rdata_int <= { up_dac_dds_init_1, up_dac_dds_incr_1}; + 4'h2: up_rdata_int <= { 16'd0, up_dac_dds_scale_2}; + 4'h3: up_rdata_int <= { up_dac_dds_init_2, up_dac_dds_incr_2}; + 4'h4: up_rdata_int <= { up_dac_pat_data_2, up_dac_pat_data_1}; + 4'h5: up_rdata_int <= { 29'd0, up_dac_iqcor_enb, up_dac_lb_enb, up_dac_pn_enb}; + 4'h6: up_rdata_int <= { 28'd0, up_dac_data_sel_m}; + 4'h7: up_rdata_int <= { up_dac_iqcor_coeff_1, up_dac_iqcor_coeff_2}; + 4'h8: up_rdata_int <= { 6'd0, dac_usr_datatype_be, dac_usr_datatype_signed, + dac_usr_datatype_shift, dac_usr_datatype_total_bits, + dac_usr_datatype_bits}; + 4'h9: up_rdata_int <= { dac_usr_interpolation_m, dac_usr_interpolation_n}; + 4'ha: up_rdata_int <= { 31'd0, up_dac_iq_mode}; + default: up_rdata_int <= 0; endcase end else begin - up_rdata <= 32'd0; + up_rdata_int <= 32'd0; end end end @@ -330,10 +393,11 @@ module up_dac_channel ( // dac control & status - up_xfer_cntrl #(.DATA_WIDTH(165)) i_xfer_cntrl ( + up_xfer_cntrl #(.DATA_WIDTH(166)) i_xfer_cntrl ( .up_rstn (up_rstn), .up_clk (up_clk), - .up_data_cntrl ({ up_dac_iqcor_enb, + .up_data_cntrl ({ up_dac_iq_mode, + up_dac_iqcor_enb, up_dac_iqcor_coeff_tc_1, up_dac_iqcor_coeff_tc_2, up_dac_dds_scale_tc_1, @@ -348,7 +412,8 @@ module up_dac_channel ( .up_xfer_done (), .d_rst (dac_rst), .d_clk (dac_clk), - .d_data_cntrl ({ dac_iqcor_enb, + .d_data_cntrl ({ dac_iq_mode, + dac_iqcor_enb, dac_iqcor_coeff_1, dac_iqcor_coeff_2, dac_dds_scale_1, diff --git a/library/common/up_dac_common.v b/library/common/up_dac_common.v index 2b1f76280..5d0968a7b 100644 --- a/library/common/up_dac_common.v +++ b/library/common/up_dac_common.v @@ -1,9 +1,9 @@ // *************************************************************************** // *************************************************************************** // Copyright 2011(c) Analog Devices, Inc. -// +// // All rights reserved. -// +// // Redistribution and use in source and binary forms, with or without modification, // are permitted provided that the following conditions are met: // - Redistributions of source code must retain the above copyright @@ -21,134 +21,92 @@ // patent holders to use this software. // - Use of the software either in source or binary form, must be run // on or directly connected to an Analog Devices Inc. component. -// +// // THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, // INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A // PARTICULAR PURPOSE ARE DISCLAIMED. // // IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, // EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY -// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR // BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // *************************************************************************** // *************************************************************************** `timescale 1ns/100ps -module up_dac_common ( - - // mmcm reset - - mmcm_rst, - - // dac interface - - dac_clk, - dac_rst, - dac_sync, - dac_frame, - dac_par_type, - dac_par_enb, - dac_r1_mode, - dac_datafmt, - dac_datarate, - dac_status, - dac_status_ovf, - dac_status_unf, - dac_clk_ratio, - - // drp interface - - up_drp_sel, - up_drp_wr, - up_drp_addr, - up_drp_wdata, - up_drp_rdata, - up_drp_ready, - up_drp_locked, - - // user channel control - - up_usr_chanmax, - dac_usr_chanmax, - up_dac_gpio_in, - up_dac_gpio_out, - - // bus interface - - up_rstn, - up_clk, - up_wreq, - up_waddr, - up_wdata, - up_wack, - up_rreq, - up_raddr, - up_rdata, - up_rack); +module up_dac_common #( // parameters - localparam PCORE_VERSION = 32'h00080062; - parameter ID = 0; + parameter ID = 0, + parameter CONFIG = 0, + parameter COMMON_ID = 6'h10, + parameter DRP_DISABLE = 6'h00, + parameter USERPORTS_DISABLE = 0) ( // mmcm reset - output mmcm_rst; + output mmcm_rst, // dac interface - input dac_clk; - output dac_rst; - output dac_sync; - output dac_frame; - output dac_par_type; - output dac_par_enb; - output dac_r1_mode; - output dac_datafmt; - output [ 7:0] dac_datarate; - input dac_status; - input dac_status_ovf; - input dac_status_unf; - input [31:0] dac_clk_ratio; + input dac_clk, + output dac_rst, + output dac_sync, + output dac_frame, + output dac_clksel, + output dac_par_type, + output dac_par_enb, + output dac_r1_mode, + output dac_datafmt, + output [ 7:0] dac_datarate, + input dac_status, + input dac_status_ovf, + input dac_status_unf, + input [31:0] dac_clk_ratio, // drp interface - output up_drp_sel; - output up_drp_wr; - output [11:0] up_drp_addr; - output [15:0] up_drp_wdata; - input [15:0] up_drp_rdata; - input up_drp_ready; - input up_drp_locked; + output up_drp_sel, + output up_drp_wr, + output [11:0] up_drp_addr, + output [31:0] up_drp_wdata, + input [31:0] up_drp_rdata, + input up_drp_ready, + input up_drp_locked, // user channel control - output [ 7:0] up_usr_chanmax; - input [ 7:0] dac_usr_chanmax; - input [31:0] up_dac_gpio_in; - output [31:0] up_dac_gpio_out; + output [ 7:0] up_usr_chanmax, + input [ 7:0] dac_usr_chanmax, + input [31:0] up_dac_gpio_in, + output [31:0] up_dac_gpio_out, // bus interface - input up_rstn; - input up_clk; - input up_wreq; - input [13:0] up_waddr; - input [31:0] up_wdata; - output up_wack; - input up_rreq; - input [13:0] up_raddr; - output [31:0] up_rdata; - output up_rack; + input up_rstn, + input up_clk, + input up_wreq, + input [13:0] up_waddr, + input [31:0] up_wdata, + output up_wack, + input up_rreq, + input [13:0] up_raddr, + output [31:0] up_rdata, + output up_rack); + + // parameters + + localparam VERSION = 32'h00090062; // internal registers - reg up_core_preset = 'd0; - reg up_mmcm_preset = 'd0; - reg up_wack = 'd0; + reg up_core_preset = 'd1; + reg up_mmcm_preset = 'd1; + reg up_wack_int = 'd0; reg [31:0] up_scratch = 'd0; reg up_mmcm_resetn = 'd0; reg up_resetn = 'd0; @@ -159,26 +117,27 @@ module up_dac_common ( reg up_dac_datafmt = 'd0; reg [ 7:0] up_dac_datarate = 'd0; reg up_dac_frame = 'd0; - reg up_drp_sel = 'd0; - reg up_drp_wr = 'd0; + reg up_dac_clksel = 'd0; + reg up_drp_sel_int = 'd0; + reg up_drp_wr_int = 'd0; reg up_drp_status = 'd0; reg up_drp_rwn = 'd0; - reg [11:0] up_drp_addr = 'd0; - reg [15:0] up_drp_wdata = 'd0; - reg [15:0] up_drp_rdata_hold = 'd0; + reg [11:0] up_drp_addr_int = 'd0; + reg [31:0] up_drp_wdata_int = 'd0; + reg [31:0] up_drp_rdata_hold = 'd0; reg up_status_ovf = 'd0; reg up_status_unf = 'd0; - reg [ 7:0] up_usr_chanmax = 'd0; - reg [31:0] up_dac_gpio_out = 'd0; - reg up_rack = 'd0; - reg [31:0] up_rdata = 'd0; + reg [ 7:0] up_usr_chanmax_int = 'd0; + reg [31:0] up_dac_gpio_out_int = 'd0; + reg up_rack_int = 'd0; + reg [31:0] up_rdata_int = 'd0; reg dac_sync_d = 'd0; reg dac_sync_2d = 'd0; reg [ 5:0] dac_sync_count = 'd0; - reg dac_sync = 'd0; + reg dac_sync_int = 'd0; reg dac_frame_d = 'd0; reg dac_frame_2d = 'd0; - reg dac_frame = 'd0; + reg dac_frame_int = 'd0; // internal signals @@ -194,16 +153,18 @@ module up_dac_common ( // decode block select - assign up_wreq_s = (up_waddr[13:8] == 6'h10) ? up_wreq : 1'b0; - assign up_rreq_s = (up_raddr[13:8] == 6'h10) ? up_rreq : 1'b0; + assign up_wreq_s = (up_waddr[13:8] == COMMON_ID) ? up_wreq : 1'b0; + assign up_rreq_s = (up_raddr[13:8] == COMMON_ID) ? up_rreq : 1'b0; // processor write interface + assign up_wack = up_wack_int; + always @(negedge up_rstn or posedge up_clk) begin if (up_rstn == 0) begin up_core_preset <= 1'd1; up_mmcm_preset <= 1'd1; - up_wack <= 'd0; + up_wack_int <= 'd0; up_scratch <= 'd0; up_mmcm_resetn <= 'd0; up_resetn <= 'd0; @@ -214,21 +175,11 @@ module up_dac_common ( up_dac_datafmt <= 'd0; up_dac_datarate <= 'd0; up_dac_frame <= 'd0; - up_drp_sel <= 'd0; - up_drp_wr <= 'd0; - up_drp_status <= 'd0; - up_drp_rwn <= 'd0; - up_drp_addr <= 'd0; - up_drp_wdata <= 'd0; - up_drp_rdata_hold <= 'd0; - up_status_ovf <= 'd0; - up_status_ovf <= 'd0; - up_usr_chanmax <= 'd0; - up_dac_gpio_out <= 'd0; + up_dac_clksel <= 'd0; end else begin up_core_preset <= ~up_resetn; up_mmcm_preset <= ~up_mmcm_resetn; - up_wack <= up_wreq_s; + up_wack_int <= up_wreq_s; if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h02)) begin up_scratch <= up_wdata; end @@ -259,12 +210,45 @@ module up_dac_common ( end else if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h14)) begin up_dac_frame <= up_wdata[0]; end + if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h18)) begin + up_dac_clksel <= up_wdata[0]; + end + end + end + + assign up_drp_sel = up_drp_sel_int; + assign up_drp_wr = up_drp_wr_int; + assign up_drp_addr = up_drp_addr_int; + assign up_drp_wdata = up_drp_wdata_int; + + generate + if (DRP_DISABLE == 1) begin + always @(posedge up_clk) begin + up_drp_sel_int <= 'd0; + up_drp_wr_int <= 'd0; + up_drp_status <= 'd0; + up_drp_rwn <= 'd0; + up_drp_addr_int <= 'd0; + up_drp_wdata_int <= 'd0; + up_drp_rdata_hold <= 'd0; + end + end else begin + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_drp_sel_int <= 'd0; + up_drp_wr_int <= 'd0; + up_drp_status <= 'd0; + up_drp_rwn <= 'd0; + up_drp_addr_int <= 'd0; + up_drp_wdata_int <= 'd0; + up_drp_rdata_hold <= 'd0; + end else begin if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h1c)) begin - up_drp_sel <= 1'b1; - up_drp_wr <= ~up_wdata[28]; + up_drp_sel_int <= 1'b1; + up_drp_wr_int <= ~up_wdata[28]; end else begin - up_drp_sel <= 1'b0; - up_drp_wr <= 1'b0; + up_drp_sel_int <= 1'b0; + up_drp_wr_int <= 1'b0; end if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h1c)) begin up_drp_status <= 1'b1; @@ -273,12 +257,24 @@ module up_dac_common ( end if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h1c)) begin up_drp_rwn <= up_wdata[28]; - up_drp_addr <= up_wdata[27:16]; - up_drp_wdata <= up_wdata[15:0]; + up_drp_addr_int <= up_wdata[27:16]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h1e)) begin + up_drp_wdata_int <= up_wdata; end if (up_drp_ready == 1'b1) begin up_drp_rdata_hold <= up_drp_rdata; end + end + end + end + endgenerate + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_status_ovf <= 'd0; + up_status_unf <= 'd0; + end else begin if (up_status_ovf_s == 1'b1) begin up_status_ovf <= 1'b1; end else if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h22)) begin @@ -289,47 +285,80 @@ module up_dac_common ( end else if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h22)) begin up_status_unf <= up_status_unf & ~up_wdata[0]; end + end + end + + assign up_usr_chanmax = up_usr_chanmax_int; + + generate + if (USERPORTS_DISABLE == 1) begin + always @(posedge up_clk) begin + up_usr_chanmax_int <= 'd0; + end + end else begin + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_usr_chanmax_int <= 'd0; + end else begin if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h28)) begin - up_usr_chanmax <= up_wdata[7:0]; + up_usr_chanmax_int <= up_wdata[7:0]; end + end + end + end + endgenerate + + assign up_dac_gpio_out = up_dac_gpio_out_int; + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_dac_gpio_out_int <= 'd0; + end else begin if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h2f)) begin - up_dac_gpio_out <= up_wdata; + up_dac_gpio_out_int <= up_wdata; end end end // processor read interface + assign up_rack = up_rack_int; + assign up_rdata = up_rdata_int; + always @(negedge up_rstn or posedge up_clk) begin if (up_rstn == 0) begin - up_rack <= 'd0; - up_rdata <= 'd0; + up_rack_int <= 'd0; + up_rdata_int <= 'd0; end else begin - up_rack <= up_rreq_s; + up_rack_int <= up_rreq_s; if (up_rreq_s == 1'b1) begin case (up_raddr[7:0]) - 8'h00: up_rdata <= PCORE_VERSION; - 8'h01: up_rdata <= ID; - 8'h02: up_rdata <= up_scratch; - 8'h10: up_rdata <= {30'd0, up_mmcm_resetn, up_resetn}; - 8'h11: up_rdata <= {31'd0, up_dac_sync}; - 8'h12: up_rdata <= {24'd0, up_dac_par_type, up_dac_par_enb, up_dac_r1_mode, + 8'h00: up_rdata_int <= VERSION; + 8'h01: up_rdata_int <= ID; + 8'h02: up_rdata_int <= up_scratch; + 8'h03: up_rdata_int <= CONFIG; + 8'h10: up_rdata_int <= {30'd0, up_mmcm_resetn, up_resetn}; + 8'h11: up_rdata_int <= {31'd0, up_dac_sync}; + 8'h12: up_rdata_int <= {24'd0, up_dac_par_type, up_dac_par_enb, up_dac_r1_mode, up_dac_datafmt, 4'd0}; - 8'h13: up_rdata <= {24'd0, up_dac_datarate}; - 8'h14: up_rdata <= {31'd0, up_dac_frame}; - 8'h15: up_rdata <= up_dac_clk_count_s; - 8'h16: up_rdata <= dac_clk_ratio; - 8'h17: up_rdata <= {31'd0, up_status_s}; - 8'h1c: up_rdata <= {3'd0, up_drp_rwn, up_drp_addr, up_drp_wdata}; - 8'h1d: up_rdata <= {14'd0, up_drp_locked, up_drp_status, up_drp_rdata_hold}; - 8'h22: up_rdata <= {30'd0, up_status_ovf, up_status_unf}; - 8'h28: up_rdata <= {24'd0, dac_usr_chanmax}; - 8'h2e: up_rdata <= up_dac_gpio_in; - 8'h2f: up_rdata <= up_dac_gpio_out; - default: up_rdata <= 0; + 8'h13: up_rdata_int <= {24'd0, up_dac_datarate}; + 8'h14: up_rdata_int <= {31'd0, up_dac_frame}; + 8'h15: up_rdata_int <= up_dac_clk_count_s; + 8'h16: up_rdata_int <= dac_clk_ratio; + 8'h17: up_rdata_int <= {31'd0, up_status_s}; + 8'h18: up_rdata_int <= {31'd0, up_dac_clksel}; + 8'h1c: up_rdata_int <= {3'd0, up_drp_rwn, up_drp_addr_int, 16'b0}; + 8'h1d: up_rdata_int <= {14'd0, up_drp_locked, up_drp_status, 16'b0}; + 8'h1e: up_rdata_int <= up_drp_wdata_int; + 8'h1f: up_rdata_int <= up_drp_rdata_hold; + 8'h22: up_rdata_int <= {30'd0, up_status_ovf, up_status_unf}; + 8'h28: up_rdata_int <= {24'd0, dac_usr_chanmax}; + 8'h2e: up_rdata_int <= up_dac_gpio_in; + 8'h2f: up_rdata_int <= up_dac_gpio_out_int; + default: up_rdata_int <= 0; endcase end else begin - up_rdata <= 32'd0; + up_rdata_int <= 32'd0; end end end @@ -341,10 +370,11 @@ module up_dac_common ( // dac control & status - up_xfer_cntrl #(.DATA_WIDTH(14)) i_xfer_cntrl ( + up_xfer_cntrl #(.DATA_WIDTH(15)) i_xfer_cntrl ( .up_rstn (up_rstn), .up_clk (up_clk), .up_data_cntrl ({ up_dac_sync, + up_dac_clksel, up_dac_frame, up_dac_par_type, up_dac_par_enb, @@ -355,6 +385,7 @@ module up_dac_common ( .d_rst (dac_rst), .d_clk (dac_clk), .d_data_cntrl ({ dac_sync_s, + dac_clksel, dac_frame_s, dac_par_type, dac_par_enb, @@ -376,6 +407,9 @@ module up_dac_common ( // generate frame and enable + assign dac_sync = dac_sync_int; + assign dac_frame = dac_frame_int; + always @(posedge dac_clk) begin dac_sync_d <= dac_sync_s; dac_sync_2d <= dac_sync_d; @@ -384,10 +418,10 @@ module up_dac_common ( end else if ((dac_sync_d == 1'b1) && (dac_sync_2d == 1'b0)) begin dac_sync_count <= 6'h20; end - dac_sync <= dac_sync_count[5]; + dac_sync_int <= dac_sync_count[5]; dac_frame_d <= dac_frame_s; dac_frame_2d <= dac_frame_d; - dac_frame <= dac_frame_d & ~dac_frame_2d; + dac_frame_int <= dac_frame_d & ~dac_frame_2d; end // dac clock monitor diff --git a/library/common/up_delay_cntrl.v b/library/common/up_delay_cntrl.v index e4dfbe6ef..68d6fdb1f 100644 --- a/library/common/up_delay_cntrl.v +++ b/library/common/up_delay_cntrl.v @@ -37,73 +37,49 @@ `timescale 1ns/100ps -module up_delay_cntrl ( - - // delay interface - - delay_clk, - delay_rst, - delay_locked, - - // io interface - - up_dld, - up_dwdata, - up_drdata, - - // processor interface - - up_rstn, - up_clk, - up_wreq, - up_waddr, - up_wdata, - up_wack, - up_rreq, - up_raddr, - up_rdata, - up_rack); +module up_delay_cntrl #( // parameters - parameter DATA_WIDTH = 8; - parameter BASE_ADDRESS = 6'h02; + parameter DISABLE = 0, + parameter DATA_WIDTH = 8, + parameter BASE_ADDRESS = 6'h02) ( // delay interface - input delay_clk; - output delay_rst; - input delay_locked; + input delay_clk, + output delay_rst, + input delay_locked, // io interface - output [(DATA_WIDTH-1):0] up_dld; - output [((DATA_WIDTH*5)-1):0] up_dwdata; - input [((DATA_WIDTH*5)-1):0] up_drdata; + output [(DATA_WIDTH-1):0] up_dld, + output [((DATA_WIDTH*5)-1):0] up_dwdata, + input [((DATA_WIDTH*5)-1):0] up_drdata, // processor interface - input up_rstn; - input up_clk; - input up_wreq; - input [13:0] up_waddr; - input [31:0] up_wdata; - output up_wack; - input up_rreq; - input [13:0] up_raddr; - output [31:0] up_rdata; - output up_rack; + input up_rstn, + input up_clk, + input up_wreq, + input [13:0] up_waddr, + input [31:0] up_wdata, + output up_wack, + input up_rreq, + input [13:0] up_raddr, + output [31:0] up_rdata, + output up_rack); // internal registers reg up_preset = 'd0; - reg up_wack = 'd0; - reg up_rack = 'd0; - reg [31:0] up_rdata = 'd0; + reg up_wack_int = 'd0; + reg up_rack_int = 'd0; + reg [31:0] up_rdata_int = 'd0; reg up_dlocked_m1 = 'd0; reg up_dlocked = 'd0; - reg [(DATA_WIDTH-1):0] up_dld = 'd0; - reg [((DATA_WIDTH*5)-1):0] up_dwdata = 'd0; + reg [(DATA_WIDTH-1):0] up_dld_int = 'd0; + reg [((DATA_WIDTH*5)-1):0] up_dwdata_int = 'd0; // internal signals @@ -115,6 +91,9 @@ module up_delay_cntrl ( wire [(DATA_WIDTH-1):0] up_drdata2_s; wire [(DATA_WIDTH-1):0] up_drdata1_s; wire [(DATA_WIDTH-1):0] up_drdata0_s; + wire [(DATA_WIDTH-1):0] up_dld_s; + wire [((DATA_WIDTH*5)-1):0] up_dwdata_s; + wire delay_rst_s; // variables @@ -142,26 +121,30 @@ module up_delay_cntrl ( // processor interface + assign up_wack = (DISABLE == 1) ? 1'd0 : up_wack_int; + assign up_rack = (DISABLE == 1) ? 1'd0 : up_rack_int; + assign up_rdata = (DISABLE == 1) ? 32'd0 : up_rdata_int; + always @(negedge up_rstn or posedge up_clk) begin if (up_rstn == 0) begin up_preset <= 1'd1; - up_wack <= 'd0; - up_rack <= 'd0; - up_rdata <= 'd0; + up_wack_int <= 'd0; + up_rack_int <= 'd0; + up_rdata_int <= 'd0; up_dlocked_m1 <= 'd0; up_dlocked <= 'd0; end else begin up_preset <= 1'd0; - up_wack <= up_wreq_s; - up_rack <= up_rreq_s; + up_wack_int <= up_wreq_s; + up_rack_int <= up_rreq_s; if (up_rreq_s == 1'b1) begin if (up_dlocked == 1'b0) begin - up_rdata <= 32'hffffffff; + up_rdata_int <= 32'hffffffff; end else begin - up_rdata <= {27'd0, up_rdata_s}; + up_rdata_int <= {27'd0, up_rdata_s}; end end else begin - up_rdata <= 32'd0; + up_rdata_int <= 32'd0; end up_dlocked_m1 <= delay_locked; up_dlocked <= up_dlocked_m1; @@ -172,29 +155,35 @@ module up_delay_cntrl ( generate for (n = 0; n < DATA_WIDTH; n = n + 1) begin: g_dwr - always @(negedge up_rstn or posedge up_clk) begin - if (up_rstn == 0) begin - up_dld[n] <= 'd0; - up_dwdata[((n*5)+4):(n*5)] <= 'd0; - end else begin - if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == n)) begin - up_dld[n] <= 1'd1; - up_dwdata[((n*5)+4):(n*5)] <= up_wdata[4:0]; - end else begin - up_dld[n] <= 1'd0; - up_dwdata[((n*5)+4):(n*5)] <= up_dwdata[((n*5)+4):(n*5)]; - end - end - end + assign up_dld_s[n] = (up_waddr[7:0] == n) ? up_wreq_s : 1'b0; + assign up_dwdata_s[((n*5)+4):(n*5)] = (up_waddr[7:0] == n) ? + up_wdata[4:0] : up_dwdata_int[((n*5)+4):(n*5)]; end endgenerate + assign up_dld = (DISABLE == 1) ? 'd0 : up_dld_int; + assign up_dwdata = (DISABLE == 1) ? 'd0 : up_dwdata_int; + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_dld_int <= 'd0; + up_dwdata_int <= 'd0; + end else begin + up_dld_int <= up_dld_s; + if (up_wreq_s == 1'b1) begin + up_dwdata_int <= up_dwdata_s; + end + end + end + // resets + assign delay_rst = (DISABLE == 1) ? 1'd0 : delay_rst_s; + ad_rst i_delay_rst_reg ( .preset (up_preset), .clk (delay_clk), - .rst (delay_rst)); + .rst (delay_rst_s)); endmodule diff --git a/library/common/up_drp_cntrl.v b/library/common/up_drp_cntrl.v deleted file mode 100644 index c9bce27a8..000000000 --- a/library/common/up_drp_cntrl.v +++ /dev/null @@ -1,194 +0,0 @@ -// *************************************************************************** -// *************************************************************************** -// Copyright 2011(c) Analog Devices, Inc. -// -// All rights reserved. -// -// Redistribution and use in source and binary forms, with or without modification, -// are permitted provided that the following conditions are met: -// - Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// - Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in -// the documentation and/or other materials provided with the -// distribution. -// - Neither the name of Analog Devices, Inc. nor the names of its -// contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// - The use of this software may or may not infringe the patent rights -// of one or more patent holders. This license does not release you -// from the requirement that you obtain separate licenses from these -// patent holders to use this software. -// - Use of the software either in source or binary form, must be run -// on or directly connected to an Analog Devices Inc. component. -// -// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, -// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A -// PARTICULAR PURPOSE ARE DISCLAIMED. -// -// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY -// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF -// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// *************************************************************************** -// *************************************************************************** -// *************************************************************************** -// *************************************************************************** - -`timescale 1ns/100ps - -module up_drp_cntrl ( - - // drp interface - - drp_clk, - drp_rst, - drp_sel, - drp_wr, - drp_addr, - drp_wdata, - drp_rdata, - drp_ready, - drp_locked, - - // processor interface - - up_rstn, - up_clk, - up_drp_sel_t, - up_drp_rwn, - up_drp_addr, - up_drp_wdata, - up_drp_rdata, - up_drp_status, - up_drp_locked); - - // drp interface - - input drp_clk; - input drp_rst; - output drp_sel; - output drp_wr; - output [11:0] drp_addr; - output [15:0] drp_wdata; - input [15:0] drp_rdata; - input drp_ready; - input drp_locked; - - // processor interface - - input up_rstn; - input up_clk; - input up_drp_sel_t; - input up_drp_rwn; - input [11:0] up_drp_addr; - input [15:0] up_drp_wdata; - output [15:0] up_drp_rdata; - output up_drp_status; - output up_drp_locked; - - // internal registers - - reg drp_sel_t_m1 = 'd0; - reg drp_sel_t_m2 = 'd0; - reg drp_sel_t_m3 = 'd0; - reg drp_sel = 'd0; - reg drp_wr = 'd0; - reg [11:0] drp_addr = 'd0; - reg [15:0] drp_wdata = 'd0; - reg drp_ready_int = 'd0; - reg [15:0] drp_rdata_int = 'd0; - reg drp_ack_t = 'd0; - reg up_drp_locked_m1 = 'd0; - reg up_drp_locked = 'd0; - reg up_drp_ack_t_m1 = 'd0; - reg up_drp_ack_t_m2 = 'd0; - reg up_drp_ack_t_m3 = 'd0; - reg up_drp_sel_t_d = 'd0; - reg up_drp_status = 'd0; - reg [15:0] up_drp_rdata = 'd0; - - // internal signals - - wire drp_sel_t_s; - wire up_drp_ack_t_s; - wire up_drp_sel_t_s; - - // drp control and status - - assign drp_sel_t_s = drp_sel_t_m2 ^ drp_sel_t_m3; - - always @(posedge drp_clk) begin - if (drp_rst == 1'b1) begin - drp_sel_t_m1 <= 'd0; - drp_sel_t_m2 <= 'd0; - drp_sel_t_m3 <= 'd0; - end else begin - drp_sel_t_m1 <= up_drp_sel_t; - drp_sel_t_m2 <= drp_sel_t_m1; - drp_sel_t_m3 <= drp_sel_t_m2; - end - end - - always @(posedge drp_clk) begin - if (drp_sel_t_s == 1'b1) begin - drp_sel <= 1'b1; - drp_wr <= ~up_drp_rwn; - drp_addr <= up_drp_addr; - drp_wdata <= up_drp_wdata; - end else begin - drp_sel <= 1'b0; - drp_wr <= 1'b0; - drp_addr <= 12'd0; - drp_wdata <= 16'd0; - end - end - - always @(posedge drp_clk) begin - drp_ready_int <= drp_ready; - if ((drp_ready_int == 1'b0) && (drp_ready == 1'b1)) begin - drp_rdata_int <= drp_rdata; - drp_ack_t <= ~drp_ack_t; - end - end - - - // drp status transfer - - assign up_drp_ack_t_s = up_drp_ack_t_m3 ^ up_drp_ack_t_m2; - assign up_drp_sel_t_s = up_drp_sel_t ^ up_drp_sel_t_d; - - always @(negedge up_rstn or posedge up_clk) begin - if (up_rstn == 1'b0) begin - up_drp_locked_m1 <= 'd0; - up_drp_locked <= 'd0; - up_drp_ack_t_m1 <= 'd0; - up_drp_ack_t_m2 <= 'd0; - up_drp_ack_t_m3 <= 'd0; - up_drp_sel_t_d <= 'd0; - up_drp_status <= 'd0; - up_drp_rdata <= 'd0; - end else begin - up_drp_locked_m1 <= drp_locked; - up_drp_locked <= up_drp_locked_m1; - up_drp_ack_t_m1 <= drp_ack_t; - up_drp_ack_t_m2 <= up_drp_ack_t_m1; - up_drp_ack_t_m3 <= up_drp_ack_t_m2; - up_drp_sel_t_d <= up_drp_sel_t; - if (up_drp_ack_t_s == 1'b1) begin - up_drp_status <= 1'b0; - end else if (up_drp_sel_t_s == 1'b1) begin - up_drp_status <= 1'b1; - end - if (up_drp_ack_t_s == 1'b1) begin - up_drp_rdata <= drp_rdata_int; - end - end - end - -endmodule - -// *************************************************************************** -// *************************************************************************** diff --git a/library/common/up_hdmi_tx.v b/library/common/up_hdmi_tx.v index e1750e76b..bbef0119e 100644 --- a/library/common/up_hdmi_tx.v +++ b/library/common/up_hdmi_tx.v @@ -43,7 +43,6 @@ module up_hdmi_tx ( hdmi_clk, hdmi_rst, - hdmi_full_range, hdmi_csc_bypass, hdmi_ss_bypass, hdmi_srcsel, @@ -94,7 +93,6 @@ module up_hdmi_tx ( input hdmi_clk; output hdmi_rst; - output hdmi_full_range; output hdmi_csc_bypass; output hdmi_ss_bypass; output [ 1:0] hdmi_srcsel; @@ -142,7 +140,6 @@ module up_hdmi_tx ( reg up_wack = 'd0; reg [31:0] up_scratch = 'd0; reg up_resetn = 'd0; - reg up_full_range = 'd0; reg up_csc_bypass = 'd0; reg up_ss_bypass = 'd0; reg [ 1:0] up_srcsel = 'd1; @@ -190,7 +187,6 @@ module up_hdmi_tx ( up_wack <= 'd0; up_scratch <= 'd0; up_resetn <= 'd0; - up_full_range <= 'd0; up_csc_bypass <= 'd0; up_ss_bypass <= 'd0; up_srcsel <= 'd1; @@ -222,7 +218,6 @@ module up_hdmi_tx ( end if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h011)) begin up_ss_bypass <= up_wdata[2]; - up_full_range <= up_wdata[1]; up_csc_bypass <= up_wdata[0]; end if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h012)) begin @@ -251,19 +246,10 @@ module up_hdmi_tx ( end else if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h019)) begin up_vdma_tpm_oos <= up_vdma_tpm_oos & ~up_wdata[0]; end - if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h011)) begin - if ((up_wdata[1]== 1'b1) || (up_wdata[0] == 1'b1)) begin - up_clip_max <= 24'hfefefe; - up_clip_min <= 24'h010101; - end else begin - up_clip_max <= 24'hf0ebf0; - up_clip_min <= 24'h101010; - end - end if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h01a)) begin up_clip_max <= up_wdata[23:0]; end - if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h01b)) begin + if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h01b)) begin up_clip_min <= up_wdata[23:0]; end if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h100)) begin @@ -305,7 +291,7 @@ module up_hdmi_tx ( 12'h001: up_rdata <= ID; 12'h002: up_rdata <= up_scratch; 12'h010: up_rdata <= {31'd0, up_resetn}; - 12'h011: up_rdata <= {29'd0, up_ss_bypass, up_full_range, up_csc_bypass}; + 12'h011: up_rdata <= {29'd0, up_ss_bypass, 1'b0, up_csc_bypass}; 12'h012: up_rdata <= {30'd0, up_srcsel}; 12'h013: up_rdata <= {8'd0, up_const_rgb}; 12'h015: up_rdata <= up_hdmi_clk_count_s; @@ -337,11 +323,10 @@ module up_hdmi_tx ( // hdmi control & status - up_xfer_cntrl #(.DATA_WIDTH(237)) i_xfer_cntrl ( + up_xfer_cntrl #(.DATA_WIDTH(236)) i_xfer_cntrl ( .up_rstn (up_rstn), .up_clk (up_clk), .up_data_cntrl ({ up_ss_bypass, - up_full_range, up_csc_bypass, up_srcsel, up_const_rgb, @@ -361,7 +346,6 @@ module up_hdmi_tx ( .d_rst (hdmi_rst), .d_clk (hdmi_clk), .d_data_cntrl ({ hdmi_ss_bypass, - hdmi_full_range, hdmi_csc_bypass, hdmi_srcsel, hdmi_const_rgb, diff --git a/library/common/up_tdd_cntrl.v b/library/common/up_tdd_cntrl.v index 98f2cf9a5..71c7ce4e8 100644 --- a/library/common/up_tdd_cntrl.v +++ b/library/common/up_tdd_cntrl.v @@ -55,13 +55,14 @@ module up_tdd_cntrl ( tdd_counter_init, tdd_frame_length, tdd_terminal_type, - tdd_sync_enable, tdd_vco_rx_on_1, tdd_vco_rx_off_1, tdd_vco_tx_on_1, tdd_vco_tx_off_1, tdd_rx_on_1, tdd_rx_off_1, + tdd_rx_dp_on_1, + tdd_rx_dp_off_1, tdd_tx_on_1, tdd_tx_off_1, tdd_tx_dp_on_1, @@ -72,6 +73,8 @@ module up_tdd_cntrl ( tdd_vco_tx_off_2, tdd_rx_on_2, tdd_rx_off_2, + tdd_rx_dp_on_2, + tdd_rx_dp_off_2, tdd_tx_on_2, tdd_tx_off_2, tdd_tx_dp_on_2, @@ -94,7 +97,7 @@ module up_tdd_cntrl ( // parameters - localparam PCORE_VERSION = 32'h00010001; + localparam PCORE_VERSION = 32'h00010061; parameter ID = 0; input clk; @@ -110,13 +113,14 @@ module up_tdd_cntrl ( output [23:0] tdd_counter_init; output [23:0] tdd_frame_length; output tdd_terminal_type; - output tdd_sync_enable; output [23:0] tdd_vco_rx_on_1; output [23:0] tdd_vco_rx_off_1; output [23:0] tdd_vco_tx_on_1; output [23:0] tdd_vco_tx_off_1; output [23:0] tdd_rx_on_1; output [23:0] tdd_rx_off_1; + output [23:0] tdd_rx_dp_on_1; + output [23:0] tdd_rx_dp_off_1; output [23:0] tdd_tx_on_1; output [23:0] tdd_tx_off_1; output [23:0] tdd_tx_dp_on_1; @@ -127,6 +131,8 @@ module up_tdd_cntrl ( output [23:0] tdd_vco_tx_off_2; output [23:0] tdd_rx_on_2; output [23:0] tdd_rx_off_2; + output [23:0] tdd_rx_dp_on_2; + output [23:0] tdd_rx_dp_off_2; output [23:0] tdd_tx_on_2; output [23:0] tdd_tx_off_2; output [23:0] tdd_tx_dp_on_2; @@ -161,7 +167,6 @@ module up_tdd_cntrl ( reg up_tdd_gated_tx_dmapath = 1'h0; reg up_tdd_gated_rx_dmapath = 1'h0; reg up_tdd_terminal_type = 1'h0; - reg up_tdd_sync_enable = 1'h0; reg [ 7:0] up_tdd_burst_count = 8'h0; reg [23:0] up_tdd_counter_init = 24'h0; @@ -173,6 +178,8 @@ module up_tdd_cntrl ( reg [23:0] up_tdd_vco_tx_off_1 = 24'h0; reg [23:0] up_tdd_rx_on_1 = 24'h0; reg [23:0] up_tdd_rx_off_1 = 24'h0; + reg [23:0] up_tdd_rx_dp_on_1 = 24'h0; + reg [23:0] up_tdd_rx_dp_off_1 = 24'h0; reg [23:0] up_tdd_tx_on_1 = 24'h0; reg [23:0] up_tdd_tx_off_1 = 24'h0; reg [23:0] up_tdd_tx_dp_on_1 = 24'h0; @@ -183,6 +190,8 @@ module up_tdd_cntrl ( reg [23:0] up_tdd_vco_tx_off_2 = 24'h0; reg [23:0] up_tdd_rx_on_2 = 24'h0; reg [23:0] up_tdd_rx_off_2 = 24'h0; + reg [23:0] up_tdd_rx_dp_on_2 = 24'h0; + reg [23:0] up_tdd_rx_dp_off_2 = 24'h0; reg [23:0] up_tdd_tx_on_2 = 24'h0; reg [23:0] up_tdd_tx_off_2 = 24'h0; reg [23:0] up_tdd_tx_dp_on_2 = 24'h0; @@ -213,7 +222,6 @@ module up_tdd_cntrl ( up_tdd_gated_tx_dmapath <= 1'h0; up_tdd_gated_rx_dmapath <= 1'h0; up_tdd_terminal_type <= 1'h0; - up_tdd_sync_enable <= 1'h0; up_tdd_counter_init <= 24'h0; up_tdd_frame_length <= 24'h0; up_tdd_burst_count <= 8'h0; @@ -223,18 +231,24 @@ module up_tdd_cntrl ( up_tdd_vco_tx_off_1 <= 24'h0; up_tdd_rx_on_1 <= 24'h0; up_tdd_rx_off_1 <= 24'h0; + up_tdd_rx_dp_on_1 <= 24'h0; + up_tdd_rx_dp_off_1 <= 24'h0; up_tdd_tx_on_1 <= 24'h0; up_tdd_tx_off_1 <= 24'h0; up_tdd_tx_dp_on_1 <= 24'h0; + up_tdd_tx_dp_off_1 <= 24'h0; up_tdd_vco_rx_on_2 <= 24'h0; up_tdd_vco_rx_off_2 <= 24'h0; up_tdd_vco_tx_on_2 <= 24'h0; up_tdd_vco_tx_off_2 <= 24'h0; up_tdd_rx_on_2 <= 24'h0; up_tdd_rx_off_2 <= 24'h0; + up_tdd_rx_dp_on_2 <= 24'h0; + up_tdd_rx_dp_off_2 <= 24'h0; up_tdd_tx_on_2 <= 24'h0; up_tdd_tx_off_2 <= 24'h0; up_tdd_tx_dp_on_2 <= 24'h0; + up_tdd_tx_dp_off_2 <= 24'h0; end else begin up_wack <= up_wreq_s; if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h02)) begin @@ -258,8 +272,7 @@ module up_tdd_cntrl ( up_tdd_frame_length <= up_wdata[23:0]; end if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h14)) begin - up_tdd_terminal_type <= up_wdata[1]; - up_tdd_sync_enable <= up_wdata[0]; + up_tdd_terminal_type <= up_wdata[0]; end if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h20)) begin up_tdd_vco_rx_on_1 <= up_wdata[23:0]; @@ -286,9 +299,15 @@ module up_tdd_cntrl ( up_tdd_tx_off_1 <= up_wdata[23:0]; end if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h28)) begin - up_tdd_tx_dp_on_1 <= up_wdata[23:0]; + up_tdd_rx_dp_on_1 <= up_wdata[23:0]; end if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h29)) begin + up_tdd_rx_dp_off_1 <= up_wdata[23:0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h2a)) begin + up_tdd_tx_dp_on_1 <= up_wdata[23:0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h2b)) begin up_tdd_tx_dp_off_1 <= up_wdata[23:0]; end if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h30)) begin @@ -316,9 +335,15 @@ module up_tdd_cntrl ( up_tdd_tx_off_2 <= up_wdata[23:0]; end if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h38)) begin - up_tdd_tx_dp_on_2 <= up_wdata[23:0]; + up_tdd_rx_dp_on_2 <= up_wdata[23:0]; end if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h39)) begin + up_tdd_rx_dp_off_2 <= up_wdata[23:0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h3a)) begin + up_tdd_tx_dp_on_2 <= up_wdata[23:0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h3b)) begin up_tdd_tx_dp_off_2 <= up_wdata[23:0]; end end @@ -346,8 +371,7 @@ module up_tdd_cntrl ( 8'h11: up_rdata <= {24'h0, up_tdd_burst_count}; 8'h12: up_rdata <= { 8'h0, up_tdd_counter_init}; 8'h13: up_rdata <= { 8'h0, up_tdd_frame_length}; - 8'h14: up_rdata <= {30'h0, up_tdd_terminal_type, - up_tdd_sync_enable}; + 8'h14: up_rdata <= {31'h0, up_tdd_terminal_type}; 8'h18: up_rdata <= {24'h0, up_tdd_status_s}; 8'h20: up_rdata <= { 8'h0, up_tdd_vco_rx_on_1}; 8'h21: up_rdata <= { 8'h0, up_tdd_vco_rx_off_1}; @@ -357,8 +381,10 @@ module up_tdd_cntrl ( 8'h25: up_rdata <= { 8'h0, up_tdd_rx_off_1}; 8'h26: up_rdata <= { 8'h0, up_tdd_tx_on_1}; 8'h27: up_rdata <= { 8'h0, up_tdd_tx_off_1}; - 8'h28: up_rdata <= { 8'h0, up_tdd_tx_dp_on_1}; - 8'h29: up_rdata <= { 8'h0, up_tdd_tx_dp_off_1}; + 8'h28: up_rdata <= { 8'h0, up_tdd_rx_dp_on_1}; + 8'h29: up_rdata <= { 8'h0, up_tdd_rx_dp_off_1}; + 8'h2a: up_rdata <= { 8'h0, up_tdd_tx_dp_on_1}; + 8'h2b: up_rdata <= { 8'h0, up_tdd_tx_dp_off_1}; 8'h30: up_rdata <= { 8'h0, up_tdd_vco_rx_on_2}; 8'h31: up_rdata <= { 8'h0, up_tdd_vco_rx_off_2}; 8'h32: up_rdata <= { 8'h0, up_tdd_vco_tx_on_2}; @@ -367,8 +393,10 @@ module up_tdd_cntrl ( 8'h35: up_rdata <= { 8'h0, up_tdd_rx_off_2}; 8'h36: up_rdata <= { 8'h0, up_tdd_tx_on_2}; 8'h37: up_rdata <= { 8'h0, up_tdd_tx_off_2}; - 8'h38: up_rdata <= { 8'h0, up_tdd_tx_dp_on_2}; - 8'h39: up_rdata <= { 8'h0, up_tdd_tx_dp_off_2}; + 8'h38: up_rdata <= { 8'h0, up_tdd_rx_dp_on_2}; + 8'h39: up_rdata <= { 8'h0, up_tdd_rx_dp_off_2}; + 8'h3a: up_rdata <= { 8'h0, up_tdd_tx_dp_on_2}; + 8'h3b: up_rdata <= { 8'h0, up_tdd_tx_dp_off_2}; default: up_rdata <= 32'h0; endcase end @@ -377,7 +405,7 @@ module up_tdd_cntrl ( // rf tdd control signal CDC - up_xfer_cntrl #(.DATA_WIDTH(16)) i_xfer_tdd_control ( + up_xfer_cntrl #(.DATA_WIDTH(15)) i_xfer_tdd_control ( .up_rstn(up_rstn), .up_clk(up_clk), .up_data_cntrl({up_tdd_enable, @@ -387,9 +415,8 @@ module up_tdd_cntrl ( up_tdd_gated_rx_dmapath, up_tdd_gated_tx_dmapath, up_tdd_burst_count, - up_tdd_terminal_type, - up_tdd_sync_enable - }), + up_tdd_terminal_type + }), .up_xfer_done(), .d_rst(rst), .d_clk(clk), @@ -400,11 +427,10 @@ module up_tdd_cntrl ( tdd_gated_rx_dmapath, tdd_gated_tx_dmapath, tdd_burst_count, - tdd_terminal_type, - tdd_sync_enable + tdd_terminal_type })); - up_xfer_cntrl #(.DATA_WIDTH(528)) i_xfer_tdd_counter_values ( + up_xfer_cntrl #(.DATA_WIDTH(624)) i_xfer_tdd_counter_values ( .up_rstn(up_rstn), .up_clk(up_clk), .up_data_cntrl({up_tdd_counter_init, @@ -417,6 +443,8 @@ module up_tdd_cntrl ( up_tdd_rx_off_1, up_tdd_tx_on_1, up_tdd_tx_off_1, + up_tdd_rx_dp_on_1, + up_tdd_rx_dp_off_1, up_tdd_tx_dp_on_1, up_tdd_tx_dp_off_1, up_tdd_vco_rx_on_2, @@ -427,6 +455,8 @@ module up_tdd_cntrl ( up_tdd_rx_off_2, up_tdd_tx_on_2, up_tdd_tx_off_2, + up_tdd_rx_dp_on_2, + up_tdd_rx_dp_off_2, up_tdd_tx_dp_on_2, up_tdd_tx_dp_off_2 }), @@ -443,6 +473,8 @@ module up_tdd_cntrl ( tdd_rx_off_1, tdd_tx_on_1, tdd_tx_off_1, + tdd_rx_dp_on_1, + tdd_rx_dp_off_1, tdd_tx_dp_on_1, tdd_tx_dp_off_1, tdd_vco_rx_on_2, @@ -453,6 +485,8 @@ module up_tdd_cntrl ( tdd_rx_off_2, tdd_tx_on_2, tdd_tx_off_2, + tdd_rx_dp_on_2, + tdd_rx_dp_off_2, tdd_tx_dp_on_2, tdd_tx_dp_off_2 })); diff --git a/library/common/up_xcvr.v b/library/common/up_xcvr.v deleted file mode 100644 index 48d9b6b18..000000000 --- a/library/common/up_xcvr.v +++ /dev/null @@ -1,344 +0,0 @@ -// *************************************************************************** -// *************************************************************************** -// Copyright 2011(c) Analog Devices, Inc. -// -// All rights reserved. -// -// Redistribution and use in source and binary forms, with or without modification, -// are permitted provided that the following conditions are met: -// - Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// - Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in -// the documentation and/or other materials provided with the -// distribution. -// - Neither the name of Analog Devices, Inc. nor the names of its -// contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// - The use of this software may or may not infringe the patent rights -// of one or more patent holders. This license does not release you -// from the requirement that you obtain separate licenses from these -// patent holders to use this software. -// - Use of the software either in source or binary form, must be run -// on or directly connected to an Analog Devices Inc. component. -// -// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, -// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A -// PARTICULAR PURPOSE ARE DISCLAIMED. -// -// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY -// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF -// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// *************************************************************************** -// *************************************************************************** - -`timescale 1ns/100ps - -module up_xcvr ( - - // common reset - - rst, - - // receive interface - - rx_clk, - rx_rstn, - rx_ext_sysref, - rx_sysref, - rx_ip_sync, - rx_sync, - rx_status, - - // transmit interface - - tx_clk, - tx_rstn, - tx_ext_sysref, - tx_sysref, - tx_sync, - tx_ip_sync, - tx_status, - - // bus interface - - up_rstn, - up_clk, - up_wreq, - up_waddr, - up_wdata, - up_wack, - up_rreq, - up_raddr, - up_rdata, - up_rack); - - // parameters - - localparam PCORE_VERSION = 32'h00060162; - parameter ID = 0; - parameter DEVICE_TYPE = 0; - - // common reset - - output rst; - - // receive interface - - input rx_clk; - output rx_rstn; - input rx_ext_sysref; - output rx_sysref; - input rx_ip_sync; - output rx_sync; - input [ 7:0] rx_status; - - // transmit interface - - input tx_clk; - output tx_rstn; - input tx_ext_sysref; - output tx_sysref; - input tx_sync; - output tx_ip_sync; - input [ 7:0] tx_status; - - // bus interface - - input up_rstn; - input up_clk; - input up_wreq; - input [13:0] up_waddr; - input [31:0] up_wdata; - output up_wack; - input up_rreq; - input [13:0] up_raddr; - output [31:0] up_rdata; - output up_rack; - - // internal registers - - reg up_reset = 'd1; - reg up_rx_reset = 'd1; - reg up_tx_reset = 'd1; - reg up_wack = 'd0; - reg [31:0] up_scratch = 'd0; - reg up_resetn = 'd0; - reg up_rx_sysref_sel = 'd0; - reg up_rx_sysref = 'd0; - reg up_rx_sync = 'd0; - reg up_rx_resetn = 'd0; - reg up_tx_sysref_sel = 'd0; - reg up_tx_sysref = 'd0; - reg up_tx_sync = 'd0; - reg up_tx_resetn = 'd0; - reg up_rack = 'd0; - reg [31:0] up_rdata = 'd0; - reg rx_rstn = 'd0; - reg rx_sysref_sel_m1 = 'd0; - reg rx_sysref_sel = 'd0; - reg rx_up_sysref_m1 = 'd0; - reg rx_up_sysref = 'd0; - reg rx_sysref = 'd0; - reg rx_up_sync_m1 = 'd0; - reg rx_up_sync = 'd0; - reg rx_sync = 'd0; - reg tx_rstn = 'd0; - reg tx_sysref_sel_m1 = 'd0; - reg tx_sysref_sel = 'd0; - reg tx_up_sysref_m1 = 'd0; - reg tx_up_sysref = 'd0; - reg tx_sysref = 'd0; - reg tx_up_sync_m1 = 'd0; - reg tx_up_sync = 'd0; - reg tx_ip_sync = 'd0; - reg [ 8:0] up_rx_status_m1 = 'd0; - reg [ 8:0] up_rx_status = 'd0; - reg [ 8:0] up_tx_status_m1 = 'd0; - reg [ 8:0] up_tx_status = 'd0; - - // internal signals - - wire rx_rst; - wire tx_rst; - wire up_wreq_s; - wire up_rreq_s; - - // decode block select - - assign up_wreq_s = (up_waddr[13:8] == 6'h00) ? up_wreq : 1'b0; - assign up_rreq_s = (up_raddr[13:8] == 6'h00) ? up_rreq : 1'b0; - - // processor write interface - - always @(negedge up_rstn or posedge up_clk) begin - if (up_rstn == 0) begin - up_reset <= 1'b1; - up_rx_reset <= 1'b1; - up_tx_reset <= 1'b1; - up_wack <= 'd0; - up_scratch <= 'd0; - up_resetn <= 'd0; - up_rx_sysref_sel <= 'd0; - up_rx_sysref <= 'd0; - up_rx_sync <= 'd0; - up_rx_resetn <= 'd0; - up_tx_sysref_sel <= 'd0; - up_tx_sysref <= 'd0; - up_tx_sync <= 'd0; - up_tx_resetn <= 'd0; - end else begin - up_reset <= ~up_resetn; - up_rx_reset <= ~(up_resetn & up_rx_resetn); - up_tx_reset <= ~(up_resetn & up_tx_resetn); - up_wack <= up_wreq_s; - if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h02)) begin - up_scratch <= up_wdata; - end - if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h03)) begin - up_resetn <= up_wdata[0]; - end - if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h10)) begin - up_rx_sysref_sel <= up_wdata[1]; - up_rx_sysref <= up_wdata[0]; - end - if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h11)) begin - up_rx_sync <= up_wdata[0]; - end - if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h13)) begin - up_rx_resetn <= up_wdata[0]; - end - if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h20)) begin - up_tx_sysref_sel <= up_wdata[1]; - up_tx_sysref <= up_wdata[0]; - end - if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h21)) begin - up_tx_sync <= up_wdata[0]; - end - if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h23)) begin - up_tx_resetn <= up_wdata[0]; - end - end - end - - // processor read interface - - always @(negedge up_rstn or posedge up_clk) begin - if (up_rstn == 0) begin - up_rack <= 'd0; - up_rdata <= 'd0; - end else begin - up_rack <= up_rreq_s; - if (up_rreq_s == 1'b1) begin - case (up_raddr[7:0]) - 8'h00: up_rdata <= PCORE_VERSION; - 8'h01: up_rdata <= ID; - 8'h02: up_rdata <= up_scratch; - 8'h03: up_rdata <= {31'd0, up_resetn}; - 8'h10: up_rdata <= {30'd0, up_rx_sysref_sel, up_rx_sysref}; - 8'h11: up_rdata <= {31'd0, up_rx_sync}; - 8'h12: up_rdata <= {23'd0, up_rx_status}; - 8'h13: up_rdata <= {31'd0, up_rx_resetn}; - 8'h20: up_rdata <= {30'd0, up_tx_sysref_sel, up_tx_sysref}; - 8'h21: up_rdata <= {31'd0, up_tx_sync}; - 8'h22: up_rdata <= {23'd0, up_tx_status}; - 8'h23: up_rdata <= {31'd0, up_tx_resetn}; - 8'h30: up_rdata <= DEVICE_TYPE; - default: up_rdata <= 0; - endcase - end else begin - up_rdata <= 32'd0; - end - end - end - - // resets - - assign rst = up_reset; - - ad_rst i_rx_rst_reg (.preset(up_rx_reset), .clk(rx_clk), .rst(rx_rst)); - ad_rst i_tx_rst_reg (.preset(up_tx_reset), .clk(tx_clk), .rst(tx_rst)); - - // rx sysref & sync - - always @(posedge rx_clk or posedge rx_rst) begin - if (rx_rst == 1'b1) begin - rx_rstn <= 'd0; - rx_sysref_sel_m1 <= 'd0; - rx_sysref_sel <= 'd0; - rx_up_sysref_m1 <= 'd0; - rx_up_sysref <= 'd0; - rx_sysref <= 'd0; - rx_up_sync_m1 <= 'd0; - rx_up_sync <= 'd0; - rx_sync <= 'd0; - end else begin - rx_rstn <= 1'd1; - rx_sysref_sel_m1 <= up_rx_sysref_sel; - rx_sysref_sel <= rx_sysref_sel_m1; - rx_up_sysref_m1 <= up_rx_sysref; - rx_up_sysref <= rx_up_sysref_m1; - if (rx_sysref_sel == 1'b1) begin - rx_sysref <= rx_ext_sysref; - end else begin - rx_sysref <= rx_up_sysref; - end - rx_up_sync_m1 <= up_rx_sync; - rx_up_sync <= rx_up_sync_m1; - rx_sync <= rx_up_sync & rx_ip_sync; - end - end - - // tx sysref & sync - - always @(posedge tx_clk or posedge tx_rst) begin - if (tx_rst == 1'b1) begin - tx_rstn <= 'd0; - tx_sysref_sel_m1 <= 'd0; - tx_sysref_sel <= 'd0; - tx_up_sysref_m1 <= 'd0; - tx_up_sysref <= 'd0; - tx_sysref <= 'd0; - tx_up_sync_m1 <= 'd0; - tx_up_sync <= 'd0; - tx_ip_sync <= 'd0; - end else begin - tx_rstn <= 1'd1; - tx_sysref_sel_m1 <= up_tx_sysref_sel; - tx_sysref_sel <= tx_sysref_sel_m1; - tx_up_sysref_m1 <= up_tx_sysref; - tx_up_sysref <= tx_up_sysref_m1; - if (tx_sysref_sel == 1'b1) begin - tx_sysref <= tx_ext_sysref; - end else begin - tx_sysref <= tx_up_sysref; - end - tx_up_sync_m1 <= up_tx_sync; - tx_up_sync <= tx_up_sync_m1; - tx_ip_sync <= tx_up_sync & tx_sync; - end - end - - // status - - always @(negedge up_rstn or posedge up_clk) begin - if (up_rstn == 0) begin - up_rx_status_m1 <= 'd0; - up_rx_status <= 'd0; - up_tx_status_m1 <= 'd0; - up_tx_status <= 'd0; - end else begin - up_rx_status_m1 <= {rx_sync, rx_status}; - up_rx_status <= up_rx_status_m1; - up_tx_status_m1 <= {tx_ip_sync, tx_status}; - up_tx_status <= up_tx_status_m1; - end - end - -endmodule - -// *************************************************************************** -// *************************************************************************** diff --git a/library/common/ad_tdd_sync.v b/library/common/util_pulse_gen.v similarity index 70% rename from library/common/ad_tdd_sync.v rename to library/common/util_pulse_gen.v index 139768863..b9803ba18 100644 --- a/library/common/ad_tdd_sync.v +++ b/library/common/util_pulse_gen.v @@ -38,57 +38,55 @@ // *************************************************************************** `timescale 1ns/1ps -module ad_tdd_sync ( +module util_pulse_gen ( - clk, // system clock (100 Mhz) + clk, rstn, - sync // re-synchronization signal + pulse ); - localparam PULSE_CNTR_WIDTH = 7; - parameter TDD_SYNC_PERIOD = 100000000; // t_period * clk_freq - 1 + parameter PULSE_WIDTH = 7; + parameter PULSE_PERIOD = 100000000; // t_period * clk_freq input clk; input rstn; - output sync; + output pulse; // internal registers - reg [(PULSE_CNTR_WIDTH-1):0] pulse_counter = {PULSE_CNTR_WIDTH{1'b1}}; - reg [31:0] sync_counter = 32'h0; - reg sync_pulse = 1'b0; - reg sync_period_eof = 1'b0; + reg [(PULSE_WIDTH-1):0] pulse_width_cnt = {PULSE_WIDTH{1'b1}}; + reg [31:0] pulse_period_cnt = 32'h0; + reg pulse = 1'b0; - assign sync = sync_pulse; + wire end_of_period_s; - // a free running sync pulse generator + // a free running pulse generator always @(posedge clk) begin if (rstn == 1'b0) begin - sync_counter <= 32'h0; - sync_period_eof <= 1'b0; + pulse_period_cnt <= 32'h0; end else begin - sync_counter <= (sync_counter < TDD_SYNC_PERIOD) ? (sync_counter + 1) : 32'b0; - sync_period_eof <= (sync_counter == (TDD_SYNC_PERIOD - 1)) ? 1'b1 : 1'b0; + pulse_period_cnt <= (pulse_period_cnt < PULSE_PERIOD) ? (pulse_period_cnt + 1) : 32'b0; end end + assign end_of_period_s = (pulse_period_cnt == (PULSE_PERIOD - 1)) ? 1'b1 : 1'b0; + // generate pulse with a specified width always @(posedge clk) begin if (rstn == 1'b0) begin - pulse_counter <= 0; - sync_pulse <= 0; + pulse_width_cnt <= 0; + pulse <= 0; end else begin - pulse_counter <= (sync_pulse == 1'b1) ? pulse_counter + 1 : {PULSE_CNTR_WIDTH{1'h0}}; - if(sync_period_eof == 1'b1) begin - sync_pulse <= 1'b1; - end else if(pulse_counter == {PULSE_CNTR_WIDTH{1'b1}}) begin - sync_pulse <= 1'b0; + pulse_width_cnt <= (pulse == 1'b1) ? pulse_width_cnt + 1 : {PULSE_WIDTH{1'h0}}; + if(end_of_period_s == 1'b1) begin + pulse <= 1'b1; + end else if(pulse_width_cnt == {PULSE_WIDTH{1'b1}}) begin + pulse <= 1'b0; end end end endmodule - diff --git a/library/cordic_demod/Makefile b/library/cordic_demod/Makefile index 4b2891ff3..dc1ad70ef 100644 --- a/library/cordic_demod/Makefile +++ b/library/cordic_demod/Makefile @@ -5,10 +5,10 @@ #################################################################################### #################################################################################### -M_DEPS := cordic_demod_ip.tcl M_DEPS += ../scripts/adi_env.tcl M_DEPS += ../scripts/adi_ip.tcl M_DEPS += cordic_demod.v +M_DEPS += cordic_demod_ip.tcl M_VIVADO := vivado -mode batch -source @@ -19,6 +19,10 @@ M_FLIST += *.log M_FLIST += component.xml M_FLIST += *.jou M_FLIST += xgui +M_FLIST += *.ip_user_files +M_FLIST += *.srcs +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil @@ -35,7 +39,7 @@ clean-all: cordic_demod.xpr: $(M_DEPS) - rm -rf $(M_FLIST) + -rm -rf $(M_FLIST) $(M_VIVADO) cordic_demod_ip.tcl >> cordic_demod_ip.log 2>&1 #################################################################################### diff --git a/library/cordic_demod/cordic_demod.v b/library/cordic_demod/cordic_demod.v index bb2e25e41..49b1fd474 100644 --- a/library/cordic_demod/cordic_demod.v +++ b/library/cordic_demod/cordic_demod.v @@ -1,14 +1,14 @@ module cordic_demod ( - input clk, - input resetn, + input clk, + input resetn, - input s_axis_valid, - output s_axis_ready, - input [63:0] s_axis_data, + input s_axis_valid, + output s_axis_ready, + input [63:0] s_axis_data, - output m_axis_valid, - input m_axis_ready, - output [63:0] m_axis_data + output m_axis_valid, + input m_axis_ready, + output [63:0] m_axis_data ); reg [4:0] step_counter; @@ -34,135 +34,135 @@ localparam STATE_DONE = 4; reg [31:0] angle[0:30]; initial begin - angle[0] = 32'h20000000; - angle[1] = 32'h12e4051e; - angle[2] = 32'h09fb385b; - angle[3] = 32'h051111d4; - angle[4] = 32'h028b0d43; - angle[5] = 32'h0145d7e1; - angle[6] = 32'h00a2f61e; - angle[7] = 32'h00517c55; - angle[8] = 32'h0028be53; - angle[9] = 32'h00145f2f; - angle[10] = 32'h000a2f98; - angle[11] = 32'h000517cc; - angle[12] = 32'h00028be6; - angle[13] = 32'h000145f3; - angle[14] = 32'h0000a2fa; - angle[15] = 32'h0000517d; - angle[16] = 32'h000028be; - angle[17] = 32'h0000145f; - angle[18] = 32'h00000a30; - angle[19] = 32'h00000518; - angle[20] = 32'h0000028c; - angle[21] = 32'h00000146; - angle[22] = 32'h000000a3; - angle[23] = 32'h00000051; - angle[24] = 32'h00000029; - angle[25] = 32'h00000014; - angle[26] = 32'h0000000a; - angle[27] = 32'h00000005; - angle[28] = 32'h00000003; - angle[29] = 32'h00000001; - angle[30] = 32'h00000001; + angle[0] = 32'h20000000; + angle[1] = 32'h12e4051e; + angle[2] = 32'h09fb385b; + angle[3] = 32'h051111d4; + angle[4] = 32'h028b0d43; + angle[5] = 32'h0145d7e1; + angle[6] = 32'h00a2f61e; + angle[7] = 32'h00517c55; + angle[8] = 32'h0028be53; + angle[9] = 32'h00145f2f; + angle[10] = 32'h000a2f98; + angle[11] = 32'h000517cc; + angle[12] = 32'h00028be6; + angle[13] = 32'h000145f3; + angle[14] = 32'h0000a2fa; + angle[15] = 32'h0000517d; + angle[16] = 32'h000028be; + angle[17] = 32'h0000145f; + angle[18] = 32'h00000a30; + angle[19] = 32'h00000518; + angle[20] = 32'h0000028c; + angle[21] = 32'h00000146; + angle[22] = 32'h000000a3; + angle[23] = 32'h00000051; + angle[24] = 32'h00000029; + angle[25] = 32'h00000014; + angle[26] = 32'h0000000a; + angle[27] = 32'h00000005; + angle[28] = 32'h00000003; + angle[29] = 32'h00000001; + angle[30] = 32'h00000001; end always @(posedge clk) begin - if (resetn == 1'b0) begin - state <= STATE_IDLE; - end else begin - case (state) - STATE_IDLE: begin - if (s_axis_valid == 1'b1) begin - state <= STATE_SHIFT_LOAD; - end - end - STATE_SHIFT_LOAD: begin - if (step_counter == 'h00) begin - state <= STATE_ADD; - end else begin - state <= STATE_SHIFT; - end - end - STATE_SHIFT: begin - if (shift_counter == 'h01) begin - state <= STATE_ADD; - end - end - STATE_ADD: begin - if (step_counter == 'd30) begin - state <= STATE_DONE; - end else begin - state <= STATE_SHIFT_LOAD; - end - end - STATE_DONE: begin - if (m_axis_ready == 1'b1) - state <= STATE_IDLE; - end - endcase - end + if (resetn == 1'b0) begin + state <= STATE_IDLE; + end else begin + case (state) + STATE_IDLE: begin + if (s_axis_valid == 1'b1) begin + state <= STATE_SHIFT_LOAD; + end + end + STATE_SHIFT_LOAD: begin + if (step_counter == 'h00) begin + state <= STATE_ADD; + end else begin + state <= STATE_SHIFT; + end + end + STATE_SHIFT: begin + if (shift_counter == 'h01) begin + state <= STATE_ADD; + end + end + STATE_ADD: begin + if (step_counter == 'd30) begin + state <= STATE_DONE; + end else begin + state <= STATE_SHIFT_LOAD; + end + end + STATE_DONE: begin + if (m_axis_ready == 1'b1) + state <= STATE_IDLE; + end + endcase + end end always @(posedge clk) begin - case(state) - STATE_SHIFT_LOAD: begin - shift_counter <= step_counter; - end - STATE_SHIFT: begin - shift_counter <= shift_counter - 1'b1; - end - endcase + case(state) + STATE_SHIFT_LOAD: begin + shift_counter <= step_counter; + end + STATE_SHIFT: begin + shift_counter <= shift_counter - 1'b1; + end + endcase end always @(posedge clk) begin - case(state) - STATE_IDLE: - if (s_axis_valid == 1'b1) begin - step_counter <= 'h00; - phase <= {1'b0,s_axis_data[61:32]}; - step_counter <= 'h00; - case (s_axis_data[63:62]) - 2'b00: begin - i <= {s_axis_data[31],s_axis_data[31:0]}; - q <= 'h00; - end - 2'b01: begin - i <= 'h00; - q <= ~{s_axis_data[31],s_axis_data[31:0]}; - end - 2'b10: begin - i <= ~{s_axis_data[31],s_axis_data[31:0]}; - q <= 'h00; - end - 2'b11: begin - i <= 'h00; - q <= {s_axis_data[31],s_axis_data[31:0]}; - end - endcase - end - STATE_SHIFT_LOAD: begin - i_shift <= i; - q_shift <= q; - end - STATE_SHIFT: begin - i_shift <= {i_shift[32],i_shift[32:1]}; - q_shift <= {q_shift[32],q_shift[32:1]}; - end - STATE_ADD: begin - if (phase[30] == 1'b0) begin - i <= i + q_shift; - q <= q - i_shift; - phase <= phase - angle[step_counter]; - end else begin - i <= i - q_shift; - q <= q + i_shift; - phase <= phase + angle[step_counter]; - end - step_counter <= step_counter + 1'b1; - end - endcase + case(state) + STATE_IDLE: + if (s_axis_valid == 1'b1) begin + step_counter <= 'h00; + phase <= {1'b0,s_axis_data[61:32]}; + step_counter <= 'h00; + case (s_axis_data[63:62]) + 2'b00: begin + i <= {s_axis_data[31],s_axis_data[31:0]}; + q <= 'h00; + end + 2'b01: begin + i <= 'h00; + q <= ~{s_axis_data[31],s_axis_data[31:0]}; + end + 2'b10: begin + i <= ~{s_axis_data[31],s_axis_data[31:0]}; + q <= 'h00; + end + 2'b11: begin + i <= 'h00; + q <= {s_axis_data[31],s_axis_data[31:0]}; + end + endcase + end + STATE_SHIFT_LOAD: begin + i_shift <= i; + q_shift <= q; + end + STATE_SHIFT: begin + i_shift <= {i_shift[32],i_shift[32:1]}; + q_shift <= {q_shift[32],q_shift[32:1]}; + end + STATE_ADD: begin + if (phase[30] == 1'b0) begin + i <= i + q_shift; + q <= q - i_shift; + phase <= phase - angle[step_counter]; + end else begin + i <= i - q_shift; + q <= q + i_shift; + phase <= phase + angle[step_counter]; + end + step_counter <= step_counter + 1'b1; + end + endcase end endmodule diff --git a/library/interfaces/Makefile b/library/interfaces/Makefile index 996cec8d9..e7165b29f 100644 --- a/library/interfaces/Makefile +++ b/library/interfaces/Makefile @@ -13,6 +13,10 @@ M_VIVADO := vivado -mode batch -source M_FLIST := *.log M_FLIST += *.jou +M_FLIST += if_xcvr_cm.xml +M_FLIST += if_xcvr_cm_rtl.xml +M_FLIST += if_xcvr_ch.xml +M_FLIST += if_xcvr_ch_rtl.xml M_FLIST += if_gt_qpll.xml M_FLIST += if_gt_qpll_rtl.xml M_FLIST += if_gt_pll.xml @@ -26,13 +30,25 @@ M_FLIST += if_gt_rx_ksig_rtl.xml .PHONY: all clean clean-all -all: if_gt_qpll.xml if_gt_qpll_rtl.xml if_gt_pll.xml if_gt_pll_rtl.xml if_gt_rx.xml if_gt_rx_rtl.xml if_gt_tx.xml if_gt_tx_rtl.xml if_gt_rx_ksig.xml if_gt_rx_ksig_rtl.xml +all: if_xcvr_cm.xml if_xcvr_cm_rtl.xml if_xcvr_ch.xml if_xcvr_ch_rtl.xml if_gt_qpll.xml if_gt_qpll_rtl.xml if_gt_pll.xml if_gt_pll_rtl.xml if_gt_rx.xml if_gt_rx_rtl.xml if_gt_tx.xml if_gt_tx_rtl.xml if_gt_rx_ksig.xml if_gt_rx_ksig_rtl.xml clean:clean-all clean-all: rm -rf $(M_FLIST) +if_xcvr_cm.xml: + $(M_VIVADO) interfaces_ip.tcl >> interfaces_ip.log 2>&1 + +if_xcvr_cm_rtl.xml: + $(M_VIVADO) interfaces_ip.tcl >> interfaces_ip.log 2>&1 + +if_xcvr_ch.xml: + $(M_VIVADO) interfaces_ip.tcl >> interfaces_ip.log 2>&1 + +if_xcvr_ch_rtl.xml: + $(M_VIVADO) interfaces_ip.tcl >> interfaces_ip.log 2>&1 + if_gt_qpll.xml: $(M_VIVADO) interfaces_ip.tcl >> interfaces_ip.log 2>&1 diff --git a/library/interfaces/interfaces_ip.tcl b/library/interfaces/interfaces_ip.tcl index 6b3c4dc15..18a15f478 100644 --- a/library/interfaces/interfaces_ip.tcl +++ b/library/interfaces/interfaces_ip.tcl @@ -3,6 +3,32 @@ source ../scripts/adi_env.tcl source $ad_hdl_dir/library/scripts/adi_ip.tcl +adi_if_define if_xcvr_cm +adi_if_ports output 8 sel +adi_if_ports output 1 enb +adi_if_ports output 12 addr +adi_if_ports output 1 wr +adi_if_ports output 16 wdata +adi_if_ports input 16 rdata +adi_if_ports input 1 ready + +adi_if_define if_xcvr_ch +adi_if_ports input 1 pll_locked +adi_if_ports output 1 rst +adi_if_ports output 1 user_ready +adi_if_ports input 1 rst_done +adi_if_ports output 1 lpm_dfe_n +adi_if_ports output 3 rate +adi_if_ports output 2 sys_clk_sel +adi_if_ports output 3 out_clk_sel +adi_if_ports output 8 sel +adi_if_ports output 1 enb +adi_if_ports output 12 addr +adi_if_ports output 1 wr +adi_if_ports output 16 wdata +adi_if_ports input 16 rdata +adi_if_ports input 1 ready + adi_if_define if_gt_qpll adi_if_ports output 1 qpll_rst reset adi_if_ports output 1 qpll_ref_clk clock diff --git a/library/scripts/adi_ip.tcl b/library/scripts/adi_ip.tcl index f9d416a59..9d5b5ebff 100644 --- a/library/scripts/adi_ip.tcl +++ b/library/scripts/adi_ip.tcl @@ -2,7 +2,7 @@ # check tool version if {![info exists REQUIRED_VIVADO_VERSION]} { - set REQUIRED_VIVADO_VERSION "2015.4.2" + set REQUIRED_VIVADO_VERSION "2016.2" } if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { @@ -26,6 +26,11 @@ proc adi_ip_create {ip_name} { create_project $ip_name . -force + set_msg_config -id {IP_Flow 19-3656} -new_severity INFO + set_msg_config -id {IP_Flow 19-2999} -new_severity INFO + set_msg_config -id {IP_Flow 19-1654} -new_severity INFO + set_msg_config -id {IP_Flow 19-459} -new_severity INFO + set lib_dirs $ad_hdl_dir/library if {$ad_hdl_dir ne $ad_phdl_dir} { lappend lib_dirs $ad_phdl_dir/library @@ -77,33 +82,8 @@ proc adi_ip_bd {ip_name ip_bd_files} { proc adi_ip_properties {ip_name} { - ipx::package_project -root_dir . + adi_ip_properties_lite $ip_name - set_property vendor {analog.com} [ipx::current_core] - set_property library {user} [ipx::current_core] - set_property taxonomy {{/AXI_Infrastructure}} [ipx::current_core] - set_property vendor_display_name {Analog Devices} [ipx::current_core] - set_property company_url {www.analog.com} [ipx::current_core] - - set_property supported_families \ - {{kintexu} {Pre-Production} \ - {virtexu} {Pre-Production} \ - {virtex7} {Production} \ - {qvirtex7} {Production} \ - {kintex7} {Production} \ - {kintex7l} {Production} \ - {qkintex7} {Production} \ - {qkintex7l} {Production} \ - {artix7} {Production} \ - {artix7l} {Production} \ - {aartix7} {Production} \ - {qartix7} {Production} \ - {zynq} {Production} \ - {qzynq} {Production} \ - {azynq} {Production}} \ - [ipx::current_core] - - ipx::remove_all_bus_interface [ipx::current_core] ipx::infer_bus_interface {\ s_axi_awvalid \ s_axi_awaddr \ @@ -138,108 +118,141 @@ proc adi_ip_properties {ip_name} { set_property value s_axi [ipx::get_bus_parameters ASSOCIATED_BUSIF \ -of_objects [ipx::get_bus_interfaces s_axi_aclk \ -of_objects [ipx::current_core]]] +} + +proc adi_ip_infer_streaming_interfaces {ip_name} { + + ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] + +} + +proc adi_ip_infer_mm_interfaces {ip_name} { + + ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] - ipx::infer_bus_interfaces xilinx.com:interface:clock_rtl:1.0 [ipx::current_core] - ipx::infer_bus_interfaces xilinx.com:interface:reset_rtl:1.0 [ipx::current_core] - ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] - ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] } proc adi_ip_properties_lite {ip_name} { - ipx::package_project -root_dir . + ipx::package_project -root_dir . \ + -vendor analog.com \ + -library user \ + -taxonomy /Analog_Devices - set_property vendor {analog.com} [ipx::current_core] - set_property library {user} [ipx::current_core] - set_property taxonomy {{/AXI_Infrastructure}} [ipx::current_core] set_property vendor_display_name {Analog Devices} [ipx::current_core] set_property company_url {www.analog.com} [ipx::current_core] - set_property supported_families \ - {{kintexu} {Pre-Production} \ - {virtexu} {Pre-Production} \ - {virtex7} {Production} \ - {qvirtex7} {Production} \ - {kintex7} {Production} \ - {kintex7l} {Production} \ - {qkintex7} {Production} \ - {qkintex7l} {Production} \ - {artix7} {Production} \ - {artix7l} {Production} \ - {aartix7} {Production} \ - {qartix7} {Production} \ - {zynq} {Production} \ - {qzynq} {Production} \ - {azynq} {Production}} \ + set_property supported_families {\ + virtex7 Production \ + qvirtex7 Production \ + kintex7 Production \ + kintex7l Production \ + qkintex7 Production \ + qkintex7l Production \ + artix7 Production \ + artix7l Production \ + aartix7 Production \ + qartix7 Production \ + zynq Production \ + qzynq Production \ + azynq Production \ + virtexu Production \ + kintexuplus Production \ + zynquplus Production \ + kintexu Production \ + virtex7 Beta \ + qvirtex7 Beta \ + kintex7 Beta \ + kintex7l Beta \ + qkintex7 Beta \ + qkintex7l Beta \ + artix7 Beta \ + artix7l Beta \ + aartix7 Beta \ + qartix7 Beta \ + zynq Beta \ + qzynq Beta \ + azynq Beta \ + virtexu Beta \ + virtexuplus Beta \ + kintexuplus Beta \ + zynquplus Beta \ + kintexu Beta}\ [ipx::current_core] + + ipx::remove_all_bus_interface [ipx::current_core] + set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] + foreach map $memory_maps { + ipx::remove_memory_map [lindex $map 2] [ipx::current_core ] + } } proc adi_set_ports_dependency {port_prefix dependency} { - foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { - set_property ENABLEMENT_DEPENDENCY $dependency $port - } + foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { + set_property ENABLEMENT_DEPENDENCY $dependency $port + } } proc adi_set_bus_dependency {bus prefix dependency} { - set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] - adi_set_ports_dependency $prefix $dependency + set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] + adi_set_ports_dependency $prefix $dependency } proc adi_add_port_map {bus phys logic} { - set map [ipx::add_port_map $phys $bus] - set_property "PHYSICAL_NAME" $phys $map - set_property "LOGICAL_NAME" $logic $map + set map [ipx::add_port_map $phys $bus] + set_property "PHYSICAL_NAME" $phys $map + set_property "LOGICAL_NAME" $logic $map } proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { - set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] + set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] - set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus - set_property "BUS_TYPE_VLNV" $bus_type $bus - set_property "INTERFACE_MODE" $mode $bus + set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus + set_property "BUS_TYPE_VLNV" $bus_type $bus + set_property "INTERFACE_MODE" $mode $bus - foreach port_map $port_maps { - adi_add_port_map $bus {*}$port_map - } + foreach port_map $port_maps { + adi_add_port_map $bus {*}$port_map + } } proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { - set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] - set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] - set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] - set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf - set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf - set_property display_name $clock_inf_name $clock_inf - set clock_map [ipx::add_port_map "CLK" $clock_inf] - set_property physical_name $clock_signal_name $clock_map + set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] + set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] + set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] + set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf + set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf + set_property display_name $clock_inf_name $clock_inf + set clock_map [ipx::add_port_map "CLK" $clock_inf] + set_property physical_name $clock_signal_name $clock_map - set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] - set_property value $bus_inf_name $assoc_busif + set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] + set_property value $bus_inf_name $assoc_busif - if { $reset_signal_name != "" } { - set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] - set_property value $reset_signal_name $assoc_reset + if { $reset_signal_name != "" } { + set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] + set_property value $reset_signal_name $assoc_reset - set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] - set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] - set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf - set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf - set_property display_name $reset_inf_name $reset_inf - set_property interface_mode $reset_signal_mode $reset_inf - set reset_map [ipx::add_port_map "RST" $reset_inf] - set_property physical_name $reset_signal_name $reset_map + set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] + set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] + set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf + set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf + set_property display_name $reset_inf_name $reset_inf + set_property interface_mode $reset_signal_mode $reset_inf + set reset_map [ipx::add_port_map "RST" $reset_inf] + set_property physical_name $reset_signal_name $reset_map - set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] - set_property value "ACTIVE_LOW" $reset_polarity - } + set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] + set_property value "ACTIVE_LOW" $reset_polarity + } } proc adi_ip_add_core_dependencies {vlnvs} { - foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { - foreach vlnv $vlnvs { - ipx::add_subcore $vlnv $file_group - } - } + foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { + foreach vlnv $vlnvs { + ipx::add_subcore $vlnv $file_group + } + } } proc adi_if_define {name} { diff --git a/library/scripts/adi_ip_alt.tcl b/library/scripts/adi_ip_alt.tcl index 3967f0a08..4cfb9b142 100644 --- a/library/scripts/adi_ip_alt.tcl +++ b/library/scripts/adi_ip_alt.tcl @@ -1,28 +1,29 @@ - +################################################################################################### +################################################################################################### # keep interface-mess out of the way - keeping it pretty is a waste of time proc ad_alt_intf {type name dir width {arg_1 ""} {arg_2 ""}} { - if {(($type eq "clock") && ($dir eq "input"))} { + if {([string equal -nocase ${type} "clock"]) && ([string equal -nocase ${dir} "input"])} { add_interface if_${name} clock sink add_interface_port if_${name} ${name} clk ${dir} ${width} return } - if {(($type eq "clock") && ($dir eq "output"))} { + if {([string equal -nocase ${type} "clock"]) && ([string equal -nocase ${dir} "output"])} { add_interface if_${name} clock source add_interface_port if_${name} ${name} clk ${dir} ${width} return } - if {(($type eq "reset") && ($dir eq "input"))} { + if {([string equal -nocase ${type} "reset"]) && ([string equal -nocase ${dir} "input"])} { add_interface if_${name} reset sink add_interface_port if_${name} ${name} reset ${dir} ${width} set_interface_property if_${name} associatedclock ${arg_1} return } - if {(($type eq "reset") && ($dir eq "output"))} { + if {([string equal -nocase ${type} "reset"]) && ([string equal -nocase ${dir} "output"])} { add_interface if_${name} reset source add_interface_port if_${name} ${name} reset ${dir} ${width} set_interface_property if_${name} associatedclock ${arg_1} @@ -30,14 +31,14 @@ proc ad_alt_intf {type name dir width {arg_1 ""} {arg_2 ""}} { return } - if {(($type eq "reset-n") && ($dir eq "input"))} { + if {([string equal -nocase ${type} "reset-n"]) && ([string equal -nocase ${dir} "input"])} { add_interface if_${name} reset sink add_interface_port if_${name} ${name} reset_n ${dir} ${width} set_interface_property if_${name} associatedclock ${arg_1} return } - if {(($type eq "reset-n") && ($dir eq "output"))} { + if {([string equal -nocase ${type} "reset-n"]) && ([string equal -nocase ${dir} "output"])} { add_interface if_${name} reset source add_interface_port if_${name} ${name} reset_n ${dir} ${width} set_interface_property if_${name} associatedclock ${arg_1} @@ -45,7 +46,7 @@ proc ad_alt_intf {type name dir width {arg_1 ""} {arg_2 ""}} { return } - if {(($type eq "intr") && ($dir eq "output"))} { + if {([string equal -nocase ${type} "intr"]) && ([string equal -nocase ${dir} "output"])} { add_interface if_${name} interrupt source add_interface_port if_${name} ${name} irq ${dir} ${width} set_interface_property if_${name} associatedclock ${arg_1} @@ -57,10 +58,181 @@ proc ad_alt_intf {type name dir width {arg_1 ""} {arg_2 ""}} { set remap $name } - if {$type eq "signal"} { + if {[string equal -nocase ${type} "signal"]} { add_interface if_${name} conduit end add_interface_port if_${name} ${name} ${remap} ${dir} ${width} return } } +proc ad_conduit {if_name if_port port dir width} { + + add_interface $if_name conduit end + add_interface_port $if_name $port $if_port $dir $width +} + +proc ad_generate_module_inst { inst_name mark source_file target_file } { + + set fp_source [open $source_file "r"] + set fp_target [open $target_file "w+"] + + fconfigure $fp_source -buffering line + + while { [gets $fp_source data] >= 0 } { + + # update the required module name + regsub $inst_name $data "&_$mark" data + puts $data + puts $fp_target $data + } + + close $fp_source + close $fp_target +} + +################################################################################################### +################################################################################################### + +proc ad_ip_create {pname pdesc {pelabfunction ""} {pcomposefunction ""}} { + + set_module_property NAME $pname + set_module_property DESCRIPTION $pdesc + set_module_property VERSION 1.0 + set_module_property GROUP "Analog Devices" + set_module_property DISPLAY_NAME $pname + + if {$pelabfunction ne ""} { + set_module_property ELABORATION_CALLBACK $pelabfunction + } + + if {$pcomposefunction ne ""} { + set_module_property COMPOSITION_CALLBACK $pcomposefunction + } +} + +################################################################################################### +################################################################################################### + +proc ad_ip_parameter {pname ptype pdefault} { + + if {$pname eq "DEVICE_FAMILY"} { + add_parameter DEVICE_FAMILY STRING + set_parameter_property DEVICE_FAMILY SYSTEM_INFO {DEVICE_FAMILY} + set_parameter_property DEVICE_FAMILY AFFECTS_GENERATION true + set_parameter_property DEVICE_FAMILY HDL_PARAMETER false + set_parameter_property DEVICE_FAMILY ENABLED false + return + } + + add_parameter $pname $ptype $pdefault + set_parameter_property $pname HDL_PARAMETER true + set_parameter_property $pname ENABLED true +} + +################################################################################################### +################################################################################################### + +proc ad_ip_addfile {pname pfile} { + + set pmodule [file tail $pfile] + + regsub {\..$} $pmodule {} mname + if {$pname eq $mname} { + add_fileset_file $pmodule VERILOG PATH $pfile TOP_LEVEL_FILE + return + } + + set ptype [file extension $pfile] + if {$ptype eq ".v"} { + add_fileset_file $pmodule VERILOG PATH $pfile + return + } + if {$ptype eq ".sdc"} { + add_fileset_file $pmodule SDC PATH $pfile + return + } +} + +proc ad_ip_files {pname pfiles {pfunction ""}} { + + add_fileset quartus_synth QUARTUS_SYNTH $pfunction "" + set_fileset_property quartus_synth TOP_LEVEL $pname + foreach pfile $pfiles { + ad_ip_addfile $pname $pfile + } + + add_fileset quartus_sim SIM_VERILOG $pfunction "" + set_fileset_property quartus_sim TOP_LEVEL $pname + foreach pfile $pfiles { + ad_ip_addfile $pname $pfile + } +} + +################################################################################################### +################################################################################################### + +proc ad_ip_intf_s_axi {aclk arstn} { + + add_interface s_axi_clock clock end + add_interface_port s_axi_clock ${aclk} clk Input 1 + + add_interface s_axi_reset reset end + set_interface_property s_axi_reset associatedClock s_axi_clock + add_interface_port s_axi_reset ${arstn} reset_n Input 1 + + add_interface s_axi axi4lite end + set_interface_property s_axi associatedClock s_axi_clock + set_interface_property s_axi associatedReset s_axi_reset + add_interface_port s_axi s_axi_awvalid awvalid Input 1 + add_interface_port s_axi s_axi_awaddr awaddr Input 16 + add_interface_port s_axi s_axi_awprot awprot Input 3 + add_interface_port s_axi s_axi_awready awready Output 1 + add_interface_port s_axi s_axi_wvalid wvalid Input 1 + add_interface_port s_axi s_axi_wdata wdata Input 32 + add_interface_port s_axi s_axi_wstrb wstrb Input 4 + add_interface_port s_axi s_axi_wready wready Output 1 + add_interface_port s_axi s_axi_bvalid bvalid Output 1 + add_interface_port s_axi s_axi_bresp bresp Output 2 + add_interface_port s_axi s_axi_bready bready Input 1 + add_interface_port s_axi s_axi_arvalid arvalid Input 1 + add_interface_port s_axi s_axi_araddr araddr Input 16 + add_interface_port s_axi s_axi_arprot arprot Input 3 + add_interface_port s_axi s_axi_arready arready Output 1 + add_interface_port s_axi s_axi_rvalid rvalid Output 1 + add_interface_port s_axi s_axi_rresp rresp Output 2 + add_interface_port s_axi s_axi_rdata rdata Output 32 + add_interface_port s_axi s_axi_rready rready Input 1 +} + +################################################################################################### +################################################################################################### + +proc ad_ip_modfile {ifile ofile flist} { + + global ad_hdl_dir + + set srcfile [open ${ad_hdl_dir}/library/altera/common/${ifile} r] + set dstfile [open ${ofile} w] + + regsub {\..$} $ifile {} imodule + regsub {\..$} $ofile {} omodule + + while {[gets $srcfile srcline] >= 0} { + regsub __${imodule}__ $srcline $omodule dstline + set index 0 + foreach fword $flist { + incr index + regsub __${imodule}_${index}__ $dstline $fword dstline + } + puts $dstfile $dstline + } + + close $srcfile + close $dstfile + + ad_ip_addfile ad_ip_addfile $ofile +} + +################################################################################################### +################################################################################################### + diff --git a/library/spi_engine/axi_spi_engine/Makefile b/library/spi_engine/axi_spi_engine/Makefile index def1365cf..1f3e10406 100644 --- a/library/spi_engine/axi_spi_engine/Makefile +++ b/library/spi_engine/axi_spi_engine/Makefile @@ -5,16 +5,22 @@ #################################################################################### #################################################################################### -M_DEPS := axi_spi_engine_ip.tcl -M_DEPS += ../../scripts/adi_env.tcl -M_DEPS += ../../scripts/adi_ip.tcl -M_DEPS += axi_spi_engine.v +M_DEPS += ../../common/ad_rst.v M_DEPS += ../../common/sync_bits.v M_DEPS += ../../common/sync_gray.v M_DEPS += ../../common/up_axi.v -M_DEPS += ../../common/ad_rst.v +M_DEPS += ../../scripts/adi_env.tcl +M_DEPS += ../../scripts/adi_ip.tcl +M_DEPS += axi_spi_engine.v +M_DEPS += axi_spi_engine_ip.tcl + M_DEPS += ../../util_axis_fifo/util_axis_fifo.xpr +M_DEPS += ../../spi_engine/interfaces/spi_engine_ctrl.xml +M_DEPS += ../../spi_engine/interfaces/spi_engine_ctrl_rtl.xml +M_DEPS += ../../spi_engine/interfaces/spi_engine_offload_ctrl.xml +M_DEPS += ../../spi_engine/interfaces/spi_engine_offload_ctrl_rtl.xml + M_VIVADO := vivado -mode batch -source M_FLIST := *.cache @@ -24,6 +30,10 @@ M_FLIST += *.log M_FLIST += component.xml M_FLIST += *.jou M_FLIST += xgui +M_FLIST += *.ip_user_files +M_FLIST += *.srcs +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil @@ -40,10 +50,10 @@ clean-all: axi_spi_engine.xpr: $(M_DEPS) - rm -rf $(M_FLIST) + -rm -rf $(M_FLIST) $(M_VIVADO) axi_spi_engine_ip.tcl >> axi_spi_engine_ip.log 2>&1 dep: - make -C ../../util_axis_fifo + make -C ../../util_axis_fifo/ #################################################################################### #################################################################################### diff --git a/library/spi_engine/axi_spi_engine/axi_spi_engine.v b/library/spi_engine/axi_spi_engine/axi_spi_engine.v index 35bf015e5..875654d14 100644 --- a/library/spi_engine/axi_spi_engine/axi_spi_engine.v +++ b/library/spi_engine/axi_spi_engine/axi_spi_engine.v @@ -1,68 +1,82 @@ module axi_spi_engine ( - // Slave AXI interface - input s_axi_aclk, - input s_axi_aresetn, + // Slave AXI interface - input s_axi_awvalid, - input [31:0] s_axi_awaddr, - output s_axi_awready, - input [2:0] s_axi_awprot, - input s_axi_wvalid, - input [31:0] s_axi_wdata, - input [ 3:0] s_axi_wstrb, - output s_axi_wready, - output s_axi_bvalid, - output [ 1:0] s_axi_bresp, - input s_axi_bready, - input s_axi_arvalid, - input [31:0] s_axi_araddr, - output s_axi_arready, - input [2:0] s_axi_arprot, - output s_axi_rvalid, - input s_axi_rready, - output [ 1:0] s_axi_rresp, - output [31:0] s_axi_rdata, + input s_axi_aclk, + input s_axi_aresetn, + input s_axi_awvalid, + input [31:0] s_axi_awaddr, + output s_axi_awready, + input [2:0] s_axi_awprot, + input s_axi_wvalid, + input [31:0] s_axi_wdata, + input [ 3:0] s_axi_wstrb, + output s_axi_wready, + output s_axi_bvalid, + output [ 1:0] s_axi_bresp, + input s_axi_bready, + input s_axi_arvalid, + input [31:0] s_axi_araddr, + output s_axi_arready, + input [2:0] s_axi_arprot, + output s_axi_rvalid, + input s_axi_rready, + output [ 1:0] s_axi_rresp, + output [31:0] s_axi_rdata, - output reg irq, + // up interface + input up_clk, + input up_rstn, + input up_wreq, + input [(UP_ADDRESS_WIDTH-1):0] up_waddr, + input [31:0] up_wdata, + output up_wack, + input up_rreq, + input [(UP_ADDRESS_WIDTH-1):0] up_raddr, + output [31:0] up_rdata, + output up_rack, - // SPI signals - input spi_clk, + output reg irq, - output spi_resetn, + // SPI signals + input spi_clk, - input cmd_ready, - output cmd_valid, - output [15:0] cmd_data, + output spi_resetn, - input sdo_data_ready, - output sdo_data_valid, - output [7:0] sdo_data, + input cmd_ready, + output cmd_valid, + output [15:0] cmd_data, - output sdi_data_ready, - input sdi_data_valid, - input [7:0] sdi_data, + input sdo_data_ready, + output sdo_data_valid, + output [(DATA_WIDTH-1):0] sdo_data, - output sync_ready, - input sync_valid, - input [7:0] sync_data, + output sdi_data_ready, + input sdi_data_valid, + input [(NUM_OF_SDI * DATA_WIDTH-1):0] sdi_data, - // Offload ctrl signals - output offload0_cmd_wr_en, - output [15:0] offload0_cmd_wr_data, + output sync_ready, + input sync_valid, + input [7:0] sync_data, - output offload0_sdo_wr_en, - output [7:0] offload0_sdo_wr_data, + // Offload ctrl signals + output offload0_cmd_wr_en, + output [15:0] offload0_cmd_wr_data, - output reg offload0_mem_reset, - output reg offload0_enable, - input offload0_enabled + output offload0_sdo_wr_en, + output [(DATA_WIDTH-1):0] offload0_sdo_wr_data, + + output reg offload0_mem_reset, + output reg offload0_enable, + input offload0_enabled ); parameter CMD_FIFO_ADDRESS_WIDTH = 4; parameter SDO_FIFO_ADDRESS_WIDTH = 5; parameter SDI_FIFO_ADDRESS_WIDTH = 5; +parameter MM_IF_TYPE = 0; +parameter UP_ADDRESS_WIDTH = 14; parameter ASYNC_SPI_CLK = 0; @@ -72,7 +86,15 @@ parameter OFFLOAD0_CMD_MEM_ADDRESS_WIDTH = 4; parameter OFFLOAD0_SDO_MEM_ADDRESS_WIDTH = 4; parameter ID = 'h00; -localparam PCORE_VERSION = 'h010061; +parameter DATA_WIDTH = 8; +parameter NUM_OF_SDI = 1; + +localparam PCORE_VERSION = 'h010071; +localparam S_AXI = 0; +localparam UP_FIFO = 1; + +wire clk; +wire rstn; wire [CMD_FIFO_ADDRESS_WIDTH:0] cmd_fifo_room; wire cmd_fifo_almost_empty; @@ -84,66 +106,103 @@ wire cmd_fifo_in_valid; wire [SDO_FIFO_ADDRESS_WIDTH:0] sdo_fifo_room; wire sdo_fifo_almost_empty; -wire [7:0] sdo_fifo_in_data; +wire [(DATA_WIDTH-1):0] sdo_fifo_in_data; wire sdo_fifo_in_ready; wire sdo_fifo_in_valid; wire [SDI_FIFO_ADDRESS_WIDTH:0] sdi_fifo_level; wire sdi_fifo_almost_full; -wire [7:0] sdi_fifo_out_data; +wire [(NUM_OF_SDI * DATA_WIDTH-1):0] sdi_fifo_out_data; wire sdi_fifo_out_ready; wire sdi_fifo_out_valid; -reg up_reset = 1'b1; -wire up_resetn = ~up_reset; +reg up_sw_reset = 1'b1; +wire up_sw_resetn = ~up_sw_reset; -reg [31:0] up_rdata = 'd0; -reg up_wack = 1'b0; -reg up_rack = 1'b0; -wire up_wreq; -wire up_rreq; -wire [31:0] up_wdata; -wire [ 7:0] up_waddr; -wire [ 7:0] up_raddr; +reg [31:0] up_rdata_ff = 'd0; +reg up_wack_ff = 1'b0; +reg up_rack_ff = 1'b0; +wire up_wreq_s; +wire up_rreq_s; +wire [31:0] up_wdata_s; +wire [(UP_ADDRESS_WIDTH-1):0] up_waddr_s; +wire [(UP_ADDRESS_WIDTH-1):0] up_raddr_s; // Scratch register reg [31:0] up_scratch = 'h00; reg [7:0] sync_id = 'h00; -reg sync_id_pending = 1'b0; +reg sync_id_pending = 1'b0; + +generate if (MM_IF_TYPE == S_AXI) begin + + // assign clock and reset + + assign clk = s_axi_aclk; + assign rstn = s_axi_aresetn; + + // interface wrapper + + up_axi #( + .ADDRESS_WIDTH (UP_ADDRESS_WIDTH) + ) i_up_axi ( + .up_rstn(rstn), + .up_clk(clk), + .up_axi_awvalid(s_axi_awvalid), + .up_axi_awaddr(s_axi_awaddr), + .up_axi_awready(s_axi_awready), + .up_axi_wvalid(s_axi_wvalid), + .up_axi_wdata(s_axi_wdata), + .up_axi_wstrb(s_axi_wstrb), + .up_axi_wready(s_axi_wready), + .up_axi_bvalid(s_axi_bvalid), + .up_axi_bresp(s_axi_bresp), + .up_axi_bready(s_axi_bready), + .up_axi_arvalid(s_axi_arvalid), + .up_axi_araddr(s_axi_araddr), + .up_axi_arready(s_axi_arready), + .up_axi_rvalid(s_axi_rvalid), + .up_axi_rresp(s_axi_rresp), + .up_axi_rdata(s_axi_rdata), + .up_axi_rready(s_axi_rready), + .up_wreq(up_wreq_s), + .up_waddr(up_waddr_s), + .up_wdata(up_wdata_s), + .up_wack(up_wack_ff), + .up_rreq(up_rreq_s), + .up_raddr(up_raddr_s), + .up_rdata(up_rdata_ff), + .up_rack(up_rack_ff) + ); + + assign up_rdata = 32'b0; + assign up_rack = 1'b0; + assign up_wack = 1'b0; + +end +endgenerate + +generate if (MM_IF_TYPE == UP_FIFO) begin + + // assign clock and reset + + assign clk = up_clk; + assign rstn = up_rstn; + + assign up_wreq_s = up_wreq; + assign up_waddr_s = up_waddr; + assign up_wdata_s = up_wdata; + assign up_wack = up_wack_ff; + assign up_rreq_s = up_rreq; + assign up_raddr_s = up_raddr; + assign up_rdata = up_rdata_ff; + assign up_rack = up_rack_ff; + +end +endgenerate + -up_axi #( - .ADDRESS_WIDTH (8) -) i_up_axi ( - .up_rstn(s_axi_aresetn), - .up_clk(s_axi_aclk), - .up_axi_awvalid(s_axi_awvalid), - .up_axi_awaddr(s_axi_awaddr), - .up_axi_awready(s_axi_awready), - .up_axi_wvalid(s_axi_wvalid), - .up_axi_wdata(s_axi_wdata), - .up_axi_wstrb(s_axi_wstrb), - .up_axi_wready(s_axi_wready), - .up_axi_bvalid(s_axi_bvalid), - .up_axi_bresp(s_axi_bresp), - .up_axi_bready(s_axi_bready), - .up_axi_arvalid(s_axi_arvalid), - .up_axi_araddr(s_axi_araddr), - .up_axi_arready(s_axi_arready), - .up_axi_rvalid(s_axi_rvalid), - .up_axi_rresp(s_axi_rresp), - .up_axi_rdata(s_axi_rdata), - .up_axi_rready(s_axi_rready), - .up_wreq(up_wreq), - .up_waddr(up_waddr), - .up_wdata(up_wdata), - .up_wack(up_wack), - .up_rreq(up_rreq), - .up_raddr(up_raddr), - .up_rdata(up_rdata), - .up_rack(up_rack) -); // IRQ handling reg [3:0] up_irq_mask = 'h0; @@ -151,85 +210,85 @@ wire [3:0] up_irq_source; wire [3:0] up_irq_pending; assign up_irq_source = { - sync_id_pending, - sdi_fifo_almost_full, - sdo_fifo_almost_empty, - cmd_fifo_almost_empty + sync_id_pending, + sdi_fifo_almost_full, + sdo_fifo_almost_empty, + cmd_fifo_almost_empty }; assign up_irq_pending = up_irq_mask & up_irq_source; -always @(posedge s_axi_aclk) begin - if (s_axi_aresetn == 1'b0) - irq <= 1'b0; - else - irq <= |up_irq_pending; +always @(posedge clk) begin + if (rstn == 1'b0) + irq <= 1'b0; + else + irq <= |up_irq_pending; end -always @(posedge s_axi_aclk) begin - if (s_axi_aresetn == 1'b0) begin - up_wack <= 1'b0; - up_scratch <= 'h00; - up_reset <= 1'b1; - up_irq_mask <= 'h00; - offload0_enable <= 1'b0; - offload0_mem_reset <= 1'b0; - end else begin - up_wack <= up_wreq; - offload0_mem_reset <= 1'b0; - if (up_wreq) begin - case (up_waddr) - 8'h02: up_scratch <= up_wdata; - 8'h10: up_reset <= up_wdata; - 8'h20: up_irq_mask <= up_wdata; - 8'h40: offload0_enable <= up_wdata[0]; - 8'h42: offload0_mem_reset <= up_wdata[0]; - endcase - end - end +always @(posedge clk) begin + if (rstn == 1'b0) begin + up_wack_ff <= 1'b0; + up_scratch <= 'h00; + up_sw_reset <= 1'b1; + up_irq_mask <= 'h00; + offload0_enable <= 1'b0; + offload0_mem_reset <= 1'b0; + end else begin + up_wack_ff <= up_wreq_s; + offload0_mem_reset <= 1'b0; + if (up_wreq_s) begin + case (up_waddr_s) + 8'h02: up_scratch <= up_wdata_s; + 8'h10: up_sw_reset <= up_wdata_s; + 8'h20: up_irq_mask <= up_wdata_s; + 8'h40: offload0_enable <= up_wdata_s[0]; + 8'h42: offload0_mem_reset <= up_wdata_s[0]; + endcase + end + end end -always @(posedge s_axi_aclk) begin - if (s_axi_aresetn == 1'b0) begin - up_rack <= 'd0; - end else begin - up_rack <= up_rreq; - end +always @(posedge clk) begin + if (rstn == 1'b0) begin + up_rack_ff <= 'd0; + end else begin + up_rack_ff <= up_rreq_s; + end end -always @(posedge s_axi_aclk) begin - case (up_raddr) - 8'h00: up_rdata <= PCORE_VERSION; - 8'h01: up_rdata <= ID; - 8'h02: up_rdata <= up_scratch; - 8'h10: up_rdata <= up_reset; - 8'h20: up_rdata <= up_irq_mask; - 8'h21: up_rdata <= up_irq_pending; - 8'h22: up_rdata <= up_irq_source; - 8'h30: up_rdata <= sync_id; - 8'h34: up_rdata <= cmd_fifo_room; - 8'h35: up_rdata <= sdo_fifo_room; - 8'h36: up_rdata <= sdi_fifo_level; - 8'h3a: up_rdata <= sdi_fifo_out_data; - 8'h3c: up_rdata <= sdi_fifo_out_data; /* PEEK register */ - 8'h40: up_rdata <= {offload0_enable}; - 8'h41: up_rdata <= {offload0_enabled}; - default: up_rdata <= 'h00; - endcase +always @(posedge clk) begin + case (up_raddr_s) + 8'h00: up_rdata_ff <= PCORE_VERSION; + 8'h01: up_rdata_ff <= ID; + 8'h02: up_rdata_ff <= up_scratch; + 8'h10: up_rdata_ff <= up_sw_reset; + 8'h20: up_rdata_ff <= up_irq_mask; + 8'h21: up_rdata_ff <= up_irq_pending; + 8'h22: up_rdata_ff <= up_irq_source; + 8'h30: up_rdata_ff <= sync_id; + 8'h34: up_rdata_ff <= cmd_fifo_room; + 8'h35: up_rdata_ff <= sdo_fifo_room; + 8'h36: up_rdata_ff <= sdi_fifo_level; + 8'h3a: up_rdata_ff <= sdi_fifo_out_data; + 8'h3c: up_rdata_ff <= sdi_fifo_out_data; /* PEEK register */ + 8'h40: up_rdata_ff <= {offload0_enable}; + 8'h41: up_rdata_ff <= {offload0_enabled}; + default: up_rdata_ff <= 'h00; + endcase end -always @(posedge s_axi_aclk) begin - if (up_resetn == 1'b0) begin - sync_id <= 'h00; - sync_id_pending <= 1'b0; - end else begin - if (sync_valid == 1'b1) begin - sync_id <= sync_data; - sync_id_pending <= 1'b1; - end else if (up_wreq == 1'b1 && up_waddr == 8'h21 && up_wdata[3] == 1'b1) begin - sync_id_pending <= 1'b0; - end - end +always @(posedge clk) begin + if (up_sw_resetn == 1'b0) begin + sync_id <= 'h00; + sync_id_pending <= 1'b0; + end else begin + if (sync_valid == 1'b1) begin + sync_id <= sync_data; + sync_id_pending <= 1'b1; + end else if (up_wreq_s == 1'b1 && up_waddr_s == 8'h21 && up_wdata_s[3] == 1'b1) begin + sync_id_pending <= 1'b0; + end + end end assign sync_ready = 1'b1; @@ -238,98 +297,98 @@ generate if (ASYNC_SPI_CLK) begin wire spi_reset; ad_rst i_spi_resetn ( - .preset(up_reset), - .clk(spi_clk), - .rst(spi_reset) + .preset(up_sw_reset), + .clk(spi_clk), + .rst(spi_reset) ); assign spi_resetn = ~spi_reset; end else begin -assign spi_resetn = ~up_reset; +assign spi_resetn = ~up_sw_reset; end endgenerate /* Evaluates to true if FIFO level/room is 3/4 or above */ `define axi_spi_engine_check_watermark(x, n) \ - (x[n] == 1'b1 || x[n-1:n-2] == 2'b11) + (x[n] == 1'b1 || x[n-1:n-2] == 2'b11) -assign cmd_fifo_in_valid = up_wreq == 1'b1 && up_waddr == 8'h38; -assign cmd_fifo_in_data = up_wdata[15:0]; +assign cmd_fifo_in_valid = up_wreq_s == 1'b1 && up_waddr_s == 8'h38; +assign cmd_fifo_in_data = up_wdata_s[15:0]; assign cmd_fifo_almost_empty = - `axi_spi_engine_check_watermark(cmd_fifo_room, CMD_FIFO_ADDRESS_WIDTH); + `axi_spi_engine_check_watermark(cmd_fifo_room, CMD_FIFO_ADDRESS_WIDTH); util_axis_fifo #( - .DATA_WIDTH(16), - .ASYNC_CLK(ASYNC_SPI_CLK), - .ADDRESS_WIDTH(CMD_FIFO_ADDRESS_WIDTH), - .S_AXIS_REGISTERED(0) + .DATA_WIDTH(16), + .ASYNC_CLK(ASYNC_SPI_CLK), + .ADDRESS_WIDTH(CMD_FIFO_ADDRESS_WIDTH), + .S_AXIS_REGISTERED(0) ) i_cmd_fifo ( - .s_axis_aclk(s_axi_aclk), - .s_axis_aresetn(up_resetn), - .s_axis_ready(cmd_fifo_in_ready), - .s_axis_valid(cmd_fifo_in_valid), - .s_axis_data(cmd_fifo_in_data), - .s_axis_room(cmd_fifo_room), + .s_axis_aclk(clk), + .s_axis_aresetn(up_sw_resetn), + .s_axis_ready(cmd_fifo_in_ready), + .s_axis_valid(cmd_fifo_in_valid), + .s_axis_data(cmd_fifo_in_data), + .s_axis_room(cmd_fifo_room), - .m_axis_aclk(spi_clk), - .m_axis_aresetn(spi_resetn), - .m_axis_ready(cmd_ready), - .m_axis_valid(cmd_valid), - .m_axis_data(cmd_data) + .m_axis_aclk(spi_clk), + .m_axis_aresetn(spi_resetn), + .m_axis_ready(cmd_ready), + .m_axis_valid(cmd_valid), + .m_axis_data(cmd_data) ); -assign sdo_fifo_in_valid = up_wreq == 1'b1 && up_waddr == 8'h39; -assign sdo_fifo_in_data = up_wdata[7:0]; +assign sdo_fifo_in_valid = up_wreq_s == 1'b1 && up_waddr_s == 8'h39; +assign sdo_fifo_in_data = up_wdata_s[(DATA_WIDTH-1):0]; assign sdo_fifo_almost_empty = - `axi_spi_engine_check_watermark(sdo_fifo_room, SDO_FIFO_ADDRESS_WIDTH); + `axi_spi_engine_check_watermark(sdo_fifo_room, SDO_FIFO_ADDRESS_WIDTH); util_axis_fifo #( - .DATA_WIDTH(8), - .ASYNC_CLK(ASYNC_SPI_CLK), - .ADDRESS_WIDTH(SDO_FIFO_ADDRESS_WIDTH), - .S_AXIS_REGISTERED(0) + .DATA_WIDTH(DATA_WIDTH), + .ASYNC_CLK(ASYNC_SPI_CLK), + .ADDRESS_WIDTH(SDO_FIFO_ADDRESS_WIDTH), + .S_AXIS_REGISTERED(0) ) i_sdo_fifo ( - .s_axis_aclk(s_axi_aclk), - .s_axis_aresetn(up_resetn), - .s_axis_ready(sdo_fifo_in_ready), - .s_axis_valid(sdo_fifo_in_valid), - .s_axis_data(sdo_fifo_in_data), - .s_axis_room(sdo_fifo_room), + .s_axis_aclk(clk), + .s_axis_aresetn(up_sw_resetn), + .s_axis_ready(sdo_fifo_in_ready), + .s_axis_valid(sdo_fifo_in_valid), + .s_axis_data(sdo_fifo_in_data), + .s_axis_room(sdo_fifo_room), - .m_axis_aclk(spi_clk), - .m_axis_aresetn(spi_resetn), - .m_axis_ready(sdo_data_ready), - .m_axis_valid(sdo_data_valid), - .m_axis_data(sdo_data) + .m_axis_aclk(spi_clk), + .m_axis_aresetn(spi_resetn), + .m_axis_ready(sdo_data_ready), + .m_axis_valid(sdo_data_valid), + .m_axis_data(sdo_data) ); -assign sdi_fifo_out_ready = up_rreq == 1'b1 && up_raddr == 8'h3a; +assign sdi_fifo_out_ready = up_rreq_s == 1'b1 && up_raddr_s == 8'h3a; assign sdi_fifo_almost_full = - `axi_spi_engine_check_watermark(sdi_fifo_level, SDI_FIFO_ADDRESS_WIDTH); + `axi_spi_engine_check_watermark(sdi_fifo_level, SDI_FIFO_ADDRESS_WIDTH); util_axis_fifo #( - .DATA_WIDTH(8), - .ASYNC_CLK(ASYNC_SPI_CLK), - .ADDRESS_WIDTH(SDI_FIFO_ADDRESS_WIDTH), - .S_AXIS_REGISTERED(0) + .DATA_WIDTH(NUM_OF_SDI * DATA_WIDTH), + .ASYNC_CLK(ASYNC_SPI_CLK), + .ADDRESS_WIDTH(SDI_FIFO_ADDRESS_WIDTH), + .S_AXIS_REGISTERED(0) ) i_sdi_fifo ( - .s_axis_aclk(spi_clk), - .s_axis_aresetn(spi_resetn), - .s_axis_ready(sdi_data_ready), - .s_axis_valid(sdi_data_valid), - .s_axis_data(sdi_data), + .s_axis_aclk(spi_clk), + .s_axis_aresetn(spi_resetn), + .s_axis_ready(sdi_data_ready), + .s_axis_valid(sdi_data_valid), + .s_axis_data(sdi_data), - .m_axis_aclk(s_axi_aclk), - .m_axis_aresetn(up_resetn), - .m_axis_ready(sdi_fifo_out_ready), - .m_axis_valid(sdi_fifo_out_valid), - .m_axis_data(sdi_fifo_out_data), - .m_axis_level(sdi_fifo_level) + .m_axis_aclk(clk), + .m_axis_aresetn(up_sw_resetn), + .m_axis_ready(sdi_fifo_out_ready), + .m_axis_valid(sdi_fifo_out_valid), + .m_axis_data(sdi_fifo_out_data), + .m_axis_level(sdi_fifo_level) ); -assign offload0_cmd_wr_en = up_wreq == 1'b1 && up_waddr == 8'h44; -assign offload0_cmd_wr_data = up_wdata[15:0]; +assign offload0_cmd_wr_en = up_wreq_s == 1'b1 && up_waddr_s == 8'h44; +assign offload0_cmd_wr_data = up_wdata_s[15:0]; -assign offload0_sdo_wr_en = up_wreq == 1'b1 && up_waddr == 8'h45; -assign offload0_sdo_wr_data = up_wdata[7:0]; +assign offload0_sdo_wr_en = up_wreq_s == 1'b1 && up_waddr_s == 8'h45; +assign offload0_sdo_wr_data = up_wdata_s[7:0]; endmodule diff --git a/library/spi_engine/axi_spi_engine/axi_spi_engine_ip.tcl b/library/spi_engine/axi_spi_engine/axi_spi_engine_ip.tcl index 22084b53b..bb4e0e1c5 100644 --- a/library/spi_engine/axi_spi_engine/axi_spi_engine_ip.tcl +++ b/library/spi_engine/axi_spi_engine/axi_spi_engine_ip.tcl @@ -56,4 +56,8 @@ adi_add_bus "spi_engine_offload_ctrl0" "master" \ adi_add_bus_clock "s_axi_aclk" "spi_engine_offload_ctrl0:s_axi" "s_axi_aresetn" +foreach port {"up_clk" "up_rstn" "up_wreq" "up_waddr" "up_wdata" "up_rreq" "up_raddr"} { + set_property DRIVER_VALUE "0" [ipx::get_ports $port] +} + ipx::save_core [ipx::current_core] diff --git a/library/spi_engine/spi_engine_execution/Makefile b/library/spi_engine/spi_engine_execution/Makefile index f3af6ed7d..0bc6175ef 100644 --- a/library/spi_engine/spi_engine_execution/Makefile +++ b/library/spi_engine/spi_engine_execution/Makefile @@ -5,10 +5,15 @@ #################################################################################### #################################################################################### -M_DEPS := spi_engine_execution_ip.tcl M_DEPS += ../../scripts/adi_env.tcl M_DEPS += ../../scripts/adi_ip.tcl M_DEPS += spi_engine_execution.v +M_DEPS += spi_engine_execution_ip.tcl + +M_DEPS += ../../spi_engine/interfaces/spi_engine_ctrl.xml +M_DEPS += ../../spi_engine/interfaces/spi_engine_ctrl_rtl.xml +M_DEPS += ../../spi_engine/interfaces/spi_master.xml +M_DEPS += ../../spi_engine/interfaces/spi_master_rtl.xml M_VIVADO := vivado -mode batch -source @@ -19,6 +24,10 @@ M_FLIST += *.log M_FLIST += component.xml M_FLIST += *.jou M_FLIST += xgui +M_FLIST += *.ip_user_files +M_FLIST += *.srcs +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil @@ -35,7 +44,7 @@ clean-all: spi_engine_execution.xpr: $(M_DEPS) - rm -rf $(M_FLIST) + -rm -rf $(M_FLIST) $(M_VIVADO) spi_engine_execution_ip.tcl >> spi_engine_execution_ip.log 2>&1 #################################################################################### diff --git a/library/spi_engine/spi_engine_execution/spi_engine_execution.v b/library/spi_engine/spi_engine_execution/spi_engine_execution.v index 12173a6e7..ed743f376 100644 --- a/library/spi_engine/spi_engine_execution/spi_engine_execution.v +++ b/library/spi_engine/spi_engine_execution/spi_engine_execution.v @@ -1,39 +1,45 @@ module spi_engine_execution ( - input clk, - input resetn, + input clk, + input resetn, - output reg active, + output reg active, - output cmd_ready, - input cmd_valid, - input [15:0] cmd, + output cmd_ready, + input cmd_valid, + input [15:0] cmd, - input sdo_data_valid, - output reg sdo_data_ready, - input [7:0] sdo_data, + input sdo_data_valid, + output reg sdo_data_ready, + input [(DATA_WIDTH-1):0] sdo_data, - input sdi_data_ready, - output reg sdi_data_valid, - output [7:0] sdi_data, - input sync_ready, - output reg sync_valid, - output [7:0] sync, + input sdi_data_ready, + output reg sdi_data_valid, + output [(NUM_OF_SDI * DATA_WIDTH-1):0] sdi_data, - output reg sclk, - output sdo, - output reg sdo_t, - input sdi, - output reg [NUM_OF_CS-1:0] cs, - output reg three_wire + input sync_ready, + output reg sync_valid, + output [7:0] sync, + + output reg sclk, + output sdo, + output reg sdo_t, + input sdi, + input sdi_1, + input sdi_2, + input sdi_3, + output reg [NUM_OF_CS-1:0] cs, + output reg three_wire ); parameter NUM_OF_CS = 1; parameter DEFAULT_SPI_CFG = 0; parameter DEFAULT_CLK_DIV = 0; +parameter DATA_WIDTH = 8; // Valid data widths values are 8/16/24/32 +parameter NUM_OF_SDI = 1; -localparam CMD_TRANSFER = 2'b00; +localparam CMD_TRANSFER = 2'b00; localparam CMD_CHIPSELECT = 2'b01; localparam CMD_WRITE = 2'b10; localparam CMD_MISC = 2'b11; @@ -44,19 +50,22 @@ localparam MISC_SLEEP = 1'b1; localparam REG_CLK_DIV = 1'b0; localparam REG_CONFIG = 1'b1; +localparam BIT_COUNTER_WIDTH = DATA_WIDTH > 16 ? 5 : + DATA_WIDTH > 8 ? 4 : 3; + reg idle; reg [7:0] clk_div_counter = 'h00; reg [7:0] clk_div_counter_next = 'h00; reg clk_div_last; -reg [11:0] counter = 'h00; +reg [(BIT_COUNTER_WIDTH+8):0] counter = 'h00; -wire [7:0] sleep_counter = counter[11:4]; -wire [1:0] cs_sleep_counter = counter[5:4]; -wire [2:0] cs_sleep_counter2 = counter[6:4]; -wire [2:0] bit_counter = counter[3:1]; -wire [7:0] transfer_counter = counter[11:4]; +wire [7:0] sleep_counter = counter[(BIT_COUNTER_WIDTH+8):(BIT_COUNTER_WIDTH+1)]; +wire [1:0] cs_sleep_counter = counter[(BIT_COUNTER_WIDTH+2):(BIT_COUNTER_WIDTH+1)]; +wire [2:0] cs_sleep_counter2 = counter[(BIT_COUNTER_WIDTH+3):(BIT_COUNTER_WIDTH+1)]; +wire [(BIT_COUNTER_WIDTH-1):0] bit_counter = counter[BIT_COUNTER_WIDTH:1]; +wire [7:0] transfer_counter = counter[(BIT_COUNTER_WIDTH+8):(BIT_COUNTER_WIDTH+1)]; wire ntx_rx = counter[0]; reg trigger = 1'b0; @@ -70,7 +79,7 @@ reg last_transfer; wire end_of_word; assign first_bit = bit_counter == 'h0; -assign last_bit = bit_counter == 'h7; +assign last_bit = bit_counter == DATA_WIDTH - 1; assign end_of_word = last_bit == 1'b1 && ntx_rx == 1'b1 && clk_div_last == 1'b1; reg [15:0] cmd_d1; @@ -82,7 +91,10 @@ reg [7:0] clk_div = DEFAULT_CLK_DIV; wire sdo_enabled = cmd_d1[8]; wire sdi_enabled = cmd_d1[9]; -reg [8:0] data_shift = 'h0; +reg [(DATA_WIDTH):0] data_shift = 'h0; +reg [(DATA_WIDTH):0] data_shift_1 = 'h0; +reg [(DATA_WIDTH):0] data_shift_2 = 'h0; +reg [(DATA_WIDTH):0] data_shift_3 = 'h0; wire [1:0] inst = cmd[13:12]; wire [1:0] inst_d1 = cmd_d1[13:12]; @@ -97,54 +109,54 @@ wire exec_sync_cmd = exec_misc_cmd && cmd[8] == MISC_SYNC; assign cmd_ready = idle; always @(posedge clk) begin - if (cmd_ready) - cmd_d1 <= cmd; + if (cmd_ready) + cmd_d1 <= cmd; end always @(posedge clk) begin - if (resetn == 1'b0) begin - active <= 1'b0; - end else begin - if (exec_cmd == 1'b1) - active <= 1'b1; - else if (sync_ready == 1'b1 && sync_valid == 1'b1) - active <= 1'b0; - end + if (resetn == 1'b0) begin + active <= 1'b0; + end else begin + if (exec_cmd == 1'b1) + active <= 1'b1; + else if (sync_ready == 1'b1 && sync_valid == 1'b1) + active <= 1'b0; + end end always @(posedge clk) begin - if (resetn == 1'b0) begin - cpha <= DEFAULT_SPI_CFG[0]; - cpol <= DEFAULT_SPI_CFG[1]; - three_wire <= DEFAULT_SPI_CFG[2]; - clk_div <= DEFAULT_CLK_DIV; - end else if (exec_write_cmd == 1'b1) begin - if (cmd[8] == REG_CONFIG) begin - cpha <= cmd[0]; - cpol <= cmd[1]; - three_wire <= cmd[2]; - end else if (cmd[8] == REG_CLK_DIV) begin - clk_div <= cmd[7:0]; - end - end + if (resetn == 1'b0) begin + cpha <= DEFAULT_SPI_CFG[0]; + cpol <= DEFAULT_SPI_CFG[1]; + three_wire <= DEFAULT_SPI_CFG[2]; + clk_div <= DEFAULT_CLK_DIV; + end else if (exec_write_cmd == 1'b1) begin + if (cmd[8] == REG_CONFIG) begin + cpha <= cmd[0]; + cpol <= cmd[1]; + three_wire <= cmd[2]; + end else if (cmd[8] == REG_CLK_DIV) begin + clk_div <= cmd[7:0]; + end + end end always @(posedge clk) begin - if ((clk_div_last == 1'b0 && idle == 1'b0 && wait_for_io == 1'b0 && - clk_div_counter == 'h01) || clk_div == 'h00) - clk_div_last <= 1'b1; - else - clk_div_last <= 1'b0; + if ((clk_div_last == 1'b0 && idle == 1'b0 && wait_for_io == 1'b0 && + clk_div_counter == 'h01) || clk_div == 'h00) + clk_div_last <= 1'b1; + else + clk_div_last <= 1'b0; end always @(posedge clk) begin - if (clk_div_last == 1'b1 || idle == 1'b1 || wait_for_io == 1'b1) begin - clk_div_counter <= clk_div; - trigger <= 1'b1; - end else begin - clk_div_counter <= clk_div_counter - 1'b1; - trigger <= 1'b0; - end + if (clk_div_last == 1'b1 || idle == 1'b1 || wait_for_io == 1'b1) begin + clk_div_counter <= clk_div; + trigger <= 1'b1; + end else begin + clk_div_counter <= clk_div_counter - 1'b1; + trigger <= 1'b0; + end end wire trigger_tx = trigger == 1'b1 && ntx_rx == 1'b0; @@ -155,159 +167,169 @@ wire cs_sleep_counter_compare = cs_sleep_counter == cmd_d1[9:8] && clk_div_last wire cs_sleep_counter_compare2 = cs_sleep_counter2 == {cmd_d1[9:8],1'b1} && clk_div_last == 1'b1; always @(posedge clk) begin - if (idle == 1'b1) - counter <= 'h00; - else if (clk_div_last == 1'b1 && wait_for_io == 1'b0) - counter <= counter + (transfer_active ? 'h1 : 'h10); + if (idle == 1'b1) + counter <= 'h00; + else if (clk_div_last == 1'b1 && wait_for_io == 1'b0) + counter <= counter + (transfer_active ? 'h1 : 'h10); end always @(posedge clk) begin - if (resetn == 1'b0) begin - idle <= 1'b1; - end else begin - if (exec_transfer_cmd || exec_chipselect_cmd || exec_misc_cmd) begin - idle <= 1'b0; - end else begin - case (inst_d1) - CMD_TRANSFER: begin - if (transfer_active == 1'b0 && wait_for_io == 1'b0) - idle <= 1'b1; - end - CMD_CHIPSELECT: begin - if (cs_sleep_counter_compare2) - idle <= 1'b1; - end - CMD_MISC: begin - case (cmd_d1[8]) - MISC_SLEEP: begin - if (sleep_counter_compare) - idle <= 1'b1; - end - MISC_SYNC: begin - if (sync_ready) - idle <= 1'b1; - end - endcase - end - endcase - end - end + if (resetn == 1'b0) begin + idle <= 1'b1; + end else begin + if (exec_transfer_cmd || exec_chipselect_cmd || exec_misc_cmd) begin + idle <= 1'b0; + end else begin + case (inst_d1) + CMD_TRANSFER: begin + if (transfer_active == 1'b0 && wait_for_io == 1'b0) + idle <= 1'b1; + end + CMD_CHIPSELECT: begin + if (cs_sleep_counter_compare2) + idle <= 1'b1; + end + CMD_MISC: begin + case (cmd_d1[8]) + MISC_SLEEP: begin + if (sleep_counter_compare) + idle <= 1'b1; + end + MISC_SYNC: begin + if (sync_ready) + idle <= 1'b1; + end + endcase + end + endcase + end + end end always @(posedge clk) begin - if (resetn == 1'b0) begin - cs <= 'hff; - end else if (inst_d1 == CMD_CHIPSELECT && cs_sleep_counter_compare == 1'b1) begin - cs <= cmd_d1[NUM_OF_CS-1:0]; - end + if (resetn == 1'b0) begin + cs <= 'hff; + end else if (inst_d1 == CMD_CHIPSELECT && cs_sleep_counter_compare == 1'b1) begin + cs <= cmd_d1[NUM_OF_CS-1:0]; + end end always @(posedge clk) begin - if (resetn == 1'b0) begin - sync_valid <= 1'b0; - end else begin - if (exec_sync_cmd == 1'b1) begin - sync_valid <= 1'b1; - end else if (sync_ready == 1'b1) begin - sync_valid <= 1'b0; - end - end + if (resetn == 1'b0) begin + sync_valid <= 1'b0; + end else begin + if (exec_sync_cmd == 1'b1) begin + sync_valid <= 1'b1; + end else if (sync_ready == 1'b1) begin + sync_valid <= 1'b0; + end + end end assign sync = cmd_d1[7:0]; always @(posedge clk) begin - if (resetn == 1'b0) - sdo_data_ready <= 1'b0; - else if (sdo_enabled == 1'b1 && first_bit == 1'b1 && trigger_tx == 1'b1 && - transfer_active == 1'b1) - sdo_data_ready <= 1'b1; - else if (sdo_data_valid == 1'b1) - sdo_data_ready <= 1'b0; + if (resetn == 1'b0) + sdo_data_ready <= 1'b0; + else if (sdo_enabled == 1'b1 && first_bit == 1'b1 && trigger_tx == 1'b1 && + transfer_active == 1'b1) + sdo_data_ready <= 1'b1; + else if (sdo_data_valid == 1'b1) + sdo_data_ready <= 1'b0; end always @(posedge clk) begin - if (resetn == 1'b0) - sdi_data_valid <= 1'b0; - else if (sdi_enabled == 1'b1 && last_bit == 1'b1 && trigger_rx == 1'b1 && - transfer_active == 1'b1) - sdi_data_valid <= 1'b1; - else if (sdi_data_ready == 1'b1) - sdi_data_valid <= 1'b0; + if (resetn == 1'b0) + sdi_data_valid <= 1'b0; + else if (sdi_enabled == 1'b1 && last_bit == 1'b1 && trigger_rx == 1'b1 && + transfer_active == 1'b1) + sdi_data_valid <= 1'b1; + else if (sdi_data_ready == 1'b1) + sdi_data_valid <= 1'b0; end wire io_ready1 = (sdi_data_valid == 1'b0 || sdi_data_ready == 1'b1) && - (sdo_enabled == 1'b0 || last_transfer == 1'b1 || sdo_data_valid == 1'b1); + (sdo_enabled == 1'b0 || last_transfer == 1'b1 || sdo_data_valid == 1'b1); wire io_ready2 = (sdi_enabled == 1'b0 || sdi_data_ready == 1'b1) && - (sdo_enabled == 1'b0 || last_transfer == 1'b1 || sdo_data_valid == 1'b1); + (sdo_enabled == 1'b0 || last_transfer == 1'b1 || sdo_data_valid == 1'b1); always @(posedge clk) begin - if (idle == 1'b1) begin - last_transfer <= 1'b0; - end else if (trigger_tx == 1'b1 && transfer_active == 1'b1) begin - if (transfer_counter == cmd_d1[7:0]) - last_transfer <= 1'b1; - else - last_transfer <= 1'b0; - end + if (idle == 1'b1) begin + last_transfer <= 1'b0; + end else if (trigger_tx == 1'b1 && transfer_active == 1'b1) begin + if (transfer_counter == cmd_d1[7:0]) + last_transfer <= 1'b1; + else + last_transfer <= 1'b0; + end end always @(posedge clk) begin - if (resetn == 1'b0) begin - transfer_active <= 1'b0; - wait_for_io <= 1'b0; - end else begin - if (exec_transfer_cmd == 1'b1) begin - wait_for_io <= 1'b1; - transfer_active <= 1'b0; - end else if (wait_for_io == 1'b1 && io_ready1 == 1'b1) begin - wait_for_io <= 1'b0; - if (last_transfer == 1'b0) - transfer_active <= 1'b1; - else - transfer_active <= 1'b0; - end else if (transfer_active == 1'b1 && end_of_word == 1'b1) begin - if (last_transfer == 1'b1 || io_ready2 == 1'b0) - transfer_active <= 1'b0; - if (io_ready2 == 1'b0) - wait_for_io <= 1'b1; - end - end + if (resetn == 1'b0) begin + transfer_active <= 1'b0; + wait_for_io <= 1'b0; + end else begin + if (exec_transfer_cmd == 1'b1) begin + wait_for_io <= 1'b1; + transfer_active <= 1'b0; + end else if (wait_for_io == 1'b1 && io_ready1 == 1'b1) begin + wait_for_io <= 1'b0; + if (last_transfer == 1'b0) + transfer_active <= 1'b1; + else + transfer_active <= 1'b0; + end else if (transfer_active == 1'b1 && end_of_word == 1'b1) begin + if (last_transfer == 1'b1 || io_ready2 == 1'b0) + transfer_active <= 1'b0; + if (io_ready2 == 1'b0) + wait_for_io <= 1'b1; + end + end end always @(posedge clk) begin - if (transfer_active == 1'b1 || wait_for_io == 1'b1) - begin - sdo_t <= ~sdo_enabled; - end else begin - sdo_t <= 1'b1; - end + if (transfer_active == 1'b1 || wait_for_io == 1'b1) + begin + sdo_t <= ~sdo_enabled; + end else begin + sdo_t <= 1'b1; + end end always @(posedge clk) begin - if (transfer_active == 1'b1 && trigger_tx == 1'b1) begin - if (first_bit == 1'b1) - data_shift[8:1] <= sdo_data; - else - data_shift[8:1] <= data_shift[7:0]; - end + if (transfer_active == 1'b1 && trigger_tx == 1'b1) begin + if (first_bit == 1'b1) + data_shift[DATA_WIDTH:1] <= sdo_data; + else + data_shift[DATA_WIDTH:1] <= data_shift[(DATA_WIDTH-1):0]; + data_shift_1[DATA_WIDTH:1] <= data_shift_1[(DATA_WIDTH-1):0]; + data_shift_2[DATA_WIDTH:1] <= data_shift_2[(DATA_WIDTH-1):0]; + data_shift_3[DATA_WIDTH:1] <= data_shift_3[(DATA_WIDTH-1):0]; + end end -assign sdo = data_shift[8]; -assign sdi_data = data_shift[7:0]; +assign sdo = data_shift[DATA_WIDTH]; +assign sdi_data = (NUM_OF_SDI == 1) ? data_shift[(DATA_WIDTH-1):0] : + (NUM_OF_SDI == 2) ? {data_shift_1[(DATA_WIDTH-1):0], data_shift[(DATA_WIDTH-1):0]} : + (NUM_OF_SDI == 3) ? {data_shift_2[(DATA_WIDTH-1):0], data_shift_1[(DATA_WIDTH-1):0], data_shift[(DATA_WIDTH-1):0]} : + (NUM_OF_SDI == 4) ? {data_shift_3[(DATA_WIDTH-1):0], data_shift_2[(DATA_WIDTH-1):0], data_shift_1[(DATA_WIDTH-1):0], data_shift[(DATA_WIDTH-1):0]} : + data_shift[7:0]; always @(posedge clk) begin - if (trigger_rx == 1'b1) begin - data_shift[0] <= sdi; - end + if (trigger_rx == 1'b1) begin + data_shift[0] <= sdi; + data_shift_1[0] <= sdi_1; + data_shift_2[0] <= sdi_2; + data_shift_3[0] <= sdi_3; + end end always @(posedge clk) begin - if (transfer_active == 1'b1) begin - sclk <= cpol ^ cpha ^ ntx_rx; - end else begin - sclk <= cpol; - end + if (transfer_active == 1'b1) begin + sclk <= cpol ^ cpha ^ ntx_rx; + end else begin + sclk <= cpol; + end end endmodule diff --git a/library/spi_engine/spi_engine_execution/spi_engine_execution_ip.tcl b/library/spi_engine/spi_engine_execution/spi_engine_execution_ip.tcl index d7a51e00b..f0100f65c 100644 --- a/library/spi_engine/spi_engine_execution/spi_engine_execution_ip.tcl +++ b/library/spi_engine/spi_engine_execution/spi_engine_execution_ip.tcl @@ -43,4 +43,8 @@ adi_add_bus "spi" "master" \ } adi_add_bus_clock "clk" "spi" "resetn" +foreach port {"sdi_1" "sdi_2" "sdi_3"} { + set_property DRIVER_VALUE "0" [ipx::get_ports $port] +} + ipx::save_core [ipx::current_core] diff --git a/library/spi_engine/spi_engine_interconnect/Makefile b/library/spi_engine/spi_engine_interconnect/Makefile index eb521ec54..fc10187e5 100644 --- a/library/spi_engine/spi_engine_interconnect/Makefile +++ b/library/spi_engine/spi_engine_interconnect/Makefile @@ -5,10 +5,13 @@ #################################################################################### #################################################################################### -M_DEPS := spi_engine_interconnect_ip.tcl M_DEPS += ../../scripts/adi_env.tcl M_DEPS += ../../scripts/adi_ip.tcl M_DEPS += spi_engine_interconnect.v +M_DEPS += spi_engine_interconnect_ip.tcl + +M_DEPS += ../../spi_engine/interfaces/spi_engine_ctrl.xml +M_DEPS += ../../spi_engine/interfaces/spi_engine_ctrl_rtl.xml M_VIVADO := vivado -mode batch -source @@ -19,6 +22,10 @@ M_FLIST += *.log M_FLIST += component.xml M_FLIST += *.jou M_FLIST += xgui +M_FLIST += *.ip_user_files +M_FLIST += *.srcs +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil @@ -35,7 +42,7 @@ clean-all: spi_engine_interconnect.xpr: $(M_DEPS) - rm -rf $(M_FLIST) + -rm -rf $(M_FLIST) $(M_VIVADO) spi_engine_interconnect_ip.tcl >> spi_engine_interconnect_ip.log 2>&1 #################################################################################### diff --git a/library/spi_engine/spi_engine_interconnect/spi_engine_interconnect.v b/library/spi_engine/spi_engine_interconnect/spi_engine_interconnect.v index 463073955..52bdf0ca5 100644 --- a/library/spi_engine/spi_engine_interconnect/spi_engine_interconnect.v +++ b/library/spi_engine/spi_engine_interconnect/spi_engine_interconnect.v @@ -1,60 +1,63 @@ module spi_engine_interconnect ( - input clk, - input resetn, + input clk, + input resetn, - output m_cmd_valid, - input m_cmd_ready, - output [15:0] m_cmd_data, + output m_cmd_valid, + input m_cmd_ready, + output [15:0] m_cmd_data, - output m_sdo_valid, - input m_sdo_ready, - output [7:0] m_sdo_data, + output m_sdo_valid, + input m_sdo_ready, + output [(DATA_WIDTH-1):0] m_sdo_data, - input m_sdi_valid, - output m_sdi_ready, - input [7:0] m_sdi_data, + input m_sdi_valid, + output m_sdi_ready, + input [(NUM_OF_SDI * DATA_WIDTH-1):0] m_sdi_data, - input m_sync_valid, - output m_sync_ready, - input [7:0] m_sync, + input m_sync_valid, + output m_sync_ready, + input [7:0] m_sync, - input s0_cmd_valid, - output s0_cmd_ready, - input [15:0] s0_cmd_data, + input s0_cmd_valid, + output s0_cmd_ready, + input [15:0] s0_cmd_data, - input s0_sdo_valid, - output s0_sdo_ready, - input [7:0] s0_sdo_data, + input s0_sdo_valid, + output s0_sdo_ready, + input [(DATA_WIDTH-1):0] s0_sdo_data, - output s0_sdi_valid, - input s0_sdi_ready, - output [7:0] s0_sdi_data, + output s0_sdi_valid, + input s0_sdi_ready, + output [(NUM_OF_SDI * DATA_WIDTH-1):0] s0_sdi_data, - output s0_sync_valid, - input s0_sync_ready, - output [7:0] s0_sync, + output s0_sync_valid, + input s0_sync_ready, + output [7:0] s0_sync, - input s1_cmd_valid, - output s1_cmd_ready, - input [15:0] s1_cmd_data, + input s1_cmd_valid, + output s1_cmd_ready, + input [15:0] s1_cmd_data, - input s1_sdo_valid, - output s1_sdo_ready, - input [7:0] s1_sdo_data, + input s1_sdo_valid, + output s1_sdo_ready, + input [(DATA_WIDTH-1):0] s1_sdo_data, - output s1_sdi_valid, - input s1_sdi_ready, - output [7:0] s1_sdi_data, + output s1_sdi_valid, + input s1_sdi_ready, + output [(NUM_OF_SDI * DATA_WIDTH-1):0] s1_sdi_data, - output s1_sync_valid, - input s1_sync_ready, - output [7:0] s1_sync + output s1_sync_valid, + input s1_sync_ready, + output [7:0] s1_sync ); +parameter DATA_WIDTH = 8; // Valid data widths values are 8/16/24/32 +parameter NUM_OF_SDI = 1; + reg s_active = 1'b0; reg idle = 1'b1; @@ -84,24 +87,24 @@ assign s0_sync_valid = `spi_engine_interconnect_mux(m_sync_valid, 1'b0); assign s1_sync_valid = `spi_engine_interconnect_mux(1'b0, m_sync_valid); always @(posedge clk) begin - if (idle == 1'b1) begin - if (s0_cmd_valid) - s_active <= 1'b0; - else if (s1_cmd_valid) - s_active <= 1'b1; - end + if (idle == 1'b1) begin + if (s0_cmd_valid) + s_active <= 1'b0; + else if (s1_cmd_valid) + s_active <= 1'b1; + end end always @(posedge clk) begin - if (resetn == 1'b0) begin - idle = 1'b1; - end else begin - if (m_sync_valid == 1'b1 && m_sync_ready == 1'b1) begin - idle <= 1'b1; - end else if (s0_cmd_valid == 1'b1 || s1_cmd_valid == 1'b1) begin - idle <= 1'b0; - end - end + if (resetn == 1'b0) begin + idle = 1'b1; + end else begin + if (m_sync_valid == 1'b1 && m_sync_ready == 1'b1) begin + idle <= 1'b1; + end else if (s0_cmd_valid == 1'b1 || s1_cmd_valid == 1'b1) begin + idle <= 1'b0; + end + end end endmodule diff --git a/library/spi_engine/spi_engine_offload/Makefile b/library/spi_engine/spi_engine_offload/Makefile index f48f54660..17b7b02f8 100644 --- a/library/spi_engine/spi_engine_offload/Makefile +++ b/library/spi_engine/spi_engine_offload/Makefile @@ -5,10 +5,16 @@ #################################################################################### #################################################################################### -M_DEPS := spi_engine_offload_ip.tcl +M_DEPS += ../../common/sync_bits.v M_DEPS += ../../scripts/adi_env.tcl M_DEPS += ../../scripts/adi_ip.tcl M_DEPS += spi_engine_offload.v +M_DEPS += spi_engine_offload_ip.tcl + +M_DEPS += ../../spi_engine/interfaces/spi_engine_ctrl.xml +M_DEPS += ../../spi_engine/interfaces/spi_engine_ctrl_rtl.xml +M_DEPS += ../../spi_engine/interfaces/spi_engine_offload_ctrl.xml +M_DEPS += ../../spi_engine/interfaces/spi_engine_offload_ctrl_rtl.xml M_VIVADO := vivado -mode batch -source @@ -19,6 +25,10 @@ M_FLIST += *.log M_FLIST += component.xml M_FLIST += *.jou M_FLIST += xgui +M_FLIST += *.ip_user_files +M_FLIST += *.srcs +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil @@ -35,7 +45,7 @@ clean-all: spi_engine_offload.xpr: $(M_DEPS) - rm -rf $(M_FLIST) + -rm -rf $(M_FLIST) $(M_VIVADO) spi_engine_offload_ip.tcl >> spi_engine_offload_ip.log 2>&1 #################################################################################### diff --git a/library/spi_engine/spi_engine_offload/spi_engine_offload.v b/library/spi_engine/spi_engine_offload/spi_engine_offload.v index 862b869b1..37242d137 100644 --- a/library/spi_engine/spi_engine_offload/spi_engine_offload.v +++ b/library/spi_engine/spi_engine_offload/spi_engine_offload.v @@ -1,46 +1,48 @@ module spi_engine_offload ( - input ctrl_clk, + input ctrl_clk, - input ctrl_cmd_wr_en, - input [15:0] ctrl_cmd_wr_data, + input ctrl_cmd_wr_en, + input [15:0] ctrl_cmd_wr_data, - input ctrl_sdo_wr_en, - input [7:0] ctrl_sdo_wr_data, + input ctrl_sdo_wr_en, + input [(DATA_WIDTH-1):0] ctrl_sdo_wr_data, - input ctrl_enable, - output ctrl_enabled, - input ctrl_mem_reset, + input ctrl_enable, + output ctrl_enabled, + input ctrl_mem_reset, - input spi_clk, - input spi_resetn, + input spi_clk, + input spi_resetn, - input trigger, + input trigger, - output cmd_valid, - input cmd_ready, - output [15:0] cmd, + output cmd_valid, + input cmd_ready, + output [15:0] cmd, - output sdo_data_valid, - input sdo_data_ready, - output [7:0] sdo_data, + output sdo_data_valid, + input sdo_data_ready, + output [(DATA_WIDTH-1):0] sdo_data, - input sdi_data_valid, - output sdi_data_ready, - input [7:0] sdi_data, + input sdi_data_valid, + output sdi_data_ready, + input [(NUM_OF_SDI * DATA_WIDTH-1):0] sdi_data, - input sync_valid, - output sync_ready, - input [7:0] sync_data, + input sync_valid, + output sync_ready, + input [7:0] sync_data, - output offload_sdi_valid, - input offload_sdi_ready, - output [7:0] offload_sdi_data + output offload_sdi_valid, + input offload_sdi_ready, + output [(NUM_OF_SDI * DATA_WIDTH-1):0] offload_sdi_data ); parameter ASYNC_SPI_CLK = 0; parameter CMD_MEM_ADDRESS_WIDTH = 4; parameter SDO_MEM_ADDRESS_WIDTH = 4; +parameter DATA_WIDTH = 8; // Valid data widths values are 8/16/24/32 +parameter NUM_OF_SDI = 1; reg spi_active = 1'b0; @@ -50,7 +52,7 @@ reg [SDO_MEM_ADDRESS_WIDTH-1:0] ctrl_sdo_wr_addr = 'h00; reg [SDO_MEM_ADDRESS_WIDTH-1:0] spi_sdo_rd_addr = 'h00; reg [15:0] cmd_mem[0:2**CMD_MEM_ADDRESS_WIDTH-1]; -reg [7:0] sdo_mem[0:2**SDO_MEM_ADDRESS_WIDTH-1]; +reg [(DATA_WIDTH-1):0] sdo_mem[0:2**SDO_MEM_ADDRESS_WIDTH-1]; wire [CMD_MEM_ADDRESS_WIDTH-1:0] spi_cmd_rd_addr_next; wire spi_enable; @@ -82,17 +84,17 @@ wire ctrl_is_enabled; reg spi_enabled = 1'b0; always @(posedge ctrl_clk) begin - if (ctrl_enable == 1'b1) begin - ctrl_do_enable <= 1'b1; - end else if (ctrl_is_enabled == 1'b1) begin - ctrl_do_enable <= 1'b0; - end + if (ctrl_enable == 1'b1) begin + ctrl_do_enable <= 1'b1; + end else if (ctrl_is_enabled == 1'b1) begin + ctrl_do_enable <= 1'b0; + end end assign ctrl_enabled = ctrl_is_enabled | ctrl_do_enable; always @(posedge spi_clk) begin - spi_enabled <= spi_enable | spi_active; + spi_enabled <= spi_enable | spi_active; end sync_bits # ( @@ -123,56 +125,56 @@ end endgenerate assign spi_cmd_rd_addr_next = spi_cmd_rd_addr + 1; always @(posedge spi_clk) begin - if (spi_resetn == 1'b0) begin - spi_active <= 1'b0; - end else begin - if (spi_active == 1'b0) begin - if (trigger == 1'b1 && spi_enable == 1'b1) - spi_active <= 1'b1; - end else if (cmd_ready == 1'b1 && spi_cmd_rd_addr_next == ctrl_cmd_wr_addr) begin - spi_active <= 1'b0; - end - end + if (spi_resetn == 1'b0) begin + spi_active <= 1'b0; + end else begin + if (spi_active == 1'b0) begin + if (trigger == 1'b1 && spi_enable == 1'b1) + spi_active <= 1'b1; + end else if (cmd_ready == 1'b1 && spi_cmd_rd_addr_next == ctrl_cmd_wr_addr) begin + spi_active <= 1'b0; + end + end end always @(posedge spi_clk) begin - if (cmd_valid == 1'b0) begin - spi_cmd_rd_addr <= 'h00; - end else if (cmd_ready == 1'b1) begin - spi_cmd_rd_addr <= spi_cmd_rd_addr_next; - end + if (cmd_valid == 1'b0) begin + spi_cmd_rd_addr <= 'h00; + end else if (cmd_ready == 1'b1) begin + spi_cmd_rd_addr <= spi_cmd_rd_addr_next; + end end always @(posedge spi_clk) begin - if (spi_active == 1'b0) begin - spi_sdo_rd_addr <= 'h00; - end else if (sdo_data_ready == 1'b1) begin - spi_sdo_rd_addr <= spi_sdo_rd_addr + 1'b1; - end + if (spi_active == 1'b0) begin + spi_sdo_rd_addr <= 'h00; + end else if (sdo_data_ready == 1'b1) begin + spi_sdo_rd_addr <= spi_sdo_rd_addr + 1'b1; + end end always @(posedge ctrl_clk) begin - if (ctrl_mem_reset == 1'b1) - ctrl_cmd_wr_addr <= 'h00; - else if (ctrl_cmd_wr_en == 1'b1) - ctrl_cmd_wr_addr <= ctrl_cmd_wr_addr + 1'b1; + if (ctrl_mem_reset == 1'b1) + ctrl_cmd_wr_addr <= 'h00; + else if (ctrl_cmd_wr_en == 1'b1) + ctrl_cmd_wr_addr <= ctrl_cmd_wr_addr + 1'b1; end always @(posedge ctrl_clk) begin - if (ctrl_cmd_wr_en == 1'b1) - cmd_mem[ctrl_cmd_wr_addr] <= ctrl_cmd_wr_data; + if (ctrl_cmd_wr_en == 1'b1) + cmd_mem[ctrl_cmd_wr_addr] <= ctrl_cmd_wr_data; end always @(posedge ctrl_clk) begin - if (ctrl_mem_reset == 1'b1) - ctrl_sdo_wr_addr <= 'h00; - else if (ctrl_sdo_wr_en == 1'b1) - ctrl_sdo_wr_addr <= ctrl_sdo_wr_addr + 1'b1; + if (ctrl_mem_reset == 1'b1) + ctrl_sdo_wr_addr <= 'h00; + else if (ctrl_sdo_wr_en == 1'b1) + ctrl_sdo_wr_addr <= ctrl_sdo_wr_addr + 1'b1; end always @(posedge ctrl_clk) begin - if (ctrl_sdo_wr_en == 1'b1) - sdo_mem[ctrl_sdo_wr_addr] <= ctrl_sdo_wr_data; + if (ctrl_sdo_wr_en == 1'b1) + sdo_mem[ctrl_sdo_wr_addr] <= ctrl_sdo_wr_data; end endmodule diff --git a/library/spi_engine/spi_engine_offload/spi_engine_offload_ip.tcl b/library/spi_engine/spi_engine_offload/spi_engine_offload_ip.tcl index 87d54e817..6124b5672 100644 --- a/library/spi_engine/spi_engine_offload/spi_engine_offload_ip.tcl +++ b/library/spi_engine/spi_engine_offload/spi_engine_offload_ip.tcl @@ -3,6 +3,7 @@ source $ad_hdl_dir/library/scripts/adi_ip.tcl adi_ip_create spi_engine_offload adi_ip_files spi_engine_offload [list \ + "$ad_hdl_dir/library/common/sync_bits.v" \ "spi_engine_offload.v" \ ] diff --git a/library/util_adc_pack/util_adc_pack.v b/library/util_adc_pack/util_adc_pack.v deleted file mode 100644 index 6a7dae0ab..000000000 --- a/library/util_adc_pack/util_adc_pack.v +++ /dev/null @@ -1,536 +0,0 @@ -// *************************************************************************** -// *************************************************************************** -// Copyright 2014(c) Analog Devices, Inc. -// -// All rights reserved. -// -// Redistribution and use in source and binary forms, with or without modification, -// are permitted provided that the following conditions are met: -// - Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// - Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in -// the documentation and/or other materials provided with the -// distribution. -// - Neither the name of Analog Devices, Inc. nor the names of its -// contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// - The use of this software may or may not infringe the patent rights -// of one or more patent holders. This license does not release you -// from the requirement that you obtain separate licenses from these -// patent holders to use this software. -// - Use of the software either in source or binary form, must be run -// on or directly connected to an Analog Devices Inc. component. -// -// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, -// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A -// PARTICULAR PURPOSE ARE DISCLAIMED. -// -// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY -// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF -// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// *************************************************************************** -// *************************************************************************** -// *************************************************************************** -// *************************************************************************** - -`timescale 1ns/100ps - -module util_adc_pack ( - - clk, - - chan_enable_0, - chan_valid_0, - chan_data_0, - - chan_enable_1, - chan_valid_1, - chan_data_1, - - chan_enable_2, - chan_valid_2, - chan_data_2, - - chan_enable_3, - chan_valid_3, - chan_data_3, - - chan_enable_4, - chan_valid_4, - chan_data_4, - - chan_enable_5, - chan_valid_5, - chan_data_5, - - chan_enable_6, - chan_valid_6, - chan_data_6, - - chan_enable_7, - chan_valid_7, - chan_data_7, - - ddata, - dvalid, - dsync - - ); - - parameter NUM_OF_CHANNELS = 8; // valid values are 4 and 8 - parameter DATA_WIDTH = 16; // valid values are 16 and 32 - // common clock - - input clk; - - input chan_enable_0; - input chan_valid_0; - input [(DATA_WIDTH-1):0] chan_data_0; - - input chan_enable_1; - input chan_valid_1; - input [(DATA_WIDTH-1):0] chan_data_1; - - input chan_enable_2; - input chan_valid_2; - input [(DATA_WIDTH-1):0] chan_data_2; - - input chan_enable_3; - input chan_valid_3; - input [(DATA_WIDTH-1):0] chan_data_3; - - input chan_enable_4; - input chan_valid_4; - input [(DATA_WIDTH-1):0] chan_data_4; - - input chan_enable_5; - input chan_valid_5; - input [(DATA_WIDTH-1):0] chan_data_5; - - input chan_enable_6; - input chan_valid_6; - input [(DATA_WIDTH-1):0] chan_data_6; - - input chan_valid_7; - input chan_enable_7; - input [(DATA_WIDTH-1):0] chan_data_7; - - output [(DATA_WIDTH*NUM_OF_CHANNELS-1):0] ddata; - output dvalid; - output dsync; - - reg [(DATA_WIDTH*NUM_OF_CHANNELS-1):0] packed_data = 0; - reg [(DATA_WIDTH*NUM_OF_CHANNELS-1):0] temp_data_0 = 0; - reg [(DATA_WIDTH*NUM_OF_CHANNELS-1):0] temp_data_1 = 0; - - reg [3:0] enable_cnt; - reg [2:0] enable_cnt_0; - reg [2:0] enable_cnt_1; - - - reg [7:0] path_enabled = 0; - reg [7:0] path_enabled_d1 = 0; - reg [6:0] counter_0 = 0; - reg [7:0] en1 = 0; - reg [7:0] en2 = 0; - reg [7:0] en4 = 0; - reg dvalid = 0; - - reg [(DATA_WIDTH*NUM_OF_CHANNELS-1):0] ddata = 0; - reg [(DATA_WIDTH-1):0] chan_data_0_r; - reg [(DATA_WIDTH-1):0] chan_data_1_r; - reg [(DATA_WIDTH-1):0] chan_data_2_r; - reg [(DATA_WIDTH-1):0] chan_data_3_r; - reg [(DATA_WIDTH-1):0] chan_data_4_r; - reg [(DATA_WIDTH-1):0] chan_data_5_r; - reg [(DATA_WIDTH-1):0] chan_data_6_r; - reg [(DATA_WIDTH-1):0] chan_data_7_r; - - wire chan_valid; - - assign dsync = dvalid; - assign chan_valid = chan_valid_0 | chan_valid_1 | chan_valid_2 | chan_valid_3 | chan_valid_4 | chan_valid_5 | chan_valid_6 | chan_valid_7 ; - - always @(posedge clk) - begin - enable_cnt = enable_cnt_0 + enable_cnt_1; - enable_cnt_0 = chan_enable_0 + chan_enable_1 + chan_enable_2 + chan_enable_3; - if (NUM_OF_CHANNELS == 8) - begin - enable_cnt_1 = chan_enable_4 + chan_enable_5 + chan_enable_6 + chan_enable_7; - end - else - begin - enable_cnt_1 = 0; - end - end - - always @(posedge clk) - begin - if(chan_valid == 1'b1) - begin - chan_data_0_r <= chan_data_0; - chan_data_1_r <= chan_data_1; - chan_data_2_r <= chan_data_2; - chan_data_3_r <= chan_data_3; - chan_data_4_r <= chan_data_4; - chan_data_5_r <= chan_data_5; - chan_data_6_r <= chan_data_6; - chan_data_7_r <= chan_data_7; - end - end - - always @(chan_data_0_r, chan_data_1_r, chan_data_2_r, chan_data_3_r, chan_enable_0, chan_enable_1, chan_enable_2, chan_enable_3 ) - begin - casex ({chan_enable_3,chan_enable_2,chan_enable_1,chan_enable_0}) - 4'bxxx1: temp_data_0[(DATA_WIDTH-1):0] = chan_data_0_r; - 4'bxx10: temp_data_0[(DATA_WIDTH-1):0] = chan_data_1_r; - 4'bx100: temp_data_0[(DATA_WIDTH-1):0] = chan_data_2_r; - 4'b1000: temp_data_0[(DATA_WIDTH-1):0] = chan_data_3_r; - default: temp_data_0 [(DATA_WIDTH-1):0] = 0; - endcase - - casex ({chan_enable_3,chan_enable_2,chan_enable_1,chan_enable_0}) - 4'bxx11: temp_data_0[2*DATA_WIDTH-1:DATA_WIDTH] = chan_data_1_r; - 4'bx110: temp_data_0[2*DATA_WIDTH-1:DATA_WIDTH] = chan_data_2_r; - 4'bx101: temp_data_0[2*DATA_WIDTH-1:DATA_WIDTH] = chan_data_2_r; - 4'b1001: temp_data_0[2*DATA_WIDTH-1:DATA_WIDTH] = chan_data_3_r; - 4'b1010: temp_data_0[2*DATA_WIDTH-1:DATA_WIDTH] = chan_data_3_r; - 4'b1100: temp_data_0[2*DATA_WIDTH-1:DATA_WIDTH] = chan_data_3_r; - default: temp_data_0[2*DATA_WIDTH-1:DATA_WIDTH] = 0; - endcase - - casex ({chan_enable_3,chan_enable_2,chan_enable_1,chan_enable_0}) - 4'bx111: temp_data_0[3*DATA_WIDTH-1:2*DATA_WIDTH] = chan_data_2_r; - 4'b1011: temp_data_0[3*DATA_WIDTH-1:2*DATA_WIDTH] = chan_data_3_r; - 4'b1101: temp_data_0[3*DATA_WIDTH-1:2*DATA_WIDTH] = chan_data_3_r; - 4'b1110: temp_data_0[3*DATA_WIDTH-1:2*DATA_WIDTH] = chan_data_3_r; - default: temp_data_0[3*DATA_WIDTH-1:2*DATA_WIDTH] = 0; - endcase - - case ({chan_enable_3,chan_enable_2,chan_enable_1,chan_enable_0}) - 4'b1111: temp_data_0[4*DATA_WIDTH-1:3*DATA_WIDTH] = chan_data_3_r; - default: temp_data_0[4*DATA_WIDTH-1:3*DATA_WIDTH] = 0; - endcase - end - - always @(chan_data_4_r, chan_data_5_r, chan_data_6_r, chan_data_7_r, chan_enable_4, chan_enable_5, chan_enable_6, chan_enable_7) - begin - casex ({chan_enable_7,chan_enable_6,chan_enable_5,chan_enable_4}) - 4'bxxx1: temp_data_1[(DATA_WIDTH-1):0] = chan_data_4_r; - 4'bxx10: temp_data_1[(DATA_WIDTH-1):0] = chan_data_5_r; - 4'bx100: temp_data_1[(DATA_WIDTH-1):0] = chan_data_6_r; - 4'b1000: temp_data_1[(DATA_WIDTH-1):0] = chan_data_7_r; - default: temp_data_1[(DATA_WIDTH-1):0] = 0; - endcase - - casex ({chan_enable_7,chan_enable_6,chan_enable_5,chan_enable_4}) - 4'bxx11: temp_data_1[2*DATA_WIDTH-1:DATA_WIDTH] = chan_data_5_r; - 4'bx110: temp_data_1[2*DATA_WIDTH-1:DATA_WIDTH] = chan_data_6_r; - 4'bx101: temp_data_1[2*DATA_WIDTH-1:DATA_WIDTH] = chan_data_6_r; - 4'b1001: temp_data_1[2*DATA_WIDTH-1:DATA_WIDTH] = chan_data_7_r; - 4'b1010: temp_data_1[2*DATA_WIDTH-1:DATA_WIDTH] = chan_data_7_r; - 4'b1100: temp_data_1[2*DATA_WIDTH-1:DATA_WIDTH] = chan_data_7_r; - default: temp_data_1[2*DATA_WIDTH-1:DATA_WIDTH] = 0; - endcase - - casex ({chan_enable_7,chan_enable_6,chan_enable_5,chan_enable_4}) - 4'bx111: temp_data_1[3*DATA_WIDTH-1:2*DATA_WIDTH] = chan_data_6_r; - 4'b1011: temp_data_1[3*DATA_WIDTH-1:2*DATA_WIDTH] = chan_data_7_r; - 4'b1101: temp_data_1[3*DATA_WIDTH-1:2*DATA_WIDTH] = chan_data_7_r; - 4'b1110: temp_data_1[3*DATA_WIDTH-1:2*DATA_WIDTH] = chan_data_7_r; - default: temp_data_1[3*DATA_WIDTH-1:2*DATA_WIDTH] = 0; - endcase - - case ({chan_enable_7,chan_enable_6,chan_enable_5,chan_enable_4}) - 4'b1111: temp_data_1[4*DATA_WIDTH-1:3*DATA_WIDTH] = chan_data_7_r; - default: temp_data_1[4*DATA_WIDTH-1:3*DATA_WIDTH] = 0; - endcase - end - - always @(enable_cnt) - begin - case(enable_cnt) - 4'h1: path_enabled = 8'h01; - 4'h2: path_enabled = 8'h02; - 4'h4: path_enabled = 8'h08; - 4'h8: path_enabled = 8'h80; - default: path_enabled = 8'h0; - endcase - end - - always @(temp_data_0, temp_data_1, enable_cnt_0) - begin - packed_data = temp_data_0 | temp_data_1 << (enable_cnt_0 * DATA_WIDTH); - end - - always @(counter_0, path_enabled) - begin - case (counter_0) - 0: - begin - en1 = path_enabled[0]; - en2 = {2{path_enabled[1]}}; - en4 = {4{path_enabled[3]}}; - end - 1: - begin - en1 = path_enabled[0] << 1; - en2 = {2{path_enabled[1]}} << 0; - en4 = {4{path_enabled[3]}} << 0; - end - 2: - begin - en1 = path_enabled[0] << 2; - en2 = {2{path_enabled[1]}} << 2; - en4 = {4{path_enabled[3]}} << 0; - end - 3: - begin - en1 = path_enabled[0] << 3; - en2 = {2{path_enabled[1]}} << 2; - en4 = {4{path_enabled[3]}} << 0; - end - 4: - begin - if (NUM_OF_CHANNELS == 8) - begin - en1 = path_enabled[0] << 4; - en2 = {2{path_enabled[1]}} << 4; - en4 = {4{path_enabled[3]}} << 4; - end - else - begin - en1 = path_enabled[0]; - en2 = {2{path_enabled[1]}}; - en4 = {4{path_enabled[3]}}; - end - end - 5: - begin - en1 = path_enabled[0] << 5; - en2 = {2{path_enabled[1]}} << 4; - en4 = {4{path_enabled[3]}} << 4; - end - 6: - begin - en1 = path_enabled[0] << 6; - en2 = {2{path_enabled[1]}} << 6; - en4 = {4{path_enabled[3]}} << 4; - end - 7: - begin - en1 = path_enabled[0] << 7; - en2 = {2{path_enabled[1]}} << 6; - en4 = {4{path_enabled[3]}} << 4; - end - 8: - begin - en1 = path_enabled[0] << 0; - en2 = {2{path_enabled[1]}} << 0; - en4 = {4{path_enabled[3]}} << 0; - end - default: - begin - en1 = 8'h0; - en2 = 8'h0; - en4 = 8'h0; - end - endcase - end - - always @(posedge clk) - begin - path_enabled_d1 <= path_enabled; - if (path_enabled == 8'h0 || path_enabled_d1 != path_enabled ) - begin - counter_0 <= 7'h0; - end - else - begin - if( chan_valid == 1'b1) - begin - if (counter_0 > (NUM_OF_CHANNELS - 1) ) - begin - counter_0 <= counter_0 - NUM_OF_CHANNELS + enable_cnt; - end - else - begin - counter_0 <= counter_0 + enable_cnt; - end - if ((counter_0 == (NUM_OF_CHANNELS - enable_cnt)) || (path_enabled == (8'h1 << (NUM_OF_CHANNELS - 1)) )) - begin - dvalid <= 1'b1; - end - else - begin - dvalid <= 1'b0; - end - end - else - begin - dvalid <= 1'b0; - end - end - end - - generate - // 8 NUM_OF_CHANNELS - if ( NUM_OF_CHANNELS == 8 ) - begin - // FIRST FOUR NUM_OF_CHANNELS - always @(posedge clk) - begin - // ddata 0 - if ((en1[0] | en2[0] | en4[0] | path_enabled[NUM_OF_CHANNELS-1]) == 1'b1) - begin - ddata[(DATA_WIDTH-1):0] <= packed_data[(DATA_WIDTH-1):0]; - end - - // ddata 1 - if( en1[1] == 1'b1) - begin - ddata[2*DATA_WIDTH-1:DATA_WIDTH] <= packed_data[(DATA_WIDTH-1):0]; - end - if ( (en2[1] | en4[1] | path_enabled[NUM_OF_CHANNELS-1]) == 1'b1) - begin - ddata[2*DATA_WIDTH-1:DATA_WIDTH] <= packed_data[2*DATA_WIDTH-1:DATA_WIDTH]; - end - - // ddata 2 - if ((en1[2] | en2[2]) == 1'b1) - begin - ddata[3*DATA_WIDTH-1:2*DATA_WIDTH] <= packed_data[(DATA_WIDTH-1):0]; - end - if ((en4[2] | path_enabled[NUM_OF_CHANNELS-1]) == 1'b1) - begin - ddata[3*DATA_WIDTH-1:2*DATA_WIDTH] <= packed_data[3*DATA_WIDTH-1:2*DATA_WIDTH]; - end - - // ddata 3 - if (en1[3] == 1'b1) - begin - ddata[4*DATA_WIDTH-1:3*DATA_WIDTH] <= packed_data[(DATA_WIDTH-1):0]; - end - if (en2[3] == 1'b1) - begin - ddata[4*DATA_WIDTH-1:3*DATA_WIDTH] <= packed_data[2*DATA_WIDTH-1:DATA_WIDTH]; - end - if ((en4[3] | path_enabled[NUM_OF_CHANNELS-1]) == 1'b1) - begin - ddata[4*DATA_WIDTH-1:3*DATA_WIDTH] <= packed_data[4*DATA_WIDTH-1:3*DATA_WIDTH]; - end - - // ddata 4 - if ((en1[4] | en2[4] | en4[4]) == 1'b1) - begin - ddata[5*DATA_WIDTH-1:4*DATA_WIDTH] <= packed_data[(DATA_WIDTH-1):0]; - end - if (path_enabled[NUM_OF_CHANNELS-1] == 1'b1) - begin - ddata[5*DATA_WIDTH-1:4*DATA_WIDTH] <= packed_data[5*DATA_WIDTH-1:4*DATA_WIDTH]; - end - - // ddata 5 - if (en1[5] == 1'b1) - begin - ddata[6*DATA_WIDTH-1:5*DATA_WIDTH] <= packed_data[(DATA_WIDTH-1):0]; - end - if ((en2[5] | en4[5]) == 1'b1) - begin - ddata[6*DATA_WIDTH-1:5*DATA_WIDTH] <= packed_data[2*DATA_WIDTH-1:DATA_WIDTH]; - end - if (path_enabled[NUM_OF_CHANNELS-1] == 1'b1) - begin - ddata[6*DATA_WIDTH-1:5*DATA_WIDTH] <= packed_data[6*DATA_WIDTH-1:5*DATA_WIDTH]; - end - - // ddata 6 - if ((en1[6] | en2[6]) == 1'b1) - begin - ddata[7*DATA_WIDTH-1:6*DATA_WIDTH] <= packed_data[(DATA_WIDTH-1):0]; - end - if (en4[6] == 1'b1) - begin - ddata[7*DATA_WIDTH-1:6*DATA_WIDTH] <= packed_data[3*DATA_WIDTH-1:2*DATA_WIDTH]; - end - if (path_enabled[NUM_OF_CHANNELS-1] == 1'b1) - begin - ddata[7*DATA_WIDTH-1:6*DATA_WIDTH] <= packed_data[7*DATA_WIDTH-1:6*DATA_WIDTH]; - end - - // ddata 7 - if (en1[7] == 1'b1) - begin - ddata[8*DATA_WIDTH-1:7*DATA_WIDTH] <= packed_data[(DATA_WIDTH-1):0]; - end - if (en2[7] == 1'b1) - begin - ddata[8*DATA_WIDTH-1:7*DATA_WIDTH] <= packed_data[2*DATA_WIDTH-1:DATA_WIDTH]; - end - if (en4[7] == 1'b1) - begin - ddata[8*DATA_WIDTH-1:7*DATA_WIDTH] <= packed_data[4*DATA_WIDTH-1:3*DATA_WIDTH]; - end - if (path_enabled[NUM_OF_CHANNELS-1] == 1'b1) - begin - ddata[8*DATA_WIDTH-1:7*DATA_WIDTH] <= packed_data[8*DATA_WIDTH-1:7*DATA_WIDTH]; - end - end - end - else - begin - always @(posedge clk) - begin - // ddata 0 - if ((en1[0] | en2[0] | path_enabled[3] ) == 1'b1) - begin - ddata[(DATA_WIDTH-1):0] <= packed_data[(DATA_WIDTH-1):0]; - end - - // ddata 1 - if( en1[1] == 1'b1) - begin - ddata[2*DATA_WIDTH-1:DATA_WIDTH] <= packed_data[(DATA_WIDTH-1):0]; - end - if ( (en2[1] | | path_enabled[3] )== 1'b1) - begin - ddata[2*DATA_WIDTH-1:DATA_WIDTH] <= packed_data[2*DATA_WIDTH-1:DATA_WIDTH]; - end - - // ddata 2 - if ((en1[2] | en2[2]) == 1'b1) - begin - ddata[3*DATA_WIDTH-1:2*DATA_WIDTH] <= packed_data[(DATA_WIDTH-1):0]; - end - if (( path_enabled[3]) == 1'b1) - begin - ddata[3*DATA_WIDTH-1:2*DATA_WIDTH] <= packed_data[3*DATA_WIDTH-1:2*DATA_WIDTH]; - end - - // ddata 3 - if (en1[3] == 1'b1) - begin - ddata[4*DATA_WIDTH-1:3*DATA_WIDTH] <= packed_data[(DATA_WIDTH-1):0]; - end - if (en2[3] == 1'b1) - begin - ddata[4*DATA_WIDTH-1:3*DATA_WIDTH] <= packed_data[2*DATA_WIDTH-1:DATA_WIDTH]; - end - if (path_enabled[3] == 1'b1) - begin - ddata[4*DATA_WIDTH-1:3*DATA_WIDTH] <= packed_data[4*DATA_WIDTH-1:3*DATA_WIDTH]; - end - - end - end - endgenerate - - endmodule - - // *************************************************************************** - // *************************************************************************** diff --git a/library/util_adc_pack/util_adc_pack_hw.tcl b/library/util_adc_pack/util_adc_pack_hw.tcl deleted file mode 100644 index 30c58480a..000000000 --- a/library/util_adc_pack/util_adc_pack_hw.tcl +++ /dev/null @@ -1,87 +0,0 @@ - -package require -exact qsys 13.0 -source ../scripts/adi_env.tcl - -set_module_property NAME util_adc_pack -set_module_property DESCRIPTION "Util ADC data packager" -set_module_property VERSION 1.0 -set_module_property GROUP "Analog Devices" -set_module_property DISPLAY_NAME util_adc_pack -set_module_property ELABORATION_CALLBACK util_adc_pack_elaborate - -# files - -add_fileset quartus_synth QUARTUS_SYNTH "" "Quartus Synthesis" -set_fileset_property quartus_synth TOP_LEVEL util_adc_pack -add_fileset_file util_adc_pack.v VERILOG PATH util_adc_pack.v - -# parameters - -add_parameter NUM_OF_CHANNELS INTEGER 0 -set_parameter_property NUM_OF_CHANNELS DEFAULT_VALUE 8 -set_parameter_property NUM_OF_CHANNELS ALLOWED_RANGES {4 8} -set_parameter_property NUM_OF_CHANNELS DESCRIPTION "Valid values are 4 and 8" -set_parameter_property NUM_OF_CHANNELS DISPLAY_NAME NUM_OF_CHANNELS -set_parameter_property NUM_OF_CHANNELS TYPE INTEGER -set_parameter_property NUM_OF_CHANNELS UNITS None -set_parameter_property NUM_OF_CHANNELS HDL_PARAMETER true - -add_parameter DATA_WIDTH INTEGER 0 -set_parameter_property DATA_WIDTH DEFAULT_VALUE 16 -set_parameter_property DATA_WIDTH ALLOWED_RANGES {16 32} -set_parameter_property DATA_WIDTH DESCRIPTION "Valid values are 16 and 32" -set_parameter_property DATA_WIDTH DISPLAY_NAME DATA_WIDTH -set_parameter_property DATA_WIDTH TYPE INTEGER -set_parameter_property DATA_WIDTH UNITS None -set_parameter_property DATA_WIDTH HDL_PARAMETER true - -add_interface data_clock clock end -add_interface_port data_clock clk clk Input 1 - -add_interface channels_data conduit end -set_interface_property channels_data associatedClock data_clock -add_interface_port channels_data chan_enable_0 chan_enable_0 Input 1 -add_interface_port channels_data chan_valid_0 chan_valid_0 Input 1 -add_interface_port channels_data chan_data_0 chan_data_0 Input DATA_WIDTH - -add_interface_port channels_data chan_enable_1 chan_enable_1 Input 1 -add_interface_port channels_data chan_valid_1 chan_valid_1 Input 1 -add_interface_port channels_data chan_data_1 chan_data_1 Input DATA_WIDTH - -add_interface_port channels_data chan_enable_2 chan_enable_2 Input 1 -add_interface_port channels_data chan_valid_2 chan_valid_2 Input 1 -add_interface_port channels_data chan_data_2 chan_data_2 Input DATA_WIDTH - -add_interface_port channels_data chan_enable_3 chan_enable_3 Input 1 -add_interface_port channels_data chan_valid_3 chan_valid_3 Input 1 -add_interface_port channels_data chan_data_3 chan_data_3 Input DATA_WIDTH - -proc util_adc_pack_elaborate {} { - - set DW [ get_parameter_value DATA_WIDTH ] - set CHAN [ get_parameter_value NUM_OF_CHANNELS ] - add_interface_port channels_data dvalid dvalid Output 1 - add_interface_port channels_data dsync dsync Output 1 - add_interface_port channels_data ddata ddata Output [expr {$DW * $CHAN}] - - if {[get_parameter_value NUM_OF_CHANNELS] == 8} { - - add_interface_port channels_data chan_enable_4 chan_enable_4 Input 1 - add_interface_port channels_data chan_valid_4 chan_valid_4 Input 1 - add_interface_port channels_data chan_data_4 chan_data_4 Input DATA_WIDTH - - add_interface_port channels_data chan_enable_5 chan_enable_5 Input 1 - add_interface_port channels_data chan_valid_5 chan_valid_5 Input 1 - add_interface_port channels_data chan_data_5 chan_data_5 Input DATA_WIDTH - - add_interface_port channels_data chan_enable_6 chan_enable_6 Input 1 - add_interface_port channels_data chan_valid_6 chan_valid_6 Input 1 - add_interface_port channels_data chan_data_6 chan_data_6 Input DATA_WIDTH - - add_interface_port channels_data chan_enable_7 chan_enable_7 Input 1 - add_interface_port channels_data chan_valid_7 chan_valid_7 Input 1 - add_interface_port channels_data chan_data_7 chan_data_7 Input DATA_WIDTH -} - -} - diff --git a/library/util_adc_pack/util_adc_pack_ip.tcl b/library/util_adc_pack/util_adc_pack_ip.tcl deleted file mode 100644 index e2f31f206..000000000 --- a/library/util_adc_pack/util_adc_pack_ip.tcl +++ /dev/null @@ -1,42 +0,0 @@ -# ip - -source ../scripts/adi_env.tcl -source $ad_hdl_dir/library/scripts/adi_ip.tcl - -adi_ip_create util_adc_pack -adi_ip_files util_adc_pack [list \ - "util_adc_pack.v" ] - -adi_ip_properties_lite util_adc_pack - -ipx::remove_bus_interface {s} [ipx::current_core] -ipx::remove_bus_interface {m} [ipx::current_core] -ipx::remove_bus_interface {fifo} [ipx::current_core] -ipx::remove_bus_interface {signal_clock} [ipx::current_core] - -ipx::remove_memory_map {m} [ipx::current_core] -ipx::remove_address_space {s} [ipx::current_core] -ipx::remove_address_space {fifo} [ipx::current_core] - -for {set i 0} {$i < 8} {incr i} { - foreach port {"chan_enable" "chan_valid" "chan_data"} { - set name [format "%s_%d" $port $i] - set_property ENABLEMENT_DEPENDENCY \ - "(spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > $i)" \ - [ipx::get_ports $name] - set_property DRIVER_VALUE "0" [ipx::get_ports $name] - } -} - -adi_add_bus "fifo_wr" "master" \ - "analog.com:interface:fifo_wr_rtl:1.0" \ - "analog.com:interface:fifo_wr:1.0" \ - { \ - {"dvalid" "EN"} \ - {"ddata" "DATA"} \ - {"dsync" "SYNC"} \ - } - -adi_add_bus_clock "clk" "fifo_wr" - -ipx::save_core [ipx::current_core] diff --git a/library/util_adcfifo/Makefile b/library/util_adcfifo/Makefile index c1d4d0865..5b56692d2 100644 --- a/library/util_adcfifo/Makefile +++ b/library/util_adcfifo/Makefile @@ -5,13 +5,13 @@ #################################################################################### #################################################################################### -M_DEPS := util_adcfifo_ip.tcl -M_DEPS += ../scripts/adi_env.tcl -M_DEPS += ../scripts/adi_ip.tcl M_DEPS += ../common/ad_axis_inf_rx.v M_DEPS += ../common/ad_mem_asym.v +M_DEPS += ../scripts/adi_env.tcl +M_DEPS += ../scripts/adi_ip.tcl M_DEPS += util_adcfifo.v M_DEPS += util_adcfifo_constr.xdc +M_DEPS += util_adcfifo_ip.tcl M_VIVADO := vivado -mode batch -source @@ -22,6 +22,10 @@ M_FLIST += *.log M_FLIST += component.xml M_FLIST += *.jou M_FLIST += xgui +M_FLIST += *.ip_user_files +M_FLIST += *.srcs +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil @@ -38,7 +42,7 @@ clean-all: util_adcfifo.xpr: $(M_DEPS) - rm -rf $(M_FLIST) + -rm -rf $(M_FLIST) $(M_VIVADO) util_adcfifo_ip.tcl >> util_adcfifo_ip.log 2>&1 #################################################################################### diff --git a/library/util_adcfifo/util_adcfifo_constr.sdc b/library/util_adcfifo/util_adcfifo_constr.sdc index 70249724e..1edeab40d 100755 --- a/library/util_adcfifo/util_adcfifo_constr.sdc +++ b/library/util_adcfifo/util_adcfifo_constr.sdc @@ -1,4 +1,4 @@ set_false_path -from [get_registers *adc_waddr*] -to [get_registers *dma_waddr*] -set_false_path -from [get_registers *dma_xfer*] -to [get_registers *adc_xfer*] -set_false_path -to [get_registers *adc_xfer_req_m*] +set_false_path -to [get_registers *adc_xfer_req_m[0]*] + diff --git a/library/util_adcfifo/util_adcfifo_hw.tcl b/library/util_adcfifo/util_adcfifo_hw.tcl index 95cc93bcc..73784bf58 100755 --- a/library/util_adcfifo/util_adcfifo_hw.tcl +++ b/library/util_adcfifo/util_adcfifo_hw.tcl @@ -57,7 +57,7 @@ ad_alt_intf clock adc_clk input 1 adc_clk ad_alt_intf reset adc_rst input 1 if_adc_clk ad_alt_intf signal adc_wr input 1 valid ad_alt_intf signal adc_wdata input ADC_DATA_WIDTH data -ad_alt_intf signal adc_wovf output 1 adc_dovf +ad_alt_intf signal adc_wovf output 1 ovf ad_alt_intf clock dma_clk input 1 clk ad_alt_intf signal dma_wr output 1 valid diff --git a/library/util_axis_fifo/Makefile b/library/util_axis_fifo/Makefile index 70453feea..d1e77a7b1 100644 --- a/library/util_axis_fifo/Makefile +++ b/library/util_axis_fifo/Makefile @@ -5,15 +5,15 @@ #################################################################################### #################################################################################### -M_DEPS := util_axis_fifo_ip.tcl -M_DEPS += ../scripts/adi_env.tcl -M_DEPS += ../scripts/adi_ip.tcl M_DEPS += ../common/sync_bits.v M_DEPS += ../common/sync_gray.v +M_DEPS += ../scripts/adi_env.tcl +M_DEPS += ../scripts/adi_ip.tcl M_DEPS += address_gray.v M_DEPS += address_gray_pipelined.v M_DEPS += address_sync.v M_DEPS += util_axis_fifo.v +M_DEPS += util_axis_fifo_ip.tcl M_VIVADO := vivado -mode batch -source @@ -24,6 +24,10 @@ M_FLIST += *.log M_FLIST += component.xml M_FLIST += *.jou M_FLIST += xgui +M_FLIST += *.ip_user_files +M_FLIST += *.srcs +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil @@ -40,7 +44,7 @@ clean-all: util_axis_fifo.xpr: $(M_DEPS) - rm -rf $(M_FLIST) + -rm -rf $(M_FLIST) $(M_VIVADO) util_axis_fifo_ip.tcl >> util_axis_fifo_ip.log 2>&1 #################################################################################### diff --git a/library/util_axis_fifo/address_gray.v b/library/util_axis_fifo/address_gray.v index a75d3368d..5c912179d 100644 --- a/library/util_axis_fifo/address_gray.v +++ b/library/util_axis_fifo/address_gray.v @@ -37,19 +37,19 @@ // *************************************************************************** module fifo_address_gray ( - input m_axis_aclk, - input m_axis_aresetn, - input m_axis_ready, - output reg m_axis_valid, - output reg [ADDRESS_WIDTH:0] m_axis_level, + input m_axis_aclk, + input m_axis_aresetn, + input m_axis_ready, + output reg m_axis_valid, + output reg [ADDRESS_WIDTH:0] m_axis_level, - input s_axis_aclk, - input s_axis_aresetn, - output reg s_axis_ready, - input s_axis_valid, - output reg s_axis_empty, - output [ADDRESS_WIDTH-1:0] s_axis_waddr, - output reg [ADDRESS_WIDTH:0] s_axis_room + input s_axis_aclk, + input s_axis_aresetn, + output reg s_axis_ready, + input s_axis_valid, + output reg s_axis_empty, + output [ADDRESS_WIDTH-1:0] s_axis_waddr, + output reg [ADDRESS_WIDTH:0] s_axis_room ); parameter ADDRESS_WIDTH = 4; @@ -72,84 +72,84 @@ assign s_axis_waddr = _s_axis_waddr[ADDRESS_WIDTH-1:0]; always @(*) begin - if (s_axis_ready && s_axis_valid) - _s_axis_waddr_next <= _s_axis_waddr + 1; - else - _s_axis_waddr_next <= _s_axis_waddr; + if (s_axis_ready && s_axis_valid) + _s_axis_waddr_next <= _s_axis_waddr + 1; + else + _s_axis_waddr_next <= _s_axis_waddr; end assign s_axis_waddr_gray_next = _s_axis_waddr_next ^ _s_axis_waddr_next[ADDRESS_WIDTH:1]; always @(posedge s_axis_aclk) begin - if (s_axis_aresetn == 1'b0) begin - _s_axis_waddr <= 'h00; - s_axis_waddr_gray <= 'h00; - end else begin - _s_axis_waddr <= _s_axis_waddr_next; - s_axis_waddr_gray <= s_axis_waddr_gray_next; - end + if (s_axis_aresetn == 1'b0) begin + _s_axis_waddr <= 'h00; + s_axis_waddr_gray <= 'h00; + end else begin + _s_axis_waddr <= _s_axis_waddr_next; + s_axis_waddr_gray <= s_axis_waddr_gray_next; + end end always @(*) begin - if (m_axis_ready && m_axis_valid) - _m_axis_raddr_next <= _m_axis_raddr + 1; - else - _m_axis_raddr_next <= _m_axis_raddr; + if (m_axis_ready && m_axis_valid) + _m_axis_raddr_next <= _m_axis_raddr + 1; + else + _m_axis_raddr_next <= _m_axis_raddr; end assign m_axis_raddr_gray_next = _m_axis_raddr_next ^ _m_axis_raddr_next[ADDRESS_WIDTH:1]; always @(posedge m_axis_aclk) begin - if (m_axis_aresetn == 1'b0) begin - _m_axis_raddr <= 'h00; - m_axis_raddr_gray <= 'h00; - end else begin - _m_axis_raddr <= _m_axis_raddr_next; - m_axis_raddr_gray <= m_axis_raddr_gray_next; - end + if (m_axis_aresetn == 1'b0) begin + _m_axis_raddr <= 'h00; + m_axis_raddr_gray <= 'h00; + end else begin + _m_axis_raddr <= _m_axis_raddr_next; + m_axis_raddr_gray <= m_axis_raddr_gray_next; + end end sync_bits #( - .NUM_OF_BITS(ADDRESS_WIDTH + 1) + .NUM_OF_BITS(ADDRESS_WIDTH + 1) ) i_waddr_sync ( - .out_clk(m_axis_aclk), - .out_resetn(m_axis_aresetn), - .in(s_axis_waddr_gray), - .out(m_axis_waddr_gray) + .out_clk(m_axis_aclk), + .out_resetn(m_axis_aresetn), + .in(s_axis_waddr_gray), + .out(m_axis_waddr_gray) ); sync_bits #( - .NUM_OF_BITS(ADDRESS_WIDTH + 1) + .NUM_OF_BITS(ADDRESS_WIDTH + 1) ) i_raddr_sync ( - .out_clk(s_axis_aclk), - .out_resetn(s_axis_aresetn), - .in(m_axis_raddr_gray), - .out(s_axis_raddr_gray) + .out_clk(s_axis_aclk), + .out_resetn(s_axis_aresetn), + .in(m_axis_raddr_gray), + .out(s_axis_raddr_gray) ); always @(posedge s_axis_aclk) begin - if (s_axis_aresetn == 1'b0) begin - s_axis_ready <= 1'b1; - s_axis_empty <= 1'b1; - end else begin - s_axis_ready <= (s_axis_raddr_gray[ADDRESS_WIDTH] == s_axis_waddr_gray_next[ADDRESS_WIDTH] || - s_axis_raddr_gray[ADDRESS_WIDTH-1] == s_axis_waddr_gray_next[ADDRESS_WIDTH-1] || - s_axis_raddr_gray[ADDRESS_WIDTH-2:0] != s_axis_waddr_gray_next[ADDRESS_WIDTH-2:0]); - s_axis_empty <= s_axis_raddr_gray == s_axis_waddr_gray_next; - end + if (s_axis_aresetn == 1'b0) begin + s_axis_ready <= 1'b1; + s_axis_empty <= 1'b1; + end else begin + s_axis_ready <= (s_axis_raddr_gray[ADDRESS_WIDTH] == s_axis_waddr_gray_next[ADDRESS_WIDTH] || + s_axis_raddr_gray[ADDRESS_WIDTH-1] == s_axis_waddr_gray_next[ADDRESS_WIDTH-1] || + s_axis_raddr_gray[ADDRESS_WIDTH-2:0] != s_axis_waddr_gray_next[ADDRESS_WIDTH-2:0]); + s_axis_empty <= s_axis_raddr_gray == s_axis_waddr_gray_next; + end end always @(posedge m_axis_aclk) begin - if (s_axis_aresetn == 1'b0) - m_axis_valid <= 1'b0; - else begin - m_axis_valid <= m_axis_waddr_gray != m_axis_raddr_gray_next; - end + if (s_axis_aresetn == 1'b0) + m_axis_valid <= 1'b0; + else begin + m_axis_valid <= m_axis_waddr_gray != m_axis_raddr_gray_next; + end end endmodule diff --git a/library/util_axis_fifo/address_gray_pipelined.v b/library/util_axis_fifo/address_gray_pipelined.v index 5541091c0..ed7055b39 100644 --- a/library/util_axis_fifo/address_gray_pipelined.v +++ b/library/util_axis_fifo/address_gray_pipelined.v @@ -37,20 +37,20 @@ // *************************************************************************** module fifo_address_gray_pipelined ( - input m_axis_aclk, - input m_axis_aresetn, - input m_axis_ready, - output reg m_axis_valid, - output [ADDRESS_WIDTH-1:0] m_axis_raddr, - output reg [ADDRESS_WIDTH:0] m_axis_level, + input m_axis_aclk, + input m_axis_aresetn, + input m_axis_ready, + output reg m_axis_valid, + output [ADDRESS_WIDTH-1:0] m_axis_raddr, + output reg [ADDRESS_WIDTH:0] m_axis_level, - input s_axis_aclk, - input s_axis_aresetn, - output reg s_axis_ready, - input s_axis_valid, - output reg s_axis_empty, - output [ADDRESS_WIDTH-1:0] s_axis_waddr, - output reg [ADDRESS_WIDTH:0] s_axis_room + input s_axis_aclk, + input s_axis_aresetn, + output reg s_axis_ready, + input s_axis_valid, + output reg s_axis_empty, + output [ADDRESS_WIDTH-1:0] s_axis_waddr, + output reg [ADDRESS_WIDTH:0] s_axis_room ); parameter ADDRESS_WIDTH = 4; @@ -68,83 +68,83 @@ assign m_axis_raddr = _m_axis_raddr[ADDRESS_WIDTH-1:0]; always @(*) begin - if (s_axis_ready && s_axis_valid) - _s_axis_waddr_next <= _s_axis_waddr + 1; - else - _s_axis_waddr_next <= _s_axis_waddr; + if (s_axis_ready && s_axis_valid) + _s_axis_waddr_next <= _s_axis_waddr + 1; + else + _s_axis_waddr_next <= _s_axis_waddr; end always @(posedge s_axis_aclk) begin - if (s_axis_aresetn == 1'b0) begin - _s_axis_waddr <= 'h00; - end else begin - _s_axis_waddr <= _s_axis_waddr_next; - end + if (s_axis_aresetn == 1'b0) begin + _s_axis_waddr <= 'h00; + end else begin + _s_axis_waddr <= _s_axis_waddr_next; + end end always @(*) begin - if (m_axis_ready && m_axis_valid) - _m_axis_raddr_next <= _m_axis_raddr + 1; - else - _m_axis_raddr_next <= _m_axis_raddr; + if (m_axis_ready && m_axis_valid) + _m_axis_raddr_next <= _m_axis_raddr + 1; + else + _m_axis_raddr_next <= _m_axis_raddr; end always @(posedge m_axis_aclk) begin - if (m_axis_aresetn == 1'b0) begin - _m_axis_raddr <= 'h00; - end else begin - _m_axis_raddr <= _m_axis_raddr_next; - end + if (m_axis_aresetn == 1'b0) begin + _m_axis_raddr <= 'h00; + end else begin + _m_axis_raddr <= _m_axis_raddr_next; + end end sync_gray #( - .DATA_WIDTH(ADDRESS_WIDTH + 1) + .DATA_WIDTH(ADDRESS_WIDTH + 1) ) i_waddr_sync ( - .in_clk(s_axis_aclk), - .in_resetn(s_axis_aresetn), - .out_clk(m_axis_aclk), - .out_resetn(m_axis_aresetn), - .in_count(_s_axis_waddr), - .out_count(_m_axis_waddr) + .in_clk(s_axis_aclk), + .in_resetn(s_axis_aresetn), + .out_clk(m_axis_aclk), + .out_resetn(m_axis_aresetn), + .in_count(_s_axis_waddr), + .out_count(_m_axis_waddr) ); sync_gray #( - .DATA_WIDTH(ADDRESS_WIDTH + 1) + .DATA_WIDTH(ADDRESS_WIDTH + 1) ) i_raddr_sync ( - .in_clk(m_axis_aclk), - .in_resetn(m_axis_aresetn), - .out_clk(s_axis_aclk), - .out_resetn(s_axis_aresetn), - .in_count(_m_axis_raddr), - .out_count(_s_axis_raddr) + .in_clk(m_axis_aclk), + .in_resetn(m_axis_aresetn), + .out_clk(s_axis_aclk), + .out_resetn(s_axis_aresetn), + .in_count(_m_axis_raddr), + .out_count(_s_axis_raddr) ); always @(posedge s_axis_aclk) begin - if (s_axis_aresetn == 1'b0) begin - s_axis_ready <= 1'b1; - s_axis_empty <= 1'b1; - s_axis_room <= 2**ADDRESS_WIDTH; - end else begin - s_axis_ready <= (_s_axis_raddr[ADDRESS_WIDTH] == _s_axis_waddr_next[ADDRESS_WIDTH] || - _s_axis_raddr[ADDRESS_WIDTH-1:0] != _s_axis_waddr_next[ADDRESS_WIDTH-1:0]); - s_axis_empty <= _s_axis_raddr == _s_axis_waddr_next; - s_axis_room <= _s_axis_raddr - _s_axis_waddr_next + 2**ADDRESS_WIDTH; - end + if (s_axis_aresetn == 1'b0) begin + s_axis_ready <= 1'b1; + s_axis_empty <= 1'b1; + s_axis_room <= 2**ADDRESS_WIDTH; + end else begin + s_axis_ready <= (_s_axis_raddr[ADDRESS_WIDTH] == _s_axis_waddr_next[ADDRESS_WIDTH] || + _s_axis_raddr[ADDRESS_WIDTH-1:0] != _s_axis_waddr_next[ADDRESS_WIDTH-1:0]); + s_axis_empty <= _s_axis_raddr == _s_axis_waddr_next; + s_axis_room <= _s_axis_raddr - _s_axis_waddr_next + 2**ADDRESS_WIDTH; + end end always @(posedge m_axis_aclk) begin - if (m_axis_aresetn == 1'b0) begin - m_axis_valid <= 1'b0; - m_axis_level <= 'h00; - end else begin - m_axis_valid <= _m_axis_waddr != _m_axis_raddr_next; - m_axis_level <= _m_axis_waddr - _m_axis_raddr_next; - end + if (m_axis_aresetn == 1'b0) begin + m_axis_valid <= 1'b0; + m_axis_level <= 'h00; + end else begin + m_axis_valid <= _m_axis_waddr != _m_axis_raddr_next; + m_axis_level <= _m_axis_waddr - _m_axis_raddr_next; + end end endmodule diff --git a/library/util_axis_fifo/address_sync.v b/library/util_axis_fifo/address_sync.v index 7b02b6e13..6c94dba9c 100644 --- a/library/util_axis_fifo/address_sync.v +++ b/library/util_axis_fifo/address_sync.v @@ -37,19 +37,19 @@ // *************************************************************************** module fifo_address_sync ( - input clk, - input resetn, + input clk, + input resetn, - input m_axis_ready, - output reg m_axis_valid, - output reg [ADDRESS_WIDTH-1:0] m_axis_raddr, - output [ADDRESS_WIDTH:0] m_axis_level, + input m_axis_ready, + output reg m_axis_valid, + output reg [ADDRESS_WIDTH-1:0] m_axis_raddr, + output [ADDRESS_WIDTH:0] m_axis_level, - output reg s_axis_ready, - input s_axis_valid, - output reg s_axis_empty, - output reg [ADDRESS_WIDTH-1:0] s_axis_waddr, - output [ADDRESS_WIDTH:0] s_axis_room + output reg s_axis_ready, + input s_axis_valid, + output reg s_axis_empty, + output reg [ADDRESS_WIDTH-1:0] s_axis_waddr, + output [ADDRESS_WIDTH:0] s_axis_room ); parameter ADDRESS_WIDTH = 4; @@ -66,42 +66,42 @@ wire write = s_axis_ready & s_axis_valid; always @(posedge clk) begin - if (resetn == 1'b0) begin - s_axis_waddr <= 'h00; - m_axis_raddr <= 'h00; - end else begin - if (write) - s_axis_waddr <= s_axis_waddr + 1'b1; - if (read) - m_axis_raddr <= m_axis_raddr + 1'b1; - end + if (resetn == 1'b0) begin + s_axis_waddr <= 'h00; + m_axis_raddr <= 'h00; + end else begin + if (write) + s_axis_waddr <= s_axis_waddr + 1'b1; + if (read) + m_axis_raddr <= m_axis_raddr + 1'b1; + end end always @(*) begin - if (read & ~write) - level_next <= level - 1'b1; - else if (~read & write) - level_next <= level + 1'b1; - else - level_next <= level; + if (read & ~write) + level_next <= level - 1'b1; + else if (~read & write) + level_next <= level + 1'b1; + else + level_next <= level; end always @(posedge clk) begin - if (resetn == 1'b0) begin - m_axis_valid <= 1'b0; - s_axis_ready <= 1'b0; - level <= 'h00; - room <= 2**ADDRESS_WIDTH; - s_axis_empty <= 'h00; - end else begin - level <= level_next; - room <= 2**ADDRESS_WIDTH - level_next; - m_axis_valid <= level_next != 0; - s_axis_ready <= level_next != 2**ADDRESS_WIDTH; - s_axis_empty <= level_next == 0; - end + if (resetn == 1'b0) begin + m_axis_valid <= 1'b0; + s_axis_ready <= 1'b0; + level <= 'h00; + room <= 2**ADDRESS_WIDTH; + s_axis_empty <= 'h00; + end else begin + level <= level_next; + room <= 2**ADDRESS_WIDTH - level_next; + m_axis_valid <= level_next != 0; + s_axis_ready <= level_next != 2**ADDRESS_WIDTH; + s_axis_empty <= level_next == 0; + end end endmodule diff --git a/library/util_axis_fifo/util_axis_fifo.v b/library/util_axis_fifo/util_axis_fifo.v index 8b30190d8..a590d6b21 100644 --- a/library/util_axis_fifo/util_axis_fifo.v +++ b/library/util_axis_fifo/util_axis_fifo.v @@ -37,20 +37,20 @@ // *************************************************************************** module util_axis_fifo ( - input m_axis_aclk, - input m_axis_aresetn, - input m_axis_ready, - output m_axis_valid, - output [DATA_WIDTH-1:0] m_axis_data, - output [ADDRESS_WIDTH:0] m_axis_level, + input m_axis_aclk, + input m_axis_aresetn, + input m_axis_ready, + output m_axis_valid, + output [DATA_WIDTH-1:0] m_axis_data, + output [ADDRESS_WIDTH:0] m_axis_level, - input s_axis_aclk, - input s_axis_aresetn, - output s_axis_ready, - input s_axis_valid, - input [DATA_WIDTH-1:0] s_axis_data, - output s_axis_empty, - output [ADDRESS_WIDTH:0] s_axis_room + input s_axis_aclk, + input s_axis_aresetn, + output s_axis_ready, + input s_axis_valid, + input [DATA_WIDTH-1:0] s_axis_data, + output s_axis_empty, + output [ADDRESS_WIDTH:0] s_axis_room ); parameter DATA_WIDTH = 64; @@ -68,23 +68,23 @@ wire m_axis_waddr; wire s_axis_raddr; sync_bits #( - .NUM_OF_BITS(1), - .ASYNC_CLK(ASYNC_CLK) + .NUM_OF_BITS(1), + .ASYNC_CLK(ASYNC_CLK) ) i_waddr_sync ( - .out_clk(m_axis_aclk), - .out_resetn(m_axis_aresetn), - .in(s_axis_waddr), - .out(m_axis_waddr) + .out_clk(m_axis_aclk), + .out_resetn(m_axis_aresetn), + .in(s_axis_waddr), + .out(m_axis_waddr) ); sync_bits #( - .NUM_OF_BITS(1), - .ASYNC_CLK(ASYNC_CLK) + .NUM_OF_BITS(1), + .ASYNC_CLK(ASYNC_CLK) ) i_raddr_sync ( - .out_clk(s_axis_aclk), - .out_resetn(s_axis_aresetn), - .in(m_axis_raddr), - .out(s_axis_raddr) + .out_clk(s_axis_aclk), + .out_resetn(s_axis_aresetn), + .in(m_axis_raddr), + .out(s_axis_raddr) ); assign m_axis_valid = m_axis_raddr != m_axis_waddr; @@ -94,27 +94,27 @@ assign s_axis_empty = s_axis_ready; assign s_axis_room = s_axis_ready; always @(posedge s_axis_aclk) begin - if (s_axis_ready) - cdc_sync_fifo_ram <= s_axis_data; + if (s_axis_ready) + cdc_sync_fifo_ram <= s_axis_data; end always @(posedge s_axis_aclk) begin - if (s_axis_aresetn == 1'b0) begin - s_axis_waddr <= 1'b0; - end else begin - if (s_axis_ready & s_axis_valid) begin - s_axis_waddr <= s_axis_waddr + 1'b1; - end - end + if (s_axis_aresetn == 1'b0) begin + s_axis_waddr <= 1'b0; + end else begin + if (s_axis_ready & s_axis_valid) begin + s_axis_waddr <= s_axis_waddr + 1'b1; + end + end end always @(posedge m_axis_aclk) begin - if (m_axis_aresetn == 1'b0) begin - m_axis_raddr <= 1'b0; - end else begin - if (m_axis_valid & m_axis_ready) - m_axis_raddr <= m_axis_raddr + 1'b1; - end + if (m_axis_aresetn == 1'b0) begin + m_axis_raddr <= 1'b0; + end else begin + if (m_axis_valid & m_axis_ready) + m_axis_raddr <= m_axis_raddr + 1'b1; + end end assign m_axis_data = cdc_sync_fifo_ram; @@ -131,48 +131,48 @@ wire _m_axis_valid; if (ASYNC_CLK == 1) begin fifo_address_gray_pipelined #( - .ADDRESS_WIDTH(ADDRESS_WIDTH) + .ADDRESS_WIDTH(ADDRESS_WIDTH) ) i_address_gray ( - .m_axis_aclk(m_axis_aclk), - .m_axis_aresetn(m_axis_aresetn), - .m_axis_ready(_m_axis_ready), - .m_axis_valid(_m_axis_valid), - .m_axis_raddr(m_axis_raddr), - .m_axis_level(m_axis_level), + .m_axis_aclk(m_axis_aclk), + .m_axis_aresetn(m_axis_aresetn), + .m_axis_ready(_m_axis_ready), + .m_axis_valid(_m_axis_valid), + .m_axis_raddr(m_axis_raddr), + .m_axis_level(m_axis_level), - .s_axis_aclk(s_axis_aclk), - .s_axis_aresetn(s_axis_aresetn), - .s_axis_ready(s_axis_ready), - .s_axis_valid(s_axis_valid), - .s_axis_empty(s_axis_empty), - .s_axis_waddr(s_axis_waddr), - .s_axis_room(s_axis_room) + .s_axis_aclk(s_axis_aclk), + .s_axis_aresetn(s_axis_aresetn), + .s_axis_ready(s_axis_ready), + .s_axis_valid(s_axis_valid), + .s_axis_empty(s_axis_empty), + .s_axis_waddr(s_axis_waddr), + .s_axis_room(s_axis_room) ); end else begin fifo_address_sync #( - .ADDRESS_WIDTH(ADDRESS_WIDTH) + .ADDRESS_WIDTH(ADDRESS_WIDTH) ) i_address_sync ( - .clk(m_axis_aclk), - .resetn(m_axis_aresetn), - .m_axis_ready(_m_axis_ready), - .m_axis_valid(_m_axis_valid), - .m_axis_raddr(m_axis_raddr), - .m_axis_level(m_axis_level), + .clk(m_axis_aclk), + .resetn(m_axis_aresetn), + .m_axis_ready(_m_axis_ready), + .m_axis_valid(_m_axis_valid), + .m_axis_raddr(m_axis_raddr), + .m_axis_level(m_axis_level), - .s_axis_ready(s_axis_ready), - .s_axis_valid(s_axis_valid), - .s_axis_empty(s_axis_empty), - .s_axis_waddr(s_axis_waddr), - .s_axis_room(s_axis_room) + .s_axis_ready(s_axis_ready), + .s_axis_valid(s_axis_valid), + .s_axis_empty(s_axis_empty), + .s_axis_waddr(s_axis_waddr), + .s_axis_room(s_axis_room) ); end always @(posedge s_axis_aclk) begin - if (s_axis_ready) - ram[s_axis_waddr] <= s_axis_data; + if (s_axis_ready) + ram[s_axis_waddr] <= s_axis_data; end if (S_AXIS_REGISTERED == 1) begin @@ -181,19 +181,19 @@ reg [DATA_WIDTH-1:0] data; reg valid; always @(posedge m_axis_aclk) begin - if (m_axis_aresetn == 1'b0) begin - valid <= 1'b0; - end else begin - if (_m_axis_valid) - valid <= 1'b1; - else if (m_axis_ready) - valid <= 1'b0; - end + if (m_axis_aresetn == 1'b0) begin + valid <= 1'b0; + end else begin + if (_m_axis_valid) + valid <= 1'b1; + else if (m_axis_ready) + valid <= 1'b0; + end end always @(posedge m_axis_aclk) begin - if (~valid || m_axis_ready) - data <= ram[m_axis_raddr]; + if (~valid || m_axis_ready) + data <= ram[m_axis_raddr]; end assign _m_axis_ready = ~valid || m_axis_ready; diff --git a/library/util_axis_resize/Makefile b/library/util_axis_resize/Makefile index d6748f31c..61cbf3263 100644 --- a/library/util_axis_resize/Makefile +++ b/library/util_axis_resize/Makefile @@ -5,10 +5,10 @@ #################################################################################### #################################################################################### -M_DEPS := util_axis_resize_ip.tcl M_DEPS += ../scripts/adi_env.tcl M_DEPS += ../scripts/adi_ip.tcl M_DEPS += util_axis_resize.v +M_DEPS += util_axis_resize_ip.tcl M_VIVADO := vivado -mode batch -source @@ -19,6 +19,10 @@ M_FLIST += *.log M_FLIST += component.xml M_FLIST += *.jou M_FLIST += xgui +M_FLIST += *.ip_user_files +M_FLIST += *.srcs +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil @@ -35,7 +39,7 @@ clean-all: util_axis_resize.xpr: $(M_DEPS) - rm -rf $(M_FLIST) + -rm -rf $(M_FLIST) $(M_VIVADO) util_axis_resize_ip.tcl >> util_axis_resize_ip.log 2>&1 #################################################################################### diff --git a/library/util_axis_resize/util_axis_resize.v b/library/util_axis_resize/util_axis_resize.v index 13a6e5634..b7694d7bf 100644 --- a/library/util_axis_resize/util_axis_resize.v +++ b/library/util_axis_resize/util_axis_resize.v @@ -37,16 +37,16 @@ // *************************************************************************** module util_axis_resize ( - input clk, - input resetn, + input clk, + input resetn, - input s_valid, - output s_ready, - input [SLAVE_DATA_WIDTH-1:0] s_data, + input s_valid, + output s_ready, + input [SLAVE_DATA_WIDTH-1:0] s_data, - output m_valid, - input m_ready, - output [MASTER_DATA_WIDTH-1:0] m_data + output m_valid, + input m_ready, + output [MASTER_DATA_WIDTH-1:0] m_data ); parameter MASTER_DATA_WIDTH = 64; @@ -69,32 +69,32 @@ reg valid; always @(posedge clk) begin - if (resetn == 1'b0) begin - count <= RATIO - 1; - valid <= 1'b0; - end else begin - if (count == 'h00 && s_ready == 1'b1 && s_valid == 1'b1) - valid <= 1'b1; - else if (m_ready == 1'b1) - valid <= 1'b0; + if (resetn == 1'b0) begin + count <= RATIO - 1; + valid <= 1'b0; + end else begin + if (count == 'h00 && s_ready == 1'b1 && s_valid == 1'b1) + valid <= 1'b1; + else if (m_ready == 1'b1) + valid <= 1'b0; - if (s_ready == 1'b1 && s_valid == 1'b1) begin - if (count == 'h00) - count <= RATIO - 1; - else - count <= count - 1'b1; - end - end + if (s_ready == 1'b1 && s_valid == 1'b1) begin + if (count == 'h00) + count <= RATIO - 1; + else + count <= count - 1'b1; + end + end end always @(posedge clk) begin - if (s_ready == 1'b1 && s_valid == 1'b1) - if (BIG_ENDIAN == 1) begin - data <= {data[MASTER_DATA_WIDTH-SLAVE_DATA_WIDTH-1:0], s_data}; - end else begin - data <= {s_data, data[MASTER_DATA_WIDTH-1:SLAVE_DATA_WIDTH]}; - end + if (s_ready == 1'b1 && s_valid == 1'b1) + if (BIG_ENDIAN == 1) begin + data <= {data[MASTER_DATA_WIDTH-SLAVE_DATA_WIDTH-1:0], s_data}; + end else begin + data <= {s_data, data[MASTER_DATA_WIDTH-1:SLAVE_DATA_WIDTH]}; + end end assign s_ready = ~valid || m_ready; @@ -111,42 +111,42 @@ reg valid; always @(posedge clk) begin - if (resetn == 1'b0) begin - count <= RATIO - 1; - valid <= 1'b0; - end else begin - if (s_valid == 1'b1 && s_ready == 1'b1) - valid <= 1'b1; - else if (count == 'h0 && m_ready == 1'b1 && m_valid == 1'b1) - valid <= 1'b0; + if (resetn == 1'b0) begin + count <= RATIO - 1; + valid <= 1'b0; + end else begin + if (s_valid == 1'b1 && s_ready == 1'b1) + valid <= 1'b1; + else if (count == 'h0 && m_ready == 1'b1 && m_valid == 1'b1) + valid <= 1'b0; - if (m_ready == 1'b1 && m_valid == 1'b1) begin - if (count == 'h00) - count <= RATIO - 1; - else - count <= count - 1'b1; - end - end + if (m_ready == 1'b1 && m_valid == 1'b1) begin + if (count == 'h00) + count <= RATIO - 1; + else + count <= count - 1'b1; + end + end end always @(posedge clk) begin - if (s_ready == 1'b1 && s_valid == 1'b1) begin - data <= s_data; - end else if (m_ready == 1'b1 && m_valid == 1'b1) begin - if (BIG_ENDIAN == 1) begin - data[SLAVE_DATA_WIDTH-1:MASTER_DATA_WIDTH] <= data[SLAVE_DATA_WIDTH-MASTER_DATA_WIDTH-1:0]; - end else begin - data[SLAVE_DATA_WIDTH-MASTER_DATA_WIDTH-1:0] <= data[SLAVE_DATA_WIDTH-1:MASTER_DATA_WIDTH]; - end - end + if (s_ready == 1'b1 && s_valid == 1'b1) begin + data <= s_data; + end else if (m_ready == 1'b1 && m_valid == 1'b1) begin + if (BIG_ENDIAN == 1) begin + data[SLAVE_DATA_WIDTH-1:MASTER_DATA_WIDTH] <= data[SLAVE_DATA_WIDTH-MASTER_DATA_WIDTH-1:0]; + end else begin + data[SLAVE_DATA_WIDTH-MASTER_DATA_WIDTH-1:0] <= data[SLAVE_DATA_WIDTH-1:MASTER_DATA_WIDTH]; + end + end end assign s_ready = ~valid || (m_ready && count == 'h0); assign m_valid = valid; assign m_data = BIG_ENDIAN == 1 ? - data[SLAVE_DATA_WIDTH-1:SLAVE_DATA_WIDTH-MASTER_DATA_WIDTH] : - data[MASTER_DATA_WIDTH-1:0]; + data[SLAVE_DATA_WIDTH-1:SLAVE_DATA_WIDTH-MASTER_DATA_WIDTH] : + data[MASTER_DATA_WIDTH-1:0]; end endgenerate diff --git a/library/util_bsplit/Makefile b/library/util_bsplit/Makefile index f411a00e7..41a6dee5d 100644 --- a/library/util_bsplit/Makefile +++ b/library/util_bsplit/Makefile @@ -5,11 +5,11 @@ #################################################################################### #################################################################################### -M_DEPS := util_bsplit_ip.tcl M_DEPS += ../scripts/adi_env.tcl M_DEPS += ../scripts/adi_ip.tcl M_DEPS += util_bsplit.v M_DEPS += util_bsplit_constr.xdc +M_DEPS += util_bsplit_ip.tcl M_VIVADO := vivado -mode batch -source @@ -20,6 +20,10 @@ M_FLIST += *.log M_FLIST += component.xml M_FLIST += *.jou M_FLIST += xgui +M_FLIST += *.ip_user_files +M_FLIST += *.srcs +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil @@ -36,7 +40,7 @@ clean-all: util_bsplit.xpr: $(M_DEPS) - rm -rf $(M_FLIST) + -rm -rf $(M_FLIST) $(M_VIVADO) util_bsplit_ip.tcl >> util_bsplit_ip.log 2>&1 #################################################################################### diff --git a/library/util_bsplit/util_bsplit_ip.tcl b/library/util_bsplit/util_bsplit_ip.tcl index 5791f5948..64440b9f8 100644 --- a/library/util_bsplit/util_bsplit_ip.tcl +++ b/library/util_bsplit/util_bsplit_ip.tcl @@ -13,31 +13,31 @@ adi_ip_constraints util_bsplit [list \ "util_bsplit_constr.xdc" ] set_property -dict {driver_value {0} enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 1}} \ - [ipx::get_port split_data_1 [ipx::current_core]] \ + [ipx::get_ports *_1* -of_objects [ipx::current_core]] \ set_property -dict {driver_value {0} enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 2}} \ - [ipx::get_port split_data_2 [ipx::current_core]] \ + [ipx::get_ports *_2* -of_objects [ipx::current_core]] \ set_property -dict {driver_value {0} enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 3}} \ - [ipx::get_port split_data_3 [ipx::current_core]] \ + [ipx::get_ports *_3* -of_objects [ipx::current_core]] \ set_property -dict {driver_value {0} enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 4}} \ - [ipx::get_port split_data_4 [ipx::current_core]] \ + [ipx::get_ports *_4* -of_objects [ipx::current_core]] \ set_property -dict {driver_value {0} enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 5}} \ - [ipx::get_port split_data_5 [ipx::current_core]] \ + [ipx::get_ports *_5* -of_objects [ipx::current_core]] \ set_property -dict {driver_value {0} enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 6}} \ - [ipx::get_port split_data_6 [ipx::current_core]] \ + [ipx::get_ports *_6* -of_objects [ipx::current_core]] \ set_property -dict {driver_value {0} enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 7}} \ - [ipx::get_port split_data_7 [ipx::current_core]] \ + [ipx::get_ports *_7* -of_objects [ipx::current_core]] \ ipx::save_core [ipx::current_core] diff --git a/library/util_ccat/Makefile b/library/util_ccat/Makefile index d4b2f97fb..00939b669 100644 --- a/library/util_ccat/Makefile +++ b/library/util_ccat/Makefile @@ -5,11 +5,11 @@ #################################################################################### #################################################################################### -M_DEPS := util_ccat_ip.tcl M_DEPS += ../scripts/adi_env.tcl M_DEPS += ../scripts/adi_ip.tcl M_DEPS += util_ccat.v M_DEPS += util_ccat_constr.xdc +M_DEPS += util_ccat_ip.tcl M_VIVADO := vivado -mode batch -source @@ -20,6 +20,10 @@ M_FLIST += *.log M_FLIST += component.xml M_FLIST += *.jou M_FLIST += xgui +M_FLIST += *.ip_user_files +M_FLIST += *.srcs +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil @@ -36,7 +40,7 @@ clean-all: util_ccat.xpr: $(M_DEPS) - rm -rf $(M_FLIST) + -rm -rf $(M_FLIST) $(M_VIVADO) util_ccat_ip.tcl >> util_ccat_ip.log 2>&1 #################################################################################### diff --git a/library/util_ccat/util_ccat_ip.tcl b/library/util_ccat/util_ccat_ip.tcl index eb326e84c..3d5843e76 100644 --- a/library/util_ccat/util_ccat_ip.tcl +++ b/library/util_ccat/util_ccat_ip.tcl @@ -13,31 +13,31 @@ adi_ip_constraints util_ccat [list \ "util_ccat_constr.xdc" ] set_property -dict {driver_value {0} enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 1}} \ - [ipx::get_port data_1 [ipx::current_core]] \ + [ipx::get_ports *_1* -of_objects [ipx::current_core]] \ set_property -dict {driver_value {0} enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 2}} \ - [ipx::get_port data_2 [ipx::current_core]] \ + [ipx::get_ports *_2* -of_objects [ipx::current_core]] \ set_property -dict {driver_value {0} enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 3}} \ - [ipx::get_port data_3 [ipx::current_core]] \ + [ipx::get_ports *_3* -of_objects [ipx::current_core]] \ set_property -dict {driver_value {0} enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 4}} \ - [ipx::get_port data_4 [ipx::current_core]] \ + [ipx::get_ports *_4* -of_objects [ipx::current_core]] \ set_property -dict {driver_value {0} enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 5}} \ - [ipx::get_port data_5 [ipx::current_core]] \ + [ipx::get_ports *_5* -of_objects [ipx::current_core]] \ set_property -dict {driver_value {0} enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 6}} \ - [ipx::get_port data_6 [ipx::current_core]] \ + [ipx::get_ports *_6* -of_objects [ipx::current_core]] \ set_property -dict {driver_value {0} enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 7}} \ - [ipx::get_port data_7 [ipx::current_core]] \ + [ipx::get_ports *_7* -of_objects [ipx::current_core]] \ ipx::save_core [ipx::current_core] diff --git a/library/util_clkdiv/Makefile b/library/util_clkdiv/Makefile index b80a36fd4..65d7aa1d0 100644 --- a/library/util_clkdiv/Makefile +++ b/library/util_clkdiv/Makefile @@ -5,10 +5,11 @@ #################################################################################### #################################################################################### -M_DEPS := util_clkdiv_ip.tcl M_DEPS += ../scripts/adi_env.tcl M_DEPS += ../scripts/adi_ip.tcl M_DEPS += util_clkdiv.v +M_DEPS += util_clkdiv_constr.xdc +M_DEPS += util_clkdiv_ip.tcl M_VIVADO := vivado -mode batch -source diff --git a/library/util_clkdiv/util_clkdiv.v b/library/util_clkdiv/util_clkdiv.v index 712375621..9e8dbd659 100644 --- a/library/util_clkdiv/util_clkdiv.v +++ b/library/util_clkdiv/util_clkdiv.v @@ -34,30 +34,71 @@ // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // *************************************************************************** // *************************************************************************** +// Divides the input clock to SEL_0_DIV if clk_sel is 0 or SEL_1_DIV if +// clk_sel is 1. Provides a glitch free output clock +// IP uses BUFR/BUFGCE_DIV and BUFGMUX_CTRL primitives // *************************************************************************** // *************************************************************************** `timescale 1ns/100ps module util_clkdiv ( - clk, - clk_out + input clk, + input clk_sel, + output clk_out ); - input clk; - output clk_out; - +parameter SIM_DEVICE = "7SERIES"; +parameter SEL_0_DIV = "4"; +parameter SEL_1_DIV = "2"; + + wire clk_div_sel_0_s; + wire clk_div_sel_1_s; + +generate if (SIM_DEVICE == "7SERIES") begin + BUFR #( - .BUFR_DIVIDE("4"), + .BUFR_DIVIDE(SEL_0_DIV), .SIM_DEVICE("7SERIES") - ) clk_divide ( + ) clk_divide_sel_0 ( .I(clk), .CE(1), .CLR(0), - .O(clk_div_s)); - - BUFG i_div_clk_gbuf ( - .I (clk_div_s), + .O(clk_div_sel_0_s)); + + BUFR #( + .BUFR_DIVIDE(SEL_1_DIV), + .SIM_DEVICE("7SERIES") + ) clk_divide_sel_1 ( + .I(clk), + .CE(1), + .CLR(0), + .O(clk_div_sel_1_s)); + +end else if (SIM_DEVICE == "ULTRASCALE") begin + + BUFGCE_DIV #( + .BUFGCE_DIVIDE(SEL_0_DIV) + ) clk_divide_sel_0 ( + .I(clk), + .CE(1), + .CLR(0), + .O(clk_div_sel_0_s)); + + BUFGCE_DIV #( + .BUFGCE_DIVIDE(SEL_1_DIV) + ) clk_divide_sel_1 ( + .I(clk), + .CE(1), + .CLR(0), + .O(clk_div_sel_1_s)); + +end endgenerate + + BUFGMUX_CTRL i_div_clk_gbuf ( + .I0(clk_div_sel_0_s), // 1-bit input: Clock input (S=0) + .I1(clk_div_sel_1_s), // 1-bit input: Clock input (S=1) + .S(clk_sel), .O (clk_out)); endmodule // util_clkdiv diff --git a/library/util_clkdiv/util_clkdiv_alt.v b/library/util_clkdiv/util_clkdiv_alt.v new file mode 100644 index 000000000..3c79f1fce --- /dev/null +++ b/library/util_clkdiv/util_clkdiv_alt.v @@ -0,0 +1,82 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2014(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// Divides the input clock to SEL_0_DIV if clk_sel is 0 or SEL_1_DIV if +// clk_sel is 1. Provides a glitch free output clock +// IP uses BUFR/BUFGCE_DIV and BUFGMUX_CTRL primitives +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module util_clkdiv_alt #( + parameter SIM_DEVICE = "CYCLONE5", + parameter CLOCK_TYPE = "Global Clock") ( + + input clk, + input reset, + output clk_out, + output reset_out + ); + +reg enable; +reg reset_d1; + +assign reset_out = reset | reset_d1; + +always @(posedge clk) begin + reset_d1 <= reset; +end + +always @(posedge clk) begin + enable <= ~enable; +end + +generate if (SIM_DEVICE == "CYCLONE5") begin + cyclonev_clkena #( + .clock_type ("Global Clock"), + .ena_register_mode ("falling edge"), + .lpm_type ("cyclonev_clkena") + ) clock_divider_by_2 ( + .ena(enable), + .enaout(), + .inclk(clk), +// .clkselect (2'b0), + .outclk(clk_out)); + +end endgenerate + +endmodule // util_clkdiv_alt diff --git a/library/util_clkdiv/util_clkdiv_constr.xdc b/library/util_clkdiv/util_clkdiv_constr.xdc new file mode 100644 index 000000000..5cbe1488e --- /dev/null +++ b/library/util_clkdiv/util_clkdiv_constr.xdc @@ -0,0 +1,2 @@ +set_clock_groups -group [get_clocks clk_div_sel_0_s] -group [get_clocks clk_div_sel_1_s] -logically_exclusive +set_false_path -to [get_pins i_div_clk_gbuf/S*] diff --git a/library/util_clkdiv/util_clkdiv_hw.tcl b/library/util_clkdiv/util_clkdiv_hw.tcl new file mode 100644 index 000000000..310801727 --- /dev/null +++ b/library/util_clkdiv/util_clkdiv_hw.tcl @@ -0,0 +1,25 @@ + +package require -exact qsys 13.0 +source ../scripts/adi_env.tcl +source ../scripts/adi_ip_alt.tcl + + +set_module_property NAME util_clkdiv +set_module_property DESCRIPTION "Clock Division Utility" +set_module_property VERSION 1.0 +set_module_property GROUP "Analog Devices" +set_module_property DISPLAY_NAME util_clkdiv + +# files + +add_fileset quartus_synth QUARTUS_SYNTH "" "Quartus Synthesis" +set_fileset_property quartus_synth TOP_LEVEL util_clkdiv_alt +add_fileset_file util_clkdiv_alt.v VERILOG PATH util_clkdiv_alt.v TOP_LEVEL_FILE + +# defaults + +ad_alt_intf clock clk input 1 +ad_alt_intf reset reset input 1 if_clk +ad_alt_intf clock clk_out output 1 +ad_alt_intf reset reset_out output 1 if_clk_out + diff --git a/library/util_clkdiv/util_clkdiv_ip.tcl b/library/util_clkdiv/util_clkdiv_ip.tcl index 66286de2a..998098dd4 100644 --- a/library/util_clkdiv/util_clkdiv_ip.tcl +++ b/library/util_clkdiv/util_clkdiv_ip.tcl @@ -1,10 +1,28 @@ source ../scripts/adi_env.tcl source $ad_hdl_dir/library/scripts/adi_ip.tcl - + adi_ip_create util_clkdiv adi_ip_files util_clkdiv [list \ -"util_clkdiv.v" ] - + "util_clkdiv_constr.xdc" \ + "util_clkdiv.v" ] + adi_ip_properties_lite util_clkdiv - + +adi_ip_constraints util_clkdiv [list \ + "util_clkdiv_constr.xdc" ] + +set_property driver_value 0 [ipx::get_ports clk_sel -of_objects [ipx::current_core]] + +set_property value_validation_type list [ipx::get_user_parameters SIM_DEVICE -of_objects [ipx::current_core]] +set_property value_validation_list {7SERIES ULTRASCALE} [ipx::get_user_parameters SIM_DEVICE -of_objects [ipx::current_core]] + +set_property value_validation_type list [ipx::get_user_parameters SEL_0_DIV -of_objects [ipx::current_core]] +set_property value_validation_list {1 2 3 4 5 6 7 8} [ipx::get_user_parameters SEL_0_DIV -of_objects [ipx::current_core]] + +set_property value_validation_type list [ipx::get_user_parameters SEL_1_DIV -of_objects [ipx::current_core]] +set_property value_validation_list {1 2 3 4 5 6 7 8} [ipx::get_user_parameters SEL_1_DIV -of_objects [ipx::current_core]] + +adi_add_bus clk_out master "xilinx.com:signal:clock_rtl:1.0" "xilinx.com:signal:clock:1.0" \ + [list {"clk_out" "CLK"}] + ipx::save_core [ipx::current_core] diff --git a/library/util_cpack/Makefile b/library/util_cpack/Makefile index 02c8b0cfc..ee2ec01cb 100644 --- a/library/util_cpack/Makefile +++ b/library/util_cpack/Makefile @@ -5,13 +5,13 @@ #################################################################################### #################################################################################### -M_DEPS := util_cpack_ip.tcl M_DEPS += ../scripts/adi_env.tcl M_DEPS += ../scripts/adi_ip.tcl -M_DEPS += util_cpack_mux.v -M_DEPS += util_cpack_dsf.v M_DEPS += util_cpack.v M_DEPS += util_cpack_constr.xdc +M_DEPS += util_cpack_dsf.v +M_DEPS += util_cpack_ip.tcl +M_DEPS += util_cpack_mux.v M_VIVADO := vivado -mode batch -source @@ -22,6 +22,10 @@ M_FLIST += *.log M_FLIST += component.xml M_FLIST += *.jou M_FLIST += xgui +M_FLIST += *.ip_user_files +M_FLIST += *.srcs +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil @@ -38,7 +42,7 @@ clean-all: util_cpack.xpr: $(M_DEPS) - rm -rf $(M_FLIST) + -rm -rf $(M_FLIST) $(M_VIVADO) util_cpack_ip.tcl >> util_cpack_ip.log 2>&1 #################################################################################### diff --git a/library/util_cpack/util_cpack_hw.tcl b/library/util_cpack/util_cpack_hw.tcl index 889704d3c..cb375a5b3 100755 --- a/library/util_cpack/util_cpack_hw.tcl +++ b/library/util_cpack/util_cpack_hw.tcl @@ -39,67 +39,97 @@ set_parameter_property NUM_OF_CHANNELS HDL_PARAMETER true # defaults ad_alt_intf clock adc_clk input 1 -ad_alt_intf reset adc_rst input 1 if_adc_clk -ad_alt_intf signal adc_valid output 1 valid -ad_alt_intf signal adc_sync output 1 sync +ad_alt_intf reset adc_rst input 1 if_adc_clk + +ad_alt_intf signal adc_valid output 1 valid +ad_alt_intf signal adc_sync output 1 sync ad_alt_intf signal adc_data output NUM_OF_CHANNELS*CHANNEL_DATA_WIDTH data -add_interface fifo_ch_0 conduit end -#set_interface_property fifo_ch_0 associatedClock if_adc_clk -add_interface_port fifo_ch_0 adc_enable_0 enable Input 1 -add_interface_port fifo_ch_0 adc_valid_0 valid Input 1 -add_interface_port fifo_ch_0 adc_data_0 data Input CHANNEL_DATA_WIDTH +add_interface adc_ch_0 conduit end +add_interface_port adc_ch_0 adc_enable_0 enable Input 1 +add_interface_port adc_ch_0 adc_valid_0 valid Input 1 +add_interface_port adc_ch_0 adc_data_0 data Input CHANNEL_DATA_WIDTH + +set_interface_property adc_ch_0 associatedClock if_adc_clk +set_interface_property adc_ch_0 associatedReset none proc p_util_cpack {} { if {[get_parameter_value NUM_OF_CHANNELS] > 1} { - add_interface fifo_ch_1 conduit end - #set_interface_property fifo_ch_1 associatedClock if_adc_clk - add_interface_port fifo_ch_1 adc_enable_1 enable Input 1 - add_interface_port fifo_ch_1 adc_valid_1 valid Input 1 - add_interface_port fifo_ch_1 adc_data_1 data Input CHANNEL_DATA_WIDTH + + add_interface adc_ch_1 conduit end + add_interface_port adc_ch_1 adc_enable_1 enable Input 1 + add_interface_port adc_ch_1 adc_valid_1 valid Input 1 + add_interface_port adc_ch_1 adc_data_1 data Input CHANNEL_DATA_WIDTH + + set_interface_property adc_ch_1 associatedClock if_adc_clk + set_interface_property adc_ch_1 associatedReset none } + if {[get_parameter_value NUM_OF_CHANNELS] > 2} { - add_interface fifo_ch_2 conduit end - #set_interface_property fifo_ch_2 associatedClock if_adc_clk - add_interface_port fifo_ch_2 adc_enable_2 enable Input 1 - add_interface_port fifo_ch_2 adc_valid_2 valid Input 1 - add_interface_port fifo_ch_2 adc_data_2 data Input CHANNEL_DATA_WIDTH + + add_interface adc_ch_2 conduit end + add_interface_port adc_ch_2 adc_enable_2 enable Input 1 + add_interface_port adc_ch_2 adc_valid_2 valid Input 1 + add_interface_port adc_ch_2 adc_data_2 data Input CHANNEL_DATA_WIDTH + + set_interface_property adc_ch_2 associatedClock if_adc_clk + set_interface_property adc_ch_2 associatedReset none } + if {[get_parameter_value NUM_OF_CHANNELS] > 3} { - add_interface fifo_ch_3 conduit end - #set_interface_property fifo_ch_3 associatedClock if_adc_clk - add_interface_port fifo_ch_3 adc_enable_3 enable Input 1 - add_interface_port fifo_ch_3 adc_valid_3 valid Input 1 - add_interface_port fifo_ch_3 adc_data_3 data Input CHANNEL_DATA_WIDTH + + add_interface adc_ch_3 conduit end + add_interface_port adc_ch_3 adc_enable_3 enable Input 1 + add_interface_port adc_ch_3 adc_valid_3 valid Input 1 + add_interface_port adc_ch_3 adc_data_3 data Input CHANNEL_DATA_WIDTH + + set_interface_property adc_ch_3 associatedClock if_adc_clk + set_interface_property adc_ch_3 associatedReset none } + if {[get_parameter_value NUM_OF_CHANNELS] > 4} { - add_interface fifo_ch_4 conduit end - #set_interface_property fifo_ch_4 associatedClock if_adc_clk - add_interface_port fifo_ch_4 adc_enable_4 enable Input 1 - add_interface_port fifo_ch_4 adc_valid_4 valid Input 1 - add_interface_port fifo_ch_4 adc_data_4 data Input CHANNEL_DATA_WIDTH + + add_interface adc_ch_4 conduit end + add_interface_port adc_ch_4 adc_enable_4 enable Input 1 + add_interface_port adc_ch_4 adc_valid_4 valid Input 1 + add_interface_port adc_ch_4 adc_data_4 data Input CHANNEL_DATA_WIDTH + + set_interface_property adc_ch_4 associatedClock if_adc_clk + set_interface_property adc_ch_4 associatedReset none } + if {[get_parameter_value NUM_OF_CHANNELS] > 5} { - add_interface fifo_ch_5 conduit end - #set_interface_property fifo_ch_5 associatedClock if_adc_clk - add_interface_port fifo_ch_5 adc_enable_5 enable Input 1 - add_interface_port fifo_ch_5 adc_valid_5 valid Input 1 - add_interface_port fifo_ch_5 adc_data_5 data Input CHANNEL_DATA_WIDTH + + add_interface adc_ch_5 conduit end + add_interface_port adc_ch_5 adc_enable_5 enable Input 1 + add_interface_port adc_ch_5 adc_valid_5 valid Input 1 + add_interface_port adc_ch_5 adc_data_5 data Input CHANNEL_DATA_WIDTH + + set_interface_property adc_ch_5 associatedClock if_adc_clk + set_interface_property adc_ch_5 associatedReset none } + if {[get_parameter_value NUM_OF_CHANNELS] > 6} { - add_interface fifo_ch_6 conduit end - #set_interface_property fifo_ch_6 associatedClock if_adc_clk - add_interface_port fifo_ch_6 adc_enable_6 enable Input 1 - add_interface_port fifo_ch_6 adc_valid_6 valid Input 1 - add_interface_port fifo_ch_6 adc_data_6 data Input CHANNEL_DATA_WIDTH + + add_interface adc_ch_6 conduit end + add_interface_port adc_ch_6 adc_enable_6 enable Input 1 + add_interface_port adc_ch_6 adc_valid_6 valid Input 1 + add_interface_port adc_ch_6 adc_data_6 data Input CHANNEL_DATA_WIDTH + + set_interface_property adc_ch_6 associatedClock if_adc_clk + set_interface_property adc_ch_6 associatedReset none } + if {[get_parameter_value NUM_OF_CHANNELS] > 7} { - add_interface fifo_ch_7 conduit end - #set_interface_property fifo_ch_7 associatedClock if_adc_clk - add_interface_port fifo_ch_7 adc_enable_7 enable Input 1 - add_interface_port fifo_ch_7 adc_valid_7 valid Input 1 - add_interface_port fifo_ch_7 adc_data_7 data Input CHANNEL_DATA_WIDTH + + add_interface adc_ch_7 conduit end + add_interface_port adc_ch_7 adc_enable_7 enable Input 1 + add_interface_port adc_ch_7 adc_valid_7 valid Input 1 + add_interface_port adc_ch_7 adc_data_7 data Input CHANNEL_DATA_WIDTH + + set_interface_property adc_ch_7 associatedClock if_adc_clk + set_interface_property adc_ch_7 associatedReset none } } diff --git a/library/util_dac_unpack/util_dac_unpack.v b/library/util_dac_unpack/util_dac_unpack.v deleted file mode 100644 index bf2edbf3d..000000000 --- a/library/util_dac_unpack/util_dac_unpack.v +++ /dev/null @@ -1,236 +0,0 @@ -// *************************************************************************** -// *************************************************************************** -// Copyright 2014(c) Analog Devices, Inc. -// -// All rights reserved. -// -// Redistribution and use in source and binary forms, with or without modification, -// are permitted provided that the following conditions are met: -// - Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// - Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in -// the documentation and/or other materials provided with the -// distribution. -// - Neither the name of Analog Devices, Inc. nor the names of its -// contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// - The use of this software may or may not infringe the patent rights -// of one or more patent holders. This license does not release you -// from the requirement that you obtain separate licenses from these -// patent holders to use this software. -// - Use of the software either in source or binary form, must be run -// on or directly connected to an Analog Devices Inc. component. -// -// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, -// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A -// PARTICULAR PURPOSE ARE DISCLAIMED. -// -// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY -// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF -// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// *************************************************************************** -// *************************************************************************** -// *************************************************************************** -// *************************************************************************** - -`timescale 1ns/100ps - -module util_dac_unpack ( - - clk, - - dac_enable_00, - dac_valid_00, - dac_data_00, - - dac_enable_01, - dac_valid_01, - dac_data_01, - - dac_enable_02, - dac_valid_02, - dac_data_02, - - dac_enable_03, - dac_valid_03, - dac_data_03, - - dac_enable_04, - dac_valid_04, - dac_data_04, - - dac_enable_05, - dac_valid_05, - dac_data_05, - - dac_enable_06, - dac_valid_06, - dac_data_06, - - dac_enable_07, - dac_valid_07, - dac_data_07, - - fifo_valid, - dma_rd, - dma_data); - - parameter NUM_OF_CHANNELS = 8; // valid values are 4 and 8 - parameter DATA_WIDTH = 16; - - input clk; - - input dac_enable_00; - input dac_valid_00; - output [DATA_WIDTH-1:0] dac_data_00; - - input dac_enable_01; - input dac_valid_01; - output [DATA_WIDTH-1:0] dac_data_01; - - input dac_enable_02; - input dac_valid_02; - output [DATA_WIDTH-1:0] dac_data_02; - - input dac_enable_03; - input dac_valid_03; - output [DATA_WIDTH-1:0] dac_data_03; - - input dac_enable_04; - input dac_valid_04; - output [DATA_WIDTH-1:0] dac_data_04; - - input dac_enable_05; - input dac_valid_05; - output [DATA_WIDTH-1:0] dac_data_05; - - input dac_enable_06; - input dac_valid_06; - output [DATA_WIDTH-1:0] dac_data_06; - - input dac_enable_07; - input dac_valid_07; - output [DATA_WIDTH-1:0] dac_data_07; - - input fifo_valid; - output dma_rd; - input [NUM_OF_CHANNELS*DATA_WIDTH-1:0] dma_data; - - - localparam DMA_DATA_WIDTH = NUM_OF_CHANNELS*DATA_WIDTH; - - wire [NUM_OF_CHANNELS-1:0] dac_enable; - wire [NUM_OF_CHANNELS-1:0] dac_valid; - - wire [DATA_WIDTH-1:0] data_array[0:NUM_OF_CHANNELS-1]; - - wire [$clog2(NUM_OF_CHANNELS)-1:0] offset [0:NUM_OF_CHANNELS-1]; - wire dac_chan_valid; - - reg [DATA_WIDTH*NUM_OF_CHANNELS-1:0] dac_data = 'h00; - reg [DMA_DATA_WIDTH-1:0] buffer = 'h00; - reg dma_rd = 1'b0; - reg [$clog2(NUM_OF_CHANNELS)-1:0] rd_counter = 'h00; - reg [$clog2(NUM_OF_CHANNELS)-1:0] req_counter = 'h00; - reg [NUM_OF_CHANNELS-1:0] dac_enable_d1 = 'h00; - - assign dac_enable[0] = dac_enable_00; - assign dac_enable[1] = dac_enable_01; - assign dac_enable[2] = dac_enable_02; - assign dac_enable[3] = dac_enable_03; - assign dac_valid[0] = dac_valid_00; - assign dac_valid[1] = dac_valid_01; - assign dac_valid[2] = dac_valid_02; - assign dac_valid[3] = dac_valid_03; - assign dac_data_00 = dac_data[DATA_WIDTH*1-1:DATA_WIDTH*0]; - assign dac_data_01 = dac_data[DATA_WIDTH*2-1:DATA_WIDTH*1]; - assign dac_data_02 = dac_data[DATA_WIDTH*3-1:DATA_WIDTH*2]; - assign dac_data_03 = dac_data[DATA_WIDTH*4-1:DATA_WIDTH*3]; - - generate - if (NUM_OF_CHANNELS >= 8) begin - assign dac_enable[4] = dac_enable_04; - assign dac_enable[5] = dac_enable_05; - assign dac_enable[6] = dac_enable_06; - assign dac_enable[7] = dac_enable_07; - assign dac_valid[4] = dac_valid_04; - assign dac_valid[5] = dac_valid_05; - assign dac_valid[6] = dac_valid_06; - assign dac_valid[7] = dac_valid_07; - assign dac_data_04 = dac_data[DATA_WIDTH*5-1:DATA_WIDTH*4]; - assign dac_data_05 = dac_data[DATA_WIDTH*6-1:DATA_WIDTH*5]; - assign dac_data_06 = dac_data[DATA_WIDTH*7-1:DATA_WIDTH*6]; - assign dac_data_07 = dac_data[DATA_WIDTH*8-1:DATA_WIDTH*7]; - end else begin - assign dac_data_04 = 'h0; - assign dac_data_05 = 'h0; - assign dac_data_06 = 'h0; - assign dac_data_07 = 'h0; - end - endgenerate - - function integer enable_reduce; - input n; - integer n; - integer i; - begin - enable_reduce = 0; - for (i = 0; i < n; i = i + 1) - enable_reduce = enable_reduce + dac_enable[i]; - end - endfunction - - assign dac_chan_valid = |dac_valid; - - always @(posedge clk) begin - if (fifo_valid == 1'b1) begin - buffer <= dma_data; - rd_counter <= 'h0; - end else if (dac_chan_valid == 1'b1) begin - rd_counter <= rd_counter + enable_reduce(NUM_OF_CHANNELS); - end - end - - always @(posedge clk) begin - dma_rd <= 1'b0; - if (dac_enable != dac_enable_d1) begin - req_counter <= 'h00; - end else if (dac_chan_valid == 1'b1) begin - req_counter <= req_counter + enable_reduce(NUM_OF_CHANNELS); - if (req_counter == 'h00) begin - dma_rd <= 1'b1; - end - end - dac_enable_d1 <= dac_enable; - end - - generate - genvar i; - for (i = 0; i < NUM_OF_CHANNELS; i = i + 1) begin : gen_data_array - assign data_array[i] = buffer[DATA_WIDTH+i*DATA_WIDTH-1:i*DATA_WIDTH]; - end - endgenerate - - generate - genvar j; - for (j = 0; j < NUM_OF_CHANNELS; j = j + 1) begin : gen_dac_data - assign offset[j] = rd_counter + enable_reduce(j); - always @(posedge clk) begin - if (dac_chan_valid) begin - if (dac_enable[j]) - dac_data[DATA_WIDTH+j*DATA_WIDTH-1:j*DATA_WIDTH] <= data_array[offset[j]]; - else - dac_data[DATA_WIDTH+j*DATA_WIDTH-1:j*DATA_WIDTH] <= 'h0000; - end - end - end - endgenerate - -endmodule - -// *************************************************************************** -// *************************************************************************** diff --git a/library/util_dac_unpack/util_dac_unpack_hw.tcl b/library/util_dac_unpack/util_dac_unpack_hw.tcl deleted file mode 100644 index 549860d43..000000000 --- a/library/util_dac_unpack/util_dac_unpack_hw.tcl +++ /dev/null @@ -1,81 +0,0 @@ - -package require -exact qsys 13.0 -source ../scripts/adi_env.tcl - -set_module_property NAME util_dac_unpack -set_module_property DESCRIPTION "Util DAC data unpacker" -set_module_property VERSION 1.0 -set_module_property GROUP "Analog Devices" -set_module_property DISPLAY_NAME util_dac_unpack -set_module_property ELABORATION_CALLBACK util_dac_unpack_elaborate - -# files - -add_fileset quartus_synth QUARTUS_SYNTH "" "Quartus Synthesis" -set_fileset_property quartus_synth TOP_LEVEL util_dac_unpack -add_fileset_file util_dac_unpack.v VERILOG PATH util_dac_unpack.v - -add_parameter NUM_OF_CHANNELS INTEGER 0 -set_parameter_property NUM_OF_CHANNELS DEFAULT_VALUE 8 -set_parameter_property NUM_OF_CHANNELS ALLOWED_RANGES {4 8} -set_parameter_property NUM_OF_CHANNELS DESCRIPTION "Valid values are 4 and 8" -set_parameter_property NUM_OF_CHANNELS DISPLAY_NAME NUM_OF_CHANNELS -set_parameter_property NUM_OF_CHANNELS TYPE INTEGER -set_parameter_property NUM_OF_CHANNELS UNITS None -set_parameter_property NUM_OF_CHANNELS HDL_PARAMETER true - -add_parameter DATA_WIDTH INTEGER 0 -set_parameter_property DATA_WIDTH DEFAULT_VALUE 16 -set_parameter_property DATA_WIDTH DISPLAY_NAME DATA_WIDTH -set_parameter_property DATA_WIDTH TYPE INTEGER -set_parameter_property DATA_WIDTH UNITS None -set_parameter_property DATA_WIDTH HDL_PARAMETER true - -add_interface data_clock clock end -add_interface_port data_clock clk clk Input 1 - -proc util_dac_unpack_elaborate {} { - set DW [ get_parameter_value DATA_WIDTH ] - set CHAN [ get_parameter_value NUM_OF_CHANNELS ] - - add_interface channels_data conduit end - set_interface_property channels_data associatedClock data_clock - add_interface_port channels_data dac_enable_00 dac_enable_00 Input 1 - add_interface_port channels_data dac_valid_00 dac_valid_00 Input 1 - add_interface_port channels_data dac_data_00 dac_data_00 Output DATA_WIDTH - - add_interface_port channels_data dac_enable_01 dac_enable_01 Input 1 - add_interface_port channels_data dac_valid_01 dac_valid_01 Input 1 - add_interface_port channels_data dac_data_01 dac_data_01 Output DATA_WIDTH - - add_interface_port channels_data dac_enable_02 dac_enable_02 Input 1 - add_interface_port channels_data dac_valid_02 dac_valid_02 Input 1 - add_interface_port channels_data dac_data_02 dac_data_02 Output DATA_WIDTH - - add_interface_port channels_data dac_enable_03 dac_enable_03 Input 1 - add_interface_port channels_data dac_valid_03 dac_valid_03 Input 1 - add_interface_port channels_data dac_data_03 dac_data_03 Output DATA_WIDTH - - if {$CHAN == 8} { - add_interface_port channels_data dac_enable_04 dac_enable_04 Input 1 - add_interface_port channels_data dac_valid_04 dac_valid_04 Input 1 - add_interface_port channels_data dac_data_04 dac_data_04 Output DATA_WIDTH - - add_interface_port channels_data dac_enable_05 dac_enable_05 Input 1 - add_interface_port channels_data dac_valid_05 dac_valid_05 Input 1 - add_interface_port channels_data dac_data_05 dac_data_05 Output DATA_WIDTH - - add_interface_port channels_data dac_enable_06 dac_enable_06 Input 1 - add_interface_port channels_data dac_valid_06 dac_valid_06 Input 1 - add_interface_port channels_data dac_data_06 dac_data_06 Output DATA_WIDTH - - add_interface_port channels_data dac_enable_07 dac_enable_07 Input 1 - add_interface_port channels_data dac_valid_07 dac_valid_07 Input 1 - add_interface_port channels_data dac_data_07 dac_data_07 Output DATA_WIDTH - } - - add_interface_port channels_data fifo_valid fifo_valid Input 1 - add_interface_port channels_data dma_rd dma_rd Output 1 - add_interface_port channels_data dma_data dma_data Input [expr {$DW * $CHAN}] -} - diff --git a/library/util_dac_unpack/util_dac_unpack_ip.tcl b/library/util_dac_unpack/util_dac_unpack_ip.tcl deleted file mode 100644 index d5ada0d9b..000000000 --- a/library/util_dac_unpack/util_dac_unpack_ip.tcl +++ /dev/null @@ -1,46 +0,0 @@ -# ip - -source ../scripts/adi_env.tcl -source $ad_hdl_dir/library/scripts/adi_ip.tcl - -adi_ip_create util_dac_unpack -adi_ip_files util_dac_unpack [list \ - "util_dac_unpack.v" ] - -adi_ip_properties_lite util_dac_unpack - -ipx::remove_bus_interface {s} [ipx::current_core] -ipx::remove_bus_interface {m} [ipx::current_core] -ipx::remove_bus_interface {fifo} [ipx::current_core] -ipx::remove_bus_interface {signal_clock} [ipx::current_core] - -ipx::remove_memory_map {m} [ipx::current_core] -ipx::remove_address_space {s} [ipx::current_core] -ipx::remove_address_space {fifo} [ipx::current_core] - -for {set i 0} {$i < 8} {incr i} { - foreach port {"dac_enable" "dac_valid" "dac_data"} { - set name [format "%s_%.2d" $port $i] - set_property ENABLEMENT_DEPENDENCY \ - "(spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > $i)" \ - [ipx::get_ports $name] - } - foreach port {"dac_enable" "dac_valid"} { - set name [format "%s_%.2d" $port $i] - set_property DRIVER_VALUE "0" [ipx::get_ports $name] - } -} - -adi_add_bus "fifo_rd" "master" \ - "analog.com:interface:fifo_rd_rtl:1.0" \ - "analog.com:interface:fifo_rd:1.0" \ - { \ - {"dma_rd" "EN"} \ - {"dma_data" "DATA"} \ - {"fifo_valid" "VALID"} \ - } -adi_add_bus_clock "clk" "fifo_rd" - -ipx::save_core [ipx::current_core] - - diff --git a/library/util_dacfifo/Makefile b/library/util_dacfifo/Makefile index 0cf20b4bd..796e81932 100644 --- a/library/util_dacfifo/Makefile +++ b/library/util_dacfifo/Makefile @@ -5,11 +5,12 @@ #################################################################################### #################################################################################### -M_DEPS := util_dacfifo_ip.tcl +M_DEPS += ../common/ad_mem.v M_DEPS += ../scripts/adi_env.tcl M_DEPS += ../scripts/adi_ip.tcl -M_DEPS += ../common/ad_mem.v M_DEPS += util_dacfifo.v +M_DEPS += util_dacfifo_constr.xdc +M_DEPS += util_dacfifo_ip.tcl M_VIVADO := vivado -mode batch -source @@ -20,6 +21,10 @@ M_FLIST += *.log M_FLIST += component.xml M_FLIST += *.jou M_FLIST += xgui +M_FLIST += *.ip_user_files +M_FLIST += *.srcs +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil @@ -36,7 +41,7 @@ clean-all: util_dacfifo.xpr: $(M_DEPS) - rm -rf $(M_FLIST) + -rm -rf $(M_FLIST) $(M_VIVADO) util_dacfifo_ip.tcl >> util_dacfifo_ip.log 2>&1 #################################################################################### diff --git a/library/util_dac_unpack/Makefile b/library/util_extract/Makefile similarity index 77% rename from library/util_dac_unpack/Makefile rename to library/util_extract/Makefile index 87fe8fceb..bd2db55b0 100644 --- a/library/util_dac_unpack/Makefile +++ b/library/util_extract/Makefile @@ -5,10 +5,10 @@ #################################################################################### #################################################################################### -M_DEPS := util_dac_unpack_ip.tcl M_DEPS += ../scripts/adi_env.tcl M_DEPS += ../scripts/adi_ip.tcl -M_DEPS += util_dac_unpack.v +M_DEPS += util_extract.v +M_DEPS += util_extract_ip.tcl M_VIVADO := vivado -mode batch -source @@ -19,12 +19,16 @@ M_FLIST += *.log M_FLIST += component.xml M_FLIST += *.jou M_FLIST += xgui +M_FLIST += *.ip_user_files +M_FLIST += *.srcs +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil .PHONY: all clean clean-all -all: util_dac_unpack.xpr +all: util_extract.xpr clean:clean-all @@ -34,9 +38,9 @@ clean-all: rm -rf $(M_FLIST) -util_dac_unpack.xpr: $(M_DEPS) - rm -rf $(M_FLIST) - $(M_VIVADO) util_dac_unpack_ip.tcl >> util_dac_unpack_ip.log 2>&1 +util_extract.xpr: $(M_DEPS) + -rm -rf $(M_FLIST) + $(M_VIVADO) util_extract_ip.tcl >> util_extract_ip.log 2>&1 #################################################################################### #################################################################################### diff --git a/library/util_extract/util_extract.v b/library/util_extract/util_extract.v new file mode 100644 index 000000000..155a49558 --- /dev/null +++ b/library/util_extract/util_extract.v @@ -0,0 +1,94 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module util_extract ( + + clk, + + data_in, + data_in_trigger, + data_valid, + + data_out, + trigger_out + +); + + parameter CHANNELS = 2; + + parameter DW = CHANNELS * 16; + input clk; + input [DW-1:0] data_in; + input [DW-1:0] data_in_trigger; + input data_valid; + + output [DW-1:0] data_out; + output trigger_out; + + // loop variables + + genvar n; + + reg trigger_out; + reg trigger_d1; + + wire [15:0] trigger; // 16 maximum channels + + generate + for (n = 0; n < CHANNELS; n = n + 1) begin: g_data_out + assign data_out[(n+1)*16-1:n*16] = {data_in[(n*16)+14],data_in[(n*16)+14:n*16]}; + assign trigger[n] = data_in_trigger[(16*n)+15]; + end + for (n = CHANNELS; n < 16; n = n + 1) begin: g_trigger_out + assign trigger[n] = 1'b0; + end + endgenerate + + // compensate delay in the FIFO + always @(posedge clk) begin + if (data_valid == 1'b1) begin + trigger_d1 <= |trigger; + trigger_out <= trigger_d1; + end + end + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/library/util_extract/util_extract_ip.tcl b/library/util_extract/util_extract_ip.tcl new file mode 100644 index 000000000..a6396741e --- /dev/null +++ b/library/util_extract/util_extract_ip.tcl @@ -0,0 +1,15 @@ +# ip + +source ../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip.tcl + +adi_ip_create util_extract +adi_ip_files util_extract [list \ + "util_extract.v" ] + +adi_ip_properties_lite util_extract + +ipx::remove_all_bus_interface [ipx::current_core] +ipx::save_core [ipx::current_core] + + diff --git a/library/util_adc_pack/Makefile b/library/util_fir_dec/Makefile similarity index 77% rename from library/util_adc_pack/Makefile rename to library/util_fir_dec/Makefile index 6bb0658f2..8bc0a7537 100644 --- a/library/util_adc_pack/Makefile +++ b/library/util_fir_dec/Makefile @@ -5,10 +5,10 @@ #################################################################################### #################################################################################### -M_DEPS := util_adc_pack_ip.tcl M_DEPS += ../scripts/adi_env.tcl M_DEPS += ../scripts/adi_ip.tcl -M_DEPS += util_adc_pack.v +M_DEPS += util_fir_dec.v +M_DEPS += util_fir_dec_ip.tcl M_VIVADO := vivado -mode batch -source @@ -19,12 +19,16 @@ M_FLIST += *.log M_FLIST += component.xml M_FLIST += *.jou M_FLIST += xgui +M_FLIST += *.ip_user_files +M_FLIST += *.srcs +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil .PHONY: all clean clean-all -all: util_adc_pack.xpr +all: util_fir_dec.xpr clean:clean-all @@ -34,9 +38,9 @@ clean-all: rm -rf $(M_FLIST) -util_adc_pack.xpr: $(M_DEPS) - rm -rf $(M_FLIST) - $(M_VIVADO) util_adc_pack_ip.tcl >> util_adc_pack_ip.log 2>&1 +util_fir_dec.xpr: $(M_DEPS) + -rm -rf $(M_FLIST) + $(M_VIVADO) util_fir_dec_ip.tcl >> util_fir_dec_ip.log 2>&1 #################################################################################### #################################################################################### diff --git a/library/util_fir_dec/coefile_dec.coe b/library/util_fir_dec/coefile_dec.coe new file mode 100644 index 000000000..06a603964 --- /dev/null +++ b/library/util_fir_dec/coefile_dec.coe @@ -0,0 +1,134 @@ +; XILINX CORE Generator(tm)Distributed Arithmetic FIR filter coefficient (.COE) File +; Generated by MATLAB(R) 9.0 and the DSP System Toolbox 9.2. +; Generated on: 24-Oct-2016 14:07:18 +Radix = 10; +Coefficient_Width = 16; +CoefData = 0, + -1, + -2, + -4, + -6, + -8, + -8, + -5, + 0, + 8, + 18, + 29, + 37, + 41, + 37, + 23, + 0, + -31, + -67, + -100, + -124, + -130, + -113, + -69, + 0, + 87, + 181, + 263, + 318, + 326, + 277, + 166, + 0, + -202, + -410, + -589, + -700, + -709, + -594, + -352, + 0, + 420, + 848, + 1211, + 1432, + 1446, + 1210, + 717, + 0, + -863, +-1756, +-2535, +-3043, +-3133, +-2690, +-1646, + 0, + 2180, + 4757, + 7534, +10278, +12743, +14697, +15951, +16384, +15951, +14697, +12743, +10278, + 7534, + 4757, + 2180, + 0, +-1646, +-2690, +-3133, +-3043, +-2535, +-1756, + -863, + 0, + 717, + 1210, + 1446, + 1432, + 1211, + 848, + 420, + 0, + -352, + -594, + -709, + -700, + -589, + -410, + -202, + 0, + 166, + 277, + 326, + 318, + 263, + 181, + 87, + 0, + -69, + -113, + -130, + -124, + -100, + -67, + -31, + 0, + 23, + 37, + 41, + 37, + 29, + 18, + 8, + 0, + -5, + -8, + -8, + -6, + -4, + -2, + -1, + 0; diff --git a/library/util_fir_dec/util_fir_dec.v b/library/util_fir_dec/util_fir_dec.v new file mode 100644 index 000000000..3a7239957 --- /dev/null +++ b/library/util_fir_dec/util_fir_dec.v @@ -0,0 +1,73 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2014(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// This IP allows the decimation by 8 of the data from the input channels +// 0 and 1. The decimation filter is implemented using a fir_compiler IP from +// Xilinx. +// *************************************************************************** + +`timescale 1ns/100ps + +module util_fir_dec ( + input aclk, + input s_axis_data_tvalid, + output s_axis_data_tready, + input [15:0] channel_0, + input [15:0] channel_1, + input decimate, + output m_axis_data_tvalid, + output [31:0] m_axis_data_tdata); + + wire [31:0] s_axis_data_tdata; + + wire m_axis_data_tvalid_s; + wire [31:0] m_axis_data_tdata_s; + + assign s_axis_data_tdata = {channel_1, channel_0}; + + assign m_axis_data_tvalid = (decimate == 1'b1) ? m_axis_data_tvalid_s : s_axis_data_tvalid; + assign m_axis_data_tdata = (decimate == 1'b1) ? {m_axis_data_tdata_s[30:16], 1'b0, m_axis_data_tdata_s[14:0], 1'b0} : {channel_1, channel_0}; + + fir_decim decimator ( + .aclk(aclk), + .s_axis_data_tvalid(s_axis_data_tvalid), + .s_axis_data_tready(s_axis_data_tready), + .s_axis_data_tdata(s_axis_data_tdata), + .m_axis_data_tvalid(m_axis_data_tvalid_s), + .m_axis_data_tdata(m_axis_data_tdata_s) + ); + +endmodule // util_fir_dec + diff --git a/library/util_fir_dec/util_fir_dec_ip.tcl b/library/util_fir_dec/util_fir_dec_ip.tcl new file mode 100644 index 000000000..1267759dd --- /dev/null +++ b/library/util_fir_dec/util_fir_dec_ip.tcl @@ -0,0 +1,40 @@ +source ../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip.tcl + +adi_ip_create util_fir_dec + +set fir_decim [create_ip -name fir_compiler -vendor xilinx.com -library ip -version 7.2 -module_name fir_decim] + set_property -dict [ list \ +CONFIG.Clock_Frequency {61.44} \ +CONFIG.CoefficientSource {COE_File} \ +CONFIG.Coefficient_File {../../../../coefile_dec.coe} \ +CONFIG.Coefficient_Fractional_Bits {0} \ +CONFIG.Data_Fractional_Bits {15} \ +CONFIG.Coefficient_Sets {1} \ +CONFIG.Coefficient_Sign {Signed} \ +CONFIG.Coefficient_Structure {Inferred} \ +CONFIG.Coefficient_Width {16} \ +CONFIG.ColumnConfig {5} \ +CONFIG.Decimation_Rate {8} \ +CONFIG.Filter_Architecture {Systolic_Multiply_Accumulate} \ +CONFIG.Filter_Type {Decimation} \ +CONFIG.Interpolation_Rate {1} \ +CONFIG.Number_Channels {1} \ +CONFIG.Number_Paths {2} \ +CONFIG.Output_Rounding_Mode {Symmetric_Rounding_to_Zero} \ +CONFIG.Output_Width {16} \ +CONFIG.Quantization {Integer_Coefficients} \ +CONFIG.RateSpecification {Frequency_Specification} \ +CONFIG.Sample_Frequency {61.44} \ +CONFIG.Zero_Pack_Factor {1} \ + ] [get_ips fir_decim] + +generate_target {all} [get_files util_fir_dec.srcs/sources_1/ip/fir_decim/fir_decim.xci] + + +adi_ip_files util_fir_dec [list \ +"util_fir_dec.v" ] + +adi_ip_properties_lite util_fir_dec + +ipx::save_core [ipx::current_core] diff --git a/library/util_fir_int/Makefile b/library/util_fir_int/Makefile new file mode 100644 index 000000000..f2724b225 --- /dev/null +++ b/library/util_fir_int/Makefile @@ -0,0 +1,46 @@ +#################################################################################### +#################################################################################### +## Copyright 2011(c) Analog Devices, Inc. +## Auto-generated, do not modify! +#################################################################################### +#################################################################################### + +M_DEPS += ../scripts/adi_env.tcl +M_DEPS += ../scripts/adi_ip.tcl +M_DEPS += util_fir_int.v +M_DEPS += util_fir_int_ip.tcl + +M_VIVADO := vivado -mode batch -source + +M_FLIST := *.cache +M_FLIST += *.data +M_FLIST += *.xpr +M_FLIST += *.log +M_FLIST += component.xml +M_FLIST += *.jou +M_FLIST += xgui +M_FLIST += *.ip_user_files +M_FLIST += *.srcs +M_FLIST += *.hw +M_FLIST += *.sim +M_FLIST += .Xil + + + +.PHONY: all clean clean-all +all: util_fir_int.xpr + + +clean:clean-all + + +clean-all: + rm -rf $(M_FLIST) + + +util_fir_int.xpr: $(M_DEPS) + -rm -rf $(M_FLIST) + $(M_VIVADO) util_fir_int_ip.tcl >> util_fir_int_ip.log 2>&1 + +#################################################################################### +#################################################################################### diff --git a/library/util_fir_int/coefile_int.coe b/library/util_fir_int/coefile_int.coe new file mode 100644 index 000000000..d7aee256a --- /dev/null +++ b/library/util_fir_int/coefile_int.coe @@ -0,0 +1,134 @@ +; XILINX CORE Generator(tm)Distributed Arithmetic FIR filter coefficient (.COE) File +; Generated by MATLAB(R) 9.0 and the DSP System Toolbox 9.2. +; Generated on: 20-Dec-2016 18:03:34 +Radix = 10; +Coefficient_Width = 16; +CoefData = 0, + -1, + -2, + -4, + -6, + -8, + -8, + -5, + 0, + 8, + 18, + 29, + 37, + 41, + 37, + 23, + 0, + -31, + -67, + -100, + -124, + -130, + -113, + -69, + 0, + 87, + 181, + 263, + 318, + 326, + 277, + 166, + 0, + -202, + -410, + -589, + -700, + -709, + -594, + -352, + 0, + 420, + 848, + 1211, + 1432, + 1446, + 1210, + 717, + 0, + -863, +-1756, +-2535, +-3043, +-3133, +-2690, +-1646, + 0, + 2180, + 4757, + 7534, +10278, +12743, +14697, +15951, +16384, +15951, +14697, +12743, +10278, + 7534, + 4757, + 2180, + 0, +-1646, +-2690, +-3133, +-3043, +-2535, +-1756, + -863, + 0, + 717, + 1210, + 1446, + 1432, + 1211, + 848, + 420, + 0, + -352, + -594, + -709, + -700, + -589, + -410, + -202, + 0, + 166, + 277, + 326, + 318, + 263, + 181, + 87, + 0, + -69, + -113, + -130, + -124, + -100, + -67, + -31, + 0, + 23, + 37, + 41, + 37, + 29, + 18, + 8, + 0, + -5, + -8, + -8, + -6, + -4, + -2, + -1, + 0; diff --git a/library/util_fir_int/util_fir_int.v b/library/util_fir_int/util_fir_int.v new file mode 100644 index 000000000..79a0b457b --- /dev/null +++ b/library/util_fir_int/util_fir_int.v @@ -0,0 +1,81 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2014(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// This IP allows the interpolation by 8 of the data from the input +// The interpolation filter is implemented using a fir_compiler IP from +// Xilinx. +// *************************************************************************** + +`timescale 1ns/100ps + +module util_fir_int ( + input aclk, + input s_axis_data_tvalid, + output s_axis_data_tready, + input [31:0] s_axis_data_tdata, + output [15:0] channel_0, + output [15:0] channel_1, + output m_axis_data_tvalid, + input interpolate, + input dac_read); + + wire [31:0] m_axis_data_tdata_s; + + reg s_axis_data_tready_r; + reg [2:0] ready_counter; + + always @(posedge aclk) begin + ready_counter <= ready_counter + 1; + if (ready_counter == 0) begin + s_axis_data_tready_r <= 1'b1; + end else begin + s_axis_data_tready_r <= 1'b0; + end + end + + assign {channel_1, channel_0} = (interpolate == 1'b1) ? {m_axis_data_tdata_s[30:16],1'b0,m_axis_data_tdata_s[14:0], 1'b0} : s_axis_data_tdata; + assign s_axis_data_tready = (interpolate == 1'b1) ? s_axis_data_tready_r : dac_read; + + fir_interp interpolator ( + .aclk(aclk), + .s_axis_data_tvalid(s_axis_data_tvalid), + .s_axis_data_tready(), + .s_axis_data_tdata(s_axis_data_tdata), + .m_axis_data_tvalid(m_axis_data_tvalid), + .m_axis_data_tdata(m_axis_data_tdata_s) + ); + +endmodule // util_fir_int + diff --git a/library/util_fir_int/util_fir_int_ip.tcl b/library/util_fir_int/util_fir_int_ip.tcl new file mode 100644 index 000000000..9c44dbab0 --- /dev/null +++ b/library/util_fir_int/util_fir_int_ip.tcl @@ -0,0 +1,42 @@ +source ../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip.tcl + +adi_ip_create util_fir_int + +set fir_interp [create_ip -name fir_compiler -vendor xilinx.com -library ip -version 7.2 -module_name fir_interp] + set_property -dict [ list \ +CONFIG.Clock_Frequency {61.44} \ +CONFIG.CoefficientSource {COE_File} \ +CONFIG.Coefficient_File {../../../../coefile_int.coe} \ +CONFIG.Coefficient_Fractional_Bits {0} \ +CONFIG.Data_Fractional_Bits {15} \ +CONFIG.Coefficient_Sets {1} \ +CONFIG.Coefficient_Sign {Signed} \ +CONFIG.S_DATA_Has_FIFO {true} \ +CONFIG.Coefficient_Structure {Inferred} \ +CONFIG.Coefficient_Width {16} \ +CONFIG.ColumnConfig {5} \ +CONFIG.Decimation_Rate {1} \ +CONFIG.Filter_Architecture {Systolic_Multiply_Accumulate} \ +CONFIG.Filter_Type {Interpolation} \ +CONFIG.Interpolation_Rate {8} \ +CONFIG.M_DATA_Has_TREADY {false} \ +CONFIG.Number_Channels {1} \ +CONFIG.Number_Paths {2} \ +CONFIG.Output_Rounding_Mode {Truncate_LSBs} \ +CONFIG.Output_Width {16} \ +CONFIG.Quantization {Integer_Coefficients} \ +CONFIG.RateSpecification {Frequency_Specification} \ +CONFIG.Sample_Frequency {7.68} \ +CONFIG.Zero_Pack_Factor {1} \ + ] [get_ips fir_interp] + +generate_target {all} [get_files util_fir_int.srcs/sources_1/ip/fir_interp/fir_interp.xci] + + +adi_ip_files util_fir_int [list \ +"util_fir_int.v" ] + +adi_ip_properties_lite util_fir_int + +ipx::save_core [ipx::current_core] diff --git a/library/util_gmii_to_rgmii/Makefile b/library/util_gmii_to_rgmii/Makefile index 648819e48..a0be6713b 100644 --- a/library/util_gmii_to_rgmii/Makefile +++ b/library/util_gmii_to_rgmii/Makefile @@ -5,12 +5,12 @@ #################################################################################### #################################################################################### -M_DEPS := util_gmii_to_rgmii_ip.tcl M_DEPS += ../scripts/adi_env.tcl M_DEPS += ../scripts/adi_ip.tcl M_DEPS += mdc_mdio.v -M_DEPS += util_gmii_to_rgmii_constr.xdc M_DEPS += util_gmii_to_rgmii.v +M_DEPS += util_gmii_to_rgmii_constr.xdc +M_DEPS += util_gmii_to_rgmii_ip.tcl M_VIVADO := vivado -mode batch -source @@ -21,6 +21,10 @@ M_FLIST += *.log M_FLIST += component.xml M_FLIST += *.jou M_FLIST += xgui +M_FLIST += *.ip_user_files +M_FLIST += *.srcs +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil @@ -37,7 +41,7 @@ clean-all: util_gmii_to_rgmii.xpr: $(M_DEPS) - rm -rf $(M_FLIST) + -rm -rf $(M_FLIST) $(M_VIVADO) util_gmii_to_rgmii_ip.tcl >> util_gmii_to_rgmii_ip.log 2>&1 #################################################################################### diff --git a/library/util_gmii_to_rgmii/util_gmii_to_rgmii_ip.tcl b/library/util_gmii_to_rgmii/util_gmii_to_rgmii_ip.tcl index be06aa5d8..12ad32b92 100644 --- a/library/util_gmii_to_rgmii/util_gmii_to_rgmii_ip.tcl +++ b/library/util_gmii_to_rgmii/util_gmii_to_rgmii_ip.tcl @@ -15,7 +15,7 @@ adi_ip_constraints util_gmii_to_rgmii [list \ "util_gmii_to_rgmii_constr.xdc" ] ipx::infer_bus_interface {gmii_tx_clk gmii_txd gmii_tx_en gmii_tx_er gmii_crs gmii_col gmii_rx_clk gmii_rxd gmii_rx_dv gmii_rx_er} xilinx.com:interface:gmii_rtl:1.0 [ipx::current_core] -set_property name {gmii} [ipx::get_bus_interface gmii_1 [ipx::current_core]] +set_property name {gmii} [ipx::get_bus_interfaces gmii_1 -of_objects [ipx::current_core]] ipx::infer_bus_interface {rgmii_td rgmii_tx_ctl rgmii_txc rgmii_rd rgmii_rx_ctl rgmii_rxc} xilinx.com:interface:rgmii_rtl:1.0 [ipx::current_core] set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.IODELAY_CTRL')) = 1} \ diff --git a/library/util_gtlb/util_gtlb.v b/library/util_gtlb/util_gtlb.v deleted file mode 100644 index 1fc9f9591..000000000 --- a/library/util_gtlb/util_gtlb.v +++ /dev/null @@ -1,387 +0,0 @@ -// *************************************************************************** -// *************************************************************************** -// Copyright 2011(c) Analog Devices, Inc. -// -// All rights reserved. -// -// Redistribution and use in source and binary forms, with or without modification, -// are permitted provided that the following conditions are met: -// - Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// - Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in -// the documentation and/or other materials provided with the -// distribution. -// - Neither the name of Analog Devices, Inc. nor the names of its -// contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// - The use of this software may or may not infringe the patent rights -// of one or more patent holders. This license does not release you -// from the requirement that you obtain separate licenses from these -// patent holders to use this software. -// - Use of the software either in source or binary form, must be run -// on or directly connected to an Analog Devices Inc. component. -// -// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, -// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A -// PARTICULAR PURPOSE ARE DISCLAIMED. -// -// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY -// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF -// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// *************************************************************************** -// *************************************************************************** - -`timescale 1ns/100ps - -module util_gtlb ( - - // pll clocks & resets - - input qpll_ref_clk, - input cpll_ref_clk, - - output qpll0_rst, - output qpll0_ref_clk_in, - - output cpll_rst_m_0, - output cpll_ref_clk_in_0, - - // channel interface (rx) - - input rx_p, - input rx_n, - - output rx_clk, - - input [ 3:0] rx_gt_charisk_0, - input [ 3:0] rx_gt_disperr_0, - input [ 3:0] rx_gt_notintable_0, - input [31:0] rx_gt_data_0, - output reg rx_gt_comma_align_enb_0, - - output rx_0_p, - output rx_0_n, - input rx_rst_0, - output rx_rst_m_0, - input rx_pll_rst_0, - input rx_gt_rst_0, - output rx_gt_rst_m_0, - input rx_pll_locked_0, - output rx_pll_locked_m_0, - input rx_user_ready_0, - output rx_user_ready_m_0, - input rx_rst_done_0, - output rx_rst_done_m_0, - input rx_out_clk_0, - output rx_clk_0, - output rx_sysref_0, - input rx_sync_0, - input rx_sof_0, - input [31:0] rx_data_0, - input rx_ip_rst_0, - output [ 3:0] rx_ip_sof_0, - output [31:0] rx_ip_data_0, - input rx_ip_sysref_0, - output rx_ip_sync_0, - input rx_ip_rst_done_0, - - // channel interface (tx) - - output tx_p, - output tx_n, - - output tx_clk, - - output [ 3:0] tx_gt_charisk_0, - output reg [31:0] tx_gt_data_0, - - input tx_0_p, - input tx_0_n, - input tx_rst_0, - output tx_rst_m_0, - input tx_pll_rst_0, - input tx_gt_rst_0, - output tx_gt_rst_m_0, - input tx_pll_locked_0, - output tx_pll_locked_m_0, - input tx_user_ready_0, - output tx_user_ready_m_0, - input tx_rst_done_0, - output tx_rst_done_m_0, - input tx_out_clk_0, - output tx_clk_0, - output tx_sysref_0, - output tx_sync_0, - output [31:0] tx_data_0, - input tx_ip_rst_0, - input [31:0] tx_ip_data_0, - input tx_ip_sysref_0, - input tx_ip_sync_0, - input tx_ip_rst_done_0, - - // up interface - - input up_clk, - input up_rstn, - input [31:0] up_gp_in, - output [31:0] up_gp_out); - - // internal registers - - reg tx_sync_m1 = 'd0; - reg tx_sync_m2 = 'd0; - reg tx_sync = 'd0; - reg [31:0] tx_pn_data = 'd0; - reg tx_charisk_1 = 'd0; - reg [ 3:0] rx_kcount = 'd0; - reg rx_sync = 'd0; - reg [31:0] rx_pn_data = 'd0; - reg rx_pn_match_d = 'd0; - reg rx_pn_match_z = 'd0; - reg rx_pn_err = 'd0; - reg rx_pn_oos = 'd0; - reg [ 3:0] rx_pn_oos_count = 'd0; - reg up_pn_err_clr_d = 'd0; - reg up_pn_oos_clr_d = 'd0; - reg up_pn_err = 'd0; - reg up_pn_oos = 'd0; - - // internal signals - - wire [31:0] rx_gt_data_0_s; - wire [31:0] rx_pn_data_s; - wire rx_pn_match_d_s; - wire rx_pn_match_z_s; - wire rx_pn_match_s; - wire rx_pn_update_s; - wire rx_pn_err_s; - wire up_pn_err_clr_s; - wire up_pn_oos_clr_s; - wire up_pn_err_s; - wire up_pn_oos_s; - - // pn31 function - - function [31:0] pn31; - input [31:0] din; - reg [31:0] dout; - begin - dout[31] = din[31] ^ din[28]; - dout[30] = din[30] ^ din[27]; - dout[29] = din[29] ^ din[26]; - dout[28] = din[28] ^ din[25]; - dout[27] = din[27] ^ din[24]; - dout[26] = din[26] ^ din[23]; - dout[25] = din[25] ^ din[22]; - dout[24] = din[24] ^ din[21]; - dout[23] = din[23] ^ din[20]; - dout[22] = din[22] ^ din[19]; - dout[21] = din[21] ^ din[18]; - dout[20] = din[20] ^ din[17]; - dout[19] = din[19] ^ din[16]; - dout[18] = din[18] ^ din[15]; - dout[17] = din[17] ^ din[14]; - dout[16] = din[16] ^ din[13]; - dout[15] = din[15] ^ din[12]; - dout[14] = din[14] ^ din[11]; - dout[13] = din[13] ^ din[10]; - dout[12] = din[12] ^ din[ 9]; - dout[11] = din[11] ^ din[ 8]; - dout[10] = din[10] ^ din[ 7]; - dout[ 9] = din[ 9] ^ din[ 6]; - dout[ 8] = din[ 8] ^ din[ 5]; - dout[ 7] = din[ 7] ^ din[ 4]; - dout[ 6] = din[ 6] ^ din[ 3]; - dout[ 5] = din[ 5] ^ din[ 2]; - dout[ 4] = din[ 4] ^ din[ 1]; - dout[ 3] = din[ 3] ^ din[ 0]; - dout[ 2] = din[ 2] ^ din[31] ^ din[28]; - dout[ 1] = din[ 1] ^ din[30] ^ din[27]; - dout[ 0] = din[ 0] ^ din[29] ^ din[26]; - pn31 = dout; - end - endfunction - - // defaults - - assign qpll0_rst = tx_pll_rst_0 | rx_pll_rst_0; - assign qpll0_ref_clk_in = qpll_ref_clk; - assign cpll_rst_m_0 = tx_pll_rst_0 | rx_pll_rst_0; - assign cpll_ref_clk_in_0 = cpll_ref_clk; - - assign rx_0_p = rx_p; - assign rx_0_n = rx_n; - assign rx_rst_m_0 = rx_rst_0; - assign rx_gt_rst_m_0 = rx_gt_rst_0; - assign rx_pll_locked_m_0 = rx_pll_locked_0; - assign rx_user_ready_m_0 = rx_user_ready_0; - assign rx_rst_done_m_0 = & rx_rst_done_0; - assign rx_clk_0 = rx_out_clk_0; - assign rx_sysref_0 = 1'd0; - assign rx_ip_sof_0 = 4'hf; - assign rx_ip_data_0 = 32'd0; - assign rx_ip_sync_0 = rx_sync; - assign rx_clk = rx_out_clk_0; - - assign tx_p = tx_0_p; - assign tx_n = tx_0_n; - assign tx_rst_m_0 = tx_rst_0; - assign tx_gt_rst_m_0 = tx_gt_rst_0; - assign tx_pll_locked_m_0 = tx_pll_locked_0; - assign tx_user_ready_m_0 = tx_user_ready_0; - assign tx_rst_done_m_0 = tx_rst_done_0; - assign tx_clk_0 = tx_out_clk_0; - assign tx_sysref_0 = 1'd0; - assign tx_sync_0 = tx_sync; - assign tx_data_0 = 32'd0; - assign tx_clk = tx_out_clk_0; - - // gt loop back - - assign tx_gt_charisk_0 = {4{tx_charisk_1}}; - - always @(posedge tx_out_clk_0 or posedge tx_rst_0) begin - if (tx_rst_0 == 1'b1) begin - tx_sync_m1 <= 1'd0; - tx_sync_m2 <= 1'd0; - tx_sync <= 1'd0; - tx_pn_data <= 32'hffffffff; - tx_charisk_1 <= 1'd0; - tx_gt_data_0 <= 32'd0; - end else begin - tx_sync_m1 <= rx_sync; - tx_sync_m2 <= tx_sync_m1; - tx_sync <= tx_sync_m2; - tx_pn_data <= pn31(tx_pn_data); - if (tx_sync == 1'b1) begin - tx_charisk_1 <= 1'd0; - tx_gt_data_0[31:24] <= tx_pn_data[ 7: 0]; - tx_gt_data_0[23:16] <= tx_pn_data[15: 8]; - tx_gt_data_0[15: 8] <= tx_pn_data[23:16]; - tx_gt_data_0[ 7: 0] <= tx_pn_data[31:24]; - end else begin - tx_charisk_1 <= 1'd1; - tx_gt_data_0[31:24] <= 8'hbc; - tx_gt_data_0[23:16] <= 8'hbc; - tx_gt_data_0[15: 8] <= 8'hbc; - tx_gt_data_0[ 7: 0] <= 8'hbc; - end - end - end - - assign rx_gt_data_0_s[31:24] = rx_gt_data_0[ 7: 0]; - assign rx_gt_data_0_s[23:16] = rx_gt_data_0[15: 8]; - assign rx_gt_data_0_s[15: 8] = rx_gt_data_0[23:16]; - assign rx_gt_data_0_s[ 7: 0] = rx_gt_data_0[31:24]; - - always @(posedge rx_out_clk_0 or posedge rx_rst_0) begin - if (rx_rst_0 == 1'b1) begin - rx_gt_comma_align_enb_0 <= 1'd0; - rx_kcount <= 4'd0; - rx_sync <= 1'd0; - end else begin - rx_gt_comma_align_enb_0 <= ~rx_sync; - if ((rx_gt_disperr_0 == 0) && (rx_gt_notintable_0 == 0)) begin - if ((rx_gt_charisk_0 == 4'hf) && (rx_gt_data_0_s == 32'hbcbcbcbc)) begin - rx_kcount <= rx_kcount + 1'b1; - if (rx_kcount == 4'hf) begin - rx_sync <= 1'b1; - end - end else begin - rx_kcount <= 4'd0; - rx_sync <= rx_sync; - end - end else begin - rx_kcount <= 4'd0; - rx_sync <= 1'd0; - end - end - end - - assign rx_pn_data_s = (rx_pn_oos == 1'b1) ? rx_gt_data_0_s : rx_pn_data; - assign rx_pn_match_d_s = (rx_gt_data_0_s == rx_pn_data) ? 1'b1 : 1'b0; - assign rx_pn_match_z_s = (rx_gt_data_0_s == 'd0) ? 1'b0 : 1'b1; - assign rx_pn_match_s = rx_pn_match_d & rx_pn_match_z; - assign rx_pn_update_s = ~(rx_pn_oos ^ rx_pn_match_s); - assign rx_pn_err_s = ~(rx_pn_oos | rx_pn_match_s); - - always @(posedge rx_out_clk_0 or posedge rx_rst_0) begin - if (rx_rst_0 == 1'b1) begin - rx_pn_data <= 32'd0; - rx_pn_match_d <= 'd0; - rx_pn_match_z <= 'd0; - rx_pn_err <= 'd0; - rx_pn_oos <= 'd0; - rx_pn_oos_count <= 'd0; - end else begin - rx_pn_data <= pn31(rx_pn_data_s); - rx_pn_match_d <= rx_pn_match_d_s; - rx_pn_match_z <= rx_pn_match_z_s; - if ((rx_gt_disperr_0 == 0) && (rx_gt_notintable_0 == 0) && (rx_gt_charisk_0 == 0)) begin - rx_pn_err <= rx_pn_err_s; - if ((rx_pn_update_s == 1'b1) && (rx_pn_oos_count >= 15)) begin - rx_pn_oos <= ~rx_pn_oos; - end - if (rx_pn_update_s == 1'b1) begin - rx_pn_oos_count <= rx_pn_oos_count + 1'b1; - end else begin - rx_pn_oos_count <= 'd0; - end - end else begin - rx_pn_err <= 1'd0; - rx_pn_oos <= 1'd1; - rx_pn_oos_count <= 'd0; - end - end - end - - // up clock - - assign up_pn_err_clr_s = up_gp_in[1]; - assign up_pn_oos_clr_s = up_gp_in[0]; - - assign up_gp_out[31:2] = 30'd0; - assign up_gp_out[1] = up_pn_err; - assign up_gp_out[0] = up_pn_oos; - - up_xfer_status #(.DATA_WIDTH(2)) i_xfer_status ( - .up_rstn (up_rstn), - .up_clk (up_clk), - .up_data_status ({up_pn_err_s, up_pn_oos_s}), - .d_rst (rx_rst_0), - .d_clk (rx_out_clk_0), - .d_data_status ({rx_pn_err, rx_pn_oos})); - - always @(posedge up_clk or negedge up_rstn) begin - if (up_rstn == 1'b0) begin - up_pn_err_clr_d <= 'd0; - up_pn_oos_clr_d <= 'd0; - up_pn_err <= 'd0; - up_pn_oos <= 'd0; - end else begin - up_pn_err_clr_d <= up_pn_err_clr_s; - up_pn_oos_clr_d <= up_pn_oos_clr_s; - if (up_pn_err_s == 1'b1) begin - up_pn_err <= 1'b1; - end else if ((up_pn_err_clr_s == 1'b1) && - (up_pn_err_clr_d == 1'b0)) begin - up_pn_err <= 1'b0; - end - if (up_pn_oos_s == 1'b1) begin - up_pn_oos <= 1'b1; - end else if ((up_pn_oos_clr_s == 1'b1) && - (up_pn_oos_clr_d == 1'b0)) begin - up_pn_oos <= 1'b0; - end - end - end - -endmodule - -// *************************************************************************** -// *************************************************************************** - diff --git a/library/util_gtlb/util_gtlb_constr.xdc b/library/util_gtlb/util_gtlb_constr.xdc deleted file mode 100644 index 644f04f85..000000000 --- a/library/util_gtlb/util_gtlb_constr.xdc +++ /dev/null @@ -1,9 +0,0 @@ - -set_property shreg_extract no [get_cells -hier -filter {name =~ *tx_sync*}] -set_property shreg_extract no [get_cells -hier -filter {name =~ *up_xfer_toggle*}] - -set_false_path -to [get_cells -hier -filter {name =~ *tx_sync_m1_reg && IS_SEQUENTIAL}] -set_false_path -from [get_cells -hier -filter {name =~ *up_xfer_toggle_reg && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *d_xfer_state_m1_reg && IS_SEQUENTIAL}] -set_false_path -from [get_cells -hier -filter {name =~ *d_xfer_toggle_reg && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *up_xfer_toggle_m1_reg && IS_SEQUENTIAL}] -set_false_path -from [get_cells -hier -filter {name =~ *d_xfer_data* && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *up_data_status* && IS_SEQUENTIAL}] - diff --git a/library/util_gtlb/util_gtlb_ip.tcl b/library/util_gtlb/util_gtlb_ip.tcl deleted file mode 100644 index cf01a575b..000000000 --- a/library/util_gtlb/util_gtlb_ip.tcl +++ /dev/null @@ -1,93 +0,0 @@ -# ip - -source ../scripts/adi_env.tcl -source $ad_hdl_dir/library/scripts/adi_ip.tcl - -adi_ip_create util_gtlb -adi_ip_files util_gtlb [list \ - "$ad_hdl_dir/library/common/up_xfer_status.v" \ - "util_gtlb_constr.xdc" \ - "util_gtlb.v" ] - -adi_ip_properties_lite util_gtlb -adi_ip_constraints util_gtlb [list \ - "util_gtlb_constr.xdc" ] - -ipx::remove_all_bus_interface [ipx::current_core] - -adi_if_infer_bus ADI:user:if_gt_qpll master gt_qpll_0 [list \ - "qpll_rst qpll0_rst "\ - "qpll_ref_clk qpll0_ref_clk_in "] - -for {set n 0} {$n < 1} {incr n} { - - adi_if_infer_bus ADI:user:if_gt_pll master gt_pll_${n} [list \ - "cpll_rst_m cpll_rst_m_${n} "\ - "cpll_ref_clk_in cpll_ref_clk_in_${n} "] - - adi_if_infer_bus xilinx.com:display_jesd204:jesd204_rx_bus slave gt_rx_ip_${n} [list \ - "rxcharisk rx_gt_charisk_${n} "\ - "rxdisperr rx_gt_disperr_${n} "\ - "rxnotintable rx_gt_notintable_${n} "\ - "rxdata rx_gt_data_${n} "] - - adi_if_infer_bus ADI:user:if_gt_rx master gt_rx_${n} [list \ - "rx_p rx_${n}_p "\ - "rx_n rx_${n}_n "\ - "rx_rst rx_rst_${n} "\ - "rx_rst_m rx_rst_m_${n} "\ - "rx_pll_rst rx_pll_rst_${n} "\ - "rx_gt_rst rx_gt_rst_${n} "\ - "rx_gt_rst_m rx_gt_rst_m_${n} "\ - "rx_pll_locked rx_pll_locked_${n} "\ - "rx_pll_locked_m rx_pll_locked_m_${n} "\ - "rx_user_ready rx_user_ready_${n} "\ - "rx_user_ready_m rx_user_ready_m_${n} "\ - "rx_rst_done rx_rst_done_${n} "\ - "rx_rst_done_m rx_rst_done_m_${n} "\ - "rx_out_clk rx_out_clk_${n} "\ - "rx_clk rx_clk_${n} "\ - "rx_sysref rx_sysref_${n} "\ - "rx_sync rx_sync_${n} "\ - "rx_sof rx_sof_${n} "\ - "rx_data rx_data_${n} "\ - "rx_ip_rst rx_ip_rst_${n} "\ - "rx_ip_sof rx_ip_sof_${n} "\ - "rx_ip_data rx_ip_data_${n} "\ - "rx_ip_sysref rx_ip_sysref_${n} "\ - "rx_ip_sync rx_ip_sync_${n} "\ - "rx_ip_rst_done rx_ip_rst_done_${n} "] - - adi_if_infer_bus xilinx.com:display_jesd204:jesd204_tx_bus master gt_tx_ip_${n} [list \ - "txcharisk tx_gt_charisk_${n} "\ - "txdata tx_gt_data_${n} "] - - adi_if_infer_bus ADI:user:if_gt_tx master gt_tx_${n} [list \ - "tx_p tx_${n}_p "\ - "tx_n tx_${n}_n "\ - "tx_rst tx_rst_${n} "\ - "tx_rst_m tx_rst_m_${n} "\ - "tx_pll_rst tx_pll_rst_${n} "\ - "tx_gt_rst tx_gt_rst_${n} "\ - "tx_gt_rst_m tx_gt_rst_m_${n} "\ - "tx_pll_locked tx_pll_locked_${n} "\ - "tx_pll_locked_m tx_pll_locked_m_${n} "\ - "tx_user_ready tx_user_ready_${n} "\ - "tx_user_ready_m tx_user_ready_m_${n} "\ - "tx_rst_done tx_rst_done_${n} "\ - "tx_rst_done_m tx_rst_done_m_${n} "\ - "tx_out_clk tx_out_clk_${n} "\ - "tx_clk tx_clk_${n} "\ - "tx_sysref tx_sysref_${n} "\ - "tx_sync tx_sync_${n} "\ - "tx_data tx_data_${n} "\ - "tx_ip_rst tx_ip_rst_${n} "\ - "tx_ip_data tx_ip_data_${n} "\ - "tx_ip_sysref tx_ip_sysref_${n} "\ - "tx_ip_sync tx_ip_sync_${n} "\ - "tx_ip_rst_done tx_ip_rst_done_${n} "] -} - -ipx::save_core [ipx::current_core] - - diff --git a/library/util_i2c_mixer/Makefile b/library/util_i2c_mixer/Makefile index 20e5a8f0c..267f22929 100644 --- a/library/util_i2c_mixer/Makefile +++ b/library/util_i2c_mixer/Makefile @@ -5,10 +5,10 @@ #################################################################################### #################################################################################### -M_DEPS := util_i2c_mixer_ip.tcl M_DEPS += ../scripts/adi_env.tcl M_DEPS += ../scripts/adi_ip.tcl M_DEPS += util_i2c_mixer.vhd +M_DEPS += util_i2c_mixer_ip.tcl M_VIVADO := vivado -mode batch -source @@ -19,6 +19,10 @@ M_FLIST += *.log M_FLIST += component.xml M_FLIST += *.jou M_FLIST += xgui +M_FLIST += *.ip_user_files +M_FLIST += *.srcs +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil @@ -35,7 +39,7 @@ clean-all: util_i2c_mixer.xpr: $(M_DEPS) - rm -rf $(M_FLIST) + -rm -rf $(M_FLIST) $(M_VIVADO) util_i2c_mixer_ip.tcl >> util_i2c_mixer_ip.log 2>&1 #################################################################################### diff --git a/library/util_jesd_gt/util_jesd_gt.v b/library/util_jesd_gt/util_jesd_gt.v deleted file mode 100644 index 7d74d2045..000000000 --- a/library/util_jesd_gt/util_jesd_gt.v +++ /dev/null @@ -1,914 +0,0 @@ -// *************************************************************************** -// *************************************************************************** -// Copyright 2011(c) Analog Devices, Inc. -// -// All rights reserved. -// -// Redistribution and use in source and binary forms, with or without modification, -// are permitted provided that the following conditions are met: -// - Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// - Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in -// the documentation and/or other materials provided with the -// distribution. -// - Neither the name of Analog Devices, Inc. nor the names of its -// contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// - The use of this software may or may not infringe the patent rights -// of one or more patent holders. This license does not release you -// from the requirement that you obtain separate licenses from these -// patent holders to use this software. -// - Use of the software either in source or binary form, must be run -// on or directly connected to an Analog Devices Inc. component. -// -// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, -// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A -// PARTICULAR PURPOSE ARE DISCLAIMED. -// -// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY -// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF -// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// *************************************************************************** -// *************************************************************************** - -`timescale 1ns/100ps - -module util_jesd_gt #( - - parameter integer QPLL0_ENABLE = 1, - parameter integer QPLL1_ENABLE = 1, - parameter integer QPLL_TX_OR_RX_N = 1, - parameter integer CPLL_TX_OR_RX_N = 0, - parameter integer NUM_OF_LANES = 8, - parameter integer RX_ENABLE = 1, - parameter integer RX_NUM_OF_LANES = 8, - parameter integer TX_ENABLE = 1, - parameter integer TX_NUM_OF_LANES = 8) - - ( - - // pll clocks & resets - - input qpll_ref_clk, - input cpll_ref_clk, - - output qpll0_rst, - output qpll0_ref_clk_in, - output qpll1_rst, - output qpll1_ref_clk_in, - - output cpll_rst_m_0, - output cpll_ref_clk_in_0, - output cpll_rst_m_1, - output cpll_ref_clk_in_1, - output cpll_rst_m_2, - output cpll_ref_clk_in_2, - output cpll_rst_m_3, - output cpll_ref_clk_in_3, - output cpll_rst_m_4, - output cpll_ref_clk_in_4, - output cpll_rst_m_5, - output cpll_ref_clk_in_5, - output cpll_rst_m_6, - output cpll_ref_clk_in_6, - output cpll_rst_m_7, - output cpll_ref_clk_in_7, - - // channel interface (rx) - - input [((RX_NUM_OF_LANES* 1)-1):0] rx_p, - input [((RX_NUM_OF_LANES* 1)-1):0] rx_n, - input rx_sysref, - output rx_sync, - - output rx_out_clk, - input rx_clk, - output rx_rst, - output rx_sof, - output [((RX_NUM_OF_LANES*32)-1):0] rx_data, - - output rx_ip_rst, - output rx_ip_rst_done, - output rx_ip_sysref, - input rx_ip_sync, - input [ 3:0] rx_ip_sof, - input [((RX_NUM_OF_LANES*32)-1):0] rx_ip_data, - - output rx_0_p, - output rx_0_n, - input rx_rst_0, - output rx_rst_m_0, - input rx_pll_rst_0, - input rx_gt_rst_0, - output rx_gt_rst_m_0, - input rx_pll_locked_0, - output rx_pll_locked_m_0, - input rx_user_ready_0, - output rx_user_ready_m_0, - input rx_rst_done_0, - output rx_rst_done_m_0, - input rx_out_clk_0, - output rx_clk_0, - output rx_sysref_0, - input rx_sync_0, - input rx_sof_0, - input [31:0] rx_data_0, - input rx_ip_rst_0, - output [ 3:0] rx_ip_sof_0, - output [31:0] rx_ip_data_0, - input rx_ip_sysref_0, - output rx_ip_sync_0, - input rx_ip_rst_done_0, - - output rx_1_p, - output rx_1_n, - input rx_rst_1, - output rx_rst_m_1, - input rx_pll_rst_1, - input rx_gt_rst_1, - output rx_gt_rst_m_1, - input rx_pll_locked_1, - output rx_pll_locked_m_1, - input rx_user_ready_1, - output rx_user_ready_m_1, - input rx_rst_done_1, - output rx_rst_done_m_1, - input rx_out_clk_1, - output rx_clk_1, - output rx_sysref_1, - input rx_sync_1, - input rx_sof_1, - input [31:0] rx_data_1, - input rx_ip_rst_1, - output [ 3:0] rx_ip_sof_1, - output [31:0] rx_ip_data_1, - input rx_ip_sysref_1, - output rx_ip_sync_1, - input rx_ip_rst_done_1, - - output rx_2_p, - output rx_2_n, - input rx_rst_2, - output rx_rst_m_2, - input rx_pll_rst_2, - input rx_gt_rst_2, - output rx_gt_rst_m_2, - input rx_pll_locked_2, - output rx_pll_locked_m_2, - input rx_user_ready_2, - output rx_user_ready_m_2, - input rx_rst_done_2, - output rx_rst_done_m_2, - input rx_out_clk_2, - output rx_clk_2, - output rx_sysref_2, - input rx_sync_2, - input rx_sof_2, - input [31:0] rx_data_2, - input rx_ip_rst_2, - output [ 3:0] rx_ip_sof_2, - output [31:0] rx_ip_data_2, - input rx_ip_sysref_2, - output rx_ip_sync_2, - input rx_ip_rst_done_2, - - output rx_3_p, - output rx_3_n, - input rx_rst_3, - output rx_rst_m_3, - input rx_pll_rst_3, - input rx_gt_rst_3, - output rx_gt_rst_m_3, - input rx_pll_locked_3, - output rx_pll_locked_m_3, - input rx_user_ready_3, - output rx_user_ready_m_3, - input rx_rst_done_3, - output rx_rst_done_m_3, - input rx_out_clk_3, - output rx_clk_3, - output rx_sysref_3, - input rx_sync_3, - input rx_sof_3, - input [31:0] rx_data_3, - input rx_ip_rst_3, - output [ 3:0] rx_ip_sof_3, - output [31:0] rx_ip_data_3, - input rx_ip_sysref_3, - output rx_ip_sync_3, - input rx_ip_rst_done_3, - - output rx_4_p, - output rx_4_n, - input rx_rst_4, - output rx_rst_m_4, - input rx_pll_rst_4, - input rx_gt_rst_4, - output rx_gt_rst_m_4, - input rx_pll_locked_4, - output rx_pll_locked_m_4, - input rx_user_ready_4, - output rx_user_ready_m_4, - input rx_rst_done_4, - output rx_rst_done_m_4, - input rx_out_clk_4, - output rx_clk_4, - output rx_sysref_4, - input rx_sync_4, - input rx_sof_4, - input [31:0] rx_data_4, - input rx_ip_rst_4, - output [ 3:0] rx_ip_sof_4, - output [31:0] rx_ip_data_4, - input rx_ip_sysref_4, - output rx_ip_sync_4, - input rx_ip_rst_done_4, - - output rx_5_p, - output rx_5_n, - input rx_rst_5, - output rx_rst_m_5, - input rx_pll_rst_5, - input rx_gt_rst_5, - output rx_gt_rst_m_5, - input rx_pll_locked_5, - output rx_pll_locked_m_5, - input rx_user_ready_5, - output rx_user_ready_m_5, - input rx_rst_done_5, - output rx_rst_done_m_5, - input rx_out_clk_5, - output rx_clk_5, - output rx_sysref_5, - input rx_sync_5, - input rx_sof_5, - input [31:0] rx_data_5, - input rx_ip_rst_5, - output [ 3:0] rx_ip_sof_5, - output [31:0] rx_ip_data_5, - input rx_ip_sysref_5, - output rx_ip_sync_5, - input rx_ip_rst_done_5, - - output rx_6_p, - output rx_6_n, - input rx_rst_6, - output rx_rst_m_6, - input rx_pll_rst_6, - input rx_gt_rst_6, - output rx_gt_rst_m_6, - input rx_pll_locked_6, - output rx_pll_locked_m_6, - input rx_user_ready_6, - output rx_user_ready_m_6, - input rx_rst_done_6, - output rx_rst_done_m_6, - input rx_out_clk_6, - output rx_clk_6, - output rx_sysref_6, - input rx_sync_6, - input rx_sof_6, - input [31:0] rx_data_6, - input rx_ip_rst_6, - output [ 3:0] rx_ip_sof_6, - output [31:0] rx_ip_data_6, - input rx_ip_sysref_6, - output rx_ip_sync_6, - input rx_ip_rst_done_6, - - output rx_7_p, - output rx_7_n, - input rx_rst_7, - output rx_rst_m_7, - input rx_pll_rst_7, - input rx_gt_rst_7, - output rx_gt_rst_m_7, - input rx_pll_locked_7, - output rx_pll_locked_m_7, - input rx_user_ready_7, - output rx_user_ready_m_7, - input rx_rst_done_7, - output rx_rst_done_m_7, - input rx_out_clk_7, - output rx_clk_7, - output rx_sysref_7, - input rx_sync_7, - input rx_sof_7, - input [31:0] rx_data_7, - input rx_ip_rst_7, - output [ 3:0] rx_ip_sof_7, - output [31:0] rx_ip_data_7, - input rx_ip_sysref_7, - output rx_ip_sync_7, - input rx_ip_rst_done_7, - - // channel interface (tx) - - output [((TX_NUM_OF_LANES* 1)-1):0] tx_p, - output [((TX_NUM_OF_LANES* 1)-1):0] tx_n, - input tx_sysref, - input tx_sync, - - output tx_out_clk, - input tx_clk, - output tx_rst, - input [((TX_NUM_OF_LANES*32)-1):0] tx_data, - - output tx_ip_rst, - output tx_ip_rst_done, - output tx_ip_sysref, - output tx_ip_sync, - output [((TX_NUM_OF_LANES*32)-1):0] tx_ip_data, - - input tx_0_p, - input tx_0_n, - input tx_rst_0, - output tx_rst_m_0, - input tx_pll_rst_0, - input tx_gt_rst_0, - output tx_gt_rst_m_0, - input tx_pll_locked_0, - output tx_pll_locked_m_0, - input tx_user_ready_0, - output tx_user_ready_m_0, - input tx_rst_done_0, - output tx_rst_done_m_0, - input tx_out_clk_0, - output tx_clk_0, - output tx_sysref_0, - output tx_sync_0, - output [31:0] tx_data_0, - input tx_ip_rst_0, - input [31:0] tx_ip_data_0, - input tx_ip_sysref_0, - input tx_ip_sync_0, - input tx_ip_rst_done_0, - - input tx_1_p, - input tx_1_n, - input tx_rst_1, - output tx_rst_m_1, - input tx_pll_rst_1, - input tx_gt_rst_1, - output tx_gt_rst_m_1, - input tx_pll_locked_1, - output tx_pll_locked_m_1, - input tx_user_ready_1, - output tx_user_ready_m_1, - input tx_rst_done_1, - output tx_rst_done_m_1, - input tx_out_clk_1, - output tx_clk_1, - output tx_sysref_1, - output tx_sync_1, - output [31:0] tx_data_1, - input tx_ip_rst_1, - input [31:0] tx_ip_data_1, - input tx_ip_sysref_1, - input tx_ip_sync_1, - input tx_ip_rst_done_1, - - input tx_2_p, - input tx_2_n, - input tx_rst_2, - output tx_rst_m_2, - input tx_pll_rst_2, - input tx_gt_rst_2, - output tx_gt_rst_m_2, - input tx_pll_locked_2, - output tx_pll_locked_m_2, - input tx_user_ready_2, - output tx_user_ready_m_2, - input tx_rst_done_2, - output tx_rst_done_m_2, - input tx_out_clk_2, - output tx_clk_2, - output tx_sysref_2, - output tx_sync_2, - output [31:0] tx_data_2, - input tx_ip_rst_2, - input [31:0] tx_ip_data_2, - input tx_ip_sysref_2, - input tx_ip_sync_2, - input tx_ip_rst_done_2, - - input tx_3_p, - input tx_3_n, - input tx_rst_3, - output tx_rst_m_3, - input tx_pll_rst_3, - input tx_gt_rst_3, - output tx_gt_rst_m_3, - input tx_pll_locked_3, - output tx_pll_locked_m_3, - input tx_user_ready_3, - output tx_user_ready_m_3, - input tx_rst_done_3, - output tx_rst_done_m_3, - input tx_out_clk_3, - output tx_clk_3, - output tx_sysref_3, - output tx_sync_3, - output [31:0] tx_data_3, - input tx_ip_rst_3, - input [31:0] tx_ip_data_3, - input tx_ip_sysref_3, - input tx_ip_sync_3, - input tx_ip_rst_done_3, - - input tx_4_p, - input tx_4_n, - input tx_rst_4, - output tx_rst_m_4, - input tx_pll_rst_4, - input tx_gt_rst_4, - output tx_gt_rst_m_4, - input tx_pll_locked_4, - output tx_pll_locked_m_4, - input tx_user_ready_4, - output tx_user_ready_m_4, - input tx_rst_done_4, - output tx_rst_done_m_4, - input tx_out_clk_4, - output tx_clk_4, - output tx_sysref_4, - output tx_sync_4, - output [31:0] tx_data_4, - input tx_ip_rst_4, - input [31:0] tx_ip_data_4, - input tx_ip_sysref_4, - input tx_ip_sync_4, - input tx_ip_rst_done_4, - - input tx_5_p, - input tx_5_n, - input tx_rst_5, - output tx_rst_m_5, - input tx_pll_rst_5, - input tx_gt_rst_5, - output tx_gt_rst_m_5, - input tx_pll_locked_5, - output tx_pll_locked_m_5, - input tx_user_ready_5, - output tx_user_ready_m_5, - input tx_rst_done_5, - output tx_rst_done_m_5, - input tx_out_clk_5, - output tx_clk_5, - output tx_sysref_5, - output tx_sync_5, - output [31:0] tx_data_5, - input tx_ip_rst_5, - input [31:0] tx_ip_data_5, - input tx_ip_sysref_5, - input tx_ip_sync_5, - input tx_ip_rst_done_5, - - input tx_6_p, - input tx_6_n, - input tx_rst_6, - output tx_rst_m_6, - input tx_pll_rst_6, - input tx_gt_rst_6, - output tx_gt_rst_m_6, - input tx_pll_locked_6, - output tx_pll_locked_m_6, - input tx_user_ready_6, - output tx_user_ready_m_6, - input tx_rst_done_6, - output tx_rst_done_m_6, - input tx_out_clk_6, - output tx_clk_6, - output tx_sysref_6, - output tx_sync_6, - output [31:0] tx_data_6, - input tx_ip_rst_6, - input [31:0] tx_ip_data_6, - input tx_ip_sysref_6, - input tx_ip_sync_6, - input tx_ip_rst_done_6, - - input tx_7_p, - input tx_7_n, - input tx_rst_7, - output tx_rst_m_7, - input tx_pll_rst_7, - input tx_gt_rst_7, - output tx_gt_rst_m_7, - input tx_pll_locked_7, - output tx_pll_locked_m_7, - input tx_user_ready_7, - output tx_user_ready_m_7, - input tx_rst_done_7, - output tx_rst_done_m_7, - input tx_out_clk_7, - output tx_clk_7, - output tx_sysref_7, - output tx_sync_7, - output [31:0] tx_data_7, - input tx_ip_rst_7, - input [31:0] tx_ip_data_7, - input tx_ip_sysref_7, - input tx_ip_sync_7, - input tx_ip_rst_done_7); - - // internal signals - - wire [(( 1*8)-1):0] rx_all_p; - wire [(( 1*8)-1):0] rx_all_n; - wire [(( 1*8)-1):0] rx_pll_locked_all; - wire [(( 1*8)-1):0] rx_user_ready_all; - wire [(( 1*8)-1):0] rx_rst_done_all; - wire [(( 1*8)-1):0] rx_ip_rst_done_all; - wire [((32*8)-1):0] rx_data_all; - wire [((32*8)-1):0] rx_ip_data_all; - wire [(( 1*8)-1):0] tx_all_p; - wire [(( 1*8)-1):0] tx_all_n; - wire [(( 1*8)-1):0] tx_pll_locked_all; - wire [(( 1*8)-1):0] tx_user_ready_all; - wire [(( 1*8)-1):0] tx_rst_done_all; - wire [(( 1*8)-1):0] tx_ip_rst_done_all; - wire [((32*8)-1):0] tx_ip_data_all; - wire [((32*8)-1):0] tx_data_all; - - // pll clocks & resets - - assign qpll0_rst = (QPLL_TX_OR_RX_N == 1) ? tx_pll_rst_0 : rx_pll_rst_0; - assign qpll0_ref_clk_in = qpll_ref_clk; - assign qpll1_rst = (QPLL_TX_OR_RX_N == 1) ? tx_pll_rst_0 : rx_pll_rst_0; - assign qpll1_ref_clk_in = qpll_ref_clk; - assign cpll_rst_m_0 = (CPLL_TX_OR_RX_N == 1) ? tx_pll_rst_0 : rx_pll_rst_0; - assign cpll_ref_clk_in_0 = cpll_ref_clk; - assign cpll_rst_m_1 = (CPLL_TX_OR_RX_N == 1) ? tx_pll_rst_0 : rx_pll_rst_0; - assign cpll_ref_clk_in_1 = cpll_ref_clk; - assign cpll_rst_m_2 = (CPLL_TX_OR_RX_N == 1) ? tx_pll_rst_0 : rx_pll_rst_0; - assign cpll_ref_clk_in_2 = cpll_ref_clk; - assign cpll_rst_m_3 = (CPLL_TX_OR_RX_N == 1) ? tx_pll_rst_0 : rx_pll_rst_0; - assign cpll_ref_clk_in_3 = cpll_ref_clk; - assign cpll_rst_m_4 = (CPLL_TX_OR_RX_N == 1) ? tx_pll_rst_0 : rx_pll_rst_0; - assign cpll_ref_clk_in_4 = cpll_ref_clk; - assign cpll_rst_m_5 = (CPLL_TX_OR_RX_N == 1) ? tx_pll_rst_0 : rx_pll_rst_0; - assign cpll_ref_clk_in_5 = cpll_ref_clk; - assign cpll_rst_m_6 = (CPLL_TX_OR_RX_N == 1) ? tx_pll_rst_0 : rx_pll_rst_0; - assign cpll_ref_clk_in_6 = cpll_ref_clk; - assign cpll_rst_m_7 = (CPLL_TX_OR_RX_N == 1) ? tx_pll_rst_0 : rx_pll_rst_0; - assign cpll_ref_clk_in_7 = cpll_ref_clk; - - // channel interface (rx) - - generate - if (RX_NUM_OF_LANES < 8) begin - assign rx_all_p[((8* 1)-1):(RX_NUM_OF_LANES* 1)] = 'd0; - assign rx_all_n[((8* 1)-1):(RX_NUM_OF_LANES* 1)] = 'd0; - end - endgenerate - - assign rx_all_p[((RX_NUM_OF_LANES* 1)-1):0] = rx_p; - assign rx_all_n[((RX_NUM_OF_LANES* 1)-1):0] = rx_n; - - assign rx_pll_locked_all[0] = (RX_NUM_OF_LANES >= 1) ? rx_pll_locked_0 : 1'b1; - assign rx_user_ready_all[0] = (RX_NUM_OF_LANES >= 1) ? rx_user_ready_0 : 1'b1; - assign rx_rst_done_all[0] = (RX_NUM_OF_LANES >= 1) ? rx_rst_done_0 : 1'b1; - assign rx_ip_rst_done_all[0] = (RX_NUM_OF_LANES >= 1) ? rx_ip_rst_done_0 : 1'b1; - assign rx_data_all[((32*0)+31):(32*0)] = rx_data_0; - - assign rx_pll_locked_all[1] = (RX_NUM_OF_LANES >= 2) ? rx_pll_locked_1 : 1'b1; - assign rx_user_ready_all[1] = (RX_NUM_OF_LANES >= 2) ? rx_user_ready_1 : 1'b1; - assign rx_rst_done_all[1] = (RX_NUM_OF_LANES >= 2) ? rx_rst_done_1 : 1'b1; - assign rx_ip_rst_done_all[1] = (RX_NUM_OF_LANES >= 2) ? rx_ip_rst_done_1 : 1'b1; - assign rx_data_all[((32*1)+31):(32*1)] = rx_data_1; - - assign rx_pll_locked_all[2] = (RX_NUM_OF_LANES >= 3) ? rx_pll_locked_2 : 1'b1; - assign rx_user_ready_all[2] = (RX_NUM_OF_LANES >= 3) ? rx_user_ready_2 : 1'b1; - assign rx_rst_done_all[2] = (RX_NUM_OF_LANES >= 3) ? rx_rst_done_2 : 1'b1; - assign rx_ip_rst_done_all[2] = (RX_NUM_OF_LANES >= 3) ? rx_ip_rst_done_2 : 1'b1; - assign rx_data_all[((32*2)+31):(32*2)] = rx_data_2; - - assign rx_pll_locked_all[3] = (RX_NUM_OF_LANES >= 4) ? rx_pll_locked_3 : 1'b1; - assign rx_user_ready_all[3] = (RX_NUM_OF_LANES >= 4) ? rx_user_ready_3 : 1'b1; - assign rx_rst_done_all[3] = (RX_NUM_OF_LANES >= 4) ? rx_rst_done_3 : 1'b1; - assign rx_ip_rst_done_all[3] = (RX_NUM_OF_LANES >= 4) ? rx_ip_rst_done_3 : 1'b1; - assign rx_data_all[((32*3)+31):(32*3)] = rx_data_3; - - assign rx_pll_locked_all[4] = (RX_NUM_OF_LANES >= 5) ? rx_pll_locked_4 : 1'b1; - assign rx_user_ready_all[4] = (RX_NUM_OF_LANES >= 5) ? rx_user_ready_4 : 1'b1; - assign rx_rst_done_all[4] = (RX_NUM_OF_LANES >= 5) ? rx_rst_done_4 : 1'b1; - assign rx_ip_rst_done_all[4] = (RX_NUM_OF_LANES >= 5) ? rx_ip_rst_done_4 : 1'b1; - assign rx_data_all[((32*4)+31):(32*4)] = rx_data_4; - - assign rx_pll_locked_all[5] = (RX_NUM_OF_LANES >= 6) ? rx_pll_locked_5 : 1'b1; - assign rx_user_ready_all[5] = (RX_NUM_OF_LANES >= 6) ? rx_user_ready_5 : 1'b1; - assign rx_rst_done_all[5] = (RX_NUM_OF_LANES >= 6) ? rx_rst_done_5 : 1'b1; - assign rx_ip_rst_done_all[5] = (RX_NUM_OF_LANES >= 6) ? rx_ip_rst_done_5 : 1'b1; - assign rx_data_all[((32*5)+31):(32*5)] = rx_data_5; - - assign rx_pll_locked_all[6] = (RX_NUM_OF_LANES >= 7) ? rx_pll_locked_6 : 1'b1; - assign rx_user_ready_all[6] = (RX_NUM_OF_LANES >= 7) ? rx_user_ready_6 : 1'b1; - assign rx_rst_done_all[6] = (RX_NUM_OF_LANES >= 7) ? rx_rst_done_6 : 1'b1; - assign rx_ip_rst_done_all[6] = (RX_NUM_OF_LANES >= 7) ? rx_ip_rst_done_6 : 1'b1; - assign rx_data_all[((32*6)+31):(32*6)] = rx_data_6; - - assign rx_pll_locked_all[7] = (RX_NUM_OF_LANES >= 8) ? rx_pll_locked_7 : 1'b1; - assign rx_user_ready_all[7] = (RX_NUM_OF_LANES >= 8) ? rx_user_ready_7 : 1'b1; - assign rx_rst_done_all[7] = (RX_NUM_OF_LANES >= 8) ? rx_rst_done_7 : 1'b1; - assign rx_ip_rst_done_all[7] = (RX_NUM_OF_LANES >= 8) ? rx_ip_rst_done_7 : 1'b1; - assign rx_data_all[((32*7)+31):(32*7)] = rx_data_7; - - generate - if (RX_NUM_OF_LANES < 8) begin - assign rx_ip_data_all[((8*32)-1):(RX_NUM_OF_LANES*32)] = 'd0; - end - endgenerate - - assign rx_ip_data_all[((RX_NUM_OF_LANES*32)-1):0] = rx_ip_data; - - assign rx_sync = rx_sync_0; - - assign rx_out_clk = rx_out_clk_0; - assign rx_rst = rx_rst_0; - assign rx_sof = rx_sof_0; - assign rx_data = rx_data_all[((RX_NUM_OF_LANES*32)-1):0]; - - assign rx_ip_rst = rx_ip_rst_0; - assign rx_ip_rst_done = & rx_ip_rst_done_all; - assign rx_ip_sysref = rx_ip_sysref_0; - - assign rx_0_p = rx_all_p[0]; - assign rx_0_n = rx_all_n[0]; - assign rx_rst_m_0 = rx_rst_0; - assign rx_gt_rst_m_0 = rx_gt_rst_0; - assign rx_pll_locked_m_0 = & rx_pll_locked_all; - assign rx_user_ready_m_0 = & rx_user_ready_all; - assign rx_rst_done_m_0 = & rx_rst_done_all; - assign rx_clk_0 = rx_clk; - assign rx_sysref_0 = rx_sysref; - assign rx_ip_sof_0 = rx_ip_sof; - assign rx_ip_data_0 = rx_ip_data_all[((32*0)+31):(32*0)]; - assign rx_ip_sync_0 = rx_ip_sync; - - assign rx_1_p = rx_all_p[1]; - assign rx_1_n = rx_all_n[1]; - assign rx_rst_m_1 = rx_rst_0; - assign rx_gt_rst_m_1 = rx_gt_rst_0; - assign rx_pll_locked_m_1 = & rx_pll_locked_all; - assign rx_user_ready_m_1 = & rx_user_ready_all; - assign rx_rst_done_m_1 = & rx_rst_done_all; - assign rx_clk_1 = rx_clk; - assign rx_sysref_1 = rx_sysref; - assign rx_ip_sof_1 = rx_ip_sof; - assign rx_ip_data_1 = rx_ip_data_all[((32*1)+31):(32*1)]; - assign rx_ip_sync_1 = rx_ip_sync; - - assign rx_2_p = rx_all_p[2]; - assign rx_2_n = rx_all_n[2]; - assign rx_rst_m_2 = rx_rst_0; - assign rx_gt_rst_m_2 = rx_gt_rst_0; - assign rx_pll_locked_m_2 = & rx_pll_locked_all; - assign rx_user_ready_m_2 = & rx_user_ready_all; - assign rx_rst_done_m_2 = & rx_rst_done_all; - assign rx_clk_2 = rx_clk; - assign rx_sysref_2 = rx_sysref; - assign rx_ip_sof_2 = rx_ip_sof; - assign rx_ip_data_2 = rx_ip_data_all[((32*2)+31):(32*2)]; - assign rx_ip_sync_2 = rx_ip_sync; - - assign rx_3_p = rx_all_p[3]; - assign rx_3_n = rx_all_n[3]; - assign rx_rst_m_3 = rx_rst_0; - assign rx_gt_rst_m_3 = rx_gt_rst_0; - assign rx_pll_locked_m_3 = & rx_pll_locked_all; - assign rx_user_ready_m_3 = & rx_user_ready_all; - assign rx_rst_done_m_3 = & rx_rst_done_all; - assign rx_clk_3 = rx_clk; - assign rx_sysref_3 = rx_sysref; - assign rx_ip_sof_3 = rx_ip_sof; - assign rx_ip_data_3 = rx_ip_data_all[((32*3)+31):(32*3)]; - assign rx_ip_sync_3 = rx_ip_sync; - - assign rx_4_p = rx_all_p[4]; - assign rx_4_n = rx_all_n[4]; - assign rx_rst_m_4 = rx_rst_0; - assign rx_gt_rst_m_4 = rx_gt_rst_0; - assign rx_pll_locked_m_4 = & rx_pll_locked_all; - assign rx_user_ready_m_4 = & rx_user_ready_all; - assign rx_rst_done_m_4 = & rx_rst_done_all; - assign rx_clk_4 = rx_clk; - assign rx_sysref_4 = rx_sysref; - assign rx_ip_sof_4 = rx_ip_sof; - assign rx_ip_data_4 = rx_ip_data_all[((32*4)+31):(32*4)]; - assign rx_ip_sync_4 = rx_ip_sync; - - assign rx_5_p = rx_all_p[5]; - assign rx_5_n = rx_all_n[5]; - assign rx_rst_m_5 = rx_rst_0; - assign rx_gt_rst_m_5 = rx_gt_rst_0; - assign rx_pll_locked_m_5 = & rx_pll_locked_all; - assign rx_user_ready_m_5 = & rx_user_ready_all; - assign rx_rst_done_m_5 = & rx_rst_done_all; - assign rx_clk_5 = rx_clk; - assign rx_sysref_5 = rx_sysref; - assign rx_ip_sof_5 = rx_ip_sof; - assign rx_ip_data_5 = rx_ip_data_all[((32*5)+31):(32*5)]; - assign rx_ip_sync_5 = rx_ip_sync; - - assign rx_6_p = rx_all_p[6]; - assign rx_6_n = rx_all_n[6]; - assign rx_rst_m_6 = rx_rst_0; - assign rx_gt_rst_m_6 = rx_gt_rst_0; - assign rx_pll_locked_m_6 = & rx_pll_locked_all; - assign rx_user_ready_m_6 = & rx_user_ready_all; - assign rx_rst_done_m_6 = & rx_rst_done_all; - assign rx_clk_6 = rx_clk; - assign rx_sysref_6 = rx_sysref; - assign rx_ip_sof_6 = rx_ip_sof; - assign rx_ip_data_6 = rx_ip_data_all[((32*6)+31):(32*6)]; - assign rx_ip_sync_6 = rx_ip_sync; - - assign rx_7_p = rx_all_p[7]; - assign rx_7_n = rx_all_n[7]; - assign rx_rst_m_7 = rx_rst_0; - assign rx_gt_rst_m_7 = rx_gt_rst_0; - assign rx_pll_locked_m_7 = & rx_pll_locked_all; - assign rx_user_ready_m_7 = & rx_user_ready_all; - assign rx_rst_done_m_7 = & rx_rst_done_all; - assign rx_clk_7 = rx_clk; - assign rx_sysref_7 = rx_sysref; - assign rx_ip_sof_7 = rx_ip_sof; - assign rx_ip_data_7 = rx_ip_data_all[((32*7)+31):(32*7)]; - assign rx_ip_sync_7 = rx_ip_sync; - - - // channel interface (tx) - - assign tx_all_p[0] = tx_0_p; - assign tx_all_n[0] = tx_0_n; - assign tx_pll_locked_all[0] = (TX_NUM_OF_LANES >= 1) ? tx_pll_locked_0 : 1'b1; - assign tx_user_ready_all[0] = (TX_NUM_OF_LANES >= 1) ? tx_user_ready_0 : 1'b1; - assign tx_rst_done_all[0] = (TX_NUM_OF_LANES >= 1) ? tx_rst_done_0 : 1'b1; - assign tx_ip_rst_done_all[0] = (TX_NUM_OF_LANES >= 1) ? tx_ip_rst_done_0 : 1'b1; - assign tx_ip_data_all[((32*0)+31):(32*0)] = tx_ip_data_0; - - assign tx_all_p[1] = tx_1_p; - assign tx_all_n[1] = tx_1_n; - assign tx_pll_locked_all[1] = (TX_NUM_OF_LANES >= 2) ? tx_pll_locked_1 : 1'b1; - assign tx_user_ready_all[1] = (TX_NUM_OF_LANES >= 2) ? tx_user_ready_1 : 1'b1; - assign tx_rst_done_all[1] = (TX_NUM_OF_LANES >= 2) ? tx_rst_done_1 : 1'b1; - assign tx_ip_rst_done_all[1] = (TX_NUM_OF_LANES >= 2) ? tx_ip_rst_done_1 : 1'b1; - assign tx_ip_data_all[((32*1)+31):(32*1)] = tx_ip_data_1; - - assign tx_all_p[2] = tx_2_p; - assign tx_all_n[2] = tx_2_n; - assign tx_pll_locked_all[2] = (TX_NUM_OF_LANES >= 3) ? tx_pll_locked_2 : 1'b1; - assign tx_user_ready_all[2] = (TX_NUM_OF_LANES >= 3) ? tx_user_ready_2 : 1'b1; - assign tx_rst_done_all[2] = (TX_NUM_OF_LANES >= 3) ? tx_rst_done_2 : 1'b1; - assign tx_ip_rst_done_all[2] = (TX_NUM_OF_LANES >= 3) ? tx_ip_rst_done_2 : 1'b1; - assign tx_ip_data_all[((32*2)+31):(32*2)] = tx_ip_data_2; - - assign tx_all_p[3] = tx_3_p; - assign tx_all_n[3] = tx_3_n; - assign tx_pll_locked_all[3] = (TX_NUM_OF_LANES >= 4) ? tx_pll_locked_3 : 1'b1; - assign tx_user_ready_all[3] = (TX_NUM_OF_LANES >= 4) ? tx_user_ready_3 : 1'b1; - assign tx_rst_done_all[3] = (TX_NUM_OF_LANES >= 4) ? tx_rst_done_3 : 1'b1; - assign tx_ip_rst_done_all[3] = (TX_NUM_OF_LANES >= 4) ? tx_ip_rst_done_3 : 1'b1; - assign tx_ip_data_all[((32*3)+31):(32*3)] = tx_ip_data_3; - - assign tx_all_p[4] = tx_4_p; - assign tx_all_n[4] = tx_4_n; - assign tx_pll_locked_all[4] = (TX_NUM_OF_LANES >= 5) ? tx_pll_locked_4 : 1'b1; - assign tx_user_ready_all[4] = (TX_NUM_OF_LANES >= 5) ? tx_user_ready_4 : 1'b1; - assign tx_rst_done_all[4] = (TX_NUM_OF_LANES >= 5) ? tx_rst_done_4 : 1'b1; - assign tx_ip_rst_done_all[4] = (TX_NUM_OF_LANES >= 5) ? tx_ip_rst_done_4 : 1'b1; - assign tx_ip_data_all[((32*4)+31):(32*4)] = tx_ip_data_4; - - assign tx_all_p[5] = tx_5_p; - assign tx_all_n[5] = tx_5_n; - assign tx_pll_locked_all[5] = (TX_NUM_OF_LANES >= 6) ? tx_pll_locked_5 : 1'b1; - assign tx_user_ready_all[5] = (TX_NUM_OF_LANES >= 6) ? tx_user_ready_5 : 1'b1; - assign tx_rst_done_all[5] = (TX_NUM_OF_LANES >= 6) ? tx_rst_done_5 : 1'b1; - assign tx_ip_rst_done_all[5] = (TX_NUM_OF_LANES >= 6) ? tx_ip_rst_done_5 : 1'b1; - assign tx_ip_data_all[((32*5)+31):(32*5)] = tx_ip_data_5; - - assign tx_all_p[6] = tx_6_p; - assign tx_all_n[6] = tx_6_n; - assign tx_pll_locked_all[6] = (TX_NUM_OF_LANES >= 7) ? tx_pll_locked_6 : 1'b1; - assign tx_user_ready_all[6] = (TX_NUM_OF_LANES >= 7) ? tx_user_ready_6 : 1'b1; - assign tx_rst_done_all[6] = (TX_NUM_OF_LANES >= 7) ? tx_rst_done_6 : 1'b1; - assign tx_ip_rst_done_all[6] = (TX_NUM_OF_LANES >= 7) ? tx_ip_rst_done_6 : 1'b1; - assign tx_ip_data_all[((32*6)+31):(32*6)] = tx_ip_data_6; - - assign tx_all_p[7] = tx_7_p; - assign tx_all_n[7] = tx_7_n; - assign tx_pll_locked_all[7] = (TX_NUM_OF_LANES >= 8) ? tx_pll_locked_7 : 1'b1; - assign tx_user_ready_all[7] = (TX_NUM_OF_LANES >= 8) ? tx_user_ready_7 : 1'b1; - assign tx_rst_done_all[7] = (TX_NUM_OF_LANES >= 8) ? tx_rst_done_7 : 1'b1; - assign tx_ip_rst_done_all[7] = (TX_NUM_OF_LANES >= 8) ? tx_ip_rst_done_7 : 1'b1; - assign tx_ip_data_all[((32*7)+31):(32*7)] = tx_ip_data_7; - - generate - if (TX_NUM_OF_LANES < 8) begin - assign tx_data_all[((8*32)-1):(TX_NUM_OF_LANES*32)] = 'd0; - end - endgenerate - - assign tx_data_all[((TX_NUM_OF_LANES*32)-1):0] = tx_data; - - assign tx_p = tx_all_p[((TX_NUM_OF_LANES* 1)-1):0]; - assign tx_n = tx_all_n[((TX_NUM_OF_LANES* 1)-1):0]; - - assign tx_out_clk = tx_out_clk_0; - assign tx_rst = tx_rst_0; - - assign tx_ip_rst = tx_ip_rst_0; - assign tx_ip_rst_done = & tx_ip_rst_done_all; - assign tx_ip_sysref = tx_ip_sysref_0; - assign tx_ip_sync = tx_ip_sync_0; - assign tx_ip_data = tx_ip_data_all[((TX_NUM_OF_LANES*32)-1):0]; - - assign tx_rst_m_0 = tx_rst_0; - assign tx_gt_rst_m_0 = tx_gt_rst_0; - assign tx_pll_locked_m_0 = & tx_pll_locked_all; - assign tx_user_ready_m_0 = & tx_user_ready_all; - assign tx_rst_done_m_0 = & tx_rst_done_all; - assign tx_clk_0 = tx_clk; - assign tx_sysref_0 = tx_sysref; - assign tx_sync_0 = tx_sync; - assign tx_data_0 = tx_data_all[((32*0)+31):(32*0)]; - - assign tx_rst_m_1 = tx_rst_0; - assign tx_gt_rst_m_1 = tx_gt_rst_0; - assign tx_pll_locked_m_1 = & tx_pll_locked_all; - assign tx_user_ready_m_1 = & tx_user_ready_all; - assign tx_rst_done_m_1 = & tx_rst_done_all; - assign tx_clk_1 = tx_clk; - assign tx_sysref_1 = tx_sysref; - assign tx_sync_1 = tx_sync; - assign tx_data_1 = tx_data_all[((32*1)+31):(32*1)]; - - assign tx_rst_m_2 = tx_rst_0; - assign tx_gt_rst_m_2 = tx_gt_rst_0; - assign tx_pll_locked_m_2 = & tx_pll_locked_all; - assign tx_user_ready_m_2 = & tx_user_ready_all; - assign tx_rst_done_m_2 = & tx_rst_done_all; - assign tx_clk_2 = tx_clk; - assign tx_sysref_2 = tx_sysref; - assign tx_sync_2 = tx_sync; - assign tx_data_2 = tx_data_all[((32*2)+31):(32*2)]; - - assign tx_rst_m_3 = tx_rst_0; - assign tx_gt_rst_m_3 = tx_gt_rst_0; - assign tx_pll_locked_m_3 = & tx_pll_locked_all; - assign tx_user_ready_m_3 = & tx_user_ready_all; - assign tx_rst_done_m_3 = & tx_rst_done_all; - assign tx_clk_3 = tx_clk; - assign tx_sysref_3 = tx_sysref; - assign tx_sync_3 = tx_sync; - assign tx_data_3 = tx_data_all[((32*3)+31):(32*3)]; - - assign tx_rst_m_4 = tx_rst_0; - assign tx_gt_rst_m_4 = tx_gt_rst_0; - assign tx_pll_locked_m_4 = & tx_pll_locked_all; - assign tx_user_ready_m_4 = & tx_user_ready_all; - assign tx_rst_done_m_4 = & tx_rst_done_all; - assign tx_clk_4 = tx_clk; - assign tx_sysref_4 = tx_sysref; - assign tx_sync_4 = tx_sync; - assign tx_data_4 = tx_data_all[((32*4)+31):(32*4)]; - - assign tx_rst_m_5 = tx_rst_0; - assign tx_gt_rst_m_5 = tx_gt_rst_0; - assign tx_pll_locked_m_5 = & tx_pll_locked_all; - assign tx_user_ready_m_5 = & tx_user_ready_all; - assign tx_rst_done_m_5 = & tx_rst_done_all; - assign tx_clk_5 = tx_clk; - assign tx_sysref_5 = tx_sysref; - assign tx_sync_5 = tx_sync; - assign tx_data_5 = tx_data_all[((32*5)+31):(32*5)]; - - assign tx_rst_m_6 = tx_rst_0; - assign tx_gt_rst_m_6 = tx_gt_rst_0; - assign tx_pll_locked_m_6 = & tx_pll_locked_all; - assign tx_user_ready_m_6 = & tx_user_ready_all; - assign tx_rst_done_m_6 = & tx_rst_done_all; - assign tx_clk_6 = tx_clk; - assign tx_sysref_6 = tx_sysref; - assign tx_sync_6 = tx_sync; - assign tx_data_6 = tx_data_all[((32*6)+31):(32*6)]; - - assign tx_rst_m_7 = tx_rst_0; - assign tx_gt_rst_m_7 = tx_gt_rst_0; - assign tx_pll_locked_m_7 = & tx_pll_locked_all; - assign tx_user_ready_m_7 = & tx_user_ready_all; - assign tx_rst_done_m_7 = & tx_rst_done_all; - assign tx_clk_7 = tx_clk; - assign tx_sysref_7 = tx_sysref; - assign tx_sync_7 = tx_sync; - assign tx_data_7 = tx_data_all[((32*7)+31):(32*7)]; - -endmodule - -// *************************************************************************** -// *************************************************************************** diff --git a/library/util_jesd_gt/util_jesd_gt_ip.tcl b/library/util_jesd_gt/util_jesd_gt_ip.tcl deleted file mode 100644 index 34986ed7b..000000000 --- a/library/util_jesd_gt/util_jesd_gt_ip.tcl +++ /dev/null @@ -1,188 +0,0 @@ -# ip - -source ../scripts/adi_env.tcl -source $ad_hdl_dir/library/scripts/adi_ip.tcl - -adi_ip_create util_jesd_gt -adi_ip_files util_jesd_gt [list \ - "util_jesd_gt.v" ] - -adi_ip_properties_lite util_jesd_gt - -ipx::remove_all_bus_interface [ipx::current_core] - -adi_if_infer_bus ADI:user:if_gt_qpll master gt_qpll_0 [list \ - "qpll_rst qpll0_rst "\ - "qpll_ref_clk qpll0_ref_clk_in "] - -adi_if_infer_bus ADI:user:if_gt_qpll master gt_qpll_1 [list \ - "qpll_rst qpll1_rst "\ - "qpll_ref_clk qpll1_ref_clk_in "] - -for {set n 0} {$n < 8} {incr n} { - - adi_if_infer_bus ADI:user:if_gt_pll master gt_pll_${n} [list \ - "cpll_rst_m cpll_rst_m_${n} "\ - "cpll_ref_clk_in cpll_ref_clk_in_${n} "] - - adi_if_infer_bus ADI:user:if_gt_rx master gt_rx_${n} [list \ - "rx_p rx_${n}_p "\ - "rx_n rx_${n}_n "\ - "rx_rst rx_rst_${n} "\ - "rx_rst_m rx_rst_m_${n} "\ - "rx_pll_rst rx_pll_rst_${n} "\ - "rx_gt_rst rx_gt_rst_${n} "\ - "rx_gt_rst_m rx_gt_rst_m_${n} "\ - "rx_pll_locked rx_pll_locked_${n} "\ - "rx_pll_locked_m rx_pll_locked_m_${n} "\ - "rx_user_ready rx_user_ready_${n} "\ - "rx_user_ready_m rx_user_ready_m_${n} "\ - "rx_rst_done rx_rst_done_${n} "\ - "rx_rst_done_m rx_rst_done_m_${n} "\ - "rx_out_clk rx_out_clk_${n} "\ - "rx_clk rx_clk_${n} "\ - "rx_sysref rx_sysref_${n} "\ - "rx_sync rx_sync_${n} "\ - "rx_sof rx_sof_${n} "\ - "rx_data rx_data_${n} "\ - "rx_ip_rst rx_ip_rst_${n} "\ - "rx_ip_sof rx_ip_sof_${n} "\ - "rx_ip_data rx_ip_data_${n} "\ - "rx_ip_sysref rx_ip_sysref_${n} "\ - "rx_ip_sync rx_ip_sync_${n} "\ - "rx_ip_rst_done rx_ip_rst_done_${n} "] - - adi_if_infer_bus ADI:user:if_gt_tx master gt_tx_${n} [list \ - "tx_p tx_${n}_p "\ - "tx_n tx_${n}_n "\ - "tx_rst tx_rst_${n} "\ - "tx_rst_m tx_rst_m_${n} "\ - "tx_pll_rst tx_pll_rst_${n} "\ - "tx_gt_rst tx_gt_rst_${n} "\ - "tx_gt_rst_m tx_gt_rst_m_${n} "\ - "tx_pll_locked tx_pll_locked_${n} "\ - "tx_pll_locked_m tx_pll_locked_m_${n} "\ - "tx_user_ready tx_user_ready_${n} "\ - "tx_user_ready_m tx_user_ready_m_${n} "\ - "tx_rst_done tx_rst_done_${n} "\ - "tx_rst_done_m tx_rst_done_m_${n} "\ - "tx_out_clk tx_out_clk_${n} "\ - "tx_clk tx_clk_${n} "\ - "tx_sysref tx_sysref_${n} "\ - "tx_sync tx_sync_${n} "\ - "tx_data tx_data_${n} "\ - "tx_ip_rst tx_ip_rst_${n} "\ - "tx_ip_data tx_ip_data_${n} "\ - "tx_ip_sysref tx_ip_sysref_${n} "\ - "tx_ip_sync tx_ip_sync_${n} "\ - "tx_ip_rst_done tx_ip_rst_done_${n} "] -} - -set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_ENABLE')) == 1} \ - [ipx::get_ports rx_p -of_objects [ipx::current_core]] \ - [ipx::get_ports rx_n -of_objects [ipx::current_core]] \ - [ipx::get_ports rx_sysref -of_objects [ipx::current_core]] \ - [ipx::get_ports rx_sync -of_objects [ipx::current_core]] \ - [ipx::get_ports rx_out_clk -of_objects [ipx::current_core]] \ - [ipx::get_ports rx_clk -of_objects [ipx::current_core]] \ - [ipx::get_ports rx_rst -of_objects [ipx::current_core]] \ - [ipx::get_ports rx_sof -of_objects [ipx::current_core]] \ - [ipx::get_ports rx_data -of_objects [ipx::current_core]] \ - [ipx::get_ports rx_ip_rst -of_objects [ipx::current_core]] \ - [ipx::get_ports rx_ip_rst_done -of_objects [ipx::current_core]] \ - [ipx::get_ports rx_ip_sysref -of_objects [ipx::current_core]] \ - [ipx::get_ports rx_ip_sync -of_objects [ipx::current_core]] \ - [ipx::get_ports rx_ip_sof -of_objects [ipx::current_core]] \ - [ipx::get_ports rx_ip_data -of_objects [ipx::current_core]] - -set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_ENABLE')) == 1} \ - [ipx::get_ports tx_p -of_objects [ipx::current_core]] \ - [ipx::get_ports tx_n -of_objects [ipx::current_core]] \ - [ipx::get_ports tx_sysref -of_objects [ipx::current_core]] \ - [ipx::get_ports tx_sync -of_objects [ipx::current_core]] \ - [ipx::get_ports tx_out_clk -of_objects [ipx::current_core]] \ - [ipx::get_ports tx_clk -of_objects [ipx::current_core]] \ - [ipx::get_ports tx_rst -of_objects [ipx::current_core]] \ - [ipx::get_ports tx_data -of_objects [ipx::current_core]] \ - [ipx::get_ports tx_ip_rst -of_objects [ipx::current_core]] \ - [ipx::get_ports tx_ip_rst_done -of_objects [ipx::current_core]] \ - [ipx::get_ports tx_ip_sysref -of_objects [ipx::current_core]] \ - [ipx::get_ports tx_ip_sync -of_objects [ipx::current_core]] \ - [ipx::get_ports tx_ip_data -of_objects [ipx::current_core]] - -set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.QPLL0_ENABLE')) == 1} \ - [ipx::get_bus_interfaces gt_qpll_0 -of_objects [ipx::current_core]] -set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.QPLL1_ENABLE')) == 1} \ - [ipx::get_bus_interfaces gt_qpll_1 -of_objects [ipx::current_core]] - -set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 0} \ - [ipx::get_bus_interfaces gt_pll_0 -of_objects [ipx::current_core]] -set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 1} \ - [ipx::get_bus_interfaces gt_pll_1 -of_objects [ipx::current_core]] -set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 2} \ - [ipx::get_bus_interfaces gt_pll_2 -of_objects [ipx::current_core]] -set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 3} \ - [ipx::get_bus_interfaces gt_pll_3 -of_objects [ipx::current_core]] -set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 4} \ - [ipx::get_bus_interfaces gt_pll_4 -of_objects [ipx::current_core]] -set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 5} \ - [ipx::get_bus_interfaces gt_pll_5 -of_objects [ipx::current_core]] -set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 6} \ - [ipx::get_bus_interfaces gt_pll_6 -of_objects [ipx::current_core]] -set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 7} \ - [ipx::get_bus_interfaces gt_pll_7 -of_objects [ipx::current_core]] - -set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 0 and \ - spirit:decode(id('MODELPARAM_VALUE.RX_ENABLE')) == 1} \ - [ipx::get_bus_interfaces gt_rx_0 -of_objects [ipx::current_core]] -set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 1 and \ - spirit:decode(id('MODELPARAM_VALUE.RX_ENABLE')) == 1} \ - [ipx::get_bus_interfaces gt_rx_1 -of_objects [ipx::current_core]] -set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 2 and \ - spirit:decode(id('MODELPARAM_VALUE.RX_ENABLE')) == 1} \ - [ipx::get_bus_interfaces gt_rx_2 -of_objects [ipx::current_core]] -set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 3 and \ - spirit:decode(id('MODELPARAM_VALUE.RX_ENABLE')) == 1} \ - [ipx::get_bus_interfaces gt_rx_3 -of_objects [ipx::current_core]] -set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 4 and \ - spirit:decode(id('MODELPARAM_VALUE.RX_ENABLE')) == 1} \ - [ipx::get_bus_interfaces gt_rx_4 -of_objects [ipx::current_core]] -set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 5 and \ - spirit:decode(id('MODELPARAM_VALUE.RX_ENABLE')) == 1} \ - [ipx::get_bus_interfaces gt_rx_5 -of_objects [ipx::current_core]] -set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 6 and \ - spirit:decode(id('MODELPARAM_VALUE.RX_ENABLE')) == 1} \ - [ipx::get_bus_interfaces gt_rx_6 -of_objects [ipx::current_core]] -set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 7 and \ - spirit:decode(id('MODELPARAM_VALUE.RX_ENABLE')) == 1} \ - [ipx::get_bus_interfaces gt_rx_7 -of_objects [ipx::current_core]] - -set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 0 and \ - spirit:decode(id('MODELPARAM_VALUE.TX_ENABLE')) == 1} \ - [ipx::get_bus_interfaces gt_tx_0 -of_objects [ipx::current_core]] -set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 1 and \ - spirit:decode(id('MODELPARAM_VALUE.TX_ENABLE')) == 1} \ - [ipx::get_bus_interfaces gt_tx_1 -of_objects [ipx::current_core]] -set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 2 and \ - spirit:decode(id('MODELPARAM_VALUE.TX_ENABLE')) == 1} \ - [ipx::get_bus_interfaces gt_tx_2 -of_objects [ipx::current_core]] -set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 3 and \ - spirit:decode(id('MODELPARAM_VALUE.TX_ENABLE')) == 1} \ - [ipx::get_bus_interfaces gt_tx_3 -of_objects [ipx::current_core]] -set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 4 and \ - spirit:decode(id('MODELPARAM_VALUE.TX_ENABLE')) == 1} \ - [ipx::get_bus_interfaces gt_tx_4 -of_objects [ipx::current_core]] -set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 5 and \ - spirit:decode(id('MODELPARAM_VALUE.TX_ENABLE')) == 1} \ - [ipx::get_bus_interfaces gt_tx_5 -of_objects [ipx::current_core]] -set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 6 and \ - spirit:decode(id('MODELPARAM_VALUE.TX_ENABLE')) == 1} \ - [ipx::get_bus_interfaces gt_tx_6 -of_objects [ipx::current_core]] -set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 7 and \ - spirit:decode(id('MODELPARAM_VALUE.TX_ENABLE')) == 1} \ - [ipx::get_bus_interfaces gt_tx_7 -of_objects [ipx::current_core]] - -set_property driver_value 0 [ipx::get_ports -filter "direction==in" -of_objects [ipx::current_core]] - -ipx::save_core [ipx::current_core] - diff --git a/library/util_mfifo/Makefile b/library/util_mfifo/Makefile index 0f3e4869c..dc730cf23 100644 --- a/library/util_mfifo/Makefile +++ b/library/util_mfifo/Makefile @@ -5,11 +5,12 @@ #################################################################################### #################################################################################### -M_DEPS := util_mfifo_ip.tcl +M_DEPS += ../common/ad_mem.v M_DEPS += ../scripts/adi_env.tcl M_DEPS += ../scripts/adi_ip.tcl -M_DEPS += ../common/ad_mem.v M_DEPS += util_mfifo.v +M_DEPS += util_mfifo_constr.xdc +M_DEPS += util_mfifo_ip.tcl M_VIVADO := vivado -mode batch -source @@ -20,6 +21,10 @@ M_FLIST += *.log M_FLIST += component.xml M_FLIST += *.jou M_FLIST += xgui +M_FLIST += *.ip_user_files +M_FLIST += *.srcs +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil @@ -36,7 +41,7 @@ clean-all: util_mfifo.xpr: $(M_DEPS) - rm -rf $(M_FLIST) + -rm -rf $(M_FLIST) $(M_VIVADO) util_mfifo_ip.tcl >> util_mfifo_ip.log 2>&1 #################################################################################### diff --git a/library/util_pmod_adc/Makefile b/library/util_pmod_adc/Makefile index b96f79884..ba1493d14 100644 --- a/library/util_pmod_adc/Makefile +++ b/library/util_pmod_adc/Makefile @@ -5,11 +5,11 @@ #################################################################################### #################################################################################### -M_DEPS := util_pmod_adc_ip.tcl M_DEPS += ../scripts/adi_env.tcl M_DEPS += ../scripts/adi_ip.tcl M_DEPS += util_pmod_adc.v M_DEPS += util_pmod_adc_constr.xdc +M_DEPS += util_pmod_adc_ip.tcl M_VIVADO := vivado -mode batch -source @@ -20,6 +20,10 @@ M_FLIST += *.log M_FLIST += component.xml M_FLIST += *.jou M_FLIST += xgui +M_FLIST += *.ip_user_files +M_FLIST += *.srcs +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil @@ -36,7 +40,7 @@ clean-all: util_pmod_adc.xpr: $(M_DEPS) - rm -rf $(M_FLIST) + -rm -rf $(M_FLIST) $(M_VIVADO) util_pmod_adc_ip.tcl >> util_pmod_adc_ip.log 2>&1 #################################################################################### diff --git a/library/util_pmod_fmeter/Makefile b/library/util_pmod_fmeter/Makefile index ec1445ae3..7242ef736 100644 --- a/library/util_pmod_fmeter/Makefile +++ b/library/util_pmod_fmeter/Makefile @@ -5,15 +5,15 @@ #################################################################################### #################################################################################### -M_DEPS := util_pmod_fmeter_ip.tcl -M_DEPS += ../scripts/adi_env.tcl -M_DEPS += ../scripts/adi_ip.tcl M_DEPS += ../common/ad_rst.v -M_DEPS += ../common/up_xfer_status.v M_DEPS += ../common/up_axi.v M_DEPS += ../common/up_pmod.v +M_DEPS += ../common/up_xfer_status.v +M_DEPS += ../scripts/adi_env.tcl +M_DEPS += ../scripts/adi_ip.tcl M_DEPS += util_pmod_fmeter.v M_DEPS += util_pmod_fmeter_core.v +M_DEPS += util_pmod_fmeter_ip.tcl M_VIVADO := vivado -mode batch -source @@ -24,6 +24,10 @@ M_FLIST += *.log M_FLIST += component.xml M_FLIST += *.jou M_FLIST += xgui +M_FLIST += *.ip_user_files +M_FLIST += *.srcs +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil @@ -40,7 +44,7 @@ clean-all: util_pmod_fmeter.xpr: $(M_DEPS) - rm -rf $(M_FLIST) + -rm -rf $(M_FLIST) $(M_VIVADO) util_pmod_fmeter_ip.tcl >> util_pmod_fmeter_ip.log 2>&1 #################################################################################### diff --git a/library/util_pmod_fmeter/util_pmod_fmeter.v b/library/util_pmod_fmeter/util_pmod_fmeter.v index da5dc5819..8cae03366 100644 --- a/library/util_pmod_fmeter/util_pmod_fmeter.v +++ b/library/util_pmod_fmeter/util_pmod_fmeter.v @@ -62,7 +62,9 @@ module util_pmod_fmeter ( s_axi_rvalid, s_axi_rresp, s_axi_rdata, - s_axi_rready); + s_axi_rready, + s_axi_awprot, + s_axi_arprot); // parameters @@ -94,6 +96,9 @@ module util_pmod_fmeter ( output [ 1:0] s_axi_rresp; output [31:0] s_axi_rdata; input s_axi_rready; + input [ 2:0] s_axi_awprot; + input [ 2:0] s_axi_arprot; + // internal signals diff --git a/library/util_rfifo/Makefile b/library/util_rfifo/Makefile index eab393fd5..341510d6f 100644 --- a/library/util_rfifo/Makefile +++ b/library/util_rfifo/Makefile @@ -5,10 +5,12 @@ #################################################################################### #################################################################################### -M_DEPS := util_rfifo_ip.tcl +M_DEPS += ../common/ad_mem.v M_DEPS += ../scripts/adi_env.tcl M_DEPS += ../scripts/adi_ip.tcl M_DEPS += util_rfifo.v +M_DEPS += util_rfifo_constr.xdc +M_DEPS += util_rfifo_ip.tcl M_VIVADO := vivado -mode batch -source @@ -19,6 +21,10 @@ M_FLIST += *.log M_FLIST += component.xml M_FLIST += *.jou M_FLIST += xgui +M_FLIST += *.ip_user_files +M_FLIST += *.srcs +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil @@ -35,7 +41,7 @@ clean-all: util_rfifo.xpr: $(M_DEPS) - rm -rf $(M_FLIST) + -rm -rf $(M_FLIST) $(M_VIVADO) util_rfifo_ip.tcl >> util_rfifo_ip.log 2>&1 #################################################################################### diff --git a/library/util_rfifo/util_rfifo.v b/library/util_rfifo/util_rfifo.v index d7c7e9ffb..e0b35a19b 100644 --- a/library/util_rfifo/util_rfifo.v +++ b/library/util_rfifo/util_rfifo.v @@ -34,131 +34,373 @@ // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // *************************************************************************** // *************************************************************************** -// allows conversions between the dac (or similar) interface to the dma (or similar). -// * asymmetric bus widths in the range allowed by the fifo -// * frequency -- dma can run slower at reduced channels -// * drop or add channels -- pre processing samples -// * interface axis -- allows axi-stream interface -// -// in all cases bandwidth requirements must be met (read <= write). -// -// axis-interface support -// * connect dma_rd as axis_ready, make sure data is present (use dma_rd as -// enable for the data pipe line). leave axis_valid open! -// * make sure read bandwidth <= write bandwidth (or interpolate samples) -// -// the fifo is external- connect all the fifo_* signals to a fifo generator IP. -// configure the IP to match the buswidths & clocks. -// *************************************************************************** -// *************************************************************************** `timescale 1ns/100ps module util_rfifo ( - // dac interface + // d-in interface - dac_clk, - dac_rd, - dac_rdata, - dac_runf, + din_rstn, + din_clk, + din_enable_0, + din_valid_0, + din_data_0, + din_enable_1, + din_valid_1, + din_data_1, + din_enable_2, + din_valid_2, + din_data_2, + din_enable_3, + din_valid_3, + din_data_3, + din_enable_4, + din_valid_4, + din_data_4, + din_enable_5, + din_valid_5, + din_data_5, + din_enable_6, + din_valid_6, + din_data_6, + din_enable_7, + din_valid_7, + din_data_7, + din_unf, - // dma interface + // d-out interface - dma_clk, - dma_rd, - dma_rdata, - dma_runf, - - // fifo interface - - fifo_rst, - fifo_rstn, - fifo_wr, - fifo_wdata, - fifo_wfull, - fifo_rd, - fifo_rdata, - fifo_rempty, - fifo_runf); + dout_rst, + dout_clk, + dout_enable_0, + dout_valid_0, + dout_data_0, + dout_enable_1, + dout_valid_1, + dout_data_1, + dout_enable_2, + dout_valid_2, + dout_data_2, + dout_enable_3, + dout_valid_3, + dout_data_3, + dout_enable_4, + dout_valid_4, + dout_data_4, + dout_enable_5, + dout_valid_5, + dout_data_5, + dout_enable_6, + dout_valid_6, + dout_data_6, + dout_enable_7, + dout_valid_7, + dout_data_7, + dout_unf); // parameters - parameter DAC_DATA_WIDTH = 32; - parameter DMA_DATA_WIDTH = 64; + parameter NUM_OF_CHANNELS = 4; + parameter DIN_DATA_WIDTH = 32; + parameter DOUT_DATA_WIDTH = 64; + parameter DIN_ADDRESS_WIDTH = 8; - // dac interface + localparam M_MEM_RATIO = DOUT_DATA_WIDTH/DIN_DATA_WIDTH; + localparam ADDRESS_WIDTH = (DIN_ADDRESS_WIDTH > 5) ? DIN_ADDRESS_WIDTH : 5; + localparam DATA_WIDTH = DOUT_DATA_WIDTH * NUM_OF_CHANNELS; + localparam T_DIN_DATA_WIDTH = DIN_DATA_WIDTH * 8; + localparam T_DOUT_DATA_WIDTH = DOUT_DATA_WIDTH * 8; - input dac_clk; - input dac_rd; - output [DAC_DATA_WIDTH-1:0] dac_rdata; - output dac_runf; + // d-in interface - // dma interface + input din_rstn; + input din_clk; + output din_enable_0; + output din_valid_0; + input [DIN_DATA_WIDTH-1:0] din_data_0; + output din_enable_1; + output din_valid_1; + input [DIN_DATA_WIDTH-1:0] din_data_1; + output din_enable_2; + output din_valid_2; + input [DIN_DATA_WIDTH-1:0] din_data_2; + output din_enable_3; + output din_valid_3; + input [DIN_DATA_WIDTH-1:0] din_data_3; + output din_enable_4; + output din_valid_4; + input [DIN_DATA_WIDTH-1:0] din_data_4; + output din_enable_5; + output din_valid_5; + input [DIN_DATA_WIDTH-1:0] din_data_5; + output din_enable_6; + output din_valid_6; + input [DIN_DATA_WIDTH-1:0] din_data_6; + output din_enable_7; + output din_valid_7; + input [DIN_DATA_WIDTH-1:0] din_data_7; + input din_unf; - input dma_clk; - output dma_rd; - input [DMA_DATA_WIDTH-1:0] dma_rdata; - input dma_runf; + // dout interface - // fifo interface - - output fifo_rst; - output fifo_rstn; - output fifo_wr; - output [DMA_DATA_WIDTH-1:0] fifo_wdata; - input fifo_wfull; - output fifo_rd; - input [DAC_DATA_WIDTH-1:0] fifo_rdata; - input fifo_rempty; - input fifo_runf; + input dout_rst; + input dout_clk; + input dout_enable_0; + input dout_valid_0; + output [DOUT_DATA_WIDTH-1:0] dout_data_0; + input dout_enable_1; + input dout_valid_1; + output [DOUT_DATA_WIDTH-1:0] dout_data_1; + input dout_enable_2; + input dout_valid_2; + output [DOUT_DATA_WIDTH-1:0] dout_data_2; + input dout_enable_3; + input dout_valid_3; + output [DOUT_DATA_WIDTH-1:0] dout_data_3; + input dout_enable_4; + input dout_valid_4; + output [DOUT_DATA_WIDTH-1:0] dout_data_4; + input dout_enable_5; + input dout_valid_5; + output [DOUT_DATA_WIDTH-1:0] dout_data_5; + input dout_enable_6; + input dout_valid_6; + output [DOUT_DATA_WIDTH-1:0] dout_data_6; + input dout_enable_7; + input dout_valid_7; + output [DOUT_DATA_WIDTH-1:0] dout_data_7; + output dout_unf; // internal registers - reg [ 1:0] dac_runf_m = 'd0; - reg dac_runf = 'd0; - reg dma_rd = 'd0; + reg [(DATA_WIDTH-1):0] din_wdata = 'd0; + reg [(ADDRESS_WIDTH-1):0] din_waddr = 'hc; + reg din_wr = 'd0; + reg din_valid = 'd0; + reg [ 6:0] din_req_cnt = 'd0; + reg [ 7:0] din_enable_m1 = 'd0; + reg [ 7:0] din_enable = 'd0; + reg din_req_t_m1 = 'd0; + reg din_req_t_m2 = 'd0; + reg din_req_t_m3 = 'd0; + reg din_req = 'd0; + reg [(ADDRESS_WIDTH-4):0] din_rinit = 'd0; + reg din_unf_d = 'd0; + reg [(T_DOUT_DATA_WIDTH+1):0] dout_data = 'd0; + reg [(DATA_WIDTH-1):0] dout_rdata = 'd0; + reg [ 7:0] dout_enable = 'd0; + reg dout_req_t = 'd0; + reg [(ADDRESS_WIDTH-4):0] dout_rinit = 'd0; + reg [(ADDRESS_WIDTH-1):0] dout_raddr = 'd0; + reg dout_unf_m1 = 'd0; + reg dout_unf = 'd0; - // dac underflow + // internal signals - always @(posedge dac_clk) begin - dac_runf_m[0] <= dma_runf | fifo_runf; - dac_runf_m[1] <= dac_runf_m[0]; - dac_runf <= dac_runf_m[1]; - end + wire [(T_DIN_DATA_WIDTH-1):0] din_data_s; + wire din_req_s; + wire [ 7:0] dout_enable_s; + wire [ 7:0] dout_valid_s; + wire [(T_DOUT_DATA_WIDTH+1):0] dout_data_s; + wire [(DATA_WIDTH-1):0] dout_rdata_s; - // dma read + // variables - always @(posedge dma_clk) begin - dma_rd <= ~fifo_wfull; - end + genvar n; - // write + // enables & valids - assign fifo_wr = dma_rd; + assign din_enable_7 = din_enable[7]; + assign din_enable_6 = din_enable[6]; + assign din_enable_5 = din_enable[5]; + assign din_enable_4 = din_enable[4]; + assign din_enable_3 = din_enable[3]; + assign din_enable_2 = din_enable[2]; + assign din_enable_1 = din_enable[1]; + assign din_enable_0 = din_enable[0]; + + assign din_valid_7 = din_valid; + assign din_valid_6 = din_valid; + assign din_valid_5 = din_valid; + assign din_valid_4 = din_valid; + assign din_valid_3 = din_valid; + assign din_valid_2 = din_valid; + assign din_valid_1 = din_valid; + assign din_valid_0 = din_valid; + + assign din_data_s = { din_data_7, din_data_6, din_data_5, din_data_4, + din_data_3, din_data_2, din_data_1, din_data_0}; + + // simple data transfer-- no ovf/unf handling- read-bw > write-bw + // dout_width >= din_width only - genvar s; generate - for (s = 0; s < DMA_DATA_WIDTH; s = s + 1) begin: g_wdata - assign fifo_wdata[s] = dma_rdata[(DMA_DATA_WIDTH-1)-s]; + for (n = 0; n < NUM_OF_CHANNELS; n = n + 1) begin: g_in + if (M_MEM_RATIO == 1) begin + always @(posedge din_clk) begin + if (din_valid == 1'b1) begin + din_wdata[((DOUT_DATA_WIDTH*(n+1))-1):(DOUT_DATA_WIDTH*n)] <= + din_data_s[((DIN_DATA_WIDTH*(n+1))-1):(DIN_DATA_WIDTH*n)]; + end + end + end else begin + always @(posedge din_clk) begin + if (din_valid == 1'b1) begin + din_wdata[((DOUT_DATA_WIDTH*(n+1))-1):(DOUT_DATA_WIDTH*n)] <= + {din_data_s[((DIN_DATA_WIDTH*(n+1))-1):(DIN_DATA_WIDTH*n)], + din_wdata[((DOUT_DATA_WIDTH*(n+1))-1):(DIN_DATA_WIDTH+(DOUT_DATA_WIDTH*n))]}; + end + end + end end endgenerate - // read + always @(posedge din_clk or negedge din_rstn) begin + if (din_rstn == 1'b0) begin + din_waddr <= 'hc; + din_wr <= 1'd0; + end else begin + if (din_req == 1'b1) begin + din_waddr <= {din_rinit, 3'd0}; + end else if (din_wr == 1'b1) begin + din_waddr <= din_waddr + 1'b1; + end + case (M_MEM_RATIO) + 8: din_wr <= din_req_cnt[6] & din_req_cnt[2] & din_req_cnt[1] & din_req_cnt[0]; + 4: din_wr <= din_req_cnt[6] & din_req_cnt[1] & din_req_cnt[0]; + 2: din_wr <= din_req_cnt[6] & din_req_cnt[0]; + default: din_wr <= din_req_cnt[6]; + endcase + end + end - assign fifo_rd = ~fifo_rempty & dac_rd; + always @(posedge din_clk or negedge din_rstn) begin + if (din_rstn == 1'b0) begin + din_valid <= 'd0; + din_req_cnt <= 'd0; + end else begin + din_valid <= din_req_cnt[6]; + if (din_req_s == 1'b1) begin + case (M_MEM_RATIO) + 8: din_req_cnt <= 7'h40; + 4: din_req_cnt <= 7'h60; + 2: din_req_cnt <= 7'h70; + default: din_req_cnt <= 7'h78; + endcase + end else if (din_req_cnt[6] == 1'b1) begin + din_req_cnt <= din_req_cnt + 1'b1; + end + end + end + + assign din_req_s = din_req_t_m3 ^ din_req_t_m2; + + always @(posedge din_clk or negedge din_rstn) begin + if (din_rstn == 1'b0) begin + din_enable_m1 <= 'd0; + din_enable <= 'd0; + din_req_t_m1 <= 'd0; + din_req_t_m2 <= 'd0; + din_req_t_m3 <= 'd0; + din_req <= 'd0; + din_rinit <= 'd0; + din_unf_d <= 'd0; + end else begin + din_enable_m1 <= dout_enable; + din_enable <= din_enable_m1; + din_req_t_m1 <= dout_req_t; + din_req_t_m2 <= din_req_t_m1; + din_req_t_m3 <= din_req_t_m2; + din_req <= din_req_s; + if (din_req_s == 1'b1) begin + din_rinit <= dout_rinit; + end + din_unf_d <= din_unf; + end + end + + // read interface (bus expansion and/or clock conversion) + + assign dout_enable_s = { dout_enable_7, dout_enable_6, dout_enable_5, dout_enable_4, + dout_enable_3, dout_enable_2, dout_enable_1, dout_enable_0}; + + assign dout_valid_s = { dout_valid_7, dout_valid_6, dout_valid_5, dout_valid_4, + dout_valid_3, dout_valid_2, dout_valid_1, dout_valid_0}; - genvar m; generate - for (m = 0; m < DAC_DATA_WIDTH; m = m + 1) begin: g_rdata - assign dac_rdata[m] = fifo_rdata[(DAC_DATA_WIDTH-1)-m]; + if (NUM_OF_CHANNELS >= 8) begin + assign dout_data_s = dout_rdata; + end else begin + assign dout_data_s[(T_DOUT_DATA_WIDTH+1):DATA_WIDTH] = 'd0; + assign dout_data_s[(DATA_WIDTH-1):0] = dout_rdata; end endgenerate - // reset & resetn + assign dout_data_7 = dout_data[((DOUT_DATA_WIDTH*8)-1):(DOUT_DATA_WIDTH*7)]; + assign dout_data_6 = dout_data[((DOUT_DATA_WIDTH*7)-1):(DOUT_DATA_WIDTH*6)]; + assign dout_data_5 = dout_data[((DOUT_DATA_WIDTH*6)-1):(DOUT_DATA_WIDTH*5)]; + assign dout_data_4 = dout_data[((DOUT_DATA_WIDTH*5)-1):(DOUT_DATA_WIDTH*4)]; + assign dout_data_3 = dout_data[((DOUT_DATA_WIDTH*4)-1):(DOUT_DATA_WIDTH*3)]; + assign dout_data_2 = dout_data[((DOUT_DATA_WIDTH*3)-1):(DOUT_DATA_WIDTH*2)]; + assign dout_data_1 = dout_data[((DOUT_DATA_WIDTH*2)-1):(DOUT_DATA_WIDTH*1)]; + assign dout_data_0 = dout_data[((DOUT_DATA_WIDTH*1)-1):(DOUT_DATA_WIDTH*0)]; - assign fifo_rst = 1'b0; - assign fifo_rstn = 1'b1; + generate + for (n = 0; n < NUM_OF_CHANNELS; n = n + 1) begin: g_out + always @(posedge dout_clk) begin + if (dout_rst == 1'b1) begin + dout_data[((DOUT_DATA_WIDTH*(n+1))-1):(DOUT_DATA_WIDTH*n)] <= 'd0; + end else if (dout_valid_s[n] == 1'b1) begin + dout_data[((DOUT_DATA_WIDTH*(n+1))-1):(DOUT_DATA_WIDTH*n)] <= + dout_data_s[((DOUT_DATA_WIDTH*(n+1))-1):(DOUT_DATA_WIDTH*n)]; + end + end + end + endgenerate + + always @(posedge dout_clk) begin + dout_rdata <= dout_rdata_s; + end + + always @(posedge dout_clk) begin + if (dout_rst == 1'b1) begin + dout_enable <= 'd0; + dout_req_t <= 'd0; + dout_rinit <= 'd0; + dout_raddr <= 'd0; + end else begin + dout_enable <= dout_enable_s; + if (dout_valid_s[0] == 1'b1) begin + if (dout_raddr[2:0] == 3'd7) begin + dout_req_t <= ~dout_req_t; + dout_rinit <= dout_raddr[(ADDRESS_WIDTH-1):3] + 2'd2; + end + dout_raddr <= dout_raddr + 1'b1; + end + end + end + + always @(posedge dout_clk) begin + if (dout_rst == 1'b1) begin + dout_unf_m1 <= 'd0; + dout_unf <= 'd0; + end else begin + dout_unf_m1 <= din_unf_d; + dout_unf <= dout_unf_m1; + end + end + + // instantiations + + ad_mem #(.ADDRESS_WIDTH(ADDRESS_WIDTH), .DATA_WIDTH(DATA_WIDTH)) i_mem ( + .clka (din_clk), + .wea (din_wr), + .addra (din_waddr), + .dina (din_wdata), + .clkb (dout_clk), + .addrb (dout_raddr), + .doutb (dout_rdata_s)); endmodule diff --git a/library/util_rfifo/util_rfifo_constr.sdc b/library/util_rfifo/util_rfifo_constr.sdc new file mode 100644 index 000000000..22c99c8cf --- /dev/null +++ b/library/util_rfifo/util_rfifo_constr.sdc @@ -0,0 +1,6 @@ + +set_false_path -from [get_registers *dout_enable*] -to [get_registers *din_enable_m1*] +set_false_path -from [get_registers *dout_req_t*] -to [get_registers *din_req_t_m1*] +set_false_path -from [get_registers *dout_rinit*] -to [get_registers *din_rinit*] +set_false_path -from [get_registers *din_unf_d*] -to [get_registers *dout_unf_m1*] + diff --git a/library/util_rfifo/util_rfifo_constr.xdc b/library/util_rfifo/util_rfifo_constr.xdc new file mode 100644 index 000000000..dc0d606ed --- /dev/null +++ b/library/util_rfifo/util_rfifo_constr.xdc @@ -0,0 +1,10 @@ + +set_property shreg_extract no [get_cells -hier -filter {name =~ *din_enable_m*}] +set_property shreg_extract no [get_cells -hier -filter {name =~ *din_req_t_m*}] +set_property shreg_extract no [get_cells -hier -filter {name =~ *dout_unf_m*}] + +set_false_path -from [get_cells -hier -filter {name =~ *dout_enable* && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *din_enable_m1* && IS_SEQUENTIAL}] +set_false_path -from [get_cells -hier -filter {name =~ *dout_req_t* && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *din_req_t_m1* && IS_SEQUENTIAL}] +set_false_path -from [get_cells -hier -filter {name =~ *dout_rinit* && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *din_rinit* && IS_SEQUENTIAL}] +set_false_path -from [get_cells -hier -filter {name =~ *din_unf* && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *dout_unf_m1* && IS_SEQUENTIAL}] + diff --git a/library/util_rfifo/util_rfifo_hw.tcl b/library/util_rfifo/util_rfifo_hw.tcl new file mode 100755 index 000000000..e64e2b3e7 --- /dev/null +++ b/library/util_rfifo/util_rfifo_hw.tcl @@ -0,0 +1,215 @@ + + +package require -exact qsys 13.0 +source ../scripts/adi_env.tcl +source ../scripts/adi_ip_alt.tcl + +set_module_property NAME util_rfifo +set_module_property DESCRIPTION "Utils Read FIFO" +set_module_property VERSION 1.0 +set_module_property GROUP "Analog Devices" +set_module_property DISPLAY_NAME util_rfifo +set_module_property ELABORATION_CALLBACK p_util_rfifo + +# files + +add_fileset quartus_synth QUARTUS_SYNTH "" "" +set_fileset_property quartus_synth TOP_LEVEL util_rfifo +add_fileset_file ad_mem.v VERILOG PATH $ad_hdl_dir/library/common/ad_mem.v +add_fileset_file util_rfifo.v VERILOG PATH util_rfifo.v TOP_LEVEL_FILE +add_fileset_file util_rfifo_constr.sdc SDC PATH util_rfifo_constr.sdc + +# parameters + +add_parameter NUM_OF_CHANNELS INTEGER 0 +set_parameter_property NUM_OF_CHANNELS DEFAULT_VALUE 4 +set_parameter_property NUM_OF_CHANNELS DISPLAY_NAME NUM_OF_CHANNELS +set_parameter_property NUM_OF_CHANNELS TYPE INTEGER +set_parameter_property NUM_OF_CHANNELS UNITS None +set_parameter_property NUM_OF_CHANNELS HDL_PARAMETER true + +add_parameter DIN_DATA_WIDTH INTEGER 0 +set_parameter_property DIN_DATA_WIDTH DEFAULT_VALUE 32 +set_parameter_property DIN_DATA_WIDTH DISPLAY_NAME DIN_DATA_WIDTH +set_parameter_property DIN_DATA_WIDTH TYPE INTEGER +set_parameter_property DIN_DATA_WIDTH UNITS None +set_parameter_property DIN_DATA_WIDTH HDL_PARAMETER true + +add_parameter DOUT_DATA_WIDTH INTEGER 0 +set_parameter_property DOUT_DATA_WIDTH DEFAULT_VALUE 64 +set_parameter_property DOUT_DATA_WIDTH DISPLAY_NAME DOUT_DATA_WIDTH +set_parameter_property DOUT_DATA_WIDTH TYPE INTEGER +set_parameter_property DOUT_DATA_WIDTH UNITS None +set_parameter_property DOUT_DATA_WIDTH HDL_PARAMETER true + +add_parameter DIN_ADDRESS_WIDTH INTEGER 0 +set_parameter_property DIN_ADDRESS_WIDTH DEFAULT_VALUE 8 +set_parameter_property DIN_ADDRESS_WIDTH DISPLAY_NAME DIN_ADDRESS_WIDTH +set_parameter_property DIN_ADDRESS_WIDTH TYPE INTEGER +set_parameter_property DIN_ADDRESS_WIDTH UNITS None +set_parameter_property DIN_ADDRESS_WIDTH HDL_PARAMETER true + +# defaults + +ad_alt_intf clock din_clk input 1 +ad_alt_intf reset-n din_rstn input 1 if_din_clk + +ad_alt_intf clock dout_clk input 1 +ad_alt_intf reset dout_rst input 1 if_dout_clk + +add_interface din_0 conduit end +add_interface_port din_0 din_enable_0 enable Output 1 +add_interface_port din_0 din_valid_0 valid Output 1 +add_interface_port din_0 din_data_0 data Input DIN_DATA_WIDTH + +set_interface_property din_0 associatedClock if_din_clk +set_interface_property din_0 associatedReset none + +add_interface dout_0 conduit end +add_interface_port dout_0 dout_enable_0 enable Input 1 +add_interface_port dout_0 dout_valid_0 valid Input 1 +add_interface_port dout_0 dout_data_0 data Output DOUT_DATA_WIDTH + +set_interface_property dout_0 associatedClock if_dout_clk +set_interface_property dout_0 associatedReset none + +ad_alt_intf signal din_unf input 1 unf +ad_alt_intf signal dout_unf output 1 unf + +proc p_util_rfifo {} { + + if {[get_parameter_value NUM_OF_CHANNELS] > 1} { + + add_interface din_1 conduit end + add_interface_port din_1 din_enable_1 enable Output 1 + add_interface_port din_1 din_valid_1 valid Output 1 + add_interface_port din_1 din_data_1 data Input DIN_DATA_WIDTH + + set_interface_property din_1 associatedClock if_din_clk + set_interface_property din_1 associatedReset none + + add_interface dout_1 conduit end + add_interface_port dout_1 dout_enable_1 enable Input 1 + add_interface_port dout_1 dout_valid_1 valid Input 1 + add_interface_port dout_1 dout_data_1 data Output DOUT_DATA_WIDTH + + set_interface_property dout_1 associatedClock if_dout_clk + set_interface_property dout_1 associatedReset none + } + + if {[get_parameter_value NUM_OF_CHANNELS] > 2} { + + add_interface din_2 conduit end + add_interface_port din_2 din_enable_2 enable Output 1 + add_interface_port din_2 din_valid_2 valid Output 1 + add_interface_port din_2 din_data_2 data Input DIN_DATA_WIDTH + + set_interface_property din_2 associatedClock if_din_clk + set_interface_property din_2 associatedReset none + + add_interface dout_2 conduit end + add_interface_port dout_2 dout_enable_2 enable Input 1 + add_interface_port dout_2 dout_valid_2 valid Input 1 + add_interface_port dout_2 dout_data_2 data Output DOUT_DATA_WIDTH + + set_interface_property dout_2 associatedClock if_dout_clk + set_interface_property dout_2 associatedReset none + } + + if {[get_parameter_value NUM_OF_CHANNELS] > 3} { + + add_interface din_3 conduit end + add_interface_port din_3 din_enable_3 enable Output 1 + add_interface_port din_3 din_valid_3 valid Output 1 + add_interface_port din_3 din_data_3 data Input DIN_DATA_WIDTH + + set_interface_property din_3 associatedClock if_din_clk + set_interface_property din_3 associatedReset none + + add_interface dout_3 conduit end + add_interface_port dout_3 dout_enable_3 enable Input 1 + add_interface_port dout_3 dout_valid_3 valid Input 1 + add_interface_port dout_3 dout_data_3 data Output DOUT_DATA_WIDTH + + set_interface_property dout_3 associatedClock if_dout_clk + set_interface_property dout_3 associatedReset none + } + + if {[get_parameter_value NUM_OF_CHANNELS] > 4} { + + add_interface din_4 conduit end + add_interface_port din_4 din_enable_4 enable Output 1 + add_interface_port din_4 din_valid_4 valid Output 1 + add_interface_port din_4 din_data_4 data Input DIN_DATA_WIDTH + + set_interface_property din_4 associatedClock if_din_clk + set_interface_property din_4 associatedReset none + + add_interface dout_4 conduit end + add_interface_port dout_4 dout_enable_4 enable Input 1 + add_interface_port dout_4 dout_valid_4 valid Input 1 + add_interface_port dout_4 dout_data_4 data Output DOUT_DATA_WIDTH + + set_interface_property dout_4 associatedClock if_dout_clk + set_interface_property dout_4 associatedReset none + } + + if {[get_parameter_value NUM_OF_CHANNELS] > 5} { + + add_interface din_5 conduit end + add_interface_port din_5 din_enable_5 enable Output 1 + add_interface_port din_5 din_valid_5 valid Output 1 + add_interface_port din_5 din_data_5 data Input DIN_DATA_WIDTH + + set_interface_property din_5 associatedClock if_din_clk + set_interface_property din_5 associatedReset none + + add_interface dout_5 conduit end + add_interface_port dout_5 dout_enable_5 enable Input 1 + add_interface_port dout_5 dout_valid_5 valid Input 1 + add_interface_port dout_5 dout_data_5 data Output DOUT_DATA_WIDTH + + set_interface_property dout_5 associatedClock if_dout_clk + set_interface_property dout_5 associatedReset none + } + + if {[get_parameter_value NUM_OF_CHANNELS] > 6} { + + add_interface din_6 conduit end + add_interface_port din_6 din_enable_6 enable Output 1 + add_interface_port din_6 din_valid_6 valid Output 1 + add_interface_port din_6 din_data_6 data Input DIN_DATA_WIDTH + + set_interface_property din_6 associatedClock if_din_clk + set_interface_property din_6 associatedReset none + + add_interface dout_6 conduit end + add_interface_port dout_6 dout_enable_6 enable Input 1 + add_interface_port dout_6 dout_valid_6 valid Input 1 + add_interface_port dout_6 dout_data_6 data Output DOUT_DATA_WIDTH + + set_interface_property dout_6 associatedClock if_dout_clk + set_interface_property dout_6 associatedReset none + } + + if {[get_parameter_value NUM_OF_CHANNELS] > 7} { + + add_interface din_7 conduit end + add_interface_port din_7 din_enable_7 enable Output 1 + add_interface_port din_7 din_valid_7 valid Output 1 + add_interface_port din_7 din_data_7 data Input DIN_DATA_WIDTH + + set_interface_property din_7 associatedClock if_din_clk + set_interface_property din_7 associatedReset none + + add_interface dout_7 conduit end + add_interface_port dout_7 dout_enable_7 enable Input 1 + add_interface_port dout_7 dout_valid_7 valid Input 1 + add_interface_port dout_7 dout_data_7 data Output DOUT_DATA_WIDTH + + set_interface_property dout_7 associatedClock if_dout_clk + set_interface_property dout_7 associatedReset none + } + +} + diff --git a/library/util_rfifo/util_rfifo_ip.tcl b/library/util_rfifo/util_rfifo_ip.tcl index d18ca94d8..d8d2b8d7f 100644 --- a/library/util_rfifo/util_rfifo_ip.tcl +++ b/library/util_rfifo/util_rfifo_ip.tcl @@ -5,11 +5,34 @@ source $ad_hdl_dir/library/scripts/adi_ip.tcl adi_ip_create util_rfifo adi_ip_files util_rfifo [list \ + "$ad_hdl_dir/library/common/ad_mem.v" \ "util_rfifo.v" ] adi_ip_properties_lite util_rfifo +adi_ip_constraints util_rfifo [list \ + "util_rfifo_constr.xdc" ] + ipx::remove_all_bus_interface [ipx::current_core] +set_property driver_value 0 [ipx::get_ports *dout_enable* -of_objects [ipx::current_core]] +set_property driver_value 0 [ipx::get_ports *dout_valid* -of_objects [ipx::current_core]] +set_property driver_value 0 [ipx::get_ports *din_data* -of_objects [ipx::current_core]] +set_property driver_value 0 [ipx::get_ports *din_unf* -of_objects [ipx::current_core]] +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 1} \ + [ipx::get_ports *_1* -of_objects [ipx::current_core]] +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 2} \ + [ipx::get_ports *_2* -of_objects [ipx::current_core]] +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 3} \ + [ipx::get_ports *_3* -of_objects [ipx::current_core]] +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 4} \ + [ipx::get_ports *_4* -of_objects [ipx::current_core]] +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 5} \ + [ipx::get_ports *_5* -of_objects [ipx::current_core]] +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 6} \ + [ipx::get_ports *_6* -of_objects [ipx::current_core]] +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 7} \ + [ipx::get_ports *_7* -of_objects [ipx::current_core]] + ipx::save_core [ipx::current_core] diff --git a/library/util_sigma_delta_spi/Makefile b/library/util_sigma_delta_spi/Makefile index bb6af71ea..51e2658ac 100644 --- a/library/util_sigma_delta_spi/Makefile +++ b/library/util_sigma_delta_spi/Makefile @@ -5,10 +5,13 @@ #################################################################################### #################################################################################### -M_DEPS := util_sigma_delta_spi_ip.tcl M_DEPS += ../scripts/adi_env.tcl M_DEPS += ../scripts/adi_ip.tcl M_DEPS += util_sigma_delta_spi.v +M_DEPS += util_sigma_delta_spi_ip.tcl + +M_DEPS += ../spi_engine/interfaces/spi_master.xml +M_DEPS += ../spi_engine/interfaces/spi_master_rtl.xml M_VIVADO := vivado -mode batch -source @@ -19,6 +22,10 @@ M_FLIST += *.log M_FLIST += component.xml M_FLIST += *.jou M_FLIST += xgui +M_FLIST += *.ip_user_files +M_FLIST += *.srcs +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil @@ -35,7 +42,7 @@ clean-all: util_sigma_delta_spi.xpr: $(M_DEPS) - rm -rf $(M_FLIST) + -rm -rf $(M_FLIST) $(M_VIVADO) util_sigma_delta_spi_ip.tcl >> util_sigma_delta_spi_ip.log 2>&1 #################################################################################### diff --git a/library/util_sigma_delta_spi/util_sigma_delta_spi.v b/library/util_sigma_delta_spi/util_sigma_delta_spi.v index 9a9f3fa3f..48fd94965 100644 --- a/library/util_sigma_delta_spi/util_sigma_delta_spi.v +++ b/library/util_sigma_delta_spi/util_sigma_delta_spi.v @@ -1,23 +1,23 @@ module util_sigma_delta_spi ( - input clk, - input resetn, + input clk, + input resetn, - input spi_active, + input spi_active, - input s_sclk, - input s_sdo, - input s_sdo_t, - output s_sdi, - input [NUM_OF_CS-1:0] s_cs, + input s_sclk, + input s_sdo, + input s_sdo_t, + output s_sdi, + input [NUM_OF_CS-1:0] s_cs, - output m_sclk, - output m_sdo, - output m_sdo_t, - input m_sdi, - output [NUM_OF_CS-1:0] m_cs, + output m_sclk, + output m_sdo, + output m_sdo_t, + input m_sdi, + output [NUM_OF_CS-1:0] m_cs, - output reg data_ready + output reg data_ready ); parameter NUM_OF_CS = 1; @@ -46,29 +46,29 @@ reg [$clog2(IDLE_TIMEOUT)-1:0] counter = IDLE_TIMEOUT; reg [2:0] sdi_d = 'h00; always @(posedge clk) begin - if (resetn == 1'b0) begin - counter <= IDLE_TIMEOUT; - end else begin - if (s_cs[CS_PIN] == 1'b0 && spi_active == 1'b0) begin - if (counter != 'h00) - counter <= counter - 1'b1; - end else begin - counter <= IDLE_TIMEOUT; - end - end + if (resetn == 1'b0) begin + counter <= IDLE_TIMEOUT; + end else begin + if (s_cs[CS_PIN] == 1'b0 && spi_active == 1'b0) begin + if (counter != 'h00) + counter <= counter - 1'b1; + end else begin + counter <= IDLE_TIMEOUT; + end + end end always @(posedge clk) begin - /* The data ready signal is fully asynchronous */ - sdi_d <= {sdi_d[1:0], m_sdi}; + /* The data ready signal is fully asynchronous */ + sdi_d <= {sdi_d[1:0], m_sdi}; end always @(posedge clk) begin - if (counter == 'h00 && sdi_d[2] == 1'b0) begin - data_ready <= 1'b1; - end else begin - data_ready <= 1'b0; - end + if (counter == 'h00 && sdi_d[2] == 1'b0) begin + data_ready <= 1'b1; + end else begin + data_ready <= 1'b0; + end end endmodule diff --git a/library/util_tdd_sync/Makefile b/library/util_tdd_sync/Makefile index 82391ca4c..fba94e565 100644 --- a/library/util_tdd_sync/Makefile +++ b/library/util_tdd_sync/Makefile @@ -5,11 +5,12 @@ #################################################################################### #################################################################################### -M_DEPS := util_tdd_sync_ip.tcl +M_DEPS += ../common/util_pulse_gen.v M_DEPS += ../scripts/adi_env.tcl M_DEPS += ../scripts/adi_ip.tcl -M_DEPS += ../common/ad_tdd_sync.v M_DEPS += util_tdd_sync.v +M_DEPS += util_tdd_sync_constr.xdc +M_DEPS += util_tdd_sync_ip.tcl M_VIVADO := vivado -mode batch -source @@ -20,6 +21,10 @@ M_FLIST += *.log M_FLIST += component.xml M_FLIST += *.jou M_FLIST += xgui +M_FLIST += *.ip_user_files +M_FLIST += *.srcs +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil @@ -36,7 +41,7 @@ clean-all: util_tdd_sync.xpr: $(M_DEPS) - rm -rf $(M_FLIST) + -rm -rf $(M_FLIST) $(M_VIVADO) util_tdd_sync_ip.tcl >> util_tdd_sync_ip.log 2>&1 #################################################################################### diff --git a/library/util_tdd_sync/util_tdd_sync.v b/library/util_tdd_sync/util_tdd_sync.v index a687e9381..e75ce0687 100644 --- a/library/util_tdd_sync/util_tdd_sync.v +++ b/library/util_tdd_sync/util_tdd_sync.v @@ -36,14 +36,20 @@ // *************************************************************************** // *************************************************************************** // *************************************************************************** +// +// Simple pulse generator for TDD control +// The module has two modes. In function of the state of sync_mode, +// the syncronization signal (sync_out) can get its value from an external +// source or from its internal generator. +// + `timescale 1ns/1ps module util_tdd_sync ( clk, rstn, - sync_en, - sync_type, + sync_mode, sync_in, sync_out @@ -52,60 +58,51 @@ module util_tdd_sync ( input clk; input rstn; - input sync_en; - input sync_type; + input sync_mode; input sync_in; output sync_out; - parameter TDD_SYNC_PERIOD = 100000000; + parameter TDD_SYNC_PERIOD = 100000000; - reg sync_en_d1 = 1'b0; - reg sync_en_d2 = 1'b0; - reg sync_type_d1 = 1'b0; - reg sync_type_d2 = 1'b0; + reg sync_mode_d1 = 1'b0; + reg sync_mode_d2 = 1'b0; reg sync_out = 1'b0; - wire sync_gen; + wire sync_internal; + wire sync_external; // pulse generator - ad_tdd_sync #( - .TDD_SYNC_PERIOD(TDD_SYNC_PERIOD) + util_pulse_gen #( + .PULSE_PERIOD(TDD_SYNC_PERIOD) ) i_tdd_sync ( .clk (clk), .rstn (rstn), - .sync (sync_gen) + .pulse (sync_internal) ); // synchronization logic always @(posedge clk) begin if(rstn == 1'b0) begin - sync_en_d1 <= 1'b0; - sync_en_d2 <= 1'b0; - sync_type_d1 <= 1'b0; - sync_type_d2 <= 1'b0; + sync_mode_d1 <= 1'b0; + sync_mode_d2 <= 1'b0; end else begin - sync_en_d1 <= sync_en; - sync_en_d2 <= sync_en_d1; - sync_type_d1 <= sync_type; - sync_type_d2 <= sync_type_d1; + sync_mode_d1 <= sync_mode; + sync_mode_d2 <= sync_mode_d1; end end // output logic + assign sync_external = sync_in; always @(posedge clk) begin if(rstn == 1'b0) begin sync_out <= 1'b0; end else begin - if(sync_en_d2 == 1'b1) begin - sync_out <= (sync_type_d2 == 1'b0) ? sync_gen : sync_in; - end else begin - sync_out <= 1'b0; - end + sync_out <= (sync_mode_d2 == 1'b0) ? sync_internal : sync_external; end end diff --git a/library/util_tdd_sync/util_tdd_sync_constr.xdc b/library/util_tdd_sync/util_tdd_sync_constr.xdc index 775e3e043..1685985a5 100644 --- a/library/util_tdd_sync/util_tdd_sync_constr.xdc +++ b/library/util_tdd_sync/util_tdd_sync_constr.xdc @@ -1,5 +1,4 @@ -set_false_path -to [get_cells -hier -filter {NAME =~ *sync_en_d1* && IS_SEQUENTIAL}] -set_false_path -to [get_cells -hier -filter {NAME =~ *sync_type_d1* && IS_SEQUENTIAL}] +set_false_path -to [get_cells -hier -filter {NAME =~ *sync_mode_d1* && IS_SEQUENTIAL}] set_false_path -from [get_cells -hier -filter {NAME =~ *sync_out_reg* && IS_SEQUENTIAL}] diff --git a/library/util_tdd_sync/util_tdd_sync_ip.tcl b/library/util_tdd_sync/util_tdd_sync_ip.tcl index c1345792d..5881b95d5 100644 --- a/library/util_tdd_sync/util_tdd_sync_ip.tcl +++ b/library/util_tdd_sync/util_tdd_sync_ip.tcl @@ -6,7 +6,7 @@ source $ad_hdl_dir/library/scripts/adi_ip.tcl adi_ip_create util_tdd_sync adi_ip_files util_tdd_sync [list \ - "$ad_hdl_dir/library/common/ad_tdd_sync.v" \ + "$ad_hdl_dir/library/common/util_pulse_gen.v" \ "util_tdd_sync.v"] adi_ip_properties_lite util_tdd_sync diff --git a/library/util_upack/Makefile b/library/util_upack/Makefile index 49a0fcda7..4dc0b413c 100644 --- a/library/util_upack/Makefile +++ b/library/util_upack/Makefile @@ -5,13 +5,13 @@ #################################################################################### #################################################################################### -M_DEPS := util_upack_ip.tcl M_DEPS += ../scripts/adi_env.tcl M_DEPS += ../scripts/adi_ip.tcl -M_DEPS += util_upack_dmx.v -M_DEPS += util_upack_dsf.v M_DEPS += util_upack.v M_DEPS += util_upack_constr.xdc +M_DEPS += util_upack_dmx.v +M_DEPS += util_upack_dsf.v +M_DEPS += util_upack_ip.tcl M_VIVADO := vivado -mode batch -source @@ -22,6 +22,10 @@ M_FLIST += *.log M_FLIST += component.xml M_FLIST += *.jou M_FLIST += xgui +M_FLIST += *.ip_user_files +M_FLIST += *.srcs +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil @@ -38,7 +42,7 @@ clean-all: util_upack.xpr: $(M_DEPS) - rm -rf $(M_FLIST) + -rm -rf $(M_FLIST) $(M_VIVADO) util_upack_ip.tcl >> util_upack_ip.log 2>&1 #################################################################################### diff --git a/library/util_upack/util_upack_hw.tcl b/library/util_upack/util_upack_hw.tcl index 0217d3734..43039d60e 100755 --- a/library/util_upack/util_upack_hw.tcl +++ b/library/util_upack/util_upack_hw.tcl @@ -6,7 +6,7 @@ source ../scripts/adi_ip_alt.tcl set_module_property NAME util_upack -set_module_property DESCRIPTION "Channel Pack Utility" +set_module_property DESCRIPTION "Channel Unpack Utility" set_module_property VERSION 1.0 set_module_property GROUP "Analog Devices" set_module_property DISPLAY_NAME util_upack @@ -39,76 +39,92 @@ set_parameter_property NUM_OF_CHANNELS HDL_PARAMETER true # defaults ad_alt_intf clock dac_clk input 1 -ad_alt_intf signal dma_xfer_in input 1 xfer_req -ad_alt_intf signal dac_xfer_out output 1 xfer_req -ad_alt_intf signal dac_valid output 1 valid -ad_alt_intf signal dac_sync output 1 sync + +ad_alt_intf signal dma_xfer_in input 1 xfer_req +ad_alt_intf signal dac_xfer_out output 1 xfer_req + +ad_alt_intf signal dac_valid output 1 valid +ad_alt_intf signal dac_sync output 1 sync ad_alt_intf signal dac_data input NUM_OF_CHANNELS*CHANNEL_DATA_WIDTH data -add_interface fifo_ch_0 conduit end -#set_interface_property fifo_ch_0 associatedClock if_dac_clk -add_interface_port fifo_ch_0 dac_enable_0 enable Input 1 -add_interface_port fifo_ch_0 dac_valid_0 valid Input 1 -#add_interface_port fifo_ch_0 upack_valid_0 valid_o Output 1 -add_interface_port fifo_ch_0 dac_data_0 data Output CHANNEL_DATA_WIDTH +add_interface dac_ch_0 conduit end +add_interface_port dac_ch_0 dac_enable_0 enable Input 1 +add_interface_port dac_ch_0 dac_valid_0 valid Input 1 +add_interface_port dac_ch_0 dac_data_0 data Output CHANNEL_DATA_WIDTH + +set_interface_property dac_ch_0 associatedClock if_dac_clk +set_interface_property dac_ch_0 associatedReset none proc p_util_upack {} { if {[get_parameter_value NUM_OF_CHANNELS] > 1} { - add_interface fifo_ch_1 conduit end - #set_interface_property fifo_ch_1 associatedClock if_dac_clk - add_interface_port fifo_ch_1 dac_enable_1 enable Input 1 - add_interface_port fifo_ch_1 dac_valid_1 valid Input 1 -# add_interface_port fifo_ch_1 upack_valid_1 valid_o Output 1 - add_interface_port fifo_ch_1 dac_data_1 data Output CHANNEL_DATA_WIDTH + + add_interface dac_ch_1 conduit end + add_interface_port dac_ch_1 dac_enable_1 enable Input 1 + add_interface_port dac_ch_1 dac_valid_1 valid Input 1 + add_interface_port dac_ch_1 dac_data_1 data Output CHANNEL_DATA_WIDTH + + set_interface_property dac_ch_1 associatedClock if_dac_clk } + if {[get_parameter_value NUM_OF_CHANNELS] > 2} { - add_interface fifo_ch_2 conduit end - #set_interface_property fifo_ch_2 associatedClock if_dac_clk - add_interface_port fifo_ch_2 dac_enable_2 enable Input 1 - add_interface_port fifo_ch_2 dac_valid_2 valid Input 1 -# add_interface_port fifo_ch_2 upack_valid_2 valid_o Output 1 - add_interface_port fifo_ch_2 dac_data_2 data Output CHANNEL_DATA_WIDTH + + add_interface dac_ch_2 conduit end + add_interface_port dac_ch_2 dac_enable_2 enable Input 1 + add_interface_port dac_ch_2 dac_valid_2 valid Input 1 + add_interface_port dac_ch_2 dac_data_2 data Output CHANNEL_DATA_WIDTH + + set_interface_property dac_ch_2 associatedClock if_dac_clk } + if {[get_parameter_value NUM_OF_CHANNELS] > 3} { - add_interface fifo_ch_3 conduit end - #set_interface_property fifo_ch_3 associatedClock if_dac_clk - add_interface_port fifo_ch_3 dac_enable_3 enable Input 1 - add_interface_port fifo_ch_3 dac_valid_3 valid Input 1 -# add_interface_port fifo_ch_3 upack_valid_3 valid_o Output 1 - add_interface_port fifo_ch_3 dac_data_3 data Output CHANNEL_DATA_WIDTH + + add_interface dac_ch_3 conduit end + add_interface_port dac_ch_3 dac_enable_3 enable Input 1 + add_interface_port dac_ch_3 dac_valid_3 valid Input 1 + add_interface_port dac_ch_3 dac_data_3 data Output CHANNEL_DATA_WIDTH + + set_interface_property dac_ch_3 associatedClock if_dac_clk } + if {[get_parameter_value NUM_OF_CHANNELS] > 4} { - add_interface fifo_ch_4 conduit end - #set_interface_property fifo_ch_4 associatedClock if_dac_clk - add_interface_port fifo_ch_4 dac_enable_4 enable Input 1 - add_interface_port fifo_ch_4 dac_valid_4 valid Input 1 -# add_interface_port fifo_ch_4 upack_valid_4 valid_o Output 1 - add_interface_port fifo_ch_4 dac_data_4 data Output CHANNEL_DATA_WIDTH + + add_interface dac_ch_4 conduit end + add_interface_port dac_ch_4 dac_enable_4 enable Input 1 + add_interface_port dac_ch_4 dac_valid_4 valid Input 1 + add_interface_port dac_ch_4 dac_data_4 data Output CHANNEL_DATA_WIDTH + + set_interface_property dac_ch_4 associatedClock if_dac_clk } + if {[get_parameter_value NUM_OF_CHANNELS] > 5} { - add_interface fifo_ch_5 conduit end - #set_interface_property fifo_ch_5 associatedClock if_dac_clk - add_interface_port fifo_ch_5 dac_enable_5 enable Input 1 - add_interface_port fifo_ch_5 dac_valid_5 valid Input 1 -# add_interface_port fifo_ch_5 upack_valid_5 valid_o Output 1 - add_interface_port fifo_ch_5 dac_data_5 data Output CHANNEL_DATA_WIDTH + + add_interface dac_ch_5 conduit end + add_interface_port dac_ch_5 dac_enable_5 enable Input 1 + add_interface_port dac_ch_5 dac_valid_5 valid Input 1 + add_interface_port dac_ch_5 dac_data_5 data Output CHANNEL_DATA_WIDTH + + set_interface_property dac_ch_5 associatedClock if_dac_clk } + if {[get_parameter_value NUM_OF_CHANNELS] > 6} { - add_interface fifo_ch_6 conduit end - #set_interface_property fifo_ch_6 associatedClock if_dac_clk - add_interface_port fifo_ch_6 dac_enable_6 enable Input 1 - add_interface_port fifo_ch_6 dac_valid_6 valid Input 1 -# add_interface_port fifo_ch_6 upack_valid_6 valid_o Output 1 - add_interface_port fifo_ch_6 dac_data_6 data Output CHANNEL_DATA_WIDTH + + add_interface dac_ch_6 conduit end + add_interface_port dac_ch_6 dac_enable_6 enable Input 1 + add_interface_port dac_ch_6 dac_valid_6 valid Input 1 + add_interface_port dac_ch_6 dac_data_6 data Output CHANNEL_DATA_WIDTH + + set_interface_property dac_ch_6 associatedClock if_dac_clk } + if {[get_parameter_value NUM_OF_CHANNELS] > 7} { - add_interface fifo_ch_7 conduit end - #set_interface_property fifo_ch_7 associatedClock if_dac_clk - add_interface_port fifo_ch_7 dac_enable_7 enable Input 1 - add_interface_port fifo_ch_7 dac_valid_7 valid Input 1 -# add_interface_port fifo_ch_7 upack_valid_7 valid_o Output 1 - add_interface_port fifo_ch_7 dac_data_7 data Output CHANNEL_DATA_WIDTH + + add_interface dac_ch_7 conduit end + add_interface_port dac_ch_7 dac_enable_7 enable Input 1 + add_interface_port dac_ch_7 dac_valid_7 valid Input 1 + add_interface_port dac_ch_7 dac_data_7 data Output CHANNEL_DATA_WIDTH + + set_interface_property dac_ch_7 associatedClock if_dac_clk } } diff --git a/library/util_var_fifo/Makefile b/library/util_var_fifo/Makefile new file mode 100644 index 000000000..6b9b6b0c8 --- /dev/null +++ b/library/util_var_fifo/Makefile @@ -0,0 +1,47 @@ +#################################################################################### +#################################################################################### +## Copyright 2011(c) Analog Devices, Inc. +## Auto-generated, do not modify! +#################################################################################### +#################################################################################### + +M_DEPS += ../common/ad_mem.v +M_DEPS += ../scripts/adi_env.tcl +M_DEPS += ../scripts/adi_ip.tcl +M_DEPS += util_var_fifo.v +M_DEPS += util_var_fifo_ip.tcl + +M_VIVADO := vivado -mode batch -source + +M_FLIST := *.cache +M_FLIST += *.data +M_FLIST += *.xpr +M_FLIST += *.log +M_FLIST += component.xml +M_FLIST += *.jou +M_FLIST += xgui +M_FLIST += *.ip_user_files +M_FLIST += *.srcs +M_FLIST += *.hw +M_FLIST += *.sim +M_FLIST += .Xil + + + +.PHONY: all clean clean-all +all: util_var_fifo.xpr + + +clean:clean-all + + +clean-all: + rm -rf $(M_FLIST) + + +util_var_fifo.xpr: $(M_DEPS) + -rm -rf $(M_FLIST) + $(M_VIVADO) util_var_fifo_ip.tcl >> util_var_fifo_ip.log 2>&1 + +#################################################################################### +#################################################################################### diff --git a/library/util_var_fifo/util_var_fifo.v b/library/util_var_fifo/util_var_fifo.v new file mode 100644 index 000000000..cc6ad2dd9 --- /dev/null +++ b/library/util_var_fifo/util_var_fifo.v @@ -0,0 +1,134 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module util_var_fifo ( + + clk, + rst, + + depth, + + data_in, + data_in_valid, + + data_out, + data_out_valid + +); + + parameter DATA_WIDTH = 32; + parameter ADDRESS_WIDTH = 13; + + localparam MAX_DEPTH = (2 ** ADDRESS_WIDTH) - 1; + + input clk; + input rst; + + input [31:0] depth; + + input [DATA_WIDTH -1:0] data_in; + input data_in_valid; + + output [DATA_WIDTH-1:0] data_out; + output data_out_valid; + + // internal registers + + reg [ADDRESS_WIDTH-1:0] addra = 'd0; + reg [ADDRESS_WIDTH-1:0] addrb = 'd0; + + reg [31:0] depth_d1 = 'd0; + reg [31:0] data_in_d1 = 'd0; + reg [31:0] data_in_d2 = 'd0; + reg data_active = 'd0; + + // internal signals + + wire reset; + wire [31:0] depth; + wire [DATA_WIDTH-1:0] data_out_s; + wire data_out_valid_s; + + assign reset = ((rst == 1'b1) || (depth != depth_d1)) ? 1 : 0; + + assign data_out = (depth == 0) ? data_in_d2 : data_out_s; + assign data_out_valid_s = data_active & data_in_valid; + assign data_out_valid = (depth == 0) ? data_in_valid : data_out_valid_s; + + always @(posedge clk) begin + depth_d1 <= depth; + data_in_d1 <= data_in; + data_in_d2 <= data_in_d1; + end + + always @(posedge clk) begin + if(reset == 1'b1) begin + addra <= 0; + addrb <= 0; + data_active <= 1'b0; + end else begin + if (data_in_valid == 1'b1) begin + addra <= addra + 1; + if (data_active == 1'b1) begin + addrb <= addrb + 1; + end + end + if (addra >= depth || addra > MAX_DEPTH - 2) begin + data_active <= 1'b1; + end + end + end + + ad_mem #( + .DATA_WIDTH(DATA_WIDTH), + .ADDRESS_WIDTH(ADDRESS_WIDTH) + ) data_fifo ( + .clka(clk), + .wea(data_in_valid), + .addra(addra), + .dina(data_in), + + .clkb(clk), + .addrb(addrb), + .doutb(data_out_s)); + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/library/util_var_fifo/util_var_fifo_ip.tcl b/library/util_var_fifo/util_var_fifo_ip.tcl new file mode 100644 index 000000000..e9981a442 --- /dev/null +++ b/library/util_var_fifo/util_var_fifo_ip.tcl @@ -0,0 +1,16 @@ +# ip + +source ../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip.tcl + +adi_ip_create util_var_fifo +adi_ip_files util_var_fifo [list \ + "$ad_hdl_dir/library/common/ad_mem.v" \ + "util_var_fifo.v" ] + +adi_ip_properties_lite util_var_fifo + +ipx::remove_all_bus_interface [ipx::current_core] +ipx::save_core [ipx::current_core] + + diff --git a/library/util_wfifo/Makefile b/library/util_wfifo/Makefile index 0d6a5b2a5..b145a2fd0 100644 --- a/library/util_wfifo/Makefile +++ b/library/util_wfifo/Makefile @@ -5,11 +5,12 @@ #################################################################################### #################################################################################### -M_DEPS := util_wfifo_ip.tcl +M_DEPS += ../common/ad_mem.v M_DEPS += ../scripts/adi_env.tcl M_DEPS += ../scripts/adi_ip.tcl -M_DEPS += ../common/ad_mem.v M_DEPS += util_wfifo.v +M_DEPS += util_wfifo_constr.xdc +M_DEPS += util_wfifo_ip.tcl M_VIVADO := vivado -mode batch -source @@ -20,6 +21,10 @@ M_FLIST += *.log M_FLIST += component.xml M_FLIST += *.jou M_FLIST += xgui +M_FLIST += *.ip_user_files +M_FLIST += *.srcs +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil @@ -36,7 +41,7 @@ clean-all: util_wfifo.xpr: $(M_DEPS) - rm -rf $(M_FLIST) + -rm -rf $(M_FLIST) $(M_VIVADO) util_wfifo_ip.tcl >> util_wfifo_ip.log 2>&1 #################################################################################### diff --git a/library/util_wfifo/util_wfifo.v b/library/util_wfifo/util_wfifo.v index c2a2a7da4..ffcdefee6 100644 --- a/library/util_wfifo/util_wfifo.v +++ b/library/util_wfifo/util_wfifo.v @@ -34,10 +34,6 @@ // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // *************************************************************************** // *************************************************************************** -// allows conversions of clock/buswidth for adc/dac channels -// in all cases bandwidth requirements must be met (read >= write). -// *************************************************************************** -// *************************************************************************** `timescale 1ns/100ps @@ -183,27 +179,30 @@ module util_wfifo ( reg [ 2:0] din_dcnt = 'd0; reg din_wr = 'd0; reg [(ADDRESS_WIDTH-1):0] din_waddr = 'd0; - reg din_waddr_rel_t = 'd0; - reg [(ADDRESS_WIDTH-1):0] din_waddr_rel = 'd0; - reg [ 2:0] din_ovf_m = 'd0; + reg din_req_t = 'd0; + reg [(ADDRESS_WIDTH-4):0] din_rinit = 'd0; + reg din_ovf_m1 = 'd0; reg din_ovf = 'd0; - reg [ 2:0] dout_waddr_rel_t_m = 'd0; - reg [(ADDRESS_WIDTH-1):0] dout_waddr_rel = 'd0; - reg dout_ovf_int = 'd0; - reg [ 7:0] dout_enable_m = 'd0; - reg [ 7:0] dout_enable = 'd0; - reg dout_rd = 'd0; - reg dout_rd_d = 'd0; - reg [(DATA_WIDTH-1):0] dout_rdata_d = 'd0; + reg dout_req_t_m1 = 'd0; + reg dout_req_t_m2 = 'd0; + reg dout_req_t_m3 = 'd0; + reg dout_req_t = 'd0; + reg [(ADDRESS_WIDTH-4):0] dout_rinit = 'd0; + reg dout_ovf_d = 'd0; + reg [ 3:0] dout_req_cnt = 'd0; reg [(ADDRESS_WIDTH-1):0] dout_raddr = 'd0; + reg dout_rd_d = 'd0; + reg dout_valid = 'd0; + reg [ 7:0] dout_enable_m1 = 'd0; + reg [ 7:0] dout_enable = 'd0; + reg [(DATA_WIDTH-1):0] dout_rdata = 'd0; // internal signals wire [ 7:0] din_enable_s; wire [ 7:0] din_valid_s; wire [(T_DIN_DATA_WIDTH-1):0] din_data_s; - wire dout_waddr_rel_t_s; - wire dout_rd_s; + wire dout_req_t_s; wire [(DATA_WIDTH-1):0] dout_rdata_s; wire [(T_DOUT_DATA_WIDTH+1):0] dout_data_s; @@ -220,7 +219,8 @@ module util_wfifo ( assign din_data_s = { din_data_7, din_data_6, din_data_5, din_data_4, din_data_3, din_data_2, din_data_1, din_data_0}; - // dout_width >= din_width only + // simple data transfer-- no ovf/unf handling- read-bw > write-bw (equal will NOT work) + // dout_width >= din_width only- generate for (n = 0; n < NUM_OF_CHANNELS; n = n + 1) begin: g_in @@ -248,10 +248,10 @@ module util_wfifo ( din_enable <= 8'd0; din_dcnt <= 3'd0; din_wr <= 1'd0; - din_waddr <= 5'd0; - din_waddr_rel_t <= 1'd0; - din_waddr_rel <= 5'd0; - din_ovf_m <= 'd0; + din_waddr <= 'd0; + din_req_t <= 1'd0; + din_rinit <= 'd0; + din_ovf_m1 <= 'd0; din_ovf <= 'd0; end else begin din_enable <= din_enable_s; @@ -267,96 +267,111 @@ module util_wfifo ( if (din_wr == 1'b1) begin din_waddr <= din_waddr + 1'b1; end - if ((din_wr == 1'b1) && (din_waddr[2:0] == 3'd0)) begin - din_waddr_rel_t <= ~din_waddr_rel_t; - din_waddr_rel <= din_waddr; + if ((din_wr == 1'b1) && (din_waddr[2:0] == 3'd7)) begin + din_req_t <= ~din_req_t; + din_rinit <= din_waddr[(ADDRESS_WIDTH-1):3]; end - din_ovf_m <= {din_ovf_m[1:0], dout_ovf_int}; - din_ovf <= din_ovf_m[2]; + din_ovf_m1 <= dout_ovf_d; + din_ovf <= din_ovf_m1; end end // read interface (bus expansion and/or clock conversion) - assign dout_waddr_rel_t_s = dout_waddr_rel_t_m[2] ^ dout_waddr_rel_t_m[1]; + assign dout_req_t_s = dout_req_t_m3 ^ dout_req_t_m2; always @(posedge dout_clk or negedge dout_rstn) begin if (dout_rstn == 1'b0) begin - dout_waddr_rel_t_m <= 3'd0; - dout_waddr_rel <= 'd0; - dout_ovf_int <= 1'b1; + dout_req_t_m1 <= 'd0; + dout_req_t_m2 <= 'd0; + dout_req_t_m3 <= 'd0; + dout_req_t <= 'd0; + dout_rinit <= 'd0; + dout_ovf_d <= 'd0; end else begin - dout_waddr_rel_t_m <= {dout_waddr_rel_t_m[1:0], din_waddr_rel_t}; - if (dout_waddr_rel_t_s == 1'b1) begin - dout_waddr_rel <= din_waddr_rel; - if (dout_raddr == dout_waddr_rel) begin - dout_ovf_int <= dout_ovf; - end else begin - dout_ovf_int <= 1'b1; - end + dout_req_t_m1 <= din_req_t; + dout_req_t_m2 <= dout_req_t_m1; + dout_req_t_m3 <= dout_req_t_m2; + dout_req_t <= dout_req_t_s; + if (dout_req_t_s == 1'b1) begin + dout_rinit <= din_rinit; end + dout_ovf_d <= dout_ovf; end end - assign dout_rd_s = (dout_raddr == dout_waddr_rel) ? 1'b0 : 1'b1; - assign dout_data_s[(T_DOUT_DATA_WIDTH+1):DATA_WIDTH] = 'd0; - assign dout_data_s[(DATA_WIDTH-1):0] = dout_rdata_d; + always @(posedge dout_clk or negedge dout_rstn) begin + if (dout_rstn == 1'b0) begin + dout_req_cnt <= 'd0; + dout_raddr <= 'd8; + dout_rd_d <= 'd0; + dout_valid <= 'd0; + end else begin + if (dout_req_t == 1'b1) begin + dout_req_cnt <= 4'h8; + dout_raddr <= {dout_rinit, 3'd0}; + end else if (dout_req_cnt[3] == 1'b1) begin + dout_req_cnt <= dout_req_cnt + 1'b1; + dout_raddr <= dout_raddr + 1'b1; + end + dout_rd_d <= dout_req_cnt[3]; + dout_valid <= dout_rd_d; + end + end always @(posedge dout_clk or negedge dout_rstn) begin if (dout_rstn == 1'b0) begin - dout_enable_m <= 'd0; + dout_enable_m1 <= 'd0; dout_enable <= 'd0; end else begin - dout_enable_m <= din_enable; - dout_enable <= dout_enable_m; + dout_enable_m1 <= din_enable; + dout_enable <= dout_enable_m1; end end always @(posedge dout_clk) begin - dout_rdata_d <= dout_rdata_s; - if (dout_rstn == 1'b0) begin - dout_rd <= 'd0; - dout_rd_d <= 'd0; - dout_raddr <= 'd0; - end else begin - dout_rd <= dout_rd_s; - dout_rd_d <= dout_rd; - if (dout_rd_s == 1'b1) begin - dout_raddr <= dout_raddr + 1'b1; - end - end + dout_rdata <= dout_rdata_s; end + generate + if (NUM_OF_CHANNELS >= 8) begin + assign dout_data_s = dout_rdata; + end else begin + assign dout_data_s[(T_DOUT_DATA_WIDTH+1):DATA_WIDTH] = 'd0; + assign dout_data_s[(DATA_WIDTH-1):0] = dout_rdata; + end + endgenerate + assign dout_enable_7 = dout_enable[7]; - assign dout_valid_7 = dout_rd_d; + assign dout_valid_7 = dout_valid; assign dout_data_7 = dout_data_s[((DOUT_DATA_WIDTH*8)-1):(DOUT_DATA_WIDTH*7)]; assign dout_enable_6 = dout_enable[6]; - assign dout_valid_6 = dout_rd_d; + assign dout_valid_6 = dout_valid; assign dout_data_6 = dout_data_s[((DOUT_DATA_WIDTH*7)-1):(DOUT_DATA_WIDTH*6)]; assign dout_enable_5 = dout_enable[5]; - assign dout_valid_5 = dout_rd_d; + assign dout_valid_5 = dout_valid; assign dout_data_5 = dout_data_s[((DOUT_DATA_WIDTH*6)-1):(DOUT_DATA_WIDTH*5)]; assign dout_enable_4 = dout_enable[4]; - assign dout_valid_4 = dout_rd_d; + assign dout_valid_4 = dout_valid; assign dout_data_4 = dout_data_s[((DOUT_DATA_WIDTH*5)-1):(DOUT_DATA_WIDTH*4)]; assign dout_enable_3 = dout_enable[3]; - assign dout_valid_3 = dout_rd_d; + assign dout_valid_3 = dout_valid; assign dout_data_3 = dout_data_s[((DOUT_DATA_WIDTH*4)-1):(DOUT_DATA_WIDTH*3)]; assign dout_enable_2 = dout_enable[2]; - assign dout_valid_2 = dout_rd_d; + assign dout_valid_2 = dout_valid; assign dout_data_2 = dout_data_s[((DOUT_DATA_WIDTH*3)-1):(DOUT_DATA_WIDTH*2)]; assign dout_enable_1 = dout_enable[1]; - assign dout_valid_1 = dout_rd_d; + assign dout_valid_1 = dout_valid; assign dout_data_1 = dout_data_s[((DOUT_DATA_WIDTH*2)-1):(DOUT_DATA_WIDTH*1)]; assign dout_enable_0 = dout_enable[0]; - assign dout_valid_0 = dout_rd_d; + assign dout_valid_0 = dout_valid; assign dout_data_0 = dout_data_s[((DOUT_DATA_WIDTH*1)-1):(DOUT_DATA_WIDTH*0)]; // instantiations diff --git a/library/util_wfifo/util_wfifo_constr.sdc b/library/util_wfifo/util_wfifo_constr.sdc new file mode 100644 index 000000000..b3226e083 --- /dev/null +++ b/library/util_wfifo/util_wfifo_constr.sdc @@ -0,0 +1,6 @@ + +set_false_path -from [get_registers *din_enable*] -to [get_registers *dout_enable_m1*] +set_false_path -from [get_registers *din_req_t*] -to [get_registers *dout_req_t_m1*] +set_false_path -from [get_registers *din_rinit*] -to [get_registers *dout_rinit*] +set_false_path -from [get_registers *dout_ovf_d*] -to [get_registers *din_ovf_m1*] + diff --git a/library/util_wfifo/util_wfifo_constr.xdc b/library/util_wfifo/util_wfifo_constr.xdc index 064dfaf99..dc52b3271 100644 --- a/library/util_wfifo/util_wfifo_constr.xdc +++ b/library/util_wfifo/util_wfifo_constr.xdc @@ -1,15 +1,10 @@ -set_property SHREG_EXTRACT NO [get_cells -hier *din_ovf_m*] -set_property SHREG_EXTRACT NO [get_cells -hier *dout_waddr_rel_t_m*] -set_property SHREG_EXTRACT NO [get_cells -hier *dout_enable_m*] +set_property shreg_extract no [get_cells -hier -filter {name =~ *dout_enable_m*}] +set_property shreg_extract no [get_cells -hier -filter {name =~ *dout_req_t_m*}] +set_property shreg_extract no [get_cells -hier -filter {name =~ *din_ovf_m*}] -set_false_path -from [get_cells -hier *dout_ovf_int* -filter {primitive_subgroup == flop}] \ - -to [get_cells -hier *din_ovf_m* -filter {primitive_subgroup == flop}] -set_false_path -from [get_cells -hier *din_waddr_rel_t* -filter {primitive_subgroup == flop}] \ - -to [get_cells -hier *dout_waddr_rel_t_m* -filter {primitive_subgroup == flop}] -set_false_path -from [get_cells -hier *din_enable* -filter {primitive_subgroup == flop}] \ - -to [get_cells -hier *dout_enable_m* -filter {primitive_subgroup == flop}] - -set_max_delay -datapath_only -from [get_cells -hier *din_waddr_rel* -filter {primitive_subgroup == flop}] \ - -to [get_cells -hier *dout_waddr_rel* -filter {primitive_subgroup == flop}] 8 +set_false_path -from [get_cells -hier -filter {name =~ *din_enable* && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *dout_enable_m1* && IS_SEQUENTIAL}] +set_false_path -from [get_cells -hier -filter {name =~ *din_req_t* && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *dout_req_t_m1* && IS_SEQUENTIAL}] +set_false_path -from [get_cells -hier -filter {name =~ *din_rinit* && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *dout_rinit* && IS_SEQUENTIAL}] +set_false_path -from [get_cells -hier -filter {name =~ *dout_ovf* && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *din_ovf_m1* && IS_SEQUENTIAL}] diff --git a/library/util_wfifo/util_wfifo_hw.tcl b/library/util_wfifo/util_wfifo_hw.tcl new file mode 100755 index 000000000..c6468f132 --- /dev/null +++ b/library/util_wfifo/util_wfifo_hw.tcl @@ -0,0 +1,215 @@ + + +package require -exact qsys 13.0 +source ../scripts/adi_env.tcl +source ../scripts/adi_ip_alt.tcl + +set_module_property NAME util_wfifo +set_module_property DESCRIPTION "Utils Write FIFO" +set_module_property VERSION 1.0 +set_module_property GROUP "Analog Devices" +set_module_property DISPLAY_NAME util_wfifo +set_module_property ELABORATION_CALLBACK p_util_wfifo + +# files + +add_fileset quartus_synth QUARTUS_SYNTH "" "" +set_fileset_property quartus_synth TOP_LEVEL util_wfifo +add_fileset_file ad_mem.v VERILOG PATH $ad_hdl_dir/library/common/ad_mem.v +add_fileset_file util_wfifo.v VERILOG PATH util_wfifo.v TOP_LEVEL_FILE +add_fileset_file util_wfifo_constr.sdc SDC PATH util_wfifo_constr.sdc + +# parameters + +add_parameter NUM_OF_CHANNELS INTEGER 0 +set_parameter_property NUM_OF_CHANNELS DEFAULT_VALUE 4 +set_parameter_property NUM_OF_CHANNELS DISPLAY_NAME NUM_OF_CHANNELS +set_parameter_property NUM_OF_CHANNELS TYPE INTEGER +set_parameter_property NUM_OF_CHANNELS UNITS None +set_parameter_property NUM_OF_CHANNELS HDL_PARAMETER true + +add_parameter DIN_DATA_WIDTH INTEGER 0 +set_parameter_property DIN_DATA_WIDTH DEFAULT_VALUE 32 +set_parameter_property DIN_DATA_WIDTH DISPLAY_NAME DIN_DATA_WIDTH +set_parameter_property DIN_DATA_WIDTH TYPE INTEGER +set_parameter_property DIN_DATA_WIDTH UNITS None +set_parameter_property DIN_DATA_WIDTH HDL_PARAMETER true + +add_parameter DOUT_DATA_WIDTH INTEGER 0 +set_parameter_property DOUT_DATA_WIDTH DEFAULT_VALUE 64 +set_parameter_property DOUT_DATA_WIDTH DISPLAY_NAME DOUT_DATA_WIDTH +set_parameter_property DOUT_DATA_WIDTH TYPE INTEGER +set_parameter_property DOUT_DATA_WIDTH UNITS None +set_parameter_property DOUT_DATA_WIDTH HDL_PARAMETER true + +add_parameter DIN_ADDRESS_WIDTH INTEGER 0 +set_parameter_property DIN_ADDRESS_WIDTH DEFAULT_VALUE 8 +set_parameter_property DIN_ADDRESS_WIDTH DISPLAY_NAME DIN_ADDRESS_WIDTH +set_parameter_property DIN_ADDRESS_WIDTH TYPE INTEGER +set_parameter_property DIN_ADDRESS_WIDTH UNITS None +set_parameter_property DIN_ADDRESS_WIDTH HDL_PARAMETER true + +# defaults + +ad_alt_intf clock din_clk input 1 +ad_alt_intf reset din_rst input 1 if_din_clk + +ad_alt_intf clock dout_clk input 1 +ad_alt_intf reset-n dout_rstn input 1 if_dout_clk + +add_interface din_0 conduit end +add_interface_port din_0 din_enable_0 enable Input 1 +add_interface_port din_0 din_valid_0 valid Input 1 +add_interface_port din_0 din_data_0 data Input DIN_DATA_WIDTH + +set_interface_property din_0 associatedClock if_din_clk +set_interface_property din_0 associatedReset none + +add_interface dout_0 conduit end +add_interface_port dout_0 dout_enable_0 enable Output 1 +add_interface_port dout_0 dout_valid_0 valid Output 1 +add_interface_port dout_0 dout_data_0 data Output DOUT_DATA_WIDTH + +set_interface_property dout_0 associatedClock if_dout_clk +set_interface_property dout_0 associatedReset none + +ad_alt_intf signal din_ovf output 1 ovf +ad_alt_intf signal dout_ovf input 1 ovf + +proc p_util_wfifo {} { + + if {[get_parameter_value NUM_OF_CHANNELS] > 1} { + + add_interface din_1 conduit end + add_interface_port din_1 din_enable_1 enable Input 1 + add_interface_port din_1 din_valid_1 valid Input 1 + add_interface_port din_1 din_data_1 data Input DIN_DATA_WIDTH + + set_interface_property din_1 associatedClock if_din_clk + set_interface_property din_1 associatedReset none + + add_interface dout_1 conduit end + add_interface_port dout_1 dout_enable_1 enable Output 1 + add_interface_port dout_1 dout_valid_1 valid Output 1 + add_interface_port dout_1 dout_data_1 data Output DOUT_DATA_WIDTH + + set_interface_property dout_1 associatedClock if_dout_clk + set_interface_property dout_1 associatedReset none + } + + if {[get_parameter_value NUM_OF_CHANNELS] > 2} { + + add_interface din_2 conduit end + add_interface_port din_2 din_enable_2 enable Input 1 + add_interface_port din_2 din_valid_2 valid Input 1 + add_interface_port din_2 din_data_2 data Input DIN_DATA_WIDTH + + set_interface_property din_2 associatedClock if_din_clk + set_interface_property din_2 associatedReset none + + add_interface dout_2 conduit end + add_interface_port dout_2 dout_enable_2 enable Output 1 + add_interface_port dout_2 dout_valid_2 valid Output 1 + add_interface_port dout_2 dout_data_2 data Output DOUT_DATA_WIDTH + + set_interface_property dout_2 associatedClock if_dout_clk + set_interface_property dout_2 associatedReset none + } + + if {[get_parameter_value NUM_OF_CHANNELS] > 3} { + + add_interface din_3 conduit end + add_interface_port din_3 din_enable_3 enable Input 1 + add_interface_port din_3 din_valid_3 valid Input 1 + add_interface_port din_3 din_data_3 data Input DIN_DATA_WIDTH + + set_interface_property din_3 associatedClock if_din_clk + set_interface_property din_3 associatedReset none + + add_interface dout_3 conduit end + add_interface_port dout_3 dout_enable_3 enable Output 1 + add_interface_port dout_3 dout_valid_3 valid Output 1 + add_interface_port dout_3 dout_data_3 data Output DOUT_DATA_WIDTH + + set_interface_property dout_3 associatedClock if_dout_clk + set_interface_property dout_3 associatedReset none + } + + if {[get_parameter_value NUM_OF_CHANNELS] > 4} { + + add_interface din_4 conduit end + add_interface_port din_4 din_enable_4 enable Input 1 + add_interface_port din_4 din_valid_4 valid Input 1 + add_interface_port din_4 din_data_4 data Input DIN_DATA_WIDTH + + set_interface_property din_4 associatedClock if_din_clk + set_interface_property din_4 associatedReset none + + add_interface dout_4 conduit end + add_interface_port dout_4 dout_enable_4 enable Output 1 + add_interface_port dout_4 dout_valid_4 valid Output 1 + add_interface_port dout_4 dout_data_4 data Output DOUT_DATA_WIDTH + + set_interface_property dout_4 associatedClock if_dout_clk + set_interface_property dout_4 associatedReset none + } + + if {[get_parameter_value NUM_OF_CHANNELS] > 5} { + + add_interface din_5 conduit end + add_interface_port din_5 din_enable_5 enable Input 1 + add_interface_port din_5 din_valid_5 valid Input 1 + add_interface_port din_5 din_data_5 data Input DIN_DATA_WIDTH + + set_interface_property din_5 associatedClock if_din_clk + set_interface_property din_5 associatedReset none + + add_interface dout_5 conduit end + add_interface_port dout_5 dout_enable_5 enable Output 1 + add_interface_port dout_5 dout_valid_5 valid Output 1 + add_interface_port dout_5 dout_data_5 data Output DOUT_DATA_WIDTH + + set_interface_property dout_5 associatedClock if_dout_clk + set_interface_property dout_5 associatedReset none + } + + if {[get_parameter_value NUM_OF_CHANNELS] > 6} { + + add_interface din_6 conduit end + add_interface_port din_6 din_enable_6 enable Input 1 + add_interface_port din_6 din_valid_6 valid Input 1 + add_interface_port din_6 din_data_6 data Input DIN_DATA_WIDTH + + set_interface_property din_6 associatedClock if_din_clk + set_interface_property din_6 associatedReset none + + add_interface dout_6 conduit end + add_interface_port dout_6 dout_enable_6 enable Output 1 + add_interface_port dout_6 dout_valid_6 valid Output 1 + add_interface_port dout_6 dout_data_6 data Output DOUT_DATA_WIDTH + + set_interface_property dout_6 associatedClock if_dout_clk + set_interface_property dout_6 associatedReset none + } + + if {[get_parameter_value NUM_OF_CHANNELS] > 7} { + + add_interface din_7 conduit end + add_interface_port din_7 din_enable_7 enable Input 1 + add_interface_port din_7 din_valid_7 valid Input 1 + add_interface_port din_7 din_data_7 data Input DIN_DATA_WIDTH + + set_interface_property din_7 associatedClock if_din_clk + set_interface_property din_7 associatedReset none + + add_interface dout_7 conduit end + add_interface_port dout_7 dout_enable_7 enable Output 1 + add_interface_port dout_7 dout_valid_7 valid Output 1 + add_interface_port dout_7 dout_data_7 data Output DOUT_DATA_WIDTH + + set_interface_property dout_7 associatedClock if_dout_clk + set_interface_property dout_7 associatedReset none + } + +} + diff --git a/library/axi_adcfifo/Makefile b/library/xilinx/axi_adcfifo/Makefile similarity index 76% rename from library/axi_adcfifo/Makefile rename to library/xilinx/axi_adcfifo/Makefile index 91db65830..0d957670f 100644 --- a/library/axi_adcfifo/Makefile +++ b/library/xilinx/axi_adcfifo/Makefile @@ -5,19 +5,19 @@ #################################################################################### #################################################################################### -M_DEPS := axi_adcfifo_ip.tcl -M_DEPS += ../scripts/adi_env.tcl -M_DEPS += ../scripts/adi_ip.tcl -M_DEPS += ../common/ad_mem.v -M_DEPS += ../common/ad_mem_asym.v -M_DEPS += ../common/up_xfer_status.v -M_DEPS += ../common/ad_axis_inf_rx.v -M_DEPS += axi_adcfifo_adc.v -M_DEPS += axi_adcfifo_dma.v -M_DEPS += axi_adcfifo_wr.v -M_DEPS += axi_adcfifo_rd.v +M_DEPS += ../../common/ad_axis_inf_rx.v +M_DEPS += ../../common/ad_mem.v +M_DEPS += ../../common/ad_mem_asym.v +M_DEPS += ../../common/up_xfer_status.v +M_DEPS += ../../scripts/adi_env.tcl +M_DEPS += ../../scripts/adi_ip.tcl M_DEPS += axi_adcfifo.v +M_DEPS += axi_adcfifo_adc.v M_DEPS += axi_adcfifo_constr.xdc +M_DEPS += axi_adcfifo_dma.v +M_DEPS += axi_adcfifo_ip.tcl +M_DEPS += axi_adcfifo_rd.v +M_DEPS += axi_adcfifo_wr.v M_VIVADO := vivado -mode batch -source @@ -28,6 +28,10 @@ M_FLIST += *.log M_FLIST += component.xml M_FLIST += *.jou M_FLIST += xgui +M_FLIST += *.ip_user_files +M_FLIST += *.srcs +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil @@ -44,7 +48,7 @@ clean-all: axi_adcfifo.xpr: $(M_DEPS) - rm -rf $(M_FLIST) + -rm -rf $(M_FLIST) $(M_VIVADO) axi_adcfifo_ip.tcl >> axi_adcfifo_ip.log 2>&1 #################################################################################### diff --git a/library/axi_adcfifo/axi_adcfifo.v b/library/xilinx/axi_adcfifo/axi_adcfifo.v similarity index 99% rename from library/axi_adcfifo/axi_adcfifo.v rename to library/xilinx/axi_adcfifo/axi_adcfifo.v index 99b1f2a1b..831ff4c33 100644 --- a/library/axi_adcfifo/axi_adcfifo.v +++ b/library/xilinx/axi_adcfifo/axi_adcfifo.v @@ -115,7 +115,6 @@ module axi_adcfifo ( parameter AXI_LENGTH = 16; parameter AXI_ADDRESS = 32'h00000000; parameter AXI_ADDRESS_LIMIT = 32'hffffffff; - parameter AXI_BYTE_WIDTH = AXI_DATA_WIDTH/8; // adc interface @@ -152,7 +151,7 @@ module axi_adcfifo ( input axi_awready; output axi_wvalid; output [AXI_DATA_WIDTH-1:0] axi_wdata; - output [AXI_BYTE_WIDTH-1:0] axi_wstrb; + output [(AXI_DATA_WIDTH/8)-1:0] axi_wstrb; output axi_wlast; output [ 3:0] axi_wuser; input axi_wready; diff --git a/library/axi_adcfifo/axi_adcfifo_adc.v b/library/xilinx/axi_adcfifo/axi_adcfifo_adc.v similarity index 100% rename from library/axi_adcfifo/axi_adcfifo_adc.v rename to library/xilinx/axi_adcfifo/axi_adcfifo_adc.v diff --git a/library/axi_adcfifo/axi_adcfifo_constr.xdc b/library/xilinx/axi_adcfifo/axi_adcfifo_constr.xdc similarity index 100% rename from library/axi_adcfifo/axi_adcfifo_constr.xdc rename to library/xilinx/axi_adcfifo/axi_adcfifo_constr.xdc diff --git a/library/axi_adcfifo/axi_adcfifo_dma.v b/library/xilinx/axi_adcfifo/axi_adcfifo_dma.v similarity index 100% rename from library/axi_adcfifo/axi_adcfifo_dma.v rename to library/xilinx/axi_adcfifo/axi_adcfifo_dma.v diff --git a/library/xilinx/axi_adcfifo/axi_adcfifo_ip.tcl b/library/xilinx/axi_adcfifo/axi_adcfifo_ip.tcl new file mode 100644 index 000000000..cfce4030d --- /dev/null +++ b/library/xilinx/axi_adcfifo/axi_adcfifo_ip.tcl @@ -0,0 +1,85 @@ +# ip + +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip.tcl + +adi_ip_create axi_adcfifo +adi_ip_files axi_adcfifo [list \ + "$ad_hdl_dir/library/common/ad_mem.v" \ + "$ad_hdl_dir/library/common/ad_mem_asym.v" \ + "$ad_hdl_dir/library/common/up_xfer_status.v" \ + "$ad_hdl_dir/library/common/ad_axis_inf_rx.v" \ + "axi_adcfifo_adc.v" \ + "axi_adcfifo_dma.v" \ + "axi_adcfifo_wr.v" \ + "axi_adcfifo_rd.v" \ + "axi_adcfifo.v" \ + "axi_adcfifo_constr.xdc" ] + +adi_ip_properties_lite axi_adcfifo +adi_ip_constraints axi_adcfifo [list \ + "axi_adcfifo_constr.xdc" ] + +ipx::infer_bus_interface {\ + axi_awvalid \ + axi_awid \ + axi_awburst \ + axi_awlock \ + axi_awcache \ + axi_awprot \ + axi_awqos \ + axi_awuser \ + axi_awlen \ + axi_awsize \ + axi_awaddr \ + axi_awready \ + axi_wvalid \ + axi_wdata \ + axi_wstrb \ + axi_wlast \ + axi_wuser \ + axi_wready \ + axi_bvalid \ + axi_bid \ + axi_bresp \ + axi_buser \ + axi_bready \ + axi_arvalid \ + axi_arid \ + axi_arburst \ + axi_arlock \ + axi_arcache \ + axi_arprot \ + axi_arqos \ + axi_aruser \ + axi_arlen \ + axi_arsize \ + axi_araddr \ + axi_arready \ + axi_rvalid \ + axi_rid \ + axi_ruser \ + axi_rresp \ + axi_rlast \ + axi_rdata \ + axi_rready} \ +xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] + +ipx::infer_bus_interface axi_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] +ipx::infer_bus_interface axi_resetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] +ipx::add_bus_parameter ASSOCIATED_BUSIF [ipx::get_bus_interfaces axi_clk \ + -of_objects [ipx::current_core]] +set_property value axi [ipx::get_bus_parameters ASSOCIATED_BUSIF \ + -of_objects [ipx::get_bus_interfaces axi_clk \ + -of_objects [ipx::current_core]]] + +ipx::add_address_space axi [ipx::current_core] +set_property master_address_space_ref axi [ipx::get_bus_interfaces axi \ + -of_objects [ipx::current_core]] +set_property range 4294967296 [ipx::get_address_spaces axi \ + -of_objects [ipx::current_core]] +set_property width 512 [ipx::get_address_spaces axi \ + -of_objects [ipx::current_core]] + +ipx::save_core [ipx::current_core] + diff --git a/library/axi_adcfifo/axi_adcfifo_rd.v b/library/xilinx/axi_adcfifo/axi_adcfifo_rd.v similarity index 100% rename from library/axi_adcfifo/axi_adcfifo_rd.v rename to library/xilinx/axi_adcfifo/axi_adcfifo_rd.v diff --git a/library/axi_adcfifo/axi_adcfifo_wr.v b/library/xilinx/axi_adcfifo/axi_adcfifo_wr.v similarity index 100% rename from library/axi_adcfifo/axi_adcfifo_wr.v rename to library/xilinx/axi_adcfifo/axi_adcfifo_wr.v diff --git a/library/util_gtlb/Makefile b/library/xilinx/axi_adxcvr/Makefile similarity index 56% rename from library/util_gtlb/Makefile rename to library/xilinx/axi_adxcvr/Makefile index 8dc22b792..c0c41eac9 100644 --- a/library/util_gtlb/Makefile +++ b/library/xilinx/axi_adxcvr/Makefile @@ -5,20 +5,20 @@ #################################################################################### #################################################################################### -M_DEPS := util_gtlb_ip.tcl -M_DEPS += ../scripts/adi_env.tcl -M_DEPS += ../scripts/adi_ip.tcl -M_DEPS += ../common/up_xfer_status.v -M_DEPS += util_gtlb_constr.xdc -M_DEPS += util_gtlb.v -M_DEPS += ../interfaces/if_gt_qpll.xml -M_DEPS += ../interfaces/if_gt_qpll_rtl.xml -M_DEPS += ../interfaces/if_gt_pll.xml -M_DEPS += ../interfaces/if_gt_pll_rtl.xml -M_DEPS += ../interfaces/if_gt_rx.xml -M_DEPS += ../interfaces/if_gt_rx_rtl.xml -M_DEPS += ../interfaces/if_gt_tx.xml -M_DEPS += ../interfaces/if_gt_tx_rtl.xml +M_DEPS += ../../common/up_axi.v +M_DEPS += ../../scripts/adi_env.tcl +M_DEPS += ../../scripts/adi_ip.tcl +M_DEPS += axi_adxcvr.v +M_DEPS += axi_adxcvr_es.v +M_DEPS += axi_adxcvr_ip.tcl +M_DEPS += axi_adxcvr_mdrp.v +M_DEPS += axi_adxcvr_mstatus.v +M_DEPS += axi_adxcvr_up.v + +M_DEPS += ../../interfaces/if_xcvr_ch.xml +M_DEPS += ../../interfaces/if_xcvr_ch_rtl.xml +M_DEPS += ../../interfaces/if_xcvr_cm.xml +M_DEPS += ../../interfaces/if_xcvr_cm_rtl.xml M_VIVADO := vivado -mode batch -source @@ -29,12 +29,16 @@ M_FLIST += *.log M_FLIST += component.xml M_FLIST += *.jou M_FLIST += xgui +M_FLIST += *.ip_user_files +M_FLIST += *.srcs +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil .PHONY: all dep clean clean-all -all: dep util_gtlb.xpr +all: dep axi_adxcvr.xpr clean:clean-all @@ -44,11 +48,11 @@ clean-all: rm -rf $(M_FLIST) -util_gtlb.xpr: $(M_DEPS) - rm -rf $(M_FLIST) - $(M_VIVADO) util_gtlb_ip.tcl >> util_gtlb_ip.log 2>&1 +axi_adxcvr.xpr: $(M_DEPS) + -rm -rf $(M_FLIST) + $(M_VIVADO) axi_adxcvr_ip.tcl >> axi_adxcvr_ip.log 2>&1 dep: - make -C ../interfaces + make -C ../../interfaces #################################################################################### #################################################################################### diff --git a/library/xilinx/axi_adxcvr/axi_adxcvr.v b/library/xilinx/axi_adxcvr/axi_adxcvr.v new file mode 100644 index 000000000..98e2b5a92 --- /dev/null +++ b/library/xilinx/axi_adxcvr/axi_adxcvr.v @@ -0,0 +1,1884 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// AUTO GENERATED BY axi_adxcvr.pl, DO NOT MODIFY! + +`timescale 1ns/1ps + +module axi_adxcvr #( + + // parameters + + parameter integer ID = 0, + parameter integer NUM_OF_LANES = 8, + parameter integer GTH_OR_GTX_N = 0, + parameter integer TX_OR_RX_N = 0, + parameter integer QPLL_ENABLE = 1, + parameter LPM_OR_DFE_N = 1, + parameter [ 2:0] RATE = 3'd0, + parameter [ 1:0] SYS_CLK_SEL = 2'd3, + parameter [ 2:0] OUT_CLK_SEL = 3'd4) ( + + output [ 7:0] up_cm_sel_0, + output up_cm_enb_0, + output [11:0] up_cm_addr_0, + output up_cm_wr_0, + output [15:0] up_cm_wdata_0, + input [15:0] up_cm_rdata_0, + input up_cm_ready_0, + + output [ 7:0] up_es_sel_0, + output up_es_enb_0, + output [11:0] up_es_addr_0, + output up_es_wr_0, + output [15:0] up_es_wdata_0, + input [15:0] up_es_rdata_0, + input up_es_ready_0, + + input up_ch_pll_locked_0, + output up_ch_rst_0, + output up_ch_user_ready_0, + input up_ch_rst_done_0, + output up_ch_lpm_dfe_n_0, + output [ 2:0] up_ch_rate_0, + output [ 1:0] up_ch_sys_clk_sel_0, + output [ 2:0] up_ch_out_clk_sel_0, + output [ 7:0] up_ch_sel_0, + output up_ch_enb_0, + output [11:0] up_ch_addr_0, + output up_ch_wr_0, + output [15:0] up_ch_wdata_0, + input [15:0] up_ch_rdata_0, + input up_ch_ready_0, + + output [ 7:0] up_es_sel_1, + output up_es_enb_1, + output [11:0] up_es_addr_1, + output up_es_wr_1, + output [15:0] up_es_wdata_1, + input [15:0] up_es_rdata_1, + input up_es_ready_1, + + input up_ch_pll_locked_1, + output up_ch_rst_1, + output up_ch_user_ready_1, + input up_ch_rst_done_1, + output up_ch_lpm_dfe_n_1, + output [ 2:0] up_ch_rate_1, + output [ 1:0] up_ch_sys_clk_sel_1, + output [ 2:0] up_ch_out_clk_sel_1, + output [ 7:0] up_ch_sel_1, + output up_ch_enb_1, + output [11:0] up_ch_addr_1, + output up_ch_wr_1, + output [15:0] up_ch_wdata_1, + input [15:0] up_ch_rdata_1, + input up_ch_ready_1, + + output [ 7:0] up_es_sel_2, + output up_es_enb_2, + output [11:0] up_es_addr_2, + output up_es_wr_2, + output [15:0] up_es_wdata_2, + input [15:0] up_es_rdata_2, + input up_es_ready_2, + + input up_ch_pll_locked_2, + output up_ch_rst_2, + output up_ch_user_ready_2, + input up_ch_rst_done_2, + output up_ch_lpm_dfe_n_2, + output [ 2:0] up_ch_rate_2, + output [ 1:0] up_ch_sys_clk_sel_2, + output [ 2:0] up_ch_out_clk_sel_2, + output [ 7:0] up_ch_sel_2, + output up_ch_enb_2, + output [11:0] up_ch_addr_2, + output up_ch_wr_2, + output [15:0] up_ch_wdata_2, + input [15:0] up_ch_rdata_2, + input up_ch_ready_2, + + output [ 7:0] up_es_sel_3, + output up_es_enb_3, + output [11:0] up_es_addr_3, + output up_es_wr_3, + output [15:0] up_es_wdata_3, + input [15:0] up_es_rdata_3, + input up_es_ready_3, + + input up_ch_pll_locked_3, + output up_ch_rst_3, + output up_ch_user_ready_3, + input up_ch_rst_done_3, + output up_ch_lpm_dfe_n_3, + output [ 2:0] up_ch_rate_3, + output [ 1:0] up_ch_sys_clk_sel_3, + output [ 2:0] up_ch_out_clk_sel_3, + output [ 7:0] up_ch_sel_3, + output up_ch_enb_3, + output [11:0] up_ch_addr_3, + output up_ch_wr_3, + output [15:0] up_ch_wdata_3, + input [15:0] up_ch_rdata_3, + input up_ch_ready_3, + + output [ 7:0] up_cm_sel_4, + output up_cm_enb_4, + output [11:0] up_cm_addr_4, + output up_cm_wr_4, + output [15:0] up_cm_wdata_4, + input [15:0] up_cm_rdata_4, + input up_cm_ready_4, + + output [ 7:0] up_es_sel_4, + output up_es_enb_4, + output [11:0] up_es_addr_4, + output up_es_wr_4, + output [15:0] up_es_wdata_4, + input [15:0] up_es_rdata_4, + input up_es_ready_4, + + input up_ch_pll_locked_4, + output up_ch_rst_4, + output up_ch_user_ready_4, + input up_ch_rst_done_4, + output up_ch_lpm_dfe_n_4, + output [ 2:0] up_ch_rate_4, + output [ 1:0] up_ch_sys_clk_sel_4, + output [ 2:0] up_ch_out_clk_sel_4, + output [ 7:0] up_ch_sel_4, + output up_ch_enb_4, + output [11:0] up_ch_addr_4, + output up_ch_wr_4, + output [15:0] up_ch_wdata_4, + input [15:0] up_ch_rdata_4, + input up_ch_ready_4, + + output [ 7:0] up_es_sel_5, + output up_es_enb_5, + output [11:0] up_es_addr_5, + output up_es_wr_5, + output [15:0] up_es_wdata_5, + input [15:0] up_es_rdata_5, + input up_es_ready_5, + + input up_ch_pll_locked_5, + output up_ch_rst_5, + output up_ch_user_ready_5, + input up_ch_rst_done_5, + output up_ch_lpm_dfe_n_5, + output [ 2:0] up_ch_rate_5, + output [ 1:0] up_ch_sys_clk_sel_5, + output [ 2:0] up_ch_out_clk_sel_5, + output [ 7:0] up_ch_sel_5, + output up_ch_enb_5, + output [11:0] up_ch_addr_5, + output up_ch_wr_5, + output [15:0] up_ch_wdata_5, + input [15:0] up_ch_rdata_5, + input up_ch_ready_5, + + output [ 7:0] up_es_sel_6, + output up_es_enb_6, + output [11:0] up_es_addr_6, + output up_es_wr_6, + output [15:0] up_es_wdata_6, + input [15:0] up_es_rdata_6, + input up_es_ready_6, + + input up_ch_pll_locked_6, + output up_ch_rst_6, + output up_ch_user_ready_6, + input up_ch_rst_done_6, + output up_ch_lpm_dfe_n_6, + output [ 2:0] up_ch_rate_6, + output [ 1:0] up_ch_sys_clk_sel_6, + output [ 2:0] up_ch_out_clk_sel_6, + output [ 7:0] up_ch_sel_6, + output up_ch_enb_6, + output [11:0] up_ch_addr_6, + output up_ch_wr_6, + output [15:0] up_ch_wdata_6, + input [15:0] up_ch_rdata_6, + input up_ch_ready_6, + + output [ 7:0] up_es_sel_7, + output up_es_enb_7, + output [11:0] up_es_addr_7, + output up_es_wr_7, + output [15:0] up_es_wdata_7, + input [15:0] up_es_rdata_7, + input up_es_ready_7, + + input up_ch_pll_locked_7, + output up_ch_rst_7, + output up_ch_user_ready_7, + input up_ch_rst_done_7, + output up_ch_lpm_dfe_n_7, + output [ 2:0] up_ch_rate_7, + output [ 1:0] up_ch_sys_clk_sel_7, + output [ 2:0] up_ch_out_clk_sel_7, + output [ 7:0] up_ch_sel_7, + output up_ch_enb_7, + output [11:0] up_ch_addr_7, + output up_ch_wr_7, + output [15:0] up_ch_wdata_7, + input [15:0] up_ch_rdata_7, + input up_ch_ready_7, + + output [ 7:0] up_cm_sel_8, + output up_cm_enb_8, + output [11:0] up_cm_addr_8, + output up_cm_wr_8, + output [15:0] up_cm_wdata_8, + input [15:0] up_cm_rdata_8, + input up_cm_ready_8, + + output [ 7:0] up_es_sel_8, + output up_es_enb_8, + output [11:0] up_es_addr_8, + output up_es_wr_8, + output [15:0] up_es_wdata_8, + input [15:0] up_es_rdata_8, + input up_es_ready_8, + + input up_ch_pll_locked_8, + output up_ch_rst_8, + output up_ch_user_ready_8, + input up_ch_rst_done_8, + output up_ch_lpm_dfe_n_8, + output [ 2:0] up_ch_rate_8, + output [ 1:0] up_ch_sys_clk_sel_8, + output [ 2:0] up_ch_out_clk_sel_8, + output [ 7:0] up_ch_sel_8, + output up_ch_enb_8, + output [11:0] up_ch_addr_8, + output up_ch_wr_8, + output [15:0] up_ch_wdata_8, + input [15:0] up_ch_rdata_8, + input up_ch_ready_8, + + output [ 7:0] up_es_sel_9, + output up_es_enb_9, + output [11:0] up_es_addr_9, + output up_es_wr_9, + output [15:0] up_es_wdata_9, + input [15:0] up_es_rdata_9, + input up_es_ready_9, + + input up_ch_pll_locked_9, + output up_ch_rst_9, + output up_ch_user_ready_9, + input up_ch_rst_done_9, + output up_ch_lpm_dfe_n_9, + output [ 2:0] up_ch_rate_9, + output [ 1:0] up_ch_sys_clk_sel_9, + output [ 2:0] up_ch_out_clk_sel_9, + output [ 7:0] up_ch_sel_9, + output up_ch_enb_9, + output [11:0] up_ch_addr_9, + output up_ch_wr_9, + output [15:0] up_ch_wdata_9, + input [15:0] up_ch_rdata_9, + input up_ch_ready_9, + + output [ 7:0] up_es_sel_10, + output up_es_enb_10, + output [11:0] up_es_addr_10, + output up_es_wr_10, + output [15:0] up_es_wdata_10, + input [15:0] up_es_rdata_10, + input up_es_ready_10, + + input up_ch_pll_locked_10, + output up_ch_rst_10, + output up_ch_user_ready_10, + input up_ch_rst_done_10, + output up_ch_lpm_dfe_n_10, + output [ 2:0] up_ch_rate_10, + output [ 1:0] up_ch_sys_clk_sel_10, + output [ 2:0] up_ch_out_clk_sel_10, + output [ 7:0] up_ch_sel_10, + output up_ch_enb_10, + output [11:0] up_ch_addr_10, + output up_ch_wr_10, + output [15:0] up_ch_wdata_10, + input [15:0] up_ch_rdata_10, + input up_ch_ready_10, + + output [ 7:0] up_es_sel_11, + output up_es_enb_11, + output [11:0] up_es_addr_11, + output up_es_wr_11, + output [15:0] up_es_wdata_11, + input [15:0] up_es_rdata_11, + input up_es_ready_11, + + input up_ch_pll_locked_11, + output up_ch_rst_11, + output up_ch_user_ready_11, + input up_ch_rst_done_11, + output up_ch_lpm_dfe_n_11, + output [ 2:0] up_ch_rate_11, + output [ 1:0] up_ch_sys_clk_sel_11, + output [ 2:0] up_ch_out_clk_sel_11, + output [ 7:0] up_ch_sel_11, + output up_ch_enb_11, + output [11:0] up_ch_addr_11, + output up_ch_wr_11, + output [15:0] up_ch_wdata_11, + input [15:0] up_ch_rdata_11, + input up_ch_ready_11, + + output [ 7:0] up_cm_sel_12, + output up_cm_enb_12, + output [11:0] up_cm_addr_12, + output up_cm_wr_12, + output [15:0] up_cm_wdata_12, + input [15:0] up_cm_rdata_12, + input up_cm_ready_12, + + output [ 7:0] up_es_sel_12, + output up_es_enb_12, + output [11:0] up_es_addr_12, + output up_es_wr_12, + output [15:0] up_es_wdata_12, + input [15:0] up_es_rdata_12, + input up_es_ready_12, + + input up_ch_pll_locked_12, + output up_ch_rst_12, + output up_ch_user_ready_12, + input up_ch_rst_done_12, + output up_ch_lpm_dfe_n_12, + output [ 2:0] up_ch_rate_12, + output [ 1:0] up_ch_sys_clk_sel_12, + output [ 2:0] up_ch_out_clk_sel_12, + output [ 7:0] up_ch_sel_12, + output up_ch_enb_12, + output [11:0] up_ch_addr_12, + output up_ch_wr_12, + output [15:0] up_ch_wdata_12, + input [15:0] up_ch_rdata_12, + input up_ch_ready_12, + + output [ 7:0] up_es_sel_13, + output up_es_enb_13, + output [11:0] up_es_addr_13, + output up_es_wr_13, + output [15:0] up_es_wdata_13, + input [15:0] up_es_rdata_13, + input up_es_ready_13, + + input up_ch_pll_locked_13, + output up_ch_rst_13, + output up_ch_user_ready_13, + input up_ch_rst_done_13, + output up_ch_lpm_dfe_n_13, + output [ 2:0] up_ch_rate_13, + output [ 1:0] up_ch_sys_clk_sel_13, + output [ 2:0] up_ch_out_clk_sel_13, + output [ 7:0] up_ch_sel_13, + output up_ch_enb_13, + output [11:0] up_ch_addr_13, + output up_ch_wr_13, + output [15:0] up_ch_wdata_13, + input [15:0] up_ch_rdata_13, + input up_ch_ready_13, + + output [ 7:0] up_es_sel_14, + output up_es_enb_14, + output [11:0] up_es_addr_14, + output up_es_wr_14, + output [15:0] up_es_wdata_14, + input [15:0] up_es_rdata_14, + input up_es_ready_14, + + input up_ch_pll_locked_14, + output up_ch_rst_14, + output up_ch_user_ready_14, + input up_ch_rst_done_14, + output up_ch_lpm_dfe_n_14, + output [ 2:0] up_ch_rate_14, + output [ 1:0] up_ch_sys_clk_sel_14, + output [ 2:0] up_ch_out_clk_sel_14, + output [ 7:0] up_ch_sel_14, + output up_ch_enb_14, + output [11:0] up_ch_addr_14, + output up_ch_wr_14, + output [15:0] up_ch_wdata_14, + input [15:0] up_ch_rdata_14, + input up_ch_ready_14, + + output [ 7:0] up_es_sel_15, + output up_es_enb_15, + output [11:0] up_es_addr_15, + output up_es_wr_15, + output [15:0] up_es_wdata_15, + input [15:0] up_es_rdata_15, + input up_es_ready_15, + + input up_ch_pll_locked_15, + output up_ch_rst_15, + output up_ch_user_ready_15, + input up_ch_rst_done_15, + output up_ch_lpm_dfe_n_15, + output [ 2:0] up_ch_rate_15, + output [ 1:0] up_ch_sys_clk_sel_15, + output [ 2:0] up_ch_out_clk_sel_15, + output [ 7:0] up_ch_sel_15, + output up_ch_enb_15, + output [11:0] up_ch_addr_15, + output up_ch_wr_15, + output [15:0] up_ch_wdata_15, + input [15:0] up_ch_rdata_15, + input up_ch_ready_15, + + input s_axi_aclk, + input s_axi_aresetn, + output up_status, + output up_pll_rst, + + input s_axi_awvalid, + input [31:0] s_axi_awaddr, + input [ 2:0] s_axi_awprot, + output s_axi_awready, + input s_axi_wvalid, + input [31:0] s_axi_wdata, + input [ 3:0] s_axi_wstrb, + output s_axi_wready, + output s_axi_bvalid, + output [ 1:0] s_axi_bresp, + input s_axi_bready, + input s_axi_arvalid, + input [31:0] s_axi_araddr, + input [ 2:0] s_axi_arprot, + output s_axi_arready, + output s_axi_rvalid, + output [ 1:0] s_axi_rresp, + output [31:0] s_axi_rdata, + input s_axi_rready, + + output m_axi_awvalid, + output [31:0] m_axi_awaddr, + output [ 2:0] m_axi_awprot, + input m_axi_awready, + output m_axi_wvalid, + output [31:0] m_axi_wdata, + output [ 3:0] m_axi_wstrb, + input m_axi_wready, + input m_axi_bvalid, + input [ 1:0] m_axi_bresp, + output m_axi_bready, + output m_axi_arvalid, + output [31:0] m_axi_araddr, + output [ 2:0] m_axi_arprot, + input m_axi_arready, + input m_axi_rvalid, + input [31:0] m_axi_rdata, + input [ 1:0] m_axi_rresp, + output m_axi_rready); + + // internal signals + + wire [ 7:0] up_cm_sel; + wire up_cm_enb; + wire [11:0] up_cm_addr; + wire up_cm_wr; + wire [15:0] up_cm_wdata; + wire [15:0] up_cm_rdata_0_s; + wire up_cm_ready_0_s; + wire [15:0] up_cm_rdata_4_s; + wire up_cm_ready_4_s; + wire [15:0] up_cm_rdata_8_s; + wire up_cm_ready_8_s; + wire [15:0] up_cm_rdata_12_s; + wire up_cm_ready_12_s; + wire [ 7:0] up_es_sel; + wire up_es_enb; + wire [11:0] up_es_addr; + wire up_es_wr; + wire [15:0] up_es_wdata; + wire [15:0] up_es_rdata_0_s; + wire up_es_ready_0_s; + wire [15:0] up_es_rdata_1_s; + wire up_es_ready_1_s; + wire [15:0] up_es_rdata_2_s; + wire up_es_ready_2_s; + wire [15:0] up_es_rdata_3_s; + wire up_es_ready_3_s; + wire [15:0] up_es_rdata_4_s; + wire up_es_ready_4_s; + wire [15:0] up_es_rdata_5_s; + wire up_es_ready_5_s; + wire [15:0] up_es_rdata_6_s; + wire up_es_ready_6_s; + wire [15:0] up_es_rdata_7_s; + wire up_es_ready_7_s; + wire [15:0] up_es_rdata_8_s; + wire up_es_ready_8_s; + wire [15:0] up_es_rdata_9_s; + wire up_es_ready_9_s; + wire [15:0] up_es_rdata_10_s; + wire up_es_ready_10_s; + wire [15:0] up_es_rdata_11_s; + wire up_es_ready_11_s; + wire [15:0] up_es_rdata_12_s; + wire up_es_ready_12_s; + wire [15:0] up_es_rdata_13_s; + wire up_es_ready_13_s; + wire [15:0] up_es_rdata_14_s; + wire up_es_ready_14_s; + wire [15:0] up_es_rdata_15_s; + wire up_es_ready_15_s; + wire up_ch_rst; + wire up_ch_user_ready; + wire up_ch_lpm_dfe_n; + wire [ 2:0] up_ch_rate; + wire [ 1:0] up_ch_sys_clk_sel; + wire [ 2:0] up_ch_out_clk_sel; + wire up_ch_pll_locked_0_s; + wire up_ch_rst_done_0_s; + wire up_ch_pll_locked_1_s; + wire up_ch_rst_done_1_s; + wire up_ch_pll_locked_2_s; + wire up_ch_rst_done_2_s; + wire up_ch_pll_locked_3_s; + wire up_ch_rst_done_3_s; + wire up_ch_pll_locked_4_s; + wire up_ch_rst_done_4_s; + wire up_ch_pll_locked_5_s; + wire up_ch_rst_done_5_s; + wire up_ch_pll_locked_6_s; + wire up_ch_rst_done_6_s; + wire up_ch_pll_locked_7_s; + wire up_ch_rst_done_7_s; + wire up_ch_pll_locked_8_s; + wire up_ch_rst_done_8_s; + wire up_ch_pll_locked_9_s; + wire up_ch_rst_done_9_s; + wire up_ch_pll_locked_10_s; + wire up_ch_rst_done_10_s; + wire up_ch_pll_locked_11_s; + wire up_ch_rst_done_11_s; + wire up_ch_pll_locked_12_s; + wire up_ch_rst_done_12_s; + wire up_ch_pll_locked_13_s; + wire up_ch_rst_done_13_s; + wire up_ch_pll_locked_14_s; + wire up_ch_rst_done_14_s; + wire up_ch_pll_locked_15_s; + wire up_ch_rst_done_15_s; + wire [ 7:0] up_ch_sel; + wire up_ch_enb; + wire [11:0] up_ch_addr; + wire up_ch_wr; + wire [15:0] up_ch_wdata; + wire [15:0] up_ch_rdata_0_s; + wire up_ch_ready_0_s; + wire [15:0] up_ch_rdata_1_s; + wire up_ch_ready_1_s; + wire [15:0] up_ch_rdata_2_s; + wire up_ch_ready_2_s; + wire [15:0] up_ch_rdata_3_s; + wire up_ch_ready_3_s; + wire [15:0] up_ch_rdata_4_s; + wire up_ch_ready_4_s; + wire [15:0] up_ch_rdata_5_s; + wire up_ch_ready_5_s; + wire [15:0] up_ch_rdata_6_s; + wire up_ch_ready_6_s; + wire [15:0] up_ch_rdata_7_s; + wire up_ch_ready_7_s; + wire [15:0] up_ch_rdata_8_s; + wire up_ch_ready_8_s; + wire [15:0] up_ch_rdata_9_s; + wire up_ch_ready_9_s; + wire [15:0] up_ch_rdata_10_s; + wire up_ch_ready_10_s; + wire [15:0] up_ch_rdata_11_s; + wire up_ch_ready_11_s; + wire [15:0] up_ch_rdata_12_s; + wire up_ch_ready_12_s; + wire [15:0] up_ch_rdata_13_s; + wire up_ch_ready_13_s; + wire [15:0] up_ch_rdata_14_s; + wire up_ch_ready_14_s; + wire [15:0] up_ch_rdata_15_s; + wire up_ch_ready_15_s; + wire up_es_req; + wire up_es_ack; + wire [ 4:0] up_es_pscale; + wire [ 1:0] up_es_vrange; + wire [ 7:0] up_es_vstep; + wire [ 7:0] up_es_vmax; + wire [ 7:0] up_es_vmin; + wire [11:0] up_es_hmax; + wire [11:0] up_es_hmin; + wire [11:0] up_es_hstep; + wire [31:0] up_es_saddr; + wire up_es_status; + wire up_rstn; + wire up_clk; + wire up_wreq; + wire [ 9:0] up_waddr; + wire [31:0] up_wdata; + wire up_wack; + wire up_rreq; + wire [ 9:0] up_raddr; + wire [31:0] up_rdata; + wire up_rack; + + // channel broadcast + + assign up_rstn = s_axi_aresetn; + assign up_clk = s_axi_aclk; + + assign up_cm_sel_0 = up_cm_sel; + assign up_cm_enb_0 = up_cm_enb; + assign up_cm_addr_0 = up_cm_addr; + assign up_cm_wr_0 = up_cm_wr; + assign up_cm_wdata_0 = up_cm_wdata; + + axi_adxcvr_mdrp #( + .XCVR_ID (0), + .NUM_OF_LANES (NUM_OF_LANES)) + i_mdrp_cm_0 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_cm_sel), + .up_enb (up_cm_enb), + .up_rdata_in (16'd0), + .up_ready_in (1'd1), + .up_rdata (up_cm_rdata_0), + .up_ready (up_cm_ready_0), + .up_rdata_out (up_cm_rdata_0_s), + .up_ready_out (up_cm_ready_0_s)); + + assign up_es_sel_0 = up_es_sel; + assign up_es_enb_0 = up_es_enb; + assign up_es_addr_0 = up_es_addr; + assign up_es_wr_0 = up_es_wr; + assign up_es_wdata_0 = up_es_wdata; + + axi_adxcvr_mdrp #( + .XCVR_ID (0), + .NUM_OF_LANES (NUM_OF_LANES)) + i_mdrp_es_0 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_es_sel), + .up_enb (up_es_enb), + .up_rdata_in (16'd0), + .up_ready_in (1'd1), + .up_rdata (up_es_rdata_0), + .up_ready (up_es_ready_0), + .up_rdata_out (up_es_rdata_0_s), + .up_ready_out (up_es_ready_0_s)); + + assign up_ch_rst_0 = up_ch_rst; + assign up_ch_user_ready_0 = up_ch_user_ready; + assign up_ch_lpm_dfe_n_0 = up_ch_lpm_dfe_n; + assign up_ch_rate_0 = up_ch_rate; + assign up_ch_sys_clk_sel_0 = up_ch_sys_clk_sel; + assign up_ch_out_clk_sel_0 = up_ch_out_clk_sel; + + axi_adxcvr_mstatus #( + .XCVR_ID (0), + .NUM_OF_LANES (NUM_OF_LANES)) + i_mstatus_ch_0 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_pll_locked_in (1'd1), + .up_rst_done_in (1'd1), + .up_pll_locked (up_ch_pll_locked_0), + .up_rst_done (up_ch_rst_done_0), + .up_pll_locked_out (up_ch_pll_locked_0_s), + .up_rst_done_out (up_ch_rst_done_0_s)); + + assign up_ch_sel_0 = up_ch_sel; + assign up_ch_enb_0 = up_ch_enb; + assign up_ch_addr_0 = up_ch_addr; + assign up_ch_wr_0 = up_ch_wr; + assign up_ch_wdata_0 = up_ch_wdata; + + axi_adxcvr_mdrp #( + .XCVR_ID (0), + .NUM_OF_LANES (NUM_OF_LANES)) + i_mdrp_ch_0 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_ch_sel), + .up_enb (up_ch_enb), + .up_rdata_in (16'd0), + .up_ready_in (1'd1), + .up_rdata (up_ch_rdata_0), + .up_ready (up_ch_ready_0), + .up_rdata_out (up_ch_rdata_0_s), + .up_ready_out (up_ch_ready_0_s)); + + assign up_es_sel_1 = up_es_sel; + assign up_es_enb_1 = up_es_enb; + assign up_es_addr_1 = up_es_addr; + assign up_es_wr_1 = up_es_wr; + assign up_es_wdata_1 = up_es_wdata; + + axi_adxcvr_mdrp #( + .XCVR_ID (1), + .NUM_OF_LANES (NUM_OF_LANES)) + i_mdrp_es_1 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_es_sel), + .up_enb (up_es_enb), + .up_rdata_in (up_es_rdata_0_s), + .up_ready_in (up_es_ready_0_s), + .up_rdata (up_es_rdata_1), + .up_ready (up_es_ready_1), + .up_rdata_out (up_es_rdata_1_s), + .up_ready_out (up_es_ready_1_s)); + + assign up_ch_rst_1 = up_ch_rst; + assign up_ch_user_ready_1 = up_ch_user_ready; + assign up_ch_lpm_dfe_n_1 = up_ch_lpm_dfe_n; + assign up_ch_rate_1 = up_ch_rate; + assign up_ch_sys_clk_sel_1 = up_ch_sys_clk_sel; + assign up_ch_out_clk_sel_1 = up_ch_out_clk_sel; + + axi_adxcvr_mstatus #( + .XCVR_ID (1), + .NUM_OF_LANES (NUM_OF_LANES)) + i_mstatus_ch_1 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_pll_locked_in (up_ch_pll_locked_0_s), + .up_rst_done_in (up_ch_rst_done_0_s), + .up_pll_locked (up_ch_pll_locked_1), + .up_rst_done (up_ch_rst_done_1), + .up_pll_locked_out (up_ch_pll_locked_1_s), + .up_rst_done_out (up_ch_rst_done_1_s)); + + assign up_ch_sel_1 = up_ch_sel; + assign up_ch_enb_1 = up_ch_enb; + assign up_ch_addr_1 = up_ch_addr; + assign up_ch_wr_1 = up_ch_wr; + assign up_ch_wdata_1 = up_ch_wdata; + + axi_adxcvr_mdrp #( + .XCVR_ID (1), + .NUM_OF_LANES (NUM_OF_LANES)) + i_mdrp_ch_1 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_ch_sel), + .up_enb (up_ch_enb), + .up_rdata_in (up_ch_rdata_0_s), + .up_ready_in (up_ch_ready_0_s), + .up_rdata (up_ch_rdata_1), + .up_ready (up_ch_ready_1), + .up_rdata_out (up_ch_rdata_1_s), + .up_ready_out (up_ch_ready_1_s)); + + assign up_es_sel_2 = up_es_sel; + assign up_es_enb_2 = up_es_enb; + assign up_es_addr_2 = up_es_addr; + assign up_es_wr_2 = up_es_wr; + assign up_es_wdata_2 = up_es_wdata; + + axi_adxcvr_mdrp #( + .XCVR_ID (2), + .NUM_OF_LANES (NUM_OF_LANES)) + i_mdrp_es_2 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_es_sel), + .up_enb (up_es_enb), + .up_rdata_in (up_es_rdata_1_s), + .up_ready_in (up_es_ready_1_s), + .up_rdata (up_es_rdata_2), + .up_ready (up_es_ready_2), + .up_rdata_out (up_es_rdata_2_s), + .up_ready_out (up_es_ready_2_s)); + + assign up_ch_rst_2 = up_ch_rst; + assign up_ch_user_ready_2 = up_ch_user_ready; + assign up_ch_lpm_dfe_n_2 = up_ch_lpm_dfe_n; + assign up_ch_rate_2 = up_ch_rate; + assign up_ch_sys_clk_sel_2 = up_ch_sys_clk_sel; + assign up_ch_out_clk_sel_2 = up_ch_out_clk_sel; + + axi_adxcvr_mstatus #( + .XCVR_ID (2), + .NUM_OF_LANES (NUM_OF_LANES)) + i_mstatus_ch_2 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_pll_locked_in (up_ch_pll_locked_1_s), + .up_rst_done_in (up_ch_rst_done_1_s), + .up_pll_locked (up_ch_pll_locked_2), + .up_rst_done (up_ch_rst_done_2), + .up_pll_locked_out (up_ch_pll_locked_2_s), + .up_rst_done_out (up_ch_rst_done_2_s)); + + assign up_ch_sel_2 = up_ch_sel; + assign up_ch_enb_2 = up_ch_enb; + assign up_ch_addr_2 = up_ch_addr; + assign up_ch_wr_2 = up_ch_wr; + assign up_ch_wdata_2 = up_ch_wdata; + + axi_adxcvr_mdrp #( + .XCVR_ID (2), + .NUM_OF_LANES (NUM_OF_LANES)) + i_mdrp_ch_2 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_ch_sel), + .up_enb (up_ch_enb), + .up_rdata_in (up_ch_rdata_1_s), + .up_ready_in (up_ch_ready_1_s), + .up_rdata (up_ch_rdata_2), + .up_ready (up_ch_ready_2), + .up_rdata_out (up_ch_rdata_2_s), + .up_ready_out (up_ch_ready_2_s)); + + assign up_es_sel_3 = up_es_sel; + assign up_es_enb_3 = up_es_enb; + assign up_es_addr_3 = up_es_addr; + assign up_es_wr_3 = up_es_wr; + assign up_es_wdata_3 = up_es_wdata; + + axi_adxcvr_mdrp #( + .XCVR_ID (3), + .NUM_OF_LANES (NUM_OF_LANES)) + i_mdrp_es_3 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_es_sel), + .up_enb (up_es_enb), + .up_rdata_in (up_es_rdata_2_s), + .up_ready_in (up_es_ready_2_s), + .up_rdata (up_es_rdata_3), + .up_ready (up_es_ready_3), + .up_rdata_out (up_es_rdata_3_s), + .up_ready_out (up_es_ready_3_s)); + + assign up_ch_rst_3 = up_ch_rst; + assign up_ch_user_ready_3 = up_ch_user_ready; + assign up_ch_lpm_dfe_n_3 = up_ch_lpm_dfe_n; + assign up_ch_rate_3 = up_ch_rate; + assign up_ch_sys_clk_sel_3 = up_ch_sys_clk_sel; + assign up_ch_out_clk_sel_3 = up_ch_out_clk_sel; + + axi_adxcvr_mstatus #( + .XCVR_ID (3), + .NUM_OF_LANES (NUM_OF_LANES)) + i_mstatus_ch_3 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_pll_locked_in (up_ch_pll_locked_2_s), + .up_rst_done_in (up_ch_rst_done_2_s), + .up_pll_locked (up_ch_pll_locked_3), + .up_rst_done (up_ch_rst_done_3), + .up_pll_locked_out (up_ch_pll_locked_3_s), + .up_rst_done_out (up_ch_rst_done_3_s)); + + assign up_ch_sel_3 = up_ch_sel; + assign up_ch_enb_3 = up_ch_enb; + assign up_ch_addr_3 = up_ch_addr; + assign up_ch_wr_3 = up_ch_wr; + assign up_ch_wdata_3 = up_ch_wdata; + + axi_adxcvr_mdrp #( + .XCVR_ID (3), + .NUM_OF_LANES (NUM_OF_LANES)) + i_mdrp_ch_3 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_ch_sel), + .up_enb (up_ch_enb), + .up_rdata_in (up_ch_rdata_2_s), + .up_ready_in (up_ch_ready_2_s), + .up_rdata (up_ch_rdata_3), + .up_ready (up_ch_ready_3), + .up_rdata_out (up_ch_rdata_3_s), + .up_ready_out (up_ch_ready_3_s)); + + assign up_cm_sel_4 = up_cm_sel; + assign up_cm_enb_4 = up_cm_enb; + assign up_cm_addr_4 = up_cm_addr; + assign up_cm_wr_4 = up_cm_wr; + assign up_cm_wdata_4 = up_cm_wdata; + + axi_adxcvr_mdrp #( + .XCVR_ID (4), + .NUM_OF_LANES (NUM_OF_LANES)) + i_mdrp_cm_4 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_cm_sel), + .up_enb (up_cm_enb), + .up_rdata_in (up_cm_rdata_0_s), + .up_ready_in (up_cm_ready_0_s), + .up_rdata (up_cm_rdata_4), + .up_ready (up_cm_ready_4), + .up_rdata_out (up_cm_rdata_4_s), + .up_ready_out (up_cm_ready_4_s)); + + assign up_es_sel_4 = up_es_sel; + assign up_es_enb_4 = up_es_enb; + assign up_es_addr_4 = up_es_addr; + assign up_es_wr_4 = up_es_wr; + assign up_es_wdata_4 = up_es_wdata; + + axi_adxcvr_mdrp #( + .XCVR_ID (4), + .NUM_OF_LANES (NUM_OF_LANES)) + i_mdrp_es_4 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_es_sel), + .up_enb (up_es_enb), + .up_rdata_in (up_es_rdata_3_s), + .up_ready_in (up_es_ready_3_s), + .up_rdata (up_es_rdata_4), + .up_ready (up_es_ready_4), + .up_rdata_out (up_es_rdata_4_s), + .up_ready_out (up_es_ready_4_s)); + + assign up_ch_rst_4 = up_ch_rst; + assign up_ch_user_ready_4 = up_ch_user_ready; + assign up_ch_lpm_dfe_n_4 = up_ch_lpm_dfe_n; + assign up_ch_rate_4 = up_ch_rate; + assign up_ch_sys_clk_sel_4 = up_ch_sys_clk_sel; + assign up_ch_out_clk_sel_4 = up_ch_out_clk_sel; + + axi_adxcvr_mstatus #( + .XCVR_ID (4), + .NUM_OF_LANES (NUM_OF_LANES)) + i_mstatus_ch_4 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_pll_locked_in (up_ch_pll_locked_3_s), + .up_rst_done_in (up_ch_rst_done_3_s), + .up_pll_locked (up_ch_pll_locked_4), + .up_rst_done (up_ch_rst_done_4), + .up_pll_locked_out (up_ch_pll_locked_4_s), + .up_rst_done_out (up_ch_rst_done_4_s)); + + assign up_ch_sel_4 = up_ch_sel; + assign up_ch_enb_4 = up_ch_enb; + assign up_ch_addr_4 = up_ch_addr; + assign up_ch_wr_4 = up_ch_wr; + assign up_ch_wdata_4 = up_ch_wdata; + + axi_adxcvr_mdrp #( + .XCVR_ID (4), + .NUM_OF_LANES (NUM_OF_LANES)) + i_mdrp_ch_4 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_ch_sel), + .up_enb (up_ch_enb), + .up_rdata_in (up_ch_rdata_3_s), + .up_ready_in (up_ch_ready_3_s), + .up_rdata (up_ch_rdata_4), + .up_ready (up_ch_ready_4), + .up_rdata_out (up_ch_rdata_4_s), + .up_ready_out (up_ch_ready_4_s)); + + assign up_es_sel_5 = up_es_sel; + assign up_es_enb_5 = up_es_enb; + assign up_es_addr_5 = up_es_addr; + assign up_es_wr_5 = up_es_wr; + assign up_es_wdata_5 = up_es_wdata; + + axi_adxcvr_mdrp #( + .XCVR_ID (5), + .NUM_OF_LANES (NUM_OF_LANES)) + i_mdrp_es_5 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_es_sel), + .up_enb (up_es_enb), + .up_rdata_in (up_es_rdata_4_s), + .up_ready_in (up_es_ready_4_s), + .up_rdata (up_es_rdata_5), + .up_ready (up_es_ready_5), + .up_rdata_out (up_es_rdata_5_s), + .up_ready_out (up_es_ready_5_s)); + + assign up_ch_rst_5 = up_ch_rst; + assign up_ch_user_ready_5 = up_ch_user_ready; + assign up_ch_lpm_dfe_n_5 = up_ch_lpm_dfe_n; + assign up_ch_rate_5 = up_ch_rate; + assign up_ch_sys_clk_sel_5 = up_ch_sys_clk_sel; + assign up_ch_out_clk_sel_5 = up_ch_out_clk_sel; + + axi_adxcvr_mstatus #( + .XCVR_ID (5), + .NUM_OF_LANES (NUM_OF_LANES)) + i_mstatus_ch_5 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_pll_locked_in (up_ch_pll_locked_4_s), + .up_rst_done_in (up_ch_rst_done_4_s), + .up_pll_locked (up_ch_pll_locked_5), + .up_rst_done (up_ch_rst_done_5), + .up_pll_locked_out (up_ch_pll_locked_5_s), + .up_rst_done_out (up_ch_rst_done_5_s)); + + assign up_ch_sel_5 = up_ch_sel; + assign up_ch_enb_5 = up_ch_enb; + assign up_ch_addr_5 = up_ch_addr; + assign up_ch_wr_5 = up_ch_wr; + assign up_ch_wdata_5 = up_ch_wdata; + + axi_adxcvr_mdrp #( + .XCVR_ID (5), + .NUM_OF_LANES (NUM_OF_LANES)) + i_mdrp_ch_5 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_ch_sel), + .up_enb (up_ch_enb), + .up_rdata_in (up_ch_rdata_4_s), + .up_ready_in (up_ch_ready_4_s), + .up_rdata (up_ch_rdata_5), + .up_ready (up_ch_ready_5), + .up_rdata_out (up_ch_rdata_5_s), + .up_ready_out (up_ch_ready_5_s)); + + assign up_es_sel_6 = up_es_sel; + assign up_es_enb_6 = up_es_enb; + assign up_es_addr_6 = up_es_addr; + assign up_es_wr_6 = up_es_wr; + assign up_es_wdata_6 = up_es_wdata; + + axi_adxcvr_mdrp #( + .XCVR_ID (6), + .NUM_OF_LANES (NUM_OF_LANES)) + i_mdrp_es_6 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_es_sel), + .up_enb (up_es_enb), + .up_rdata_in (up_es_rdata_5_s), + .up_ready_in (up_es_ready_5_s), + .up_rdata (up_es_rdata_6), + .up_ready (up_es_ready_6), + .up_rdata_out (up_es_rdata_6_s), + .up_ready_out (up_es_ready_6_s)); + + assign up_ch_rst_6 = up_ch_rst; + assign up_ch_user_ready_6 = up_ch_user_ready; + assign up_ch_lpm_dfe_n_6 = up_ch_lpm_dfe_n; + assign up_ch_rate_6 = up_ch_rate; + assign up_ch_sys_clk_sel_6 = up_ch_sys_clk_sel; + assign up_ch_out_clk_sel_6 = up_ch_out_clk_sel; + + axi_adxcvr_mstatus #( + .XCVR_ID (6), + .NUM_OF_LANES (NUM_OF_LANES)) + i_mstatus_ch_6 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_pll_locked_in (up_ch_pll_locked_5_s), + .up_rst_done_in (up_ch_rst_done_5_s), + .up_pll_locked (up_ch_pll_locked_6), + .up_rst_done (up_ch_rst_done_6), + .up_pll_locked_out (up_ch_pll_locked_6_s), + .up_rst_done_out (up_ch_rst_done_6_s)); + + assign up_ch_sel_6 = up_ch_sel; + assign up_ch_enb_6 = up_ch_enb; + assign up_ch_addr_6 = up_ch_addr; + assign up_ch_wr_6 = up_ch_wr; + assign up_ch_wdata_6 = up_ch_wdata; + + axi_adxcvr_mdrp #( + .XCVR_ID (6), + .NUM_OF_LANES (NUM_OF_LANES)) + i_mdrp_ch_6 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_ch_sel), + .up_enb (up_ch_enb), + .up_rdata_in (up_ch_rdata_5_s), + .up_ready_in (up_ch_ready_5_s), + .up_rdata (up_ch_rdata_6), + .up_ready (up_ch_ready_6), + .up_rdata_out (up_ch_rdata_6_s), + .up_ready_out (up_ch_ready_6_s)); + + assign up_es_sel_7 = up_es_sel; + assign up_es_enb_7 = up_es_enb; + assign up_es_addr_7 = up_es_addr; + assign up_es_wr_7 = up_es_wr; + assign up_es_wdata_7 = up_es_wdata; + + axi_adxcvr_mdrp #( + .XCVR_ID (7), + .NUM_OF_LANES (NUM_OF_LANES)) + i_mdrp_es_7 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_es_sel), + .up_enb (up_es_enb), + .up_rdata_in (up_es_rdata_6_s), + .up_ready_in (up_es_ready_6_s), + .up_rdata (up_es_rdata_7), + .up_ready (up_es_ready_7), + .up_rdata_out (up_es_rdata_7_s), + .up_ready_out (up_es_ready_7_s)); + + assign up_ch_rst_7 = up_ch_rst; + assign up_ch_user_ready_7 = up_ch_user_ready; + assign up_ch_lpm_dfe_n_7 = up_ch_lpm_dfe_n; + assign up_ch_rate_7 = up_ch_rate; + assign up_ch_sys_clk_sel_7 = up_ch_sys_clk_sel; + assign up_ch_out_clk_sel_7 = up_ch_out_clk_sel; + + axi_adxcvr_mstatus #( + .XCVR_ID (7), + .NUM_OF_LANES (NUM_OF_LANES)) + i_mstatus_ch_7 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_pll_locked_in (up_ch_pll_locked_6_s), + .up_rst_done_in (up_ch_rst_done_6_s), + .up_pll_locked (up_ch_pll_locked_7), + .up_rst_done (up_ch_rst_done_7), + .up_pll_locked_out (up_ch_pll_locked_7_s), + .up_rst_done_out (up_ch_rst_done_7_s)); + + assign up_ch_sel_7 = up_ch_sel; + assign up_ch_enb_7 = up_ch_enb; + assign up_ch_addr_7 = up_ch_addr; + assign up_ch_wr_7 = up_ch_wr; + assign up_ch_wdata_7 = up_ch_wdata; + + axi_adxcvr_mdrp #( + .XCVR_ID (7), + .NUM_OF_LANES (NUM_OF_LANES)) + i_mdrp_ch_7 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_ch_sel), + .up_enb (up_ch_enb), + .up_rdata_in (up_ch_rdata_6_s), + .up_ready_in (up_ch_ready_6_s), + .up_rdata (up_ch_rdata_7), + .up_ready (up_ch_ready_7), + .up_rdata_out (up_ch_rdata_7_s), + .up_ready_out (up_ch_ready_7_s)); + + assign up_cm_sel_8 = up_cm_sel; + assign up_cm_enb_8 = up_cm_enb; + assign up_cm_addr_8 = up_cm_addr; + assign up_cm_wr_8 = up_cm_wr; + assign up_cm_wdata_8 = up_cm_wdata; + + axi_adxcvr_mdrp #( + .XCVR_ID (8), + .NUM_OF_LANES (NUM_OF_LANES)) + i_mdrp_cm_8 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_cm_sel), + .up_enb (up_cm_enb), + .up_rdata_in (up_cm_rdata_4_s), + .up_ready_in (up_cm_ready_4_s), + .up_rdata (up_cm_rdata_8), + .up_ready (up_cm_ready_8), + .up_rdata_out (up_cm_rdata_8_s), + .up_ready_out (up_cm_ready_8_s)); + + assign up_es_sel_8 = up_es_sel; + assign up_es_enb_8 = up_es_enb; + assign up_es_addr_8 = up_es_addr; + assign up_es_wr_8 = up_es_wr; + assign up_es_wdata_8 = up_es_wdata; + + axi_adxcvr_mdrp #( + .XCVR_ID (8), + .NUM_OF_LANES (NUM_OF_LANES)) + i_mdrp_es_8 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_es_sel), + .up_enb (up_es_enb), + .up_rdata_in (up_es_rdata_7_s), + .up_ready_in (up_es_ready_7_s), + .up_rdata (up_es_rdata_8), + .up_ready (up_es_ready_8), + .up_rdata_out (up_es_rdata_8_s), + .up_ready_out (up_es_ready_8_s)); + + assign up_ch_rst_8 = up_ch_rst; + assign up_ch_user_ready_8 = up_ch_user_ready; + assign up_ch_lpm_dfe_n_8 = up_ch_lpm_dfe_n; + assign up_ch_rate_8 = up_ch_rate; + assign up_ch_sys_clk_sel_8 = up_ch_sys_clk_sel; + assign up_ch_out_clk_sel_8 = up_ch_out_clk_sel; + + axi_adxcvr_mstatus #( + .XCVR_ID (8), + .NUM_OF_LANES (NUM_OF_LANES)) + i_mstatus_ch_8 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_pll_locked_in (up_ch_pll_locked_7_s), + .up_rst_done_in (up_ch_rst_done_7_s), + .up_pll_locked (up_ch_pll_locked_8), + .up_rst_done (up_ch_rst_done_8), + .up_pll_locked_out (up_ch_pll_locked_8_s), + .up_rst_done_out (up_ch_rst_done_8_s)); + + assign up_ch_sel_8 = up_ch_sel; + assign up_ch_enb_8 = up_ch_enb; + assign up_ch_addr_8 = up_ch_addr; + assign up_ch_wr_8 = up_ch_wr; + assign up_ch_wdata_8 = up_ch_wdata; + + axi_adxcvr_mdrp #( + .XCVR_ID (8), + .NUM_OF_LANES (NUM_OF_LANES)) + i_mdrp_ch_8 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_ch_sel), + .up_enb (up_ch_enb), + .up_rdata_in (up_ch_rdata_7_s), + .up_ready_in (up_ch_ready_7_s), + .up_rdata (up_ch_rdata_8), + .up_ready (up_ch_ready_8), + .up_rdata_out (up_ch_rdata_8_s), + .up_ready_out (up_ch_ready_8_s)); + + assign up_es_sel_9 = up_es_sel; + assign up_es_enb_9 = up_es_enb; + assign up_es_addr_9 = up_es_addr; + assign up_es_wr_9 = up_es_wr; + assign up_es_wdata_9 = up_es_wdata; + + axi_adxcvr_mdrp #( + .XCVR_ID (9), + .NUM_OF_LANES (NUM_OF_LANES)) + i_mdrp_es_9 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_es_sel), + .up_enb (up_es_enb), + .up_rdata_in (up_es_rdata_8_s), + .up_ready_in (up_es_ready_8_s), + .up_rdata (up_es_rdata_9), + .up_ready (up_es_ready_9), + .up_rdata_out (up_es_rdata_9_s), + .up_ready_out (up_es_ready_9_s)); + + assign up_ch_rst_9 = up_ch_rst; + assign up_ch_user_ready_9 = up_ch_user_ready; + assign up_ch_lpm_dfe_n_9 = up_ch_lpm_dfe_n; + assign up_ch_rate_9 = up_ch_rate; + assign up_ch_sys_clk_sel_9 = up_ch_sys_clk_sel; + assign up_ch_out_clk_sel_9 = up_ch_out_clk_sel; + + axi_adxcvr_mstatus #( + .XCVR_ID (9), + .NUM_OF_LANES (NUM_OF_LANES)) + i_mstatus_ch_9 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_pll_locked_in (up_ch_pll_locked_8_s), + .up_rst_done_in (up_ch_rst_done_8_s), + .up_pll_locked (up_ch_pll_locked_9), + .up_rst_done (up_ch_rst_done_9), + .up_pll_locked_out (up_ch_pll_locked_9_s), + .up_rst_done_out (up_ch_rst_done_9_s)); + + assign up_ch_sel_9 = up_ch_sel; + assign up_ch_enb_9 = up_ch_enb; + assign up_ch_addr_9 = up_ch_addr; + assign up_ch_wr_9 = up_ch_wr; + assign up_ch_wdata_9 = up_ch_wdata; + + axi_adxcvr_mdrp #( + .XCVR_ID (9), + .NUM_OF_LANES (NUM_OF_LANES)) + i_mdrp_ch_9 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_ch_sel), + .up_enb (up_ch_enb), + .up_rdata_in (up_ch_rdata_8_s), + .up_ready_in (up_ch_ready_8_s), + .up_rdata (up_ch_rdata_9), + .up_ready (up_ch_ready_9), + .up_rdata_out (up_ch_rdata_9_s), + .up_ready_out (up_ch_ready_9_s)); + + assign up_es_sel_10 = up_es_sel; + assign up_es_enb_10 = up_es_enb; + assign up_es_addr_10 = up_es_addr; + assign up_es_wr_10 = up_es_wr; + assign up_es_wdata_10 = up_es_wdata; + + axi_adxcvr_mdrp #( + .XCVR_ID (10), + .NUM_OF_LANES (NUM_OF_LANES)) + i_mdrp_es_10 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_es_sel), + .up_enb (up_es_enb), + .up_rdata_in (up_es_rdata_9_s), + .up_ready_in (up_es_ready_9_s), + .up_rdata (up_es_rdata_10), + .up_ready (up_es_ready_10), + .up_rdata_out (up_es_rdata_10_s), + .up_ready_out (up_es_ready_10_s)); + + assign up_ch_rst_10 = up_ch_rst; + assign up_ch_user_ready_10 = up_ch_user_ready; + assign up_ch_lpm_dfe_n_10 = up_ch_lpm_dfe_n; + assign up_ch_rate_10 = up_ch_rate; + assign up_ch_sys_clk_sel_10 = up_ch_sys_clk_sel; + assign up_ch_out_clk_sel_10 = up_ch_out_clk_sel; + + axi_adxcvr_mstatus #( + .XCVR_ID (10), + .NUM_OF_LANES (NUM_OF_LANES)) + i_mstatus_ch_10 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_pll_locked_in (up_ch_pll_locked_9_s), + .up_rst_done_in (up_ch_rst_done_9_s), + .up_pll_locked (up_ch_pll_locked_10), + .up_rst_done (up_ch_rst_done_10), + .up_pll_locked_out (up_ch_pll_locked_10_s), + .up_rst_done_out (up_ch_rst_done_10_s)); + + assign up_ch_sel_10 = up_ch_sel; + assign up_ch_enb_10 = up_ch_enb; + assign up_ch_addr_10 = up_ch_addr; + assign up_ch_wr_10 = up_ch_wr; + assign up_ch_wdata_10 = up_ch_wdata; + + axi_adxcvr_mdrp #( + .XCVR_ID (10), + .NUM_OF_LANES (NUM_OF_LANES)) + i_mdrp_ch_10 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_ch_sel), + .up_enb (up_ch_enb), + .up_rdata_in (up_ch_rdata_9_s), + .up_ready_in (up_ch_ready_9_s), + .up_rdata (up_ch_rdata_10), + .up_ready (up_ch_ready_10), + .up_rdata_out (up_ch_rdata_10_s), + .up_ready_out (up_ch_ready_10_s)); + + assign up_es_sel_11 = up_es_sel; + assign up_es_enb_11 = up_es_enb; + assign up_es_addr_11 = up_es_addr; + assign up_es_wr_11 = up_es_wr; + assign up_es_wdata_11 = up_es_wdata; + + axi_adxcvr_mdrp #( + .XCVR_ID (11), + .NUM_OF_LANES (NUM_OF_LANES)) + i_mdrp_es_11 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_es_sel), + .up_enb (up_es_enb), + .up_rdata_in (up_es_rdata_10_s), + .up_ready_in (up_es_ready_10_s), + .up_rdata (up_es_rdata_11), + .up_ready (up_es_ready_11), + .up_rdata_out (up_es_rdata_11_s), + .up_ready_out (up_es_ready_11_s)); + + assign up_ch_rst_11 = up_ch_rst; + assign up_ch_user_ready_11 = up_ch_user_ready; + assign up_ch_lpm_dfe_n_11 = up_ch_lpm_dfe_n; + assign up_ch_rate_11 = up_ch_rate; + assign up_ch_sys_clk_sel_11 = up_ch_sys_clk_sel; + assign up_ch_out_clk_sel_11 = up_ch_out_clk_sel; + + axi_adxcvr_mstatus #( + .XCVR_ID (11), + .NUM_OF_LANES (NUM_OF_LANES)) + i_mstatus_ch_11 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_pll_locked_in (up_ch_pll_locked_10_s), + .up_rst_done_in (up_ch_rst_done_10_s), + .up_pll_locked (up_ch_pll_locked_11), + .up_rst_done (up_ch_rst_done_11), + .up_pll_locked_out (up_ch_pll_locked_11_s), + .up_rst_done_out (up_ch_rst_done_11_s)); + + assign up_ch_sel_11 = up_ch_sel; + assign up_ch_enb_11 = up_ch_enb; + assign up_ch_addr_11 = up_ch_addr; + assign up_ch_wr_11 = up_ch_wr; + assign up_ch_wdata_11 = up_ch_wdata; + + axi_adxcvr_mdrp #( + .XCVR_ID (11), + .NUM_OF_LANES (NUM_OF_LANES)) + i_mdrp_ch_11 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_ch_sel), + .up_enb (up_ch_enb), + .up_rdata_in (up_ch_rdata_10_s), + .up_ready_in (up_ch_ready_10_s), + .up_rdata (up_ch_rdata_11), + .up_ready (up_ch_ready_11), + .up_rdata_out (up_ch_rdata_11_s), + .up_ready_out (up_ch_ready_11_s)); + + assign up_cm_sel_12 = up_cm_sel; + assign up_cm_enb_12 = up_cm_enb; + assign up_cm_addr_12 = up_cm_addr; + assign up_cm_wr_12 = up_cm_wr; + assign up_cm_wdata_12 = up_cm_wdata; + + axi_adxcvr_mdrp #( + .XCVR_ID (12), + .NUM_OF_LANES (NUM_OF_LANES)) + i_mdrp_cm_12 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_cm_sel), + .up_enb (up_cm_enb), + .up_rdata_in (up_cm_rdata_8_s), + .up_ready_in (up_cm_ready_8_s), + .up_rdata (up_cm_rdata_12), + .up_ready (up_cm_ready_12), + .up_rdata_out (up_cm_rdata_12_s), + .up_ready_out (up_cm_ready_12_s)); + + assign up_es_sel_12 = up_es_sel; + assign up_es_enb_12 = up_es_enb; + assign up_es_addr_12 = up_es_addr; + assign up_es_wr_12 = up_es_wr; + assign up_es_wdata_12 = up_es_wdata; + + axi_adxcvr_mdrp #( + .XCVR_ID (12), + .NUM_OF_LANES (NUM_OF_LANES)) + i_mdrp_es_12 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_es_sel), + .up_enb (up_es_enb), + .up_rdata_in (up_es_rdata_11_s), + .up_ready_in (up_es_ready_11_s), + .up_rdata (up_es_rdata_12), + .up_ready (up_es_ready_12), + .up_rdata_out (up_es_rdata_12_s), + .up_ready_out (up_es_ready_12_s)); + + assign up_ch_rst_12 = up_ch_rst; + assign up_ch_user_ready_12 = up_ch_user_ready; + assign up_ch_lpm_dfe_n_12 = up_ch_lpm_dfe_n; + assign up_ch_rate_12 = up_ch_rate; + assign up_ch_sys_clk_sel_12 = up_ch_sys_clk_sel; + assign up_ch_out_clk_sel_12 = up_ch_out_clk_sel; + + axi_adxcvr_mstatus #( + .XCVR_ID (12), + .NUM_OF_LANES (NUM_OF_LANES)) + i_mstatus_ch_12 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_pll_locked_in (up_ch_pll_locked_11_s), + .up_rst_done_in (up_ch_rst_done_11_s), + .up_pll_locked (up_ch_pll_locked_12), + .up_rst_done (up_ch_rst_done_12), + .up_pll_locked_out (up_ch_pll_locked_12_s), + .up_rst_done_out (up_ch_rst_done_12_s)); + + assign up_ch_sel_12 = up_ch_sel; + assign up_ch_enb_12 = up_ch_enb; + assign up_ch_addr_12 = up_ch_addr; + assign up_ch_wr_12 = up_ch_wr; + assign up_ch_wdata_12 = up_ch_wdata; + + axi_adxcvr_mdrp #( + .XCVR_ID (12), + .NUM_OF_LANES (NUM_OF_LANES)) + i_mdrp_ch_12 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_ch_sel), + .up_enb (up_ch_enb), + .up_rdata_in (up_ch_rdata_11_s), + .up_ready_in (up_ch_ready_11_s), + .up_rdata (up_ch_rdata_12), + .up_ready (up_ch_ready_12), + .up_rdata_out (up_ch_rdata_12_s), + .up_ready_out (up_ch_ready_12_s)); + + assign up_es_sel_13 = up_es_sel; + assign up_es_enb_13 = up_es_enb; + assign up_es_addr_13 = up_es_addr; + assign up_es_wr_13 = up_es_wr; + assign up_es_wdata_13 = up_es_wdata; + + axi_adxcvr_mdrp #( + .XCVR_ID (13), + .NUM_OF_LANES (NUM_OF_LANES)) + i_mdrp_es_13 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_es_sel), + .up_enb (up_es_enb), + .up_rdata_in (up_es_rdata_12_s), + .up_ready_in (up_es_ready_12_s), + .up_rdata (up_es_rdata_13), + .up_ready (up_es_ready_13), + .up_rdata_out (up_es_rdata_13_s), + .up_ready_out (up_es_ready_13_s)); + + assign up_ch_rst_13 = up_ch_rst; + assign up_ch_user_ready_13 = up_ch_user_ready; + assign up_ch_lpm_dfe_n_13 = up_ch_lpm_dfe_n; + assign up_ch_rate_13 = up_ch_rate; + assign up_ch_sys_clk_sel_13 = up_ch_sys_clk_sel; + assign up_ch_out_clk_sel_13 = up_ch_out_clk_sel; + + axi_adxcvr_mstatus #( + .XCVR_ID (13), + .NUM_OF_LANES (NUM_OF_LANES)) + i_mstatus_ch_13 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_pll_locked_in (up_ch_pll_locked_12_s), + .up_rst_done_in (up_ch_rst_done_12_s), + .up_pll_locked (up_ch_pll_locked_13), + .up_rst_done (up_ch_rst_done_13), + .up_pll_locked_out (up_ch_pll_locked_13_s), + .up_rst_done_out (up_ch_rst_done_13_s)); + + assign up_ch_sel_13 = up_ch_sel; + assign up_ch_enb_13 = up_ch_enb; + assign up_ch_addr_13 = up_ch_addr; + assign up_ch_wr_13 = up_ch_wr; + assign up_ch_wdata_13 = up_ch_wdata; + + axi_adxcvr_mdrp #( + .XCVR_ID (13), + .NUM_OF_LANES (NUM_OF_LANES)) + i_mdrp_ch_13 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_ch_sel), + .up_enb (up_ch_enb), + .up_rdata_in (up_ch_rdata_12_s), + .up_ready_in (up_ch_ready_12_s), + .up_rdata (up_ch_rdata_13), + .up_ready (up_ch_ready_13), + .up_rdata_out (up_ch_rdata_13_s), + .up_ready_out (up_ch_ready_13_s)); + + assign up_es_sel_14 = up_es_sel; + assign up_es_enb_14 = up_es_enb; + assign up_es_addr_14 = up_es_addr; + assign up_es_wr_14 = up_es_wr; + assign up_es_wdata_14 = up_es_wdata; + + axi_adxcvr_mdrp #( + .XCVR_ID (14), + .NUM_OF_LANES (NUM_OF_LANES)) + i_mdrp_es_14 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_es_sel), + .up_enb (up_es_enb), + .up_rdata_in (up_es_rdata_13_s), + .up_ready_in (up_es_ready_13_s), + .up_rdata (up_es_rdata_14), + .up_ready (up_es_ready_14), + .up_rdata_out (up_es_rdata_14_s), + .up_ready_out (up_es_ready_14_s)); + + assign up_ch_rst_14 = up_ch_rst; + assign up_ch_user_ready_14 = up_ch_user_ready; + assign up_ch_lpm_dfe_n_14 = up_ch_lpm_dfe_n; + assign up_ch_rate_14 = up_ch_rate; + assign up_ch_sys_clk_sel_14 = up_ch_sys_clk_sel; + assign up_ch_out_clk_sel_14 = up_ch_out_clk_sel; + + axi_adxcvr_mstatus #( + .XCVR_ID (14), + .NUM_OF_LANES (NUM_OF_LANES)) + i_mstatus_ch_14 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_pll_locked_in (up_ch_pll_locked_13_s), + .up_rst_done_in (up_ch_rst_done_13_s), + .up_pll_locked (up_ch_pll_locked_14), + .up_rst_done (up_ch_rst_done_14), + .up_pll_locked_out (up_ch_pll_locked_14_s), + .up_rst_done_out (up_ch_rst_done_14_s)); + + assign up_ch_sel_14 = up_ch_sel; + assign up_ch_enb_14 = up_ch_enb; + assign up_ch_addr_14 = up_ch_addr; + assign up_ch_wr_14 = up_ch_wr; + assign up_ch_wdata_14 = up_ch_wdata; + + axi_adxcvr_mdrp #( + .XCVR_ID (14), + .NUM_OF_LANES (NUM_OF_LANES)) + i_mdrp_ch_14 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_ch_sel), + .up_enb (up_ch_enb), + .up_rdata_in (up_ch_rdata_13_s), + .up_ready_in (up_ch_ready_13_s), + .up_rdata (up_ch_rdata_14), + .up_ready (up_ch_ready_14), + .up_rdata_out (up_ch_rdata_14_s), + .up_ready_out (up_ch_ready_14_s)); + + assign up_es_sel_15 = up_es_sel; + assign up_es_enb_15 = up_es_enb; + assign up_es_addr_15 = up_es_addr; + assign up_es_wr_15 = up_es_wr; + assign up_es_wdata_15 = up_es_wdata; + + axi_adxcvr_mdrp #( + .XCVR_ID (15), + .NUM_OF_LANES (NUM_OF_LANES)) + i_mdrp_es_15 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_es_sel), + .up_enb (up_es_enb), + .up_rdata_in (up_es_rdata_14_s), + .up_ready_in (up_es_ready_14_s), + .up_rdata (up_es_rdata_15), + .up_ready (up_es_ready_15), + .up_rdata_out (up_es_rdata_15_s), + .up_ready_out (up_es_ready_15_s)); + + assign up_ch_rst_15 = up_ch_rst; + assign up_ch_user_ready_15 = up_ch_user_ready; + assign up_ch_lpm_dfe_n_15 = up_ch_lpm_dfe_n; + assign up_ch_rate_15 = up_ch_rate; + assign up_ch_sys_clk_sel_15 = up_ch_sys_clk_sel; + assign up_ch_out_clk_sel_15 = up_ch_out_clk_sel; + + axi_adxcvr_mstatus #( + .XCVR_ID (15), + .NUM_OF_LANES (NUM_OF_LANES)) + i_mstatus_ch_15 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_pll_locked_in (up_ch_pll_locked_14_s), + .up_rst_done_in (up_ch_rst_done_14_s), + .up_pll_locked (up_ch_pll_locked_15), + .up_rst_done (up_ch_rst_done_15), + .up_pll_locked_out (up_ch_pll_locked_15_s), + .up_rst_done_out (up_ch_rst_done_15_s)); + + assign up_ch_sel_15 = up_ch_sel; + assign up_ch_enb_15 = up_ch_enb; + assign up_ch_addr_15 = up_ch_addr; + assign up_ch_wr_15 = up_ch_wr; + assign up_ch_wdata_15 = up_ch_wdata; + + axi_adxcvr_mdrp #( + .XCVR_ID (15), + .NUM_OF_LANES (NUM_OF_LANES)) + i_mdrp_ch_15 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_ch_sel), + .up_enb (up_ch_enb), + .up_rdata_in (up_ch_rdata_14_s), + .up_ready_in (up_ch_ready_14_s), + .up_rdata (up_ch_rdata_15), + .up_ready (up_ch_ready_15), + .up_rdata_out (up_ch_rdata_15_s), + .up_ready_out (up_ch_ready_15_s)); + + axi_adxcvr_es #( + .GTH_OR_GTX_N (GTH_OR_GTX_N), + .TX_OR_RX_N (TX_OR_RX_N)) + i_es ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_es_enb (up_es_enb), + .up_es_addr (up_es_addr), + .up_es_wr (up_es_wr), + .up_es_wdata (up_es_wdata), + .up_es_rdata (up_es_rdata_15_s), + .up_es_ready (up_es_ready_15_s), + .up_ch_lpm_dfe_n (up_ch_lpm_dfe_n), + .up_es_req (up_es_req), + .up_es_ack (up_es_ack), + .up_es_pscale (up_es_pscale), + .up_es_vrange (up_es_vrange), + .up_es_vstep (up_es_vstep), + .up_es_vmax (up_es_vmax), + .up_es_vmin (up_es_vmin), + .up_es_hmax (up_es_hmax), + .up_es_hmin (up_es_hmin), + .up_es_hstep (up_es_hstep), + .up_es_saddr (up_es_saddr), + .up_es_status (up_es_status), + .up_axi_awvalid (m_axi_awvalid), + .up_axi_awaddr (m_axi_awaddr), + .up_axi_awprot (m_axi_awprot), + .up_axi_awready (m_axi_awready), + .up_axi_wvalid (m_axi_wvalid), + .up_axi_wdata (m_axi_wdata), + .up_axi_wstrb (m_axi_wstrb), + .up_axi_wready (m_axi_wready), + .up_axi_bvalid (m_axi_bvalid), + .up_axi_bresp (m_axi_bresp), + .up_axi_bready (m_axi_bready), + .up_axi_arvalid (m_axi_arvalid), + .up_axi_araddr (m_axi_araddr), + .up_axi_arprot (m_axi_arprot), + .up_axi_arready (m_axi_arready), + .up_axi_rvalid (m_axi_rvalid), + .up_axi_rdata (m_axi_rdata), + .up_axi_rresp (m_axi_rresp), + .up_axi_rready (m_axi_rready)); + + axi_adxcvr_up #( + .ID (ID), + .NUM_OF_LANES (NUM_OF_LANES), + .GTH_OR_GTX_N (GTH_OR_GTX_N), + .TX_OR_RX_N (TX_OR_RX_N), + .QPLL_ENABLE (QPLL_ENABLE), + .LPM_OR_DFE_N (LPM_OR_DFE_N), + .RATE (RATE), + .SYS_CLK_SEL (SYS_CLK_SEL), + .OUT_CLK_SEL (OUT_CLK_SEL)) + i_up ( + .up_cm_sel (up_cm_sel), + .up_cm_enb (up_cm_enb), + .up_cm_addr (up_cm_addr), + .up_cm_wr (up_cm_wr), + .up_cm_wdata (up_cm_wdata), + .up_cm_rdata (up_cm_rdata_12_s), + .up_cm_ready (up_cm_ready_12_s), + .up_ch_pll_locked (up_ch_pll_locked_15_s), + .up_ch_rst (up_ch_rst), + .up_ch_user_ready (up_ch_user_ready), + .up_ch_rst_done (up_ch_rst_done_15_s), + .up_ch_lpm_dfe_n (up_ch_lpm_dfe_n), + .up_ch_rate (up_ch_rate), + .up_ch_sys_clk_sel (up_ch_sys_clk_sel), + .up_ch_out_clk_sel (up_ch_out_clk_sel), + .up_ch_sel (up_ch_sel), + .up_ch_enb (up_ch_enb), + .up_ch_addr (up_ch_addr), + .up_ch_wr (up_ch_wr), + .up_ch_wdata (up_ch_wdata), + .up_ch_rdata (up_ch_rdata_15_s), + .up_ch_ready (up_ch_ready_15_s), + .up_es_sel (up_es_sel), + .up_es_req (up_es_req), + .up_es_ack (up_es_ack), + .up_es_pscale (up_es_pscale), + .up_es_vrange (up_es_vrange), + .up_es_vstep (up_es_vstep), + .up_es_vmax (up_es_vmax), + .up_es_vmin (up_es_vmin), + .up_es_hmax (up_es_hmax), + .up_es_hmin (up_es_hmin), + .up_es_hstep (up_es_hstep), + .up_es_saddr (up_es_saddr), + .up_es_status (up_es_status), + .up_status (up_status), + .up_pll_rst (up_pll_rst), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata), + .up_rack (up_rack)); + + up_axi #(.ADDRESS_WIDTH (10)) i_axi ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_axi_awvalid (s_axi_awvalid), + .up_axi_awaddr (s_axi_awaddr), + .up_axi_awready (s_axi_awready), + .up_axi_wvalid (s_axi_wvalid), + .up_axi_wdata (s_axi_wdata), + .up_axi_wstrb (s_axi_wstrb), + .up_axi_wready (s_axi_wready), + .up_axi_bvalid (s_axi_bvalid), + .up_axi_bresp (s_axi_bresp), + .up_axi_bready (s_axi_bready), + .up_axi_arvalid (s_axi_arvalid), + .up_axi_araddr (s_axi_araddr), + .up_axi_arready (s_axi_arready), + .up_axi_rvalid (s_axi_rvalid), + .up_axi_rresp (s_axi_rresp), + .up_axi_rdata (s_axi_rdata), + .up_axi_rready (s_axi_rready), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata), + .up_rack (up_rack)); + +endmodule + +// *************************************************************************** +// *************************************************************************** + diff --git a/library/xilinx/axi_adxcvr/axi_adxcvr_es.v b/library/xilinx/axi_adxcvr/axi_adxcvr_es.v new file mode 100644 index 000000000..eaff6065e --- /dev/null +++ b/library/xilinx/axi_adxcvr/axi_adxcvr_es.v @@ -0,0 +1,567 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_adxcvr_es ( + + // up interface + + input up_rstn, + input up_clk, + output up_es_enb, + output [11:0] up_es_addr, + output up_es_wr, + output [15:0] up_es_wdata, + input [15:0] up_es_rdata, + input up_es_ready, + input up_ch_lpm_dfe_n, + input up_es_req, + output up_es_ack, + input [ 4:0] up_es_pscale, + input [ 1:0] up_es_vrange, + input [ 7:0] up_es_vstep, + input [ 7:0] up_es_vmax, + input [ 7:0] up_es_vmin, + input [11:0] up_es_hmax, + input [11:0] up_es_hmin, + input [11:0] up_es_hstep, + input [31:0] up_es_saddr, + output up_es_status, + + // axi interface + + output up_axi_awvalid, + output [31:0] up_axi_awaddr, + output [ 2:0] up_axi_awprot, + input up_axi_awready, + output up_axi_wvalid, + output [31:0] up_axi_wdata, + output [ 3:0] up_axi_wstrb, + input up_axi_wready, + input up_axi_bvalid, + input [ 1:0] up_axi_bresp, + output up_axi_bready, + output up_axi_arvalid, + output [31:0] up_axi_araddr, + output [ 2:0] up_axi_arprot, + input up_axi_arready, + input up_axi_rvalid, + input [31:0] up_axi_rdata, + input [ 1:0] up_axi_rresp, + output up_axi_rready); + + // parameters + + parameter integer GTH_OR_GTX_N = 0; + parameter integer TX_OR_RX_N = 0; + + // addresses + + localparam [11:0] ES_DRP_CTRL_ADDR = (GTH_OR_GTX_N == 1) ? 12'h03c : 12'h03d; // GTH-7 12'h03d + localparam [11:0] ES_DRP_HOFFSET_ADDR = (GTH_OR_GTX_N == 1) ? 12'h04f : 12'h03c; // GTH-7 12'h03c + localparam [11:0] ES_DRP_VOFFSET_ADDR = (GTH_OR_GTX_N == 1) ? 12'h097 : 12'h03b; // GTH-7 12'h03b + localparam [11:0] ES_DRP_STATUS_ADDR = (GTH_OR_GTX_N == 1) ? 12'h153 : 12'h151; // GTH-7 12'h153 + localparam [11:0] ES_DRP_SCNT_ADDR = (GTH_OR_GTX_N == 1) ? 12'h152 : 12'h150; // GTH-7 12'h152 + localparam [11:0] ES_DRP_ECNT_ADDR = (GTH_OR_GTX_N == 1) ? 12'h151 : 12'h14f; // GTH-7 12'h151 + + // fsm-states + + localparam [ 4:0] ES_FSM_IDLE = 6'h00; + localparam [ 4:0] ES_FSM_HOFFSET_READ = 6'h01; + localparam [ 4:0] ES_FSM_HOFFSET_RRDY = 6'h02; + localparam [ 4:0] ES_FSM_HOFFSET_WRITE = 6'h03; + localparam [ 4:0] ES_FSM_HOFFSET_WRDY = 6'h04; + localparam [ 4:0] ES_FSM_VOFFSET_READ = 6'h05; + localparam [ 4:0] ES_FSM_VOFFSET_RRDY = 6'h06; + localparam [ 4:0] ES_FSM_VOFFSET_WRITE = 6'h07; + localparam [ 4:0] ES_FSM_VOFFSET_WRDY = 6'h08; + localparam [ 4:0] ES_FSM_CTRL_READ = 6'h09; + localparam [ 4:0] ES_FSM_CTRL_RRDY = 6'h0a; + localparam [ 4:0] ES_FSM_START_WRITE = 6'h0b; + localparam [ 4:0] ES_FSM_START_WRDY = 6'h0c; + localparam [ 4:0] ES_FSM_STATUS_READ = 6'h0d; + localparam [ 4:0] ES_FSM_STATUS_RRDY = 6'h0e; + localparam [ 4:0] ES_FSM_STOP_WRITE = 6'h0f; + localparam [ 4:0] ES_FSM_STOP_WRDY = 6'h10; + localparam [ 4:0] ES_FSM_SCNT_READ = 6'h11; + localparam [ 4:0] ES_FSM_SCNT_RRDY = 6'h12; + localparam [ 4:0] ES_FSM_ECNT_READ = 6'h13; + localparam [ 4:0] ES_FSM_ECNT_RRDY = 6'h14; + localparam [ 4:0] ES_FSM_AXI_WRITE = 6'h15; + localparam [ 4:0] ES_FSM_AXI_READY = 6'h16; + localparam [ 4:0] ES_FSM_UPDATE = 6'h17; + + // internal registers + + reg up_awvalid = 'd0; + reg [31:0] up_awaddr = 'd0; + reg up_wvalid = 'd0; + reg [31:0] up_wdata = 'd0; + reg up_status = 'd0; + reg up_ut = 'd0; + reg [31:0] up_daddr = 'd0; + reg [11:0] up_hindex = 'd0; + reg [ 7:0] up_vindex = 'd0; + reg [15:0] up_hdata = 'd0; + reg [15:0] up_vdata = 'd0; + reg [15:0] up_cdata = 'd0; + reg [15:0] up_sdata = 'd0; + reg [15:0] up_edata = 'd0; + reg up_req_d = 'd0; + reg up_ack = 'd0; + reg [ 4:0] up_fsm = 'd0; + reg up_enb = 'd0; + reg [11:0] up_addr = 'd0; + reg up_wr = 'd0; + reg [15:0] up_data = 'd0; + + // internal signals + + wire up_heos_s; + wire up_eos_s; + wire up_ut_s; + wire [ 7:0] up_vindex_m_s; + wire [ 7:0] up_vindex_n_s; + wire [ 7:0] up_vindex_s; + wire up_start_s; + + // axi interface + + generate + if (TX_OR_RX_N == 1) begin + assign up_axi_awvalid = 1'b0; + assign up_axi_awaddr = 32'd0; + assign up_axi_awprot = 3'd0; + assign up_axi_wvalid = 1'b0; + assign up_axi_wdata = 32'd0; + assign up_axi_wstrb = 4'hf; + assign up_axi_bready = 1'b1; + assign up_axi_arvalid = 1'b0; + assign up_axi_araddr = 32'd0; + assign up_axi_arprot = 3'd0; + assign up_axi_rready = 1'b1; + end else begin + assign up_axi_awvalid = up_awvalid; + assign up_axi_awaddr = up_awaddr; + assign up_axi_awprot = 3'd0; + assign up_axi_wvalid = up_wvalid; + assign up_axi_wdata = up_wdata; + assign up_axi_wstrb = 4'hf; + assign up_axi_bready = 1'b1; + assign up_axi_arvalid = 1'b0; + assign up_axi_araddr = 32'd0; + assign up_axi_arprot = 3'd0; + assign up_axi_rready = 1'b1; + end + endgenerate + + // reconfig interface + + generate + if (TX_OR_RX_N == 1) begin + assign up_es_ack = 1'b1; + assign up_es_enb = 1'b0; + assign up_es_addr = 12'd0; + assign up_es_wr = 1'd0; + assign up_es_wdata = 16'd0; + assign up_es_status = 1'd0; + end else begin + assign up_es_ack = up_ack; + assign up_es_enb = up_enb; + assign up_es_addr = up_addr; + assign up_es_wr = up_wr; + assign up_es_wdata = up_data; + assign up_es_status = up_status; + end + endgenerate + + // axi write + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_awvalid <= 'b0; + up_awaddr <= 'd0; + up_wvalid <= 'b0; + up_wdata <= 'd0; + up_status <= 'd0; + end else begin + if ((up_awvalid == 1'b1) && (up_axi_awready == 1'b1)) begin + up_awvalid <= 1'b0; + up_awaddr <= 32'd0; + end else if (up_fsm == ES_FSM_AXI_WRITE) begin + up_awvalid <= 1'b1; + up_awaddr <= up_daddr; + end + if ((up_wvalid == 1'b1) && (up_axi_wready == 1'b1)) begin + up_wvalid <= 1'b0; + up_wdata <= 32'd0; + end else if (up_fsm == ES_FSM_AXI_WRITE) begin + up_wvalid <= 1'b1; + up_wdata <= {up_sdata, up_edata}; + end + if (up_axi_bvalid == 1'b1) begin + up_status <= | up_axi_bresp; + end + end + end + + // prescale, horizontal and vertical offsets + + assign up_heos_s = (up_hindex == up_es_hmax) ? up_ut : 1'b0; + assign up_eos_s = (up_vindex == up_es_vmax) ? up_heos_s : 1'b0; + + assign up_ut_s = up_ut & ~up_ch_lpm_dfe_n; + assign up_vindex_m_s = ~up_vindex + 1'b1; + assign up_vindex_n_s = {1'b1, up_vindex_m_s[6:0]}; + assign up_vindex_s = (up_vindex[7] == 1'b1) ? up_vindex_n_s : up_vindex; + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 1'b0) begin + up_ut <= 'd0; + up_daddr <= 'd0; + up_hindex <= 'd0; + up_vindex <= 'd0; + end else begin + if (up_fsm == ES_FSM_IDLE) begin + up_ut <= up_ch_lpm_dfe_n; + up_daddr <= up_es_saddr; + up_hindex <= up_es_hmin; + up_vindex <= up_es_vmin; + end else if (up_fsm == ES_FSM_UPDATE) begin + up_ut <= ~up_ut | up_ch_lpm_dfe_n; + up_daddr <= up_daddr + 3'd4; + if (up_heos_s == 1'b1) begin + up_hindex <= up_es_hmin; + end else if (up_ut == 1'b1) begin + up_hindex <= up_hindex + up_es_hstep; + end + if (up_heos_s == 1'b1) begin + up_vindex <= up_vindex + up_es_vstep; + end + end + end + end + + // read-modify-write + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 1'b0) begin + up_hdata <= 'd0; + up_vdata <= 'd0; + up_cdata <= 'd0; + up_sdata <= 'd0; + up_edata <= 'd0; + end else begin + if ((up_fsm == ES_FSM_HOFFSET_RRDY) && (up_es_ready == 1'b1)) begin + up_hdata <= up_es_rdata; + end + if ((up_fsm == ES_FSM_VOFFSET_RRDY) && (up_es_ready == 1'b1)) begin + up_vdata <= up_es_rdata; + end + if ((up_fsm == ES_FSM_CTRL_RRDY) && (up_es_ready == 1'b1)) begin + up_cdata <= up_es_rdata; + end + if ((up_fsm == ES_FSM_SCNT_RRDY) && (up_es_ready == 1'b1)) begin + up_sdata <= up_es_rdata; + end + if ((up_fsm == ES_FSM_ECNT_RRDY) && (up_es_ready == 1'b1)) begin + up_edata <= up_es_rdata; + end + end + end + + // request, start and ack + + assign up_start_s = up_es_req & ~up_req_d; + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 1'b0) begin + up_req_d <= 1'b0; + up_ack <= 1'b0; + end else begin + up_req_d <= up_es_req; + if (up_fsm == ES_FSM_UPDATE) begin + up_ack <= up_eos_s | ~up_es_req; + end else begin + up_ack <= 1'b0; + end + end + end + + // es-fsm + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 1'b0) begin + up_fsm <= ES_FSM_IDLE; + end else begin + case (up_fsm) + ES_FSM_IDLE: begin + if (up_start_s == 1'b1) begin + up_fsm <= ES_FSM_HOFFSET_READ; + end else begin + up_fsm <= ES_FSM_IDLE; + end + end + ES_FSM_HOFFSET_READ: begin + up_fsm <= ES_FSM_HOFFSET_RRDY; + end + ES_FSM_HOFFSET_RRDY: begin + if (up_es_ready == 1'b1) begin + up_fsm <= ES_FSM_HOFFSET_WRITE; + end else begin + up_fsm <= ES_FSM_HOFFSET_RRDY; + end + end + ES_FSM_HOFFSET_WRITE: begin + up_fsm <= ES_FSM_HOFFSET_WRDY; + end + ES_FSM_HOFFSET_WRDY: begin + if (up_es_ready == 1'b1) begin + up_fsm <= ES_FSM_VOFFSET_READ; + end else begin + up_fsm <= ES_FSM_HOFFSET_WRDY; + end + end + ES_FSM_VOFFSET_READ: begin + up_fsm <= ES_FSM_VOFFSET_RRDY; + end + ES_FSM_VOFFSET_RRDY: begin + if (up_es_ready == 1'b1) begin + up_fsm <= ES_FSM_VOFFSET_WRITE; + end else begin + up_fsm <= ES_FSM_VOFFSET_RRDY; + end + end + ES_FSM_VOFFSET_WRITE: begin + up_fsm <= ES_FSM_VOFFSET_WRDY; + end + ES_FSM_VOFFSET_WRDY: begin + if (up_es_ready == 1'b1) begin + up_fsm <= ES_FSM_CTRL_READ; + end else begin + up_fsm <= ES_FSM_VOFFSET_WRDY; + end + end + ES_FSM_CTRL_READ: begin + up_fsm <= ES_FSM_CTRL_RRDY; + end + ES_FSM_CTRL_RRDY: begin + if (up_es_ready == 1'b1) begin + up_fsm <= ES_FSM_START_WRITE; + end else begin + up_fsm <= ES_FSM_CTRL_RRDY; + end + end + ES_FSM_START_WRITE: begin + up_fsm <= ES_FSM_START_WRDY; + end + ES_FSM_START_WRDY: begin + if (up_es_ready == 1'b1) begin + up_fsm <= ES_FSM_STATUS_READ; + end else begin + up_fsm <= ES_FSM_START_WRDY; + end + end + ES_FSM_STATUS_READ: begin + up_fsm <= ES_FSM_STATUS_RRDY; + end + ES_FSM_STATUS_RRDY: begin + if (up_es_ready == 1'b0) begin + up_fsm <= ES_FSM_STATUS_RRDY; + end else if (up_es_rdata[3:0] == 4'b0101) begin + up_fsm <= ES_FSM_STOP_WRITE; + end else begin + up_fsm <= ES_FSM_STATUS_READ; + end + end + ES_FSM_STOP_WRITE: begin + up_fsm <= ES_FSM_STOP_WRDY; + end + ES_FSM_STOP_WRDY: begin + if (up_es_ready == 1'b1) begin + up_fsm <= ES_FSM_SCNT_READ; + end else begin + up_fsm <= ES_FSM_STOP_WRDY; + end + end + ES_FSM_SCNT_READ: begin + up_fsm <= ES_FSM_SCNT_RRDY; + end + ES_FSM_SCNT_RRDY: begin + if (up_es_ready == 1'b1) begin + up_fsm <= ES_FSM_ECNT_READ; + end else begin + up_fsm <= ES_FSM_SCNT_RRDY; + end + end + ES_FSM_ECNT_READ: begin + up_fsm <= ES_FSM_ECNT_RRDY; + end + ES_FSM_ECNT_RRDY: begin + if (up_es_ready == 1'b1) begin + up_fsm <= ES_FSM_AXI_WRITE; + end else begin + up_fsm <= ES_FSM_ECNT_RRDY; + end + end + ES_FSM_AXI_WRITE: begin + up_fsm <= ES_FSM_AXI_READY; + end + ES_FSM_AXI_READY: begin + if (up_axi_bvalid == 1'b1) begin + up_fsm <= ES_FSM_UPDATE; + end else begin + up_fsm <= ES_FSM_AXI_READY; + end + end + ES_FSM_UPDATE: begin + if ((up_eos_s == 1'b1) || (up_es_req == 1'b0)) begin + up_fsm <= ES_FSM_IDLE; + end else if (up_ut == 1'b1) begin + up_fsm <= ES_FSM_HOFFSET_READ; + end else begin + up_fsm <= ES_FSM_VOFFSET_READ; + end + end + default: begin + up_fsm <= ES_FSM_IDLE; + end + endcase + end + end + + // channel access + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 1'b0) begin + up_enb <= 'd0; + up_addr <= 'd0; + up_wr <= 'd0; + up_data <= 'd0; + end else begin + case (up_fsm) + ES_FSM_HOFFSET_READ: begin + up_enb <= 1'b1; + up_addr <= ES_DRP_HOFFSET_ADDR; + up_wr <= 1'b0; + up_data <= 16'h0000; + end + ES_FSM_HOFFSET_WRITE: begin + up_enb <= 1'b1; + up_addr <= ES_DRP_HOFFSET_ADDR; + up_wr <= 1'b1; + if (GTH_OR_GTX_N == 1) begin + up_data <= {up_hindex, up_hdata[3:0]}; + end else begin + up_data <= {up_hdata[15:12], up_hindex}; + end + end + ES_FSM_VOFFSET_READ: begin + up_enb <= 1'b1; + up_addr <= ES_DRP_VOFFSET_ADDR; + up_wr <= 1'b0; + up_data <= 16'h0000; + end + ES_FSM_VOFFSET_WRITE: begin + up_enb <= 1'b1; + up_addr <= ES_DRP_VOFFSET_ADDR; + up_wr <= 1'b1; + if (GTH_OR_GTX_N == 1) begin + up_data <= {up_vdata[15:11], up_vindex_s[7], up_ut_s, up_vindex_s[6:0], up_es_vrange}; + end else begin + up_data <= {up_es_pscale, up_vdata[10:9], up_ut_s, up_vindex_s}; + end + end + ES_FSM_CTRL_READ: begin + up_enb <= 1'b1; + up_addr <= ES_DRP_CTRL_ADDR; + up_wr <= 1'b0; + up_data <= 16'h0000; + end + ES_FSM_START_WRITE: begin + up_enb <= 1'b1; + up_addr <= ES_DRP_CTRL_ADDR; + up_wr <= 1'b1; + if (GTH_OR_GTX_N == 1) begin + up_data <= {6'd1, 2'b11, up_cdata[7:5], up_es_pscale}; + end else begin + up_data <= {up_cdata[15:10], 2'b11, up_cdata[7:6], 6'd1}; + end + end + ES_FSM_STATUS_READ: begin + up_enb <= 1'b1; + up_addr <= ES_DRP_STATUS_ADDR; + up_wr <= 1'b0; + up_data <= 16'h0000; + end + ES_FSM_STOP_WRITE: begin + up_enb <= 1'b1; + up_addr <= ES_DRP_CTRL_ADDR; + up_wr <= 1'b1; + if (GTH_OR_GTX_N == 1) begin + up_data <= {6'd0, 2'b11, up_cdata[7:5], up_es_pscale}; + end else begin + up_data <= {up_cdata[15:10], 2'b11, up_cdata[7:6], 6'd0}; + end + end + ES_FSM_SCNT_READ: begin + up_enb <= 1'b1; + up_addr <= ES_DRP_SCNT_ADDR; + up_wr <= 1'b0; + up_data <= 16'h0000; + end + ES_FSM_ECNT_READ: begin + up_enb <= 1'b1; + up_addr <= ES_DRP_ECNT_ADDR; + up_wr <= 1'b0; + up_data <= 16'h0000; + end + default: begin + up_enb <= 1'b0; + up_addr <= 9'h000; + up_wr <= 1'b0; + up_data <= 16'h0000; + end + endcase + end + end + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/library/xilinx/axi_adxcvr/axi_adxcvr_ip.tcl b/library/xilinx/axi_adxcvr/axi_adxcvr_ip.tcl new file mode 100644 index 000000000..5ca8237ed --- /dev/null +++ b/library/xilinx/axi_adxcvr/axi_adxcvr_ip.tcl @@ -0,0 +1,221 @@ +## AUTO GENERATED BY axi_adxcvr.pl, DO NOT MODIFY! + +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip.tcl + +adi_ip_create axi_adxcvr +adi_ip_files axi_adxcvr [list \ + "$ad_hdl_dir/library/common/up_axi.v" \ + "axi_adxcvr_es.v" \ + "axi_adxcvr_up.v" \ + "axi_adxcvr_mdrp.v" \ + "axi_adxcvr_mstatus.v" \ + "axi_adxcvr.v" ] + +adi_ip_properties axi_adxcvr +adi_ip_infer_mm_interfaces axi_adxcvr + +set_property driver_value 0 [ipx::get_ports -filter "direction==in" -of_objects [ipx::current_core]] + +set_property master_address_space_ref m_axi \ + [ipx::get_bus_interfaces m_axi \ + -of_objects [ipx::current_core]] + +for {set n 0} {$n < 16} {incr n} { + + if {($n%4) == 0} { + adi_if_infer_bus ADI:user:if_xcvr_cm master up_cm_${n} [list \ + "sel up_cm_sel_${n} "\ + "enb up_cm_enb_${n} "\ + "addr up_cm_addr_${n} "\ + "wr up_cm_wr_${n} "\ + "wdata up_cm_wdata_${n} "\ + "rdata up_cm_rdata_${n} "\ + "ready up_cm_ready_${n} "] + } + + adi_if_infer_bus ADI:user:if_xcvr_cm master up_es_${n} [list \ + "sel up_es_sel_${n} "\ + "enb up_es_enb_${n} "\ + "addr up_es_addr_${n} "\ + "wr up_es_wr_${n} "\ + "wdata up_es_wdata_${n} "\ + "rdata up_es_rdata_${n} "\ + "ready up_es_ready_${n} "] + + adi_if_infer_bus ADI:user:if_xcvr_ch master up_ch_${n} [list \ + "pll_locked up_ch_pll_locked_${n} "\ + "rst up_ch_rst_${n} "\ + "user_ready up_ch_user_ready_${n} "\ + "rst_done up_ch_rst_done_${n} "\ + "lpm_dfe_n up_ch_lpm_dfe_n_${n} "\ + "rate up_ch_rate_${n} "\ + "sys_clk_sel up_ch_sys_clk_sel_${n} "\ + "out_clk_sel up_ch_out_clk_sel_${n} "\ + "sel up_ch_sel_${n} "\ + "enb up_ch_enb_${n} "\ + "addr up_ch_addr_${n} "\ + "wr up_ch_wr_${n} "\ + "wdata up_ch_wdata_${n} "\ + "rdata up_ch_rdata_${n} "\ + "ready up_ch_ready_${n} "] + +} + +set_property value s_axi:m_axi [ipx::get_bus_parameters ASSOCIATED_BUSIF \ + -of_objects [ipx::get_bus_interfaces s_axi_aclk -of_objects [ipx::current_core]]] + +set_property enablement_dependency \ + {spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0} \ + [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \ + (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 0))} \ + [ipx::get_bus_interfaces up_es_0 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 0} \ + [ipx::get_bus_interfaces up_ch_0 -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {((spirit:decode(id('MODELPARAM_VALUE.QPLL_ENABLE')) = 1) and \ + (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 0))} \ + [ipx::get_bus_interfaces up_cm_0 -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \ + (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 1))} \ + [ipx::get_bus_interfaces up_es_1 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 1} \ + [ipx::get_bus_interfaces up_ch_1 -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \ + (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 2))} \ + [ipx::get_bus_interfaces up_es_2 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 2} \ + [ipx::get_bus_interfaces up_ch_2 -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \ + (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 3))} \ + [ipx::get_bus_interfaces up_es_3 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 3} \ + [ipx::get_bus_interfaces up_ch_3 -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \ + (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 4))} \ + [ipx::get_bus_interfaces up_es_4 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 4} \ + [ipx::get_bus_interfaces up_ch_4 -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {((spirit:decode(id('MODELPARAM_VALUE.QPLL_ENABLE')) = 1) and \ + (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 4))} \ + [ipx::get_bus_interfaces up_cm_4 -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \ + (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 5))} \ + [ipx::get_bus_interfaces up_es_5 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 5} \ + [ipx::get_bus_interfaces up_ch_5 -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \ + (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 6))} \ + [ipx::get_bus_interfaces up_es_6 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 6} \ + [ipx::get_bus_interfaces up_ch_6 -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \ + (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 7))} \ + [ipx::get_bus_interfaces up_es_7 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 7} \ + [ipx::get_bus_interfaces up_ch_7 -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \ + (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 8))} \ + [ipx::get_bus_interfaces up_es_8 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 8} \ + [ipx::get_bus_interfaces up_ch_8 -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {((spirit:decode(id('MODELPARAM_VALUE.QPLL_ENABLE')) = 1) and \ + (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 8))} \ + [ipx::get_bus_interfaces up_cm_8 -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \ + (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 9))} \ + [ipx::get_bus_interfaces up_es_9 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 9} \ + [ipx::get_bus_interfaces up_ch_9 -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \ + (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 10))} \ + [ipx::get_bus_interfaces up_es_10 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 10} \ + [ipx::get_bus_interfaces up_ch_10 -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \ + (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 11))} \ + [ipx::get_bus_interfaces up_es_11 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 11} \ + [ipx::get_bus_interfaces up_ch_11 -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \ + (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 12))} \ + [ipx::get_bus_interfaces up_es_12 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 12} \ + [ipx::get_bus_interfaces up_ch_12 -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {((spirit:decode(id('MODELPARAM_VALUE.QPLL_ENABLE')) = 1) and \ + (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 12))} \ + [ipx::get_bus_interfaces up_cm_12 -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \ + (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 13))} \ + [ipx::get_bus_interfaces up_es_13 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 13} \ + [ipx::get_bus_interfaces up_ch_13 -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \ + (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 14))} \ + [ipx::get_bus_interfaces up_es_14 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 14} \ + [ipx::get_bus_interfaces up_ch_14 -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \ + (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 15))} \ + [ipx::get_bus_interfaces up_es_15 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 15} \ + [ipx::get_bus_interfaces up_ch_15 -of_objects [ipx::current_core]] + +ipx::save_core [ipx::current_core] + diff --git a/library/xilinx/axi_adxcvr/axi_adxcvr_mdrp.v b/library/xilinx/axi_adxcvr/axi_adxcvr_mdrp.v new file mode 100644 index 000000000..4ec6d2db0 --- /dev/null +++ b/library/xilinx/axi_adxcvr/axi_adxcvr_mdrp.v @@ -0,0 +1,161 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/1ps + +module axi_adxcvr_mdrp ( + + input up_rstn, + input up_clk, + + input [ 7:0] up_sel, + input up_enb, + input [15:0] up_rdata_in, + input up_ready_in, + input [15:0] up_rdata, + input up_ready, + output [15:0] up_rdata_out, + output up_ready_out); + + // parameters + + parameter integer XCVR_ID = 0; + parameter integer NUM_OF_LANES = 8; + + // internal registers + + reg [15:0] up_rdata_int = 'd0; + reg up_ready_int = 'd0; + reg up_ready_mi = 'd0; + reg [15:0] up_rdata_i = 'd0; + reg up_ready_i = 'd0; + reg [15:0] up_rdata_m = 'd0; + reg up_ready_m = 'd0; + + // internal signals + + wire up_ready_s; + wire [15:0] up_rdata_mi_s; + wire up_ready_mi_s; + + // disable if not selected + + assign up_rdata_out = up_rdata_int; + assign up_ready_out = up_ready_int; + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 1'b0) begin + up_rdata_int <= 16'd0; + up_ready_int <= 1'b0; + end else begin + case (up_sel) + 8'hff: begin + up_rdata_int <= up_rdata_mi_s; + up_ready_int <= up_ready_mi_s & ~up_ready_mi; + end + XCVR_ID: begin + up_rdata_int <= up_rdata; + up_ready_int <= up_ready; + end + default: begin + up_rdata_int <= up_rdata_in; + up_ready_int <= up_ready_in; + end + endcase + end + end + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 1'b0) begin + up_ready_mi <= 1'b0; + end else begin + up_ready_mi <= up_ready_mi_s; + end + end + + assign up_rdata_mi_s = up_rdata_m | up_rdata_i; + assign up_ready_mi_s = up_ready_m & up_ready_i; + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 1'b0) begin + up_rdata_i <= 16'd0; + up_ready_i <= 1'b0; + end else begin + if (up_ready_in == 1'b1) begin + up_rdata_i <= up_rdata_in; + up_ready_i <= 1'b1; + end else if (up_enb == 1'b1) begin + up_rdata_i <= 16'd0; + up_ready_i <= 1'b0; + end + end + end + + generate + if (XCVR_ID < NUM_OF_LANES) begin + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 1'b0) begin + up_rdata_m <= 16'd0; + up_ready_m <= 1'b0; + end else begin + if (up_ready == 1'b1) begin + up_rdata_m <= up_rdata; + up_ready_m <= 1'b1; + end else if (up_enb == 1'b1) begin + up_rdata_m <= 16'd0; + up_ready_m <= 1'b0; + end + end + end + end else begin + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 1'b0) begin + up_rdata_m <= 16'd0; + up_ready_m <= 1'b0; + end else begin + up_rdata_m <= 16'd0; + up_ready_m <= 1'b1; + end + end + end + endgenerate + +endmodule + +// *************************************************************************** +// *************************************************************************** + diff --git a/library/xilinx/axi_adxcvr/axi_adxcvr_mstatus.v b/library/xilinx/axi_adxcvr/axi_adxcvr_mstatus.v new file mode 100644 index 000000000..2319886da --- /dev/null +++ b/library/xilinx/axi_adxcvr/axi_adxcvr_mstatus.v @@ -0,0 +1,89 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/1ps + +module axi_adxcvr_mstatus ( + + input up_rstn, + input up_clk, + + input up_pll_locked_in, + input up_rst_done_in, + input up_pll_locked, + input up_rst_done, + output up_pll_locked_out, + output up_rst_done_out); + + // parameters + + parameter integer XCVR_ID = 0; + parameter integer NUM_OF_LANES = 8; + + // internal registers + + reg up_pll_locked_int = 'd0; + reg up_rst_done_int = 'd0; + + // internal signals + + wire up_pll_locked_s; + wire up_rst_done_s; + + // daisy-chain the signals + + assign up_pll_locked_out = up_pll_locked_int; + assign up_rst_done_out = up_rst_done_int; + + assign up_pll_locked_s = (XCVR_ID < NUM_OF_LANES) ? up_pll_locked : 1'b1; + assign up_rst_done_s = (XCVR_ID < NUM_OF_LANES) ? up_rst_done : 1'b1; + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 1'b0) begin + up_pll_locked_int <= 1'd0; + up_rst_done_int <= 1'd0; + end else begin + up_pll_locked_int <= up_pll_locked_in & up_pll_locked_s; + up_rst_done_int <= up_rst_done_in & up_rst_done_s; + end + end + +endmodule + +// *************************************************************************** +// *************************************************************************** + diff --git a/library/xilinx/axi_adxcvr/axi_adxcvr_up.v b/library/xilinx/axi_adxcvr/axi_adxcvr_up.v new file mode 100644 index 000000000..650b79941 --- /dev/null +++ b/library/xilinx/axi_adxcvr/axi_adxcvr_up.v @@ -0,0 +1,504 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_adxcvr_up #( + + // parameters + + parameter integer ID = 0, + parameter integer NUM_OF_LANES = 8, + parameter integer GTH_OR_GTX_N = 0, + parameter integer TX_OR_RX_N = 0, + parameter integer QPLL_ENABLE = 1, + parameter LPM_OR_DFE_N = 1, + parameter [ 2:0] RATE = 3'd0, + parameter [ 1:0] SYS_CLK_SEL = 2'd3, + parameter [ 2:0] OUT_CLK_SEL = 3'd4) ( + + // common + + output [ 7:0] up_cm_sel, + output up_cm_enb, + output [11:0] up_cm_addr, + output up_cm_wr, + output [15:0] up_cm_wdata, + input [15:0] up_cm_rdata, + input up_cm_ready, + + // channel + + input up_ch_pll_locked, + output up_ch_rst, + output up_ch_user_ready, + input up_ch_rst_done, + output up_ch_lpm_dfe_n, + output [ 2:0] up_ch_rate, + output [ 1:0] up_ch_sys_clk_sel, + output [ 2:0] up_ch_out_clk_sel, + output [ 7:0] up_ch_sel, + output up_ch_enb, + output [11:0] up_ch_addr, + output up_ch_wr, + output [15:0] up_ch_wdata, + input [15:0] up_ch_rdata, + input up_ch_ready, + + // eye-scan + + output [ 7:0] up_es_sel, + output up_es_req, + input up_es_ack, + output [ 4:0] up_es_pscale, + output [ 1:0] up_es_vrange, + output [ 7:0] up_es_vstep, + output [ 7:0] up_es_vmax, + output [ 7:0] up_es_vmin, + output [11:0] up_es_hmax, + output [11:0] up_es_hmin, + output [11:0] up_es_hstep, + output [31:0] up_es_saddr, + input up_es_status, + + // status + + output up_status, + output up_pll_rst, + + // bus interface + + input up_rstn, + input up_clk, + input up_wreq, + input [ 9:0] up_waddr, + input [31:0] up_wdata, + output up_wack, + input up_rreq, + input [ 9:0] up_raddr, + output [31:0] up_rdata, + output up_rack); + + // parameters + + localparam [31:0] VERSION = 32'h00100161; + + // internal registers + + reg up_wreq_d = 'd0; + reg [31:0] up_scratch = 'd0; + reg up_resetn = 'd0; + reg [ 3:0] up_pll_rst_cnt = 'd0; + reg [ 3:0] up_rst_cnt = 'd0; + reg [ 6:0] up_user_ready_cnt = 'd0; + reg up_status_int = 'd0; + reg up_lpm_dfe_n = 'd0; + reg [ 2:0] up_rate = 'd0; + reg [ 1:0] up_sys_clk_sel = 'd0; + reg [ 2:0] up_out_clk_sel = 'd0; + reg [ 7:0] up_icm_sel = 'd0; + reg up_icm_enb = 'd0; + reg up_icm_wr = 'd0; + reg [28:0] up_icm_data = 'd0; + reg [15:0] up_icm_rdata = 'd0; + reg up_icm_busy = 'd0; + reg [ 7:0] up_ich_sel = 'd0; + reg up_ich_enb = 'd0; + reg up_ich_wr = 'd0; + reg [28:0] up_ich_data = 'd0; + reg [15:0] up_ich_rdata = 'd0; + reg up_ich_busy = 'd0; + reg [ 7:0] up_ies_sel = 'd0; + reg up_ies_req = 'd0; + reg [ 4:0] up_ies_prescale = 'd0; + reg [ 1:0] up_ies_voffset_range = 'd0; + reg [ 7:0] up_ies_voffset_step = 'd0; + reg [ 7:0] up_ies_voffset_max = 'd0; + reg [ 7:0] up_ies_voffset_min = 'd0; + reg [11:0] up_ies_hoffset_max = 'd0; + reg [11:0] up_ies_hoffset_min = 'd0; + reg [11:0] up_ies_hoffset_step = 'd0; + reg [31:0] up_ies_start_addr = 'd0; + reg up_ies_status = 'd0; + reg up_rreq_d = 'd0; + reg [31:0] up_rdata_d = 'd0; + + // internal signals + + wire [31:0] up_rparam_s; + + // defaults + + assign up_wack = up_wreq_d; + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_wreq_d <= 'd0; + up_scratch <= 'd0; + end else begin + up_wreq_d <= up_wreq; + if ((up_wreq == 1'b1) && (up_waddr == 10'h002)) begin + up_scratch <= up_wdata; + end + end + end + + // reset-controller + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_resetn <= 'd0; + end else begin + if ((up_wreq == 1'b1) && (up_waddr == 10'h004)) begin + up_resetn <= up_wdata[0]; + end + end + end + + assign up_pll_rst = up_pll_rst_cnt[3]; + assign up_ch_rst = up_rst_cnt[3]; + assign up_ch_user_ready = up_user_ready_cnt[6]; + assign up_status = up_status_int; + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_pll_rst_cnt <= 4'h8; + up_rst_cnt <= 4'h8; + up_user_ready_cnt <= 7'h00; + up_status_int <= 1'b0; + end else begin + if (up_resetn == 1'b0) begin + up_pll_rst_cnt <= 4'h8; + end else if (up_pll_rst_cnt[3] == 1'b1) begin + up_pll_rst_cnt <= up_pll_rst_cnt + 1'b1; + end + if ((up_resetn == 1'b0) || (up_pll_rst_cnt[3] == 1'b1) || + (up_ch_pll_locked == 1'b0)) begin + up_rst_cnt <= 4'h8; + end else if (up_rst_cnt[3] == 1'b1) begin + up_rst_cnt <= up_rst_cnt + 1'b1; + end + if ((up_resetn == 1'b0) || (up_rst_cnt[3] == 1'b1)) begin + up_user_ready_cnt <= 7'h00; + end else if (up_user_ready_cnt[6] == 1'b0) begin + up_user_ready_cnt <= up_user_ready_cnt + 1'b1; + end + if (up_resetn == 1'b0) begin + up_status_int <= 1'b0; + end else if (up_ch_rst_done == 1'b1) begin + up_status_int <= 1'b1; + end + end + end + + // control signals + + assign up_ch_lpm_dfe_n = up_lpm_dfe_n; + assign up_ch_rate = up_rate; + assign up_ch_sys_clk_sel = up_sys_clk_sel; + assign up_ch_out_clk_sel = up_out_clk_sel; + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_lpm_dfe_n <= LPM_OR_DFE_N; + up_rate <= RATE; + up_sys_clk_sel <= SYS_CLK_SEL; + up_out_clk_sel <= OUT_CLK_SEL; + end else begin + if ((up_wreq == 1'b1) && (up_waddr == 10'h008)) begin + up_lpm_dfe_n <= up_wdata[12]; + up_rate <= up_wdata[10:8]; + up_sys_clk_sel <= up_wdata[5:4]; + up_out_clk_sel <= up_wdata[2:0]; + end + end + end + + // common access + + assign up_cm_sel = up_icm_sel; + assign up_cm_enb = up_icm_enb; + assign up_cm_wr = up_icm_wr; + assign up_cm_addr = up_icm_data[27:16]; + assign up_cm_wdata = up_icm_data[15:0]; + + generate + if (QPLL_ENABLE == 0) begin + always @(posedge up_clk) begin + up_icm_sel <= 'd0; + up_icm_enb <= 'd0; + up_icm_wr <= 'd0; + up_icm_data <= 'd0; + up_icm_rdata <= 'd0; + up_icm_busy <= 'd0; + end + end else begin + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_icm_sel <= 'd0; + up_icm_enb <= 'd0; + up_icm_wr <= 'd0; + up_icm_data <= 'd0; + up_icm_rdata <= 'd0; + up_icm_busy <= 'd0; + end else begin + if ((up_wreq == 1'b1) && (up_waddr == 10'h010)) begin + up_icm_sel <= up_wdata[7:0]; + end + if ((up_wreq == 1'b1) && (up_waddr == 10'h011)) begin + up_icm_enb <= 1'b1; + up_icm_wr <= up_wdata[28]; + end else begin + up_icm_enb <= 1'b0; + up_icm_wr <= 1'b0; + end + if ((up_wreq == 1'b1) && (up_waddr == 10'h011)) begin + up_icm_data <= up_wdata[28:0]; + end + if (up_cm_ready == 1'b1) begin + up_icm_rdata <= up_cm_rdata; + up_icm_busy <= 1'b0; + end else if ((up_wreq == 1'b1) && (up_waddr == 10'h011)) begin + up_icm_rdata <= 16'd0; + up_icm_busy <= 1'b1; + end + end + end + end + endgenerate + + // channel access + + assign up_ch_sel = up_ich_sel; + assign up_ch_enb = up_ich_enb; + assign up_ch_wr = up_ich_wr; + assign up_ch_addr = up_ich_data[27:16]; + assign up_ch_wdata = up_ich_data[15:0]; + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_ich_sel <= 'd0; + up_ich_enb <= 'd0; + up_ich_wr <= 'd0; + up_ich_data <= 'd0; + up_ich_rdata <= 'd0; + up_ich_busy <= 'd0; + end else begin + if ((up_wreq == 1'b1) && (up_waddr == 10'h018)) begin + up_ich_sel <= up_wdata[7:0]; + end + if ((up_wreq == 1'b1) && (up_waddr == 10'h019)) begin + up_ich_enb <= 1'b1; + up_ich_wr <= up_wdata[28]; + end else begin + up_ich_enb <= 1'b0; + up_ich_wr <= 1'b0; + end + if ((up_wreq == 1'b1) && (up_waddr == 10'h019)) begin + up_ich_data <= up_wdata[28:0]; + end + if (up_ch_ready == 1'b1) begin + up_ich_rdata <= up_ch_rdata; + up_ich_busy <= 1'b0; + end else if ((up_wreq == 1'b1) && (up_waddr == 10'h019)) begin + up_ich_rdata <= 16'd0; + up_ich_busy <= 1'b1; + end + end + end + + // eye-scan + + assign up_es_sel = up_ies_sel; + assign up_es_req = up_ies_req; + assign up_es_pscale = up_ies_prescale; + assign up_es_vrange = up_ies_voffset_range; + assign up_es_vstep = up_ies_voffset_step; + assign up_es_vmax = up_ies_voffset_max; + assign up_es_vmin = up_ies_voffset_min; + assign up_es_hmax = up_ies_hoffset_max; + assign up_es_hmin = up_ies_hoffset_min; + assign up_es_hstep = up_ies_hoffset_step; + assign up_es_saddr = up_ies_start_addr; + + generate + if (TX_OR_RX_N == 1) begin + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_ies_sel <= 'd0; + up_ies_req <= 'd0; + up_ies_prescale <= 'd0; + up_ies_voffset_range <= 'd0; + up_ies_voffset_step <= 'd0; + up_ies_voffset_max <= 'd0; + up_ies_voffset_min <= 'd0; + up_ies_hoffset_max <= 'd0; + up_ies_hoffset_min <= 'd0; + up_ies_hoffset_step <= 'd0; + up_ies_start_addr <= 'd0; + up_ies_status <= 'd0; + end else begin + up_ies_sel <= 'd0; + up_ies_req <= 'd0; + up_ies_prescale <= 'd0; + up_ies_voffset_range <= 'd0; + up_ies_voffset_step <= 'd0; + up_ies_voffset_max <= 'd0; + up_ies_voffset_min <= 'd0; + up_ies_hoffset_max <= 'd0; + up_ies_hoffset_min <= 'd0; + up_ies_hoffset_step <= 'd0; + up_ies_start_addr <= 'd0; + up_ies_status <= 'd0; + end + end + end else begin + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_ies_sel <= 'd0; + up_ies_req <= 'd0; + up_ies_prescale <= 'd0; + up_ies_voffset_range <= 'd0; + up_ies_voffset_step <= 'd0; + up_ies_voffset_max <= 'd0; + up_ies_voffset_min <= 'd0; + up_ies_hoffset_max <= 'd0; + up_ies_hoffset_min <= 'd0; + up_ies_hoffset_step <= 'd0; + up_ies_start_addr <= 'd0; + up_ies_status <= 'd0; + end else begin + if ((up_wreq == 1'b1) && (up_waddr == 10'h020)) begin + up_ies_sel <= up_wdata[7:0]; + end + if (up_es_ack == 1'b1) begin + up_ies_req <= 1'b0; + end else if ((up_wreq == 1'b1) && (up_waddr == 10'h028)) begin + up_ies_req <= up_wdata[0]; + end + if ((up_wreq == 1'b1) && (up_waddr == 10'h029)) begin + up_ies_prescale <= up_wdata[4:0]; + end + if ((up_wreq == 1'b1) && (up_waddr == 10'h02a)) begin + up_ies_voffset_range <= up_wdata[25:24]; + up_ies_voffset_step <= up_wdata[23:16]; + up_ies_voffset_max <= up_wdata[15:8]; + up_ies_voffset_min <= up_wdata[7:0]; + end + if ((up_wreq == 1'b1) && (up_waddr == 10'h02b)) begin + up_ies_hoffset_max <= up_wdata[27:16]; + up_ies_hoffset_min <= up_wdata[11:0]; + end + if ((up_wreq == 1'b1) && (up_waddr == 10'h02c)) begin + up_ies_hoffset_step <= up_wdata[11:0]; + end + if ((up_wreq == 1'b1) && (up_waddr == 10'h02d)) begin + up_ies_start_addr <= up_wdata; + end + if (up_es_status == 1'b1) begin + up_ies_status <= 1'b1; + end else if ((up_wreq == 1'b1) && (up_waddr == 10'h02e)) begin + up_ies_status <= up_ies_status & ~up_wdata[0]; + end + end + end + end + endgenerate + + // read interface + + assign up_rack = up_rreq_d; + assign up_rdata = up_rdata_d; + + // altera specific + + assign up_rparam_s[31:24] = 8'd0; + + // xilinx specific + + assign up_rparam_s[23:21] = 3'd0; + assign up_rparam_s[20:20] = (QPLL_ENABLE == 0) ? 1'b0 : 1'b1; + assign up_rparam_s[19:16] = (GTH_OR_GTX_N == 0) ? 1'b0 : 1'b1; + + // generic + + assign up_rparam_s[15: 9] = 7'd0; + assign up_rparam_s[ 8: 8] = (TX_OR_RX_N == 0) ? 1'b0 : 1'b1; + assign up_rparam_s[ 7: 0] = NUM_OF_LANES; + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_rreq_d <= 'd0; + up_rdata_d <= 'd0; + end else begin + up_rreq_d <= up_rreq; + if (up_rreq == 1'b1) begin + case (up_raddr) + 10'h000: up_rdata_d <= VERSION; + 10'h001: up_rdata_d <= ID; + 10'h002: up_rdata_d <= up_scratch; + 10'h004: up_rdata_d <= {31'd0, up_resetn}; + 10'h005: up_rdata_d <= {31'd0, up_status_int}; + 10'h006: up_rdata_d <= {17'd0, up_user_ready_cnt, up_rst_cnt, up_pll_rst_cnt}; + 10'h008: up_rdata_d <= {19'd0, up_lpm_dfe_n, 1'd0, up_rate, 2'd0, up_sys_clk_sel, 1'd0, up_out_clk_sel}; + 10'h009: up_rdata_d <= up_rparam_s; + 10'h010: up_rdata_d <= {24'd0, up_icm_sel}; + 10'h011: up_rdata_d <= {3'd0, up_icm_data}; + 10'h012: up_rdata_d <= {15'd0, up_icm_busy, up_icm_rdata}; + 10'h018: up_rdata_d <= {24'd0, up_ich_sel}; + 10'h019: up_rdata_d <= {3'd0, up_ich_data}; + 10'h01a: up_rdata_d <= {15'd0, up_ich_busy, up_ich_rdata}; + 10'h020: up_rdata_d <= {24'd0, up_ies_sel}; + 10'h028: up_rdata_d <= {31'd0, up_ies_req}; + 10'h029: up_rdata_d <= {27'd0, up_ies_prescale}; + 10'h02a: up_rdata_d <= {6'd0, up_ies_voffset_range, up_ies_voffset_step, up_ies_voffset_max, up_ies_voffset_min}; + 10'h02b: up_rdata_d <= {4'd0, up_ies_hoffset_max, 4'd0, up_ies_hoffset_min}; + 10'h02c: up_rdata_d <= {20'd0, up_ies_hoffset_step}; + 10'h02d: up_rdata_d <= up_ies_start_addr; + 10'h02e: up_rdata_d <= {31'd0, up_es_status}; + default: up_rdata_d <= 32'd0; + endcase + end else begin + up_rdata_d <= 32'd0; + end + end + end + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/library/xilinx/axi_dacfifo/Makefile b/library/xilinx/axi_dacfifo/Makefile new file mode 100644 index 000000000..468a9e6d0 --- /dev/null +++ b/library/xilinx/axi_dacfifo/Makefile @@ -0,0 +1,54 @@ +#################################################################################### +#################################################################################### +## Copyright 2011(c) Analog Devices, Inc. +## Auto-generated, do not modify! +#################################################################################### +#################################################################################### + +M_DEPS += ../../common/ad_axis_inf_rx.v +M_DEPS += ../../common/ad_mem_asym.v +M_DEPS += ../../scripts/adi_env.tcl +M_DEPS += ../../scripts/adi_ip.tcl +M_DEPS += ../../util_axis_resize/util_axis_resize.v +M_DEPS += axi_dacfifo.v +M_DEPS += axi_dacfifo_constr.xdc +M_DEPS += axi_dacfifo_dac.v +M_DEPS += axi_dacfifo_ip.tcl +M_DEPS += axi_dacfifo_rd.v +M_DEPS += axi_dacfifo_wr.v +M_DEPS += axi_dacfifo_bypass.v + +M_VIVADO := vivado -mode batch -source + +M_FLIST := *.cache +M_FLIST += *.data +M_FLIST += *.xpr +M_FLIST += *.log +M_FLIST += component.xml +M_FLIST += *.jou +M_FLIST += xgui +M_FLIST += *.ip_user_files +M_FLIST += *.srcs +M_FLIST += *.hw +M_FLIST += *.sim +M_FLIST += .Xil + + + +.PHONY: all clean clean-all +all: axi_dacfifo.xpr + + +clean:clean-all + + +clean-all: + rm -rf $(M_FLIST) + + +axi_dacfifo.xpr: $(M_DEPS) + -rm -rf $(M_FLIST) + $(M_VIVADO) axi_dacfifo_ip.tcl >> axi_dacfifo_ip.log 2>&1 + +#################################################################################### +#################################################################################### diff --git a/library/xilinx/axi_dacfifo/axi_dacfifo.v b/library/xilinx/axi_dacfifo/axi_dacfifo.v new file mode 100644 index 000000000..c20632d85 --- /dev/null +++ b/library/xilinx/axi_dacfifo/axi_dacfifo.v @@ -0,0 +1,386 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2016(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_dacfifo ( + + // dma interface (AXI Stream) + + dma_clk, + dma_valid, + dma_data, + dma_ready, + dma_xfer_req, + dma_xfer_last, + + // dac interface + + dac_clk, + dac_rst, + dac_valid, + dac_data, + dac_dunf, + dac_xfer_out, + + bypass, + + // axi interface + + axi_clk, + axi_resetn, + axi_awvalid, + axi_awid, + axi_awburst, + axi_awlock, + axi_awcache, + axi_awprot, + axi_awqos, + axi_awuser, + axi_awlen, + axi_awsize, + axi_awaddr, + axi_awready, + axi_wvalid, + axi_wdata, + axi_wstrb, + axi_wlast, + axi_wuser, + axi_wready, + axi_bvalid, + axi_bid, + axi_bresp, + axi_buser, + axi_bready, + axi_arvalid, + axi_arid, + axi_arburst, + axi_arlock, + axi_arcache, + axi_arprot, + axi_arqos, + axi_aruser, + axi_arlen, + axi_arsize, + axi_araddr, + axi_arready, + axi_rvalid, + axi_rid, + axi_ruser, + axi_rresp, + axi_rlast, + axi_rdata, + axi_rready); + + // parameters + + parameter DAC_DATA_WIDTH = 64; + parameter DMA_DATA_WIDTH = 64; + parameter AXI_DATA_WIDTH = 512; + parameter AXI_SIZE = 2; + parameter AXI_LENGTH = 15; + parameter AXI_ADDRESS = 32'h00000000; + parameter AXI_ADDRESS_LIMIT = 32'hffffffff; + + localparam FIFO_BYPASS = (DAC_DATA_WIDTH == DMA_DATA_WIDTH) ? 1 : 0; + + // dma interface + + input dma_clk; + input dma_valid; + input [(DMA_DATA_WIDTH-1):0] dma_data; + output dma_ready; + input dma_xfer_req; + input dma_xfer_last; + + // dac interface + + input dac_clk; + input dac_rst; + input dac_valid; + output [(DAC_DATA_WIDTH-1):0] dac_data; + output dac_dunf; + output dac_xfer_out; + + input bypass; + + // axi interface + + input axi_clk; + input axi_resetn; + output axi_awvalid; + output [ 3:0] axi_awid; + output [ 1:0] axi_awburst; + output axi_awlock; + output [ 3:0] axi_awcache; + output [ 2:0] axi_awprot; + output [ 3:0] axi_awqos; + output [ 3:0] axi_awuser; + output [ 7:0] axi_awlen; + output [ 2:0] axi_awsize; + output [ 31:0] axi_awaddr; + input axi_awready; + output axi_wvalid; + output [(AXI_DATA_WIDTH-1):0] axi_wdata; + output [(AXI_DATA_WIDTH/8-1):0] axi_wstrb; + output axi_wlast; + output [ 3:0] axi_wuser; + input axi_wready; + input axi_bvalid; + input [ 3:0] axi_bid; + input [ 1:0] axi_bresp; + input [ 3:0] axi_buser; + output axi_bready; + output axi_arvalid; + output [ 3:0] axi_arid; + output [ 1:0] axi_arburst; + output axi_arlock; + output [ 3:0] axi_arcache; + output [ 2:0] axi_arprot; + output [ 3:0] axi_arqos; + output [ 3:0] axi_aruser; + output [ 7:0] axi_arlen; + output [ 2:0] axi_arsize; + output [ 31:0] axi_araddr; + input axi_arready; + input axi_rvalid; + input [ 3:0] axi_rid; + input [ 3:0] axi_ruser; + input [ 1:0] axi_rresp; + input axi_rlast; + input [(AXI_DATA_WIDTH-1):0] axi_rdata; + output axi_rready; + + reg dma_ready = 1'b0; + reg dma_bypass_m1 = 1'b0; + reg dma_bypass = 1'b0; + reg dac_bypass_m1 = 1'b0; + reg dac_bypass = 1'b0; + reg dac_xfer_out = 1'b0; + reg dac_xfer_out_m1 = 1'b0; + reg dac_xfer_out_bypass = 1'b0; + reg dac_dunf = 1'b0; + reg [(DAC_DATA_WIDTH-1):0] dac_data = 'b0; + + // internal signals + + wire [(AXI_DATA_WIDTH-1):0] axi_rd_data_s; + wire axi_rd_ready_s; + wire axi_rd_valid_s; + wire axi_xfer_req_s; + wire [31:0] axi_last_addr_s; + wire [ 3:0] axi_last_beats_s; + wire axi_dlast_s; + wire [ 3:0] dma_last_beats_s; + wire [(DAC_DATA_WIDTH-1):0] dac_data_fifo_s; + wire [(DAC_DATA_WIDTH-1):0] dac_data_bypass_s; + wire dac_xfer_fifo_out_s; + wire dac_dunf_fifo_s; + wire dac_dunf_bypass_s; + wire dma_ready_wr_s; + + axi_dacfifo_wr #( + .AXI_DATA_WIDTH (AXI_DATA_WIDTH), + .DMA_DATA_WIDTH (DMA_DATA_WIDTH), + .AXI_SIZE (AXI_SIZE), + .AXI_LENGTH (AXI_LENGTH), + .AXI_ADDRESS (AXI_ADDRESS), + .AXI_ADDRESS_LIMIT (AXI_ADDRESS_LIMIT) + ) i_wr ( + .dma_clk (dma_clk), + .dma_data (dma_data), + .dma_ready (dma_ready), + .dma_ready_out (dma_ready_wr_s), + .dma_valid (dma_valid), + .dma_xfer_req (dma_xfer_req), + .dma_xfer_last (dma_xfer_last), + .dma_last_beats (dma_last_beats_s), + .axi_last_addr (axi_last_addr_s), + .axi_last_beats (axi_last_beats_s), + .axi_xfer_out (axi_xfer_req_s), + .axi_clk (axi_clk), + .axi_resetn (axi_resetn), + .axi_awvalid (axi_awvalid), + .axi_awid (axi_awid), + .axi_awburst (axi_awburst), + .axi_awlock (axi_awlock), + .axi_awcache (axi_awcache), + .axi_awprot (axi_awprot), + .axi_awqos (axi_awqos), + .axi_awuser (axi_awuser), + .axi_awlen (axi_awlen), + .axi_awsize (axi_awsize), + .axi_awaddr (axi_awaddr), + .axi_awready (axi_awready), + .axi_wvalid (axi_wvalid), + .axi_wdata (axi_wdata), + .axi_wstrb (axi_wstrb), + .axi_wlast (axi_wlast), + .axi_wuser (axi_wuser), + .axi_wready (axi_wready), + .axi_bvalid (axi_bvalid), + .axi_bid (axi_bid), + .axi_bresp (axi_bresp), + .axi_buser (axi_buser), + .axi_bready (axi_bready), + .axi_werror (axi_werror)); + + axi_dacfifo_rd #( + .AXI_DATA_WIDTH (AXI_DATA_WIDTH), + .AXI_SIZE (AXI_SIZE), + .AXI_LENGTH (AXI_LENGTH), + .AXI_ADDRESS (AXI_ADDRESS) + ) i_rd ( + .axi_xfer_req (axi_xfer_req_s), + .axi_last_raddr (axi_last_addr_s), + .axi_last_beats (axi_last_beats_s), + .axi_clk (axi_clk), + .axi_resetn (axi_resetn), + .axi_arvalid (axi_arvalid), + .axi_arid (axi_arid), + .axi_arburst (axi_arburst), + .axi_arlock (axi_arlock), + .axi_arcache (axi_arcache), + .axi_arprot (axi_arprot), + .axi_arqos (axi_arqos), + .axi_aruser (axi_aruser), + .axi_arlen (axi_arlen), + .axi_arsize (axi_arsize), + .axi_araddr (axi_araddr), + .axi_arready (axi_arready), + .axi_rvalid (axi_rvalid), + .axi_rid (axi_rid), + .axi_ruser (axi_ruser), + .axi_rresp (axi_rresp), + .axi_rlast (axi_rlast), + .axi_rdata (axi_rdata), + .axi_rready (axi_rready), + .axi_rerror (axi_rerror), + .axi_dvalid (axi_rd_valid_s), + .axi_ddata (axi_rd_data_s), + .axi_dready (axi_rd_ready_s), + .axi_dlast (axi_dlast_s)); + + axi_dacfifo_dac #( + .AXI_DATA_WIDTH (AXI_DATA_WIDTH), + .AXI_LENGTH(AXI_LENGTH), + .DAC_DATA_WIDTH (DAC_DATA_WIDTH) + ) i_dac ( + .axi_clk (axi_clk), + .axi_dvalid (axi_rd_valid_s), + .axi_ddata (axi_rd_data_s), + .axi_dready (axi_rd_ready_s), + .axi_dlast (axi_dlast_s), + .axi_xfer_req (axi_xfer_req_s), + .dma_last_beats (dma_last_beats_s), + .dac_clk (dac_clk), + .dac_rst (dac_rst), + .dac_valid (dac_valid), + .dac_data (dac_data_fifo_s), + .dac_xfer_out (dac_xfer_fifo_out_s), + .dac_dunf (dac_dunf_fifo_s)); + + // bypass logic -- supported if DAC_DATA_WIDTH == DMA_DATA_WIDTH + + generate + if (FIFO_BYPASS) begin + + axi_dacfifo_bypass #( + .DAC_DATA_WIDTH (DAC_DATA_WIDTH), + .DMA_DATA_WIDTH (DMA_DATA_WIDTH) + ) i_dacfifo_bypass ( + .dma_clk(dma_clk), + .dma_data(dma_data), + .dma_ready(dma_ready), + .dma_ready_out(dma_ready_bypass_s), + .dma_valid(dma_valid), + .dma_xfer_req(dma_xfer_req), + .dac_clk(dac_clk), + .dac_rst(dac_rst), + .dac_valid(dac_valid), + .dac_data(dac_data_bypass_s), + .dac_dunf(dac_dunf_bypass_s) + ); + + always @(posedge dma_clk) begin + dma_bypass_m1 <= bypass; + dma_bypass <= dma_bypass_m1; + end + + always @(posedge dac_clk) begin + dac_bypass_m1 <= bypass; + dac_bypass <= dac_bypass_m1; + dac_xfer_out_m1 <= dma_xfer_req; + dac_xfer_out_bypass <= dac_xfer_out_m1; + end + + // mux for the dma_ready + + always @(posedge dma_clk) begin + dma_ready <= (dma_bypass) ? dma_ready_wr_s : dma_ready_bypass_s; + end + + // mux for dac data + + always @(posedge dac_clk) begin + if (dac_valid) begin + dac_data <= (dac_bypass) ? dac_data_bypass_s : dac_data_fifo_s; + end + dac_xfer_out <= (dac_bypass) ? dac_xfer_out_bypass : dac_xfer_fifo_out_s; + dac_dunf <= (dac_bypass) ? dac_dunf_bypass_s : dac_dunf_fifo_s; + end + + end else begin /* if (~FIFO_BYPASS) */ + + always @(posedge dma_clk) begin + dma_ready <= dma_ready_wr_s; + end + always @(posedge dac_clk) begin + if (dac_valid) begin + dac_data <= dac_data_fifo_s; + end + dac_xfer_out <= dac_xfer_fifo_out_s; + dac_dunf <= dac_dunf_fifo_s; + end + + end + endgenerate + +endmodule + diff --git a/library/xilinx/axi_dacfifo/axi_dacfifo_bypass.v b/library/xilinx/axi_dacfifo/axi_dacfifo_bypass.v new file mode 100644 index 000000000..b4adeb401 --- /dev/null +++ b/library/xilinx/axi_dacfifo/axi_dacfifo_bypass.v @@ -0,0 +1,292 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2016(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_dacfifo_bypass #( + + parameter DAC_DATA_WIDTH = 64, + parameter DMA_DATA_WIDTH = 64) ( + + // dma fifo interface + + input dma_clk, + input [(DMA_DATA_WIDTH-1):0] dma_data, + input dma_ready, + output reg dma_ready_out, + input dma_valid, + + // request and syncronizaiton + + input dma_xfer_req, + + // dac fifo interface + + input dac_clk, + input dac_rst, + input dac_valid, + output reg [(DAC_DATA_WIDTH-1):0] dac_data, + output reg dac_dunf +); + + // suported ratios: 1:1 / 1:2 / 1:4 / 1:8 / 2:1 / 4:1 / 8:1 + + localparam MEM_RATIO = (DMA_DATA_WIDTH > DAC_DATA_WIDTH) ? DMA_DATA_WIDTH/DAC_DATA_WIDTH : + DAC_DATA_WIDTH/DMA_DATA_WIDTH; + localparam DAC_ADDRESS_WIDTH = 10; + localparam DMA_ADDRESS_WIDTH = (MEM_RATIO == 1) ? DAC_ADDRESS_WIDTH : + (MEM_RATIO == 2) ? ((DMA_DATA_WIDTH > DAC_DATA_WIDTH) ? (DAC_ADDRESS_WIDTH - 1) : (DAC_ADDRESS_WIDTH + 1)) : + (MEM_RATIO == 4) ? ((DMA_DATA_WIDTH > DAC_DATA_WIDTH) ? (DAC_ADDRESS_WIDTH - 2) : (DAC_ADDRESS_WIDTH + 2)) : + ((DMA_DATA_WIDTH > DAC_DATA_WIDTH) ? (DAC_ADDRESS_WIDTH - 3) : (DAC_ADDRESS_WIDTH + 3)); + localparam DMA_BUF_THRESHOLD_HI = {(DMA_ADDRESS_WIDTH){1'b1}} - 4; + localparam DAC_BUF_THRESHOLD_LO = 4; + + reg [(DMA_ADDRESS_WIDTH-1):0] dma_mem_waddr = 'd0; + reg [(DMA_ADDRESS_WIDTH-1):0] dma_mem_waddr_g = 'd0; + reg [(DAC_ADDRESS_WIDTH-1):0] dac_mem_raddr = 'd0; + reg [(DAC_ADDRESS_WIDTH-1):0] dac_mem_raddr_g = 'd0; + reg dma_rst_m1 = 1'b0; + reg dma_rst = 1'b0; + reg [DMA_ADDRESS_WIDTH-1:0] dma_mem_addr_diff = 1'b0; + reg [(DAC_ADDRESS_WIDTH-1):0] dma_mem_raddr_m1 = 1'b0; + reg [(DAC_ADDRESS_WIDTH-1):0] dma_mem_raddr_m2 = 1'b0; + reg [(DAC_ADDRESS_WIDTH-1):0] dma_mem_raddr = 1'b0; + reg [DAC_ADDRESS_WIDTH-1:0] dac_mem_addr_diff = 1'b0; + reg [(DMA_ADDRESS_WIDTH-1):0] dac_mem_waddr_m1 = 1'b0; + reg [(DMA_ADDRESS_WIDTH-1):0] dac_mem_waddr_m2 = 1'b0; + reg [(DMA_ADDRESS_WIDTH-1):0] dac_mem_waddr = 1'b0; + reg dac_mem_ready = 1'b0; + reg dac_xfer_out = 1'b0; + reg dac_xfer_out_m1 = 1'b0; + + // internal signals + + wire dma_mem_last_read_s; + wire [(DMA_ADDRESS_WIDTH):0] dma_mem_addr_diff_s; + wire [(DAC_ADDRESS_WIDTH):0] dac_mem_addr_diff_s; + wire [(DMA_ADDRESS_WIDTH-1):0] dma_mem_raddr_s; + wire [(DAC_ADDRESS_WIDTH-1):0] dac_mem_waddr_s; + wire dma_mem_wea_s; + wire dac_mem_rea_s; + wire [(DAC_DATA_WIDTH-1):0] dac_mem_rdata_s; + wire [DMA_ADDRESS_WIDTH:0] dma_address_diff_s; + wire [DAC_ADDRESS_WIDTH:0] dac_address_diff_s; + + // binary to grey conversion + + function [7:0] b2g; + input [7:0] b; + reg [7:0] g; + begin + g[7] = b[7]; + g[6] = b[7] ^ b[6]; + g[5] = b[6] ^ b[5]; + g[4] = b[5] ^ b[4]; + g[3] = b[4] ^ b[3]; + g[2] = b[3] ^ b[2]; + g[1] = b[2] ^ b[1]; + g[0] = b[1] ^ b[0]; + b2g = g; + end + endfunction + + // grey to binary conversion + + function [7:0] g2b; + input [7:0] g; + reg [7:0] b; + begin + b[7] = g[7]; + b[6] = b[7] ^ g[6]; + b[5] = b[6] ^ g[5]; + b[4] = b[5] ^ g[4]; + b[3] = b[4] ^ g[3]; + b[2] = b[3] ^ g[2]; + b[1] = b[2] ^ g[1]; + b[0] = b[1] ^ g[0]; + g2b = b; + end + endfunction + + // An asymmetric memory to transfer data from DMAC interface to DAC interface + + ad_mem_asym #( + .A_ADDRESS_WIDTH (DMA_ADDRESS_WIDTH), + .A_DATA_WIDTH (DMA_DATA_WIDTH), + .B_ADDRESS_WIDTH (DAC_ADDRESS_WIDTH), + .B_DATA_WIDTH (DAC_DATA_WIDTH)) + i_mem_asym ( + .clka (dma_clk), + .wea (dma_mem_wea_s), + .addra (dma_mem_waddr), + .dina (dma_data), + .clkb (dac_clk), + .addrb (dac_mem_raddr), + .doutb (dac_mem_rdata_s)); + + // dma reset is brought from dac domain + + always @(posedge dma_clk) begin + dma_rst_m1 <= dac_rst; + dma_rst <= dma_rst_m1; + end + + // Write address generation for the asymmetric memory + + assign dma_mem_wea_s = dma_xfer_req & dma_valid & dma_ready; + + always @(posedge dma_clk) begin + if (dma_rst == 1'b1) begin + dma_mem_waddr <= 'h0; + dma_mem_waddr_g <= 'h0; + end else begin + if (dma_mem_wea_s == 1'b1) begin + dma_mem_waddr <= dma_mem_waddr + 1; + end + dma_mem_waddr_g <= b2g(dma_mem_waddr); + end + end + + // The memory module request data until reaches the high threshold. + + always @(posedge dma_clk) begin + if (dma_rst == 1'b1) begin + dma_mem_addr_diff <= 'b0; + dma_mem_raddr_m1 <= 'b0; + dma_mem_raddr_m2 <= 'b0; + dma_mem_raddr <= 'b0; + dma_ready_out <= 1'b0; + end else begin + dma_mem_raddr_m1 <= dac_mem_raddr_g; + dma_mem_raddr_m2 <= dma_mem_raddr_m1; + dma_mem_raddr <= g2b(dma_mem_raddr_m2); + dma_mem_addr_diff <= dma_address_diff_s[DMA_ADDRESS_WIDTH-1:0]; + if (dma_mem_addr_diff >= DMA_BUF_THRESHOLD_HI) begin + dma_ready_out <= 1'b0; + end else begin + dma_ready_out <= 1'b1; + end + end + end + + // relative address offset on dma domain + assign dma_address_diff_s = {1'b1, dma_mem_waddr} - dma_mem_raddr_s; + assign dma_mem_raddr_s = (DMA_DATA_WIDTH>DAC_DATA_WIDTH) ? + ((MEM_RATIO == 1) ? (dma_mem_raddr) : + (MEM_RATIO == 2) ? (dma_mem_raddr[(DAC_ADDRESS_WIDTH-1):1]) : + (MEM_RATIO == 4) ? (dma_mem_raddr[(DAC_ADDRESS_WIDTH-1):2]) : (dma_mem_raddr[(DAC_ADDRESS_WIDTH-1):3])) : + ((MEM_RATIO == 1) ? (dma_mem_raddr) : + (MEM_RATIO == 2) ? ({dma_mem_raddr, 1'b0}) : + (MEM_RATIO == 4) ? ({dma_mem_raddr, 2'b0}) : ({dma_mem_raddr, 3'b0})); + + + // relative address offset on dac domain + assign dac_address_diff_s = {1'b1, dac_mem_raddr} - dac_mem_waddr_s; + assign dac_mem_waddr_s = (DAC_DATA_WIDTH>DMA_DATA_WIDTH) ? + ((MEM_RATIO == 1) ? (dac_mem_waddr) : + (MEM_RATIO == 2) ? (dac_mem_waddr[(DMA_ADDRESS_WIDTH-1):1]) : + (MEM_RATIO == 4) ? (dac_mem_waddr[(DMA_ADDRESS_WIDTH-1):2]) : (dac_mem_waddr[(DMA_ADDRESS_WIDTH-1):3])) : + ((MEM_RATIO == 1) ? (dac_mem_waddr) : + (MEM_RATIO == 2) ? ({dac_mem_waddr, 1'b0}) : + (MEM_RATIO == 4) ? ({dac_mem_waddr, 2'b0}) : ({dac_mem_waddr, 3'b0})); + + // Read address generation for the asymmetric memory + + assign dac_mem_rea_s = dac_valid & dac_mem_ready; + + always @(posedge dac_clk) begin + if (dac_rst == 1'b1) begin + dac_mem_raddr <= 'h0; + dac_mem_raddr_g <= 'h0; + end else begin + if (dac_mem_rea_s == 1'b1) begin + dac_mem_raddr <= dac_mem_raddr + 1; + end + dac_mem_raddr_g <= b2g(dac_mem_raddr); + end + end + + // The memory module is ready if it's not empty + + always @(posedge dac_clk) begin + if (dac_rst == 1'b1) begin + dac_mem_addr_diff <= 'b0; + dac_mem_waddr_m1 <= 'b0; + dac_mem_waddr_m2 <= 'b0; + dac_mem_waddr <= 'b0; + dac_mem_ready <= 1'b0; + end else begin + dac_mem_waddr_m1 <= dma_mem_waddr_g; + dac_mem_waddr_m2 <= dac_mem_waddr_m1; + dac_mem_waddr <= g2b(dac_mem_waddr_m2); + dac_mem_addr_diff <= dac_address_diff_s[DAC_ADDRESS_WIDTH-1:0]; + if (dac_mem_addr_diff > 0) begin + dac_mem_ready <= 1'b1; + end else begin + dac_mem_ready <= 1'b0; + end + end + end + + // define underflow + + always @(posedge dac_clk) begin + if (dac_rst == 1'b1) begin + dac_xfer_out_m1 <= 1'b0; + dac_xfer_out <= 1'b0; + dac_dunf <= 1'b0; + end else begin + dac_xfer_out_m1 <= dma_xfer_req; + dac_xfer_out <= dac_xfer_out_m1; + dac_dunf <= (dac_valid == 1'b1) ? (dac_xfer_out & ~dac_mem_ready) : dac_dunf; + end + end + + // DAC data output logic + + always @(posedge dac_clk) begin + if (dac_rst == 1'b1) begin + dac_data <= 0; + end else begin + dac_data <= dac_mem_rdata_s; + end + end + +endmodule + diff --git a/library/xilinx/axi_dacfifo/axi_dacfifo_constr.xdc b/library/xilinx/axi_dacfifo/axi_dacfifo_constr.xdc new file mode 100644 index 000000000..bc1fdb2fa --- /dev/null +++ b/library/xilinx/axi_dacfifo/axi_dacfifo_constr.xdc @@ -0,0 +1,29 @@ + +set_property ASYNC_REG TRUE \ + [get_cells -hier *_xfer_req_m*] \ + [get_cells -hier *_xfer_last_m*] \ + [get_cells -hier *dac_xfer_out*] \ + [get_cells -hier *dac_bypass_*] \ + [get_cells -hier *dma_bypass_*] + + +set_false_path -to [get_cells -hier -filter {name =~ *_xfer_req_m_reg[0]* && IS_SEQUENTIAL}] +set_false_path -to [get_cells -hier -filter {name =~ *_xfer_last_m_reg[0]* && IS_SEQUENTIAL}] +set_false_path -to [get_cells -hier -filter {name =~ *dac_xfer_out_m1* && IS_SEQUENTIAL}] +set_false_path -to [get_cells -hier -filter {name =~ *_bypass_m1* && IS_SEQUENTIAL}] +set_false_path -to [get_cells -hier -filter {name =~ *dma_rst_m1* && IS_SEQUENTIAL}] + +set_false_path -from [get_cells -hier -filter {name =~ *dma_* && IS_SEQUENTIAL}] \ + -to [get_cells -hier -filter {name =~ *axi_*_m* && IS_SEQUENTIAL}] +set_false_path -from [get_cells -hier -filter {name =~ *axi_* && IS_SEQUENTIAL}] \ + -to [get_cells -hier -filter {name =~ *dma_*_m* && IS_SEQUENTIAL}] + +set_false_path -from [get_cells -hier -filter {name =~ *dac_* && IS_SEQUENTIAL}] \ + -to [get_cells -hier -filter {name =~ *axi_*_m* && IS_SEQUENTIAL}] +set_false_path -from [get_cells -hier -filter {name =~ *axi_* && IS_SEQUENTIAL}] \ + -to [get_cells -hier -filter {name =~ *dac_*_m* && IS_SEQUENTIAL}] + +set_false_path -from [get_cells -hier -filter {name =~ *dac_* && IS_SEQUENTIAL}] \ + -to [get_cells -hier -filter {name =~ *dma_*_m* && IS_SEQUENTIAL}] +set_false_path -from [get_cells -hier -filter {name =~ *dma_* && IS_SEQUENTIAL}] \ + -to [get_cells -hier -filter {name =~ *dac_*_m* && IS_SEQUENTIAL}] diff --git a/library/xilinx/axi_dacfifo/axi_dacfifo_dac.v b/library/xilinx/axi_dacfifo/axi_dacfifo_dac.v new file mode 100644 index 000000000..5042abfb6 --- /dev/null +++ b/library/xilinx/axi_dacfifo/axi_dacfifo_dac.v @@ -0,0 +1,381 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2016(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_dacfifo_dac ( + + axi_clk, + axi_dvalid, + axi_ddata, + axi_dready, + axi_dlast, + axi_xfer_req, + + dma_last_beats, + + dac_clk, + dac_rst, + dac_valid, + dac_data, + dac_xfer_out, + dac_dunf +); + + // parameters + + parameter AXI_DATA_WIDTH = 512; + parameter AXI_LENGTH = 15; + parameter DAC_DATA_WIDTH = 64; + + localparam MEM_RATIO = AXI_DATA_WIDTH/DAC_DATA_WIDTH; + localparam DAC_ADDRESS_WIDTH = 10; + localparam AXI_ADDRESS_WIDTH = (MEM_RATIO == 1) ? DAC_ADDRESS_WIDTH : + (MEM_RATIO == 2) ? (DAC_ADDRESS_WIDTH - 1) : + (MEM_RATIO == 4) ? (DAC_ADDRESS_WIDTH - 2) : + (DAC_ADDRESS_WIDTH - 3); + + // BUF_THRESHOLD_LO will make sure that there are always at least two burst in the memmory + + localparam AXI_BUF_THRESHOLD_LO = 3 * (AXI_LENGTH+1); + localparam AXI_BUF_THRESHOLD_HI = {(AXI_ADDRESS_WIDTH){1'b1}} - (AXI_LENGTH+1); + localparam DAC_BUF_THRESHOLD_LO = 3 * (AXI_LENGTH+1) * MEM_RATIO; + localparam DAC_BUF_THRESHOLD_HI = {(DAC_ADDRESS_WIDTH){1'b1}} - (AXI_LENGTH+1) * MEM_RATIO; + localparam DAC_ARINCR = (AXI_LENGTH+1) * MEM_RATIO; + + // dma write + + input axi_clk; + input axi_dvalid; + input [(AXI_DATA_WIDTH-1):0] axi_ddata; + output axi_dready; + input axi_dlast; + input axi_xfer_req; + + input [ 3:0] dma_last_beats; + + // dac read + + input dac_clk; + input dac_rst; + input dac_valid; + output [(DAC_DATA_WIDTH-1):0] dac_data; + output dac_xfer_out; + output dac_dunf; + + // internal registers + + reg [(AXI_ADDRESS_WIDTH-1):0] axi_mem_waddr = 'd0; + reg [(AXI_ADDRESS_WIDTH-1):0] axi_mem_laddr = 'd0; + reg [(DAC_ADDRESS_WIDTH-1):0] axi_mem_waddr_g = 'd0; + reg [(DAC_ADDRESS_WIDTH-1):0] axi_mem_laddr_g = 'd0; + reg [(DAC_ADDRESS_WIDTH-1):0] axi_mem_raddr = 'd0; + reg [(DAC_ADDRESS_WIDTH-1):0] axi_mem_raddr_m1 = 'd0; + reg [(DAC_ADDRESS_WIDTH-1):0] axi_mem_raddr_m2 = 'd0; + reg [(AXI_ADDRESS_WIDTH-1):0] axi_mem_addr_diff = 'd0; + reg axi_dready = 'd0; + + reg [(DAC_ADDRESS_WIDTH-1):0] dac_mem_raddr = 'd0; + reg [(DAC_ADDRESS_WIDTH-1):0] dac_mem_raddr_g = 'd0; + reg [(DAC_ADDRESS_WIDTH-1):0] dac_mem_waddr = 'd0; + reg [(DAC_ADDRESS_WIDTH-1):0] dac_mem_waddr_m1 = 'd0; + reg [(DAC_ADDRESS_WIDTH-1):0] dac_mem_waddr_m2 = 'd0; + reg [(DAC_ADDRESS_WIDTH-1):0] dac_mem_laddr = 'd0; + reg [(DAC_ADDRESS_WIDTH-1):0] dac_mem_laddr_m1 = 'd0; + reg [(DAC_ADDRESS_WIDTH-1):0] dac_mem_laddr_m2 = 'd0; + reg [(DAC_ADDRESS_WIDTH-1):0] dac_mem_addr_diff = 'd0; + reg dac_mem_init = 1'b0; + reg dac_mem_init_d = 1'b0; + reg dac_mem_enable = 1'b0; + + reg [ 2:0] dac_xfer_req_m = 3'b0; + reg dac_xfer_init = 1'b0; + + reg [ 3:0] dac_last_beats = 4'b0; + reg [ 3:0] dac_last_beats_m = 4'b0; + reg dac_dunf = 1'b0; + reg [ 3:0] dac_beat_cnt = 4'b0; + reg dac_dlast = 1'b0; + reg dac_dlast_m1 = 1'b0; + reg dac_dlast_m2 = 1'b0; + reg dac_dlast_inmem = 1'b0; + reg dac_mem_valid = 1'b0; + + // internal signals + + wire [AXI_ADDRESS_WIDTH:0] axi_mem_addr_diff_s; + wire [(AXI_ADDRESS_WIDTH-1):0] axi_mem_raddr_s; + wire [(DAC_ADDRESS_WIDTH-1):0] axi_mem_waddr_s; + wire [(DAC_ADDRESS_WIDTH-1):0] axi_mem_laddr_s; + + wire [DAC_ADDRESS_WIDTH:0] dac_mem_addr_diff_s; + wire dac_xfer_init_s; + wire dac_last_axi_beats_s; + + // binary to grey conversion + + function [9:0] b2g; + input [9:0] b; + reg [9:0] g; + begin + g[9] = b[9]; + g[8] = b[9] ^ b[8]; + g[7] = b[8] ^ b[7]; + g[6] = b[7] ^ b[6]; + g[5] = b[6] ^ b[5]; + g[4] = b[5] ^ b[4]; + g[3] = b[4] ^ b[3]; + g[2] = b[3] ^ b[2]; + g[1] = b[2] ^ b[1]; + g[0] = b[1] ^ b[0]; + b2g = g; + end + endfunction + + // grey to binary conversion + + function [9:0] g2b; + input [9:0] g; + reg [9:0] b; + begin + b[9] = g[9]; + b[8] = b[9] ^ g[8]; + b[7] = b[8] ^ g[7]; + b[6] = b[7] ^ g[6]; + b[5] = b[6] ^ g[5]; + b[4] = b[5] ^ g[4]; + b[3] = b[4] ^ g[3]; + b[2] = b[3] ^ g[2]; + b[1] = b[2] ^ g[1]; + b[0] = b[1] ^ g[0]; + g2b = b; + end + endfunction + + // write interface + + always @(posedge axi_clk) begin + if (axi_xfer_req == 1'b0) begin + axi_mem_waddr <= 'd0; + axi_mem_waddr_g <= 'd0; + axi_mem_laddr <= {AXI_ADDRESS_WIDTH{1'b1}}; + end else begin + if (axi_dvalid == 1'b1) begin + axi_mem_waddr <= axi_mem_waddr + 1'b1; + axi_mem_laddr <= (axi_dlast == 1'b1) ? axi_mem_waddr : axi_mem_laddr; + end + axi_mem_waddr_g <= b2g(axi_mem_waddr_s); + axi_mem_laddr_g <= b2g(axi_mem_laddr_s); + end + end + + // scale the axi_mem_* addresses + + assign axi_mem_raddr_s = (MEM_RATIO == 1) ? axi_mem_raddr : + (MEM_RATIO == 2) ? axi_mem_raddr[(DAC_ADDRESS_WIDTH-1):1] : + (MEM_RATIO == 4) ? axi_mem_raddr[(DAC_ADDRESS_WIDTH-1):2] : + axi_mem_raddr[(DAC_ADDRESS_WIDTH-1):3]; + assign axi_mem_waddr_s = (MEM_RATIO == 1) ? axi_mem_waddr : + (MEM_RATIO == 2) ? {axi_mem_waddr, 1'b0} : + (MEM_RATIO == 4) ? {axi_mem_waddr, 2'b0} : + {axi_mem_waddr, 3'b0}; + assign axi_mem_laddr_s = (MEM_RATIO == 1) ? axi_mem_laddr : + (MEM_RATIO == 2) ? {axi_mem_laddr, 1'b0} : + (MEM_RATIO == 4) ? {axi_mem_laddr, 2'b0} : + {axi_mem_laddr, 3'b0}; + + // incomming data flow control + + assign axi_mem_addr_diff_s = {1'b1, axi_mem_waddr} - axi_mem_raddr_s; + + always @(posedge axi_clk) begin + if (axi_xfer_req == 1'b0) begin + axi_mem_addr_diff <= 'd0; + axi_mem_raddr <= 'd0; + axi_mem_raddr_m1 <= 'd0; + axi_mem_raddr_m2 <= 'd0; + axi_dready <= 'd0; + end else begin + axi_mem_raddr_m1 <= dac_mem_raddr_g; + axi_mem_raddr_m2 <= axi_mem_raddr_m1; + axi_mem_raddr <= g2b(axi_mem_raddr_m2); + axi_mem_addr_diff <= axi_mem_addr_diff_s[AXI_ADDRESS_WIDTH-1:0]; + if (axi_mem_addr_diff >= AXI_BUF_THRESHOLD_HI) begin + axi_dready <= 1'b0; + end else if (axi_mem_addr_diff <= AXI_BUF_THRESHOLD_LO) begin + axi_dready <= 1'b1; + end + end + end + + // CDC for xfer_req signal + + always @(posedge dac_clk) begin + if (dac_rst == 1'b1) begin + dac_xfer_req_m <= 3'b0; + end else begin + dac_xfer_req_m <= {dac_xfer_req_m[1:0], axi_xfer_req}; + end + end + + assign dac_xfer_out = dac_xfer_req_m[2]; + assign dac_xfer_init_s = ~dac_xfer_req_m[2] & dac_xfer_req_m[1]; + + // read interface + + always @(posedge dac_clk) begin + if (dac_xfer_out == 1'b0) begin + dac_mem_init <= 1'b0; + dac_mem_init_d <= 1'b0; + dac_mem_enable <= 1'b0; + end else begin + if (dac_xfer_init == 1'b1) begin + dac_mem_init <= 1'b1; + end + if ((dac_mem_init == 1'b1) && (dac_mem_addr_diff > DAC_BUF_THRESHOLD_LO)) begin + dac_mem_init <= 1'b0; + end + dac_mem_init_d <= dac_mem_init; + // memory is ready when the initial fill up is done + dac_mem_enable <= (dac_mem_init_d & ~dac_mem_init) ? 1'b1 : dac_mem_enable; + end + dac_xfer_init <= dac_xfer_init_s; + end + + always @(posedge dac_clk) begin + if (dac_xfer_out == 1'b0) begin + dac_mem_waddr <= 'b0; + dac_mem_waddr_m1 <= 'b0; + dac_mem_waddr_m2 <= 'b0; + dac_mem_laddr <= 'b0; + dac_mem_laddr_m1 <= 'b0; + dac_mem_laddr_m2 <= 'b0; + dac_dlast <= 1'b0; + dac_dlast_m1 <= 1'b0; + dac_dlast_m2 <= 1'b0; + end else begin + dac_mem_waddr_m1 <= axi_mem_waddr_g; + dac_mem_waddr_m2 <= dac_mem_waddr_m1; + dac_mem_waddr <= g2b(dac_mem_waddr_m2); + dac_mem_laddr_m1 <= axi_mem_laddr_g; + dac_mem_laddr_m2 <= dac_mem_laddr_m1; + dac_mem_laddr <= g2b(dac_mem_laddr_m2); + dac_dlast_m1 <= axi_dlast; + dac_dlast_m2 <= dac_dlast_m1; + dac_dlast <= dac_dlast_m2; + end + end + + assign dac_mem_addr_diff_s = {1'b1, dac_mem_waddr} - dac_mem_raddr; + always @(posedge dac_clk) begin + dac_mem_valid <= (dac_mem_enable) ? dac_valid : 1'b0; + end + + // CDC for the dma_last_beats + + always @(posedge dac_clk) begin + if (dac_rst == 1'b1) begin + dac_last_beats <= 32'b0; + dac_last_beats_m <= 32'b0; + end else begin + dac_last_beats_m <= dma_last_beats; + dac_last_beats <= dac_last_beats_m; + end + end + + // If the MEM_RATIO is grater than one, it can happen that not all the DAC beats from + // an AXI beat are valid. In this case the invalid data is dropped. + // The axi_dlast indicates the last AXI beat. The valid number of DAC beats on the last AXI beat + // commes from the AXI write module. (axi_dacfifo_wr.v) + + assign dac_last_axi_beats_s = ((dac_dlast_inmem == 1'b1) && (dac_mem_raddr >= dac_mem_laddr) && (dac_mem_raddr < dac_mem_laddr + MEM_RATIO)) ? 1'b1 : 1'b0; + + always @(posedge dac_clk) begin + if (dac_xfer_out == 1'b0) begin + dac_mem_raddr <= 'd0; + dac_beat_cnt <= 'd0; + dac_dlast_inmem <= 1'b0; + end else begin + if (dac_dlast == 1'b1) begin + dac_dlast_inmem <= 1'b1; + end else if (dac_mem_raddr == dac_mem_laddr + MEM_RATIO) begin + dac_dlast_inmem <= 1'b0; + end + if (dac_mem_valid == 1'b1) begin + dac_beat_cnt <= ((dac_beat_cnt >= MEM_RATIO-1) || + ((dac_last_beats > 1'b1) && (dac_last_axi_beats_s > 1'b0) && (dac_beat_cnt == dac_last_beats-1))) ? 0 : dac_beat_cnt + 1; + dac_mem_raddr <= ((dac_last_axi_beats_s) && (dac_beat_cnt == dac_last_beats-1)) ? (dac_mem_laddr + MEM_RATIO) : dac_mem_raddr + 1'b1; + end + dac_mem_raddr_g <= b2g(dac_mem_raddr); + end + end + + // underflow generation, there is no overflow + + always @(posedge dac_clk) begin + if(dac_xfer_out == 1'b0) begin + dac_mem_addr_diff <= 'b0; + dac_dunf <= 1'b0; + end else begin + dac_mem_addr_diff <= dac_mem_addr_diff_s[DAC_ADDRESS_WIDTH-1:0]; + dac_dunf <= (dac_mem_addr_diff == 1'b0) ? 1'b1 : 1'b0; + end + end + + // instantiations + + ad_mem_asym #( + .A_ADDRESS_WIDTH (AXI_ADDRESS_WIDTH), + .A_DATA_WIDTH (AXI_DATA_WIDTH), + .B_ADDRESS_WIDTH (DAC_ADDRESS_WIDTH), + .B_DATA_WIDTH (DAC_DATA_WIDTH)) + i_mem_asym ( + .clka (axi_clk), + .wea (axi_dvalid), + .addra (axi_mem_waddr), + .dina (axi_ddata), + .clkb (dac_clk), + .addrb (dac_mem_raddr), + .doutb (dac_data)); + +endmodule + +// *************************************************************************** +// *************************************************************************** + diff --git a/library/xilinx/axi_dacfifo/axi_dacfifo_ip.tcl b/library/xilinx/axi_dacfifo/axi_dacfifo_ip.tcl new file mode 100644 index 000000000..0bb293baa --- /dev/null +++ b/library/xilinx/axi_dacfifo/axi_dacfifo_ip.tcl @@ -0,0 +1,85 @@ +# ip + +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip.tcl + +adi_ip_create axi_dacfifo + +adi_ip_files axi_dacfifo [list \ + "$ad_hdl_dir/library/common/ad_mem_asym.v" \ + "$ad_hdl_dir/library/common/ad_axis_inf_rx.v" \ + "$ad_hdl_dir/library/util_axis_resize/util_axis_resize.v" \ + "axi_dacfifo_constr.xdc" \ + "axi_dacfifo_dac.v" \ + "axi_dacfifo_wr.v" \ + "axi_dacfifo_rd.v" \ + "axi_dacfifo_bypass.v" \ + "axi_dacfifo.v"] + +adi_ip_properties_lite axi_dacfifo +adi_ip_constraints axi_dacfifo [list \ + "axi_dacfifo_constr.xdc" ] + +ipx::infer_bus_interface {\ + axi_awvalid \ + axi_awid \ + axi_awburst \ + axi_awlock \ + axi_awcache \ + axi_awprot \ + axi_awqos \ + axi_awuser \ + axi_awlen \ + axi_awsize \ + axi_awaddr \ + axi_awready \ + axi_wvalid \ + axi_wdata \ + axi_wstrb \ + axi_wlast \ + axi_wuser \ + axi_wready \ + axi_bvalid \ + axi_bid \ + axi_bresp \ + axi_buser \ + axi_bready \ + axi_arvalid \ + axi_arid \ + axi_arburst \ + axi_arlock \ + axi_arcache \ + axi_arprot \ + axi_arqos \ + axi_aruser \ + axi_arlen \ + axi_arsize \ + axi_araddr \ + axi_arready \ + axi_rvalid \ + axi_rid \ + axi_ruser \ + axi_rresp \ + axi_rlast \ + axi_rdata \ + axi_rready} \ +xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] + +ipx::infer_bus_interface axi_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] +ipx::infer_bus_interface axi_resetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] +ipx::add_bus_parameter ASSOCIATED_BUSIF [ipx::get_bus_interfaces axi_clk \ + -of_objects [ipx::current_core]] +set_property value axi [ipx::get_bus_parameters ASSOCIATED_BUSIF \ + -of_objects [ipx::get_bus_interfaces axi_clk \ + -of_objects [ipx::current_core]]] + +ipx::add_address_space axi [ipx::current_core] +set_property master_address_space_ref axi [ipx::get_bus_interfaces axi \ + -of_objects [ipx::current_core]] +set_property range 4294967296 [ipx::get_address_spaces axi \ + -of_objects [ipx::current_core]] +set_property width 512 [ipx::get_address_spaces axi \ + -of_objects [ipx::current_core]] + +ipx::save_core [ipx::current_core] + diff --git a/library/xilinx/axi_dacfifo/axi_dacfifo_rd.v b/library/xilinx/axi_dacfifo/axi_dacfifo_rd.v new file mode 100644 index 000000000..3e93a6ee6 --- /dev/null +++ b/library/xilinx/axi_dacfifo/axi_dacfifo_rd.v @@ -0,0 +1,260 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2016(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_dacfifo_rd ( + + // xfer last for read/write synchronization + + axi_xfer_req, + axi_last_raddr, + axi_last_beats, + + // axi read address and read data channels + + axi_clk, + axi_resetn, + axi_arvalid, + axi_arid, + axi_arburst, + axi_arlock, + axi_arcache, + axi_arprot, + axi_arqos, + axi_aruser, + axi_arlen, + axi_arsize, + axi_araddr, + axi_arready, + axi_rvalid, + axi_rid, + axi_ruser, + axi_rresp, + axi_rlast, + axi_rdata, + axi_rready, + + // axi status + + axi_rerror, + + // fifo interface + + axi_dvalid, + axi_ddata, + axi_dready, + axi_dlast); + + // parameters + + parameter AXI_DATA_WIDTH = 512; + parameter AXI_SIZE = 2; + parameter AXI_LENGTH = 15; + parameter AXI_ADDRESS = 32'h00000000; + localparam AXI_BYTE_WIDTH = AXI_DATA_WIDTH/8; + localparam AXI_AWINCR = (AXI_LENGTH + 1) * AXI_BYTE_WIDTH; + + // xfer last for read/write synchronization + + input axi_xfer_req; + input [31:0] axi_last_raddr; + input [ 3:0] axi_last_beats; + + // axi interface + + input axi_clk; + input axi_resetn; + output axi_arvalid; + output [ 3:0] axi_arid; + output [ 1:0] axi_arburst; + output axi_arlock; + output [ 3:0] axi_arcache; + output [ 2:0] axi_arprot; + output [ 3:0] axi_arqos; + output [ 3:0] axi_aruser; + output [ 7:0] axi_arlen; + output [ 2:0] axi_arsize; + output [31:0] axi_araddr; + input axi_arready; + input axi_rvalid; + input [ 3:0] axi_rid; + input [ 3:0] axi_ruser; + input [ 1:0] axi_rresp; + input axi_rlast; + input [(AXI_DATA_WIDTH-1):0] axi_rdata; + output axi_rready; + + // axi status + + output axi_rerror; + + // fifo interface + + output axi_dvalid; + output [(AXI_DATA_WIDTH-1):0] axi_ddata; + input axi_dready; + output axi_dlast; + + // internal registers + + reg axi_rnext = 1'b0; + reg axi_ractive = 1'b0; + reg axi_arvalid = 1'b0; + reg [ 31:0] axi_araddr = 32'b0; + reg [ 31:0] axi_araddr_prev = 32'b0; + reg [(AXI_DATA_WIDTH-1):0] axi_ddata = 'b0; + reg axi_dvalid = 1'b0; + reg axi_dlast = 1'b0; + reg axi_rready = 1'b0; + reg axi_rerror = 1'b0; + reg [ 1:0] axi_xfer_req_m = 2'b0; + reg [ 4:0] axi_last_beats_cntr = 16'b0; + + // internal signals + + wire axi_ready_s; + wire axi_xfer_req_init; + wire axi_dvalid_s; + wire axi_dlast_s; + wire [ 4:0] axi_last_beats_s; + + assign axi_ready_s = (~axi_arvalid | axi_arready) & axi_dready; + + always @(posedge axi_clk) begin + if (axi_resetn == 1'b0) begin + axi_rnext <= 1'b0; + axi_ractive <= 1'b0; + axi_xfer_req_m <= 2'b0; + end else begin + if (axi_ractive == 1'b1) begin + axi_rnext <= 1'b0; + if ((axi_rvalid == 1'b1) && (axi_rlast == 1'b1)) begin + axi_ractive <= 1'b0; + end + end else if ((axi_ready_s == 1'b1)) begin + axi_rnext <= axi_xfer_req; + axi_ractive <= axi_xfer_req; + end + axi_xfer_req_m <= {axi_xfer_req_m[0], axi_xfer_req}; + end + end + + assign axi_xfer_req_init = axi_xfer_req_m[0] & ~axi_xfer_req_m[1]; + + always @(posedge axi_clk) begin + if ((axi_resetn == 1'b0) || (axi_xfer_req == 1'b0)) begin + axi_last_beats_cntr <= 0; + end else begin + if ((axi_rready == 1'b1) && (axi_rvalid == 1'b1)) begin + axi_last_beats_cntr <= (axi_rlast == 1'b1) ? 0 : axi_last_beats_cntr + 1; + end + end + end + + // address channel + + assign axi_arid = 4'b0000; + assign axi_arburst = 2'b01; + assign axi_arlock = 1'b0; + assign axi_arcache = 4'b0010; + assign axi_arprot = 3'b000; + assign axi_arqos = 4'b0000; + assign axi_aruser = 4'b0001; + assign axi_arlen = AXI_LENGTH; + assign axi_arsize = AXI_SIZE; + + always @(posedge axi_clk) begin + if (axi_resetn == 1'b0) begin + axi_arvalid <= 'd0; + axi_araddr <= AXI_ADDRESS; + axi_araddr_prev <= AXI_ADDRESS; + end else begin + if (axi_arvalid == 1'b1) begin + if (axi_arready == 1'b1) begin + axi_arvalid <= 1'b0; + end + end else begin + if (axi_rnext == 1'b1) begin + axi_arvalid <= 1'b1; + end + end + if ((axi_xfer_req == 1'b1) && + (axi_arvalid == 1'b1) && + (axi_arready == 1'b1)) begin + axi_araddr <= (axi_araddr >= axi_last_raddr) ? AXI_ADDRESS : axi_araddr + AXI_AWINCR; + axi_araddr_prev <= axi_araddr; + end + end + end + + // read data channel + + assign axi_last_beats_s = {1'b0, axi_last_beats} - 1; + assign axi_dvalid_s = ((axi_last_beats_cntr > axi_last_beats_s) && (axi_araddr_prev == axi_last_raddr)) ? 0 : axi_rvalid & axi_rready; + assign axi_dlast_s = (axi_araddr_prev == axi_last_raddr) ? 1 : 0; + + always @(posedge axi_clk) begin + if (axi_resetn == 1'b0) begin + axi_ddata <= 'd0; + axi_rready <= 1'b0; + axi_dvalid <= 1'b0; + end else begin + axi_ddata <= axi_rdata; + axi_dvalid <= axi_dvalid_s; + axi_dlast <= axi_dlast_s; + if (axi_xfer_req == 1'b1) begin + axi_rready <= axi_rvalid; + end + end + end + + always @(posedge axi_clk) begin + if (axi_resetn == 1'b0) begin + axi_rerror <= 'd0; + end else begin + axi_rerror <= axi_rvalid & axi_rresp[1]; + end + end + +endmodule + +// *************************************************************************** +// *************************************************************************** + diff --git a/library/xilinx/axi_dacfifo/axi_dacfifo_wr.v b/library/xilinx/axi_dacfifo/axi_dacfifo_wr.v new file mode 100644 index 000000000..513c1a7af --- /dev/null +++ b/library/xilinx/axi_dacfifo/axi_dacfifo_wr.v @@ -0,0 +1,568 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2016(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_dacfifo_wr ( + + // dma fifo interface + + dma_clk, + dma_data, + dma_ready, + dma_ready_out, + dma_valid, + + // request and syncronizaiton + + dma_xfer_req, + dma_xfer_last, + dma_last_beats, + + // syncronization for the read side + + axi_last_addr, + axi_last_beats, + axi_xfer_out, + + // axi write address, write data and write response channels + + axi_clk, + axi_resetn, + axi_awvalid, + axi_awid, + axi_awburst, + axi_awlock, + axi_awcache, + axi_awprot, + axi_awqos, + axi_awuser, + axi_awlen, + axi_awsize, + axi_awaddr, + axi_awready, + axi_wvalid, + axi_wdata, + axi_wstrb, + axi_wlast, + axi_wuser, + axi_wready, + axi_bvalid, + axi_bid, + axi_bresp, + axi_buser, + axi_bready, + + axi_werror); + + // parameters + + parameter AXI_DATA_WIDTH = 512; + parameter DMA_DATA_WIDTH = 64; + parameter AXI_SIZE = 6; // axi_awsize format + parameter AXI_LENGTH = 15; // axi_awlength format + parameter AXI_ADDRESS = 32'h00000000; + parameter AXI_ADDRESS_LIMIT = 32'h00000000; + parameter DMA_MEM_ADDRESS_WIDTH = 8; + + // for the syncronization buffer + + localparam MEM_RATIO = AXI_DATA_WIDTH/DMA_DATA_WIDTH; // Max supported MEM_RATIO is 16 + localparam AXI_MEM_ADDRESS_WIDTH = (MEM_RATIO == 1) ? DMA_MEM_ADDRESS_WIDTH : + (MEM_RATIO == 2) ? (DMA_MEM_ADDRESS_WIDTH - 1) : + (MEM_RATIO == 4) ? (DMA_MEM_ADDRESS_WIDTH - 2) : + (MEM_RATIO == 8) ? (DMA_MEM_ADDRESS_WIDTH - 3) : + (DMA_MEM_ADDRESS_WIDTH - 4); + + // for the AXI interface + + localparam AXI_BYTE_WIDTH = AXI_DATA_WIDTH/8; + localparam DMA_BYTE_WIDTH = DMA_DATA_WIDTH/8; + localparam AXI_AWINCR = (AXI_LENGTH + 1) * AXI_BYTE_WIDTH; + localparam DMA_BUF_THRESHOLD_HI = {(DMA_MEM_ADDRESS_WIDTH){1'b1}} - 4; + + // dma fifo interface + + input dma_clk; + input [(DMA_DATA_WIDTH-1):0] dma_data; + input dma_ready; + output dma_ready_out; + input dma_valid; + + input dma_xfer_req; + input dma_xfer_last; + output [ 3:0] dma_last_beats; + + output [31:0] axi_last_addr; + output [ 3:0] axi_last_beats; + output axi_xfer_out; + + // axi interface + + input axi_clk; + input axi_resetn; + output axi_awvalid; + output [ 3:0] axi_awid; + output [ 1:0] axi_awburst; + output axi_awlock; + output [ 3:0] axi_awcache; + output [ 2:0] axi_awprot; + output [ 3:0] axi_awqos; + output [ 3:0] axi_awuser; + output [ 7:0] axi_awlen; + output [ 2:0] axi_awsize; + output [31:0] axi_awaddr; + input axi_awready; + output axi_wvalid; + output [(AXI_DATA_WIDTH-1):0] axi_wdata; + output [(AXI_BYTE_WIDTH-1):0] axi_wstrb; + output axi_wlast; + output [ 3:0] axi_wuser; + input axi_wready; + input axi_bvalid; + input [ 3:0] axi_bid; + input [ 1:0] axi_bresp; + input [ 3:0] axi_buser; + output axi_bready; + + output axi_werror; + + // registers + + reg [(DMA_MEM_ADDRESS_WIDTH-1):0] dma_mem_waddr = 'd0; + reg [(DMA_MEM_ADDRESS_WIDTH-1):0] dma_mem_waddr_g = 'd0; + reg [(DMA_MEM_ADDRESS_WIDTH-1):0] dma_mem_addr_diff = 'd0; + reg [(AXI_MEM_ADDRESS_WIDTH-1):0] dma_mem_raddr_m1 = 'd0; + reg [(AXI_MEM_ADDRESS_WIDTH-1):0] dma_mem_raddr_m2 = 'd0; + reg [(AXI_MEM_ADDRESS_WIDTH-1):0] dma_mem_raddr = 'd0; + reg dma_ready_out = 1'b0; + reg dma_rst_m1 = 1'b0; + reg dma_rst_m2 = 1'b0; + reg [ 2:0] dma_mem_last_read_toggle_m = 3'b0; + reg dma_xfer_req_d = 1'b0; + reg [ 3:0] dma_last_beats = 4'b0; + + reg [ 4:0] axi_xfer_req_m = 3'b0; + reg [ 4:0] axi_xfer_last_m = 3'b0; + + reg [(DMA_MEM_ADDRESS_WIDTH-1):0] axi_mem_waddr_m1 = 'b0; + reg [(DMA_MEM_ADDRESS_WIDTH-1):0] axi_mem_waddr_m2 = 'b0; + reg [(DMA_MEM_ADDRESS_WIDTH-1):0] axi_mem_waddr = 'b0; + reg axi_mem_rvalid = 1'b0; + reg axi_mem_rvalid_d = 1'b0; + reg axi_mem_last = 1'b0; + reg axi_mem_last_d = 1'b0; + reg [(AXI_DATA_WIDTH-1):0] axi_mem_rdata = 'b0; + reg [(AXI_MEM_ADDRESS_WIDTH-1):0] axi_mem_raddr = 'd0; + reg [(AXI_MEM_ADDRESS_WIDTH-1):0] axi_mem_raddr_g = 'd0; + reg axi_mem_read_en = 1'b0; + reg axi_mem_read_en_d = 1'b0; + reg axi_mem_read_en_delay = 1'b0; + reg [(AXI_MEM_ADDRESS_WIDTH-1):0] axi_mem_addr_diff = 'b0; + reg axi_mem_last_read_toggle = 1'b0; + + reg axi_reset = 1'b0; + reg axi_xfer_out = 1'b0; + reg [31:0] axi_last_addr = 32'b0; + reg [ 3:0] axi_last_beats = 4'b0; + reg axi_awvalid = 1'b0; + reg [31:0] axi_awaddr = 32'b0; + reg axi_xfer_init = 1'b0; + reg axi_werror = 1'b0; + reg [ 3:0] axi_wvalid_counter = 4'b0; + + reg axi_endof_transaction = 1'b0; + reg axi_endof_transaction_d = 1'b0; + + // internal signals + + wire [(DMA_MEM_ADDRESS_WIDTH):0] dma_mem_addr_diff_s; + wire [(DMA_MEM_ADDRESS_WIDTH-1):0] dma_mem_raddr_s; + wire dma_mem_last_read_s; + wire dma_xfer_init; + wire dma_mem_wea_s; + wire dma_rst_s; + + wire [(AXI_MEM_ADDRESS_WIDTH-1):0] axi_mem_waddr_s; + wire [AXI_MEM_ADDRESS_WIDTH:0] axi_mem_addr_diff_s; + wire [(AXI_DATA_WIDTH-1):0] axi_mem_rdata_s; + wire axi_mem_rvalid_s; + wire axi_mem_last_s; + + wire axi_waddr_ready_s; + wire axi_wready_s; + + // binary to grey conversion + + function [7:0] b2g; + input [7:0] b; + reg [7:0] g; + begin + g[7] = b[7]; + g[6] = b[7] ^ b[6]; + g[5] = b[6] ^ b[5]; + g[4] = b[5] ^ b[4]; + g[3] = b[4] ^ b[3]; + g[2] = b[3] ^ b[2]; + g[1] = b[2] ^ b[1]; + g[0] = b[1] ^ b[0]; + b2g = g; + end + endfunction + + // grey to binary conversion + + function [7:0] g2b; + input [7:0] g; + reg [7:0] b; + begin + b[7] = g[7]; + b[6] = b[7] ^ g[6]; + b[5] = b[6] ^ g[5]; + b[4] = b[5] ^ g[4]; + b[3] = b[4] ^ g[3]; + b[2] = b[3] ^ g[2]; + b[1] = b[2] ^ g[1]; + b[0] = b[1] ^ g[0]; + g2b = b; + end + endfunction + + // Instantiations + + // An asymmetric memory to transfer data from DMAC interface to AXI Memory Map + // interface + + ad_mem_asym #( + .A_ADDRESS_WIDTH (DMA_MEM_ADDRESS_WIDTH), + .A_DATA_WIDTH (DMA_DATA_WIDTH), + .B_ADDRESS_WIDTH (AXI_MEM_ADDRESS_WIDTH), + .B_DATA_WIDTH (AXI_DATA_WIDTH)) + i_mem_asym ( + .clka (dma_clk), + .wea (dma_mem_wea_s), + .addra (dma_mem_waddr), + .dina (dma_data), + .clkb (axi_clk), + .addrb (axi_mem_raddr), + .doutb (axi_mem_rdata_s)); + + ad_axis_inf_rx #(.DATA_WIDTH(AXI_DATA_WIDTH)) i_axis_inf ( + .clk (axi_clk), + .rst (axi_reset), + .valid (axi_mem_rvalid_d), + .last (axi_mem_last_d), + .data (axi_mem_rdata), + .inf_valid (axi_wvalid), + .inf_last (axi_wlast), + .inf_data (axi_wdata), + .inf_ready (axi_wready)); + + // fifo needs a reset + + always @(posedge axi_clk) begin + if (axi_resetn == 1'b0) begin + axi_reset <= 1'b1; + end else begin + axi_reset <= 1'b0; + end + end + + always @(posedge dma_clk) begin + dma_rst_m1 <= ~axi_resetn; + dma_rst_m2 <= dma_rst_m1; + end + assign dma_rst_s = dma_rst_m2; + + // DMA beat counter + + assign dma_xfer_init = dma_xfer_req & ~dma_xfer_req_d; + always @(posedge dma_clk) begin + dma_xfer_req_d <= dma_xfer_req; + if ((dma_rst_s == 1'b1) || (dma_xfer_init == 1'b1)) begin + dma_last_beats <= 4'b0; + end else begin + if ((dma_ready == 1'b1) && (dma_valid == 1'b1)) begin + dma_last_beats <= (dma_last_beats < MEM_RATIO-1) ? dma_last_beats + 4'b1 : 4'b0; + end + end + end + + // Write address generation for the asymmetric memory + + assign dma_mem_addr_diff_s = {1'b1, dma_mem_waddr} - dma_mem_raddr_s; + assign dma_mem_raddr_s = (MEM_RATIO == 1) ? dma_mem_raddr : + (MEM_RATIO == 2) ? {dma_mem_raddr, 1'b0} : + (MEM_RATIO == 4) ? {dma_mem_raddr, 2'b0} : + (MEM_RATIO == 8) ? {dma_mem_raddr, 3'b0} : + {dma_mem_raddr, 4'b0}; + assign dma_mem_last_read_s = dma_mem_last_read_toggle_m[2] ^ dma_mem_last_read_toggle_m[1]; + assign dma_mem_wea_s = dma_xfer_req & dma_valid & dma_ready; + + always @(posedge dma_clk) begin + if (dma_rst_s == 1'b1) begin + dma_mem_waddr <= 'h0; + dma_mem_waddr_g <= 'h0; + dma_mem_last_read_toggle_m <= 3'b0; + end else begin + dma_mem_last_read_toggle_m = {dma_mem_last_read_toggle_m[1:0], axi_mem_last_read_toggle}; + if (dma_mem_wea_s == 1'b1) begin + dma_mem_waddr <= dma_mem_waddr + 1; + if (dma_xfer_last == 1'b1) begin + if (dma_last_beats != (MEM_RATIO - 1)) begin + dma_mem_waddr <= dma_mem_waddr + (MEM_RATIO - dma_last_beats); + end + end + end + if (dma_mem_last_read_s == 1'b1) begin + dma_mem_waddr <= 'h0; + end + dma_mem_waddr_g <= b2g(dma_mem_waddr); + end + end + + // The memory module request data until reaches the high threshold. + + always @(posedge dma_clk) begin + if (dma_rst_s == 1'b1) begin + dma_mem_addr_diff <= 'b0; + dma_mem_raddr_m1 <= 'b0; + dma_mem_raddr_m2 <= 'b0; + dma_mem_raddr <= 'b0; + dma_ready_out <= 1'b0; + end else begin + dma_mem_raddr_m1 <= axi_mem_raddr_g; + dma_mem_raddr_m2 <= dma_mem_raddr_m1; + dma_mem_raddr <= g2b(dma_mem_raddr_m2); + dma_mem_addr_diff <= dma_mem_addr_diff_s[DMA_MEM_ADDRESS_WIDTH-1:0]; + if (dma_mem_addr_diff >= DMA_BUF_THRESHOLD_HI) begin + dma_ready_out <= 1'b0; + end else begin + dma_ready_out <= 1'b1; + end + end + end + + // Read address generation for the asymmetric memory + + // CDC for the memory write address, xfer_req and xfer_last + + always @(posedge axi_clk) begin + if (axi_resetn == 1'b0) begin + axi_xfer_req_m <= 4'b0; + axi_xfer_last_m <= 5'b0; + axi_xfer_init <= 1'b0; + axi_mem_waddr_m1 <= 'b0; + axi_mem_waddr_m2 <= 'b0; + axi_mem_waddr <= 'b0; + end else begin + axi_xfer_req_m <= {axi_xfer_req_m[3:0], dma_xfer_req}; + axi_xfer_last_m <= {axi_xfer_last_m[3:0], dma_xfer_last}; + axi_xfer_init = ~axi_xfer_req_m[2] & axi_xfer_req_m[1]; + axi_mem_waddr_m1 <= dma_mem_waddr_g; + axi_mem_waddr_m2 <= axi_mem_waddr_m1; + axi_mem_waddr <= g2b(axi_mem_waddr_m2); + end + end + + // check if the AXI write channel is ready + + assign axi_wready_s = ~axi_wvalid | axi_wready; + + // check if there is enough data in the asymmetric memory + + assign axi_mem_waddr_s = (MEM_RATIO == 1) ? axi_mem_waddr : + (MEM_RATIO == 2) ? axi_mem_waddr[(DMA_MEM_ADDRESS_WIDTH-1):1] : + (MEM_RATIO == 4) ? axi_mem_waddr[(DMA_MEM_ADDRESS_WIDTH-1):2] : + (MEM_RATIO == 8) ? axi_mem_waddr[(DMA_MEM_ADDRESS_WIDTH-1):3] : + axi_mem_waddr[(DMA_MEM_ADDRESS_WIDTH-1):4]; + + assign axi_mem_addr_diff_s = {1'b1, axi_mem_waddr_s} - axi_mem_raddr; + + always @(posedge axi_clk) begin + if (axi_resetn == 1'b0) begin + axi_endof_transaction <= 1'b0; + axi_endof_transaction_d <= 1'b0; + end else begin + axi_endof_transaction_d <= axi_endof_transaction; + if ((axi_xfer_req_m[4] == 1'b1) && (axi_xfer_last_m[4] == 1'b1) && (axi_xfer_last_m[3] == 1'b0)) begin + axi_endof_transaction <= 1'b1; + end else if((axi_endof_transaction == 1'b1) && (axi_wlast == 1'b1) && ((axi_mem_addr_diff == 0) || (axi_mem_addr_diff > AXI_LENGTH))) begin + axi_endof_transaction <= 1'b0; + end + end + end + + // The asymmetric memory have to have enough data for at least one AXI burst, + // before the controller start an AXI write transaction. + + always @(posedge axi_clk) begin + if (axi_resetn == 1'b0) begin + axi_mem_read_en <= 1'b0; + axi_mem_read_en_d <= 1'b0; + axi_mem_read_en_delay <= 1'b0; + axi_mem_addr_diff <= 'b0; + end else begin + axi_mem_addr_diff <= axi_mem_addr_diff_s[(AXI_MEM_ADDRESS_WIDTH-1):0]; + if ((axi_mem_read_en == 1'b0) && (axi_mem_read_en_delay == 1'b0)) begin + if (((axi_xfer_req_m[2] == 1'b1) && (axi_mem_addr_diff > AXI_LENGTH)) || + ((axi_endof_transaction == 1'b1) && (axi_mem_addr_diff > AXI_LENGTH)) || + ((axi_endof_transaction == 1'b1) && (axi_mem_addr_diff > 0))) begin + axi_mem_read_en <= 1'b1; + end + end else if (axi_mem_last_s == 1'b1) begin + axi_mem_read_en <= 1'b0; + axi_mem_read_en_delay <= 1; + end + if (axi_wlast == 1'b1) begin + axi_mem_read_en_delay <= 0; + end + axi_mem_read_en_d <= axi_mem_read_en; + end + end + + assign axi_mem_rvalid_s = axi_mem_read_en & axi_wready_s; + assign axi_mem_last_s = (axi_wvalid_counter == axi_awlen) ? axi_mem_rvalid_s : 1'b0; + + always @(posedge axi_clk) begin + if (axi_resetn == 1'b0) begin + axi_mem_rvalid <= 1'b0; + axi_mem_rvalid_d <= 1'b0; + axi_mem_last <= 1'b0; + axi_mem_last_d <= 1'b0; + axi_mem_rdata <= 'b0; + axi_mem_raddr <= 'b0; + axi_wvalid_counter <= 4'b0; + axi_mem_last_read_toggle <= 1'b1; + axi_mem_raddr_g <= 'b0; + end else begin + axi_mem_rvalid <= axi_mem_rvalid_s; + axi_mem_rvalid_d <= axi_mem_rvalid; + axi_mem_last <= axi_mem_last_s; + axi_mem_last_d <= axi_mem_last; + axi_mem_rdata <= axi_mem_rdata_s; + if (axi_mem_rvalid_s == 1'b1) begin + axi_mem_raddr <= axi_mem_raddr + 1; + axi_wvalid_counter <= ((axi_wvalid_counter == axi_awlen) || (axi_xfer_init == 1'b1)) ? 4'b0 : axi_wvalid_counter + 4'b1; + end + if ((axi_endof_transaction == 1'b0) && (axi_endof_transaction_d == 1'b1)) begin + axi_mem_raddr <= 'b0; + axi_mem_last_read_toggle <= ~axi_mem_last_read_toggle; + end + axi_mem_raddr_g <= b2g(axi_mem_raddr); + end + end + + // AXI Memory Map interface write address channel + + assign axi_awid = 4'b0000; + assign axi_awburst = 2'b01; + assign axi_awlock = 1'b0; + assign axi_awcache = 4'b0010; + assign axi_awprot = 3'b000; + assign axi_awqos = 4'b0000; + assign axi_awuser = 4'b0001; + assign axi_awlen = AXI_LENGTH; + assign axi_awsize = AXI_SIZE; + + assign axi_waddr_ready_s = axi_mem_read_en & ~axi_mem_read_en_d; + + always @(posedge axi_clk) begin + if (axi_resetn == 1'b0) begin + axi_awvalid <= 'd0; + axi_awaddr <= AXI_ADDRESS; + axi_last_addr <= AXI_ADDRESS; + axi_xfer_out <= 1'b0; + end else begin + if (axi_awvalid == 1'b1) begin + if (axi_awready == 1'b1) begin + axi_awvalid <= 1'b0; + end + end else begin + if (axi_waddr_ready_s == 1'b1) begin + axi_awvalid <= 1'b1; + end + end + if (axi_xfer_init == 1'b1) begin + axi_awaddr <= (axi_xfer_out == 1'b1) ? AXI_ADDRESS : axi_last_addr; + axi_xfer_out <= 1'b0; + end else if ((axi_awvalid == 1'b1) && (axi_awready == 1'b1)) begin + axi_awaddr <= axi_awaddr + AXI_AWINCR; + end + if (axi_xfer_last_m[2] == 1'b1) begin + axi_xfer_out <= 1'b1; + end + if ((axi_awvalid == 1'b1) && (axi_endof_transaction == 1'b1)) begin + axi_last_addr <= axi_awaddr; + end + end + end + + // write data channel controls + + assign axi_wstrb = {AXI_BYTE_WIDTH{1'b1}}; + assign axi_wuser = 4'b0000; + + // response channel + + assign axi_bready = 1'b1; + + always @(posedge axi_clk) begin + if (axi_resetn == 1'b0) begin + axi_werror <= 'd0; + end else begin + axi_werror <= axi_bvalid & axi_bresp[1]; + end + end + + // AXI beat counter + + always @(posedge axi_clk) begin + if(axi_resetn == 1'b0) begin + axi_last_beats <= 4'b0; + end else begin + if ((axi_endof_transaction == 1'b1) && (axi_awready == 1'b1) && (axi_awvalid == 1'b1)) begin + axi_last_beats <= axi_mem_addr_diff; + end else begin + axi_last_beats <= axi_last_beats; + end + end + end + +endmodule diff --git a/library/xilinx/axi_xcvrlb/Makefile b/library/xilinx/axi_xcvrlb/Makefile new file mode 100644 index 000000000..8dee022ba --- /dev/null +++ b/library/xilinx/axi_xcvrlb/Makefile @@ -0,0 +1,52 @@ +#################################################################################### +#################################################################################### +## Copyright 2011(c) Analog Devices, Inc. +## Auto-generated, do not modify! +#################################################################################### +#################################################################################### + +M_DEPS += ../../common/ad_pnmon.v +M_DEPS += ../../common/up_axi.v +M_DEPS += ../../common/up_xfer_status.v +M_DEPS += ../../scripts/adi_env.tcl +M_DEPS += ../../scripts/adi_ip.tcl +M_DEPS += ../../xilinx/util_adxcvr/util_adxcvr_xch.v +M_DEPS += axi_xcvrlb.v +M_DEPS += axi_xcvrlb_1.v +M_DEPS += axi_xcvrlb_constr.xdc +M_DEPS += axi_xcvrlb_ip.tcl + +M_VIVADO := vivado -mode batch -source + +M_FLIST := *.cache +M_FLIST += *.data +M_FLIST += *.xpr +M_FLIST += *.log +M_FLIST += component.xml +M_FLIST += *.jou +M_FLIST += xgui +M_FLIST += *.ip_user_files +M_FLIST += *.srcs +M_FLIST += *.hw +M_FLIST += *.sim +M_FLIST += .Xil + + + +.PHONY: all clean clean-all +all: axi_xcvrlb.xpr + + +clean:clean-all + + +clean-all: + rm -rf $(M_FLIST) + + +axi_xcvrlb.xpr: $(M_DEPS) + -rm -rf $(M_FLIST) + $(M_VIVADO) axi_xcvrlb_ip.tcl >> axi_xcvrlb_ip.log 2>&1 + +#################################################################################### +#################################################################################### diff --git a/library/xilinx/axi_xcvrlb/axi_xcvrlb.v b/library/xilinx/axi_xcvrlb/axi_xcvrlb.v new file mode 100644 index 000000000..ffa9fb9e3 --- /dev/null +++ b/library/xilinx/axi_xcvrlb/axi_xcvrlb.v @@ -0,0 +1,203 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/1ps + +module axi_xcvrlb #( + + // parameters + + parameter NUM_OF_LANES = 1) ( + + // transceiver interface + + input ref_clk, + input [(NUM_OF_LANES-1):0] rx_p, + input [(NUM_OF_LANES-1):0] rx_n, + output [(NUM_OF_LANES-1):0] tx_p, + output [(NUM_OF_LANES-1):0] tx_n, + + // axi interface + + input s_axi_aclk, + input s_axi_aresetn, + input s_axi_awvalid, + input [31:0] s_axi_awaddr, + input [ 2:0] s_axi_awprot, + output s_axi_awready, + input s_axi_wvalid, + input [31:0] s_axi_wdata, + input [ 3:0] s_axi_wstrb, + output s_axi_wready, + output s_axi_bvalid, + output [ 1:0] s_axi_bresp, + input s_axi_bready, + input s_axi_arvalid, + input [31:0] s_axi_araddr, + input [ 2:0] s_axi_arprot, + output s_axi_arready, + output s_axi_rvalid, + output [ 1:0] s_axi_rresp, + output [31:0] s_axi_rdata, + input s_axi_rready); + + // internal registers + + reg up_wack = 'd0; + reg [31:0] up_scratch = 'd0; + reg up_resetn = 'd0; + reg [31:0] up_status = 'd0; + reg up_rack = 'd0; + reg [31:0] up_rdata = 'd0; + + // internal signals + + wire up_rstn; + wire up_clk; + wire up_wreq_s; + wire [ 7:0] up_waddr_s; + wire [31:0] up_wdata_s; + wire up_rreq_s; + wire [ 7:0] up_raddr_s; + wire [31:0] up_status_s; + + // parameters + + localparam [31:0] VERSION = 32'h00100161; + + // defaults + + assign up_rstn = s_axi_aresetn; + assign up_clk = s_axi_aclk; + assign up_status_s[31:NUM_OF_LANES] = 'd0; + + // register access + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_wack <= 'd0; + up_scratch <= 'd0; + up_resetn <= 'd0; + up_status <= 'd0; + end else begin + up_wack <= up_wreq_s; + if ((up_wreq_s == 1'b1) && (up_waddr_s == 8'h02)) begin + up_scratch <= up_wdata_s; + end + if ((up_wreq_s == 1'b1) && (up_waddr_s == 8'h04)) begin + up_resetn <= up_wdata_s[0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr_s == 8'h05)) begin + up_status <= up_status_s | (up_status & ~up_wdata_s); + end else begin + up_status <= up_status_s | up_status; + end + end + end + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_rack <= 'd0; + up_rdata <= 'd0; + end else begin + up_rack <= up_rreq_s; + if (up_rreq_s == 1'b1) begin + case (up_raddr_s) + 10'h000: up_rdata <= VERSION; + 10'h002: up_rdata <= up_scratch; + 10'h004: up_rdata <= {31'd0, up_resetn}; + 10'h005: up_rdata <= up_status; + default: up_rdata <= 32'd0; + endcase + end else begin + up_rdata <= 32'd0; + end + end + end + + // instantiations + + genvar n; + generate + for (n = 0; n < NUM_OF_LANES; n = n + 1) begin: g_lanes + axi_xcvrlb_1 i_xcvrlb_1 ( + .ref_clk (ref_clk), + .rx_p (rx_p[n]), + .rx_n (rx_n[n]), + .tx_p (tx_p[n]), + .tx_n (tx_n[n]), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_resetn (up_resetn), + .up_status (up_status_s[n])); + end + endgenerate + + up_axi #(.ADDRESS_WIDTH (8)) i_axi ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_axi_awvalid (s_axi_awvalid), + .up_axi_awaddr (s_axi_awaddr), + .up_axi_awready (s_axi_awready), + .up_axi_wvalid (s_axi_wvalid), + .up_axi_wdata (s_axi_wdata), + .up_axi_wstrb (s_axi_wstrb), + .up_axi_wready (s_axi_wready), + .up_axi_bvalid (s_axi_bvalid), + .up_axi_bresp (s_axi_bresp), + .up_axi_bready (s_axi_bready), + .up_axi_arvalid (s_axi_arvalid), + .up_axi_araddr (s_axi_araddr), + .up_axi_arready (s_axi_arready), + .up_axi_rvalid (s_axi_rvalid), + .up_axi_rresp (s_axi_rresp), + .up_axi_rdata (s_axi_rdata), + .up_axi_rready (s_axi_rready), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata), + .up_rack (up_rack)); + +endmodule + +// *************************************************************************** +// *************************************************************************** + diff --git a/library/xilinx/axi_xcvrlb/axi_xcvrlb_1.v b/library/xilinx/axi_xcvrlb/axi_xcvrlb_1.v new file mode 100644 index 000000000..8e2c5d4e0 --- /dev/null +++ b/library/xilinx/axi_xcvrlb/axi_xcvrlb_1.v @@ -0,0 +1,322 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/1ps + +module axi_xcvrlb_1 ( + + // transceiver interface + + input ref_clk, + input rx_p, + input rx_n, + output tx_p, + output tx_n, + + // processor interface + + input up_rstn, + input up_clk, + input up_resetn, + output up_status); + + // internal registers + + reg [ 3:0] rx_kcount = 'd0; + reg rx_calign = 'd0; + reg [31:0] rx_data = 'd0; + reg [31:0] rx_pn_data = 'd0; + reg tx_charisk = 'd0; + reg [31:0] tx_data = 'd0; + reg [31:0] tx_pn_data = 'd0; + reg [ 3:0] up_pll_rst_cnt = 'd0; + reg [ 3:0] up_rst_cnt = 'd0; + reg [ 6:0] up_user_ready_cnt = 'd0; + reg up_status_int = 'd1; + + // internal signals + + wire clk; + wire rx_status_s; + wire [31:0] rx_pn_data_s; + wire rx_pn_oos_s; + wire rx_pn_err_s; + wire [ 3:0] rx_charisk_s; + wire [ 7:0] rx_error_s; + wire [31:0] rx_data_s; + wire up_pll_rst_s; + wire up_rst_s; + wire up_user_ready_s; + wire up_pll_locked_s; + wire up_rst_done_s; + wire up_pn_oos_s; + wire up_pn_err_s; + wire up_rx_pll_locked_s; + wire up_rx_rst_done_s; + wire up_tx_pll_locked_s; + wire up_tx_rst_done_s; + + // pn31 function + + function [31:0] pn31; + input [31:0] din; + reg [31:0] dout; + begin + dout[31] = din[31] ^ din[28]; + dout[30] = din[30] ^ din[27]; + dout[29] = din[29] ^ din[26]; + dout[28] = din[28] ^ din[25]; + dout[27] = din[27] ^ din[24]; + dout[26] = din[26] ^ din[23]; + dout[25] = din[25] ^ din[22]; + dout[24] = din[24] ^ din[21]; + dout[23] = din[23] ^ din[20]; + dout[22] = din[22] ^ din[19]; + dout[21] = din[21] ^ din[18]; + dout[20] = din[20] ^ din[17]; + dout[19] = din[19] ^ din[16]; + dout[18] = din[18] ^ din[15]; + dout[17] = din[17] ^ din[14]; + dout[16] = din[16] ^ din[13]; + dout[15] = din[15] ^ din[12]; + dout[14] = din[14] ^ din[11]; + dout[13] = din[13] ^ din[10]; + dout[12] = din[12] ^ din[ 9]; + dout[11] = din[11] ^ din[ 8]; + dout[10] = din[10] ^ din[ 7]; + dout[ 9] = din[ 9] ^ din[ 6]; + dout[ 8] = din[ 8] ^ din[ 5]; + dout[ 7] = din[ 7] ^ din[ 4]; + dout[ 6] = din[ 6] ^ din[ 3]; + dout[ 5] = din[ 5] ^ din[ 2]; + dout[ 4] = din[ 4] ^ din[ 1]; + dout[ 3] = din[ 3] ^ din[ 0]; + dout[ 2] = din[ 2] ^ din[31] ^ din[28]; + dout[ 1] = din[ 1] ^ din[30] ^ din[27]; + dout[ 0] = din[ 0] ^ din[29] ^ din[26]; + pn31 = dout; + end + endfunction + + // receive + + assign rx_status_s = ~(| rx_error_s); + assign rx_pn_data_s = (rx_pn_oos_s == 1'b1) ? rx_data : rx_pn_data; + + always @(posedge clk) begin + if (rx_status_s == 1'b0) begin + rx_kcount <= 4'd0; + rx_calign <= 1'd1; + end else if ((rx_charisk_s == 4'hf) && (rx_data_s == {4{8'hbc}})) begin + rx_kcount <= rx_kcount + 1'b1; + if (rx_kcount == 4'hf) begin + rx_calign <= 1'd0; + end + end + end + + always @(posedge clk) begin + if (rx_status_s == 1'b1) begin + rx_data[31:24] = rx_data_s[ 7: 0]; + rx_data[23:16] = rx_data_s[15: 8]; + rx_data[15: 8] = rx_data_s[23:16]; + rx_data[ 7: 0] = rx_data_s[31:24]; + end else begin + rx_data[31:24] = 8'hff; + rx_data[23:16] = 8'hff; + rx_data[15: 8] = 8'hff; + rx_data[ 7: 0] = 8'hff; + end + rx_pn_data <= pn31(rx_pn_data_s); + end + + // transmit + + always @(posedge clk) begin + if (rx_calign == 1'b0) begin + tx_charisk <= 1'd0; + tx_data[31:24] <= tx_pn_data[ 7: 0]; + tx_data[23:16] <= tx_pn_data[15: 8]; + tx_data[15: 8] <= tx_pn_data[23:16]; + tx_data[ 7: 0] <= tx_pn_data[31:24]; + tx_pn_data <= pn31(tx_pn_data); + end else begin + tx_charisk <= 1'd1; + tx_data[31:24] <= 8'hbc; + tx_data[23:16] <= 8'hbc; + tx_data[15: 8] <= 8'hbc; + tx_data[ 7: 0] <= 8'hbc; + tx_pn_data <= {32{1'b1}}; + end + end + + // reset & init + + assign up_status = up_status_int; + assign up_pll_rst_s = up_pll_rst_cnt[3]; + assign up_rst_s = up_rst_cnt[3]; + assign up_user_ready_s = up_user_ready_cnt[6]; + assign up_pll_locked_s = up_rx_pll_locked_s & up_tx_pll_locked_s; + assign up_rst_done_s = up_rx_rst_done_s & up_tx_rst_done_s; + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_pll_rst_cnt <= 4'h8; + up_rst_cnt <= 4'h8; + up_user_ready_cnt <= 7'h00; + up_status_int <= 1'b1; + end else begin + if (up_resetn == 1'b0) begin + up_pll_rst_cnt <= 4'h8; + end else if (up_pll_rst_cnt[3] == 1'b1) begin + up_pll_rst_cnt <= up_pll_rst_cnt + 1'b1; + end + if ((up_resetn == 1'b0) || (up_pll_rst_cnt[3] == 1'b1) || + (up_pll_locked_s == 1'b0)) begin + up_rst_cnt <= 4'h8; + end else if (up_rst_cnt[3] == 1'b1) begin + up_rst_cnt <= up_rst_cnt + 1'b1; + end + if ((up_resetn == 1'b0) || (up_rst_cnt[3] == 1'b1)) begin + up_user_ready_cnt <= 7'h00; + end else if (up_user_ready_cnt[6] == 1'b0) begin + up_user_ready_cnt <= up_user_ready_cnt + 1'b1; + end + if ((up_resetn == 1'b0) || (up_rst_done_s == 1'b0)) begin + up_status_int <= 1'b1; + end else begin + up_status_int <= up_pn_oos_s | up_pn_err_s; + end + end + end + + // instantiations + + ad_pnmon #(.DATA_WIDTH(32)) i_pnmon ( + .adc_clk (clk), + .adc_valid_in (1'b1), + .adc_data_in (rx_data), + .adc_data_pn (rx_pn_data), + .adc_pn_oos (rx_pn_oos_s), + .adc_pn_err (rx_pn_err_s)); + + up_xfer_status #(.DATA_WIDTH(2)) i_xfer_status ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_data_status ({up_pn_err_s, up_pn_oos_s}), + .d_rst (1'b0), + .d_clk (clk), + .d_data_status ({rx_pn_err_s, rx_pn_oos_s})); + + util_adxcvr_xch #( + .XCVR_ID (0), + .XCVR_TYPE (0), + .CPLL_FBDIV (2), + .CPLL_FBDIV_4_5 (5), + .TX_OUT_DIV (1), + .TX_CLK25_DIV (10), + .RX_OUT_DIV (1), + .RX_CLK25_DIV (10), + .RX_DFE_LPM_CFG (16'h0904), + .RX_PMA_CFG ('h00018480), + .RX_CDR_CFG ('h03000023ff10200020)) + i_xch ( + .qpll2ch_clk (1'b0), + .qpll2ch_ref_clk (1'b0), + .qpll2ch_locked (1'b1), + .cpll_ref_clk (ref_clk), + .up_cpll_rst (up_pll_rst_s), + .rx_p (rx_p), + .rx_n (rx_n), + .rx_out_clk (clk), + .rx_clk (clk), + .rx_charisk (rx_charisk_s), + .rx_disperr (rx_error_s[3:0]), + .rx_notintable (rx_error_s[7:4]), + .rx_data (rx_data_s), + .rx_calign (rx_calign), + .tx_p (tx_p), + .tx_n (tx_n), + .tx_out_clk (), + .tx_clk (clk), + .tx_charisk ({4{tx_charisk}}), + .tx_data (tx_data), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_es_sel (1'd0), + .up_es_enb (1'd0), + .up_es_addr (12'd0), + .up_es_wr (1'd0), + .up_es_wdata (16'd0), + .up_es_rdata (), + .up_es_ready (), + .up_rx_pll_locked (up_rx_pll_locked_s), + .up_rx_rst (up_rst_s), + .up_rx_user_ready (up_user_ready_s), + .up_rx_rst_done (up_rx_rst_done_s), + .up_rx_lpm_dfe_n (1'd0), + .up_rx_rate (3'd0), + .up_rx_sys_clk_sel (2'd0), + .up_rx_out_clk_sel (3'd2), + .up_rx_sel (1'd0), + .up_rx_enb (1'd0), + .up_rx_addr (12'd0), + .up_rx_wr (1'd0), + .up_rx_wdata (16'd0), + .up_rx_rdata (), + .up_rx_ready (), + .up_tx_pll_locked (up_tx_pll_locked_s), + .up_tx_rst (up_rst_s), + .up_tx_user_ready (up_user_ready_s), + .up_tx_rst_done (up_tx_rst_done_s), + .up_tx_lpm_dfe_n (1'd0), + .up_tx_rate (3'd0), + .up_tx_sys_clk_sel (2'd0), + .up_tx_out_clk_sel (3'd2), + .up_tx_sel (1'd0), + .up_tx_enb (1'd0), + .up_tx_addr (12'd0), + .up_tx_wr (1'd0), + .up_tx_wdata (16'd0), + .up_tx_rdata (), + .up_tx_ready ()); + +endmodule + +// *************************************************************************** +// *************************************************************************** + diff --git a/library/xilinx/axi_xcvrlb/axi_xcvrlb_constr.xdc b/library/xilinx/axi_xcvrlb/axi_xcvrlb_constr.xdc new file mode 100644 index 000000000..89ed37ca6 --- /dev/null +++ b/library/xilinx/axi_xcvrlb/axi_xcvrlb_constr.xdc @@ -0,0 +1,12 @@ + +set_property shreg_extract no [get_cells -hier -filter {name =~ *d_xfer_state*}] +set_property shreg_extract no [get_cells -hier -filter {name =~ *up_xfer_toggle*}] +set_property shreg_extract no [get_cells -hier -filter {name =~ *up_rx_rst_done*}] +set_property shreg_extract no [get_cells -hier -filter {name =~ *up_tx_rst_done*}] + +set_false_path -to [get_cells -hier -filter {name =~ *up_rx_rst_done_m1_reg && IS_SEQUENTIAL}] +set_false_path -to [get_cells -hier -filter {name =~ *up_tx_rst_done_m1_reg && IS_SEQUENTIAL}] +set_false_path -to [get_cells -hier -filter {name =~ *d_xfer_state_m1_reg && IS_SEQUENTIAL}] +set_false_path -to [get_cells -hier -filter {name =~ *up_xfer_toggle_m1_reg && IS_SEQUENTIAL}] +set_false_path -to [get_cells -hier -filter {name =~ *up_data_status* && IS_SEQUENTIAL}] + diff --git a/library/xilinx/axi_xcvrlb/axi_xcvrlb_ip.tcl b/library/xilinx/axi_xcvrlb/axi_xcvrlb_ip.tcl new file mode 100644 index 000000000..965d9a64b --- /dev/null +++ b/library/xilinx/axi_xcvrlb/axi_xcvrlb_ip.tcl @@ -0,0 +1,60 @@ + +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip.tcl + +adi_ip_create axi_xcvrlb +adi_ip_files axi_xcvrlb [list \ + "$ad_hdl_dir/library/xilinx/util_adxcvr/util_adxcvr_xch.v" \ + "$ad_hdl_dir/library/common/up_xfer_status.v" \ + "$ad_hdl_dir/library/common/ad_pnmon.v" \ + "$ad_hdl_dir/library/common/up_axi.v" \ + "axi_xcvrlb_constr.xdc" \ + "axi_xcvrlb_1.v" \ + "axi_xcvrlb.v" ] + +adi_ip_properties_lite axi_xcvrlb +adi_ip_constraints axi_xcvrlb "axi_xcvrlb_constr.xdc" + +ipx::remove_all_bus_interface [ipx::current_core] + +set_property driver_value 0 [ipx::get_ports -filter "direction==in" -of_objects [ipx::current_core]] + +ipx::infer_bus_interface {\ + s_axi_awvalid \ + s_axi_awaddr \ + s_axi_awprot \ + s_axi_awready \ + s_axi_wvalid \ + s_axi_wdata \ + s_axi_wstrb \ + s_axi_wready \ + s_axi_bvalid \ + s_axi_bresp \ + s_axi_bready \ + s_axi_arvalid \ + s_axi_araddr \ + s_axi_arprot \ + s_axi_arready \ + s_axi_rvalid \ + s_axi_rdata \ + s_axi_rresp \ + s_axi_rready} \ +xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] + +ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] +ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] + +ipx::add_bus_parameter ASSOCIATED_BUSIF [ipx::get_bus_interfaces s_axi_aclk \ + -of_objects [ipx::current_core]] +set_property value s_axi [ipx::get_bus_parameters ASSOCIATED_BUSIF \ + -of_objects [ipx::get_bus_interfaces s_axi_aclk \ + -of_objects [ipx::current_core]]] + +ipx::add_memory_map {s_axi} [ipx::current_core] +set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] +ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] +set_property range {1024} [ipx::get_address_blocks axi_lite \ + -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] + +ipx::save_core [ipx::current_core] + diff --git a/library/common/altera/MULT_MACRO.v b/library/xilinx/common/ad_cmos_clk.v similarity index 77% rename from library/common/altera/MULT_MACRO.v rename to library/xilinx/common/ad_cmos_clk.v index 54e6207ec..bbd9d8e1f 100644 --- a/library/common/altera/MULT_MACRO.v +++ b/library/xilinx/common/ad_cmos_clk.v @@ -34,48 +34,54 @@ // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // *************************************************************************** // *************************************************************************** -// replacing Xilinx's macro with Altera's LPM -`timescale 1ps/1ps +`timescale 1ns/100ps -module MULT_MACRO ( +module ad_cmos_clk ( - CE, - RST, - CLK, - A, - B, - P); + rst, + locked, - parameter LATENCY = 3; - parameter WIDTH_A = 16; - parameter WIDTH_B = 16; + clk_in, + clk); - localparam WIDTH_P = WIDTH_A + WIDTH_B; + parameter DEVICE_TYPE = 0; + localparam SERIES7 = 0; + localparam VIRTEX6 = 1; - input CE; - input RST; - input CLK; + input rst; + output locked; - input [WIDTH_A-1:0] A; - input [WIDTH_B-1:0] B; - output [WIDTH_P-1:0] P; + input clk_in; + output clk; - lpm_mult #( - .lpm_type ("lpm_mult"), - .lpm_widtha (WIDTH_A), - .lpm_widthb (WIDTH_B), - .lpm_widthp (WIDTH_P), - .lpm_representation ("SIGNED"), - .lpm_pipeline (3)) - i_lpm_mult ( - .clken (CE), - .aclr (RST), - .sum (1'b0), - .clock (CLK), - .dataa (A), - .datab (B), - .result (P)); + // wires + + wire clk_ibuf_s; + + // defaults + + assign locked = 1'b1; + + // instantiations + + IBUFG i_rx_clk_ibuf ( + .I (clk_in), + .O (clk_ibuf_s)); + + generate + if (DEVICE_TYPE == VIRTEX6) begin + BUFR #(.BUFR_DIVIDE("BYPASS")) i_clk_rbuf ( + .CLR (1'b0), + .CE (1'b1), + .I (clk_ibuf_s), + .O (clk)); + end else begin + BUFG i_clk_gbuf ( + .I (clk_ibuf_s), + .O (clk)); + end + endgenerate endmodule diff --git a/library/common/ad_lvds_in.v b/library/xilinx/common/ad_cmos_in.v similarity index 91% rename from library/common/ad_lvds_in.v rename to library/xilinx/common/ad_cmos_in.v index 9e977b193..cf2081778 100644 --- a/library/common/ad_lvds_in.v +++ b/library/xilinx/common/ad_cmos_in.v @@ -34,18 +34,15 @@ // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // *************************************************************************** // *************************************************************************** -// *************************************************************************** -// *************************************************************************** `timescale 1ns/100ps -module ad_lvds_in ( +module ad_cmos_in ( // data interface rx_clk, - rx_data_in_p, - rx_data_in_n, + rx_data_in, rx_data_p, rx_data_n, @@ -74,8 +71,7 @@ module ad_lvds_in ( // data interface input rx_clk; - input rx_data_in_p; - input rx_data_in_n; + input rx_data_in; output rx_data_p; output rx_data_n; @@ -118,20 +114,11 @@ module ad_lvds_in ( // receive data interface, ibuf -> idelay -> iddr - generate - if (SINGLE_ENDED == 1) begin - assign tx_data_out_n = 1'b0; - IBUF i_rx_data_ibuf ( - .I (rx_data_in_p), - .O (rx_data_ibuf_s)); - end else begin - IBUFDS i_rx_data_ibuf ( - .I (rx_data_in_p), - .IB (rx_data_in_n), + IBUF i_rx_data_ibuf ( + .I (rx_data_in), .O (rx_data_ibuf_s)); - end - endgenerate + generate if (DEVICE_TYPE == VIRTEX6) begin (* IODELAY_GROUP = IODELAY_GROUP *) IODELAYE1 #( @@ -183,6 +170,7 @@ module ad_lvds_in ( .CNTVALUEIN (up_dwdata), .CNTVALUEOUT (up_drdata)); end + endgenerate IDDR #( .DDR_CLK_EDGE ("SAME_EDGE_PIPELINED"), diff --git a/library/common/ad_lvds_out.v b/library/xilinx/common/ad_cmos_out.v similarity index 93% rename from library/common/ad_lvds_out.v rename to library/xilinx/common/ad_cmos_out.v index 5c3cdfd88..9537d6dd1 100644 --- a/library/common/ad_lvds_out.v +++ b/library/xilinx/common/ad_cmos_out.v @@ -37,15 +37,14 @@ `timescale 1ns/100ps -module ad_lvds_out ( +module ad_cmos_out ( // data interface tx_clk, tx_data_p, tx_data_n, - tx_data_out_p, - tx_data_out_n, + tx_data_out, // delay-data interface @@ -75,8 +74,7 @@ module ad_lvds_out ( input tx_clk; input tx_data_p; input tx_data_n; - output tx_data_out_p; - output tx_data_out_n; + output tx_data_out; // delay-data interface @@ -156,19 +154,9 @@ module ad_lvds_out ( end endgenerate - generate - if (SINGLE_ENDED == 1) begin - assign tx_data_out_n = 1'b0; OBUF i_tx_data_obuf ( .I (tx_data_odelay_s), - .O (tx_data_out_p)); - end else begin - OBUFDS i_tx_data_obuf ( - .I (tx_data_odelay_s), - .O (tx_data_out_p), - .OB (tx_data_out_n)); - end - endgenerate + .O (tx_data_out)); endmodule diff --git a/library/common/ad_iobuf.v b/library/xilinx/common/ad_iobuf.v similarity index 100% rename from library/common/ad_iobuf.v rename to library/xilinx/common/ad_iobuf.v diff --git a/library/common/ad_lvds_clk.v b/library/xilinx/common/ad_lvds_clk.v similarity index 96% rename from library/common/ad_lvds_clk.v rename to library/xilinx/common/ad_lvds_clk.v index e65ea434f..a4c0ca153 100644 --- a/library/common/ad_lvds_clk.v +++ b/library/xilinx/common/ad_lvds_clk.v @@ -41,14 +41,20 @@ module ad_lvds_clk ( + rst, + locked, + clk_in_p, clk_in_n, clk); - parameter DEVICE_TYPE = 0; + parameter DEVICE_TYPE = 0; localparam SERIES7 = 0; localparam VIRTEX6 = 1; + input rst; + output locked; + input clk_in_p; input clk_in_n; output clk; @@ -57,6 +63,10 @@ module ad_lvds_clk ( wire clk_ibuf_s; + // defaults + + assign locked = 1'b1; + // instantiations IBUFGDS i_rx_clk_ibuf ( diff --git a/library/xilinx/common/ad_lvds_in.v b/library/xilinx/common/ad_lvds_in.v new file mode 100644 index 000000000..4e8530ac7 --- /dev/null +++ b/library/xilinx/common/ad_lvds_in.v @@ -0,0 +1,314 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2014(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module ad_lvds_in #( + + // parameters + + parameter SINGLE_ENDED = 0, + parameter DEVICE_TYPE = 0, + parameter IODELAY_CTRL = 0, + parameter IODELAY_GROUP = "dev_if_delay_group") ( + + // data interface + + input rx_clk, + input rx_data_in_p, + input rx_data_in_n, + output rx_data_p, + output rx_data_n, + + // delay-data interface + + input up_clk, + input up_dld, + input [ 4:0] up_dwdata, + output [ 4:0] up_drdata, + + // delay-cntrl interface + + input delay_clk, + input delay_rst, + output delay_locked); + + // internal parameters + + localparam VIRTEX7 = 0; + localparam VIRTEX6 = 1; + localparam ULTRASCALE_PLUS = 2; + localparam ULTRASCALE = 3; + + // internal registers + + reg rx_data_n_d = 'd0; + + // internal signals + + wire rx_data_n_s; + wire rx_data_ibuf_s; + wire rx_data_idelay_s; + wire [ 8:0] up_drdata_s; + + // delay controller + + generate + if ((IODELAY_CTRL == 1) && (DEVICE_TYPE == ULTRASCALE_PLUS)) begin + (* IODELAY_GROUP = IODELAY_GROUP *) + IDELAYCTRL #(.SIM_DEVICE ("ULTRASCALE")) i_delay_ctrl ( + .RST (delay_rst), + .REFCLK (delay_clk), + .RDY (delay_locked)); + end + endgenerate + + generate + if ((IODELAY_CTRL == 1) && (DEVICE_TYPE == ULTRASCALE)) begin + (* IODELAY_GROUP = IODELAY_GROUP *) + IDELAYCTRL #(.SIM_DEVICE ("ULTRASCALE")) i_delay_ctrl ( + .RST (delay_rst), + .REFCLK (delay_clk), + .RDY (delay_locked)); + end + endgenerate + + generate + if ((IODELAY_CTRL == 1) && ((DEVICE_TYPE == VIRTEX7) || (DEVICE_TYPE == VIRTEX6))) begin + (* IODELAY_GROUP = IODELAY_GROUP *) + IDELAYCTRL i_delay_ctrl ( + .RST (delay_rst), + .REFCLK (delay_clk), + .RDY (delay_locked)); + end + endgenerate + + generate + if (IODELAY_CTRL == 0) begin + assign delay_locked = 1'b1; + end + endgenerate + + // receive data interface, ibuf -> idelay -> iddr + + generate + if (SINGLE_ENDED == 1) begin + IBUF i_rx_data_ibuf ( + .I (rx_data_in_p), + .O (rx_data_ibuf_s)); + end else begin + IBUFDS i_rx_data_ibuf ( + .I (rx_data_in_p), + .IB (rx_data_in_n), + .O (rx_data_ibuf_s)); + end + endgenerate + + // idelay + + generate + if (DEVICE_TYPE == VIRTEX6) begin + (* IODELAY_GROUP = IODELAY_GROUP *) + IODELAYE1 #( + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("I"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .IDELAY_TYPE ("VAR_LOADABLE"), + .IDELAY_VALUE (0), + .ODELAY_TYPE ("FIXED"), + .ODELAY_VALUE (0), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA")) + i_rx_data_idelay ( + .T (1'b1), + .CE (1'b0), + .INC (1'b0), + .CLKIN (1'b0), + .DATAIN (1'b0), + .ODATAIN (1'b0), + .CINVCTRL (1'b0), + .C (up_clk), + .IDATAIN (rx_data_ibuf_s), + .DATAOUT (rx_data_idelay_s), + .RST (up_dld), + .CNTVALUEIN (up_dwdata), + .CNTVALUEOUT (up_drdata)); + end + endgenerate + + generate + if (DEVICE_TYPE == VIRTEX7) begin + (* IODELAY_GROUP = IODELAY_GROUP *) + IDELAYE2 #( + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("IDATAIN"), + .HIGH_PERFORMANCE_MODE ("FALSE"), + .IDELAY_TYPE ("VAR_LOAD"), + .IDELAY_VALUE (0), + .REFCLK_FREQUENCY (200.0), + .PIPE_SEL ("FALSE"), + .SIGNAL_PATTERN ("DATA")) + i_rx_data_idelay ( + .CE (1'b0), + .INC (1'b0), + .DATAIN (1'b0), + .LDPIPEEN (1'b0), + .CINVCTRL (1'b0), + .REGRST (1'b0), + .C (up_clk), + .IDATAIN (rx_data_ibuf_s), + .DATAOUT (rx_data_idelay_s), + .LD (up_dld), + .CNTVALUEIN (up_dwdata), + .CNTVALUEOUT (up_drdata)); + end + endgenerate + + generate + if (DEVICE_TYPE == ULTRASCALE) begin + assign up_drdata = up_drdata_s[8:4]; + (* IODELAY_GROUP = IODELAY_GROUP *) + IDELAYE3 #( + .SIM_DEVICE ("ULTRASCALE"), + .DELAY_SRC ("IDATAIN"), + .DELAY_TYPE ("VAR_LOAD"), + .REFCLK_FREQUENCY (200.0), + .DELAY_FORMAT ("COUNT")) + i_rx_data_idelay ( + .CASC_RETURN (1'b0), + .CASC_IN (1'b0), + .CASC_OUT (), + .CE (1'b0), + .CLK (up_clk), + .INC (1'b0), + .LOAD (up_dld), + .CNTVALUEIN ({up_dwdata, 4'd0}), + .CNTVALUEOUT (up_drdata_s), + .DATAIN (1'b0), + .IDATAIN (rx_data_ibuf_s), + .DATAOUT (rx_data_idelay_s), + .RST (1'b0), + .EN_VTC (~up_dld)); + end + endgenerate + + generate + if (DEVICE_TYPE == ULTRASCALE_PLUS) begin + assign up_drdata = up_drdata_s[8:4]; + (* IODELAY_GROUP = IODELAY_GROUP *) + IDELAYE3 #( + .SIM_DEVICE ("ULTRASCALE_PLUS_ES1"), + .DELAY_SRC ("IDATAIN"), + .DELAY_TYPE ("VAR_LOAD"), + .REFCLK_FREQUENCY (200.0), + .DELAY_FORMAT ("COUNT")) + i_rx_data_idelay ( + .CASC_RETURN (1'b0), + .CASC_IN (1'b0), + .CASC_OUT (), + .CE (1'b0), + .CLK (up_clk), + .INC (1'b0), + .LOAD (up_dld), + .CNTVALUEIN ({up_dwdata, 4'd0}), + .CNTVALUEOUT (up_drdata_s), + .DATAIN (1'b0), + .IDATAIN (rx_data_ibuf_s), + .DATAOUT (rx_data_idelay_s), + .RST (1'b0), + .EN_VTC (~up_dld)); + end + endgenerate + + // iddr + + generate + if (DEVICE_TYPE == ULTRASCALE) begin + IDDRE1 #( + .DDR_CLK_EDGE ("SAME_EDGE_PIPELINED")) + i_rx_data_iddr ( + .R (1'b0), + .C (rx_clk), + .CB (~rx_clk), + .D (rx_data_idelay_s), + .Q1 (rx_data_p), + .Q2 (rx_data_n_s)); + end + endgenerate + + generate + if (DEVICE_TYPE == ULTRASCALE_PLUS) begin + IDDRE1 #( + .DDR_CLK_EDGE ("SAME_EDGE_PIPELINED")) + i_rx_data_iddr ( + .R (1'b0), + .C (rx_clk), + .CB (~rx_clk), + .D (rx_data_idelay_s), + .Q1 (rx_data_p), + .Q2 (rx_data_n_s)); + end + endgenerate + + generate + if ((DEVICE_TYPE == VIRTEX7) || (DEVICE_TYPE == VIRTEX6)) begin + IDDR #( + .DDR_CLK_EDGE ("SAME_EDGE_PIPELINED"), + .INIT_Q1 (1'b0), + .INIT_Q2 (1'b0), + .SRTYPE ("ASYNC")) + i_rx_data_iddr ( + .CE (1'b1), + .R (1'b0), + .S (1'b0), + .C (rx_clk), + .D (rx_data_idelay_s), + .Q1 (rx_data_p), + .Q2 (rx_data_n_s)); + end + endgenerate + + assign rx_data_n = rx_data_n_d; + + always @(posedge rx_clk) begin + rx_data_n_d <= rx_data_n_s; + end + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/library/xilinx/common/ad_lvds_out.v b/library/xilinx/common/ad_lvds_out.v new file mode 100644 index 000000000..1cbc93389 --- /dev/null +++ b/library/xilinx/common/ad_lvds_out.v @@ -0,0 +1,188 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2014(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module ad_lvds_out ( + + // data interface + + tx_clk, + tx_data_p, + tx_data_n, + tx_data_out_p, + tx_data_out_n, + + // delay-data interface + + up_clk, + up_dld, + up_dwdata, + up_drdata, + + // delay-cntrl interface + + delay_clk, + delay_rst, + delay_locked); + + // parameters + + parameter DEVICE_TYPE = 0; + parameter SINGLE_ENDED = 0; + parameter IODELAY_ENABLE = 0; + parameter IODELAY_CTRL = 0; + parameter IODELAY_GROUP = "dev_if_delay_group"; + localparam VIRTEX7 = 0; + localparam VIRTEX6 = 1; + localparam ULTRASCALE = 2; + + // data interface + + input tx_clk; + input tx_data_p; + input tx_data_n; + output tx_data_out_p; + output tx_data_out_n; + + // delay-data interface + + input up_clk; + input up_dld; + input [ 4:0] up_dwdata; + output [ 4:0] up_drdata; + + // delay-cntrl interface + + input delay_clk; + input delay_rst; + output delay_locked; + + // internal signals + + wire tx_data_oddr_s; + wire tx_data_odelay_s; + + // delay controller + + generate + if ((IODELAY_ENABLE == 1) && (DEVICE_TYPE == VIRTEX7) && (IODELAY_CTRL == 1)) begin + (* IODELAY_GROUP = IODELAY_GROUP *) + IDELAYCTRL i_delay_ctrl ( + .RST (delay_rst), + .REFCLK (delay_clk), + .RDY (delay_locked)); + end else begin + assign delay_locked = 1'b1; + end + endgenerate + + // transmit data interface, oddr -> odelay -> obuf + + generate + if (DEVICE_TYPE == ULTRASCALE) begin + ODDRE1 i_tx_data_oddr ( + .SR (1'b0), + .C (tx_clk), + .D1 (tx_data_p), + .D2 (tx_data_n), + .Q (tx_data_oddr_s)); + end else begin + ODDR #( + .DDR_CLK_EDGE ("SAME_EDGE"), + .INIT (1'b0), + .SRTYPE ("ASYNC")) + i_tx_data_oddr ( + .CE (1'b1), + .R (1'b0), + .S (1'b0), + .C (tx_clk), + .D1 (tx_data_p), + .D2 (tx_data_n), + .Q (tx_data_oddr_s)); + end + endgenerate + + generate + if ((IODELAY_ENABLE == 1) && (DEVICE_TYPE == VIRTEX7)) begin + (* IODELAY_GROUP = IODELAY_GROUP *) + ODELAYE2 #( + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("ODATAIN"), + .HIGH_PERFORMANCE_MODE ("FALSE"), + .ODELAY_TYPE ("VAR_LOAD"), + .ODELAY_VALUE (0), + .REFCLK_FREQUENCY (200.0), + .PIPE_SEL ("FALSE"), + .SIGNAL_PATTERN ("DATA")) + i_tx_data_odelay ( + .CE (1'b0), + .CLKIN (1'b0), + .INC (1'b0), + .LDPIPEEN (1'b0), + .CINVCTRL (1'b0), + .REGRST (1'b0), + .C (up_clk), + .ODATAIN (tx_data_oddr_s), + .DATAOUT (tx_data_odelay_s), + .LD (up_dld), + .CNTVALUEIN (up_dwdata), + .CNTVALUEOUT (up_drdata)); + end else begin + assign up_drdata = 5'd0; + assign tx_data_odelay_s = tx_data_oddr_s; + end + endgenerate + + generate + if (SINGLE_ENDED == 1) begin + assign tx_data_out_n = 1'b0; + OBUF i_tx_data_obuf ( + .I (tx_data_odelay_s), + .O (tx_data_out_p)); + end else begin + OBUFDS i_tx_data_obuf ( + .I (tx_data_odelay_s), + .O (tx_data_out_p), + .OB (tx_data_out_n)); + end + endgenerate + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/library/common/ad_mmcm_drp.v b/library/xilinx/common/ad_mmcm_drp.v similarity index 51% rename from library/common/ad_mmcm_drp.v rename to library/xilinx/common/ad_mmcm_drp.v index e423ad03b..a8201cc05 100644 --- a/library/common/ad_mmcm_drp.v +++ b/library/xilinx/common/ad_mmcm_drp.v @@ -1,9 +1,9 @@ // *************************************************************************** // *************************************************************************** // Copyright 2011(c) Analog Devices, Inc. -// +// // All rights reserved. -// +// // Redistribution and use in source and binary forms, with or without modification, // are permitted provided that the following conditions are met: // - Redistributions of source code must retain the above copyright @@ -21,16 +21,16 @@ // patent holders to use this software. // - Use of the software either in source or binary form, must be run // on or directly connected to an Analog Devices Inc. component. -// +// // THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, // INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A // PARTICULAR PURPOSE ARE DISCLAIMED. // // IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, // EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY -// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR // BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // *************************************************************************** // *************************************************************************** @@ -44,10 +44,11 @@ module ad_mmcm_drp ( clk, clk2, - mmcm_rst, clk_sel, + mmcm_rst, mmcm_clk_0, mmcm_clk_1, + mmcm_clk_2, // drp interface @@ -72,16 +73,21 @@ module ad_mmcm_drp ( parameter MMCM_VCO_DIV = 6; parameter MMCM_VCO_MUL = 12.000; parameter MMCM_CLK0_DIV = 2.000; + parameter MMCM_CLK0_PHASE = 0.000; parameter MMCM_CLK1_DIV = 6; + parameter MMCM_CLK1_PHASE = 0.000; + parameter MMCM_CLK2_DIV = 2.000; + parameter MMCM_CLK2_PHASE = 0.000; // clocks input clk; input clk2; - input mmcm_rst; input clk_sel; + input mmcm_rst; output mmcm_clk_0; output mmcm_clk_1; + output mmcm_clk_2; // drp interface @@ -108,6 +114,7 @@ module ad_mmcm_drp ( wire mmcm_fb_clk_s; wire mmcm_clk_0_s; wire mmcm_clk_1_s; + wire mmcm_clk_2_s; wire mmcm_locked_s; wire [15:0] up_drp_rdata_s; wire up_drp_ready_s; @@ -131,125 +138,141 @@ module ad_mmcm_drp ( // instantiations generate - if (MMCM_DEVICE_TYPE == MMCM_DEVICE_VIRTEX6) begin - MMCM_ADV #( - .BANDWIDTH ("OPTIMIZED"), - .CLKOUT4_CASCADE ("FALSE"), - .CLOCK_HOLD ("FALSE"), - .COMPENSATION ("ZHOLD"), - .STARTUP_WAIT ("FALSE"), - .DIVCLK_DIVIDE (MMCM_VCO_DIV), - .CLKFBOUT_MULT_F (MMCM_VCO_MUL), - .CLKFBOUT_PHASE (0.000), - .CLKFBOUT_USE_FINE_PS ("FALSE"), - .CLKOUT0_DIVIDE_F (MMCM_CLK0_DIV), - .CLKOUT0_PHASE (0.000), - .CLKOUT0_DUTY_CYCLE (0.500), - .CLKOUT0_USE_FINE_PS ("FALSE"), - .CLKOUT1_DIVIDE (MMCM_CLK1_DIV), - .CLKOUT1_PHASE (0.000), - .CLKOUT1_DUTY_CYCLE (0.500), - .CLKOUT1_USE_FINE_PS ("FALSE"), - .CLKIN1_PERIOD (MMCM_CLKIN_PERIOD), - .CLKIN2_PERIOD (MMCM_CLKIN2_PERIOD), - .REF_JITTER1 (0.010)) - i_mmcm ( - .CLKIN1 (clk), - .CLKFBIN (bufg_fb_clk_s), - .CLKFBOUT (mmcm_fb_clk_s), - .CLKOUT0 (mmcm_clk_0_s), - .CLKOUT1 (mmcm_clk_1_s), - .LOCKED (mmcm_locked_s), - .DCLK (up_clk), - .DEN (up_drp_sel), - .DADDR (up_drp_addr[6:0]), - .DWE (up_drp_wr), - .DI (up_drp_wdata), - .DO (up_drp_rdata_s), - .DRDY (up_drp_ready_s), - .CLKFBOUTB (), - .CLKOUT0B (), - .CLKOUT1B (), - .CLKOUT2 (), - .CLKOUT2B (), - .CLKOUT3 (), - .CLKOUT3B (), - .CLKOUT4 (), - .CLKOUT5 (), - .CLKOUT6 (), - .CLKIN2 (clk2), - .CLKINSEL (clk_sel), - .PSCLK (1'b0), - .PSEN (1'b0), - .PSINCDEC (1'b0), - .PSDONE (), - .CLKINSTOPPED (), - .CLKFBSTOPPED (), - .PWRDWN (1'b0), - .RST (mmcm_rst)); - end - if (MMCM_DEVICE_TYPE == MMCM_DEVICE_7SERIES) begin - MMCME2_ADV #( - .BANDWIDTH ("OPTIMIZED"), - .CLKOUT4_CASCADE ("FALSE"), - .COMPENSATION ("ZHOLD"), - .STARTUP_WAIT ("FALSE"), - .DIVCLK_DIVIDE (MMCM_VCO_DIV), - .CLKFBOUT_MULT_F (MMCM_VCO_MUL), - .CLKFBOUT_PHASE (0.000), - .CLKFBOUT_USE_FINE_PS ("FALSE"), - .CLKOUT0_DIVIDE_F (MMCM_CLK0_DIV), - .CLKOUT0_PHASE (0.000), - .CLKOUT0_DUTY_CYCLE (0.500), - .CLKOUT0_USE_FINE_PS ("FALSE"), - .CLKOUT1_DIVIDE (MMCM_CLK1_DIV), - .CLKOUT1_PHASE (0.000), - .CLKOUT1_DUTY_CYCLE (0.500), - .CLKOUT1_USE_FINE_PS ("FALSE"), - .CLKIN1_PERIOD (MMCM_CLKIN_PERIOD), - .CLKIN2_PERIOD (MMCM_CLKIN2_PERIOD), - .REF_JITTER1 (0.010)) - i_mmcm ( - .CLKIN1 (clk), - .CLKFBIN (bufg_fb_clk_s), - .CLKFBOUT (mmcm_fb_clk_s), - .CLKOUT0 (mmcm_clk_0_s), - .CLKOUT1 (mmcm_clk_1_s), - .LOCKED (mmcm_locked_s), - .DCLK (up_clk), - .DEN (up_drp_sel), - .DADDR (up_drp_addr[6:0]), - .DWE (up_drp_wr), - .DI (up_drp_wdata), - .DO (up_drp_rdata_s), - .DRDY (up_drp_ready_s), - .CLKFBOUTB (), - .CLKOUT0B (), - .CLKOUT1B (), - .CLKOUT2 (), - .CLKOUT2B (), - .CLKOUT3 (), - .CLKOUT3B (), - .CLKOUT4 (), - .CLKOUT5 (), - .CLKOUT6 (), - .CLKIN2 (clk2), - .CLKINSEL (clk_sel), - .PSCLK (1'b0), - .PSEN (1'b0), - .PSINCDEC (1'b0), - .PSDONE (), - .CLKINSTOPPED (), - .CLKFBSTOPPED (), - .PWRDWN (1'b0), - .RST (mmcm_rst)); + MMCME2_ADV #( + .BANDWIDTH ("OPTIMIZED"), + .CLKOUT4_CASCADE ("FALSE"), + .COMPENSATION ("ZHOLD"), + .STARTUP_WAIT ("FALSE"), + .DIVCLK_DIVIDE (MMCM_VCO_DIV), + .CLKFBOUT_MULT_F (MMCM_VCO_MUL), + .CLKFBOUT_PHASE (0.000), + .CLKFBOUT_USE_FINE_PS ("FALSE"), + .CLKOUT0_DIVIDE_F (MMCM_CLK0_DIV), + .CLKOUT0_PHASE (MMCM_CLK0_PHASE), + .CLKOUT0_DUTY_CYCLE (0.500), + .CLKOUT0_USE_FINE_PS ("FALSE"), + .CLKOUT1_DIVIDE (MMCM_CLK1_DIV), + .CLKOUT1_PHASE (MMCM_CLK1_PHASE), + .CLKOUT1_DUTY_CYCLE (0.500), + .CLKOUT1_USE_FINE_PS ("FALSE"), + .CLKOUT2_DIVIDE (MMCM_CLK2_DIV), + .CLKOUT2_PHASE (MMCM_CLK2_PHASE), + .CLKOUT2_DUTY_CYCLE (0.500), + .CLKOUT2_USE_FINE_PS ("FALSE"), + .CLKIN1_PERIOD (MMCM_CLKIN_PERIOD), + .CLKIN2_PERIOD (MMCM_CLKIN2_PERIOD), + .REF_JITTER1 (0.010)) + i_mmcm ( + .CLKIN1 (clk), + .CLKFBIN (bufg_fb_clk_s), + .CLKFBOUT (mmcm_fb_clk_s), + .CLKOUT0 (mmcm_clk_0_s), + .CLKOUT1 (mmcm_clk_1_s), + .CLKOUT2 (mmcm_clk_2_s), + .LOCKED (mmcm_locked_s), + .DCLK (up_clk), + .DEN (up_drp_sel), + .DADDR (up_drp_addr[6:0]), + .DWE (up_drp_wr), + .DI (up_drp_wdata), + .DO (up_drp_rdata_s), + .DRDY (up_drp_ready_s), + .CLKFBOUTB (), + .CLKOUT0B (), + .CLKOUT1B (), + .CLKOUT2B (), + .CLKOUT3 (), + .CLKOUT3B (), + .CLKOUT4 (), + .CLKOUT5 (), + .CLKOUT6 (), + .CLKIN2 (clk2), + .CLKINSEL (clk_sel), + .PSCLK (1'b0), + .PSEN (1'b0), + .PSINCDEC (1'b0), + .PSDONE (), + .CLKINSTOPPED (), + .CLKFBSTOPPED (), + .PWRDWN (1'b0), + .RST (mmcm_rst)); + + BUFG i_fb_clk_bufg (.I (mmcm_fb_clk_s), .O (bufg_fb_clk_s)); + BUFG i_clk_0_bufg (.I (mmcm_clk_0_s), .O (mmcm_clk_0)); + BUFG i_clk_1_bufg (.I (mmcm_clk_1_s), .O (mmcm_clk_1)); + BUFG i_clk_2_bufg (.I (mmcm_clk_2_s), .O (mmcm_clk_2)); + + end else begin /* MMCM_DEVICE_TYPE == 1 */ + + MMCM_ADV #( + .BANDWIDTH ("OPTIMIZED"), + .CLKOUT4_CASCADE ("FALSE"), + .CLOCK_HOLD ("FALSE"), + .COMPENSATION ("ZHOLD"), + .STARTUP_WAIT ("FALSE"), + .DIVCLK_DIVIDE (MMCM_VCO_DIV), + .CLKFBOUT_MULT_F (MMCM_VCO_MUL), + .CLKFBOUT_PHASE (0.000), + .CLKFBOUT_USE_FINE_PS ("FALSE"), + .CLKOUT0_DIVIDE_F (MMCM_CLK0_DIV), + .CLKOUT0_PHASE (MMCM_CLK0_PHASE), + .CLKOUT0_DUTY_CYCLE (0.500), + .CLKOUT0_USE_FINE_PS ("FALSE"), + .CLKOUT1_DIVIDE (MMCM_CLK1_DIV), + .CLKOUT1_PHASE (MMCM_CLK1_PHASE), + .CLKOUT1_DUTY_CYCLE (0.500), + .CLKOUT1_USE_FINE_PS ("FALSE"), + .CLKOUT2_DIVIDE (MMCM_CLK2_DIV), + .CLKOUT2_PHASE (MMCM_CLK2_PHASE), + .CLKOUT2_DUTY_CYCLE (0.500), + .CLKOUT2_USE_FINE_PS ("FALSE"), + .CLKIN1_PERIOD (MMCM_CLKIN_PERIOD), + .CLKIN2_PERIOD (MMCM_CLKIN2_PERIOD), + .REF_JITTER1 (0.010)) + i_mmcm ( + .CLKIN1 (clk), + .CLKFBIN (bufg_fb_clk_s), + .CLKFBOUT (mmcm_fb_clk_s), + .CLKOUT0 (mmcm_clk_0_s), + .CLKOUT1 (mmcm_clk_1_s), + .CLKOUT2 (mmcm_clk_2_s), + .LOCKED (mmcm_locked_s), + .DCLK (up_clk), + .DEN (up_drp_sel), + .DADDR (up_drp_addr[6:0]), + .DWE (up_drp_wr), + .DI (up_drp_wdata), + .DO (up_drp_rdata_s), + .DRDY (up_drp_ready_s), + .CLKFBOUTB (), + .CLKOUT0B (), + .CLKOUT1B (), + .CLKOUT2B (), + .CLKOUT3 (), + .CLKOUT3B (), + .CLKOUT4 (), + .CLKOUT5 (), + .CLKOUT6 (), + .CLKIN2 (clk2), + .CLKINSEL (clk_sel), + .PSCLK (1'b0), + .PSEN (1'b0), + .PSINCDEC (1'b0), + .PSDONE (), + .CLKINSTOPPED (), + .CLKFBSTOPPED (), + .PWRDWN (1'b0), + .RST (mmcm_rst)); + + BUFG i_fb_clk_bufg (.I (mmcm_fb_clk_s), .O (bufg_fb_clk_s)); + BUFG i_clk_0_bufg (.I (mmcm_clk_0_s), .O (mmcm_clk_0)); + BUFG i_clk_1_bufg (.I (mmcm_clk_1_s), .O (mmcm_clk_1)); + BUFG i_clk_2_bufg (.I (mmcm_clk_2_s), .O (mmcm_clk_2)); + end endgenerate - BUFG i_fb_clk_bufg (.I (mmcm_fb_clk_s), .O (bufg_fb_clk_s)); - BUFG i_clk_0_bufg (.I (mmcm_clk_0_s), .O (mmcm_clk_0)); - BUFG i_clk_1_bufg (.I (mmcm_clk_1_s), .O (mmcm_clk_1)); endmodule diff --git a/library/common/ad_mul.v b/library/xilinx/common/ad_mul.v similarity index 100% rename from library/common/ad_mul.v rename to library/xilinx/common/ad_mul.v diff --git a/library/common/ad_serdes_clk.v b/library/xilinx/common/ad_serdes_clk.v similarity index 53% rename from library/common/ad_serdes_clk.v rename to library/xilinx/common/ad_serdes_clk.v index 6adb1811f..b0aa9e2e4 100644 --- a/library/common/ad_serdes_clk.v +++ b/library/xilinx/common/ad_serdes_clk.v @@ -1,9 +1,9 @@ // *************************************************************************** // *************************************************************************** // Copyright 2011(c) Analog Devices, Inc. -// +// // All rights reserved. -// +// // Redistribution and use in source and binary forms, with or without modification, // are permitted provided that the following conditions are met: // - Redistributions of source code must retain the above copyright @@ -21,82 +21,68 @@ // patent holders to use this software. // - Use of the software either in source or binary form, must be run // on or directly connected to an Analog Devices Inc. component. -// +// // THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, // INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A // PARTICULAR PURPOSE ARE DISCLAIMED. // // IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, // EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY -// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR // BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // *************************************************************************** // *************************************************************************** -// serial data output interface: serdes(x8) or oddr(x2) output module +// serial data output interface: serdes(x8) `timescale 1ps/1ps -module ad_serdes_clk ( +module ad_serdes_clk #( + + parameter DEVICE_TYPE = 0, + parameter DDR_OR_SDR_N = 1, + parameter SERDES_FACTOR = 8, + parameter MMCM_OR_BUFR_N = 1, + parameter MMCM_CLKIN_PERIOD = 1.667, + parameter MMCM_VCO_DIV = 6, + parameter MMCM_VCO_MUL = 12.000, + parameter MMCM_CLK0_DIV = 2.000, + parameter MMCM_CLK1_DIV = 6) ( // clock and divided clock - mmcm_rst, - clk_in_p, - clk_in_n, - - clk, - div_clk, + input rst, + input clk_in_p, + input clk_in_n, + output clk, + output div_clk, + output out_clk, + output loaden, + output [ 7:0] phase, // drp interface - up_clk, - up_rstn, - up_drp_sel, - up_drp_wr, - up_drp_addr, - up_drp_wdata, - up_drp_rdata, - up_drp_ready, - up_drp_locked); - - // parameters - - parameter SERDES_OR_DDR_N = 1; - parameter MMCM_OR_BUFR_N = 1; - parameter MMCM_DEVICE_TYPE = 0; - parameter MMCM_CLKIN_PERIOD = 1.667; - parameter MMCM_VCO_DIV = 6; - parameter MMCM_VCO_MUL = 12.000; - parameter MMCM_CLK0_DIV = 2.000; - parameter MMCM_CLK1_DIV = 6; - - // clock and divided clock - - input mmcm_rst; - input clk_in_p; - input clk_in_n; - - output clk; - output div_clk; - - // drp interface - - input up_clk; - input up_rstn; - input up_drp_sel; - input up_drp_wr; - input [11:0] up_drp_addr; - input [15:0] up_drp_wdata; - output [15:0] up_drp_rdata; - output up_drp_ready; - output up_drp_locked; + input up_clk, + input up_rstn, + input up_drp_sel, + input up_drp_wr, + input [11:0] up_drp_addr, + input [31:0] up_drp_wdata, + output [31:0] up_drp_rdata, + output up_drp_ready, + output up_drp_locked); // internal signals wire clk_in_s; + // defaults + + assign loaden = 'd0; + assign phase = 'd0; + assign up_drp_rdata[31:16] = 'd0; + // instantiations IBUFGDS i_clk_in_ibuf ( @@ -106,49 +92,53 @@ module ad_serdes_clk ( generate if (MMCM_OR_BUFR_N == 1) begin - ad_mmcm_drp #( - .MMCM_DEVICE_TYPE (MMCM_DEVICE_TYPE), - .MMCM_CLKIN_PERIOD (MMCM_CLKIN_PERIOD), - .MMCM_VCO_DIV (MMCM_VCO_DIV), - .MMCM_VCO_MUL (MMCM_VCO_MUL), - .MMCM_CLK0_DIV (MMCM_CLK0_DIV), - .MMCM_CLK1_DIV (MMCM_CLK1_DIV)) - i_mmcm_drp ( - .clk (clk_in_s), - .mmcm_rst (mmcm_rst), - .mmcm_clk_0 (clk), - .mmcm_clk_1 (div_clk), - .up_clk (up_clk), - .up_rstn (up_rstn), - .up_drp_sel (up_drp_sel), - .up_drp_wr (up_drp_wr), - .up_drp_addr (up_drp_addr), - .up_drp_wdata (up_drp_wdata), - .up_drp_rdata (up_drp_rdata), - .up_drp_ready (up_drp_ready), - .up_drp_locked (up_drp_locked)); - end + ad_mmcm_drp #( + .MMCM_DEVICE_TYPE (DEVICE_TYPE), + .MMCM_CLKIN_PERIOD (MMCM_CLKIN_PERIOD), + .MMCM_CLKIN2_PERIOD (MMCM_CLKIN_PERIOD), + .MMCM_VCO_DIV (MMCM_VCO_DIV), + .MMCM_VCO_MUL (MMCM_VCO_MUL), + .MMCM_CLK0_DIV (MMCM_CLK0_DIV), + .MMCM_CLK0_PHASE (0.0), + .MMCM_CLK1_DIV (MMCM_CLK1_DIV), + .MMCM_CLK1_PHASE (0.0), + .MMCM_CLK2_DIV (MMCM_CLK0_DIV), + .MMCM_CLK2_PHASE (90.0)) + i_mmcm_drp ( + .clk (clk_in_s), + .clk2 (1'b0), + .clk_sel (1'b1), + .mmcm_rst (rst), + .mmcm_clk_0 (clk), + .mmcm_clk_1 (div_clk), + .mmcm_clk_2 (out_clk), + .up_clk (up_clk), + .up_rstn (up_rstn), + .up_drp_sel (up_drp_sel), + .up_drp_wr (up_drp_wr), + .up_drp_addr (up_drp_addr), + .up_drp_wdata (up_drp_wdata[15:0]), + .up_drp_rdata (up_drp_rdata[15:0]), + .up_drp_ready (up_drp_ready), + .up_drp_locked (up_drp_locked)); - if ((MMCM_OR_BUFR_N == 0) && (SERDES_OR_DDR_N == 0)) begin - BUFR #(.BUFR_DIVIDE("BYPASS")) i_clk_buf ( - .CLR (1'b0), - .CE (1'b1), - .I (clk_in_s), - .O (clk)); + end else if (MMCM_OR_BUFR_N == 0) begin - assign div_clk = clk; - end + BUFIO i_clk_buf ( + .I (clk_in_s), + .O (clk)); - if ((MMCM_OR_BUFR_N == 0) && (SERDES_OR_DDR_N == 1)) begin - BUFIO i_clk_buf ( - .I (clk_in_s), - .O (clk)); + BUFR #(.BUFR_DIVIDE("4")) i_div_clk_buf ( + .CLR (1'b0), + .CE (1'b1), + .I (clk_in_s), + .O (div_clk)); + + assign out_clk = clk; + assign up_drp_rdata[15:0] = 'd0; + assign up_drp_ready = 'd0; + assign up_drp_locked = 'd0; - BUFR #(.BUFR_DIVIDE("4")) i_div_clk_buf ( - .CLR (1'b0), - .CE (1'b1), - .I (clk_in_s), - .O (div_clk)); end endgenerate diff --git a/library/xilinx/common/ad_serdes_in.v b/library/xilinx/common/ad_serdes_in.v new file mode 100644 index 000000000..dccc0d5e6 --- /dev/null +++ b/library/xilinx/common/ad_serdes_in.v @@ -0,0 +1,325 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR +// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR +// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE +// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +`timescale 1ps/1ps + +module ad_serdes_in #( + + parameter DEVICE_TYPE = 0, + parameter DDR_OR_SDR_N = 0, + parameter SERDES_FACTOR = 8, + parameter DATA_WIDTH = 16, + parameter IODELAY_CTRL = 0, + parameter IODELAY_GROUP = "dev_if_delay_group") ( + + // reset and clocks + + input rst, + input clk, + input div_clk, + input loaden, + input [ 7:0] phase, + input locked, + + // data interface + + output [(DATA_WIDTH-1):0] data_s0, + output [(DATA_WIDTH-1):0] data_s1, + output [(DATA_WIDTH-1):0] data_s2, + output [(DATA_WIDTH-1):0] data_s3, + output [(DATA_WIDTH-1):0] data_s4, + output [(DATA_WIDTH-1):0] data_s5, + output [(DATA_WIDTH-1):0] data_s6, + output [(DATA_WIDTH-1):0] data_s7, + input [(DATA_WIDTH-1):0] data_in_p, + input [(DATA_WIDTH-1):0] data_in_n, + + // delay-data interface + + input up_clk, + input [(DATA_WIDTH-1):0] up_dld, + input [((DATA_WIDTH*5)-1):0] up_dwdata, + output [((DATA_WIDTH*5)-1):0] up_drdata, + + // delay-control interface + + input delay_clk, + input delay_rst, + output delay_locked); + + localparam DEVICE_6SERIES = 1; + localparam DEVICE_7SERIES = 0; + localparam DATA_RATE = (DDR_OR_SDR_N) ? "DDR" : "SDR"; + + // internal signals + + wire [(DATA_WIDTH-1):0] data_in_ibuf_s; + wire [(DATA_WIDTH-1):0] data_in_idelay_s; + wire [(DATA_WIDTH-1):0] data_shift1_s; + wire [(DATA_WIDTH-1):0] data_shift2_s; + + // delay controller + + generate + if (IODELAY_CTRL == 1) begin + (* IODELAY_GROUP = IODELAY_GROUP *) + IDELAYCTRL i_delay_ctrl ( + .RST (delay_rst), + .REFCLK (delay_clk), + .RDY (delay_locked)); + end else begin + assign delay_locked = 1'b1; + end + endgenerate + + // received data interface: ibuf -> idelay -> iserdes + + genvar l_inst; + generate if (DEVICE_TYPE == 0) begin + for (l_inst = 0; l_inst <= (DATA_WIDTH-1); l_inst = l_inst + 1) begin: g_data + + IBUFDS i_ibuf ( + .I (data_in_p[l_inst]), + .IB (data_in_n[l_inst]), + .O (data_in_ibuf_s[l_inst])); + + (* IODELAY_GROUP = IODELAY_GROUP *) + IDELAYE2 #( + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("IDATAIN"), + .HIGH_PERFORMANCE_MODE ("FALSE"), + .IDELAY_TYPE ("VAR_LOAD"), + .IDELAY_VALUE (0), + .REFCLK_FREQUENCY (200.0), + .PIPE_SEL ("FALSE"), + .SIGNAL_PATTERN ("DATA")) + i_idelay ( + .CE (1'b0), + .INC (1'b0), + .DATAIN (1'b0), + .LDPIPEEN (1'b0), + .CINVCTRL (1'b0), + .REGRST (1'b0), + .C (up_clk), + .IDATAIN (data_in_ibuf_s[l_inst]), + .DATAOUT (data_in_idelay_s[l_inst]), + .LD (up_dld[l_inst]), + .CNTVALUEIN (up_dwdata[((5*l_inst)+4):(5*l_inst)]), + .CNTVALUEOUT (up_drdata[((5*l_inst)+4):(5*l_inst)])); + + ISERDESE2 #( + .DATA_RATE (DATA_RATE), + .DATA_WIDTH (SERDES_FACTOR), + .DYN_CLKDIV_INV_EN ("FALSE"), + .DYN_CLK_INV_EN ("FALSE"), + .INIT_Q1 (1'b0), + .INIT_Q2 (1'b0), + .INIT_Q3 (1'b0), + .INIT_Q4 (1'b0), + .INTERFACE_TYPE ("NETWORKING"), + .IOBDELAY ("IFD"), + .NUM_CE (2), + .OFB_USED ("FALSE"), + .SERDES_MODE ("MASTER"), + .SRVAL_Q1 (1'b0), + .SRVAL_Q2 (1'b0), + .SRVAL_Q3 (1'b0), + .SRVAL_Q4 (1'b0)) + i_iserdes ( + .O (), + .Q1 (data_s0[l_inst]), + .Q2 (data_s1[l_inst]), + .Q3 (data_s2[l_inst]), + .Q4 (data_s3[l_inst]), + .Q5 (data_s4[l_inst]), + .Q6 (data_s5[l_inst]), + .Q7 (data_s6[l_inst]), + .Q8 (data_s7[l_inst]), + .SHIFTOUT1 (), + .SHIFTOUT2 (), + .BITSLIP (1'b0), + .CE1 (1'b1), + .CE2 (1'b1), + .CLKDIVP (1'b0), + .CLK (clk), + .CLKB (~clk), + .CLKDIV (div_clk), + .OCLK (1'b0), + .DYNCLKDIVSEL (1'b0), + .DYNCLKSEL (1'b0), + .D (1'b0), + .DDLY (data_in_idelay_s[l_inst]), + .OFB (1'b0), + .OCLKB (1'b0), + .RST (rst), + .SHIFTIN1 (1'b0), + .SHIFTIN2 (1'b0)); + end /* g_data */ + + end else begin + + for (l_inst = 0; l_inst <= (DATA_WIDTH-1); l_inst = l_inst + 1) begin: g_data + + IBUFDS i_ibuf ( + .I (data_in_p[l_inst]), + .IB (data_in_n[l_inst]), + .O (data_in_ibuf_s[l_inst])); + + (* IODELAY_GROUP = IODELAY_GROUP *) + IODELAYE1 #( + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("I"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .IDELAY_TYPE ("VAR_LOADABLE"), + .IDELAY_VALUE (0), + .ODELAY_TYPE ("FIXED"), + .ODELAY_VALUE (0), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA")) + i_idelay ( + .T (1'b1), + .CE (1'b0), + .INC (1'b0), + .CLKIN (1'b0), + .DATAIN (1'b0), + .ODATAIN (1'b0), + .CINVCTRL (1'b0), + .C (up_clk), + .IDATAIN (data_in_ibuf_s[l_inst]), + .DATAOUT (data_in_idelay_s[l_inst]), + .RST (up_dld[l_inst]), + .CNTVALUEIN (up_dwdata[((5*l_inst)+4):(5*l_inst)]), + .CNTVALUEOUT (up_drdata[((5*l_inst)+4):(5*l_inst)])); + + ISERDESE1 #( + .DATA_RATE (DATA_RATE), + .DATA_WIDTH (SERDES_FACTOR), + .DYN_CLKDIV_INV_EN ("FALSE"), + .DYN_CLK_INV_EN ("FALSE"), + .INIT_Q1 (1'b0), + .INIT_Q2 (1'b0), + .INIT_Q3 (1'b0), + .INIT_Q4 (1'b0), + .INTERFACE_TYPE ("NETWORKING"), + .IOBDELAY ("NONE"), + .NUM_CE (1), + .OFB_USED ("FALSE"), + .SERDES_MODE ("MASTER"), + .SRVAL_Q1 (1'b0), + .SRVAL_Q2 (1'b0), + .SRVAL_Q3 (1'b0), + .SRVAL_Q4 (1'b0)) + i_iserdes_m ( + .O (), + .Q1 (data_s0[l_inst]), + .Q2 (data_s1[l_inst]), + .Q3 (data_s2[l_inst]), + .Q4 (data_s3[l_inst]), + .Q5 (data_s4[l_inst]), + .Q6 (data_s5[l_inst]), + .SHIFTOUT1 (data_shift1_s[l_inst]), + .SHIFTOUT2 (data_shift2_s[l_inst]), + .BITSLIP (1'b0), + .CE1 (1'b1), + .CE2 (1'b1), + .CLK (clk), + .CLKB (~clk), + .CLKDIV (div_clk), + .OCLK (1'b0), + .DYNCLKDIVSEL (1'b0), + .DYNCLKSEL (1'b0), + .D (1'b0), + .DDLY (data_in_idelay_s[l_inst]), + .OFB (1'b0), + .RST (rst), + .SHIFTIN1 (1'b0), + .SHIFTIN2 (1'b0)); + + ISERDESE1 #( + .DATA_RATE (DATA_RATE), + .DATA_WIDTH (SERDES_FACTOR), + .DYN_CLKDIV_INV_EN ("FALSE"), + .DYN_CLK_INV_EN ("FALSE"), + .INIT_Q1 (1'b0), + .INIT_Q2 (1'b0), + .INIT_Q3 (1'b0), + .INIT_Q4 (1'b0), + .INTERFACE_TYPE ("NETWORKING"), + .IOBDELAY ("NONE"), + .NUM_CE (1), + .OFB_USED ("FALSE"), + .SERDES_MODE ("SLAVE"), + .SRVAL_Q1 (1'b0), + .SRVAL_Q2 (1'b0), + .SRVAL_Q3 (1'b0), + .SRVAL_Q4 (1'b0)) + i_iserdes_s ( + .O (), + .Q1 (), + .Q2 (), + .Q3 (data_s6[l_inst]), + .Q4 (data_s7[l_inst]), + .Q5 (), + .Q6 (), + .SHIFTOUT1 (), + .SHIFTOUT2 (), + .BITSLIP (1'b0), + .CE1 (1'b1), + .CE2 (1'b1), + .CLK (clk), + .CLKB (~clk), + .CLKDIV (div_clk), + .OCLK (1'b0), + .DYNCLKDIVSEL (1'b0), + .DYNCLKSEL (1'b0), + .D (1'b0), + .DDLY (data_in_idelay_s[l_inst]), + .OFB (1'b0), + .RST (rst), + .SHIFTIN1 (data_shift1_s[l_inst]), + .SHIFTIN2 (data_shift2_s[l_inst])); + + end /* g_data */ + end + endgenerate + + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/library/xilinx/common/ad_serdes_out.v b/library/xilinx/common/ad_serdes_out.v new file mode 100644 index 000000000..22b801b9e --- /dev/null +++ b/library/xilinx/common/ad_serdes_out.v @@ -0,0 +1,208 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// serial data output interface: serdes(x8) + +`timescale 1ps/1ps + +module ad_serdes_out #( + + parameter DEVICE_TYPE = 0, + parameter DDR_OR_SDR_N = 1, + parameter SERDES_FACTOR = 8, + parameter DATA_WIDTH = 16) ( + + // reset and clocks + + input rst, + input clk, + input div_clk, + input loaden, + + // data interface + + input [(DATA_WIDTH-1):0] data_s0, + input [(DATA_WIDTH-1):0] data_s1, + input [(DATA_WIDTH-1):0] data_s2, + input [(DATA_WIDTH-1):0] data_s3, + input [(DATA_WIDTH-1):0] data_s4, + input [(DATA_WIDTH-1):0] data_s5, + input [(DATA_WIDTH-1):0] data_s6, + input [(DATA_WIDTH-1):0] data_s7, + output [(DATA_WIDTH-1):0] data_out_p, + output [(DATA_WIDTH-1):0] data_out_n); + + localparam DEVICE_6SERIES = 1; + localparam DEVICE_7SERIES = 0; + + // internal signals + + wire [(DATA_WIDTH-1):0] data_out_s; + wire [(DATA_WIDTH-1):0] serdes_shift1_s; + wire [(DATA_WIDTH-1):0] serdes_shift2_s; + + // instantiations + + genvar l_inst; + generate + for (l_inst = 0; l_inst <= (DATA_WIDTH-1); l_inst = l_inst + 1) begin: g_data + + if (DEVICE_TYPE == DEVICE_7SERIES) begin + OSERDESE2 #( + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("SDR"), + .DATA_WIDTH (SERDES_FACTOR), + .TRISTATE_WIDTH (1), + .SERDES_MODE ("MASTER")) + i_serdes ( + .D1 (data_s0[l_inst]), + .D2 (data_s1[l_inst]), + .D3 (data_s2[l_inst]), + .D4 (data_s3[l_inst]), + .D5 (data_s4[l_inst]), + .D6 (data_s5[l_inst]), + .D7 (data_s6[l_inst]), + .D8 (data_s7[l_inst]), + .T1 (1'b0), + .T2 (1'b0), + .T3 (1'b0), + .T4 (1'b0), + .SHIFTIN1 (1'b0), + .SHIFTIN2 (1'b0), + .SHIFTOUT1 (), + .SHIFTOUT2 (), + .OCE (1'b1), + .CLK (clk), + .CLKDIV (div_clk), + .OQ (data_out_s[l_inst]), + .TQ (), + .OFB (), + .TFB (), + .TBYTEIN (1'b0), + .TBYTEOUT (), + .TCE (1'b0), + .RST (rst)); + end + + if (DEVICE_TYPE == DEVICE_6SERIES) begin + OSERDESE1 #( + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("SDR"), + .DATA_WIDTH (SERDES_FACTOR), + .INTERFACE_TYPE ("DEFAULT"), + .TRISTATE_WIDTH (1), + .SERDES_MODE ("MASTER")) + i_serdes_m ( + .D1 (data_s0[l_inst]), + .D2 (data_s1[l_inst]), + .D3 (data_s2[l_inst]), + .D4 (data_s3[l_inst]), + .D5 (data_s4[l_inst]), + .D6 (data_s5[l_inst]), + .T1 (1'b0), + .T2 (1'b0), + .T3 (1'b0), + .T4 (1'b0), + .SHIFTIN1 (serdes_shift1_s[l_inst]), + .SHIFTIN2 (serdes_shift2_s[l_inst]), + .SHIFTOUT1 (), + .SHIFTOUT2 (), + .OCE (1'b1), + .CLK (clk), + .CLKDIV (div_clk), + .CLKPERF (1'b0), + .CLKPERFDELAY (1'b0), + .WC (1'b0), + .ODV (1'b0), + .OQ (data_out_s[l_inst]), + .TQ (), + .OCBEXTEND (), + .OFB (), + .TFB (), + .TCE (1'b0), + .RST (rst)); + + OSERDESE1 #( + .DATA_RATE_OQ ("DDR"), + .DATA_RATE_TQ ("SDR"), + .DATA_WIDTH (SERDES_FACTOR), + .INTERFACE_TYPE ("DEFAULT"), + .TRISTATE_WIDTH (1), + .SERDES_MODE ("SLAVE")) + i_serdes_s ( + .D1 (1'b0), + .D2 (1'b0), + .D3 (data_s6[l_inst]), + .D4 (data_s7[l_inst]), + .D5 (1'b0), + .D6 (1'b0), + .T1 (1'b0), + .T2 (1'b0), + .T3 (1'b0), + .T4 (1'b0), + .SHIFTIN1 (1'b0), + .SHIFTIN2 (1'b0), + .SHIFTOUT1 (serdes_shift1_s[l_inst]), + .SHIFTOUT2 (serdes_shift2_s[l_inst]), + .OCE (1'b1), + .CLK (clk), + .CLKDIV (div_clk), + .CLKPERF (1'b0), + .CLKPERFDELAY (1'b0), + .WC (1'b0), + .ODV (1'b0), + .OQ (), + .TQ (), + .OCBEXTEND (), + .OFB (), + .TFB (), + .TCE (1'b0), + .RST (rst)); + end + + OBUFDS i_obuf ( + .I (data_out_s[l_inst]), + .O (data_out_p[l_inst]), + .OB (data_out_n[l_inst])); + + end + endgenerate + +endmodule + +// *************************************************************************** +// *************************************************************************** + diff --git a/library/util_jesd_gt/Makefile b/library/xilinx/util_adxcvr/Makefile similarity index 58% rename from library/util_jesd_gt/Makefile rename to library/xilinx/util_adxcvr/Makefile index c78666c37..7df5f8cd8 100644 --- a/library/util_jesd_gt/Makefile +++ b/library/xilinx/util_adxcvr/Makefile @@ -5,18 +5,18 @@ #################################################################################### #################################################################################### -M_DEPS := util_jesd_gt_ip.tcl -M_DEPS += ../scripts/adi_env.tcl -M_DEPS += ../scripts/adi_ip.tcl -M_DEPS += util_jesd_gt.v -M_DEPS += ../interfaces/if_gt_qpll.xml -M_DEPS += ../interfaces/if_gt_qpll_rtl.xml -M_DEPS += ../interfaces/if_gt_pll.xml -M_DEPS += ../interfaces/if_gt_pll_rtl.xml -M_DEPS += ../interfaces/if_gt_rx.xml -M_DEPS += ../interfaces/if_gt_rx_rtl.xml -M_DEPS += ../interfaces/if_gt_tx.xml -M_DEPS += ../interfaces/if_gt_tx_rtl.xml +M_DEPS += ../../scripts/adi_env.tcl +M_DEPS += ../../scripts/adi_ip.tcl +M_DEPS += util_adxcvr.v +M_DEPS += util_adxcvr_constr.xdc +M_DEPS += util_adxcvr_ip.tcl +M_DEPS += util_adxcvr_xch.v +M_DEPS += util_adxcvr_xcm.v + +M_DEPS += ../../interfaces/if_xcvr_ch.xml +M_DEPS += ../../interfaces/if_xcvr_ch_rtl.xml +M_DEPS += ../../interfaces/if_xcvr_cm.xml +M_DEPS += ../../interfaces/if_xcvr_cm_rtl.xml M_VIVADO := vivado -mode batch -source @@ -27,12 +27,16 @@ M_FLIST += *.log M_FLIST += component.xml M_FLIST += *.jou M_FLIST += xgui +M_FLIST += *.ip_user_files +M_FLIST += *.srcs +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil .PHONY: all dep clean clean-all -all: dep util_jesd_gt.xpr +all: dep util_adxcvr.xpr clean:clean-all @@ -42,11 +46,11 @@ clean-all: rm -rf $(M_FLIST) -util_jesd_gt.xpr: $(M_DEPS) - rm -rf $(M_FLIST) - $(M_VIVADO) util_jesd_gt_ip.tcl >> util_jesd_gt_ip.log 2>&1 +util_adxcvr.xpr: $(M_DEPS) + -rm -rf $(M_FLIST) + $(M_VIVADO) util_adxcvr_ip.tcl >> util_adxcvr_ip.log 2>&1 dep: - make -C ../interfaces + make -C ../../interfaces #################################################################################### #################################################################################### diff --git a/library/xilinx/util_adxcvr/util_adxcvr.v b/library/xilinx/util_adxcvr/util_adxcvr.v new file mode 100644 index 000000000..043cde0a5 --- /dev/null +++ b/library/xilinx/util_adxcvr/util_adxcvr.v @@ -0,0 +1,2747 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// AUTO GENERATED BY util_adxcvr.pl, DO NOT MODIFY! + +`timescale 1ns/1ps + +module util_adxcvr #( + + // gtxe2(0), gthe3(1), gthe4(2) + + parameter integer XCVR_TYPE = 0, + + // qpll-configuration + + parameter integer QPLL_REFCLK_DIV = 1, + parameter integer QPLL_FBDIV_RATIO = 1, + parameter [26:0] QPLL_CFG = 27'h0680181, + parameter [ 9:0] QPLL_FBDIV = 10'b0000110000, + + // cpll-configuration + + parameter integer CPLL_FBDIV = 2, + parameter integer CPLL_FBDIV_4_5 = 5, + + // tx-configuration + + parameter integer TX_NUM_OF_LANES = 8, + parameter integer TX_OUT_DIV = 1, + parameter integer TX_CLK25_DIV = 20, + + // rx-configuration + + parameter integer RX_NUM_OF_LANES = 8, + parameter integer RX_OUT_DIV = 1, + parameter integer RX_CLK25_DIV = 20, + parameter [15:0] RX_DFE_LPM_CFG = 16'h0104, + parameter [31:0] RX_PMA_CFG = 32'h001e7080, + parameter [72:0] RX_CDR_CFG = 72'h0b000023ff10400020) ( + + input up_rstn, + input up_clk, + + input qpll_ref_clk_0, + input up_qpll_rst_0, + input cpll_ref_clk_0, + input up_cpll_rst_0, + + input rx_0_p, + input rx_0_n, + output rx_out_clk_0, + input rx_clk_0, + output [ 3:0] rx_charisk_0, + output [ 3:0] rx_disperr_0, + output [ 3:0] rx_notintable_0, + output [31:0] rx_data_0, + input rx_calign_0, + + output tx_0_p, + output tx_0_n, + output tx_out_clk_0, + input tx_clk_0, + input [ 3:0] tx_charisk_0, + input [31:0] tx_data_0, + + input [ 7:0] up_cm_sel_0, + input up_cm_enb_0, + input [11:0] up_cm_addr_0, + input up_cm_wr_0, + input [15:0] up_cm_wdata_0, + output [15:0] up_cm_rdata_0, + output up_cm_ready_0, + input [ 7:0] up_es_sel_0, + input up_es_enb_0, + input [11:0] up_es_addr_0, + input up_es_wr_0, + input [15:0] up_es_wdata_0, + output [15:0] up_es_rdata_0, + output up_es_ready_0, + output up_rx_pll_locked_0, + input up_rx_rst_0, + input up_rx_user_ready_0, + output up_rx_rst_done_0, + input up_rx_lpm_dfe_n_0, + input [ 2:0] up_rx_rate_0, + input [ 1:0] up_rx_sys_clk_sel_0, + input [ 2:0] up_rx_out_clk_sel_0, + input [ 7:0] up_rx_sel_0, + input up_rx_enb_0, + input [11:0] up_rx_addr_0, + input up_rx_wr_0, + input [15:0] up_rx_wdata_0, + output [15:0] up_rx_rdata_0, + output up_rx_ready_0, + output up_tx_pll_locked_0, + input up_tx_rst_0, + input up_tx_user_ready_0, + output up_tx_rst_done_0, + input up_tx_lpm_dfe_n_0, + input [ 2:0] up_tx_rate_0, + input [ 1:0] up_tx_sys_clk_sel_0, + input [ 2:0] up_tx_out_clk_sel_0, + input [ 7:0] up_tx_sel_0, + input up_tx_enb_0, + input [11:0] up_tx_addr_0, + input up_tx_wr_0, + input [15:0] up_tx_wdata_0, + output [15:0] up_tx_rdata_0, + output up_tx_ready_0, + + input cpll_ref_clk_1, + input up_cpll_rst_1, + + input rx_1_p, + input rx_1_n, + output rx_out_clk_1, + input rx_clk_1, + output [ 3:0] rx_charisk_1, + output [ 3:0] rx_disperr_1, + output [ 3:0] rx_notintable_1, + output [31:0] rx_data_1, + input rx_calign_1, + + output tx_1_p, + output tx_1_n, + output tx_out_clk_1, + input tx_clk_1, + input [ 3:0] tx_charisk_1, + input [31:0] tx_data_1, + + input [ 7:0] up_es_sel_1, + input up_es_enb_1, + input [11:0] up_es_addr_1, + input up_es_wr_1, + input [15:0] up_es_wdata_1, + output [15:0] up_es_rdata_1, + output up_es_ready_1, + output up_rx_pll_locked_1, + input up_rx_rst_1, + input up_rx_user_ready_1, + output up_rx_rst_done_1, + input up_rx_lpm_dfe_n_1, + input [ 2:0] up_rx_rate_1, + input [ 1:0] up_rx_sys_clk_sel_1, + input [ 2:0] up_rx_out_clk_sel_1, + input [ 7:0] up_rx_sel_1, + input up_rx_enb_1, + input [11:0] up_rx_addr_1, + input up_rx_wr_1, + input [15:0] up_rx_wdata_1, + output [15:0] up_rx_rdata_1, + output up_rx_ready_1, + output up_tx_pll_locked_1, + input up_tx_rst_1, + input up_tx_user_ready_1, + output up_tx_rst_done_1, + input up_tx_lpm_dfe_n_1, + input [ 2:0] up_tx_rate_1, + input [ 1:0] up_tx_sys_clk_sel_1, + input [ 2:0] up_tx_out_clk_sel_1, + input [ 7:0] up_tx_sel_1, + input up_tx_enb_1, + input [11:0] up_tx_addr_1, + input up_tx_wr_1, + input [15:0] up_tx_wdata_1, + output [15:0] up_tx_rdata_1, + output up_tx_ready_1, + + input cpll_ref_clk_2, + input up_cpll_rst_2, + + input rx_2_p, + input rx_2_n, + output rx_out_clk_2, + input rx_clk_2, + output [ 3:0] rx_charisk_2, + output [ 3:0] rx_disperr_2, + output [ 3:0] rx_notintable_2, + output [31:0] rx_data_2, + input rx_calign_2, + + output tx_2_p, + output tx_2_n, + output tx_out_clk_2, + input tx_clk_2, + input [ 3:0] tx_charisk_2, + input [31:0] tx_data_2, + + input [ 7:0] up_es_sel_2, + input up_es_enb_2, + input [11:0] up_es_addr_2, + input up_es_wr_2, + input [15:0] up_es_wdata_2, + output [15:0] up_es_rdata_2, + output up_es_ready_2, + output up_rx_pll_locked_2, + input up_rx_rst_2, + input up_rx_user_ready_2, + output up_rx_rst_done_2, + input up_rx_lpm_dfe_n_2, + input [ 2:0] up_rx_rate_2, + input [ 1:0] up_rx_sys_clk_sel_2, + input [ 2:0] up_rx_out_clk_sel_2, + input [ 7:0] up_rx_sel_2, + input up_rx_enb_2, + input [11:0] up_rx_addr_2, + input up_rx_wr_2, + input [15:0] up_rx_wdata_2, + output [15:0] up_rx_rdata_2, + output up_rx_ready_2, + output up_tx_pll_locked_2, + input up_tx_rst_2, + input up_tx_user_ready_2, + output up_tx_rst_done_2, + input up_tx_lpm_dfe_n_2, + input [ 2:0] up_tx_rate_2, + input [ 1:0] up_tx_sys_clk_sel_2, + input [ 2:0] up_tx_out_clk_sel_2, + input [ 7:0] up_tx_sel_2, + input up_tx_enb_2, + input [11:0] up_tx_addr_2, + input up_tx_wr_2, + input [15:0] up_tx_wdata_2, + output [15:0] up_tx_rdata_2, + output up_tx_ready_2, + + input cpll_ref_clk_3, + input up_cpll_rst_3, + + input rx_3_p, + input rx_3_n, + output rx_out_clk_3, + input rx_clk_3, + output [ 3:0] rx_charisk_3, + output [ 3:0] rx_disperr_3, + output [ 3:0] rx_notintable_3, + output [31:0] rx_data_3, + input rx_calign_3, + + output tx_3_p, + output tx_3_n, + output tx_out_clk_3, + input tx_clk_3, + input [ 3:0] tx_charisk_3, + input [31:0] tx_data_3, + + input [ 7:0] up_es_sel_3, + input up_es_enb_3, + input [11:0] up_es_addr_3, + input up_es_wr_3, + input [15:0] up_es_wdata_3, + output [15:0] up_es_rdata_3, + output up_es_ready_3, + output up_rx_pll_locked_3, + input up_rx_rst_3, + input up_rx_user_ready_3, + output up_rx_rst_done_3, + input up_rx_lpm_dfe_n_3, + input [ 2:0] up_rx_rate_3, + input [ 1:0] up_rx_sys_clk_sel_3, + input [ 2:0] up_rx_out_clk_sel_3, + input [ 7:0] up_rx_sel_3, + input up_rx_enb_3, + input [11:0] up_rx_addr_3, + input up_rx_wr_3, + input [15:0] up_rx_wdata_3, + output [15:0] up_rx_rdata_3, + output up_rx_ready_3, + output up_tx_pll_locked_3, + input up_tx_rst_3, + input up_tx_user_ready_3, + output up_tx_rst_done_3, + input up_tx_lpm_dfe_n_3, + input [ 2:0] up_tx_rate_3, + input [ 1:0] up_tx_sys_clk_sel_3, + input [ 2:0] up_tx_out_clk_sel_3, + input [ 7:0] up_tx_sel_3, + input up_tx_enb_3, + input [11:0] up_tx_addr_3, + input up_tx_wr_3, + input [15:0] up_tx_wdata_3, + output [15:0] up_tx_rdata_3, + output up_tx_ready_3, + + input qpll_ref_clk_4, + input up_qpll_rst_4, + input cpll_ref_clk_4, + input up_cpll_rst_4, + + input rx_4_p, + input rx_4_n, + output rx_out_clk_4, + input rx_clk_4, + output [ 3:0] rx_charisk_4, + output [ 3:0] rx_disperr_4, + output [ 3:0] rx_notintable_4, + output [31:0] rx_data_4, + input rx_calign_4, + + output tx_4_p, + output tx_4_n, + output tx_out_clk_4, + input tx_clk_4, + input [ 3:0] tx_charisk_4, + input [31:0] tx_data_4, + + input [ 7:0] up_cm_sel_4, + input up_cm_enb_4, + input [11:0] up_cm_addr_4, + input up_cm_wr_4, + input [15:0] up_cm_wdata_4, + output [15:0] up_cm_rdata_4, + output up_cm_ready_4, + input [ 7:0] up_es_sel_4, + input up_es_enb_4, + input [11:0] up_es_addr_4, + input up_es_wr_4, + input [15:0] up_es_wdata_4, + output [15:0] up_es_rdata_4, + output up_es_ready_4, + output up_rx_pll_locked_4, + input up_rx_rst_4, + input up_rx_user_ready_4, + output up_rx_rst_done_4, + input up_rx_lpm_dfe_n_4, + input [ 2:0] up_rx_rate_4, + input [ 1:0] up_rx_sys_clk_sel_4, + input [ 2:0] up_rx_out_clk_sel_4, + input [ 7:0] up_rx_sel_4, + input up_rx_enb_4, + input [11:0] up_rx_addr_4, + input up_rx_wr_4, + input [15:0] up_rx_wdata_4, + output [15:0] up_rx_rdata_4, + output up_rx_ready_4, + output up_tx_pll_locked_4, + input up_tx_rst_4, + input up_tx_user_ready_4, + output up_tx_rst_done_4, + input up_tx_lpm_dfe_n_4, + input [ 2:0] up_tx_rate_4, + input [ 1:0] up_tx_sys_clk_sel_4, + input [ 2:0] up_tx_out_clk_sel_4, + input [ 7:0] up_tx_sel_4, + input up_tx_enb_4, + input [11:0] up_tx_addr_4, + input up_tx_wr_4, + input [15:0] up_tx_wdata_4, + output [15:0] up_tx_rdata_4, + output up_tx_ready_4, + + input cpll_ref_clk_5, + input up_cpll_rst_5, + + input rx_5_p, + input rx_5_n, + output rx_out_clk_5, + input rx_clk_5, + output [ 3:0] rx_charisk_5, + output [ 3:0] rx_disperr_5, + output [ 3:0] rx_notintable_5, + output [31:0] rx_data_5, + input rx_calign_5, + + output tx_5_p, + output tx_5_n, + output tx_out_clk_5, + input tx_clk_5, + input [ 3:0] tx_charisk_5, + input [31:0] tx_data_5, + + input [ 7:0] up_es_sel_5, + input up_es_enb_5, + input [11:0] up_es_addr_5, + input up_es_wr_5, + input [15:0] up_es_wdata_5, + output [15:0] up_es_rdata_5, + output up_es_ready_5, + output up_rx_pll_locked_5, + input up_rx_rst_5, + input up_rx_user_ready_5, + output up_rx_rst_done_5, + input up_rx_lpm_dfe_n_5, + input [ 2:0] up_rx_rate_5, + input [ 1:0] up_rx_sys_clk_sel_5, + input [ 2:0] up_rx_out_clk_sel_5, + input [ 7:0] up_rx_sel_5, + input up_rx_enb_5, + input [11:0] up_rx_addr_5, + input up_rx_wr_5, + input [15:0] up_rx_wdata_5, + output [15:0] up_rx_rdata_5, + output up_rx_ready_5, + output up_tx_pll_locked_5, + input up_tx_rst_5, + input up_tx_user_ready_5, + output up_tx_rst_done_5, + input up_tx_lpm_dfe_n_5, + input [ 2:0] up_tx_rate_5, + input [ 1:0] up_tx_sys_clk_sel_5, + input [ 2:0] up_tx_out_clk_sel_5, + input [ 7:0] up_tx_sel_5, + input up_tx_enb_5, + input [11:0] up_tx_addr_5, + input up_tx_wr_5, + input [15:0] up_tx_wdata_5, + output [15:0] up_tx_rdata_5, + output up_tx_ready_5, + + input cpll_ref_clk_6, + input up_cpll_rst_6, + + input rx_6_p, + input rx_6_n, + output rx_out_clk_6, + input rx_clk_6, + output [ 3:0] rx_charisk_6, + output [ 3:0] rx_disperr_6, + output [ 3:0] rx_notintable_6, + output [31:0] rx_data_6, + input rx_calign_6, + + output tx_6_p, + output tx_6_n, + output tx_out_clk_6, + input tx_clk_6, + input [ 3:0] tx_charisk_6, + input [31:0] tx_data_6, + + input [ 7:0] up_es_sel_6, + input up_es_enb_6, + input [11:0] up_es_addr_6, + input up_es_wr_6, + input [15:0] up_es_wdata_6, + output [15:0] up_es_rdata_6, + output up_es_ready_6, + output up_rx_pll_locked_6, + input up_rx_rst_6, + input up_rx_user_ready_6, + output up_rx_rst_done_6, + input up_rx_lpm_dfe_n_6, + input [ 2:0] up_rx_rate_6, + input [ 1:0] up_rx_sys_clk_sel_6, + input [ 2:0] up_rx_out_clk_sel_6, + input [ 7:0] up_rx_sel_6, + input up_rx_enb_6, + input [11:0] up_rx_addr_6, + input up_rx_wr_6, + input [15:0] up_rx_wdata_6, + output [15:0] up_rx_rdata_6, + output up_rx_ready_6, + output up_tx_pll_locked_6, + input up_tx_rst_6, + input up_tx_user_ready_6, + output up_tx_rst_done_6, + input up_tx_lpm_dfe_n_6, + input [ 2:0] up_tx_rate_6, + input [ 1:0] up_tx_sys_clk_sel_6, + input [ 2:0] up_tx_out_clk_sel_6, + input [ 7:0] up_tx_sel_6, + input up_tx_enb_6, + input [11:0] up_tx_addr_6, + input up_tx_wr_6, + input [15:0] up_tx_wdata_6, + output [15:0] up_tx_rdata_6, + output up_tx_ready_6, + + input cpll_ref_clk_7, + input up_cpll_rst_7, + + input rx_7_p, + input rx_7_n, + output rx_out_clk_7, + input rx_clk_7, + output [ 3:0] rx_charisk_7, + output [ 3:0] rx_disperr_7, + output [ 3:0] rx_notintable_7, + output [31:0] rx_data_7, + input rx_calign_7, + + output tx_7_p, + output tx_7_n, + output tx_out_clk_7, + input tx_clk_7, + input [ 3:0] tx_charisk_7, + input [31:0] tx_data_7, + + input [ 7:0] up_es_sel_7, + input up_es_enb_7, + input [11:0] up_es_addr_7, + input up_es_wr_7, + input [15:0] up_es_wdata_7, + output [15:0] up_es_rdata_7, + output up_es_ready_7, + output up_rx_pll_locked_7, + input up_rx_rst_7, + input up_rx_user_ready_7, + output up_rx_rst_done_7, + input up_rx_lpm_dfe_n_7, + input [ 2:0] up_rx_rate_7, + input [ 1:0] up_rx_sys_clk_sel_7, + input [ 2:0] up_rx_out_clk_sel_7, + input [ 7:0] up_rx_sel_7, + input up_rx_enb_7, + input [11:0] up_rx_addr_7, + input up_rx_wr_7, + input [15:0] up_rx_wdata_7, + output [15:0] up_rx_rdata_7, + output up_rx_ready_7, + output up_tx_pll_locked_7, + input up_tx_rst_7, + input up_tx_user_ready_7, + output up_tx_rst_done_7, + input up_tx_lpm_dfe_n_7, + input [ 2:0] up_tx_rate_7, + input [ 1:0] up_tx_sys_clk_sel_7, + input [ 2:0] up_tx_out_clk_sel_7, + input [ 7:0] up_tx_sel_7, + input up_tx_enb_7, + input [11:0] up_tx_addr_7, + input up_tx_wr_7, + input [15:0] up_tx_wdata_7, + output [15:0] up_tx_rdata_7, + output up_tx_ready_7, + + input qpll_ref_clk_8, + input up_qpll_rst_8, + input cpll_ref_clk_8, + input up_cpll_rst_8, + + input rx_8_p, + input rx_8_n, + output rx_out_clk_8, + input rx_clk_8, + output [ 3:0] rx_charisk_8, + output [ 3:0] rx_disperr_8, + output [ 3:0] rx_notintable_8, + output [31:0] rx_data_8, + input rx_calign_8, + + output tx_8_p, + output tx_8_n, + output tx_out_clk_8, + input tx_clk_8, + input [ 3:0] tx_charisk_8, + input [31:0] tx_data_8, + + input [ 7:0] up_cm_sel_8, + input up_cm_enb_8, + input [11:0] up_cm_addr_8, + input up_cm_wr_8, + input [15:0] up_cm_wdata_8, + output [15:0] up_cm_rdata_8, + output up_cm_ready_8, + input [ 7:0] up_es_sel_8, + input up_es_enb_8, + input [11:0] up_es_addr_8, + input up_es_wr_8, + input [15:0] up_es_wdata_8, + output [15:0] up_es_rdata_8, + output up_es_ready_8, + output up_rx_pll_locked_8, + input up_rx_rst_8, + input up_rx_user_ready_8, + output up_rx_rst_done_8, + input up_rx_lpm_dfe_n_8, + input [ 2:0] up_rx_rate_8, + input [ 1:0] up_rx_sys_clk_sel_8, + input [ 2:0] up_rx_out_clk_sel_8, + input [ 7:0] up_rx_sel_8, + input up_rx_enb_8, + input [11:0] up_rx_addr_8, + input up_rx_wr_8, + input [15:0] up_rx_wdata_8, + output [15:0] up_rx_rdata_8, + output up_rx_ready_8, + output up_tx_pll_locked_8, + input up_tx_rst_8, + input up_tx_user_ready_8, + output up_tx_rst_done_8, + input up_tx_lpm_dfe_n_8, + input [ 2:0] up_tx_rate_8, + input [ 1:0] up_tx_sys_clk_sel_8, + input [ 2:0] up_tx_out_clk_sel_8, + input [ 7:0] up_tx_sel_8, + input up_tx_enb_8, + input [11:0] up_tx_addr_8, + input up_tx_wr_8, + input [15:0] up_tx_wdata_8, + output [15:0] up_tx_rdata_8, + output up_tx_ready_8, + + input cpll_ref_clk_9, + input up_cpll_rst_9, + + input rx_9_p, + input rx_9_n, + output rx_out_clk_9, + input rx_clk_9, + output [ 3:0] rx_charisk_9, + output [ 3:0] rx_disperr_9, + output [ 3:0] rx_notintable_9, + output [31:0] rx_data_9, + input rx_calign_9, + + output tx_9_p, + output tx_9_n, + output tx_out_clk_9, + input tx_clk_9, + input [ 3:0] tx_charisk_9, + input [31:0] tx_data_9, + + input [ 7:0] up_es_sel_9, + input up_es_enb_9, + input [11:0] up_es_addr_9, + input up_es_wr_9, + input [15:0] up_es_wdata_9, + output [15:0] up_es_rdata_9, + output up_es_ready_9, + output up_rx_pll_locked_9, + input up_rx_rst_9, + input up_rx_user_ready_9, + output up_rx_rst_done_9, + input up_rx_lpm_dfe_n_9, + input [ 2:0] up_rx_rate_9, + input [ 1:0] up_rx_sys_clk_sel_9, + input [ 2:0] up_rx_out_clk_sel_9, + input [ 7:0] up_rx_sel_9, + input up_rx_enb_9, + input [11:0] up_rx_addr_9, + input up_rx_wr_9, + input [15:0] up_rx_wdata_9, + output [15:0] up_rx_rdata_9, + output up_rx_ready_9, + output up_tx_pll_locked_9, + input up_tx_rst_9, + input up_tx_user_ready_9, + output up_tx_rst_done_9, + input up_tx_lpm_dfe_n_9, + input [ 2:0] up_tx_rate_9, + input [ 1:0] up_tx_sys_clk_sel_9, + input [ 2:0] up_tx_out_clk_sel_9, + input [ 7:0] up_tx_sel_9, + input up_tx_enb_9, + input [11:0] up_tx_addr_9, + input up_tx_wr_9, + input [15:0] up_tx_wdata_9, + output [15:0] up_tx_rdata_9, + output up_tx_ready_9, + + input cpll_ref_clk_10, + input up_cpll_rst_10, + + input rx_10_p, + input rx_10_n, + output rx_out_clk_10, + input rx_clk_10, + output [ 3:0] rx_charisk_10, + output [ 3:0] rx_disperr_10, + output [ 3:0] rx_notintable_10, + output [31:0] rx_data_10, + input rx_calign_10, + + output tx_10_p, + output tx_10_n, + output tx_out_clk_10, + input tx_clk_10, + input [ 3:0] tx_charisk_10, + input [31:0] tx_data_10, + + input [ 7:0] up_es_sel_10, + input up_es_enb_10, + input [11:0] up_es_addr_10, + input up_es_wr_10, + input [15:0] up_es_wdata_10, + output [15:0] up_es_rdata_10, + output up_es_ready_10, + output up_rx_pll_locked_10, + input up_rx_rst_10, + input up_rx_user_ready_10, + output up_rx_rst_done_10, + input up_rx_lpm_dfe_n_10, + input [ 2:0] up_rx_rate_10, + input [ 1:0] up_rx_sys_clk_sel_10, + input [ 2:0] up_rx_out_clk_sel_10, + input [ 7:0] up_rx_sel_10, + input up_rx_enb_10, + input [11:0] up_rx_addr_10, + input up_rx_wr_10, + input [15:0] up_rx_wdata_10, + output [15:0] up_rx_rdata_10, + output up_rx_ready_10, + output up_tx_pll_locked_10, + input up_tx_rst_10, + input up_tx_user_ready_10, + output up_tx_rst_done_10, + input up_tx_lpm_dfe_n_10, + input [ 2:0] up_tx_rate_10, + input [ 1:0] up_tx_sys_clk_sel_10, + input [ 2:0] up_tx_out_clk_sel_10, + input [ 7:0] up_tx_sel_10, + input up_tx_enb_10, + input [11:0] up_tx_addr_10, + input up_tx_wr_10, + input [15:0] up_tx_wdata_10, + output [15:0] up_tx_rdata_10, + output up_tx_ready_10, + + input cpll_ref_clk_11, + input up_cpll_rst_11, + + input rx_11_p, + input rx_11_n, + output rx_out_clk_11, + input rx_clk_11, + output [ 3:0] rx_charisk_11, + output [ 3:0] rx_disperr_11, + output [ 3:0] rx_notintable_11, + output [31:0] rx_data_11, + input rx_calign_11, + + output tx_11_p, + output tx_11_n, + output tx_out_clk_11, + input tx_clk_11, + input [ 3:0] tx_charisk_11, + input [31:0] tx_data_11, + + input [ 7:0] up_es_sel_11, + input up_es_enb_11, + input [11:0] up_es_addr_11, + input up_es_wr_11, + input [15:0] up_es_wdata_11, + output [15:0] up_es_rdata_11, + output up_es_ready_11, + output up_rx_pll_locked_11, + input up_rx_rst_11, + input up_rx_user_ready_11, + output up_rx_rst_done_11, + input up_rx_lpm_dfe_n_11, + input [ 2:0] up_rx_rate_11, + input [ 1:0] up_rx_sys_clk_sel_11, + input [ 2:0] up_rx_out_clk_sel_11, + input [ 7:0] up_rx_sel_11, + input up_rx_enb_11, + input [11:0] up_rx_addr_11, + input up_rx_wr_11, + input [15:0] up_rx_wdata_11, + output [15:0] up_rx_rdata_11, + output up_rx_ready_11, + output up_tx_pll_locked_11, + input up_tx_rst_11, + input up_tx_user_ready_11, + output up_tx_rst_done_11, + input up_tx_lpm_dfe_n_11, + input [ 2:0] up_tx_rate_11, + input [ 1:0] up_tx_sys_clk_sel_11, + input [ 2:0] up_tx_out_clk_sel_11, + input [ 7:0] up_tx_sel_11, + input up_tx_enb_11, + input [11:0] up_tx_addr_11, + input up_tx_wr_11, + input [15:0] up_tx_wdata_11, + output [15:0] up_tx_rdata_11, + output up_tx_ready_11, + + input qpll_ref_clk_12, + input up_qpll_rst_12, + input cpll_ref_clk_12, + input up_cpll_rst_12, + + input rx_12_p, + input rx_12_n, + output rx_out_clk_12, + input rx_clk_12, + output [ 3:0] rx_charisk_12, + output [ 3:0] rx_disperr_12, + output [ 3:0] rx_notintable_12, + output [31:0] rx_data_12, + input rx_calign_12, + + output tx_12_p, + output tx_12_n, + output tx_out_clk_12, + input tx_clk_12, + input [ 3:0] tx_charisk_12, + input [31:0] tx_data_12, + + input [ 7:0] up_cm_sel_12, + input up_cm_enb_12, + input [11:0] up_cm_addr_12, + input up_cm_wr_12, + input [15:0] up_cm_wdata_12, + output [15:0] up_cm_rdata_12, + output up_cm_ready_12, + input [ 7:0] up_es_sel_12, + input up_es_enb_12, + input [11:0] up_es_addr_12, + input up_es_wr_12, + input [15:0] up_es_wdata_12, + output [15:0] up_es_rdata_12, + output up_es_ready_12, + output up_rx_pll_locked_12, + input up_rx_rst_12, + input up_rx_user_ready_12, + output up_rx_rst_done_12, + input up_rx_lpm_dfe_n_12, + input [ 2:0] up_rx_rate_12, + input [ 1:0] up_rx_sys_clk_sel_12, + input [ 2:0] up_rx_out_clk_sel_12, + input [ 7:0] up_rx_sel_12, + input up_rx_enb_12, + input [11:0] up_rx_addr_12, + input up_rx_wr_12, + input [15:0] up_rx_wdata_12, + output [15:0] up_rx_rdata_12, + output up_rx_ready_12, + output up_tx_pll_locked_12, + input up_tx_rst_12, + input up_tx_user_ready_12, + output up_tx_rst_done_12, + input up_tx_lpm_dfe_n_12, + input [ 2:0] up_tx_rate_12, + input [ 1:0] up_tx_sys_clk_sel_12, + input [ 2:0] up_tx_out_clk_sel_12, + input [ 7:0] up_tx_sel_12, + input up_tx_enb_12, + input [11:0] up_tx_addr_12, + input up_tx_wr_12, + input [15:0] up_tx_wdata_12, + output [15:0] up_tx_rdata_12, + output up_tx_ready_12, + + input cpll_ref_clk_13, + input up_cpll_rst_13, + + input rx_13_p, + input rx_13_n, + output rx_out_clk_13, + input rx_clk_13, + output [ 3:0] rx_charisk_13, + output [ 3:0] rx_disperr_13, + output [ 3:0] rx_notintable_13, + output [31:0] rx_data_13, + input rx_calign_13, + + output tx_13_p, + output tx_13_n, + output tx_out_clk_13, + input tx_clk_13, + input [ 3:0] tx_charisk_13, + input [31:0] tx_data_13, + + input [ 7:0] up_es_sel_13, + input up_es_enb_13, + input [11:0] up_es_addr_13, + input up_es_wr_13, + input [15:0] up_es_wdata_13, + output [15:0] up_es_rdata_13, + output up_es_ready_13, + output up_rx_pll_locked_13, + input up_rx_rst_13, + input up_rx_user_ready_13, + output up_rx_rst_done_13, + input up_rx_lpm_dfe_n_13, + input [ 2:0] up_rx_rate_13, + input [ 1:0] up_rx_sys_clk_sel_13, + input [ 2:0] up_rx_out_clk_sel_13, + input [ 7:0] up_rx_sel_13, + input up_rx_enb_13, + input [11:0] up_rx_addr_13, + input up_rx_wr_13, + input [15:0] up_rx_wdata_13, + output [15:0] up_rx_rdata_13, + output up_rx_ready_13, + output up_tx_pll_locked_13, + input up_tx_rst_13, + input up_tx_user_ready_13, + output up_tx_rst_done_13, + input up_tx_lpm_dfe_n_13, + input [ 2:0] up_tx_rate_13, + input [ 1:0] up_tx_sys_clk_sel_13, + input [ 2:0] up_tx_out_clk_sel_13, + input [ 7:0] up_tx_sel_13, + input up_tx_enb_13, + input [11:0] up_tx_addr_13, + input up_tx_wr_13, + input [15:0] up_tx_wdata_13, + output [15:0] up_tx_rdata_13, + output up_tx_ready_13, + + input cpll_ref_clk_14, + input up_cpll_rst_14, + + input rx_14_p, + input rx_14_n, + output rx_out_clk_14, + input rx_clk_14, + output [ 3:0] rx_charisk_14, + output [ 3:0] rx_disperr_14, + output [ 3:0] rx_notintable_14, + output [31:0] rx_data_14, + input rx_calign_14, + + output tx_14_p, + output tx_14_n, + output tx_out_clk_14, + input tx_clk_14, + input [ 3:0] tx_charisk_14, + input [31:0] tx_data_14, + + input [ 7:0] up_es_sel_14, + input up_es_enb_14, + input [11:0] up_es_addr_14, + input up_es_wr_14, + input [15:0] up_es_wdata_14, + output [15:0] up_es_rdata_14, + output up_es_ready_14, + output up_rx_pll_locked_14, + input up_rx_rst_14, + input up_rx_user_ready_14, + output up_rx_rst_done_14, + input up_rx_lpm_dfe_n_14, + input [ 2:0] up_rx_rate_14, + input [ 1:0] up_rx_sys_clk_sel_14, + input [ 2:0] up_rx_out_clk_sel_14, + input [ 7:0] up_rx_sel_14, + input up_rx_enb_14, + input [11:0] up_rx_addr_14, + input up_rx_wr_14, + input [15:0] up_rx_wdata_14, + output [15:0] up_rx_rdata_14, + output up_rx_ready_14, + output up_tx_pll_locked_14, + input up_tx_rst_14, + input up_tx_user_ready_14, + output up_tx_rst_done_14, + input up_tx_lpm_dfe_n_14, + input [ 2:0] up_tx_rate_14, + input [ 1:0] up_tx_sys_clk_sel_14, + input [ 2:0] up_tx_out_clk_sel_14, + input [ 7:0] up_tx_sel_14, + input up_tx_enb_14, + input [11:0] up_tx_addr_14, + input up_tx_wr_14, + input [15:0] up_tx_wdata_14, + output [15:0] up_tx_rdata_14, + output up_tx_ready_14, + + input cpll_ref_clk_15, + input up_cpll_rst_15, + + input rx_15_p, + input rx_15_n, + output rx_out_clk_15, + input rx_clk_15, + output [ 3:0] rx_charisk_15, + output [ 3:0] rx_disperr_15, + output [ 3:0] rx_notintable_15, + output [31:0] rx_data_15, + input rx_calign_15, + + output tx_15_p, + output tx_15_n, + output tx_out_clk_15, + input tx_clk_15, + input [ 3:0] tx_charisk_15, + input [31:0] tx_data_15, + + input [ 7:0] up_es_sel_15, + input up_es_enb_15, + input [11:0] up_es_addr_15, + input up_es_wr_15, + input [15:0] up_es_wdata_15, + output [15:0] up_es_rdata_15, + output up_es_ready_15, + output up_rx_pll_locked_15, + input up_rx_rst_15, + input up_rx_user_ready_15, + output up_rx_rst_done_15, + input up_rx_lpm_dfe_n_15, + input [ 2:0] up_rx_rate_15, + input [ 1:0] up_rx_sys_clk_sel_15, + input [ 2:0] up_rx_out_clk_sel_15, + input [ 7:0] up_rx_sel_15, + input up_rx_enb_15, + input [11:0] up_rx_addr_15, + input up_rx_wr_15, + input [15:0] up_rx_wdata_15, + output [15:0] up_rx_rdata_15, + output up_rx_ready_15, + output up_tx_pll_locked_15, + input up_tx_rst_15, + input up_tx_user_ready_15, + output up_tx_rst_done_15, + input up_tx_lpm_dfe_n_15, + input [ 2:0] up_tx_rate_15, + input [ 1:0] up_tx_sys_clk_sel_15, + input [ 2:0] up_tx_out_clk_sel_15, + input [ 7:0] up_tx_sel_15, + input up_tx_enb_15, + input [11:0] up_tx_addr_15, + input up_tx_wr_15, + input [15:0] up_tx_wdata_15, + output [15:0] up_tx_rdata_15, + output up_tx_ready_15); + + // parameters + + localparam integer NUM_OF_LANES = (TX_NUM_OF_LANES > RX_NUM_OF_LANES) ? + TX_NUM_OF_LANES : RX_NUM_OF_LANES; + + // internal signals + + wire qpll2ch_clk_0; + wire qpll2ch_ref_clk_0; + wire qpll2ch_locked_0; + wire qpll2ch_clk_4; + wire qpll2ch_ref_clk_4; + wire qpll2ch_locked_4; + wire qpll2ch_clk_8; + wire qpll2ch_ref_clk_8; + wire qpll2ch_locked_8; + wire qpll2ch_clk_12; + wire qpll2ch_ref_clk_12; + wire qpll2ch_locked_12; + + // instantiations + + generate + if (NUM_OF_LANES >= 1) begin + util_adxcvr_xcm #( + .XCVR_ID (0), + .XCVR_TYPE (XCVR_TYPE), + .QPLL_REFCLK_DIV (QPLL_REFCLK_DIV), + .QPLL_FBDIV_RATIO (QPLL_FBDIV_RATIO), + .QPLL_CFG (QPLL_CFG), + .QPLL_FBDIV (QPLL_FBDIV)) + i_xcm_0 ( + .qpll_ref_clk (qpll_ref_clk_0), + .qpll2ch_clk (qpll2ch_clk_0), + .qpll2ch_ref_clk (qpll2ch_ref_clk_0), + .qpll2ch_locked (qpll2ch_locked_0), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_qpll_rst (up_qpll_rst_0), + .up_cm_sel (up_cm_sel_0), + .up_cm_enb (up_cm_enb_0), + .up_cm_addr (up_cm_addr_0), + .up_cm_wr (up_cm_wr_0), + .up_cm_wdata (up_cm_wdata_0), + .up_cm_rdata (up_cm_rdata_0), + .up_cm_ready (up_cm_ready_0)); + end else begin + assign qpll2ch_clk_0 = 1'd0; + assign qpll2ch_ref_clk_0 = 1'd0; + assign qpll2ch_locked_0 = 1'd0; + assign up_cm_rdata_0 = 16'd0; + assign up_cm_ready_0 = 1'd0; + end + endgenerate + + generate + if (NUM_OF_LANES >= 1) begin + util_adxcvr_xch #( + .XCVR_ID (0), + .XCVR_TYPE (XCVR_TYPE), + .CPLL_FBDIV (CPLL_FBDIV), + .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5), + .TX_OUT_DIV (TX_OUT_DIV), + .TX_CLK25_DIV (TX_CLK25_DIV), + .RX_OUT_DIV (RX_OUT_DIV), + .RX_CLK25_DIV (RX_CLK25_DIV), + .RX_DFE_LPM_CFG (RX_DFE_LPM_CFG), + .RX_PMA_CFG (RX_PMA_CFG), + .RX_CDR_CFG (RX_CDR_CFG)) + i_xch_0 ( + .qpll2ch_clk (qpll2ch_clk_0), + .qpll2ch_ref_clk (qpll2ch_ref_clk_0), + .qpll2ch_locked (qpll2ch_locked_0), + .cpll_ref_clk (cpll_ref_clk_0), + .up_cpll_rst (up_cpll_rst_0), + .rx_p (rx_0_p), + .rx_n (rx_0_n), + .rx_out_clk (rx_out_clk_0), + .rx_clk (rx_clk_0), + .rx_charisk (rx_charisk_0), + .rx_disperr (rx_disperr_0), + .rx_notintable (rx_notintable_0), + .rx_data (rx_data_0), + .rx_calign (rx_calign_0), + .tx_p (tx_0_p), + .tx_n (tx_0_n), + .tx_out_clk (tx_out_clk_0), + .tx_clk (tx_clk_0), + .tx_charisk (tx_charisk_0), + .tx_data (tx_data_0), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_es_sel (up_es_sel_0), + .up_es_enb (up_es_enb_0), + .up_es_addr (up_es_addr_0), + .up_es_wr (up_es_wr_0), + .up_es_wdata (up_es_wdata_0), + .up_es_rdata (up_es_rdata_0), + .up_es_ready (up_es_ready_0), + .up_rx_pll_locked (up_rx_pll_locked_0), + .up_rx_rst (up_rx_rst_0), + .up_rx_user_ready (up_rx_user_ready_0), + .up_rx_rst_done (up_rx_rst_done_0), + .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_0), + .up_rx_rate (up_rx_rate_0), + .up_rx_sys_clk_sel (up_rx_sys_clk_sel_0), + .up_rx_out_clk_sel (up_rx_out_clk_sel_0), + .up_rx_sel (up_rx_sel_0), + .up_rx_enb (up_rx_enb_0), + .up_rx_addr (up_rx_addr_0), + .up_rx_wr (up_rx_wr_0), + .up_rx_wdata (up_rx_wdata_0), + .up_rx_rdata (up_rx_rdata_0), + .up_rx_ready (up_rx_ready_0), + .up_tx_pll_locked (up_tx_pll_locked_0), + .up_tx_rst (up_tx_rst_0), + .up_tx_user_ready (up_tx_user_ready_0), + .up_tx_rst_done (up_tx_rst_done_0), + .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_0), + .up_tx_rate (up_tx_rate_0), + .up_tx_sys_clk_sel (up_tx_sys_clk_sel_0), + .up_tx_out_clk_sel (up_tx_out_clk_sel_0), + .up_tx_sel (up_tx_sel_0), + .up_tx_enb (up_tx_enb_0), + .up_tx_addr (up_tx_addr_0), + .up_tx_wr (up_tx_wr_0), + .up_tx_wdata (up_tx_wdata_0), + .up_tx_rdata (up_tx_rdata_0), + .up_tx_ready (up_tx_ready_0)); + end else begin + assign rx_out_clk_0 = 1'd0; + assign rx_charisk_0 = 4'd0; + assign rx_disperr_0 = 4'd0; + assign rx_notintable_0 = 4'd0; + assign rx_data_0 = 32'd0; + assign tx_0_p = 1'd0; + assign tx_0_n = 1'd0; + assign tx_out_clk_0 = 1'd0; + assign up_es_rdata_0 = 16'd0; + assign up_es_ready_0 = 1'd0; + assign up_rx_pll_locked_0 = 1'd0; + assign up_rx_rst_done_0 = 1'd0; + assign up_rx_rdata_0 = 16'd0; + assign up_rx_ready_0 = 1'd0; + assign up_tx_pll_locked_0 = 1'd0; + assign up_tx_rst_done_0 = 1'd0; + assign up_tx_rdata_0 = 16'd0; + assign up_tx_ready_0 = 1'd0; + end + endgenerate + + + generate + if (NUM_OF_LANES >= 2) begin + util_adxcvr_xch #( + .XCVR_ID (1), + .XCVR_TYPE (XCVR_TYPE), + .CPLL_FBDIV (CPLL_FBDIV), + .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5), + .TX_OUT_DIV (TX_OUT_DIV), + .TX_CLK25_DIV (TX_CLK25_DIV), + .RX_OUT_DIV (RX_OUT_DIV), + .RX_CLK25_DIV (RX_CLK25_DIV), + .RX_DFE_LPM_CFG (RX_DFE_LPM_CFG), + .RX_PMA_CFG (RX_PMA_CFG), + .RX_CDR_CFG (RX_CDR_CFG)) + i_xch_1 ( + .qpll2ch_clk (qpll2ch_clk_0), + .qpll2ch_ref_clk (qpll2ch_ref_clk_0), + .qpll2ch_locked (qpll2ch_locked_0), + .cpll_ref_clk (cpll_ref_clk_1), + .up_cpll_rst (up_cpll_rst_1), + .rx_p (rx_1_p), + .rx_n (rx_1_n), + .rx_out_clk (rx_out_clk_1), + .rx_clk (rx_clk_1), + .rx_charisk (rx_charisk_1), + .rx_disperr (rx_disperr_1), + .rx_notintable (rx_notintable_1), + .rx_data (rx_data_1), + .rx_calign (rx_calign_1), + .tx_p (tx_1_p), + .tx_n (tx_1_n), + .tx_out_clk (tx_out_clk_1), + .tx_clk (tx_clk_1), + .tx_charisk (tx_charisk_1), + .tx_data (tx_data_1), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_es_sel (up_es_sel_1), + .up_es_enb (up_es_enb_1), + .up_es_addr (up_es_addr_1), + .up_es_wr (up_es_wr_1), + .up_es_wdata (up_es_wdata_1), + .up_es_rdata (up_es_rdata_1), + .up_es_ready (up_es_ready_1), + .up_rx_pll_locked (up_rx_pll_locked_1), + .up_rx_rst (up_rx_rst_1), + .up_rx_user_ready (up_rx_user_ready_1), + .up_rx_rst_done (up_rx_rst_done_1), + .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_1), + .up_rx_rate (up_rx_rate_1), + .up_rx_sys_clk_sel (up_rx_sys_clk_sel_1), + .up_rx_out_clk_sel (up_rx_out_clk_sel_1), + .up_rx_sel (up_rx_sel_1), + .up_rx_enb (up_rx_enb_1), + .up_rx_addr (up_rx_addr_1), + .up_rx_wr (up_rx_wr_1), + .up_rx_wdata (up_rx_wdata_1), + .up_rx_rdata (up_rx_rdata_1), + .up_rx_ready (up_rx_ready_1), + .up_tx_pll_locked (up_tx_pll_locked_1), + .up_tx_rst (up_tx_rst_1), + .up_tx_user_ready (up_tx_user_ready_1), + .up_tx_rst_done (up_tx_rst_done_1), + .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_1), + .up_tx_rate (up_tx_rate_1), + .up_tx_sys_clk_sel (up_tx_sys_clk_sel_1), + .up_tx_out_clk_sel (up_tx_out_clk_sel_1), + .up_tx_sel (up_tx_sel_1), + .up_tx_enb (up_tx_enb_1), + .up_tx_addr (up_tx_addr_1), + .up_tx_wr (up_tx_wr_1), + .up_tx_wdata (up_tx_wdata_1), + .up_tx_rdata (up_tx_rdata_1), + .up_tx_ready (up_tx_ready_1)); + end else begin + assign rx_out_clk_1 = 1'd0; + assign rx_charisk_1 = 4'd0; + assign rx_disperr_1 = 4'd0; + assign rx_notintable_1 = 4'd0; + assign rx_data_1 = 32'd0; + assign tx_1_p = 1'd0; + assign tx_1_n = 1'd0; + assign tx_out_clk_1 = 1'd0; + assign up_es_rdata_1 = 16'd0; + assign up_es_ready_1 = 1'd0; + assign up_rx_pll_locked_1 = 1'd0; + assign up_rx_rst_done_1 = 1'd0; + assign up_rx_rdata_1 = 16'd0; + assign up_rx_ready_1 = 1'd0; + assign up_tx_pll_locked_1 = 1'd0; + assign up_tx_rst_done_1 = 1'd0; + assign up_tx_rdata_1 = 16'd0; + assign up_tx_ready_1 = 1'd0; + end + endgenerate + + + generate + if (NUM_OF_LANES >= 3) begin + util_adxcvr_xch #( + .XCVR_ID (2), + .XCVR_TYPE (XCVR_TYPE), + .CPLL_FBDIV (CPLL_FBDIV), + .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5), + .TX_OUT_DIV (TX_OUT_DIV), + .TX_CLK25_DIV (TX_CLK25_DIV), + .RX_OUT_DIV (RX_OUT_DIV), + .RX_CLK25_DIV (RX_CLK25_DIV), + .RX_DFE_LPM_CFG (RX_DFE_LPM_CFG), + .RX_PMA_CFG (RX_PMA_CFG), + .RX_CDR_CFG (RX_CDR_CFG)) + i_xch_2 ( + .qpll2ch_clk (qpll2ch_clk_0), + .qpll2ch_ref_clk (qpll2ch_ref_clk_0), + .qpll2ch_locked (qpll2ch_locked_0), + .cpll_ref_clk (cpll_ref_clk_2), + .up_cpll_rst (up_cpll_rst_2), + .rx_p (rx_2_p), + .rx_n (rx_2_n), + .rx_out_clk (rx_out_clk_2), + .rx_clk (rx_clk_2), + .rx_charisk (rx_charisk_2), + .rx_disperr (rx_disperr_2), + .rx_notintable (rx_notintable_2), + .rx_data (rx_data_2), + .rx_calign (rx_calign_2), + .tx_p (tx_2_p), + .tx_n (tx_2_n), + .tx_out_clk (tx_out_clk_2), + .tx_clk (tx_clk_2), + .tx_charisk (tx_charisk_2), + .tx_data (tx_data_2), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_es_sel (up_es_sel_2), + .up_es_enb (up_es_enb_2), + .up_es_addr (up_es_addr_2), + .up_es_wr (up_es_wr_2), + .up_es_wdata (up_es_wdata_2), + .up_es_rdata (up_es_rdata_2), + .up_es_ready (up_es_ready_2), + .up_rx_pll_locked (up_rx_pll_locked_2), + .up_rx_rst (up_rx_rst_2), + .up_rx_user_ready (up_rx_user_ready_2), + .up_rx_rst_done (up_rx_rst_done_2), + .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_2), + .up_rx_rate (up_rx_rate_2), + .up_rx_sys_clk_sel (up_rx_sys_clk_sel_2), + .up_rx_out_clk_sel (up_rx_out_clk_sel_2), + .up_rx_sel (up_rx_sel_2), + .up_rx_enb (up_rx_enb_2), + .up_rx_addr (up_rx_addr_2), + .up_rx_wr (up_rx_wr_2), + .up_rx_wdata (up_rx_wdata_2), + .up_rx_rdata (up_rx_rdata_2), + .up_rx_ready (up_rx_ready_2), + .up_tx_pll_locked (up_tx_pll_locked_2), + .up_tx_rst (up_tx_rst_2), + .up_tx_user_ready (up_tx_user_ready_2), + .up_tx_rst_done (up_tx_rst_done_2), + .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_2), + .up_tx_rate (up_tx_rate_2), + .up_tx_sys_clk_sel (up_tx_sys_clk_sel_2), + .up_tx_out_clk_sel (up_tx_out_clk_sel_2), + .up_tx_sel (up_tx_sel_2), + .up_tx_enb (up_tx_enb_2), + .up_tx_addr (up_tx_addr_2), + .up_tx_wr (up_tx_wr_2), + .up_tx_wdata (up_tx_wdata_2), + .up_tx_rdata (up_tx_rdata_2), + .up_tx_ready (up_tx_ready_2)); + end else begin + assign rx_out_clk_2 = 1'd0; + assign rx_charisk_2 = 4'd0; + assign rx_disperr_2 = 4'd0; + assign rx_notintable_2 = 4'd0; + assign rx_data_2 = 32'd0; + assign tx_2_p = 1'd0; + assign tx_2_n = 1'd0; + assign tx_out_clk_2 = 1'd0; + assign up_es_rdata_2 = 16'd0; + assign up_es_ready_2 = 1'd0; + assign up_rx_pll_locked_2 = 1'd0; + assign up_rx_rst_done_2 = 1'd0; + assign up_rx_rdata_2 = 16'd0; + assign up_rx_ready_2 = 1'd0; + assign up_tx_pll_locked_2 = 1'd0; + assign up_tx_rst_done_2 = 1'd0; + assign up_tx_rdata_2 = 16'd0; + assign up_tx_ready_2 = 1'd0; + end + endgenerate + + + generate + if (NUM_OF_LANES >= 4) begin + util_adxcvr_xch #( + .XCVR_ID (3), + .XCVR_TYPE (XCVR_TYPE), + .CPLL_FBDIV (CPLL_FBDIV), + .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5), + .TX_OUT_DIV (TX_OUT_DIV), + .TX_CLK25_DIV (TX_CLK25_DIV), + .RX_OUT_DIV (RX_OUT_DIV), + .RX_CLK25_DIV (RX_CLK25_DIV), + .RX_DFE_LPM_CFG (RX_DFE_LPM_CFG), + .RX_PMA_CFG (RX_PMA_CFG), + .RX_CDR_CFG (RX_CDR_CFG)) + i_xch_3 ( + .qpll2ch_clk (qpll2ch_clk_0), + .qpll2ch_ref_clk (qpll2ch_ref_clk_0), + .qpll2ch_locked (qpll2ch_locked_0), + .cpll_ref_clk (cpll_ref_clk_3), + .up_cpll_rst (up_cpll_rst_3), + .rx_p (rx_3_p), + .rx_n (rx_3_n), + .rx_out_clk (rx_out_clk_3), + .rx_clk (rx_clk_3), + .rx_charisk (rx_charisk_3), + .rx_disperr (rx_disperr_3), + .rx_notintable (rx_notintable_3), + .rx_data (rx_data_3), + .rx_calign (rx_calign_3), + .tx_p (tx_3_p), + .tx_n (tx_3_n), + .tx_out_clk (tx_out_clk_3), + .tx_clk (tx_clk_3), + .tx_charisk (tx_charisk_3), + .tx_data (tx_data_3), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_es_sel (up_es_sel_3), + .up_es_enb (up_es_enb_3), + .up_es_addr (up_es_addr_3), + .up_es_wr (up_es_wr_3), + .up_es_wdata (up_es_wdata_3), + .up_es_rdata (up_es_rdata_3), + .up_es_ready (up_es_ready_3), + .up_rx_pll_locked (up_rx_pll_locked_3), + .up_rx_rst (up_rx_rst_3), + .up_rx_user_ready (up_rx_user_ready_3), + .up_rx_rst_done (up_rx_rst_done_3), + .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_3), + .up_rx_rate (up_rx_rate_3), + .up_rx_sys_clk_sel (up_rx_sys_clk_sel_3), + .up_rx_out_clk_sel (up_rx_out_clk_sel_3), + .up_rx_sel (up_rx_sel_3), + .up_rx_enb (up_rx_enb_3), + .up_rx_addr (up_rx_addr_3), + .up_rx_wr (up_rx_wr_3), + .up_rx_wdata (up_rx_wdata_3), + .up_rx_rdata (up_rx_rdata_3), + .up_rx_ready (up_rx_ready_3), + .up_tx_pll_locked (up_tx_pll_locked_3), + .up_tx_rst (up_tx_rst_3), + .up_tx_user_ready (up_tx_user_ready_3), + .up_tx_rst_done (up_tx_rst_done_3), + .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_3), + .up_tx_rate (up_tx_rate_3), + .up_tx_sys_clk_sel (up_tx_sys_clk_sel_3), + .up_tx_out_clk_sel (up_tx_out_clk_sel_3), + .up_tx_sel (up_tx_sel_3), + .up_tx_enb (up_tx_enb_3), + .up_tx_addr (up_tx_addr_3), + .up_tx_wr (up_tx_wr_3), + .up_tx_wdata (up_tx_wdata_3), + .up_tx_rdata (up_tx_rdata_3), + .up_tx_ready (up_tx_ready_3)); + end else begin + assign rx_out_clk_3 = 1'd0; + assign rx_charisk_3 = 4'd0; + assign rx_disperr_3 = 4'd0; + assign rx_notintable_3 = 4'd0; + assign rx_data_3 = 32'd0; + assign tx_3_p = 1'd0; + assign tx_3_n = 1'd0; + assign tx_out_clk_3 = 1'd0; + assign up_es_rdata_3 = 16'd0; + assign up_es_ready_3 = 1'd0; + assign up_rx_pll_locked_3 = 1'd0; + assign up_rx_rst_done_3 = 1'd0; + assign up_rx_rdata_3 = 16'd0; + assign up_rx_ready_3 = 1'd0; + assign up_tx_pll_locked_3 = 1'd0; + assign up_tx_rst_done_3 = 1'd0; + assign up_tx_rdata_3 = 16'd0; + assign up_tx_ready_3 = 1'd0; + end + endgenerate + + generate + if (NUM_OF_LANES >= 5) begin + util_adxcvr_xcm #( + .XCVR_ID (4), + .XCVR_TYPE (XCVR_TYPE), + .QPLL_REFCLK_DIV (QPLL_REFCLK_DIV), + .QPLL_FBDIV_RATIO (QPLL_FBDIV_RATIO), + .QPLL_CFG (QPLL_CFG), + .QPLL_FBDIV (QPLL_FBDIV)) + i_xcm_4 ( + .qpll_ref_clk (qpll_ref_clk_4), + .qpll2ch_clk (qpll2ch_clk_4), + .qpll2ch_ref_clk (qpll2ch_ref_clk_4), + .qpll2ch_locked (qpll2ch_locked_4), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_qpll_rst (up_qpll_rst_4), + .up_cm_sel (up_cm_sel_4), + .up_cm_enb (up_cm_enb_4), + .up_cm_addr (up_cm_addr_4), + .up_cm_wr (up_cm_wr_4), + .up_cm_wdata (up_cm_wdata_4), + .up_cm_rdata (up_cm_rdata_4), + .up_cm_ready (up_cm_ready_4)); + end else begin + assign qpll2ch_clk_4 = 1'd0; + assign qpll2ch_ref_clk_4 = 1'd0; + assign qpll2ch_locked_4 = 1'd0; + assign up_cm_rdata_4 = 16'd0; + assign up_cm_ready_4 = 1'd0; + end + endgenerate + + generate + if (NUM_OF_LANES >= 5) begin + util_adxcvr_xch #( + .XCVR_ID (4), + .XCVR_TYPE (XCVR_TYPE), + .CPLL_FBDIV (CPLL_FBDIV), + .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5), + .TX_OUT_DIV (TX_OUT_DIV), + .TX_CLK25_DIV (TX_CLK25_DIV), + .RX_OUT_DIV (RX_OUT_DIV), + .RX_CLK25_DIV (RX_CLK25_DIV), + .RX_DFE_LPM_CFG (RX_DFE_LPM_CFG), + .RX_PMA_CFG (RX_PMA_CFG), + .RX_CDR_CFG (RX_CDR_CFG)) + i_xch_4 ( + .qpll2ch_clk (qpll2ch_clk_4), + .qpll2ch_ref_clk (qpll2ch_ref_clk_4), + .qpll2ch_locked (qpll2ch_locked_4), + .cpll_ref_clk (cpll_ref_clk_4), + .up_cpll_rst (up_cpll_rst_4), + .rx_p (rx_4_p), + .rx_n (rx_4_n), + .rx_out_clk (rx_out_clk_4), + .rx_clk (rx_clk_4), + .rx_charisk (rx_charisk_4), + .rx_disperr (rx_disperr_4), + .rx_notintable (rx_notintable_4), + .rx_data (rx_data_4), + .rx_calign (rx_calign_4), + .tx_p (tx_4_p), + .tx_n (tx_4_n), + .tx_out_clk (tx_out_clk_4), + .tx_clk (tx_clk_4), + .tx_charisk (tx_charisk_4), + .tx_data (tx_data_4), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_es_sel (up_es_sel_4), + .up_es_enb (up_es_enb_4), + .up_es_addr (up_es_addr_4), + .up_es_wr (up_es_wr_4), + .up_es_wdata (up_es_wdata_4), + .up_es_rdata (up_es_rdata_4), + .up_es_ready (up_es_ready_4), + .up_rx_pll_locked (up_rx_pll_locked_4), + .up_rx_rst (up_rx_rst_4), + .up_rx_user_ready (up_rx_user_ready_4), + .up_rx_rst_done (up_rx_rst_done_4), + .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_4), + .up_rx_rate (up_rx_rate_4), + .up_rx_sys_clk_sel (up_rx_sys_clk_sel_4), + .up_rx_out_clk_sel (up_rx_out_clk_sel_4), + .up_rx_sel (up_rx_sel_4), + .up_rx_enb (up_rx_enb_4), + .up_rx_addr (up_rx_addr_4), + .up_rx_wr (up_rx_wr_4), + .up_rx_wdata (up_rx_wdata_4), + .up_rx_rdata (up_rx_rdata_4), + .up_rx_ready (up_rx_ready_4), + .up_tx_pll_locked (up_tx_pll_locked_4), + .up_tx_rst (up_tx_rst_4), + .up_tx_user_ready (up_tx_user_ready_4), + .up_tx_rst_done (up_tx_rst_done_4), + .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_4), + .up_tx_rate (up_tx_rate_4), + .up_tx_sys_clk_sel (up_tx_sys_clk_sel_4), + .up_tx_out_clk_sel (up_tx_out_clk_sel_4), + .up_tx_sel (up_tx_sel_4), + .up_tx_enb (up_tx_enb_4), + .up_tx_addr (up_tx_addr_4), + .up_tx_wr (up_tx_wr_4), + .up_tx_wdata (up_tx_wdata_4), + .up_tx_rdata (up_tx_rdata_4), + .up_tx_ready (up_tx_ready_4)); + end else begin + assign rx_out_clk_4 = 1'd0; + assign rx_charisk_4 = 4'd0; + assign rx_disperr_4 = 4'd0; + assign rx_notintable_4 = 4'd0; + assign rx_data_4 = 32'd0; + assign tx_4_p = 1'd0; + assign tx_4_n = 1'd0; + assign tx_out_clk_4 = 1'd0; + assign up_es_rdata_4 = 16'd0; + assign up_es_ready_4 = 1'd0; + assign up_rx_pll_locked_4 = 1'd0; + assign up_rx_rst_done_4 = 1'd0; + assign up_rx_rdata_4 = 16'd0; + assign up_rx_ready_4 = 1'd0; + assign up_tx_pll_locked_4 = 1'd0; + assign up_tx_rst_done_4 = 1'd0; + assign up_tx_rdata_4 = 16'd0; + assign up_tx_ready_4 = 1'd0; + end + endgenerate + + + generate + if (NUM_OF_LANES >= 6) begin + util_adxcvr_xch #( + .XCVR_ID (5), + .XCVR_TYPE (XCVR_TYPE), + .CPLL_FBDIV (CPLL_FBDIV), + .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5), + .TX_OUT_DIV (TX_OUT_DIV), + .TX_CLK25_DIV (TX_CLK25_DIV), + .RX_OUT_DIV (RX_OUT_DIV), + .RX_CLK25_DIV (RX_CLK25_DIV), + .RX_DFE_LPM_CFG (RX_DFE_LPM_CFG), + .RX_PMA_CFG (RX_PMA_CFG), + .RX_CDR_CFG (RX_CDR_CFG)) + i_xch_5 ( + .qpll2ch_clk (qpll2ch_clk_4), + .qpll2ch_ref_clk (qpll2ch_ref_clk_4), + .qpll2ch_locked (qpll2ch_locked_4), + .cpll_ref_clk (cpll_ref_clk_5), + .up_cpll_rst (up_cpll_rst_5), + .rx_p (rx_5_p), + .rx_n (rx_5_n), + .rx_out_clk (rx_out_clk_5), + .rx_clk (rx_clk_5), + .rx_charisk (rx_charisk_5), + .rx_disperr (rx_disperr_5), + .rx_notintable (rx_notintable_5), + .rx_data (rx_data_5), + .rx_calign (rx_calign_5), + .tx_p (tx_5_p), + .tx_n (tx_5_n), + .tx_out_clk (tx_out_clk_5), + .tx_clk (tx_clk_5), + .tx_charisk (tx_charisk_5), + .tx_data (tx_data_5), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_es_sel (up_es_sel_5), + .up_es_enb (up_es_enb_5), + .up_es_addr (up_es_addr_5), + .up_es_wr (up_es_wr_5), + .up_es_wdata (up_es_wdata_5), + .up_es_rdata (up_es_rdata_5), + .up_es_ready (up_es_ready_5), + .up_rx_pll_locked (up_rx_pll_locked_5), + .up_rx_rst (up_rx_rst_5), + .up_rx_user_ready (up_rx_user_ready_5), + .up_rx_rst_done (up_rx_rst_done_5), + .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_5), + .up_rx_rate (up_rx_rate_5), + .up_rx_sys_clk_sel (up_rx_sys_clk_sel_5), + .up_rx_out_clk_sel (up_rx_out_clk_sel_5), + .up_rx_sel (up_rx_sel_5), + .up_rx_enb (up_rx_enb_5), + .up_rx_addr (up_rx_addr_5), + .up_rx_wr (up_rx_wr_5), + .up_rx_wdata (up_rx_wdata_5), + .up_rx_rdata (up_rx_rdata_5), + .up_rx_ready (up_rx_ready_5), + .up_tx_pll_locked (up_tx_pll_locked_5), + .up_tx_rst (up_tx_rst_5), + .up_tx_user_ready (up_tx_user_ready_5), + .up_tx_rst_done (up_tx_rst_done_5), + .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_5), + .up_tx_rate (up_tx_rate_5), + .up_tx_sys_clk_sel (up_tx_sys_clk_sel_5), + .up_tx_out_clk_sel (up_tx_out_clk_sel_5), + .up_tx_sel (up_tx_sel_5), + .up_tx_enb (up_tx_enb_5), + .up_tx_addr (up_tx_addr_5), + .up_tx_wr (up_tx_wr_5), + .up_tx_wdata (up_tx_wdata_5), + .up_tx_rdata (up_tx_rdata_5), + .up_tx_ready (up_tx_ready_5)); + end else begin + assign rx_out_clk_5 = 1'd0; + assign rx_charisk_5 = 4'd0; + assign rx_disperr_5 = 4'd0; + assign rx_notintable_5 = 4'd0; + assign rx_data_5 = 32'd0; + assign tx_5_p = 1'd0; + assign tx_5_n = 1'd0; + assign tx_out_clk_5 = 1'd0; + assign up_es_rdata_5 = 16'd0; + assign up_es_ready_5 = 1'd0; + assign up_rx_pll_locked_5 = 1'd0; + assign up_rx_rst_done_5 = 1'd0; + assign up_rx_rdata_5 = 16'd0; + assign up_rx_ready_5 = 1'd0; + assign up_tx_pll_locked_5 = 1'd0; + assign up_tx_rst_done_5 = 1'd0; + assign up_tx_rdata_5 = 16'd0; + assign up_tx_ready_5 = 1'd0; + end + endgenerate + + + generate + if (NUM_OF_LANES >= 7) begin + util_adxcvr_xch #( + .XCVR_ID (6), + .XCVR_TYPE (XCVR_TYPE), + .CPLL_FBDIV (CPLL_FBDIV), + .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5), + .TX_OUT_DIV (TX_OUT_DIV), + .TX_CLK25_DIV (TX_CLK25_DIV), + .RX_OUT_DIV (RX_OUT_DIV), + .RX_CLK25_DIV (RX_CLK25_DIV), + .RX_DFE_LPM_CFG (RX_DFE_LPM_CFG), + .RX_PMA_CFG (RX_PMA_CFG), + .RX_CDR_CFG (RX_CDR_CFG)) + i_xch_6 ( + .qpll2ch_clk (qpll2ch_clk_4), + .qpll2ch_ref_clk (qpll2ch_ref_clk_4), + .qpll2ch_locked (qpll2ch_locked_4), + .cpll_ref_clk (cpll_ref_clk_6), + .up_cpll_rst (up_cpll_rst_6), + .rx_p (rx_6_p), + .rx_n (rx_6_n), + .rx_out_clk (rx_out_clk_6), + .rx_clk (rx_clk_6), + .rx_charisk (rx_charisk_6), + .rx_disperr (rx_disperr_6), + .rx_notintable (rx_notintable_6), + .rx_data (rx_data_6), + .rx_calign (rx_calign_6), + .tx_p (tx_6_p), + .tx_n (tx_6_n), + .tx_out_clk (tx_out_clk_6), + .tx_clk (tx_clk_6), + .tx_charisk (tx_charisk_6), + .tx_data (tx_data_6), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_es_sel (up_es_sel_6), + .up_es_enb (up_es_enb_6), + .up_es_addr (up_es_addr_6), + .up_es_wr (up_es_wr_6), + .up_es_wdata (up_es_wdata_6), + .up_es_rdata (up_es_rdata_6), + .up_es_ready (up_es_ready_6), + .up_rx_pll_locked (up_rx_pll_locked_6), + .up_rx_rst (up_rx_rst_6), + .up_rx_user_ready (up_rx_user_ready_6), + .up_rx_rst_done (up_rx_rst_done_6), + .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_6), + .up_rx_rate (up_rx_rate_6), + .up_rx_sys_clk_sel (up_rx_sys_clk_sel_6), + .up_rx_out_clk_sel (up_rx_out_clk_sel_6), + .up_rx_sel (up_rx_sel_6), + .up_rx_enb (up_rx_enb_6), + .up_rx_addr (up_rx_addr_6), + .up_rx_wr (up_rx_wr_6), + .up_rx_wdata (up_rx_wdata_6), + .up_rx_rdata (up_rx_rdata_6), + .up_rx_ready (up_rx_ready_6), + .up_tx_pll_locked (up_tx_pll_locked_6), + .up_tx_rst (up_tx_rst_6), + .up_tx_user_ready (up_tx_user_ready_6), + .up_tx_rst_done (up_tx_rst_done_6), + .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_6), + .up_tx_rate (up_tx_rate_6), + .up_tx_sys_clk_sel (up_tx_sys_clk_sel_6), + .up_tx_out_clk_sel (up_tx_out_clk_sel_6), + .up_tx_sel (up_tx_sel_6), + .up_tx_enb (up_tx_enb_6), + .up_tx_addr (up_tx_addr_6), + .up_tx_wr (up_tx_wr_6), + .up_tx_wdata (up_tx_wdata_6), + .up_tx_rdata (up_tx_rdata_6), + .up_tx_ready (up_tx_ready_6)); + end else begin + assign rx_out_clk_6 = 1'd0; + assign rx_charisk_6 = 4'd0; + assign rx_disperr_6 = 4'd0; + assign rx_notintable_6 = 4'd0; + assign rx_data_6 = 32'd0; + assign tx_6_p = 1'd0; + assign tx_6_n = 1'd0; + assign tx_out_clk_6 = 1'd0; + assign up_es_rdata_6 = 16'd0; + assign up_es_ready_6 = 1'd0; + assign up_rx_pll_locked_6 = 1'd0; + assign up_rx_rst_done_6 = 1'd0; + assign up_rx_rdata_6 = 16'd0; + assign up_rx_ready_6 = 1'd0; + assign up_tx_pll_locked_6 = 1'd0; + assign up_tx_rst_done_6 = 1'd0; + assign up_tx_rdata_6 = 16'd0; + assign up_tx_ready_6 = 1'd0; + end + endgenerate + + + generate + if (NUM_OF_LANES >= 8) begin + util_adxcvr_xch #( + .XCVR_ID (7), + .XCVR_TYPE (XCVR_TYPE), + .CPLL_FBDIV (CPLL_FBDIV), + .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5), + .TX_OUT_DIV (TX_OUT_DIV), + .TX_CLK25_DIV (TX_CLK25_DIV), + .RX_OUT_DIV (RX_OUT_DIV), + .RX_CLK25_DIV (RX_CLK25_DIV), + .RX_DFE_LPM_CFG (RX_DFE_LPM_CFG), + .RX_PMA_CFG (RX_PMA_CFG), + .RX_CDR_CFG (RX_CDR_CFG)) + i_xch_7 ( + .qpll2ch_clk (qpll2ch_clk_4), + .qpll2ch_ref_clk (qpll2ch_ref_clk_4), + .qpll2ch_locked (qpll2ch_locked_4), + .cpll_ref_clk (cpll_ref_clk_7), + .up_cpll_rst (up_cpll_rst_7), + .rx_p (rx_7_p), + .rx_n (rx_7_n), + .rx_out_clk (rx_out_clk_7), + .rx_clk (rx_clk_7), + .rx_charisk (rx_charisk_7), + .rx_disperr (rx_disperr_7), + .rx_notintable (rx_notintable_7), + .rx_data (rx_data_7), + .rx_calign (rx_calign_7), + .tx_p (tx_7_p), + .tx_n (tx_7_n), + .tx_out_clk (tx_out_clk_7), + .tx_clk (tx_clk_7), + .tx_charisk (tx_charisk_7), + .tx_data (tx_data_7), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_es_sel (up_es_sel_7), + .up_es_enb (up_es_enb_7), + .up_es_addr (up_es_addr_7), + .up_es_wr (up_es_wr_7), + .up_es_wdata (up_es_wdata_7), + .up_es_rdata (up_es_rdata_7), + .up_es_ready (up_es_ready_7), + .up_rx_pll_locked (up_rx_pll_locked_7), + .up_rx_rst (up_rx_rst_7), + .up_rx_user_ready (up_rx_user_ready_7), + .up_rx_rst_done (up_rx_rst_done_7), + .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_7), + .up_rx_rate (up_rx_rate_7), + .up_rx_sys_clk_sel (up_rx_sys_clk_sel_7), + .up_rx_out_clk_sel (up_rx_out_clk_sel_7), + .up_rx_sel (up_rx_sel_7), + .up_rx_enb (up_rx_enb_7), + .up_rx_addr (up_rx_addr_7), + .up_rx_wr (up_rx_wr_7), + .up_rx_wdata (up_rx_wdata_7), + .up_rx_rdata (up_rx_rdata_7), + .up_rx_ready (up_rx_ready_7), + .up_tx_pll_locked (up_tx_pll_locked_7), + .up_tx_rst (up_tx_rst_7), + .up_tx_user_ready (up_tx_user_ready_7), + .up_tx_rst_done (up_tx_rst_done_7), + .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_7), + .up_tx_rate (up_tx_rate_7), + .up_tx_sys_clk_sel (up_tx_sys_clk_sel_7), + .up_tx_out_clk_sel (up_tx_out_clk_sel_7), + .up_tx_sel (up_tx_sel_7), + .up_tx_enb (up_tx_enb_7), + .up_tx_addr (up_tx_addr_7), + .up_tx_wr (up_tx_wr_7), + .up_tx_wdata (up_tx_wdata_7), + .up_tx_rdata (up_tx_rdata_7), + .up_tx_ready (up_tx_ready_7)); + end else begin + assign rx_out_clk_7 = 1'd0; + assign rx_charisk_7 = 4'd0; + assign rx_disperr_7 = 4'd0; + assign rx_notintable_7 = 4'd0; + assign rx_data_7 = 32'd0; + assign tx_7_p = 1'd0; + assign tx_7_n = 1'd0; + assign tx_out_clk_7 = 1'd0; + assign up_es_rdata_7 = 16'd0; + assign up_es_ready_7 = 1'd0; + assign up_rx_pll_locked_7 = 1'd0; + assign up_rx_rst_done_7 = 1'd0; + assign up_rx_rdata_7 = 16'd0; + assign up_rx_ready_7 = 1'd0; + assign up_tx_pll_locked_7 = 1'd0; + assign up_tx_rst_done_7 = 1'd0; + assign up_tx_rdata_7 = 16'd0; + assign up_tx_ready_7 = 1'd0; + end + endgenerate + + generate + if (NUM_OF_LANES >= 9) begin + util_adxcvr_xcm #( + .XCVR_ID (8), + .XCVR_TYPE (XCVR_TYPE), + .QPLL_REFCLK_DIV (QPLL_REFCLK_DIV), + .QPLL_FBDIV_RATIO (QPLL_FBDIV_RATIO), + .QPLL_CFG (QPLL_CFG), + .QPLL_FBDIV (QPLL_FBDIV)) + i_xcm_8 ( + .qpll_ref_clk (qpll_ref_clk_8), + .qpll2ch_clk (qpll2ch_clk_8), + .qpll2ch_ref_clk (qpll2ch_ref_clk_8), + .qpll2ch_locked (qpll2ch_locked_8), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_qpll_rst (up_qpll_rst_8), + .up_cm_sel (up_cm_sel_8), + .up_cm_enb (up_cm_enb_8), + .up_cm_addr (up_cm_addr_8), + .up_cm_wr (up_cm_wr_8), + .up_cm_wdata (up_cm_wdata_8), + .up_cm_rdata (up_cm_rdata_8), + .up_cm_ready (up_cm_ready_8)); + end else begin + assign qpll2ch_clk_8 = 1'd0; + assign qpll2ch_ref_clk_8 = 1'd0; + assign qpll2ch_locked_8 = 1'd0; + assign up_cm_rdata_8 = 16'd0; + assign up_cm_ready_8 = 1'd0; + end + endgenerate + + generate + if (NUM_OF_LANES >= 9) begin + util_adxcvr_xch #( + .XCVR_ID (8), + .XCVR_TYPE (XCVR_TYPE), + .CPLL_FBDIV (CPLL_FBDIV), + .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5), + .TX_OUT_DIV (TX_OUT_DIV), + .TX_CLK25_DIV (TX_CLK25_DIV), + .RX_OUT_DIV (RX_OUT_DIV), + .RX_CLK25_DIV (RX_CLK25_DIV), + .RX_DFE_LPM_CFG (RX_DFE_LPM_CFG), + .RX_PMA_CFG (RX_PMA_CFG), + .RX_CDR_CFG (RX_CDR_CFG)) + i_xch_8 ( + .qpll2ch_clk (qpll2ch_clk_8), + .qpll2ch_ref_clk (qpll2ch_ref_clk_8), + .qpll2ch_locked (qpll2ch_locked_8), + .cpll_ref_clk (cpll_ref_clk_8), + .up_cpll_rst (up_cpll_rst_8), + .rx_p (rx_8_p), + .rx_n (rx_8_n), + .rx_out_clk (rx_out_clk_8), + .rx_clk (rx_clk_8), + .rx_charisk (rx_charisk_8), + .rx_disperr (rx_disperr_8), + .rx_notintable (rx_notintable_8), + .rx_data (rx_data_8), + .rx_calign (rx_calign_8), + .tx_p (tx_8_p), + .tx_n (tx_8_n), + .tx_out_clk (tx_out_clk_8), + .tx_clk (tx_clk_8), + .tx_charisk (tx_charisk_8), + .tx_data (tx_data_8), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_es_sel (up_es_sel_8), + .up_es_enb (up_es_enb_8), + .up_es_addr (up_es_addr_8), + .up_es_wr (up_es_wr_8), + .up_es_wdata (up_es_wdata_8), + .up_es_rdata (up_es_rdata_8), + .up_es_ready (up_es_ready_8), + .up_rx_pll_locked (up_rx_pll_locked_8), + .up_rx_rst (up_rx_rst_8), + .up_rx_user_ready (up_rx_user_ready_8), + .up_rx_rst_done (up_rx_rst_done_8), + .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_8), + .up_rx_rate (up_rx_rate_8), + .up_rx_sys_clk_sel (up_rx_sys_clk_sel_8), + .up_rx_out_clk_sel (up_rx_out_clk_sel_8), + .up_rx_sel (up_rx_sel_8), + .up_rx_enb (up_rx_enb_8), + .up_rx_addr (up_rx_addr_8), + .up_rx_wr (up_rx_wr_8), + .up_rx_wdata (up_rx_wdata_8), + .up_rx_rdata (up_rx_rdata_8), + .up_rx_ready (up_rx_ready_8), + .up_tx_pll_locked (up_tx_pll_locked_8), + .up_tx_rst (up_tx_rst_8), + .up_tx_user_ready (up_tx_user_ready_8), + .up_tx_rst_done (up_tx_rst_done_8), + .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_8), + .up_tx_rate (up_tx_rate_8), + .up_tx_sys_clk_sel (up_tx_sys_clk_sel_8), + .up_tx_out_clk_sel (up_tx_out_clk_sel_8), + .up_tx_sel (up_tx_sel_8), + .up_tx_enb (up_tx_enb_8), + .up_tx_addr (up_tx_addr_8), + .up_tx_wr (up_tx_wr_8), + .up_tx_wdata (up_tx_wdata_8), + .up_tx_rdata (up_tx_rdata_8), + .up_tx_ready (up_tx_ready_8)); + end else begin + assign rx_out_clk_8 = 1'd0; + assign rx_charisk_8 = 4'd0; + assign rx_disperr_8 = 4'd0; + assign rx_notintable_8 = 4'd0; + assign rx_data_8 = 32'd0; + assign tx_8_p = 1'd0; + assign tx_8_n = 1'd0; + assign tx_out_clk_8 = 1'd0; + assign up_es_rdata_8 = 16'd0; + assign up_es_ready_8 = 1'd0; + assign up_rx_pll_locked_8 = 1'd0; + assign up_rx_rst_done_8 = 1'd0; + assign up_rx_rdata_8 = 16'd0; + assign up_rx_ready_8 = 1'd0; + assign up_tx_pll_locked_8 = 1'd0; + assign up_tx_rst_done_8 = 1'd0; + assign up_tx_rdata_8 = 16'd0; + assign up_tx_ready_8 = 1'd0; + end + endgenerate + + + generate + if (NUM_OF_LANES >= 10) begin + util_adxcvr_xch #( + .XCVR_ID (9), + .XCVR_TYPE (XCVR_TYPE), + .CPLL_FBDIV (CPLL_FBDIV), + .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5), + .TX_OUT_DIV (TX_OUT_DIV), + .TX_CLK25_DIV (TX_CLK25_DIV), + .RX_OUT_DIV (RX_OUT_DIV), + .RX_CLK25_DIV (RX_CLK25_DIV), + .RX_DFE_LPM_CFG (RX_DFE_LPM_CFG), + .RX_PMA_CFG (RX_PMA_CFG), + .RX_CDR_CFG (RX_CDR_CFG)) + i_xch_9 ( + .qpll2ch_clk (qpll2ch_clk_8), + .qpll2ch_ref_clk (qpll2ch_ref_clk_8), + .qpll2ch_locked (qpll2ch_locked_8), + .cpll_ref_clk (cpll_ref_clk_9), + .up_cpll_rst (up_cpll_rst_9), + .rx_p (rx_9_p), + .rx_n (rx_9_n), + .rx_out_clk (rx_out_clk_9), + .rx_clk (rx_clk_9), + .rx_charisk (rx_charisk_9), + .rx_disperr (rx_disperr_9), + .rx_notintable (rx_notintable_9), + .rx_data (rx_data_9), + .rx_calign (rx_calign_9), + .tx_p (tx_9_p), + .tx_n (tx_9_n), + .tx_out_clk (tx_out_clk_9), + .tx_clk (tx_clk_9), + .tx_charisk (tx_charisk_9), + .tx_data (tx_data_9), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_es_sel (up_es_sel_9), + .up_es_enb (up_es_enb_9), + .up_es_addr (up_es_addr_9), + .up_es_wr (up_es_wr_9), + .up_es_wdata (up_es_wdata_9), + .up_es_rdata (up_es_rdata_9), + .up_es_ready (up_es_ready_9), + .up_rx_pll_locked (up_rx_pll_locked_9), + .up_rx_rst (up_rx_rst_9), + .up_rx_user_ready (up_rx_user_ready_9), + .up_rx_rst_done (up_rx_rst_done_9), + .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_9), + .up_rx_rate (up_rx_rate_9), + .up_rx_sys_clk_sel (up_rx_sys_clk_sel_9), + .up_rx_out_clk_sel (up_rx_out_clk_sel_9), + .up_rx_sel (up_rx_sel_9), + .up_rx_enb (up_rx_enb_9), + .up_rx_addr (up_rx_addr_9), + .up_rx_wr (up_rx_wr_9), + .up_rx_wdata (up_rx_wdata_9), + .up_rx_rdata (up_rx_rdata_9), + .up_rx_ready (up_rx_ready_9), + .up_tx_pll_locked (up_tx_pll_locked_9), + .up_tx_rst (up_tx_rst_9), + .up_tx_user_ready (up_tx_user_ready_9), + .up_tx_rst_done (up_tx_rst_done_9), + .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_9), + .up_tx_rate (up_tx_rate_9), + .up_tx_sys_clk_sel (up_tx_sys_clk_sel_9), + .up_tx_out_clk_sel (up_tx_out_clk_sel_9), + .up_tx_sel (up_tx_sel_9), + .up_tx_enb (up_tx_enb_9), + .up_tx_addr (up_tx_addr_9), + .up_tx_wr (up_tx_wr_9), + .up_tx_wdata (up_tx_wdata_9), + .up_tx_rdata (up_tx_rdata_9), + .up_tx_ready (up_tx_ready_9)); + end else begin + assign rx_out_clk_9 = 1'd0; + assign rx_charisk_9 = 4'd0; + assign rx_disperr_9 = 4'd0; + assign rx_notintable_9 = 4'd0; + assign rx_data_9 = 32'd0; + assign tx_9_p = 1'd0; + assign tx_9_n = 1'd0; + assign tx_out_clk_9 = 1'd0; + assign up_es_rdata_9 = 16'd0; + assign up_es_ready_9 = 1'd0; + assign up_rx_pll_locked_9 = 1'd0; + assign up_rx_rst_done_9 = 1'd0; + assign up_rx_rdata_9 = 16'd0; + assign up_rx_ready_9 = 1'd0; + assign up_tx_pll_locked_9 = 1'd0; + assign up_tx_rst_done_9 = 1'd0; + assign up_tx_rdata_9 = 16'd0; + assign up_tx_ready_9 = 1'd0; + end + endgenerate + + + generate + if (NUM_OF_LANES >= 11) begin + util_adxcvr_xch #( + .XCVR_ID (10), + .XCVR_TYPE (XCVR_TYPE), + .CPLL_FBDIV (CPLL_FBDIV), + .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5), + .TX_OUT_DIV (TX_OUT_DIV), + .TX_CLK25_DIV (TX_CLK25_DIV), + .RX_OUT_DIV (RX_OUT_DIV), + .RX_CLK25_DIV (RX_CLK25_DIV), + .RX_DFE_LPM_CFG (RX_DFE_LPM_CFG), + .RX_PMA_CFG (RX_PMA_CFG), + .RX_CDR_CFG (RX_CDR_CFG)) + i_xch_10 ( + .qpll2ch_clk (qpll2ch_clk_8), + .qpll2ch_ref_clk (qpll2ch_ref_clk_8), + .qpll2ch_locked (qpll2ch_locked_8), + .cpll_ref_clk (cpll_ref_clk_10), + .up_cpll_rst (up_cpll_rst_10), + .rx_p (rx_10_p), + .rx_n (rx_10_n), + .rx_out_clk (rx_out_clk_10), + .rx_clk (rx_clk_10), + .rx_charisk (rx_charisk_10), + .rx_disperr (rx_disperr_10), + .rx_notintable (rx_notintable_10), + .rx_data (rx_data_10), + .rx_calign (rx_calign_10), + .tx_p (tx_10_p), + .tx_n (tx_10_n), + .tx_out_clk (tx_out_clk_10), + .tx_clk (tx_clk_10), + .tx_charisk (tx_charisk_10), + .tx_data (tx_data_10), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_es_sel (up_es_sel_10), + .up_es_enb (up_es_enb_10), + .up_es_addr (up_es_addr_10), + .up_es_wr (up_es_wr_10), + .up_es_wdata (up_es_wdata_10), + .up_es_rdata (up_es_rdata_10), + .up_es_ready (up_es_ready_10), + .up_rx_pll_locked (up_rx_pll_locked_10), + .up_rx_rst (up_rx_rst_10), + .up_rx_user_ready (up_rx_user_ready_10), + .up_rx_rst_done (up_rx_rst_done_10), + .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_10), + .up_rx_rate (up_rx_rate_10), + .up_rx_sys_clk_sel (up_rx_sys_clk_sel_10), + .up_rx_out_clk_sel (up_rx_out_clk_sel_10), + .up_rx_sel (up_rx_sel_10), + .up_rx_enb (up_rx_enb_10), + .up_rx_addr (up_rx_addr_10), + .up_rx_wr (up_rx_wr_10), + .up_rx_wdata (up_rx_wdata_10), + .up_rx_rdata (up_rx_rdata_10), + .up_rx_ready (up_rx_ready_10), + .up_tx_pll_locked (up_tx_pll_locked_10), + .up_tx_rst (up_tx_rst_10), + .up_tx_user_ready (up_tx_user_ready_10), + .up_tx_rst_done (up_tx_rst_done_10), + .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_10), + .up_tx_rate (up_tx_rate_10), + .up_tx_sys_clk_sel (up_tx_sys_clk_sel_10), + .up_tx_out_clk_sel (up_tx_out_clk_sel_10), + .up_tx_sel (up_tx_sel_10), + .up_tx_enb (up_tx_enb_10), + .up_tx_addr (up_tx_addr_10), + .up_tx_wr (up_tx_wr_10), + .up_tx_wdata (up_tx_wdata_10), + .up_tx_rdata (up_tx_rdata_10), + .up_tx_ready (up_tx_ready_10)); + end else begin + assign rx_out_clk_10 = 1'd0; + assign rx_charisk_10 = 4'd0; + assign rx_disperr_10 = 4'd0; + assign rx_notintable_10 = 4'd0; + assign rx_data_10 = 32'd0; + assign tx_10_p = 1'd0; + assign tx_10_n = 1'd0; + assign tx_out_clk_10 = 1'd0; + assign up_es_rdata_10 = 16'd0; + assign up_es_ready_10 = 1'd0; + assign up_rx_pll_locked_10 = 1'd0; + assign up_rx_rst_done_10 = 1'd0; + assign up_rx_rdata_10 = 16'd0; + assign up_rx_ready_10 = 1'd0; + assign up_tx_pll_locked_10 = 1'd0; + assign up_tx_rst_done_10 = 1'd0; + assign up_tx_rdata_10 = 16'd0; + assign up_tx_ready_10 = 1'd0; + end + endgenerate + + + generate + if (NUM_OF_LANES >= 12) begin + util_adxcvr_xch #( + .XCVR_ID (11), + .XCVR_TYPE (XCVR_TYPE), + .CPLL_FBDIV (CPLL_FBDIV), + .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5), + .TX_OUT_DIV (TX_OUT_DIV), + .TX_CLK25_DIV (TX_CLK25_DIV), + .RX_OUT_DIV (RX_OUT_DIV), + .RX_CLK25_DIV (RX_CLK25_DIV), + .RX_DFE_LPM_CFG (RX_DFE_LPM_CFG), + .RX_PMA_CFG (RX_PMA_CFG), + .RX_CDR_CFG (RX_CDR_CFG)) + i_xch_11 ( + .qpll2ch_clk (qpll2ch_clk_8), + .qpll2ch_ref_clk (qpll2ch_ref_clk_8), + .qpll2ch_locked (qpll2ch_locked_8), + .cpll_ref_clk (cpll_ref_clk_11), + .up_cpll_rst (up_cpll_rst_11), + .rx_p (rx_11_p), + .rx_n (rx_11_n), + .rx_out_clk (rx_out_clk_11), + .rx_clk (rx_clk_11), + .rx_charisk (rx_charisk_11), + .rx_disperr (rx_disperr_11), + .rx_notintable (rx_notintable_11), + .rx_data (rx_data_11), + .rx_calign (rx_calign_11), + .tx_p (tx_11_p), + .tx_n (tx_11_n), + .tx_out_clk (tx_out_clk_11), + .tx_clk (tx_clk_11), + .tx_charisk (tx_charisk_11), + .tx_data (tx_data_11), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_es_sel (up_es_sel_11), + .up_es_enb (up_es_enb_11), + .up_es_addr (up_es_addr_11), + .up_es_wr (up_es_wr_11), + .up_es_wdata (up_es_wdata_11), + .up_es_rdata (up_es_rdata_11), + .up_es_ready (up_es_ready_11), + .up_rx_pll_locked (up_rx_pll_locked_11), + .up_rx_rst (up_rx_rst_11), + .up_rx_user_ready (up_rx_user_ready_11), + .up_rx_rst_done (up_rx_rst_done_11), + .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_11), + .up_rx_rate (up_rx_rate_11), + .up_rx_sys_clk_sel (up_rx_sys_clk_sel_11), + .up_rx_out_clk_sel (up_rx_out_clk_sel_11), + .up_rx_sel (up_rx_sel_11), + .up_rx_enb (up_rx_enb_11), + .up_rx_addr (up_rx_addr_11), + .up_rx_wr (up_rx_wr_11), + .up_rx_wdata (up_rx_wdata_11), + .up_rx_rdata (up_rx_rdata_11), + .up_rx_ready (up_rx_ready_11), + .up_tx_pll_locked (up_tx_pll_locked_11), + .up_tx_rst (up_tx_rst_11), + .up_tx_user_ready (up_tx_user_ready_11), + .up_tx_rst_done (up_tx_rst_done_11), + .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_11), + .up_tx_rate (up_tx_rate_11), + .up_tx_sys_clk_sel (up_tx_sys_clk_sel_11), + .up_tx_out_clk_sel (up_tx_out_clk_sel_11), + .up_tx_sel (up_tx_sel_11), + .up_tx_enb (up_tx_enb_11), + .up_tx_addr (up_tx_addr_11), + .up_tx_wr (up_tx_wr_11), + .up_tx_wdata (up_tx_wdata_11), + .up_tx_rdata (up_tx_rdata_11), + .up_tx_ready (up_tx_ready_11)); + end else begin + assign rx_out_clk_11 = 1'd0; + assign rx_charisk_11 = 4'd0; + assign rx_disperr_11 = 4'd0; + assign rx_notintable_11 = 4'd0; + assign rx_data_11 = 32'd0; + assign tx_11_p = 1'd0; + assign tx_11_n = 1'd0; + assign tx_out_clk_11 = 1'd0; + assign up_es_rdata_11 = 16'd0; + assign up_es_ready_11 = 1'd0; + assign up_rx_pll_locked_11 = 1'd0; + assign up_rx_rst_done_11 = 1'd0; + assign up_rx_rdata_11 = 16'd0; + assign up_rx_ready_11 = 1'd0; + assign up_tx_pll_locked_11 = 1'd0; + assign up_tx_rst_done_11 = 1'd0; + assign up_tx_rdata_11 = 16'd0; + assign up_tx_ready_11 = 1'd0; + end + endgenerate + + generate + if (NUM_OF_LANES >= 13) begin + util_adxcvr_xcm #( + .XCVR_ID (12), + .XCVR_TYPE (XCVR_TYPE), + .QPLL_REFCLK_DIV (QPLL_REFCLK_DIV), + .QPLL_FBDIV_RATIO (QPLL_FBDIV_RATIO), + .QPLL_CFG (QPLL_CFG), + .QPLL_FBDIV (QPLL_FBDIV)) + i_xcm_12 ( + .qpll_ref_clk (qpll_ref_clk_12), + .qpll2ch_clk (qpll2ch_clk_12), + .qpll2ch_ref_clk (qpll2ch_ref_clk_12), + .qpll2ch_locked (qpll2ch_locked_12), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_qpll_rst (up_qpll_rst_12), + .up_cm_sel (up_cm_sel_12), + .up_cm_enb (up_cm_enb_12), + .up_cm_addr (up_cm_addr_12), + .up_cm_wr (up_cm_wr_12), + .up_cm_wdata (up_cm_wdata_12), + .up_cm_rdata (up_cm_rdata_12), + .up_cm_ready (up_cm_ready_12)); + end else begin + assign qpll2ch_clk_12 = 1'd0; + assign qpll2ch_ref_clk_12 = 1'd0; + assign qpll2ch_locked_12 = 1'd0; + assign up_cm_rdata_12 = 16'd0; + assign up_cm_ready_12 = 1'd0; + end + endgenerate + + generate + if (NUM_OF_LANES >= 13) begin + util_adxcvr_xch #( + .XCVR_ID (12), + .XCVR_TYPE (XCVR_TYPE), + .CPLL_FBDIV (CPLL_FBDIV), + .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5), + .TX_OUT_DIV (TX_OUT_DIV), + .TX_CLK25_DIV (TX_CLK25_DIV), + .RX_OUT_DIV (RX_OUT_DIV), + .RX_CLK25_DIV (RX_CLK25_DIV), + .RX_DFE_LPM_CFG (RX_DFE_LPM_CFG), + .RX_PMA_CFG (RX_PMA_CFG), + .RX_CDR_CFG (RX_CDR_CFG)) + i_xch_12 ( + .qpll2ch_clk (qpll2ch_clk_12), + .qpll2ch_ref_clk (qpll2ch_ref_clk_12), + .qpll2ch_locked (qpll2ch_locked_12), + .cpll_ref_clk (cpll_ref_clk_12), + .up_cpll_rst (up_cpll_rst_12), + .rx_p (rx_12_p), + .rx_n (rx_12_n), + .rx_out_clk (rx_out_clk_12), + .rx_clk (rx_clk_12), + .rx_charisk (rx_charisk_12), + .rx_disperr (rx_disperr_12), + .rx_notintable (rx_notintable_12), + .rx_data (rx_data_12), + .rx_calign (rx_calign_12), + .tx_p (tx_12_p), + .tx_n (tx_12_n), + .tx_out_clk (tx_out_clk_12), + .tx_clk (tx_clk_12), + .tx_charisk (tx_charisk_12), + .tx_data (tx_data_12), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_es_sel (up_es_sel_12), + .up_es_enb (up_es_enb_12), + .up_es_addr (up_es_addr_12), + .up_es_wr (up_es_wr_12), + .up_es_wdata (up_es_wdata_12), + .up_es_rdata (up_es_rdata_12), + .up_es_ready (up_es_ready_12), + .up_rx_pll_locked (up_rx_pll_locked_12), + .up_rx_rst (up_rx_rst_12), + .up_rx_user_ready (up_rx_user_ready_12), + .up_rx_rst_done (up_rx_rst_done_12), + .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_12), + .up_rx_rate (up_rx_rate_12), + .up_rx_sys_clk_sel (up_rx_sys_clk_sel_12), + .up_rx_out_clk_sel (up_rx_out_clk_sel_12), + .up_rx_sel (up_rx_sel_12), + .up_rx_enb (up_rx_enb_12), + .up_rx_addr (up_rx_addr_12), + .up_rx_wr (up_rx_wr_12), + .up_rx_wdata (up_rx_wdata_12), + .up_rx_rdata (up_rx_rdata_12), + .up_rx_ready (up_rx_ready_12), + .up_tx_pll_locked (up_tx_pll_locked_12), + .up_tx_rst (up_tx_rst_12), + .up_tx_user_ready (up_tx_user_ready_12), + .up_tx_rst_done (up_tx_rst_done_12), + .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_12), + .up_tx_rate (up_tx_rate_12), + .up_tx_sys_clk_sel (up_tx_sys_clk_sel_12), + .up_tx_out_clk_sel (up_tx_out_clk_sel_12), + .up_tx_sel (up_tx_sel_12), + .up_tx_enb (up_tx_enb_12), + .up_tx_addr (up_tx_addr_12), + .up_tx_wr (up_tx_wr_12), + .up_tx_wdata (up_tx_wdata_12), + .up_tx_rdata (up_tx_rdata_12), + .up_tx_ready (up_tx_ready_12)); + end else begin + assign rx_out_clk_12 = 1'd0; + assign rx_charisk_12 = 4'd0; + assign rx_disperr_12 = 4'd0; + assign rx_notintable_12 = 4'd0; + assign rx_data_12 = 32'd0; + assign tx_12_p = 1'd0; + assign tx_12_n = 1'd0; + assign tx_out_clk_12 = 1'd0; + assign up_es_rdata_12 = 16'd0; + assign up_es_ready_12 = 1'd0; + assign up_rx_pll_locked_12 = 1'd0; + assign up_rx_rst_done_12 = 1'd0; + assign up_rx_rdata_12 = 16'd0; + assign up_rx_ready_12 = 1'd0; + assign up_tx_pll_locked_12 = 1'd0; + assign up_tx_rst_done_12 = 1'd0; + assign up_tx_rdata_12 = 16'd0; + assign up_tx_ready_12 = 1'd0; + end + endgenerate + + + generate + if (NUM_OF_LANES >= 14) begin + util_adxcvr_xch #( + .XCVR_ID (13), + .XCVR_TYPE (XCVR_TYPE), + .CPLL_FBDIV (CPLL_FBDIV), + .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5), + .TX_OUT_DIV (TX_OUT_DIV), + .TX_CLK25_DIV (TX_CLK25_DIV), + .RX_OUT_DIV (RX_OUT_DIV), + .RX_CLK25_DIV (RX_CLK25_DIV), + .RX_DFE_LPM_CFG (RX_DFE_LPM_CFG), + .RX_PMA_CFG (RX_PMA_CFG), + .RX_CDR_CFG (RX_CDR_CFG)) + i_xch_13 ( + .qpll2ch_clk (qpll2ch_clk_12), + .qpll2ch_ref_clk (qpll2ch_ref_clk_12), + .qpll2ch_locked (qpll2ch_locked_12), + .cpll_ref_clk (cpll_ref_clk_13), + .up_cpll_rst (up_cpll_rst_13), + .rx_p (rx_13_p), + .rx_n (rx_13_n), + .rx_out_clk (rx_out_clk_13), + .rx_clk (rx_clk_13), + .rx_charisk (rx_charisk_13), + .rx_disperr (rx_disperr_13), + .rx_notintable (rx_notintable_13), + .rx_data (rx_data_13), + .rx_calign (rx_calign_13), + .tx_p (tx_13_p), + .tx_n (tx_13_n), + .tx_out_clk (tx_out_clk_13), + .tx_clk (tx_clk_13), + .tx_charisk (tx_charisk_13), + .tx_data (tx_data_13), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_es_sel (up_es_sel_13), + .up_es_enb (up_es_enb_13), + .up_es_addr (up_es_addr_13), + .up_es_wr (up_es_wr_13), + .up_es_wdata (up_es_wdata_13), + .up_es_rdata (up_es_rdata_13), + .up_es_ready (up_es_ready_13), + .up_rx_pll_locked (up_rx_pll_locked_13), + .up_rx_rst (up_rx_rst_13), + .up_rx_user_ready (up_rx_user_ready_13), + .up_rx_rst_done (up_rx_rst_done_13), + .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_13), + .up_rx_rate (up_rx_rate_13), + .up_rx_sys_clk_sel (up_rx_sys_clk_sel_13), + .up_rx_out_clk_sel (up_rx_out_clk_sel_13), + .up_rx_sel (up_rx_sel_13), + .up_rx_enb (up_rx_enb_13), + .up_rx_addr (up_rx_addr_13), + .up_rx_wr (up_rx_wr_13), + .up_rx_wdata (up_rx_wdata_13), + .up_rx_rdata (up_rx_rdata_13), + .up_rx_ready (up_rx_ready_13), + .up_tx_pll_locked (up_tx_pll_locked_13), + .up_tx_rst (up_tx_rst_13), + .up_tx_user_ready (up_tx_user_ready_13), + .up_tx_rst_done (up_tx_rst_done_13), + .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_13), + .up_tx_rate (up_tx_rate_13), + .up_tx_sys_clk_sel (up_tx_sys_clk_sel_13), + .up_tx_out_clk_sel (up_tx_out_clk_sel_13), + .up_tx_sel (up_tx_sel_13), + .up_tx_enb (up_tx_enb_13), + .up_tx_addr (up_tx_addr_13), + .up_tx_wr (up_tx_wr_13), + .up_tx_wdata (up_tx_wdata_13), + .up_tx_rdata (up_tx_rdata_13), + .up_tx_ready (up_tx_ready_13)); + end else begin + assign rx_out_clk_13 = 1'd0; + assign rx_charisk_13 = 4'd0; + assign rx_disperr_13 = 4'd0; + assign rx_notintable_13 = 4'd0; + assign rx_data_13 = 32'd0; + assign tx_13_p = 1'd0; + assign tx_13_n = 1'd0; + assign tx_out_clk_13 = 1'd0; + assign up_es_rdata_13 = 16'd0; + assign up_es_ready_13 = 1'd0; + assign up_rx_pll_locked_13 = 1'd0; + assign up_rx_rst_done_13 = 1'd0; + assign up_rx_rdata_13 = 16'd0; + assign up_rx_ready_13 = 1'd0; + assign up_tx_pll_locked_13 = 1'd0; + assign up_tx_rst_done_13 = 1'd0; + assign up_tx_rdata_13 = 16'd0; + assign up_tx_ready_13 = 1'd0; + end + endgenerate + + + generate + if (NUM_OF_LANES >= 15) begin + util_adxcvr_xch #( + .XCVR_ID (14), + .XCVR_TYPE (XCVR_TYPE), + .CPLL_FBDIV (CPLL_FBDIV), + .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5), + .TX_OUT_DIV (TX_OUT_DIV), + .TX_CLK25_DIV (TX_CLK25_DIV), + .RX_OUT_DIV (RX_OUT_DIV), + .RX_CLK25_DIV (RX_CLK25_DIV), + .RX_DFE_LPM_CFG (RX_DFE_LPM_CFG), + .RX_PMA_CFG (RX_PMA_CFG), + .RX_CDR_CFG (RX_CDR_CFG)) + i_xch_14 ( + .qpll2ch_clk (qpll2ch_clk_12), + .qpll2ch_ref_clk (qpll2ch_ref_clk_12), + .qpll2ch_locked (qpll2ch_locked_12), + .cpll_ref_clk (cpll_ref_clk_14), + .up_cpll_rst (up_cpll_rst_14), + .rx_p (rx_14_p), + .rx_n (rx_14_n), + .rx_out_clk (rx_out_clk_14), + .rx_clk (rx_clk_14), + .rx_charisk (rx_charisk_14), + .rx_disperr (rx_disperr_14), + .rx_notintable (rx_notintable_14), + .rx_data (rx_data_14), + .rx_calign (rx_calign_14), + .tx_p (tx_14_p), + .tx_n (tx_14_n), + .tx_out_clk (tx_out_clk_14), + .tx_clk (tx_clk_14), + .tx_charisk (tx_charisk_14), + .tx_data (tx_data_14), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_es_sel (up_es_sel_14), + .up_es_enb (up_es_enb_14), + .up_es_addr (up_es_addr_14), + .up_es_wr (up_es_wr_14), + .up_es_wdata (up_es_wdata_14), + .up_es_rdata (up_es_rdata_14), + .up_es_ready (up_es_ready_14), + .up_rx_pll_locked (up_rx_pll_locked_14), + .up_rx_rst (up_rx_rst_14), + .up_rx_user_ready (up_rx_user_ready_14), + .up_rx_rst_done (up_rx_rst_done_14), + .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_14), + .up_rx_rate (up_rx_rate_14), + .up_rx_sys_clk_sel (up_rx_sys_clk_sel_14), + .up_rx_out_clk_sel (up_rx_out_clk_sel_14), + .up_rx_sel (up_rx_sel_14), + .up_rx_enb (up_rx_enb_14), + .up_rx_addr (up_rx_addr_14), + .up_rx_wr (up_rx_wr_14), + .up_rx_wdata (up_rx_wdata_14), + .up_rx_rdata (up_rx_rdata_14), + .up_rx_ready (up_rx_ready_14), + .up_tx_pll_locked (up_tx_pll_locked_14), + .up_tx_rst (up_tx_rst_14), + .up_tx_user_ready (up_tx_user_ready_14), + .up_tx_rst_done (up_tx_rst_done_14), + .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_14), + .up_tx_rate (up_tx_rate_14), + .up_tx_sys_clk_sel (up_tx_sys_clk_sel_14), + .up_tx_out_clk_sel (up_tx_out_clk_sel_14), + .up_tx_sel (up_tx_sel_14), + .up_tx_enb (up_tx_enb_14), + .up_tx_addr (up_tx_addr_14), + .up_tx_wr (up_tx_wr_14), + .up_tx_wdata (up_tx_wdata_14), + .up_tx_rdata (up_tx_rdata_14), + .up_tx_ready (up_tx_ready_14)); + end else begin + assign rx_out_clk_14 = 1'd0; + assign rx_charisk_14 = 4'd0; + assign rx_disperr_14 = 4'd0; + assign rx_notintable_14 = 4'd0; + assign rx_data_14 = 32'd0; + assign tx_14_p = 1'd0; + assign tx_14_n = 1'd0; + assign tx_out_clk_14 = 1'd0; + assign up_es_rdata_14 = 16'd0; + assign up_es_ready_14 = 1'd0; + assign up_rx_pll_locked_14 = 1'd0; + assign up_rx_rst_done_14 = 1'd0; + assign up_rx_rdata_14 = 16'd0; + assign up_rx_ready_14 = 1'd0; + assign up_tx_pll_locked_14 = 1'd0; + assign up_tx_rst_done_14 = 1'd0; + assign up_tx_rdata_14 = 16'd0; + assign up_tx_ready_14 = 1'd0; + end + endgenerate + + + generate + if (NUM_OF_LANES >= 16) begin + util_adxcvr_xch #( + .XCVR_ID (15), + .XCVR_TYPE (XCVR_TYPE), + .CPLL_FBDIV (CPLL_FBDIV), + .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5), + .TX_OUT_DIV (TX_OUT_DIV), + .TX_CLK25_DIV (TX_CLK25_DIV), + .RX_OUT_DIV (RX_OUT_DIV), + .RX_CLK25_DIV (RX_CLK25_DIV), + .RX_DFE_LPM_CFG (RX_DFE_LPM_CFG), + .RX_PMA_CFG (RX_PMA_CFG), + .RX_CDR_CFG (RX_CDR_CFG)) + i_xch_15 ( + .qpll2ch_clk (qpll2ch_clk_12), + .qpll2ch_ref_clk (qpll2ch_ref_clk_12), + .qpll2ch_locked (qpll2ch_locked_12), + .cpll_ref_clk (cpll_ref_clk_15), + .up_cpll_rst (up_cpll_rst_15), + .rx_p (rx_15_p), + .rx_n (rx_15_n), + .rx_out_clk (rx_out_clk_15), + .rx_clk (rx_clk_15), + .rx_charisk (rx_charisk_15), + .rx_disperr (rx_disperr_15), + .rx_notintable (rx_notintable_15), + .rx_data (rx_data_15), + .rx_calign (rx_calign_15), + .tx_p (tx_15_p), + .tx_n (tx_15_n), + .tx_out_clk (tx_out_clk_15), + .tx_clk (tx_clk_15), + .tx_charisk (tx_charisk_15), + .tx_data (tx_data_15), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_es_sel (up_es_sel_15), + .up_es_enb (up_es_enb_15), + .up_es_addr (up_es_addr_15), + .up_es_wr (up_es_wr_15), + .up_es_wdata (up_es_wdata_15), + .up_es_rdata (up_es_rdata_15), + .up_es_ready (up_es_ready_15), + .up_rx_pll_locked (up_rx_pll_locked_15), + .up_rx_rst (up_rx_rst_15), + .up_rx_user_ready (up_rx_user_ready_15), + .up_rx_rst_done (up_rx_rst_done_15), + .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_15), + .up_rx_rate (up_rx_rate_15), + .up_rx_sys_clk_sel (up_rx_sys_clk_sel_15), + .up_rx_out_clk_sel (up_rx_out_clk_sel_15), + .up_rx_sel (up_rx_sel_15), + .up_rx_enb (up_rx_enb_15), + .up_rx_addr (up_rx_addr_15), + .up_rx_wr (up_rx_wr_15), + .up_rx_wdata (up_rx_wdata_15), + .up_rx_rdata (up_rx_rdata_15), + .up_rx_ready (up_rx_ready_15), + .up_tx_pll_locked (up_tx_pll_locked_15), + .up_tx_rst (up_tx_rst_15), + .up_tx_user_ready (up_tx_user_ready_15), + .up_tx_rst_done (up_tx_rst_done_15), + .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_15), + .up_tx_rate (up_tx_rate_15), + .up_tx_sys_clk_sel (up_tx_sys_clk_sel_15), + .up_tx_out_clk_sel (up_tx_out_clk_sel_15), + .up_tx_sel (up_tx_sel_15), + .up_tx_enb (up_tx_enb_15), + .up_tx_addr (up_tx_addr_15), + .up_tx_wr (up_tx_wr_15), + .up_tx_wdata (up_tx_wdata_15), + .up_tx_rdata (up_tx_rdata_15), + .up_tx_ready (up_tx_ready_15)); + end else begin + assign rx_out_clk_15 = 1'd0; + assign rx_charisk_15 = 4'd0; + assign rx_disperr_15 = 4'd0; + assign rx_notintable_15 = 4'd0; + assign rx_data_15 = 32'd0; + assign tx_15_p = 1'd0; + assign tx_15_n = 1'd0; + assign tx_out_clk_15 = 1'd0; + assign up_es_rdata_15 = 16'd0; + assign up_es_ready_15 = 1'd0; + assign up_rx_pll_locked_15 = 1'd0; + assign up_rx_rst_done_15 = 1'd0; + assign up_rx_rdata_15 = 16'd0; + assign up_rx_ready_15 = 1'd0; + assign up_tx_pll_locked_15 = 1'd0; + assign up_tx_rst_done_15 = 1'd0; + assign up_tx_rdata_15 = 16'd0; + assign up_tx_ready_15 = 1'd0; + end + endgenerate + +endmodule + +// *************************************************************************** +// *************************************************************************** + diff --git a/library/xilinx/util_adxcvr/util_adxcvr_constr.xdc b/library/xilinx/util_adxcvr/util_adxcvr_constr.xdc new file mode 100644 index 000000000..92336c93a --- /dev/null +++ b/library/xilinx/util_adxcvr/util_adxcvr_constr.xdc @@ -0,0 +1,11 @@ + +set_property shreg_extract no [get_cells -hier -filter {name =~ *up_rx_rst_done*}] +set_property shreg_extract no [get_cells -hier -filter {name =~ *up_tx_rst_done*}] +set_property shreg_extract no [get_cells -hier -filter {name =~ *rx_rate*}] +set_property shreg_extract no [get_cells -hier -filter {name =~ *tx_rate*}] + +set_false_path -to [get_cells -hier -filter {name =~ *up_rx_rst_done_m1_reg && IS_SEQUENTIAL}] +set_false_path -to [get_cells -hier -filter {name =~ *up_tx_rst_done_m1_reg && IS_SEQUENTIAL}] +set_false_path -to [get_cells -hier -filter {name =~ *rx_rate_m1_reg* && IS_SEQUENTIAL}] +set_false_path -to [get_cells -hier -filter {name =~ *tx_rate_m1_reg* && IS_SEQUENTIAL}] + diff --git a/library/xilinx/util_adxcvr/util_adxcvr_ip.tcl b/library/xilinx/util_adxcvr/util_adxcvr_ip.tcl new file mode 100644 index 000000000..b7f5c03f2 --- /dev/null +++ b/library/xilinx/util_adxcvr/util_adxcvr_ip.tcl @@ -0,0 +1,587 @@ +## AUTO GENERATED BY util_adxcvr.pl, DO NOT MODIFY! + +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip.tcl + +adi_ip_create util_adxcvr +adi_ip_files util_adxcvr [list \ + "util_adxcvr_constr.xdc" \ + "util_adxcvr_xcm.v" \ + "util_adxcvr_xch.v" \ + "util_adxcvr.v" ] + +adi_ip_properties_lite util_adxcvr +adi_ip_constraints util_adxcvr "util_adxcvr_constr.xdc" + +ipx::remove_all_bus_interface [ipx::current_core] + +set_property driver_value 0 [ipx::get_ports -filter "direction==in" -of_objects [ipx::current_core]] + +for {set n 0} {$n < 16} {incr n} { + + if {($n%4) == 0} { + adi_if_infer_bus ADI:user:if_xcvr_cm slave up_cm_${n} [list \ + "sel up_cm_sel_${n} "\ + "enb up_cm_enb_${n} "\ + "addr up_cm_addr_${n} "\ + "wr up_cm_wr_${n} "\ + "wdata up_cm_wdata_${n} "\ + "rdata up_cm_rdata_${n} "\ + "ready up_cm_ready_${n} "] + } + + adi_if_infer_bus ADI:user:if_xcvr_cm slave up_es_${n} [list \ + "sel up_es_sel_${n} "\ + "enb up_es_enb_${n} "\ + "addr up_es_addr_${n} "\ + "wr up_es_wr_${n} "\ + "wdata up_es_wdata_${n} "\ + "rdata up_es_rdata_${n} "\ + "ready up_es_ready_${n} "] + + adi_if_infer_bus ADI:user:if_xcvr_ch slave up_rx_${n} [list \ + "pll_locked up_rx_pll_locked_${n} "\ + "rst up_rx_rst_${n} "\ + "user_ready up_rx_user_ready_${n} "\ + "rst_done up_rx_rst_done_${n} "\ + "lpm_dfe_n up_rx_lpm_dfe_n_${n} "\ + "rate up_rx_rate_${n} "\ + "sys_clk_sel up_rx_sys_clk_sel_${n} "\ + "out_clk_sel up_rx_out_clk_sel_${n} "\ + "sel up_rx_sel_${n} "\ + "enb up_rx_enb_${n} "\ + "addr up_rx_addr_${n} "\ + "wr up_rx_wr_${n} "\ + "wdata up_rx_wdata_${n} "\ + "rdata up_rx_rdata_${n} "\ + "ready up_rx_ready_${n} "] + + adi_if_infer_bus ADI:user:if_xcvr_ch slave up_tx_${n} [list \ + "pll_locked up_tx_pll_locked_${n} "\ + "rst up_tx_rst_${n} "\ + "user_ready up_tx_user_ready_${n} "\ + "rst_done up_tx_rst_done_${n} "\ + "lpm_dfe_n up_tx_lpm_dfe_n_${n} "\ + "rate up_tx_rate_${n} "\ + "sys_clk_sel up_tx_sys_clk_sel_${n} "\ + "out_clk_sel up_tx_out_clk_sel_${n} "\ + "sel up_tx_sel_${n} "\ + "enb up_tx_enb_${n} "\ + "addr up_tx_addr_${n} "\ + "wr up_tx_wr_${n} "\ + "wdata up_tx_wdata_${n} "\ + "rdata up_tx_rdata_${n} "\ + "ready up_tx_ready_${n} "] + + ipx::add_bus_interface rx_${n} [ipx::current_core] + set_property abstraction_type_vlnv xilinx.com:display_jesd204:jesd204_rx_bus_rtl:1.0 \ + [ipx::get_bus_interfaces rx_${n} -of_objects [ipx::current_core]] + set_property bus_type_vlnv xilinx.com:display_jesd204:jesd204_rx_bus:1.0 \ + [ipx::get_bus_interfaces rx_${n} -of_objects [ipx::current_core]] + set_property interface_mode master [ipx::get_bus_interfaces rx_${n} -of_objects [ipx::current_core]] + ipx::add_port_map rxcharisk [ipx::get_bus_interfaces rx_${n} -of_objects [ipx::current_core]] + set_property physical_name rx_charisk_${n} [ipx::get_port_maps rxcharisk -of_objects \ + [ipx::get_bus_interfaces rx_${n} -of_objects [ipx::current_core]]] + ipx::add_port_map rxnotintable [ipx::get_bus_interfaces rx_${n} -of_objects [ipx::current_core]] + set_property physical_name rx_notintable_${n} [ipx::get_port_maps rxnotintable -of_objects \ + [ipx::get_bus_interfaces rx_${n} -of_objects [ipx::current_core]]] + ipx::add_port_map rxdisperr [ipx::get_bus_interfaces rx_${n} -of_objects [ipx::current_core]] + set_property physical_name rx_disperr_${n} [ipx::get_port_maps rxdisperr -of_objects \ + [ipx::get_bus_interfaces rx_${n} -of_objects [ipx::current_core]]] + ipx::add_port_map rxdata [ipx::get_bus_interfaces rx_${n} -of_objects [ipx::current_core]] + set_property physical_name rx_data_${n} [ipx::get_port_maps rxdata -of_objects \ + [ipx::get_bus_interfaces rx_${n} -of_objects [ipx::current_core]]] + + ipx::add_bus_interface tx_${n} [ipx::current_core] + set_property abstraction_type_vlnv xilinx.com:display_jesd204:jesd204_tx_bus_rtl:1.0 \ + [ipx::get_bus_interfaces tx_${n} -of_objects [ipx::current_core]] + set_property bus_type_vlnv xilinx.com:display_jesd204:jesd204_tx_bus:1.0 \ + [ipx::get_bus_interfaces tx_${n} -of_objects [ipx::current_core]] + set_property interface_mode slave [ipx::get_bus_interfaces tx_${n} -of_objects [ipx::current_core]] + ipx::add_port_map txcharisk [ipx::get_bus_interfaces tx_${n} -of_objects [ipx::current_core]] + set_property physical_name tx_charisk_${n} [ipx::get_port_maps txcharisk -of_objects \ + [ipx::get_bus_interfaces tx_${n} -of_objects [ipx::current_core]]] + ipx::add_port_map txdata [ipx::get_bus_interfaces tx_${n} -of_objects [ipx::current_core]] + set_property physical_name tx_data_${n} [ipx::get_port_maps txdata -of_objects \ + [ipx::get_bus_interfaces tx_${n} -of_objects [ipx::current_core]]] + +} + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 0} \ + [ipx::get_bus_interfaces up_es_0 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 0} \ + [ipx::get_bus_interfaces up_rx_0 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 0} \ + [ipx::get_bus_interfaces rx_0 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 0} \ + [ipx::get_ports rx_*0* -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 0} \ + [ipx::get_bus_interfaces up_tx_0 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 0} \ + [ipx::get_bus_interfaces tx_0 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 0} \ + [ipx::get_ports tx_*0* -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 0) or \ + (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 0)} \ + [ipx::get_ports cpll_ref_clk_0 -of_objects [ipx::current_core]] \ + [ipx::get_ports up_cpll_rst_0 -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 0) or \ + (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 0)} \ + [ipx::get_ports qpll_ref_clk_0 -of_objects [ipx::current_core]] \ + [ipx::get_ports up_qpll_rst_0 -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 0) or \ + (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 0)} \ + [ipx::get_bus_interfaces up_cm_0 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 1} \ + [ipx::get_bus_interfaces up_es_1 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 1} \ + [ipx::get_bus_interfaces up_rx_1 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 1} \ + [ipx::get_bus_interfaces rx_1 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 1} \ + [ipx::get_ports rx_*1* -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 1} \ + [ipx::get_bus_interfaces up_tx_1 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 1} \ + [ipx::get_bus_interfaces tx_1 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 1} \ + [ipx::get_ports tx_*1* -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 1) or \ + (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 1)} \ + [ipx::get_ports cpll_ref_clk_1 -of_objects [ipx::current_core]] \ + [ipx::get_ports up_cpll_rst_1 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 2} \ + [ipx::get_bus_interfaces up_es_2 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 2} \ + [ipx::get_bus_interfaces up_rx_2 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 2} \ + [ipx::get_bus_interfaces rx_2 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 2} \ + [ipx::get_ports rx_*2* -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 2} \ + [ipx::get_bus_interfaces up_tx_2 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 2} \ + [ipx::get_bus_interfaces tx_2 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 2} \ + [ipx::get_ports tx_*2* -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 2) or \ + (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 2)} \ + [ipx::get_ports cpll_ref_clk_2 -of_objects [ipx::current_core]] \ + [ipx::get_ports up_cpll_rst_2 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 3} \ + [ipx::get_bus_interfaces up_es_3 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 3} \ + [ipx::get_bus_interfaces up_rx_3 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 3} \ + [ipx::get_bus_interfaces rx_3 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 3} \ + [ipx::get_ports rx_*3* -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 3} \ + [ipx::get_bus_interfaces up_tx_3 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 3} \ + [ipx::get_bus_interfaces tx_3 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 3} \ + [ipx::get_ports tx_*3* -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 3) or \ + (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 3)} \ + [ipx::get_ports cpll_ref_clk_3 -of_objects [ipx::current_core]] \ + [ipx::get_ports up_cpll_rst_3 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 4} \ + [ipx::get_bus_interfaces up_es_4 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 4} \ + [ipx::get_bus_interfaces up_rx_4 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 4} \ + [ipx::get_bus_interfaces rx_4 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 4} \ + [ipx::get_ports rx_*4* -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 4} \ + [ipx::get_bus_interfaces up_tx_4 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 4} \ + [ipx::get_bus_interfaces tx_4 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 4} \ + [ipx::get_ports tx_*4* -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 4) or \ + (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 4)} \ + [ipx::get_ports cpll_ref_clk_4 -of_objects [ipx::current_core]] \ + [ipx::get_ports up_cpll_rst_4 -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 4) or \ + (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 4)} \ + [ipx::get_ports qpll_ref_clk_4 -of_objects [ipx::current_core]] \ + [ipx::get_ports up_qpll_rst_4 -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 4) or \ + (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 4)} \ + [ipx::get_bus_interfaces up_cm_4 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 5} \ + [ipx::get_bus_interfaces up_es_5 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 5} \ + [ipx::get_bus_interfaces up_rx_5 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 5} \ + [ipx::get_bus_interfaces rx_5 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 5} \ + [ipx::get_ports rx_*5* -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 5} \ + [ipx::get_bus_interfaces up_tx_5 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 5} \ + [ipx::get_bus_interfaces tx_5 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 5} \ + [ipx::get_ports tx_*5* -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 5) or \ + (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 5)} \ + [ipx::get_ports cpll_ref_clk_5 -of_objects [ipx::current_core]] \ + [ipx::get_ports up_cpll_rst_5 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 6} \ + [ipx::get_bus_interfaces up_es_6 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 6} \ + [ipx::get_bus_interfaces up_rx_6 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 6} \ + [ipx::get_bus_interfaces rx_6 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 6} \ + [ipx::get_ports rx_*6* -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 6} \ + [ipx::get_bus_interfaces up_tx_6 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 6} \ + [ipx::get_bus_interfaces tx_6 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 6} \ + [ipx::get_ports tx_*6* -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 6) or \ + (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 6)} \ + [ipx::get_ports cpll_ref_clk_6 -of_objects [ipx::current_core]] \ + [ipx::get_ports up_cpll_rst_6 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 7} \ + [ipx::get_bus_interfaces up_es_7 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 7} \ + [ipx::get_bus_interfaces up_rx_7 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 7} \ + [ipx::get_bus_interfaces rx_7 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 7} \ + [ipx::get_ports rx_*7* -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 7} \ + [ipx::get_bus_interfaces up_tx_7 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 7} \ + [ipx::get_bus_interfaces tx_7 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 7} \ + [ipx::get_ports tx_*7* -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 7) or \ + (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 7)} \ + [ipx::get_ports cpll_ref_clk_7 -of_objects [ipx::current_core]] \ + [ipx::get_ports up_cpll_rst_7 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 8} \ + [ipx::get_bus_interfaces up_es_8 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 8} \ + [ipx::get_bus_interfaces up_rx_8 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 8} \ + [ipx::get_bus_interfaces rx_8 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 8} \ + [ipx::get_ports rx_*8* -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 8} \ + [ipx::get_bus_interfaces up_tx_8 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 8} \ + [ipx::get_bus_interfaces tx_8 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 8} \ + [ipx::get_ports tx_*8* -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 8) or \ + (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 8)} \ + [ipx::get_ports cpll_ref_clk_8 -of_objects [ipx::current_core]] \ + [ipx::get_ports up_cpll_rst_8 -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 8) or \ + (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 8)} \ + [ipx::get_ports qpll_ref_clk_8 -of_objects [ipx::current_core]] \ + [ipx::get_ports up_qpll_rst_8 -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 8) or \ + (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 8)} \ + [ipx::get_bus_interfaces up_cm_8 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 9} \ + [ipx::get_bus_interfaces up_es_9 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 9} \ + [ipx::get_bus_interfaces up_rx_9 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 9} \ + [ipx::get_bus_interfaces rx_9 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 9} \ + [ipx::get_ports rx_*9* -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 9} \ + [ipx::get_bus_interfaces up_tx_9 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 9} \ + [ipx::get_bus_interfaces tx_9 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 9} \ + [ipx::get_ports tx_*9* -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 9) or \ + (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 9)} \ + [ipx::get_ports cpll_ref_clk_9 -of_objects [ipx::current_core]] \ + [ipx::get_ports up_cpll_rst_9 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 10} \ + [ipx::get_bus_interfaces up_es_10 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 10} \ + [ipx::get_bus_interfaces up_rx_10 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 10} \ + [ipx::get_bus_interfaces rx_10 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 10} \ + [ipx::get_ports rx_*10* -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 10} \ + [ipx::get_bus_interfaces up_tx_10 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 10} \ + [ipx::get_bus_interfaces tx_10 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 10} \ + [ipx::get_ports tx_*10* -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 10) or \ + (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 10)} \ + [ipx::get_ports cpll_ref_clk_10 -of_objects [ipx::current_core]] \ + [ipx::get_ports up_cpll_rst_10 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 11} \ + [ipx::get_bus_interfaces up_es_11 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 11} \ + [ipx::get_bus_interfaces up_rx_11 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 11} \ + [ipx::get_bus_interfaces rx_11 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 11} \ + [ipx::get_ports rx_*11* -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 11} \ + [ipx::get_bus_interfaces up_tx_11 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 11} \ + [ipx::get_bus_interfaces tx_11 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 11} \ + [ipx::get_ports tx_*11* -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 11) or \ + (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 11)} \ + [ipx::get_ports cpll_ref_clk_11 -of_objects [ipx::current_core]] \ + [ipx::get_ports up_cpll_rst_11 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 12} \ + [ipx::get_bus_interfaces up_es_12 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 12} \ + [ipx::get_bus_interfaces up_rx_12 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 12} \ + [ipx::get_bus_interfaces rx_12 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 12} \ + [ipx::get_ports rx_*12* -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 12} \ + [ipx::get_bus_interfaces up_tx_12 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 12} \ + [ipx::get_bus_interfaces tx_12 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 12} \ + [ipx::get_ports tx_*12* -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 12) or \ + (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 12)} \ + [ipx::get_ports cpll_ref_clk_12 -of_objects [ipx::current_core]] \ + [ipx::get_ports up_cpll_rst_12 -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 12) or \ + (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 12)} \ + [ipx::get_ports qpll_ref_clk_12 -of_objects [ipx::current_core]] \ + [ipx::get_ports up_qpll_rst_12 -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 12) or \ + (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 12)} \ + [ipx::get_bus_interfaces up_cm_12 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 13} \ + [ipx::get_bus_interfaces up_es_13 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 13} \ + [ipx::get_bus_interfaces up_rx_13 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 13} \ + [ipx::get_bus_interfaces rx_13 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 13} \ + [ipx::get_ports rx_*13* -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 13} \ + [ipx::get_bus_interfaces up_tx_13 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 13} \ + [ipx::get_bus_interfaces tx_13 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 13} \ + [ipx::get_ports tx_*13* -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 13) or \ + (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 13)} \ + [ipx::get_ports cpll_ref_clk_13 -of_objects [ipx::current_core]] \ + [ipx::get_ports up_cpll_rst_13 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 14} \ + [ipx::get_bus_interfaces up_es_14 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 14} \ + [ipx::get_bus_interfaces up_rx_14 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 14} \ + [ipx::get_bus_interfaces rx_14 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 14} \ + [ipx::get_ports rx_*14* -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 14} \ + [ipx::get_bus_interfaces up_tx_14 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 14} \ + [ipx::get_bus_interfaces tx_14 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 14} \ + [ipx::get_ports tx_*14* -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 14) or \ + (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 14)} \ + [ipx::get_ports cpll_ref_clk_14 -of_objects [ipx::current_core]] \ + [ipx::get_ports up_cpll_rst_14 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 15} \ + [ipx::get_bus_interfaces up_es_15 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 15} \ + [ipx::get_bus_interfaces up_rx_15 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 15} \ + [ipx::get_bus_interfaces rx_15 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 15} \ + [ipx::get_ports rx_*15* -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 15} \ + [ipx::get_bus_interfaces up_tx_15 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 15} \ + [ipx::get_bus_interfaces tx_15 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 15} \ + [ipx::get_ports tx_*15* -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 15) or \ + (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 15)} \ + [ipx::get_ports cpll_ref_clk_15 -of_objects [ipx::current_core]] \ + [ipx::get_ports up_cpll_rst_15 -of_objects [ipx::current_core]] + +ipx::save_core [ipx::current_core] + diff --git a/library/xilinx/util_adxcvr/util_adxcvr_xch.v b/library/xilinx/util_adxcvr/util_adxcvr_xch.v new file mode 100644 index 000000000..8c1c50724 --- /dev/null +++ b/library/xilinx/util_adxcvr/util_adxcvr_xch.v @@ -0,0 +1,2398 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/1ps + +module util_adxcvr_xch #( + + // parameters + + parameter integer XCVR_ID = 0, + parameter integer XCVR_TYPE = 0, + + parameter integer CPLL_FBDIV = 2, + parameter integer CPLL_FBDIV_4_5 = 5, + + parameter integer TX_OUT_DIV = 1, + parameter integer TX_CLK25_DIV = 20, + + parameter integer RX_OUT_DIV = 1, + parameter integer RX_CLK25_DIV = 20, + parameter [15:0] RX_DFE_LPM_CFG = 16'h0104, + parameter [31:0] RX_PMA_CFG = 32'h001e7080, + parameter [72:0] RX_CDR_CFG = 72'h0b000023ff10400020) ( + + // pll interface + + input qpll2ch_clk, + input qpll2ch_ref_clk, + input qpll2ch_locked, + input cpll_ref_clk, + input up_cpll_rst, + + // receive + + input rx_p, + input rx_n, + + output rx_out_clk, + input rx_clk, + output [ 3:0] rx_charisk, + output [ 3:0] rx_disperr, + output [ 3:0] rx_notintable, + output [31:0] rx_data, + input rx_calign, + + // transmit + + output tx_p, + output tx_n, + + output tx_out_clk, + input tx_clk, + input [ 3:0] tx_charisk, + input [31:0] tx_data, + + // up interface + + input up_rstn, + input up_clk, + input [ 7:0] up_es_sel, + input up_es_enb, + input [11:0] up_es_addr, + input up_es_wr, + input [15:0] up_es_wdata, + output [15:0] up_es_rdata, + output up_es_ready, + output up_rx_pll_locked, + input up_rx_rst, + input up_rx_user_ready, + output up_rx_rst_done, + input up_rx_lpm_dfe_n, + input [ 2:0] up_rx_rate, + input [ 1:0] up_rx_sys_clk_sel, + input [ 2:0] up_rx_out_clk_sel, + input [ 7:0] up_rx_sel, + input up_rx_enb, + input [11:0] up_rx_addr, + input up_rx_wr, + input [15:0] up_rx_wdata, + output [15:0] up_rx_rdata, + output up_rx_ready, + output up_tx_pll_locked, + input up_tx_rst, + input up_tx_user_ready, + output up_tx_rst_done, + input up_tx_lpm_dfe_n, + input [ 2:0] up_tx_rate, + input [ 1:0] up_tx_sys_clk_sel, + input [ 2:0] up_tx_out_clk_sel, + input [ 7:0] up_tx_sel, + input up_tx_enb, + input [11:0] up_tx_addr, + input up_tx_wr, + input [15:0] up_tx_wdata, + output [15:0] up_tx_rdata, + output up_tx_ready); + + // internal registers + + reg [15:0] up_es_rdata_int = 'd0; + reg up_es_ready_int = 'd0; + reg [15:0] up_rx_rdata_int = 'd0; + reg up_rx_ready_int = 'd0; + reg [15:0] up_tx_rdata_int = 'd0; + reg up_tx_ready_int = 'd0; + reg [ 2:0] up_sel_int = 'd0; + reg up_enb_int = 'd0; + reg [11:0] up_addr_int = 'd0; + reg up_wr_int = 'd0; + reg [15:0] up_wdata_int = 'd0; + reg up_rx_rst_done_m1 = 'd0; + reg up_rx_rst_done_m2 = 'd0; + reg up_tx_rst_done_m1 = 'd0; + reg up_tx_rst_done_m2 = 'd0; + reg [ 2:0] rx_rate_m1 = 'd0; + reg [ 2:0] rx_rate_m2 = 'd0; + reg [ 2:0] tx_rate_m1 = 'd0; + reg [ 2:0] tx_rate_m2 = 'd0; + + // internal signals + + wire up_es_enb_s; + wire up_rx_enb_s; + wire up_tx_enb_s; + wire [15:0] up_rdata_s; + wire up_ready_s; + wire [ 1:0] rx_sys_clk_sel_s; + wire rx_out_clk_s; + wire rx_rst_done_s; + wire [ 1:0] tx_sys_clk_sel_s; + wire tx_out_clk_s; + wire tx_rst_done_s; + wire [ 1:0] rx_pll_clk_sel_s; + wire [ 1:0] tx_pll_clk_sel_s; + wire [11:0] rx_charisk_open_s; + wire [11:0] rx_disperr_open_s; + wire [ 3:0] rx_notintable_open_s; + wire [95:0] rx_data_open_s; + wire cpll_locked_s; + + // pll + + assign up_rx_pll_locked = (up_rx_sys_clk_sel == 2'd3) ? qpll2ch_locked : cpll_locked_s; + assign up_tx_pll_locked = (up_tx_sys_clk_sel == 2'd3) ? qpll2ch_locked : cpll_locked_s; + + // drp access + + assign up_es_rdata = up_es_rdata_int; + assign up_es_ready = up_es_ready_int; + assign up_rx_rdata = up_rx_rdata_int; + assign up_rx_ready = up_rx_ready_int; + assign up_tx_rdata = up_tx_rdata_int; + assign up_tx_ready = up_tx_ready_int; + + assign up_es_enb_s = ((up_es_sel == XCVR_ID) || + (up_es_sel == 8'hff)) ? up_es_enb : 1'b0; + + assign up_rx_enb_s = ((up_rx_sel == XCVR_ID) || + (up_rx_sel == 8'hff)) ? up_rx_enb : 1'b0; + + assign up_tx_enb_s = ((up_tx_sel == XCVR_ID) || + (up_tx_sel == 8'hff)) ? up_tx_enb : 1'b0; + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 1'b0) begin + up_es_rdata_int <= 15'd0; + up_es_ready_int <= 1'd0; + up_rx_rdata_int <= 15'd0; + up_rx_ready_int <= 1'd0; + up_tx_rdata_int <= 15'd0; + up_tx_ready_int <= 1'd0; + up_sel_int <= 3'd0; + up_enb_int <= 1'd0; + up_addr_int <= 12'd0; + up_wr_int <= 1'd0; + up_wdata_int <= 15'd0; + end else begin + if (up_sel_int == 3'b100) begin + up_es_rdata_int <= up_rdata_s; + up_es_ready_int <= up_ready_s; + end else begin + up_es_rdata_int <= 15'd0; + up_es_ready_int <= 1'd0; + end + if (up_sel_int == 3'b101) begin + up_rx_rdata_int <= up_rdata_s; + up_rx_ready_int <= up_ready_s; + end else begin + up_rx_rdata_int <= 15'd0; + up_rx_ready_int <= 1'd0; + end + if (up_sel_int == 3'b110) begin + up_tx_rdata_int <= up_rdata_s; + up_tx_ready_int <= up_ready_s; + end else begin + up_tx_rdata_int <= 15'd0; + up_tx_ready_int <= 1'd0; + end + if (up_sel_int[2] == 1'b1) begin + if (up_ready_s == 1'b1) begin + up_sel_int <= 3'b000; + end + up_enb_int <= 1'b0; + up_addr_int <= 12'd0; + up_wr_int <= 1'd0; + up_wdata_int <= 15'd0; + end else if (up_es_enb_s == 1'b1) begin + up_sel_int <= 3'b100; + up_enb_int <= 1'b1; + up_addr_int <= up_es_addr; + up_wr_int <= up_es_wr; + up_wdata_int <= up_es_wdata; + end else if (up_rx_enb_s == 1'b1) begin + up_sel_int <= 3'b101; + up_enb_int <= 1'b1; + up_addr_int <= up_rx_addr; + up_wr_int <= up_rx_wr; + up_wdata_int <= up_rx_wdata; + end else if (up_tx_enb_s == 1'b1) begin + up_sel_int <= 3'b110; + up_enb_int <= 1'b1; + up_addr_int <= up_tx_addr; + up_wr_int <= up_tx_wr; + up_wdata_int <= up_tx_wdata; + end else begin + up_sel_int <= 3'b000; + up_enb_int <= 1'b0; + up_addr_int <= 12'd0; + up_wr_int <= 1'd0; + up_wdata_int <= 15'd0; + end + end + end + + assign up_rx_rst_done = up_rx_rst_done_m2; + assign up_tx_rst_done = up_tx_rst_done_m2; + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 1'b0) begin + up_rx_rst_done_m1 <= 'd0; + up_rx_rst_done_m2 <= 'd0; + up_tx_rst_done_m1 <= 'd0; + up_tx_rst_done_m2 <= 'd0; + end else begin + up_rx_rst_done_m1 <= rx_rst_done_s; + up_rx_rst_done_m2 <= up_rx_rst_done_m1; + up_tx_rst_done_m1 <= tx_rst_done_s; + up_tx_rst_done_m2 <= up_tx_rst_done_m1; + end + end + + always @(posedge rx_clk) begin + rx_rate_m1 <= up_rx_rate; + rx_rate_m2 <= rx_rate_m1; + end + + always @(posedge tx_clk) begin + tx_rate_m1 <= up_tx_rate; + tx_rate_m2 <= tx_rate_m1; + end + + // instantiations + + generate + if (XCVR_TYPE == 0) begin + BUFG i_rx_bufg (.I (rx_out_clk_s), .O (rx_out_clk)); + BUFG i_tx_bufg (.I (tx_out_clk_s), .O (tx_out_clk)); + end + endgenerate + + generate + if (XCVR_TYPE == 0) begin + assign rx_sys_clk_sel_s = up_rx_sys_clk_sel; + assign tx_sys_clk_sel_s = up_tx_sys_clk_sel; + assign rx_pll_clk_sel_s = 2'd0; + assign tx_pll_clk_sel_s = 2'd0; + end + endgenerate + + generate + if (XCVR_TYPE == 0) begin + GTXE2_CHANNEL #( + .ALIGN_COMMA_DOUBLE ("FALSE"), + .ALIGN_COMMA_ENABLE (10'b1111111111), + .ALIGN_COMMA_WORD (4), + .ALIGN_MCOMMA_DET ("TRUE"), + .ALIGN_MCOMMA_VALUE (10'b1010000011), + .ALIGN_PCOMMA_DET ("TRUE"), + .ALIGN_PCOMMA_VALUE (10'b0101111100), + .CBCC_DATA_SOURCE_SEL ("DECODED"), + .CHAN_BOND_KEEP_ALIGN ("FALSE"), + .CHAN_BOND_MAX_SKEW (1), + .CHAN_BOND_SEQ_1_1 (10'b0000000000), + .CHAN_BOND_SEQ_1_2 (10'b0000000000), + .CHAN_BOND_SEQ_1_3 (10'b0000000000), + .CHAN_BOND_SEQ_1_4 (10'b0000000000), + .CHAN_BOND_SEQ_1_ENABLE (4'b1111), + .CHAN_BOND_SEQ_2_1 (10'b0000000000), + .CHAN_BOND_SEQ_2_2 (10'b0000000000), + .CHAN_BOND_SEQ_2_3 (10'b0000000000), + .CHAN_BOND_SEQ_2_4 (10'b0000000000), + .CHAN_BOND_SEQ_2_ENABLE (4'b1111), + .CHAN_BOND_SEQ_2_USE ("FALSE"), + .CHAN_BOND_SEQ_LEN (1), + .CLK_CORRECT_USE ("FALSE"), + .CLK_COR_KEEP_IDLE ("FALSE"), + .CLK_COR_MAX_LAT (12), + .CLK_COR_MIN_LAT (8), + .CLK_COR_PRECEDENCE ("TRUE"), + .CLK_COR_REPEAT_WAIT (0), + .CLK_COR_SEQ_1_1 (10'b0100000000), + .CLK_COR_SEQ_1_2 (10'b0000000000), + .CLK_COR_SEQ_1_3 (10'b0000000000), + .CLK_COR_SEQ_1_4 (10'b0000000000), + .CLK_COR_SEQ_1_ENABLE (4'b1111), + .CLK_COR_SEQ_2_1 (10'b0100000000), + .CLK_COR_SEQ_2_2 (10'b0000000000), + .CLK_COR_SEQ_2_3 (10'b0000000000), + .CLK_COR_SEQ_2_4 (10'b0000000000), + .CLK_COR_SEQ_2_ENABLE (4'b1111), + .CLK_COR_SEQ_2_USE ("FALSE"), + .CLK_COR_SEQ_LEN (1), + .CPLL_CFG (24'hBC07DC), + .CPLL_FBDIV (CPLL_FBDIV), + .CPLL_FBDIV_45 (CPLL_FBDIV_4_5), + .CPLL_INIT_CFG (24'h00001E), + .CPLL_LOCK_CFG (16'h01E8), + .CPLL_REFCLK_DIV (1), + .DEC_MCOMMA_DETECT ("TRUE"), + .DEC_PCOMMA_DETECT ("TRUE"), + .DEC_VALID_COMMA_ONLY ("FALSE"), + .DMONITOR_CFG (24'h000A00), + .ES_CONTROL (6'b000000), + .ES_ERRDET_EN ("TRUE"), + .ES_EYE_SCAN_EN ("TRUE"), + .ES_HORZ_OFFSET (12'h000), + .ES_PMA_CFG (10'b0000000000), + .ES_PRESCALE (5'b00000), + .ES_QUALIFIER (80'h00000000000000000000), + .ES_QUAL_MASK (80'h00000000000000000000), + .ES_SDATA_MASK (80'h00000000000000000000), + .ES_VERT_OFFSET (9'b000000000), + .FTS_DESKEW_SEQ_ENABLE (4'b1111), + .FTS_LANE_DESKEW_CFG (4'b1111), + .FTS_LANE_DESKEW_EN ("FALSE"), + .GEARBOX_MODE (3'b000), + .IS_CPLLLOCKDETCLK_INVERTED (1'b0), + .IS_DRPCLK_INVERTED (1'b0), + .IS_GTGREFCLK_INVERTED (1'b0), + .IS_RXUSRCLK2_INVERTED (1'b0), + .IS_RXUSRCLK_INVERTED (1'b0), + .IS_TXPHDLYTSTCLK_INVERTED (1'b0), + .IS_TXUSRCLK2_INVERTED (1'b0), + .IS_TXUSRCLK_INVERTED (1'b0), + .OUTREFCLK_SEL_INV (2'b11), + .PCS_PCIE_EN ("FALSE"), + .PCS_RSVD_ATTR (48'h000000000000), + .PD_TRANS_TIME_FROM_P2 (12'h03c), + .PD_TRANS_TIME_NONE_P2 (8'h3c), + .PD_TRANS_TIME_TO_P2 (8'h64), + .PMA_RSV (RX_PMA_CFG), + .PMA_RSV2 (16'h2050), + .PMA_RSV3 (2'b00), + .PMA_RSV4 (32'h00000000), + .RXBUFRESET_TIME (5'b00001), + .RXBUF_ADDR_MODE ("FAST"), + .RXBUF_EIDLE_HI_CNT (4'b1000), + .RXBUF_EIDLE_LO_CNT (4'b0000), + .RXBUF_EN ("TRUE"), + .RXBUF_RESET_ON_CB_CHANGE ("TRUE"), + .RXBUF_RESET_ON_COMMAALIGN ("FALSE"), + .RXBUF_RESET_ON_EIDLE ("FALSE"), + .RXBUF_RESET_ON_RATE_CHANGE ("TRUE"), + .RXBUF_THRESH_OVFLW (57), + .RXBUF_THRESH_OVRD ("TRUE"), + .RXBUF_THRESH_UNDFLW (3), + .RXCDRFREQRESET_TIME (5'b00001), + .RXCDRPHRESET_TIME (5'b00001), + .RXCDR_CFG (RX_CDR_CFG), + .RXCDR_FR_RESET_ON_EIDLE (1'b0), + .RXCDR_HOLD_DURING_EIDLE (1'b0), + .RXCDR_LOCK_CFG (6'b010101), + .RXCDR_PH_RESET_ON_EIDLE (1'b0), + .RXDFELPMRESET_TIME (7'b0001111), + .RXDLY_CFG (16'h001F), + .RXDLY_LCFG (9'h030), + .RXDLY_TAP_CFG (16'h0000), + .RXGEARBOX_EN ("FALSE"), + .RXISCANRESET_TIME (5'b00001), + .RXLPM_HF_CFG (14'b00000011110000), + .RXLPM_LF_CFG (14'b00000011110000), + .RXOOB_CFG (7'b0000110), + .RXOUT_DIV (RX_OUT_DIV), + .RXPCSRESET_TIME (5'b00001), + .RXPHDLY_CFG (24'h084020), + .RXPH_CFG (24'h000000), + .RXPH_MONITOR_SEL (5'b00000), + .RXPMARESET_TIME (5'b00011), + .RXPRBS_ERR_LOOPBACK (1'b0), + .RXSLIDE_AUTO_WAIT (7), + .RXSLIDE_MODE ("OFF"), + .RX_BIAS_CFG (12'b000000000100), + .RX_BUFFER_CFG (6'b000000), + .RX_CLK25_DIV (RX_CLK25_DIV), + .RX_CLKMUX_PD (1'b1), + .RX_CM_SEL (2'b11), + .RX_CM_TRIM (3'b010), + .RX_DATA_WIDTH (40), + .RX_DDI_SEL (6'b000000), + .RX_DEBUG_CFG (12'b000000000000), + .RX_DEFER_RESET_BUF_EN ("TRUE"), + .RX_DFE_GAIN_CFG (23'h020FEA), + .RX_DFE_H2_CFG (12'b000000000000), + .RX_DFE_H3_CFG (12'b000001000000), + .RX_DFE_H4_CFG (11'b00011110000), + .RX_DFE_H5_CFG (11'b00011100000), + .RX_DFE_KL_CFG (13'b0000011111110), + .RX_DFE_KL_CFG2 (32'h301148AC), + .RX_DFE_LPM_CFG (RX_DFE_LPM_CFG), + .RX_DFE_LPM_HOLD_DURING_EIDLE (1'b0), + .RX_DFE_UT_CFG (17'b10001111000000000), + .RX_DFE_VP_CFG (17'b00011111100000011), + .RX_DFE_XYD_CFG (13'b0000000000000), + .RX_DISPERR_SEQ_MATCH ("TRUE"), + .RX_INT_DATAWIDTH (1), + .RX_OS_CFG (13'b0000010000000), + .RX_SIG_VALID_DLY (10), + .RX_XCLK_SEL ("RXREC"), + .SAS_MAX_COM (64), + .SAS_MIN_COM (36), + .SATA_BURST_SEQ_LEN (4'b0101), + .SATA_BURST_VAL (3'b111), + .SATA_CPLL_CFG ("VCO_3000MHZ"), + .SATA_EIDLE_VAL (3'b111), + .SATA_MAX_BURST (8), + .SATA_MAX_INIT (21), + .SATA_MAX_WAKE (7), + .SATA_MIN_BURST (4), + .SATA_MIN_INIT (12), + .SATA_MIN_WAKE (4), + .SHOW_REALIGN_COMMA ("TRUE"), + .SIM_CPLLREFCLK_SEL (3'b001), + .SIM_RECEIVER_DETECT_PASS ("TRUE"), + .SIM_RESET_SPEEDUP ("TRUE"), + .SIM_TX_EIDLE_DRIVE_LEVEL ("X"), + .SIM_VERSION ("4.0"), + .TERM_RCAL_CFG (5'b10000), + .TERM_RCAL_OVRD (1'b0), + .TRANS_TIME_RATE (8'h0E), + .TST_RSV (32'h00000000), + .TXBUF_EN ("TRUE"), + .TXBUF_RESET_ON_RATE_CHANGE ("TRUE"), + .TXDLY_CFG (16'h001F), + .TXDLY_LCFG (9'h030), + .TXDLY_TAP_CFG (16'h0000), + .TXGEARBOX_EN ("FALSE"), + .TXOUT_DIV (TX_OUT_DIV), + .TXPCSRESET_TIME (5'b00001), + .TXPHDLY_CFG (24'h084020), + .TXPH_CFG (16'h0780), + .TXPH_MONITOR_SEL (5'b00000), + .TXPMARESET_TIME (5'b00001), + .TX_CLK25_DIV (TX_CLK25_DIV), + .TX_CLKMUX_PD (1'b1), + .TX_DATA_WIDTH (40), + .TX_DEEMPH0 (5'b00000), + .TX_DEEMPH1 (5'b00000), + .TX_DRIVE_MODE ("DIRECT"), + .TX_EIDLE_ASSERT_DELAY (3'b110), + .TX_EIDLE_DEASSERT_DELAY (3'b100), + .TX_INT_DATAWIDTH (1), + .TX_LOOPBACK_DRIVE_HIZ ("FALSE"), + .TX_MAINCURSOR_SEL (1'b0), + .TX_MARGIN_FULL_0 (7'b1001110), + .TX_MARGIN_FULL_1 (7'b1001001), + .TX_MARGIN_FULL_2 (7'b1000101), + .TX_MARGIN_FULL_3 (7'b1000010), + .TX_MARGIN_FULL_4 (7'b1000000), + .TX_MARGIN_LOW_0 (7'b1000110), + .TX_MARGIN_LOW_1 (7'b1000100), + .TX_MARGIN_LOW_2 (7'b1000010), + .TX_MARGIN_LOW_3 (7'b1000000), + .TX_MARGIN_LOW_4 (7'b1000000), + .TX_PREDRIVER_MODE (1'b0), + .TX_QPI_STATUS_EN (1'b0), + .TX_RXDETECT_CFG (14'h1832), + .TX_RXDETECT_REF (3'b100), + .TX_XCLK_SEL ("TXOUT"), + .UCODEER_CLR (1'b0)) + i_gtxe2_channel ( + .RXOUTCLKPCS (), + .RXPHSLIPMONITOR (), + .PHYSTATUS (), + .RXCDRLOCK (), + .RXCHANBONDSEQ (), + .RXCHANISALIGNED (), + .RXCHANREALIGN (), + .RXCOMINITDET (), + .RXCOMSASDET (), + .RXCOMWAKEDET (), + .RXDATAVALID (), + .RXDLYSRESETDONE (), + .RXELECIDLE (), + .RXHEADERVALID (), + .RXPHALIGNDONE (), + .RXQPISENN (), + .RXQPISENP (), + .RXRATEDONE (), + .RXSTARTOFSEQ (), + .RXVALID (), + .TXCOMFINISH (), + .TXDLYSRESETDONE (), + .TXGEARBOXREADY (), + .TXPHALIGNDONE (), + .TXPHINITDONE (), + .TXQPISENN (), + .TXQPISENP (), + .TXRATEDONE (), + .PCSRSVDOUT (), + .RXCLKCORCNT (), + .RXHEADER (), + .RXCHBONDO (), + .RXPHMONITOR (), + .TSTOUT (), + .GTREFCLKMONITOR (), + .CFGRESET (1'h0), + .CLKRSVD (4'h0), + .CPLLFBCLKLOST (), + .CPLLLOCK (cpll_locked_s), + .CPLLLOCKDETCLK (up_clk), + .CPLLLOCKEN (1'h1), + .CPLLPD (1'h0), + .CPLLREFCLKLOST (), + .CPLLREFCLKSEL (3'h1), + .CPLLRESET (up_cpll_rst), + .DMONITOROUT (), + .DRPADDR (up_addr_int[8:0]), + .DRPCLK (up_clk), + .DRPDI (up_wdata_int), + .DRPDO (up_rdata_s), + .DRPEN (up_enb_int), + .DRPRDY (up_ready_s), + .DRPWE (up_wr_int), + .EYESCANDATAERROR (), + .EYESCANMODE (1'h0), + .EYESCANRESET (1'h0), + .EYESCANTRIGGER (1'h0), + .GTGREFCLK (1'h0), + .GTNORTHREFCLK0 (1'h0), + .GTNORTHREFCLK1 (1'h0), + .GTREFCLK0 (cpll_ref_clk), + .GTREFCLK1 (1'h0), + .GTRESETSEL (1'h0), + .GTRSVD (16'h0), + .GTRXRESET (up_rx_rst), + .GTSOUTHREFCLK0 (1'h0), + .GTSOUTHREFCLK1 (1'h0), + .GTTXRESET (up_tx_rst), + .GTXRXN (rx_n), + .GTXRXP (rx_p), + .GTXTXN (tx_n), + .GTXTXP (tx_p), + .LOOPBACK (3'h0), + .PCSRSVDIN (16'h0), + .PCSRSVDIN2 (5'h0), + .PMARSVDIN (5'h0), + .PMARSVDIN2 (5'h0), + .QPLLCLK (qpll2ch_clk), + .QPLLREFCLK (qpll2ch_ref_clk), + .RESETOVRD (1'h0), + .RX8B10BEN (1'h1), + .RXBUFRESET (1'h0), + .RXBUFSTATUS (), + .RXBYTEISALIGNED (), + .RXBYTEREALIGN (), + .RXCDRFREQRESET (1'h0), + .RXCDRHOLD (1'h0), + .RXCDROVRDEN (1'h0), + .RXCDRRESET (1'h0), + .RXCDRRESETRSV (1'h0), + .RXCHARISCOMMA (), + .RXCHARISK ({rx_charisk_open_s[3:0], rx_charisk}), + .RXCHBONDEN (1'h0), + .RXCHBONDI (5'h0), + .RXCHBONDLEVEL (3'h0), + .RXCHBONDMASTER (1'h1), + .RXCHBONDSLAVE (1'h0), + .RXCOMMADET (), + .RXCOMMADETEN (1'h1), + .RXDATA ({rx_data_open_s[31:0], rx_data}), + .RXDDIEN (1'h0), + .RXDFEAGCHOLD (1'h0), + .RXDFEAGCOVRDEN (1'h0), + .RXDFECM1EN (1'h0), + .RXDFELFHOLD (1'h0), + .RXDFELFOVRDEN (1'h0), + .RXDFELPMRESET (1'h0), + .RXDFETAP2HOLD (1'h0), + .RXDFETAP2OVRDEN (1'h0), + .RXDFETAP3HOLD (1'h0), + .RXDFETAP3OVRDEN (1'h0), + .RXDFETAP4HOLD (1'h0), + .RXDFETAP4OVRDEN (1'h0), + .RXDFETAP5HOLD (1'h0), + .RXDFETAP5OVRDEN (1'h0), + .RXDFEUTHOLD (1'h0), + .RXDFEUTOVRDEN (1'h0), + .RXDFEVPHOLD (1'h0), + .RXDFEVPOVRDEN (1'h0), + .RXDFEVSEN (1'h0), + .RXDFEXYDEN (1'h1), + .RXDFEXYDHOLD (1'h0), + .RXDFEXYDOVRDEN (1'h0), + .RXDISPERR ({rx_disperr_open_s[3:0], rx_disperr}), + .RXDLYBYPASS (1'h1), + .RXDLYEN (1'h0), + .RXDLYOVRDEN (1'h0), + .RXDLYSRESET (1'h0), + .RXELECIDLEMODE (2'h3), + .RXGEARBOXSLIP (1'h0), + .RXLPMEN (up_rx_lpm_dfe_n), + .RXLPMHFHOLD (1'h0), + .RXLPMHFOVRDEN (1'h0), + .RXLPMLFHOLD (1'h0), + .RXLPMLFKLOVRDEN (1'h0), + .RXMCOMMAALIGNEN (rx_calign), + .RXMONITOROUT (), + .RXMONITORSEL (2'h0), + .RXNOTINTABLE ({rx_notintable_open_s, rx_notintable}), + .RXOOBRESET (1'h0), + .RXOSHOLD (1'h0), + .RXOSOVRDEN (1'h0), + .RXOUTCLK (rx_out_clk_s), + .RXOUTCLKFABRIC (), + .RXOUTCLKSEL (up_rx_out_clk_sel), + .RXPCOMMAALIGNEN (rx_calign), + .RXPCSRESET (1'h0), + .RXPD (2'h0), + .RXPHALIGN (1'h0), + .RXPHALIGNEN (1'h0), + .RXPHDLYPD (1'h0), + .RXPHDLYRESET (1'h0), + .RXPHOVRDEN (1'h0), + .RXPMARESET (1'h0), + .RXPOLARITY (1'h0), + .RXPRBSCNTRESET (1'h0), + .RXPRBSERR (), + .RXPRBSSEL (3'h0), + .RXQPIEN (1'h0), + .RXRATE (rx_rate_m2), + .RXRESETDONE (rx_rst_done_s), + .RXSLIDE (1'h0), + .RXSTATUS (), + .RXSYSCLKSEL (rx_sys_clk_sel_s), + .RXUSERRDY (up_rx_user_ready), + .RXUSRCLK (rx_clk), + .RXUSRCLK2 (rx_clk), + .SETERRSTATUS (1'h0), + .TSTIN (20'hfffff), + .TX8B10BBYPASS (8'h0), + .TX8B10BEN (1'h1), + .TXBUFDIFFCTRL (3'h4), + .TXBUFSTATUS (), + .TXCHARDISPMODE (8'h0), + .TXCHARDISPVAL (8'h0), + .TXCHARISK ({4'd0, tx_charisk}), + .TXCOMINIT (1'h0), + .TXCOMSAS (1'h0), + .TXCOMWAKE (1'h0), + .TXDATA ({32'd0, tx_data}), + .TXDEEMPH (1'h0), + .TXDETECTRX (1'h0), + .TXDIFFCTRL (4'h8), + .TXDIFFPD (1'h0), + .TXDLYBYPASS (1'h1), + .TXDLYEN (1'h0), + .TXDLYHOLD (1'h0), + .TXDLYOVRDEN (1'h0), + .TXDLYSRESET (1'h0), + .TXDLYUPDOWN (1'h0), + .TXELECIDLE (1'h0), + .TXHEADER (3'h0), + .TXINHIBIT (1'h0), + .TXMAINCURSOR (7'h0), + .TXMARGIN (3'h0), + .TXOUTCLK (tx_out_clk_s), + .TXOUTCLKFABRIC (), + .TXOUTCLKPCS (), + .TXOUTCLKSEL (up_tx_out_clk_sel), + .TXPCSRESET (1'h0), + .TXPD (2'h0), + .TXPDELECIDLEMODE (1'h0), + .TXPHALIGN (1'h0), + .TXPHALIGNEN (1'h0), + .TXPHDLYPD (1'h0), + .TXPHDLYRESET (1'h0), + .TXPHDLYTSTCLK (1'h0), + .TXPHINIT (1'h0), + .TXPHOVRDEN (1'h0), + .TXPISOPD (1'h0), + .TXPMARESET (1'h0), + .TXPOLARITY (1'h0), + .TXPOSTCURSOR (5'h0), + .TXPOSTCURSORINV (1'h0), + .TXPRBSFORCEERR (1'h0), + .TXPRBSSEL (3'd0), + .TXPRECURSOR (5'h0), + .TXPRECURSORINV (1'h0), + .TXQPIBIASEN (1'h0), + .TXQPISTRONGPDOWN (1'h0), + .TXQPIWEAKPUP (1'h0), + .TXRATE (tx_rate_m2), + .TXRESETDONE (tx_rst_done_s), + .TXSEQUENCE (7'h0), + .TXSTARTSEQ (1'h0), + .TXSWING (1'h0), + .TXSYSCLKSEL (tx_sys_clk_sel_s), + .TXUSERRDY (up_tx_user_ready), + .TXUSRCLK (tx_clk), + .TXUSRCLK2 (tx_clk)); + end + endgenerate + + generate + if (XCVR_TYPE == 1) begin + BUFG_GT i_rx_bufg ( + .CE (1'b1), + .CEMASK (1'b0), + .CLR (1'b0), + .CLRMASK (1'b0), + .DIV (3'd0), + .I (rx_out_clk_s), + .O (rx_out_clk)); + + BUFG_GT i_tx_bufg ( + .CE (1'b1), + .CEMASK (1'b0), + .CLR (1'b0), + .CLRMASK (1'b0), + .DIV (3'd0), + .I (tx_out_clk_s), + .O (tx_out_clk)); + end + endgenerate + + generate + if (XCVR_TYPE == 1) begin + assign rx_sys_clk_sel_s = (up_rx_sys_clk_sel == 2'd3) ? 2'b10 : 2'b00; + assign tx_sys_clk_sel_s = (up_tx_sys_clk_sel == 2'd3) ? 2'b10 : 2'b00; + assign rx_pll_clk_sel_s = up_rx_sys_clk_sel; + assign tx_pll_clk_sel_s = up_tx_sys_clk_sel; + end + endgenerate + + generate + if (XCVR_TYPE == 1) begin + GTHE3_CHANNEL #( + .ACJTAG_DEBUG_MODE (1'b0), + .ACJTAG_MODE (1'b0), + .ACJTAG_RESET (1'b0), + .ADAPT_CFG0 (16'hf800), + .ADAPT_CFG1 (16'h0000), + .ALIGN_COMMA_DOUBLE ("FALSE"), + .ALIGN_COMMA_ENABLE (10'b1111111111), + .ALIGN_COMMA_WORD (1), + .ALIGN_MCOMMA_DET ("TRUE"), + .ALIGN_MCOMMA_VALUE (10'b1010000011), + .ALIGN_PCOMMA_DET ("TRUE"), + .ALIGN_PCOMMA_VALUE (10'b0101111100), + .A_RXOSCALRESET (1'b0), + .A_RXPROGDIVRESET (1'b0), + .A_TXPROGDIVRESET (1'b0), + .CBCC_DATA_SOURCE_SEL ("DECODED"), + .CDR_SWAP_MODE_EN (1'b0), + .CHAN_BOND_KEEP_ALIGN ("FALSE"), + .CHAN_BOND_MAX_SKEW (1), + .CHAN_BOND_SEQ_1_1 (10'b0000000000), + .CHAN_BOND_SEQ_1_2 (10'b0000000000), + .CHAN_BOND_SEQ_1_3 (10'b0000000000), + .CHAN_BOND_SEQ_1_4 (10'b0000000000), + .CHAN_BOND_SEQ_1_ENABLE (4'b1111), + .CHAN_BOND_SEQ_2_1 (10'b0000000000), + .CHAN_BOND_SEQ_2_2 (10'b0000000000), + .CHAN_BOND_SEQ_2_3 (10'b0000000000), + .CHAN_BOND_SEQ_2_4 (10'b0000000000), + .CHAN_BOND_SEQ_2_ENABLE (4'b1111), + .CHAN_BOND_SEQ_2_USE ("FALSE"), + .CHAN_BOND_SEQ_LEN (1), + .CLK_CORRECT_USE ("FALSE"), + .CLK_COR_KEEP_IDLE ("FALSE"), + .CLK_COR_MAX_LAT (12), + .CLK_COR_MIN_LAT (8), + .CLK_COR_PRECEDENCE ("TRUE"), + .CLK_COR_REPEAT_WAIT (0), + .CLK_COR_SEQ_1_1 (10'b0100000000), + .CLK_COR_SEQ_1_2 (10'b0100000000), + .CLK_COR_SEQ_1_3 (10'b0100000000), + .CLK_COR_SEQ_1_4 (10'b0100000000), + .CLK_COR_SEQ_1_ENABLE (4'b1111), + .CLK_COR_SEQ_2_1 (10'b0100000000), + .CLK_COR_SEQ_2_2 (10'b0100000000), + .CLK_COR_SEQ_2_3 (10'b0100000000), + .CLK_COR_SEQ_2_4 (10'b0100000000), + .CLK_COR_SEQ_2_ENABLE (4'b1111), + .CLK_COR_SEQ_2_USE ("FALSE"), + .CLK_COR_SEQ_LEN (1), + .CPLL_CFG0 (16'h67f8), + .CPLL_CFG1 (16'ha4ac), + .CPLL_CFG2 (16'h0007), + .CPLL_CFG3 (6'h00), + .CPLL_FBDIV (CPLL_FBDIV), + .CPLL_FBDIV_45 (CPLL_FBDIV_4_5), + .CPLL_INIT_CFG0 (16'h02b2), + .CPLL_INIT_CFG1 (8'h00), + .CPLL_LOCK_CFG (16'h01e8), + .CPLL_REFCLK_DIV (1), + .DDI_CTRL (2'b00), + .DDI_REALIGN_WAIT (15), + .DEC_MCOMMA_DETECT ("TRUE"), + .DEC_PCOMMA_DETECT ("TRUE"), + .DEC_VALID_COMMA_ONLY ("FALSE"), + .DFE_D_X_REL_POS (1'b0), + .DFE_VCM_COMP_EN (1'b0), + .DMONITOR_CFG0 (10'h000), + .DMONITOR_CFG1 (8'h00), + .ES_CLK_PHASE_SEL (1'b0), + .ES_CONTROL (6'b000000), + .ES_ERRDET_EN ("TRUE"), + .ES_EYE_SCAN_EN ("TRUE"), + .ES_HORZ_OFFSET (12'h000), + .ES_PMA_CFG (10'b0000000000), + .ES_PRESCALE (5'b00000), + .ES_QUALIFIER0 (16'h0000), + .ES_QUALIFIER1 (16'h0000), + .ES_QUALIFIER2 (16'h0000), + .ES_QUALIFIER3 (16'h0000), + .ES_QUALIFIER4 (16'h0000), + .ES_QUAL_MASK0 (16'h0000), + .ES_QUAL_MASK1 (16'h0000), + .ES_QUAL_MASK2 (16'h0000), + .ES_QUAL_MASK3 (16'h0000), + .ES_QUAL_MASK4 (16'h0000), + .ES_SDATA_MASK0 (16'h0000), + .ES_SDATA_MASK1 (16'h0000), + .ES_SDATA_MASK2 (16'h0000), + .ES_SDATA_MASK3 (16'h0000), + .ES_SDATA_MASK4 (16'h0000), + .EVODD_PHI_CFG (11'b00000000000), + .EYE_SCAN_SWAP_EN (1'b0), + .FTS_DESKEW_SEQ_ENABLE (4'b1111), + .FTS_LANE_DESKEW_CFG (4'b1111), + .FTS_LANE_DESKEW_EN ("FALSE"), + .GEARBOX_MODE (5'b00000), + .GM_BIAS_SELECT (1'b0), + .LOCAL_MASTER (1'b1), + .OOBDIVCTL (2'b00), + .OOB_PWRUP (1'b0), + .PCI3_AUTO_REALIGN ("OVR_1K_BLK"), + .PCI3_PIPE_RX_ELECIDLE (1'b0), + .PCI3_RX_ASYNC_EBUF_BYPASS (2'b00), + .PCI3_RX_ELECIDLE_EI2_ENABLE (1'b0), + .PCI3_RX_ELECIDLE_H2L_COUNT (6'b000000), + .PCI3_RX_ELECIDLE_H2L_DISABLE (3'b000), + .PCI3_RX_ELECIDLE_HI_COUNT (6'b000000), + .PCI3_RX_ELECIDLE_LP4_DISABLE (1'b0), + .PCI3_RX_FIFO_DISABLE (1'b0), + .PCIE_BUFG_DIV_CTRL (16'h1000), + .PCIE_RXPCS_CFG_GEN3 (16'h02a4), + .PCIE_RXPMA_CFG (16'h000a), + .PCIE_TXPCS_CFG_GEN3 (16'h24a4), + .PCIE_TXPMA_CFG (16'h000a), + .PCS_PCIE_EN ("FALSE"), + .PCS_RSVD0 (16'b0000000000000000), + .PCS_RSVD1 (3'b000), + .PD_TRANS_TIME_FROM_P2 (12'h03c), + .PD_TRANS_TIME_NONE_P2 (8'h19), + .PD_TRANS_TIME_TO_P2 (8'h64), + .PLL_SEL_MODE_GEN12 (2'h3), + .PLL_SEL_MODE_GEN3 (2'h3), + .PMA_RSV1 (16'hf000), + .PROCESS_PAR (3'b010), + .RATE_SW_USE_DRP (1'b1), + .RESET_POWERSAVE_DISABLE (1'b0), + .RXBUFRESET_TIME (5'b00011), + .RXBUF_ADDR_MODE ("FAST"), + .RXBUF_EIDLE_HI_CNT (4'b1000), + .RXBUF_EIDLE_LO_CNT (4'b0000), + .RXBUF_EN ("TRUE"), + .RXBUF_RESET_ON_CB_CHANGE ("TRUE"), + .RXBUF_RESET_ON_COMMAALIGN ("FALSE"), + .RXBUF_RESET_ON_EIDLE ("FALSE"), + .RXBUF_RESET_ON_RATE_CHANGE ("TRUE"), + .RXBUF_THRESH_OVFLW (57), + .RXBUF_THRESH_OVRD ("TRUE"), + .RXBUF_THRESH_UNDFLW (3), + .RXCDRFREQRESET_TIME (5'b00001), + .RXCDRPHRESET_TIME (5'b00001), + .RXCDR_CFG0 (16'h0000), + .RXCDR_CFG0_GEN3 (16'h0000), + .RXCDR_CFG1 (16'h0000), + .RXCDR_CFG1_GEN3 (16'h0000), + .RXCDR_CFG2 (16'h0766), + .RXCDR_CFG2_GEN3 (16'h07e6), + .RXCDR_CFG3 (16'h0000), + .RXCDR_CFG3_GEN3 (16'h0000), + .RXCDR_CFG4 (16'h0000), + .RXCDR_CFG4_GEN3 (16'h0000), + .RXCDR_CFG5 (16'h0000), + .RXCDR_CFG5_GEN3 (16'h0000), + .RXCDR_FR_RESET_ON_EIDLE (1'b0), + .RXCDR_HOLD_DURING_EIDLE (1'b0), + .RXCDR_LOCK_CFG0 (16'h4480), + .RXCDR_LOCK_CFG1 (16'h5fff), + .RXCDR_LOCK_CFG2 (16'h77c3), + .RXCDR_PH_RESET_ON_EIDLE (1'b0), + .RXCFOK_CFG0 (16'h4000), + .RXCFOK_CFG1 (16'h0065), + .RXCFOK_CFG2 (16'h002e), + .RXDFELPMRESET_TIME (7'b0001111), + .RXDFELPM_KL_CFG0 (16'h0000), + .RXDFELPM_KL_CFG1 (16'h0032), + .RXDFELPM_KL_CFG2 (16'h0000), + .RXDFE_CFG0 (16'h0a00), + .RXDFE_CFG1 (16'h0000), + .RXDFE_GC_CFG0 (16'h0000), + .RXDFE_GC_CFG1 (16'h7870), + .RXDFE_GC_CFG2 (16'h0000), + .RXDFE_H2_CFG0 (16'h0000), + .RXDFE_H2_CFG1 (16'h0000), + .RXDFE_H3_CFG0 (16'h4000), + .RXDFE_H3_CFG1 (16'h0000), + .RXDFE_H4_CFG0 (16'h2000), + .RXDFE_H4_CFG1 (16'h0003), + .RXDFE_H5_CFG0 (16'h2000), + .RXDFE_H5_CFG1 (16'h0003), + .RXDFE_H6_CFG0 (16'h2000), + .RXDFE_H6_CFG1 (16'h0000), + .RXDFE_H7_CFG0 (16'h2000), + .RXDFE_H7_CFG1 (16'h0000), + .RXDFE_H8_CFG0 (16'h2000), + .RXDFE_H8_CFG1 (16'h0000), + .RXDFE_H9_CFG0 (16'h2000), + .RXDFE_H9_CFG1 (16'h0000), + .RXDFE_HA_CFG0 (16'h2000), + .RXDFE_HA_CFG1 (16'h0000), + .RXDFE_HB_CFG0 (16'h2000), + .RXDFE_HB_CFG1 (16'h0000), + .RXDFE_HC_CFG0 (16'h0000), + .RXDFE_HC_CFG1 (16'h0000), + .RXDFE_HD_CFG0 (16'h0000), + .RXDFE_HD_CFG1 (16'h0000), + .RXDFE_HE_CFG0 (16'h0000), + .RXDFE_HE_CFG1 (16'h0000), + .RXDFE_HF_CFG0 (16'h0000), + .RXDFE_HF_CFG1 (16'h0000), + .RXDFE_OS_CFG0 (16'h8000), + .RXDFE_OS_CFG1 (16'h0000), + .RXDFE_UT_CFG0 (16'h8000), + .RXDFE_UT_CFG1 (16'h0003), + .RXDFE_VP_CFG0 (16'haa00), + .RXDFE_VP_CFG1 (16'h0033), + .RXDLY_CFG (16'h001f), + .RXDLY_LCFG (16'h0030), + .RXELECIDLE_CFG ("Sigcfg_4"), + .RXGBOX_FIFO_INIT_RD_ADDR (4), + .RXGEARBOX_EN ("FALSE"), + .RXISCANRESET_TIME (5'b00001), + .RXLPM_CFG (16'h0000), + .RXLPM_GC_CFG (16'h1000), + .RXLPM_KH_CFG0 (16'h0000), + .RXLPM_KH_CFG1 (16'h0002), + .RXLPM_OS_CFG0 (16'h8000), + .RXLPM_OS_CFG1 (16'h0002), + .RXOOB_CFG (9'b000000110), + .RXOOB_CLK_CFG ("PMA"), + .RXOSCALRESET_TIME (5'b00011), + .RXOUT_DIV (RX_OUT_DIV), + .RXPCSRESET_TIME (5'b00011), + .RXPHBEACON_CFG (16'h0000), + .RXPHDLY_CFG (16'h2020), + .RXPHSAMP_CFG (16'h2100), + .RXPHSLIP_CFG (16'h6622), + .RXPH_MONITOR_SEL (5'b00000), + .RXPI_CFG0 (2'b01), + .RXPI_CFG1 (2'b01), + .RXPI_CFG2 (2'b01), + .RXPI_CFG3 (2'b01), + .RXPI_CFG4 (1'b0), + .RXPI_CFG5 (1'b1), + .RXPI_CFG6 (3'b011), + .RXPI_LPM (1'b0), + .RXPI_VREFSEL (1'b0), + .RXPMACLK_SEL ("DATA"), + .RXPMARESET_TIME (5'b00011), + .RXPRBS_ERR_LOOPBACK (1'b0), + .RXPRBS_LINKACQ_CNT (15), + .RXSLIDE_AUTO_WAIT (7), + .RXSLIDE_MODE ("OFF"), + .RXSYNC_MULTILANE (1'b1), + .RXSYNC_OVRD (1'b0), + .RXSYNC_SKIP_DA (1'b0), + .RX_AFE_CM_EN (1'b0), + .RX_BIAS_CFG0 (16'h0ab4), + .RX_BUFFER_CFG (6'b000000), + .RX_CAPFF_SARC_ENB (1'b0), + .RX_CLK25_DIV (RX_CLK25_DIV), + .RX_CLKMUX_EN (1'b1), + .RX_CLK_SLIP_OVRD (5'b00000), + .RX_CM_BUF_CFG (4'b1010), + .RX_CM_BUF_PD (1'b0), + .RX_CM_SEL (2'b11), + .RX_CM_TRIM (4'b1010), + .RX_CTLE3_LPF (8'b00000001), + .RX_DATA_WIDTH (40), + .RX_DDI_SEL (6'b000000), + .RX_DEFER_RESET_BUF_EN ("TRUE"), + .RX_DFELPM_CFG0 (4'b0110), + .RX_DFELPM_CFG1 (1'b1), + .RX_DFELPM_KLKH_AGC_STUP_EN (1'b1), + .RX_DFE_AGC_CFG0 (2'b10), + .RX_DFE_AGC_CFG1 (3'b000), + .RX_DFE_KL_LPM_KH_CFG0 (2'b01), + .RX_DFE_KL_LPM_KH_CFG1 (3'b000), + .RX_DFE_KL_LPM_KL_CFG0 (2'b01), + .RX_DFE_KL_LPM_KL_CFG1 (3'b000), + .RX_DFE_LPM_HOLD_DURING_EIDLE (1'b0), + .RX_DISPERR_SEQ_MATCH ("TRUE"), + .RX_DIVRESET_TIME (5'b00001), + .RX_EN_HI_LR (1'b1), + .RX_EYESCAN_VS_CODE (7'b0000000), + .RX_EYESCAN_VS_NEG_DIR (1'b0), + .RX_EYESCAN_VS_RANGE (2'b00), + .RX_EYESCAN_VS_UT_SIGN (1'b0), + .RX_FABINT_USRCLK_FLOP (1'b0), + .RX_INT_DATAWIDTH (1), + .RX_PMA_POWER_SAVE (1'b0), + .RX_PROGDIV_CFG (0.000000), + .RX_SAMPLE_PERIOD (3'b111), + .RX_SIG_VALID_DLY (11), + .RX_SUM_DFETAPREP_EN (1'b0), + .RX_SUM_IREF_TUNE (4'b1100), + .RX_SUM_RES_CTRL (2'b11), + .RX_SUM_VCMTUNE (4'b0000), + .RX_SUM_VCM_OVWR (1'b0), + .RX_SUM_VREF_TUNE (3'b000), + .RX_TUNE_AFE_OS (2'b10), + .RX_WIDEMODE_CDR (1'b1), + .RX_XCLK_SEL ("RXDES"), + .SAS_MAX_COM (64), + .SAS_MIN_COM (36), + .SATA_BURST_SEQ_LEN (4'b1110), + .SATA_BURST_VAL (3'b100), + .SATA_CPLL_CFG ("VCO_3000MHZ"), + .SATA_EIDLE_VAL (3'b100), + .SATA_MAX_BURST (8), + .SATA_MAX_INIT (21), + .SATA_MAX_WAKE (7), + .SATA_MIN_BURST (4), + .SATA_MIN_INIT (12), + .SATA_MIN_WAKE (4), + .SHOW_REALIGN_COMMA ("TRUE"), + .SIM_MODE ("FAST"), + .SIM_RECEIVER_DETECT_PASS ("TRUE"), + .SIM_RESET_SPEEDUP ("TRUE"), + .SIM_TX_EIDLE_DRIVE_LEVEL (1'b0), + .SIM_VERSION (2), + .TAPDLY_SET_TX (2'h0), + .TEMPERATUR_PAR (4'b0010), + .TERM_RCAL_CFG (15'b100001000010000), + .TERM_RCAL_OVRD (3'b000), + .TRANS_TIME_RATE (8'h0e), + .TST_RSV0 (8'h00), + .TST_RSV1 (8'h00), + .TXBUF_EN ("TRUE"), + .TXBUF_RESET_ON_RATE_CHANGE ("TRUE"), + .TXDLY_CFG (16'h0009), + .TXDLY_LCFG (16'h0050), + .TXDRVBIAS_N (4'b1010), + .TXDRVBIAS_P (4'b1010), + .TXFIFO_ADDR_CFG ("LOW"), + .TXGBOX_FIFO_INIT_RD_ADDR (4), + .TXGEARBOX_EN ("FALSE"), + .TXOUT_DIV (TX_OUT_DIV), + .TXPCSRESET_TIME (5'b00011), + .TXPHDLY_CFG0 (16'h2020), + .TXPHDLY_CFG1 (16'h0075), + .TXPH_CFG (16'h0980), + .TXPH_MONITOR_SEL (5'b00000), + .TXPI_CFG0 (2'b01), + .TXPI_CFG1 (2'b01), + .TXPI_CFG2 (2'b01), + .TXPI_CFG3 (1'b0), + .TXPI_CFG4 (1'b1), + .TXPI_CFG5 (3'b011), + .TXPI_GRAY_SEL (1'b0), + .TXPI_INVSTROBE_SEL (1'b0), + .TXPI_LPM (1'b0), + .TXPI_PPMCLK_SEL ("TXUSRCLK2"), + .TXPI_PPM_CFG (8'b00000000), + .TXPI_SYNFREQ_PPM (3'b001), + .TXPI_VREFSEL (1'b0), + .TXPMARESET_TIME (5'b00011), + .TXSYNC_MULTILANE (1'b1), + .TXSYNC_OVRD (1'b0), + .TXSYNC_SKIP_DA (1'b0), + .TX_CLK25_DIV (TX_CLK25_DIV), + .TX_CLKMUX_EN (1'b1), + .TX_DATA_WIDTH (40), + .TX_DCD_CFG (6'b000010), + .TX_DCD_EN (1'b0), + .TX_DEEMPH0 (6'b000000), + .TX_DEEMPH1 (6'b000000), + .TX_DIVRESET_TIME (5'b00001), + .TX_DRIVE_MODE ("DIRECT"), + .TX_EIDLE_ASSERT_DELAY (3'b100), + .TX_EIDLE_DEASSERT_DELAY (3'b011), + .TX_EML_PHI_TUNE (1'b0), + .TX_FABINT_USRCLK_FLOP (1'b0), + .TX_IDLE_DATA_ZERO (1'b0), + .TX_INT_DATAWIDTH (1), + .TX_LOOPBACK_DRIVE_HIZ ("FALSE"), + .TX_MAINCURSOR_SEL (1'b0), + .TX_MARGIN_FULL_0 (7'b1001111), + .TX_MARGIN_FULL_1 (7'b1001110), + .TX_MARGIN_FULL_2 (7'b1001100), + .TX_MARGIN_FULL_3 (7'b1001010), + .TX_MARGIN_FULL_4 (7'b1001000), + .TX_MARGIN_LOW_0 (7'b1000110), + .TX_MARGIN_LOW_1 (7'b1000101), + .TX_MARGIN_LOW_2 (7'b1000011), + .TX_MARGIN_LOW_3 (7'b1000010), + .TX_MARGIN_LOW_4 (7'b1000000), + .TX_MODE_SEL (3'b000), + .TX_PMADATA_OPT (1'b0), + .TX_PMA_POWER_SAVE (1'b0), + .TX_PROGCLK_SEL ("PREPI"), + .TX_PROGDIV_CFG (0.000000), + .TX_QPI_STATUS_EN (1'b0), + .TX_RXDETECT_CFG (14'h0032), + .TX_RXDETECT_REF (3'b100), + .TX_SAMPLE_PERIOD (3'b111), + .TX_SARC_LPBK_ENB (1'b0), + .TX_XCLK_SEL ("TXOUT"), + .USE_PCS_CLK_PHASE_SEL (1'b0), + .WB_MODE (2'b00)) + i_gthe3_channel ( + .BUFGTCE (), + .BUFGTCEMASK (), + .BUFGTDIV (), + .BUFGTRESET (), + .BUFGTRSTMASK (), + .CFGRESET (1'h0), + .CLKRSVD0 (1'h0), + .CLKRSVD1 (1'h0), + .CPLLFBCLKLOST (), + .CPLLLOCK (cpll_locked_s), + .CPLLLOCKDETCLK (up_clk), + .CPLLLOCKEN (1'h1), + .CPLLPD (1'h0), + .CPLLREFCLKLOST (), + .CPLLREFCLKSEL (3'h1), + .CPLLRESET (up_cpll_rst), + .DMONFIFORESET (1'h0), + .DMONITORCLK (1'h0), + .DMONITOROUT (), + .DRPADDR (up_addr_int[8:0]), + .DRPCLK (up_clk), + .DRPDI (up_wdata_int), + .DRPDO (up_rdata_s), + .DRPEN (up_enb_int), + .DRPRDY (up_ready_s), + .DRPWE (up_wr_int), + .EVODDPHICALDONE (1'h0), + .EVODDPHICALSTART (1'h0), + .EVODDPHIDRDEN (1'h0), + .EVODDPHIDWREN (1'h0), + .EVODDPHIXRDEN (1'h0), + .EVODDPHIXWREN (1'h0), + .EYESCANDATAERROR (), + .EYESCANMODE (1'h0), + .EYESCANRESET (1'h0), + .EYESCANTRIGGER (1'h0), + .GTGREFCLK (1'h0), + .GTHRXN (rx_n), + .GTHRXP (rx_p), + .GTHTXN (tx_n), + .GTHTXP (tx_p), + .GTNORTHREFCLK0 (1'h0), + .GTNORTHREFCLK1 (1'h0), + .GTPOWERGOOD (), + .GTREFCLK0 (cpll_ref_clk), + .GTREFCLK1 (1'h0), + .GTREFCLKMONITOR (), + .GTRESETSEL (1'h0), + .GTRSVD (16'h0), + .GTRXRESET (up_rx_rst), + .GTSOUTHREFCLK0 (1'h0), + .GTSOUTHREFCLK1 (1'h0), + .GTTXRESET (up_tx_rst), + .LOOPBACK (3'h0), + .LPBKRXTXSEREN (1'h0), + .LPBKTXRXSEREN (1'h0), + .PCIEEQRXEQADAPTDONE (1'h0), + .PCIERATEGEN3 (), + .PCIERATEIDLE (), + .PCIERATEQPLLPD (), + .PCIERATEQPLLRESET (), + .PCIERSTIDLE (1'h0), + .PCIERSTTXSYNCSTART (1'h0), + .PCIESYNCTXSYNCDONE (), + .PCIEUSERGEN3RDY (), + .PCIEUSERPHYSTATUSRST (), + .PCIEUSERRATEDONE (1'h0), + .PCIEUSERRATESTART (), + .PCSRSVDIN (16'h0), + .PCSRSVDIN2 (5'h0), + .PCSRSVDOUT (), + .PHYSTATUS (), + .PINRSRVDAS (), + .PMARSVDIN (5'h0), + .QPLL0CLK (qpll2ch_clk), + .QPLL0REFCLK (qpll2ch_ref_clk), + .QPLL1CLK (1'h0), + .QPLL1REFCLK (1'h0), + .RESETEXCEPTION (), + .RESETOVRD (1'h0), + .RSTCLKENTX (1'h0), + .RX8B10BEN (1'h1), + .RXBUFRESET (1'h0), + .RXBUFSTATUS (), + .RXBYTEISALIGNED (), + .RXBYTEREALIGN (), + .RXCDRFREQRESET (1'h0), + .RXCDRHOLD (1'h0), + .RXCDRLOCK (), + .RXCDROVRDEN (1'h0), + .RXCDRPHDONE (), + .RXCDRRESET (1'h0), + .RXCDRRESETRSV (1'h0), + .RXCHANBONDSEQ (), + .RXCHANISALIGNED (), + .RXCHANREALIGN (), + .RXCHBONDEN (1'h0), + .RXCHBONDI (5'h0), + .RXCHBONDLEVEL (3'h0), + .RXCHBONDMASTER (1'h0), + .RXCHBONDO (), + .RXCHBONDSLAVE (1'h0), + .RXCLKCORCNT (), + .RXCOMINITDET (), + .RXCOMMADET (), + .RXCOMMADETEN (1'h1), + .RXCOMSASDET (), + .RXCOMWAKEDET (), + .RXCTRL0 ({rx_charisk_open_s, rx_charisk}), + .RXCTRL1 ({rx_disperr_open_s, rx_disperr}), + .RXCTRL2 (), + .RXCTRL3 ({rx_notintable_open_s, rx_notintable}), + .RXDATA ({rx_data_open_s, rx_data}), + .RXDATAEXTENDRSVD (), + .RXDATAVALID (), + .RXDFEAGCCTRL (2'h1), + .RXDFEAGCHOLD (1'h0), + .RXDFEAGCOVRDEN (1'h0), + .RXDFELFHOLD (1'h0), + .RXDFELFOVRDEN (1'h0), + .RXDFELPMRESET (1'h0), + .RXDFETAP10HOLD (1'h0), + .RXDFETAP10OVRDEN (1'h0), + .RXDFETAP11HOLD (1'h0), + .RXDFETAP11OVRDEN (1'h0), + .RXDFETAP12HOLD (1'h0), + .RXDFETAP12OVRDEN (1'h0), + .RXDFETAP13HOLD (1'h0), + .RXDFETAP13OVRDEN (1'h0), + .RXDFETAP14HOLD (1'h0), + .RXDFETAP14OVRDEN (1'h0), + .RXDFETAP15HOLD (1'h0), + .RXDFETAP15OVRDEN (1'h0), + .RXDFETAP2HOLD (1'h0), + .RXDFETAP2OVRDEN (1'h0), + .RXDFETAP3HOLD (1'h0), + .RXDFETAP3OVRDEN (1'h0), + .RXDFETAP4HOLD (1'h0), + .RXDFETAP4OVRDEN (1'h0), + .RXDFETAP5HOLD (1'h0), + .RXDFETAP5OVRDEN (1'h0), + .RXDFETAP6HOLD (1'h0), + .RXDFETAP6OVRDEN (1'h0), + .RXDFETAP7HOLD (1'h0), + .RXDFETAP7OVRDEN (1'h0), + .RXDFETAP8HOLD (1'h0), + .RXDFETAP8OVRDEN (1'h0), + .RXDFETAP9HOLD (1'h0), + .RXDFETAP9OVRDEN (1'h0), + .RXDFEUTHOLD (1'h0), + .RXDFEUTOVRDEN (1'h0), + .RXDFEVPHOLD (1'h0), + .RXDFEVPOVRDEN (1'h0), + .RXDFEVSEN (1'h0), + .RXDFEXYDEN (1'h1), + .RXDLYBYPASS (1'h1), + .RXDLYEN (1'h0), + .RXDLYOVRDEN (1'h0), + .RXDLYSRESET (1'h0), + .RXDLYSRESETDONE (), + .RXELECIDLE (), + .RXELECIDLEMODE (2'h3), + .RXGEARBOXSLIP (1'h0), + .RXHEADER (), + .RXHEADERVALID (), + .RXLATCLK (1'h0), + .RXLPMEN (up_rx_lpm_dfe_n), + .RXLPMGCHOLD (1'h0), + .RXLPMGCOVRDEN (1'h0), + .RXLPMHFHOLD (1'h0), + .RXLPMHFOVRDEN (1'h0), + .RXLPMLFHOLD (1'h0), + .RXLPMLFKLOVRDEN (1'h0), + .RXLPMOSHOLD (1'h0), + .RXLPMOSOVRDEN (1'h0), + .RXMCOMMAALIGNEN (rx_calign), + .RXMONITOROUT (), + .RXMONITORSEL (2'h0), + .RXOOBRESET (1'h0), + .RXOSCALRESET (1'h0), + .RXOSHOLD (1'h0), + .RXOSINTCFG (4'hd), + .RXOSINTDONE (), + .RXOSINTEN (1'h1), + .RXOSINTHOLD (1'h0), + .RXOSINTOVRDEN (1'h0), + .RXOSINTSTARTED (), + .RXOSINTSTROBE (1'h0), + .RXOSINTSTROBEDONE (), + .RXOSINTSTROBESTARTED (), + .RXOSINTTESTOVRDEN (1'h0), + .RXOSOVRDEN (1'h0), + .RXOUTCLK (rx_out_clk_s), + .RXOUTCLKFABRIC (), + .RXOUTCLKPCS (), + .RXOUTCLKSEL (up_rx_out_clk_sel), + .RXPCOMMAALIGNEN (rx_calign), + .RXPCSRESET (1'h0), + .RXPD (2'h0), + .RXPHALIGN (1'h0), + .RXPHALIGNDONE (), + .RXPHALIGNEN (1'h0), + .RXPHALIGNERR (), + .RXPHDLYPD (1'h1), + .RXPHDLYRESET (1'h0), + .RXPHOVRDEN (1'h0), + .RXPLLCLKSEL (rx_pll_clk_sel_s), + .RXPMARESET (1'h0), + .RXPMARESETDONE (), + .RXPOLARITY (1'h0), + .RXPRBSCNTRESET (1'h0), + .RXPRBSERR (), + .RXPRBSLOCKED (), + .RXPRBSSEL (4'h0), + .RXPRGDIVRESETDONE (), + .RXPROGDIVRESET (1'h0), + .RXQPIEN (1'h0), + .RXQPISENN (), + .RXQPISENP (), + .RXRATE (rx_rate_m2), + .RXRATEDONE (), + .RXRATEMODE (1'h0), + .RXRECCLKOUT (), + .RXRESETDONE (rx_rst_done_s), + .RXSLIDE (1'h0), + .RXSLIDERDY (), + .RXSLIPDONE (), + .RXSLIPOUTCLK (1'h0), + .RXSLIPOUTCLKRDY (), + .RXSLIPPMA (1'h0), + .RXSLIPPMARDY (), + .RXSTARTOFSEQ (), + .RXSTATUS (), + .RXSYNCALLIN (1'h0), + .RXSYNCDONE (), + .RXSYNCIN (1'h0), + .RXSYNCMODE (1'h0), + .RXSYNCOUT (), + .RXSYSCLKSEL (rx_sys_clk_sel_s), + .RXUSERRDY (up_rx_user_ready), + .RXUSRCLK (rx_clk), + .RXUSRCLK2 (rx_clk), + .RXVALID (), + .SIGVALIDCLK (1'h0), + .TSTIN (20'h0), + .TX8B10BBYPASS (8'h0), + .TX8B10BEN (1'h1), + .TXBUFDIFFCTRL (3'h0), + .TXBUFSTATUS (), + .TXCOMFINISH (), + .TXCOMINIT (1'h0), + .TXCOMSAS (1'h0), + .TXCOMWAKE (1'h0), + .TXCTRL0 (16'h0), + .TXCTRL1 (16'h0), + .TXCTRL2 ({4'd0, tx_charisk}), + .TXDATA ({96'd0, tx_data}), + .TXDATAEXTENDRSVD (8'h0), + .TXDEEMPH (1'h0), + .TXDETECTRX (1'h0), + .TXDIFFCTRL (4'h8), + .TXDIFFPD (1'h0), + .TXDLYBYPASS (1'h1), + .TXDLYEN (1'h0), + .TXDLYHOLD (1'h0), + .TXDLYOVRDEN (1'h0), + .TXDLYSRESET (1'h0), + .TXDLYSRESETDONE (), + .TXDLYUPDOWN (1'h0), + .TXELECIDLE (1'h0), + .TXHEADER (6'h0), + .TXINHIBIT (1'h0), + .TXLATCLK (1'h0), + .TXMAINCURSOR (7'h40), + .TXMARGIN (3'h0), + .TXOUTCLK (tx_out_clk_s), + .TXOUTCLKFABRIC (), + .TXOUTCLKPCS (), + .TXOUTCLKSEL (up_tx_out_clk_sel), + .TXPCSRESET (1'h0), + .TXPD (2'h0), + .TXPDELECIDLEMODE (1'h0), + .TXPHALIGN (1'h0), + .TXPHALIGNDONE (), + .TXPHALIGNEN (1'h0), + .TXPHDLYPD (1'h1), + .TXPHDLYRESET (1'h0), + .TXPHDLYTSTCLK (1'h0), + .TXPHINIT (1'h0), + .TXPHINITDONE (), + .TXPHOVRDEN (1'h0), + .TXPIPPMEN (1'h0), + .TXPIPPMOVRDEN (1'h0), + .TXPIPPMPD (1'h0), + .TXPIPPMSEL (1'h0), + .TXPIPPMSTEPSIZE (5'h0), + .TXPISOPD (1'h0), + .TXPLLCLKSEL (tx_pll_clk_sel_s), + .TXPMARESET (1'h0), + .TXPMARESETDONE (), + .TXPOLARITY (1'h0), + .TXPOSTCURSOR (5'h0), + .TXPOSTCURSORINV (1'h0), + .TXPRBSFORCEERR (1'h0), + .TXPRBSSEL (4'h0), + .TXPRECURSOR (5'h0), + .TXPRECURSORINV (1'h0), + .TXPRGDIVRESETDONE (), + .TXPROGDIVRESET (up_tx_rst), + .TXQPIBIASEN (1'h0), + .TXQPISENN (), + .TXQPISENP (), + .TXQPISTRONGPDOWN (1'h0), + .TXQPIWEAKPUP (1'h0), + .TXRATE (tx_rate_m2), + .TXRATEDONE (), + .TXRATEMODE (1'h0), + .TXRESETDONE (tx_rst_done_s), + .TXSEQUENCE (7'h0), + .TXSWING (1'h0), + .TXSYNCALLIN (1'h0), + .TXSYNCDONE (), + .TXSYNCIN (1'h0), + .TXSYNCMODE (1'h0), + .TXSYNCOUT (), + .TXSYSCLKSEL (tx_sys_clk_sel_s), + .TXUSERRDY (up_tx_user_ready), + .TXUSRCLK (tx_clk), + .TXUSRCLK2 (tx_clk)); + end + endgenerate + + generate + if (XCVR_TYPE == 2) begin + BUFG_GT i_rx_bufg ( + .CE (1'b1), + .CEMASK (1'b0), + .CLR (1'b0), + .CLRMASK (1'b0), + .DIV (3'd0), + .I (rx_out_clk_s), + .O (rx_out_clk)); + + BUFG_GT i_tx_bufg ( + .CE (1'b1), + .CEMASK (1'b0), + .CLR (1'b0), + .CLRMASK (1'b0), + .DIV (3'd0), + .I (tx_out_clk_s), + .O (tx_out_clk)); + end + endgenerate + + generate + if (XCVR_TYPE == 2) begin + assign rx_sys_clk_sel_s = (up_rx_sys_clk_sel == 2'd3) ? 2'b10 : 2'b00; + assign tx_sys_clk_sel_s = (up_tx_sys_clk_sel == 2'd3) ? 2'b10 : 2'b00; + assign rx_pll_clk_sel_s = up_rx_sys_clk_sel; + assign tx_pll_clk_sel_s = up_tx_sys_clk_sel; + end + endgenerate + + generate + if (XCVR_TYPE == 2) begin + GTHE4_CHANNEL #( + .ACJTAG_DEBUG_MODE (1'b0), + .ACJTAG_MODE (1'b0), + .ACJTAG_RESET (1'b0), + .ADAPT_CFG0 (16'h1000), + .ADAPT_CFG1 (16'hc800), + .ADAPT_CFG2 (16'h0000), + .ALIGN_COMMA_DOUBLE ("FALSE"), + .ALIGN_COMMA_ENABLE (10'b1111111111), + .ALIGN_COMMA_WORD (1'h1), + .ALIGN_MCOMMA_DET ("TRUE"), + .ALIGN_MCOMMA_VALUE (10'b1010000011), + .ALIGN_PCOMMA_DET ("TRUE"), + .ALIGN_PCOMMA_VALUE (10'b0101111100), + .A_RXOSCALRESET (1'b0), + .A_RXPROGDIVRESET (1'b0), + .A_RXTERMINATION (1'b1), + .A_TXDIFFCTRL (5'b01100), + .A_TXPROGDIVRESET (1'b0), + .CAPBYPASS_FORCE (1'b0), + .CBCC_DATA_SOURCE_SEL ("DECODED"), + .CDR_SWAP_MODE_EN (1'b0), + .CFOK_PWRSVE_EN (1'b1), + .CHAN_BOND_KEEP_ALIGN ("FALSE"), + .CHAN_BOND_MAX_SKEW (1'h1), + .CHAN_BOND_SEQ_1_1 (10'b0000000000), + .CHAN_BOND_SEQ_1_2 (10'b0000000000), + .CHAN_BOND_SEQ_1_3 (10'b0000000000), + .CHAN_BOND_SEQ_1_4 (10'b0000000000), + .CHAN_BOND_SEQ_1_ENABLE (4'b1111), + .CHAN_BOND_SEQ_2_1 (10'b0000000000), + .CHAN_BOND_SEQ_2_2 (10'b0000000000), + .CHAN_BOND_SEQ_2_3 (10'b0000000000), + .CHAN_BOND_SEQ_2_4 (10'b0000000000), + .CHAN_BOND_SEQ_2_ENABLE (4'b1111), + .CHAN_BOND_SEQ_2_USE ("FALSE"), + .CHAN_BOND_SEQ_LEN (1'h1), + .CH_HSPMUX (16'h2424), + .CKCAL1_CFG_0 (16'b1100000011000000), + .CKCAL1_CFG_1 (16'b0101000011000000), + .CKCAL1_CFG_2 (16'b0000000000001010), + .CKCAL1_CFG_3 (16'b0000000000000000), + .CKCAL2_CFG_0 (16'b1100000011000000), + .CKCAL2_CFG_1 (16'b1000000011000000), + .CKCAL2_CFG_2 (16'b0000000000000000), + .CKCAL2_CFG_3 (16'b0000000000000000), + .CKCAL2_CFG_4 (16'b0000000000000000), + .CKCAL_RSVD0 (16'h0080), + .CKCAL_RSVD1 (16'h0400), + .CLK_CORRECT_USE ("FALSE"), + .CLK_COR_KEEP_IDLE ("FALSE"), + .CLK_COR_MAX_LAT (12), + .CLK_COR_MIN_LAT (8), + .CLK_COR_PRECEDENCE ("TRUE"), + .CLK_COR_REPEAT_WAIT (1'h0), + .CLK_COR_SEQ_1_1 (10'b0100000000), + .CLK_COR_SEQ_1_2 (10'b0100000000), + .CLK_COR_SEQ_1_3 (10'b0100000000), + .CLK_COR_SEQ_1_4 (10'b0100000000), + .CLK_COR_SEQ_1_ENABLE (4'b1111), + .CLK_COR_SEQ_2_1 (10'b0100000000), + .CLK_COR_SEQ_2_2 (10'b0100000000), + .CLK_COR_SEQ_2_3 (10'b0100000000), + .CLK_COR_SEQ_2_4 (10'b0100000000), + .CLK_COR_SEQ_2_ENABLE (4'b1111), + .CLK_COR_SEQ_2_USE ("FALSE"), + .CLK_COR_SEQ_LEN (1'h1), + .CPLL_CFG0 (16'h01fa), + .CPLL_CFG1 (16'h0023), + .CPLL_CFG2 (16'h0002), + .CPLL_CFG3 (16'h0000), + .CPLL_FBDIV (CPLL_FBDIV), + .CPLL_FBDIV_45 (5), + .CPLL_INIT_CFG0 (16'h02b2), + .CPLL_LOCK_CFG (16'h01e8), + .CPLL_REFCLK_DIV (1'h1), + .CTLE3_OCAP_EXT_CTRL (3'b000), + .CTLE3_OCAP_EXT_EN (1'b0), + .DDI_CTRL (2'b00), + .DDI_REALIGN_WAIT (15), + .DEC_MCOMMA_DETECT ("TRUE"), + .DEC_PCOMMA_DETECT ("TRUE"), + .DEC_VALID_COMMA_ONLY ("FALSE"), + .DELAY_ELEC (1'b0), + .DMONITOR_CFG0 (10'h000), + .DMONITOR_CFG1 (8'h00), + .ES_CLK_PHASE_SEL (1'b0), + .ES_CONTROL (6'b000000), + .ES_ERRDET_EN ("TRUE"), + .ES_EYE_SCAN_EN ("TRUE"), + .ES_HORZ_OFFSET (12'h000), + .ES_PRESCALE (5'b00000), + .ES_QUALIFIER0 (16'h0000), + .ES_QUALIFIER1 (16'h0000), + .ES_QUALIFIER2 (16'h0000), + .ES_QUALIFIER3 (16'h0000), + .ES_QUALIFIER4 (16'h0000), + .ES_QUALIFIER5 (16'h0000), + .ES_QUALIFIER6 (16'h0000), + .ES_QUALIFIER7 (16'h0000), + .ES_QUALIFIER8 (16'h0000), + .ES_QUALIFIER9 (16'h0000), + .ES_QUAL_MASK0 (16'h0000), + .ES_QUAL_MASK1 (16'h0000), + .ES_QUAL_MASK2 (16'h0000), + .ES_QUAL_MASK3 (16'h0000), + .ES_QUAL_MASK4 (16'h0000), + .ES_QUAL_MASK5 (16'h0000), + .ES_QUAL_MASK6 (16'h0000), + .ES_QUAL_MASK7 (16'h0000), + .ES_QUAL_MASK8 (16'h0000), + .ES_QUAL_MASK9 (16'h0000), + .ES_SDATA_MASK0 (16'h0000), + .ES_SDATA_MASK1 (16'h0000), + .ES_SDATA_MASK2 (16'h0000), + .ES_SDATA_MASK3 (16'h0000), + .ES_SDATA_MASK4 (16'h0000), + .ES_SDATA_MASK5 (16'h0000), + .ES_SDATA_MASK6 (16'h0000), + .ES_SDATA_MASK7 (16'h0000), + .ES_SDATA_MASK8 (16'h0000), + .ES_SDATA_MASK9 (16'h0000), + .EYE_SCAN_SWAP_EN (1'b0), + .FTS_DESKEW_SEQ_ENABLE (4'b1111), + .FTS_LANE_DESKEW_CFG (4'b1111), + .FTS_LANE_DESKEW_EN ("FALSE"), + .GEARBOX_MODE (5'b00000), + .ISCAN_CK_PH_SEL2 (1'b0), + .LOCAL_MASTER (1'b1), + .LPBK_BIAS_CTRL (3'b100), + .LPBK_EN_RCAL_B (1'b0), + .LPBK_EXT_RCAL (4'b1000), + .LPBK_IND_CTRL0 (3'b000), + .LPBK_IND_CTRL1 (3'b000), + .LPBK_IND_CTRL2 (3'b000), + .LPBK_RG_CTRL (4'b1110), + .OOBDIVCTL (2'b00), + .OOB_PWRUP (1'b0), + .PCI3_AUTO_REALIGN ("OVR_1K_BLK"), + .PCI3_PIPE_RX_ELECIDLE (1'b0), + .PCI3_RX_ASYNC_EBUF_BYPASS (2'b00), + .PCI3_RX_ELECIDLE_EI2_ENABLE (1'b0), + .PCI3_RX_ELECIDLE_H2L_COUNT (6'b000000), + .PCI3_RX_ELECIDLE_H2L_DISABLE (3'b000), + .PCI3_RX_ELECIDLE_HI_COUNT (6'b000000), + .PCI3_RX_ELECIDLE_LP4_DISABLE (1'b0), + .PCI3_RX_FIFO_DISABLE (1'b0), + .PCIE3_CLK_COR_EMPTY_THRSH (5'b00000), + .PCIE3_CLK_COR_FULL_THRSH (6'b010000), + .PCIE3_CLK_COR_MAX_LAT (5'b00100), + .PCIE3_CLK_COR_MIN_LAT (5'b00000), + .PCIE3_CLK_COR_THRSH_TIMER (6'b001000), + .PCIE_BUFG_DIV_CTRL (16'h3500), + .PCIE_PLL_SEL_MODE_GEN12 (2'h2), + .PCIE_PLL_SEL_MODE_GEN3 (2'h2), + .PCIE_PLL_SEL_MODE_GEN4 (2'h2), + .PCIE_RXPCS_CFG_GEN3 (16'h0aa5), + .PCIE_RXPMA_CFG (16'h280a), + .PCIE_TXPCS_CFG_GEN3 (16'h24a4), + .PCIE_TXPMA_CFG (16'h280a), + .PCS_PCIE_EN ("FALSE"), + .PCS_RSVD0 (16'b0000000000000000), + .PD_TRANS_TIME_FROM_P2 (12'h03c), + .PD_TRANS_TIME_NONE_P2 (8'h19), + .PD_TRANS_TIME_TO_P2 (8'h64), + .PREIQ_FREQ_BST (1'h0), + .PROCESS_PAR (3'b010), + .RATE_SW_USE_DRP (1'b1), + .RCLK_SIPO_DLY_ENB (1'b0), + .RCLK_SIPO_INV_EN (1'b0), + .RESET_POWERSAVE_DISABLE (1'b0), + .RTX_BUF_CML_CTRL (3'b010), + .RTX_BUF_TERM_CTRL (2'b00), + .RXBUFRESET_TIME (5'b00011), + .RXBUF_ADDR_MODE ("FAST"), + .RXBUF_EIDLE_HI_CNT (4'b1000), + .RXBUF_EIDLE_LO_CNT (4'b0000), + .RXBUF_EN ("TRUE"), + .RXBUF_RESET_ON_CB_CHANGE ("TRUE"), + .RXBUF_RESET_ON_COMMAALIGN ("FALSE"), + .RXBUF_RESET_ON_EIDLE ("FALSE"), + .RXBUF_RESET_ON_RATE_CHANGE ("TRUE"), + .RXBUF_THRESH_OVFLW (57), + .RXBUF_THRESH_OVRD ("TRUE"), + .RXBUF_THRESH_UNDFLW (3), + .RXCDRFREQRESET_TIME (5'b00001), + .RXCDRPHRESET_TIME (5'b00001), + .RXCDR_CFG0 (16'h0002), + .RXCDR_CFG0_GEN3 (16'h0003), + .RXCDR_CFG1 (16'h0000), + .RXCDR_CFG1_GEN3 (16'h0000), + .RXCDR_CFG2 (16'h0265), + .RXCDR_CFG2_GEN3 (16'h0265), + .RXCDR_CFG2_GEN4 (16'h00b4), + .RXCDR_CFG3 (16'h0012), + .RXCDR_CFG3_GEN3 (16'h0012), + .RXCDR_CFG3_GEN4 (16'h0024), + .RXCDR_CFG4 (16'h5cf6), + .RXCDR_CFG4_GEN3 (16'h5cf6), + .RXCDR_CFG5 (16'hb46b), + .RXCDR_CFG5_GEN3 (16'h146b), + .RXCDR_FR_RESET_ON_EIDLE (1'b0), + .RXCDR_HOLD_DURING_EIDLE (1'b0), + .RXCDR_LOCK_CFG0 (16'h2201), + .RXCDR_LOCK_CFG1 (16'h9fff), + .RXCDR_LOCK_CFG2 (16'h77c3), + .RXCDR_LOCK_CFG3 (16'h0001), + .RXCDR_LOCK_CFG4 (16'h0000), + .RXCDR_PH_RESET_ON_EIDLE (1'b0), + .RXCFOK_CFG0 (16'h0000), + .RXCFOK_CFG1 (16'h8015), + .RXCFOK_CFG2 (16'h02ae), + .RXCKCAL1_IQ_LOOP_RST_CFG (16'h0004), + .RXCKCAL1_I_LOOP_RST_CFG (16'h0004), + .RXCKCAL1_Q_LOOP_RST_CFG (16'h0004), + .RXCKCAL2_DX_LOOP_RST_CFG (16'h0004), + .RXCKCAL2_D_LOOP_RST_CFG (16'h0004), + .RXCKCAL2_S_LOOP_RST_CFG (16'h0004), + .RXCKCAL2_X_LOOP_RST_CFG (16'h0004), + .RXDFELPMRESET_TIME (7'b0001111), + .RXDFELPM_KL_CFG0 (16'h0000), + .RXDFELPM_KL_CFG1 (16'ha0e2), + .RXDFELPM_KL_CFG2 (16'h0100), + .RXDFE_CFG0 (16'h0a00), + .RXDFE_CFG1 (16'h0280), + .RXDFE_GC_CFG0 (16'h0000), + .RXDFE_GC_CFG1 (16'h8000), + .RXDFE_GC_CFG2 (16'hffe0), + .RXDFE_H2_CFG0 (16'h0000), + .RXDFE_H2_CFG1 (16'h0002), + .RXDFE_H3_CFG0 (16'h0000), + .RXDFE_H3_CFG1 (16'h8002), + .RXDFE_H4_CFG0 (16'h0000), + .RXDFE_H4_CFG1 (16'h8002), + .RXDFE_H5_CFG0 (16'h0000), + .RXDFE_H5_CFG1 (16'h8002), + .RXDFE_H6_CFG0 (16'h0000), + .RXDFE_H6_CFG1 (16'h8002), + .RXDFE_H7_CFG0 (16'h0000), + .RXDFE_H7_CFG1 (16'h8002), + .RXDFE_H8_CFG0 (16'h0000), + .RXDFE_H8_CFG1 (16'h8002), + .RXDFE_H9_CFG0 (16'h0000), + .RXDFE_H9_CFG1 (16'h8002), + .RXDFE_HA_CFG0 (16'h0000), + .RXDFE_HA_CFG1 (16'h8002), + .RXDFE_HB_CFG0 (16'h0000), + .RXDFE_HB_CFG1 (16'h8002), + .RXDFE_HC_CFG0 (16'h0000), + .RXDFE_HC_CFG1 (16'h8002), + .RXDFE_HD_CFG0 (16'h0000), + .RXDFE_HD_CFG1 (16'h8002), + .RXDFE_HE_CFG0 (16'h0000), + .RXDFE_HE_CFG1 (16'h8002), + .RXDFE_HF_CFG0 (16'h0000), + .RXDFE_HF_CFG1 (16'h8002), + .RXDFE_KH_CFG0 (16'h0000), + .RXDFE_KH_CFG1 (16'h8000), + .RXDFE_KH_CFG2 (16'h2613), + .RXDFE_KH_CFG3 (16'h411c), + .RXDFE_OS_CFG0 (16'h0000), + .RXDFE_OS_CFG1 (16'h8002), + .RXDFE_PWR_SAVING (1'b1), + .RXDFE_UT_CFG0 (16'h0000), + .RXDFE_UT_CFG1 (16'h0003), + .RXDFE_UT_CFG2 (16'h0000), + .RXDFE_VP_CFG0 (16'h0000), + .RXDFE_VP_CFG1 (16'h8033), + .RXDLY_CFG (16'h0010), + .RXDLY_LCFG (16'h0030), + .RXELECIDLE_CFG ("SIGCFG_4"), + .RXGBOX_FIFO_INIT_RD_ADDR (4), + .RXGEARBOX_EN ("FALSE"), + .RXISCANRESET_TIME (5'b00001), + .RXLPM_CFG (16'h0000), + .RXLPM_GC_CFG (16'h8000), + .RXLPM_KH_CFG0 (16'h0000), + .RXLPM_KH_CFG1 (16'h0002), + .RXLPM_OS_CFG0 (16'h0000), + .RXLPM_OS_CFG1 (16'h8002), + .RXOOB_CFG (9'b000000110), + .RXOOB_CLK_CFG ("PMA"), + .RXOSCALRESET_TIME (5'b00011), + .RXOUT_DIV (RX_OUT_DIV), + .RXPCSRESET_TIME (5'b00011), + .RXPHBEACON_CFG (16'h0000), + .RXPHDLY_CFG (16'h2070), + .RXPHSAMP_CFG (16'h2100), + .RXPHSLIP_CFG (16'h9933), + .RXPH_MONITOR_SEL (5'b00000), + .RXPI_AUTO_BW_SEL_BYPASS (1'b0), + .RXPI_CFG0 (16'h0002), + .RXPI_CFG1 (16'b0000000000010101), + .RXPI_LPM (1'b0), + .RXPI_SEL_LC (2'b00), + .RXPI_STARTCODE (2'b00), + .RXPI_VREFSEL (1'b0), + .RXPMACLK_SEL ("DATA"), + .RXPMARESET_TIME (5'b00011), + .RXPRBS_ERR_LOOPBACK (1'b0), + .RXPRBS_LINKACQ_CNT (15), + .RXREFCLKDIV2_SEL (1'b0), + .RXSLIDE_AUTO_WAIT (7), + .RXSLIDE_MODE ("OFF"), + .RXSYNC_MULTILANE (1'b1), + .RXSYNC_OVRD (1'b0), + .RXSYNC_SKIP_DA (1'b0), + .RX_AFE_CM_EN (1'b0), + .RX_BIAS_CFG0 (16'h1554), + .RX_BUFFER_CFG (6'b000000), + .RX_CAPFF_SARC_ENB (1'b0), + .RX_CLK25_DIV (RX_CLK25_DIV), + .RX_CLKMUX_EN (1'b1), + .RX_CLK_SLIP_OVRD (5'b00000), + .RX_CM_BUF_CFG (4'b1010), + .RX_CM_BUF_PD (1'b0), + .RX_CM_SEL (3), + .RX_CM_TRIM (10), + .RX_CTLE3_LPF (8'b11111111), + .RX_DATA_WIDTH (40), + .RX_DDI_SEL (6'b000000), + .RX_DEFER_RESET_BUF_EN ("TRUE"), + .RX_DEGEN_CTRL (3'b011), + .RX_DFELPM_CFG0 (6), + .RX_DFELPM_CFG1 (1'b1), + .RX_DFELPM_KLKH_AGC_STUP_EN (1'b1), + .RX_DFE_AGC_CFG0 (2'b10), + .RX_DFE_AGC_CFG1 (4), + .RX_DFE_KL_LPM_KH_CFG0 (1'h1), + .RX_DFE_KL_LPM_KH_CFG1 (4), + .RX_DFE_KL_LPM_KL_CFG0 (2'b01), + .RX_DFE_KL_LPM_KL_CFG1 (4), + .RX_DFE_LPM_HOLD_DURING_EIDLE (1'b0), + .RX_DISPERR_SEQ_MATCH ("TRUE"), + .RX_DIV2_MODE_B (1'b0), + .RX_DIVRESET_TIME (5'b00001), + .RX_EN_CTLE_RCAL_B (1'b0), + .RX_EN_HI_LR (1'b1), + .RX_EXT_RL_CTRL (9'b000000000), + .RX_EYESCAN_VS_CODE (7'b0000000), + .RX_EYESCAN_VS_NEG_DIR (1'b0), + .RX_EYESCAN_VS_RANGE (2'b00), + .RX_EYESCAN_VS_UT_SIGN (1'b0), + .RX_FABINT_USRCLK_FLOP (1'b0), + .RX_INT_DATAWIDTH (1'h1), + .RX_PMA_POWER_SAVE (1'b0), + .RX_PMA_RSV0 (16'h0000), + .RX_PROGDIV_CFG (0.000000), + .RX_PROGDIV_RATE (16'h0001), + .RX_RESLOAD_CTRL (4'b0000), + .RX_RESLOAD_OVRD (1'b0), + .RX_SAMPLE_PERIOD (3'b111), + .RX_SIG_VALID_DLY (11), + .RX_SUM_DFETAPREP_EN (1'b0), + .RX_SUM_IREF_TUNE (4'b0100), + .RX_SUM_RESLOAD_CTRL (4'b0011), + .RX_SUM_VCMTUNE (4'b0110), + .RX_SUM_VCM_OVWR (1'b0), + .RX_SUM_VREF_TUNE (3'b100), + .RX_TUNE_AFE_OS (2'b00), + .RX_VREG_CTRL (3'b101), + .RX_VREG_PDB (1'b1), + .RX_WIDEMODE_CDR (2'b00), + .RX_WIDEMODE_CDR_GEN3 (2'b00), + .RX_WIDEMODE_CDR_GEN4 (2'b01), + .RX_XCLK_SEL ("RXDES"), + .RX_XMODE_SEL (1'b0), + .SAMPLE_CLK_PHASE (1'b0), + .SAS_12G_MODE (1'b0), + .SATA_BURST_SEQ_LEN (4'b1111), + .SATA_BURST_VAL (3'b100), + .SATA_CPLL_CFG ("VCO_3000MHZ"), + .SATA_EIDLE_VAL (3'b100), + .SHOW_REALIGN_COMMA ("TRUE"), + .SIM_MODE ("FAST"), + .SIM_RECEIVER_DETECT_PASS ("TRUE"), + .SIM_RESET_SPEEDUP ("TRUE"), + .SIM_TX_EIDLE_DRIVE_LEVEL ("Z"), + .SIM_VERSION (1'h1), + .SRSTMODE (1'b0), + .TAPDLY_SET_TX (2'h0), + .TEMPERATURE_PAR (4'b0010), + .TERM_RCAL_CFG (15'b100001000010001), + .TERM_RCAL_OVRD (3'b000), + .TRANS_TIME_RATE (8'h0e), + .TST_RSV0 (8'h00), + .TST_RSV1 (8'h00), + .TXBUF_EN ("TRUE"), + .TXBUF_RESET_ON_RATE_CHANGE ("TRUE"), + .TXDLY_CFG (16'h8010), + .TXDLY_LCFG (16'h0030), + .TXDRVBIAS_N (4'b1010), + .TXFIFO_ADDR_CFG ("LOW"), + .TXGBOX_FIFO_INIT_RD_ADDR (4), + .TXGEARBOX_EN ("FALSE"), + .TXOUT_DIV (TX_OUT_DIV), + .TXPCSRESET_TIME (5'b00011), + .TXPHDLY_CFG0 (16'h6070), + .TXPHDLY_CFG1 (16'h000f), + .TXPH_CFG (16'h0323), + .TXPH_CFG2 (16'h0000), + .TXPH_MONITOR_SEL (5'b00000), + .TXPI_CFG (16'h0054), + .TXPI_CFG0 (2'b00), + .TXPI_CFG1 (2'b00), + .TXPI_CFG2 (2'b00), + .TXPI_CFG3 (1'b0), + .TXPI_CFG4 (1'b0), + .TXPI_CFG5 (3'b000), + .TXPI_GRAY_SEL (1'b0), + .TXPI_INVSTROBE_SEL (1'b0), + .TXPI_LPM (1'b0), + .TXPI_PPM (1'b0), + .TXPI_PPMCLK_SEL ("TXUSRCLK2"), + .TXPI_PPM_CFG (8'b00000000), + .TXPI_SYNFREQ_PPM (3'b001), + .TXPI_VREFSEL (1'b0), + .TXPMARESET_TIME (5'b00011), + .TXREFCLKDIV2_SEL (1'b0), + .TXSYNC_MULTILANE (1'b1), + .TXSYNC_OVRD (1'b0), + .TXSYNC_SKIP_DA (1'b0), + .TX_CLK25_DIV (TX_CLK25_DIV), + .TX_CLKMUX_EN (1'b1), + .TX_DATA_WIDTH (40), + .TX_DCC_LOOP_RST_CFG (16'h0004), + .TX_DEEMPH0 (6'b000000), + .TX_DEEMPH1 (6'b000000), + .TX_DEEMPH2 (6'b000000), + .TX_DEEMPH3 (6'b000000), + .TX_DIVRESET_TIME (5'b00001), + .TX_DRIVE_MODE ("DIRECT"), + .TX_DRVMUX_CTRL (2), + .TX_EIDLE_ASSERT_DELAY (3'b100), + .TX_EIDLE_DEASSERT_DELAY (3'b011), + .TX_FABINT_USRCLK_FLOP (1'b0), + .TX_FIFO_BYP_EN (1'b0), + .TX_IDLE_DATA_ZERO (1'b0), + .TX_INT_DATAWIDTH (1'h1), + .TX_LOOPBACK_DRIVE_HIZ ("FALSE"), + .TX_MAINCURSOR_SEL (1'b0), + .TX_MARGIN_FULL_0 (7'b1011111), + .TX_MARGIN_FULL_1 (7'b1011110), + .TX_MARGIN_FULL_2 (7'b1011100), + .TX_MARGIN_FULL_3 (7'b1011010), + .TX_MARGIN_FULL_4 (7'b1011000), + .TX_MARGIN_LOW_0 (7'b1000110), + .TX_MARGIN_LOW_1 (7'b1000101), + .TX_MARGIN_LOW_2 (7'b1000011), + .TX_MARGIN_LOW_3 (7'b1000010), + .TX_MARGIN_LOW_4 (7'b1000000), + .TX_PHICAL_CFG0 (16'h0000), + .TX_PHICAL_CFG1 (16'h7e00), + .TX_PHICAL_CFG2 (16'h0201), + .TX_PI_BIASSET (1'h1), + .TX_PI_IBIAS_MID (2'b00), + .TX_PMADATA_OPT (1'b0), + .TX_PMA_POWER_SAVE (1'b0), + .TX_PMA_RSV0 (16'h0008), + .TX_PREDRV_CTRL (2), + .TX_PROGCLK_SEL ("PREPI"), + .TX_PROGDIV_CFG (0.000000), + .TX_PROGDIV_RATE (16'h0001), + .TX_QPI_STATUS_EN (1'b0), + .TX_RXDETECT_CFG (14'h0032), + .TX_RXDETECT_REF (4), + .TX_SAMPLE_PERIOD (3'b111), + .TX_SARC_LPBK_ENB (1'b0), + .TX_SW_MEAS (2'b00), + .TX_VREG_CTRL (3'b000), + .TX_VREG_PDB (1'b0), + .TX_VREG_VREFSEL (2'b00), + .TX_XCLK_SEL ("TXOUT"), + .USB_BOTH_BURST_IDLE (1'b0), + .USB_BURSTMAX_U3WAKE (7'b1111111), + .USB_BURSTMIN_U3WAKE (7'b1100011), + .USB_CLK_COR_EQ_EN (1'b0), + .USB_EXT_CNTL (1'b1), + .USB_IDLEMAX_POLLING (10'b1010111011), + .USB_IDLEMIN_POLLING (10'b0100101011), + .USB_LFPSPING_BURST (9'b000000101), + .USB_LFPSPOLLING_BURST (9'b000110001), + .USB_LFPSPOLLING_IDLE_MS (9'b000000100), + .USB_LFPSU1EXIT_BURST (9'b000011101), + .USB_LFPSU2LPEXIT_BURST_MS (9'b001100011), + .USB_LFPSU3WAKE_BURST_MS (9'b111110011), + .USB_LFPS_TPERIOD (4'b0011), + .USB_LFPS_TPERIOD_ACCURATE (1'b1), + .USB_MODE (1'b0), + .USB_PCIE_ERR_REP_DIS (1'b0), + .USB_PING_SATA_MAX_INIT (21), + .USB_PING_SATA_MIN_INIT (12), + .USB_POLL_SATA_MAX_BURST (8), + .USB_POLL_SATA_MIN_BURST (4), + .USB_RAW_ELEC (1'b0), + .USB_RXIDLE_P0_CTRL (1'b1), + .USB_TXIDLE_TUNE_ENABLE (1'b1), + .USB_U1_SATA_MAX_WAKE (7), + .USB_U1_SATA_MIN_WAKE (4), + .USB_U2_SAS_MAX_COM (64), + .USB_U2_SAS_MIN_COM (36), + .USE_PCS_CLK_PHASE_SEL (1'b0), + .Y_ALL_MODE (1'b0)) + i_gthe4_channel ( + .BUFGTCE (), + .BUFGTCEMASK (), + .BUFGTDIV (), + .BUFGTRESET (), + .BUFGTRSTMASK (), + .CDRSTEPDIR (1'd0), + .CDRSTEPSQ (1'd0), + .CDRSTEPSX (1'd0), + .CFGRESET (1'd0), + .CLKRSVD0 (1'd0), + .CLKRSVD1 (1'd0), + .CPLLFBCLKLOST (), + .CPLLFREQLOCK (1'd0), + .CPLLLOCK (cpll_locked_s), + .CPLLLOCKDETCLK (up_clk), + .CPLLLOCKEN (1'd1), + .CPLLPD (1'b0), + .CPLLREFCLKLOST (), + .CPLLREFCLKSEL (3'b001), + .CPLLRESET (up_cpll_rst), + .DMONFIFORESET (1'd0), + .DMONITORCLK (1'd0), + .DMONITOROUT (), + .DMONITOROUTCLK (), + .DRPADDR (up_addr_int[9:0]), + .DRPCLK (up_clk), + .DRPDI (up_wdata_int), + .DRPDO (up_rdata_s), + .DRPEN (up_enb_int), + .DRPRDY (up_ready_s), + .DRPRST (1'd0), + .DRPWE (up_wr_int), + .EYESCANDATAERROR (), + .EYESCANRESET (1'd0), + .EYESCANTRIGGER (1'd0), + .FREQOS (1'd0), + .GTGREFCLK (1'd0), + .GTHRXN (rx_n), + .GTHRXP (rx_p), + .GTHTXN (tx_n), + .GTHTXP (tx_p), + .GTNORTHREFCLK0 (1'd0), + .GTNORTHREFCLK1 (1'd0), + .GTPOWERGOOD (), + .GTREFCLK0 (cpll_ref_clk), + .GTREFCLK1 (1'd0), + .GTREFCLKMONITOR (), + .GTRSVD (15'd0), + .GTRXRESET (up_rx_rst), + .GTRXRESETSEL (1'd0), + .GTSOUTHREFCLK0 (1'd0), + .GTSOUTHREFCLK1 (1'd0), + .GTTXRESET (up_tx_rst), + .GTTXRESETSEL (1'd0), + .INCPCTRL (1'd0), + .LOOPBACK (3'd0), + .PCIEEQRXEQADAPTDONE (1'd0), + .PCIERATEGEN3 (), + .PCIERATEIDLE (), + .PCIERATEQPLLPD (), + .PCIERATEQPLLRESET (), + .PCIERSTIDLE (1'd0), + .PCIERSTTXSYNCSTART (1'd0), + .PCIESYNCTXSYNCDONE (), + .PCIEUSERGEN3RDY (), + .PCIEUSERPHYSTATUSRST (), + .PCIEUSERRATEDONE (1'd0), + .PCIEUSERRATESTART (), + .PCSRSVDIN (16'd0), + .PCSRSVDOUT (), + .PHYSTATUS (), + .PINRSRVDAS (), + .POWERPRESENT (), + .QPLL0CLK (qpll2ch_clk), + .QPLL0FREQLOCK (1'd0), + .QPLL0REFCLK (qpll2ch_ref_clk), + .QPLL1CLK (1'd0), + .QPLL1FREQLOCK (1'd0), + .QPLL1REFCLK (1'd0), + .RESETEXCEPTION (), + .RESETOVRD (1'd0), + .RX8B10BEN (1'd1), + .RXAFECFOKEN (1'b1), + .RXBUFRESET (1'd0), + .RXBUFSTATUS (), + .RXBYTEISALIGNED (), + .RXBYTEREALIGN (), + .RXCDRFREQRESET (1'd0), + .RXCDRHOLD (1'd0), + .RXCDRLOCK (), + .RXCDROVRDEN (1'd0), + .RXCDRPHDONE (), + .RXCDRRESET (1'd0), + .RXCHANBONDSEQ (), + .RXCHANISALIGNED (), + .RXCHANREALIGN (), + .RXCHBONDEN (1'd0), + .RXCHBONDI (5'd0), + .RXCHBONDLEVEL (3'd0), + .RXCHBONDMASTER (1'd0), + .RXCHBONDO (), + .RXCHBONDSLAVE (1'd0), + .RXCKCALDONE (), + .RXCKCALRESET (1'd0), + .RXCKCALSTART (7'd0), + .RXCLKCORCNT (), + .RXCOMINITDET (), + .RXCOMMADET (), + .RXCOMMADETEN (1'd1), + .RXCOMSASDET (), + .RXCOMWAKEDET (), + .RXCTRL0 ({rx_charisk_open_s, rx_charisk}), + .RXCTRL1 ({rx_disperr_open_s, rx_disperr}), + .RXCTRL2 (), + .RXCTRL3 ({rx_notintable_open_s, rx_notintable}), + .RXDATA ({rx_data_open_s, rx_data}), + .RXDATAEXTENDRSVD (), + .RXDATAVALID (), + .RXDFEAGCCTRL (2'b01), + .RXDFEAGCHOLD (1'd0), + .RXDFEAGCOVRDEN (1'd0), + .RXDFECFOKFCNUM (4'b1101), + .RXDFECFOKFEN (1'd0), + .RXDFECFOKFPULSE (1'd0), + .RXDFECFOKHOLD (1'd0), + .RXDFECFOKOVREN (1'd0), + .RXDFEKHHOLD (1'd0), + .RXDFEKHOVRDEN (1'd0), + .RXDFELFHOLD (1'd0), + .RXDFELFOVRDEN (1'd0), + .RXDFELPMRESET (1'd0), + .RXDFETAP10HOLD (1'd0), + .RXDFETAP10OVRDEN (1'd0), + .RXDFETAP11HOLD (1'd0), + .RXDFETAP11OVRDEN (1'd0), + .RXDFETAP12HOLD (1'd0), + .RXDFETAP12OVRDEN (1'd0), + .RXDFETAP13HOLD (1'd0), + .RXDFETAP13OVRDEN (1'd0), + .RXDFETAP14HOLD (1'd0), + .RXDFETAP14OVRDEN (1'd0), + .RXDFETAP15HOLD (1'd0), + .RXDFETAP15OVRDEN (1'd0), + .RXDFETAP2HOLD (1'd0), + .RXDFETAP2OVRDEN (1'd0), + .RXDFETAP3HOLD (1'd0), + .RXDFETAP3OVRDEN (1'd0), + .RXDFETAP4HOLD (1'd0), + .RXDFETAP4OVRDEN (1'd0), + .RXDFETAP5HOLD (1'd0), + .RXDFETAP5OVRDEN (1'd0), + .RXDFETAP6HOLD (1'd0), + .RXDFETAP6OVRDEN (1'd0), + .RXDFETAP7HOLD (1'd0), + .RXDFETAP7OVRDEN (1'd0), + .RXDFETAP8HOLD (1'd0), + .RXDFETAP8OVRDEN (1'd0), + .RXDFETAP9HOLD (1'd0), + .RXDFETAP9OVRDEN (1'd0), + .RXDFEUTHOLD (1'd0), + .RXDFEUTOVRDEN (1'd0), + .RXDFEVPHOLD (1'd0), + .RXDFEVPOVRDEN (1'd0), + .RXDFEXYDEN (1'd1), + .RXDLYBYPASS (1'd1), + .RXDLYEN (1'd0), + .RXDLYOVRDEN (1'd0), + .RXDLYSRESET (1'd0), + .RXDLYSRESETDONE (), + .RXELECIDLE (), + .RXELECIDLEMODE (2'b11), + .RXEQTRAINING (1'd0), + .RXGEARBOXSLIP (1'd0), + .RXHEADER (), + .RXHEADERVALID (), + .RXLATCLK (1'd0), + .RXLFPSTRESETDET (), + .RXLFPSU2LPEXITDET (), + .RXLFPSU3WAKEDET (), + .RXLPMEN (up_rx_lpm_dfe_n), + .RXLPMGCHOLD (1'd0), + .RXLPMGCOVRDEN (1'd0), + .RXLPMHFHOLD (1'd0), + .RXLPMHFOVRDEN (1'd0), + .RXLPMLFHOLD (1'd0), + .RXLPMLFKLOVRDEN (1'd0), + .RXLPMOSHOLD (1'd0), + .RXLPMOSOVRDEN (1'd0), + .RXMCOMMAALIGNEN (rx_calign), + .RXMONITOROUT (), + .RXMONITORSEL (2'd0), + .RXOOBRESET (1'd0), + .RXOSCALRESET (1'd0), + .RXOSHOLD (1'd0), + .RXOSINTDONE (), + .RXOSINTSTARTED (), + .RXOSINTSTROBEDONE (), + .RXOSINTSTROBESTARTED (), + .RXOSOVRDEN (1'd0), + .RXOUTCLK (rx_out_clk_s), + .RXOUTCLKFABRIC (), + .RXOUTCLKPCS (), + .RXOUTCLKSEL (up_rx_out_clk_sel), + .RXPCOMMAALIGNEN (rx_calign), + .RXPCSRESET (1'd0), + .RXPD (2'd0), + .RXPHALIGN (1'd0), + .RXPHALIGNDONE (), + .RXPHALIGNEN (1'd0), + .RXPHALIGNERR (), + .RXPHDLYPD (1'd1), + .RXPHDLYRESET (1'd0), + .RXPHOVRDEN (1'd0), + .RXPLLCLKSEL (rx_pll_clk_sel_s), + .RXPMARESET (1'd0), + .RXPMARESETDONE (), + .RXPOLARITY (1'd0), + .RXPRBSCNTRESET (1'd0), + .RXPRBSERR (), + .RXPRBSLOCKED (), + .RXPRBSSEL (4'd0), + .RXPRGDIVRESETDONE (), + .RXPROGDIVRESET (1'd0), + .RXQPIEN (1'd0), + .RXQPISENN (), + .RXQPISENP (), + .RXRATE (rx_rate_m2), + .RXRATEDONE (), + .RXRATEMODE (1'd0), + .RXRECCLKOUT (), + .RXRESETDONE (rx_rst_done_s), + .RXSLIDE (1'd0), + .RXSLIDERDY (), + .RXSLIPDONE (), + .RXSLIPOUTCLK (1'd0), + .RXSLIPOUTCLKRDY (), + .RXSLIPPMA (1'd0), + .RXSLIPPMARDY (), + .RXSTARTOFSEQ (), + .RXSTATUS (), + .RXSYNCALLIN (1'd0), + .RXSYNCDONE (), + .RXSYNCIN (1'd0), + .RXSYNCMODE (1'd0), + .RXSYNCOUT (), + .RXSYSCLKSEL (rx_sys_clk_sel_s), + .RXTERMINATION (1'd0), + .RXUSERRDY (up_rx_user_ready), + .RXUSRCLK (rx_clk), + .RXUSRCLK2 (rx_clk), + .RXVALID (), + .SIGVALIDCLK (1'd0), + .TSTIN (20'd0), + .TX8B10BBYPASS (8'd0), + .TX8B10BEN (1'd1), + .TXBUFSTATUS (), + .TXCOMFINISH (), + .TXCOMINIT (1'd0), + .TXCOMSAS (1'd0), + .TXCOMWAKE (1'd0), + .TXCTRL0 (16'd0), + .TXCTRL1 (16'd0), + .TXCTRL2 ({4'd0, tx_charisk}), + .TXDATA ({96'd0, tx_data}), + .TXDATAEXTENDRSVD (8'd0), + .TXDCCDONE (), + .TXDCCFORCESTART (1'd0), + .TXDCCRESET (1'd0), + .TXDEEMPH (2'd0), + .TXDETECTRX (1'd0), + .TXDIFFCTRL (5'b00000), + .TXDLYBYPASS (1'd1), + .TXDLYEN (1'd0), + .TXDLYHOLD (1'd0), + .TXDLYOVRDEN (1'd0), + .TXDLYSRESET (1'd0), + .TXDLYSRESETDONE (), + .TXDLYUPDOWN (1'd0), + .TXELECIDLE (1'd0), + .TXHEADER (6'd0), + .TXINHIBIT (1'd0), + .TXLATCLK (1'd0), + .TXLFPSTRESET (1'd0), + .TXLFPSU2LPEXIT (1'd0), + .TXLFPSU3WAKE (1'd0), + .TXMAINCURSOR (7'b1000000), + .TXMARGIN (3'd0), + .TXMUXDCDEXHOLD (1'd0), + .TXMUXDCDORWREN (1'd0), + .TXONESZEROS (1'd0), + .TXOUTCLK (tx_out_clk_s), + .TXOUTCLKFABRIC (), + .TXOUTCLKPCS (), + .TXOUTCLKSEL (up_tx_out_clk_sel), + .TXPCSRESET (1'd0), + .TXPD (2'd0), + .TXPDELECIDLEMODE (1'd0), + .TXPHALIGN (1'd0), + .TXPHALIGNDONE (), + .TXPHALIGNEN (1'd0), + .TXPHDLYPD (1'd1), + .TXPHDLYRESET (1'd0), + .TXPHDLYTSTCLK (1'd0), + .TXPHINIT (1'd0), + .TXPHINITDONE (), + .TXPHOVRDEN (1'd0), + .TXPIPPMEN (1'd0), + .TXPIPPMOVRDEN (1'd0), + .TXPIPPMPD (1'd0), + .TXPIPPMSEL (1'd0), + .TXPIPPMSTEPSIZE (5'd0), + .TXPISOPD (1'd0), + .TXPLLCLKSEL (tx_pll_clk_sel_s), + .TXPMARESET (1'd0), + .TXPMARESETDONE (), + .TXPOLARITY (1'd0), + .TXPOSTCURSOR (5'd0), + .TXPRBSFORCEERR (1'd0), + .TXPRBSSEL (4'd0), + .TXPRECURSOR (5'd0), + .TXPRGDIVRESETDONE (), + .TXPROGDIVRESET (up_tx_rst), + .TXQPIBIASEN (1'd0), + .TXQPISENN (), + .TXQPISENP (), + .TXQPIWEAKPUP (1'd0), + .TXRATE (tx_rate_m2), + .TXRATEDONE (), + .TXRATEMODE (1'd0), + .TXRESETDONE (tx_rst_done_s), + .TXSEQUENCE (7'd0), + .TXSWING (1'd0), + .TXSYNCALLIN (1'd0), + .TXSYNCDONE (), + .TXSYNCIN (1'd0), + .TXSYNCMODE (1'd0), + .TXSYNCOUT (), + .TXSYSCLKSEL (tx_sys_clk_sel_s), + .TXUSERRDY (up_tx_user_ready), + .TXUSRCLK (tx_clk), + .TXUSRCLK2 (tx_clk)); + end + endgenerate + +endmodule + +// *************************************************************************** +// *************************************************************************** + diff --git a/library/xilinx/util_adxcvr/util_adxcvr_xcm.v b/library/xilinx/util_adxcvr/util_adxcvr_xcm.v new file mode 100644 index 000000000..75128cb50 --- /dev/null +++ b/library/xilinx/util_adxcvr/util_adxcvr_xcm.v @@ -0,0 +1,509 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/1ps + +module util_adxcvr_xcm #( + + // parameters + + parameter integer XCVR_ID = 0, + parameter integer XCVR_TYPE = 0, + parameter integer QPLL_REFCLK_DIV = 1, + parameter integer QPLL_FBDIV_RATIO = 1, + parameter [26:0] QPLL_CFG = 27'h0680181, + parameter [ 9:0] QPLL_FBDIV = 10'b0000110000) ( + + // reset and clocks + + input qpll_ref_clk, + output qpll2ch_clk, + output qpll2ch_ref_clk, + output qpll2ch_locked, + + // drp interface + + input up_rstn, + input up_clk, + input up_qpll_rst, + input [ 7:0] up_cm_sel, + input up_cm_enb, + input [11:0] up_cm_addr, + input up_cm_wr, + input [15:0] up_cm_wdata, + output [15:0] up_cm_rdata, + output up_cm_ready); + + // internal registers + + reg up_enb_int = 'd0; + reg [11:0] up_addr_int = 'd0; + reg up_wr_int = 'd0; + reg [15:0] up_wdata_int = 'd0; + reg [15:0] up_rdata_int = 'd0; + reg up_ready_int = 'd0; + + // internal signals + + wire [15:0] up_rdata_s; + wire up_ready_s; + + // drp access + + assign up_cm_rdata = up_rdata_int; + assign up_cm_ready = up_ready_int; + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 1'b0) begin + up_enb_int <= 1'd0; + up_addr_int <= 12'd0; + up_wr_int <= 1'd0; + up_wdata_int <= 16'd0; + up_rdata_int <= 16'd0; + up_ready_int <= 1'd0; + end else begin + if ((up_cm_sel == XCVR_ID) || (up_cm_sel == 8'hff)) begin + up_enb_int <= up_cm_enb; + up_addr_int <= up_cm_addr; + up_wr_int <= up_cm_wr; + up_wdata_int <= up_cm_wdata; + up_rdata_int <= up_rdata_s; + up_ready_int <= up_ready_s; + end else begin + up_enb_int <= 1'd0; + up_addr_int <= 12'd0; + up_wr_int <= 1'd0; + up_wdata_int <= 16'd0; + up_rdata_int <= 16'd0; + up_ready_int <= 1'd0; + end + end + end + + // instantiations + + generate + if (XCVR_TYPE == 0) begin + GTXE2_COMMON #( + .BIAS_CFG (64'h0000040000001000), + .COMMON_CFG (32'h00000000), + .IS_DRPCLK_INVERTED (1'b0), + .IS_GTGREFCLK_INVERTED (1'b0), + .IS_QPLLLOCKDETCLK_INVERTED (1'b0), + .QPLL_CFG (QPLL_CFG), + .QPLL_CLKOUT_CFG (4'b0000), + .QPLL_COARSE_FREQ_OVRD (6'b010000), + .QPLL_COARSE_FREQ_OVRD_EN (1'b0), + .QPLL_CP (10'b0000011111), + .QPLL_CP_MONITOR_EN (1'b0), + .QPLL_DMONITOR_SEL (1'b0), + .QPLL_FBDIV (QPLL_FBDIV), + .QPLL_FBDIV_MONITOR_EN (1'b0), + .QPLL_FBDIV_RATIO (QPLL_FBDIV_RATIO), + .QPLL_INIT_CFG (24'h000006), + .QPLL_LOCK_CFG (16'h21E8), + .QPLL_LPF (4'b1111), + .QPLL_REFCLK_DIV (QPLL_REFCLK_DIV), + .SIM_QPLLREFCLK_SEL (3'b001), + .SIM_RESET_SPEEDUP ("TRUE"), + .SIM_VERSION ("4.0")) + i_gtxe2_common ( + .QPLLDMONITOR (), + .QPLLFBCLKLOST (), + .REFCLKOUTMONITOR (), + .BGBYPASSB (1'h1), + .BGMONITORENB (1'h1), + .BGPDB (1'h1), + .BGRCALOVRD (5'h1f), + .DRPADDR (up_addr_int[7:0]), + .DRPCLK (up_clk), + .DRPDI (up_wdata_int), + .DRPDO (up_rdata_s), + .DRPEN (up_enb_int), + .DRPRDY (up_ready_s), + .DRPWE (up_wr_int), + .GTGREFCLK (1'h0), + .GTNORTHREFCLK0 (1'h0), + .GTNORTHREFCLK1 (1'h0), + .GTREFCLK0 (qpll_ref_clk), + .GTREFCLK1 (1'h0), + .GTSOUTHREFCLK0 (1'h0), + .GTSOUTHREFCLK1 (1'h0), + .PMARSVD (8'h0), + .QPLLLOCK (qpll2ch_locked), + .QPLLLOCKDETCLK (up_clk), + .QPLLLOCKEN (1'h1), + .QPLLOUTCLK (qpll2ch_clk), + .QPLLOUTREFCLK (qpll2ch_ref_clk), + .QPLLOUTRESET (1'h0), + .QPLLPD (1'h0), + .QPLLREFCLKLOST (), + .QPLLREFCLKSEL (3'h1), + .QPLLRESET (up_qpll_rst), + .QPLLRSVD1 (16'h0), + .QPLLRSVD2 (5'h1f), + .RCALENB (1'h1)); + end + endgenerate + + generate + if (XCVR_TYPE == 1) begin + GTHE3_COMMON #( + .BIAS_CFG0 (16'h0000), + .BIAS_CFG1 (16'h0000), + .BIAS_CFG2 (16'h0000), + .BIAS_CFG3 (16'h0040), + .BIAS_CFG4 (16'h0000), + .BIAS_CFG_RSVD (10'b0000000000), + .COMMON_CFG0 (16'h0000), + .COMMON_CFG1 (16'h0000), + .POR_CFG (16'h0004), + .QPLL0_CFG0 (16'h321c), + .QPLL0_CFG1 (16'h1018), + .QPLL0_CFG1_G3 (16'h1018), + .QPLL0_CFG2 (16'h0048), + .QPLL0_CFG2_G3 (16'h0048), + .QPLL0_CFG3 (16'h0120), + .QPLL0_CFG4 (16'h0000), + .QPLL0_CP (10'b0000011111), + .QPLL0_CP_G3 (10'b1111111111), + .QPLL0_FBDIV (QPLL_FBDIV), + .QPLL0_FBDIV_G3 (80), + .QPLL0_INIT_CFG0 (16'h02b2), + .QPLL0_INIT_CFG1 (8'h00), + .QPLL0_LOCK_CFG (16'h21e8), + .QPLL0_LOCK_CFG_G3 (16'h21e8), + .QPLL0_LPF (10'b1111111111), + .QPLL0_LPF_G3 (10'b0000010101), + .QPLL0_REFCLK_DIV (QPLL_REFCLK_DIV), + .QPLL0_SDM_CFG0 (16'b0000000000000000), + .QPLL0_SDM_CFG1 (16'b0000000000000000), + .QPLL0_SDM_CFG2 (16'b0000000000000000), + .QPLL1_CFG0 (16'h321c), + .QPLL1_CFG1 (16'h1018), + .QPLL1_CFG1_G3 (16'h1018), + .QPLL1_CFG2 (16'h0040), + .QPLL1_CFG2_G3 (16'h0040), + .QPLL1_CFG3 (16'h0120), + .QPLL1_CFG4 (16'h0000), + .QPLL1_CP (10'b0000011111), + .QPLL1_CP_G3 (10'b1111111111), + .QPLL1_FBDIV (QPLL_FBDIV), + .QPLL1_FBDIV_G3 (80), + .QPLL1_INIT_CFG0 (16'h02b2), + .QPLL1_INIT_CFG1 (8'h00), + .QPLL1_LOCK_CFG (16'h21e8), + .QPLL1_LOCK_CFG_G3 (16'h21e8), + .QPLL1_LPF (10'b1111111111), + .QPLL1_LPF_G3 (10'b0000010101), + .QPLL1_REFCLK_DIV (QPLL_REFCLK_DIV), + .QPLL1_SDM_CFG0 (16'b0000000000000000), + .QPLL1_SDM_CFG1 (16'b0000000000000000), + .QPLL1_SDM_CFG2 (16'b0000000000000000), + .RSVD_ATTR0 (16'h0000), + .RSVD_ATTR1 (16'h0000), + .RSVD_ATTR2 (16'h0000), + .RSVD_ATTR3 (16'h0000), + .RXRECCLKOUT0_SEL (2'b00), + .RXRECCLKOUT1_SEL (2'b00), + .SARC_EN (1'b1), + .SARC_SEL (1'b0), + .SDM0DATA1_0 (16'b0000000000000000), + .SDM0DATA1_1 (9'b000000000), + .SDM0INITSEED0_0 (16'b0000000000000000), + .SDM0INITSEED0_1 (9'b000000000), + .SDM0_DATA_PIN_SEL (1'b0), + .SDM0_WIDTH_PIN_SEL (1'b0), + .SDM1DATA1_0 (16'b0000000000000000), + .SDM1DATA1_1 (9'b000000000), + .SDM1INITSEED0_0 (16'b0000000000000000), + .SDM1INITSEED0_1 (9'b000000000), + .SDM1_DATA_PIN_SEL (1'b0), + .SDM1_WIDTH_PIN_SEL (1'b0), + .SIM_MODE ("FAST"), + .SIM_RESET_SPEEDUP ("TRUE"), + .SIM_VERSION (2)) + i_gthe3_common ( + .BGBYPASSB (1'h1), + .BGMONITORENB (1'h1), + .BGPDB (1'h1), + .BGRCALOVRD (5'h1f), + .BGRCALOVRDENB (1'h1), + .DRPADDR (up_addr_int[8:0]), + .DRPCLK (up_clk), + .DRPDI (up_wdata_int), + .DRPDO (up_rdata_s), + .DRPEN (up_enb_int), + .DRPRDY (up_ready_s), + .DRPWE (up_wr_int), + .GTGREFCLK0 (1'h0), + .GTGREFCLK1 (1'h0), + .GTNORTHREFCLK00 (1'h0), + .GTNORTHREFCLK01 (1'h0), + .GTNORTHREFCLK10 (1'h0), + .GTNORTHREFCLK11 (1'h0), + .GTREFCLK00 (qpll_ref_clk), + .GTREFCLK01 (1'h0), + .GTREFCLK10 (1'h0), + .GTREFCLK11 (1'h0), + .GTSOUTHREFCLK00 (1'h0), + .GTSOUTHREFCLK01 (1'h0), + .GTSOUTHREFCLK10 (1'h0), + .GTSOUTHREFCLK11 (1'h0), + .PMARSVD0 (8'h0), + .PMARSVD1 (8'h0), + .PMARSVDOUT0 (), + .PMARSVDOUT1 (), + .QPLL0CLKRSVD0 (1'h0), + .QPLL0CLKRSVD1 (1'h0), + .QPLL0FBCLKLOST (), + .QPLL0LOCK (qpll2ch_locked), + .QPLL0LOCKDETCLK (up_clk), + .QPLL0LOCKEN (1'h1), + .QPLL0OUTCLK (qpll2ch_clk), + .QPLL0OUTREFCLK (qpll2ch_ref_clk), + .QPLL0PD (1'h0), + .QPLL0REFCLKLOST (), + .QPLL0REFCLKSEL (3'h1), + .QPLL0RESET (up_qpll_rst), + .QPLL1CLKRSVD0 (1'h0), + .QPLL1CLKRSVD1 (1'h0), + .QPLL1FBCLKLOST (), + .QPLL1LOCK (), + .QPLL1LOCKDETCLK (1'h0), + .QPLL1LOCKEN (1'h0), + .QPLL1OUTCLK (), + .QPLL1OUTREFCLK (), + .QPLL1PD (1'h0), + .QPLL1REFCLKLOST (), + .QPLL1REFCLKSEL (3'h1), + .QPLL1RESET (1'h1), + .QPLLDMONITOR0 (), + .QPLLDMONITOR1 (), + .QPLLRSVD1 (8'h0), + .QPLLRSVD2 (5'h0), + .QPLLRSVD3 (5'h0), + .QPLLRSVD4 (8'h0), + .RCALENB (1'h1), + .REFCLKOUTMONITOR0 (), + .REFCLKOUTMONITOR1 (), + .RXRECCLK0_SEL (), + .RXRECCLK1_SEL ()); + end + endgenerate + + generate + if (XCVR_TYPE == 2) begin + GTHE4_COMMON #( + .AEN_QPLL0_FBDIV (1'b1), + .AEN_QPLL1_FBDIV (1'b1), + .AEN_SDM0TOGGLE (1'b0), + .AEN_SDM1TOGGLE (1'b0), + .A_SDM0TOGGLE (1'b0), + .A_SDM1DATA_HIGH (9'b000000000), + .A_SDM1DATA_LOW (16'b0000000000000000), + .A_SDM1TOGGLE (1'b0), + .BIAS_CFG0 (16'h0000), + .BIAS_CFG1 (16'h0000), + .BIAS_CFG2 (16'h0124), + .BIAS_CFG3 (16'h0041), + .BIAS_CFG4 (16'h0010), + .BIAS_CFG_RSVD (16'h0000), + .COMMON_CFG0 (16'h0000), + .COMMON_CFG1 (16'h0000), + .POR_CFG (16'h0006), + .PPF0_CFG (16'h0600), + .PPF1_CFG (16'h0600), + .QPLL0CLKOUT_RATE ("HALF"), + .QPLL0_CFG0 (16'h331c), + .QPLL0_CFG1 (16'hd038), + .QPLL0_CFG1_G3 (16'hd038), + .QPLL0_CFG2 (16'h0fc0), + .QPLL0_CFG2_G3 (16'h0fc0), + .QPLL0_CFG3 (16'h0120), + .QPLL0_CFG4 (16'h0003), + .QPLL0_CP (10'b0001111111), + .QPLL0_CP_G3 (10'b0000011111), + .QPLL0_FBDIV (QPLL_FBDIV), + .QPLL0_FBDIV_G3 (160), + .QPLL0_INIT_CFG0 (16'h02b2), + .QPLL0_INIT_CFG1 (8'h00), + .QPLL0_LOCK_CFG (16'h25e8), + .QPLL0_LOCK_CFG_G3 (16'h25e8), + .QPLL0_LPF (10'b0100110111), + .QPLL0_LPF_G3 (10'b0111010101), + .QPLL0_PCI_EN (1'b0), + .QPLL0_RATE_SW_USE_DRP (1'b1), + .QPLL0_REFCLK_DIV (QPLL_REFCLK_DIV), + .QPLL0_SDM_CFG0 (16'h0080), + .QPLL0_SDM_CFG1 (16'h0000), + .QPLL0_SDM_CFG2 (16'h0000), + .QPLL1CLKOUT_RATE ("HALF"), + .QPLL1_CFG0 (16'h331c), + .QPLL1_CFG1 (16'hd038), + .QPLL1_CFG1_G3 (16'hd038), + .QPLL1_CFG2 (16'h0fc0), + .QPLL1_CFG2_G3 (16'h0fc0), + .QPLL1_CFG3 (16'h0120), + .QPLL1_CFG4 (16'h0003), + .QPLL1_CP (10'b1111111111), + .QPLL1_CP_G3 (10'b0011111111), + .QPLL1_FBDIV (QPLL_FBDIV), + .QPLL1_FBDIV_G3 (80), + .QPLL1_INIT_CFG0 (16'h02b2), + .QPLL1_INIT_CFG1 (8'h00), + .QPLL1_LOCK_CFG (16'h25e8), + .QPLL1_LOCK_CFG_G3 (16'h25e8), + .QPLL1_LPF (10'b0100110101), + .QPLL1_LPF_G3 (10'b0111010100), + .QPLL1_PCI_EN (1'b0), + .QPLL1_RATE_SW_USE_DRP (1'b1), + .QPLL1_REFCLK_DIV (QPLL_REFCLK_DIV), + .QPLL1_SDM_CFG0 (16'h0080), + .QPLL1_SDM_CFG1 (16'h0000), + .QPLL1_SDM_CFG2 (16'h0000), + .RSVD_ATTR0 (16'h0000), + .RSVD_ATTR1 (16'h0000), + .RSVD_ATTR2 (16'h0000), + .RSVD_ATTR3 (16'h0000), + .RXRECCLKOUT0_SEL (2'b00), + .RXRECCLKOUT1_SEL (2'b00), + .SARC_ENB (1'b0), + .SARC_SEL (1'b0), + .SDM0INITSEED0_0 (16'b0000000100010001), + .SDM0INITSEED0_1 (9'b000010001), + .SDM1INITSEED0_0 (16'b0000000100010001), + .SDM1INITSEED0_1 (9'b000010001), + .SIM_MODE ("FAST"), + .SIM_RESET_SPEEDUP ("TRUE"), + .SIM_VERSION (1'h1)) + i_gthe4_common ( + .BGBYPASSB (1'd1), + .BGMONITORENB (1'd1), + .BGPDB (1'd1), + .BGRCALOVRD (5'b11111), + .BGRCALOVRDENB (1'd1), + .DRPADDR ({4'd0, up_addr_int}), + .DRPCLK (up_clk), + .DRPDI (up_wdata_int), + .DRPDO (up_rdata_s), + .DRPEN (up_enb_int), + .DRPRDY (up_ready_s), + .DRPWE (up_wr_int), + .GTGREFCLK0 (1'd0), + .GTGREFCLK1 (1'd0), + .GTNORTHREFCLK00 (1'd0), + .GTNORTHREFCLK01 (1'd0), + .GTNORTHREFCLK10 (1'd0), + .GTNORTHREFCLK11 (1'd0), + .GTREFCLK00 (qpll_ref_clk), + .GTREFCLK01 (1'd0), + .GTREFCLK10 (1'd0), + .GTREFCLK11 (1'd0), + .GTSOUTHREFCLK00 (1'd0), + .GTSOUTHREFCLK01 (1'd0), + .GTSOUTHREFCLK10 (1'd0), + .GTSOUTHREFCLK11 (1'd0), + .PCIERATEQPLL0 (3'd0), + .PCIERATEQPLL1 (3'd0), + .PMARSVD0 (8'd0), + .PMARSVD1 (8'd0), + .PMARSVDOUT0 (), + .PMARSVDOUT1 (), + .QPLL0CLKRSVD0 (1'd0), + .QPLL0CLKRSVD1 (1'd0), + .QPLL0FBCLKLOST (), + .QPLL0FBDIV (8'd0), + .QPLL0LOCK (qpll2ch_locked), + .QPLL0LOCKDETCLK (up_clk), + .QPLL0LOCKEN (1'd1), + .QPLL0OUTCLK (qpll2ch_clk), + .QPLL0OUTREFCLK (qpll2ch_ref_clk), + .QPLL0PD (1'd0), + .QPLL0REFCLKLOST (), + .QPLL0REFCLKSEL (3'b001), + .QPLL0RESET (up_qpll_rst), + .QPLL1CLKRSVD0 (1'd0), + .QPLL1CLKRSVD1 (1'd0), + .QPLL1FBCLKLOST (), + .QPLL1FBDIV (8'd0), + .QPLL1LOCK (), + .QPLL1LOCKDETCLK (1'd0), + .QPLL1LOCKEN (1'd0), + .QPLL1OUTCLK (), + .QPLL1OUTREFCLK (), + .QPLL1PD (1'd1), + .QPLL1REFCLKLOST (), + .QPLL1REFCLKSEL (3'b001), + .QPLL1RESET (1'd1), + .QPLLDMONITOR0 (), + .QPLLDMONITOR1 (), + .QPLLRSVD1 (8'd0), + .QPLLRSVD2 (5'd0), + .QPLLRSVD3 (5'd0), + .QPLLRSVD4 (8'd0), + .RCALENB (1'd1), + .REFCLKOUTMONITOR0 (), + .REFCLKOUTMONITOR1 (), + .RXRECCLK0SEL (), + .RXRECCLK1SEL (), + .SDM0DATA (25'd0), + .SDM0FINALOUT (), + .SDM0RESET (1'd0), + .SDM0TESTDATA (), + .SDM0TOGGLE (1'd0), + .SDM0WIDTH (2'd0), + .SDM1DATA (25'd0), + .SDM1FINALOUT (), + .SDM1RESET (1'd0), + .SDM1TESTDATA (), + .SDM1TOGGLE (1'd0), + .SDM1WIDTH (2'd0), + .TCONGPI (10'd0), + .TCONGPO (), + .TCONPOWERUP (1'd0), + .TCONRESET (2'd0), + .TCONRSVDIN1 (2'd0), + .TCONRSVDOUT0 ()); + end + endgenerate + +endmodule + +// *************************************************************************** +// *************************************************************************** + diff --git a/projects/Makefile b/projects/Makefile index 75ec31ca4..e3a53b392 100644 --- a/projects/Makefile +++ b/projects/Makefile @@ -8,10 +8,13 @@ .PHONY: all clean clean_all all: -make -C ad6676evb all + -make -C ad7616_sdz all + -make -C ad7768evb all -make -C ad9265_fmc all -make -C ad9434_fmc all -make -C ad9467_fmc all -make -C ad9739a_fmc all + -make -C adrv9371x all -make -C adv7511 all -make -C arradio all -make -C cftl_cip all @@ -25,24 +28,30 @@ all: -make -C fmcadc4 all -make -C fmcadc5 all -make -C fmcjesdadc1 all - -make -C fmcomms1 all + -make -C fmcomms11 all -make -C fmcomms2 all -make -C fmcomms5 all - -make -C fmcomms6 all -make -C fmcomms7 all -make -C imageon all + -make -C m2k all -make -C motcon2_fmc all - -make -C pzsdr all + -make -C pluto all + -make -C pzsdr1 all + -make -C pzsdr2 all -make -C usb_fx3 all -make -C usdrx1 all + -make -C usrpe31x all clean: make -C ad6676evb clean + make -C ad7616_sdz clean + make -C ad7768evb clean make -C ad9265_fmc clean make -C ad9434_fmc clean make -C ad9467_fmc clean make -C ad9739a_fmc clean + make -C adrv9371x clean make -C adv7511 clean make -C arradio clean make -C cftl_cip clean @@ -56,24 +65,30 @@ clean: make -C fmcadc4 clean make -C fmcadc5 clean make -C fmcjesdadc1 clean - make -C fmcomms1 clean + make -C fmcomms11 clean make -C fmcomms2 clean make -C fmcomms5 clean - make -C fmcomms6 clean make -C fmcomms7 clean make -C imageon clean + make -C m2k clean make -C motcon2_fmc clean - make -C pzsdr clean + make -C pluto clean + make -C pzsdr1 clean + make -C pzsdr2 clean make -C usb_fx3 clean make -C usdrx1 clean + make -C usrpe31x clean clean-all: make -C ad6676evb clean-all + make -C ad7616_sdz clean-all + make -C ad7768evb clean-all make -C ad9265_fmc clean-all make -C ad9434_fmc clean-all make -C ad9467_fmc clean-all make -C ad9739a_fmc clean-all + make -C adrv9371x clean-all make -C adv7511 clean-all make -C arradio clean-all make -C cftl_cip clean-all @@ -87,16 +102,19 @@ clean-all: make -C fmcadc4 clean-all make -C fmcadc5 clean-all make -C fmcjesdadc1 clean-all - make -C fmcomms1 clean-all + make -C fmcomms11 clean-all make -C fmcomms2 clean-all make -C fmcomms5 clean-all - make -C fmcomms6 clean-all make -C fmcomms7 clean-all make -C imageon clean-all + make -C m2k clean-all make -C motcon2_fmc clean-all - make -C pzsdr clean-all + make -C pluto clean-all + make -C pzsdr1 clean-all + make -C pzsdr2 clean-all make -C usb_fx3 clean-all make -C usdrx1 clean-all + make -C usrpe31x clean-all #################################################################################### #################################################################################### diff --git a/projects/ad6676evb/common/ad6676evb_bd.tcl b/projects/ad6676evb/common/ad6676evb_bd.tcl index 11d73bd7f..0990c2bc4 100644 --- a/projects/ad6676evb/common/ad6676evb_bd.tcl +++ b/projects/ad6676evb/common/ad6676evb_bd.tcl @@ -1,48 +1,22 @@ -# ad6676 - -create_bd_port -dir I rx_ref_clk -create_bd_port -dir O rx_sync -create_bd_port -dir O rx_sysref -create_bd_port -dir I -from 1 -to 0 rx_data_p -create_bd_port -dir I -from 1 -to 0 rx_data_n - # adc peripherals -set axi_ad6676_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad6676:1.0 axi_ad6676_core] +set axi_ad6676_xcvr [create_bd_cell -type ip -vlnv analog.com:user:axi_adxcvr:1.0 axi_ad6676_xcvr] +set_property -dict [list CONFIG.NUM_OF_LANES {2}] $axi_ad6676_xcvr +set_property -dict [list CONFIG.QPLL_ENABLE {0}] $axi_ad6676_xcvr +set_property -dict [list CONFIG.TX_OR_RX_N {0}] $axi_ad6676_xcvr +set_property -dict [list CONFIG.LPM_OR_DFE_N {0}] $axi_ad6676_xcvr +set_property -dict [list CONFIG.SYS_CLK_SEL {"00"}] $axi_ad6676_xcvr +set_property -dict [list CONFIG.OUT_CLK_SEL {"100"}] $axi_ad6676_xcvr -set axi_ad6676_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.2 axi_ad6676_jesd] +set axi_ad6676_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:7.0 axi_ad6676_jesd] set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad6676_jesd set_property -dict [list CONFIG.C_LANES {2}] $axi_ad6676_jesd -set axi_ad6676_gt [create_bd_cell -type ip -vlnv analog.com:user:axi_jesd_gt:1.0 axi_ad6676_gt] -set_property -dict [list CONFIG.NUM_OF_LANES {2}] $axi_ad6676_gt -set_property -dict [list CONFIG.QPLL0_ENABLE {0}] $axi_ad6676_gt -set_property -dict [list CONFIG.QPLL1_ENABLE {0}] $axi_ad6676_gt -set_property -dict [list CONFIG.RX_NUM_OF_LANES {2}] $axi_ad6676_gt -set_property -dict [list CONFIG.TX_NUM_OF_LANES {0}] $axi_ad6676_gt -set_property -dict [list CONFIG.CPLL_FBDIV_0 {2}] $axi_ad6676_gt -set_property -dict [list CONFIG.RX_OUT_DIV_0 {1}] $axi_ad6676_gt -set_property -dict [list CONFIG.TX_OUT_DIV_0 {1}] $axi_ad6676_gt -set_property -dict [list CONFIG.RX_CLK25_DIV_0 {13}] $axi_ad6676_gt -set_property -dict [list CONFIG.TX_CLK25_DIV_0 {13}] $axi_ad6676_gt -set_property -dict [list CONFIG.PMA_RSV_0 {0x00018480}] $axi_ad6676_gt -set_property -dict [list CONFIG.RX_CDR_CFG_0 {0x03000023ff20400020}] $axi_ad6676_gt -set_property -dict [list CONFIG.CPLL_FBDIV_1 {2}] $axi_ad6676_gt -set_property -dict [list CONFIG.RX_OUT_DIV_1 {1}] $axi_ad6676_gt -set_property -dict [list CONFIG.TX_OUT_DIV_1 {1}] $axi_ad6676_gt -set_property -dict [list CONFIG.RX_CLK25_DIV_1 {13}] $axi_ad6676_gt -set_property -dict [list CONFIG.TX_CLK25_DIV_1 {13}] $axi_ad6676_gt -set_property -dict [list CONFIG.PMA_RSV_1 {0x00018480}] $axi_ad6676_gt -set_property -dict [list CONFIG.RX_CDR_CFG_1 {0x03000023ff20400020}] $axi_ad6676_gt +set axi_ad6676_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad6676:1.0 axi_ad6676_core] -set util_ad6676_gt [create_bd_cell -type ip -vlnv analog.com:user:util_jesd_gt:1.0 util_ad6676_gt] -set_property -dict [list CONFIG.QPLL0_ENABLE {0}] $util_ad6676_gt -set_property -dict [list CONFIG.QPLL1_ENABLE {0}] $util_ad6676_gt -set_property -dict [list CONFIG.NUM_OF_LANES {2}] $util_ad6676_gt -set_property -dict [list CONFIG.RX_ENABLE {1}] $util_ad6676_gt -set_property -dict [list CONFIG.RX_NUM_OF_LANES {2}] $util_ad6676_gt -set_property -dict [list CONFIG.TX_ENABLE {0}] $util_ad6676_gt +set axi_ad6676_cpack [create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 axi_ad6676_cpack] +set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $axi_ad6676_cpack set axi_ad6676_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad6676_dma] set_property -dict [list CONFIG.DMA_TYPE_SRC {2}] $axi_ad6676_dma @@ -57,71 +31,63 @@ set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad6676_dma set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {64}] $axi_ad6676_dma set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $axi_ad6676_dma -set adc_pack [create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 adc_pack] -set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $adc_pack +# transceiver core -# connections (gt) +set util_ad6676_xcvr [create_bd_cell -type ip -vlnv analog.com:user:util_adxcvr:1.0 util_ad6676_xcvr] +set_property -dict [list CONFIG.QPLL_FBDIV {"0010000000"}] $util_ad6676_xcvr +set_property -dict [list CONFIG.CPLL_FBDIV {2}] $util_ad6676_xcvr +set_property -dict [list CONFIG.CPLL_FBDIV_4_5 {5}] $util_ad6676_xcvr +set_property -dict [list CONFIG.TX_NUM_OF_LANES {0}] $util_ad6676_xcvr +set_property -dict [list CONFIG.RX_NUM_OF_LANES {2}] $util_ad6676_xcvr +set_property -dict [list CONFIG.RX_OUT_DIV {1}] $util_ad6676_xcvr +set_property -dict [list CONFIG.RX_CLK25_DIV {8}] $util_ad6676_xcvr +set_property -dict [list CONFIG.RX_DFE_LPM_CFG {0x0904}] $util_ad6676_xcvr +set_property -dict [list CONFIG.RX_CDR_CFG {0x03000023ff20400020}] $util_ad6676_xcvr -ad_connect util_ad6676_gt/qpll_ref_clk rx_ref_clk -ad_connect util_ad6676_gt/cpll_ref_clk rx_ref_clk +# reference clocks & resets -ad_connect axi_ad6676_gt/gt_pll_0 util_ad6676_gt/gt_pll_0 -ad_connect axi_ad6676_gt/gt_pll_1 util_ad6676_gt/gt_pll_1 +create_bd_port -dir I rx_ref_clk_0 +create_bd_port -dir O rx_core_clk -ad_connect axi_ad6676_gt/gt_rx_0 util_ad6676_gt/gt_rx_0 -ad_connect axi_ad6676_gt/gt_rx_1 util_ad6676_gt/gt_rx_1 - -ad_connect axi_ad6676_gt/gt_rx_ip_0 axi_ad6676_jesd/gt0_rx -ad_connect axi_ad6676_gt/gt_rx_ip_1 axi_ad6676_jesd/gt1_rx - -ad_connect axi_ad6676_gt/rx_gt_comma_align_enb_0 axi_ad6676_jesd/rxencommaalign_out -ad_connect axi_ad6676_gt/rx_gt_comma_align_enb_1 axi_ad6676_jesd/rxencommaalign_out +ad_xcvrpll rx_ref_clk_0 util_ad6676_xcvr/qpll_ref_clk_* +ad_xcvrpll rx_ref_clk_0 util_ad6676_xcvr/cpll_ref_clk_* +ad_xcvrpll axi_ad6676_xcvr/up_pll_rst util_ad6676_xcvr/up_qpll_rst_* +ad_xcvrpll axi_ad6676_xcvr/up_pll_rst util_ad6676_xcvr/up_cpll_rst_* +ad_connect sys_cpu_resetn util_ad6676_xcvr/up_rstn +ad_connect sys_cpu_clk util_ad6676_xcvr/up_clk # connections (adc) -ad_connect util_ad6676_gt/rx_p rx_data_p -ad_connect util_ad6676_gt/rx_n rx_data_n -ad_connect util_ad6676_gt/rx_sync rx_sync -ad_connect util_ad6676_gt/rx_ip_sysref rx_sysref - -ad_connect util_ad6676_gt/rx_out_clk util_ad6676_gt/rx_clk -ad_connect util_ad6676_gt/rx_out_clk axi_ad6676_jesd/rx_core_clk -ad_connect util_ad6676_gt/rx_ip_rst axi_ad6676_jesd/rx_reset -ad_connect util_ad6676_gt/rx_ip_rst_done axi_ad6676_jesd/rx_reset_done -ad_connect util_ad6676_gt/rx_ip_sysref axi_ad6676_jesd/rx_sysref -ad_connect util_ad6676_gt/rx_ip_sync axi_ad6676_jesd/rx_sync -ad_connect util_ad6676_gt/rx_ip_sof axi_ad6676_jesd/rx_start_of_frame -ad_connect util_ad6676_gt/rx_ip_data axi_ad6676_jesd/rx_tdata - -ad_connect axi_ad6676_core/adc_clk adc_pack/adc_clk -ad_connect axi_ad6676_core/adc_rst adc_pack/adc_rst -ad_connect util_ad6676_gt/rx_out_clk axi_ad6676_core/rx_clk -ad_connect util_ad6676_gt/rx_data axi_ad6676_core/rx_data - -ad_connect axi_ad6676_core/adc_enable_a adc_pack/adc_enable_0 -ad_connect axi_ad6676_core/adc_valid_a adc_pack/adc_valid_0 -ad_connect axi_ad6676_core/adc_data_a adc_pack/adc_data_0 -ad_connect axi_ad6676_core/adc_enable_b adc_pack/adc_enable_1 -ad_connect axi_ad6676_core/adc_valid_b adc_pack/adc_valid_1 -ad_connect axi_ad6676_core/adc_data_b adc_pack/adc_data_1 - -ad_connect axi_ad6676_core/adc_clk axi_ad6676_dma/fifo_wr_clk -ad_connect axi_ad6676_dma/fifo_wr_en adc_pack/adc_valid -ad_connect axi_ad6676_dma/fifo_wr_sync adc_pack/adc_sync -ad_connect axi_ad6676_dma/fifo_wr_din adc_pack/adc_data -ad_connect axi_ad6676_core/adc_dovf axi_ad6676_dma/fifo_wr_overflow +ad_xcvrcon util_ad6676_xcvr axi_ad6676_xcvr axi_ad6676_jesd +ad_connect util_ad6676_xcvr/rx_out_clk_0 axi_ad6676_core/rx_clk +ad_connect util_ad6676_xcvr/rx_out_clk_0 rx_core_clk +ad_connect axi_ad6676_jesd/rx_start_of_frame axi_ad6676_core/rx_sof +ad_connect axi_ad6676_jesd/rx_tdata axi_ad6676_core/rx_data +ad_connect util_ad6676_xcvr/rx_out_clk_0 axi_ad6676_cpack/adc_clk +ad_connect axi_ad6676_jesd_rstgen/peripheral_reset axi_ad6676_cpack/adc_rst +ad_connect axi_ad6676_core/adc_enable_0 axi_ad6676_cpack/adc_enable_0 +ad_connect axi_ad6676_core/adc_valid_0 axi_ad6676_cpack/adc_valid_0 +ad_connect axi_ad6676_core/adc_data_0 axi_ad6676_cpack/adc_data_0 +ad_connect axi_ad6676_core/adc_enable_1 axi_ad6676_cpack/adc_enable_1 +ad_connect axi_ad6676_core/adc_valid_1 axi_ad6676_cpack/adc_valid_1 +ad_connect axi_ad6676_core/adc_data_1 axi_ad6676_cpack/adc_data_1 +ad_connect axi_ad6676_core/adc_clk axi_ad6676_dma/fifo_wr_clk +ad_connect axi_ad6676_dma/fifo_wr_en axi_ad6676_cpack/adc_valid +ad_connect axi_ad6676_dma/fifo_wr_sync axi_ad6676_cpack/adc_sync +ad_connect axi_ad6676_dma/fifo_wr_din axi_ad6676_cpack/adc_data +ad_connect axi_ad6676_core/adc_dovf axi_ad6676_dma/fifo_wr_overflow # interconnect (cpu) -ad_cpu_interconnect 0x44A60000 axi_ad6676_gt +ad_cpu_interconnect 0x44A60000 axi_ad6676_xcvr ad_cpu_interconnect 0x44A10000 axi_ad6676_core ad_cpu_interconnect 0x44A91000 axi_ad6676_jesd ad_cpu_interconnect 0x7c420000 axi_ad6676_dma -# gt uses hp3, and 100MHz clock for both DRP and AXI4 +# xcvr uses hp3, and 100MHz clock for both DRP and AXI4 ad_mem_hp3_interconnect sys_cpu_clk sys_ps7/S_AXI_HP3 -ad_mem_hp3_interconnect sys_cpu_clk axi_ad6676_gt/m_axi +ad_mem_hp3_interconnect sys_cpu_clk axi_ad6676_xcvr/m_axi # interconnect (adc) diff --git a/projects/ad6676evb/vc707/Makefile b/projects/ad6676evb/vc707/Makefile index 5e0c9487c..d7ab4a93c 100644 --- a/projects/ad6676evb/vc707/Makefile +++ b/projects/ad6676evb/vc707/Makefile @@ -16,12 +16,13 @@ M_DEPS += ../../scripts/adi_board.tcl M_DEPS += ../../common/vc707/vc707_system_mig.prj M_DEPS += ../../common/vc707/vc707_system_constr.xdc M_DEPS += ../../common/vc707/vc707_system_bd.tcl -M_DEPS += ../../../library/common/ad_iobuf.v +M_DEPS += ../../../library/xilinx/common/ad_iobuf.v +M_DEPS += ../../../library/common/ad_sysref_gen.v M_DEPS += ../../../library/axi_ad6676/axi_ad6676.xpr +M_DEPS += ../../../library/xilinx/axi_adxcvr/axi_adxcvr.xpr M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr -M_DEPS += ../../../library/axi_jesd_gt/axi_jesd_gt.xpr +M_DEPS += ../../../library/xilinx/util_adxcvr/util_adxcvr.xpr M_DEPS += ../../../library/util_cpack/util_cpack.xpr -M_DEPS += ../../../library/util_jesd_gt/util_jesd_gt.xpr M_VIVADO := vivado -mode batch -source @@ -37,6 +38,7 @@ M_FLIST += *.sdk M_FLIST += *.hw M_FLIST += *.sim M_FLIST += .Xil +M_FLIST += *.ip_user_files @@ -50,23 +52,23 @@ clean: clean-all:clean make -C ../../../library/axi_ad6676 clean + make -C ../../../library/xilinx/axi_adxcvr clean make -C ../../../library/axi_dmac clean - make -C ../../../library/axi_jesd_gt clean + make -C ../../../library/xilinx/util_adxcvr clean make -C ../../../library/util_cpack clean - make -C ../../../library/util_jesd_gt clean ad6676evb_vc707.sdk/system_top.hdf: $(M_DEPS) - rm -rf $(M_FLIST) + -rm -rf $(M_FLIST) $(M_VIVADO) system_project.tcl >> ad6676evb_vc707_vivado.log 2>&1 lib: make -C ../../../library/axi_ad6676 + make -C ../../../library/xilinx/axi_adxcvr make -C ../../../library/axi_dmac - make -C ../../../library/axi_jesd_gt + make -C ../../../library/xilinx/util_adxcvr make -C ../../../library/util_cpack - make -C ../../../library/util_jesd_gt #################################################################################### #################################################################################### diff --git a/projects/ad6676evb/vc707/system_constr.xdc b/projects/ad6676evb/vc707/system_constr.xdc index a7ad92199..2113457bd 100644 --- a/projects/ad6676evb/vc707/system_constr.xdc +++ b/projects/ad6676evb/vc707/system_constr.xdc @@ -17,11 +17,11 @@ set_property -dict {PACKAGE_PIN H41 IOSTANDARD LVCMOS18} [get_ports spi_clk] set_property -dict {PACKAGE_PIN H40 IOSTANDARD LVCMOS18} [get_ports spi_mosi] ; ## H10 FMC_HPC_LA04_P set_property -dict {PACKAGE_PIN M41 IOSTANDARD LVCMOS18} [get_ports spi_miso] ; ## D11 FMC_HPC_LA05_P -set_property -dict {PACKAGE_PIN J42 IOSTANDARD LVCMOS18} [get_ports adc_oen] ; ## C11 FMC_HPC_LA06_N -set_property -dict {PACKAGE_PIN M37 IOSTANDARD LVCMOS18} [get_ports adc_sela] ; ## G12 FMC_HPC_LA08_P -set_property -dict {PACKAGE_PIN M38 IOSTANDARD LVCMOS18} [get_ports adc_selb] ; ## G13 FMC_HPC_LA08_N -set_property -dict {PACKAGE_PIN G41 IOSTANDARD LVCMOS18} [get_ports adc_s0] ; ## H13 FMC_HPC_LA07_P -set_property -dict {PACKAGE_PIN G42 IOSTANDARD LVCMOS18} [get_ports adc_s1] ; ## H14 FMC_HPC_LA07_N +set_property -dict {PACKAGE_PIN J42 IOSTANDARD LVCMOS18} [get_ports adc_oen] ; ## C11 FMC_HPC_LA06_N +set_property -dict {PACKAGE_PIN M37 IOSTANDARD LVCMOS18} [get_ports adc_sela] ; ## G12 FMC_HPC_LA08_P +set_property -dict {PACKAGE_PIN M38 IOSTANDARD LVCMOS18} [get_ports adc_selb] ; ## G13 FMC_HPC_LA08_N +set_property -dict {PACKAGE_PIN G41 IOSTANDARD LVCMOS18} [get_ports adc_s0] ; ## H13 FMC_HPC_LA07_P +set_property -dict {PACKAGE_PIN G42 IOSTANDARD LVCMOS18} [get_ports adc_s1] ; ## H14 FMC_HPC_LA07_N set_property -dict {PACKAGE_PIN K42 IOSTANDARD LVCMOS18} [get_ports adc_resetb] ; ## C10 FMC_HPC_LA06_P set_property -dict {PACKAGE_PIN P41 IOSTANDARD LVCMOS18} [get_ports adc_agc1] ; ## H07 FMC_HPC_LA02_P set_property -dict {PACKAGE_PIN N41 IOSTANDARD LVCMOS18} [get_ports adc_agc2] ; ## H08 FMC_HPC_LA02_N @@ -30,5 +30,11 @@ set_property -dict {PACKAGE_PIN L42 IOSTANDARD LVCMOS18} [get_ports adc_agc4] # clocks -create_clock -name rx_ref_clk -period 3.30 [get_ports rx_ref_clk_p] -create_clock -name rx_div_clk -period 6.60 [get_pins i_system_wrapper/system_i/axi_ad6676_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK] +create_clock -name rx_ref_clk -period 5.00 [get_ports rx_ref_clk_p] +create_clock -name rx_div_clk -period 10.00 [get_pins i_system_wrapper/system_i/util_ad6676_xcvr/inst/i_xch_0/i_gtxe2_channel/RXOUTCLK] + +set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad6676_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]] + +set_property shreg_extract no [get_cells -hier -filter {name =~ *sysref_en_m*}] +set_false_path -to [get_cells -hier -filter {name =~ *sysref_en_m1* && IS_SEQUENTIAL}] + diff --git a/projects/ad6676evb/vc707/system_project.tcl b/projects/ad6676evb/vc707/system_project.tcl index 2d69b5316..ad7d4e5c0 100644 --- a/projects/ad6676evb/vc707/system_project.tcl +++ b/projects/ad6676evb/vc707/system_project.tcl @@ -9,12 +9,10 @@ adi_project_create ad6676evb_vc707 adi_project_files ad6676evb_vc707 [list \ "system_top.v" \ "system_constr.xdc"\ - "$ad_hdl_dir/library/common/ad_iobuf.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \ + "$ad_hdl_dir/library/common/ad_sysref_gen.v" \ "$ad_hdl_dir/projects/common/vc707/vc707_system_constr.xdc" ] -set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/vc707/vc707_system_constr.xdc] -set_property PROCESSING_ORDER EARLY [get_files system_constr.xdc] - adi_project_run ad6676evb_vc707 diff --git a/projects/ad6676evb/vc707/system_top.v b/projects/ad6676evb/vc707/system_top.v index 160ea710b..6a5f4a892 100644 --- a/projects/ad6676evb/vc707/system_top.v +++ b/projects/ad6676evb/vc707/system_top.v @@ -200,6 +200,7 @@ module system_top ( wire rx_ref_clk; wire rx_sysref; wire rx_sync; + wire rx_clk; // default logic @@ -240,12 +241,17 @@ module system_top ( adc_agc3, adc_agc4})); - ad_iobuf #(.DATA_WIDTH(15)) i_iobuf_bd ( - .dio_t (gpio_t[14:0]), - .dio_i (gpio_o[14:0]), - .dio_o (gpio_i[14:0]), + ad_iobuf #(.DATA_WIDTH(21)) i_iobuf_bd ( + .dio_t (gpio_t[20:0]), + .dio_i (gpio_o[20:0]), + .dio_o (gpio_i[20:0]), .dio_p (gpio_bd)); + ad_sysref_gen i_sysref ( + .core_clk (rx_clk), + .sysref_en (gpio_o[48]), + .sysref_out (rx_sysref)); + system_wrapper i_system_wrapper ( .ddr3_addr (ddr3_addr), .ddr3_ba (ddr3_ba), @@ -289,11 +295,14 @@ module system_top ( .mgt_clk_clk_p (mgt_clk_p), .phy_rstn (phy_rstn), .phy_sd (1'b1), - .rx_data_n (rx_data_n), - .rx_data_p (rx_data_p), - .rx_ref_clk (rx_ref_clk), - .rx_sync (rx_sync), - .rx_sysref (rx_sysref), + .rx_data_0_n (rx_data_n[0]), + .rx_data_0_p (rx_data_p[0]), + .rx_data_1_n (rx_data_n[1]), + .rx_data_1_p (rx_data_p[1]), + .rx_ref_clk_0 (rx_ref_clk), + .rx_sync_0 (rx_sync), + .rx_sysref_0 (rx_sysref), + .rx_core_clk (rx_clk), .sgmii_rxn (sgmii_rxn), .sgmii_rxp (sgmii_rxp), .sgmii_txn (sgmii_txn), diff --git a/projects/ad6676evb/zc706/Makefile b/projects/ad6676evb/zc706/Makefile index b11811429..62979f9e8 100644 --- a/projects/ad6676evb/zc706/Makefile +++ b/projects/ad6676evb/zc706/Makefile @@ -15,15 +15,16 @@ M_DEPS += ../../scripts/adi_env.tcl M_DEPS += ../../scripts/adi_board.tcl M_DEPS += ../../common/zc706/zc706_system_constr.xdc M_DEPS += ../../common/zc706/zc706_system_bd.tcl -M_DEPS += ../../../library/common/ad_iobuf.v +M_DEPS += ../../../library/xilinx/common/ad_iobuf.v +M_DEPS += ../../../library/common/ad_sysref_gen.v M_DEPS += ../../../library/axi_ad6676/axi_ad6676.xpr +M_DEPS += ../../../library/xilinx/axi_adxcvr/axi_adxcvr.xpr M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr -M_DEPS += ../../../library/axi_jesd_gt/axi_jesd_gt.xpr M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr +M_DEPS += ../../../library/xilinx/util_adxcvr/util_adxcvr.xpr M_DEPS += ../../../library/util_cpack/util_cpack.xpr -M_DEPS += ../../../library/util_jesd_gt/util_jesd_gt.xpr M_VIVADO := vivado -mode batch -source @@ -39,6 +40,7 @@ M_FLIST += *.sdk M_FLIST += *.hw M_FLIST += *.sim M_FLIST += .Xil +M_FLIST += *.ip_user_files @@ -52,29 +54,29 @@ clean: clean-all:clean make -C ../../../library/axi_ad6676 clean + make -C ../../../library/xilinx/axi_adxcvr clean make -C ../../../library/axi_clkgen clean make -C ../../../library/axi_dmac clean make -C ../../../library/axi_hdmi_tx clean - make -C ../../../library/axi_jesd_gt clean make -C ../../../library/axi_spdif_tx clean + make -C ../../../library/xilinx/util_adxcvr clean make -C ../../../library/util_cpack clean - make -C ../../../library/util_jesd_gt clean ad6676evb_zc706.sdk/system_top.hdf: $(M_DEPS) - rm -rf $(M_FLIST) + -rm -rf $(M_FLIST) $(M_VIVADO) system_project.tcl >> ad6676evb_zc706_vivado.log 2>&1 lib: make -C ../../../library/axi_ad6676 + make -C ../../../library/xilinx/axi_adxcvr make -C ../../../library/axi_clkgen make -C ../../../library/axi_dmac make -C ../../../library/axi_hdmi_tx - make -C ../../../library/axi_jesd_gt make -C ../../../library/axi_spdif_tx + make -C ../../../library/xilinx/util_adxcvr make -C ../../../library/util_cpack - make -C ../../../library/util_jesd_gt #################################################################################### #################################################################################### diff --git a/projects/ad6676evb/zc706/system_constr.xdc b/projects/ad6676evb/zc706/system_constr.xdc index 44e3a8ee7..e73918db8 100644 --- a/projects/ad6676evb/zc706/system_constr.xdc +++ b/projects/ad6676evb/zc706/system_constr.xdc @@ -9,26 +9,32 @@ set_property -dict {PACKAGE_PIN AJ8 } [get_ports rx_data_p[1]] set_property -dict {PACKAGE_PIN AJ7 } [get_ports rx_data_n[1]] ; ## A03 FMC_HPC_DP1_M2C_N set_property -dict {PACKAGE_PIN AG21 IOSTANDARD LVDS_25} [get_ports rx_sync_p] ; ## D08 FMC_HPC_LA01_CC_P set_property -dict {PACKAGE_PIN AH21 IOSTANDARD LVDS_25} [get_ports rx_sync_n] ; ## D09 FMC_HPC_LA01_CC_N -set_property -dict {PACKAGE_PIN AF20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_sysref_p] ; ## G06 FMC_HPC_LA00_CC_P -set_property -dict {PACKAGE_PIN AG20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_sysref_n] ; ## G07 FMC_HPC_LA00_CC_N +set_property -dict {PACKAGE_PIN AF20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_sysref_p] ; ## G06 FMC_HPC_LA00_CC_P +set_property -dict {PACKAGE_PIN AG20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_sysref_n] ; ## G07 FMC_HPC_LA00_CC_N -set_property -dict {PACKAGE_PIN AH24 IOSTANDARD LVCMOS25} [get_ports spi_csn] ; ## D12 FMC_HPC_LA05_N -set_property -dict {PACKAGE_PIN AK20 IOSTANDARD LVCMOS25} [get_ports spi_clk] ; ## H11 FMC_HPC_LA04_N -set_property -dict {PACKAGE_PIN AJ20 IOSTANDARD LVCMOS25} [get_ports spi_mosi] ; ## H10 FMC_HPC_LA04_P -set_property -dict {PACKAGE_PIN AH23 IOSTANDARD LVCMOS25} [get_ports spi_miso] ; ## D11 FMC_HPC_LA05_P +set_property -dict {PACKAGE_PIN AH24 IOSTANDARD LVCMOS25} [get_ports spi_csn] ; ## D12 FMC_HPC_LA05_N +set_property -dict {PACKAGE_PIN AK20 IOSTANDARD LVCMOS25} [get_ports spi_clk] ; ## H11 FMC_HPC_LA04_N +set_property -dict {PACKAGE_PIN AJ20 IOSTANDARD LVCMOS25} [get_ports spi_mosi] ; ## H10 FMC_HPC_LA04_P +set_property -dict {PACKAGE_PIN AH23 IOSTANDARD LVCMOS25} [get_ports spi_miso] ; ## D11 FMC_HPC_LA05_P -set_property -dict {PACKAGE_PIN AH22 IOSTANDARD LVCMOS25} [get_ports adc_oen] ; ## C11 FMC_HPC_LA06_N -set_property -dict {PACKAGE_PIN AF19 IOSTANDARD LVCMOS25} [get_ports adc_sela] ; ## G12 FMC_HPC_LA08_P -set_property -dict {PACKAGE_PIN AG19 IOSTANDARD LVCMOS25} [get_ports adc_selb] ; ## G13 FMC_HPC_LA08_N -set_property -dict {PACKAGE_PIN AJ23 IOSTANDARD LVCMOS25} [get_ports adc_s0] ; ## H13 FMC_HPC_LA07_P -set_property -dict {PACKAGE_PIN AJ24 IOSTANDARD LVCMOS25} [get_ports adc_s1] ; ## H14 FMC_HPC_LA07_N -set_property -dict {PACKAGE_PIN AG22 IOSTANDARD LVCMOS25} [get_ports adc_resetb] ; ## C10 FMC_HPC_LA06_P -set_property -dict {PACKAGE_PIN AK17 IOSTANDARD LVCMOS25} [get_ports adc_agc1] ; ## H07 FMC_HPC_LA02_P -set_property -dict {PACKAGE_PIN AK18 IOSTANDARD LVCMOS25} [get_ports adc_agc2] ; ## H08 FMC_HPC_LA02_N -set_property -dict {PACKAGE_PIN AH19 IOSTANDARD LVCMOS25} [get_ports adc_agc3] ; ## G09 FMC_HPC_LA03_P -set_property -dict {PACKAGE_PIN AJ19 IOSTANDARD LVCMOS25} [get_ports adc_agc4] ; ## G10 FMC_HPC_LA03_N +set_property -dict {PACKAGE_PIN AH22 IOSTANDARD LVCMOS25} [get_ports adc_oen] ; ## C11 FMC_HPC_LA06_N +set_property -dict {PACKAGE_PIN AF19 IOSTANDARD LVCMOS25} [get_ports adc_sela] ; ## G12 FMC_HPC_LA08_P +set_property -dict {PACKAGE_PIN AG19 IOSTANDARD LVCMOS25} [get_ports adc_selb] ; ## G13 FMC_HPC_LA08_N +set_property -dict {PACKAGE_PIN AJ23 IOSTANDARD LVCMOS25} [get_ports adc_s0] ; ## H13 FMC_HPC_LA07_P +set_property -dict {PACKAGE_PIN AJ24 IOSTANDARD LVCMOS25} [get_ports adc_s1] ; ## H14 FMC_HPC_LA07_N +set_property -dict {PACKAGE_PIN AG22 IOSTANDARD LVCMOS25} [get_ports adc_resetb] ; ## C10 FMC_HPC_LA06_P +set_property -dict {PACKAGE_PIN AK17 IOSTANDARD LVCMOS25} [get_ports adc_agc1] ; ## H07 FMC_HPC_LA02_P +set_property -dict {PACKAGE_PIN AK18 IOSTANDARD LVCMOS25} [get_ports adc_agc2] ; ## H08 FMC_HPC_LA02_N +set_property -dict {PACKAGE_PIN AH19 IOSTANDARD LVCMOS25} [get_ports adc_agc3] ; ## G09 FMC_HPC_LA03_P +set_property -dict {PACKAGE_PIN AJ19 IOSTANDARD LVCMOS25} [get_ports adc_agc4] ; ## G10 FMC_HPC_LA03_N # clocks -create_clock -name rx_ref_clk -period 3.30 [get_ports rx_ref_clk_p] -create_clock -name rx_div_clk -period 6.60 [get_pins i_system_wrapper/system_i/axi_ad6676_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK] +create_clock -name rx_ref_clk -period 5.00 [get_ports rx_ref_clk_p] +create_clock -name rx_div_clk -period 10.00 [get_pins i_system_wrapper/system_i/util_ad6676_xcvr/inst/i_xch_0/i_gtxe2_channel/RXOUTCLK] + +set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad6676_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]] + +set_property shreg_extract no [get_cells -hier -filter {name =~ *sysref_en_m*}] +set_false_path -to [get_cells -hier -filter {name =~ *sysref_en_m1* && IS_SEQUENTIAL}] + diff --git a/projects/ad6676evb/zc706/system_project.tcl b/projects/ad6676evb/zc706/system_project.tcl index f7b46e8ac..c5982e29f 100644 --- a/projects/ad6676evb/zc706/system_project.tcl +++ b/projects/ad6676evb/zc706/system_project.tcl @@ -9,12 +9,10 @@ adi_project_create ad6676evb_zc706 adi_project_files ad6676evb_zc706 [list \ "system_top.v" \ "system_constr.xdc"\ - "$ad_hdl_dir/library/common/ad_iobuf.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \ + "$ad_hdl_dir/library/common/ad_sysref_gen.v" \ "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ] -set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc] -set_property PROCESSING_ORDER EARLY [get_files system_constr.xdc] - adi_project_run ad6676evb_zc706 diff --git a/projects/ad6676evb/zc706/system_top.v b/projects/ad6676evb/zc706/system_top.v index 043fdbc68..fc387b1d8 100644 --- a/projects/ad6676evb/zc706/system_top.v +++ b/projects/ad6676evb/zc706/system_top.v @@ -177,8 +177,9 @@ module system_top ( wire spi1_mosi; wire spi1_miso; wire rx_ref_clk; - wire rx_sysref; wire rx_sync; + wire rx_sysref; + wire rx_clk; // instantiations @@ -225,6 +226,11 @@ module system_top ( .dio_o (gpio_i[14:0]), .dio_p (gpio_bd)); + ad_sysref_gen i_sysref ( + .core_clk (rx_clk), + .sysref_en (gpio_o[48]), + .sysref_out (rx_sysref)); + system_wrapper i_system_wrapper ( .ddr_addr (ddr_addr), .ddr_ba (ddr_ba), @@ -270,11 +276,14 @@ module system_top ( .ps_intr_10 (1'b0), .ps_intr_11 (1'b0), .ps_intr_12 (1'b0), - .rx_data_n (rx_data_n), - .rx_data_p (rx_data_p), - .rx_ref_clk (rx_ref_clk), - .rx_sync (rx_sync), - .rx_sysref (rx_sysref), + .rx_data_0_n (rx_data_n[0]), + .rx_data_0_p (rx_data_p[0]), + .rx_data_1_n (rx_data_n[1]), + .rx_data_1_p (rx_data_p[1]), + .rx_ref_clk_0 (rx_ref_clk), + .rx_sync_0 (rx_sync), + .rx_sysref_0 (rx_sysref), + .rx_core_clk (rx_clk), .spdif (spdif), .spi0_clk_i (spi0_clk), .spi0_clk_o (spi0_clk), diff --git a/projects/pzsdr/Makefile b/projects/ad7616_sdz/Makefile similarity index 76% rename from projects/pzsdr/Makefile rename to projects/ad7616_sdz/Makefile index f6284afab..8c0cfc6f5 100644 --- a/projects/pzsdr/Makefile +++ b/projects/ad7616_sdz/Makefile @@ -7,21 +7,18 @@ .PHONY: all clean clean-all all: - -make -C ccbrk all - -make -C ccfmc all - -make -C ccpci all + -make -C zc706 all + -make -C zed all clean: - make -C ccbrk clean - make -C ccfmc clean - make -C ccpci clean + make -C zc706 clean + make -C zed clean clean-all: - make -C ccbrk clean-all - make -C ccfmc clean-all - make -C ccpci clean-all + make -C zc706 clean-all + make -C zed clean-all #################################################################################### #################################################################################### diff --git a/projects/ad7616_sdz/common/ad7616_bd.tcl b/projects/ad7616_sdz/common/ad7616_bd.tcl new file mode 100644 index 000000000..e61e1da78 --- /dev/null +++ b/projects/ad7616_sdz/common/ad7616_bd.tcl @@ -0,0 +1,83 @@ + +global ad7616_if + +# data interfaces + +create_bd_port -dir O rx_sclk +create_bd_port -dir O rx_sdo +create_bd_port -dir I rx_sdi_0 +create_bd_port -dir I rx_sdi_1 + +create_bd_port -dir O -from 15 -to 0 rx_db_o +create_bd_port -dir I -from 15 -to 0 rx_db_i +create_bd_port -dir O rx_db_t +create_bd_port -dir O rx_rd_n +create_bd_port -dir O rx_wr_n + +# control lines + +create_bd_port -dir O rx_cnvst +create_bd_port -dir O rx_cs_n +create_bd_port -dir I rx_busy + +# instantiation + +set axi_ad7616 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad7616:1.0 axi_ad7616] +set_property -dict [list CONFIG.IF_TYPE $ad7616_if] $axi_ad7616 + +set axi_ad7616_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad7616_dma] +set_property -dict [list CONFIG.DMA_TYPE_SRC {2}] $axi_ad7616_dma +set_property -dict [list CONFIG.DMA_TYPE_DEST {0}] $axi_ad7616_dma +set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad7616_dma +set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad7616_dma +set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {16}] $axi_ad7616_dma +set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $axi_ad7616_dma + +# interface connections +if {$ad7616_if == 0} { + + ad_connect rx_sclk axi_ad7616/rx_sclk + ad_connect rx_sdo axi_ad7616/rx_sdo + ad_connect rx_sdi_0 axi_ad7616/rx_sdi_0 + ad_connect rx_sdi_1 axi_ad7616/rx_sdi_1 + ad_connect rx_cs_n axi_ad7616/rx_cs_n + + ad_connect rx_cnvst axi_ad7616/rx_cnvst + ad_connect rx_busy axi_ad7616/rx_busy + +} else { + + ad_connect rx_db_o axi_ad7616/rx_db_o + ad_connect rx_db_i axi_ad7616/rx_db_i + ad_connect rx_db_t axi_ad7616/rx_db_t + ad_connect rx_rd_n axi_ad7616/rx_rd_n + ad_connect rx_wr_n axi_ad7616/rx_wr_n + + ad_connect rx_cs_n axi_ad7616/rx_cs_n + ad_connect rx_cnvst axi_ad7616/rx_cnvst + ad_connect rx_busy axi_ad7616/rx_busy + +} + +ad_connect sys_cpu_clk axi_ad7616_dma/s_axi_aclk +ad_connect sys_cpu_clk axi_ad7616_dma/fifo_wr_clk +ad_connect axi_ad7616/adc_valid axi_ad7616_dma/fifo_wr_en +ad_connect axi_ad7616/adc_data axi_ad7616_dma/fifo_wr_din +ad_connect axi_ad7616/adc_sync axi_ad7616_dma/fifo_wr_sync + +# interconnect + +ad_cpu_interconnect 0x44A00000 axi_ad7616 +ad_cpu_interconnect 0x44A30000 axi_ad7616_dma + +# memory interconnect + +ad_mem_hp1_interconnect sys_cpu_clk sys_ps7/S_AXI_HP1 +ad_mem_hp1_interconnect sys_cpu_clk axi_ad7616_dma/m_dest_axi +ad_connect sys_cpu_resetn axi_ad7616_dma/m_dest_axi_aresetn + +# interrupts + +ad_cpu_interrupt ps-13 mb-12 axi_ad7616_dma/irq +ad_cpu_interrupt ps-12 mb-13 axi_ad7616/irq + diff --git a/projects/fmcomms6/zc706/Makefile b/projects/ad7616_sdz/zc706/Makefile similarity index 70% rename from projects/fmcomms6/zc706/Makefile rename to projects/ad7616_sdz/zc706/Makefile index 3846e87f0..81de40959 100644 --- a/projects/fmcomms6/zc706/Makefile +++ b/projects/ad7616_sdz/zc706/Makefile @@ -5,25 +5,24 @@ #################################################################################### #################################################################################### -M_DEPS += system_top.v +M_DEPS += system_top_si.v +M_DEPS += system_top_pi.v M_DEPS += system_project.tcl -M_DEPS += system_constr.xdc M_DEPS += system_bd.tcl -M_DEPS += ../common/fmcomms6_spi.v -M_DEPS += ../common/fmcomms6_bd.tcl +M_DEPS += serial_if_constr.xdc +M_DEPS += parallel_if_constr.xdc +M_DEPS += ../common/ad7616_bd.tcl M_DEPS += ../../scripts/adi_project.tcl M_DEPS += ../../scripts/adi_env.tcl M_DEPS += ../../scripts/adi_board.tcl M_DEPS += ../../common/zc706/zc706_system_constr.xdc M_DEPS += ../../common/zc706/zc706_system_bd.tcl -M_DEPS += ../../../library/common/ad_iobuf.v -M_DEPS += ../../../library/axi_ad9652/axi_ad9652.xpr +M_DEPS += ../../../library/xilinx/common/ad_iobuf.v +M_DEPS += ../../../library/axi_ad7616/axi_ad7616.xpr M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr -M_DEPS += ../../../library/util_cpack/util_cpack.xpr -M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr M_VIVADO := vivado -mode batch -source @@ -39,11 +38,12 @@ M_FLIST += *.sdk M_FLIST += *.hw M_FLIST += *.sim M_FLIST += .Xil +M_FLIST += *.ip_user_files .PHONY: all lib clean clean-all -all: lib fmcomms6_zc706.sdk/system_top.hdf +all: lib ad7616_sdz_zc706.sdk/system_top.hdf clean: @@ -51,28 +51,24 @@ clean: clean-all:clean - make -C ../../../library/axi_ad9652 clean + make -C ../../../library/axi_ad7616 clean make -C ../../../library/axi_clkgen clean make -C ../../../library/axi_dmac clean make -C ../../../library/axi_hdmi_tx clean make -C ../../../library/axi_spdif_tx clean - make -C ../../../library/util_cpack clean - make -C ../../../library/util_wfifo clean -fmcomms6_zc706.sdk/system_top.hdf: $(M_DEPS) - rm -rf $(M_FLIST) - $(M_VIVADO) system_project.tcl >> fmcomms6_zc706_vivado.log 2>&1 +ad7616_sdz_zc706.sdk/system_top.hdf: $(M_DEPS) + -rm -rf $(M_FLIST) + $(M_VIVADO) system_project.tcl >> ad7616_sdz_zc706_vivado.log 2>&1 lib: - make -C ../../../library/axi_ad9652 + make -C ../../../library/axi_ad7616 make -C ../../../library/axi_clkgen make -C ../../../library/axi_dmac make -C ../../../library/axi_hdmi_tx make -C ../../../library/axi_spdif_tx - make -C ../../../library/util_cpack - make -C ../../../library/util_wfifo #################################################################################### #################################################################################### diff --git a/projects/ad7616_sdz/zc706/parallel_if_constr.xdc b/projects/ad7616_sdz/zc706/parallel_if_constr.xdc new file mode 100644 index 000000000..97007b624 --- /dev/null +++ b/projects/ad7616_sdz/zc706/parallel_if_constr.xdc @@ -0,0 +1,36 @@ + +# ad7616 + +set_property -dict {PACKAGE_PIN AC14 IOSTANDARD LVCMOS25} [get_ports adc_db[0] ] ; ## FMC_LPC_LA10_P +set_property -dict {PACKAGE_PIN AJ15 IOSTANDARD LVCMOS25} [get_ports adc_db[1] ] ; ## FMC_LPC_LA04_P +set_property -dict {PACKAGE_PIN AH14 IOSTANDARD LVCMOS25} [get_ports adc_db[2] ] ; ## FMC_LPC_LA09_P +set_property -dict {PACKAGE_PIN AG12 IOSTANDARD LVCMOS25} [get_ports adc_db[3] ] ; ## FMC_LPC_LA03_P +set_property -dict {PACKAGE_PIN AE15 IOSTANDARD LVCMOS25} [get_ports adc_db[4] ] ; ## FMC_LPC_LA05_N +set_property -dict {PACKAGE_PIN AF12 IOSTANDARD LVCMOS25} [get_ports adc_db[5] ] ; ## FMC_LPC_LA02_N +set_property -dict {PACKAGE_PIN AC12 IOSTANDARD LVCMOS25} [get_ports adc_db[6] ] ; ## FMC_LPC_LA06_N +set_property -dict {PACKAGE_PIN AF13 IOSTANDARD LVCMOS25} [get_ports adc_db[7] ] ; ## FMC_LPC_LA00_CC_N +set_property -dict {PACKAGE_PIN AE16 IOSTANDARD LVCMOS25} [get_ports adc_db[8] ] ; ## FMC_LPC_LA05_P +set_property -dict {PACKAGE_PIN AE12 IOSTANDARD LVCMOS25} [get_ports adc_db[9] ] ; ## FMC_LPC_LA02_P +set_property -dict {PACKAGE_PIN AA15 IOSTANDARD LVCMOS25} [get_ports adc_db[10]] ; ## FMC_LPC_LA06_P +set_property -dict {PACKAGE_PIN AE13 IOSTANDARD LVCMOS25} [get_ports adc_db[11]] ; ## FMC_LPC_LA00_CC_P +set_property -dict {PACKAGE_PIN AG15 IOSTANDARD LVCMOS25} [get_ports adc_db[12]] ; ## FMC_LPC_LA01_CC_N +set_property -dict {PACKAGE_PIN AG16 IOSTANDARD LVCMOS25} [get_ports adc_db[13]] ; ## FMC_LPC_CLK0_M2C_N +set_property -dict {PACKAGE_PIN AG17 IOSTANDARD LVCMOS25} [get_ports adc_db[14]] ; ## FMC_LPC_CLK0_M2C_P +set_property -dict {PACKAGE_PIN AF15 IOSTANDARD LVCMOS25} [get_ports adc_db[15]] ; ## FMC_LPC_LA01_CC_P + +set_property -dict {PACKAGE_PIN AH12 IOSTANDARD LVCMOS25} [get_ports adc_rd_n] ; ## FMC_LPC_LA03_N +set_property -dict {PACKAGE_PIN AH13 IOSTANDARD LVCMOS25} [get_ports adc_wr_n] ; ## FMC_LPC_LA09_N + +# control lines + +set_property -dict {PACKAGE_PIN AF30 IOSTANDARD LVCMOS25} [get_ports adc_convst] ; ## FMC_LPC_LA24_P +set_property -dict {PACKAGE_PIN AH29 IOSTANDARD LVCMOS25} [get_ports adc_chsel[0]] ; ## FMC_LPC_LA21_N +set_property -dict {PACKAGE_PIN AK30 IOSTANDARD LVCMOS25} [get_ports adc_chsel[1]] ; ## FMC_LPC_LA26_N +set_property -dict {PACKAGE_PIN AF29 IOSTANDARD LVCMOS25} [get_ports adc_chsel[2]] ; ## FMC_LPC_LA25_P +set_property -dict {PACKAGE_PIN AH28 IOSTANDARD LVCMOS25} [get_ports adc_hw_rngsel[0]] ; ## FMC_LPC_LA21_P +set_property -dict {PACKAGE_PIN AJ30 IOSTANDARD LVCMOS25} [get_ports adc_hw_rngsel[1]] ; ## FMC_LPC_LA26_P +set_property -dict {PACKAGE_PIN AC13 IOSTANDARD LVCMOS25} [get_ports adc_busy] ; ## FMC_LPC_LA10_N +set_property -dict {PACKAGE_PIN AJ28 IOSTANDARD LVCMOS25} [get_ports adc_seq_en] ; ## FMC_LPC_LA27_P +set_property -dict {PACKAGE_PIN AK28 IOSTANDARD LVCMOS25} [get_ports adc_reset_n] ; ## FMC_LPC_LA22_N +set_property -dict {PACKAGE_PIN AK15 IOSTANDARD LVCMOS25} [get_ports adc_cs_n] ; ## FMC_LPC_LA04_N + diff --git a/projects/ad7616_sdz/zc706/serial_if_constr.xdc b/projects/ad7616_sdz/zc706/serial_if_constr.xdc new file mode 100644 index 000000000..e360f98d3 --- /dev/null +++ b/projects/ad7616_sdz/zc706/serial_if_constr.xdc @@ -0,0 +1,29 @@ + +# ad7616 + +# data interface + +set_property -dict {PACKAGE_PIN AH12 IOSTANDARD LVCMOS25} [get_ports spi_sclk] ; ## FMC_LPC_LA03_N +set_property -dict {PACKAGE_PIN AB12 IOSTANDARD LVCMOS25} [get_ports spi_sdo] ; ## FMC_LPC_LA06_P +set_property -dict {PACKAGE_PIN AE13 IOSTANDARD LVCMOS25} [get_ports spi_sdi_0] ; ## FMC_LPC_LA00_CC_P +set_property -dict {PACKAGE_PIN AG15 IOSTANDARD LVCMOS25} [get_ports spi_sdi_1] ; ## FMC_LPC_LA01_CC_N +set_property -dict {PACKAGE_PIN AK15 IOSTANDARD LVCMOS25} [get_ports spi_cs_n] ; ## FMC_LPC_LA04_N + +# control lines + +set_property -dict {PACKAGE_PIN AF30 IOSTANDARD LVCMOS25} [get_ports adc_convst] ; ## FMC_LPC_LA24_P +set_property -dict {PACKAGE_PIN AH29 IOSTANDARD LVCMOS25} [get_ports adc_chsel[0]] ; ## FMC_LPC_LA21_N +set_property -dict {PACKAGE_PIN AK30 IOSTANDARD LVCMOS25} [get_ports adc_chsel[1]] ; ## FMC_LPC_LA26_N +set_property -dict {PACKAGE_PIN AF29 IOSTANDARD LVCMOS25} [get_ports adc_chsel[2]] ; ## FMC_LPC_LA25_P +set_property -dict {PACKAGE_PIN AH28 IOSTANDARD LVCMOS25} [get_ports adc_hw_rngsel[0]] ; ## FMC_LPC_LA21_P +set_property -dict {PACKAGE_PIN AJ30 IOSTANDARD LVCMOS25} [get_ports adc_hw_rngsel[1]] ; ## FMC_LPC_LA26_P +set_property -dict {PACKAGE_PIN AC13 IOSTANDARD LVCMOS25} [get_ports adc_busy] ; ## FMC_LPC_LA10_N +set_property -dict {PACKAGE_PIN AJ28 IOSTANDARD LVCMOS25} [get_ports adc_seq_en] ; ## FMC_LPC_LA27_P +set_property -dict {PACKAGE_PIN AK28 IOSTANDARD LVCMOS25} [get_ports adc_reset_n] ; ## FMC_LPC_LA22_N + +set_property -dict {PACKAGE_PIN AG16 IOSTANDARD LVCMOS25} [get_ports adc_os[0]] ; ## FMC_LPC_CLK0_M2C_N +set_property -dict {PACKAGE_PIN AG17 IOSTANDARD LVCMOS25} [get_ports adc_os[1]] ; ## FMC_LPC_CLK0_M2C_P +set_property -dict {PACKAGE_PIN AF15 IOSTANDARD LVCMOS25} [get_ports adc_os[2]] ; ## FMC_LPC_LA01_CC_P +set_property -dict {PACKAGE_PIN AH13 IOSTANDARD LVCMOS25} [get_ports adc_burst] ; ## FMC_LPC_LA09_N +set_property -dict {PACKAGE_PIN AF12 IOSTANDARD LVCMOS25} [get_ports adc_crcen] ; ## FMC_LPC_LA02_N + diff --git a/projects/fmcomms6/zc706/system_bd.tcl b/projects/ad7616_sdz/zc706/system_bd.tcl similarity index 65% rename from projects/fmcomms6/zc706/system_bd.tcl rename to projects/ad7616_sdz/zc706/system_bd.tcl index 8f853b9cb..74f34ef33 100644 --- a/projects/fmcomms6/zc706/system_bd.tcl +++ b/projects/ad7616_sdz/zc706/system_bd.tcl @@ -1,4 +1,4 @@ source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl -source ../common/fmcomms6_bd.tcl +source ../common/ad7616_bd.tcl diff --git a/projects/ad7616_sdz/zc706/system_project.tcl b/projects/ad7616_sdz/zc706/system_project.tcl new file mode 100644 index 000000000..7d5ea14c0 --- /dev/null +++ b/projects/ad7616_sdz/zc706/system_project.tcl @@ -0,0 +1,46 @@ + +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/projects/scripts/adi_project.tcl +source $ad_hdl_dir/projects/scripts/adi_board.tcl + +##-------------------------------------------------------------- +# IMPORTANT: Set AD7616 operation and interface mode +# +# ad7616_if - Defines the interface type (serial OR parallel) +# +# LEGEND: Serial - 0 +# Parallel - 1 +# +# NOTE : This switch is a 'hardware' switch. Please reimplenent the +# design if the variable has been changed. +# +##-------------------------------------------------------------- + +set ad7616_if 0 + +adi_project_create ad7616_sdz_zc706 + +if { $ad7616_if == 0 } { + + adi_project_files ad7616_sdz_zc706 [list \ + "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \ + "system_top_si.v" \ + "serial_if_constr.xdc" \ + "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc"] + +} elseif { $ad7616_if == 1 } { + + adi_project_files ad7616_sdz_zc706 [list \ + "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \ + "system_top_pi.v" \ + "parallel_if_constr.xdc" \ + "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc"] + +} else { + + return -code error [format "ERROR: Invalid interface type! Define as \'serial\' or \'parallel\' ..."] + +} + +adi_project_run ad7616_sdz_zc706 + diff --git a/projects/fmcomms6/zc706/system_top.v b/projects/ad7616_sdz/zc706/system_top_pi.v similarity index 71% rename from projects/fmcomms6/zc706/system_top.v rename to projects/ad7616_sdz/zc706/system_top_pi.v index d2c0bd8d6..3abb0fbef 100644 --- a/projects/fmcomms6/zc706/system_top.v +++ b/projects/ad7616_sdz/zc706/system_top_pi.v @@ -77,19 +77,17 @@ module system_top ( iic_scl, iic_sda, - adc_clk_in_p, - adc_clk_in_n, - adc_or_in_p, - adc_or_in_n, - adc_data_in_p, - adc_data_in_n, + adc_db, + adc_rd_n, + adc_wr_n, - spi_adf4351_csn, - spi_ad9652_csn, - spi_ad9517_csn, - spi_clk, - spi_sdio, - adf4351_ld); + adc_cs_n, + adc_reset_n, + adc_convst, + adc_busy, + adc_seq_en, + adc_hw_rngsel, + adc_chsel); inout [14:0] ddr_addr; inout [ 2:0] ddr_ba; @@ -127,69 +125,60 @@ module system_top ( inout iic_scl; inout iic_sda; - input adc_clk_in_p; - input adc_clk_in_n; - input adc_or_in_p; - input adc_or_in_n; - input [15:0] adc_data_in_p; - input [15:0] adc_data_in_n; + inout [15:0] adc_db; + output adc_rd_n; + output adc_wr_n; - output spi_adf4351_csn; - output spi_ad9652_csn; - output spi_ad9517_csn; - output spi_clk; - inout spi_sdio; - inout adf4351_ld; + output adc_cs_n; + output adc_reset_n; + output adc_convst; + input adc_busy; + output adc_seq_en; + output [ 1:0] adc_hw_rngsel; + output [ 2:0] adc_chsel; // internal signals wire [63:0] gpio_i; wire [63:0] gpio_o; wire [63:0] gpio_t; - wire [ 2:0] spi0_csn; - wire spi0_clk; - wire spi0_mosi; - wire spi0_miso; - wire [ 2:0] spi1_csn; - wire spi1_clk; - wire spi1_mosi; - wire spi1_miso; - // spi + wire adc_db_t; + wire [15:0] adc_db_o; + wire [15:0] adc_db_i; - assign spi_clk = spi0_clk; - assign spi_ad9517_csn = spi0_csn[0]; - assign spi_ad9652_csn = spi0_csn[1]; - assign spi_adf4351_csn = spi0_csn[2]; + genvar i; // instantiations - fmcomms6_spi i_spi ( - .spi_csn (spi0_csn), - .spi_clk (spi0_clk), - .spi_mosi (spi0_mosi), - .spi_miso (spi0_miso), - .spi_sdio (spi_sdio)); + ad_iobuf #(.DATA_WIDTH(7)) i_iobuf_adc_cntrl ( + .dio_t (gpio_t[43:41], gpio_t[37], gpio_t[35:33]}), + .dio_i (gpio_o[43:41], gpio_o[37], gpio_o[35:33]}), + .dio_o (gpio_i[43:41], gpio_i[37], gpio_i[35:33]}), + .dio_p ({adc_reset_n, // 43 + adc_hw_rngsel, // 42:41 + adc_seq_en, // 37 + adc_chsel})); // 35:33 - ad_iobuf #(.DATA_WIDTH(1)) i_iobuf ( - .dio_t (gpio_t[32]), - .dio_i (gpio_o[32]), - .dio_o (gpio_i[32]), - .dio_p (adf4351_ld)); + generate + for (i = 0; i < 16; i = i + 1) begin: adc_db_io + ad_iobuf i_iobuf_adc_db ( + .dio_t(adc_db_t), + .dio_i(adc_db_o[i]), + .dio_o(adc_db_i[i]), + .dio_p(adc_db[i])); + end + endgenerate - ad_iobuf #(.DATA_WIDTH(15)) i_iobuf_bd ( - .dio_t (gpio_t[14:0]), - .dio_i (gpio_o[14:0]), - .dio_o (gpio_i[14:0]), - .dio_p (gpio_bd)); + ad_iobuf #( + .DATA_WIDTH(15) + ) i_iobuf_gpio ( + .dio_t(gpio_t[14:0]), + .dio_i(gpio_o[14:0]), + .dio_o(gpio_i[14:0]), + .dio_p(gpio_bd)); system_wrapper i_system_wrapper ( - .adc_clk_in_n (adc_clk_in_n), - .adc_clk_in_p (adc_clk_in_p), - .adc_data_in_n (adc_data_in_n), - .adc_data_in_p (adc_data_in_p), - .adc_or_in_n (adc_or_in_n), - .adc_or_in_p (adc_or_in_p), .ddr_addr (ddr_addr), .ddr_ba (ddr_ba), .ddr_cas_n (ddr_cas_n), @@ -233,26 +222,16 @@ module system_top ( .ps_intr_09 (1'b0), .ps_intr_10 (1'b0), .ps_intr_11 (1'b0), - .ps_intr_12 (1'b0), .spdif (spdif), - .spi0_clk_i (spi0_clk), - .spi0_clk_o (spi0_clk), - .spi0_csn_0_o (spi0_csn[0]), - .spi0_csn_1_o (spi0_csn[1]), - .spi0_csn_2_o (spi0_csn[2]), - .spi0_csn_i (1'b1), - .spi0_sdi_i (spi0_miso), - .spi0_sdo_i (spi0_mosi), - .spi0_sdo_o (spi0_mosi), - .spi1_clk_i (spi1_clk), - .spi1_clk_o (spi1_clk), - .spi1_csn_0_o (spi1_csn[0]), - .spi1_csn_1_o (spi1_csn[1]), - .spi1_csn_2_o (spi1_csn[2]), - .spi1_csn_i (1'b1), - .spi1_sdi_i (1'b1), - .spi1_sdo_i (spi1_mosi), - .spi1_sdo_o (spi1_mosi)); + .rx_cnvst (adc_convst), + .rx_cs_n (adc_cs_n), + .rx_busy (adc_busy), + .rx_db_o (adc_db_o), + .rx_db_i (adc_db_i), + .rx_db_t (adc_db_t), + .rx_rd_n (adc_rd_n), + .rx_wr_n (adc_wr_n) + ); endmodule diff --git a/projects/fmcomms1/zc706/system_top.v b/projects/ad7616_sdz/zc706/system_top_si.v similarity index 68% rename from projects/fmcomms1/zc706/system_top.v rename to projects/ad7616_sdz/zc706/system_top_si.v index 298adf428..fef99aef4 100644 --- a/projects/fmcomms1/zc706/system_top.v +++ b/projects/ad7616_sdz/zc706/system_top_si.v @@ -74,27 +74,24 @@ module system_top ( spdif, - dac_clk_in_p, - dac_clk_in_n, - dac_clk_out_p, - dac_clk_out_n, - dac_frame_out_p, - dac_frame_out_n, - dac_data_out_p, - dac_data_out_n, - - adc_clk_in_p, - adc_clk_in_n, - adc_or_in_p, - adc_or_in_n, - adc_data_in_p, - adc_data_in_n, - - ref_clk_out_p, - ref_clk_out_n, - iic_scl, - iic_sda); + iic_sda, + + spi_sclk, + spi_sdo, + spi_sdi_0, + spi_sdi_1, + spi_cs_n, + + adc_reset_n, + adc_convst, + adc_busy, + adc_seq_en, + adc_hw_rngsel, + adc_chsel, + adc_crcen, + adc_burst, + adc_os); inout [14:0] ddr_addr; inout [ 2:0] ddr_ba; @@ -129,67 +126,48 @@ module system_top ( output spdif; - input dac_clk_in_p; - input dac_clk_in_n; - output dac_clk_out_p; - output dac_clk_out_n; - output dac_frame_out_p; - output dac_frame_out_n; - output [15:0] dac_data_out_p; - output [15:0] dac_data_out_n; - - input adc_clk_in_p; - input adc_clk_in_n; - input adc_or_in_p; - input adc_or_in_n; - input [13:0] adc_data_in_p; - input [13:0] adc_data_in_n; - - output ref_clk_out_p; - output ref_clk_out_n; - inout iic_scl; inout iic_sda; + output spi_sclk; + output spi_sdo; + input spi_sdi_0; + input spi_sdi_1; + output spi_cs_n; + + output adc_reset_n; + output adc_convst; + input adc_busy; + output adc_seq_en; + output [ 1:0] adc_hw_rngsel; + output [ 2:0] adc_chsel; + output adc_crcen; + output adc_burst; + output [ 2:0] adc_os; + // internal signals wire [63:0] gpio_i; wire [63:0] gpio_o; wire [63:0] gpio_t; - wire [ 2:0] spi0_csn; - wire spi0_clk; - wire spi0_mosi; - wire spi0_miso; - wire [ 2:0] spi1_csn; - wire spi1_clk; - wire spi1_mosi; - wire spi1_miso; - wire ref_clk; - wire oddr_ref_clk; // instantiations - ODDR #( - .DDR_CLK_EDGE ("SAME_EDGE"), - .INIT (1'b0), - .SRTYPE ("ASYNC")) - i_oddr_ref_clk ( - .S (1'b0), - .CE (1'b1), - .R (1'b0), - .C (ref_clk), - .D1 (1'b1), - .D2 (1'b0), - .Q (oddr_ref_clk)); + ad_iobuf #(.DATA_WIDTH(12)) i_iobuf_adc_cntrl ( + .dio_t (gpio_t[43:32]), + .dio_i (gpio_o[43:32]), + .dio_o (gpio_i[43:32]), + .dio_p ({adc_reset_n, // 43 + adc_hw_rngsel, // 42:41 + adc_os, // 40:38 + adc_seq_en, // 37 + adc_burst, // 36 + adc_chsel, // 35:33 + adc_crcen})); // 32 - OBUFDS i_obufds_ref_clk ( - .I (oddr_ref_clk), - .O (ref_clk_out_p), - .OB (ref_clk_out_n)); - - ad_iobuf #( - .DATA_WIDTH(15)) - i_gpio_bd ( + ad_iobuf #( + .DATA_WIDTH(15) + ) i_iobuf_gpio ( .dio_t(gpio_t[14:0]), .dio_i(gpio_o[14:0]), .dio_o(gpio_i[14:0]), @@ -220,20 +198,6 @@ module system_top ( .gpio_i (gpio_i), .gpio_o (gpio_o), .gpio_t (gpio_t), - .adc_clk_in_n (adc_clk_in_n), - .adc_clk_in_p (adc_clk_in_p), - .adc_data_in_n (adc_data_in_n), - .adc_data_in_p (adc_data_in_p), - .adc_or_in_n (adc_or_in_n), - .adc_or_in_p (adc_or_in_p), - .dac_clk_in_n (dac_clk_in_n), - .dac_clk_in_p (dac_clk_in_p), - .dac_clk_out_n (dac_clk_out_n), - .dac_clk_out_p (dac_clk_out_p), - .dac_data_out_n (dac_data_out_n), - .dac_data_out_p (dac_data_out_p), - .dac_frame_out_n (dac_frame_out_n), - .dac_frame_out_p (dac_frame_out_p), .hdmi_data (hdmi_data), .hdmi_data_e (hdmi_data_e), .hdmi_hsync (hdmi_hsync), @@ -253,26 +217,14 @@ module system_top ( .ps_intr_09 (1'b0), .ps_intr_10 (1'b0), .ps_intr_11 (1'b0), - .ref_clk (ref_clk), .spdif (spdif), - .spi0_clk_i (spi0_clk), - .spi0_clk_o (spi0_clk), - .spi0_csn_0_o (spi0_csn[0]), - .spi0_csn_1_o (spi0_csn[1]), - .spi0_csn_2_o (spi0_csn[2]), - .spi0_csn_i (1'b1), - .spi0_sdi_i (spi0_miso), - .spi0_sdo_i (spi0_mosi), - .spi0_sdo_o (spi0_mosi), - .spi1_clk_i (spi1_clk), - .spi1_clk_o (spi1_clk), - .spi1_csn_0_o (spi1_csn[0]), - .spi1_csn_1_o (spi1_csn[1]), - .spi1_csn_2_o (spi1_csn[2]), - .spi1_csn_i (1'b1), - .spi1_sdi_i (1'b1), - .spi1_sdo_i (spi1_mosi), - .spi1_sdo_o (spi1_mosi)); + .rx_sclk (spi_sclk), + .rx_sdo (spi_sdo), + .rx_sdi_0 (spi_sdi_0), + .rx_sdi_1 (spi_sdi_1), + .rx_cnvst (adc_convst), + .rx_cs_n (spi_cs_n), + .rx_busy (adc_busy)); endmodule diff --git a/projects/fmcomms1/zc702/Makefile b/projects/ad7616_sdz/zed/Makefile similarity index 60% rename from projects/fmcomms1/zc702/Makefile rename to projects/ad7616_sdz/zed/Makefile index c5faab08a..bf5b20304 100644 --- a/projects/fmcomms1/zc702/Makefile +++ b/projects/ad7616_sdz/zed/Makefile @@ -5,26 +5,26 @@ #################################################################################### #################################################################################### -M_DEPS += system_top.v +M_DEPS += system_top_si.v +M_DEPS += system_top_pi.v M_DEPS += system_project.tcl -M_DEPS += system_constr.xdc M_DEPS += system_bd.tcl -M_DEPS += ../common/fmcomms1_bd.tcl +M_DEPS += serial_if_constr.xdc +M_DEPS += parallel_if_constr.xdc +M_DEPS += ../common/ad7616_bd.tcl M_DEPS += ../../scripts/adi_project.tcl M_DEPS += ../../scripts/adi_env.tcl M_DEPS += ../../scripts/adi_board.tcl -M_DEPS += ../../common/zc702/zc702_system_constr.xdc -M_DEPS += ../../common/zc702/zc702_system_bd.tcl -M_DEPS += ../../../library/common/ad_iobuf.v -M_DEPS += ../../../library/axi_ad9122/axi_ad9122.xpr -M_DEPS += ../../../library/axi_ad9643/axi_ad9643.xpr +M_DEPS += ../../common/zed/zed_system_constr.xdc +M_DEPS += ../../common/zed/zed_system_bd.tcl +M_DEPS += ../../../library/xilinx/common/ad_iobuf.v +M_DEPS += ../../../library/axi_ad7616/axi_ad7616.xpr M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr +M_DEPS += ../../../library/axi_i2s_adi/axi_i2s_adi.xpr M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr -M_DEPS += ../../../library/util_cpack/util_cpack.xpr -M_DEPS += ../../../library/util_upack/util_upack.xpr -M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr +M_DEPS += ../../../library/util_i2c_mixer/util_i2c_mixer.xpr M_VIVADO := vivado -mode batch -source @@ -40,11 +40,12 @@ M_FLIST += *.sdk M_FLIST += *.hw M_FLIST += *.sim M_FLIST += .Xil +M_FLIST += *.ip_user_files .PHONY: all lib clean clean-all -all: lib fmcomms1_zc702.sdk/system_top.hdf +all: lib ad7616_sdz_zed.sdk/system_top.hdf clean: @@ -52,32 +53,28 @@ clean: clean-all:clean - make -C ../../../library/axi_ad9122 clean - make -C ../../../library/axi_ad9643 clean + make -C ../../../library/axi_ad7616 clean make -C ../../../library/axi_clkgen clean make -C ../../../library/axi_dmac clean make -C ../../../library/axi_hdmi_tx clean + make -C ../../../library/axi_i2s_adi clean make -C ../../../library/axi_spdif_tx clean - make -C ../../../library/util_cpack clean - make -C ../../../library/util_upack clean - make -C ../../../library/util_wfifo clean + make -C ../../../library/util_i2c_mixer clean -fmcomms1_zc702.sdk/system_top.hdf: $(M_DEPS) - rm -rf $(M_FLIST) - $(M_VIVADO) system_project.tcl >> fmcomms1_zc702_vivado.log 2>&1 +ad7616_sdz_zed.sdk/system_top.hdf: $(M_DEPS) + -rm -rf $(M_FLIST) + $(M_VIVADO) system_project.tcl >> ad7616_sdz_zed_vivado.log 2>&1 lib: - make -C ../../../library/axi_ad9122 - make -C ../../../library/axi_ad9643 + make -C ../../../library/axi_ad7616 make -C ../../../library/axi_clkgen make -C ../../../library/axi_dmac make -C ../../../library/axi_hdmi_tx + make -C ../../../library/axi_i2s_adi make -C ../../../library/axi_spdif_tx - make -C ../../../library/util_cpack - make -C ../../../library/util_upack - make -C ../../../library/util_wfifo + make -C ../../../library/util_i2c_mixer #################################################################################### #################################################################################### diff --git a/projects/ad7616_sdz/zed/parallel_if_constr.xdc b/projects/ad7616_sdz/zed/parallel_if_constr.xdc new file mode 100644 index 000000000..4c2e01de6 --- /dev/null +++ b/projects/ad7616_sdz/zed/parallel_if_constr.xdc @@ -0,0 +1,37 @@ + +# ad7616 + +set_property -dict {PACKAGE_PIN R19 IOSTANDARD LVCMOS25} [get_ports adc_db[0] ] ; ## FMC_LPC_LA10_P +set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVCMOS25} [get_ports adc_db[1] ] ; ## FMC_LPC_LA04_P +set_property -dict {PACKAGE_PIN R20 IOSTANDARD LVCMOS25} [get_ports adc_db[2] ] ; ## FMC_LPC_LA09_P +set_property -dict {PACKAGE_PIN N22 IOSTANDARD LVCMOS25} [get_ports adc_db[3] ] ; ## FMC_LPC_LA03_P + +set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVCMOS25} [get_ports adc_db[4] ] ; ## FMC_LPC_LA05_N +set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS25} [get_ports adc_db[5] ] ; ## FMC_LPC_LA02_N +set_property -dict {PACKAGE_PIN L22 IOSTANDARD LVCMOS25} [get_ports adc_db[6] ] ; ## FMC_LPC_LA06_N +set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVCMOS25} [get_ports adc_db[7] ] ; ## FMC_LPC_LA00_CC_N +set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS25} [get_ports adc_db[8] ] ; ## FMC_LPC_LA05_P +set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [get_ports adc_db[9] ] ; ## FMC_LPC_LA02_P +set_property -dict {PACKAGE_PIN L21 IOSTANDARD LVCMOS25} [get_ports adc_db[10]] ; ## FMC_LPC_LA06_P +set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVCMOS25} [get_ports adc_db[11]] ; ## FMC_LPC_LA00_CC_P +set_property -dict {PACKAGE_PIN N20 IOSTANDARD LVCMOS25} [get_ports adc_db[12]] ; ## FMC_LPC_LA01_CC_N +set_property -dict {PACKAGE_PIN L19 IOSTANDARD LVCMOS25} [get_ports adc_db[13]] ; ## FMC_LPC_CLK0_M2C_N +set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVCMOS25} [get_ports adc_db[14]] ; ## FMC_LPC_CLK0_M2C_P +set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVCMOS25} [get_ports adc_db[15]] ; ## FMC_LPC_LA01_CC_P + +set_property -dict {PACKAGE_PIN P22 IOSTANDARD LVCMOS25} [get_ports adc_rd_n] ; ## FMC_LPC_LA03_N +set_property -dict {PACKAGE_PIN R21 IOSTANDARD LVCMOS25} [get_ports adc_wr_n] ; ## FMC_LPC_LA09_N + +# control lines + +set_property -dict {PACKAGE_PIN A18 IOSTANDARD LVCMOS25} [get_ports adc_convst] ; ## FMC_LPC_LA24_P +set_property -dict {PACKAGE_PIN E20 IOSTANDARD LVCMOS25} [get_ports adc_chsel[0]] ; ## FMC_LPC_LA21_N +set_property -dict {PACKAGE_PIN E18 IOSTANDARD LVCMOS25} [get_ports adc_chsel[1]] ; ## FMC_LPC_LA26_N +set_property -dict {PACKAGE_PIN D22 IOSTANDARD LVCMOS25} [get_ports adc_chsel[2]] ; ## FMC_LPC_LA25_P +set_property -dict {PACKAGE_PIN E19 IOSTANDARD LVCMOS25} [get_ports adc_hw_rngsel[0]] ; ## FMC_LPC_LA21_P +set_property -dict {PACKAGE_PIN F18 IOSTANDARD LVCMOS25} [get_ports adc_hw_rngsel[1]] ; ## FMC_LPC_LA26_P +set_property -dict {PACKAGE_PIN T19 IOSTANDARD LVCMOS25} [get_ports adc_busy] ; ## FMC_LPC_LA10_N +set_property -dict {PACKAGE_PIN E21 IOSTANDARD LVCMOS25} [get_ports adc_seq_en] ; ## FMC_LPC_LA27_P +set_property -dict {PACKAGE_PIN F19 IOSTANDARD LVCMOS25} [get_ports adc_reset_n] ; ## FMC_LPC_LA22_N +set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVCMOS25} [get_ports adc_cs_n] ; ## FMC_LPC_LA04_N + diff --git a/projects/ad7616_sdz/zed/serial_if_constr.xdc b/projects/ad7616_sdz/zed/serial_if_constr.xdc new file mode 100644 index 000000000..ab6704dba --- /dev/null +++ b/projects/ad7616_sdz/zed/serial_if_constr.xdc @@ -0,0 +1,29 @@ + +# ad7616 + +# data interface + +set_property -dict {PACKAGE_PIN P22 IOSTANDARD LVCMOS25} [get_ports spi_sclk] ; ## FMC_LPC_LA03_N +set_property -dict {PACKAGE_PIN L21 IOSTANDARD LVCMOS25} [get_ports spi_sdo] ; ## FMC_LPC_LA06_P +set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVCMOS25} [get_ports spi_sdi_0] ; ## FMC_LPC_LA00_CC_P +set_property -dict {PACKAGE_PIN N20 IOSTANDARD LVCMOS25} [get_ports spi_sdi_1] ; ## FMC_LPC_LA01_CC_N +set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVCMOS25} [get_ports spi_cs_n] ; ## FMC_LPC_LA04_N + +# control lines + +set_property -dict {PACKAGE_PIN A18 IOSTANDARD LVCMOS25} [get_ports adc_convst] ; ## FMC_LPC_LA24_P +set_property -dict {PACKAGE_PIN E20 IOSTANDARD LVCMOS25} [get_ports adc_chsel[0]] ; ## FMC_LPC_LA21_N +set_property -dict {PACKAGE_PIN E18 IOSTANDARD LVCMOS25} [get_ports adc_chsel[1]] ; ## FMC_LPC_LA26_N +set_property -dict {PACKAGE_PIN D22 IOSTANDARD LVCMOS25} [get_ports adc_chsel[2]] ; ## FMC_LPC_LA25_P +set_property -dict {PACKAGE_PIN E19 IOSTANDARD LVCMOS25} [get_ports adc_hw_rngsel[0]] ; ## FMC_LPC_LA21_P +set_property -dict {PACKAGE_PIN F18 IOSTANDARD LVCMOS25} [get_ports adc_hw_rngsel[1]] ; ## FMC_LPC_LA26_P +set_property -dict {PACKAGE_PIN T19 IOSTANDARD LVCMOS25} [get_ports adc_busy] ; ## FMC_LPC_LA10_N +set_property -dict {PACKAGE_PIN E21 IOSTANDARD LVCMOS25} [get_ports adc_seq_en] ; ## FMC_LPC_LA27_P +set_property -dict {PACKAGE_PIN F19 IOSTANDARD LVCMOS25} [get_ports adc_reset_n] ; ## FMC_LPC_LA22_N + +set_property -dict {PACKAGE_PIN L19 IOSTANDARD LVCMOS25} [get_ports adc_os[0]] ; ## FMC_LPC_CLK0_M2C_N +set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVCMOS25} [get_ports adc_os[1]] ; ## FMC_LPC_CLK0_M2C_P +set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVCMOS25} [get_ports adc_os[2]] ; ## FMC_LPC_LA01_CC_P +set_property -dict {PACKAGE_PIN R21 IOSTANDARD LVCMOS25} [get_ports adc_burst] ; ## FMC_LPC_LA09_N +set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS25} [get_ports adc_crcen] ; ## FMC_LPC_LA02_N + diff --git a/projects/ad7616_sdz/zed/system_bd.tcl b/projects/ad7616_sdz/zed/system_bd.tcl new file mode 100644 index 000000000..cf4941e23 --- /dev/null +++ b/projects/ad7616_sdz/zed/system_bd.tcl @@ -0,0 +1,4 @@ + +source $ad_hdl_dir/projects/common/zed/zed_system_bd.tcl +source ../common/ad7616_bd.tcl + diff --git a/projects/ad7616_sdz/zed/system_project.tcl b/projects/ad7616_sdz/zed/system_project.tcl new file mode 100644 index 000000000..e74dc8376 --- /dev/null +++ b/projects/ad7616_sdz/zed/system_project.tcl @@ -0,0 +1,46 @@ + +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/projects/scripts/adi_project.tcl +source $ad_hdl_dir/projects/scripts/adi_board.tcl + +##-------------------------------------------------------------- +# IMPORTANT: Set AD7616 operation and interface mode +# +# ad7616_if - Defines the interface type (serial OR parallel) +# +# LEGEND: Serial - 0 +# Parallel - 1 +# +# NOTE : This switch is a 'hardware' switch. Please reimplenent the +# design if the variable has been changed. +# +##-------------------------------------------------------------- + +set ad7616_if 0 + +adi_project_create ad7616_sdz_zed + +if { $ad7616_if == 0 } { + + adi_project_files ad7616_sdz_zed [list \ + "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \ + "system_top_si.v" \ + "serial_if_constr.xdc" \ + "$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc"] + +} elseif { $ad7616_if == 1 } { + + adi_project_files ad7616_sdz_zed [list \ + "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \ + "system_top_pi.v" \ + "parallel_if_constr.xdc" \ + "$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc"] + +} else { + + return -code error [format "ERROR: Invalid interface type! Define as \'serial\' or \'parallel\' ..."] + +} + +adi_project_run ad7616_sdz_zed + diff --git a/projects/fmcomms1/zed/system_top.v b/projects/ad7616_sdz/zed/system_top_pi.v similarity index 72% rename from projects/fmcomms1/zed/system_top.v rename to projects/ad7616_sdz/zed/system_top_pi.v index 8bf4fc58a..0a21783d3 100644 --- a/projects/fmcomms1/zed/system_top.v +++ b/projects/ad7616_sdz/zed/system_top_pi.v @@ -80,31 +80,24 @@ module system_top ( spdif, - dac_clk_in_p, - dac_clk_in_n, - dac_clk_out_p, - dac_clk_out_n, - dac_frame_out_p, - dac_frame_out_n, - dac_data_out_p, - dac_data_out_n, - - adc_clk_in_p, - adc_clk_in_n, - adc_or_in_p, - adc_or_in_n, - adc_data_in_p, - adc_data_in_n, - - ref_clk_out_p, - ref_clk_out_n, - iic_scl, iic_sda, iic_mux_scl, iic_mux_sda, - otg_vbusoc); + otg_vbusoc, + + adc_db, + adc_rd_n, + adc_wr_n, + + adc_cs_n, + adc_reset_n, + adc_convst, + adc_busy, + adc_seq_en, + adc_hw_rngsel, + adc_chsel); inout [14:0] ddr_addr; inout [ 2:0] ddr_ba; @@ -145,24 +138,6 @@ module system_top ( output i2s_sdata_out; input i2s_sdata_in; - input dac_clk_in_p; - input dac_clk_in_n; - output dac_clk_out_p; - output dac_clk_out_n; - output dac_frame_out_p; - output dac_frame_out_n; - output [15:0] dac_data_out_p; - output [15:0] dac_data_out_n; - - input adc_clk_in_p; - input adc_clk_in_n; - input adc_or_in_p; - input adc_or_in_n; - input [13:0] adc_data_in_p; - input [13:0] adc_data_in_n; - - output ref_clk_out_p; - output ref_clk_out_n; inout iic_scl; inout iic_sda; @@ -171,69 +146,76 @@ module system_top ( input otg_vbusoc; + inout [15:0] adc_db; + output adc_rd_n; + output adc_wr_n; + + output adc_cs_n; + output adc_reset_n; + output adc_convst; + input adc_busy; + output adc_seq_en; + output [ 1:0] adc_hw_rngsel; + output [ 2:0] adc_chsel; + // internal signals wire [63:0] gpio_i; wire [63:0] gpio_o; wire [63:0] gpio_t; - wire [ 2:0] spi0_csn; - wire spi0_clk; - wire spi0_mosi; - wire spi0_miso; - wire [ 2:0] spi1_csn; - wire spi1_clk; - wire spi1_mosi; - wire spi1_miso; - wire ref_clk; - wire oddr_ref_clk; - wire [ 1:0] iic_mux_scl_i_s; wire [ 1:0] iic_mux_scl_o_s; wire iic_mux_scl_t_s; wire [ 1:0] iic_mux_sda_i_s; wire [ 1:0] iic_mux_sda_o_s; wire iic_mux_sda_t_s; - wire [15:0] ps_intrs; + + wire adc_db_t; + wire [15:0] adc_db_o; + wire [15:0] adc_db_i; + + genvar i; // instantiations - ODDR #( - .DDR_CLK_EDGE ("SAME_EDGE"), - .INIT (1'b0), - .SRTYPE ("ASYNC")) - i_oddr_ref_clk ( - .S (1'b0), - .CE (1'b1), - .R (1'b0), - .C (ref_clk), - .D1 (1'b1), - .D2 (1'b0), - .Q (oddr_ref_clk)); + ad_iobuf #(.DATA_WIDTH(7)) i_iobuf_adc_cntrl ( + .dio_t ({gpio_t[43:41], gpio_t[37], gpio_t[35:33]}), + .dio_i ({gpio_o[43:41], gpio_o[37], gpio_o[35:33]}), + .dio_o ({gpio_i[43:41], gpio_i[37], gpio_i[35:33]}), + .dio_p ({adc_reset_n, // 43 + adc_hw_rngsel, // 42:41 + adc_seq_en, // 37 + adc_chsel})); // 35:33 - OBUFDS i_obufds_ref_clk ( - .I (oddr_ref_clk), - .O (ref_clk_out_p), - .OB (ref_clk_out_n)); + generate + for (i = 0; i < 16; i = i + 1) begin: adc_db_io + ad_iobuf i_iobuf_adc_db ( + .dio_t(adc_db_t), + .dio_i(adc_db_o[i]), + .dio_o(adc_db_i[i]), + .dio_p(adc_db[i])); + end + endgenerate ad_iobuf #( - .DATA_WIDTH(32)) - i_gpio_bd ( + .DATA_WIDTH(32) + ) i_iobuf_gpio ( .dio_t(gpio_t[31:0]), .dio_i(gpio_o[31:0]), .dio_o(gpio_i[31:0]), .dio_p(gpio_bd)); - ad_iobuf #( - .DATA_WIDTH(2)) - i_iic_mux_scl ( + ad_iobuf #( + .DATA_WIDTH(2) + ) i_iobuf_iic_mux_scl ( .dio_t({iic_mux_scl_t_s, iic_mux_scl_t_s}), .dio_i(iic_mux_scl_o_s), .dio_o(iic_mux_scl_i_s), .dio_p(iic_mux_scl)); ad_iobuf #( - .DATA_WIDTH(2)) - i_iic_mux_sda ( + .DATA_WIDTH(2) + ) i_iobuf_iic_mux_sda ( .dio_t({iic_mux_sda_t_s, iic_mux_sda_t_s}), .dio_i(iic_mux_sda_o_s), .dio_o(iic_mux_sda_i_s), @@ -264,20 +246,6 @@ module system_top ( .gpio_i (gpio_i), .gpio_o (gpio_o), .gpio_t (gpio_t), - .adc_clk_in_n (adc_clk_in_n), - .adc_clk_in_p (adc_clk_in_p), - .adc_data_in_n (adc_data_in_n), - .adc_data_in_p (adc_data_in_p), - .adc_or_in_n (adc_or_in_n), - .adc_or_in_p (adc_or_in_p), - .dac_clk_in_n (dac_clk_in_n), - .dac_clk_in_p (dac_clk_in_p), - .dac_clk_out_n (dac_clk_out_n), - .dac_clk_out_p (dac_clk_out_p), - .dac_data_out_n (dac_data_out_n), - .dac_data_out_p (dac_data_out_p), - .dac_frame_out_n (dac_frame_out_n), - .dac_frame_out_p (dac_frame_out_p), .hdmi_data (hdmi_data), .hdmi_data_e (hdmi_data_e), .hdmi_hsync (hdmi_hsync), @@ -307,27 +275,17 @@ module system_top ( .ps_intr_08 (1'b0), .ps_intr_09 (1'b0), .ps_intr_10 (1'b0), - .ref_clk (ref_clk), .otg_vbusoc (otg_vbusoc), .spdif (spdif), - .spi0_clk_i (spi0_clk), - .spi0_clk_o (spi0_clk), - .spi0_csn_0_o (spi0_csn[0]), - .spi0_csn_1_o (spi0_csn[1]), - .spi0_csn_2_o (spi0_csn[2]), - .spi0_csn_i (1'b1), - .spi0_sdi_i (spi0_miso), - .spi0_sdo_i (spi0_mosi), - .spi0_sdo_o (spi0_mosi), - .spi1_clk_i (spi1_clk), - .spi1_clk_o (spi1_clk), - .spi1_csn_0_o (spi1_csn[0]), - .spi1_csn_1_o (spi1_csn[1]), - .spi1_csn_2_o (spi1_csn[2]), - .spi1_csn_i (1'b1), - .spi1_sdi_i (1'b1), - .spi1_sdo_i (spi1_mosi), - .spi1_sdo_o (spi1_mosi)); + .rx_cnvst (adc_convst), + .rx_cs_n (adc_cs_n), + .rx_busy (adc_busy), + .rx_db_o (adc_db_o), + .rx_db_i (adc_db_i), + .rx_db_t (adc_db_t), + .rx_rd_n (adc_rd_n), + .rx_wr_n (adc_wr_n) + ); endmodule diff --git a/projects/fmcomms1/zc702/system_top.v b/projects/ad7616_sdz/zed/system_top_si.v similarity index 65% rename from projects/fmcomms1/zc702/system_top.v rename to projects/ad7616_sdz/zed/system_top_si.v index c1ddc048b..312baad48 100644 --- a/projects/fmcomms1/zc702/system_top.v +++ b/projects/ad7616_sdz/zed/system_top_si.v @@ -72,29 +72,36 @@ module system_top ( hdmi_data_e, hdmi_data, + i2s_mclk, + i2s_bclk, + i2s_lrclk, + i2s_sdata_out, + i2s_sdata_in, + spdif, - dac_clk_in_p, - dac_clk_in_n, - dac_clk_out_p, - dac_clk_out_n, - dac_frame_out_p, - dac_frame_out_n, - dac_data_out_p, - dac_data_out_n, - - adc_clk_in_p, - adc_clk_in_n, - adc_or_in_p, - adc_or_in_n, - adc_data_in_p, - adc_data_in_n, - - ref_clk_out_p, - ref_clk_out_n, - iic_scl, - iic_sda); + iic_sda, + iic_mux_scl, + iic_mux_sda, + + otg_vbusoc, + + spi_sclk, + spi_sdo, + spi_sdi_0, + spi_sdi_1, + spi_cs_n, + + adc_reset_n, + adc_convst, + adc_busy, + adc_seq_en, + adc_hw_rngsel, + adc_chsel, + adc_crcen, + adc_burst, + adc_os); inout [14:0] ddr_addr; inout [ 2:0] ddr_ba; @@ -119,7 +126,7 @@ module system_top ( inout fixed_io_ps_porb; inout fixed_io_ps_srstb; - inout [15:0] gpio_bd; + inout [31:0] gpio_bd; output hdmi_out_clk; output hdmi_vsync; @@ -129,73 +136,86 @@ module system_top ( output spdif; - input dac_clk_in_p; - input dac_clk_in_n; - output dac_clk_out_p; - output dac_clk_out_n; - output dac_frame_out_p; - output dac_frame_out_n; - output [15:0] dac_data_out_p; - output [15:0] dac_data_out_n; + output i2s_mclk; + output i2s_bclk; + output i2s_lrclk; + output i2s_sdata_out; + input i2s_sdata_in; - input adc_clk_in_p; - input adc_clk_in_n; - input adc_or_in_n; - input adc_or_in_p; - input [13:0] adc_data_in_n; - input [13:0] adc_data_in_p; - - output ref_clk_out_p; - output ref_clk_out_n; inout iic_scl; inout iic_sda; + inout [ 1:0] iic_mux_scl; + inout [ 1:0] iic_mux_sda; + + input otg_vbusoc; + + output spi_sclk; + output spi_sdo; + input spi_sdi_0; + input spi_sdi_1; + output spi_cs_n; + + output adc_reset_n; + output adc_convst; + input adc_busy; + output adc_seq_en; + output [ 1:0] adc_hw_rngsel; + output [ 2:0] adc_chsel; + output adc_crcen; + output adc_burst; + output [ 2:0] adc_os; // internal signals wire [63:0] gpio_i; wire [63:0] gpio_o; wire [63:0] gpio_t; - wire [ 2:0] spi0_csn; - wire spi0_clk; - wire spi0_mosi; - wire spi0_miso; - wire [ 2:0] spi1_csn; - wire spi1_clk; - wire spi1_mosi; - wire spi1_miso; - wire ref_clk; - wire oddr_ref_clk; - wire [15:0] ps_intrs; + wire [ 1:0] iic_mux_scl_i_s; + wire [ 1:0] iic_mux_scl_o_s; + wire iic_mux_scl_t_s; + wire [ 1:0] iic_mux_sda_i_s; + wire [ 1:0] iic_mux_sda_o_s; + wire iic_mux_sda_t_s; // instantiations - ODDR #( - .DDR_CLK_EDGE ("SAME_EDGE"), - .INIT (1'b0), - .SRTYPE ("ASYNC")) - i_oddr_ref_clk ( - .S (1'b0), - .CE (1'b1), - .R (1'b0), - .C (ref_clk), - .D1 (1'b1), - .D2 (1'b0), - .Q (oddr_ref_clk)); - - OBUFDS i_obufds_ref_clk ( - .I (oddr_ref_clk), - .O (ref_clk_out_p), - .OB (ref_clk_out_n)); + ad_iobuf #(.DATA_WIDTH(12)) i_iobuf_adc_cntrl ( + .dio_t (gpio_t[43:32]), + .dio_i (gpio_o[43:32]), + .dio_o (gpio_i[43:32]), + .dio_p ({adc_reset_n, // 43 + adc_hw_rngsel, // 42:41 + adc_os, // 40:38 + adc_seq_en, // 37 + adc_burst, // 36 + adc_chsel, // 35:33 + adc_crcen})); // 32 ad_iobuf #( - .DATA_WIDTH(16)) - i_gpio_bd ( - .dio_t(gpio_t[15:0]), - .dio_i(gpio_o[15:0]), - .dio_o(gpio_i[15:0]), + .DATA_WIDTH(32) + ) i_iobuf_gpio ( + .dio_t(gpio_t[31:0]), + .dio_i(gpio_o[31:0]), + .dio_o(gpio_i[31:0]), .dio_p(gpio_bd)); + ad_iobuf #( + .DATA_WIDTH(2) + ) i_iobuf_iic_mux_scl ( + .dio_t({iic_mux_scl_t_s, iic_mux_scl_t_s}), + .dio_i(iic_mux_scl_o_s), + .dio_o(iic_mux_scl_i_s), + .dio_p(iic_mux_scl)); + + ad_iobuf #( + .DATA_WIDTH(2) + ) i_iobuf_iic_mux_sda ( + .dio_t({iic_mux_sda_t_s, iic_mux_sda_t_s}), + .dio_i(iic_mux_sda_o_s), + .dio_o(iic_mux_sda_i_s), + .dio_p(iic_mux_sda)); + system_wrapper i_system_wrapper ( .ddr_addr (ddr_addr), .ddr_ba (ddr_ba), @@ -221,27 +241,24 @@ module system_top ( .gpio_i (gpio_i), .gpio_o (gpio_o), .gpio_t (gpio_t), - .adc_clk_in_n (adc_clk_in_n), - .adc_clk_in_p (adc_clk_in_p), - .adc_data_in_n (adc_data_in_n), - .adc_data_in_p (adc_data_in_p), - .adc_or_in_n (adc_or_in_n), - .adc_or_in_p (adc_or_in_p), - .dac_clk_in_n (dac_clk_in_n), - .dac_clk_in_p (dac_clk_in_p), - .dac_clk_out_n (dac_clk_out_n), - .dac_clk_out_p (dac_clk_out_p), - .dac_data_out_n (dac_data_out_n), - .dac_data_out_p (dac_data_out_p), - .dac_frame_out_n (dac_frame_out_n), - .dac_frame_out_p (dac_frame_out_p), .hdmi_data (hdmi_data), .hdmi_data_e (hdmi_data_e), .hdmi_hsync (hdmi_hsync), .hdmi_out_clk (hdmi_out_clk), .hdmi_vsync (hdmi_vsync), - .iic_main_scl_io (iic_scl), - .iic_main_sda_io (iic_sda), + .i2s_bclk (i2s_bclk), + .i2s_lrclk (i2s_lrclk), + .i2s_mclk (i2s_mclk), + .i2s_sdata_in (i2s_sdata_in), + .i2s_sdata_out (i2s_sdata_out), + .iic_fmc_scl_io (iic_scl), + .iic_fmc_sda_io (iic_sda), + .iic_mux_scl_i (iic_mux_scl_i_s), + .iic_mux_scl_o (iic_mux_scl_o_s), + .iic_mux_scl_t (iic_mux_scl_t_s), + .iic_mux_sda_i (iic_mux_sda_i_s), + .iic_mux_sda_o (iic_mux_sda_o_s), + .iic_mux_sda_t (iic_mux_sda_t_s), .ps_intr_00 (1'b0), .ps_intr_01 (1'b0), .ps_intr_02 (1'b0), @@ -253,27 +270,16 @@ module system_top ( .ps_intr_08 (1'b0), .ps_intr_09 (1'b0), .ps_intr_10 (1'b0), - .ps_intr_11 (1'b0), - .ref_clk (ref_clk), + .otg_vbusoc (otg_vbusoc), .spdif (spdif), - .spi0_clk_i (spi0_clk), - .spi0_clk_o (spi0_clk), - .spi0_csn_0_o (spi0_csn[0]), - .spi0_csn_1_o (spi0_csn[1]), - .spi0_csn_2_o (spi0_csn[2]), - .spi0_csn_i (1'b1), - .spi0_sdi_i (spi0_miso), - .spi0_sdo_i (spi0_mosi), - .spi0_sdo_o (spi0_mosi), - .spi1_clk_i (spi1_clk), - .spi1_clk_o (spi1_clk), - .spi1_csn_0_o (spi1_csn[0]), - .spi1_csn_1_o (spi1_csn[1]), - .spi1_csn_2_o (spi1_csn[2]), - .spi1_csn_i (1'b1), - .spi1_sdi_i (1'b1), - .spi1_sdo_i (spi1_mosi), - .spi1_sdo_o (spi1_mosi)); + .rx_cnvst (adc_convst), + .rx_sclk (spi_sclk), + .rx_sdo (spi_sdo), + .rx_sdi_0 (spi_sdi_0), + .rx_sdi_1 (spi_sdi_1), + .rx_cs_n (spi_cs_n), + .rx_busy (adc_busy) + ); endmodule diff --git a/projects/ad7768evb/Makefile b/projects/ad7768evb/Makefile new file mode 100644 index 000000000..141f88d2a --- /dev/null +++ b/projects/ad7768evb/Makefile @@ -0,0 +1,21 @@ +#################################################################################### +#################################################################################### +## Copyright 2011(c) Analog Devices, Inc. +## Auto-generated, do not modify! +#################################################################################### +#################################################################################### + +.PHONY: all clean clean-all +all: + -make -C zed all + + +clean: + make -C zed clean + + +clean-all: + make -C zed clean-all + +#################################################################################### +#################################################################################### diff --git a/projects/ad7768evb/common/ad7768_if.v b/projects/ad7768evb/common/ad7768_if.v new file mode 100644 index 000000000..c51f44e04 --- /dev/null +++ b/projects/ad7768evb/common/ad7768_if.v @@ -0,0 +1,553 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module ad7768_if ( + + // device-interface + + clk_in, + ready_in, + data_in, + + // data path interface + + adc_clk, + adc_valid, + adc_data, + + // control interface + + up_sshot, + up_format, + up_crc_enable, + up_crc_4_or_16_n, + up_status_clr, + up_status); + + // device-interface + + input clk_in; + input ready_in; + input [ 7:0] data_in; + + // data path interface + + output adc_clk; + output adc_valid; + output [ 31:0] adc_data; + + // control interface + + input up_sshot; + input [ 1:0] up_format; + input up_crc_enable; + input up_crc_4_or_16_n; + input [ 35:0] up_status_clr; + output [ 35:0] up_status; + + // internal registers + + reg [ 1:0] adc_status_8 = 'd0; + reg [ 2:0] adc_status_7 = 'd0; + reg [ 2:0] adc_status_6 = 'd0; + reg [ 2:0] adc_status_5 = 'd0; + reg [ 2:0] adc_status_4 = 'd0; + reg [ 2:0] adc_status_3 = 'd0; + reg [ 2:0] adc_status_2 = 'd0; + reg [ 2:0] adc_status_1 = 'd0; + reg [ 2:0] adc_status_0 = 'd0; + reg adc_valid = 'd0; + reg [ 31:0] adc_data = 'd0; + reg [ 2:0] adc_seq = 'd0; + reg [ 4:0] adc_status = 'd0; + reg [ 63:0] adc_crc_8 = 'd0; + reg [ 7:0] adc_crc_mismatch_int = 'd0; + reg adc_crc_valid = 'd0; + reg [ 7:0] adc_crc_data = 'd0; + reg [ 7:0] adc_crc_mismatch_8 = 'd0; + reg adc_valid_int = 'd0; + reg [ 31:0] adc_data_int = 'd0; + reg [ 2:0] adc_seq_int = 'd0; + reg adc_enable_int = 'd0; + reg [ 3:0] adc_crc_scnt_int = 'd0; + reg [ 3:0] adc_crc_scnt_8 = 'd0; + reg [ 23:0] adc_seq_data = 'd0; + reg adc_seq_fmatch = 'd0; + reg [ 23:0] adc_seq_fdata = 'd0; + reg adc_seq_foos = 'd0; + reg [ 7:0] adc_enable_8 = 'd0; + reg [ 23:0] adc_seq_8 = 'd0; + reg adc_valid_8 = 'd0; + reg [ 31:0] adc_data_8 = 'd0; + reg [ 7:0] adc_ch_valid_d = 'd0; + reg [255:0] adc_ch_data_d0 = 'd0; + reg [255:0] adc_ch_data_d1 = 'd0; + reg [255:0] adc_ch_data_d2 = 'd0; + reg [255:0] adc_ch_data_d3 = 'd0; + reg [255:0] adc_ch_data_d4 = 'd0; + reg [255:0] adc_ch_data_d5 = 'd0; + reg [255:0] adc_ch_data_d6 = 'd0; + reg [255:0] adc_ch_data_d7 = 'd0; + reg adc_ch_valid_0 = 'd0; + reg adc_ch_valid_1 = 'd0; + reg adc_ch_valid_2 = 'd0; + reg adc_ch_valid_3 = 'd0; + reg adc_ch_valid_4 = 'd0; + reg adc_ch_valid_5 = 'd0; + reg adc_ch_valid_6 = 'd0; + reg adc_ch_valid_7 = 'd0; + reg [ 31:0] adc_ch_data_0 = 'd0; + reg [ 31:0] adc_ch_data_1 = 'd0; + reg [ 31:0] adc_ch_data_2 = 'd0; + reg [ 31:0] adc_ch_data_3 = 'd0; + reg [ 31:0] adc_ch_data_4 = 'd0; + reg [ 31:0] adc_ch_data_5 = 'd0; + reg [ 31:0] adc_ch_data_6 = 'd0; + reg [ 31:0] adc_ch_data_7 = 'd0; + reg adc_ch_valid = 'd0; + reg [255:0] adc_ch_data = 'd0; + reg [ 8:0] adc_cnt_p = 'd0; + reg adc_valid_p = 'd0; + reg [255:0] adc_data_p = 'd0; + reg [ 7:0] adc_data_d1 = 'd0; + reg [ 7:0] adc_data_d2 = 'd0; + reg adc_ready_d1 = 'd0; + reg adc_ready = 'd0; + reg adc_ready_d = 'd0; + reg adc_sshot_m1 = 'd0; + reg adc_sshot = 'd0; + reg [ 1:0] adc_format_m1 = 'd0; + reg [ 1:0] adc_format = 'd0; + reg adc_crc_enable_m1 = 'd0; + reg adc_crc_enable = 'd0; + reg adc_crc_4_or_16_n_m1 = 'd0; + reg adc_crc_4_or_16_n = 'd0; + reg [ 35:0] adc_status_clr_m1 = 'd0; + reg [ 35:0] adc_status_clr = 'd0; + reg [ 35:0] adc_status_clr_d = 'd0; + + // internal signals + + wire [ 7:0] adc_crc_in_s; + wire [ 7:0] adc_crc_s; + wire adc_crc_mismatch_s; + wire adc_seq_fmatch_s; + wire adc_seq_fupdate_s; + wire [ 7:0] adc_enable_8_s; + wire [ 23:0] adc_seq_8_s; + wire adc_cnt_enable_1_s; + wire adc_cnt_enable_4_s; + wire adc_cnt_enable_8_s; + wire adc_cnt_enable_s; + wire [ 7:0] adc_data_in_s; + wire adc_ready_in_s; + wire adc_clk_in_s; + wire [ 35:0] adc_status_clr_s; + + // function (crc) + + function [ 7:0] crc8; + input [23:0] din; + input [ 7:0] cin; + reg [ 7:0] cout; + begin + cout[ 7] = cin[ 1] ^ cin[ 2] ^ cin[ 4] ^ cin[ 6] ^ din[ 5] ^ din[ 6] ^ din[ 7] ^ din[11] ^ + din[13] ^ din[15] ^ din[17] ^ din[18] ^ din[20] ^ din[22]; + cout[ 6] = cin[ 0] ^ cin[ 1] ^ cin[ 3] ^ cin[ 5] ^ din[ 4] ^ din[ 5] ^ din[ 6] ^ din[10] ^ + din[12] ^ din[14] ^ din[16] ^ din[17] ^ din[19] ^ din[21]; + cout[ 5] = cin[ 0] ^ cin[ 2] ^ cin[ 4] ^ din[ 3] ^ din[ 4] ^ din[ 5] ^ din[ 9] ^ din[11] ^ + din[13] ^ din[15] ^ din[16] ^ din[18] ^ din[20]; + cout[ 4] = cin[ 1] ^ cin[ 3] ^ din[ 2] ^ din[ 3] ^ din[ 4] ^ din[ 8] ^ din[10] ^ din[12] ^ + din[14] ^ din[15] ^ din[17] ^ din[19]; + cout[ 3] = cin[ 0] ^ cin[ 2] ^ cin[ 7] ^ din[ 1] ^ din[ 2] ^ din[ 3] ^ din[ 7] ^ din[ 9] ^ + din[11] ^ din[13] ^ din[14] ^ din[16] ^ din[18] ^ din[23]; + cout[ 2] = cin[ 1] ^ cin[ 6] ^ din[ 0] ^ din[ 1] ^ din[ 2] ^ din[ 6] ^ din[ 8] ^ din[10] ^ + din[12] ^ din[13] ^ din[15] ^ din[17] ^ din[22]; + cout[ 1] = cin[ 0] ^ cin[ 1] ^ cin[ 2] ^ cin[ 4] ^ cin[ 5] ^ cin[ 6] ^ cin[ 7] ^ din[ 0] ^ + din[ 1] ^ din[ 6] ^ din[ 9] ^ din[12] ^ din[13] ^ din[14] ^ din[15] ^ din[16] ^ + din[17] ^ din[18] ^ din[20] ^ din[21] ^ din[22] ^ din[23]; + cout[ 0] = cin[ 0] ^ cin[ 2] ^ cin[ 3] ^ cin[ 5] ^ cin[ 7] ^ din[ 0] ^ din[ 6] ^ din[ 7] ^ + din[ 8] ^ din[12] ^ din[14] ^ din[16] ^ din[18] ^ din[19] ^ din[21] ^ din[23]; + crc8 = cout; + end + endfunction + + // status + + assign up_status[35:32] = {2'd0, adc_status_8}; + assign up_status[31:28] = {1'd0, adc_status_7}; + assign up_status[27:24] = {1'd0, adc_status_6}; + assign up_status[23:20] = {1'd0, adc_status_5}; + assign up_status[19:16] = {1'd0, adc_status_4}; + assign up_status[15:12] = {1'd0, adc_status_3}; + assign up_status[11: 8] = {1'd0, adc_status_2}; + assign up_status[ 7: 4] = {1'd0, adc_status_1}; + assign up_status[ 3: 0] = {1'd0, adc_status_0}; + + always @(posedge adc_clk) begin + if (adc_valid == 1'b1) begin + adc_status_8 <= adc_status_8 | adc_status[1:0]; + end else begin + adc_status_8 <= adc_status_8 & ~adc_status_clr_s[33:32]; + end + if ((adc_valid == 1'b1) && (adc_seq[2:0] == 3'd7)) begin + adc_status_7 <= adc_status_7 | adc_status[4:2]; + end else begin + adc_status_7 <= adc_status_7 & ~adc_status_clr_s[30:28]; + end + if ((adc_valid == 1'b1) && (adc_seq[2:0] == 3'd6)) begin + adc_status_6 <= adc_status_6 | adc_status[4:2]; + end else begin + adc_status_6 <= adc_status_6 & ~adc_status_clr_s[26:24]; + end + if ((adc_valid == 1'b1) && (adc_seq[2:0] == 3'd5)) begin + adc_status_5 <= adc_status_5 | adc_status[4:2]; + end else begin + adc_status_5 <= adc_status_5 & ~adc_status_clr_s[22:20]; + end + if ((adc_valid == 1'b1) && (adc_seq[2:0] == 3'd4)) begin + adc_status_4 <= adc_status_4 | adc_status[4:2]; + end else begin + adc_status_4 <= adc_status_4 & ~adc_status_clr_s[18:16]; + end + if ((adc_valid == 1'b1) && (adc_seq[2:0] == 3'd3)) begin + adc_status_3 <= adc_status_3 | adc_status[4:2]; + end else begin + adc_status_3 <= adc_status_3 & ~adc_status_clr_s[14:12]; + end + if ((adc_valid == 1'b1) && (adc_seq[2:0] == 3'd2)) begin + adc_status_2 <= adc_status_2 | adc_status[4:2]; + end else begin + adc_status_2 <= adc_status_2 & ~adc_status_clr_s[10: 8]; + end + if ((adc_valid == 1'b1) && (adc_seq[2:0] == 3'd1)) begin + adc_status_1 <= adc_status_1 | adc_status[4:2]; + end else begin + adc_status_1 <= adc_status_1 & ~adc_status_clr_s[ 6: 4]; + end + if ((adc_valid == 1'b1) && (adc_seq[2:0] == 3'd0)) begin + adc_status_0 <= adc_status_0 | adc_status[4:2]; + end else begin + adc_status_0 <= adc_status_0 & ~adc_status_clr_s[ 2: 0]; + end + end + + // data & status + + always @(posedge adc_clk) begin + adc_valid <= adc_valid_int & adc_enable_int; + adc_data <= {{8{adc_data_int[23]}}, adc_data_int[23:0]}; + adc_seq <= adc_seq_int; + if ((adc_crc_enable == 1'b1) && (adc_crc_scnt_int == 4'd0)) begin + adc_status[4] <= adc_crc_mismatch_8[7] & adc_enable_int; + adc_status[3] <= 1'b0; + adc_status[2] <= 1'b0; + adc_status[1] <= 1'b0; + adc_status[0] <= adc_seq_foos; + end else begin + adc_status[4] <= adc_crc_mismatch_8[7] & adc_enable_int; + adc_status[3] <= adc_data_int[30] & adc_enable_int; + adc_status[2] <= adc_data_int[27] & adc_enable_int; + adc_status[1] <= adc_data_int[31] & adc_enable_int; + adc_status[0] <= adc_seq_foos; + end + end + + // crc- not much useful at the interface, since it is post-framing + + assign adc_crc_in_s = (adc_crc_scnt_int == 4'd1) ? 8'hff : adc_crc_8[63:56]; + assign adc_crc_s = crc8(adc_data_int[23:0], adc_crc_in_s); + assign adc_crc_mismatch_s = (adc_crc_data == adc_crc_8[7:0]) ? 1'b0 : adc_crc_enable; + + always @(posedge adc_clk) begin + if (adc_valid_int == 1'b1) begin + adc_crc_8 <= {adc_crc_8[55:0], adc_crc_s}; + end + if (adc_valid_int == 1'b1) begin + adc_crc_mismatch_int <= {adc_crc_mismatch_int[6:0], 1'd0}; + end else begin + adc_crc_mismatch_int <= adc_crc_mismatch_8; + end + if (adc_crc_scnt_int == 4'd0) begin + adc_crc_valid <= adc_valid_int; + end else begin + adc_crc_valid <= 1'd0; + end + adc_crc_data <= adc_data_int[31:24]; + if (adc_crc_valid == 1'b1) begin + adc_crc_mismatch_8 <= {adc_crc_mismatch_8[6:0], adc_crc_mismatch_s}; + end + end + + // data interleaved & all-aligned + + always @(posedge adc_clk) begin + adc_valid_int <= adc_valid_8; + adc_data_int <= adc_data_8; + adc_seq_int <= adc_seq_8[23:21]; + adc_enable_int <= adc_enable_8[7] & adc_valid_8; + adc_crc_scnt_int <= adc_crc_scnt_8; + end + + // crc- count + + always @(posedge adc_clk) begin + if ((adc_ready == 1'b0) && (adc_ready_d == 1'b1)) begin + if (adc_seq_fmatch_s == 1'b0) begin + adc_crc_scnt_8 <= 4'd1; + end else if ((adc_crc_4_or_16_n == 1'b1) && (adc_crc_scnt_8 == 4'h3)) begin + adc_crc_scnt_8 <= 4'd0; + end else begin + adc_crc_scnt_8 <= adc_crc_scnt_8 + 1'b1; + end + end + end + + // three sample framing logic + + always @(posedge adc_clk) begin + if (adc_ready == 1'b0) begin + adc_seq_data <= 24'd0; + end else if (adc_valid_8 == 1'b1) begin + adc_seq_data <= {adc_seq_data[20:0], adc_data_8[26:24]}; + end + end + + assign adc_seq_fmatch_s = (adc_seq_data == adc_seq_fdata) ? 1'b1 : 1'b0; + assign adc_seq_fupdate_s = adc_seq_fmatch_s ^ adc_seq_fmatch; + + always @(posedge adc_clk) begin + if ((adc_ready == 1'b0) && (adc_ready_d == 1'b1)) begin + adc_seq_fmatch <= adc_seq_fmatch_s; + if (adc_seq_foos == 1'b1) begin + adc_seq_fdata <= adc_seq_data; + end + if (adc_seq_fupdate_s == 1'b0) begin + adc_seq_foos <= ~adc_seq_fmatch_s; + end + end + end + + // we are cluless on 0 -- safe to compare all 32bits against 0x0? + + assign adc_enable_8_s[7] = (adc_seq_8[23:21] == adc_seq_fdata[23:21]) ? 1'b1 : 1'b0; + assign adc_enable_8_s[6] = (adc_seq_8[20:18] == adc_seq_fdata[20:18]) ? 1'b1 : 1'b0; + assign adc_enable_8_s[5] = (adc_seq_8[17:15] == adc_seq_fdata[17:15]) ? 1'b1 : 1'b0; + assign adc_enable_8_s[4] = (adc_seq_8[14:12] == adc_seq_fdata[14:12]) ? 1'b1 : 1'b0; + assign adc_enable_8_s[3] = (adc_seq_8[11: 9] == adc_seq_fdata[11: 9]) ? 1'b1 : 1'b0; + assign adc_enable_8_s[2] = (adc_seq_8[ 8: 6] == adc_seq_fdata[ 8: 6]) ? 1'b1 : 1'b0; + assign adc_enable_8_s[1] = (adc_seq_8[ 5: 3] == adc_seq_fdata[ 5: 3]) ? 1'b1 : 1'b0; + assign adc_enable_8_s[0] = (adc_seq_8[ 2: 0] == adc_seq_fdata[ 2: 0]) ? 1'b1 : 1'b0; + + always @(posedge adc_clk) begin + if (adc_ready_d == 1'b0) begin + adc_enable_8 <= adc_enable_8_s; + end else if (adc_valid_8 == 1'b1) begin + adc_enable_8 <= {adc_enable_8[6:0], 1'd0}; + end + end + + // channel-sequence + + assign adc_seq_8_s[23:21] = (adc_format == 2'b01) ? 3'd0 : 3'd0; + assign adc_seq_8_s[20:18] = (adc_format == 2'b01) ? 3'd4 : 3'd1; + assign adc_seq_8_s[17:15] = (adc_format == 2'b01) ? 3'd1 : 3'd2; + assign adc_seq_8_s[14:12] = (adc_format == 2'b01) ? 3'd5 : 3'd3; + assign adc_seq_8_s[11: 9] = (adc_format == 2'b01) ? 3'd2 : 3'd4; + assign adc_seq_8_s[ 8: 6] = (adc_format == 2'b01) ? 3'd6 : 3'd5; + assign adc_seq_8_s[ 5: 3] = (adc_format == 2'b01) ? 3'd3 : 3'd6; + assign adc_seq_8_s[ 2: 0] = (adc_format == 2'b01) ? 3'd7 : 3'd7; + + always @(posedge adc_clk) begin + if ((adc_ready == 1'b0) && (adc_ready_d == 1'b1)) begin + adc_seq_8 <= adc_seq_8_s; + end else if (adc_valid_8 == 1'b1) begin + adc_seq_8 <= {adc_seq_8[20:0], 3'd0}; + end + end + + // data (interleaving) + + always @(posedge adc_clk) begin + adc_valid_8 <= adc_ch_valid_0 | adc_ch_valid_1 | adc_ch_valid_2 | adc_ch_valid_3 | + adc_ch_valid_4 | adc_ch_valid_5 | adc_ch_valid_6 | adc_ch_valid_7; + adc_data_8 <= adc_ch_data_0 | adc_ch_data_1 | adc_ch_data_2 | adc_ch_data_3 | + adc_ch_data_4 | adc_ch_data_5 | adc_ch_data_6 | adc_ch_data_7; + end + + always @(posedge adc_clk) begin + adc_ch_valid_d <= {adc_ch_valid_d[6:0], adc_ch_valid}; + adc_ch_data_d0[((32*0)+31):(32*0)] <= adc_ch_data[((32*0)+31):(32*0)]; + adc_ch_data_d0[((32*7)+31):(32*1)] <= adc_ch_data_d0[((32*6)+31):(32*0)]; + adc_ch_data_d1[((32*0)+31):(32*0)] <= adc_ch_data[((32*1)+31):(32*1)]; + adc_ch_data_d1[((32*7)+31):(32*1)] <= adc_ch_data_d1[((32*6)+31):(32*0)]; + adc_ch_data_d2[((32*0)+31):(32*0)] <= adc_ch_data[((32*2)+31):(32*2)]; + adc_ch_data_d2[((32*7)+31):(32*1)] <= adc_ch_data_d2[((32*6)+31):(32*0)]; + adc_ch_data_d3[((32*0)+31):(32*0)] <= adc_ch_data[((32*3)+31):(32*3)]; + adc_ch_data_d3[((32*7)+31):(32*1)] <= adc_ch_data_d3[((32*6)+31):(32*0)]; + adc_ch_data_d4[((32*0)+31):(32*0)] <= adc_ch_data[((32*4)+31):(32*4)]; + adc_ch_data_d4[((32*7)+31):(32*1)] <= adc_ch_data_d4[((32*6)+31):(32*0)]; + adc_ch_data_d5[((32*0)+31):(32*0)] <= adc_ch_data[((32*5)+31):(32*5)]; + adc_ch_data_d5[((32*7)+31):(32*1)] <= adc_ch_data_d5[((32*6)+31):(32*0)]; + adc_ch_data_d6[((32*0)+31):(32*0)] <= adc_ch_data[((32*6)+31):(32*6)]; + adc_ch_data_d6[((32*7)+31):(32*1)] <= adc_ch_data_d6[((32*6)+31):(32*0)]; + adc_ch_data_d7[((32*0)+31):(32*0)] <= adc_ch_data[((32*7)+31):(32*7)]; + adc_ch_data_d7[((32*7)+31):(32*1)] <= adc_ch_data_d7[((32*6)+31):(32*0)]; + end + + always @(posedge adc_clk) begin + adc_ch_valid_0 <= adc_ch_valid_d[0]; + adc_ch_valid_1 <= adc_ch_valid_d[1] & ~adc_format[1]; + adc_ch_valid_2 <= adc_ch_valid_d[2] & ~adc_format[1] & ~adc_format[0]; + adc_ch_valid_3 <= adc_ch_valid_d[3] & ~adc_format[1] & ~adc_format[0]; + adc_ch_valid_4 <= adc_ch_valid_d[4] & ~adc_format[1] & ~adc_format[0]; + adc_ch_valid_5 <= adc_ch_valid_d[5] & ~adc_format[1] & ~adc_format[0]; + adc_ch_valid_6 <= adc_ch_valid_d[6] & ~adc_format[1] & ~adc_format[0]; + adc_ch_valid_7 <= adc_ch_valid_d[7] & ~adc_format[1] & ~adc_format[0]; + adc_ch_data_0 <= adc_ch_data_d0[((32*0)+31):(32*0)]; + adc_ch_data_1 <= adc_ch_data_d1[((32*1)+31):(32*1)]; + adc_ch_data_2 <= adc_ch_data_d2[((32*2)+31):(32*2)]; + adc_ch_data_3 <= adc_ch_data_d3[((32*3)+31):(32*3)]; + adc_ch_data_4 <= adc_ch_data_d4[((32*4)+31):(32*4)]; + adc_ch_data_5 <= adc_ch_data_d5[((32*5)+31):(32*5)]; + adc_ch_data_6 <= adc_ch_data_d6[((32*6)+31):(32*6)]; + adc_ch_data_7 <= adc_ch_data_d7[((32*7)+31):(32*7)]; + end + + always @(posedge adc_clk) begin + adc_ch_valid <= adc_valid_p; + if (adc_valid_p == 1'b1) begin + adc_ch_data <= adc_data_p; + end else begin + adc_ch_data <= 256'd0; + end + end + + // data (common) + + assign adc_cnt_enable_1_s = (adc_cnt_p <= 9'h01f) ? 1'b1 : 1'b0; + assign adc_cnt_enable_4_s = (adc_cnt_p <= 9'h07f) ? 1'b1 : 1'b0; + assign adc_cnt_enable_8_s = (adc_cnt_p <= 9'h0ff) ? 1'b1 : 1'b0; + + assign adc_cnt_enable_s = (adc_format == 2'b00) ? adc_cnt_enable_1_s : + ((adc_format == 2'b01) ? adc_cnt_enable_4_s : adc_cnt_enable_8_s); + + always @(posedge adc_clk) begin + if (adc_ready == 1'b0) begin + adc_cnt_p <= 9'h000; + end else if (adc_cnt_enable_s == 1'b1) begin + adc_cnt_p <= adc_cnt_p + 1'b1; + end + if (adc_cnt_p[4:0] == 5'h1f) begin + adc_valid_p <= 1'b1; + end else begin + adc_valid_p <= 1'b0; + end + end + + // data (individual lanes) + + genvar n; + generate + for (n = 0; n < 8; n = n + 1) begin: g_data + + always @(posedge adc_clk) begin + if (adc_cnt_p[4:0] == 5'h00) begin + adc_data_p[((32*n)+31):(32*n)] <= {31'd0, adc_data_d2[n]}; + end else begin + adc_data_p[((32*n)+31):(32*n)] <= {adc_data_p[((32*n)+30):(32*n)], adc_data_d2[n]}; + end + end + + always @(posedge adc_clk) begin + adc_data_d1[n] <= adc_data_in_s[n]; + adc_data_d2[n] <= adc_data_d1[n]; + end + + IBUF i_ibuf_data ( + .I (data_in[n]), + .O (adc_data_in_s[n])); + + end + endgenerate + + // ready (single shot or continous) + + always @(posedge adc_clk) begin + adc_ready_d1 <= adc_ready_in_s; + adc_ready <= adc_sshot ~^ adc_ready_d1; + adc_ready_d <= adc_ready; + end + + IBUF i_ibuf_ready ( + .I (ready_in), + .O (adc_ready_in_s)); + + // clock (use bufg delay ~4ns on 29ns) + + BUFG i_bufg_clk ( + .I (adc_clk_in_s), + .O (adc_clk)); + + IBUFG i_ibufg_clk ( + .I (clk_in), + .O (adc_clk_in_s)); + + // control signals + + assign adc_status_clr_s = adc_status_clr & ~adc_status_clr_d; + + always @(posedge adc_clk) begin + adc_sshot_m1 <= up_sshot; + adc_sshot <= adc_sshot_m1; + adc_format_m1 <= up_format; + adc_format <= adc_format_m1; + adc_crc_enable_m1 <= up_crc_enable; + adc_crc_enable <= adc_crc_enable_m1; + adc_crc_4_or_16_n_m1 <= up_crc_4_or_16_n; + adc_crc_4_or_16_n <= adc_crc_4_or_16_n_m1; + adc_status_clr_m1 <= up_status_clr; + adc_status_clr <= adc_status_clr_m1; + adc_status_clr_d <= adc_status_clr; + end + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/projects/ad7768evb/common/ad7768evb_bd.tcl b/projects/ad7768evb/common/ad7768evb_bd.tcl new file mode 100644 index 000000000..69369dc1f --- /dev/null +++ b/projects/ad7768evb/common/ad7768evb_bd.tcl @@ -0,0 +1,62 @@ + +# ad7768 interface + +create_bd_port -dir I adc_clk +create_bd_port -dir I adc_valid +create_bd_port -dir I -from 31 -to 0 adc_data +create_bd_port -dir I -from 31 -to 0 adc_gpio_0_i +create_bd_port -dir O -from 31 -to 0 adc_gpio_0_o +create_bd_port -dir O -from 31 -to 0 adc_gpio_0_t +create_bd_port -dir I -from 31 -to 0 adc_gpio_1_i +create_bd_port -dir O -from 31 -to 0 adc_gpio_1_o +create_bd_port -dir O -from 31 -to 0 adc_gpio_1_t + +# instances + +set ad7768_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 ad7768_dma] +set_property -dict [list CONFIG.DMA_TYPE_SRC {2}] $ad7768_dma +set_property -dict [list CONFIG.DMA_TYPE_DEST {0}] $ad7768_dma +set_property -dict [list CONFIG.CYCLIC {0}] $ad7768_dma +set_property -dict [list CONFIG.SYNC_TRANSFER_START {1}] $ad7768_dma +set_property -dict [list CONFIG.AXI_SLICE_SRC {0}] $ad7768_dma +set_property -dict [list CONFIG.AXI_SLICE_DEST {0}] $ad7768_dma +set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $ad7768_dma +set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {32}] $ad7768_dma + +# ps7-hp1 + +set_property -dict [list CONFIG.PCW_USE_S_AXI_HP1 {1}] $sys_ps7 + +# gpio + +set ad7768_gpio [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 ad7768_gpio] +set_property -dict [list CONFIG.C_IS_DUAL {1}] $ad7768_gpio +set_property -dict [list CONFIG.C_GPIO_WIDTH {32}] $ad7768_gpio +set_property -dict [list CONFIG.C_GPIO2_WIDTH {32}] $ad7768_gpio +set_property -dict [list CONFIG.C_INTERRUPT_PRESENT {1}] $ad7768_gpio + +# interconnects + +ad_connect adc_clk ad7768_dma/fifo_wr_clk +ad_connect adc_valid ad7768_dma/fifo_wr_en +ad_connect adc_data ad7768_dma/fifo_wr_din +ad_connect adc_gpio_0_i ad7768_gpio/gpio_io_i +ad_connect adc_gpio_0_o ad7768_gpio/gpio_io_o +ad_connect adc_gpio_0_t ad7768_gpio/gpio_io_t +ad_connect adc_gpio_1_i ad7768_gpio/gpio2_io_i +ad_connect adc_gpio_1_o ad7768_gpio/gpio2_io_o +ad_connect adc_gpio_1_t ad7768_gpio/gpio2_io_t + +# interrupts + +ad_cpu_interrupt ps-13 mb-13 ad7768_dma/irq +ad_cpu_interrupt ps-12 mb-12 ad7768_gpio/ip2intc_irpt + +# cpu / memory interconnects + +ad_cpu_interconnect 0x7C400000 ad7768_dma +ad_cpu_interconnect 0x7C420000 ad7768_gpio + +ad_mem_hp1_interconnect sys_cpu_clk sys_ps7/S_AXI_HP1 +ad_mem_hp1_interconnect sys_cpu_clk ad7768_dma/m_dest_axi + diff --git a/projects/fmcomms1/zed/Makefile b/projects/ad7768evb/zed/Makefile similarity index 69% rename from projects/fmcomms1/zed/Makefile rename to projects/ad7768evb/zed/Makefile index 79e54721f..c15c5a91f 100644 --- a/projects/fmcomms1/zed/Makefile +++ b/projects/ad7768evb/zed/Makefile @@ -9,24 +9,20 @@ M_DEPS += system_top.v M_DEPS += system_project.tcl M_DEPS += system_constr.xdc M_DEPS += system_bd.tcl -M_DEPS += ../common/fmcomms1_bd.tcl +M_DEPS += ../common/ad7768evb_bd.tcl +M_DEPS += ../common/ad7768_if.v M_DEPS += ../../scripts/adi_project.tcl M_DEPS += ../../scripts/adi_env.tcl M_DEPS += ../../scripts/adi_board.tcl M_DEPS += ../../common/zed/zed_system_constr.xdc M_DEPS += ../../common/zed/zed_system_bd.tcl -M_DEPS += ../../../library/common/ad_iobuf.v -M_DEPS += ../../../library/axi_ad9122/axi_ad9122.xpr -M_DEPS += ../../../library/axi_ad9643/axi_ad9643.xpr +M_DEPS += ../../../library/xilinx/common/ad_iobuf.v M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr M_DEPS += ../../../library/axi_i2s_adi/axi_i2s_adi.xpr M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr -M_DEPS += ../../../library/util_cpack/util_cpack.xpr M_DEPS += ../../../library/util_i2c_mixer/util_i2c_mixer.xpr -M_DEPS += ../../../library/util_upack/util_upack.xpr -M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr M_VIVADO := vivado -mode batch -source @@ -42,11 +38,12 @@ M_FLIST += *.sdk M_FLIST += *.hw M_FLIST += *.sim M_FLIST += .Xil +M_FLIST += *.ip_user_files .PHONY: all lib clean clean-all -all: lib fmcomms1_zed.sdk/system_top.hdf +all: lib ad7768evb_zed.sdk/system_top.hdf clean: @@ -54,36 +51,26 @@ clean: clean-all:clean - make -C ../../../library/axi_ad9122 clean - make -C ../../../library/axi_ad9643 clean make -C ../../../library/axi_clkgen clean make -C ../../../library/axi_dmac clean make -C ../../../library/axi_hdmi_tx clean make -C ../../../library/axi_i2s_adi clean make -C ../../../library/axi_spdif_tx clean - make -C ../../../library/util_cpack clean make -C ../../../library/util_i2c_mixer clean - make -C ../../../library/util_upack clean - make -C ../../../library/util_wfifo clean -fmcomms1_zed.sdk/system_top.hdf: $(M_DEPS) - rm -rf $(M_FLIST) - $(M_VIVADO) system_project.tcl >> fmcomms1_zed_vivado.log 2>&1 +ad7768evb_zed.sdk/system_top.hdf: $(M_DEPS) + -rm -rf $(M_FLIST) + $(M_VIVADO) system_project.tcl >> ad7768evb_zed_vivado.log 2>&1 lib: - make -C ../../../library/axi_ad9122 - make -C ../../../library/axi_ad9643 make -C ../../../library/axi_clkgen make -C ../../../library/axi_dmac make -C ../../../library/axi_hdmi_tx make -C ../../../library/axi_i2s_adi make -C ../../../library/axi_spdif_tx - make -C ../../../library/util_cpack make -C ../../../library/util_i2c_mixer - make -C ../../../library/util_upack - make -C ../../../library/util_wfifo #################################################################################### #################################################################################### diff --git a/projects/ad7768evb/zed/system_bd.tcl b/projects/ad7768evb/zed/system_bd.tcl new file mode 100644 index 000000000..ec644da27 --- /dev/null +++ b/projects/ad7768evb/zed/system_bd.tcl @@ -0,0 +1,4 @@ + +source $ad_hdl_dir/projects/common/zed/zed_system_bd.tcl +source ../common/ad7768evb_bd.tcl + diff --git a/projects/ad7768evb/zed/system_constr.xdc b/projects/ad7768evb/zed/system_constr.xdc new file mode 100644 index 000000000..0ecfe8c9d --- /dev/null +++ b/projects/ad7768evb/zed/system_constr.xdc @@ -0,0 +1,29 @@ + + +set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVCMOS25} [get_ports clk_in] ; ## H04 FMC_LPC_CLK0_M2C_P IO_L12P_T1_MRCC_34 +set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVCMOS25} [get_ports ready_in] ; ## G06 FMC_LPC_LA00_CC_P IO_L13P_T2_MRCC_34 +set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVCMOS25} [get_ports data_in[0]] ; ## G07 FMC_LPC_LA00_CC_N IO_L13N_T2_MRCC_34 +set_property -dict {PACKAGE_PIN L22 IOSTANDARD LVCMOS25} [get_ports data_in[1]] ; ## C11 FMC_LPC_LA06_N IO_L10N_T1_34 +set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [get_ports data_in[2]] ; ## H07 FMC_LPC_LA02_P IO_L20P_T3_34 +set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS25} [get_ports data_in[3]] ; ## H08 FMC_LPC_LA02_N IO_L20N_T3_34 +set_property -dict {PACKAGE_PIN J21 IOSTANDARD LVCMOS25} [get_ports data_in[4]] ; ## G12 FMC_LPC_LA08_P IO_L8P_T1_34 +set_property -dict {PACKAGE_PIN J22 IOSTANDARD LVCMOS25} [get_ports data_in[5]] ; ## G13 FMC_LPC_LA08_N IO_L8N_T1_34 +set_property -dict {PACKAGE_PIN R20 IOSTANDARD LVCMOS25} [get_ports data_in[6]] ; ## D14 FMC_LPC_LA09_P IO_L17P_T2_34 +set_property -dict {PACKAGE_PIN R21 IOSTANDARD LVCMOS25} [get_ports data_in[7]] ; ## D15 FMC_LPC_LA09_N IO_L17N_T2_34 +set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS25} [get_ports spi_csn] ; ## D11 FMC_LPC_LA05_P IO_L7P_T1_34 +set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVCMOS25} [get_ports spi_clk] ; ## D08 FMC_LPC_LA01_CC_P IO_L14P_T2_SRCC_34 +set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVCMOS25} [get_ports spi_mosi] ; ## H11 FMC_LPC_LA04_N IO_L15N_T2_DQS_34 +set_property -dict {PACKAGE_PIN N22 IOSTANDARD LVCMOS25} [get_ports spi_miso] ; ## G09 FMC_LPC_LA03_P IO_L16P_T2_34 +set_property -dict {PACKAGE_PIN T19 IOSTANDARD LVCMOS25} [get_ports gpio_0_mode_0] ; ## C15 FMC_LPC_LA10_N IO_L22N_T3_34 +set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVCMOS25} [get_ports gpio_1_mode_1] ; ## H13 FMC_LPC_LA07_P IO_L21P_T3_DQS_34 +set_property -dict {PACKAGE_PIN T17 IOSTANDARD LVCMOS25} [get_ports gpio_2_mode_2] ; ## H14 FMC_LPC_LA07_N IO_L21N_T3_DQS_34 +set_property -dict {PACKAGE_PIN N17 IOSTANDARD LVCMOS25} [get_ports gpio_3_mode_3] ; ## H16 FMC_LPC_LA11_P IO_L5P_T0_34 +set_property -dict {PACKAGE_PIN R19 IOSTANDARD LVCMOS25} [get_ports gpio_4_filter] ; ## C14 FMC_LPC_LA10_P IO_L22P_T3_34 +set_property -dict {PACKAGE_PIN L21 IOSTANDARD LVCMOS25} [get_ports reset_n] ; ## C10 FMC_LPC_LA06_P IO_L10P_T1_34 +set_property -dict {PACKAGE_PIN P22 IOSTANDARD LVCMOS25} [get_ports start_n] ; ## G10 FMC_LPC_LA03_N IO_L16N_T2_34 +set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVCMOS25} [get_ports sync_n] ; ## H10 FMC_LPC_LA04_P IO_L15P_T2_DQS_34 +set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVCMOS25} [get_ports sync_in_n] ; ## D12 FMC_LPC_LA05_N IO_L7N_T1_34 +set_property -dict {PACKAGE_PIN N20 IOSTANDARD LVCMOS25} [get_ports mclk] ; ## D09 FMC_LPC_LA01_CC_N IO_L14N_T2_SRCC_34 + +create_clock -name adc_clk -period 20 [get_ports clk_in] + diff --git a/projects/ad7768evb/zed/system_project.tcl b/projects/ad7768evb/zed/system_project.tcl new file mode 100644 index 000000000..3373673c1 --- /dev/null +++ b/projects/ad7768evb/zed/system_project.tcl @@ -0,0 +1,15 @@ + +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/projects/scripts/adi_project.tcl +source $ad_hdl_dir/projects/scripts/adi_board.tcl + +adi_project_create ad7768evb_zed +adi_project_files ad7768evb_zed [list \ + "../common/ad7768_if.v" \ + "system_top.v" \ + "system_constr.xdc" \ + "$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc" \ + "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" ] + +adi_project_run ad7768evb_zed + diff --git a/projects/ad7768evb/zed/system_top.v b/projects/ad7768evb/zed/system_top.v new file mode 100644 index 000000000..64814dba9 --- /dev/null +++ b/projects/ad7768evb/zed/system_top.v @@ -0,0 +1,341 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top ( + + ddr_addr, + ddr_ba, + ddr_cas_n, + ddr_ck_n, + ddr_ck_p, + ddr_cke, + ddr_cs_n, + ddr_dm, + ddr_dq, + ddr_dqs_n, + ddr_dqs_p, + ddr_odt, + ddr_ras_n, + ddr_reset_n, + ddr_we_n, + + fixed_io_ddr_vrn, + fixed_io_ddr_vrp, + fixed_io_mio, + fixed_io_ps_clk, + fixed_io_ps_porb, + fixed_io_ps_srstb, + + gpio_bd, + + hdmi_out_clk, + hdmi_vsync, + hdmi_hsync, + hdmi_data_e, + hdmi_data, + + i2s_mclk, + i2s_bclk, + i2s_lrclk, + i2s_sdata_out, + i2s_sdata_in, + + spdif, + + iic_scl, + iic_sda, + iic_mux_scl, + iic_mux_sda, + + otg_vbusoc, + + clk_in, + ready_in, + data_in, + + spi_csn, + spi_clk, + spi_mosi, + spi_miso, + + gpio_0_mode_0, + gpio_1_mode_1, + gpio_2_mode_2, + gpio_3_mode_3, + gpio_4_filter, + reset_n, + start_n, + sync_n, + sync_in_n, + mclk); + + inout [14:0] ddr_addr; + inout [ 2:0] ddr_ba; + inout ddr_cas_n; + inout ddr_ck_n; + inout ddr_ck_p; + inout ddr_cke; + inout ddr_cs_n; + inout [ 3:0] ddr_dm; + inout [31:0] ddr_dq; + inout [ 3:0] ddr_dqs_n; + inout [ 3:0] ddr_dqs_p; + inout ddr_odt; + inout ddr_ras_n; + inout ddr_reset_n; + inout ddr_we_n; + + inout fixed_io_ddr_vrn; + inout fixed_io_ddr_vrp; + inout [53:0] fixed_io_mio; + inout fixed_io_ps_clk; + inout fixed_io_ps_porb; + inout fixed_io_ps_srstb; + + inout [31:0] gpio_bd; + + output hdmi_out_clk; + output hdmi_vsync; + output hdmi_hsync; + output hdmi_data_e; + output [15:0] hdmi_data; + + output spdif; + + output i2s_mclk; + output i2s_bclk; + output i2s_lrclk; + output i2s_sdata_out; + input i2s_sdata_in; + + inout iic_scl; + inout iic_sda; + inout [ 1:0] iic_mux_scl; + inout [ 1:0] iic_mux_sda; + + input otg_vbusoc; + + input clk_in; + input ready_in; + input [ 7:0] data_in; + + output spi_csn; + output spi_clk; + output spi_mosi; + input spi_miso; + + inout gpio_0_mode_0; + inout gpio_1_mode_1; + inout gpio_2_mode_2; + inout gpio_3_mode_3; + inout gpio_4_filter; + inout reset_n; + inout start_n; + inout sync_n; + inout sync_in_n; + output mclk; + + // internal signals + + wire adc_clk; + wire adc_valid; + wire [31:0] adc_data; + wire up_sshot; + wire [ 1:0] up_format; + wire up_crc_enable; + wire up_crc_4_or_16_n; + wire [63:0] adc_gpio_i; + wire [63:0] adc_gpio_o; + wire [63:0] adc_gpio_t; + wire [63:0] gpio_i; + wire [63:0] gpio_o; + wire [63:0] gpio_t; + wire [ 1:0] iic_mux_scl_i_s; + wire [ 1:0] iic_mux_scl_o_s; + wire iic_mux_scl_t_s; + wire [ 1:0] iic_mux_sda_i_s; + wire [ 1:0] iic_mux_sda_o_s; + wire iic_mux_sda_t_s; + + // use crystal + + assign mclk = 1'b0; + assign up_sshot = gpio_o[36]; + assign up_format = gpio_o[35:34]; + assign up_crc_enable = gpio_o[33]; + assign up_crc_4_or_16_n = gpio_o[32]; + + // instantiations + + ad_iobuf #(.DATA_WIDTH(9)) i_iobuf ( + .dio_t ({gpio_t[52:48], gpio_t[43:40]}), + .dio_i ({gpio_o[52:48], gpio_o[43:40]}), + .dio_o ({gpio_i[52:48], gpio_i[43:40]}), + .dio_p ({ gpio_4_filter, // 52 + gpio_3_mode_3, // 51 + gpio_2_mode_2, // 50 + gpio_1_mode_1, // 49 + gpio_0_mode_0, // 48 + sync_in_n, // 43 + sync_n, // 42 + start_n, // 41 + reset_n})); // 40 + + ad_iobuf #(.DATA_WIDTH(32)) i_iobuf_bd ( + .dio_t (gpio_t[31:0]), + .dio_i (gpio_o[31:0]), + .dio_o (gpio_i[31:0]), + .dio_p (gpio_bd)); + + ad_iobuf #(.DATA_WIDTH(2)) i_iic_mux_scl ( + .dio_t ({iic_mux_scl_t_s, iic_mux_scl_t_s}), + .dio_i (iic_mux_scl_o_s), + .dio_o (iic_mux_scl_i_s), + .dio_p (iic_mux_scl)); + + ad_iobuf #(.DATA_WIDTH(2)) i_iic_mux_sda ( + .dio_t ({iic_mux_sda_t_s, iic_mux_sda_t_s}), + .dio_i (iic_mux_sda_o_s), + .dio_o (iic_mux_sda_i_s), + .dio_p (iic_mux_sda)); + + ad7768_if i_ad7768_if ( + .clk_in (clk_in), + .ready_in (ready_in), + .data_in (data_in), + .adc_clk (adc_clk), + .adc_valid (adc_valid), + .adc_data (adc_data), + .up_sshot (up_sshot), + .up_format (up_format), + .up_crc_enable (up_crc_enable), + .up_crc_4_or_16_n (up_crc_4_or_16_n), + .up_status_clr (adc_gpio_o[32:0]), + .up_status (adc_gpio_i[32:0])); + + system_wrapper i_system_wrapper ( + .adc_clk (adc_clk), + .adc_data (adc_data), + .adc_gpio_0_i (adc_gpio_i[31:0]), + .adc_gpio_0_o (adc_gpio_o[31:0]), + .adc_gpio_0_t (adc_gpio_t[31:0]), + .adc_gpio_1_i (adc_gpio_i[63:32]), + .adc_gpio_1_o (adc_gpio_o[63:32]), + .adc_gpio_1_t (adc_gpio_t[63:32]), + .adc_valid (adc_valid), + .ddr_addr (ddr_addr), + .ddr_ba (ddr_ba), + .ddr_cas_n (ddr_cas_n), + .ddr_ck_n (ddr_ck_n), + .ddr_ck_p (ddr_ck_p), + .ddr_cke (ddr_cke), + .ddr_cs_n (ddr_cs_n), + .ddr_dm (ddr_dm), + .ddr_dq (ddr_dq), + .ddr_dqs_n (ddr_dqs_n), + .ddr_dqs_p (ddr_dqs_p), + .ddr_odt (ddr_odt), + .ddr_ras_n (ddr_ras_n), + .ddr_reset_n (ddr_reset_n), + .ddr_we_n (ddr_we_n), + .fixed_io_ddr_vrn (fixed_io_ddr_vrn), + .fixed_io_ddr_vrp (fixed_io_ddr_vrp), + .fixed_io_mio (fixed_io_mio), + .fixed_io_ps_clk (fixed_io_ps_clk), + .fixed_io_ps_porb (fixed_io_ps_porb), + .fixed_io_ps_srstb (fixed_io_ps_srstb), + .gpio_i (gpio_i), + .gpio_o (gpio_o), + .gpio_t (gpio_t), + .hdmi_data (hdmi_data), + .hdmi_data_e (hdmi_data_e), + .hdmi_hsync (hdmi_hsync), + .hdmi_out_clk (hdmi_out_clk), + .hdmi_vsync (hdmi_vsync), + .i2s_bclk (i2s_bclk), + .i2s_lrclk (i2s_lrclk), + .i2s_mclk (i2s_mclk), + .i2s_sdata_in (i2s_sdata_in), + .i2s_sdata_out (i2s_sdata_out), + .iic_fmc_scl_io (iic_scl), + .iic_fmc_sda_io (iic_sda), + .iic_mux_scl_i (iic_mux_scl_i_s), + .iic_mux_scl_o (iic_mux_scl_o_s), + .iic_mux_scl_t (iic_mux_scl_t_s), + .iic_mux_sda_i (iic_mux_sda_i_s), + .iic_mux_sda_o (iic_mux_sda_o_s), + .iic_mux_sda_t (iic_mux_sda_t_s), + .otg_vbusoc (otg_vbusoc), + .ps_intr_00 (1'b0), + .ps_intr_01 (1'b0), + .ps_intr_02 (1'b0), + .ps_intr_03 (1'b0), + .ps_intr_04 (1'b0), + .ps_intr_05 (1'b0), + .ps_intr_06 (1'b0), + .ps_intr_07 (1'b0), + .ps_intr_08 (1'b0), + .ps_intr_09 (1'b0), + .ps_intr_10 (1'b0), + .spdif (spdif), + .spi0_clk_i (1'b0), + .spi0_clk_o (spi_clk), + .spi0_csn_0_o (spi_csn), + .spi0_csn_1_o (), + .spi0_csn_2_o (), + .spi0_csn_i (1'b1), + .spi0_sdi_i (spi_miso), + .spi0_sdo_i (1'b0), + .spi0_sdo_o (spi_mosi), + .spi1_clk_i (1'b0), + .spi1_clk_o (), + .spi1_csn_0_o (), + .spi1_csn_1_o (), + .spi1_csn_2_o (), + .spi1_csn_i (1'b1), + .spi1_sdi_i (1'b0), + .spi1_sdo_i (1'b0), + .spi1_sdo_o ()); + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/projects/ad9265_fmc/zc706/Makefile b/projects/ad9265_fmc/zc706/Makefile index 9ad95e317..e51b8b86c 100644 --- a/projects/ad9265_fmc/zc706/Makefile +++ b/projects/ad9265_fmc/zc706/Makefile @@ -16,7 +16,7 @@ M_DEPS += ../../scripts/adi_env.tcl M_DEPS += ../../scripts/adi_board.tcl M_DEPS += ../../common/zc706/zc706_system_constr.xdc M_DEPS += ../../common/zc706/zc706_system_bd.tcl -M_DEPS += ../../../library/common/ad_iobuf.v +M_DEPS += ../../../library/xilinx/common/ad_iobuf.v M_DEPS += ../../../library/axi_ad9265/axi_ad9265.xpr M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr @@ -37,6 +37,7 @@ M_FLIST += *.sdk M_FLIST += *.hw M_FLIST += *.sim M_FLIST += .Xil +M_FLIST += *.ip_user_files @@ -57,7 +58,7 @@ clean-all:clean ad9265_fmc_zc706.sdk/system_top.hdf: $(M_DEPS) - rm -rf $(M_FLIST) + -rm -rf $(M_FLIST) $(M_VIVADO) system_project.tcl >> ad9265_fmc_zc706_vivado.log 2>&1 diff --git a/projects/ad9265_fmc/zc706/system_project.tcl b/projects/ad9265_fmc/zc706/system_project.tcl index 17e5cab4e..92bce7ecf 100644 --- a/projects/ad9265_fmc/zc706/system_project.tcl +++ b/projects/ad9265_fmc/zc706/system_project.tcl @@ -8,7 +8,7 @@ adi_project_files ad9265_fmc_zc706 [list \ "../common/ad9265_spi.v" \ "system_top.v" \ "system_constr.xdc" \ - "$ad_hdl_dir/library/common/ad_iobuf.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \ "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc"] adi_project_run ad9265_fmc_zc706 diff --git a/projects/ad9434_fmc/common/ad9434_bd.tcl b/projects/ad9434_fmc/common/ad9434_bd.tcl index 8529e8f24..a15381c2a 100644 --- a/projects/ad9434_fmc/common/ad9434_bd.tcl +++ b/projects/ad9434_fmc/common/ad9434_bd.tcl @@ -23,10 +23,6 @@ set_property -dict [list CONFIG.AXI_SLICE_DEST {0}] $axi_ad9434_dma set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9434_dma set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {64}] $axi_ad9434_dma -# additions to default configuration - -set_property -dict [list CONFIG.PCW_USE_S_AXI_HP1 {1}] $sys_ps7 - # ad9434 connections ad_connect sys_200m_clk axi_ad9434/delay_clk diff --git a/projects/ad9434_fmc/zc706/Makefile b/projects/ad9434_fmc/zc706/Makefile index 70d247f5c..e47d747f9 100644 --- a/projects/ad9434_fmc/zc706/Makefile +++ b/projects/ad9434_fmc/zc706/Makefile @@ -16,7 +16,7 @@ M_DEPS += ../../scripts/adi_env.tcl M_DEPS += ../../scripts/adi_board.tcl M_DEPS += ../../common/zc706/zc706_system_constr.xdc M_DEPS += ../../common/zc706/zc706_system_bd.tcl -M_DEPS += ../../../library/common/ad_iobuf.v +M_DEPS += ../../../library/xilinx/common/ad_iobuf.v M_DEPS += ../../../library/axi_ad9434/axi_ad9434.xpr M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr @@ -37,6 +37,7 @@ M_FLIST += *.sdk M_FLIST += *.hw M_FLIST += *.sim M_FLIST += .Xil +M_FLIST += *.ip_user_files @@ -57,7 +58,7 @@ clean-all:clean ad9434_fmc_zc706.sdk/system_top.hdf: $(M_DEPS) - rm -rf $(M_FLIST) + -rm -rf $(M_FLIST) $(M_VIVADO) system_project.tcl >> ad9434_fmc_zc706_vivado.log 2>&1 diff --git a/projects/ad9434_fmc/zc706/system_project.tcl b/projects/ad9434_fmc/zc706/system_project.tcl index 090308c24..8014a0f5e 100644 --- a/projects/ad9434_fmc/zc706/system_project.tcl +++ b/projects/ad9434_fmc/zc706/system_project.tcl @@ -8,7 +8,7 @@ adi_project_files ad9434_fmc_zc706 [list \ "../common/ad9434_spi.v" \ "system_top.v" \ "system_constr.xdc" \ - "$ad_hdl_dir/library/common/ad_iobuf.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \ "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc"] adi_project_run ad9434_fmc_zc706 diff --git a/projects/ad9467_fmc/kc705/Makefile b/projects/ad9467_fmc/kc705/Makefile index 887838189..1287d339f 100644 --- a/projects/ad9467_fmc/kc705/Makefile +++ b/projects/ad9467_fmc/kc705/Makefile @@ -17,7 +17,7 @@ M_DEPS += ../../scripts/adi_board.tcl M_DEPS += ../../common/kc705/kc705_system_mig.prj M_DEPS += ../../common/kc705/kc705_system_constr.xdc M_DEPS += ../../common/kc705/kc705_system_bd.tcl -M_DEPS += ../../../library/common/ad_iobuf.v +M_DEPS += ../../../library/xilinx/common/ad_iobuf.v M_DEPS += ../../../library/axi_ad9467/axi_ad9467.xpr M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr @@ -35,6 +35,7 @@ M_FLIST += *.sdk M_FLIST += *.hw M_FLIST += *.sim M_FLIST += .Xil +M_FLIST += *.ip_user_files @@ -52,7 +53,7 @@ clean-all:clean ad9467_fmc_kc705.sdk/system_top.hdf: $(M_DEPS) - rm -rf $(M_FLIST) + -rm -rf $(M_FLIST) $(M_VIVADO) system_project.tcl >> ad9467_fmc_kc705_vivado.log 2>&1 diff --git a/projects/ad9467_fmc/kc705/system_constr.xdc b/projects/ad9467_fmc/kc705/system_constr.xdc index 8406a49fe..dcdcd551a 100644 --- a/projects/ad9467_fmc/kc705/system_constr.xdc +++ b/projects/ad9467_fmc/kc705/system_constr.xdc @@ -32,6 +32,3 @@ set_property -dict {PACKAGE_PIN Y30 IOSTANDARD LVCMOS25} [get_ports spi_sdio # clocks create_clock -name adc_clk -period 4.00 [get_ports adc_clk_in_p] -set_clock_groups -asynchronous -group {adc_clk} - - diff --git a/projects/ad9467_fmc/kc705/system_project.tcl b/projects/ad9467_fmc/kc705/system_project.tcl index 8e0368385..23c50fa2c 100644 --- a/projects/ad9467_fmc/kc705/system_project.tcl +++ b/projects/ad9467_fmc/kc705/system_project.tcl @@ -6,7 +6,7 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl adi_project_create ad9467_fmc_kc705 adi_project_files ad9467_fmc_kc705 [list \ "../common/ad9467_spi.v" \ - "$ad_hdl_dir/library/common/ad_iobuf.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \ "system_top.v" \ "system_constr.xdc" \ "$ad_hdl_dir/projects/common/kc705/kc705_system_constr.xdc"] diff --git a/projects/ad9467_fmc/kc705/system_top.v b/projects/ad9467_fmc/kc705/system_top.v index 85e60b69b..a44c82b11 100644 --- a/projects/ad9467_fmc/kc705/system_top.v +++ b/projects/ad9467_fmc/kc705/system_top.v @@ -95,14 +95,6 @@ module system_top ( iic_scl, iic_sda, - hdmi_out_clk, - hdmi_hsync, - hdmi_vsync, - hdmi_data_e, - hdmi_data, - - spdif, - adc_clk_in_n, adc_clk_in_p, adc_data_in_n, @@ -169,14 +161,6 @@ module system_top ( inout iic_scl; inout iic_sda; - output hdmi_out_clk; - output hdmi_hsync; - output hdmi_vsync; - output hdmi_data_e; - output [15:0] hdmi_data; - - output spdif; - input adc_clk_in_n; input adc_clk_in_p; input [ 7:0] adc_data_in_n; @@ -189,7 +173,7 @@ module system_top ( inout spi_sdio; // internal signals - wire [ 1:0] spi_csn; + wire [ 7:0] spi_csn; wire spi_miso; wire spi_mosi; @@ -206,7 +190,7 @@ module system_top ( assign spi_csn_clk = spi_csn[1]; ad9467_spi i_spi ( - .spi_csn(spi_csn), + .spi_csn(spi_csn[1:0]), .spi_clk(spi_clk), .spi_mosi(spi_mosi), .spi_miso(spi_miso), @@ -275,19 +259,19 @@ module system_top ( .sys_rst (sys_rst), .uart_sin (uart_sin), .uart_sout (uart_sout), - .adc_clk_in_n(adc_clk_in_n), - .adc_clk_in_p(adc_clk_in_p), - .adc_data_in_n(adc_data_in_n), - .adc_data_in_p(adc_data_in_p), - .adc_data_or_n(adc_data_or_n), - .adc_data_or_p(adc_data_or_p), - .spi_clk_i(1'b0), - .spi_clk_o(spi_clk), - .spi_csn_i(1'b1), - .spi_csn_o(spi_csn), - .spi_sdi_i(spi_miso), - .spi_sdo_i(1'b0), - .spi_sdo_o(spi_mosi)); + .adc_clk_in_n (adc_clk_in_n), + .adc_clk_in_p (adc_clk_in_p), + .adc_data_in_n (adc_data_in_n), + .adc_data_in_p (adc_data_in_p), + .adc_data_or_n (adc_data_or_n), + .adc_data_or_p (adc_data_or_p), + .spi_clk_i (1'b0), + .spi_clk_o (spi_clk), + .spi_csn_i (1'b1), + .spi_csn_o (spi_csn), + .spi_sdi_i (spi_miso), + .spi_sdo_i (1'b0), + .spi_sdo_o (spi_mosi)); endmodule diff --git a/projects/ad9467_fmc/zed/Makefile b/projects/ad9467_fmc/zed/Makefile index 0eee2b11c..e986af978 100644 --- a/projects/ad9467_fmc/zed/Makefile +++ b/projects/ad9467_fmc/zed/Makefile @@ -16,7 +16,7 @@ M_DEPS += ../../scripts/adi_env.tcl M_DEPS += ../../scripts/adi_board.tcl M_DEPS += ../../common/zed/zed_system_constr.xdc M_DEPS += ../../common/zed/zed_system_bd.tcl -M_DEPS += ../../../library/common/ad_iobuf.v +M_DEPS += ../../../library/xilinx/common/ad_iobuf.v M_DEPS += ../../../library/axi_ad9467/axi_ad9467.xpr M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr @@ -39,6 +39,7 @@ M_FLIST += *.sdk M_FLIST += *.hw M_FLIST += *.sim M_FLIST += .Xil +M_FLIST += *.ip_user_files @@ -61,7 +62,7 @@ clean-all:clean ad9467_fmc_zed.sdk/system_top.hdf: $(M_DEPS) - rm -rf $(M_FLIST) + -rm -rf $(M_FLIST) $(M_VIVADO) system_project.tcl >> ad9467_fmc_zed_vivado.log 2>&1 diff --git a/projects/ad9467_fmc/zed/system_constr.xdc b/projects/ad9467_fmc/zed/system_constr.xdc index 444a99fed..8b1d5c7d3 100644 --- a/projects/ad9467_fmc/zed/system_constr.xdc +++ b/projects/ad9467_fmc/zed/system_constr.xdc @@ -32,6 +32,3 @@ set_property -dict {PACKAGE_PIN A21 IOSTANDARD LVCMOS25} [get_ports spi_sdio # clocks create_clock -name adc_clk -period 4.00 [get_ports adc_clk_in_p] -set_clock_groups -asynchronous -group {adc_clk} - - diff --git a/projects/ad9467_fmc/zed/system_project.tcl b/projects/ad9467_fmc/zed/system_project.tcl index 6e503e355..dfd7ca2ee 100644 --- a/projects/ad9467_fmc/zed/system_project.tcl +++ b/projects/ad9467_fmc/zed/system_project.tcl @@ -6,7 +6,7 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl adi_project_create ad9467_fmc_zed adi_project_files ad9467_fmc_zed [list \ "../common/ad9467_spi.v" \ - "$ad_hdl_dir/library/common/ad_iobuf.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \ "system_top.v" \ "system_constr.xdc" \ "$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc"] diff --git a/projects/ad9739a_fmc/zc706/Makefile b/projects/ad9739a_fmc/zc706/Makefile index 481327975..c7ff8e8ac 100644 --- a/projects/ad9739a_fmc/zc706/Makefile +++ b/projects/ad9739a_fmc/zc706/Makefile @@ -15,7 +15,7 @@ M_DEPS += ../../scripts/adi_env.tcl M_DEPS += ../../scripts/adi_board.tcl M_DEPS += ../../common/zc706/zc706_system_constr.xdc M_DEPS += ../../common/zc706/zc706_system_bd.tcl -M_DEPS += ../../../library/common/ad_iobuf.v +M_DEPS += ../../../library/xilinx/common/ad_iobuf.v M_DEPS += ../../../library/axi_ad9739a/axi_ad9739a.xpr M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr @@ -36,6 +36,7 @@ M_FLIST += *.sdk M_FLIST += *.hw M_FLIST += *.sim M_FLIST += .Xil +M_FLIST += *.ip_user_files @@ -56,7 +57,7 @@ clean-all:clean ad9739a_fmc_zc706.sdk/system_top.hdf: $(M_DEPS) - rm -rf $(M_FLIST) + -rm -rf $(M_FLIST) $(M_VIVADO) system_project.tcl >> ad9739a_fmc_zc706_vivado.log 2>&1 diff --git a/projects/ad9739a_fmc/zc706/system_project.tcl b/projects/ad9739a_fmc/zc706/system_project.tcl index f42d59f2c..4a681d17e 100644 --- a/projects/ad9739a_fmc/zc706/system_project.tcl +++ b/projects/ad9739a_fmc/zc706/system_project.tcl @@ -9,7 +9,7 @@ adi_project_create ad9739a_fmc_zc706 adi_project_files ad9739a_fmc_zc706 [list \ "system_top.v" \ "system_constr.xdc"\ - "$ad_hdl_dir/library/common/ad_iobuf.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \ "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ] set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc] diff --git a/projects/fmcomms1/Makefile b/projects/adrv9371x/Makefile similarity index 68% rename from projects/fmcomms1/Makefile rename to projects/adrv9371x/Makefile index 82b83fb73..4947b6146 100644 --- a/projects/fmcomms1/Makefile +++ b/projects/adrv9371x/Makefile @@ -7,30 +7,21 @@ .PHONY: all clean clean-all all: - -make -C ac701 all - -make -C kc705 all - -make -C vc707 all - -make -C zc702 all + -make -C a10gx all + -make -C a10soc all -make -C zc706 all - -make -C zed all clean: - make -C ac701 clean - make -C kc705 clean - make -C vc707 clean - make -C zc702 clean + make -C a10gx clean + make -C a10soc clean make -C zc706 clean - make -C zed clean clean-all: - make -C ac701 clean-all - make -C kc705 clean-all - make -C vc707 clean-all - make -C zc702 clean-all + make -C a10gx clean-all + make -C a10soc clean-all make -C zc706 clean-all - make -C zed clean-all #################################################################################### #################################################################################### diff --git a/projects/adrv9371x/a10gx/Makefile b/projects/adrv9371x/a10gx/Makefile new file mode 100644 index 000000000..9ea98e593 --- /dev/null +++ b/projects/adrv9371x/a10gx/Makefile @@ -0,0 +1,152 @@ +#################################################################################### +#################################################################################### +## Copyright 2011(c) Analog Devices, Inc. +## Auto-generated, do not modify! +#################################################################################### +#################################################################################### + +ifeq ($(MMU),) + MMU := 1 +endif + +export ALT_NIOS_MMU_ENABLED := $(MMU) + +M_DEPS += system_top.v +M_DEPS += system_qsys.tcl +M_DEPS += system_project.tcl +M_DEPS += system_constr.sdc +M_DEPS += ../common/adrv9371x_qsys.tcl +M_DEPS += ../../scripts/adi_tquest.tcl +M_DEPS += ../../scripts/adi_env.tcl +M_DEPS += ../../common/altera/sys_gen.tcl +M_DEPS += ../../common/a10gx/a10gx_system_qsys.tcl +M_DEPS += ../../common/a10gx/a10gx_system_assign.tcl +M_DEPS += ../../../library/altera/avl_adxcfg/avl_adxcfg.v +M_DEPS += ../../../library/altera/avl_adxcfg/avl_adxcfg_hw.tcl +M_DEPS += ../../../library/altera/avl_adxcvr/avl_adxcvr_hw.tcl +M_DEPS += ../../../library/altera/axi_adxcvr/axi_adxcvr.v +M_DEPS += ../../../library/altera/axi_adxcvr/axi_adxcvr_hw.tcl +M_DEPS += ../../../library/altera/axi_adxcvr/axi_adxcvr_up.v +M_DEPS += ../../../library/altera/common/ad_dcfilter.v +M_DEPS += ../../../library/altera/common/ad_mul.v +M_DEPS += ../../../library/axi_ad9371/axi_ad9371.v +M_DEPS += ../../../library/axi_ad9371/axi_ad9371_hw.tcl +M_DEPS += ../../../library/axi_ad9371/axi_ad9371_if.v +M_DEPS += ../../../library/axi_ad9371/axi_ad9371_rx.v +M_DEPS += ../../../library/axi_ad9371/axi_ad9371_rx_channel.v +M_DEPS += ../../../library/axi_ad9371/axi_ad9371_rx_os.v +M_DEPS += ../../../library/axi_ad9371/axi_ad9371_tx.v +M_DEPS += ../../../library/axi_ad9371/axi_ad9371_tx_channel.v +M_DEPS += ../../../library/axi_dmac/2d_transfer.v +M_DEPS += ../../../library/axi_dmac/address_generator.v +M_DEPS += ../../../library/axi_dmac/axi_dmac.v +M_DEPS += ../../../library/axi_dmac/axi_dmac_constr.sdc +M_DEPS += ../../../library/axi_dmac/axi_dmac_hw.tcl +M_DEPS += ../../../library/axi_dmac/axi_register_slice.v +M_DEPS += ../../../library/axi_dmac/data_mover.v +M_DEPS += ../../../library/axi_dmac/dest_axi_mm.v +M_DEPS += ../../../library/axi_dmac/dest_axi_stream.v +M_DEPS += ../../../library/axi_dmac/dest_fifo_inf.v +M_DEPS += ../../../library/axi_dmac/inc_id.h +M_DEPS += ../../../library/axi_dmac/request_arb.v +M_DEPS += ../../../library/axi_dmac/request_generator.v +M_DEPS += ../../../library/axi_dmac/resp.h +M_DEPS += ../../../library/axi_dmac/response_generator.v +M_DEPS += ../../../library/axi_dmac/response_handler.v +M_DEPS += ../../../library/axi_dmac/splitter.v +M_DEPS += ../../../library/axi_dmac/src_axi_mm.v +M_DEPS += ../../../library/axi_dmac/src_axi_stream.v +M_DEPS += ../../../library/axi_dmac/src_fifo_inf.v +M_DEPS += ../../../library/common/ad_axi_ip_constr.sdc +M_DEPS += ../../../library/common/ad_axis_inf_rx.v +M_DEPS += ../../../library/common/ad_datafmt.v +M_DEPS += ../../../library/common/ad_dds.v +M_DEPS += ../../../library/common/ad_dds_1.v +M_DEPS += ../../../library/common/ad_dds_sine.v +M_DEPS += ../../../library/common/ad_iqcor.v +M_DEPS += ../../../library/common/ad_mem_asym.v +M_DEPS += ../../../library/common/ad_rst.v +M_DEPS += ../../../library/common/ad_xcvr_rx_if.v +M_DEPS += ../../../library/common/sync_bits.v +M_DEPS += ../../../library/common/sync_gray.v +M_DEPS += ../../../library/common/up_adc_channel.v +M_DEPS += ../../../library/common/up_adc_common.v +M_DEPS += ../../../library/common/up_axi.v +M_DEPS += ../../../library/common/up_clock_mon.v +M_DEPS += ../../../library/common/up_dac_channel.v +M_DEPS += ../../../library/common/up_dac_common.v +M_DEPS += ../../../library/common/up_xfer_cntrl.v +M_DEPS += ../../../library/common/up_xfer_status.v +M_DEPS += ../../../library/scripts/adi_env.tcl +M_DEPS += ../../../library/scripts/adi_ip_alt.tcl +M_DEPS += ../../../library/util_adcfifo/util_adcfifo.v +M_DEPS += ../../../library/util_adcfifo/util_adcfifo_constr.sdc +M_DEPS += ../../../library/util_adcfifo/util_adcfifo_hw.tcl +M_DEPS += ../../../library/util_axis_fifo/address_gray.v +M_DEPS += ../../../library/util_axis_fifo/address_gray_pipelined.v +M_DEPS += ../../../library/util_axis_fifo/address_sync.v +M_DEPS += ../../../library/util_axis_fifo/util_axis_fifo.v +M_DEPS += ../../../library/util_axis_resize/util_axis_resize.v +M_DEPS += ../../../library/util_cpack/util_cpack.v +M_DEPS += ../../../library/util_cpack/util_cpack_dsf.v +M_DEPS += ../../../library/util_cpack/util_cpack_hw.tcl +M_DEPS += ../../../library/util_cpack/util_cpack_mux.v +M_DEPS += ../../../library/util_upack/util_upack.v +M_DEPS += ../../../library/util_upack/util_upack_dmx.v +M_DEPS += ../../../library/util_upack/util_upack_dsf.v +M_DEPS += ../../../library/util_upack/util_upack_hw.tcl + + +M_ALTERA := quartus_sh --64bit -t + + +M_FLIST += *.log +M_FLIST += *_INFO.txt +M_FLIST += *_dump.txt +M_FLIST += db +M_FLIST += *.asm.rpt +M_FLIST += *.done +M_FLIST += *.eda.rpt +M_FLIST += *.fit.* +M_FLIST += *.map.* +M_FLIST += *.sta.* +M_FLIST += *.qsf +M_FLIST += *.qpf +M_FLIST += *.qws +M_FLIST += *.sof +M_FLIST += *.cdf +M_FLIST += *.sld +M_FLIST += *.qdf +M_FLIST += hc_output +M_FLIST += system_bd +M_FLIST += hps_isw_handoff +M_FLIST += hps_sdram_*.csv +M_FLIST += *ddr3_*.csv +M_FLIST += incremental_db +M_FLIST += reconfig_mif +M_FLIST += *.sopcinfo +M_FLIST += *.jdi +M_FLIST += *.pin +M_FLIST += *_summary.csv +M_FLIST += *.dpf + + + +.PHONY: all clean clean-all +all: adrv9371x_a10gx.sof + + + +clean:clean-all + + +clean-all: + rm -rf $(M_FLIST) + + +adrv9371x_a10gx.sof: $(M_DEPS) + -rm -rf $(M_FLIST) + $(M_ALTERA) system_project.tcl >> adrv9371x_a10gx_quartus.log 2>&1 + +#################################################################################### +#################################################################################### diff --git a/projects/adrv9371x/a10gx/system_constr.sdc b/projects/adrv9371x/a10gx/system_constr.sdc new file mode 100644 index 000000000..029e779b7 --- /dev/null +++ b/projects/adrv9371x/a10gx/system_constr.sdc @@ -0,0 +1,40 @@ + +create_clock -period "10.000 ns" -name sys_clk_100mhz [get_ports {sys_clk}] +create_clock -period "8.139 ns" -name ref_clk0_122mhz [get_ports {ref_clk0}] +create_clock -period "8.139 ns" -name ref_clk1_122mhz [get_ports {ref_clk1}] + +derive_pll_clocks +derive_clock_uncertainty + +set_false_path -from [get_clocks {sys_clk_100mhz}]\ + -through [get_nets *altera_jesd204_tx_csr_inst*]\ + -to [get_clocks {i_system_bd|avl_ad9371_tx_xcvr|alt_core_pll|outclk0}] + +set_false_path -from [get_clocks {sys_clk_100mhz}]\ + -through [get_nets *altera_jesd204_tx_ctl_inst*]\ + -to [get_clocks {i_system_bd|avl_ad9371_tx_xcvr|alt_core_pll|outclk0}] + +set_false_path -from [get_clocks {sys_clk_100mhz}]\ + -through [get_nets *altera_jesd204_rx_csr_inst*]\ + -to [get_clocks {i_system_bd|avl_ad9371_rx_xcvr|alt_core_pll|outclk0}] + +set_false_path -from [get_clocks {sys_clk_100mhz}]\ + -through [get_nets *altera_jesd204_rx_csr_inst*]\ + -to [get_clocks {i_system_bd|avl_ad9371_rx_os_xcvr|alt_core_pll|outclk0}] + +set_false_path -from [get_clocks {i_system_bd|avl_ad9371_tx_xcvr|alt_core_pll|outclk0}]\ + -through [get_nets *altera_jesd204_tx_csr_inst*]\ + -to [get_clocks {sys_clk_100mhz}] + +set_false_path -from [get_clocks {i_system_bd|avl_ad9371_tx_xcvr|alt_core_pll|outclk0}]\ + -through [get_nets *altera_jesd204_tx_ctl_inst*]\ + -to [get_clocks {sys_clk_100mhz}] + +set_false_path -from [get_clocks {i_system_bd|avl_ad9371_rx_xcvr|alt_core_pll|outclk0}]\ + -through [get_nets *altera_jesd204_rx_csr_inst*]\ + -to [get_clocks {sys_clk_100mhz}] + +set_false_path -from [get_clocks {i_system_bd|avl_ad9371_rx_os_xcvr|alt_core_pll|outclk0}]\ + -through [get_nets *altera_jesd204_rx_csr_inst*]\ + -to [get_clocks {sys_clk_100mhz}] + diff --git a/projects/adrv9371x/a10gx/system_project.tcl b/projects/adrv9371x/a10gx/system_project.tcl new file mode 100644 index 000000000..884886fbd --- /dev/null +++ b/projects/adrv9371x/a10gx/system_project.tcl @@ -0,0 +1,152 @@ + +load_package flow + +source ../../scripts/adi_env.tcl +project_new adrv9371x_a10gx -overwrite + +source "../../common/a10gx/a10gx_system_assign.tcl" + +set_global_assignment -name VERILOG_FILE system_top.v +set_global_assignment -name QSYS_FILE system_bd.qsys + +set_global_assignment -name SDC_FILE system_constr.sdc +set_global_assignment -name TOP_LEVEL_ENTITY system_top + +# lane interface + +set_location_assignment PIN_AL8 -to ref_clk0 ; ## D04 FMCA_GBTCLK0_M2C_P +set_location_assignment PIN_AL7 -to "ref_clk0(n)" ; ## D05 FMCA_GBTCLK0_M2C_N +set_location_assignment PIN_AJ8 -to ref_clk1 ; ## B20 FMCA_GBTCLK1_M2C_P +set_location_assignment PIN_AJ7 -to "ref_clk1(n)" ; ## B21 FMCA_GBTCLK1_M2C_N +set_location_assignment PIN_BA7 -to rx_data[0] ; ## A02 FMCA_DP1_M2C_P +set_location_assignment PIN_BA8 -to "rx_data[0](n)" ; ## A03 FMCA_DP1_M2C_N +set_location_assignment PIN_AY5 -to rx_data[1] ; ## A06 FMCA_DP2_M2C_P +set_location_assignment PIN_AY6 -to "rx_data[1](n)" ; ## A07 FMCA_DP2_M2C_N +set_location_assignment PIN_AW7 -to rx_data[2] ; ## C06 FMCA_DP0_M2C_P +set_location_assignment PIN_AW8 -to "rx_data[2](n)" ; ## C07 FMCA_DP0_M2C_N +set_location_assignment PIN_AV5 -to rx_data[3] ; ## A10 FMCA_DP3_M2C_P +set_location_assignment PIN_AV6 -to "rx_data[3](n)" ; ## A11 FMCA_DP3_M2C_N +set_location_assignment PIN_BD5 -to tx_data[0] ; ## A22 FMCA_DP1_C2M_P (tx_data_p[0]) +set_location_assignment PIN_BD6 -to "tx_data[0](n)" ; ## A23 FMCA_DP1_C2M_N (tx_data_n[0]) +set_location_assignment PIN_BB5 -to tx_data[1] ; ## A26 FMCA_DP2_C2M_P (tx_data_p[1]) +set_location_assignment PIN_BB6 -to "tx_data[1](n)" ; ## A27 FMCA_DP2_C2M_N (tx_data_n[1]) +set_location_assignment PIN_BC7 -to tx_data[2] ; ## C02 FMCA_DP0_C2M_P (tx_data_p[2]) +set_location_assignment PIN_BC8 -to "tx_data[2](n)" ; ## C03 FMCA_DP0_C2M_N (tx_data_n[2]) +set_location_assignment PIN_BC3 -to tx_data[3] ; ## A30 FMCA_DP3_C2M_P (tx_data_p[3]) +set_location_assignment PIN_BC4 -to "tx_data[3](n)" ; ## A31 FMCA_DP3_C2M_N (tx_data_n[3]) + + +set_instance_assignment -name IO_STANDARD LVDS -to ref_clk0 +set_instance_assignment -name IO_STANDARD LVDS -to ref_clk1 +set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to rx_data[0] +set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to rx_data[1] +set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to rx_data[2] +set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to rx_data[3] +set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to tx_data[0] +set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to tx_data[1] +set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to tx_data[2] +set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to tx_data[3] + +set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_0 -to rx_data[0] +set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_1 -to rx_data[1] +set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_2 -to rx_data[2] +set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_3 -to rx_data[3] + +set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_0 -to tx_data[0] +set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_1 -to tx_data[1] +set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_2 -to tx_data[2] +set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_3 -to tx_data[3] + + +set_location_assignment PIN_AR20 -to rx_sync ; ## G09 FMCA_HPC_LA03_P +set_location_assignment PIN_AR19 -to rx_sync(n) ; ## G10 FMCA_HPC_LA03_N +set_location_assignment PIN_AY15 -to rx_os_sync ; ## G27 FMCA_HPC_LA25_P (Sniffer) +set_location_assignment PIN_AY14 -to rx_os_sync(n) ; ## G28 FMCA_HPC_LA25_N (Sniffer) +set_location_assignment PIN_AR22 -to tx_sync ; ## H07 FMCA_HPC_LA02_P +set_location_assignment PIN_AT22 -to tx_sync(n) ; ## H08 FMCA_HPC_LA02_N +set_location_assignment PIN_AY17 -to sysref ; ## G36 FMCA_HPC_LA33_P +set_location_assignment PIN_AW17 -to sysref(n) ; ## G37 FMCA_HPC_LA33_N + +set_instance_assignment -name IO_STANDARD LVDS -to rx_sync +set_instance_assignment -name IO_STANDARD LVDS -to rx_os_sync +set_instance_assignment -name IO_STANDARD LVDS -to tx_sync +set_instance_assignment -name IO_STANDARD LVDS -to sysref +set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to tx_sync +set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to sysref + +set_location_assignment PIN_AW13 -to spi_csn_ad9371 ; ## D14 FMCA_HPC_LA09_P +set_location_assignment PIN_AV13 -to spi_csn_ad9528 ; ## D15 FMCA_HPC_LA09_N +set_location_assignment PIN_AT17 -to spi_clk ; ## H13 FMCA_HPC_LA07_P +set_location_assignment PIN_AU17 -to spi_mosi ; ## H14 FMCA_HPC_LA07_N +set_location_assignment PIN_AP18 -to spi_miso ; ## G12 FMCA_HPC_LA08_P + +set_instance_assignment -name IO_STANDARD "1.8 V" -to spi_csn_ad9528 +set_instance_assignment -name IO_STANDARD "1.8 V" -to spi_csn_ad9371 +set_instance_assignment -name IO_STANDARD "1.8 V" -to spi_clk +set_instance_assignment -name IO_STANDARD "1.8 V" -to spi_mosi +set_instance_assignment -name IO_STANDARD "1.8 V" -to spi_miso + +set_location_assignment PIN_AT19 -to ad9528_reset_b ; ## D26 FMCA_HPC_LA26_P +set_location_assignment PIN_AT20 -to ad9528_sysref_req ; ## D27 FMCA_HPC_LA26_N +set_location_assignment PIN_AR17 -to ad9371_tx1_enable ; ## D17 FMCA_HPC_LA13_P +set_location_assignment PIN_AW18 -to ad9371_tx2_enable ; ## C18 FMCA_HPC_LA14_P +set_location_assignment PIN_AP17 -to ad9371_rx1_enable ; ## D18 FMCA_HPC_LA13_N +set_location_assignment PIN_AV18 -to ad9371_rx2_enable ; ## C19 FMCA_HPC_LA14_N +set_location_assignment PIN_AV11 -to ad9371_test ; ## D11 FMCA_HPC_LA05_P (DNI/NC) +set_location_assignment PIN_AN20 -to ad9371_reset_b ; ## H10 FMCA_HPC_LA04_P +set_location_assignment PIN_AP19 -to ad9371_gpint ; ## H11 FMCA_HPC_LA04_N + +set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9528_reset_b +set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9528_sysref_req +set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_tx1_enable +set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_tx2_enable +set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_rx1_enable +set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_rx2_enable +set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_test +set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_reset_b +set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpint + +# single ended default + +set_location_assignment PIN_AR9 -to ad9371_gpio[0] ; ## H19 FMCA_HPC_LA15_P +set_location_assignment PIN_AT9 -to ad9371_gpio[1] ; ## H20 FMCA_HPC_LA15_N +set_location_assignment PIN_AT13 -to ad9371_gpio[2] ; ## G18 FMCA_HPC_LA16_P +set_location_assignment PIN_AU13 -to ad9371_gpio[3] ; ## G19 FMCA_HPC_LA16_N +set_location_assignment PIN_AY10 -to ad9371_gpio[4] ; ## H25 FMCA_HPC_LA21_P +set_location_assignment PIN_AY11 -to ad9371_gpio[5] ; ## H26 FMCA_HPC_LA21_N +set_location_assignment PIN_AU21 -to ad9371_gpio[6] ; ## C22 FMCA_HPC_LA18_CC_P +set_location_assignment PIN_AV21 -to ad9371_gpio[7] ; ## C23 FMCA_HPC_LA18_CC_N +set_location_assignment PIN_AY12 -to ad9371_gpio[8] ; ## G25 FMCA_HPC_LA22_N (LVDS_1N) +set_location_assignment PIN_AU11 -to ad9371_gpio[9] ; ## H22 FMCA_HPC_LA19_P (LVDS_2P) +set_location_assignment PIN_AU12 -to ad9371_gpio[10] ; ## H23 FMCA_HPC_LA19_N (LVDS_2N) +set_location_assignment PIN_AU8 -to ad9371_gpio[11] ; ## G21 FMCA_HPC_LA20_P (LVDS_3P) +set_location_assignment PIN_AT8 -to ad9371_gpio[12] ; ## G22 FMCA_HPC_LA20_N (LVDS_3N) +set_location_assignment PIN_BA14 -to ad9371_gpio[13] ; ## G31 FMCA_HPC_LA29_N (LVDS_4N) +set_location_assignment PIN_BA15 -to ad9371_gpio[14] ; ## G30 FMCA_HPC_LA29_P (LVDS_4P) +set_location_assignment PIN_AW12 -to ad9371_gpio[15] ; ## G24 FMCA_HPC_LA22_P (LVDS_1P) +set_location_assignment PIN_AP16 -to ad9371_gpio[16] ; ## G16 FMCA_HPC_LA12_N (LVDS_5N) +set_location_assignment PIN_AR16 -to ad9371_gpio[17] ; ## G15 FMCA_HPC_LA12_P (LVDS_5P) +set_location_assignment PIN_AW11 -to ad9371_gpio[18] ; ## D12 FMCA_HPC_LA05_N + +set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio[0] +set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio[1] +set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio[2] +set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio[3] +set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio[4] +set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio[5] +set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio[6] +set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio[7] +set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio[8] +set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio[9] +set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio[10] +set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio[11] +set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio[12] +set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio[13] +set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio[14] +set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio[15] +set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio[16] +set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio[17] +set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio[18] + +execute_flow -compile + diff --git a/projects/adrv9371x/a10gx/system_qsys.tcl b/projects/adrv9371x/a10gx/system_qsys.tcl new file mode 100644 index 000000000..7bf3e3032 --- /dev/null +++ b/projects/adrv9371x/a10gx/system_qsys.tcl @@ -0,0 +1,6 @@ + + +source $ad_hdl_dir/projects/common/a10gx/a10gx_system_qsys.tcl +source ../common/adrv9371x_qsys.tcl + + diff --git a/projects/adrv9371x/a10gx/system_top.v b/projects/adrv9371x/a10gx/system_top.v new file mode 100644 index 000000000..d795e8f6d --- /dev/null +++ b/projects/adrv9371x/a10gx/system_top.v @@ -0,0 +1,213 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top ( + + // clock and resets + + input sys_clk, + input sys_resetn, + + // ddr3 + + output ddr3_clk_p, + output ddr3_clk_n, + output [ 14:0] ddr3_a, + output [ 2:0] ddr3_ba, + output ddr3_cke, + output ddr3_cs_n, + output ddr3_odt, + output ddr3_reset_n, + output ddr3_we_n, + output ddr3_ras_n, + output ddr3_cas_n, + inout [ 7:0] ddr3_dqs_p, + inout [ 7:0] ddr3_dqs_n, + inout [ 63:0] ddr3_dq, + output [ 7:0] ddr3_dm, + input ddr3_rzq, + input ddr3_ref_clk, + + // ethernet + + input eth_ref_clk, + input eth_rxd, + output eth_txd, + output eth_mdc, + inout eth_mdio, + output eth_resetn, + input eth_intn, + + // board gpio + + input [ 10:0] gpio_bd_i, + output [ 15:0] gpio_bd_o, + + // lane interface + + input ref_clk0, + input ref_clk1, + input [ 3:0] rx_data, + output [ 3:0] tx_data, + output rx_sync, + output rx_os_sync, + input tx_sync, + input sysref, + + output ad9528_reset_b, + output ad9528_sysref_req, + output ad9371_tx1_enable, + output ad9371_tx2_enable, + output ad9371_rx1_enable, + output ad9371_rx2_enable, + output ad9371_test, + output ad9371_reset_b, + input ad9371_gpint, + + inout [ 18:0] ad9371_gpio, + + output spi_csn_ad9528, + output spi_csn_ad9371, + output spi_clk, + output spi_mosi, + input spi_miso); + + // internal signals + + wire eth_reset; + wire eth_mdio_i; + wire eth_mdio_o; + wire eth_mdio_t; + wire [ 63:0] gpio_i; + wire [ 63:0] gpio_o; + wire [ 7:0] spi_csn_s; + + // assignments + + assign spi_csn_ad9371 = spi_csn_s[0]; + assign spi_csn_ad9528 = spi_csn_s[1]; + + // gpio (ad9371) + + assign ad9371_tx1_enable = gpio_o[55]; + assign ad9371_tx2_enable = gpio_o[54]; + assign ad9371_rx1_enable = gpio_o[53]; + assign ad9371_rx2_enable = gpio_o[52]; + assign ad9371_test = gpio_o[51]; + assign ad9371_reset_b = gpio_o[50]; + assign ad9528_sysref_req = gpio_o[49]; + assign ad9528_reset_b = gpio_o[48]; + + assign gpio_i[63:57] = gpio_o[63:57]; + assign gpio_i[56:56] = ad9371_gpint; + assign gpio_i[55:32] = gpio_o[55:32]; + + // board stuff + + assign eth_resetn = ~eth_reset; + assign eth_mdio_i = eth_mdio; + assign eth_mdio = (eth_mdio_t == 1'b1) ? 1'bz : eth_mdio_o; + + assign ddr3_a[14:12] = 3'd0; + + assign gpio_i[31:27] = gpio_o[31:27]; + assign gpio_i[26:16] = gpio_bd_i; + assign gpio_i[15: 0] = gpio_o[15:0]; + + assign gpio_bd_o = gpio_o[15:0]; + + system_bd i_system_bd ( + .avl_ad9371_gpio_export(ad9371_gpio), + .rx_data_0_rx_serial_data (rx_data[0]), + .rx_data_1_rx_serial_data (rx_data[1]), + .rx_data_2_rx_serial_data (rx_data[2]), + .rx_data_3_rx_serial_data (rx_data[3]), + .rx_os_ref_clk_clk (ref_clk1), + .rx_os_sync_export (rx_os_sync), + .rx_os_sysref_export (sysref), + .rx_ref_clk_clk (ref_clk1), + .rx_sync_export (rx_sync), + .rx_sysref_export (sysref), + .sys_clk_clk (sys_clk), + .sys_ddr3_cntrl_mem_mem_ck (ddr3_clk_p), + .sys_ddr3_cntrl_mem_mem_ck_n (ddr3_clk_n), + .sys_ddr3_cntrl_mem_mem_a (ddr3_a[11:0]), + .sys_ddr3_cntrl_mem_mem_ba (ddr3_ba), + .sys_ddr3_cntrl_mem_mem_cke (ddr3_cke), + .sys_ddr3_cntrl_mem_mem_cs_n (ddr3_cs_n), + .sys_ddr3_cntrl_mem_mem_odt (ddr3_odt), + .sys_ddr3_cntrl_mem_mem_reset_n (ddr3_reset_n), + .sys_ddr3_cntrl_mem_mem_we_n (ddr3_we_n), + .sys_ddr3_cntrl_mem_mem_ras_n (ddr3_ras_n), + .sys_ddr3_cntrl_mem_mem_cas_n (ddr3_cas_n), + .sys_ddr3_cntrl_mem_mem_dqs (ddr3_dqs_p[7:0]), + .sys_ddr3_cntrl_mem_mem_dqs_n (ddr3_dqs_n[7:0]), + .sys_ddr3_cntrl_mem_mem_dq (ddr3_dq[63:0]), + .sys_ddr3_cntrl_mem_mem_dm (ddr3_dm[7:0]), + .sys_ddr3_cntrl_oct_oct_rzqin (ddr3_rzq), + .sys_ddr3_cntrl_pll_ref_clk_clk (ddr3_ref_clk), + .sys_ethernet_mdio_mdc (eth_mdc), + .sys_ethernet_mdio_mdio_in (eth_mdio_i), + .sys_ethernet_mdio_mdio_out (eth_mdio_o), + .sys_ethernet_mdio_mdio_oen (eth_mdio_t), + .sys_ethernet_ref_clk_clk (eth_ref_clk), + .sys_ethernet_reset_reset (eth_reset), + .sys_ethernet_sgmii_rxp_0 (eth_rxd), + .sys_ethernet_sgmii_txp_0 (eth_txd), + .sys_gpio_bd_in_port (gpio_i[31:0]), + .sys_gpio_bd_out_port (gpio_o[31:0]), + .sys_gpio_in_export (gpio_i[63:32]), + .sys_gpio_out_export (gpio_o[63:32]), + .sys_rst_reset_n (sys_resetn), + .sys_spi_MISO (spi_miso), + .sys_spi_MOSI (spi_mosi), + .sys_spi_SCLK (spi_clk), + .sys_spi_SS_n (spi_csn_s), + .tx_data_0_tx_serial_data (tx_data[0]), + .tx_data_1_tx_serial_data (tx_data[1]), + .tx_data_2_tx_serial_data (tx_data[2]), + .tx_data_3_tx_serial_data (tx_data[3]), + .tx_ref_clk_clk (ref_clk1), + .tx_sync_export (tx_sync), + .tx_sysref_export (sysref)); + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/projects/adrv9371x/a10soc/Makefile b/projects/adrv9371x/a10soc/Makefile new file mode 100644 index 000000000..07188ad32 --- /dev/null +++ b/projects/adrv9371x/a10soc/Makefile @@ -0,0 +1,152 @@ +#################################################################################### +#################################################################################### +## Copyright 2011(c) Analog Devices, Inc. +## Auto-generated, do not modify! +#################################################################################### +#################################################################################### + +ifeq ($(MMU),) + MMU := 1 +endif + +export ALT_NIOS_MMU_ENABLED := $(MMU) + +M_DEPS += system_top.v +M_DEPS += system_qsys.tcl +M_DEPS += system_project.tcl +M_DEPS += system_constr.sdc +M_DEPS += ../common/adrv9371x_qsys.tcl +M_DEPS += ../../scripts/adi_tquest.tcl +M_DEPS += ../../scripts/adi_env.tcl +M_DEPS += ../../common/altera/sys_gen.tcl +M_DEPS += ../../common/a10soc/a10soc_system_qsys.tcl +M_DEPS += ../../common/a10soc/a10soc_system_assign.tcl +M_DEPS += ../../../library/altera/avl_adxcfg/avl_adxcfg.v +M_DEPS += ../../../library/altera/avl_adxcfg/avl_adxcfg_hw.tcl +M_DEPS += ../../../library/altera/avl_adxcvr/avl_adxcvr_hw.tcl +M_DEPS += ../../../library/altera/axi_adxcvr/axi_adxcvr.v +M_DEPS += ../../../library/altera/axi_adxcvr/axi_adxcvr_hw.tcl +M_DEPS += ../../../library/altera/axi_adxcvr/axi_adxcvr_up.v +M_DEPS += ../../../library/altera/common/ad_dcfilter.v +M_DEPS += ../../../library/altera/common/ad_mul.v +M_DEPS += ../../../library/axi_ad9371/axi_ad9371.v +M_DEPS += ../../../library/axi_ad9371/axi_ad9371_hw.tcl +M_DEPS += ../../../library/axi_ad9371/axi_ad9371_if.v +M_DEPS += ../../../library/axi_ad9371/axi_ad9371_rx.v +M_DEPS += ../../../library/axi_ad9371/axi_ad9371_rx_channel.v +M_DEPS += ../../../library/axi_ad9371/axi_ad9371_rx_os.v +M_DEPS += ../../../library/axi_ad9371/axi_ad9371_tx.v +M_DEPS += ../../../library/axi_ad9371/axi_ad9371_tx_channel.v +M_DEPS += ../../../library/axi_dmac/2d_transfer.v +M_DEPS += ../../../library/axi_dmac/address_generator.v +M_DEPS += ../../../library/axi_dmac/axi_dmac.v +M_DEPS += ../../../library/axi_dmac/axi_dmac_constr.sdc +M_DEPS += ../../../library/axi_dmac/axi_dmac_hw.tcl +M_DEPS += ../../../library/axi_dmac/axi_register_slice.v +M_DEPS += ../../../library/axi_dmac/data_mover.v +M_DEPS += ../../../library/axi_dmac/dest_axi_mm.v +M_DEPS += ../../../library/axi_dmac/dest_axi_stream.v +M_DEPS += ../../../library/axi_dmac/dest_fifo_inf.v +M_DEPS += ../../../library/axi_dmac/inc_id.h +M_DEPS += ../../../library/axi_dmac/request_arb.v +M_DEPS += ../../../library/axi_dmac/request_generator.v +M_DEPS += ../../../library/axi_dmac/resp.h +M_DEPS += ../../../library/axi_dmac/response_generator.v +M_DEPS += ../../../library/axi_dmac/response_handler.v +M_DEPS += ../../../library/axi_dmac/splitter.v +M_DEPS += ../../../library/axi_dmac/src_axi_mm.v +M_DEPS += ../../../library/axi_dmac/src_axi_stream.v +M_DEPS += ../../../library/axi_dmac/src_fifo_inf.v +M_DEPS += ../../../library/common/ad_axi_ip_constr.sdc +M_DEPS += ../../../library/common/ad_axis_inf_rx.v +M_DEPS += ../../../library/common/ad_datafmt.v +M_DEPS += ../../../library/common/ad_dds.v +M_DEPS += ../../../library/common/ad_dds_1.v +M_DEPS += ../../../library/common/ad_dds_sine.v +M_DEPS += ../../../library/common/ad_iqcor.v +M_DEPS += ../../../library/common/ad_mem_asym.v +M_DEPS += ../../../library/common/ad_rst.v +M_DEPS += ../../../library/common/ad_xcvr_rx_if.v +M_DEPS += ../../../library/common/sync_bits.v +M_DEPS += ../../../library/common/sync_gray.v +M_DEPS += ../../../library/common/up_adc_channel.v +M_DEPS += ../../../library/common/up_adc_common.v +M_DEPS += ../../../library/common/up_axi.v +M_DEPS += ../../../library/common/up_clock_mon.v +M_DEPS += ../../../library/common/up_dac_channel.v +M_DEPS += ../../../library/common/up_dac_common.v +M_DEPS += ../../../library/common/up_xfer_cntrl.v +M_DEPS += ../../../library/common/up_xfer_status.v +M_DEPS += ../../../library/scripts/adi_env.tcl +M_DEPS += ../../../library/scripts/adi_ip_alt.tcl +M_DEPS += ../../../library/util_adcfifo/util_adcfifo.v +M_DEPS += ../../../library/util_adcfifo/util_adcfifo_constr.sdc +M_DEPS += ../../../library/util_adcfifo/util_adcfifo_hw.tcl +M_DEPS += ../../../library/util_axis_fifo/address_gray.v +M_DEPS += ../../../library/util_axis_fifo/address_gray_pipelined.v +M_DEPS += ../../../library/util_axis_fifo/address_sync.v +M_DEPS += ../../../library/util_axis_fifo/util_axis_fifo.v +M_DEPS += ../../../library/util_axis_resize/util_axis_resize.v +M_DEPS += ../../../library/util_cpack/util_cpack.v +M_DEPS += ../../../library/util_cpack/util_cpack_dsf.v +M_DEPS += ../../../library/util_cpack/util_cpack_hw.tcl +M_DEPS += ../../../library/util_cpack/util_cpack_mux.v +M_DEPS += ../../../library/util_upack/util_upack.v +M_DEPS += ../../../library/util_upack/util_upack_dmx.v +M_DEPS += ../../../library/util_upack/util_upack_dsf.v +M_DEPS += ../../../library/util_upack/util_upack_hw.tcl + + +M_ALTERA := quartus_sh --64bit -t + + +M_FLIST += *.log +M_FLIST += *_INFO.txt +M_FLIST += *_dump.txt +M_FLIST += db +M_FLIST += *.asm.rpt +M_FLIST += *.done +M_FLIST += *.eda.rpt +M_FLIST += *.fit.* +M_FLIST += *.map.* +M_FLIST += *.sta.* +M_FLIST += *.qsf +M_FLIST += *.qpf +M_FLIST += *.qws +M_FLIST += *.sof +M_FLIST += *.cdf +M_FLIST += *.sld +M_FLIST += *.qdf +M_FLIST += hc_output +M_FLIST += system_bd +M_FLIST += hps_isw_handoff +M_FLIST += hps_sdram_*.csv +M_FLIST += *ddr3_*.csv +M_FLIST += incremental_db +M_FLIST += reconfig_mif +M_FLIST += *.sopcinfo +M_FLIST += *.jdi +M_FLIST += *.pin +M_FLIST += *_summary.csv +M_FLIST += *.dpf + + + +.PHONY: all clean clean-all +all: adrv9371x_a10soc.sof + + + +clean:clean-all + + +clean-all: + rm -rf $(M_FLIST) + + +adrv9371x_a10soc.sof: $(M_DEPS) + -rm -rf $(M_FLIST) + $(M_ALTERA) system_project.tcl >> adrv9371x_a10soc_quartus.log 2>&1 + +#################################################################################### +#################################################################################### diff --git a/projects/adrv9371x/a10soc/system_constr.sdc b/projects/adrv9371x/a10soc/system_constr.sdc new file mode 100644 index 000000000..029e779b7 --- /dev/null +++ b/projects/adrv9371x/a10soc/system_constr.sdc @@ -0,0 +1,40 @@ + +create_clock -period "10.000 ns" -name sys_clk_100mhz [get_ports {sys_clk}] +create_clock -period "8.139 ns" -name ref_clk0_122mhz [get_ports {ref_clk0}] +create_clock -period "8.139 ns" -name ref_clk1_122mhz [get_ports {ref_clk1}] + +derive_pll_clocks +derive_clock_uncertainty + +set_false_path -from [get_clocks {sys_clk_100mhz}]\ + -through [get_nets *altera_jesd204_tx_csr_inst*]\ + -to [get_clocks {i_system_bd|avl_ad9371_tx_xcvr|alt_core_pll|outclk0}] + +set_false_path -from [get_clocks {sys_clk_100mhz}]\ + -through [get_nets *altera_jesd204_tx_ctl_inst*]\ + -to [get_clocks {i_system_bd|avl_ad9371_tx_xcvr|alt_core_pll|outclk0}] + +set_false_path -from [get_clocks {sys_clk_100mhz}]\ + -through [get_nets *altera_jesd204_rx_csr_inst*]\ + -to [get_clocks {i_system_bd|avl_ad9371_rx_xcvr|alt_core_pll|outclk0}] + +set_false_path -from [get_clocks {sys_clk_100mhz}]\ + -through [get_nets *altera_jesd204_rx_csr_inst*]\ + -to [get_clocks {i_system_bd|avl_ad9371_rx_os_xcvr|alt_core_pll|outclk0}] + +set_false_path -from [get_clocks {i_system_bd|avl_ad9371_tx_xcvr|alt_core_pll|outclk0}]\ + -through [get_nets *altera_jesd204_tx_csr_inst*]\ + -to [get_clocks {sys_clk_100mhz}] + +set_false_path -from [get_clocks {i_system_bd|avl_ad9371_tx_xcvr|alt_core_pll|outclk0}]\ + -through [get_nets *altera_jesd204_tx_ctl_inst*]\ + -to [get_clocks {sys_clk_100mhz}] + +set_false_path -from [get_clocks {i_system_bd|avl_ad9371_rx_xcvr|alt_core_pll|outclk0}]\ + -through [get_nets *altera_jesd204_rx_csr_inst*]\ + -to [get_clocks {sys_clk_100mhz}] + +set_false_path -from [get_clocks {i_system_bd|avl_ad9371_rx_os_xcvr|alt_core_pll|outclk0}]\ + -through [get_nets *altera_jesd204_rx_csr_inst*]\ + -to [get_clocks {sys_clk_100mhz}] + diff --git a/projects/adrv9371x/a10soc/system_project.tcl b/projects/adrv9371x/a10soc/system_project.tcl new file mode 100644 index 000000000..21612194e --- /dev/null +++ b/projects/adrv9371x/a10soc/system_project.tcl @@ -0,0 +1,149 @@ + +load_package flow + +source ../../scripts/adi_env.tcl +project_new adrv9371x_a10soc -overwrite + +source "../../common/a10soc/a10soc_system_assign.tcl" + +set_global_assignment -name QSYS_FILE system_bd.qsys +set_global_assignment -name VERILOG_FILE system_top.v +set_global_assignment -name SDC_FILE system_constr.sdc +set_global_assignment -name TOP_LEVEL_ENTITY system_top + +# ad9371 + +set_location_assignment PIN_N29 -to ref_clk0 ; ## D04 FMC_HPC_GBTCLK0_M2C_P (NC) +set_location_assignment PIN_N28 -to "ref_clk0(n)" ; ## D05 FMC_HPC_GBTCLK0_M2C_N (NC) +set_location_assignment PIN_R29 -to ref_clk1 ; ## B20 FMC_HPC_GBTCLK1_M2C_P +set_location_assignment PIN_R28 -to "ref_clk1(n)" ; ## B21 FMC_HPC_GBTCLK1_M2C_N +set_location_assignment PIN_R33 -to rx_data[0] ; ## A02 FMC_HPC_DP1_M2C_P +set_location_assignment PIN_R32 -to "rx_data[0](n)" ; ## A03 FMC_HPC_DP1_M2C_N +set_location_assignment PIN_P35 -to rx_data[1] ; ## A06 FMC_HPC_DP2_M2C_P +set_location_assignment PIN_P34 -to "rx_data[1](n)" ; ## A07 FMC_HPC_DP2_M2C_N +set_location_assignment PIN_T31 -to rx_data[2] ; ## C06 FMC_HPC_DP0_M2C_P +set_location_assignment PIN_T30 -to "rx_data[2](n)" ; ## C07 FMC_HPC_DP0_M2C_N +set_location_assignment PIN_P31 -to rx_data[3] ; ## A10 FMC_HPC_DP3_M2C_P +set_location_assignment PIN_P30 -to "rx_data[3](n)" ; ## A11 FMC_HPC_DP3_M2C_N +set_location_assignment PIN_M39 -to tx_data[0] ; ## A22 FMC_HPC_DP1_C2M_P (tx_data_p[3]) +set_location_assignment PIN_M38 -to "tx_data[0](n)" ; ## A23 FMC_HPC_DP1_C2M_N (tx_data_n[3]) +set_location_assignment PIN_L37 -to tx_data[1] ; ## A26 FMC_HPC_DP2_C2M_P (tx_data_p[0]) +set_location_assignment PIN_L36 -to "tx_data[1](n)" ; ## A27 FMC_HPC_DP2_C2M_N (tx_data_n[0]) +set_location_assignment PIN_N37 -to tx_data[2] ; ## C02 FMC_HPC_DP0_C2M_P (tx_data_p[1]) +set_location_assignment PIN_N36 -to "tx_data[2](n)" ; ## C03 FMC_HPC_DP0_C2M_N (tx_data_n[1]) +set_location_assignment PIN_K39 -to tx_data[3] ; ## A30 FMC_HPC_DP3_C2M_P (tx_data_p[2]) +set_location_assignment PIN_K38 -to "tx_data[3](n)" ; ## A31 FMC_HPC_DP3_C2M_N (tx_data_n[2]) + +set_instance_assignment -name IO_STANDARD LVDS -to ref_clk0 +set_instance_assignment -name IO_STANDARD LVDS -to ref_clk1 +set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to rx_data[0] +set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to rx_data[1] +set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to rx_data[2] +set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to rx_data[3] +set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to tx_data[0] +set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to tx_data[1] +set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to tx_data[2] +set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to tx_data[3] + +set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_0 -to rx_data[0] +set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_1 -to rx_data[1] +set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_2 -to rx_data[2] +set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_3 -to rx_data[3] + +set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_0 -to tx_data[0] +set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_1 -to tx_data[1] +set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_2 -to tx_data[2] +set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_3 -to tx_data[3] + +set_location_assignment PIN_C14 -to rx_sync ; ## G09 FMC_HPC_LA03_P +set_location_assignment PIN_D14 -to rx_sync(n) ; ## G10 FMC_HPC_LA03_N +set_location_assignment PIN_E3 -to rx_os_sync ; ## G27 FMC_HPC_LA25_P (Sniffer) +set_location_assignment PIN_F3 -to rx_os_sync(n) ; ## G28 FMC_HPC_LA25_N (Sniffer) +set_location_assignment PIN_C13 -to tx_sync ; ## H07 FMC_HPC_LA02_P +set_location_assignment PIN_D13 -to tx_sync(n) ; ## H08 FMC_HPC_LA02_N +set_location_assignment PIN_P11 -to sysref ; ## G36 FMC_HPC_LA33_P +set_location_assignment PIN_R11 -to sysref(n) ; ## G37 FMC_HPC_LA33_N + +set_instance_assignment -name IO_STANDARD LVDS -to rx_sync +set_instance_assignment -name IO_STANDARD LVDS -to rx_os_sync +set_instance_assignment -name IO_STANDARD LVDS -to tx_sync +set_instance_assignment -name IO_STANDARD LVDS -to sysref +set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to tx_sync +set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to sysref + +set_location_assignment PIN_A13 -to spi_csn_ad9528 ; ## D15 FMC_HPC_LA09_N +set_location_assignment PIN_A12 -to spi_csn_ad9371 ; ## D14 FMC_HPC_LA09_P +set_location_assignment PIN_A9 -to spi_clk ; ## H13 FMC_HPC_LA07_P +set_location_assignment PIN_B9 -to spi_mosi ; ## H14 FMC_HPC_LA07_N +set_location_assignment PIN_B11 -to spi_miso ; ## G12 FMC_HPC_LA08_P + +set_instance_assignment -name IO_STANDARD "1.8 V" -to spi_csn_ad9528 +set_instance_assignment -name IO_STANDARD "1.8 V" -to spi_csn_ad9371 +set_instance_assignment -name IO_STANDARD "1.8 V" -to spi_clk +set_instance_assignment -name IO_STANDARD "1.8 V" -to spi_mosi +set_instance_assignment -name IO_STANDARD "1.8 V" -to spi_miso + +set_location_assignment PIN_F2 -to ad9528_reset_b ; ## D26 FMC_HPC_LA26_P +set_location_assignment PIN_G2 -to ad9528_sysref_req ; ## D27 FMC_HPC_LA26_N +set_location_assignment PIN_J11 -to ad9371_tx1_enable ; ## D17 FMC_HPC_LA13_P +set_location_assignment PIN_J9 -to ad9371_tx2_enable ; ## C18 FMC_HPC_LA14_P +set_location_assignment PIN_K11 -to ad9371_rx1_enable ; ## D18 FMC_HPC_LA13_N +set_location_assignment PIN_J10 -to ad9371_rx2_enable ; ## C19 FMC_HPC_LA14_N +set_location_assignment PIN_F13 -to ad9371_test ; ## D11 FMC_HPC_LA05_P (DNI/NC) +set_location_assignment PIN_H12 -to ad9371_reset_b ; ## H10 FMC_HPC_LA04_P +set_location_assignment PIN_H13 -to ad9371_gpint ; ## H11 FMC_HPC_LA04_N + +set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9528_reset_b +set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9528_sysref_req +set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_tx1_enable +set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_tx2_enable +set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_rx1_enable +set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_rx2_enable +set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_test +set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_reset_b +set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpint + +# single ended default + +set_location_assignment PIN_D4 -to ad9371_gpio[0] ; ## H19 FMC_HPC_LA15_P +set_location_assignment PIN_D5 -to ad9371_gpio[1] ; ## H20 FMC_HPC_LA15_N +set_location_assignment PIN_D6 -to ad9371_gpio[2] ; ## G18 FMC_HPC_LA16_P +set_location_assignment PIN_E6 -to ad9371_gpio[3] ; ## G19 FMC_HPC_LA16_N +set_location_assignment PIN_C2 -to ad9371_gpio[4] ; ## H25 FMC_HPC_LA21_P +set_location_assignment PIN_D3 -to ad9371_gpio[5] ; ## H26 FMC_HPC_LA21_N +set_location_assignment PIN_G7 -to ad9371_gpio[6] ; ## C22 FMC_HPC_LA18_CC_P +set_location_assignment PIN_H7 -to ad9371_gpio[7] ; ## C23 FMC_HPC_LA18_CC_N +set_location_assignment PIN_G4 -to ad9371_gpio[8] ; ## G25 FMC_HPC_LA22_N (LVDS_1N) +set_location_assignment PIN_G5 -to ad9371_gpio[9] ; ## H22 FMC_HPC_LA19_P (LVDS_2P) +set_location_assignment PIN_G6 -to ad9371_gpio[10] ; ## H23 FMC_HPC_LA19_N (LVDS_2N) +set_location_assignment PIN_C3 -to ad9371_gpio[11] ; ## G21 FMC_HPC_LA20_P (LVDS_3P) +set_location_assignment PIN_C4 -to ad9371_gpio[12] ; ## G22 FMC_HPC_LA20_N (LVDS_3N) +set_location_assignment PIN_P10 -to ad9371_gpio[13] ; ## G31 FMC_HPC_LA29_N (LVDS_4N) +set_location_assignment PIN_N9 -to ad9371_gpio[14] ; ## G30 FMC_HPC_LA29_P (LVDS_4P) +set_location_assignment PIN_F4 -to ad9371_gpio[15] ; ## G24 FMC_HPC_LA22_P (LVDS_1P) +set_location_assignment PIN_N13 -to ad9371_gpio[16] ; ## G16 FMC_HPC_LA12_N (LVDS_5N) +set_location_assignment PIN_M12 -to ad9371_gpio[17] ; ## G15 FMC_HPC_LA12_P (LVDS_5P) +set_location_assignment PIN_F14 -to ad9371_gpio[18] ; ## D12 FMC_HPC_LA05_N + +set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio[0] +set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio[1] +set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio[2] +set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio[3] +set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio[4] +set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio[5] +set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio[6] +set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio[7] +set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio[8] +set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio[9] +set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio[10] +set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio[11] +set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio[12] +set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio[13] +set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio[14] +set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio[15] +set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio[16] +set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio[17] +set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio[18] + +execute_flow -compile + diff --git a/projects/adrv9371x/a10soc/system_qsys.tcl b/projects/adrv9371x/a10soc/system_qsys.tcl new file mode 100644 index 000000000..7581f7875 --- /dev/null +++ b/projects/adrv9371x/a10soc/system_qsys.tcl @@ -0,0 +1,6 @@ + + +source $ad_hdl_dir/projects/common/a10soc/a10soc_system_qsys.tcl +source ../common/adrv9371x_qsys.tcl + + diff --git a/projects/adrv9371x/a10soc/system_top.v b/projects/adrv9371x/a10soc/system_top.v new file mode 100644 index 000000000..c56298487 --- /dev/null +++ b/projects/adrv9371x/a10soc/system_top.v @@ -0,0 +1,276 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top ( + + // clock and resets + + input sys_clk, + input sys_resetn, + + // hps-ddr4 (32) + + input hps_ddr_ref_clk, + output [ 0:0] hps_ddr_clk_p, + output [ 0:0] hps_ddr_clk_n, + output [ 16:0] hsp_ddr_a, + output [ 1:0] hps_ddr_ba, + output [ 0:0] hps_ddr_bg, + output [ 0:0] hps_ddr_cke, + output [ 0:0] hps_ddr_cs_n, + output [ 0:0] hps_ddr_odt, + output [ 0:0] hps_ddr_reset_n, + output [ 0:0] hps_ddr_act_n, + output [ 0:0] hps_ddr_par, + input [ 0:0] hps_ddr_alert_n, + inout [ 3:0] hps_ddr_dqs_p, + inout [ 3:0] hps_ddr_dqs_n, + inout [ 31:0] hps_ddr_dq, + inout [ 3:0] hps_ddr_dbi_n, + input hps_ddr_rzq, + + // hps-ethernet + + input [ 0:0] hps_eth_rxclk, + input [ 0:0] hps_eth_rxctl, + input [ 3:0] hps_eth_rxd, + output [ 0:0] hps_eth_txclk, + output [ 0:0] hps_eth_txctl, + output [ 3:0] hps_eth_txd, + output [ 0:0] hps_eth_mdc, + inout [ 0:0] hps_eth_mdio, + + // hps-sdio + + output [ 0:0] hps_sdio_clk, + inout [ 0:0] hps_sdio_cmd, + inout [ 7:0] hps_sdio_d, + + // hps-usb + + input [ 0:0] hps_usb_clk, + input [ 0:0] hps_usb_dir, + input [ 0:0] hps_usb_nxt, + output [ 0:0] hps_usb_stp, + inout [ 7:0] hps_usb_d, + + // hps-uart + + input [ 0:0] hps_uart_rx, + output [ 0:0] hps_uart_tx, + + // hps-i2c (shared w fmc-a, fmc-b) + + inout [ 0:0] hps_i2c_sda, + inout [ 0:0] hps_i2c_scl, + + // hps-gpio (max-v-u16) + + inout [ 3:0] hps_gpio, + + // gpio (max-v-u21) + + input [ 7:0] gpio_bd_i, + output [ 3:0] gpio_bd_o, + + // ad9371-interface + + input ref_clk0, + input ref_clk1, + input [ 3:0] rx_data, + output [ 3:0] tx_data, + output rx_sync, + output rx_os_sync, + input tx_sync, + input sysref, + + output ad9528_reset_b, + output ad9528_sysref_req, + output ad9371_tx1_enable, + output ad9371_tx2_enable, + output ad9371_rx1_enable, + output ad9371_rx2_enable, + output ad9371_test, + output ad9371_reset_b, + input ad9371_gpint, + + inout [ 18:0] ad9371_gpio, + + output spi_csn_ad9528, + output spi_csn_ad9371, + output spi_clk, + output spi_mosi, + input spi_miso); + + // internal signals + + wire sys_hps_resetn; + wire sys_resetn_s; + wire [ 7:0] spi_csn; + wire [ 31:0] gpio_i; + wire [ 31:0] gpio_o; + + // gpio (ad9371) + + assign ad9371_tx1_enable = gpio_o[23]; + assign ad9371_tx2_enable = gpio_o[22]; + assign ad9371_rx1_enable = gpio_o[21]; + assign ad9371_rx2_enable = gpio_o[20]; + assign ad9371_test = gpio_o[19]; + assign ad9371_reset_b = gpio_o[18]; + assign ad9528_sysref_req = gpio_o[17]; + assign ad9528_reset_b = gpio_o[16]; + + assign gpio_i[31:25] = gpio_o[31:25]; + assign gpio_i[24:24] = ad9371_gpint; + assign gpio_i[23:16] = gpio_o[23:16]; + + // gpio (max-v-u21) + + assign gpio_i[15:12] = gpio_o[15:12]; + assign gpio_i[11: 4] = gpio_bd_i; + assign gpio_i[ 3: 0] = gpio_o[3:0]; + + assign gpio_bd_o = gpio_o[3:0]; + + // spi + + assign spi_csn_ad9528 = spi_csn[1]; + assign spi_csn_ad9371 = spi_csn[0]; + assign sys_resetn_s = sys_resetn & sys_hps_resetn; + + // instantiations + + system_bd i_system_bd ( + .avl_ad9371_gpio_export (ad9371_gpio), + .rx_data_0_rx_serial_data (rx_data[0]), + .rx_data_1_rx_serial_data (rx_data[1]), + .rx_data_2_rx_serial_data (rx_data[2]), + .rx_data_3_rx_serial_data (rx_data[3]), + .rx_os_ref_clk_clk (ref_clk1), + .rx_os_sync_export (rx_os_sync), + .rx_os_sysref_export (sysref), + .rx_ref_clk_clk (ref_clk1), + .rx_sync_export (rx_sync), + .rx_sysref_export (sysref), + .sys_clk_clk (sys_clk), + .sys_gpio_in_export (gpio_i), + .sys_gpio_out_export (gpio_o), + .sys_hps_ddr_mem_ck (hps_ddr_clk_p), + .sys_hps_ddr_mem_ck_n (hps_ddr_clk_n), + .sys_hps_ddr_mem_a (hsp_ddr_a), + .sys_hps_ddr_mem_act_n (hps_ddr_act_n), + .sys_hps_ddr_mem_ba (hps_ddr_ba), + .sys_hps_ddr_mem_bg (hps_ddr_bg), + .sys_hps_ddr_mem_cke (hps_ddr_cke), + .sys_hps_ddr_mem_cs_n (hps_ddr_cs_n), + .sys_hps_ddr_mem_odt (hps_ddr_odt), + .sys_hps_ddr_mem_reset_n (hps_ddr_reset_n), + .sys_hps_ddr_mem_par (hps_ddr_par), + .sys_hps_ddr_mem_alert_n (hps_ddr_alert_n), + .sys_hps_ddr_mem_dqs (hps_ddr_dqs_p), + .sys_hps_ddr_mem_dqs_n (hps_ddr_dqs_n), + .sys_hps_ddr_mem_dq (hps_ddr_dq), + .sys_hps_ddr_mem_dbi_n (hps_ddr_dbi_n), + .sys_hps_ddr_oct_oct_rzqin (hps_ddr_rzq), + .sys_hps_ddr_ref_clk_clk (hps_ddr_ref_clk), + .sys_hps_ddr_rstn_reset_n (sys_resetn), + .sys_hps_io_hps_io_phery_emac0_TX_CLK (hps_eth_txclk), + .sys_hps_io_hps_io_phery_emac0_TXD0 (hps_eth_txd[0]), + .sys_hps_io_hps_io_phery_emac0_TXD1 (hps_eth_txd[1]), + .sys_hps_io_hps_io_phery_emac0_TXD2 (hps_eth_txd[2]), + .sys_hps_io_hps_io_phery_emac0_TXD3 (hps_eth_txd[3]), + .sys_hps_io_hps_io_phery_emac0_RX_CTL (hps_eth_rxctl), + .sys_hps_io_hps_io_phery_emac0_TX_CTL (hps_eth_txctl), + .sys_hps_io_hps_io_phery_emac0_RX_CLK (hps_eth_rxclk), + .sys_hps_io_hps_io_phery_emac0_RXD0 (hps_eth_rxd[0]), + .sys_hps_io_hps_io_phery_emac0_RXD1 (hps_eth_rxd[1]), + .sys_hps_io_hps_io_phery_emac0_RXD2 (hps_eth_rxd[2]), + .sys_hps_io_hps_io_phery_emac0_RXD3 (hps_eth_rxd[3]), + .sys_hps_io_hps_io_phery_emac0_MDIO (hps_eth_mdio), + .sys_hps_io_hps_io_phery_emac0_MDC (hps_eth_mdc), + .sys_hps_io_hps_io_phery_sdmmc_CMD (hps_sdio_cmd), + .sys_hps_io_hps_io_phery_sdmmc_D0 (hps_sdio_d[0]), + .sys_hps_io_hps_io_phery_sdmmc_D1 (hps_sdio_d[1]), + .sys_hps_io_hps_io_phery_sdmmc_D2 (hps_sdio_d[2]), + .sys_hps_io_hps_io_phery_sdmmc_D3 (hps_sdio_d[3]), + .sys_hps_io_hps_io_phery_sdmmc_D4 (hps_sdio_d[4]), + .sys_hps_io_hps_io_phery_sdmmc_D5 (hps_sdio_d[5]), + .sys_hps_io_hps_io_phery_sdmmc_D6 (hps_sdio_d[6]), + .sys_hps_io_hps_io_phery_sdmmc_D7 (hps_sdio_d[7]), + .sys_hps_io_hps_io_phery_sdmmc_CCLK (hps_sdio_clk), + .sys_hps_io_hps_io_phery_usb0_DATA0 (hps_usb_d[0]), + .sys_hps_io_hps_io_phery_usb0_DATA1 (hps_usb_d[1]), + .sys_hps_io_hps_io_phery_usb0_DATA2 (hps_usb_d[2]), + .sys_hps_io_hps_io_phery_usb0_DATA3 (hps_usb_d[3]), + .sys_hps_io_hps_io_phery_usb0_DATA4 (hps_usb_d[4]), + .sys_hps_io_hps_io_phery_usb0_DATA5 (hps_usb_d[5]), + .sys_hps_io_hps_io_phery_usb0_DATA6 (hps_usb_d[6]), + .sys_hps_io_hps_io_phery_usb0_DATA7 (hps_usb_d[7]), + .sys_hps_io_hps_io_phery_usb0_CLK (hps_usb_clk), + .sys_hps_io_hps_io_phery_usb0_STP (hps_usb_stp), + .sys_hps_io_hps_io_phery_usb0_DIR (hps_usb_dir), + .sys_hps_io_hps_io_phery_usb0_NXT (hps_usb_nxt), + .sys_hps_io_hps_io_phery_uart1_RX (hps_uart_rx), + .sys_hps_io_hps_io_phery_uart1_TX (hps_uart_tx), + .sys_hps_io_hps_io_phery_i2c1_SDA (hps_i2c_sda), + .sys_hps_io_hps_io_phery_i2c1_SCL (hps_i2c_scl), + .sys_hps_io_hps_io_gpio_gpio1_io5 (hps_gpio[0]), + .sys_hps_io_hps_io_gpio_gpio1_io14 (hps_gpio[1]), + .sys_hps_io_hps_io_gpio_gpio1_io16 (hps_gpio[2]), + .sys_hps_io_hps_io_gpio_gpio1_io17 (hps_gpio[3]), + .sys_hps_out_rstn_reset_n (sys_hps_resetn), + .sys_hps_rstn_reset_n (sys_resetn), + .sys_rstn_reset_n (sys_resetn_s), + .sys_spi_MISO (spi_miso), + .sys_spi_MOSI (spi_mosi), + .sys_spi_SCLK (spi_clk), + .sys_spi_SS_n (spi_csn), + .tx_data_0_tx_serial_data (tx_data[0]), + .tx_data_1_tx_serial_data (tx_data[1]), + .tx_data_2_tx_serial_data (tx_data[2]), + .tx_data_3_tx_serial_data (tx_data[3]), + .tx_ref_clk_clk (ref_clk1), + .tx_sync_export (tx_sync), + .tx_sysref_export (sysref)); + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/projects/adrv9371x/common/adrv9371x_bd.tcl b/projects/adrv9371x/common/adrv9371x_bd.tcl new file mode 100644 index 000000000..c655a8c58 --- /dev/null +++ b/projects/adrv9371x/common/adrv9371x_bd.tcl @@ -0,0 +1,343 @@ + +# ad9371 + +create_bd_port -dir I dac_fifo_bypass + +# dac peripherals + +set axi_ad9371_tx_clkgen [create_bd_cell -type ip -vlnv analog.com:user:axi_clkgen:1.0 axi_ad9371_tx_clkgen] +set_property -dict [list CONFIG.ID {2}] $axi_ad9371_tx_clkgen +set_property -dict [list CONFIG.CLKIN_PERIOD {8}] $axi_ad9371_tx_clkgen +set_property -dict [list CONFIG.VCO_DIV {1}] $axi_ad9371_tx_clkgen +set_property -dict [list CONFIG.VCO_MUL {8}] $axi_ad9371_tx_clkgen +set_property -dict [list CONFIG.CLK0_DIV {8}] $axi_ad9371_tx_clkgen + +set axi_ad9371_tx_xcvr [create_bd_cell -type ip -vlnv analog.com:user:axi_adxcvr:1.0 axi_ad9371_tx_xcvr] +set_property -dict [list CONFIG.NUM_OF_LANES {4}] $axi_ad9371_tx_xcvr +set_property -dict [list CONFIG.QPLL_ENABLE {1}] $axi_ad9371_tx_xcvr +set_property -dict [list CONFIG.TX_OR_RX_N {1}] $axi_ad9371_tx_xcvr + +set axi_ad9371_tx_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:7.0 axi_ad9371_tx_jesd] +set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {1}] $axi_ad9371_tx_jesd +set_property -dict [list CONFIG.C_LANES {4}] $axi_ad9371_tx_jesd + +set util_ad9371_tx_upack [create_bd_cell -type ip -vlnv analog.com:user:util_upack:1.0 util_ad9371_tx_upack] +set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {32}] $util_ad9371_tx_upack +set_property -dict [list CONFIG.NUM_OF_CHANNELS {4}] $util_ad9371_tx_upack + +set axi_ad9371_tx_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9371_tx_dma] +set_property -dict [list CONFIG.DMA_TYPE_SRC {0}] $axi_ad9371_tx_dma +set_property -dict [list CONFIG.DMA_TYPE_DEST {1}] $axi_ad9371_tx_dma +set_property -dict [list CONFIG.CYCLIC {1}] $axi_ad9371_tx_dma +set_property -dict [list CONFIG.AXI_SLICE_SRC {0}] $axi_ad9371_tx_dma +set_property -dict [list CONFIG.AXI_SLICE_DEST {1}] $axi_ad9371_tx_dma +set_property -dict [list CONFIG.ASYNC_CLK_DEST_REQ {1}] $axi_ad9371_tx_dma +set_property -dict [list CONFIG.ASYNC_CLK_SRC_DEST {1}] $axi_ad9371_tx_dma +set_property -dict [list CONFIG.ASYNC_CLK_REQ_SRC {1}] $axi_ad9371_tx_dma +set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9371_tx_dma +set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {128}] $axi_ad9371_tx_dma + +# adc peripherals + +set axi_ad9371_rx_clkgen [create_bd_cell -type ip -vlnv analog.com:user:axi_clkgen:1.0 axi_ad9371_rx_clkgen] +set_property -dict [list CONFIG.ID {2}] $axi_ad9371_rx_clkgen +set_property -dict [list CONFIG.CLKIN_PERIOD {8}] $axi_ad9371_rx_clkgen +set_property -dict [list CONFIG.VCO_DIV {1}] $axi_ad9371_rx_clkgen +set_property -dict [list CONFIG.VCO_MUL {8}] $axi_ad9371_rx_clkgen +set_property -dict [list CONFIG.CLK0_DIV {8}] $axi_ad9371_rx_clkgen + +set axi_ad9371_rx_xcvr [create_bd_cell -type ip -vlnv analog.com:user:axi_adxcvr:1.0 axi_ad9371_rx_xcvr] +set_property -dict [list CONFIG.NUM_OF_LANES {2}] $axi_ad9371_rx_xcvr +set_property -dict [list CONFIG.QPLL_ENABLE {0}] $axi_ad9371_rx_xcvr +set_property -dict [list CONFIG.TX_OR_RX_N {0}] $axi_ad9371_rx_xcvr + +set axi_ad9371_rx_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:7.0 axi_ad9371_rx_jesd] +set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9371_rx_jesd +set_property -dict [list CONFIG.C_LANES {2}] $axi_ad9371_rx_jesd + +set util_ad9371_rx_cpack [create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 util_ad9371_rx_cpack] +set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {16}] $util_ad9371_rx_cpack +set_property -dict [list CONFIG.NUM_OF_CHANNELS {4}] $util_ad9371_rx_cpack + +set axi_ad9371_rx_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9371_rx_dma] +set_property -dict [list CONFIG.DMA_TYPE_SRC {2}] $axi_ad9371_rx_dma +set_property -dict [list CONFIG.DMA_TYPE_DEST {0}] $axi_ad9371_rx_dma +set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad9371_rx_dma +set_property -dict [list CONFIG.SYNC_TRANSFER_START {1}] $axi_ad9371_rx_dma +set_property -dict [list CONFIG.AXI_SLICE_SRC {0}] $axi_ad9371_rx_dma +set_property -dict [list CONFIG.AXI_SLICE_DEST {0}] $axi_ad9371_rx_dma +set_property -dict [list CONFIG.ASYNC_CLK_DEST_REQ {1}] $axi_ad9371_rx_dma +set_property -dict [list CONFIG.ASYNC_CLK_SRC_DEST {1}] $axi_ad9371_rx_dma +set_property -dict [list CONFIG.ASYNC_CLK_REQ_SRC {1}] $axi_ad9371_rx_dma +set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9371_rx_dma +set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {64}] $axi_ad9371_rx_dma + +# adc-os peripherals + +set axi_ad9371_rx_os_clkgen [create_bd_cell -type ip -vlnv analog.com:user:axi_clkgen:1.0 axi_ad9371_rx_os_clkgen] +set_property -dict [list CONFIG.ID {2}] $axi_ad9371_rx_os_clkgen +set_property -dict [list CONFIG.CLKIN_PERIOD {8}] $axi_ad9371_rx_os_clkgen +set_property -dict [list CONFIG.VCO_DIV {1}] $axi_ad9371_rx_os_clkgen +set_property -dict [list CONFIG.VCO_MUL {8}] $axi_ad9371_rx_os_clkgen +set_property -dict [list CONFIG.CLK0_DIV {8}] $axi_ad9371_rx_os_clkgen + +set axi_ad9371_rx_os_xcvr [create_bd_cell -type ip -vlnv analog.com:user:axi_adxcvr:1.0 axi_ad9371_rx_os_xcvr] +set_property -dict [list CONFIG.NUM_OF_LANES {2}] $axi_ad9371_rx_os_xcvr +set_property -dict [list CONFIG.QPLL_ENABLE {0}] $axi_ad9371_rx_os_xcvr +set_property -dict [list CONFIG.TX_OR_RX_N {0}] $axi_ad9371_rx_os_xcvr + +set axi_ad9371_rx_os_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:7.0 axi_ad9371_rx_os_jesd] +set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9371_rx_os_jesd +set_property -dict [list CONFIG.C_LANES {2}] $axi_ad9371_rx_os_jesd + +set util_ad9371_rx_os_cpack [create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 util_ad9371_rx_os_cpack] +set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {32}] $util_ad9371_rx_os_cpack +set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $util_ad9371_rx_os_cpack + +set axi_ad9371_rx_os_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9371_rx_os_dma] +set_property -dict [list CONFIG.DMA_TYPE_SRC {2}] $axi_ad9371_rx_os_dma +set_property -dict [list CONFIG.DMA_TYPE_DEST {0}] $axi_ad9371_rx_os_dma +set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad9371_rx_os_dma +set_property -dict [list CONFIG.SYNC_TRANSFER_START {1}] $axi_ad9371_rx_os_dma +set_property -dict [list CONFIG.AXI_SLICE_SRC {0}] $axi_ad9371_rx_os_dma +set_property -dict [list CONFIG.AXI_SLICE_DEST {0}] $axi_ad9371_rx_os_dma +set_property -dict [list CONFIG.ASYNC_CLK_DEST_REQ {1}] $axi_ad9371_rx_os_dma +set_property -dict [list CONFIG.ASYNC_CLK_SRC_DEST {1}] $axi_ad9371_rx_os_dma +set_property -dict [list CONFIG.ASYNC_CLK_REQ_SRC {1}] $axi_ad9371_rx_os_dma +set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9371_rx_os_dma +set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {64}] $axi_ad9371_rx_os_dma + +# common cores + +set axi_ad9371_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9371:1.0 axi_ad9371_core] + +set util_ad9371_xcvr [create_bd_cell -type ip -vlnv analog.com:user:util_adxcvr:1.0 util_ad9371_xcvr] +set_property -dict [list CONFIG.RX_NUM_OF_LANES {4}] $util_ad9371_xcvr +set_property -dict [list CONFIG.TX_NUM_OF_LANES {4}] $util_ad9371_xcvr +set_property -dict [list CONFIG.TX_OUT_DIV {2}] $util_ad9371_xcvr +set_property -dict [list CONFIG.CPLL_FBDIV {4}] $util_ad9371_xcvr +set_property -dict [list CONFIG.RX_CLK25_DIV {5}] $util_ad9371_xcvr +set_property -dict [list CONFIG.TX_CLK25_DIV {5}] $util_ad9371_xcvr +set_property -dict [list CONFIG.RX_PMA_CFG {0x00018480}] $util_ad9371_xcvr +set_property -dict [list CONFIG.RX_CDR_CFG {0x03000023ff20400020}] $util_ad9371_xcvr +set_property -dict [list CONFIG.QPLL_FBDIV {"0100100000"}] $util_ad9371_xcvr + +# xcvr interfaces + +create_bd_port -dir I tx_ref_clk_0 +create_bd_port -dir I rx_ref_clk_0 +create_bd_port -dir I rx_ref_clk_2 + +ad_xcvrpll tx_ref_clk_0 util_ad9371_xcvr/qpll_ref_clk_0 +ad_xcvrpll rx_ref_clk_0 util_ad9371_xcvr/cpll_ref_clk_0 +ad_xcvrpll rx_ref_clk_0 util_ad9371_xcvr/cpll_ref_clk_1 +ad_xcvrpll rx_ref_clk_2 util_ad9371_xcvr/cpll_ref_clk_2 +ad_xcvrpll rx_ref_clk_2 util_ad9371_xcvr/cpll_ref_clk_3 +ad_xcvrpll axi_ad9371_tx_xcvr/up_pll_rst util_ad9371_xcvr/up_qpll_rst_0 +ad_xcvrpll axi_ad9371_rx_xcvr/up_pll_rst util_ad9371_xcvr/up_cpll_rst_0 +ad_xcvrpll axi_ad9371_rx_xcvr/up_pll_rst util_ad9371_xcvr/up_cpll_rst_1 +ad_xcvrpll axi_ad9371_rx_os_xcvr/up_pll_rst util_ad9371_xcvr/up_cpll_rst_2 +ad_xcvrpll axi_ad9371_rx_os_xcvr/up_pll_rst util_ad9371_xcvr/up_cpll_rst_3 +ad_connect sys_cpu_resetn util_ad9371_xcvr/up_rstn +ad_connect sys_cpu_clk util_ad9371_xcvr/up_clk + +ad_xcvrcon util_ad9371_xcvr axi_ad9371_tx_xcvr axi_ad9371_tx_jesd +ad_reconct util_ad9371_xcvr/tx_out_clk_0 axi_ad9371_tx_clkgen/clk +ad_connect axi_ad9371_tx_clkgen/clk_0 util_ad9371_xcvr/tx_clk_0 +ad_connect axi_ad9371_tx_clkgen/clk_0 util_ad9371_xcvr/tx_clk_1 +ad_connect axi_ad9371_tx_clkgen/clk_0 util_ad9371_xcvr/tx_clk_2 +ad_connect axi_ad9371_tx_clkgen/clk_0 util_ad9371_xcvr/tx_clk_3 +ad_connect axi_ad9371_tx_clkgen/clk_0 axi_ad9371_tx_jesd/tx_core_clk +ad_connect axi_ad9371_tx_clkgen/clk_0 axi_ad9371_tx_jesd_rstgen/slowest_sync_clk +ad_reconct util_ad9371_xcvr/tx_0 axi_ad9371_tx_jesd/gt3_tx +ad_reconct util_ad9371_xcvr/tx_1 axi_ad9371_tx_jesd/gt0_tx +ad_reconct util_ad9371_xcvr/tx_2 axi_ad9371_tx_jesd/gt1_tx +ad_reconct util_ad9371_xcvr/tx_3 axi_ad9371_tx_jesd/gt2_tx +ad_xcvrcon util_ad9371_xcvr axi_ad9371_rx_xcvr axi_ad9371_rx_jesd +ad_reconct util_ad9371_xcvr/rx_out_clk_0 axi_ad9371_rx_clkgen/clk +ad_connect axi_ad9371_rx_clkgen/clk_0 util_ad9371_xcvr/rx_clk_0 +ad_connect axi_ad9371_rx_clkgen/clk_0 util_ad9371_xcvr/rx_clk_1 +ad_connect axi_ad9371_rx_clkgen/clk_0 axi_ad9371_rx_jesd/rx_core_clk +ad_connect axi_ad9371_rx_clkgen/clk_0 axi_ad9371_rx_jesd_rstgen/slowest_sync_clk +ad_xcvrcon util_ad9371_xcvr axi_ad9371_rx_os_xcvr axi_ad9371_rx_os_jesd +ad_reconct util_ad9371_xcvr/rx_out_clk_2 axi_ad9371_rx_os_clkgen/clk +ad_connect axi_ad9371_rx_os_clkgen/clk_0 util_ad9371_xcvr/rx_clk_2 +ad_connect axi_ad9371_rx_os_clkgen/clk_0 util_ad9371_xcvr/rx_clk_3 +ad_connect axi_ad9371_rx_os_clkgen/clk_0 axi_ad9371_rx_os_jesd/rx_core_clk +ad_connect axi_ad9371_rx_os_clkgen/clk_0 axi_ad9371_rx_os_jesd_rstgen/slowest_sync_clk + +# dma clock & reset + +set_property -dict [list CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {150}] $sys_ps7 + +set sys_dma_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 sys_dma_rstgen] +set_property -dict [list CONFIG.C_EXT_RST_WIDTH {1}] $sys_dma_rstgen + +ad_connect sys_dma_clk sys_ps7/FCLK_CLK2 +ad_connect sys_dma_clk sys_dma_rstgen/slowest_sync_clk +ad_connect sys_ps7/FCLK_RESET2_N sys_dma_rstgen/ext_reset_in +ad_connect sys_dma_resetn sys_dma_rstgen/peripheral_aresetn + +# connections (dac) + +ad_connect axi_ad9371_tx_clkgen/clk_0 axi_ad9371_core/dac_clk +ad_connect axi_ad9371_tx_jesd/tx_tdata axi_ad9371_core/dac_tx_data +ad_connect axi_ad9371_tx_clkgen/clk_0 util_ad9371_tx_upack/dac_clk +ad_connect axi_ad9371_core/dac_valid_i0 util_ad9371_tx_upack/dac_valid_0 +ad_connect axi_ad9371_core/dac_enable_i0 util_ad9371_tx_upack/dac_enable_0 +ad_connect axi_ad9371_core/dac_data_i0 util_ad9371_tx_upack/dac_data_0 +ad_connect axi_ad9371_core/dac_valid_q0 util_ad9371_tx_upack/dac_valid_1 +ad_connect axi_ad9371_core/dac_enable_q0 util_ad9371_tx_upack/dac_enable_1 +ad_connect axi_ad9371_core/dac_data_q0 util_ad9371_tx_upack/dac_data_1 +ad_connect axi_ad9371_core/dac_valid_i1 util_ad9371_tx_upack/dac_valid_2 +ad_connect axi_ad9371_core/dac_enable_i1 util_ad9371_tx_upack/dac_enable_2 +ad_connect axi_ad9371_core/dac_data_i1 util_ad9371_tx_upack/dac_data_2 +ad_connect axi_ad9371_core/dac_valid_q1 util_ad9371_tx_upack/dac_valid_3 +ad_connect axi_ad9371_core/dac_enable_q1 util_ad9371_tx_upack/dac_enable_3 +ad_connect axi_ad9371_core/dac_data_q1 util_ad9371_tx_upack/dac_data_3 +ad_connect axi_ad9371_tx_clkgen/clk_0 axi_ad9371_dacfifo/dac_clk +ad_connect axi_ad9371_rx_jesd_rstgen/peripheral_reset axi_ad9371_dacfifo/dac_rst +ad_connect util_ad9371_tx_upack/dac_valid axi_ad9371_dacfifo/dac_valid +ad_connect util_ad9371_tx_upack/dac_data axi_ad9371_dacfifo/dac_data +ad_connect util_ad9371_tx_upack/dma_xfer_in axi_ad9371_dacfifo/dac_xfer_out +ad_connect axi_ad9371_dacfifo/ddr_clk axi_ad9371_dacfifo/dma_clk +ad_connect axi_ad9371_dacfifo/ddr_clk axi_ad9371_tx_dma/m_axis_aclk +ad_connect axi_ad9371_dacfifo/dma_rvalid axi_ad9371_tx_dma/m_axis_valid +ad_connect axi_ad9371_dacfifo/dma_rdata axi_ad9371_tx_dma/m_axis_data +ad_connect axi_ad9371_dacfifo/dma_rready axi_ad9371_tx_dma/m_axis_ready +ad_connect axi_ad9371_dacfifo/dma_xfer_req axi_ad9371_tx_dma/m_axis_xfer_req +ad_connect axi_ad9371_dacfifo/dma_xfer_last axi_ad9371_tx_dma/m_axis_last +ad_connect axi_ad9371_dacfifo/dac_dunf axi_ad9371_core/dac_dunf +ad_connect axi_ad9371_dacfifo/dac_fifo_bypass dac_fifo_bypass +ad_connect sys_dma_resetn axi_ad9371_tx_dma/m_src_axi_aresetn + +# connections (adc) + +ad_connect axi_ad9371_rx_clkgen/clk_0 axi_ad9371_core/adc_clk +ad_connect axi_ad9371_rx_jesd/rx_start_of_frame axi_ad9371_core/adc_rx_sof +ad_connect axi_ad9371_rx_jesd/rx_tdata axi_ad9371_core/adc_rx_data +ad_connect axi_ad9371_rx_clkgen/clk_0 util_ad9371_rx_cpack/adc_clk +ad_connect axi_ad9371_rx_jesd_rstgen/peripheral_reset util_ad9371_rx_cpack/adc_rst +ad_connect axi_ad9371_core/adc_enable_i0 util_ad9371_rx_cpack/adc_enable_0 +ad_connect axi_ad9371_core/adc_valid_i0 util_ad9371_rx_cpack/adc_valid_0 +ad_connect axi_ad9371_core/adc_data_i0 util_ad9371_rx_cpack/adc_data_0 +ad_connect axi_ad9371_core/adc_enable_q0 util_ad9371_rx_cpack/adc_enable_1 +ad_connect axi_ad9371_core/adc_valid_q0 util_ad9371_rx_cpack/adc_valid_1 +ad_connect axi_ad9371_core/adc_data_q0 util_ad9371_rx_cpack/adc_data_1 +ad_connect axi_ad9371_core/adc_enable_i1 util_ad9371_rx_cpack/adc_enable_2 +ad_connect axi_ad9371_core/adc_valid_i1 util_ad9371_rx_cpack/adc_valid_2 +ad_connect axi_ad9371_core/adc_data_i1 util_ad9371_rx_cpack/adc_data_2 +ad_connect axi_ad9371_core/adc_enable_q1 util_ad9371_rx_cpack/adc_enable_3 +ad_connect axi_ad9371_core/adc_valid_q1 util_ad9371_rx_cpack/adc_valid_3 +ad_connect axi_ad9371_core/adc_data_q1 util_ad9371_rx_cpack/adc_data_3 +ad_connect axi_ad9371_rx_clkgen/clk_0 axi_ad9371_rx_dma/fifo_wr_clk +ad_connect util_ad9371_rx_cpack/adc_valid axi_ad9371_rx_dma/fifo_wr_en +ad_connect util_ad9371_rx_cpack/adc_sync axi_ad9371_rx_dma/fifo_wr_sync +ad_connect util_ad9371_rx_cpack/adc_data axi_ad9371_rx_dma/fifo_wr_din +ad_connect axi_ad9371_rx_dma/fifo_wr_overflow axi_ad9371_core/adc_dovf +ad_connect sys_dma_resetn axi_ad9371_rx_dma/m_dest_axi_aresetn + +# connections (adc-os) + +ad_connect axi_ad9371_rx_os_clkgen/clk_0 axi_ad9371_core/adc_os_clk +ad_connect axi_ad9371_rx_os_jesd/rx_start_of_frame axi_ad9371_core/adc_rx_os_sof +ad_connect axi_ad9371_rx_os_jesd/rx_tdata axi_ad9371_core/adc_rx_os_data +ad_connect axi_ad9371_rx_os_clkgen/clk_0 util_ad9371_rx_os_cpack/adc_clk +ad_connect axi_ad9371_rx_os_jesd_rstgen/peripheral_reset util_ad9371_rx_os_cpack/adc_rst +ad_connect axi_ad9371_core/adc_os_enable_i0 util_ad9371_rx_os_cpack/adc_enable_0 +ad_connect axi_ad9371_core/adc_os_valid_i0 util_ad9371_rx_os_cpack/adc_valid_0 +ad_connect axi_ad9371_core/adc_os_data_i0 util_ad9371_rx_os_cpack/adc_data_0 +ad_connect axi_ad9371_core/adc_os_enable_q0 util_ad9371_rx_os_cpack/adc_enable_1 +ad_connect axi_ad9371_core/adc_os_valid_q0 util_ad9371_rx_os_cpack/adc_valid_1 +ad_connect axi_ad9371_core/adc_os_data_q0 util_ad9371_rx_os_cpack/adc_data_1 +ad_connect axi_ad9371_rx_os_clkgen/clk_0 axi_ad9371_rx_os_dma/fifo_wr_clk +ad_connect util_ad9371_rx_os_cpack/adc_valid axi_ad9371_rx_os_dma/fifo_wr_en +ad_connect util_ad9371_rx_os_cpack/adc_sync axi_ad9371_rx_os_dma/fifo_wr_sync +ad_connect util_ad9371_rx_os_cpack/adc_data axi_ad9371_rx_os_dma/fifo_wr_din +ad_connect axi_ad9371_rx_os_dma/fifo_wr_overflow axi_ad9371_core/adc_os_dovf +ad_connect sys_dma_resetn axi_ad9371_rx_os_dma/m_dest_axi_aresetn + +# interconnect (cpu) + +ad_cpu_interconnect 0x44A00000 axi_ad9371_core +ad_cpu_interconnect 0x44A80000 axi_ad9371_tx_xcvr +ad_cpu_interconnect 0x43C00000 axi_ad9371_tx_clkgen +ad_cpu_interconnect 0x44A90000 axi_ad9371_tx_jesd +ad_cpu_interconnect 0x7c420000 axi_ad9371_tx_dma +ad_cpu_interconnect 0x44A60000 axi_ad9371_rx_xcvr +ad_cpu_interconnect 0x43C10000 axi_ad9371_rx_clkgen +ad_cpu_interconnect 0x44A91000 axi_ad9371_rx_jesd +ad_cpu_interconnect 0x7c400000 axi_ad9371_rx_dma +ad_cpu_interconnect 0x44A70000 axi_ad9371_rx_os_xcvr +ad_cpu_interconnect 0x43C20000 axi_ad9371_rx_os_clkgen +ad_cpu_interconnect 0x44A92000 axi_ad9371_rx_os_jesd +ad_cpu_interconnect 0x7c440000 axi_ad9371_rx_os_dma + +# gt uses hp3, and 100MHz clock for both DRP and AXI4 + +ad_mem_hp3_interconnect sys_cpu_clk sys_ps7/S_AXI_HP3 +ad_mem_hp3_interconnect sys_cpu_clk axi_ad9371_rx_xcvr/m_axi +ad_mem_hp3_interconnect sys_cpu_clk axi_ad9371_rx_os_xcvr/m_axi + +# interconnect (mem/dac) + +ad_mem_hp1_interconnect sys_dma_clk sys_ps7/S_AXI_HP1 +ad_mem_hp1_interconnect sys_dma_clk axi_ad9371_tx_dma/m_src_axi +ad_mem_hp2_interconnect sys_dma_clk sys_ps7/S_AXI_HP2 +ad_mem_hp2_interconnect sys_dma_clk axi_ad9371_rx_dma/m_dest_axi +ad_mem_hp2_interconnect sys_dma_clk axi_ad9371_rx_os_dma/m_dest_axi + +# interrupts + +ad_cpu_interrupt ps-11 mb-11 axi_ad9371_rx_os_dma/irq +ad_cpu_interrupt ps-12 mb-12 axi_ad9371_tx_dma/irq +ad_cpu_interrupt ps-13 mb-13 axi_ad9371_rx_dma/irq + +# ila + +set ila_adc [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.1 ila_adc] +set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_adc +set_property -dict [list CONFIG.C_NUM_OF_PROBES {4}] $ila_adc +set_property -dict [list CONFIG.C_PROBE0_WIDTH {16}] $ila_adc +set_property -dict [list CONFIG.C_PROBE1_WIDTH {16}] $ila_adc +set_property -dict [list CONFIG.C_PROBE2_WIDTH {16}] $ila_adc +set_property -dict [list CONFIG.C_PROBE3_WIDTH {16}] $ila_adc +set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila_adc +set_property -dict [list CONFIG.C_TRIGIN_EN {false}] $ila_adc + +ad_connect axi_ad9371_rx_clkgen/clk_0 ila_adc/clk +ad_connect axi_ad9371_core/adc_data_i0 ila_adc/probe0 +ad_connect axi_ad9371_core/adc_data_q0 ila_adc/probe1 +ad_connect axi_ad9371_core/adc_data_i1 ila_adc/probe2 +ad_connect axi_ad9371_core/adc_data_q1 ila_adc/probe3 + +set bsplit_os_adc_0 [create_bd_cell -type ip -vlnv analog.com:user:util_bsplit:1.0 bsplit_os_adc_0] +set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {16}] $bsplit_os_adc_0 +set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $bsplit_os_adc_0 + +set bsplit_os_adc_1 [create_bd_cell -type ip -vlnv analog.com:user:util_bsplit:1.0 bsplit_os_adc_1] +set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {16}] $bsplit_os_adc_1 +set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $bsplit_os_adc_1 + +set ila_os_adc [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.1 ila_os_adc] +set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_os_adc +set_property -dict [list CONFIG.C_NUM_OF_PROBES {6}] $ila_os_adc +set_property -dict [list CONFIG.C_PROBE0_WIDTH {1}] $ila_os_adc +set_property -dict [list CONFIG.C_PROBE1_WIDTH {16}] $ila_os_adc +set_property -dict [list CONFIG.C_PROBE2_WIDTH {16}] $ila_os_adc +set_property -dict [list CONFIG.C_PROBE3_WIDTH {1}] $ila_os_adc +set_property -dict [list CONFIG.C_PROBE4_WIDTH {16}] $ila_os_adc +set_property -dict [list CONFIG.C_PROBE5_WIDTH {16}] $ila_os_adc +set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila_os_adc +set_property -dict [list CONFIG.C_TRIGIN_EN {false}] $ila_os_adc + +ad_connect axi_ad9371_core/adc_os_data_i0 bsplit_os_adc_0/data +ad_connect axi_ad9371_core/adc_os_data_q0 bsplit_os_adc_1/data +ad_connect axi_ad9371_rx_os_clkgen/clk_0 ila_os_adc/clk +ad_connect axi_ad9371_core/adc_os_valid_i0 ila_os_adc/probe0 +ad_connect bsplit_os_adc_0/split_data_0 ila_os_adc/probe1 +ad_connect bsplit_os_adc_0/split_data_1 ila_os_adc/probe2 +ad_connect axi_ad9371_core/adc_os_valid_q0 ila_os_adc/probe3 +ad_connect bsplit_os_adc_1/split_data_0 ila_os_adc/probe4 +ad_connect bsplit_os_adc_1/split_data_1 ila_os_adc/probe5 + diff --git a/projects/adrv9371x/common/adrv9371x_qsys.tcl b/projects/adrv9371x/common/adrv9371x_qsys.tcl new file mode 100644 index 000000000..ebbf33fb2 --- /dev/null +++ b/projects/adrv9371x/common/adrv9371x_qsys.tcl @@ -0,0 +1,334 @@ + +# ad9371_tx-xcvr + +add_instance avl_ad9371_tx_xcvr avl_adxcvr 1.0 +set_instance_parameter_value avl_ad9371_tx_xcvr {ID} {0} +set_instance_parameter_value avl_ad9371_tx_xcvr {TX_OR_RX_N} {1} +set_instance_parameter_value avl_ad9371_tx_xcvr {PCS_CONFIG} {JESD_PCS_CFG2} +set_instance_parameter_value avl_ad9371_tx_xcvr {LANE_RATE} {4915.2} +set_instance_parameter_value avl_ad9371_tx_xcvr {PLLCLK_FREQUENCY} {2457.6} +set_instance_parameter_value avl_ad9371_tx_xcvr {REFCLK_FREQUENCY} {122.88} +set_instance_parameter_value avl_ad9371_tx_xcvr {CORECLK_FREQUENCY} {122.88} +set_instance_parameter_value avl_ad9371_tx_xcvr {NUM_OF_LANES} {4} +set_instance_parameter_value avl_ad9371_tx_xcvr {NUM_OF_CONVS} {4} +set_instance_parameter_value avl_ad9371_tx_xcvr {FRM_BCNT} {2} +set_instance_parameter_value avl_ad9371_tx_xcvr {FRM_SCNT} {1} +set_instance_parameter_value avl_ad9371_tx_xcvr {MF_FCNT} {32} +set_instance_parameter_value avl_ad9371_tx_xcvr {HD} {1} +add_connection sys_clk.clk avl_ad9371_tx_xcvr.sys_clk +add_connection sys_clk.clk_reset avl_ad9371_tx_xcvr.sys_resetn +add_interface tx_ref_clk clock sink +set_interface_property tx_ref_clk EXPORT_OF avl_ad9371_tx_xcvr.ref_clk +add_interface tx_data_0 conduit end +set_interface_property tx_data_0 EXPORT_OF avl_ad9371_tx_xcvr.tx_data_0 +add_interface tx_data_1 conduit end +set_interface_property tx_data_1 EXPORT_OF avl_ad9371_tx_xcvr.tx_data_1 +add_interface tx_data_2 conduit end +set_interface_property tx_data_2 EXPORT_OF avl_ad9371_tx_xcvr.tx_data_2 +add_interface tx_data_3 conduit end +set_interface_property tx_data_3 EXPORT_OF avl_ad9371_tx_xcvr.tx_data_3 +add_interface tx_sysref conduit end +set_interface_property tx_sysref EXPORT_OF avl_ad9371_tx_xcvr.sysref +add_interface tx_sync conduit end +set_interface_property tx_sync EXPORT_OF avl_ad9371_tx_xcvr.sync +add_connection avl_ad9371_tx_xcvr.tx_phy_s_0 avl_ad9371_tx_xcvr.tx_ip_s_3 +add_connection avl_ad9371_tx_xcvr.tx_phy_s_1 avl_ad9371_tx_xcvr.tx_ip_s_0 +add_connection avl_ad9371_tx_xcvr.tx_phy_s_2 avl_ad9371_tx_xcvr.tx_ip_s_1 +add_connection avl_ad9371_tx_xcvr.tx_phy_s_3 avl_ad9371_tx_xcvr.tx_ip_s_2 +add_connection avl_ad9371_tx_xcvr.tx_ip_d_3 avl_ad9371_tx_xcvr.tx_phy_d_0 +add_connection avl_ad9371_tx_xcvr.tx_ip_d_0 avl_ad9371_tx_xcvr.tx_phy_d_1 +add_connection avl_ad9371_tx_xcvr.tx_ip_d_1 avl_ad9371_tx_xcvr.tx_phy_d_2 +add_connection avl_ad9371_tx_xcvr.tx_ip_d_2 avl_ad9371_tx_xcvr.tx_phy_d_3 + +# ad9371_tx-xcvr + +add_instance axi_ad9371_tx_xcvr axi_adxcvr 1.0 +set_instance_parameter_value axi_ad9371_tx_xcvr {ID} {0} +set_instance_parameter_value axi_ad9371_tx_xcvr {TX_OR_RX_N} {1} +set_instance_parameter_value axi_ad9371_tx_xcvr {NUM_OF_LANES} {4} +add_connection sys_clk.clk axi_ad9371_tx_xcvr.s_axi_clock +add_connection sys_clk.clk_reset axi_ad9371_tx_xcvr.s_axi_reset +add_connection axi_ad9371_tx_xcvr.if_up_rst avl_ad9371_tx_xcvr.rst +add_connection avl_ad9371_tx_xcvr.ready axi_ad9371_tx_xcvr.ready +add_connection axi_ad9371_tx_xcvr.core_pll_locked avl_ad9371_tx_xcvr.core_pll_locked + +# ad9371_rx-xcvr + +add_instance avl_ad9371_rx_xcvr avl_adxcvr 1.0 +set_instance_parameter_value avl_ad9371_rx_xcvr {ID} {1} +set_instance_parameter_value avl_ad9371_rx_xcvr {TX_OR_RX_N} {0} +set_instance_parameter_value avl_ad9371_rx_xcvr {PCS_CONFIG} {JESD_PCS_CFG2} +set_instance_parameter_value avl_ad9371_rx_xcvr {LANE_RATE} {4915.2} +set_instance_parameter_value avl_ad9371_rx_xcvr {PLLCLK_FREQUENCY} {2457.6} +set_instance_parameter_value avl_ad9371_rx_xcvr {REFCLK_FREQUENCY} {122.88} +set_instance_parameter_value avl_ad9371_rx_xcvr {CORECLK_FREQUENCY} {122.88} +set_instance_parameter_value avl_ad9371_rx_xcvr {NUM_OF_LANES} {2} +set_instance_parameter_value avl_ad9371_rx_xcvr {NUM_OF_CONVS} {4} +set_instance_parameter_value avl_ad9371_rx_xcvr {FRM_BCNT} {4} +set_instance_parameter_value avl_ad9371_rx_xcvr {FRM_SCNT} {1} +set_instance_parameter_value avl_ad9371_rx_xcvr {MF_FCNT} {32} +set_instance_parameter_value avl_ad9371_rx_xcvr {HD} {1} +add_connection sys_clk.clk avl_ad9371_rx_xcvr.sys_clk +add_connection sys_clk.clk_reset avl_ad9371_rx_xcvr.sys_resetn +add_interface rx_ref_clk clock sink +set_interface_property rx_ref_clk EXPORT_OF avl_ad9371_rx_xcvr.ref_clk +add_interface rx_data_0 conduit end +set_interface_property rx_data_0 EXPORT_OF avl_ad9371_rx_xcvr.rx_data_0 +add_interface rx_data_1 conduit end +set_interface_property rx_data_1 EXPORT_OF avl_ad9371_rx_xcvr.rx_data_1 +add_interface rx_sysref conduit end +set_interface_property rx_sysref EXPORT_OF avl_ad9371_rx_xcvr.sysref +add_interface rx_sync conduit end +set_interface_property rx_sync EXPORT_OF avl_ad9371_rx_xcvr.sync + +# ad9371_rx-xcvr + +add_instance axi_ad9371_rx_xcvr axi_adxcvr 1.0 +set_instance_parameter_value axi_ad9371_rx_xcvr {ID} {1} +set_instance_parameter_value axi_ad9371_rx_xcvr {TX_OR_RX_N} {0} +set_instance_parameter_value axi_ad9371_rx_xcvr {NUM_OF_LANES} {2} +add_connection sys_clk.clk axi_ad9371_rx_xcvr.s_axi_clock +add_connection sys_clk.clk_reset axi_ad9371_rx_xcvr.s_axi_reset +add_connection axi_ad9371_rx_xcvr.if_up_rst avl_ad9371_rx_xcvr.rst +add_connection avl_ad9371_rx_xcvr.ready axi_ad9371_rx_xcvr.ready +add_connection axi_ad9371_rx_xcvr.core_pll_locked avl_ad9371_rx_xcvr.core_pll_locked + +# ad9371_rx_os-xcvr + +add_instance avl_ad9371_rx_os_xcvr avl_adxcvr 1.0 +set_instance_parameter_value avl_ad9371_rx_os_xcvr {ID} {1} +set_instance_parameter_value avl_ad9371_rx_os_xcvr {TX_OR_RX_N} {0} +set_instance_parameter_value avl_ad9371_rx_os_xcvr {PCS_CONFIG} {JESD_PCS_CFG2} +set_instance_parameter_value avl_ad9371_rx_os_xcvr {LANE_RATE} {4915.2} +set_instance_parameter_value avl_ad9371_rx_os_xcvr {PLLCLK_FREQUENCY} {2457.6} +set_instance_parameter_value avl_ad9371_rx_os_xcvr {REFCLK_FREQUENCY} {122.88} +set_instance_parameter_value avl_ad9371_rx_os_xcvr {CORECLK_FREQUENCY} {122.88} +set_instance_parameter_value avl_ad9371_rx_os_xcvr {NUM_OF_LANES} {2} +set_instance_parameter_value avl_ad9371_rx_os_xcvr {NUM_OF_CONVS} {2} +set_instance_parameter_value avl_ad9371_rx_os_xcvr {FRM_BCNT} {2} +set_instance_parameter_value avl_ad9371_rx_os_xcvr {FRM_SCNT} {1} +set_instance_parameter_value avl_ad9371_rx_os_xcvr {MF_FCNT} {32} +set_instance_parameter_value avl_ad9371_rx_os_xcvr {HD} {1} +add_connection sys_clk.clk avl_ad9371_rx_os_xcvr.sys_clk +add_connection sys_clk.clk_reset avl_ad9371_rx_os_xcvr.sys_resetn +add_interface rx_os_ref_clk clock sink +set_interface_property rx_os_ref_clk EXPORT_OF avl_ad9371_rx_os_xcvr.ref_clk +add_interface rx_data_2 conduit end +set_interface_property rx_data_2 EXPORT_OF avl_ad9371_rx_os_xcvr.rx_data_0 +add_interface rx_data_3 conduit end +set_interface_property rx_data_3 EXPORT_OF avl_ad9371_rx_os_xcvr.rx_data_1 +add_interface rx_os_sysref conduit end +set_interface_property rx_os_sysref EXPORT_OF avl_ad9371_rx_os_xcvr.sysref +add_interface rx_os_sync conduit end +set_interface_property rx_os_sync EXPORT_OF avl_ad9371_rx_os_xcvr.sync + +# ad9371_rx_os-xcvr + +add_instance axi_ad9371_rx_os_xcvr axi_adxcvr 1.0 +set_instance_parameter_value axi_ad9371_rx_os_xcvr {ID} {2} +set_instance_parameter_value axi_ad9371_rx_os_xcvr {TX_OR_RX_N} {0} +set_instance_parameter_value axi_ad9371_rx_os_xcvr {NUM_OF_LANES} {2} +add_connection sys_clk.clk axi_ad9371_rx_os_xcvr.s_axi_clock +add_connection sys_clk.clk_reset axi_ad9371_rx_os_xcvr.s_axi_reset +add_connection axi_ad9371_rx_os_xcvr.if_up_rst avl_ad9371_rx_os_xcvr.rst +add_connection avl_ad9371_rx_os_xcvr.ready axi_ad9371_rx_os_xcvr.ready +add_connection axi_ad9371_rx_os_xcvr.core_pll_locked avl_ad9371_rx_os_xcvr.core_pll_locked + +# ad9371-core + +add_instance axi_ad9371 axi_ad9371 1.0 +add_connection avl_ad9371_tx_xcvr.core_clk axi_ad9371.if_dac_clk +add_connection axi_ad9371.if_dac_tx_data avl_ad9371_tx_xcvr.ip_data +add_connection avl_ad9371_rx_xcvr.core_clk axi_ad9371.if_adc_clk +add_connection avl_ad9371_rx_xcvr.ip_sof axi_ad9371.if_adc_rx_sof +add_connection avl_ad9371_rx_xcvr.ip_data axi_ad9371.if_adc_rx_data +add_connection avl_ad9371_rx_os_xcvr.core_clk axi_ad9371.if_adc_os_clk +add_connection avl_ad9371_rx_os_xcvr.ip_sof axi_ad9371.if_adc_rx_os_sof +add_connection avl_ad9371_rx_os_xcvr.ip_data axi_ad9371.if_adc_rx_os_data +add_connection sys_clk.clk axi_ad9371.s_axi_clock +add_connection sys_clk.clk_reset axi_ad9371.s_axi_reset + +# pack(s) & unpack(s) + +add_instance axi_ad9371_tx_upack util_upack 1.0 +set_instance_parameter_value axi_ad9371_tx_upack {NUM_OF_CHANNELS} {4} +set_instance_parameter_value axi_ad9371_tx_upack {CHANNEL_DATA_WIDTH} {32} +add_connection avl_ad9371_tx_xcvr.core_clk axi_ad9371_tx_upack.if_dac_clk +add_connection axi_ad9371_tx_upack.dac_ch_0 axi_ad9371.dac_ch_0 +add_connection axi_ad9371_tx_upack.dac_ch_1 axi_ad9371.dac_ch_1 +add_connection axi_ad9371_tx_upack.dac_ch_2 axi_ad9371.dac_ch_2 +add_connection axi_ad9371_tx_upack.dac_ch_3 axi_ad9371.dac_ch_3 + +add_instance axi_ad9371_rx_cpack util_cpack 1.0 +set_instance_parameter_value axi_ad9371_rx_cpack {NUM_OF_CHANNELS} {4} +set_instance_parameter_value axi_ad9371_rx_cpack {CHANNEL_DATA_WIDTH} {16} +add_connection sys_clk.clk_reset axi_ad9371_rx_cpack.if_adc_rst +add_connection avl_ad9371_rx_xcvr.core_clk axi_ad9371_rx_cpack.if_adc_clk +add_connection axi_ad9371.adc_ch_0 axi_ad9371_rx_cpack.adc_ch_0 +add_connection axi_ad9371.adc_ch_1 axi_ad9371_rx_cpack.adc_ch_1 +add_connection axi_ad9371.adc_ch_2 axi_ad9371_rx_cpack.adc_ch_2 +add_connection axi_ad9371.adc_ch_3 axi_ad9371_rx_cpack.adc_ch_3 + +add_instance axi_ad9371_rx_os_cpack util_cpack 1.0 +set_instance_parameter_value axi_ad9371_rx_os_cpack {NUM_OF_CHANNELS} {2} +set_instance_parameter_value axi_ad9371_rx_os_cpack {CHANNEL_DATA_WIDTH} {32} +add_connection sys_clk.clk_reset axi_ad9371_rx_os_cpack.if_adc_rst +add_connection avl_ad9371_rx_os_xcvr.core_clk axi_ad9371_rx_os_cpack.if_adc_clk +add_connection axi_ad9371.adc_os_ch_0 axi_ad9371_rx_os_cpack.adc_ch_0 +add_connection axi_ad9371.adc_os_ch_1 axi_ad9371_rx_os_cpack.adc_ch_1 + +# dac & adc dma + +add_instance axi_ad9371_tx_dma axi_dmac 1.0 +set_instance_parameter_value axi_ad9371_tx_dma {ID} {0} +set_instance_parameter_value axi_ad9371_tx_dma {DMA_DATA_WIDTH_SRC} {128} +set_instance_parameter_value axi_ad9371_tx_dma {DMA_DATA_WIDTH_DEST} {128} +set_instance_parameter_value axi_ad9371_tx_dma {DMA_LENGTH_WIDTH} {24} +set_instance_parameter_value axi_ad9371_tx_dma {DMA_2D_TRANSFER} {0} +set_instance_parameter_value axi_ad9371_tx_dma {ASYNC_CLK_REQ_SRC} {1} +set_instance_parameter_value axi_ad9371_tx_dma {ASYNC_CLK_SRC_DEST} {1} +set_instance_parameter_value axi_ad9371_tx_dma {ASYNC_CLK_DEST_REQ} {1} +set_instance_parameter_value axi_ad9371_tx_dma {AXI_SLICE_DEST} {0} +set_instance_parameter_value axi_ad9371_tx_dma {AXI_SLICE_SRC} {0} +set_instance_parameter_value axi_ad9371_tx_dma {SYNC_TRANSFER_START} {0} +set_instance_parameter_value axi_ad9371_tx_dma {CYCLIC} {1} +set_instance_parameter_value axi_ad9371_tx_dma {DMA_TYPE_DEST} {2} +set_instance_parameter_value axi_ad9371_tx_dma {DMA_TYPE_SRC} {0} +set_instance_parameter_value axi_ad9371_tx_dma {FIFO_SIZE} {16} +add_connection avl_ad9371_tx_xcvr.core_clk axi_ad9371_tx_dma.if_fifo_rd_clk +add_connection axi_ad9371_tx_upack.if_dac_valid axi_ad9371_tx_dma.if_fifo_rd_en +add_connection axi_ad9371_tx_dma.if_fifo_rd_dout axi_ad9371_tx_upack.if_dac_data +add_connection axi_ad9371_tx_dma.if_fifo_rd_underflow axi_ad9371.if_dac_dunf +add_connection sys_clk.clk axi_ad9371_tx_dma.s_axi_clock +add_connection sys_clk.clk_reset axi_ad9371_tx_dma.s_axi_reset +add_connection sys_dma_clk.clk axi_ad9371_tx_dma.m_src_axi_clock +add_connection sys_dma_clk.clk_reset axi_ad9371_tx_dma.m_src_axi_reset + +add_instance axi_ad9371_rx_dma axi_dmac 1.0 +set_instance_parameter_value axi_ad9371_rx_dma {ID} {0} +set_instance_parameter_value axi_ad9371_rx_dma {DMA_DATA_WIDTH_SRC} {64} +set_instance_parameter_value axi_ad9371_rx_dma {DMA_DATA_WIDTH_DEST} {128} +set_instance_parameter_value axi_ad9371_rx_dma {DMA_LENGTH_WIDTH} {24} +set_instance_parameter_value axi_ad9371_rx_dma {DMA_2D_TRANSFER} {0} +set_instance_parameter_value axi_ad9371_rx_dma {ASYNC_CLK_REQ_SRC} {1} +set_instance_parameter_value axi_ad9371_rx_dma {ASYNC_CLK_SRC_DEST} {1} +set_instance_parameter_value axi_ad9371_rx_dma {ASYNC_CLK_DEST_REQ} {1} +set_instance_parameter_value axi_ad9371_rx_dma {AXI_SLICE_DEST} {0} +set_instance_parameter_value axi_ad9371_rx_dma {AXI_SLICE_SRC} {0} +set_instance_parameter_value axi_ad9371_rx_dma {SYNC_TRANSFER_START} {0} +set_instance_parameter_value axi_ad9371_rx_dma {CYCLIC} {0} +set_instance_parameter_value axi_ad9371_rx_dma {DMA_TYPE_DEST} {0} +set_instance_parameter_value axi_ad9371_rx_dma {DMA_TYPE_SRC} {2} +set_instance_parameter_value axi_ad9371_rx_dma {FIFO_SIZE} {16} +add_connection avl_ad9371_rx_xcvr.core_clk axi_ad9371_rx_dma.if_fifo_wr_clk +add_connection axi_ad9371_rx_cpack.if_adc_valid axi_ad9371_rx_dma.if_fifo_wr_en +add_connection axi_ad9371_rx_cpack.if_adc_sync axi_ad9371_rx_dma.if_fifo_wr_sync +add_connection axi_ad9371_rx_cpack.if_adc_data axi_ad9371_rx_dma.if_fifo_wr_din +add_connection axi_ad9371_rx_dma.if_fifo_wr_overflow axi_ad9371.if_adc_dovf +add_connection sys_clk.clk axi_ad9371_rx_dma.s_axi_clock +add_connection sys_clk.clk_reset axi_ad9371_rx_dma.s_axi_reset +add_connection sys_dma_clk.clk axi_ad9371_rx_dma.m_dest_axi_clock +add_connection sys_dma_clk.clk_reset axi_ad9371_rx_dma.m_dest_axi_reset + +add_instance axi_ad9371_rx_os_dma axi_dmac 1.0 +set_instance_parameter_value axi_ad9371_rx_os_dma {ID} {0} +set_instance_parameter_value axi_ad9371_rx_os_dma {DMA_DATA_WIDTH_SRC} {64} +set_instance_parameter_value axi_ad9371_rx_os_dma {DMA_DATA_WIDTH_DEST} {128} +set_instance_parameter_value axi_ad9371_rx_os_dma {DMA_LENGTH_WIDTH} {24} +set_instance_parameter_value axi_ad9371_rx_os_dma {DMA_2D_TRANSFER} {0} +set_instance_parameter_value axi_ad9371_rx_os_dma {ASYNC_CLK_REQ_SRC} {1} +set_instance_parameter_value axi_ad9371_rx_os_dma {ASYNC_CLK_SRC_DEST} {1} +set_instance_parameter_value axi_ad9371_rx_os_dma {ASYNC_CLK_DEST_REQ} {1} +set_instance_parameter_value axi_ad9371_rx_os_dma {AXI_SLICE_DEST} {0} +set_instance_parameter_value axi_ad9371_rx_os_dma {AXI_SLICE_SRC} {0} +set_instance_parameter_value axi_ad9371_rx_os_dma {SYNC_TRANSFER_START} {0} +set_instance_parameter_value axi_ad9371_rx_os_dma {CYCLIC} {0} +set_instance_parameter_value axi_ad9371_rx_os_dma {DMA_TYPE_DEST} {0} +set_instance_parameter_value axi_ad9371_rx_os_dma {DMA_TYPE_SRC} {2} +set_instance_parameter_value axi_ad9371_rx_os_dma {FIFO_SIZE} {16} +add_connection avl_ad9371_rx_os_xcvr.core_clk axi_ad9371_rx_os_dma.if_fifo_wr_clk +add_connection axi_ad9371_rx_os_cpack.if_adc_valid axi_ad9371_rx_os_dma.if_fifo_wr_en +add_connection axi_ad9371_rx_os_cpack.if_adc_sync axi_ad9371_rx_os_dma.if_fifo_wr_sync +add_connection axi_ad9371_rx_os_cpack.if_adc_data axi_ad9371_rx_os_dma.if_fifo_wr_din +add_connection axi_ad9371_rx_os_dma.if_fifo_wr_overflow axi_ad9371.if_adc_os_dovf +add_connection sys_clk.clk axi_ad9371_rx_os_dma.s_axi_clock +add_connection sys_clk.clk_reset axi_ad9371_rx_os_dma.s_axi_reset +add_connection sys_dma_clk.clk axi_ad9371_rx_os_dma.m_dest_axi_clock +add_connection sys_dma_clk.clk_reset axi_ad9371_rx_os_dma.m_dest_axi_reset + +# ad9371 gpio + +add_instance avl_ad9371_gpio altera_avalon_pio 16.0 +set_instance_parameter_value avl_ad9371_gpio {direction} {Bidir} +set_instance_parameter_value avl_ad9371_gpio {generateIRQ} {1} +set_instance_parameter_value avl_ad9371_gpio {width} {19} +add_connection sys_clk.clk avl_ad9371_gpio.clk +add_connection sys_clk.clk_reset avl_ad9371_gpio.reset +add_interface avl_ad9371_gpio conduit end +set_interface_property avl_ad9371_gpio EXPORT_OF avl_ad9371_gpio.external_connection + +# reconfig sharing + +add_instance avl_adxcfg_0 avl_adxcfg 1.0 +add_connection sys_clk.clk avl_adxcfg_0.rcfg_clk +add_connection sys_clk.clk_reset avl_adxcfg_0.rcfg_reset_n +add_connection avl_adxcfg_0.rcfg_m0 avl_ad9371_tx_xcvr.phy_reconfig_0 +add_connection avl_adxcfg_0.rcfg_m1 avl_ad9371_rx_xcvr.phy_reconfig_0 + +add_instance avl_adxcfg_1 avl_adxcfg 1.0 +add_connection sys_clk.clk avl_adxcfg_1.rcfg_clk +add_connection sys_clk.clk_reset avl_adxcfg_1.rcfg_reset_n +add_connection avl_adxcfg_1.rcfg_m0 avl_ad9371_tx_xcvr.phy_reconfig_1 +add_connection avl_adxcfg_1.rcfg_m1 avl_ad9371_rx_xcvr.phy_reconfig_1 + +add_instance avl_adxcfg_2 avl_adxcfg 1.0 +add_connection sys_clk.clk avl_adxcfg_2.rcfg_clk +add_connection sys_clk.clk_reset avl_adxcfg_2.rcfg_reset_n +add_connection avl_adxcfg_2.rcfg_m0 avl_ad9371_tx_xcvr.phy_reconfig_2 +add_connection avl_adxcfg_2.rcfg_m1 avl_ad9371_rx_os_xcvr.phy_reconfig_0 + +add_instance avl_adxcfg_3 avl_adxcfg 1.0 +add_connection sys_clk.clk avl_adxcfg_3.rcfg_clk +add_connection sys_clk.clk_reset avl_adxcfg_3.rcfg_reset_n +add_connection avl_adxcfg_3.rcfg_m0 avl_ad9371_tx_xcvr.phy_reconfig_3 +add_connection avl_adxcfg_3.rcfg_m1 avl_ad9371_rx_os_xcvr.phy_reconfig_1 + +# addresses + +ad_cpu_interconnect 0x00010000 avl_adxcfg_0.rcfg_s0 +ad_cpu_interconnect 0x00011000 avl_adxcfg_0.rcfg_s1 +ad_cpu_interconnect 0x00012000 avl_adxcfg_1.rcfg_s0 +ad_cpu_interconnect 0x00013000 avl_adxcfg_1.rcfg_s1 +ad_cpu_interconnect 0x00014000 avl_adxcfg_2.rcfg_s0 +ad_cpu_interconnect 0x00015000 avl_adxcfg_2.rcfg_s1 +ad_cpu_interconnect 0x00016000 avl_adxcfg_3.rcfg_s0 +ad_cpu_interconnect 0x00017000 avl_adxcfg_3.rcfg_s1 +ad_cpu_interconnect 0x00018000 avl_ad9371_tx_xcvr.core_pll_reconfig +ad_cpu_interconnect 0x00019000 avl_ad9371_tx_xcvr.ip_reconfig +ad_cpu_interconnect 0x0001a000 avl_ad9371_tx_xcvr.lane_pll_reconfig +ad_cpu_interconnect 0x0001b000 avl_ad9371_rx_xcvr.core_pll_reconfig +ad_cpu_interconnect 0x0001c000 avl_ad9371_rx_xcvr.ip_reconfig +ad_cpu_interconnect 0x0001d000 avl_ad9371_rx_os_xcvr.core_pll_reconfig +ad_cpu_interconnect 0x0001e000 avl_ad9371_rx_os_xcvr.ip_reconfig +ad_cpu_interconnect 0x00020000 axi_ad9371_tx_xcvr.s_axi +ad_cpu_interconnect 0x00030000 axi_ad9371_rx_xcvr.s_axi +ad_cpu_interconnect 0x00040000 axi_ad9371_rx_os_xcvr.s_axi +ad_cpu_interconnect 0x00050000 axi_ad9371_tx_dma.s_axi +ad_cpu_interconnect 0x00060000 axi_ad9371_rx_dma.s_axi +ad_cpu_interconnect 0x00070000 axi_ad9371_rx_os_dma.s_axi +ad_cpu_interconnect 0x00080000 axi_ad9371.s_axi +ad_cpu_interconnect 0x00090000 avl_ad9371_gpio.s1 + +# dma interconnects + +ad_dma_interconnect axi_ad9371_tx_dma.m_src_axi +ad_dma_interconnect axi_ad9371_rx_dma.m_dest_axi +ad_dma_interconnect axi_ad9371_rx_os_dma.m_dest_axi + +# interrupts + +ad_cpu_interrupt 11 axi_ad9371_tx_dma.interrupt_sender +ad_cpu_interrupt 12 axi_ad9371_rx_dma.interrupt_sender +ad_cpu_interrupt 13 axi_ad9371_rx_os_dma.interrupt_sender +ad_cpu_interrupt 14 avl_ad9371_gpio.irq + diff --git a/projects/fmcomms1/zc706/Makefile b/projects/adrv9371x/zc706/Makefile similarity index 63% rename from projects/fmcomms1/zc706/Makefile rename to projects/adrv9371x/zc706/Makefile index 5170046cd..f2145cd19 100644 --- a/projects/fmcomms1/zc706/Makefile +++ b/projects/adrv9371x/zc706/Makefile @@ -9,22 +9,27 @@ M_DEPS += system_top.v M_DEPS += system_project.tcl M_DEPS += system_constr.xdc M_DEPS += system_bd.tcl -M_DEPS += ../common/fmcomms1_bd.tcl +M_DEPS += ../common/adrv9371x_bd.tcl M_DEPS += ../../scripts/adi_project.tcl M_DEPS += ../../scripts/adi_env.tcl M_DEPS += ../../scripts/adi_board.tcl +M_DEPS += ../../common/zc706/zc706_system_plddr3_dacfifo.tcl +M_DEPS += ../../common/zc706/zc706_system_mig_constr.xdc +M_DEPS += ../../common/zc706/zc706_system_mig.prj M_DEPS += ../../common/zc706/zc706_system_constr.xdc M_DEPS += ../../common/zc706/zc706_system_bd.tcl -M_DEPS += ../../../library/common/ad_iobuf.v -M_DEPS += ../../../library/axi_ad9122/axi_ad9122.xpr -M_DEPS += ../../../library/axi_ad9643/axi_ad9643.xpr +M_DEPS += ../../../library/xilinx/common/ad_iobuf.v +M_DEPS += ../../../library/axi_ad9371/axi_ad9371.xpr +M_DEPS += ../../../library/xilinx/axi_adxcvr/axi_adxcvr.xpr M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr +M_DEPS += ../../../library/xilinx/axi_dacfifo/axi_dacfifo.xpr M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr +M_DEPS += ../../../library/xilinx/util_adxcvr/util_adxcvr.xpr +M_DEPS += ../../../library/util_bsplit/util_bsplit.xpr M_DEPS += ../../../library/util_cpack/util_cpack.xpr M_DEPS += ../../../library/util_upack/util_upack.xpr -M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr M_VIVADO := vivado -mode batch -source @@ -40,11 +45,12 @@ M_FLIST += *.sdk M_FLIST += *.hw M_FLIST += *.sim M_FLIST += .Xil +M_FLIST += *.ip_user_files .PHONY: all lib clean clean-all -all: lib fmcomms1_zc706.sdk/system_top.hdf +all: lib adrv9371x_zc706.sdk/system_top.hdf clean: @@ -52,32 +58,36 @@ clean: clean-all:clean - make -C ../../../library/axi_ad9122 clean - make -C ../../../library/axi_ad9643 clean + make -C ../../../library/axi_ad9371 clean + make -C ../../../library/xilinx/axi_adxcvr clean make -C ../../../library/axi_clkgen clean + make -C ../../../library/xilinx/axi_dacfifo clean make -C ../../../library/axi_dmac clean make -C ../../../library/axi_hdmi_tx clean make -C ../../../library/axi_spdif_tx clean + make -C ../../../library/xilinx/util_adxcvr clean + make -C ../../../library/util_bsplit clean make -C ../../../library/util_cpack clean make -C ../../../library/util_upack clean - make -C ../../../library/util_wfifo clean -fmcomms1_zc706.sdk/system_top.hdf: $(M_DEPS) - rm -rf $(M_FLIST) - $(M_VIVADO) system_project.tcl >> fmcomms1_zc706_vivado.log 2>&1 +adrv9371x_zc706.sdk/system_top.hdf: $(M_DEPS) + -rm -rf $(M_FLIST) + $(M_VIVADO) system_project.tcl >> adrv9371x_zc706_vivado.log 2>&1 lib: - make -C ../../../library/axi_ad9122 - make -C ../../../library/axi_ad9643 + make -C ../../../library/axi_ad9371 + make -C ../../../library/xilinx/axi_adxcvr make -C ../../../library/axi_clkgen + make -C ../../../library/xilinx/axi_dacfifo make -C ../../../library/axi_dmac make -C ../../../library/axi_hdmi_tx make -C ../../../library/axi_spdif_tx + make -C ../../../library/xilinx/util_adxcvr + make -C ../../../library/util_bsplit make -C ../../../library/util_cpack make -C ../../../library/util_upack - make -C ../../../library/util_wfifo #################################################################################### #################################################################################### diff --git a/projects/adrv9371x/zc706/system_bd.tcl b/projects/adrv9371x/zc706/system_bd.tcl new file mode 100644 index 000000000..92ff569bc --- /dev/null +++ b/projects/adrv9371x/zc706/system_bd.tcl @@ -0,0 +1,23 @@ + +source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl +source $ad_hdl_dir/projects/common/zc706/zc706_system_plddr3_dacfifo.tcl + +p_plddr3_dacfifo [current_bd_instance .] axi_ad9371_dacfifo 128 128 + +create_bd_port -dir I -type rst sys_rst +create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr3 +create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sys_clk + +set_property CONFIG.POLARITY ACTIVE_HIGH [get_bd_ports sys_rst] + +ad_connect sys_rst axi_ad9371_dacfifo/sys_rst +ad_connect sys_clk axi_ad9371_dacfifo/sys_clk +ad_connect ddr3 axi_ad9371_dacfifo/ddr3 + +create_bd_addr_seg -range 0x40000000 -offset 0x80000000 \ + [get_bd_addr_spaces axi_ad9371_dacfifo/axi_dacfifo/axi] \ + [get_bd_addr_segs axi_ad9371_dacfifo/axi_ddr_cntrl/memmap/memaddr] \ + SEG_axi_ddr_cntrl_memaddr + +source ../common/adrv9371x_bd.tcl + diff --git a/projects/adrv9371x/zc706/system_constr.xdc b/projects/adrv9371x/zc706/system_constr.xdc new file mode 100644 index 000000000..fa75a515d --- /dev/null +++ b/projects/adrv9371x/zc706/system_constr.xdc @@ -0,0 +1,80 @@ + +# ad9371 + +set_property -dict {PACKAGE_PIN AD10} [get_ports ref_clk0_p] ; ## D04 FMC_HPC_GBTCLK0_M2C_P (NC) +set_property -dict {PACKAGE_PIN AD9 } [get_ports ref_clk0_n] ; ## D05 FMC_HPC_GBTCLK0_M2C_N (NC) +set_property -dict {PACKAGE_PIN AA8 } [get_ports ref_clk1_p] ; ## B20 FMC_HPC_GBTCLK1_M2C_P +set_property -dict {PACKAGE_PIN AA7 } [get_ports ref_clk1_n] ; ## B21 FMC_HPC_GBTCLK1_M2C_N +set_property -dict {PACKAGE_PIN AJ8 } [get_ports rx_data_p[0]] ; ## A02 FMC_HPC_DP1_M2C_P +set_property -dict {PACKAGE_PIN AJ7 } [get_ports rx_data_n[0]] ; ## A03 FMC_HPC_DP1_M2C_N +set_property -dict {PACKAGE_PIN AG8 } [get_ports rx_data_p[1]] ; ## A06 FMC_HPC_DP2_M2C_P +set_property -dict {PACKAGE_PIN AG7 } [get_ports rx_data_n[1]] ; ## A07 FMC_HPC_DP2_M2C_N +set_property -dict {PACKAGE_PIN AH10} [get_ports rx_data_p[2]] ; ## C06 FMC_HPC_DP0_M2C_P +set_property -dict {PACKAGE_PIN AH9 } [get_ports rx_data_n[2]] ; ## C07 FMC_HPC_DP0_M2C_N +set_property -dict {PACKAGE_PIN AE8 } [get_ports rx_data_p[3]] ; ## A10 FMC_HPC_DP3_M2C_P +set_property -dict {PACKAGE_PIN AE7 } [get_ports rx_data_n[3]] ; ## A11 FMC_HPC_DP3_M2C_N +set_property -dict {PACKAGE_PIN AK6 } [get_ports tx_data_p[0]] ; ## A22 FMC_HPC_DP1_C2M_P (tx_data_p[3]) +set_property -dict {PACKAGE_PIN AK5 } [get_ports tx_data_n[0]] ; ## A23 FMC_HPC_DP1_C2M_N (tx_data_n[3]) +set_property -dict {PACKAGE_PIN AJ4 } [get_ports tx_data_p[1]] ; ## A26 FMC_HPC_DP2_C2M_P (tx_data_p[0]) +set_property -dict {PACKAGE_PIN AJ3 } [get_ports tx_data_n[1]] ; ## A27 FMC_HPC_DP2_C2M_N (tx_data_n[0]) +set_property -dict {PACKAGE_PIN AK10} [get_ports tx_data_p[2]] ; ## C02 FMC_HPC_DP0_C2M_P (tx_data_p[1]) +set_property -dict {PACKAGE_PIN AK9 } [get_ports tx_data_n[2]] ; ## C03 FMC_HPC_DP0_C2M_N (tx_data_n[1]) +set_property -dict {PACKAGE_PIN AK2 } [get_ports tx_data_p[3]] ; ## A30 FMC_HPC_DP3_C2M_P (tx_data_p[2]) +set_property -dict {PACKAGE_PIN AK1 } [get_ports tx_data_n[3]] ; ## A31 FMC_HPC_DP3_C2M_N (tx_data_n[2]) +set_property -dict {PACKAGE_PIN AH19 IOSTANDARD LVDS_25} [get_ports rx_sync_p] ; ## G09 FMC_HPC_LA03_P +set_property -dict {PACKAGE_PIN AJ19 IOSTANDARD LVDS_25} [get_ports rx_sync_n] ; ## G10 FMC_HPC_LA03_N +set_property -dict {PACKAGE_PIN T29 IOSTANDARD LVDS_25} [get_ports rx_os_sync_p] ; ## G27 FMC_HPC_LA25_P (Sniffer) +set_property -dict {PACKAGE_PIN U29 IOSTANDARD LVDS_25} [get_ports rx_os_sync_n] ; ## G28 FMC_HPC_LA25_N (Sniffer) +set_property -dict {PACKAGE_PIN AK17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sync_p] ; ## H07 FMC_HPC_LA02_P +set_property -dict {PACKAGE_PIN AK18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sync_n] ; ## H08 FMC_HPC_LA02_N +set_property -dict {PACKAGE_PIN N26 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports sysref_p] ; ## G36 FMC_HPC_LA33_P +set_property -dict {PACKAGE_PIN N27 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports sysref_n] ; ## G37 FMC_HPC_LA33_N + +set_property -dict {PACKAGE_PIN AE21 IOSTANDARD LVCMOS25} [get_ports spi_csn_ad9528] ; ## D15 FMC_HPC_LA09_N +set_property -dict {PACKAGE_PIN AD21 IOSTANDARD LVCMOS25} [get_ports spi_csn_ad9371] ; ## D14 FMC_HPC_LA09_P +set_property -dict {PACKAGE_PIN AJ23 IOSTANDARD LVCMOS25} [get_ports spi_clk] ; ## H13 FMC_HPC_LA07_P +set_property -dict {PACKAGE_PIN AJ24 IOSTANDARD LVCMOS25} [get_ports spi_mosi] ; ## H14 FMC_HPC_LA07_N +set_property -dict {PACKAGE_PIN AF19 IOSTANDARD LVCMOS25} [get_ports spi_miso] ; ## G12 FMC_HPC_LA08_P + +set_property -dict {PACKAGE_PIN R28 IOSTANDARD LVCMOS25} [get_ports ad9528_reset_b] ; ## D26 FMC_HPC_LA26_P +set_property -dict {PACKAGE_PIN T28 IOSTANDARD LVCMOS25} [get_ports ad9528_sysref_req] ; ## D27 FMC_HPC_LA26_N +set_property -dict {PACKAGE_PIN AA22 IOSTANDARD LVCMOS25} [get_ports ad9371_tx1_enable] ; ## D17 FMC_HPC_LA13_P +set_property -dict {PACKAGE_PIN AC24 IOSTANDARD LVCMOS25} [get_ports ad9371_tx2_enable] ; ## C18 FMC_HPC_LA14_P +set_property -dict {PACKAGE_PIN AA23 IOSTANDARD LVCMOS25} [get_ports ad9371_rx1_enable] ; ## D18 FMC_HPC_LA13_N +set_property -dict {PACKAGE_PIN AD24 IOSTANDARD LVCMOS25} [get_ports ad9371_rx2_enable] ; ## C19 FMC_HPC_LA14_N +set_property -dict {PACKAGE_PIN AH23 IOSTANDARD LVCMOS25} [get_ports ad9371_test] ; ## D11 FMC_HPC_LA05_P +set_property -dict {PACKAGE_PIN AJ20 IOSTANDARD LVCMOS25} [get_ports ad9371_reset_b] ; ## H10 FMC_HPC_LA04_P +set_property -dict {PACKAGE_PIN AK20 IOSTANDARD LVCMOS25} [get_ports ad9371_gpint] ; ## H11 FMC_HPC_LA04_N + +set_property -dict {PACKAGE_PIN Y22 IOSTANDARD LVCMOS25} [get_ports ad9371_gpio_00] ; ## H19 FMC_HPC_LA15_P +set_property -dict {PACKAGE_PIN Y23 IOSTANDARD LVCMOS25} [get_ports ad9371_gpio_01] ; ## H20 FMC_HPC_LA15_N +set_property -dict {PACKAGE_PIN AA24 IOSTANDARD LVCMOS25} [get_ports ad9371_gpio_02] ; ## G18 FMC_HPC_LA16_P +set_property -dict {PACKAGE_PIN AB24 IOSTANDARD LVCMOS25} [get_ports ad9371_gpio_03] ; ## G19 FMC_HPC_LA16_N +set_property -dict {PACKAGE_PIN W29 IOSTANDARD LVCMOS25} [get_ports ad9371_gpio_04] ; ## H25 FMC_HPC_LA21_P +set_property -dict {PACKAGE_PIN W30 IOSTANDARD LVCMOS25} [get_ports ad9371_gpio_05] ; ## H26 FMC_HPC_LA21_N +set_property -dict {PACKAGE_PIN W25 IOSTANDARD LVCMOS25} [get_ports ad9371_gpio_06] ; ## C22 FMC_HPC_LA18_CC_P +set_property -dict {PACKAGE_PIN W26 IOSTANDARD LVCMOS25} [get_ports ad9371_gpio_07] ; ## C23 FMC_HPC_LA18_CC_N +set_property -dict {PACKAGE_PIN V27 IOSTANDARD LVCMOS25} [get_ports ad9371_gpio_15] ; ## G24 FMC_HPC_LA22_P (LVDS Pairs?) +set_property -dict {PACKAGE_PIN W28 IOSTANDARD LVCMOS25} [get_ports ad9371_gpio_08] ; ## G25 FMC_HPC_LA22_N (LVDS Pairs?) +set_property -dict {PACKAGE_PIN T24 IOSTANDARD LVCMOS25} [get_ports ad9371_gpio_09] ; ## H22 FMC_HPC_LA19_P (LVDS Pairs?) +set_property -dict {PACKAGE_PIN T25 IOSTANDARD LVCMOS25} [get_ports ad9371_gpio_10] ; ## H23 FMC_HPC_LA19_N (LVDS Pairs?) +set_property -dict {PACKAGE_PIN U25 IOSTANDARD LVCMOS25} [get_ports ad9371_gpio_11] ; ## G21 FMC_HPC_LA20_P (LVDS Pairs?) +set_property -dict {PACKAGE_PIN V26 IOSTANDARD LVCMOS25} [get_ports ad9371_gpio_12] ; ## G22 FMC_HPC_LA20_N (LVDS Pairs?) +set_property -dict {PACKAGE_PIN R25 IOSTANDARD LVCMOS25} [get_ports ad9371_gpio_14] ; ## G30 FMC_HPC_LA29_P (LVDS Pairs?) +set_property -dict {PACKAGE_PIN R26 IOSTANDARD LVCMOS25} [get_ports ad9371_gpio_13] ; ## G31 FMC_HPC_LA29_N (LVDS Pairs?) +set_property -dict {PACKAGE_PIN AF23 IOSTANDARD LVCMOS25} [get_ports ad9371_gpio_17] ; ## G15 FMC_HPC_LA12_P (LVDS Pairs?) +set_property -dict {PACKAGE_PIN AF24 IOSTANDARD LVCMOS25} [get_ports ad9371_gpio_16] ; ## G16 FMC_HPC_LA12_N (LVDS Pairs?) +set_property -dict {PACKAGE_PIN AH24 IOSTANDARD LVCMOS25} [get_ports ad9371_gpio_18] ; ## D12 FMC_HPC_LA05_N + +# clocks + +create_clock -name tx_ref_clk -period 8.00 [get_ports ref_clk0_p] +create_clock -name rx_ref_clk -period 8.00 [get_ports ref_clk1_p] +create_clock -name tx_div_clk -period 8.00 [get_pins i_system_wrapper/system_i/util_ad9371_xcvr/inst/i_xch_0/i_gtxe2_channel/TXOUTCLK] +create_clock -name rx_div_clk -period 8.00 [get_pins i_system_wrapper/system_i/util_ad9371_xcvr/inst/i_xch_0/i_gtxe2_channel/RXOUTCLK] +create_clock -name rx_os_div_clk -period 8.00 [get_pins i_system_wrapper/system_i/util_ad9371_xcvr/inst/i_xch_2/i_gtxe2_channel/RXOUTCLK] + +set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9371_rx_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]] +set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9371_tx_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]] +set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9371_rx_os_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]] + diff --git a/projects/fmcomms6/zc706/system_project.tcl b/projects/adrv9371x/zc706/system_project.tcl similarity index 64% rename from projects/fmcomms6/zc706/system_project.tcl rename to projects/adrv9371x/zc706/system_project.tcl index 6be65ff55..183270edb 100644 --- a/projects/fmcomms6/zc706/system_project.tcl +++ b/projects/adrv9371x/zc706/system_project.tcl @@ -5,17 +5,17 @@ source ../../scripts/adi_env.tcl source $ad_hdl_dir/projects/scripts/adi_project.tcl source $ad_hdl_dir/projects/scripts/adi_board.tcl -adi_project_create fmcomms6_zc706 -adi_project_files fmcomms6_zc706 [list \ - "../common/fmcomms6_spi.v" \ +adi_project_create adrv9371x_zc706 +adi_project_files adrv9371x_zc706 [list \ "system_top.v" \ "system_constr.xdc"\ - "$ad_hdl_dir/library/common/ad_iobuf.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \ + "$ad_hdl_dir/projects/common/zc706/zc706_system_mig_constr.xdc" \ "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ] set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc] set_property PROCESSING_ORDER EARLY [get_files system_constr.xdc] -adi_project_run fmcomms6_zc706 +adi_project_run adrv9371x_zc706 diff --git a/projects/adrv9371x/zc706/system_top.v b/projects/adrv9371x/zc706/system_top.v new file mode 100644 index 000000000..ddda7293e --- /dev/null +++ b/projects/adrv9371x/zc706/system_top.v @@ -0,0 +1,458 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top ( + + ddr_addr, + ddr_ba, + ddr_cas_n, + ddr_ck_n, + ddr_ck_p, + ddr_cke, + ddr_cs_n, + ddr_dm, + ddr_dq, + ddr_dqs_n, + ddr_dqs_p, + ddr_odt, + ddr_ras_n, + ddr_reset_n, + ddr_we_n, + + fixed_io_ddr_vrn, + fixed_io_ddr_vrp, + fixed_io_mio, + fixed_io_ps_clk, + fixed_io_ps_porb, + fixed_io_ps_srstb, + + gpio_bd, + + hdmi_out_clk, + hdmi_vsync, + hdmi_hsync, + hdmi_data_e, + hdmi_data, + + spdif, + + iic_scl, + iic_sda, + + ref_clk0_p, + ref_clk0_n, + ref_clk1_p, + ref_clk1_n, + rx_data_p, + rx_data_n, + tx_data_p, + tx_data_n, + rx_sync_p, + rx_sync_n, + rx_os_sync_p, + rx_os_sync_n, + tx_sync_p, + tx_sync_n, + sysref_p, + sysref_n, + + spi_csn_ad9528, + spi_csn_ad9371, + spi_clk, + spi_mosi, + spi_miso, + + ad9528_reset_b, + ad9528_sysref_req, + ad9371_tx1_enable, + ad9371_tx2_enable, + ad9371_rx1_enable, + ad9371_rx2_enable, + ad9371_test, + ad9371_reset_b, + ad9371_gpint, + + ad9371_gpio_00, + ad9371_gpio_01, + ad9371_gpio_02, + ad9371_gpio_03, + ad9371_gpio_04, + ad9371_gpio_05, + ad9371_gpio_06, + ad9371_gpio_07, + ad9371_gpio_15, + ad9371_gpio_08, + ad9371_gpio_09, + ad9371_gpio_10, + ad9371_gpio_11, + ad9371_gpio_12, + ad9371_gpio_14, + ad9371_gpio_13, + ad9371_gpio_17, + ad9371_gpio_16, + ad9371_gpio_18, + + sys_rst, + sys_clk_p, + sys_clk_n, + + ddr3_addr, + ddr3_ba, + ddr3_cas_n, + ddr3_ck_n, + ddr3_ck_p, + ddr3_cke, + ddr3_cs_n, + ddr3_dm, + ddr3_dq, + ddr3_dqs_n, + ddr3_dqs_p, + ddr3_odt, + ddr3_ras_n, + ddr3_reset_n, + ddr3_we_n); + + inout [14:0] ddr_addr; + inout [ 2:0] ddr_ba; + inout ddr_cas_n; + inout ddr_ck_n; + inout ddr_ck_p; + inout ddr_cke; + inout ddr_cs_n; + inout [ 3:0] ddr_dm; + inout [31:0] ddr_dq; + inout [ 3:0] ddr_dqs_n; + inout [ 3:0] ddr_dqs_p; + inout ddr_odt; + inout ddr_ras_n; + inout ddr_reset_n; + inout ddr_we_n; + + inout fixed_io_ddr_vrn; + inout fixed_io_ddr_vrp; + inout [53:0] fixed_io_mio; + inout fixed_io_ps_clk; + inout fixed_io_ps_porb; + inout fixed_io_ps_srstb; + + inout [14:0] gpio_bd; + + output hdmi_out_clk; + output hdmi_vsync; + output hdmi_hsync; + output hdmi_data_e; + output [23:0] hdmi_data; + + output spdif; + + inout iic_scl; + inout iic_sda; + + input ref_clk0_p; + input ref_clk0_n; + input ref_clk1_p; + input ref_clk1_n; + input [ 3:0] rx_data_p; + input [ 3:0] rx_data_n; + output [ 3:0] tx_data_p; + output [ 3:0] tx_data_n; + output rx_sync_p; + output rx_sync_n; + output rx_os_sync_p; + output rx_os_sync_n; + input tx_sync_p; + input tx_sync_n; + input sysref_p; + input sysref_n; + + output spi_csn_ad9528; + output spi_csn_ad9371; + output spi_clk; + output spi_mosi; + input spi_miso; + + inout ad9528_reset_b; + inout ad9528_sysref_req; + inout ad9371_tx1_enable; + inout ad9371_tx2_enable; + inout ad9371_rx1_enable; + inout ad9371_rx2_enable; + inout ad9371_test; + inout ad9371_reset_b; + inout ad9371_gpint; + + inout ad9371_gpio_00; + inout ad9371_gpio_01; + inout ad9371_gpio_02; + inout ad9371_gpio_03; + inout ad9371_gpio_04; + inout ad9371_gpio_05; + inout ad9371_gpio_06; + inout ad9371_gpio_07; + inout ad9371_gpio_15; + inout ad9371_gpio_08; + inout ad9371_gpio_09; + inout ad9371_gpio_10; + inout ad9371_gpio_11; + inout ad9371_gpio_12; + inout ad9371_gpio_14; + inout ad9371_gpio_13; + inout ad9371_gpio_17; + inout ad9371_gpio_16; + inout ad9371_gpio_18; + + input sys_rst; + input sys_clk_p; + input sys_clk_n; + + + output [13:0] ddr3_addr; + output [ 2:0] ddr3_ba; + output ddr3_cas_n; + output [ 0:0] ddr3_ck_n; + output [ 0:0] ddr3_ck_p; + output [ 0:0] ddr3_cke; + output [ 0:0] ddr3_cs_n; + output [ 7:0] ddr3_dm; + inout [63:0] ddr3_dq; + inout [ 7:0] ddr3_dqs_n; + inout [ 7:0] ddr3_dqs_p; + output [ 0:0] ddr3_odt; + output ddr3_ras_n; + output ddr3_reset_n; + output ddr3_we_n; + + // internal signals + + wire [63:0] gpio_i; + wire [63:0] gpio_o; + wire [63:0] gpio_t; + wire ref_clk0; + wire ref_clk1; + wire rx_sync; + wire rx_os_sync; + wire tx_sync; + wire sysref; + + // instantiations + + IBUFDS_GTE2 i_ibufds_rx_ref_clk ( + .CEB (1'd0), + .I (ref_clk0_p), + .IB (ref_clk0_n), + .O (ref_clk0), + .ODIV2 ()); + + IBUFDS_GTE2 i_ibufds_ref_clk1 ( + .CEB (1'd0), + .I (ref_clk1_p), + .IB (ref_clk1_n), + .O (ref_clk1), + .ODIV2 ()); + + OBUFDS i_obufds_rx_sync ( + .I (rx_sync), + .O (rx_sync_p), + .OB (rx_sync_n)); + + OBUFDS i_obufds_rx_os_sync ( + .I (rx_os_sync), + .O (rx_os_sync_p), + .OB (rx_os_sync_n)); + + IBUFDS i_ibufds_tx_sync ( + .I (tx_sync_p), + .IB (tx_sync_n), + .O (tx_sync)); + + IBUFDS i_ibufds_sysref ( + .I (sysref_p), + .IB (sysref_n), + .O (sysref)); + + ad_iobuf #(.DATA_WIDTH(28)) i_iobuf ( + .dio_t ({gpio_t[59:32]}), + .dio_i ({gpio_o[59:32]}), + .dio_o ({gpio_i[59:32]}), + .dio_p ({ ad9528_reset_b, // 59 + ad9528_sysref_req, // 58 + ad9371_tx1_enable, // 57 + ad9371_tx2_enable, // 56 + ad9371_rx1_enable, // 55 + ad9371_rx2_enable, // 54 + ad9371_test, // 53 + ad9371_reset_b, // 52 + ad9371_gpint, // 51 + ad9371_gpio_00, // 50 + ad9371_gpio_01, // 49 + ad9371_gpio_02, // 48 + ad9371_gpio_03, // 47 + ad9371_gpio_04, // 46 + ad9371_gpio_05, // 45 + ad9371_gpio_06, // 44 + ad9371_gpio_07, // 43 + ad9371_gpio_15, // 42 + ad9371_gpio_08, // 41 + ad9371_gpio_09, // 40 + ad9371_gpio_10, // 39 + ad9371_gpio_11, // 38 + ad9371_gpio_12, // 37 + ad9371_gpio_14, // 36 + ad9371_gpio_13, // 35 + ad9371_gpio_17, // 34 + ad9371_gpio_16, // 33 + ad9371_gpio_18})); // 32 + + ad_iobuf #(.DATA_WIDTH(15)) i_iobuf_bd ( + .dio_t (gpio_t[14:0]), + .dio_i (gpio_o[14:0]), + .dio_o (gpio_i[14:0]), + .dio_p (gpio_bd)); + + system_wrapper i_system_wrapper ( + .dac_fifo_bypass (gpio_o[60]), + .ddr3_addr (ddr3_addr), + .ddr3_ba (ddr3_ba), + .ddr3_cas_n (ddr3_cas_n), + .ddr3_ck_n (ddr3_ck_n), + .ddr3_ck_p (ddr3_ck_p), + .ddr3_cke (ddr3_cke), + .ddr3_cs_n (ddr3_cs_n), + .ddr3_dm (ddr3_dm), + .ddr3_dq (ddr3_dq), + .ddr3_dqs_n (ddr3_dqs_n), + .ddr3_dqs_p (ddr3_dqs_p), + .ddr3_odt (ddr3_odt), + .ddr3_ras_n (ddr3_ras_n), + .ddr3_reset_n (ddr3_reset_n), + .ddr3_we_n (ddr3_we_n), + .ddr_addr (ddr_addr), + .ddr_ba (ddr_ba), + .ddr_cas_n (ddr_cas_n), + .ddr_ck_n (ddr_ck_n), + .ddr_ck_p (ddr_ck_p), + .ddr_cke (ddr_cke), + .ddr_cs_n (ddr_cs_n), + .ddr_dm (ddr_dm), + .ddr_dq (ddr_dq), + .ddr_dqs_n (ddr_dqs_n), + .ddr_dqs_p (ddr_dqs_p), + .ddr_odt (ddr_odt), + .ddr_ras_n (ddr_ras_n), + .ddr_reset_n (ddr_reset_n), + .ddr_we_n (ddr_we_n), + .fixed_io_ddr_vrn (fixed_io_ddr_vrn), + .fixed_io_ddr_vrp (fixed_io_ddr_vrp), + .fixed_io_mio (fixed_io_mio), + .fixed_io_ps_clk (fixed_io_ps_clk), + .fixed_io_ps_porb (fixed_io_ps_porb), + .fixed_io_ps_srstb (fixed_io_ps_srstb), + .gpio_i (gpio_i), + .gpio_o (gpio_o), + .gpio_t (gpio_t), + .hdmi_data (hdmi_data), + .hdmi_data_e (hdmi_data_e), + .hdmi_hsync (hdmi_hsync), + .hdmi_out_clk (hdmi_out_clk), + .hdmi_vsync (hdmi_vsync), + .iic_main_scl_io (iic_scl), + .iic_main_sda_io (iic_sda), + .ps_intr_00 (1'b0), + .ps_intr_01 (1'b0), + .ps_intr_02 (1'b0), + .ps_intr_03 (1'b0), + .ps_intr_04 (1'b0), + .ps_intr_05 (1'b0), + .ps_intr_06 (1'b0), + .ps_intr_07 (1'b0), + .ps_intr_08 (1'b0), + .ps_intr_09 (1'b0), + .ps_intr_10 (1'b0), + .rx_data_0_n (rx_data_n[0]), + .rx_data_0_p (rx_data_p[0]), + .rx_data_1_n (rx_data_n[1]), + .rx_data_1_p (rx_data_p[1]), + .rx_data_2_n (rx_data_n[2]), + .rx_data_2_p (rx_data_p[2]), + .rx_data_3_n (rx_data_n[3]), + .rx_data_3_p (rx_data_p[3]), + .rx_ref_clk_0 (ref_clk1), + .rx_ref_clk_2 (ref_clk1), + .rx_sync_0 (rx_sync), + .rx_sync_2 (rx_os_sync), + .rx_sysref_0 (sysref), + .rx_sysref_2 (sysref), + .spdif (spdif), + .spi0_clk_i (spi_clk), + .spi0_clk_o (spi_clk), + .spi0_csn_0_o (spi_csn_ad9528), + .spi0_csn_1_o (spi_csn_ad9371), + .spi0_csn_2_o (), + .spi0_csn_i (1'b1), + .spi0_sdi_i (spi_miso), + .spi0_sdo_i (spi_mosi), + .spi0_sdo_o (spi_mosi), + .spi1_clk_i (1'd0), + .spi1_clk_o (), + .spi1_csn_0_o (), + .spi1_csn_1_o (), + .spi1_csn_2_o (), + .spi1_csn_i (1'b1), + .spi1_sdi_i (1'd0), + .spi1_sdo_i (1'd0), + .spi1_sdo_o (), + .sys_clk_clk_n (sys_clk_n), + .sys_clk_clk_p (sys_clk_p), + .sys_rst(sys_rst), + .tx_data_0_n (tx_data_n[0]), + .tx_data_0_p (tx_data_p[0]), + .tx_data_1_n (tx_data_n[1]), + .tx_data_1_p (tx_data_p[1]), + .tx_data_2_n (tx_data_n[2]), + .tx_data_2_p (tx_data_p[2]), + .tx_data_3_n (tx_data_n[3]), + .tx_data_3_p (tx_data_p[3]), + .tx_ref_clk_0 (ref_clk1), + .tx_sync_0 (tx_sync), + .tx_sysref_0 (sysref)); + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/projects/adv7511/ac701/Makefile b/projects/adv7511/ac701/Makefile index 0dfca3289..a6c78b927 100644 --- a/projects/adv7511/ac701/Makefile +++ b/projects/adv7511/ac701/Makefile @@ -16,7 +16,7 @@ M_DEPS += ../../common/ac701/ac701_system_constr.xdc M_DEPS += ../../common/ac701/ac701_system_bd.tcl M_DEPS += ../../adv7511/common/adv7511_bd.tcl M_DEPS += ../../adv7511/ac701/system_constr.xdc -M_DEPS += ../../../library/common/ad_iobuf.v +M_DEPS += ../../../library/xilinx/common/ad_iobuf.v M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr @@ -35,6 +35,7 @@ M_FLIST += *.sdk M_FLIST += *.hw M_FLIST += *.sim M_FLIST += .Xil +M_FLIST += *.ip_user_files @@ -53,7 +54,7 @@ clean-all:clean adv7511_ac701.sdk/system_top.hdf: $(M_DEPS) - rm -rf $(M_FLIST) + -rm -rf $(M_FLIST) $(M_VIVADO) system_project.tcl >> adv7511_ac701_vivado.log 2>&1 diff --git a/projects/adv7511/ac701/system_project.tcl b/projects/adv7511/ac701/system_project.tcl index 0e7089508..053a42176 100644 --- a/projects/adv7511/ac701/system_project.tcl +++ b/projects/adv7511/ac701/system_project.tcl @@ -6,7 +6,7 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl adi_project_create adv7511_ac701 adi_project_files adv7511_ac701 [list \ "system_top.v" \ - "$ad_hdl_dir/library/common/ad_iobuf.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \ "$ad_hdl_dir/projects/common/ac701/ac701_system_constr.xdc" \ "$ad_hdl_dir/projects/adv7511/ac701/system_constr.xdc"] diff --git a/projects/adv7511/common/adv7511_bd.tcl b/projects/adv7511/common/adv7511_bd.tcl index 51b9c2ab3..d33aadccf 100755 --- a/projects/adv7511/common/adv7511_bd.tcl +++ b/projects/adv7511/common/adv7511_bd.tcl @@ -31,7 +31,7 @@ set_property -dict [list CONFIG.c_include_s2mm {0}] $axi_hdmi_dma # audio peripherals -set sys_audio_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.2 sys_audio_clkgen] +set sys_audio_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.3 sys_audio_clkgen] set_property -dict [list CONFIG.PRIM_IN_FREQ {200.000}] $sys_audio_clkgen set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {12.288}] $sys_audio_clkgen diff --git a/projects/adv7511/kc705/Makefile b/projects/adv7511/kc705/Makefile index 69dea3d47..0700ae64e 100644 --- a/projects/adv7511/kc705/Makefile +++ b/projects/adv7511/kc705/Makefile @@ -16,7 +16,7 @@ M_DEPS += ../../common/kc705/kc705_system_mig.prj M_DEPS += ../../common/kc705/kc705_system_constr.xdc M_DEPS += ../../common/kc705/kc705_system_bd.tcl M_DEPS += ../../adv7511/common/adv7511_bd.tcl -M_DEPS += ../../../library/common/ad_iobuf.v +M_DEPS += ../../../library/xilinx/common/ad_iobuf.v M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr @@ -35,6 +35,7 @@ M_FLIST += *.sdk M_FLIST += *.hw M_FLIST += *.sim M_FLIST += .Xil +M_FLIST += *.ip_user_files @@ -53,7 +54,7 @@ clean-all:clean adv7511_kc705.sdk/system_top.hdf: $(M_DEPS) - rm -rf $(M_FLIST) + -rm -rf $(M_FLIST) $(M_VIVADO) system_project.tcl >> adv7511_kc705_vivado.log 2>&1 diff --git a/projects/adv7511/kc705/system_project.tcl b/projects/adv7511/kc705/system_project.tcl index 848ad356a..134972a38 100755 --- a/projects/adv7511/kc705/system_project.tcl +++ b/projects/adv7511/kc705/system_project.tcl @@ -7,7 +7,7 @@ adi_project_create adv7511_kc705 adi_project_files adv7511_kc705 [list \ "system_top.v" \ "system_constr.xdc"\ - "$ad_hdl_dir/library/common/ad_iobuf.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \ "$ad_hdl_dir/projects/common/kc705/kc705_system_constr.xdc" ] adi_project_run adv7511_kc705 diff --git a/projects/adv7511/kc705/system_top.v b/projects/adv7511/kc705/system_top.v index c5588cfdc..6be7fd3ed 100644 --- a/projects/adv7511/kc705/system_top.v +++ b/projects/adv7511/kc705/system_top.v @@ -223,6 +223,21 @@ module system_top ( .mb_intr_13 (1'b0), .mb_intr_14 (1'b0), .mb_intr_15 (1'b0), + .hdmi_24_data (), + .hdmi_24_data_e (), + .hdmi_24_hsync (), + .hdmi_24_vsync (), + .hdmi_36_data (), + .hdmi_36_data_e (), + .hdmi_36_hsync (), + .hdmi_36_vsync (), + .spi_clk_i (1'b0), + .spi_clk_o (), + .spi_csn_i (1'b0), + .spi_csn_o (), + .spi_sdi_i (1'b0), + .spi_sdo_i (1'b0), + .spi_sdo_o (), .mdio_mdc (mdio_mdc), .mdio_mdio_io (mdio_mdio), .mii_col (mii_col), diff --git a/projects/adv7511/kcu105/Makefile b/projects/adv7511/kcu105/Makefile index 9a09b9f4f..edaf81d6a 100644 --- a/projects/adv7511/kcu105/Makefile +++ b/projects/adv7511/kcu105/Makefile @@ -13,10 +13,9 @@ M_DEPS += ../common/adv7511_bd.tcl M_DEPS += ../../scripts/adi_project.tcl M_DEPS += ../../scripts/adi_env.tcl M_DEPS += ../../scripts/adi_board.tcl -M_DEPS += ../../common/kcu105/kcu105_system_mig.tcl M_DEPS += ../../common/kcu105/kcu105_system_constr.xdc M_DEPS += ../../common/kcu105/kcu105_system_bd.tcl -M_DEPS += ../../../library/common/ad_iobuf.v +M_DEPS += ../../../library/xilinx/common/ad_iobuf.v M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr @@ -35,6 +34,7 @@ M_FLIST += *.sdk M_FLIST += *.hw M_FLIST += *.sim M_FLIST += .Xil +M_FLIST += *.ip_user_files @@ -53,7 +53,7 @@ clean-all:clean adv7511_kcu105.sdk/system_top.hdf: $(M_DEPS) - rm -rf $(M_FLIST) + -rm -rf $(M_FLIST) $(M_VIVADO) system_project.tcl >> adv7511_kcu105_vivado.log 2>&1 diff --git a/projects/adv7511/kcu105/system_project.tcl b/projects/adv7511/kcu105/system_project.tcl index b66326b79..46799e383 100644 --- a/projects/adv7511/kcu105/system_project.tcl +++ b/projects/adv7511/kcu105/system_project.tcl @@ -7,7 +7,7 @@ adi_project_create adv7511_kcu105 adi_project_files adv7511_kcu105 [list \ "system_top.v" \ "system_constr.xdc"\ - "$ad_hdl_dir/library/common/ad_iobuf.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \ "$ad_hdl_dir/projects/common/kcu105/kcu105_system_constr.xdc" ] set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/kcu105/kcu105_system_constr.xdc] diff --git a/projects/adv7511/kcu105/system_top.v b/projects/adv7511/kcu105/system_top.v index cd7993914..751017452 100644 --- a/projects/adv7511/kcu105/system_top.v +++ b/projects/adv7511/kcu105/system_top.v @@ -144,6 +144,7 @@ module system_top ( // default logic assign fan_pwm = 1'b1; + assign gpio_i[63:17] = gpio_o[63:17]; // instantiations @@ -195,6 +196,13 @@ module system_top ( .mb_intr_13 (1'b0), .mb_intr_14 (1'b0), .mb_intr_15 (1'b0), + .spi_clk_i (1'b0), + .spi_clk_o (), + .spi_csn_i (1'b1), + .spi_csn_o (), + .spi_sdi_i (1'b0), + .spi_sdo_i (1'b0), + .spi_sdo_o (), .mdio_mdc (mdio_mdc), .mdio_mdio_io (mdio_mdio), .phy_clk_clk_n (phy_clk_n), diff --git a/projects/adv7511/mitx045/Makefile b/projects/adv7511/mitx045/Makefile index 80c65e379..20e6df52c 100644 --- a/projects/adv7511/mitx045/Makefile +++ b/projects/adv7511/mitx045/Makefile @@ -14,7 +14,7 @@ M_DEPS += ../../scripts/adi_board.tcl M_DEPS += ../../common/mitx045/mitx045_system_ps7.tcl M_DEPS += ../../common/mitx045/mitx045_system_constr.xdc M_DEPS += ../../common/mitx045/mitx045_system_bd.tcl -M_DEPS += ../../../library/common/ad_iobuf.v +M_DEPS += ../../../library/xilinx/common/ad_iobuf.v M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr M_DEPS += ../../../library/axi_i2s_adi/axi_i2s_adi.xpr @@ -34,6 +34,7 @@ M_FLIST += *.sdk M_FLIST += *.hw M_FLIST += *.sim M_FLIST += .Xil +M_FLIST += *.ip_user_files @@ -53,7 +54,7 @@ clean-all:clean adv7511_mitx045.sdk/system_top.hdf: $(M_DEPS) - rm -rf $(M_FLIST) + -rm -rf $(M_FLIST) $(M_VIVADO) system_project.tcl >> adv7511_mitx045_vivado.log 2>&1 diff --git a/projects/adv7511/mitx045/system_project.tcl b/projects/adv7511/mitx045/system_project.tcl index c6c812573..cb94ecb7d 100755 --- a/projects/adv7511/mitx045/system_project.tcl +++ b/projects/adv7511/mitx045/system_project.tcl @@ -6,7 +6,7 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl adi_project_create adv7511_mitx045 adi_project_files adv7511_mitx045 [list \ "system_top.v" \ - "$ad_hdl_dir/library/common/ad_iobuf.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \ "$ad_hdl_dir/projects/common/mitx045/mitx045_system_constr.xdc"] adi_project_run adv7511_mitx045 diff --git a/projects/adv7511/vc707/Makefile b/projects/adv7511/vc707/Makefile index b347dcd33..01f33d999 100644 --- a/projects/adv7511/vc707/Makefile +++ b/projects/adv7511/vc707/Makefile @@ -16,7 +16,7 @@ M_DEPS += ../../common/vc707/vc707_system_constr.xdc M_DEPS += ../../common/vc707/vc707_system_bd.tcl M_DEPS += ../../adv7511/vc707/system_constr.xdc M_DEPS += ../../adv7511/common/adv7511_bd.tcl -M_DEPS += ../../../library/common/ad_iobuf.v +M_DEPS += ../../../library/xilinx/common/ad_iobuf.v M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr @@ -35,6 +35,7 @@ M_FLIST += *.sdk M_FLIST += *.hw M_FLIST += *.sim M_FLIST += .Xil +M_FLIST += *.ip_user_files @@ -53,7 +54,7 @@ clean-all:clean adv7511_vc707.sdk/system_top.hdf: $(M_DEPS) - rm -rf $(M_FLIST) + -rm -rf $(M_FLIST) $(M_VIVADO) system_project.tcl >> adv7511_vc707_vivado.log 2>&1 diff --git a/projects/adv7511/vc707/system_project.tcl b/projects/adv7511/vc707/system_project.tcl index 90ce54fda..f1564ded2 100644 --- a/projects/adv7511/vc707/system_project.tcl +++ b/projects/adv7511/vc707/system_project.tcl @@ -5,7 +5,7 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl adi_project_create adv7511_vc707 adi_project_files adv7511_vc707 [list \ - "$ad_hdl_dir/library/common/ad_iobuf.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \ "system_top.v" \ "$ad_hdl_dir/projects/common/vc707/vc707_system_constr.xdc" \ "$ad_hdl_dir/projects/adv7511/vc707/system_constr.xdc"] diff --git a/projects/adv7511/zc702/Makefile b/projects/adv7511/zc702/Makefile index 876158ecd..71f192a50 100644 --- a/projects/adv7511/zc702/Makefile +++ b/projects/adv7511/zc702/Makefile @@ -13,7 +13,7 @@ M_DEPS += ../../scripts/adi_env.tcl M_DEPS += ../../scripts/adi_board.tcl M_DEPS += ../../common/zc702/zc702_system_constr.xdc M_DEPS += ../../common/zc702/zc702_system_bd.tcl -M_DEPS += ../../../library/common/ad_iobuf.v +M_DEPS += ../../../library/xilinx/common/ad_iobuf.v M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr @@ -32,6 +32,7 @@ M_FLIST += *.sdk M_FLIST += *.hw M_FLIST += *.sim M_FLIST += .Xil +M_FLIST += *.ip_user_files @@ -50,7 +51,7 @@ clean-all:clean adv7511_zc702.sdk/system_top.hdf: $(M_DEPS) - rm -rf $(M_FLIST) + -rm -rf $(M_FLIST) $(M_VIVADO) system_project.tcl >> adv7511_zc702_vivado.log 2>&1 diff --git a/projects/adv7511/zc702/system_project.tcl b/projects/adv7511/zc702/system_project.tcl index 1f20c8ff0..01a7677c5 100644 --- a/projects/adv7511/zc702/system_project.tcl +++ b/projects/adv7511/zc702/system_project.tcl @@ -7,7 +7,7 @@ adi_project_create adv7511_zc702 adi_project_files adv7511_zc702 [list \ "system_top.v" \ "$ad_hdl_dir/projects/common/zc702/zc702_system_constr.xdc" \ - "$ad_hdl_dir/library/common/ad_iobuf.v" ] + "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" ] adi_project_run adv7511_zc702 diff --git a/projects/adv7511/zc706/Makefile b/projects/adv7511/zc706/Makefile index d00baa5e9..65085d55b 100644 --- a/projects/adv7511/zc706/Makefile +++ b/projects/adv7511/zc706/Makefile @@ -13,7 +13,7 @@ M_DEPS += ../../scripts/adi_env.tcl M_DEPS += ../../scripts/adi_board.tcl M_DEPS += ../../common/zc706/zc706_system_constr.xdc M_DEPS += ../../common/zc706/zc706_system_bd.tcl -M_DEPS += ../../../library/common/ad_iobuf.v +M_DEPS += ../../../library/xilinx/common/ad_iobuf.v M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr @@ -32,6 +32,7 @@ M_FLIST += *.sdk M_FLIST += *.hw M_FLIST += *.sim M_FLIST += .Xil +M_FLIST += *.ip_user_files @@ -50,7 +51,7 @@ clean-all:clean adv7511_zc706.sdk/system_top.hdf: $(M_DEPS) - rm -rf $(M_FLIST) + -rm -rf $(M_FLIST) $(M_VIVADO) system_project.tcl >> adv7511_zc706_vivado.log 2>&1 diff --git a/projects/adv7511/zc706/system_project.tcl b/projects/adv7511/zc706/system_project.tcl index ffcd1819f..66167473f 100644 --- a/projects/adv7511/zc706/system_project.tcl +++ b/projects/adv7511/zc706/system_project.tcl @@ -7,7 +7,7 @@ adi_project_create adv7511_zc706 adi_project_files adv7511_zc706 [list \ "system_top.v" \ "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" \ - "$ad_hdl_dir/library/common/ad_iobuf.v"] + "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v"] adi_project_run adv7511_zc706 diff --git a/projects/adv7511/zed/Makefile b/projects/adv7511/zed/Makefile index 26d233c0b..d5f12056a 100644 --- a/projects/adv7511/zed/Makefile +++ b/projects/adv7511/zed/Makefile @@ -13,7 +13,7 @@ M_DEPS += ../../scripts/adi_env.tcl M_DEPS += ../../scripts/adi_board.tcl M_DEPS += ../../common/zed/zed_system_constr.xdc M_DEPS += ../../common/zed/zed_system_bd.tcl -M_DEPS += ../../../library/common/ad_iobuf.v +M_DEPS += ../../../library/xilinx/common/ad_iobuf.v M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr M_DEPS += ../../../library/axi_i2s_adi/axi_i2s_adi.xpr @@ -34,6 +34,7 @@ M_FLIST += *.sdk M_FLIST += *.hw M_FLIST += *.sim M_FLIST += .Xil +M_FLIST += *.ip_user_files @@ -54,7 +55,7 @@ clean-all:clean adv7511_zed.sdk/system_top.hdf: $(M_DEPS) - rm -rf $(M_FLIST) + -rm -rf $(M_FLIST) $(M_VIVADO) system_project.tcl >> adv7511_zed_vivado.log 2>&1 diff --git a/projects/adv7511/zed/system_project.tcl b/projects/adv7511/zed/system_project.tcl index a18cd7bf5..fc46b54e4 100644 --- a/projects/adv7511/zed/system_project.tcl +++ b/projects/adv7511/zed/system_project.tcl @@ -9,7 +9,7 @@ adi_project_create adv7511_zed adi_project_files adv7511_zed [list \ "system_top.v" \ "$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc" \ - "$ad_hdl_dir/library/common/ad_iobuf.v"] + "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v"] adi_project_run adv7511_zed diff --git a/projects/adv7511/zed/system_top.v b/projects/adv7511/zed/system_top.v index c0514e529..67f4c72c8 100644 --- a/projects/adv7511/zed/system_top.v +++ b/projects/adv7511/zed/system_top.v @@ -146,6 +146,8 @@ module system_top ( wire [ 1:0] iic_mux_sda_o_s; wire iic_mux_sda_t_s; + assign gpio_i[63:32] = gpio_o[63:32]; + // instantiations ad_iobuf #( @@ -229,7 +231,25 @@ module system_top ( .ps_intr_12 (1'b0), .ps_intr_13 (1'b0), .otg_vbusoc (otg_vbusoc), - .spdif (spdif)); + .spdif (spdif), + .spi0_clk_i (1'b0), + .spi0_clk_o (), + .spi0_csn_0_o (), + .spi0_csn_1_o (), + .spi0_csn_2_o (), + .spi0_csn_i (1'b1), + .spi0_sdi_i (1'b0), + .spi0_sdo_i (1'b0), + .spi0_sdo_o (), + .spi1_clk_i (1'b0), + .spi1_clk_o (), + .spi1_csn_0_o (), + .spi1_csn_1_o (), + .spi1_csn_2_o (), + .spi1_csn_i (1'b1), + .spi1_sdi_i (1'b0), + .spi1_sdo_i (1'b0), + .spi1_sdo_o ()); endmodule diff --git a/projects/arradio/c5soc/Makefile b/projects/arradio/c5soc/Makefile index 336822c5b..1fbc2a606 100644 --- a/projects/arradio/c5soc/Makefile +++ b/projects/arradio/c5soc/Makefile @@ -13,11 +13,11 @@ M_DEPS += ../common/arradio_bd.qsys M_DEPS += ../../scripts/adi_env.tcl M_DEPS += ../../common/c5soc/c5soc_system_bd.qsys M_DEPS += ../../common/c5soc/c5soc_system_assign.tcl -M_DEPS += ../../../library/common/ad_iobuf.v +M_DEPS += ../../../library/xilinx/common/ad_iobuf.v M_DEPS += ../../../library/axi_ad9361/axi_ad9361.v -M_DEPS += ../../../library/axi_ad9361/axi_ad9361_alt_lvds_rx.v -M_DEPS += ../../../library/axi_ad9361/axi_ad9361_alt_lvds_tx.v -M_DEPS += ../../../library/axi_ad9361/axi_ad9361_dev_if_alt.v +M_DEPS += ../../../library/axi_ad9361/altera/axi_ad9361_alt_lvds_rx.v +M_DEPS += ../../../library/axi_ad9361/altera/axi_ad9361_alt_lvds_tx.v +M_DEPS += ../../../library/axi_ad9361/altera/axi_ad9361_lvds_if.v M_DEPS += ../../../library/axi_ad9361/axi_ad9361_hw.tcl M_DEPS += ../../../library/axi_ad9361/axi_ad9361_rx.v M_DEPS += ../../../library/axi_ad9361/axi_ad9361_rx_channel.v @@ -52,15 +52,10 @@ M_DEPS += ../../../library/common/ad_dds.v M_DEPS += ../../../library/common/ad_dds_1.v M_DEPS += ../../../library/common/ad_dds_sine.v M_DEPS += ../../../library/common/ad_iqcor.v -M_DEPS += ../../../library/common/ad_mul.v +M_DEPS += ../../../library/altera/common/ad_mul.v M_DEPS += ../../../library/common/ad_pnmon.v M_DEPS += ../../../library/common/ad_rst.v M_DEPS += ../../../library/common/ad_tdd_control.v -M_DEPS += ../../../library/common/altera/DSP48E1.v -M_DEPS += ../../../library/common/altera/MULT_MACRO.v -M_DEPS += ../../../library/common/altera/ad_lvds_clk.v -M_DEPS += ../../../library/common/altera/ad_lvds_in.v -M_DEPS += ../../../library/common/altera/ad_lvds_out.v M_DEPS += ../../../library/common/sync_bits.v M_DEPS += ../../../library/common/sync_gray.v M_DEPS += ../../../library/common/up_adc_channel.v diff --git a/projects/arradio/c5soc/system_bd.qsys b/projects/arradio/c5soc/system_bd.qsys old mode 100644 new mode 100755 index ff3917be9..7f5780e09 --- a/projects/arradio/c5soc/system_bd.qsys +++ b/projects/arradio/c5soc/system_bd.qsys @@ -168,9 +168,7 @@ + internal="arradio.axi_ad9361_device_clock" /> - - - ]]> - + - - + + - + $${FILENAME}_arradio @@ -277,20 +272,20 @@ - + - + ]]> - + - + - + @@ -298,7 +293,7 @@ @@ -307,7 +302,7 @@ @@ -316,7 +311,7 @@ @@ -325,7 +320,7 @@ @@ -334,7 +329,7 @@ @@ -343,7 +338,7 @@ @@ -352,54 +347,54 @@ - - + + diff --git a/projects/arradio/c5soc/system_top.v b/projects/arradio/c5soc/system_top.v index 47f5af1f2..183359e50 100644 --- a/projects/arradio/c5soc/system_top.v +++ b/projects/arradio/c5soc/system_top.v @@ -436,7 +436,6 @@ ALT_IOBUF sda_iobuf (.i(1'b0), .oe(i2c0_out_data), .o(i2c0_sda), .io(sda)); // .sys_hps_spim0_ss_2_n (), .sys_hps_spim0_ss_3_n (), .sys_hps_spim0_sclk_out_clk (), - .axi_ad9361_device_clock_clk (clk), .axi_ad9361_device_if_rx_clk_in_p (rx_clk_in), .axi_ad9361_device_if_rx_clk_in_n (1'b0), .axi_ad9361_device_if_rx_frame_in_p (rx_frame_in), diff --git a/projects/arradio/common/arradio_bd.qsys b/projects/arradio/common/arradio_bd.qsys index 52bcd0e88..b3e2d51e0 100755 --- a/projects/arradio/common/arradio_bd.qsys +++ b/projects/arradio/common/arradio_bd.qsys @@ -252,11 +252,7 @@ - + @@ -349,8 +345,23 @@ + + + + + + + + + + + + + + + @@ -390,7 +401,7 @@ - + @@ -404,19 +415,19 @@ - + - + - + @@ -432,12 +443,12 @@ - + - + @@ -446,70 +457,75 @@ + - + + end="axi_ad9361.if_delay_clk" /> + version="16.0" + start="adc_pack.adc_ch_0" + end="axi_ad9361.adc_ch_0"> @@ -518,9 +534,9 @@ + version="16.0" + start="axi_ad9361.adc_ch_1" + end="adc_pack.adc_ch_1"> @@ -529,9 +545,9 @@ + version="16.0" + start="axi_ad9361.adc_ch_2" + end="adc_pack.adc_ch_2"> @@ -540,9 +556,9 @@ + version="16.0" + start="adc_pack.adc_ch_3" + end="axi_ad9361.adc_ch_3"> @@ -551,9 +567,9 @@ + version="16.0" + start="axi_ad9361.dac_ch_0" + end="dac_upack.dac_ch_0"> @@ -562,9 +578,9 @@ + version="16.0" + start="dac_upack.dac_ch_1" + end="axi_ad9361.dac_ch_1"> @@ -573,9 +589,9 @@ + version="16.0" + start="axi_ad9361.dac_ch_2" + end="dac_upack.dac_ch_2"> @@ -584,9 +600,9 @@ + version="16.0" + start="dac_upack.dac_ch_3" + end="axi_ad9361.dac_ch_3"> @@ -595,7 +611,7 @@ @@ -606,7 +622,7 @@ @@ -617,7 +633,7 @@ @@ -628,7 +644,7 @@ @@ -639,7 +655,7 @@ @@ -650,7 +666,7 @@ @@ -661,7 +677,7 @@ @@ -672,7 +688,7 @@ @@ -683,52 +699,52 @@ diff --git a/projects/cftl_cip/zed/Makefile b/projects/cftl_cip/zed/Makefile index 687b6a0e0..fbd23dc41 100644 --- a/projects/cftl_cip/zed/Makefile +++ b/projects/cftl_cip/zed/Makefile @@ -15,7 +15,7 @@ M_DEPS += ../../scripts/adi_env.tcl M_DEPS += ../../scripts/adi_board.tcl M_DEPS += ../../common/zed/zed_system_constr.xdc M_DEPS += ../../common/zed/zed_system_bd.tcl -M_DEPS += ../../../library/common/ad_iobuf.v +M_DEPS += ../../../library/xilinx/common/ad_iobuf.v M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr @@ -39,6 +39,7 @@ M_FLIST += *.sdk M_FLIST += *.hw M_FLIST += *.sim M_FLIST += .Xil +M_FLIST += *.ip_user_files @@ -62,7 +63,7 @@ clean-all:clean cftl_custom_zed.sdk/system_top.hdf: $(M_DEPS) - rm -rf $(M_FLIST) + -rm -rf $(M_FLIST) $(M_VIVADO) system_project.tcl >> cftl_custom_zed_vivado.log 2>&1 diff --git a/projects/cftl_cip/zed/system_project.tcl b/projects/cftl_cip/zed/system_project.tcl index 7fd75f90c..7f66bf329 100644 --- a/projects/cftl_cip/zed/system_project.tcl +++ b/projects/cftl_cip/zed/system_project.tcl @@ -16,7 +16,7 @@ adi_project_files cftl_custom_zed [list \ "system_top.v" \ "system_constr.xdc" \ "$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc" \ - "$ad_hdl_dir/library/common/ad_iobuf.v"] + "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v"] adi_project_run cftl_custom_zed diff --git a/projects/cftl_std/zed/Makefile b/projects/cftl_std/zed/Makefile index 55923a3eb..7b2f85d78 100644 --- a/projects/cftl_std/zed/Makefile +++ b/projects/cftl_std/zed/Makefile @@ -15,7 +15,7 @@ M_DEPS += ../../scripts/adi_env.tcl M_DEPS += ../../scripts/adi_board.tcl M_DEPS += ../../common/zed/zed_system_constr.xdc M_DEPS += ../../common/zed/zed_system_bd.tcl -M_DEPS += ../../../library/common/ad_iobuf.v +M_DEPS += ../../../library/xilinx/common/ad_iobuf.v M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr M_DEPS += ../../../library/axi_i2s_adi/axi_i2s_adi.xpr @@ -36,6 +36,7 @@ M_FLIST += *.sdk M_FLIST += *.hw M_FLIST += *.sim M_FLIST += .Xil +M_FLIST += *.ip_user_files @@ -56,7 +57,7 @@ clean-all:clean cftl_std_zed.sdk/system_top.hdf: $(M_DEPS) - rm -rf $(M_FLIST) + -rm -rf $(M_FLIST) $(M_VIVADO) system_project.tcl >> cftl_std_zed_vivado.log 2>&1 diff --git a/projects/cftl_std/zed/system_project.tcl b/projects/cftl_std/zed/system_project.tcl index 8967736a9..f33858eef 100644 --- a/projects/cftl_std/zed/system_project.tcl +++ b/projects/cftl_std/zed/system_project.tcl @@ -7,7 +7,7 @@ adi_project_create cftl_std_zed adi_project_files cftl_std_zed [list \ "system_top.v" \ "system_constr.xdc" \ - "$ad_hdl_dir/library/common/ad_iobuf.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \ "$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc" ] adi_project_run cftl_std_zed diff --git a/projects/cn0363/Makefile b/projects/cn0363/Makefile index 141f88d2a..da85fadb8 100644 --- a/projects/cn0363/Makefile +++ b/projects/cn0363/Makefile @@ -7,14 +7,17 @@ .PHONY: all clean clean-all all: + -make -C microzed all -make -C zed all clean: + make -C microzed clean make -C zed clean clean-all: + make -C microzed clean-all make -C zed clean-all #################################################################################### diff --git a/projects/cn0363/common/cn0363_bd.tcl b/projects/cn0363/common/cn0363_bd.tcl new file mode 100644 index 000000000..ac70789a5 --- /dev/null +++ b/projects/cn0363/common/cn0363_bd.tcl @@ -0,0 +1,294 @@ +proc load_fir_filter_vector {filter_file} { + set fp [open $filter_file r] + set data [split [read $fp] "\n"] + set filter "" + close $fp + foreach line $data { + set line [string trim $line] + if {[string equal -length 1 $line "#"] || $line eq ""} { + continue + } + if {$filter ne ""} { + append filter "," + } + append filter $line + } + + return $filter +} + +set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_IO {35}] $sys_ps7 + +set_property LEFT 34 [get_bd_ports GPIO_I] +set_property LEFT 34 [get_bd_ports GPIO_O] +set_property LEFT 34 [get_bd_ports GPIO_T] + +set axi_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_dma] +set_property -dict [list \ + CONFIG.FIFO_SIZE 2 \ + CONFIG.DMA_TYPE_SRC 2 \ + CONFIG.DMA_TYPE_DEST 0 \ + CONFIG.CYCLIC 0 \ + CONFIG.SYNC_TRANSFER_START 1 \ + CONFIG.AXI_SLICE_SRC 0 \ + CONFIG.AXI_SLICE_DEST 0 \ + CONFIG.DMA_2D_TRANSFER 0 \ + CONFIG.DMA_DATA_WIDTH_SRC 32 \ + CONFIG.DMA_DATA_WIDTH_DEST 64 \ + CONFIG.DMA_AXI_PROTOCOL_DEST 1 \ + ] $axi_dma + +# Create SPI engine controller with offload +create_bd_cell -type hier spi +current_bd_instance /spi + + create_bd_pin -dir I -type clk clk + create_bd_pin -dir I -type rst resetn + create_bd_pin -dir O conv_done + create_bd_pin -dir O irq + create_bd_intf_pin -mode Master -vlnv analog.com:interface:spi_master_rtl:1.0 m_spi + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 M_AXIS_SAMPLE + + set spi_engine [create_bd_cell -type ip -vlnv analog.com:user:spi_engine_execution:1.0 execution] + set axi_spi_engine [create_bd_cell -type ip -vlnv analog.com:user:axi_spi_engine:1.0 axi] + set spi_engine_offload [create_bd_cell -type ip -vlnv analog.com:user:spi_engine_offload:1.0 offload] + set spi_engine_interconnect [create_bd_cell -type ip -vlnv analog.com:user:spi_engine_interconnect:1.0 interconnect] + set util_sigma_delta_spi [create_bd_cell -type ip -vlnv analog.com:user:util_sigma_delta_spi:1.0 util_sigma_delta_spi] + + set_property -dict [list CONFIG.NUM_OF_CS 2] $spi_engine + + set_property -dict [list CONFIG.NUM_OF_CS 2] $util_sigma_delta_spi + + ad_connect axi/spi_engine_offload_ctrl0 offload/spi_engine_offload_ctrl + ad_connect offload/spi_engine_ctrl interconnect/s0_ctrl + ad_connect axi/spi_engine_ctrl interconnect/s1_ctrl + ad_connect interconnect/m_ctrl execution/ctrl + ad_connect offload/offload_sdi M_AXIS_SAMPLE + + ad_connect util_sigma_delta_spi/data_ready offload/trigger + ad_connect util_sigma_delta_spi/data_ready conv_done + + ad_connect execution/active util_sigma_delta_spi/spi_active + ad_connect execution/spi util_sigma_delta_spi/s_spi + ad_connect util_sigma_delta_spi/m_spi m_spi + + connect_bd_net \ + [get_bd_pins clk] \ + [get_bd_pins offload/spi_clk] \ + [get_bd_pins offload/ctrl_clk] \ + [get_bd_pins execution/clk] \ + [get_bd_pins axi/s_axi_aclk] \ + [get_bd_pins axi/spi_clk] \ + [get_bd_pins interconnect/clk] \ + [get_bd_pins util_sigma_delta_spi/clk] + + connect_bd_net \ + [get_bd_pins axi/spi_resetn] \ + [get_bd_pins offload/spi_resetn] \ + [get_bd_pins execution/resetn] \ + [get_bd_pins interconnect/resetn] \ + [get_bd_pins util_sigma_delta_spi/resetn] + + connect_bd_net [get_bd_pins resetn] [get_bd_pins axi/s_axi_aresetn] + ad_connect irq axi/irq + +current_bd_instance / + +create_bd_intf_port -mode Master -vlnv analog.com:interface:spi_master_rtl:1.0 spi +ad_connect spi/m_spi spi + +set phase_gen [create_bd_cell -type ip -vlnv xilinx.com:ip:c_counter_binary:12.0 phase_gen] +set phase_slice [create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 phase_slice] +create_bd_port -dir O excitation + +set excitation_freq 1020 + +set_property -dict [list \ + CONFIG.Output_Width 32 \ + CONFIG.Increment_Value [format "%x" [expr $excitation_freq * (1<<32) / 100000000]] \ + ] $phase_gen + +set_property -dict [list \ + CONFIG.DIN_TO {31} \ + CONFIG.DIN_FROM {31} \ + CONFIG.DOUT_WIDTH {1} \ + ] $phase_slice + +ad_connect /phase_gen/Q /phase_slice/Din +ad_connect /phase_slice/Dout excitation + +create_bd_cell -type hier processing +current_bd_instance /processing + + create_bd_pin -dir I -type clk clk + create_bd_pin -dir I -type rst resetn + create_bd_pin -dir I conv_done + create_bd_pin -dir I -from 31 -to 0 phase + create_bd_pin -dir O overflow + create_bd_pin -dir I -from 13 -to 0 channel_enable + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 S_AXIS_SAMPLE + create_bd_intf_pin -mode Master -vlnv analog.com:interface:fifo_wr_rtl:1.0 DMA_WR + + create_bd_cell -type ip -vlnv analog.com:user:cn0363_phase_data_sync:1.0 phase_data_sync + create_bd_cell -type ip -vlnv analog.com:user:cn0363_dma_sequencer:1.0 sequencer + create_bd_cell -type ip -vlnv analog.com:user:cordic_demod:1.0 cordic_demod + + create_bd_cell -type ip -vlnv xilinx.com:ip:axis_broadcaster:1.1 phase_broadcast + create_bd_cell -type ip -vlnv xilinx.com:ip:axis_broadcaster:1.1 sample_broadcast + create_bd_cell -type ip -vlnv xilinx.com:ip:axis_broadcaster:1.1 sample_filtered_broadcast + create_bd_cell -type ip -vlnv xilinx.com:ip:axis_broadcaster:1.1 i_q_broadcast + create_bd_cell -type ip -vlnv xilinx.com:ip:axis_combiner:1.1 phase_sample_combine + set i_q_resize [create_bd_cell -type ip -vlnv analog.com:user:util_axis_resize:1.0 i_q_resize] + + set_property -dict [list \ + CONFIG.MASTER_DATA_WIDTH 32 \ + CONFIG.SLAVE_DATA_WIDTH 64 \ + ] $i_q_resize + + set hpf [create_bd_cell -type ip -vlnv xilinx.com:ip:fir_compiler:7.2 hpf] + set lpf [create_bd_cell -type ip -vlnv xilinx.com:ip:fir_compiler:7.2 lpf] + + set_property -dict [list \ + CONFIG.Data_Fractional_Bits.VALUE_SRC USER \ + CONFIG.Data_Sign.VALUE_SRC USER \ + CONFIG.Data_Width.VALUE_SRC USER \ + CONFIG.M_DATA_Has_TREADY true \ + CONFIG.Number_Channels 2 \ + CONFIG.Sample_Frequency 0.025 \ + CONFIG.Clock_Frequency 100 \ + CONFIG.Coefficient_Width 16 \ + CONFIG.Data_Width 24 \ + CONFIG.Output_Width 32 \ + CONFIG.Output_Rounding_Mode Truncate_LSBs \ + CONFIG.Has_ARESETn true \ + CONFIG.Reset_Data_Vector false \ + CONFIG.CoefficientVector [load_fir_filter_vector "../common/filters/hpf.mat"] \ + ] $hpf + + set_property -dict [list \ + CONFIG.Data_Fractional_Bits.VALUE_SRC USER \ + CONFIG.Data_Sign.VALUE_SRC USER \ + CONFIG.Data_Width.VALUE_SRC USER \ + CONFIG.M_DATA_Has_TREADY true \ + CONFIG.Number_Channels 4 \ + CONFIG.Sample_Frequency 0.025 \ + CONFIG.Clock_Frequency 100 \ + CONFIG.Coefficient_Width 24 \ + CONFIG.Data_Width 32 \ + CONFIG.Output_Width 32 \ + CONFIG.Output_Rounding_Mode Truncate_LSBs \ + CONFIG.Has_ARESETn true \ + CONFIG.Reset_Data_Vector false \ + CONFIG.CoefficientVector [load_fir_filter_vector "../common/filters/lpf.mat"] \ + ] $lpf + + set overflow_or [create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 overflow_or] + set_property -dict [list \ + CONFIG.C_SIZE 1 \ + CONFIG.C_OPERATION {or} \ + ] $overflow_or + + ad_connect S_AXIS_SAMPLE phase_data_sync/S_AXIS_SAMPLE + ad_connect conv_done phase_data_sync/conv_done + ad_connect phase phase_data_sync/phase + + ad_connect phase_data_sync/M_AXIS_PHASE phase_broadcast/S_AXIS + ad_connect phase_broadcast/M00_AXIS sequencer/phase + ad_connect phase_broadcast/M01_AXIS phase_sample_combine/S01_AXIS + + ad_connect phase_data_sync/M_AXIS_SAMPLE sample_broadcast/S_AXIS + ad_connect sample_broadcast/M00_AXIS sequencer/data + ad_connect sample_broadcast/M01_AXIS hpf/S_AXIS_DATA + + ad_connect hpf/M_AXIS_DATA sample_filtered_broadcast/S_AXIS + ad_connect sample_filtered_broadcast/M00_AXIS sequencer/data_filtered + ad_connect sample_filtered_broadcast/M01_AXIS phase_sample_combine/S00_AXIS + + ad_connect phase_sample_combine/M_AXIS cordic_demod/S_AXIS + ad_connect cordic_demod/M_AXIS i_q_resize/s_axis + + ad_connect i_q_resize/m_axis i_q_broadcast/S_AXIS + ad_connect i_q_broadcast/M00_AXIS sequencer/i_q + ad_connect i_q_broadcast/M01_AXIS lpf/S_AXIS_DATA + + ad_connect lpf/M_AXIS_DATA sequencer/i_q_filtered + + connect_bd_net \ + [get_bd_pins clk] \ + [get_bd_pins phase_data_sync/clk] \ + [get_bd_pins sequencer/clk] \ + [get_bd_pins cordic_demod/clk] \ + [get_bd_pins phase_broadcast/aclk] \ + [get_bd_pins sample_broadcast/aclk] \ + [get_bd_pins sample_filtered_broadcast/aclk] \ + [get_bd_pins i_q_broadcast/aclk] \ + [get_bd_pins phase_sample_combine/aclk] \ + [get_bd_pins i_q_resize/clk] \ + [get_bd_pins hpf/aclk] \ + [get_bd_pins lpf/aclk] + + connect_bd_net \ + [get_bd_pins resetn] \ + [get_bd_pins sequencer/resetn] \ + [get_bd_pins phase_data_sync/resetn] \ + + connect_bd_net \ + [get_bd_pins sequencer/processing_resetn] \ + [get_bd_pins phase_data_sync/processing_resetn] \ + [get_bd_pins cordic_demod/resetn] \ + [get_bd_pins phase_broadcast/aresetn] \ + [get_bd_pins sample_broadcast/aresetn] \ + [get_bd_pins sample_filtered_broadcast/aresetn] \ + [get_bd_pins i_q_broadcast/aresetn] \ + [get_bd_pins phase_sample_combine/aresetn] \ + [get_bd_pins i_q_resize/resetn] \ + [get_bd_pins hpf/aresetn] \ + [get_bd_pins lpf/aresetn] + + ad_connect channel_enable sequencer/channel_enable + ad_connect sequencer/dma_wr DMA_WR + + ad_connect phase_data_sync/overflow overflow_or/Op1 + ad_connect sequencer/overflow overflow_or/Op2 + ad_connect overflow_or/Res overflow + + ad_connect phase_data_sync/sample_has_stat GND + +current_bd_instance / + +ad_connect /spi/M_AXIS_SAMPLE /processing/S_AXIS_SAMPLE +ad_connect /spi/conv_done /processing/conv_done +ad_connect /phase_gen/Q /processing/phase + +set axi_adc [create_bd_cell -type ip -vlnv analog.com:user:axi_generic_adc:1.0 axi_adc] +set_property -dict [list \ + CONFIG.NUM_OF_CHANNELS 14 \ + ] $axi_adc + +ad_connect processing/overflow axi_adc/adc_dovf +ad_connect axi_adc/adc_enable processing/channel_enable + +connect_bd_net -net sys_cpu_clk \ + [get_bd_pins /spi/clk] \ + [get_bd_pins /processing/clk] \ + [get_bd_pins /axi_dma/m_dest_axi_aclk] \ + [get_bd_pins /axi_dma/fifo_wr_clk] \ + [get_bd_pins /phase_gen/CLK] \ + [get_bd_pins /axi_adc/adc_clk] + +connect_bd_net -net sys_cpu_resetn \ + [get_bd_pins /spi/resetn] \ + [get_bd_pins /processing/resetn] \ + [get_bd_pins /axi_dma/m_dest_axi_aresetn] + +ad_connect /processing/dma_wr /axi_dma/fifo_wr + +ad_cpu_interconnect 0x43c00000 /axi_adc +ad_cpu_interconnect 0x44a00000 /spi/axi +ad_cpu_interconnect 0x44a30000 /axi_dma + +ad_cpu_interrupt "ps-13" "mb-13" /axi_dma/irq +ad_cpu_interrupt "ps-12" "mb-12" /spi/irq + +ad_mem_hp2_interconnect sys_cpu_clk sys_ps7/S_AXI_HP2 +ad_mem_hp2_interconnect sys_cpu_clk axi_dma/m_dest_axi diff --git a/projects/cn0363/zed/filters/hpf.mat b/projects/cn0363/common/filters/hpf.mat similarity index 100% rename from projects/cn0363/zed/filters/hpf.mat rename to projects/cn0363/common/filters/hpf.mat diff --git a/projects/cn0363/zed/filters/lpf.mat b/projects/cn0363/common/filters/lpf.mat similarity index 100% rename from projects/cn0363/zed/filters/lpf.mat rename to projects/cn0363/common/filters/lpf.mat diff --git a/projects/cn0363/microzed/Makefile b/projects/cn0363/microzed/Makefile new file mode 100644 index 000000000..246d22806 --- /dev/null +++ b/projects/cn0363/microzed/Makefile @@ -0,0 +1,91 @@ +#################################################################################### +#################################################################################### +## Copyright 2011(c) Analog Devices, Inc. +## Auto-generated, do not modify! +#################################################################################### +#################################################################################### + +M_DEPS += system_top.v +M_DEPS += system_project.tcl +M_DEPS += system_constr.xdc +M_DEPS += system_bd.tcl +M_DEPS += ../common/cn0363_bd.tcl +M_DEPS += ../../scripts/adi_project.tcl +M_DEPS += ../../scripts/adi_env.tcl +M_DEPS += ../../scripts/adi_board.tcl +M_DEPS += ../../common/microzed/microzed_system_ps7.tcl +M_DEPS += ../../common/microzed/microzed_system_constr.xdc +M_DEPS += ../../common/microzed/microzed_system_bd.tcl +M_DEPS += ../../../library/xilinx/common/ad_iobuf.v +M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr +M_DEPS += ../../../library/axi_generic_adc/axi_generic_adc.xpr +M_DEPS += ../../../library/spi_engine/axi_spi_engine/axi_spi_engine.xpr +M_DEPS += ../../../library/cn0363/cn0363_dma_sequencer/cn0363_dma_sequencer.xpr +M_DEPS += ../../../library/cn0363/cn0363_phase_data_sync/cn0363_phase_data_sync.xpr +M_DEPS += ../../../library/cordic_demod/cordic_demod.xpr +M_DEPS += ../../../library/spi_engine/spi_engine_execution/spi_engine_execution.xpr +M_DEPS += ../../../library/spi_engine/spi_engine_interconnect/spi_engine_interconnect.xpr +M_DEPS += ../../../library/spi_engine/spi_engine_offload/spi_engine_offload.xpr +M_DEPS += ../../../library/util_axis_resize/util_axis_resize.xpr +M_DEPS += ../../../library/util_sigma_delta_spi/util_sigma_delta_spi.xpr + +M_VIVADO := vivado -mode batch -source + +M_FLIST := *.cache +M_FLIST += *.data +M_FLIST += *.xpr +M_FLIST += *.log +M_FLIST += *.jou +M_FLIST += xgui +M_FLIST += *.runs +M_FLIST += *.srcs +M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim +M_FLIST += .Xil +M_FLIST += *.ip_user_files + + + +.PHONY: all lib clean clean-all +all: lib cn0363_microzed.sdk/system_top.hdf + + +clean: + rm -rf $(M_FLIST) + + +clean-all:clean + make -C ../../../library/axi_dmac clean + make -C ../../../library/axi_generic_adc clean + make -C ../../../library/spi_engine/axi_spi_engine clean + make -C ../../../library/cn0363/cn0363_dma_sequencer clean + make -C ../../../library/cn0363/cn0363_phase_data_sync clean + make -C ../../../library/cordic_demod clean + make -C ../../../library/spi_engine/spi_engine_execution clean + make -C ../../../library/spi_engine/spi_engine_interconnect clean + make -C ../../../library/spi_engine/spi_engine_offload clean + make -C ../../../library/util_axis_resize clean + make -C ../../../library/util_sigma_delta_spi clean + + +cn0363_microzed.sdk/system_top.hdf: $(M_DEPS) + -rm -rf $(M_FLIST) + $(M_VIVADO) system_project.tcl >> cn0363_microzed_vivado.log 2>&1 + + +lib: + make -C ../../../library/axi_dmac + make -C ../../../library/axi_generic_adc + make -C ../../../library/spi_engine/axi_spi_engine + make -C ../../../library/cn0363/cn0363_dma_sequencer + make -C ../../../library/cn0363/cn0363_phase_data_sync + make -C ../../../library/cordic_demod + make -C ../../../library/spi_engine/spi_engine_execution + make -C ../../../library/spi_engine/spi_engine_interconnect + make -C ../../../library/spi_engine/spi_engine_offload + make -C ../../../library/util_axis_resize + make -C ../../../library/util_sigma_delta_spi + +#################################################################################### +#################################################################################### diff --git a/projects/cn0363/microzed/system_bd.tcl b/projects/cn0363/microzed/system_bd.tcl new file mode 100644 index 000000000..6c09795d3 --- /dev/null +++ b/projects/cn0363/microzed/system_bd.tcl @@ -0,0 +1,3 @@ + +source $ad_hdl_dir/projects/common/microzed/microzed_system_bd.tcl +source ../common/cn0363_bd.tcl diff --git a/projects/cn0363/microzed/system_constr.xdc b/projects/cn0363/microzed/system_constr.xdc new file mode 100644 index 000000000..0816b1b0a --- /dev/null +++ b/projects/cn0363/microzed/system_constr.xdc @@ -0,0 +1,23 @@ + +# PL PMOD + +set_property PACKAGE_PIN G17 [get_ports gain0_o] +set_property IOSTANDARD LVCMOS33 [get_ports gain0_o] +set_property PACKAGE_PIN G18 [get_ports gain1_o] +set_property IOSTANDARD LVCMOS33 [get_ports gain1_o] +set_property PACKAGE_PIN F19 [get_ports {spi_cs[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {spi_cs[1]}] +set_property PACKAGE_PIN F20 [get_ports led_clk_o] +set_property IOSTANDARD LVCMOS33 [get_ports led_clk_o] + +set_property PACKAGE_PIN N15 [get_ports {spi_cs[0]}] +set_property IOSTANDARD LVCMOS33 [get_ports {spi_cs[0]}] +set_property PACKAGE_PIN N16 [get_ports spi_sdo] +set_property IOSTANDARD LVCMOS33 [get_ports spi_sdo] +set_property PULLUP true [get_ports spi_sdo] +set_property PACKAGE_PIN L14 [get_ports spi_sdi] +set_property IOSTANDARD LVCMOS33 [get_ports spi_sdi] +set_property PULLUP true [get_ports spi_sdi] +set_property PACKAGE_PIN L15 [get_ports spi_sclk] +set_property IOSTANDARD LVCMOS33 [get_ports spi_sclk] + diff --git a/projects/cn0363/microzed/system_project.tcl b/projects/cn0363/microzed/system_project.tcl new file mode 100644 index 000000000..e56e42a4d --- /dev/null +++ b/projects/cn0363/microzed/system_project.tcl @@ -0,0 +1,12 @@ +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/projects/scripts/adi_project.tcl +source $ad_hdl_dir/projects/scripts/adi_board.tcl + +adi_project_create cn0363_microzed +adi_project_files cn0363_microzed [list \ + "system_top.v" \ + "system_constr.xdc" \ + "$ad_hdl_dir/projects/common/microzed/microzed_system_constr.xdc" \ + "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v"] + +adi_project_run cn0363_microzed diff --git a/projects/cn0363/microzed/system_top.v b/projects/cn0363/microzed/system_top.v new file mode 100644 index 000000000..d123450d7 --- /dev/null +++ b/projects/cn0363/microzed/system_top.v @@ -0,0 +1,203 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top ( + ddr_addr, + ddr_ba, + ddr_cas_n, + ddr_ck_n, + ddr_ck_p, + ddr_cke, + ddr_cs_n, + ddr_dm, + ddr_dq, + ddr_dqs_n, + ddr_dqs_p, + ddr_odt, + ddr_ras_n, + ddr_reset_n, + ddr_we_n, + + fixed_io_ddr_vrn, + fixed_io_ddr_vrp, + fixed_io_mio, + fixed_io_ps_clk, + fixed_io_ps_porb, + fixed_io_ps_srstb, + + spi_sdo, + spi_sdi, + spi_cs, + spi_sclk, + led_clk_o, + gain0_o, + gain1_o, + + otg_vbusoc); + + inout [14:0] ddr_addr; + inout [ 2:0] ddr_ba; + inout ddr_cas_n; + inout ddr_ck_n; + inout ddr_ck_p; + inout ddr_cke; + inout ddr_cs_n; + inout [ 3:0] ddr_dm; + inout [31:0] ddr_dq; + inout [ 3:0] ddr_dqs_n; + inout [ 3:0] ddr_dqs_p; + inout ddr_odt; + inout ddr_ras_n; + inout ddr_reset_n; + inout ddr_we_n; + + inout fixed_io_ddr_vrn; + inout fixed_io_ddr_vrp; + inout [53:0] fixed_io_mio; + inout fixed_io_ps_clk; + inout fixed_io_ps_porb; + inout fixed_io_ps_srstb; + + input spi_sdi; + inout spi_sdo; + output spi_sclk; + output [ 1:0] spi_cs; + output led_clk_o; + output gain0_o; + output gain1_o; + + input otg_vbusoc; + + // internal signals + + wire [34:0] gpio_i; + wire [34:0] gpio_o; + wire [34:0] gpio_t; + wire [23:0] offload_sdi_data; + + wire spi_sdo_o; + wire spi_sdo_t; + wire excitation; + + assign gain0_o = gpio_o[32]; + assign gain1_o = gpio_o[33]; + + assign gpio_i[34] = spi_sdi; // Interrupt + assign gpio_i[33:0] = gpio_o[33:0]; + assign led_clk_o = excitation; + + ad_iobuf #( + .DATA_WIDTH(1) + ) i_sdo_iobuf ( + .dio_t(spi_sdo_t), + .dio_i(spi_sdo_o), + .dio_o(), + .dio_p(spi_sdo) + ); + + system_wrapper i_system_wrapper ( + .ddr_addr (ddr_addr), + .ddr_ba (ddr_ba), + .ddr_cas_n (ddr_cas_n), + .ddr_ck_n (ddr_ck_n), + .ddr_ck_p (ddr_ck_p), + .ddr_cke (ddr_cke), + .ddr_cs_n (ddr_cs_n), + .ddr_dm (ddr_dm), + .ddr_dq (ddr_dq), + .ddr_dqs_n (ddr_dqs_n), + .ddr_dqs_p (ddr_dqs_p), + .ddr_odt (ddr_odt), + .ddr_ras_n (ddr_ras_n), + .ddr_reset_n (ddr_reset_n), + .ddr_we_n (ddr_we_n), + .fixed_io_ddr_vrn (fixed_io_ddr_vrn), + .fixed_io_ddr_vrp (fixed_io_ddr_vrp), + .fixed_io_mio (fixed_io_mio), + .fixed_io_ps_clk (fixed_io_ps_clk), + .fixed_io_ps_porb (fixed_io_ps_porb), + .fixed_io_ps_srstb (fixed_io_ps_srstb), + .gpio_i (gpio_i), + .gpio_o (gpio_o), + .gpio_t (gpio_t), + .ps_intr_00 (1'b0), + .ps_intr_01 (1'b0), + .ps_intr_02 (1'b0), + .ps_intr_03 (1'b0), + .ps_intr_04 (1'b0), + .ps_intr_05 (1'b0), + .ps_intr_06 (1'b0), + .ps_intr_07 (1'b0), + .ps_intr_08 (1'b0), + .ps_intr_09 (1'b0), + .ps_intr_11 (1'b0), + .ps_intr_14 (1'b0), + .ps_intr_15 (1'b0), + .ps_intr_10 (1'b0), + .spi0_clk_i (1'b0), + .spi0_clk_o (), + .spi0_csn_0_o (), + .spi0_csn_1_o (), + .spi0_csn_2_o (), + .spi0_csn_i (1'b1), + .spi0_sdi_i (), + .spi0_sdo_i (1'b0), + .spi0_sdo_o (), + .spi1_clk_i (1'b0), + .spi1_clk_o (), + .spi1_csn_0_o (), + .spi1_csn_1_o (), + .spi1_csn_2_o (), + .spi1_csn_i (1'b1), + .spi1_sdi_i (1'b0), + .spi1_sdo_i (1'b0), + .spi1_sdo_o (), + .spi_sdo (spi_sdo_o), + .spi_sdo_t (spi_sdo_t), + .spi_sdi (spi_sdi), + .spi_cs (spi_cs), + .spi_sclk (spi_sclk), + .excitation (excitation)); + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/projects/cn0363/zed/Makefile b/projects/cn0363/zed/Makefile index c9f80d8c5..53871a020 100644 --- a/projects/cn0363/zed/Makefile +++ b/projects/cn0363/zed/Makefile @@ -9,12 +9,13 @@ M_DEPS += system_top.v M_DEPS += system_project.tcl M_DEPS += system_constr.xdc M_DEPS += system_bd.tcl +M_DEPS += ../common/cn0363_bd.tcl M_DEPS += ../../scripts/adi_project.tcl M_DEPS += ../../scripts/adi_env.tcl M_DEPS += ../../scripts/adi_board.tcl M_DEPS += ../../common/zed/zed_system_constr.xdc M_DEPS += ../../common/zed/zed_system_bd.tcl -M_DEPS += ../../../library/common/ad_iobuf.v +M_DEPS += ../../../library/xilinx/common/ad_iobuf.v M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr M_DEPS += ../../../library/axi_generic_adc/axi_generic_adc.xpr @@ -46,6 +47,7 @@ M_FLIST += *.sdk M_FLIST += *.hw M_FLIST += *.sim M_FLIST += .Xil +M_FLIST += *.ip_user_files @@ -77,7 +79,7 @@ clean-all:clean cn0363_zed.sdk/system_top.hdf: $(M_DEPS) - rm -rf $(M_FLIST) + -rm -rf $(M_FLIST) $(M_VIVADO) system_project.tcl >> cn0363_zed_vivado.log 2>&1 diff --git a/projects/cn0363/zed/system_bd.tcl b/projects/cn0363/zed/system_bd.tcl index 3ccb75fa9..626e401e3 100644 --- a/projects/cn0363/zed/system_bd.tcl +++ b/projects/cn0363/zed/system_bd.tcl @@ -1,297 +1,9 @@ source $ad_hdl_dir/projects/common/zed/zed_system_bd.tcl - -proc load_fir_filter_vector {filter_file} { - set fp [open $filter_file r] - set data [split [read $fp] "\n"] - set filter "" - close $fp - foreach line $data { - set line [string trim $line] - if {[string equal -length 1 $line "#"] || $line eq ""} { - continue - } - if {$filter ne ""} { - append filter "," - } - append filter $line - } - - return $filter -} +source ../common/cn0363_bd.tcl set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_IO {35}] $sys_ps7 set_property LEFT 34 [get_bd_ports GPIO_I] set_property LEFT 34 [get_bd_ports GPIO_O] set_property LEFT 34 [get_bd_ports GPIO_T] - -set axi_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_dma] -set_property -dict [list \ - CONFIG.FIFO_SIZE 2 \ - CONFIG.DMA_TYPE_SRC 2 \ - CONFIG.DMA_TYPE_DEST 0 \ - CONFIG.CYCLIC 0 \ - CONFIG.SYNC_TRANSFER_START 1 \ - CONFIG.AXI_SLICE_SRC 0 \ - CONFIG.AXI_SLICE_DEST 0 \ - CONFIG.DMA_2D_TRANSFER 0 \ - CONFIG.DMA_DATA_WIDTH_SRC 32 \ - CONFIG.DMA_DATA_WIDTH_DEST 64 \ - CONFIG.DMA_AXI_PROTOCOL_DEST 1 \ - ] $axi_dma - -# Create SPI engine controller with offload -create_bd_cell -type hier spi -current_bd_instance /spi - - create_bd_pin -dir I -type clk clk - create_bd_pin -dir I -type rst resetn - create_bd_pin -dir O conv_done - create_bd_pin -dir O irq - create_bd_intf_pin -mode Master -vlnv analog.com:interface:spi_master_rtl:1.0 m_spi - create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 M_AXIS_SAMPLE - - set spi_engine [create_bd_cell -type ip -vlnv analog.com:user:spi_engine_execution:1.0 execution] - set axi_spi_engine [create_bd_cell -type ip -vlnv analog.com:user:axi_spi_engine:1.0 axi] - set spi_engine_offload [create_bd_cell -type ip -vlnv analog.com:user:spi_engine_offload:1.0 offload] - set spi_engine_interconnect [create_bd_cell -type ip -vlnv analog.com:user:spi_engine_interconnect:1.0 interconnect] - set util_sigma_delta_spi [create_bd_cell -type ip -vlnv analog.com:user:util_sigma_delta_spi:1.0 util_sigma_delta_spi] - - set_property -dict [list CONFIG.NUM_OF_CS 2] $spi_engine - - set_property -dict [list CONFIG.NUM_OF_CS 2] $util_sigma_delta_spi - - ad_connect axi/spi_engine_offload_ctrl0 offload/spi_engine_offload_ctrl - ad_connect offload/spi_engine_ctrl interconnect/s0_ctrl - ad_connect axi/spi_engine_ctrl interconnect/s1_ctrl - ad_connect interconnect/m_ctrl execution/ctrl - ad_connect offload/offload_sdi M_AXIS_SAMPLE - - ad_connect util_sigma_delta_spi/data_ready offload/trigger - ad_connect util_sigma_delta_spi/data_ready conv_done - - ad_connect execution/active util_sigma_delta_spi/spi_active - ad_connect execution/spi util_sigma_delta_spi/s_spi - ad_connect util_sigma_delta_spi/m_spi m_spi - - connect_bd_net \ - [get_bd_pins clk] \ - [get_bd_pins offload/spi_clk] \ - [get_bd_pins offload/ctrl_clk] \ - [get_bd_pins execution/clk] \ - [get_bd_pins axi/s_axi_aclk] \ - [get_bd_pins axi/spi_clk] \ - [get_bd_pins interconnect/clk] \ - [get_bd_pins util_sigma_delta_spi/clk] - - connect_bd_net \ - [get_bd_pins axi/spi_resetn] \ - [get_bd_pins offload/spi_resetn] \ - [get_bd_pins execution/resetn] \ - [get_bd_pins interconnect/resetn] \ - [get_bd_pins util_sigma_delta_spi/resetn] - - connect_bd_net [get_bd_pins resetn] [get_bd_pins axi/s_axi_aresetn] - ad_connect irq axi/irq - -current_bd_instance / - -create_bd_intf_port -mode Master -vlnv analog.com:interface:spi_master_rtl:1.0 spi -ad_connect spi/m_spi spi - -set phase_gen [create_bd_cell -type ip -vlnv xilinx.com:ip:c_counter_binary:12.0 phase_gen] -set phase_slice [create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 phase_slice] -create_bd_port -dir O excitation - -set excitation_freq 1020 - -set_property -dict [list \ - CONFIG.Output_Width 32 \ - CONFIG.Increment_Value [format "%x" [expr $excitation_freq * (1<<32) / 100000000]] \ - ] $phase_gen - -set_property -dict [list \ - CONFIG.DIN_TO {31} \ - CONFIG.DIN_FROM {31} \ - CONFIG.DOUT_WIDTH {1} \ - ] $phase_slice - -ad_connect /phase_gen/Q /phase_slice/Din -ad_connect /phase_slice/Dout excitation - -create_bd_cell -type hier processing -current_bd_instance /processing - - create_bd_pin -dir I -type clk clk - create_bd_pin -dir I -type rst resetn - create_bd_pin -dir I conv_done - create_bd_pin -dir I -from 31 -to 0 phase - create_bd_pin -dir O overflow - create_bd_pin -dir I -from 13 -to 0 channel_enable - create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 S_AXIS_SAMPLE - create_bd_intf_pin -mode Master -vlnv analog.com:interface:fifo_wr_rtl:1.0 DMA_WR - - create_bd_cell -type ip -vlnv analog.com:user:cn0363_phase_data_sync:1.0 phase_data_sync - create_bd_cell -type ip -vlnv analog.com:user:cn0363_dma_sequencer:1.0 sequencer - create_bd_cell -type ip -vlnv analog.com:user:cordic_demod:1.0 cordic_demod - - create_bd_cell -type ip -vlnv xilinx.com:ip:axis_broadcaster:1.1 phase_broadcast - create_bd_cell -type ip -vlnv xilinx.com:ip:axis_broadcaster:1.1 sample_broadcast - create_bd_cell -type ip -vlnv xilinx.com:ip:axis_broadcaster:1.1 sample_filtered_broadcast - create_bd_cell -type ip -vlnv xilinx.com:ip:axis_broadcaster:1.1 i_q_broadcast - create_bd_cell -type ip -vlnv xilinx.com:ip:axis_combiner:1.1 phase_sample_combine - set i_q_resize [create_bd_cell -type ip -vlnv analog.com:user:util_axis_resize:1.0 i_q_resize] - - set_property -dict [list \ - CONFIG.MASTER_DATA_WIDTH 32 \ - CONFIG.SLAVE_DATA_WIDTH 64 \ - ] $i_q_resize - - set hpf [create_bd_cell -type ip -vlnv xilinx.com:ip:fir_compiler:7.2 hpf] - set lpf [create_bd_cell -type ip -vlnv xilinx.com:ip:fir_compiler:7.2 lpf] - - set_property -dict [list \ - CONFIG.Data_Fractional_Bits.VALUE_SRC USER \ - CONFIG.Data_Sign.VALUE_SRC USER \ - CONFIG.Data_Width.VALUE_SRC USER \ - CONFIG.M_DATA_Has_TREADY true \ - CONFIG.Number_Channels 2 \ - CONFIG.Sample_Frequency 0.025 \ - CONFIG.Clock_Frequency 100 \ - CONFIG.Coefficient_Width 16 \ - CONFIG.Data_Width 24 \ - CONFIG.Output_Width 32 \ - CONFIG.Output_Rounding_Mode Truncate_LSBs \ - CONFIG.Has_ARESETn true \ - CONFIG.Reset_Data_Vector false \ - CONFIG.CoefficientVector [load_fir_filter_vector "filters/hpf.mat"] \ - ] $hpf - - set_property -dict [list \ - CONFIG.Data_Fractional_Bits.VALUE_SRC USER \ - CONFIG.Data_Sign.VALUE_SRC USER \ - CONFIG.Data_Width.VALUE_SRC USER \ - CONFIG.M_DATA_Has_TREADY true \ - CONFIG.Number_Channels 4 \ - CONFIG.Sample_Frequency 0.025 \ - CONFIG.Clock_Frequency 100 \ - CONFIG.Coefficient_Width 24 \ - CONFIG.Data_Width 32 \ - CONFIG.Output_Width 32 \ - CONFIG.Output_Rounding_Mode Truncate_LSBs \ - CONFIG.Has_ARESETn true \ - CONFIG.Reset_Data_Vector false \ - CONFIG.CoefficientVector [load_fir_filter_vector "filters/lpf.mat"] \ - ] $lpf - - set overflow_or [create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 overflow_or] - set_property -dict [list \ - CONFIG.C_SIZE 1 \ - CONFIG.C_OPERATION {or} \ - ] $overflow_or - - ad_connect S_AXIS_SAMPLE phase_data_sync/S_AXIS_SAMPLE - ad_connect conv_done phase_data_sync/conv_done - ad_connect phase phase_data_sync/phase - - ad_connect phase_data_sync/M_AXIS_PHASE phase_broadcast/S_AXIS - ad_connect phase_broadcast/M00_AXIS sequencer/phase - ad_connect phase_broadcast/M01_AXIS phase_sample_combine/S01_AXIS - - ad_connect phase_data_sync/M_AXIS_SAMPLE sample_broadcast/S_AXIS - ad_connect sample_broadcast/M00_AXIS sequencer/data - ad_connect sample_broadcast/M01_AXIS hpf/S_AXIS_DATA - - ad_connect hpf/M_AXIS_DATA sample_filtered_broadcast/S_AXIS - ad_connect sample_filtered_broadcast/M00_AXIS sequencer/data_filtered - ad_connect sample_filtered_broadcast/M01_AXIS phase_sample_combine/S00_AXIS - - ad_connect phase_sample_combine/M_AXIS cordic_demod/S_AXIS - ad_connect cordic_demod/M_AXIS i_q_resize/s_axis - - ad_connect i_q_resize/m_axis i_q_broadcast/S_AXIS - ad_connect i_q_broadcast/M00_AXIS sequencer/i_q - ad_connect i_q_broadcast/M01_AXIS lpf/S_AXIS_DATA - - ad_connect lpf/M_AXIS_DATA sequencer/i_q_filtered - - connect_bd_net \ - [get_bd_pins clk] \ - [get_bd_pins phase_data_sync/clk] \ - [get_bd_pins sequencer/clk] \ - [get_bd_pins cordic_demod/clk] \ - [get_bd_pins phase_broadcast/aclk] \ - [get_bd_pins sample_broadcast/aclk] \ - [get_bd_pins sample_filtered_broadcast/aclk] \ - [get_bd_pins i_q_broadcast/aclk] \ - [get_bd_pins phase_sample_combine/aclk] \ - [get_bd_pins i_q_resize/clk] \ - [get_bd_pins hpf/aclk] \ - [get_bd_pins lpf/aclk] - - connect_bd_net \ - [get_bd_pins resetn] \ - [get_bd_pins sequencer/resetn] \ - [get_bd_pins phase_data_sync/resetn] \ - - connect_bd_net \ - [get_bd_pins sequencer/processing_resetn] \ - [get_bd_pins phase_data_sync/processing_resetn] \ - [get_bd_pins cordic_demod/resetn] \ - [get_bd_pins phase_broadcast/aresetn] \ - [get_bd_pins sample_broadcast/aresetn] \ - [get_bd_pins sample_filtered_broadcast/aresetn] \ - [get_bd_pins i_q_broadcast/aresetn] \ - [get_bd_pins phase_sample_combine/aresetn] \ - [get_bd_pins i_q_resize/resetn] \ - [get_bd_pins hpf/aresetn] \ - [get_bd_pins lpf/aresetn] - - ad_connect channel_enable sequencer/channel_enable - ad_connect sequencer/dma_wr DMA_WR - - ad_connect phase_data_sync/overflow overflow_or/Op1 - ad_connect sequencer/overflow overflow_or/Op2 - ad_connect overflow_or/Res overflow - - ad_connect phase_data_sync/sample_has_stat GND - -current_bd_instance / - -ad_connect /spi/M_AXIS_SAMPLE /processing/S_AXIS_SAMPLE -ad_connect /spi/conv_done /processing/conv_done -ad_connect /phase_gen/Q /processing/phase - -set axi_adc [create_bd_cell -type ip -vlnv analog.com:user:axi_generic_adc:1.0 axi_adc] -set_property -dict [list \ - CONFIG.NUM_OF_CHANNELS 14 \ - ] $axi_adc - -ad_connect processing/overflow axi_adc/adc_dovf -ad_connect axi_adc/adc_enable processing/channel_enable - -connect_bd_net -net sys_cpu_clk \ - [get_bd_pins /spi/clk] \ - [get_bd_pins /processing/clk] \ - [get_bd_pins /axi_dma/m_dest_axi_aclk] \ - [get_bd_pins /axi_dma/fifo_wr_clk] \ - [get_bd_pins /phase_gen/CLK] \ - [get_bd_pins /axi_adc/adc_clk] - -connect_bd_net -net sys_cpu_resetn \ - [get_bd_pins /spi/resetn] \ - [get_bd_pins /processing/resetn] \ - [get_bd_pins /axi_dma/m_dest_axi_aresetn] - -ad_connect /processing/dma_wr /axi_dma/fifo_wr - -ad_cpu_interconnect 0x43c00000 /axi_adc -ad_cpu_interconnect 0x44a00000 /spi/axi -ad_cpu_interconnect 0x44a30000 /axi_dma - -ad_cpu_interrupt "ps-13" "mb-13" /axi_dma/irq -ad_cpu_interrupt "ps-12" "mb-12" /spi/irq - -ad_mem_hp2_interconnect sys_cpu_clk sys_ps7/S_AXI_HP2 -ad_mem_hp2_interconnect sys_cpu_clk axi_dma/m_dest_axi diff --git a/projects/cn0363/zed/system_project.tcl b/projects/cn0363/zed/system_project.tcl index 9aff54995..10baae44f 100644 --- a/projects/cn0363/zed/system_project.tcl +++ b/projects/cn0363/zed/system_project.tcl @@ -7,6 +7,6 @@ adi_project_files cn0363_zed [list \ "system_top.v" \ "system_constr.xdc" \ "$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc" \ - "$ad_hdl_dir/library/common/ad_iobuf.v"] + "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v"] adi_project_run cn0363_zed diff --git a/projects/cn0363/zed/system_top.v b/projects/cn0363/zed/system_top.v index 5a1df69a1..4c13ce0f5 100644 --- a/projects/cn0363/zed/system_top.v +++ b/projects/cn0363/zed/system_top.v @@ -1,9 +1,9 @@ // *************************************************************************** // *************************************************************************** // Copyright 2011(c) Analog Devices, Inc. -// +// // All rights reserved. -// +// // Redistribution and use in source and binary forms, with or without modification, // are permitted provided that the following conditions are met: // - Redistributions of source code must retain the above copyright @@ -21,16 +21,16 @@ // patent holders to use this software. // - Use of the software either in source or binary form, must be run // on or directly connected to an Analog Devices Inc. component. -// +// // THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, // INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A // PARTICULAR PURPOSE ARE DISCLAIMED. // // IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, // EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY -// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR // BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // *************************************************************************** // *************************************************************************** @@ -91,7 +91,7 @@ module system_top ( led_clk_o, gain0_o, gain1_o, - + otg_vbusoc); inout [14:0] ddr_addr; @@ -138,7 +138,7 @@ module system_top ( inout iic_sda; inout [ 1:0] iic_mux_scl; inout [ 1:0] iic_mux_sda; - + input spi_sdi; inout spi_sdo; output spi_sclk; @@ -168,8 +168,10 @@ module system_top ( assign gain0_o = gpio_o[32]; assign gain1_o = gpio_o[33]; - + assign gpio_i[34] = spi_sdi; // Interrupt + assign gpio_i[33] = gpio_o[33]; + assign gpio_i[32] = gpio_o[32]; assign led_clk_o = excitation; ad_iobuf #( @@ -177,6 +179,7 @@ module system_top ( ) i_sdo_iobuf ( .dio_t(spi_sdo_t), .dio_i(spi_sdo_o), + .dio_o(), .dio_p(spi_sdo) ); @@ -268,7 +271,25 @@ module system_top ( .spi_sclk (spi_sclk), .excitation (excitation), .otg_vbusoc (otg_vbusoc), - .spdif (spdif)); + .spdif (spdif), + .spi0_clk_i (1'b0), + .spi0_clk_o (), + .spi0_csn_0_o (), + .spi0_csn_1_o (), + .spi0_csn_2_o (), + .spi0_csn_i (1'b1), + .spi0_sdi_i (1'b0), + .spi0_sdo_i (1'b0), + .spi0_sdo_o (), + .spi1_clk_i (1'b0), + .spi1_clk_o (), + .spi1_csn_0_o (), + .spi1_csn_1_o (), + .spi1_csn_2_o (), + .spi1_csn_i (1'b1), + .spi1_sdi_i (1'b0), + .spi1_sdo_i (1'b0), + .spi1_sdo_o ()); endmodule diff --git a/projects/common/a10gx/a10gx_system_assign.tcl b/projects/common/a10gx/a10gx_system_assign.tcl index 145c90666..e31c7cf93 100755 --- a/projects/common/a10gx/a10gx_system_assign.tcl +++ b/projects/common/a10gx/a10gx_system_assign.tcl @@ -227,14 +227,7 @@ set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_i[8] set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_i[9] set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_i[10] -# globals - -set_global_assignment -name SYNCHRONIZER_IDENTIFICATION AUTO -set_global_assignment -name ENABLE_ADVANCED_IO_TIMING ON -set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER ON -set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON -set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON -set_global_assignment -name TIMEQUEST_REPORT_SCRIPT $ad_hdl_dir/projects/scripts/adi_tquest.tcl -set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION OFF +# source defaults +source $ad_hdl_dir/projects/common/altera/sys_gen.tcl diff --git a/projects/common/a10gx/a10gx_system_bd.qsys b/projects/common/a10gx/a10gx_system_bd.qsys deleted file mode 100644 index 9cb193b00..000000000 --- a/projects/common/a10gx/a10gx_system_bd.qsys +++ /dev/null @@ -1,2801 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - sys_cpu.jtag_debug_module - - - - - - - - - - - - - ]]> - - - - - - - - - - - - - - - - - - - - - - ADDRESS_STALL 0 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 0 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 0 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 0 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 1 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 1 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 0 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 0 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 0 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 0 HAS_FITTER_ECO_SUPPORT 0 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 0 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 1 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 0 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 0 HAS_MIN_TIMING_ANALYSIS_SUPPORT 0 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 1 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 1 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 1 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 1 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 0 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 0 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 1 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 1 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 1 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 1 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 0 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 0 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 0 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 0 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 0 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 1 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 1 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 1 USES_SECOND_GENERATION_PART_INFO 1 USES_SECOND_GENERATION_POWER_ANALYZER 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 1 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 1 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 0 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 0 - - - sys_ddr3_cntrl_arch.ctrl_amm_0 - - - - - - - - - - - - - - ]]> - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - sys_ddr3_cntrl_arch.ctrl_amm_0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ]]> - - - - - - - - ]]> - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - DDR3_CTRL_ADDR_ORDER_CS_R_B_C - - - - CTRL_AVL_PROTOCOL_MM - - - - - - - - - - - - - - - DDR4_CTRL_ADDR_ORDER_CS_R_B_C_BG - - - - CTRL_AVL_PROTOCOL_MM - - - - - - - - - - - - - - - LPDDR3_CTRL_ADDR_ORDER_CS_R_B_C - - - - CTRL_AVL_PROTOCOL_MM - - - - - - - - - - - - - - - CTRL_AVL_PROTOCOL_MM - - - - - CTRL_AVL_PROTOCOL_MM - CTRL_AVL_PROTOCOL_MM - RLD3_CTRL_ADDR_ORDER_CS_R_B_C - CTRL_AVL_PROTOCOL_MM - - - - - - - - - - EFFMON_MODE_DISABLED - - CAL_DEBUG_EXPORT_MODE_DISABLED - - - - - - - - - - - - - - - EFFMON_MODE_DISABLED - - CAL_DEBUG_EXPORT_MODE_DISABLED - - - - - - - - - - - - - - - - - - - FAST_SIM_OVERRIDE_DEFAULT - - - - EFFMON_MODE_DISABLED - - CAL_DEBUG_EXPORT_MODE_DISABLED - - - - - - - - - - - - - EFFMON_MODE_DISABLED - - CAL_DEBUG_EXPORT_MODE_DISABLED - - - - - - - - - - - EFFMON_MODE_DISABLED - - CAL_DEBUG_EXPORT_MODE_DISABLED - - - - - - - - - - - - EFFMON_MODE_DISABLED - - CAL_DEBUG_EXPORT_MODE_DISABLED - - - - - - - - - - - EFFMON_MODE_DISABLED - - CAL_DEBUG_EXPORT_MODE_DISABLED - - - - - - - - - - - SOFT_NIOS_MODE_DISABLED - - - - - - - - - - - AVAIL_EX_DESIGNS_GEN_DESIGN - - - - - - AVAIL_EX_DESIGNS_GEN_DESIGN - - - - - - AVAIL_EX_DESIGNS_GEN_DESIGN - - - - - - AVAIL_EX_DESIGNS_GEN_DESIGN - - - - - - AVAIL_EX_DESIGNS_GEN_DESIGN - - - - - - AVAIL_EX_DESIGNS_GEN_DESIGN - - - - - - AVAIL_EX_DESIGNS_GEN_DESIGN - - - - - DDR3_ALERT_N_PLACEMENT_AC_LANES - - - - - - - - - - - - - - - - - - - - - - - DDR3_RTT_NOM_ODT_DISABLED - - - - - - - - - - - - - Rank 0,Rank 1,Rank 2,Rank 3 - Rank 0,Rank 1,Rank 2,Rank 3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Rank 0,Rank 1,Rank 2,Rank 3 - Rank 0,Rank 1,Rank 2,Rank 3 - DDR4_AC_PARITY_LATENCY_DISABLE - - - - - DDR4_ALERT_N_PLACEMENT_AUTO - - DDR4_ASR_MANUAL_NORMAL - - - - - - - - - - - - - - - - - - DDR4_FINE_REFRESH_FIXED_1X - - - - - - - - DDR4_MPR_READ_FORMAT_SERIAL - - - - - 0000000000000000000000000000000F000000 - - - - - DDR4_RTT_NOM_ODT_DISABLED - DDR4_RTT_PARK_ODT_DISABLED - - - - - - - - - - - - - Rank 0,Rank 1,Rank 2,Rank 3 - Rank 0,Rank 1,Rank 2,Rank 3 - - - - - - - - - - - - - - - DDR4_TEMP_CONTROLLED_RFSH_NORMAL - - - - - - - - - - - - - - - - - - - - - - - - DDR4_VREFDQ_TRAINING_RANGE_1 - - - - - - - - - - - - - - - - - - - Rank 0,Rank 1,Rank 2,Rank 3 - Rank 0,Rank 1,Rank 2,Rank 3 - - - - - - - LPDDR3_DQODT_DISABLE - - LPDDR3_DRV_STR_40D_40U - - LPDDR3_PDODT_DISABLED - - - - - - - - - - - Rank 0,Rank 1,Rank 2,Rank 3 - LPDDR3_SPEEDBIN_1600 - - - - - - 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CORE_CLKS_SHARING_DISABLED - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - $${FILENAME}_sys_ddr3_cntrl - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ]]> - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ]]> - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - $${FILENAME}_sys_int_mem - - - - - ADDRESS_STALL 0 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 0 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 0 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 0 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 1 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 1 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 0 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 0 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 0 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 0 HAS_FITTER_ECO_SUPPORT 0 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 0 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 1 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 0 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 0 HAS_MIN_TIMING_ANALYSIS_SUPPORT 0 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 1 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 1 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 1 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 1 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 0 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 0 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 1 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 1 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 1 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 1 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 0 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 0 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 0 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 0 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 0 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 1 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 1 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 1 USES_SECOND_GENERATION_PART_INFO 1 USES_SECOND_GENERATION_POWER_ANALYZER 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 1 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 1 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 0 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - $${FILENAME}_sys_tlb_mem - - - - - ADDRESS_STALL 0 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 0 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 0 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 0 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 1 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 1 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 0 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 0 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 0 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 0 HAS_FITTER_ECO_SUPPORT 0 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 0 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 1 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 0 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 0 HAS_MIN_TIMING_ANALYSIS_SUPPORT 0 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 1 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 1 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 1 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 1 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 0 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 0 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 1 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 1 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 1 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 1 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 0 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 0 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 0 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 0 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 0 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 1 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 1 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 1 USES_SECOND_GENERATION_PART_INFO 1 USES_SECOND_GENERATION_POWER_ANALYZER 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 1 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 1 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 0 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 0 - - - - - - - - - - - - - - - - - - - - - - - - - - NO_INTERACTIVE_WINDOWS - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/projects/common/a10gx/a10gx_system_qsys.tcl b/projects/common/a10gx/a10gx_system_qsys.tcl new file mode 100644 index 000000000..ce0bf0b5c --- /dev/null +++ b/projects/common/a10gx/a10gx_system_qsys.tcl @@ -0,0 +1,321 @@ + +package require qsys + +set_module_property NAME {system_bd} +set_project_property DEVICE_FAMILY {Arria 10} +set_project_property DEVICE {10AX115S3F45E2SGE3} + +set system_type nios + +# clock-&-reset + +add_instance sys_clk clock_source 16.0 +add_interface sys_clk clock sink +add_interface sys_rst reset sink +set_interface_property sys_clk EXPORT_OF sys_clk.clk_in +set_interface_property sys_rst EXPORT_OF sys_clk.clk_in_reset +set_instance_parameter_value sys_clk {clockFrequency} {100000000.0} +set_instance_parameter_value sys_clk {clockFrequencyKnown} {1} +set_instance_parameter_value sys_clk {resetSynchronousEdges} {DEASSERT} + +# memory (int) + +add_instance sys_int_mem altera_avalon_onchip_memory2 16.0 +set_instance_parameter_value sys_int_mem {dataWidth} {32} +set_instance_parameter_value sys_int_mem {dualPort} {0} +set_instance_parameter_value sys_int_mem {initMemContent} {0} +set_instance_parameter_value sys_int_mem {memorySize} {163840.0} +add_connection sys_clk.clk sys_int_mem.clk1 +add_connection sys_clk.clk_reset sys_int_mem.reset1 + +# memory (tlb) + +add_instance sys_tlb_mem altera_avalon_onchip_memory2 16.0 +set_instance_parameter_value sys_tlb_mem {dataWidth} {32} +set_instance_parameter_value sys_tlb_mem {dualPort} {1} +set_instance_parameter_value sys_tlb_mem {initMemContent} {1} +set_instance_parameter_value sys_tlb_mem {memorySize} {163840.0} +add_connection sys_clk.clk sys_tlb_mem.clk1 +add_connection sys_clk.clk_reset sys_tlb_mem.reset1 +add_connection sys_clk.clk sys_tlb_mem.clk2 +add_connection sys_clk.clk_reset sys_tlb_mem.reset2 + +# memory (ddr) + +add_instance sys_ddr3_cntrl altera_emif 16.0 +set_instance_parameter_value sys_ddr3_cntrl {PROTOCOL_ENUM} {PROTOCOL_DDR3} +set_instance_parameter_value sys_ddr3_cntrl {PHY_DDR3_CONFIG_ENUM} {CONFIG_PHY_AND_HARD_CTRL} +set_instance_parameter_value sys_ddr3_cntrl {PHY_DDR3_MEM_CLK_FREQ_MHZ} {533.333} +set_instance_parameter_value sys_ddr3_cntrl {PHY_DDR3_DEFAULT_REF_CLK_FREQ} {0} +set_instance_parameter_value sys_ddr3_cntrl {PHY_DDR3_USER_REF_CLK_FREQ_MHZ} {133.333} +set_instance_parameter_value sys_ddr3_cntrl {PHY_DDR3_DEFAULT_IO} {0} +set_instance_parameter_value sys_ddr3_cntrl {PHY_DDR3_USER_AC_IO_STD_ENUM} {IO_STD_SSTL_15_C1} +set_instance_parameter_value sys_ddr3_cntrl {PHY_DDR3_USER_AC_MODE_ENUM} {CURRENT_ST_12} +set_instance_parameter_value sys_ddr3_cntrl {PHY_DDR3_USER_CK_IO_STD_ENUM} {IO_STD_SSTL_15_C1} +set_instance_parameter_value sys_ddr3_cntrl {PHY_DDR3_USER_CK_MODE_ENUM} {CURRENT_ST_12} +set_instance_parameter_value sys_ddr3_cntrl {PHY_DDR3_USER_DATA_IO_STD_ENUM} {IO_STD_SSTL_15} +set_instance_parameter_value sys_ddr3_cntrl {PHY_DDR3_USER_DATA_OUT_MODE_ENUM} {OUT_OCT_34_CAL} +set_instance_parameter_value sys_ddr3_cntrl {PHY_DDR3_USER_RZQ_IO_STD_ENUM} {IO_STD_CMOS_15} +set_instance_parameter_value sys_ddr3_cntrl {PHY_DDR3_USER_DATA_IN_MODE_ENUM} {IN_OCT_40_CAL} +set_instance_parameter_value sys_ddr3_cntrl {PHY_DDR3_USER_PLL_REF_CLK_IO_STD_ENUM} {IO_STD_LVDS} +set_instance_parameter_value sys_ddr3_cntrl {MEM_DDR3_FORMAT_ENUM} {MEM_FORMAT_UDIMM} +set_instance_parameter_value sys_ddr3_cntrl {MEM_DDR3_DQ_WIDTH} {64} +set_instance_parameter_value sys_ddr3_cntrl {MEM_DDR3_ROW_ADDR_WIDTH} {12} +set_instance_parameter_value sys_ddr3_cntrl {MEM_DDR3_COL_ADDR_WIDTH} {10} +set_instance_parameter_value sys_ddr3_cntrl {MEM_DDR3_BANK_ADDR_WIDTH} {3} +set_instance_parameter_value sys_ddr3_cntrl {MEM_DDR3_DM_EN} {1} +set_instance_parameter_value sys_ddr3_cntrl {MEM_DDR3_TCL} {13} +set_instance_parameter_value sys_ddr3_cntrl {MEM_DDR3_WTCL} {9} +set_instance_parameter_value sys_ddr3_cntrl {MEM_DDR3_TRCD_NS} {10.285} +set_instance_parameter_value sys_ddr3_cntrl {MEM_DDR3_TRP_NS} {10.285} +set_instance_parameter_value sys_ddr3_cntrl {BOARD_DDR3_USER_RCLK_SLEW_RATE} {4.0} +set_instance_parameter_value sys_ddr3_cntrl {SHORT_QSYS_INTERFACE_NAMES} {1} +add_connection sys_clk.clk_reset sys_ddr3_cntrl.global_reset_n +add_interface sys_ddr3_cntrl_mem conduit end +add_interface sys_ddr3_cntrl_oct conduit end +add_interface sys_ddr3_cntrl_pll_ref_clk clock sink +set_interface_property sys_ddr3_cntrl_mem EXPORT_OF sys_ddr3_cntrl.mem +set_interface_property sys_ddr3_cntrl_oct EXPORT_OF sys_ddr3_cntrl.oct +set_interface_property sys_ddr3_cntrl_pll_ref_clk EXPORT_OF sys_ddr3_cntrl.pll_ref_clk + +# cpu + +add_instance sys_cpu altera_nios2_gen2 16.0 +set_instance_parameter_value sys_cpu {setting_support31bitdcachebypass} {0} +set_instance_parameter_value sys_cpu {setting_activateTrace} {1} +set_instance_parameter_value sys_cpu {mmu_autoAssignTlbPtrSz} {0} +set_instance_parameter_value sys_cpu {mmu_TLBMissExcOffset} {4096} +set_instance_parameter_value sys_cpu {resetSlave} {sys_ddr3_cntrl_arch.ctrl_amm_0} +set_instance_parameter_value sys_cpu {mmu_TLBMissExcSlave} {sys_tlb_mem.s2} +set_instance_parameter_value sys_cpu {exceptionSlave} {sys_ddr3_cntrl_arch.ctrl_amm_0} +set_instance_parameter_value sys_cpu {breakSlave} {sys_cpu.jtag_debug_module} +set_instance_parameter_value sys_cpu {mul_32_impl} {3} +set_instance_parameter_value sys_cpu {shift_rot_impl} {0} +set_instance_parameter_value sys_cpu {icache_size} {32768} +set_instance_parameter_value sys_cpu {icache_numTCIM} {1} +set_instance_parameter_value sys_cpu {dcache_size} {32768} +set_instance_parameter_value sys_cpu {dcache_numTCDM} {1} +set_instance_parameter_value sys_cpu {setting_dc_ecc_present} {0} +set_instance_parameter_value sys_cpu {setting_itcm_ecc_present} {0} +set_instance_parameter_value sys_cpu {setting_dtcm_ecc_present} {0} +set_instance_parameter_value sys_cpu {mmu_enabled} $mmu_enabled +add_connection sys_clk.clk sys_cpu.clk +add_connection sys_clk.clk_reset sys_cpu.reset +add_connection sys_cpu.debug_reset_request sys_cpu.reset +add_connection sys_cpu.instruction_master sys_cpu.debug_mem_slave +add_connection sys_cpu.instruction_master sys_int_mem.s1 +add_connection sys_cpu.tightly_coupled_instruction_master_0 sys_tlb_mem.s2 +add_connection sys_cpu.tightly_coupled_data_master_0 sys_tlb_mem.s1 +add_connection sys_cpu.instruction_master sys_ddr3_cntrl.ctrl_amm_0 +add_connection sys_cpu.data_master sys_ddr3_cntrl.ctrl_amm_0 +set_connection_parameter_value sys_cpu.data_master/sys_ddr3_cntrl.ctrl_amm_0 baseAddress {0x0} +set_connection_parameter_value sys_cpu.instruction_master/sys_ddr3_cntrl.ctrl_amm_0 baseAddress {0x0} +set_connection_parameter_value sys_cpu.instruction_master/sys_cpu.debug_mem_slave baseAddress {0x10180800} +set_connection_parameter_value sys_cpu.instruction_master/sys_int_mem.s1 baseAddress {0x10140000} +set_connection_parameter_value sys_cpu.tightly_coupled_instruction_master_0/sys_tlb_mem.s2 baseAddress {0x10200000} +set_connection_parameter_value sys_cpu.tightly_coupled_data_master_0/sys_tlb_mem.s1 baseAddress {0x10200000} + +# cpu/hps handling + +proc ad_cpu_interrupt {m_irq m_port} { + + add_connection sys_cpu.irq ${m_port} + set_connection_parameter_value sys_cpu.irq/${m_port} irqNumber ${m_irq} +} + +proc ad_cpu_interconnect {m_base m_port} { + + add_connection sys_cpu.data_master ${m_port} + set_connection_parameter_value sys_cpu.data_master/${m_port} baseAddress [expr ($m_base + 0x10000000)] +} + +proc ad_dma_interconnect {m_port} { + + add_connection ${m_port} sys_ddr3_cntrl.ctrl_amm_0 + set_connection_parameter_value ${m_port}/sys_ddr3_cntrl.ctrl_amm_0 baseAddress {0x0} +} + +# common dma interfaces + +add_instance sys_dma_clk clock_source 16.0 +add_connection sys_ddr3_cntrl.emif_usr_clk sys_dma_clk.clk_in +add_connection sys_ddr3_cntrl.emif_usr_reset_n sys_dma_clk.clk_in_reset + +# ethernet + +add_instance sys_ethernet altera_eth_tse 16.0 +set_instance_parameter_value sys_ethernet {core_variation} {MAC_PCS} +set_instance_parameter_value sys_ethernet {ifGMII} {MII_GMII} +set_instance_parameter_value sys_ethernet {transceiver_type} {LVDS_IO} +set_instance_parameter_value sys_ethernet {enable_hd_logic} {0} +set_instance_parameter_value sys_ethernet {useMDIO} {1} +set_instance_parameter_value sys_ethernet {eg_addr} {12} +set_instance_parameter_value sys_ethernet {ing_addr} {12} +set_instance_parameter_value sys_ethernet {enable_sgmii} {1} + +add_instance sys_ethernet_dma_rx altera_msgdma 16.0 +set_instance_parameter_value sys_ethernet_dma_rx {MODE} {2} +set_instance_parameter_value sys_ethernet_dma_rx {DATA_WIDTH} {64} +set_instance_parameter_value sys_ethernet_dma_rx {DATA_FIFO_DEPTH} {256} +set_instance_parameter_value sys_ethernet_dma_rx {DESCRIPTOR_FIFO_DEPTH} {512} +set_instance_parameter_value sys_ethernet_dma_rx {RESPONSE_PORT} {0} +set_instance_parameter_value sys_ethernet_dma_rx {MAX_BYTE} {2048} +set_instance_parameter_value sys_ethernet_dma_rx {TRANSFER_TYPE} {Unaligned Accesses} +set_instance_parameter_value sys_ethernet_dma_rx {BURST_ENABLE} {1} +set_instance_parameter_value sys_ethernet_dma_rx {MAX_BURST_COUNT} {64} +set_instance_parameter_value sys_ethernet_dma_rx {ENHANCED_FEATURES} {1} +set_instance_parameter_value sys_ethernet_dma_rx {PACKET_ENABLE} {1} +set_instance_parameter_value sys_ethernet_dma_rx {ERROR_ENABLE} {1} +set_instance_parameter_value sys_ethernet_dma_rx {ERROR_WIDTH} {6} + +add_instance sys_ethernet_dma_tx altera_msgdma 16.0 +set_instance_parameter_value sys_ethernet_dma_tx {MODE} {1} +set_instance_parameter_value sys_ethernet_dma_tx {DATA_WIDTH} {64} +set_instance_parameter_value sys_ethernet_dma_tx {DATA_FIFO_DEPTH} {256} +set_instance_parameter_value sys_ethernet_dma_tx {DESCRIPTOR_FIFO_DEPTH} {512} +set_instance_parameter_value sys_ethernet_dma_tx {MAX_BYTE} {2048} +set_instance_parameter_value sys_ethernet_dma_tx {TRANSFER_TYPE} {Unaligned Accesses} +set_instance_parameter_value sys_ethernet_dma_tx {BURST_ENABLE} {1} +set_instance_parameter_value sys_ethernet_dma_tx {MAX_BURST_COUNT} {64} +set_instance_parameter_value sys_ethernet_dma_tx {ENHANCED_FEATURES} {1} +set_instance_parameter_value sys_ethernet_dma_tx {PACKET_ENABLE} {1} +set_instance_parameter_value sys_ethernet_dma_tx {ERROR_ENABLE} {1} +set_instance_parameter_value sys_ethernet_dma_tx {ERROR_WIDTH} {1} + +add_instance sys_ethernet_reset altera_reset_bridge 16.0 +set_instance_parameter_value sys_ethernet_reset {ACTIVE_LOW_RESET} {0} +set_instance_parameter_value sys_ethernet_reset {NUM_RESET_OUTPUTS} {1} + +add_connection sys_clk.clk_reset sys_ethernet.reset_connection +add_connection sys_clk.clk_reset sys_ethernet_dma_rx.reset_n +add_connection sys_clk.clk_reset sys_ethernet_dma_tx.reset_n +add_connection sys_clk.clk_reset sys_ethernet_reset.in_reset +add_connection sys_clk.clk sys_ethernet.control_port_clock_connection +add_connection sys_clk.clk sys_ethernet.receive_clock_connection +add_connection sys_clk.clk sys_ethernet.transmit_clock_connection +add_connection sys_clk.clk sys_ethernet_dma_rx.clock +add_connection sys_clk.clk sys_ethernet_dma_tx.clock +add_connection sys_clk.clk sys_ethernet_reset.clk +add_connection sys_ethernet.receive sys_ethernet_dma_rx.st_sink +add_connection sys_ethernet_dma_tx.st_source sys_ethernet.transmit +add_interface sys_ethernet_reset reset source +add_interface sys_ethernet_ref_clk clock sink +add_interface sys_ethernet_mdio conduit end +add_interface sys_ethernet_sgmii conduit end + +set_interface_property sys_ethernet_mdio EXPORT_OF sys_ethernet.mac_mdio_connection +set_interface_property sys_ethernet_ref_clk EXPORT_OF sys_ethernet.pcs_ref_clk_clock_connection +set_interface_property sys_ethernet_reset EXPORT_OF sys_ethernet_reset.out_reset +set_interface_property sys_ethernet_sgmii EXPORT_OF sys_ethernet.serial_connection + +# sys-id + +add_instance sys_id altera_avalon_sysid_qsys 16.0 +set_instance_parameter_value sys_id {id} {182193580} +add_connection sys_clk.clk_reset sys_id.reset +add_connection sys_clk.clk sys_id.clk + +# timer-1 + +add_instance sys_timer_1 altera_avalon_timer 16.0 +set_instance_parameter_value sys_timer_1 {counterSize} {32} +add_connection sys_clk.clk_reset sys_timer_1.reset +add_connection sys_clk.clk sys_timer_1.clk + +# timer-2 + +add_instance sys_timer_2 altera_avalon_timer 16.0 +set_instance_parameter_value sys_timer_2 {counterSize} {32} +add_connection sys_clk.clk_reset sys_timer_2.reset +add_connection sys_clk.clk sys_timer_2.clk + +# uart + +add_instance sys_uart altera_avalon_jtag_uart 16.0 +set_instance_parameter_value sys_uart {allowMultipleConnections} {0} +add_connection sys_clk.clk_reset sys_uart.reset +add_connection sys_clk.clk sys_uart.clk + +# gpio-bd + +add_instance sys_gpio_bd altera_avalon_pio 16.0 +set_instance_parameter_value sys_gpio_bd {direction} {InOut} +set_instance_parameter_value sys_gpio_bd {generateIRQ} {1} +set_instance_parameter_value sys_gpio_bd {width} {32} +add_connection sys_clk.clk_reset sys_gpio_bd.reset +add_connection sys_clk.clk sys_gpio_bd.clk +add_interface sys_gpio_bd conduit end +set_interface_property sys_gpio_bd EXPORT_OF sys_gpio_bd.external_connection + +# gpio-in + +add_instance sys_gpio_in altera_avalon_pio 16.0 +set_instance_parameter_value sys_gpio_in {direction} {Input} +set_instance_parameter_value sys_gpio_in {generateIRQ} {1} +set_instance_parameter_value sys_gpio_in {width} {32} +add_connection sys_clk.clk_reset sys_gpio_in.reset +add_connection sys_clk.clk sys_gpio_in.clk +add_interface sys_gpio_in conduit end +set_interface_property sys_gpio_in EXPORT_OF sys_gpio_in.external_connection + +# gpio-out + +add_instance sys_gpio_out altera_avalon_pio 16.0 +set_instance_parameter_value sys_gpio_out {direction} {Output} +set_instance_parameter_value sys_gpio_out {generateIRQ} {0} +set_instance_parameter_value sys_gpio_out {width} {32} +add_connection sys_clk.clk_reset sys_gpio_out.reset +add_connection sys_clk.clk sys_gpio_out.clk +add_interface sys_gpio_out conduit end +set_interface_property sys_gpio_out EXPORT_OF sys_gpio_out.external_connection + +# spi + +add_instance sys_spi altera_avalon_spi 16.0 +set_instance_parameter_value sys_spi {clockPhase} {0} +set_instance_parameter_value sys_spi {clockPolarity} {0} +set_instance_parameter_value sys_spi {dataWidth} {8} +set_instance_parameter_value sys_spi {masterSPI} {1} +set_instance_parameter_value sys_spi {numberOfSlaves} {8} +set_instance_parameter_value sys_spi {targetClockRate} {128000.0} +add_connection sys_clk.clk_reset sys_spi.reset +add_connection sys_clk.clk sys_spi.clk +add_interface sys_spi conduit end +set_interface_property sys_spi EXPORT_OF sys_spi.external + +# base-addresses + +ad_cpu_interconnect 0x00180800 sys_cpu.debug_mem_slave +ad_cpu_interconnect 0x00140000 sys_int_mem.s1 +ad_cpu_interconnect 0x00181000 sys_ethernet.control_port +ad_cpu_interconnect 0x001814a0 sys_ethernet_dma_rx.csr +ad_cpu_interconnect 0x001814e0 sys_ethernet_dma_rx.response +ad_cpu_interconnect 0x00181440 sys_ethernet_dma_rx.descriptor_slave +ad_cpu_interconnect 0x00181480 sys_ethernet_dma_tx.csr +ad_cpu_interconnect 0x00181460 sys_ethernet_dma_tx.descriptor_slave +ad_cpu_interconnect 0x001814e8 sys_id.control_slave +ad_cpu_interconnect 0x00181420 sys_timer_1.s1 +ad_cpu_interconnect 0x00181520 sys_timer_2.s1 +ad_cpu_interconnect 0x001814f0 sys_uart.avalon_jtag_slave +ad_cpu_interconnect 0x001814d0 sys_gpio_bd.s1 +ad_cpu_interconnect 0x001814c0 sys_gpio_in.s1 +ad_cpu_interconnect 0x00181500 sys_gpio_out.s1 +ad_cpu_interconnect 0x00181400 sys_spi.spi_control_port + +# dma interconnects + +ad_dma_interconnect sys_ethernet_dma_tx.mm_read +ad_dma_interconnect sys_ethernet_dma_rx.mm_write + +# interrupts + +ad_cpu_interrupt 0 sys_ethernet_dma_rx.csr_irq +ad_cpu_interrupt 1 sys_ethernet_dma_tx.csr_irq +ad_cpu_interrupt 2 sys_uart.irq +ad_cpu_interrupt 3 sys_timer_2.irq +ad_cpu_interrupt 4 sys_timer_1.irq +ad_cpu_interrupt 5 sys_gpio_in.irq +ad_cpu_interrupt 6 sys_gpio_bd.irq +ad_cpu_interrupt 7 sys_spi.irq + + diff --git a/projects/common/a10soc/a10soc_system_assign.tcl b/projects/common/a10soc/a10soc_system_assign.tcl new file mode 100755 index 000000000..80b9fcd7d --- /dev/null +++ b/projects/common/a10soc/a10soc_system_assign.tcl @@ -0,0 +1,259 @@ + +# device settings + +set_global_assignment -name FAMILY "Arria 10" +set_global_assignment -name DEVICE 10AS066N3F40E2SGE2 + +# clocks and resets + +set_location_assignment PIN_AM10 -to sys_clk +set_location_assignment PIN_AL10 -to "sys_clk(n)" +set_location_assignment PIN_AV21 -to sys_resetn +set_instance_assignment -name IO_STANDARD LVDS -to sys_clk +set_instance_assignment -name IO_STANDARD "1.8 V" -to sys_resetn + +# hps-ddr4 (32) + +set_location_assignment PIN_F25 -to hps_ddr_ref_clk +set_location_assignment PIN_G24 -to "hps_ddr_ref_clk(n)" + +set_instance_assignment -name IO_STANDARD LVDS -to hps_ddr_ref_clk +set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to hps_ddr_ref_clk -disable + +set_location_assignment PIN_B20 -to hps_ddr_clk_p +set_location_assignment PIN_B19 -to hps_ddr_clk_n +set_location_assignment PIN_B26 -to hps_ddr_a[0] +set_location_assignment PIN_C26 -to hps_ddr_a[1] +set_location_assignment PIN_C22 -to hps_ddr_a[2] +set_location_assignment PIN_C21 -to hps_ddr_a[3] +set_location_assignment PIN_C25 -to hps_ddr_a[4] +set_location_assignment PIN_B24 -to hps_ddr_a[5] +set_location_assignment PIN_B22 -to hps_ddr_a[6] +set_location_assignment PIN_C23 -to hps_ddr_a[7] +set_location_assignment PIN_D23 -to hps_ddr_a[8] +set_location_assignment PIN_E23 -to hps_ddr_a[9] +set_location_assignment PIN_C24 -to hps_ddr_a[10] +set_location_assignment PIN_D24 -to hps_ddr_a[11] +set_location_assignment PIN_F26 -to hps_ddr_a[12] +set_location_assignment PIN_G26 -to hps_ddr_a[13] +set_location_assignment PIN_G25 -to hps_ddr_a[14] +set_location_assignment PIN_F24 -to hps_ddr_a[15] +set_location_assignment PIN_F23 -to hps_ddr_a[16] +set_location_assignment PIN_E25 -to hps_ddr_ba[0] +set_location_assignment PIN_H24 -to hps_ddr_ba[1] +set_location_assignment PIN_J24 -to hps_ddr_bg +set_location_assignment PIN_A24 -to hps_ddr_cke +set_location_assignment PIN_A22 -to hps_ddr_cs_n +set_location_assignment PIN_A26 -to hps_ddr_odt +set_location_assignment PIN_A19 -to hps_ddr_reset_n +set_location_assignment PIN_B21 -to hps_ddr_act_n +set_location_assignment PIN_A18 -to hps_ddr_par +set_location_assignment PIN_AG24 -to hps_ddr_alert_n +set_location_assignment PIN_AM25 -to hps_ddr_dqs_p[0] +set_location_assignment PIN_AL25 -to hps_ddr_dqs_n[0] +set_location_assignment PIN_AT25 -to hps_ddr_dqs_p[1] +set_location_assignment PIN_AT24 -to hps_ddr_dqs_n[1] +set_location_assignment PIN_AW26 -to hps_ddr_dqs_p[2] +set_location_assignment PIN_AW25 -to hps_ddr_dqs_n[2] +set_location_assignment PIN_AK25 -to hps_ddr_dqs_p[3] +set_location_assignment PIN_AJ25 -to hps_ddr_dqs_n[3] +set_location_assignment PIN_AP26 -to hps_ddr_dq[0] +set_location_assignment PIN_AN24 -to hps_ddr_dq[1] +set_location_assignment PIN_AN23 -to hps_ddr_dq[2] +set_location_assignment PIN_AM24 -to hps_ddr_dq[3] +set_location_assignment PIN_AK26 -to hps_ddr_dq[4] +set_location_assignment PIN_AL23 -to hps_ddr_dq[5] +set_location_assignment PIN_AL26 -to hps_ddr_dq[6] +set_location_assignment PIN_AK23 -to hps_ddr_dq[7] +set_location_assignment PIN_AP23 -to hps_ddr_dq[8] +set_location_assignment PIN_AT26 -to hps_ddr_dq[9] +set_location_assignment PIN_AR26 -to hps_ddr_dq[10] +set_location_assignment PIN_AR25 -to hps_ddr_dq[11] +set_location_assignment PIN_AT23 -to hps_ddr_dq[12] +set_location_assignment PIN_AP25 -to hps_ddr_dq[13] +set_location_assignment PIN_AU24 -to hps_ddr_dq[14] +set_location_assignment PIN_AU26 -to hps_ddr_dq[15] +set_location_assignment PIN_AU28 -to hps_ddr_dq[16] +set_location_assignment PIN_AU27 -to hps_ddr_dq[17] +set_location_assignment PIN_AV23 -to hps_ddr_dq[18] +set_location_assignment PIN_AW28 -to hps_ddr_dq[19] +set_location_assignment PIN_AV24 -to hps_ddr_dq[20] +set_location_assignment PIN_AW24 -to hps_ddr_dq[21] +set_location_assignment PIN_AV28 -to hps_ddr_dq[22] +set_location_assignment PIN_AV27 -to hps_ddr_dq[23] +set_location_assignment PIN_AH24 -to hps_ddr_dq[24] +set_location_assignment PIN_AH23 -to hps_ddr_dq[25] +set_location_assignment PIN_AG25 -to hps_ddr_dq[26] +set_location_assignment PIN_AF24 -to hps_ddr_dq[27] +set_location_assignment PIN_AF25 -to hps_ddr_dq[28] +set_location_assignment PIN_AJ24 -to hps_ddr_dq[29] +set_location_assignment PIN_AJ23 -to hps_ddr_dq[30] +set_location_assignment PIN_AJ26 -to hps_ddr_dq[31] +set_location_assignment PIN_AN26 -to hps_ddr_dbi_n[0] +set_location_assignment PIN_AU25 -to hps_ddr_dbi_n[1] +set_location_assignment PIN_AV26 -to hps_ddr_dbi_n[2] +set_location_assignment PIN_AH25 -to hps_ddr_dbi_n[3] +set_location_assignment PIN_E26 -to hps_ddr_rzq + +# hps-ethernet + +set_location_assignment PIN_F18 -to hps_eth_rxclk +set_location_assignment PIN_G17 -to hps_eth_rxctl +set_location_assignment PIN_G20 -to hps_eth_rxd[0] +set_location_assignment PIN_G21 -to hps_eth_rxd[1] +set_location_assignment PIN_F22 -to hps_eth_rxd[2] +set_location_assignment PIN_G22 -to hps_eth_rxd[3] +set_location_assignment PIN_H18 -to hps_eth_txclk +set_location_assignment PIN_H19 -to hps_eth_txctl +set_location_assignment PIN_E20 -to hps_eth_txd[0] +set_location_assignment PIN_F20 -to hps_eth_txd[1] +set_location_assignment PIN_F19 -to hps_eth_txd[2] +set_location_assignment PIN_G19 -to hps_eth_txd[3] +set_location_assignment PIN_K20 -to hps_eth_mdc +set_location_assignment PIN_K21 -to hps_eth_mdio + +set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_eth_rxclk +set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_eth_rxctl +set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_eth_rxd[0] +set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_eth_rxd[1] +set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_eth_rxd[2] +set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_eth_rxd[3] +set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_eth_txclk +set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_eth_txctl +set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_eth_txd[0] +set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_eth_txd[1] +set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_eth_txd[2] +set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_eth_txd[3] +set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_eth_mdc +set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_eth_mdio + +set_instance_assignment -name OUTPUT_DELAY_CHAIN 8 -to hps_eth_txclk + +# hps-sdio + +set_location_assignment PIN_K16 -to hps_sdio_clk +set_location_assignment PIN_H16 -to hps_sdio_cmd +set_location_assignment PIN_E16 -to hps_sdio_d[0] +set_location_assignment PIN_G16 -to hps_sdio_d[1] +set_location_assignment PIN_H17 -to hps_sdio_d[2] +set_location_assignment PIN_F15 -to hps_sdio_d[3] +set_location_assignment PIN_M19 -to hps_sdio_d[4] +set_location_assignment PIN_E15 -to hps_sdio_d[5] +set_location_assignment PIN_J16 -to hps_sdio_d[6] +set_location_assignment PIN_L18 -to hps_sdio_d[7] + +set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_sdio_clk +set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_sdio_cmd +set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_sdio_d[0] +set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_sdio_d[1] +set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_sdio_d[2] +set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_sdio_d[3] +set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_sdio_d[4] +set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_sdio_d[5] +set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_sdio_d[6] +set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_sdio_d[7] + +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to hps_sdio_clk +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to hps_sdio_cmd +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to hps_sdio_d[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to hps_sdio_d[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to hps_sdio_d[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to hps_sdio_d[3] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to hps_sdio_d[4] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to hps_sdio_d[5] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to hps_sdio_d[6] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to hps_sdio_d[7] +set_instance_assignment -name SLEW_RATE 1 -to hps_sdio_clk +set_instance_assignment -name SLEW_RATE 1 -to hps_sdio_cmd +set_instance_assignment -name SLEW_RATE 1 -to hps_sdio_d[0] +set_instance_assignment -name SLEW_RATE 1 -to hps_sdio_d[1] +set_instance_assignment -name SLEW_RATE 1 -to hps_sdio_d[2] +set_instance_assignment -name SLEW_RATE 1 -to hps_sdio_d[3] + +# hps-usb + +set_location_assignment PIN_D18 -to hps_usb_clk +set_location_assignment PIN_C19 -to hps_usb_dir +set_location_assignment PIN_F17 -to hps_usb_nxt +set_location_assignment PIN_E18 -to hps_usb_stp +set_location_assignment PIN_D19 -to hps_usb_d[0] +set_location_assignment PIN_E17 -to hps_usb_d[1] +set_location_assignment PIN_C17 -to hps_usb_d[2] +set_location_assignment PIN_C18 -to hps_usb_d[3] +set_location_assignment PIN_D21 -to hps_usb_d[4] +set_location_assignment PIN_D20 -to hps_usb_d[5] +set_location_assignment PIN_E21 -to hps_usb_d[6] +set_location_assignment PIN_E22 -to hps_usb_d[7] + +set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_usb_clk +set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_usb_dir +set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_usb_nxt +set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_usb_stp +set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_usb_d[0] +set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_usb_d[1] +set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_usb_d[2] +set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_usb_d[3] +set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_usb_d[4] +set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_usb_d[5] +set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_usb_d[6] +set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_usb_d[7] + +# hps-uart + +set_location_assignment PIN_M17 -to hps_uart_tx +set_location_assignment PIN_K17 -to hps_uart_rx + +set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_uart_tx +set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_uart_rx + +# hps-i2c (shared w fmc-a, fmc-b) + +set_location_assignment PIN_M20 -to hps_i2c_scl +set_location_assignment PIN_L20 -to hps_i2c_sda + +set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_i2c_scl +set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_i2c_sda + +# gpio (max-v-u21) + +set_location_assignment PIN_AR23 -to gpio_bd_o[0] ; ## led[0] +set_location_assignment PIN_AR22 -to gpio_bd_o[1] ; ## led[1] +set_location_assignment PIN_AM21 -to gpio_bd_o[2] ; ## led[2] +set_location_assignment PIN_AL20 -to gpio_bd_o[3] ; ## led[3] +set_location_assignment PIN_P3 -to gpio_bd_i[0] ; ## dipsw[0] +set_location_assignment PIN_P4 -to gpio_bd_i[1] ; ## dipsw[1] +set_location_assignment PIN_P1 -to gpio_bd_i[2] ; ## dipsw[2] +set_location_assignment PIN_R1 -to gpio_bd_i[3] ; ## dipsw[3] +set_location_assignment PIN_R5 -to gpio_bd_i[4] ; ## pb[0] +set_location_assignment PIN_T5 -to gpio_bd_i[5] ; ## pb[1] +set_location_assignment PIN_P5 -to gpio_bd_i[6] ; ## pb[2] +set_location_assignment PIN_P6 -to gpio_bd_i[7] ; ## pb[3] + +set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_o[0] +set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_o[1] +set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_o[2] +set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_o[3] +set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_i[0] +set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_i[1] +set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_i[2] +set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_i[3] +set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_i[0] +set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_i[1] +set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_i[2] +set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_i[3] + +# hps-gpio (max-v-u16) + +set_location_assignment PIN_J20 -to hps_gpio[0] +set_location_assignment PIN_N20 -to hps_gpio[1] +set_location_assignment PIN_K23 -to hps_gpio[2] +set_location_assignment PIN_L23 -to hps_gpio[3] + +set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_gpio[0] +set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_gpio[1] +set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_gpio[2] +set_instance_assignment -name IO_STANDARD "1.8 V" -to hps_gpio[3] + +# source defaults + +source $ad_hdl_dir/projects/common/altera/sys_gen.tcl diff --git a/projects/common/a10soc/a10soc_system_qsys.tcl b/projects/common/a10soc/a10soc_system_qsys.tcl new file mode 100755 index 000000000..9e725a863 --- /dev/null +++ b/projects/common/a10soc/a10soc_system_qsys.tcl @@ -0,0 +1,247 @@ + +package require qsys + +set_module_property NAME {system_bd} +set_project_property DEVICE_FAMILY {Arria 10} +set_project_property DEVICE {10AS066N3F40E2SGE2} + +set system_type a10soc + +add_instance sys_clk clock_source 16.0 +add_interface sys_clk clock sink +set_interface_property sys_clk EXPORT_OF sys_clk.clk_in +add_interface sys_rstn reset sink +set_interface_property sys_rstn EXPORT_OF sys_clk.clk_in_reset +set_instance_parameter_value sys_clk {clockFrequency} {100000000.0} +set_instance_parameter_value sys_clk {clockFrequencyKnown} {1} +set_instance_parameter_value sys_clk {resetSynchronousEdges} {DEASSERT} + +# hps +# round-about way - qsys-script doesn't support {*}? + +variable hps_io_list + +proc set_hps_io {io_index io_type} { + + global hps_io_list + lappend hps_io_list $io_type +} + +set_hps_io IO_DEDICATED_04 SDMMC:D0 +set_hps_io IO_DEDICATED_05 SDMMC:CMD +set_hps_io IO_DEDICATED_06 SDMMC:CCLK +set_hps_io IO_DEDICATED_07 SDMMC:D1 +set_hps_io IO_DEDICATED_08 SDMMC:D2 +set_hps_io IO_DEDICATED_09 SDMMC:D3 +set_hps_io IO_DEDICATED_10 NONE +set_hps_io IO_DEDICATED_11 NONE +set_hps_io IO_DEDICATED_12 SDMMC:D4 +set_hps_io IO_DEDICATED_13 SDMMC:D5 +set_hps_io IO_DEDICATED_14 SDMMC:D6 +set_hps_io IO_DEDICATED_15 SDMMC:D7 +set_hps_io IO_DEDICATED_16 UART1:TX +set_hps_io IO_DEDICATED_17 UART1:RX +set_hps_io IO_SHARED_Q1_01 USB0:CLK +set_hps_io IO_SHARED_Q1_02 USB0:STP +set_hps_io IO_SHARED_Q1_03 USB0:DIR +set_hps_io IO_SHARED_Q1_04 USB0:DATA0 +set_hps_io IO_SHARED_Q1_05 USB0:DATA1 +set_hps_io IO_SHARED_Q1_06 USB0:NXT +set_hps_io IO_SHARED_Q1_07 USB0:DATA2 +set_hps_io IO_SHARED_Q1_08 USB0:DATA3 +set_hps_io IO_SHARED_Q1_09 USB0:DATA4 +set_hps_io IO_SHARED_Q1_10 USB0:DATA5 +set_hps_io IO_SHARED_Q1_11 USB0:DATA6 +set_hps_io IO_SHARED_Q1_12 USB0:DATA7 +set_hps_io IO_SHARED_Q2_01 EMAC0:TX_CLK +set_hps_io IO_SHARED_Q2_02 EMAC0:TX_CTL +set_hps_io IO_SHARED_Q2_03 EMAC0:RX_CLK +set_hps_io IO_SHARED_Q2_04 EMAC0:RX_CTL +set_hps_io IO_SHARED_Q2_05 EMAC0:TXD0 +set_hps_io IO_SHARED_Q2_06 EMAC0:TXD1 +set_hps_io IO_SHARED_Q2_07 EMAC0:RXD0 +set_hps_io IO_SHARED_Q2_08 EMAC0:RXD1 +set_hps_io IO_SHARED_Q2_09 EMAC0:TXD2 +set_hps_io IO_SHARED_Q2_10 EMAC0:TXD3 +set_hps_io IO_SHARED_Q2_11 EMAC0:RXD2 +set_hps_io IO_SHARED_Q2_12 EMAC0:RXD3 +set_hps_io IO_SHARED_Q3_01 NONE +set_hps_io IO_SHARED_Q3_02 NONE +set_hps_io IO_SHARED_Q3_03 NONE +set_hps_io IO_SHARED_Q3_04 NONE +set_hps_io IO_SHARED_Q3_05 NONE +set_hps_io IO_SHARED_Q3_06 GPIO +set_hps_io IO_SHARED_Q3_07 NONE +set_hps_io IO_SHARED_Q3_08 NONE +set_hps_io IO_SHARED_Q3_09 NONE +set_hps_io IO_SHARED_Q3_10 NONE +set_hps_io IO_SHARED_Q3_11 MDIO0:MDIO +set_hps_io IO_SHARED_Q3_12 MDIO0:MDC +set_hps_io IO_SHARED_Q4_01 I2C1:SDA +set_hps_io IO_SHARED_Q4_02 I2C1:SCL +set_hps_io IO_SHARED_Q4_03 GPIO +set_hps_io IO_SHARED_Q4_04 NONE +set_hps_io IO_SHARED_Q4_05 GPIO +set_hps_io IO_SHARED_Q4_06 GPIO +set_hps_io IO_SHARED_Q4_07 NONE +set_hps_io IO_SHARED_Q4_08 NONE +set_hps_io IO_SHARED_Q4_09 NONE +set_hps_io IO_SHARED_Q4_10 NONE +set_hps_io IO_SHARED_Q4_11 NONE +set_hps_io IO_SHARED_Q4_12 NONE + +add_instance sys_hps altera_arria10_hps 16.0 +set_instance_parameter_value sys_hps {MPU_EVENTS_Enable} {0} +set_instance_parameter_value sys_hps {F2S_Width} {0} +set_instance_parameter_value sys_hps {S2F_Width} {0} +set_instance_parameter_value sys_hps {LWH2F_Enable} {1} +set_instance_parameter_value sys_hps {F2SDRAM_PORT_CONFIG} {6} +set_instance_parameter_value sys_hps {F2SDRAM0_ENABLED} {1} +set_instance_parameter_value sys_hps {F2SINTERRUPT_Enable} {1} +set_instance_parameter_value sys_hps {HPS_IO_Enable} $hps_io_list +set_instance_parameter_value sys_hps {SDMMC_PinMuxing} {IO} +set_instance_parameter_value sys_hps {SDMMC_Mode} {8-bit} +set_instance_parameter_value sys_hps {USB0_PinMuxing} {IO} +set_instance_parameter_value sys_hps {USB0_Mode} {default} +set_instance_parameter_value sys_hps {EMAC0_PinMuxing} {IO} +set_instance_parameter_value sys_hps {EMAC0_Mode} {RGMII_with_MDIO} +set_instance_parameter_value sys_hps {UART1_PinMuxing} {IO} +set_instance_parameter_value sys_hps {UART1_Mode} {No_flow_control} +set_instance_parameter_value sys_hps {I2C1_PinMuxing} {IO} +set_instance_parameter_value sys_hps {I2C1_Mode} {default} +set_instance_parameter_value sys_hps {F2H_COLD_RST_Enable} {1} +set_instance_parameter_value sys_hps {H2F_USER0_CLK_Enable} {1} +set_instance_parameter_value sys_hps {H2F_USER0_CLK_FREQ} {175} +set_instance_parameter_value sys_hps {CLK_SDMMC_SOURCE} {1} + +add_interface sys_hps_rstn reset sink +set_interface_property sys_hps_rstn EXPORT_OF sys_hps.f2h_cold_reset_req +add_interface sys_hps_out_rstn reset source +set_interface_property sys_hps_out_rstn EXPORT_OF sys_hps.h2f_reset +add_connection sys_clk.clk sys_hps.h2f_lw_axi_clock +add_connection sys_hps.h2f_user0_clock sys_hps.f2sdram0_clock +add_interface sys_hps_io conduit end +set_interface_property sys_hps_io EXPORT_OF sys_hps.hps_io + +# ddr4 interface + +add_instance sys_hps_ddr4_cntrl altera_emif_a10_hps 16.0 +set_instance_parameter_value sys_hps_ddr4_cntrl {PROTOCOL_ENUM} {PROTOCOL_DDR4} +set_instance_parameter_value sys_hps_ddr4_cntrl {PHY_DDR4_MEM_CLK_FREQ_MHZ} {1066.667} +set_instance_parameter_value sys_hps_ddr4_cntrl {PHY_DDR4_DEFAULT_REF_CLK_FREQ} {0} +set_instance_parameter_value sys_hps_ddr4_cntrl {PHY_DDR4_USER_REF_CLK_FREQ_MHZ} {133.333} +set_instance_parameter_value sys_hps_ddr4_cntrl {MEM_DDR4_BANK_GROUP_WIDTH} {1} +set_instance_parameter_value sys_hps_ddr4_cntrl {MEM_DDR4_ALERT_N_PLACEMENT_ENUM} {DDR4_ALERT_N_PLACEMENT_DATA_LANES} +set_instance_parameter_value sys_hps_ddr4_cntrl {MEM_DDR4_ALERT_N_DQS_GROUP} {3} +set_instance_parameter_value sys_hps_ddr4_cntrl {MEM_DDR4_READ_DBI} {1} +set_instance_parameter_value sys_hps_ddr4_cntrl {MEM_DDR4_TCL} {20} +set_instance_parameter_value sys_hps_ddr4_cntrl {MEM_DDR4_WTCL} {18} +set_instance_parameter_value sys_hps_ddr4_cntrl {MEM_DDR4_RTT_NOM_ENUM} {DDR4_RTT_NOM_RZQ_6} +set_instance_parameter_value sys_hps_ddr4_cntrl {PHY_DDR4_DEFAULT_IO} {0} +set_instance_parameter_value sys_hps_ddr4_cntrl {PHY_DDR4_USER_AC_IO_STD_ENUM} {IO_STD_SSTL_12} +set_instance_parameter_value sys_hps_ddr4_cntrl {PHY_DDR4_USER_AC_MODE_ENUM} {OUT_OCT_40_CAL} +set_instance_parameter_value sys_hps_ddr4_cntrl {PHY_DDR4_USER_CK_IO_STD_ENUM} {IO_STD_SSTL_12} +set_instance_parameter_value sys_hps_ddr4_cntrl {PHY_DDR4_USER_CK_MODE_ENUM} {OUT_OCT_40_CAL} +set_instance_parameter_value sys_hps_ddr4_cntrl {PHY_DDR4_USER_DATA_IO_STD_ENUM} {IO_STD_POD_12} +set_instance_parameter_value sys_hps_ddr4_cntrl {PHY_DDR4_USER_DATA_OUT_MODE_ENUM} {OUT_OCT_34_CAL} +set_instance_parameter_value sys_hps_ddr4_cntrl {PHY_DDR4_USER_DATA_IN_MODE_ENUM} {IN_OCT_60_CAL} +set_instance_parameter_value sys_hps_ddr4_cntrl {PHY_DDR4_USER_PLL_REF_CLK_IO_STD_ENUM} {IO_STD_CMOS_12} +set_instance_parameter_value sys_hps_ddr4_cntrl {PHY_DDR4_USER_RZQ_IO_STD_ENUM} {IO_STD_CMOS_12} +set_instance_parameter_value sys_hps_ddr4_cntrl {MEM_DDR4_SPEEDBIN_ENUM} {DDR4_SPEEDBIN_2666} +set_instance_parameter_value sys_hps_ddr4_cntrl {MEM_DDR4_TRCD_NS} {14.25} +set_instance_parameter_value sys_hps_ddr4_cntrl {MEM_DDR4_TRP_NS} {14.25} +set_instance_parameter_value sys_hps_ddr4_cntrl {MEM_DDR4_TRRD_S_CYC} {7} +set_instance_parameter_value sys_hps_ddr4_cntrl {MEM_DDR4_TRRD_L_CYC} {8} +set_instance_parameter_value sys_hps_ddr4_cntrl {MEM_DDR4_TFAW_NS} {30.0} +set_instance_parameter_value sys_hps_ddr4_cntrl {MEM_DDR4_TWTR_S_CYC} {4} +set_instance_parameter_value sys_hps_ddr4_cntrl {MEM_DDR4_TWTR_L_CYC} {10} +set_instance_parameter_value sys_hps_ddr4_cntrl {MEM_DDR4_LRDIMM_VREFDQ_VALUE} {1D} +set_instance_parameter_value sys_hps_ddr4_cntrl {DIAG_DDR4_SKIP_CA_LEVEL} {1} +set_instance_parameter_value sys_hps_ddr4_cntrl {SHORT_QSYS_INTERFACE_NAMES} {0} + +add_interface sys_hps_ddr_rstn reset sink +set_interface_property sys_hps_ddr_rstn EXPORT_OF sys_hps_ddr4_cntrl.global_reset_reset_sink +add_connection sys_hps_ddr4_cntrl.hps_emif_conduit_end sys_hps.emif +add_interface sys_hps_ddr conduit end +set_interface_property sys_hps_ddr EXPORT_OF sys_hps_ddr4_cntrl.mem_conduit_end +add_interface sys_hps_ddr_oct conduit end +set_interface_property sys_hps_ddr_oct EXPORT_OF sys_hps_ddr4_cntrl.oct_conduit_end +add_interface sys_hps_ddr_ref_clk clock sink +set_interface_property sys_hps_ddr_ref_clk EXPORT_OF sys_hps_ddr4_cntrl.pll_ref_clk_clock_sink + +# cpu/hps handling + +proc ad_cpu_interrupt {m_irq m_port} { + + add_connection sys_hps.f2h_irq0 ${m_port} + set_connection_parameter_value sys_hps.f2h_irq0/${m_port} irqNumber ${m_irq} +} + +proc ad_cpu_interconnect {m_base m_port} { + + add_connection sys_hps.h2f_lw_axi_master ${m_port} + set_connection_parameter_value sys_hps.h2f_lw_axi_master/${m_port} baseAddress ${m_base} +} + +proc ad_dma_interconnect {m_port} { + + add_connection ${m_port} sys_hps.f2sdram0_data + set_connection_parameter_value ${m_port}/sys_hps.f2sdram0_data baseAddress {0x0} +} + +# common dma interfaces + +add_instance sys_dma_clk clock_source 16.0 +add_connection sys_hps.h2f_user0_clock sys_dma_clk.clk_in +add_connection sys_clk.clk_reset sys_dma_clk.clk_in_reset + +# gpio-in + +add_instance sys_gpio_in altera_avalon_pio 16.0 +set_instance_parameter_value sys_gpio_in {direction} {Input} +set_instance_parameter_value sys_gpio_in {generateIRQ} {1} +set_instance_parameter_value sys_gpio_in {width} {32} + +add_connection sys_clk.clk_reset sys_gpio_in.reset +add_connection sys_clk.clk sys_gpio_in.clk +add_interface sys_gpio_in conduit end +set_interface_property sys_gpio_in EXPORT_OF sys_gpio_in.external_connection + +# gpio-out + +add_instance sys_gpio_out altera_avalon_pio 16.0 +set_instance_parameter_value sys_gpio_out {direction} {Output} +set_instance_parameter_value sys_gpio_out {generateIRQ} {0} +set_instance_parameter_value sys_gpio_out {width} {32} + +add_connection sys_clk.clk_reset sys_gpio_out.reset +add_connection sys_clk.clk sys_gpio_out.clk +add_interface sys_gpio_out conduit end +set_interface_property sys_gpio_out EXPORT_OF sys_gpio_out.external_connection + +# spi + +add_instance sys_spi altera_avalon_spi 16.0 +set_instance_parameter_value sys_spi {clockPhase} {0} +set_instance_parameter_value sys_spi {clockPolarity} {0} +set_instance_parameter_value sys_spi {dataWidth} {8} +set_instance_parameter_value sys_spi {masterSPI} {1} +set_instance_parameter_value sys_spi {numberOfSlaves} {8} +set_instance_parameter_value sys_spi {targetClockRate} {128000.0} + +add_connection sys_clk.clk_reset sys_spi.reset +add_connection sys_clk.clk sys_spi.clk +add_interface sys_spi conduit end +set_interface_property sys_spi EXPORT_OF sys_spi.external + +# base-addresses + +ad_cpu_interconnect 0x00000000 sys_gpio_in.s1 +ad_cpu_interconnect 0x00000020 sys_gpio_out.s1 +ad_cpu_interconnect 0x00000040 sys_spi.spi_control_port + +# interrupts + +ad_cpu_interrupt 5 sys_gpio_in.irq +ad_cpu_interrupt 7 sys_spi.irq + diff --git a/projects/common/a5gt/a5gt_system_assign.tcl b/projects/common/a5gt/a5gt_system_assign.tcl index c26253e51..2247d763c 100644 --- a/projects/common/a5gt/a5gt_system_assign.tcl +++ b/projects/common/a5gt/a5gt_system_assign.tcl @@ -659,42 +659,6 @@ set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING - set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[30] set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[31] -set_instance_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION_FOR_NON_GLOBAL_CLOCKS ON -to i_system_bd|sys_ddr3_cntrl - -set_instance_assignment -name GLOBAL_SIGNAL "DUAL-REGIONAL CLOCK" -to i_system_bd|sys_ddr3_cntrl|pll0|pll_addr_cmd_clk -set_instance_assignment -name GLOBAL_SIGNAL "DUAL-REGIONAL CLOCK" -to i_system_bd|sys_ddr3_cntrl|pll0|pll_avl_clk -set_instance_assignment -name GLOBAL_SIGNAL "DUAL-REGIONAL CLOCK" -to i_system_bd|sys_ddr3_cntrl|pll0|pll_config_clk -set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to i_system_bd|sys_ddr3_cntrl|pll0|pll_afi_clk -set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to i_system_bd|sys_ddr3_cntrl|pll0|pll_hr_clk - -set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_system_bd|sys_ddr3_cntrl|p0|umemphy|uio_pads|dq_ddio[0].read_capture_clk_buffer -set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_system_bd|sys_ddr3_cntrl|p0|umemphy|uio_pads|dq_ddio[1].read_capture_clk_buffer -set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_system_bd|sys_ddr3_cntrl|p0|umemphy|uio_pads|dq_ddio[2].read_capture_clk_buffer -set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_system_bd|sys_ddr3_cntrl|p0|umemphy|uio_pads|dq_ddio[3].read_capture_clk_buffer -set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_system_bd|sys_ddr3_cntrl|p0|umemphy|uio_pads|dq_ddio[4].read_capture_clk_buffer -set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_system_bd|sys_ddr3_cntrl|p0|umemphy|uio_pads|dq_ddio[5].read_capture_clk_buffer -set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_system_bd|sys_ddr3_cntrl|p0|umemphy|uio_pads|dq_ddio[6].read_capture_clk_buffer -set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_system_bd|sys_ddr3_cntrl|p0|umemphy|uio_pads|dq_ddio[7].read_capture_clk_buffer -set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_system_bd|sys_ddr3_cntrl|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[0] -set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_system_bd|sys_ddr3_cntrl|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[1] -set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_system_bd|sys_ddr3_cntrl|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[2] -set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_system_bd|sys_ddr3_cntrl|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[3] -set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_system_bd|sys_ddr3_cntrl|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[4] -set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_system_bd|sys_ddr3_cntrl|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[5] -set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_system_bd|sys_ddr3_cntrl|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[6] -set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_system_bd|sys_ddr3_cntrl|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[7] -set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_system_bd|sys_ddr3_cntrl|p0|umemphy|uread_datapath|reset_n_fifo_write_side[0] -set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_system_bd|sys_ddr3_cntrl|p0|umemphy|uread_datapath|reset_n_fifo_write_side[1] -set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_system_bd|sys_ddr3_cntrl|p0|umemphy|uread_datapath|reset_n_fifo_write_side[2] -set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_system_bd|sys_ddr3_cntrl|p0|umemphy|uread_datapath|reset_n_fifo_write_side[3] -set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_system_bd|sys_ddr3_cntrl|p0|umemphy|uread_datapath|reset_n_fifo_write_side[4] -set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_system_bd|sys_ddr3_cntrl|p0|umemphy|uread_datapath|reset_n_fifo_write_side[5] -set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_system_bd|sys_ddr3_cntrl|p0|umemphy|uread_datapath|reset_n_fifo_write_side[6] -set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_system_bd|sys_ddr3_cntrl|p0|umemphy|uread_datapath|reset_n_fifo_write_side[7] -set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_system_bd|sys_ddr3_cntrl|p0|umemphy|ureset|phy_reset_mem_stable_n -set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_system_bd|sys_ddr3_cntrl|p0|umemphy|ureset|phy_reset_n -set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_system_bd|sys_ddr3_cntrl|s0|sequencer_rw_mgr_inst|rw_mgr_inst|rw_mgr_core_inst|rw_soft_reset_n - # ethernet interface set_location_assignment PIN_A6 -to eth_rx_clk @@ -751,70 +715,113 @@ set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to eth_rx_clk # leds -set_location_assignment PIN_M19 -to gpio_bd[0] ; ## led_grn[0] -set_location_assignment PIN_L19 -to gpio_bd[1] ; ## led_grn[1] -set_location_assignment PIN_K19 -to gpio_bd[2] ; ## led_grn[2] -set_location_assignment PIN_J19 -to gpio_bd[3] ; ## led_grn[3] -set_location_assignment PIN_K20 -to gpio_bd[4] ; ## led_grn[4] -set_location_assignment PIN_J20 -to gpio_bd[5] ; ## led_grn[5] -set_location_assignment PIN_T20 -to gpio_bd[6] ; ## led_grn[6] -set_location_assignment PIN_R20 -to gpio_bd[7] ; ## led_grn[7] -set_location_assignment PIN_N20 -to gpio_bd[8] ; ## led_red[0] -set_location_assignment PIN_C15 -to gpio_bd[9] ; ## led_red[1] -set_location_assignment PIN_AL28 -to gpio_bd[10] ; ## led_red[2] -set_location_assignment PIN_F11 -to gpio_bd[11] ; ## led_red[3] -set_location_assignment PIN_AJ31 -to gpio_bd[12] ; ## led_red[4] -set_location_assignment PIN_AN34 -to gpio_bd[13] ; ## led_red[5] -set_location_assignment PIN_AJ34 -to gpio_bd[14] ; ## led_red[6] -set_location_assignment PIN_AK33 -to gpio_bd[15] ; ## led_red[7] -set_location_assignment PIN_C8 -to gpio_bd[16] ; ## dip_switches[0] -set_location_assignment PIN_D8 -to gpio_bd[17] ; ## dip_switches[1] -set_location_assignment PIN_E7 -to gpio_bd[18] ; ## dip_switches[2] -set_location_assignment PIN_E6 -to gpio_bd[19] ; ## dip_switches[3] -set_location_assignment PIN_G8 -to gpio_bd[20] ; ## dip_switches[4] -set_location_assignment PIN_F8 -to gpio_bd[21] ; ## dip_switches[5] -set_location_assignment PIN_D15 -to gpio_bd[22] ; ## dip_switches[6] -set_location_assignment PIN_G11 -to gpio_bd[23] ; ## dip_switches[7] -set_location_assignment PIN_D6 -to gpio_bd[24] ; ## push_buttons[0] -set_location_assignment PIN_C6 -to gpio_bd[25] ; ## push_buttons[1] -set_location_assignment PIN_K7 -to gpio_bd[26] ; ## push_buttons[2] +set_location_assignment PIN_M19 -to gpio_bd_o[0] ; ## led_grn[0] +set_location_assignment PIN_L19 -to gpio_bd_o[1] ; ## led_grn[1] +set_location_assignment PIN_K19 -to gpio_bd_o[2] ; ## led_grn[2] +set_location_assignment PIN_J19 -to gpio_bd_o[3] ; ## led_grn[3] +set_location_assignment PIN_K20 -to gpio_bd_o[4] ; ## led_grn[4] +set_location_assignment PIN_J20 -to gpio_bd_o[5] ; ## led_grn[5] +set_location_assignment PIN_T20 -to gpio_bd_o[6] ; ## led_grn[6] +set_location_assignment PIN_R20 -to gpio_bd_o[7] ; ## led_grn[7] +set_location_assignment PIN_N20 -to gpio_bd_o[8] ; ## led_red[0] +set_location_assignment PIN_C15 -to gpio_bd_o[9] ; ## led_red[1] +set_location_assignment PIN_AL28 -to gpio_bd_o[10] ; ## led_red[2] +set_location_assignment PIN_F11 -to gpio_bd_o[11] ; ## led_red[3] +set_location_assignment PIN_AJ31 -to gpio_bd_o[12] ; ## led_red[4] +set_location_assignment PIN_AN34 -to gpio_bd_o[13] ; ## led_red[5] +set_location_assignment PIN_AJ34 -to gpio_bd_o[14] ; ## led_red[6] +set_location_assignment PIN_AK33 -to gpio_bd_o[15] ; ## led_red[7] +set_location_assignment PIN_C8 -to gpio_bd_i[0] ; ## dip_switches[0] +set_location_assignment PIN_D8 -to gpio_bd_i[1] ; ## dip_switches[1] +set_location_assignment PIN_E7 -to gpio_bd_i[2] ; ## dip_switches[2] +set_location_assignment PIN_E6 -to gpio_bd_i[3] ; ## dip_switches[3] +set_location_assignment PIN_G8 -to gpio_bd_i[4] ; ## dip_switches[4] +set_location_assignment PIN_F8 -to gpio_bd_i[5] ; ## dip_switches[5] +set_location_assignment PIN_D15 -to gpio_bd_i[6] ; ## dip_switches[6] +set_location_assignment PIN_G11 -to gpio_bd_i[7] ; ## dip_switches[7] +set_location_assignment PIN_D6 -to gpio_bd_i[8] ; ## push_buttons[0] +set_location_assignment PIN_C6 -to gpio_bd_i[9] ; ## push_buttons[1] +set_location_assignment PIN_K7 -to gpio_bd_i[10] ; ## push_buttons[2] -set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd[0] -set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd[1] -set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd[2] -set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd[3] -set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd[4] -set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd[5] -set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd[6] -set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd[7] -set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd[8] -set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd[9] -set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd[10] -set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd[11] -set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd[12] -set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd[13] -set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd[14] -set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd[15] -set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd[16] -set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd[17] -set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd[18] -set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd[19] -set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd[20] -set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd[21] -set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd[22] -set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd[23] -set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd[24] -set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd[25] -set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd[26] +set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd_o[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd_o[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd_o[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd_o[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd_o[4] +set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd_o[5] +set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd_o[6] +set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd_o[7] +set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd_o[8] +set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd_o[9] +set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd_o[10] +set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd_o[11] +set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd_o[12] +set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd_o[13] +set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd_o[14] +set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd_o[15] +set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd_i[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd_i[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd_i[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd_i[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd_i[4] +set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd_i[5] +set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd_i[6] +set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd_i[7] +set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd_i[8] +set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd_i[9] +set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd_i[10] -# globals +set_instance_assignment -name OPTIMIZATION_TECHNIQUE SPEED -to * +set_instance_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON -to * -set_global_assignment -name SYNCHRONIZER_IDENTIFICATION AUTO -set_global_assignment -name ENABLE_ADVANCED_IO_TIMING ON -set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER ON -set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON -set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON -set_global_assignment -name TIMEQUEST_REPORT_SCRIPT $ad_hdl_dir/projects/scripts/adi_tquest.tcl -set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION OFF +set_location_assignment FF_X25_Y136_N31 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:ucke_qr_to_hr|dataout_r[0][0] +set_location_assignment FF_X25_Y136_N1 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:ucke_qr_to_hr|dataout_r[0][1] +set_location_assignment FF_X15_Y136_N56 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:ucs_n_qr_to_hr|dataout_r[0][0] +set_location_assignment FF_X15_Y136_N2 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:ucs_n_qr_to_hr|dataout_r[0][1] +set_location_assignment FF_X18_Y136_N5 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:ubank_qr_to_hr|dataout_r[0][0] +set_location_assignment FF_X18_Y136_N14 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:ubank_qr_to_hr|dataout_r[0][1] +set_location_assignment FF_X18_Y136_N35 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:ubank_qr_to_hr|dataout_r[0][2] +set_location_assignment FF_X18_Y136_N56 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:ubank_qr_to_hr|dataout_r[0][3] +set_location_assignment FF_X18_Y136_N38 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:ubank_qr_to_hr|dataout_r[0][4] +set_location_assignment FF_X18_Y136_N29 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:ubank_qr_to_hr|dataout_r[0][5] +set_location_assignment FF_X25_Y136_N14 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uaddress_qr_to_hr|dataout_r[0][0] +set_location_assignment FF_X25_Y136_N17 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uaddress_qr_to_hr|dataout_r[0][1] +set_location_assignment FF_X25_Y136_N50 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uaddress_qr_to_hr|dataout_r[0][2] +set_location_assignment FF_X25_Y136_N44 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uaddress_qr_to_hr|dataout_r[0][3] +set_location_assignment FF_X21_Y136_N31 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uaddress_qr_to_hr|dataout_r[0][4] +set_location_assignment FF_X21_Y136_N55 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uaddress_qr_to_hr|dataout_r[0][5] +set_location_assignment FF_X21_Y136_N43 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uaddress_qr_to_hr|dataout_r[0][6] +set_location_assignment FF_X21_Y136_N16 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uaddress_qr_to_hr|dataout_r[0][7] +set_location_assignment FF_X20_Y136_N13 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uaddress_qr_to_hr|dataout_r[0][8] +set_location_assignment FF_X20_Y136_N37 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uaddress_qr_to_hr|dataout_r[0][9] +set_location_assignment FF_X20_Y136_N43 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uaddress_qr_to_hr|dataout_r[0][10] +set_location_assignment FF_X20_Y136_N55 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uaddress_qr_to_hr|dataout_r[0][11] +set_location_assignment FF_X18_Y136_N22 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uaddress_qr_to_hr|dataout_r[0][12] +set_location_assignment FF_X25_Y136_N41 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uaddress_qr_to_hr|dataout_r[0][13] +set_location_assignment FF_X25_Y136_N38 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uaddress_qr_to_hr|dataout_r[0][14] +set_location_assignment FF_X25_Y136_N35 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uaddress_qr_to_hr|dataout_r[0][15] +set_location_assignment FF_X25_Y136_N8 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uaddress_qr_to_hr|dataout_r[0][16] +set_location_assignment FF_X21_Y136_N58 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uaddress_qr_to_hr|dataout_r[0][17] +set_location_assignment FF_X21_Y136_N40 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uaddress_qr_to_hr|dataout_r[0][18] +set_location_assignment FF_X21_Y136_N7 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uaddress_qr_to_hr|dataout_r[0][19] +set_location_assignment FF_X21_Y136_N49 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uaddress_qr_to_hr|dataout_r[0][20] +set_location_assignment FF_X20_Y136_N7 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uaddress_qr_to_hr|dataout_r[0][21] +set_location_assignment FF_X20_Y136_N49 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uaddress_qr_to_hr|dataout_r[0][22] +set_location_assignment FF_X20_Y136_N25 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uaddress_qr_to_hr|dataout_r[0][23] +set_location_assignment FF_X20_Y136_N31 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uaddress_qr_to_hr|dataout_r[0][24] +set_location_assignment FF_X18_Y136_N49 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uaddress_qr_to_hr|dataout_r[0][25] +set_location_assignment FF_X28_Y136_N47 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:ureset_n_qr_to_hr|dataout_r[0][0] +set_location_assignment FF_X28_Y136_N26 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:ureset_n_qr_to_hr|dataout_r[0][1] +set_location_assignment FF_X18_Y136_N47 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uras_n_qr_to_hr|dataout_r[0][0] +set_location_assignment FF_X18_Y136_N8 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uras_n_qr_to_hr|dataout_r[0][1] +set_location_assignment FF_X15_Y136_N7 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:ucas_n_qr_to_hr|dataout_r[0][0] +set_location_assignment FF_X15_Y136_N34 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:ucas_n_qr_to_hr|dataout_r[0][1] +set_location_assignment FF_X15_Y136_N52 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uwe_n_qr_to_hr|dataout_r[0][0] +set_location_assignment FF_X15_Y136_N40 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uwe_n_qr_to_hr|dataout_r[0][1] +set_location_assignment FF_X15_Y136_N13 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uodt_qr_to_hr|dataout_r[0][0] +set_location_assignment FF_X15_Y136_N43 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uodt_qr_to_hr|dataout_r[0][1] +# source defaults + +source $ad_hdl_dir/projects/common/altera/sys_gen.tcl diff --git a/projects/common/a5gt/a5gt_system_bd.qsys b/projects/common/a5gt/a5gt_system_bd.qsys deleted file mode 100644 index 37f968cb1..000000000 --- a/projects/common/a5gt/a5gt_system_bd.qsys +++ /dev/null @@ -1,2326 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - sys_cpu.jtag_debug_module - - - - - - - - - - - - - ]]> - - - - - - - - - - - - - - - - - - - - - - ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 1 HARDCOPY 0 HAS_18_BIT_MULTS 1 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 1 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 1 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 0 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 1 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 0 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 1 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 0 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 1 M144K_MEMORY 1 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 1 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 1 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 1 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 1 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 1 TRANSCEIVER_6G_BLOCK 1 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 1 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1 - - - - - - - - - - - - - - - - - ]]> - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ]]> - - - - - - - - ]]> - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ]]> - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ]]> - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - $${FILENAME}_sys_int_mem - - - - - ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 1 HARDCOPY 0 HAS_18_BIT_MULTS 1 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 1 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 1 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 0 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 1 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 0 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 1 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 0 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 1 M144K_MEMORY 1 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 1 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 1 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 1 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 1 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 1 TRANSCEIVER_6G_BLOCK 1 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 1 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Create an adjpllin signal to connect with an upstream PLL - - - - - - - - - - - - - - - - - - - - - - - - Automatic Switchover - - - - - - - - - - - - - - - - - - - - - - - - - - - - $${FILENAME}_sys_tcm_mem - - - - - ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 1 HARDCOPY 0 HAS_18_BIT_MULTS 1 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 1 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 1 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 0 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 1 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 0 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 1 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 0 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 1 M144K_MEMORY 1 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 1 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 1 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 1 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 1 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 1 TRANSCEIVER_6G_BLOCK 1 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 1 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - NO_INTERACTIVE_WINDOWS - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/projects/common/a5gt/a5gt_system_qsys.tcl b/projects/common/a5gt/a5gt_system_qsys.tcl new file mode 100644 index 000000000..9ff874d16 --- /dev/null +++ b/projects/common/a5gt/a5gt_system_qsys.tcl @@ -0,0 +1,364 @@ + +package require qsys + +set_module_property NAME {system_bd} +set_project_property DEVICE_FAMILY {Arria V} +set_project_property DEVICE {5AGTFD7K3F40I3} + +set system_type nios + +# clock-&-reset + +add_instance sys_ref_clk clock_source 16.0 +add_interface sys_ref_clk clock sink +add_interface sys_ref_rst reset sink +set_interface_property sys_ref_clk EXPORT_OF sys_ref_clk.clk_in +set_interface_property sys_ref_rst EXPORT_OF sys_ref_clk.clk_in_reset +set_instance_parameter_value sys_ref_clk {clockFrequency} {100000000.0} +set_instance_parameter_value sys_ref_clk {clockFrequencyKnown} {1} +set_instance_parameter_value sys_ref_clk {resetSynchronousEdges} {DEASSERT} + +add_instance sys_clk clock_source 16.0 +add_interface sys_clk clock sink +add_interface sys_rst reset sink +set_interface_property sys_clk EXPORT_OF sys_clk.clk_in +set_interface_property sys_rst EXPORT_OF sys_clk.clk_in_reset +set_instance_parameter_value sys_clk {clockFrequency} {50000000.0} +set_instance_parameter_value sys_clk {clockFrequencyKnown} {1} +set_instance_parameter_value sys_clk {resetSynchronousEdges} {DEASSERT} + +# system-pll + +add_instance sys_pll altera_pll 16.0 +set_instance_parameter_value sys_pll {gui_reference_clock_frequency} {100.0} +set_instance_parameter_value sys_pll {gui_use_locked} {1} +set_instance_parameter_value sys_pll {gui_number_of_clocks} {3} +set_instance_parameter_value sys_pll {gui_output_clock_frequency0} {125.0} +set_instance_parameter_value sys_pll {gui_output_clock_frequency1} {25.0} +set_instance_parameter_value sys_pll {gui_output_clock_frequency2} {2.5} +add_connection sys_ref_clk.clk sys_pll.refclk +add_connection sys_ref_clk.clk_reset sys_pll.reset +add_interface sys_125m_clk clock source +add_interface sys_25m_clk clock source +add_interface sys_2m5_clk clock source +add_interface sys_pll_locked conduit end +set_interface_property sys_125m_clk EXPORT_OF sys_pll.outclk0 +set_interface_property sys_25m_clk EXPORT_OF sys_pll.outclk1 +set_interface_property sys_2m5_clk EXPORT_OF sys_pll.outclk2 +set_interface_property sys_pll_locked EXPORT_OF sys_pll.locked + +# memory (int) + +add_instance sys_int_mem altera_avalon_onchip_memory2 16.0 +set_instance_parameter_value sys_int_mem {dataWidth} {32} +set_instance_parameter_value sys_int_mem {dualPort} {0} +set_instance_parameter_value sys_int_mem {initMemContent} {0} +set_instance_parameter_value sys_int_mem {memorySize} {163840.0} +add_connection sys_clk.clk sys_int_mem.clk1 +add_connection sys_clk.clk_reset sys_int_mem.reset1 + +# memory (tlb) + +add_instance sys_tlb_mem altera_avalon_onchip_memory2 16.0 +set_instance_parameter_value sys_tlb_mem {dataWidth} {32} +set_instance_parameter_value sys_tlb_mem {dualPort} {1} +set_instance_parameter_value sys_tlb_mem {initMemContent} {1} +set_instance_parameter_value sys_tlb_mem {memorySize} {163840.0} +add_connection sys_clk.clk sys_tlb_mem.clk1 +add_connection sys_clk.clk_reset sys_tlb_mem.reset1 +add_connection sys_clk.clk sys_tlb_mem.clk2 +add_connection sys_clk.clk_reset sys_tlb_mem.reset2 + +# memory (ddr) + +add_instance sys_ddr3_cntrl altera_mem_if_ddr3_emif 16.0 +set_instance_parameter_value sys_ddr3_cntrl {SPEED_GRADE} {3} +set_instance_parameter_value sys_ddr3_cntrl {MEM_CLK_FREQ} {400.0} +set_instance_parameter_value sys_ddr3_cntrl {REF_CLK_FREQ} {100.0} +set_instance_parameter_value sys_ddr3_cntrl {RATE} {Quarter} +set_instance_parameter_value sys_ddr3_cntrl {EXPORT_AFI_HALF_CLK} {1} +set_instance_parameter_value sys_ddr3_cntrl {MEM_VENDOR} {Micron} +set_instance_parameter_value sys_ddr3_cntrl {MEM_CLK_FREQ_MAX} {666.667} +set_instance_parameter_value sys_ddr3_cntrl {MEM_DQ_WIDTH} {64} +set_instance_parameter_value sys_ddr3_cntrl {MEM_ROW_ADDR_WIDTH} {12} +set_instance_parameter_value sys_ddr3_cntrl {MEM_COL_ADDR_WIDTH} {10} +set_instance_parameter_value sys_ddr3_cntrl {MEM_TCL} {11} +set_instance_parameter_value sys_ddr3_cntrl {MEM_RTT_NOM} {RZQ/6} +set_instance_parameter_value sys_ddr3_cntrl {MEM_WTCL} {8} +set_instance_parameter_value sys_ddr3_cntrl {MEM_RTT_WR} {RZQ/4} +set_instance_parameter_value sys_ddr3_cntrl {TIMING_TIS} {170} +set_instance_parameter_value sys_ddr3_cntrl {TIMING_TIH} {120} +set_instance_parameter_value sys_ddr3_cntrl {TIMING_TDS} {10} +set_instance_parameter_value sys_ddr3_cntrl {TIMING_TDH} {45} +set_instance_parameter_value sys_ddr3_cntrl {TIMING_TDQSQ} {100} +set_instance_parameter_value sys_ddr3_cntrl {TIMING_TQH} {0.38} +set_instance_parameter_value sys_ddr3_cntrl {TIMING_TDQSCK} {255} +set_instance_parameter_value sys_ddr3_cntrl {TIMING_TDQSS} {0.27} +set_instance_parameter_value sys_ddr3_cntrl {TIMING_TQSH} {0.4} +set_instance_parameter_value sys_ddr3_cntrl {TIMING_TDSH} {0.18} +set_instance_parameter_value sys_ddr3_cntrl {TIMING_TDSS} {0.18} +set_instance_parameter_value sys_ddr3_cntrl {MEM_TINIT_US} {500} +set_instance_parameter_value sys_ddr3_cntrl {MEM_TMRD_CK} {4} +set_instance_parameter_value sys_ddr3_cntrl {MEM_TRAS_NS} {35.0} +set_instance_parameter_value sys_ddr3_cntrl {MEM_TRCD_NS} {13.75} +set_instance_parameter_value sys_ddr3_cntrl {MEM_TRP_NS} {13.75} +set_instance_parameter_value sys_ddr3_cntrl {MEM_TREFI_US} {7.8} +set_instance_parameter_value sys_ddr3_cntrl {MEM_TRFC_NS} {110.0} +set_instance_parameter_value sys_ddr3_cntrl {MEM_TWR_NS} {15.0} +set_instance_parameter_value sys_ddr3_cntrl {MEM_TWTR} {6} +set_instance_parameter_value sys_ddr3_cntrl {MEM_TFAW_NS} {30.0} +set_instance_parameter_value sys_ddr3_cntrl {MEM_TRRD_NS} {6.0} +set_instance_parameter_value sys_ddr3_cntrl {MEM_TRTP_NS} {7.5} +set_instance_parameter_value sys_ddr3_cntrl {AVL_MAX_SIZE} {256} +add_connection sys_ref_clk.clk sys_ddr3_cntrl.pll_ref_clk +add_connection sys_ref_clk.clk_reset sys_ddr3_cntrl.global_reset +add_connection sys_ref_clk.clk_reset sys_ddr3_cntrl.soft_reset +add_interface sys_ddr3_cntrl_mem conduit end +set_interface_property sys_ddr3_cntrl_mem EXPORT_OF sys_ddr3_cntrl.memory +add_interface sys_ddr3_cntrl_oct conduit end +set_interface_property sys_ddr3_cntrl_oct EXPORT_OF sys_ddr3_cntrl.oct + +# cpu clock + +add_instance sys_cpu_clk clock_source 16.0 +add_connection sys_ddr3_cntrl.afi_half_clk sys_cpu_clk.clk_in +add_connection sys_ddr3_cntrl.afi_reset sys_cpu_clk.clk_in_reset +add_interface sys_cpu_clk clock source +set_interface_property sys_cpu_clk EXPORT_OF sys_cpu_clk.clk +add_interface sys_cpu_reset reset source +set_interface_property sys_cpu_reset EXPORT_OF sys_cpu_clk.clk_reset + +# cpu + +add_instance sys_cpu altera_nios2_gen2 16.0 +set_instance_parameter_value sys_cpu {setting_support31bitdcachebypass} {0} +set_instance_parameter_value sys_cpu {setting_activateTrace} {1} +set_instance_parameter_value sys_cpu {mmu_autoAssignTlbPtrSz} {0} +set_instance_parameter_value sys_cpu {mmu_TLBMissExcOffset} {4096} +set_instance_parameter_value sys_cpu {resetSlave} {sys_ddr3_cntrl.avl} +set_instance_parameter_value sys_cpu {mmu_TLBMissExcSlave} {sys_tlb_mem.s2} +set_instance_parameter_value sys_cpu {exceptionSlave} {sys_ddr3_cntrl.avl} +set_instance_parameter_value sys_cpu {breakSlave} {sys_cpu.jtag_debug_module} +set_instance_parameter_value sys_cpu {mul_32_impl} {3} +set_instance_parameter_value sys_cpu {shift_rot_impl} {0} +set_instance_parameter_value sys_cpu {icache_size} {32768} +set_instance_parameter_value sys_cpu {icache_numTCIM} {1} +set_instance_parameter_value sys_cpu {dcache_size} {32768} +set_instance_parameter_value sys_cpu {dcache_numTCDM} {1} +set_instance_parameter_value sys_cpu {setting_dc_ecc_present} {0} +set_instance_parameter_value sys_cpu {setting_itcm_ecc_present} {0} +set_instance_parameter_value sys_cpu {setting_dtcm_ecc_present} {0} +set_instance_parameter_value sys_cpu {mmu_enabled} $mmu_enabled +add_connection sys_clk.clk sys_cpu.clk +add_connection sys_clk.clk_reset sys_cpu.reset +add_connection sys_cpu.debug_reset_request sys_cpu.reset +add_connection sys_cpu.instruction_master sys_cpu.debug_mem_slave +add_connection sys_cpu.instruction_master sys_int_mem.s1 +add_connection sys_cpu.tightly_coupled_instruction_master_0 sys_tlb_mem.s2 +add_connection sys_cpu.tightly_coupled_data_master_0 sys_tlb_mem.s1 +add_connection sys_cpu.instruction_master sys_ddr3_cntrl.avl +add_connection sys_cpu.data_master sys_ddr3_cntrl.avl +set_connection_parameter_value sys_cpu.data_master/sys_ddr3_cntrl.avl baseAddress {0x0} +set_connection_parameter_value sys_cpu.instruction_master/sys_ddr3_cntrl.avl baseAddress {0x0} +set_connection_parameter_value sys_cpu.instruction_master/sys_cpu.debug_mem_slave baseAddress {0x10180800} +set_connection_parameter_value sys_cpu.instruction_master/sys_int_mem.s1 baseAddress {0x10140000} +set_connection_parameter_value sys_cpu.tightly_coupled_instruction_master_0/sys_tlb_mem.s2 baseAddress {0x10200000} +set_connection_parameter_value sys_cpu.tightly_coupled_data_master_0/sys_tlb_mem.s1 baseAddress {0x10200000} + +# cpu/hps handling + +proc ad_cpu_interrupt {m_irq m_port} { + + add_connection sys_cpu.irq ${m_port} + set_connection_parameter_value sys_cpu.irq/${m_port} irqNumber ${m_irq} +} + +proc ad_cpu_interconnect {m_base m_port} { + + add_connection sys_cpu.data_master ${m_port} + set_connection_parameter_value sys_cpu.data_master/${m_port} baseAddress [expr ($m_base + 0x10000000)] +} + +proc ad_dma_interconnect {m_port} { + + add_connection ${m_port} sys_ddr3_cntrl.avl + set_connection_parameter_value ${m_port}/sys_ddr3_cntrl.avl baseAddress {0x0} +} + +# common dma interfaces + +add_instance sys_dma_clk clock_source 16.0 +add_connection sys_ddr3_cntrl.afi_clk sys_dma_clk.clk_in +add_connection sys_ddr3_cntrl.afi_reset sys_dma_clk.clk_in_reset + +# ethernet + +add_instance sys_ethernet altera_eth_tse 16.0 +set_instance_parameter_value sys_ethernet {core_variation} {MAC_ONLY} +set_instance_parameter_value sys_ethernet {ifGMII} {RGMII} +set_instance_parameter_value sys_ethernet {enable_mac_flow_ctrl} {1} +set_instance_parameter_value sys_ethernet {useMDIO} {1} +set_instance_parameter_value sys_ethernet {mdio_clk_div} {30} + +add_instance sys_ethernet_dma_rx altera_msgdma 16.0 +set_instance_parameter_value sys_ethernet_dma_rx {MODE} {2} +set_instance_parameter_value sys_ethernet_dma_rx {DATA_WIDTH} {64} +set_instance_parameter_value sys_ethernet_dma_rx {DATA_FIFO_DEPTH} {256} +set_instance_parameter_value sys_ethernet_dma_rx {DESCRIPTOR_FIFO_DEPTH} {512} +set_instance_parameter_value sys_ethernet_dma_rx {RESPONSE_PORT} {0} +set_instance_parameter_value sys_ethernet_dma_rx {MAX_BYTE} {2048} +set_instance_parameter_value sys_ethernet_dma_rx {TRANSFER_TYPE} {Unaligned Accesses} +set_instance_parameter_value sys_ethernet_dma_rx {BURST_ENABLE} {1} +set_instance_parameter_value sys_ethernet_dma_rx {MAX_BURST_COUNT} {64} +set_instance_parameter_value sys_ethernet_dma_rx {ENHANCED_FEATURES} {1} +set_instance_parameter_value sys_ethernet_dma_rx {PACKET_ENABLE} {1} +set_instance_parameter_value sys_ethernet_dma_rx {ERROR_ENABLE} {1} +set_instance_parameter_value sys_ethernet_dma_rx {ERROR_WIDTH} {6} + +add_instance sys_ethernet_dma_tx altera_msgdma 16.0 +set_instance_parameter_value sys_ethernet_dma_tx {MODE} {1} +set_instance_parameter_value sys_ethernet_dma_tx {DATA_WIDTH} {64} +set_instance_parameter_value sys_ethernet_dma_tx {DATA_FIFO_DEPTH} {256} +set_instance_parameter_value sys_ethernet_dma_tx {DESCRIPTOR_FIFO_DEPTH} {512} +set_instance_parameter_value sys_ethernet_dma_tx {MAX_BYTE} {2048} +set_instance_parameter_value sys_ethernet_dma_tx {TRANSFER_TYPE} {Unaligned Accesses} +set_instance_parameter_value sys_ethernet_dma_tx {BURST_ENABLE} {1} +set_instance_parameter_value sys_ethernet_dma_tx {MAX_BURST_COUNT} {64} +set_instance_parameter_value sys_ethernet_dma_tx {ENHANCED_FEATURES} {1} +set_instance_parameter_value sys_ethernet_dma_tx {PACKET_ENABLE} {1} +set_instance_parameter_value sys_ethernet_dma_tx {ERROR_ENABLE} {1} +set_instance_parameter_value sys_ethernet_dma_tx {ERROR_WIDTH} {1} + +add_connection sys_clk.clk_reset sys_ethernet.reset_connection +add_connection sys_clk.clk_reset sys_ethernet_dma_rx.reset_n +add_connection sys_clk.clk_reset sys_ethernet_dma_tx.reset_n +add_connection sys_clk.clk sys_ethernet.control_port_clock_connection +add_connection sys_clk.clk sys_ethernet.receive_clock_connection +add_connection sys_clk.clk sys_ethernet.transmit_clock_connection +add_connection sys_clk.clk sys_ethernet_dma_rx.clock +add_connection sys_clk.clk sys_ethernet_dma_tx.clock +add_connection sys_ethernet.receive sys_ethernet_dma_rx.st_sink +add_connection sys_ethernet_dma_tx.st_source sys_ethernet.transmit +add_interface sys_ethernet_rx_clk clock sink +add_interface sys_ethernet_tx_clk clock sink +add_interface sys_ethernet_rgmii conduit end +add_interface sys_ethernet_mdio conduit end +add_interface sys_ethernet_status conduit end + +set_interface_property sys_ethernet_rx_clk EXPORT_OF sys_ethernet.pcs_mac_rx_clock_connection +set_interface_property sys_ethernet_tx_clk EXPORT_OF sys_ethernet.pcs_mac_tx_clock_connection +set_interface_property sys_ethernet_status EXPORT_OF sys_ethernet.mac_status_connection +set_interface_property sys_ethernet_rgmii EXPORT_OF sys_ethernet.mac_rgmii_connection +set_interface_property sys_ethernet_mdio EXPORT_OF sys_ethernet.mac_mdio_connection + +# sys-id + +add_instance sys_id altera_avalon_sysid_qsys 16.0 +set_instance_parameter_value sys_id {id} {182193580} +add_connection sys_clk.clk_reset sys_id.reset +add_connection sys_clk.clk sys_id.clk + +# timer-1 + +add_instance sys_timer_1 altera_avalon_timer 16.0 +set_instance_parameter_value sys_timer_1 {counterSize} {32} +add_connection sys_clk.clk_reset sys_timer_1.reset +add_connection sys_clk.clk sys_timer_1.clk + +# timer-2 + +add_instance sys_timer_2 altera_avalon_timer 16.0 +set_instance_parameter_value sys_timer_2 {counterSize} {32} +add_connection sys_clk.clk_reset sys_timer_2.reset +add_connection sys_clk.clk sys_timer_2.clk + +# uart + +add_instance sys_uart altera_avalon_jtag_uart 16.0 +set_instance_parameter_value sys_uart {allowMultipleConnections} {0} +add_connection sys_clk.clk_reset sys_uart.reset +add_connection sys_clk.clk sys_uart.clk + +# gpio-bd + +add_instance sys_gpio_bd altera_avalon_pio 16.0 +set_instance_parameter_value sys_gpio_bd {direction} {InOut} +set_instance_parameter_value sys_gpio_bd {generateIRQ} {1} +set_instance_parameter_value sys_gpio_bd {width} {32} +add_connection sys_clk.clk_reset sys_gpio_bd.reset +add_connection sys_clk.clk sys_gpio_bd.clk +add_interface sys_gpio_bd conduit end +set_interface_property sys_gpio_bd EXPORT_OF sys_gpio_bd.external_connection + +# gpio-in + +add_instance sys_gpio_in altera_avalon_pio 16.0 +set_instance_parameter_value sys_gpio_in {direction} {Input} +set_instance_parameter_value sys_gpio_in {generateIRQ} {1} +set_instance_parameter_value sys_gpio_in {width} {32} +add_connection sys_clk.clk_reset sys_gpio_in.reset +add_connection sys_clk.clk sys_gpio_in.clk +add_interface sys_gpio_in conduit end +set_interface_property sys_gpio_in EXPORT_OF sys_gpio_in.external_connection + +# gpio-out + +add_instance sys_gpio_out altera_avalon_pio 16.0 +set_instance_parameter_value sys_gpio_out {direction} {Output} +set_instance_parameter_value sys_gpio_out {generateIRQ} {0} +set_instance_parameter_value sys_gpio_out {width} {32} +add_connection sys_clk.clk_reset sys_gpio_out.reset +add_connection sys_clk.clk sys_gpio_out.clk +add_interface sys_gpio_out conduit end +set_interface_property sys_gpio_out EXPORT_OF sys_gpio_out.external_connection + +# spi + +add_instance sys_spi altera_avalon_spi 16.0 +set_instance_parameter_value sys_spi {clockPhase} {0} +set_instance_parameter_value sys_spi {clockPolarity} {0} +set_instance_parameter_value sys_spi {dataWidth} {8} +set_instance_parameter_value sys_spi {masterSPI} {1} +set_instance_parameter_value sys_spi {numberOfSlaves} {8} +set_instance_parameter_value sys_spi {targetClockRate} {128000.0} +add_connection sys_clk.clk_reset sys_spi.reset +add_connection sys_clk.clk sys_spi.clk +add_interface sys_spi conduit end +set_interface_property sys_spi EXPORT_OF sys_spi.external + +# base-addresses + +ad_cpu_interconnect 0x00180800 sys_cpu.debug_mem_slave +ad_cpu_interconnect 0x00140000 sys_int_mem.s1 +ad_cpu_interconnect 0x00181000 sys_ethernet.control_port +ad_cpu_interconnect 0x001814a0 sys_ethernet_dma_rx.csr +ad_cpu_interconnect 0x001814e0 sys_ethernet_dma_rx.response +ad_cpu_interconnect 0x00181440 sys_ethernet_dma_rx.descriptor_slave +ad_cpu_interconnect 0x00181480 sys_ethernet_dma_tx.csr +ad_cpu_interconnect 0x00181460 sys_ethernet_dma_tx.descriptor_slave +ad_cpu_interconnect 0x001814e8 sys_id.control_slave +ad_cpu_interconnect 0x00181420 sys_timer_1.s1 +ad_cpu_interconnect 0x00181520 sys_timer_2.s1 +ad_cpu_interconnect 0x001814f0 sys_uart.avalon_jtag_slave +ad_cpu_interconnect 0x001814d0 sys_gpio_bd.s1 +ad_cpu_interconnect 0x001814c0 sys_gpio_in.s1 +ad_cpu_interconnect 0x00181500 sys_gpio_out.s1 +ad_cpu_interconnect 0x00181400 sys_spi.spi_control_port + +# dma interconnects + +ad_dma_interconnect sys_ethernet_dma_tx.mm_read +ad_dma_interconnect sys_ethernet_dma_rx.mm_write + +# interrupts + +ad_cpu_interrupt 0 sys_ethernet_dma_rx.csr_irq +ad_cpu_interrupt 1 sys_ethernet_dma_tx.csr_irq +ad_cpu_interrupt 2 sys_uart.irq +ad_cpu_interrupt 3 sys_timer_2.irq +ad_cpu_interrupt 4 sys_timer_1.irq +ad_cpu_interrupt 5 sys_gpio_in.irq +ad_cpu_interrupt 6 sys_gpio_bd.irq +ad_cpu_interrupt 7 sys_spi.irq + + diff --git a/projects/common/a5gte/Makefile b/projects/common/a5gte/Makefile index 7b79c11f7..ee7bdeb71 100644 --- a/projects/common/a5gte/Makefile +++ b/projects/common/a5gte/Makefile @@ -5,10 +5,15 @@ #################################################################################### #################################################################################### +ifeq ($(MMU),) + MMU := 1 +endif + +export ALT_NIOS_MMU_ENABLED := $(MMU) + M_DEPS += system_top.v M_DEPS += system_project.tcl M_DEPS += ../../scripts/adi_env.tcl -M_DEPS += ../../../projects/scripts/adi_tquest.tcl M_ALTERA := quartus_sh --64bit -t @@ -41,6 +46,8 @@ M_FLIST += reconfig_mif M_FLIST += *.sopcinfo M_FLIST += *.jdi M_FLIST += *.pin +M_FLIST += *_summary.csv +M_FLIST += *.dpf @@ -57,7 +64,7 @@ clean-all: a5gte.sof: $(M_DEPS) - rm -rf $(M_FLIST) + -rm -rf $(M_FLIST) $(M_ALTERA) system_project.tcl >> a5gte_quartus.log 2>&1 #################################################################################### diff --git a/projects/common/a5gte/system_top.v b/projects/common/a5gte/system_top.v index cf2f47b8f..8891789e6 100644 --- a/projects/common/a5gte/system_top.v +++ b/projects/common/a5gte/system_top.v @@ -100,7 +100,8 @@ module system_top ( reg [ 4:0] eth_tx_data_h_d; reg [ 4:0] phy_rx_data_h_d; - + reg [ 4:0] phy_rx_data_h_d1; + reg [ 4:0] phy_rx_data_l_d; // RX path altera_pll #( @@ -194,9 +195,10 @@ module system_top ( always @(posedge phy_rx_clk) begin phy_rx_data_h_d <= phy_rx_data_h; + phy_rx_data_h_d1 <= phy_rx_data_h_d; + phy_rx_data_l_d <= phy_rx_data_l; end - altddio_out #( .extend_oe_disable("OFF"), .intended_device_family("Arria V"), @@ -207,8 +209,8 @@ module system_top ( .power_up_high("OFF"), .width(5) ) eth_rx_path_out ( - .datain_h (phy_rx_data_h_d), - .datain_l (phy_rx_data_l), + .datain_h (phy_rx_data_h_d1), + .datain_l (phy_rx_data_l_d), .outclock (phy_rx_clk), .dataout ({eth_rx_cntrl,eth_rx_data}), .aclr (~eth_phy_resetn), diff --git a/projects/common/a5soc/a5soc_system_assign.tcl b/projects/common/a5soc/a5soc_system_assign.tcl index 4f5d287e8..2491a667b 100755 --- a/projects/common/a5soc/a5soc_system_assign.tcl +++ b/projects/common/a5soc/a5soc_system_assign.tcl @@ -6,42 +6,40 @@ set_global_assignment -name DEVICE 5ASTFD5K3F40I3ES # i2c (fmc) -set_location_assignment PIN_F26 -to hdmi_scl -set_location_assignment PIN_G26 -to hdmi_sda -set_location_assignment PIN_N23 -to hdmi_rstn -set_instance_assignment -name IO_STANDARD "2.5 V" -to hdmi_scl -set_instance_assignment -name IO_STANDARD "2.5 V" -to hdmi_sda -set_instance_assignment -name IO_STANDARD "2.5 V" -to hdmi_rstn -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to hdmi_scl -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to hdmi_sda +set_location_assignment PIN_F26 -to fmca_scl +set_location_assignment PIN_G26 -to fmca_sda +set_instance_assignment -name IO_STANDARD "2.5 V" -to fmca_scl +set_instance_assignment -name IO_STANDARD "2.5 V" -to fmca_sda +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to fmca_scl +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to fmca_sda # led & switches -set_location_assignment PIN_AH24 -to gpio_bd[0] ; ## led[0] -set_location_assignment PIN_AU24 -to gpio_bd[1] ; ## led[1] -set_location_assignment PIN_AT24 -to gpio_bd[2] ; ## led[2] -set_location_assignment PIN_AD24 -to gpio_bd[3] ; ## led[3] -set_location_assignment PIN_AT23 -to gpio_bd[4] ; ## push_buttons[0] -set_location_assignment PIN_AP24 -to gpio_bd[5] ; ## push_buttons[1] -set_location_assignment PIN_AW24 -to gpio_bd[6] ; ## push_buttons[2] -set_location_assignment PIN_AW23 -to gpio_bd[7] ; ## push_buttons[3] -set_location_assignment PIN_AL24 -to gpio_bd[8] ; ## dip_switches[0] -set_location_assignment PIN_AF24 -to gpio_bd[9] ; ## dip_switches[1] -set_location_assignment PIN_AE24 -to gpio_bd[10] ; ## dip_switches[2] -set_location_assignment PIN_AU23 -to gpio_bd[11] ; ## dip_switches[3] +set_location_assignment PIN_AH24 -to gpio_bd_o[0] ; ## led[0] +set_location_assignment PIN_AU24 -to gpio_bd_o[1] ; ## led[1] +set_location_assignment PIN_AT24 -to gpio_bd_o[2] ; ## led[2] +set_location_assignment PIN_AD24 -to gpio_bd_o[3] ; ## led[3] +set_location_assignment PIN_AT23 -to gpio_bd_i[0] ; ## push_buttons[0] +set_location_assignment PIN_AP24 -to gpio_bd_i[1] ; ## push_buttons[1] +set_location_assignment PIN_AW24 -to gpio_bd_i[2] ; ## push_buttons[2] +set_location_assignment PIN_AW23 -to gpio_bd_i[3] ; ## push_buttons[3] +set_location_assignment PIN_AL24 -to gpio_bd_i[4] ; ## dip_switches[0] +set_location_assignment PIN_AF24 -to gpio_bd_i[5] ; ## dip_switches[1] +set_location_assignment PIN_AE24 -to gpio_bd_i[6] ; ## dip_switches[2] +set_location_assignment PIN_AU23 -to gpio_bd_i[7] ; ## dip_switches[3] -set_instance_assignment -name IO_STANDARD "1.5 V" -to gpio_bd[0] -set_instance_assignment -name IO_STANDARD "1.5 V" -to gpio_bd[1] -set_instance_assignment -name IO_STANDARD "1.5 V" -to gpio_bd[2] -set_instance_assignment -name IO_STANDARD "1.5 V" -to gpio_bd[3] -set_instance_assignment -name IO_STANDARD "1.5 V" -to gpio_bd[4] -set_instance_assignment -name IO_STANDARD "1.5 V" -to gpio_bd[5] -set_instance_assignment -name IO_STANDARD "1.5 V" -to gpio_bd[6] -set_instance_assignment -name IO_STANDARD "1.5 V" -to gpio_bd[7] -set_instance_assignment -name IO_STANDARD "1.5 V" -to gpio_bd[8] -set_instance_assignment -name IO_STANDARD "1.5 V" -to gpio_bd[9] -set_instance_assignment -name IO_STANDARD "1.5 V" -to gpio_bd[10] -set_instance_assignment -name IO_STANDARD "1.5 V" -to gpio_bd[11] +set_instance_assignment -name IO_STANDARD "1.5 V" -to gpio_bd_o[0] +set_instance_assignment -name IO_STANDARD "1.5 V" -to gpio_bd_o[1] +set_instance_assignment -name IO_STANDARD "1.5 V" -to gpio_bd_o[2] +set_instance_assignment -name IO_STANDARD "1.5 V" -to gpio_bd_o[3] +set_instance_assignment -name IO_STANDARD "1.5 V" -to gpio_bd_i[0] +set_instance_assignment -name IO_STANDARD "1.5 V" -to gpio_bd_i[1] +set_instance_assignment -name IO_STANDARD "1.5 V" -to gpio_bd_i[2] +set_instance_assignment -name IO_STANDARD "1.5 V" -to gpio_bd_i[3] +set_instance_assignment -name IO_STANDARD "1.5 V" -to gpio_bd_i[4] +set_instance_assignment -name IO_STANDARD "1.5 V" -to gpio_bd_i[5] +set_instance_assignment -name IO_STANDARD "1.5 V" -to gpio_bd_i[6] +set_instance_assignment -name IO_STANDARD "1.5 V" -to gpio_bd_i[7] # uart @@ -434,14 +432,9 @@ set_global_assignment -name UNIPHY_SEQUENCER_DQS_CONFIG_ENABLE ON set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS" set_global_assignment -name ECO_REGENERATE_REPORT ON -set_global_assignment -name SYNCHRONIZER_IDENTIFICATION AUTO -set_global_assignment -name ENABLE_ADVANCED_IO_TIMING ON -set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER ON -set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V" -set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON -set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON -set_global_assignment -name TIMEQUEST_REPORT_SCRIPT $ad_hdl_dir/projects/scripts/adi_tquest.tcl -set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION OFF +# source defaults + +source $ad_hdl_dir/projects/common/altera/sys_gen.tcl diff --git a/projects/common/a5soc/a5soc_system_bd.qsys b/projects/common/a5soc/a5soc_system_bd.qsys deleted file mode 100644 index 68d81e091..000000000 --- a/projects/common/a5soc/a5soc_system_bd.qsys +++ /dev/null @@ -1,1107 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - No,No,No,No,No,No,No,No - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No - - - - - - - - - - - - - - - - - - - - - - - - - No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No - - 0x000000000000000000 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - {320000000 1600000000} {320000000 1000000000} {800000000 400000000 400000000} - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - $${FILENAME}_sys_int_mem - - - - - ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 1 HARDCOPY 0 HAS_18_BIT_MULTS 1 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 1 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 1 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 0 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 1 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 0 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 1 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 0 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 1 M144K_MEMORY 1 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 1 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 1 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 1 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 1 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 1 TRANSCEIVER_6G_BLOCK 1 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 1 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/projects/common/a5soc/a5soc_system_qsys.tcl b/projects/common/a5soc/a5soc_system_qsys.tcl new file mode 100644 index 000000000..5699a3a26 --- /dev/null +++ b/projects/common/a5soc/a5soc_system_qsys.tcl @@ -0,0 +1,200 @@ + +package require qsys + +set_module_property NAME {system_bd} +set_project_property DEVICE_FAMILY {Arria V} +set_project_property DEVICE {5ASTFD5K3F40I3ES} + +set system_type nios + +# clock-&-reset + +add_instance sys_clk clock_source 16.0 +add_interface sys_clk clock sink +add_interface sys_rst reset sink +set_interface_property sys_clk EXPORT_OF sys_clk.clk_in +set_interface_property sys_rst EXPORT_OF sys_clk.clk_in_reset +set_instance_parameter_value sys_clk {clockFrequency} {100000000.0} +set_instance_parameter_value sys_clk {clockFrequencyKnown} {1} +set_instance_parameter_value sys_clk {resetSynchronousEdges} {DEASSERT} + +# memory (int) + +add_instance sys_int_mem altera_avalon_onchip_memory2 16.0 +set_instance_parameter_value sys_int_mem {dataWidth} {64} +set_instance_parameter_value sys_int_mem {dualPort} {0} +set_instance_parameter_value sys_int_mem {initMemContent} {0} +set_instance_parameter_value sys_int_mem {memorySize} {65536.0} +add_connection sys_clk.clk sys_int_mem.clk1 +add_connection sys_clk.clk_reset sys_int_mem.reset1 + +# hps + +add_instance sys_hps altera_hps 16.0 +set_instance_parameter_value sys_hps {MPU_EVENTS_Enable} {0} +set_instance_parameter_value sys_hps {F2SDRAM_Type} {} +set_instance_parameter_value sys_hps {F2SDRAM_Width} {} +set_instance_parameter_value sys_hps {F2SINTERRUPT_Enable} {1} +set_instance_parameter_value sys_hps {EMAC1_PinMuxing} {HPS I/O Set 0} +set_instance_parameter_value sys_hps {EMAC1_Mode} {RGMII} +set_instance_parameter_value sys_hps {QSPI_PinMuxing} {HPS I/O Set 0} +set_instance_parameter_value sys_hps {QSPI_Mode} {1 SS} +set_instance_parameter_value sys_hps {SDIO_PinMuxing} {HPS I/O Set 0} +set_instance_parameter_value sys_hps {SDIO_Mode} {4-bit Data} +set_instance_parameter_value sys_hps {USB1_PinMuxing} {HPS I/O Set 0} +set_instance_parameter_value sys_hps {USB1_Mode} {SDR} +set_instance_parameter_value sys_hps {SPIM0_PinMuxing} {FPGA} +set_instance_parameter_value sys_hps {SPIM0_Mode} {Full} +set_instance_parameter_value sys_hps {UART0_PinMuxing} {HPS I/O Set 1} +set_instance_parameter_value sys_hps {UART0_Mode} {No Flow Control} +set_instance_parameter_value sys_hps {I2C0_PinMuxing} {FPGA} +set_instance_parameter_value sys_hps {I2C0_Mode} {Full} +set_instance_parameter_value sys_hps {use_default_mpu_clk} {0} +set_instance_parameter_value sys_hps {desired_cfg_clk_mhz} {50.0} +set_instance_parameter_value sys_hps {S2FCLK_USER0CLK_Enable} {1} +set_instance_parameter_value sys_hps {S2FCLK_USER1CLK_Enable} {1} +set_instance_parameter_value sys_hps {S2FCLK_USER2CLK_Enable} {0} +set_instance_parameter_value sys_hps {S2FCLK_USER1CLK_FREQ} {100.0} +set_instance_parameter_value sys_hps {S2FCLK_USER2CLK_FREQ} {100.0} +set_instance_parameter_value sys_hps {HPS_PROTOCOL} {DDR3} +set_instance_parameter_value sys_hps {MEM_CLK_FREQ} {400.0} +set_instance_parameter_value sys_hps {REF_CLK_FREQ} {25.0} +set_instance_parameter_value sys_hps {MEM_CLK_FREQ_MAX} {800.0} +set_instance_parameter_value sys_hps {MEM_DQ_WIDTH} {40} +set_instance_parameter_value sys_hps {MEM_ROW_ADDR_WIDTH} {15} +set_instance_parameter_value sys_hps {MEM_COL_ADDR_WIDTH} {10} +set_instance_parameter_value sys_hps {MEM_BANKADDR_WIDTH} {3} +set_instance_parameter_value sys_hps {MEM_RTT_NOM} {RZQ/4} +set_instance_parameter_value sys_hps {TIMING_TIS} {170} +set_instance_parameter_value sys_hps {TIMING_TIH} {120} +set_instance_parameter_value sys_hps {TIMING_TDS} {10} +set_instance_parameter_value sys_hps {TIMING_TDH} {45} +set_instance_parameter_value sys_hps {TIMING_TDQSQ} {100} +set_instance_parameter_value sys_hps {TIMING_TQH} {0.38} +set_instance_parameter_value sys_hps {TIMING_TDQSCK} {225} +set_instance_parameter_value sys_hps {TIMING_TDQSS} {0.27} +set_instance_parameter_value sys_hps {TIMING_TQSH} {0.4} +set_instance_parameter_value sys_hps {TIMING_TDSH} {0.18} +set_instance_parameter_value sys_hps {TIMING_TDSS} {0.18} +set_instance_parameter_value sys_hps {MEM_TINIT_US} {500} +set_instance_parameter_value sys_hps {MEM_TMRD_CK} {4} +set_instance_parameter_value sys_hps {MEM_TRAS_NS} {35.0} +set_instance_parameter_value sys_hps {MEM_TRCD_NS} {13.75} +set_instance_parameter_value sys_hps {MEM_TRP_NS} {13.75} +set_instance_parameter_value sys_hps {MEM_TREFI_US} {7.8} +set_instance_parameter_value sys_hps {MEM_TRFC_NS} {260.0} +set_instance_parameter_value sys_hps {MEM_TWR_NS} {15.0} +set_instance_parameter_value sys_hps {MEM_TWTR} {4} +set_instance_parameter_value sys_hps {MEM_TFAW_NS} {35.0} +set_instance_parameter_value sys_hps {MEM_TRRD_NS} {6.0} +set_instance_parameter_value sys_hps {MEM_TRTP_NS} {7.5} + +add_interface sys_hps_cpu_clk clock source +set_interface_property sys_hps_cpu_clk EXPORT_OF sys_hps.h2f_user0_clock +add_interface sys_hps_dma_clk clock source +set_interface_property sys_hps_dma_clk EXPORT_OF sys_hps.h2f_user1_clock +add_interface sys_hps_spim0 conduit end +set_interface_property sys_hps_spim0 EXPORT_OF sys_hps.spim0 +add_interface sys_hps_spim0_sclk clock source +set_interface_property sys_hps_spim0_sclk EXPORT_OF sys_hps.spim0_sclk_out +add_interface sys_hps_i2c0_scl clock sink +set_interface_property sys_hps_i2c0_scl EXPORT_OF sys_hps.i2c0_scl_in +add_interface sys_hps_i2c0_clk clock source +set_interface_property sys_hps_i2c0_clk EXPORT_OF sys_hps.i2c0_clk +add_interface sys_hps_i2c0 conduit end +set_interface_property sys_hps_i2c0 EXPORT_OF sys_hps.i2c0 +add_interface sys_hps_ddr3 conduit end +set_interface_property sys_hps_ddr3 EXPORT_OF sys_hps.memory +add_interface sys_hps_io conduit end +set_interface_property sys_hps_io EXPORT_OF sys_hps.hps_io +add_interface sys_hps_rstn conduit end +set_interface_property sys_hps_rstn EXPORT_OF sys_hps.h2f_reset +add_connection sys_clk.clk sys_hps.h2f_axi_clock +add_connection sys_hps.h2f_axi_master sys_int_mem.s1 +set_connection_parameter_value sys_hps.h2f_axi_master/sys_int_mem.s1 baseAddress {0x0} +add_connection sys_clk.clk sys_hps.h2f_lw_axi_clock + +# cpu/hps handling + +proc ad_cpu_interrupt {m_irq m_port} { + + add_connection sys_hps.f2h_irq0 ${m_port} + set_connection_parameter_value sys_hps.f2h_irq0/${m_port} irqNumber ${m_irq} +} + +proc ad_cpu_interconnect {m_base m_port} { + + add_connection sys_hps.h2f_lw_axi_master ${m_port} + set_connection_parameter_value sys_hps.h2f_lw_axi_master/${m_port} baseAddress $m_base +} + +proc ad_dma_interconnect {m_port} { + + add_connection ${m_port} sys_hps.f2h_axi_slave + set_connection_parameter_value ${m_port}/sys_hps.f2h_axi_slave baseAddress {0x0} +} + +# common dma interfaces + +add_instance sys_dma_clk clock_source 16.0 +add_interface sys_dma_clk clock sink +add_interface sys_dma_rst reset sink +set_interface_property sys_dma_clk EXPORT_OF sys_dma_clk.clk_in +set_interface_property sys_dma_rst EXPORT_OF sys_dma_clk.clk_in_reset +set_instance_parameter_value sys_dma_clk {clockFrequency} {100000000.0} +set_instance_parameter_value sys_dma_clk {clockFrequencyKnown} {1} +set_instance_parameter_value sys_dma_clk {resetSynchronousEdges} {DEASSERT} +add_connection sys_dma_clk.clk sys_hps.f2h_axi_clock + +# sys-id + +add_instance sys_id altera_avalon_sysid_qsys 16.0 +set_instance_parameter_value sys_id {id} {182193580} +add_connection sys_clk.clk_reset sys_id.reset +add_connection sys_clk.clk sys_id.clk + +# gpio-bd + +add_instance sys_gpio_bd altera_avalon_pio 16.0 +set_instance_parameter_value sys_gpio_bd {direction} {InOut} +set_instance_parameter_value sys_gpio_bd {generateIRQ} {1} +set_instance_parameter_value sys_gpio_bd {width} {32} +add_connection sys_clk.clk_reset sys_gpio_bd.reset +add_connection sys_clk.clk sys_gpio_bd.clk +add_interface sys_gpio_bd conduit end +set_interface_property sys_gpio_bd EXPORT_OF sys_gpio_bd.external_connection + +# gpio-in + +add_instance sys_gpio_in altera_avalon_pio 16.0 +set_instance_parameter_value sys_gpio_in {direction} {Input} +set_instance_parameter_value sys_gpio_in {generateIRQ} {1} +set_instance_parameter_value sys_gpio_in {width} {32} +add_connection sys_clk.clk_reset sys_gpio_in.reset +add_connection sys_clk.clk sys_gpio_in.clk +add_interface sys_gpio_in conduit end +set_interface_property sys_gpio_in EXPORT_OF sys_gpio_in.external_connection + +# gpio-out + +add_instance sys_gpio_out altera_avalon_pio 16.0 +set_instance_parameter_value sys_gpio_out {direction} {Output} +set_instance_parameter_value sys_gpio_out {generateIRQ} {0} +set_instance_parameter_value sys_gpio_out {width} {32} +add_connection sys_clk.clk_reset sys_gpio_out.reset +add_connection sys_clk.clk sys_gpio_out.clk +add_interface sys_gpio_out conduit end +set_interface_property sys_gpio_out EXPORT_OF sys_gpio_out.external_connection + +# base-addresses + +ad_cpu_interconnect 0x001814e8 sys_id.control_slave +ad_cpu_interconnect 0x001814d0 sys_gpio_bd.s1 +ad_cpu_interconnect 0x001814c0 sys_gpio_in.s1 +ad_cpu_interconnect 0x00181500 sys_gpio_out.s1 + +# interrupts + +ad_cpu_interrupt 0 sys_gpio_in.irq +ad_cpu_interrupt 1 sys_gpio_bd.irq + diff --git a/projects/common/ac701/ac701_system_bd.tcl b/projects/common/ac701/ac701_system_bd.tcl index 2ee349106..57afc4be2 100644 --- a/projects/common/ac701/ac701_system_bd.tcl +++ b/projects/common/ac701/ac701_system_bd.tcl @@ -47,7 +47,7 @@ set_property -dict [list CONFIG.POLARITY {ACTIVE_HIGH}] [get_bd_ports sys_rst] # instance: microblaze - processor -set sys_mb [create_bd_cell -type ip -vlnv xilinx.com:ip:microblaze:9.5 sys_mb] +set sys_mb [create_bd_cell -type ip -vlnv xilinx.com:ip:microblaze:9.6 sys_mb] set_property -dict [list CONFIG.G_TEMPLATE_LIST {4}] $sys_mb set_property -dict [list CONFIG.C_DCACHE_FORCE_TAG_LUTRAM {1}] $sys_mb @@ -76,14 +76,14 @@ set sys_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 s # instance: ddr (mig) -set axi_ddr_cntrl [create_bd_cell -type ip -vlnv xilinx.com:ip:mig_7series:2.4 axi_ddr_cntrl] +set axi_ddr_cntrl [create_bd_cell -type ip -vlnv xilinx.com:ip:mig_7series:4.0 axi_ddr_cntrl] set axi_ddr_cntrl_dir [get_property IP_DIR [get_ips [get_property CONFIG.Component_Name $axi_ddr_cntrl]]] file copy -force $ad_hdl_dir/projects/common/ac701/ac701_system_mig.prj "$axi_ddr_cntrl_dir/" set_property -dict [list CONFIG.XML_INPUT_FILE {ac701_system_mig.prj}] $axi_ddr_cntrl # instance: default peripherals -set sys_ethernet_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.2 sys_ethernet_clkgen] +set sys_ethernet_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.3 sys_ethernet_clkgen] set_property -dict [list CONFIG.PRIM_IN_FREQ {200.000}] $sys_ethernet_clkgen set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {125.000}] $sys_ethernet_clkgen @@ -152,6 +152,7 @@ ad_connect sys_concat_intc/dout axi_intc/intr # defaults (peripherals) ad_connect axi_ddr_cntrl/mmcm_locked sys_rstgen/dcm_locked +ad_connect axi_ddr_cntrl/device_temp_i GND ad_connect sys_cpu_clk axi_ddr_cntrl/ui_clk ad_connect sys_200m_clk axi_ddr_cntrl/ui_addn_clk_0 diff --git a/projects/common/altera/sys_gen.tcl b/projects/common/altera/sys_gen.tcl new file mode 100644 index 000000000..c0f2114e1 --- /dev/null +++ b/projects/common/altera/sys_gen.tcl @@ -0,0 +1,49 @@ + +# globals + +set_global_assignment -name SYNCHRONIZER_IDENTIFICATION AUTO +set_global_assignment -name ENABLE_ADVANCED_IO_TIMING ON +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER ON +set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON +set_global_assignment -name TIMEQUEST_REPORT_SCRIPT $ad_hdl_dir/projects/scripts/adi_tquest.tcl +set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION OFF + +# library paths + +set ad_lib_folders "$ad_hdl_dir/library/**/*;$ad_phdl_dir/library/**/*" + +set_user_option -name USER_IP_SEARCH_PATHS $ad_lib_folders +set_global_assignment -name IP_SEARCH_PATHS $ad_lib_folders + +# qsys-script is a crippled tool, so work around is generate a run-time one + +set mmu_enabled 1 +if [info exists ::env(ALT_NIOS_MMU_ENABLED)] { + set mmu_enabled $::env(ALT_NIOS_MMU_ENABLED) +} + +set QFILE [open "system_qsys_script.tcl" "w"] +puts $QFILE "set mmu_enabled $mmu_enabled" +puts $QFILE "set ad_hdl_dir $ad_hdl_dir" +puts $QFILE "set ad_phdl_dir $ad_phdl_dir" +puts $QFILE "source system_qsys.tcl" +puts $QFILE "set_interconnect_requirement {\$system} {qsys_mm.clockCrossingAdapter} {FIFO}" +puts $QFILE "set_interconnect_requirement {\$system} {qsys_mm.maxAdditionalLatency} {2}" +puts $QFILE "save_system {system_bd.qsys}" +close $QFILE + +exec -ignorestderr $quartus(quartus_rootpath)/sopc_builder/bin/qsys-script \ + --script=system_qsys_script.tcl + +# remove altshift_taps + +set_instance_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -to * -entity up_xfer_cntrl +set_instance_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -to * -entity up_xfer_status +set_instance_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -to * -entity up_clock_mon +set_instance_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -to * -entity ad_rst +set_instance_assignment -name QII_AUTO_PACKED_REGISTERS OFF -to * -entity up_xfer_cntrl +set_instance_assignment -name QII_AUTO_PACKED_REGISTERS OFF -to * -entity up_xfer_status +set_instance_assignment -name QII_AUTO_PACKED_REGISTERS OFF -to * -entity up_clock_mon +set_instance_assignment -name QII_AUTO_PACKED_REGISTERS OFF -to * -entity ad_rst + diff --git a/projects/common/c5soc/c5soc_system_bd.qsys b/projects/common/c5soc/c5soc_system_bd.qsys old mode 100644 new mode 100755 index 8f6673b95..ad63dfc44 --- a/projects/common/c5soc/c5soc_system_bd.qsys +++ b/projects/common/c5soc/c5soc_system_bd.qsys @@ -471,19 +471,19 @@ internal="vga_pixel_clock_bridge.out_clk" type="clock" dir="start" /> - + - + - + @@ -491,7 +491,7 @@ @@ -557,7 +557,7 @@ - + @@ -571,7 +571,7 @@ - + @@ -646,8 +646,10 @@ + + @@ -683,6 +685,7 @@ + @@ -1102,25 +1105,26 @@ - $${FILENAME}_sys_int_mem + - ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 0 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 1 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 1 HARDCOPY 0 HAS_18_BIT_MULTS 1 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 1 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 1 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 1 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 0 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 1 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 0 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 1 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 1 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 1 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 1 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 1 TRANSCEIVER_6G_BLOCK 1 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 1 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1 + ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 0 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 1 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PHYSICAL_DESIGN_PLANNER 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 1 HARDCOPY 0 HAS_18_BIT_MULTS 1 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 1 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 1 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 1 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 0 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 1 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 0 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 1 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 1 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 1 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 1 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 1 TRANSCEIVER_6G_BLOCK 1 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 1 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1 + @@ -1136,9 +1140,7 @@ - - - + @@ -1146,7 +1148,7 @@ @@ -1215,7 +1217,7 @@ @@ -1281,7 +1283,7 @@ - + @@ -1345,13 +1347,13 @@ - + @@ -1556,7 +1558,7 @@ @@ -1565,7 +1567,7 @@ @@ -1574,7 +1576,7 @@ @@ -1583,7 +1585,7 @@ @@ -1592,7 +1594,7 @@ @@ -1601,7 +1603,7 @@ @@ -1610,7 +1612,7 @@ @@ -1619,7 +1621,7 @@ @@ -1628,228 +1630,228 @@ - + diff --git a/projects/common/kc705/kc705_system_bd.tcl b/projects/common/kc705/kc705_system_bd.tcl index f762c2b5d..d97d57bb8 100644 --- a/projects/common/kc705/kc705_system_bd.tcl +++ b/projects/common/kc705/kc705_system_bd.tcl @@ -53,7 +53,7 @@ set_property -dict [list CONFIG.POLARITY {ACTIVE_HIGH}] [get_bd_ports sys_rst] # instance: microblaze - processor -set sys_mb [create_bd_cell -type ip -vlnv xilinx.com:ip:microblaze:9.5 sys_mb] +set sys_mb [create_bd_cell -type ip -vlnv xilinx.com:ip:microblaze:9.6 sys_mb] set_property -dict [list CONFIG.G_TEMPLATE_LIST {4}] $sys_mb set_property -dict [list CONFIG.C_DCACHE_FORCE_TAG_LUTRAM {1}] $sys_mb @@ -82,7 +82,7 @@ set sys_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 s # instance: ddr (mig) -set axi_ddr_cntrl [create_bd_cell -type ip -vlnv xilinx.com:ip:mig_7series:2.4 axi_ddr_cntrl] +set axi_ddr_cntrl [create_bd_cell -type ip -vlnv xilinx.com:ip:mig_7series:4.0 axi_ddr_cntrl] set axi_ddr_cntrl_dir [get_property IP_DIR [get_ips [get_property CONFIG.Component_Name $axi_ddr_cntrl]]] file copy -force $ad_hdl_dir/projects/common/kc705/kc705_system_mig.prj "$axi_ddr_cntrl_dir/" set_property -dict [list CONFIG.XML_INPUT_FILE {kc705_system_mig.prj}] $axi_ddr_cntrl @@ -262,3 +262,9 @@ create_bd_addr_seg -range 0x20000 -offset 0x0 [get_bd_addr_spaces sys_mb/Instruc [get_bd_addr_segs sys_ilmb_cntlr/SLMB/Mem] SEG_ilmb_cntlr set_property range 0x2000000 [get_bd_addr_segs {sys_mb/Data/SEG_data_axi_linear_flash}] +set_property range 0x2000 [get_bd_addr_segs {sys_mb/Data/SEG_data_axi_ethernet}] + + +ad_connect axi_ddr_cntrl/device_temp_i GND + + diff --git a/projects/common/kcu105/kcu105_system_bd.tcl b/projects/common/kcu105/kcu105_system_bd.tcl index 715b597e0..29abe3d87 100644 --- a/projects/common/kcu105/kcu105_system_bd.tcl +++ b/projects/common/kcu105/kcu105_system_bd.tcl @@ -3,8 +3,8 @@ # interface ports create_bd_port -dir I -type rst sys_rst -create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddr4_rtl:1.0 c0_ddr4 create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sys_clk +create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddr4_rtl:1.0 c0_ddr4 create_bd_port -dir I phy_sd create_bd_port -dir O -type rst phy_rst_n @@ -51,7 +51,7 @@ set_property -dict [list CONFIG.FREQ_HZ {625000000}] [get_bd_intf_ports phy_clk] # instance: microblaze - processor -set sys_mb [create_bd_cell -type ip -vlnv xilinx.com:ip:microblaze:9.5 sys_mb] +set sys_mb [create_bd_cell -type ip -vlnv xilinx.com:ip:microblaze:9.6 sys_mb] set_property -dict [list CONFIG.G_TEMPLATE_LIST {4}] $sys_mb set_property -dict [list CONFIG.C_DCACHE_FORCE_TAG_LUTRAM {1}] $sys_mb @@ -78,13 +78,12 @@ set_property -dict [list CONFIG.C_USE_UART {1}] $sys_mb_debug set sys_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 sys_rstgen] -# instance: ddr (mig) +# instance: ddr4 -set axi_ddr_cntrl [ create_bd_cell -type ip -vlnv xilinx.com:ip:ddr4:1.1 axi_ddr_cntrl ] +set axi_ddr_cntrl [create_bd_cell -type ip -vlnv xilinx.com:ip:ddr4:2.0 axi_ddr_cntrl] set_property -dict [list CONFIG.C0_CLOCK_BOARD_INTERFACE {default_sysclk_300}] $axi_ddr_cntrl set_property -dict [list CONFIG.C0_DDR4_BOARD_INTERFACE {ddr4_sdram}] $axi_ddr_cntrl set_property -dict [list CONFIG.RESET_BOARD_INTERFACE {reset}] $axi_ddr_cntrl -set_property -dict [list CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {100}] $axi_ddr_cntrl set_property -dict [list CONFIG.ADDN_UI_CLKOUT2_FREQ_HZ {200}] $axi_ddr_cntrl set axi_ddr_cntrl_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 axi_ddr_cntrl_rstgen] @@ -92,11 +91,10 @@ set axi_ddr_cntrl_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_r # instance: default peripherals set axi_ethernet [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_ethernet:7.0 axi_ethernet] -set_property -dict [list CONFIG.SupportLevel {1}] $axi_ethernet set_property -dict [list CONFIG.ETHERNET_BOARD_INTERFACE {sgmii_lvds}] $axi_ethernet set_property -dict [list CONFIG.MDIO_BOARD_INTERFACE {mdio_mdc}] $axi_ethernet set_property -dict [list CONFIG.DIFFCLK_BOARD_INTERFACE {sgmii_phyclk}] $axi_ethernet -set_property -dict [list CONFIG.lvdsclkrate {625}] $axi_ethernet +set_property -dict [list CONFIG.PHYRST_BOARD_INTERFACE {phy_reset_out}] $axi_ethernet set_property -dict [list CONFIG.TXCSUM {Full}] $axi_ethernet set_property -dict [list CONFIG.RXCSUM {Full}] $axi_ethernet set_property -dict [list CONFIG.TXMEM {8k}] $axi_ethernet @@ -133,94 +131,64 @@ set_property -dict [list CONFIG.C_HAS_FAST {0}] $axi_intc set sys_concat_intc [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 sys_concat_intc] set_property -dict [list CONFIG.NUM_PORTS {16}] $sys_concat_intc -# connections +# ddr4 -ad_connect sys_mb_debug/Debug_SYS_Rst sys_rstgen/mb_debug_sys_rst +ad_connect sys_rst axi_ddr_cntrl/sys_rst +ad_connect sys_clk axi_ddr_cntrl/C0_SYS_CLK +ad_connect c0_ddr4 axi_ddr_cntrl/C0_DDR4 +ad_connect axi_ddr_cntrl/c0_ddr4_ui_clk_sync_rst sys_rstgen/ext_reset_in +ad_connect axi_ddr_cntrl/c0_ddr4_ui_clk_sync_rst axi_ddr_cntrl_rstgen/ext_reset_in +ad_connect sys_mem_clk axi_ddr_cntrl/c0_ddr4_ui_clk +ad_connect sys_mem_clk axi_ddr_cntrl_rstgen/slowest_sync_clk +ad_connect sys_cpu_clk axi_ddr_cntrl/addn_ui_clkout1 +ad_connect sys_cpu_clk sys_rstgen/slowest_sync_clk +ad_connect sys_mem_resetn axi_ddr_cntrl_rstgen/peripheral_aresetn +ad_connect sys_mem_resetn axi_ddr_cntrl/c0_ddr4_aresetn +ad_connect sys_200m_clk axi_ddr_cntrl/addn_ui_clkout2 + +# microblaze + +ad_connect sys_cpu_reset sys_rstgen/peripheral_reset +ad_connect sys_cpu_resetn sys_rstgen/peripheral_aresetn +ad_connect sys_cpu_clk sys_mb/Clk +ad_connect sys_cpu_clk sys_dlmb/LMB_Clk +ad_connect sys_cpu_clk sys_ilmb/LMB_Clk +ad_connect sys_cpu_clk sys_dlmb_cntlr/LMB_Clk +ad_connect sys_cpu_clk sys_ilmb_cntlr/LMB_Clk ad_connect sys_rstgen/mb_reset sys_mb/Reset ad_connect sys_rstgen/bus_struct_reset sys_dlmb/SYS_Rst ad_connect sys_rstgen/bus_struct_reset sys_ilmb/SYS_Rst ad_connect sys_rstgen/bus_struct_reset sys_dlmb_cntlr/LMB_Rst ad_connect sys_rstgen/bus_struct_reset sys_ilmb_cntlr/LMB_Rst - -# microblaze local memory - ad_connect sys_mb/DLMB sys_dlmb/LMB_M ad_connect sys_mb/ILMB sys_ilmb/LMB_M ad_connect sys_dlmb/LMB_Sl_0 sys_dlmb_cntlr/SLMB ad_connect sys_ilmb/LMB_Sl_0 sys_ilmb_cntlr/SLMB ad_connect sys_dlmb_cntlr/BRAM_PORT sys_lmb_bram/BRAM_PORTA ad_connect sys_ilmb_cntlr/BRAM_PORT sys_lmb_bram/BRAM_PORTB - -# microblaze debug & interrupt - +ad_connect sys_mb_debug/Debug_SYS_Rst sys_rstgen/mb_debug_sys_rst ad_connect sys_mb_debug/MBDEBUG_0 sys_mb/DEBUG ad_connect axi_intc/interrupt sys_mb/INTERRUPT ad_connect axi_intc/intr sys_concat_intc/dout -# defaults (peripherals) - -ad_connect sys_mem_clk axi_ddr_cntrl/c0_ddr4_ui_clk -ad_connect sys_cpu_clk axi_ddr_cntrl/addn_ui_clkout1 -ad_connect sys_200m_clk axi_ddr_cntrl/addn_ui_clkout2 -ad_connect sys_cpu_reset sys_rstgen/peripheral_reset -ad_connect sys_cpu_resetn sys_rstgen/peripheral_aresetn -ad_connect sys_mem_resetn axi_ddr_cntrl_rstgen/peripheral_aresetn -ad_connect sys_mem_resetn axi_ddr_cntrl/c0_ddr4_aresetn - -ad_connect sys_cpu_clk sys_rstgen/slowest_sync_clk -ad_connect sys_cpu_clk sys_mb/Clk -ad_connect sys_cpu_clk sys_dlmb/LMB_Clk -ad_connect sys_cpu_clk sys_ilmb/LMB_Clk -ad_connect sys_cpu_clk sys_dlmb_cntlr/LMB_Clk -ad_connect sys_cpu_clk sys_ilmb_cntlr/LMB_Clk -ad_connect sys_cpu_clk axi_ethernet/axis_clk - -# defaults (interrupts) - -ad_connect sys_concat_intc/In0 axi_timer/interrupt -ad_connect sys_concat_intc/In1 axi_ethernet/interrupt -ad_connect sys_concat_intc/In2 axi_ethernet_dma/mm2s_introut -ad_connect sys_concat_intc/In3 axi_ethernet_dma/s2mm_introut -ad_connect sys_concat_intc/In4 axi_uart/interrupt -ad_connect sys_concat_intc/In5 mb_intr_05 -ad_connect sys_concat_intc/In6 mb_intr_06 -ad_connect sys_concat_intc/In7 mb_intr_07 -ad_connect sys_concat_intc/In8 mb_intr_08 -ad_connect sys_concat_intc/In9 axi_iic_main/iic2intc_irpt -ad_connect sys_concat_intc/In10 axi_spi/ip2intc_irpt -ad_connect sys_concat_intc/In11 axi_gpio/ip2intc_irpt -ad_connect sys_concat_intc/In12 mb_intr_12 -ad_connect sys_concat_intc/In13 mb_intr_13 -ad_connect sys_concat_intc/In14 mb_intr_14 -ad_connect sys_concat_intc/In15 mb_intr_15 - -# defaults (ddr) - -ad_connect sys_rst axi_ddr_cntrl/sys_rst -ad_connect c0_ddr4 axi_ddr_cntrl/C0_DDR4 -ad_connect sys_clk axi_ddr_cntrl/C0_SYS_CLK - -ad_connect axi_ddr_cntrl/c0_ddr4_ui_clk_sync_rst sys_rstgen/ext_reset_in -ad_connect axi_ddr_cntrl/c0_ddr4_ui_clk_sync_rst axi_ddr_cntrl_rstgen/ext_reset_in -ad_connect sys_mem_clk axi_ddr_cntrl_rstgen/slowest_sync_clk - -# defaults (ethernet) +# ethernet +ad_connect sgmii axi_ethernet/sgmii ad_connect phy_clk axi_ethernet/lvds_clk ad_connect mdio axi_ethernet/mdio -ad_connect sgmii axi_ethernet/sgmii +ad_connect phy_sd axi_ethernet/signal_detect +ad_connect axi_ethernet/phy_rst_n phy_rst_n +ad_connect sys_cpu_clk axi_ethernet/axis_clk ad_connect axi_ethernet/s_axis_txd axi_ethernet_dma/M_AXIS_MM2S ad_connect axi_ethernet/s_axis_txc axi_ethernet_dma/M_AXIS_CNTRL ad_connect axi_ethernet/m_axis_rxd axi_ethernet_dma/S_AXIS_S2MM ad_connect axi_ethernet/m_axis_rxs axi_ethernet_dma/S_AXIS_STS -ad_connect phy_sd axi_ethernet/signal_detect -ad_connect sys_cpu_resetn phy_rst_n ad_connect axi_ethernet/axi_txd_arstn axi_ethernet_dma/mm2s_prmry_reset_out_n ad_connect axi_ethernet/axi_txc_arstn axi_ethernet_dma/mm2s_cntrl_reset_out_n ad_connect axi_ethernet/axi_rxd_arstn axi_ethernet_dma/s2mm_prmry_reset_out_n ad_connect axi_ethernet/axi_rxs_arstn axi_ethernet_dma/s2mm_sts_reset_out_n -# defaults (misc) +# iic, spi and gpio ad_connect iic_main axi_iic_main/iic ad_connect uart_sin axi_uart/rx @@ -240,7 +208,26 @@ ad_connect gpio1_o axi_gpio/gpio2_io_o ad_connect gpio1_t axi_gpio/gpio2_io_t ad_connect sys_cpu_clk axi_spi/ext_spi_clk -# defaults (interconnect - processor) +# interrupts + +ad_connect sys_concat_intc/In0 axi_timer/interrupt +ad_connect sys_concat_intc/In1 axi_ethernet/interrupt +ad_connect sys_concat_intc/In2 axi_ethernet_dma/mm2s_introut +ad_connect sys_concat_intc/In3 axi_ethernet_dma/s2mm_introut +ad_connect sys_concat_intc/In4 axi_uart/interrupt +ad_connect sys_concat_intc/In5 mb_intr_05 +ad_connect sys_concat_intc/In6 mb_intr_06 +ad_connect sys_concat_intc/In7 mb_intr_07 +ad_connect sys_concat_intc/In8 mb_intr_08 +ad_connect sys_concat_intc/In9 axi_iic_main/iic2intc_irpt +ad_connect sys_concat_intc/In10 axi_spi/ip2intc_irpt +ad_connect sys_concat_intc/In11 axi_gpio/ip2intc_irpt +ad_connect sys_concat_intc/In12 mb_intr_12 +ad_connect sys_concat_intc/In13 mb_intr_13 +ad_connect sys_concat_intc/In14 mb_intr_14 +ad_connect sys_concat_intc/In15 mb_intr_15 + +# interconnect - processor ad_cpu_interconnect 0x41400000 sys_mb_debug ad_cpu_interconnect 0x40E00000 axi_ethernet @@ -252,31 +239,27 @@ ad_cpu_interconnect 0x41600000 axi_iic_main ad_cpu_interconnect 0x40000000 axi_gpio ad_cpu_interconnect 0x44A70000 axi_spi -create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_ddr_interconnect -set_property CONFIG.NUM_MI {1} [get_bd_cells axi_ddr_interconnect] -set_property CONFIG.NUM_SI {1} [get_bd_cells axi_ddr_interconnect] -set_property CONFIG.S00_HAS_REGSLICE {4} [get_bd_cells axi_ddr_interconnect] -set_property CONFIG.S00_HAS_DATA_FIFO {1} [get_bd_cells axi_ddr_interconnect] +# interconnect - memory -ad_connect axi_ddr_interconnect/M00_AXI axi_ddr_cntrl/C0_DDR4_S_AXI -ad_connect sys_mem_clk axi_ddr_interconnect/ACLK -ad_connect sys_mem_clk axi_ddr_interconnect/M00_ACLK -ad_connect sys_mem_resetn axi_ddr_interconnect/ARESETN -ad_connect sys_mem_resetn axi_ddr_interconnect/M00_ARESETN -ad_connect sys_cpu_resetn axi_ddr_interconnect/S00_ARESETN +#ad_connect sys_mem_resetn axi_ddr_interconnect/ARESETN +#ad_connect sys_mem_resetn axi_ddr_interconnect/M00_ARESETN -ad_mem_hp0_interconnect sys_cpu_clk axi_ddr_interconnect/S00_AXI +ad_mem_hp0_interconnect sys_mem_clk axi_ddr_cntrl/C0_DDR4_S_AXI ad_mem_hp0_interconnect sys_cpu_clk sys_mb/M_AXI_DC ad_mem_hp0_interconnect sys_cpu_clk sys_mb/M_AXI_IC ad_mem_hp0_interconnect sys_cpu_clk axi_ethernet_dma/M_AXI_SG ad_mem_hp0_interconnect sys_cpu_clk axi_ethernet_dma/M_AXI_MM2S ad_mem_hp0_interconnect sys_cpu_clk axi_ethernet_dma/M_AXI_S2MM +ad_disconnect sys_mem_clk axi_mem_interconnect/ACLK +ad_disconnect sys_mem_resetn axi_mem_interconnect/ARESETN + +ad_connect sys_cpu_clk axi_mem_interconnect/ACLK +ad_connect sys_cpu_resetn axi_mem_interconnect/ARESETN + create_bd_addr_seg -range 0x20000 -offset 0x0 [get_bd_addr_spaces sys_mb/Data] \ [get_bd_addr_segs sys_dlmb_cntlr/SLMB/Mem] SEG_dlmb_cntlr create_bd_addr_seg -range 0x20000 -offset 0x0 [get_bd_addr_spaces sys_mb/Instruction] \ [get_bd_addr_segs sys_ilmb_cntlr/SLMB/Mem] SEG_ilmb_cntlr - - diff --git a/projects/common/microzed/microzed_system_bd.tcl b/projects/common/microzed/microzed_system_bd.tcl new file mode 100644 index 000000000..f0d3eb673 --- /dev/null +++ b/projects/common/microzed/microzed_system_bd.tcl @@ -0,0 +1,129 @@ + +# create board design +# interface ports + +create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr +create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 fixed_io + +create_bd_port -dir O spi0_csn_2_o +create_bd_port -dir O spi0_csn_1_o +create_bd_port -dir O spi0_csn_0_o +create_bd_port -dir I spi0_csn_i +create_bd_port -dir I spi0_clk_i +create_bd_port -dir O spi0_clk_o +create_bd_port -dir I spi0_sdo_i +create_bd_port -dir O spi0_sdo_o +create_bd_port -dir I spi0_sdi_i + +create_bd_port -dir O spi1_csn_2_o +create_bd_port -dir O spi1_csn_1_o +create_bd_port -dir O spi1_csn_0_o +create_bd_port -dir I spi1_csn_i +create_bd_port -dir I spi1_clk_i +create_bd_port -dir O spi1_clk_o +create_bd_port -dir I spi1_sdo_i +create_bd_port -dir O spi1_sdo_o +create_bd_port -dir I spi1_sdi_i + +create_bd_port -dir I -from 63 -to 0 gpio_i +create_bd_port -dir O -from 63 -to 0 gpio_o +create_bd_port -dir O -from 63 -to 0 gpio_t + +# instance: sys_ps7 + +set sys_ps7 [create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 sys_ps7] +source $ad_hdl_dir/projects/common/microzed/microzed_system_ps7.tcl +set_property -dict [list CONFIG.PCW_TTC0_PERIPHERAL_ENABLE {0}] $sys_ps7 +set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_IO {64}] $sys_ps7 +set_property -dict [list CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_SPI0_SPI0_IO {EMIO}] $sys_ps7 +set_property -dict [list CONFIG.PCW_SPI1_PERIPHERAL_ENABLE {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_SPI1_SPI1_IO {EMIO}] $sys_ps7 +set_property -dict [list CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100.0}] $sys_ps7 +set_property -dict [list CONFIG.PCW_USE_FABRIC_INTERRUPT {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_IRQ_F2P_INTR {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_IRQ_F2P_MODE {REVERSE}] $sys_ps7 + +set sys_concat_intc [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 sys_concat_intc] +set_property -dict [list CONFIG.NUM_PORTS {16}] $sys_concat_intc + +set sys_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 sys_rstgen] +set_property -dict [list CONFIG.C_EXT_RST_WIDTH {1}] $sys_rstgen + +# interrupts + +create_bd_port -dir I -type intr ps_intr_00 +create_bd_port -dir I -type intr ps_intr_01 +create_bd_port -dir I -type intr ps_intr_02 +create_bd_port -dir I -type intr ps_intr_03 +create_bd_port -dir I -type intr ps_intr_04 +create_bd_port -dir I -type intr ps_intr_05 +create_bd_port -dir I -type intr ps_intr_06 +create_bd_port -dir I -type intr ps_intr_07 +create_bd_port -dir I -type intr ps_intr_08 +create_bd_port -dir I -type intr ps_intr_09 +create_bd_port -dir I -type intr ps_intr_10 +create_bd_port -dir I -type intr ps_intr_11 +create_bd_port -dir I -type intr ps_intr_12 +create_bd_port -dir I -type intr ps_intr_13 +create_bd_port -dir I -type intr ps_intr_14 +create_bd_port -dir I -type intr ps_intr_15 + +# system reset/clock definitions + +ad_connect sys_cpu_clk sys_ps7/FCLK_CLK0 +ad_connect sys_cpu_reset sys_rstgen/peripheral_reset +ad_connect sys_cpu_resetn sys_rstgen/peripheral_aresetn +ad_connect sys_cpu_clk sys_rstgen/slowest_sync_clk +ad_connect sys_rstgen/ext_reset_in sys_ps7/FCLK_RESET0_N + +# interface connections + +ad_connect ddr sys_ps7/DDR +ad_connect gpio_i sys_ps7/GPIO_I +ad_connect gpio_o sys_ps7/GPIO_O +ad_connect gpio_t sys_ps7/GPIO_T +ad_connect fixed_io sys_ps7/FIXED_IO + +# spi connections + +ad_connect spi0_csn_2_o sys_ps7/SPI0_SS2_O +ad_connect spi0_csn_1_o sys_ps7/SPI0_SS1_O +ad_connect spi0_csn_0_o sys_ps7/SPI0_SS_O +ad_connect spi0_csn_i sys_ps7/SPI0_SS_I +ad_connect spi0_clk_i sys_ps7/SPI0_SCLK_I +ad_connect spi0_clk_o sys_ps7/SPI0_SCLK_O +ad_connect spi0_sdo_i sys_ps7/SPI0_MOSI_I +ad_connect spi0_sdo_o sys_ps7/SPI0_MOSI_O +ad_connect spi0_sdi_i sys_ps7/SPI0_MISO_I + +ad_connect spi1_csn_2_o sys_ps7/SPI1_SS2_O +ad_connect spi1_csn_1_o sys_ps7/SPI1_SS1_O +ad_connect spi1_csn_0_o sys_ps7/SPI1_SS_O +ad_connect spi1_csn_i sys_ps7/SPI1_SS_I +ad_connect spi1_clk_i sys_ps7/SPI1_SCLK_I +ad_connect spi1_clk_o sys_ps7/SPI1_SCLK_O +ad_connect spi1_sdo_i sys_ps7/SPI1_MOSI_I +ad_connect spi1_sdo_o sys_ps7/SPI1_MOSI_O +ad_connect spi1_sdi_i sys_ps7/SPI1_MISO_I + +# interrupts + +ad_connect sys_concat_intc/dout sys_ps7/IRQ_F2P +ad_connect sys_concat_intc/In15 ps_intr_15 +ad_connect sys_concat_intc/In14 ps_intr_14 +ad_connect sys_concat_intc/In13 ps_intr_13 +ad_connect sys_concat_intc/In12 ps_intr_12 +ad_connect sys_concat_intc/In11 ps_intr_11 +ad_connect sys_concat_intc/In10 ps_intr_10 +ad_connect sys_concat_intc/In9 ps_intr_09 +ad_connect sys_concat_intc/In8 ps_intr_08 +ad_connect sys_concat_intc/In7 ps_intr_07 +ad_connect sys_concat_intc/In6 ps_intr_06 +ad_connect sys_concat_intc/In5 ps_intr_05 +ad_connect sys_concat_intc/In4 ps_intr_04 +ad_connect sys_concat_intc/In3 ps_intr_03 +ad_connect sys_concat_intc/In2 ps_intr_02 +ad_connect sys_concat_intc/In1 ps_intr_01 +ad_connect sys_concat_intc/In0 ps_intr_00 diff --git a/projects/common/microzed/microzed_system_constr.xdc b/projects/common/microzed/microzed_system_constr.xdc new file mode 100644 index 000000000..1f118304a --- /dev/null +++ b/projects/common/microzed/microzed_system_constr.xdc @@ -0,0 +1,3 @@ + +# constraints + diff --git a/projects/common/microzed/microzed_system_ps7.tcl b/projects/common/microzed/microzed_system_ps7.tcl new file mode 100755 index 000000000..9aac962c6 --- /dev/null +++ b/projects/common/microzed/microzed_system_ps7.tcl @@ -0,0 +1,145 @@ + +set_property CONFIG.PCW_PRESET_BANK0_VOLTAGE {LVCMOS 3.3V} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 1.8V} [get_bd_cells sys_ps7] + +set_property CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {1} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_ENET0_PERIPHERAL_ENABLE {1} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_ENET0_ENET0_IO {MIO 16 .. 27} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_ENET0_GRP_MDIO_ENABLE {1} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_ENET0_GRP_MDIO_IO {MIO 52 .. 53} [get_bd_cells sys_ps7] + +set_property CONFIG.PCW_USB0_PERIPHERAL_ENABLE {1} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_USB0_RESET_ENABLE {1} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_USB0_RESET_IO {MIO 7} [get_bd_cells sys_ps7] + +set_property CONFIG.PCW_SD0_PERIPHERAL_ENABLE {1} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_SD0_GRP_CD_ENABLE {1} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_SD0_GRP_CD_IO {MIO 46} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_SD0_GRP_WP_ENABLE {1} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_SD0_GRP_WP_IO {MIO 50} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ {50} [get_bd_cells sys_ps7] + +set_property CONFIG.PCW_UART1_PERIPHERAL_ENABLE {1} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_UART_PERIPHERAL_FREQMHZ {50} [get_bd_cells sys_ps7] + +set_property CONFIG.PCW_QSPI_PERIPHERAL_ENABLE {1} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE {1} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_QSPI_GRP_FBCLK_ENABLE {1} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_TTC0_PERIPHERAL_ENABLE {1} [get_bd_cells sys_ps7] + +set_property CONFIG.PCW_UIPARAM_DDR_PARTNO {MT41K256M16 RE-125} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_UIPARAM_DDR_USE_INTERNAL_VREF {1} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL {1} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_UIPARAM_DDR_TRAIN_READ_GATE {1} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_UIPARAM_DDR_TRAIN_DATA_EYE {1} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 {-0.073} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 {-0.072} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 {0.024} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 {0.023} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0 {0.294} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1 {0.298} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2 {0.338} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3 {0.334} [get_bd_cells sys_ps7] + +set_property CONFIG.PCW_MIO_0_PULLUP {disabled} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_MIO_1_PULLUP {disabled} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_MIO_9_PULLUP {disabled} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_MIO_10_PULLUP {disabled} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_MIO_11_PULLUP {disabled} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_MIO_12_PULLUP {disabled} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_MIO_13_PULLUP {disabled} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_MIO_14_PULLUP {disabled} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_MIO_15_PULLUP {disabled} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_MIO_16_PULLUP {disabled} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_MIO_17_PULLUP {disabled} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_MIO_18_PULLUP {disabled} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_MIO_19_PULLUP {disabled} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_MIO_20_PULLUP {disabled} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_MIO_21_PULLUP {disabled} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_MIO_22_PULLUP {disabled} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_MIO_23_PULLUP {disabled} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_MIO_24_PULLUP {disabled} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_MIO_25_PULLUP {disabled} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_MIO_26_PULLUP {disabled} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_MIO_27_PULLUP {disabled} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_MIO_28_PULLUP {disabled} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_MIO_29_PULLUP {disabled} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_MIO_30_PULLUP {disabled} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_MIO_31_PULLUP {disabled} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_MIO_32_PULLUP {disabled} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_MIO_33_PULLUP {disabled} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_MIO_34_PULLUP {disabled} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_MIO_35_PULLUP {disabled} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_MIO_36_PULLUP {disabled} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_MIO_37_PULLUP {disabled} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_MIO_38_PULLUP {disabled} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_MIO_39_PULLUP {disabled} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_MIO_40_PULLUP {disabled} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_MIO_41_PULLUP {disabled} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_MIO_42_PULLUP {disabled} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_MIO_43_PULLUP {disabled} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_MIO_44_PULLUP {disabled} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_MIO_45_PULLUP {disabled} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_MIO_46_PULLUP {disabled} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_MIO_47_PULLUP {disabled} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_MIO_48_PULLUP {disabled} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_MIO_49_PULLUP {disabled} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_MIO_50_PULLUP {disabled} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_MIO_51_PULLUP {disabled} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_MIO_52_PULLUP {disabled} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_MIO_53_PULLUP {disabled} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_MIO_0_SLEW {slow} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_MIO_1_SLEW {slow} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_MIO_2_SLEW {slow} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_MIO_3_SLEW {slow} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_MIO_4_SLEW {slow} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_MIO_5_SLEW {slow} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_MIO_6_SLEW {slow} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_MIO_7_SLEW {slow} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_MIO_8_SLEW {slow} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_MIO_9_SLEW {slow} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_MIO_10_SLEW {slow} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_MIO_11_SLEW {slow} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_MIO_12_SLEW {slow} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_MIO_13_SLEW {slow} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_MIO_14_SLEW {slow} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_MIO_15_SLEW {slow} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_MIO_16_SLEW {slow} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_MIO_17_SLEW {slow} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_MIO_18_SLEW {slow} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_MIO_19_SLEW {slow} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_MIO_20_SLEW {slow} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_MIO_21_SLEW {slow} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_MIO_22_SLEW {slow} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_MIO_23_SLEW {slow} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_MIO_24_SLEW {slow} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_MIO_25_SLEW {slow} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_MIO_26_SLEW {slow} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_MIO_27_SLEW {slow} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_MIO_28_SLEW {slow} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_MIO_29_SLEW {slow} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_MIO_30_SLEW {slow} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_MIO_31_SLEW {slow} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_MIO_32_SLEW {slow} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_MIO_33_SLEW {slow} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_MIO_34_SLEW {slow} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_MIO_35_SLEW {slow} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_MIO_36_SLEW {slow} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_MIO_37_SLEW {slow} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_MIO_38_SLEW {slow} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_MIO_39_SLEW {slow} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_MIO_40_SLEW {slow} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_MIO_41_SLEW {slow} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_MIO_42_SLEW {slow} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_MIO_43_SLEW {slow} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_MIO_44_SLEW {slow} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_MIO_45_SLEW {slow} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_MIO_46_SLEW {slow} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_MIO_47_SLEW {slow} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_MIO_48_SLEW {slow} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_MIO_49_SLEW {slow} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_MIO_50_SLEW {slow} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_MIO_51_SLEW {slow} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_MIO_52_SLEW {slow} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_MIO_53_SLEW {slow} [get_bd_cells sys_ps7] + diff --git a/projects/common/mitx045/mitx045_system_bd.tcl b/projects/common/mitx045/mitx045_system_bd.tcl index c114e8302..63c19e1fd 100644 --- a/projects/common/mitx045/mitx045_system_bd.tcl +++ b/projects/common/mitx045/mitx045_system_bd.tcl @@ -111,7 +111,7 @@ set_property -dict [list CONFIG.C_INCLUDE_S2MM {0}] $axi_hdmi_dma # audio peripherals -set sys_audio_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.2 sys_audio_clkgen] +set sys_audio_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.3 sys_audio_clkgen] set_property -dict [list CONFIG.PRIM_IN_FREQ {200.000}] $sys_audio_clkgen set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {12.288}] $sys_audio_clkgen set_property -dict [list CONFIG.USE_LOCKED {false}] $sys_audio_clkgen diff --git a/projects/common/pzsdr/pzsdr_system_constr.xdc b/projects/common/pzsdr/pzsdr_system_constr.xdc deleted file mode 100644 index ef43a4869..000000000 --- a/projects/common/pzsdr/pzsdr_system_constr.xdc +++ /dev/null @@ -1,88 +0,0 @@ - -# constraints -# ad9361 - -set_property -dict {PACKAGE_PIN J14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_clk_in_p] ; ## IO_L12P_T1_MRCC_35 -set_property -dict {PACKAGE_PIN H14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_clk_in_n] ; ## IO_L12N_T1_MRCC_35 -set_property -dict {PACKAGE_PIN H13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_frame_in_p] ; ## IO_L7P_T1_AD2P_35 -set_property -dict {PACKAGE_PIN H12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_frame_in_n] ; ## IO_L7N_T1_AD2N_35 -set_property -dict {PACKAGE_PIN F12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_p[0]] ; ## IO_L1P_T0_AD0P_35 -set_property -dict {PACKAGE_PIN E12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_n[0]] ; ## IO_L1N_T0_AD0N_35 -set_property -dict {PACKAGE_PIN E10 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_p[1]] ; ## IO_L2P_T0_AD8P_35 -set_property -dict {PACKAGE_PIN D10 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_n[1]] ; ## IO_L2N_T0_AD8N_35 -set_property -dict {PACKAGE_PIN G10 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_p[2]] ; ## IO_L3P_T0_DQS_AD1P_35 -set_property -dict {PACKAGE_PIN F10 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_n[2]] ; ## IO_L3N_T0_DQS_AD1N_35 -set_property -dict {PACKAGE_PIN E11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_p[3]] ; ## IO_L4P_T0_35 -set_property -dict {PACKAGE_PIN D11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_n[3]] ; ## IO_L4N_T0_35 -set_property -dict {PACKAGE_PIN G12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_p[4]] ; ## IO_L5P_T0_AD9P_35 -set_property -dict {PACKAGE_PIN G11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_n[4]] ; ## IO_L5N_T0_AD9N_35 -set_property -dict {PACKAGE_PIN F13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_p[5]] ; ## IO_L6P_T0_35 -set_property -dict {PACKAGE_PIN E13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_n[5]] ; ## IO_L6N_T0_VREF_35 -set_property -dict {PACKAGE_PIN K13 IOSTANDARD LVDS} [get_ports tx_clk_out_p] ; ## IO_L8P_T1_AD10P_35 -set_property -dict {PACKAGE_PIN J13 IOSTANDARD LVDS} [get_ports tx_clk_out_n] ; ## IO_L8N_T1_AD10N_35 -set_property -dict {PACKAGE_PIN K15 IOSTANDARD LVDS} [get_ports tx_frame_out_p] ; ## IO_L9P_T1_DQS_AD3P_35 -set_property -dict {PACKAGE_PIN J15 IOSTANDARD LVDS} [get_ports tx_frame_out_n] ; ## IO_L9N_T1_DQS_AD3N_35 -set_property -dict {PACKAGE_PIN D15 IOSTANDARD LVDS} [get_ports tx_data_out_p[0]] ; ## IO_L13P_T2_MRCC_35 -set_property -dict {PACKAGE_PIN D14 IOSTANDARD LVDS} [get_ports tx_data_out_n[0]] ; ## IO_L13N_T2_MRCC_35 -set_property -dict {PACKAGE_PIN F15 IOSTANDARD LVDS} [get_ports tx_data_out_p[1]] ; ## IO_L14P_T2_AD4P_SRCC_35 -set_property -dict {PACKAGE_PIN E15 IOSTANDARD LVDS} [get_ports tx_data_out_n[1]] ; ## IO_L14N_T2_AD4N_SRCC_35 -set_property -dict {PACKAGE_PIN C17 IOSTANDARD LVDS} [get_ports tx_data_out_p[2]] ; ## IO_L15P_T2_DQS_AD12P_35 -set_property -dict {PACKAGE_PIN C16 IOSTANDARD LVDS} [get_ports tx_data_out_n[2]] ; ## IO_L15N_T2_DQS_AD12N_35 -set_property -dict {PACKAGE_PIN E16 IOSTANDARD LVDS} [get_ports tx_data_out_p[3]] ; ## IO_L16P_T2_35 -set_property -dict {PACKAGE_PIN D16 IOSTANDARD LVDS} [get_ports tx_data_out_n[3]] ; ## IO_L16N_T2_35 -set_property -dict {PACKAGE_PIN B16 IOSTANDARD LVDS} [get_ports tx_data_out_p[4]] ; ## IO_L17P_T2_AD5P_35 -set_property -dict {PACKAGE_PIN B15 IOSTANDARD LVDS} [get_ports tx_data_out_n[4]] ; ## IO_L17N_T2_AD5N_35 -set_property -dict {PACKAGE_PIN B17 IOSTANDARD LVDS} [get_ports tx_data_out_p[5]] ; ## IO_L18P_T2_AD13P_35 -set_property -dict {PACKAGE_PIN A17 IOSTANDARD LVDS} [get_ports tx_data_out_n[5]] ; ## IO_L18N_T2_AD13N_35 -set_property -dict {PACKAGE_PIN G14 IOSTANDARD LVCMOS18} [get_ports enable] ; ## IO_L11P_T1_SRCC_35 -set_property -dict {PACKAGE_PIN F14 IOSTANDARD LVCMOS18} [get_ports txnrx] ; ## IO_L11N_T1_SRCC_35 - -set_property -dict {PACKAGE_PIN D13 IOSTANDARD LVCMOS18} [get_ports gpio_status[0]] ; ## IO_L19P_T3_35 -set_property -dict {PACKAGE_PIN C13 IOSTANDARD LVCMOS18} [get_ports gpio_status[1]] ; ## IO_L19N_T3_VREF_35 -set_property -dict {PACKAGE_PIN C14 IOSTANDARD LVCMOS18} [get_ports gpio_status[2]] ; ## IO_L20P_T3_AD6P_35 -set_property -dict {PACKAGE_PIN B14 IOSTANDARD LVCMOS18} [get_ports gpio_status[3]] ; ## IO_L20N_T3_AD6N_35 -set_property -dict {PACKAGE_PIN A15 IOSTANDARD LVCMOS18} [get_ports gpio_status[4]] ; ## IO_L21P_T3_DQS_AD14P_35 -set_property -dict {PACKAGE_PIN A14 IOSTANDARD LVCMOS18} [get_ports gpio_status[5]] ; ## IO_L21N_T3_DQS_AD14N_35 -set_property -dict {PACKAGE_PIN C12 IOSTANDARD LVCMOS18} [get_ports gpio_status[6]] ; ## IO_L22P_T3_AD7P_35 -set_property -dict {PACKAGE_PIN B12 IOSTANDARD LVCMOS18} [get_ports gpio_status[7]] ; ## IO_L22N_T3_AD7N_35 -set_property -dict {PACKAGE_PIN C2 IOSTANDARD LVCMOS18} [get_ports gpio_ctl[0]] ; ## IO_L23P_T3_34 -set_property -dict {PACKAGE_PIN B1 IOSTANDARD LVCMOS18} [get_ports gpio_ctl[1]] ; ## IO_L23N_T3_34 -set_property -dict {PACKAGE_PIN B2 IOSTANDARD LVCMOS18} [get_ports gpio_ctl[2]] ; ## IO_L24P_T3_34 -set_property -dict {PACKAGE_PIN A2 IOSTANDARD LVCMOS18} [get_ports gpio_ctl[3]] ; ## IO_L24N_T3_34 -set_property -dict {PACKAGE_PIN G16 IOSTANDARD LVCMOS18} [get_ports gpio_en_agc] ; ## IO_L10P_T1_AD11P_35 -set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVCMOS18} [get_ports gpio_sync] ; ## IO_L10N_T1_AD11N_35 -set_property -dict {PACKAGE_PIN H16 IOSTANDARD LVCMOS18} [get_ports gpio_resetb] ; ## IO_0_VRN_35 -set_property -dict {PACKAGE_PIN K11 IOSTANDARD LVCMOS18} [get_ports gpio_clksel] ; ## IO_0_VRN_34 - -set_property -dict {PACKAGE_PIN C11 IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports spi_csn] ; ## IO_L23P_T3_35 -set_property -dict {PACKAGE_PIN B11 IOSTANDARD LVCMOS18} [get_ports spi_clk] ; ## IO_L23N_T3_35 -set_property -dict {PACKAGE_PIN A13 IOSTANDARD LVCMOS18} [get_ports spi_mosi] ; ## IO_L24P_T3_AD15P_35 -set_property -dict {PACKAGE_PIN A12 IOSTANDARD LVCMOS18} [get_ports spi_miso] ; ## IO_L24N_T3_AD15N_35 - -set_property -dict {PACKAGE_PIN K12 IOSTANDARD LVCMOS18} [get_ports clk_out] ; ## IO_25_VRP_35 - -# iic - -set_property -dict {PACKAGE_PIN AF24 IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports iic_scl] ; ## IO_L5P_T0_13 -set_property -dict {PACKAGE_PIN AF25 IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports iic_sda] ; ## IO_L5N_T0_13 - -# gpio - -set_property -dict {PACKAGE_PIN J3 IOSTANDARD LVCMOS18} [get_ports gpio_bd[0]] ; ## (pb) IO_L12N_T1_MRCC_33 -set_property -dict {PACKAGE_PIN D8 IOSTANDARD LVCMOS18} [get_ports gpio_bd[1]] ; ## (pb) IO_L8N_T1_34 -set_property -dict {PACKAGE_PIN F9 IOSTANDARD LVCMOS18} [get_ports gpio_bd[2]] ; ## (pb) IO_L9P_T1_DQS_34 -set_property -dict {PACKAGE_PIN E8 IOSTANDARD LVCMOS18} [get_ports gpio_bd[3]] ; ## (pb) IO_L9N_T1_DQS_34 -set_property -dict {PACKAGE_PIN A8 IOSTANDARD LVCMOS18} [get_ports gpio_bd[4]] ; ## (led) IO_L17N_T2_34 -set_property -dict {PACKAGE_PIN W14 IOSTANDARD LVCMOS25} [get_ports gpio_bd[5]] ; ## (led) IO_0_12 -set_property -dict {PACKAGE_PIN W17 IOSTANDARD LVCMOS25} [get_ports gpio_bd[6]] ; ## (led) IO_25_12 -set_property -dict {PACKAGE_PIN Y16 IOSTANDARD LVCMOS25} [get_ports gpio_bd[7]] ; ## (led) IO_L23P_T3_12 -set_property -dict {PACKAGE_PIN Y15 IOSTANDARD LVCMOS25} [get_ports gpio_bd[8]] ; ## (dip) IO_L23N_T3_12 -set_property -dict {PACKAGE_PIN W16 IOSTANDARD LVCMOS25} [get_ports gpio_bd[9]] ; ## (dip) IO_L24P_T3_12 -set_property -dict {PACKAGE_PIN W15 IOSTANDARD LVCMOS25} [get_ports gpio_bd[10]] ; ## (dip) IO_L24N_T3_12 -set_property -dict {PACKAGE_PIN V19 IOSTANDARD LVCMOS25} [get_ports gpio_bd[11]] ; ## (dip) IO_0_13 - -# clocks - -create_clock -name rx_clk -period 4 [get_ports rx_clk_in_p] -create_clock -name ad9361_clk -period 4 [get_pins i_system_wrapper/system_i/axi_ad9361/clk] - diff --git a/projects/common/pzsdr/pzsdr_system_ps7.tcl b/projects/common/pzsdr/pzsdr_system_ps7.tcl deleted file mode 100755 index fd86195cf..000000000 --- a/projects/common/pzsdr/pzsdr_system_ps7.tcl +++ /dev/null @@ -1,43 +0,0 @@ - -set_property CONFIG.PCW_PRESET_BANK0_VOLTAGE {LVCMOS 1.8V} [get_bd_cells sys_ps7] -set_property CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 1.8V} [get_bd_cells sys_ps7] -set_property CONFIG.PCW_PACKAGE_NAME {fbg676} [get_bd_cells sys_ps7] - -set_property CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {1} [get_bd_cells sys_ps7] -set_property CONFIG.PCW_ENET0_PERIPHERAL_ENABLE {1} [get_bd_cells sys_ps7] -set_property CONFIG.PCW_ENET0_ENET0_IO {MIO 16 .. 27} [get_bd_cells sys_ps7] -set_property CONFIG.PCW_ENET0_GRP_MDIO_ENABLE {1} [get_bd_cells sys_ps7] -set_property CONFIG.PCW_ENET1_PERIPHERAL_ENABLE {1} [get_bd_cells sys_ps7] -set_property CONFIG.PCW_ENET_RESET_SELECT {Separate reset pins} [get_bd_cells sys_ps7] -set_property CONFIG.PCW_ENET0_RESET_ENABLE {1} [get_bd_cells sys_ps7] -set_property CONFIG.PCW_ENET0_RESET_IO {MIO 8} [get_bd_cells sys_ps7] -set_property CONFIG.PCW_ENET1_RESET_ENABLE {1} [get_bd_cells sys_ps7] -set_property CONFIG.PCW_ENET1_RESET_IO {MIO 51} [get_bd_cells sys_ps7] - -set_property CONFIG.PCW_SD0_PERIPHERAL_ENABLE {1} [get_bd_cells sys_ps7] -set_property CONFIG.PCW_SD0_GRP_CD_ENABLE {1} [get_bd_cells sys_ps7] -set_property CONFIG.PCW_SD0_GRP_CD_IO {MIO 50} [get_bd_cells sys_ps7] -set_property CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ {50} [get_bd_cells sys_ps7] -set_property CONFIG.PCW_UART1_PERIPHERAL_ENABLE {1} [get_bd_cells sys_ps7] -set_property CONFIG.PCW_USB0_PERIPHERAL_ENABLE {1} [get_bd_cells sys_ps7] -set_property CONFIG.PCW_USB0_RESET_ENABLE {1} [get_bd_cells sys_ps7] -set_property CONFIG.PCW_USB0_RESET_IO {MIO 7} [get_bd_cells sys_ps7] -set_property CONFIG.PCW_QSPI_PERIPHERAL_ENABLE {1} [get_bd_cells sys_ps7] - -## DDR MT41K256M16 HA-125 (32M, 16bit, 8banks) - -set_property CONFIG.PCW_UIPARAM_DDR_PARTNO {MT41K256M16 RE-125} [get_bd_cells sys_ps7] -set_property CONFIG.PCW_UIPARAM_DDR_BUS_WIDTH {32 Bit} [get_bd_cells sys_ps7] -set_property CONFIG.PCW_UIPARAM_DDR_USE_INTERNAL_VREF {0} [get_bd_cells sys_ps7] -set_property CONFIG.PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL {1} [get_bd_cells sys_ps7] -set_property CONFIG.PCW_UIPARAM_DDR_TRAIN_READ_GATE {1} [get_bd_cells sys_ps7] -set_property CONFIG.PCW_UIPARAM_DDR_TRAIN_DATA_EYE {1} [get_bd_cells sys_ps7] -set_property CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 {-0.053} [get_bd_cells sys_ps7] -set_property CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 {-0.059} [get_bd_cells sys_ps7] -set_property CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 {0.065} [get_bd_cells sys_ps7] -set_property CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 {0.066} [get_bd_cells sys_ps7] -set_property CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0 {0.264} [get_bd_cells sys_ps7] -set_property CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1 {0.265} [get_bd_cells sys_ps7] -set_property CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2 {0.330} [get_bd_cells sys_ps7] -set_property CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3 {0.330} [get_bd_cells sys_ps7] - diff --git a/projects/common/vc707/vc707_system_bd.tcl b/projects/common/vc707/vc707_system_bd.tcl index 37c94841f..113d45541 100644 --- a/projects/common/vc707/vc707_system_bd.tcl +++ b/projects/common/vc707/vc707_system_bd.tcl @@ -49,7 +49,7 @@ set_property -dict [list CONFIG.POLARITY {ACTIVE_HIGH}] [get_bd_ports sys_rst] # instance: microblaze - processor -set sys_mb [create_bd_cell -type ip -vlnv xilinx.com:ip:microblaze:9.5 sys_mb] +set sys_mb [create_bd_cell -type ip -vlnv xilinx.com:ip:microblaze:9.6 sys_mb] set_property -dict [list CONFIG.G_TEMPLATE_LIST {4}] $sys_mb set_property -dict [list CONFIG.C_DCACHE_FORCE_TAG_LUTRAM {1}] $sys_mb @@ -78,7 +78,7 @@ set sys_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 s # instance: ddr (mig) -set axi_ddr_cntrl [create_bd_cell -type ip -vlnv xilinx.com:ip:mig_7series:2.4 axi_ddr_cntrl] +set axi_ddr_cntrl [create_bd_cell -type ip -vlnv xilinx.com:ip:mig_7series:4.0 axi_ddr_cntrl] set axi_ddr_cntrl_dir [get_property IP_DIR [get_ips [get_property CONFIG.Component_Name $axi_ddr_cntrl]]] file copy -force $ad_hdl_dir/projects/common/vc707/vc707_system_mig.prj "$axi_ddr_cntrl_dir/" set_property -dict [list CONFIG.XML_INPUT_FILE {vc707_system_mig.prj}] $axi_ddr_cntrl diff --git a/projects/common/xilinx/sys_adcfifo.tcl b/projects/common/xilinx/sys_adcfifo.tcl new file mode 100644 index 000000000..2c07f900f --- /dev/null +++ b/projects/common/xilinx/sys_adcfifo.tcl @@ -0,0 +1,50 @@ + +# sys bram (use only when dma is not capable of keeping up). +# generic fifo interface - existence is oblivious to software. + +proc p_sys_adcfifo {p_name m_name adc_data_width dma_addr_width} { + + global ad_hdl_dir + + set p_instance [get_bd_cells $p_name] + set c_instance [current_bd_instance .] + + current_bd_instance $p_instance + + set m_instance [create_bd_cell -type hier $m_name] + current_bd_instance $m_instance + + create_bd_pin -dir I adc_rst + create_bd_pin -dir I -type clk adc_clk + create_bd_pin -dir I adc_wr + create_bd_pin -dir I -from [expr ($adc_data_width-1)] -to 0 adc_wdata + create_bd_pin -dir O adc_wovf + + create_bd_pin -dir I -type clk dma_clk + create_bd_pin -dir O dma_wr + create_bd_pin -dir O -from 63 -to 0 dma_wdata + create_bd_pin -dir I dma_wready + create_bd_pin -dir I dma_xfer_req + create_bd_pin -dir O -from 3 -to 0 dma_xfer_status + + set util_adcfifo [create_bd_cell -type ip -vlnv analog.com:user:util_adcfifo:1.0 util_adcfifo] + set_property -dict [list CONFIG.ADC_DATA_WIDTH $adc_data_width] $util_adcfifo + set_property -dict [list CONFIG.DMA_DATA_WIDTH {64}] $util_adcfifo + set_property -dict [list CONFIG.DMA_READY_ENABLE {1}] $util_adcfifo + set_property -dict [list CONFIG.DMA_ADDRESS_WIDTH $dma_addr_width] $util_adcfifo + + ad_connect adc_rst util_adcfifo/adc_rst + ad_connect adc_clk util_adcfifo/adc_clk + ad_connect adc_wr util_adcfifo/adc_wr + ad_connect adc_wdata util_adcfifo/adc_wdata + ad_connect adc_wovf util_adcfifo/adc_wovf + ad_connect dma_clk util_adcfifo/dma_clk + ad_connect dma_wr util_adcfifo/dma_wr + ad_connect dma_wdata util_adcfifo/dma_wdata + ad_connect dma_wready util_adcfifo/dma_wready + ad_connect dma_xfer_req util_adcfifo/dma_xfer_req + ad_connect dma_xfer_status util_adcfifo/dma_xfer_status + + current_bd_instance $c_instance +} + diff --git a/projects/common/xilinx/sys_dmafifo.tcl b/projects/common/xilinx/sys_dacfifo.tcl similarity index 51% rename from projects/common/xilinx/sys_dmafifo.tcl rename to projects/common/xilinx/sys_dacfifo.tcl index f6876fd9b..e4ae5132b 100644 --- a/projects/common/xilinx/sys_dmafifo.tcl +++ b/projects/common/xilinx/sys_dacfifo.tcl @@ -2,52 +2,6 @@ # sys bram (use only when dma is not capable of keeping up). # generic fifo interface - existence is oblivious to software. -proc p_sys_dmafifo {p_name m_name adc_data_width dma_addr_width} { - - global ad_hdl_dir - - set p_instance [get_bd_cells $p_name] - set c_instance [current_bd_instance .] - - current_bd_instance $p_instance - - set m_instance [create_bd_cell -type hier $m_name] - current_bd_instance $m_instance - - create_bd_pin -dir I adc_rst - create_bd_pin -dir I -type clk adc_clk - create_bd_pin -dir I adc_wr - create_bd_pin -dir I -from [expr ($adc_data_width-1)] -to 0 adc_wdata - create_bd_pin -dir O adc_wovf - - create_bd_pin -dir I -type clk dma_clk - create_bd_pin -dir O dma_wr - create_bd_pin -dir O -from 63 -to 0 dma_wdata - create_bd_pin -dir I dma_wready - create_bd_pin -dir I dma_xfer_req - create_bd_pin -dir O -from 3 -to 0 dma_xfer_status - - set util_adcfifo [create_bd_cell -type ip -vlnv analog.com:user:util_adcfifo:1.0 util_adcfifo] - set_property -dict [list CONFIG.ADC_DATA_WIDTH $adc_data_width] $util_adcfifo - set_property -dict [list CONFIG.DMA_DATA_WIDTH {64}] $util_adcfifo - set_property -dict [list CONFIG.DMA_READY_ENABLE {1}] $util_adcfifo - set_property -dict [list CONFIG.DMA_ADDRESS_WIDTH $dma_addr_width] $util_adcfifo - - ad_connect adc_rst util_adcfifo/adc_rst - ad_connect adc_clk util_adcfifo/adc_clk - ad_connect adc_wr util_adcfifo/adc_wr - ad_connect adc_wdata util_adcfifo/adc_wdata - ad_connect adc_wovf util_adcfifo/adc_wovf - ad_connect dma_clk util_adcfifo/dma_clk - ad_connect dma_wr util_adcfifo/dma_wr - ad_connect dma_wdata util_adcfifo/dma_wdata - ad_connect dma_wready util_adcfifo/dma_wready - ad_connect dma_xfer_req util_adcfifo/dma_xfer_req - ad_connect dma_xfer_status util_adcfifo/dma_xfer_status - - current_bd_instance $c_instance -} - proc p_sys_dacfifo {p_name m_name data_width addr_width} { global ad_hdl_dir @@ -93,3 +47,4 @@ proc p_sys_dacfifo {p_name m_name data_width addr_width} { current_bd_instance $c_instance } + diff --git a/projects/common/zc702/zc702_system_bd.tcl b/projects/common/zc702/zc702_system_bd.tcl index bbcf32a50..f2d2bb3f2 100644 --- a/projects/common/zc702/zc702_system_bd.tcl +++ b/projects/common/zc702/zc702_system_bd.tcl @@ -100,7 +100,7 @@ set_property -dict [list CONFIG.c_include_s2mm {0}] $axi_hdmi_dma # audio peripherals -set sys_audio_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.2 sys_audio_clkgen] +set sys_audio_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.3 sys_audio_clkgen] set_property -dict [list CONFIG.PRIM_IN_FREQ {200.000}] $sys_audio_clkgen set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {12.288}] $sys_audio_clkgen set_property -dict [list CONFIG.USE_LOCKED {false}] $sys_audio_clkgen diff --git a/projects/common/zc706/zc706_system_bd.tcl b/projects/common/zc706/zc706_system_bd.tcl index 49380211b..0a1776c7c 100644 --- a/projects/common/zc706/zc706_system_bd.tcl +++ b/projects/common/zc706/zc706_system_bd.tcl @@ -103,7 +103,7 @@ set_property -dict [list CONFIG.C_INCLUDE_S2MM {0}] $axi_hdmi_dma # audio peripherals -set sys_audio_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.2 sys_audio_clkgen] +set sys_audio_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.3 sys_audio_clkgen] set_property -dict [list CONFIG.PRIM_IN_FREQ {200.000}] $sys_audio_clkgen set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {12.288}] $sys_audio_clkgen set_property -dict [list CONFIG.USE_LOCKED {false}] $sys_audio_clkgen diff --git a/projects/common/zc706/zc706_system_mig.prj b/projects/common/zc706/zc706_system_mig.prj index 5823f5a31..e56ffb640 100644 --- a/projects/common/zc706/zc706_system_mig.prj +++ b/projects/common/zc706/zc706_system_mig.prj @@ -9,7 +9,7 @@ ON Disabled xc7z045-ffg900/-2 - 2.1 + 4.0 Differential Use System Clock ACTIVE HIGH @@ -24,6 +24,7 @@ 4:1 200 1 + 800 1.000 1 1 diff --git a/projects/common/zc706/zc706_system_plddr3.tcl b/projects/common/zc706/zc706_system_plddr3_adcfifo.tcl similarity index 89% rename from projects/common/zc706/zc706_system_plddr3.tcl rename to projects/common/zc706/zc706_system_plddr3_adcfifo.tcl index 799f55021..23c2c95d3 100644 --- a/projects/common/zc706/zc706_system_plddr3.tcl +++ b/projects/common/zc706/zc706_system_plddr3_adcfifo.tcl @@ -2,7 +2,7 @@ # pl ddr3 (use only when dma is not capable of keeping up). # generic fifo interface - existence is oblivious to software. -proc p_plddr3_fifo {p_name m_name adc_data_width} { +proc p_plddr3_adcfifo {p_name m_name adc_data_width} { global ad_hdl_dir @@ -31,14 +31,12 @@ proc p_plddr3_fifo {p_name m_name adc_data_width} { create_bd_pin -dir I dma_xfer_req create_bd_pin -dir O -from 3 -to 0 dma_xfer_status - set axi_ddr_cntrl [create_bd_cell -type ip -vlnv xilinx.com:ip:mig_7series:2.4 axi_ddr_cntrl] + set axi_ddr_cntrl [create_bd_cell -type ip -vlnv xilinx.com:ip:mig_7series:4.0 axi_ddr_cntrl] set axi_ddr_cntrl_dir [get_property IP_DIR [get_ips [get_property CONFIG.Component_Name $axi_ddr_cntrl]]] file copy -force $ad_hdl_dir/projects/common/zc706/zc706_system_mig.prj "$axi_ddr_cntrl_dir/" set_property -dict [list CONFIG.XML_INPUT_FILE {zc706_system_mig.prj}] $axi_ddr_cntrl set axi_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 axi_rstgen] - set_property -dict [list CONFIG.USE_BOARD_FLOW {true}] $axi_rstgen - set_property -dict [list CONFIG.RESET_BOARD_INTERFACE {reset}] $axi_rstgen set axi_adcfifo [create_bd_cell -type ip -vlnv analog.com:user:axi_adcfifo:1.0 axi_adcfifo] set_property -dict [list CONFIG.ADC_DATA_WIDTH $adc_data_width] $axi_adcfifo @@ -49,7 +47,6 @@ proc p_plddr3_fifo {p_name m_name adc_data_width} { set_property -dict [list CONFIG.AXI_LENGTH {4}] $axi_adcfifo set_property -dict [list CONFIG.AXI_ADDRESS {0x80000000}] $axi_adcfifo set_property -dict [list CONFIG.AXI_ADDRESS_LIMIT {0xa0000000}] $axi_adcfifo - set_property -dict [list CONFIG.AXI_BYTE_WIDTH {64}] $axi_adcfifo ad_connect sys_rst axi_ddr_cntrl/sys_rst ad_connect sys_clk axi_ddr_cntrl/SYS_CLK @@ -57,8 +54,8 @@ proc p_plddr3_fifo {p_name m_name adc_data_width} { ad_connect axi_ddr_cntrl/S_AXI axi_adcfifo/axi ad_connect adc_rst axi_adcfifo/adc_rst ad_connect adc_rst axi_rstgen/ext_reset_in - ad_connect adc_clk axi_adcfifo/adc_clk - ad_connect adc_wr axi_adcfifo/adc_wr + ad_connect adc_clk axi_adcfifo/adc_clk + ad_connect adc_wr axi_adcfifo/adc_wr ad_connect adc_wdata axi_adcfifo/adc_wdata ad_connect adc_wovf axi_adcfifo/adc_wovf ad_connect dma_clk axi_adcfifo/dma_clk diff --git a/projects/common/zc706/zc706_system_plddr3_dacfifo.tcl b/projects/common/zc706/zc706_system_plddr3_dacfifo.tcl new file mode 100644 index 000000000..44a3c9d30 --- /dev/null +++ b/projects/common/zc706/zc706_system_plddr3_dacfifo.tcl @@ -0,0 +1,91 @@ + +# pl ddr3 (use only when dma is not capable of keeping up). +# generic fifo interface - existence is oblivious to software. + +proc p_plddr3_dacfifo {p_name m_name dma_data_width dac_data_width} { + + global ad_hdl_dir + + set p_instance [get_bd_cells $p_name] + set c_instance [current_bd_instance .] + + current_bd_instance $p_instance + + set m_instance [create_bd_cell -type hier $m_name] + current_bd_instance $m_instance + + create_bd_pin -dir I -type rst sys_rst + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr3 + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sys_clk + + create_bd_pin -dir I dac_rst + create_bd_pin -dir I -type clk dac_clk + create_bd_pin -dir I dac_valid + create_bd_pin -dir O -from [expr ($dac_data_width-1)] -to 0 dac_data + create_bd_pin -dir O dac_dunf + create_bd_pin -dir O dac_xfer_out + create_bd_pin -dir I dac_fifo_bypass + + create_bd_pin -dir I -type clk dma_clk + create_bd_pin -dir I dma_rvalid + create_bd_pin -dir I -from [expr ($dma_data_width-1)] -to 0 dma_rdata + create_bd_pin -dir O dma_rready + create_bd_pin -dir I dma_xfer_req + create_bd_pin -dir I dma_xfer_last + + create_bd_pin -dir O ddr_clk + + set axi_ddr_cntrl [create_bd_cell -type ip -vlnv xilinx.com:ip:mig_7series:4.0 axi_ddr_cntrl] + set axi_ddr_cntrl_dir [get_property IP_DIR [get_ips [get_property CONFIG.Component_Name $axi_ddr_cntrl]]] + file copy -force $ad_hdl_dir/projects/common/zc706/zc706_system_mig.prj "$axi_ddr_cntrl_dir/" + set_property -dict [list CONFIG.XML_INPUT_FILE {zc706_system_mig.prj}] $axi_ddr_cntrl + + set axi_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 axi_rstgen] + + set axi_dacfifo [create_bd_cell -type ip -vlnv analog.com:user:axi_dacfifo:1.0 axi_dacfifo] + set_property -dict [list CONFIG.DAC_DATA_WIDTH $dac_data_width] $axi_dacfifo + set_property -dict [list CONFIG.DMA_DATA_WIDTH $dma_data_width] $axi_dacfifo + set_property -dict [list CONFIG.AXI_DATA_WIDTH {512}] $axi_dacfifo + set_property -dict [list CONFIG.AXI_SIZE {6}] $axi_dacfifo + set_property -dict [list CONFIG.AXI_LENGTH {15}] $axi_dacfifo + set_property -dict [list CONFIG.AXI_ADDRESS {0x80000000}] $axi_dacfifo + set_property -dict [list CONFIG.AXI_ADDRESS_LIMIT {0xa0000000}] $axi_dacfifo + + ## clock and reset + + ad_connect sys_clk axi_ddr_cntrl/SYS_CLK + ad_connect sys_rst axi_ddr_cntrl/sys_rst + ad_connect axi_clk axi_ddr_cntrl/ui_clk + ad_connect axi_clk axi_dacfifo/axi_clk + ad_connect axi_clk axi_rstgen/slowest_sync_clk + ad_connect dma_clk axi_dacfifo/dma_clk + ad_connect ddr_clk axi_ddr_cntrl/ui_clk + ad_connect dac_clk axi_dacfifo/dac_clk + + ad_connect axi_resetn axi_rstgen/peripheral_aresetn + ad_connect axi_resetn axi_dacfifo/axi_resetn + ad_connect axi_resetn axi_ddr_cntrl/aresetn + ad_connect dac_rst axi_dacfifo/dac_rst + ad_connect dac_rst axi_rstgen/ext_reset_in + + ## interfaces + + ad_connect ddr3 axi_ddr_cntrl/DDR3 + ad_connect axi_ddr_cntrl/S_AXI axi_dacfifo/axi + + ad_connect dma_rvalid axi_dacfifo/dma_valid + ad_connect dma_rready axi_dacfifo/dma_ready + ad_connect dma_rdata axi_dacfifo/dma_data + ad_connect dma_xfer_req axi_dacfifo/dma_xfer_req + ad_connect dma_xfer_last axi_dacfifo/dma_xfer_last + + ad_connect dac_fifo_bypass axi_dacfifo/bypass + ad_connect dac_valid axi_dacfifo/dac_valid + ad_connect dac_data axi_dacfifo/dac_data + ad_connect dac_dunf axi_dacfifo/dac_dunf + ad_connect dac_xfer_out axi_dacfifo/dac_xfer_out + + ad_connect axi_ddr_cntrl/device_temp_i GND + + current_bd_instance $c_instance +} diff --git a/projects/common/zc706pr/zc706pr_system_bd.tcl b/projects/common/zc706pr/zc706pr_system_bd.tcl deleted file mode 100644 index d42c8bd3f..000000000 --- a/projects/common/zc706pr/zc706pr_system_bd.tcl +++ /dev/null @@ -1,3 +0,0 @@ - -# place holder for partial reconfiguration bases -- use zc706 base - diff --git a/projects/common/zcu102/zcu102_system_bd.tcl b/projects/common/zcu102/zcu102_system_bd.tcl new file mode 100644 index 000000000..0631b0fa3 --- /dev/null +++ b/projects/common/zcu102/zcu102_system_bd.tcl @@ -0,0 +1,2531 @@ + +# create board design +# default ports + +create_bd_port -dir O -from 2 -to 0 spi0_csn +create_bd_port -dir O spi0_sclk +create_bd_port -dir O spi0_mosi +create_bd_port -dir I spi0_miso + +create_bd_port -dir O -from 2 -to 0 spi1_csn +create_bd_port -dir O spi1_sclk +create_bd_port -dir O spi1_mosi +create_bd_port -dir I spi1_miso + +create_bd_port -dir I -from 94 -to 0 gpio_i +create_bd_port -dir O -from 94 -to 0 gpio_o + +# interrupts + +create_bd_port -dir I -type intr ps_intr_00 +create_bd_port -dir I -type intr ps_intr_01 +create_bd_port -dir I -type intr ps_intr_02 +create_bd_port -dir I -type intr ps_intr_03 +create_bd_port -dir I -type intr ps_intr_04 +create_bd_port -dir I -type intr ps_intr_05 +create_bd_port -dir I -type intr ps_intr_06 +create_bd_port -dir I -type intr ps_intr_07 +create_bd_port -dir I -type intr ps_intr_08 +create_bd_port -dir I -type intr ps_intr_09 +create_bd_port -dir I -type intr ps_intr_10 +create_bd_port -dir I -type intr ps_intr_11 +create_bd_port -dir I -type intr ps_intr_12 +create_bd_port -dir I -type intr ps_intr_13 +create_bd_port -dir I -type intr ps_intr_14 +create_bd_port -dir I -type intr ps_intr_15 + +# instance: sys_ps8 + +set sys_ps8 [create_bd_cell -type ip -vlnv xilinx.com:ip:zynq_ultra_ps_e:1.2 sys_ps8] + +# defaults -- remove after board is supported in the tool + +set_property -dict [list \ + CONFIG.PSU_BANK_0_IO_STANDARD {LVCMOS33} \ + CONFIG.PSU_BANK_1_IO_STANDARD {LVCMOS33} \ + CONFIG.PSU_BANK_2_IO_STANDARD {LVCMOS33} \ + CONFIG.PSU_DDR_RAM_HIGHADDR {0xFFFFFFFF} \ + CONFIG.PSU_DDR_RAM_HIGHADDR_OFFSET {0x80000000} \ + CONFIG.PSU_MIO_0_DIRECTION {out} \ + CONFIG.PSU_MIO_0_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_0_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_0_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_0_SLEW {slow} \ + CONFIG.PSU_MIO_10_DIRECTION {inout} \ + CONFIG.PSU_MIO_10_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_10_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_10_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_10_SLEW {slow} \ + CONFIG.PSU_MIO_11_DIRECTION {inout} \ + CONFIG.PSU_MIO_11_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_11_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_11_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_11_SLEW {slow} \ + CONFIG.PSU_MIO_12_DIRECTION {out} \ + CONFIG.PSU_MIO_12_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_12_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_12_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_12_SLEW {slow} \ + CONFIG.PSU_MIO_13_DIRECTION {inout} \ + CONFIG.PSU_MIO_13_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_13_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_13_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_13_SLEW {slow} \ + CONFIG.PSU_MIO_14_DIRECTION {inout} \ + CONFIG.PSU_MIO_14_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_14_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_14_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_14_SLEW {slow} \ + CONFIG.PSU_MIO_15_DIRECTION {inout} \ + CONFIG.PSU_MIO_15_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_15_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_15_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_15_SLEW {slow} \ + CONFIG.PSU_MIO_16_DIRECTION {inout} \ + CONFIG.PSU_MIO_16_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_16_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_16_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_16_SLEW {slow} \ + CONFIG.PSU_MIO_17_DIRECTION {inout} \ + CONFIG.PSU_MIO_17_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_17_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_17_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_17_SLEW {slow} \ + CONFIG.PSU_MIO_18_DIRECTION {in} \ + CONFIG.PSU_MIO_18_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_18_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_18_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_18_SLEW {slow} \ + CONFIG.PSU_MIO_19_DIRECTION {out} \ + CONFIG.PSU_MIO_19_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_19_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_19_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_19_SLEW {slow} \ + CONFIG.PSU_MIO_1_DIRECTION {inout} \ + CONFIG.PSU_MIO_1_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_1_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_1_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_1_SLEW {slow} \ + CONFIG.PSU_MIO_20_DIRECTION {out} \ + CONFIG.PSU_MIO_20_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_20_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_20_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_20_SLEW {slow} \ + CONFIG.PSU_MIO_21_DIRECTION {in} \ + CONFIG.PSU_MIO_21_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_21_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_21_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_21_SLEW {slow} \ + CONFIG.PSU_MIO_22_DIRECTION {inout} \ + CONFIG.PSU_MIO_22_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_22_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_22_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_22_SLEW {slow} \ + CONFIG.PSU_MIO_23_DIRECTION {inout} \ + CONFIG.PSU_MIO_23_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_23_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_23_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_23_SLEW {slow} \ + CONFIG.PSU_MIO_24_DIRECTION {out} \ + CONFIG.PSU_MIO_24_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_24_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_24_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_24_SLEW {slow} \ + CONFIG.PSU_MIO_25_DIRECTION {in} \ + CONFIG.PSU_MIO_25_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_25_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_25_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_25_SLEW {slow} \ + CONFIG.PSU_MIO_26_DIRECTION {inout} \ + CONFIG.PSU_MIO_26_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_26_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_26_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_26_SLEW {slow} \ + CONFIG.PSU_MIO_27_DIRECTION {inout} \ + CONFIG.PSU_MIO_27_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_27_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_27_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_27_SLEW {slow} \ + CONFIG.PSU_MIO_28_DIRECTION {inout} \ + CONFIG.PSU_MIO_28_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_28_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_28_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_28_SLEW {slow} \ + CONFIG.PSU_MIO_29_DIRECTION {inout} \ + CONFIG.PSU_MIO_29_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_29_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_29_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_29_SLEW {slow} \ + CONFIG.PSU_MIO_2_DIRECTION {inout} \ + CONFIG.PSU_MIO_2_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_2_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_2_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_2_SLEW {slow} \ + CONFIG.PSU_MIO_30_DIRECTION {inout} \ + CONFIG.PSU_MIO_30_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_30_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_30_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_30_SLEW {slow} \ + CONFIG.PSU_MIO_31_DIRECTION {out} \ + CONFIG.PSU_MIO_31_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_31_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_31_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_31_SLEW {slow} \ + CONFIG.PSU_MIO_32_DIRECTION {inout} \ + CONFIG.PSU_MIO_32_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_32_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_32_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_32_SLEW {slow} \ + CONFIG.PSU_MIO_33_DIRECTION {inout} \ + CONFIG.PSU_MIO_33_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_33_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_33_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_33_SLEW {slow} \ + CONFIG.PSU_MIO_34_DIRECTION {inout} \ + CONFIG.PSU_MIO_34_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_34_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_34_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_34_SLEW {slow} \ + CONFIG.PSU_MIO_35_DIRECTION {inout} \ + CONFIG.PSU_MIO_35_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_35_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_35_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_35_SLEW {slow} \ + CONFIG.PSU_MIO_36_DIRECTION {inout} \ + CONFIG.PSU_MIO_36_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_36_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_36_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_36_SLEW {slow} \ + CONFIG.PSU_MIO_37_DIRECTION {inout} \ + CONFIG.PSU_MIO_37_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_37_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_37_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_37_SLEW {slow} \ + CONFIG.PSU_MIO_38_DIRECTION {inout} \ + CONFIG.PSU_MIO_38_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_38_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_38_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_38_SLEW {slow} \ + CONFIG.PSU_MIO_39_DIRECTION {inout} \ + CONFIG.PSU_MIO_39_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_39_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_39_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_39_SLEW {slow} \ + CONFIG.PSU_MIO_3_DIRECTION {inout} \ + CONFIG.PSU_MIO_3_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_3_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_3_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_3_SLEW {slow} \ + CONFIG.PSU_MIO_40_DIRECTION {inout} \ + CONFIG.PSU_MIO_40_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_40_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_40_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_40_SLEW {slow} \ + CONFIG.PSU_MIO_41_DIRECTION {inout} \ + CONFIG.PSU_MIO_41_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_41_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_41_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_41_SLEW {slow} \ + CONFIG.PSU_MIO_42_DIRECTION {inout} \ + CONFIG.PSU_MIO_42_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_42_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_42_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_42_SLEW {slow} \ + CONFIG.PSU_MIO_43_DIRECTION {out} \ + CONFIG.PSU_MIO_43_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_43_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_43_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_43_SLEW {slow} \ + CONFIG.PSU_MIO_44_DIRECTION {in} \ + CONFIG.PSU_MIO_44_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_44_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_44_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_44_SLEW {slow} \ + CONFIG.PSU_MIO_45_DIRECTION {in} \ + CONFIG.PSU_MIO_45_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_45_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_45_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_45_SLEW {slow} \ + CONFIG.PSU_MIO_46_DIRECTION {inout} \ + CONFIG.PSU_MIO_46_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_46_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_46_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_46_SLEW {slow} \ + CONFIG.PSU_MIO_47_DIRECTION {inout} \ + CONFIG.PSU_MIO_47_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_47_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_47_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_47_SLEW {slow} \ + CONFIG.PSU_MIO_48_DIRECTION {inout} \ + CONFIG.PSU_MIO_48_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_48_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_48_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_48_SLEW {slow} \ + CONFIG.PSU_MIO_49_DIRECTION {inout} \ + CONFIG.PSU_MIO_49_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_49_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_49_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_49_SLEW {slow} \ + CONFIG.PSU_MIO_4_DIRECTION {inout} \ + CONFIG.PSU_MIO_4_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_4_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_4_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_4_SLEW {slow} \ + CONFIG.PSU_MIO_50_DIRECTION {inout} \ + CONFIG.PSU_MIO_50_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_50_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_50_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_50_SLEW {slow} \ + CONFIG.PSU_MIO_51_DIRECTION {out} \ + CONFIG.PSU_MIO_51_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_51_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_51_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_51_SLEW {slow} \ + CONFIG.PSU_MIO_52_DIRECTION {in} \ + CONFIG.PSU_MIO_52_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_52_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_52_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_52_SLEW {slow} \ + CONFIG.PSU_MIO_53_DIRECTION {in} \ + CONFIG.PSU_MIO_53_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_53_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_53_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_53_SLEW {slow} \ + CONFIG.PSU_MIO_54_DIRECTION {inout} \ + CONFIG.PSU_MIO_54_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_54_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_54_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_54_SLEW {slow} \ + CONFIG.PSU_MIO_55_DIRECTION {in} \ + CONFIG.PSU_MIO_55_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_55_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_55_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_55_SLEW {slow} \ + CONFIG.PSU_MIO_56_DIRECTION {inout} \ + CONFIG.PSU_MIO_56_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_56_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_56_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_56_SLEW {slow} \ + CONFIG.PSU_MIO_57_DIRECTION {inout} \ + CONFIG.PSU_MIO_57_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_57_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_57_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_57_SLEW {slow} \ + CONFIG.PSU_MIO_58_DIRECTION {out} \ + CONFIG.PSU_MIO_58_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_58_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_58_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_58_SLEW {slow} \ + CONFIG.PSU_MIO_59_DIRECTION {inout} \ + CONFIG.PSU_MIO_59_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_59_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_59_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_59_SLEW {slow} \ + CONFIG.PSU_MIO_5_DIRECTION {out} \ + CONFIG.PSU_MIO_5_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_5_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_5_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_5_SLEW {slow} \ + CONFIG.PSU_MIO_60_DIRECTION {inout} \ + CONFIG.PSU_MIO_60_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_60_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_60_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_60_SLEW {slow} \ + CONFIG.PSU_MIO_61_DIRECTION {inout} \ + CONFIG.PSU_MIO_61_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_61_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_61_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_61_SLEW {slow} \ + CONFIG.PSU_MIO_62_DIRECTION {inout} \ + CONFIG.PSU_MIO_62_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_62_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_62_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_62_SLEW {slow} \ + CONFIG.PSU_MIO_63_DIRECTION {inout} \ + CONFIG.PSU_MIO_63_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_63_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_63_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_63_SLEW {slow} \ + CONFIG.PSU_MIO_64_DIRECTION {out} \ + CONFIG.PSU_MIO_64_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_64_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_64_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_64_SLEW {slow} \ + CONFIG.PSU_MIO_65_DIRECTION {out} \ + CONFIG.PSU_MIO_65_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_65_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_65_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_65_SLEW {slow} \ + CONFIG.PSU_MIO_66_DIRECTION {out} \ + CONFIG.PSU_MIO_66_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_66_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_66_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_66_SLEW {slow} \ + CONFIG.PSU_MIO_67_DIRECTION {out} \ + CONFIG.PSU_MIO_67_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_67_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_67_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_67_SLEW {slow} \ + CONFIG.PSU_MIO_68_DIRECTION {out} \ + CONFIG.PSU_MIO_68_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_68_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_68_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_68_SLEW {slow} \ + CONFIG.PSU_MIO_69_DIRECTION {out} \ + CONFIG.PSU_MIO_69_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_69_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_69_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_69_SLEW {slow} \ + CONFIG.PSU_MIO_6_DIRECTION {out} \ + CONFIG.PSU_MIO_6_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_6_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_6_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_6_SLEW {slow} \ + CONFIG.PSU_MIO_70_DIRECTION {in} \ + CONFIG.PSU_MIO_70_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_70_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_70_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_70_SLEW {slow} \ + CONFIG.PSU_MIO_71_DIRECTION {in} \ + CONFIG.PSU_MIO_71_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_71_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_71_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_71_SLEW {slow} \ + CONFIG.PSU_MIO_72_DIRECTION {in} \ + CONFIG.PSU_MIO_72_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_72_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_72_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_72_SLEW {slow} \ + CONFIG.PSU_MIO_73_DIRECTION {in} \ + CONFIG.PSU_MIO_73_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_73_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_73_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_73_SLEW {slow} \ + CONFIG.PSU_MIO_74_DIRECTION {in} \ + CONFIG.PSU_MIO_74_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_74_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_74_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_74_SLEW {slow} \ + CONFIG.PSU_MIO_75_DIRECTION {in} \ + CONFIG.PSU_MIO_75_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_75_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_75_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_75_SLEW {slow} \ + CONFIG.PSU_MIO_76_DIRECTION {out} \ + CONFIG.PSU_MIO_76_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_76_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_76_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_76_SLEW {slow} \ + CONFIG.PSU_MIO_77_DIRECTION {inout} \ + CONFIG.PSU_MIO_77_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_77_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_77_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_77_SLEW {slow} \ + CONFIG.PSU_MIO_7_DIRECTION {out} \ + CONFIG.PSU_MIO_7_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_7_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_7_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_7_SLEW {slow} \ + CONFIG.PSU_MIO_8_DIRECTION {inout} \ + CONFIG.PSU_MIO_8_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_8_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_8_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_8_SLEW {slow} \ + CONFIG.PSU_MIO_9_DIRECTION {inout} \ + CONFIG.PSU_MIO_9_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_9_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_9_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_9_SLEW {slow} \ + CONFIG.PSU_MIO_TREE_PERIPHERALS {Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Feedback Clk#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#GPIO0 MIO#I2C 0#I2C 0#I2C 1#I2C 1#UART 0#UART 0#UART 1#UART 1#GPIO0 MIO#GPIO0 MIO#CAN 1#CAN 1#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#PCIE#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#MDIO 3#MDIO 3} \ + CONFIG.PSU_MIO_TREE_SIGNALS {sclk_out#so_mo1#mo2#mo3#si_mi0#n_ss_out#clk_for_lpbk#n_ss_out_upper#mo_upper[0]#mo_upper[1]#mo_upper[2]#mo_upper[3]#sclk_out_upper#gpio0[13]#scl_out#sda_out#scl_out#sda_out#rxd#txd#txd#rxd#gpio0[22]#gpio0[23]#phy_tx#phy_rx#gpio1[26]#gpio1[27]#gpio1[28]#gpio1[29]#gpio1[30]#reset_n#gpio1[32]#gpio1[33]#gpio1[34]#gpio1[35]#gpio1[36]#gpio1[37]#gpio1[38]#gpio1[39]#gpio1[40]#gpio1[41]#gpio1[42]#sdio1_bus_pow#sdio1_wp#sdio1_cd_n#sdio1_data_out[0]#sdio1_data_out[1]#sdio1_data_out[2]#sdio1_data_out[3]#sdio1_cmd_out#sdio1_clk_out#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#rgmii_tx_clk#rgmii_txd[0]#rgmii_txd[1]#rgmii_txd[2]#rgmii_txd[3]#rgmii_tx_ctl#rgmii_rx_clk#rgmii_rxd[0]#rgmii_rxd[1]#rgmii_rxd[2]#rgmii_rxd[3]#rgmii_rx_ctl#gem3_mdc#gem3_mdio_out} \ + CONFIG.PSU_PACKAGE_DDR_BOARD_DELAY3 {0.100} \ + CONFIG.PSU_PRESET_BANK0_VOLTAGE {} \ + CONFIG.PSU_UIPARAM_GENERATE_SUMMARY {} \ + CONFIG.PSU__CAN0__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__CAN0__PERIPHERAL__IO {} \ + CONFIG.PSU__CAN1__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__CAN1__PERIPHERAL__IO {MIO 24 .. 25} \ + CONFIG.PSU__CPU_CPU_6X4X_MAX_RANGE {1} \ + CONFIG.PSU__CPU_R5__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__CRF_APB__ACPU_CTRL__ACT_FREQMHZ {1099.989014} \ + CONFIG.PSU__CRF_APB__ACPU_CTRL__DIVISOR0 {1} \ + CONFIG.PSU__CRF_APB__ACPU_CTRL__FREQMHZ {1200} \ + CONFIG.PSU__CRF_APB__ACPU_CTRL__SRCSEL {APLL} \ + CONFIG.PSU__CRF_APB__ACPU__ENABLE {1} \ + CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__ACT_FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__SRCSEL {DPLL} \ + CONFIG.PSU__CRF_APB__AFI0_REF__ENABLE {0} \ + CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__ACT_FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__SRCSEL {DPLL} \ + CONFIG.PSU__CRF_APB__AFI1_REF__ENABLE {0} \ + CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__ACT_FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__SRCSEL {DPLL} \ + CONFIG.PSU__CRF_APB__AFI2_REF__ENABLE {0} \ + CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__ACT_FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__SRCSEL {DPLL} \ + CONFIG.PSU__CRF_APB__AFI3_REF__ENABLE {0} \ + CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__ACT_FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__SRCSEL {DPLL} \ + CONFIG.PSU__CRF_APB__AFI4_REF__ENABLE {0} \ + CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__ACT_FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__SRCSEL {DPLL} \ + CONFIG.PSU__CRF_APB__AFI5_REF__ENABLE {0} \ + CONFIG.PSU__CRF_APB__APLL_CTRL__DIV2 {1} \ + CONFIG.PSU__CRF_APB__APLL_CTRL__FBDIV {66} \ + CONFIG.PSU__CRF_APB__APLL_CTRL__FRACDATA {0.000} \ + CONFIG.PSU__CRF_APB__APLL_CTRL__FRACFREQ {27.138} \ + CONFIG.PSU__CRF_APB__APLL_CTRL__SRCSEL {PSS_REF_CLK} \ + CONFIG.PSU__CRF_APB__APLL_FRAC_CFG__ENABLED {0} \ + CONFIG.PSU__CRF_APB__APLL_TO_LPD_CTRL__DIVISOR0 {3} \ + CONFIG.PSU__CRF_APB__APLL_TO_LPD_CTRL__SRCSEL {APLL} \ + CONFIG.PSU__CRF_APB__APM_CTRL__ACT_FREQMHZ {1} \ + CONFIG.PSU__CRF_APB__APM_CTRL__DIVISOR0 {1} \ + CONFIG.PSU__CRF_APB__APM_CTRL__FREQMHZ {1} \ + CONFIG.PSU__CRF_APB__APM_CTRL__SRCSEL {} \ + CONFIG.PSU__CSU__CSU_TAMPER_10__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_10__ERASE_BBRAM {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_10__RESPONSE {} \ + CONFIG.PSU__CSU__CSU_TAMPER_12__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_12__ERASE_BBRAM {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_12__RESPONSE {} \ + CONFIG.PSU__CSU__CSU_TAMPER_2__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_2__ERASE_BBRAM {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_2__RESPONSE {} \ + CONFIG.PSU__CSU__CSU_TAMPER_4__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_4__ERASE_BBRAM {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_4__RESPONSE {} \ + CONFIG.PSU__CSU__CSU_TAMPER_6__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_6__ERASE_BBRAM {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_6__RESPONSE {} \ + CONFIG.PSU__CSU__CSU_TAMPER_8__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_8__ERASE_BBRAM {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_8__RESPONSE {} \ + CONFIG.PSU__CSU__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__CSU__PERIPHERAL__IO {} \ + CONFIG.PSU__DDRC__DEVICE_CAPACITY {4096 MBits} \ + CONFIG.PSU__DDRC__DIMM_ADDR_MIRROR {0} \ + CONFIG.PSU__DDRC__DQS_0_LENGTH_MM {1} \ + CONFIG.PSU__DDRC__DQS_0_PACKAGE_LENGTH {1} \ + CONFIG.PSU__DDRC__DQS_0_PROPOGATION_DELAY {1} \ + CONFIG.PSU__DDRC__DQS_1_LENGTH_MM {1} \ + CONFIG.PSU__DDRC__DQS_1_PACKAGE_LENGTH {1} \ + CONFIG.PSU__DDRC__DQS_1_PROPOGATION_DELAY {1} \ + CONFIG.PSU__DDRC__DQS_2_LENGTH_MM {1} \ + CONFIG.PSU__DDRC__DQS_2_PACKAGE_LENGTH {1} \ + CONFIG.PSU__DDRC__DQS_2_PROPOGATION_DELAY {1} \ + CONFIG.PSU__DDRC__DQS_3_LENGTH_MM {1} \ + CONFIG.PSU__DDRC__DQS_3_PACKAGE_LENGTH {1} \ + CONFIG.PSU__DDRC__DQS_3_PROPOGATION_DELAY {1} \ + CONFIG.PSU__DDRC__DQS_TO_CLK_DELAY_0 {0.00} \ + CONFIG.PSU__DDRC__DQS_TO_CLK_DELAY_1 {0.05} \ + CONFIG.PSU__DDRC__DQS_TO_CLK_DELAY_2 {0.10} \ + CONFIG.PSU__DDRC__DQS_TO_CLK_DELAY_3 {0.15} \ + CONFIG.PSU__DDRC__DQ_0_LENGTH_MM {1} \ + CONFIG.PSU__DDRC__DQ_0_PACKAGE_LENGTH {1} \ + CONFIG.PSU__DDRC__DQ_0_PROPOGATION_DELAY {1} \ + CONFIG.PSU__DDRC__DQ_1_LENGTH_MM {1} \ + CONFIG.PSU__DDRC__DQ_1_PACKAGE_LENGTH {1} \ + CONFIG.PSU__DDRC__DQ_1_PROPOGATION_DELAY {1} \ + CONFIG.PSU__DDRC__DQ_2_LENGTH_MM {1} \ + CONFIG.PSU__DDRC__DQ_2_PACKAGE_LENGTH {1} \ + CONFIG.PSU__DDRC__DQ_2_PROPOGATION_DELAY {1} \ + CONFIG.PSU__DDRC__DQ_3_LENGTH_MM {1} \ + CONFIG.PSU__DDRC__DQ_3_PACKAGE_LENGTH {1} \ + CONFIG.PSU__DDRC__DQ_3_PROPOGATION_DELAY {1} \ + CONFIG.PSU__DDRC__DRAM_WIDTH {8 Bits} \ + CONFIG.PSU__DDRC__ECC {0} \ + CONFIG.PSU__DDRC__ECC_SCRUB {0} \ + CONFIG.PSU__DDRC__ENABLE {1} \ + CONFIG.PSU__DDRC__EN_2ND_CLK {0} \ + CONFIG.PSU__DDRC__FGRM {0} \ + CONFIG.PSU__DDRC__FREQ_MHZ {1066.50} \ + CONFIG.PSU__DDRC__HIGH_TEMP {} \ + CONFIG.PSU__DDRC__PER_BANK_REFRESH {0} \ + CONFIG.PSU__DDRC__PHY_DBI_MODE {0} \ + CONFIG.PSU__DDRC__PLL_BYPASS {0} \ + CONFIG.PSU__DDRC__PWR_DOWN_EN {0} \ + CONFIG.PSU__DDRC__RANK_ADDR_COUNT {0} \ + CONFIG.PSU__DDRC__RDIMM_INDICATOR {0} \ + CONFIG.PSU__DDRC__RD_DBI_ENABLE {0} \ + CONFIG.PSU__DDRC__ROW_ADDR_COUNT {15} \ + CONFIG.PSU__DDRC__SELF_REF_ABORT {0} \ + CONFIG.PSU__DDRC__SPEED_BIN {DDR4_2133P} \ + CONFIG.PSU__DDRC__STATIC_RD_MODE {0} \ + CONFIG.PSU__DDRC__TRAIN_DATA_EYE {1} \ + CONFIG.PSU__DDRC__TRAIN_READ_GATE {1} \ + CONFIG.PSU__DDRC__TRAIN_WRITE_LEVEL {1} \ + CONFIG.PSU__DDRC__T_FAW {21.0} \ + CONFIG.PSU__DDRC__T_RAS_MIN {33} \ + CONFIG.PSU__DDRC__T_RC {46.5} \ + CONFIG.PSU__DDRC__T_RCD {15} \ + CONFIG.PSU__DDRC__T_RP {15} \ + CONFIG.PSU__DDRC__UDIMM_INDICATOR {1} \ + CONFIG.PSU__DDRC__USE_INTERNAL_VREF {0} \ + CONFIG.PSU__DDRC__VIDEO_BUFFER_SIZE {0} \ + CONFIG.PSU__DDRC__VREF {1} \ + CONFIG.PSU__DDRC__WR_DBI_ENABLE {0} \ + CONFIG.PSU__DDR_HIGH_ADDRESS_GUI_ENABLE {1} \ + CONFIG.PSU__DDR__INTERFACE__FREQMHZ {533.500} \ + CONFIG.PSU__DISPLAYPORT__LANE0__ENABLE {} \ + CONFIG.PSU__DISPLAYPORT__LANE1__ENABLE {} \ + CONFIG.PSU__DISPLAYPORT__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__DPAUX__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__DPAUX__PERIPHERAL__IO {} \ + CONFIG.PSU__ENET0__GRP_MDIO__ENABLE {0} \ + CONFIG.PSU__ENET0__GRP_MDIO__IO {} \ + CONFIG.PSU__ENET1__GRP_MDIO__ENABLE {0} \ + CONFIG.PSU__ENET1__GRP_MDIO__IO {} \ + CONFIG.PSU__ENET2__GRP_MDIO__ENABLE {0} \ + CONFIG.PSU__ENET2__GRP_MDIO__IO {} \ + CONFIG.PSU__ENET3__GRP_MDIO__ENABLE {1} \ + CONFIG.PSU__ENET3__GRP_MDIO__IO {MIO 76 .. 77} \ + CONFIG.PSU__ENET3__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__ENET3__PERIPHERAL__IO {MIO 64 .. 75} \ + CONFIG.PSU__FPGA_PL0_ENABLE {1} \ + CONFIG.PSU__FP__POWER__ON {1} \ + CONFIG.PSU__GEM0_COHERENCY {1} \ + CONFIG.PSU__GEM1_COHERENCY {0} \ + CONFIG.PSU__GEM2_COHERENCY {1} \ + CONFIG.PSU__GEM3_COHERENCY {1} \ + CONFIG.PSU__GEM__TSU__ENABLE {0} \ + CONFIG.PSU__GEM__TSU__IO {} \ + CONFIG.PSU__GPIO2_MIO__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__GPIO_EMIO__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__GPIO_EMIO__PERIPHERAL__IO {} \ + CONFIG.PSU__GT__REF_SEL0 {100} \ + CONFIG.PSU__GT__REF_SEL1 {100} \ + CONFIG.PSU__GT__REF_SEL2 {26} \ + CONFIG.PSU__GT__REF_SEL3 {125} \ + CONFIG.PSU__I2C0_LOOP_I2C1__ENABLE {0} \ + CONFIG.PSU__I2C0__GRP_INT__ENABLE {0} \ + CONFIG.PSU__I2C0__GRP_INT__IO {} \ + CONFIG.PSU__I2C1__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__I2C1__PERIPHERAL__IO {MIO 16 .. 17} \ + CONFIG.PSU__L2_BANK0__POWER__ON {1} \ + CONFIG.PSU__MAXIGP2__DATA_WIDTH {64} \ + CONFIG.PSU__NAND_COHERENCY {1} \ + CONFIG.PSU__NAND__CHIP_ENABLE__ENABLE {0} \ + CONFIG.PSU__NAND__CHIP_ENABLE__IO {} \ + CONFIG.PSU__NAND__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__NAND__PERIPHERAL__IO {} \ + CONFIG.PSU__OCM_BANK0__POWER__ON {1} \ + CONFIG.PSU__OCM_BANK1__POWER__ON {1} \ + CONFIG.PSU__OCM_BANK2__POWER__ON {1} \ + CONFIG.PSU__OCM_BANK3__POWER__ON {1} \ + CONFIG.PSU__OVERRIDE__BASIC_CLOCK {1} \ + CONFIG.PSU__PCIE__ACS_VIOLATION {0} \ + CONFIG.PSU__PCIE__AER_CAPABILITY {0} \ + CONFIG.PSU__PCIE__ATOMICOP_EGRESS_BLOCKED {0} \ + CONFIG.PSU__PCIE__BAR0_64BIT {0} \ + CONFIG.PSU__PCIE__BAR0_ENABLE {0} \ + CONFIG.PSU__PCIE__BAR0_PREFETCHABLE {0} \ + CONFIG.PSU__PCIE__BAR0_SCALE {} \ + CONFIG.PSU__PCIE__BAR0_TYPE {} \ + CONFIG.PSU__PCIE__BAR1_SIZE {} \ + CONFIG.PSU__PCIE__BAR1_VAL {0x0} \ + CONFIG.PSU__PCIE__BAR2_64BIT {0} \ + CONFIG.PSU__PCIE__BAR2_ENABLE {0} \ + CONFIG.PSU__PCIE__BAR2_PREFETCHABLE {0} \ + CONFIG.PSU__PCIE__BAR2_SCALE {} \ + CONFIG.PSU__PCIE__BAR2_TYPE {} \ + CONFIG.PSU__PCIE__BAR3_SIZE {} \ + CONFIG.PSU__PCIE__BAR3_VAL {0x0} \ + CONFIG.PSU__PCIE__BAR4_64BIT {0} \ + CONFIG.PSU__PCIE__BAR4_ENABLE {0} \ + CONFIG.PSU__PCIE__BAR4_PREFETCHABLE {0} \ + CONFIG.PSU__PCIE__BAR4_SCALE {} \ + CONFIG.PSU__PCIE__BAR4_TYPE {} \ + CONFIG.PSU__PCIE__BAR5_SIZE {} \ + CONFIG.PSU__PCIE__BAR5_VAL {0x0} \ + CONFIG.PSU__PCIE__BASE_CLASS_MENU {} \ + CONFIG.PSU__PCIE__CAP_SLOT_IMPLEMENTED {} \ + CONFIG.PSU__PCIE__EROM_SIZE {} \ + CONFIG.PSU__PCIE__INTX_GENERATION {0} \ + CONFIG.PSU__PCIE__INTX_PIN {} \ + CONFIG.PSU__PCIE__LANE2__ENABLE {0} \ + CONFIG.PSU__PCIE__LANE2__IO {} \ + CONFIG.PSU__PCIE__LEGACY_INTERRUPT {} \ + CONFIG.PSU__PCIE__MSIX_CAPABILITY {0} \ + CONFIG.PSU__PCIE__MSIX_PBA_BAR_INDICATOR {} \ + CONFIG.PSU__PCIE__MULTIHEADER {0} \ + CONFIG.PSU__PCIE__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__PCIE__PERIPHERAL__ENDPOINT_ENABLE {0} \ + CONFIG.PSU__PCIE__PERIPHERAL__ENDPOINT_IO {} \ + CONFIG.PSU__PCIE__SURPRISE_DOWN {0} \ + CONFIG.PSU__PCIE__TLP_PREFIX_BLOCKED {0} \ + CONFIG.PSU__PCIE__UNCORRECTABL_INT_ERR {0} \ + CONFIG.PSU__PCIE__USE_CLASS_CODE_LOOKUP_ASSISTANT {} \ + CONFIG.PSU__PL__POWER__ON {1} \ + CONFIG.PSU__PMU_COHERENCY {1} \ + CONFIG.PSU__PMU__EMIO_GPI__ENABLE {} \ + CONFIG.PSU__PMU__GPI0__ENABLE {} \ + CONFIG.PSU__PMU__GPI1__ENABLE {} \ + CONFIG.PSU__PMU__GPI2__ENABLE {} \ + CONFIG.PSU__PMU__GPI3__ENABLE {} \ + CONFIG.PSU__PMU__GPI4__ENABLE {} \ + CONFIG.PSU__PMU__GPI5__ENABLE {} \ + CONFIG.PSU__PMU__GPO0__ENABLE {} \ + CONFIG.PSU__PMU__GPO1__ENABLE {} \ + CONFIG.PSU__PMU__GPO2__ENABLE {} \ + CONFIG.PSU__PMU__GPO3__ENABLE {} \ + CONFIG.PSU__PMU__GPO4__ENABLE {} \ + CONFIG.PSU__PMU__GPO5__ENABLE {} \ + CONFIG.PSU__PMU__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__PMU__PERIPHERAL__IO {} \ + CONFIG.PSU__SATA__LANE1__ENABLE {1} \ + CONFIG.PSU__SATA__LANE1__IO {GT Lane3} \ + CONFIG.PSU__SATA__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__SD0_COHERENCY {1} \ + CONFIG.PSU__SD0__DATA_TRANSFER_MODE {} \ + CONFIG.PSU__SD0__GRP_POW__ENABLE {0} \ + CONFIG.PSU__SD0__GRP_POW__IO {} \ + CONFIG.PSU__SD0__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__SD0__PERIPHERAL__IO {} \ + CONFIG.PSU__SD1_COHERENCY {1} \ + CONFIG.PSU__SD1__DATA_TRANSFER_MODE {4Bit} \ + CONFIG.PSU__SD1__GRP_CD__ENABLE {1} \ + CONFIG.PSU__SD1__GRP_CD__IO {MIO 45} \ + CONFIG.PSU__SD1__GRP_POW__ENABLE {1} \ + CONFIG.PSU__SD1__GRP_POW__IO {MIO 43} \ + CONFIG.PSU__SD1__GRP_WP__ENABLE {1} \ + CONFIG.PSU__SD1__GRP_WP__IO {MIO 44} \ + CONFIG.PSU__SD1__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__SD1__PERIPHERAL__IO {MIO 46 .. 51} \ + CONFIG.PSU__SD1__RESET__ENABLE {} \ + CONFIG.PSU__SPI0__GRP_SS1__ENABLE {0} \ + CONFIG.PSU__SPI0__GRP_SS1__IO {} \ + CONFIG.PSU__SPI0__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__SPI0__PERIPHERAL__IO {} \ + CONFIG.PSU__SPI1__GRP_SS1__ENABLE {0} \ + CONFIG.PSU__SPI1__GRP_SS1__IO {} \ + CONFIG.PSU__SPI1__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__SPI1__PERIPHERAL__IO {} \ + CONFIG.PSU__SWDT1__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__SWDT1__PERIPHERAL__IO {} \ + CONFIG.PSU__TRACE__WIDTH {} \ + CONFIG.PSU__TTC2__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__TTC2__PERIPHERAL__IO {} \ + CONFIG.PSU__UART0_LOOP_UART1__ENABLE {0} \ + CONFIG.PSU__UART0__BAUD_RATE {115200} \ + CONFIG.PSU__UART0__MODEM__ENABLE {0} \ + CONFIG.PSU__UART0__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__UART0__PERIPHERAL__IO {MIO 18 .. 19} \ + CONFIG.PSU__UART1__BAUD_RATE {115200} \ + CONFIG.PSU__UART1__MODEM__ENABLE {0} \ + CONFIG.PSU__UART1__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__UART1__PERIPHERAL__IO {MIO 20 .. 21} \ + CONFIG.PSU__USB0_COHERENCY {1} \ + CONFIG.PSU__USB0__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__USB0__PERIPHERAL__IO {MIO 52 .. 63} \ + CONFIG.PSU__USB1_COHERENCY {1} \ + CONFIG.PSU__USB1__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__USB1__PERIPHERAL__IO {} \ + CONFIG.PSU__USE__FABRIC__RST {1} \ + CONFIG.PSU__USE__IRQ0 {1} \ + CONFIG.PSU__USE__M_AXI_GP2 {1} \ + CONFIG.PSU__VIDEO_REF_CLK__FREQMHZ {33.333} \ +] $sys_ps8 + +set_property -dict [list \ + CONFIG.PSU_BANK_0_IO_STANDARD.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_BANK_1_IO_STANDARD.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_BANK_2_IO_STANDARD.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_DDR_RAM_HIGHADDR.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_DDR_RAM_HIGHADDR_OFFSET.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_0_DIRECTION.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_0_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_0_INPUT_TYPE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_0_PULLUPDOWN.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_0_SLEW.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_10_DIRECTION.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_10_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_10_INPUT_TYPE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_10_PULLUPDOWN.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_10_SLEW.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_11_DIRECTION.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_11_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_11_INPUT_TYPE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_11_PULLUPDOWN.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_11_SLEW.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_12_DIRECTION.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_12_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_12_INPUT_TYPE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_12_PULLUPDOWN.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_12_SLEW.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_13_DIRECTION.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_13_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_13_INPUT_TYPE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_13_PULLUPDOWN.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_13_SLEW.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_14_DIRECTION.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_14_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_14_INPUT_TYPE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_14_PULLUPDOWN.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_14_SLEW.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_15_DIRECTION.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_15_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_15_INPUT_TYPE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_15_PULLUPDOWN.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_15_SLEW.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_16_DIRECTION.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_16_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_16_INPUT_TYPE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_16_PULLUPDOWN.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_16_SLEW.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_17_DIRECTION.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_17_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_17_INPUT_TYPE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_17_PULLUPDOWN.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_17_SLEW.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_18_DIRECTION.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_18_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_18_INPUT_TYPE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_18_PULLUPDOWN.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_18_SLEW.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_19_DIRECTION.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_19_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_19_INPUT_TYPE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_19_PULLUPDOWN.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_19_SLEW.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_1_DIRECTION.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_1_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_1_INPUT_TYPE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_1_PULLUPDOWN.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_1_SLEW.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_20_DIRECTION.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_20_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_20_INPUT_TYPE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_20_PULLUPDOWN.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_20_SLEW.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_21_DIRECTION.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_21_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_21_INPUT_TYPE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_21_PULLUPDOWN.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_21_SLEW.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_22_DIRECTION.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_22_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_22_INPUT_TYPE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_22_PULLUPDOWN.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_22_SLEW.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_23_DIRECTION.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_23_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_23_INPUT_TYPE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_23_PULLUPDOWN.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_23_SLEW.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_24_DIRECTION.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_24_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_24_INPUT_TYPE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_24_PULLUPDOWN.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_24_SLEW.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_25_DIRECTION.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_25_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_25_INPUT_TYPE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_25_PULLUPDOWN.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_25_SLEW.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_26_DIRECTION.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_26_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_26_INPUT_TYPE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_26_PULLUPDOWN.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_26_SLEW.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_27_DIRECTION.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_27_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_27_INPUT_TYPE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_27_PULLUPDOWN.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_27_SLEW.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_28_DIRECTION.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_28_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_28_INPUT_TYPE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_28_PULLUPDOWN.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_28_SLEW.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_29_DIRECTION.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_29_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_29_INPUT_TYPE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_29_PULLUPDOWN.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_29_SLEW.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_2_DIRECTION.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_2_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_2_INPUT_TYPE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_2_PULLUPDOWN.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_2_SLEW.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_30_DIRECTION.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_30_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_30_INPUT_TYPE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_30_PULLUPDOWN.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_30_SLEW.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_31_DIRECTION.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_31_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_31_INPUT_TYPE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_31_PULLUPDOWN.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_31_SLEW.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_32_DIRECTION.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_32_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_32_INPUT_TYPE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_32_PULLUPDOWN.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_32_SLEW.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_33_DIRECTION.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_33_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_33_INPUT_TYPE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_33_PULLUPDOWN.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_33_SLEW.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_34_DIRECTION.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_34_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_34_INPUT_TYPE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_34_PULLUPDOWN.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_34_SLEW.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_35_DIRECTION.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_35_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_35_INPUT_TYPE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_35_PULLUPDOWN.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_35_SLEW.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_36_DIRECTION.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_36_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_36_INPUT_TYPE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_36_PULLUPDOWN.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_36_SLEW.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_37_DIRECTION.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_37_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_37_INPUT_TYPE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_37_PULLUPDOWN.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_37_SLEW.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_38_DIRECTION.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_38_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_38_INPUT_TYPE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_38_PULLUPDOWN.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_38_SLEW.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_39_DIRECTION.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_39_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_39_INPUT_TYPE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_39_PULLUPDOWN.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_39_SLEW.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_3_DIRECTION.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_3_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_3_INPUT_TYPE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_3_PULLUPDOWN.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_3_SLEW.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_40_DIRECTION.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_40_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_40_INPUT_TYPE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_40_PULLUPDOWN.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_40_SLEW.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_41_DIRECTION.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_41_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_41_INPUT_TYPE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_41_PULLUPDOWN.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_41_SLEW.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_42_DIRECTION.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_42_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_42_INPUT_TYPE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_42_PULLUPDOWN.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_42_SLEW.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_43_DIRECTION.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_43_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_43_INPUT_TYPE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_43_PULLUPDOWN.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_43_SLEW.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_44_DIRECTION.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_44_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_44_INPUT_TYPE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_44_PULLUPDOWN.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_44_SLEW.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_45_DIRECTION.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_45_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_45_INPUT_TYPE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_45_PULLUPDOWN.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_45_SLEW.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_46_DIRECTION.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_46_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_46_INPUT_TYPE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_46_PULLUPDOWN.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_46_SLEW.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_47_DIRECTION.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_47_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_47_INPUT_TYPE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_47_PULLUPDOWN.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_47_SLEW.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_48_DIRECTION.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_48_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_48_INPUT_TYPE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_48_PULLUPDOWN.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_48_SLEW.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_49_DIRECTION.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_49_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_49_INPUT_TYPE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_49_PULLUPDOWN.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_49_SLEW.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_4_DIRECTION.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_4_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_4_INPUT_TYPE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_4_PULLUPDOWN.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_4_SLEW.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_50_DIRECTION.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_50_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_50_INPUT_TYPE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_50_PULLUPDOWN.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_50_SLEW.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_51_DIRECTION.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_51_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_51_INPUT_TYPE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_51_PULLUPDOWN.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_51_SLEW.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_52_DIRECTION.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_52_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_52_INPUT_TYPE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_52_PULLUPDOWN.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_52_SLEW.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_53_DIRECTION.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_53_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_53_INPUT_TYPE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_53_PULLUPDOWN.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_53_SLEW.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_54_DIRECTION.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_54_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_54_INPUT_TYPE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_54_PULLUPDOWN.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_54_SLEW.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_55_DIRECTION.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_55_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_55_INPUT_TYPE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_55_PULLUPDOWN.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_55_SLEW.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_56_DIRECTION.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_56_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_56_INPUT_TYPE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_56_PULLUPDOWN.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_56_SLEW.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_57_DIRECTION.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_57_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_57_INPUT_TYPE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_57_PULLUPDOWN.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_57_SLEW.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_58_DIRECTION.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_58_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_58_INPUT_TYPE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_58_PULLUPDOWN.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_58_SLEW.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_59_DIRECTION.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_59_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_59_INPUT_TYPE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_59_PULLUPDOWN.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_59_SLEW.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_5_DIRECTION.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_5_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_5_INPUT_TYPE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_5_PULLUPDOWN.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_5_SLEW.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_60_DIRECTION.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_60_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_60_INPUT_TYPE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_60_PULLUPDOWN.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_60_SLEW.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_61_DIRECTION.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_61_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_61_INPUT_TYPE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_61_PULLUPDOWN.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_61_SLEW.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_62_DIRECTION.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_62_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_62_INPUT_TYPE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_62_PULLUPDOWN.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_62_SLEW.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_63_DIRECTION.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_63_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_63_INPUT_TYPE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_63_PULLUPDOWN.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_63_SLEW.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_64_DIRECTION.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_64_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_64_INPUT_TYPE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_64_PULLUPDOWN.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_64_SLEW.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_65_DIRECTION.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_65_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_65_INPUT_TYPE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_65_PULLUPDOWN.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_65_SLEW.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_66_DIRECTION.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_66_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_66_INPUT_TYPE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_66_PULLUPDOWN.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_66_SLEW.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_67_DIRECTION.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_67_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_67_INPUT_TYPE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_67_PULLUPDOWN.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_67_SLEW.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_68_DIRECTION.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_68_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_68_INPUT_TYPE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_68_PULLUPDOWN.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_68_SLEW.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_69_DIRECTION.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_69_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_69_INPUT_TYPE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_69_PULLUPDOWN.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_69_SLEW.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_6_DIRECTION.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_6_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_6_INPUT_TYPE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_6_PULLUPDOWN.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_6_SLEW.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_70_DIRECTION.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_70_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_70_INPUT_TYPE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_70_PULLUPDOWN.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_70_SLEW.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_71_DIRECTION.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_71_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_71_INPUT_TYPE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_71_PULLUPDOWN.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_71_SLEW.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_72_DIRECTION.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_72_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_72_INPUT_TYPE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_72_PULLUPDOWN.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_72_SLEW.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_73_DIRECTION.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_73_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_73_INPUT_TYPE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_73_PULLUPDOWN.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_73_SLEW.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_74_DIRECTION.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_74_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_74_INPUT_TYPE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_74_PULLUPDOWN.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_74_SLEW.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_75_DIRECTION.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_75_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_75_INPUT_TYPE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_75_PULLUPDOWN.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_75_SLEW.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_76_DIRECTION.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_76_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_76_INPUT_TYPE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_76_PULLUPDOWN.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_76_SLEW.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_77_DIRECTION.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_77_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_77_INPUT_TYPE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_77_PULLUPDOWN.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_77_SLEW.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_7_DIRECTION.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_7_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_7_INPUT_TYPE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_7_PULLUPDOWN.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_7_SLEW.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_8_DIRECTION.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_8_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_8_INPUT_TYPE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_8_PULLUPDOWN.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_8_SLEW.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_9_DIRECTION.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_9_DRIVE_STRENGTH.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_9_INPUT_TYPE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_9_PULLUPDOWN.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_9_SLEW.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_TREE_PERIPHERALS.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_MIO_TREE_SIGNALS.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_PACKAGE_DDR_BOARD_DELAY3.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_PRESET_BANK0_VOLTAGE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_PRESET_BANK1_VOLTAGE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU_UIPARAM_GENERATE_SUMMARY.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__ACPU0__POWER__ON.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__ACPU1__POWER__ON.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__ACPU2__POWER__ON.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__ACPU3__POWER__ON.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__ACT_DDR_FREQ_MHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__ADMA_COHERENCY.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__AUX_REF_CLK__FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CAN0_LOOP_CAN1__ENABLE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CAN0__GRP_CLK__ENABLE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CAN0__GRP_CLK__IO.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CAN0__PERIPHERAL__ENABLE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CAN0__PERIPHERAL__IO.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CAN1__GRP_CLK__ENABLE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CAN1__GRP_CLK__IO.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CPU_CPU_6X4X_MAX_RANGE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CPU_R5__PERIPHERAL__ENABLE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRF_APB__ACPU_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRF_APB__ACPU_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRF_APB__ACPU__ENABLE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__DIVISOR0.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__SRCSEL.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRF_APB__AFI0_REF__ENABLE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__DIVISOR0.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__SRCSEL.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRF_APB__AFI1_REF__ENABLE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__DIVISOR0.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__SRCSEL.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRF_APB__AFI2_REF__ENABLE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__DIVISOR0.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__SRCSEL.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRF_APB__AFI3_REF__ENABLE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__DIVISOR0.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__SRCSEL.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRF_APB__AFI4_REF__ENABLE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__DIVISOR0.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__SRCSEL.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRF_APB__AFI5_REF__ENABLE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRF_APB__APLL_CTRL__FRACDATA.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRF_APB__APLL_CTRL__FRACFREQ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRF_APB__APLL_FRAC_CFG__ENABLED.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRF_APB__APM_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRF_APB__APM_CTRL__DIVISOR0.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRF_APB__APM_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRF_APB__APM_CTRL__SRCSEL.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRF_APB__DDR_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRF_APB__DFT125_REF_CTRL__DIVISOR0.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRF_APB__DFT125_REF_CTRL__SRCSEL.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRF_APB__DFT250_REF_CTRL__DIVISOR0.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRF_APB__DFT250_REF_CTRL__SRCSEL.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRF_APB__DFT270_REF_CTRL__DIVISOR0.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRF_APB__DFT270_REF_CTRL__SRCSEL.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRF_APB__DFT300_REF_CTRL__DIVISOR0.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRF_APB__DFT300_REF_CTRL__SRCSEL.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRF_APB__DPLL_CTRL__FRACDATA.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRF_APB__DPLL_CTRL__FRACFREQ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRF_APB__DPLL_FRAC_CFG__ENABLED.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRF_APB__GPU_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRF_APB__GPU_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRF_APB__GPU__ENABLE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRF_APB__SATA_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRF_APB__SATA_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACFREQ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__DIVISOR0.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__SRCSEL.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRL_APB__AFI6__ENABLE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRL_APB__AMS_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR0.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR1.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRL_APB__AMS_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRL_APB__AMS_REF_CTRL__SRCSEL.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRL_APB__AMS__ENABLE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRL_APB__CPU_R5_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRL_APB__CPU_R5_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__DIVISOR0.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__SRCSEL.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRL_APB__DLL_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRL_APB__DLL_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRL_APB__DLL_REF_CTRL__SRCSEL.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRL_APB__IOPLL_CTRL__FRACDATA.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRL_APB__IOPLL_CTRL__FRACFREQ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRL_APB__IOPLL_FRAC_CFG__ENABLED.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRL_APB__NAND_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRL_APB__NAND_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__DIVISOR0.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__SRCSEL.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRL_APB__OCM_MAIN__ENABLE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRL_APB__PCAP_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRL_APB__PCAP_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRL_APB__PICDEBUG_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRL_APB__PICDEBUG_CTRL__DIVISOR0.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRL_APB__PICDEBUG_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRL_APB__PICDEBUG_CTRL__SRCSEL.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRL_APB__PICDEBUG_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRL_APB__PICDEBUG_REF_CTRL__DIVISOR0.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRL_APB__PICDEBUG_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRL_APB__PICDEBUG_REF_CTRL__SRCSEL.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRL_APB__PICDEBUG_TEMP_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRL_APB__PICDEBUG_TEMP_CTRL__DIVISOR0.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRL_APB__PICDEBUG_TEMP_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRL_APB__PICDEBUG_TEMP_CTRL__SRCSEL.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRL_APB__PL0_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRL_APB__PL0_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRL_APB__PL1_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR0.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR1.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRL_APB__PL1_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRL_APB__PL1_REF_CTRL__SRCSEL.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRL_APB__PL2_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR0.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR1.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRL_APB__PL2_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRL_APB__PL2_REF_CTRL__SRCSEL.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRL_APB__PL3_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR0.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR1.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRL_APB__PL3_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRL_APB__PL3_REF_CTRL__SRCSEL.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACDATA.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACFREQ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRL_APB__RPLL_FRAC_CFG__ENABLED.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRL_APB__UART0_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRL_APB__UART0_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRL_APB__UART1_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRL_APB__UART1_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__ACT_FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CRYSTAL__PERIPHERAL__FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CSU_COHERENCY.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CSU__CSU_TAMPER_0__ENABLE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CSU__CSU_TAMPER_0__ERASE_BBRAM.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CSU__CSU_TAMPER_0__RESPONSE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CSU__CSU_TAMPER_10__ENABLE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CSU__CSU_TAMPER_10__ERASE_BBRAM.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CSU__CSU_TAMPER_10__RESPONSE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CSU__CSU_TAMPER_11__ENABLE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CSU__CSU_TAMPER_11__ERASE_BBRAM.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CSU__CSU_TAMPER_11__RESPONSE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CSU__CSU_TAMPER_12__ENABLE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CSU__CSU_TAMPER_12__ERASE_BBRAM.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CSU__CSU_TAMPER_12__RESPONSE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CSU__CSU_TAMPER_1__ENABLE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CSU__CSU_TAMPER_1__ERASE_BBRAM.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CSU__CSU_TAMPER_1__RESPONSE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CSU__CSU_TAMPER_2__ENABLE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CSU__CSU_TAMPER_2__ERASE_BBRAM.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CSU__CSU_TAMPER_2__RESPONSE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CSU__CSU_TAMPER_3__ENABLE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CSU__CSU_TAMPER_3__ERASE_BBRAM.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CSU__CSU_TAMPER_3__RESPONSE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CSU__CSU_TAMPER_4__ENABLE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CSU__CSU_TAMPER_4__ERASE_BBRAM.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CSU__CSU_TAMPER_4__RESPONSE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CSU__CSU_TAMPER_5__ENABLE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CSU__CSU_TAMPER_5__ERASE_BBRAM.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CSU__CSU_TAMPER_5__RESPONSE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CSU__CSU_TAMPER_6__ENABLE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CSU__CSU_TAMPER_6__ERASE_BBRAM.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CSU__CSU_TAMPER_6__RESPONSE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CSU__CSU_TAMPER_7__ENABLE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CSU__CSU_TAMPER_7__ERASE_BBRAM.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CSU__CSU_TAMPER_7__RESPONSE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CSU__CSU_TAMPER_8__ENABLE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CSU__CSU_TAMPER_8__ERASE_BBRAM.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CSU__CSU_TAMPER_8__RESPONSE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CSU__CSU_TAMPER_9__ENABLE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CSU__CSU_TAMPER_9__ERASE_BBRAM.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CSU__CSU_TAMPER_9__RESPONSE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CSU__PERIPHERAL__ENABLE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__CSU__PERIPHERAL__IO.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__DAP_COHERENCY.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__DDRC__BOARD_DELAY0.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__DDRC__BOARD_DELAY1.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__DDRC__BOARD_DELAY2.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__DDRC__BOARD_DELAY3.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__DDRC__CLOCK_0_LENGTH_MM.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__DDRC__CLOCK_0_PACKAGE_LENGTH.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__DDRC__CLOCK_0_PROPOGATION_DELAY.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__DDRC__CLOCK_1_LENGTH_MM.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__DDRC__CLOCK_1_PACKAGE_LENGTH.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__DDRC__CLOCK_1_PROPOGATION_DELAY.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__DDRC__CLOCK_2_LENGTH_MM.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__DDRC__CLOCK_2_PACKAGE_LENGTH.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__DDRC__CLOCK_2_PROPOGATION_DELAY.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__DDRC__CLOCK_3_LENGTH_MM.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__DDRC__CLOCK_3_PACKAGE_LENGTH.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__DDRC__CLOCK_3_PROPOGATION_DELAY.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__DDRC__DDR4_MAXPWR_SAVING_EN.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__DDRC__DEEP_PWR_DOWN_EN.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__DDRC__DERATE_INT_D.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__DDRC__DQS_0_LENGTH_MM.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__DDRC__DQS_0_PACKAGE_LENGTH.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__DDRC__DQS_0_PROPOGATION_DELAY.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__DDRC__DQS_1_LENGTH_MM.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__DDRC__DQS_1_PACKAGE_LENGTH.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__DDRC__DQS_1_PROPOGATION_DELAY.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__DDRC__DQS_2_LENGTH_MM.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__DDRC__DQS_2_PACKAGE_LENGTH.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__DDRC__DQS_2_PROPOGATION_DELAY.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__DDRC__DQS_3_LENGTH_MM.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__DDRC__DQS_3_PACKAGE_LENGTH.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__DDRC__DQS_3_PROPOGATION_DELAY.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__DDRC__DQS_TO_CLK_DELAY_0.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__DDRC__DQS_TO_CLK_DELAY_1.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__DDRC__DQS_TO_CLK_DELAY_2.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__DDRC__DQS_TO_CLK_DELAY_3.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__DDRC__DQ_0_LENGTH_MM.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__DDRC__DQ_0_PACKAGE_LENGTH.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__DDRC__DQ_0_PROPOGATION_DELAY.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__DDRC__DQ_1_LENGTH_MM.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__DDRC__DQ_1_PACKAGE_LENGTH.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__DDRC__DQ_1_PROPOGATION_DELAY.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__DDRC__DQ_2_LENGTH_MM.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__DDRC__DQ_2_PACKAGE_LENGTH.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__DDRC__DQ_2_PROPOGATION_DELAY.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__DDRC__DQ_3_LENGTH_MM.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__DDRC__DQ_3_PACKAGE_LENGTH.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__DDRC__DQ_3_PROPOGATION_DELAY.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__DDRC__ECC_SCRUB.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__DDRC__ENABLE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__DDRC__EN_2ND_CLK.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__DDRC__HIGH_TEMP.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__DDRC__PARTNO.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__DDRC__PLL_BYPASS.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__DDRC__PWR_DOWN_EN.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__DDRC__USE_INTERNAL_VREF.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__DDRC__VIDEO_BUFFER_SIZE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__DDR_HIGH_ADDRESS_GUI_ENABLE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__DDR__INTERFACE__FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__DISPLAYPORT__LANE0__ENABLE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__DISPLAYPORT__LANE0__IO.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__DISPLAYPORT__LANE1__ENABLE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__DISPLAYPORT__LANE1__IO.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__DISPLAYPORT__PERIPHERAL__ENABLE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__DPAUX__PERIPHERAL__ENABLE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__DPAUX__PERIPHERAL__IO.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__DP__LANE_SEL.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__ENET0__GRP_MDIO__ENABLE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__ENET0__GRP_MDIO__IO.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__ENET0__PERIPHERAL__ENABLE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__ENET0__PERIPHERAL__IO.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__ENET1__GRP_MDIO__ENABLE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__ENET1__GRP_MDIO__IO.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__ENET1__PERIPHERAL__ENABLE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__ENET1__PERIPHERAL__IO.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__ENET2__GRP_MDIO__ENABLE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__ENET2__GRP_MDIO__IO.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__ENET2__PERIPHERAL__ENABLE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__ENET2__PERIPHERAL__IO.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__FP__POWER__ON.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__GEM0_COHERENCY.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__GEM1_COHERENCY.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__GEM2_COHERENCY.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__GEM3_COHERENCY.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__GEM__TSU__ENABLE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__GEM__TSU__IO.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__GENERATE_SECURITY_REGISTERS.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__GEN_IPI_0__MASTER.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__GEN_IPI_10__MASTER.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__GEN_IPI_1__MASTER.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__GEN_IPI_2__MASTER.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__GEN_IPI_3__MASTER.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__GEN_IPI_4__MASTER.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__GEN_IPI_5__MASTER.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__GEN_IPI_6__MASTER.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__GEN_IPI_7__MASTER.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__GEN_IPI_8__MASTER.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__GEN_IPI_9__MASTER.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__GPIO2_MIO__IO.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__GPIO2_MIO__PERIPHERAL__ENABLE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__GPIO_EMIO__PERIPHERAL__ENABLE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__GPIO_EMIO__PERIPHERAL__IO.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__GPIO_EMIO__WIDTH.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__GPU_PP0__POWER__ON.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__GPU_PP1__POWER__ON.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__GT_REF_CLK__FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__GT__LINK_SPEED.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__I2C0_LOOP_I2C1__ENABLE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__I2C0__GRP_INT__ENABLE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__I2C0__GRP_INT__IO.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__I2C1__GRP_INT__ENABLE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__I2C1__GRP_INT__IO.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__L2_BANK0__POWER__ON.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__NAND_COHERENCY.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__NAND__CHIP_ENABLE__ENABLE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__NAND__CHIP_ENABLE__IO.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__NAND__DATA_STROBE__ENABLE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__NAND__DATA_STROBE__IO.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__NAND__PERIPHERAL__ENABLE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__NAND__PERIPHERAL__IO.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__NAND__READY_BUSY__ENABLE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__NAND__READY_BUSY__IO.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__OCM_BANK0__POWER__ON.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__OCM_BANK1__POWER__ON.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__OCM_BANK2__POWER__ON.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__OCM_BANK3__POWER__ON.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PCIE__ACS_VIOLATION.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PCIE__AER_CAPABILITY.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PCIE__ATOMICOP_EGRESS_BLOCKED.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PCIE__BAR0_64BIT.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PCIE__BAR0_PREFETCHABLE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PCIE__BAR0_SCALE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PCIE__BAR0_SIZE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PCIE__BAR0_TYPE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PCIE__BAR0_VAL.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PCIE__BAR1_64BIT.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PCIE__BAR1_ENABLE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PCIE__BAR1_PREFETCHABLE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PCIE__BAR1_SCALE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PCIE__BAR1_SIZE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PCIE__BAR1_TYPE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PCIE__BAR1_VAL.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PCIE__BAR2_64BIT.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PCIE__BAR2_ENABLE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PCIE__BAR2_PREFETCHABLE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PCIE__BAR2_SCALE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PCIE__BAR2_SIZE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PCIE__BAR2_TYPE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PCIE__BAR2_VAL.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PCIE__BAR3_64BIT.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PCIE__BAR3_ENABLE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PCIE__BAR3_PREFETCHABLE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PCIE__BAR3_SCALE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PCIE__BAR3_SIZE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PCIE__BAR3_TYPE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PCIE__BAR3_VAL.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PCIE__BAR4_64BIT.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PCIE__BAR4_ENABLE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PCIE__BAR4_PREFETCHABLE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PCIE__BAR4_SCALE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PCIE__BAR4_SIZE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PCIE__BAR4_TYPE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PCIE__BAR4_VAL.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PCIE__BAR5_64BIT.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PCIE__BAR5_ENABLE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PCIE__BAR5_PREFETCHABLE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PCIE__BAR5_SCALE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PCIE__BAR5_SIZE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PCIE__BAR5_TYPE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PCIE__BAR5_VAL.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PCIE__BASE_CLASS_MENU.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PCIE__BRIDGE_BAR_INDICATOR.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PCIE__CAP_SLOT_IMPLEMENTED.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PCIE__CLASS_CODE_INTERFACE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PCIE__CLASS_CODE_VALUE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PCIE__COMPLETER_ABORT.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PCIE__COMPLTION_TIMEOUT.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PCIE__CORRECTABLE_INT_ERR.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PCIE__ECRC_CHECK.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PCIE__ECRC_ERR.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PCIE__ECRC_GEN.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PCIE__EROM_ENABLE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PCIE__EROM_SCALE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PCIE__EROM_SIZE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PCIE__EROM_VAL.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PCIE__FLOW_CONTROL_ERR.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PCIE__FLOW_CONTROL_PROTOCOL_ERR.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PCIE__HEADER_LOG_OVERFLOW.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PCIE__INTERFACE_WIDTH.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PCIE__INTX_GENERATION.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PCIE__INTX_PIN.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PCIE__LANE1__IO.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PCIE__LANE2__ENABLE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PCIE__LANE2__IO.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PCIE__LANE3__ENABLE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PCIE__LANE3__IO.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PCIE__LEGACY_INTERRUPT.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PCIE__MAX_PAYLOAD_SIZE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PCIE__MC_BLOCKED_TLP.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PCIE__MSIX_BAR_INDICATOR.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PCIE__MSIX_CAPABILITY.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PCIE__MSIX_PBA_BAR_INDICATOR.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PCIE__MSIX_PBA_OFFSET.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PCIE__MSIX_TABLE_OFFSET.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PCIE__MSIX_TABLE_SIZE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PCIE__MSI_64BIT_ADDR_CAPABLE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PCIE__MSI_CAPABILITY.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PCIE__MSI_MULTIPLE_MSG_CAPABLE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PCIE__MULTIHEADER.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PCIE__PERIPHERAL__ENDPOINT_ENABLE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PCIE__PERIPHERAL__ENDPOINT_IO.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PCIE__PERIPHERAL__ROOTPORT_ENABLE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PCIE__PERM_ROOT_ERR_UPDATE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PCIE__RECEIVER_ERR.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PCIE__RECEIVER_OVERFLOW.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PCIE__REVISION_ID.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PCIE__SUBSYSTEM_ID.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PCIE__SUBSYSTEM_VENDOR_ID.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PCIE__SUB_CLASS_INTERFACE_MENU.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PCIE__SURPRISE_DOWN.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PCIE__TLP_PREFIX_BLOCKED.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PCIE__UNCORRECTABL_INT_ERR.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PCIE__USE_CLASS_CODE_LOOKUP_ASSISTANT.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PCIE__VENDOR_ID.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PJTAG__PERIPHERAL__ENABLE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PJTAG__PERIPHERAL__IO.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PL__POWER__ON.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PMU_COHERENCY.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PMU__EMIO_GPI__ENABLE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PMU__EMIO_GPO__ENABLE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PMU__GPI0__ENABLE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PMU__GPI0__IO.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PMU__GPI1__ENABLE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PMU__GPI1__IO.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PMU__GPI2__ENABLE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PMU__GPI2__IO.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PMU__GPI3__ENABLE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PMU__GPI3__IO.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PMU__GPI4__ENABLE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PMU__GPI4__IO.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PMU__GPI5__ENABLE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PMU__GPI5__IO.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PMU__GPO0__ENABLE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PMU__GPO0__IO.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PMU__GPO1__ENABLE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PMU__GPO1__IO.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PMU__GPO2__ENABLE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PMU__GPO2__IO.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PMU__GPO3__ENABLE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PMU__GPO3__IO.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PMU__GPO4__ENABLE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PMU__GPO4__IO.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PMU__GPO5__ENABLE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PMU__GPO5__IO.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PMU__PERIPHERAL__ENABLE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PMU__PERIPHERAL__IO.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__POWER_SUMMARY__DYNAMIC__ANALOG.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__POWER_SUMMARY__DYNAMIC__DDR.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__POWER_SUMMARY__DYNAMIC__FPD.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__POWER_SUMMARY__DYNAMIC__LPD.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__POWER_SUMMARY__DYNAMIC__MIO.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__POWER_SUMMARY__DYNAMIC__PLL.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__POWER_SUMMARY__DYNAMIC__SERDES.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__POWER_SUMMARY__DYNAMIC__TOTAL.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__POWER_SUMMARY__ONCHIP.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__POWER_SUMMARY__STATIC__ANALOG.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__POWER_SUMMARY__STATIC__DDR.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__POWER_SUMMARY__STATIC__FPD.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__POWER_SUMMARY__STATIC__LPD.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__POWER_SUMMARY__STATIC__MIO.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__POWER_SUMMARY__STATIC__PLL.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__POWER_SUMMARY__STATIC__SERDES.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__POWER_SUMMARY__STATIC__TOTAL.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__POWER__ACPU__VCCPSINTFP.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__POWER__AFI_FPD__VCCPSINTFP.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__POWER__AFI_LPD__VCCPSINTLP.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__POWER__APLL__VCCPSPLL.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__POWER__CAN0__VCCPSIO.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__POWER__CAN1__VCCPSIO.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__POWER__CSU__VCCPSIO.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__POWER__DDR__VCCPSDDR.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__POWER__DDR__VCCPSINTFP.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__POWER__DPAUX__VCCPSIO.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__POWER__DPLL__VCCPSPLL.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__POWER__DP__VCCPSGTA.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__POWER__DP__VCCPSINTFP.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__POWER__FPINT__VCCPSINTFP.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__POWER__GEM0__VCCPSINTLP.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__POWER__GEM0__VCCPSIO.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__POWER__GEM1__VCCPSINTLP.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__POWER__GEM1__VCCPSIO.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__POWER__GEM2__VCCPSINTLP.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__POWER__GEM2__VCCPSIO.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__POWER__GEM3__VCCPSINTLP.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__POWER__GEM3__VCCPSIO.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__POWER__GPIO0__VCCPSIO.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__POWER__GPIO1__VCCPSIO.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__POWER__GPIO2__VCCPSIO.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__POWER__GPU__VCCPSINTFP.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__POWER__IOPLL__VCCPSPLL.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__POWER__LPINT__VCCPSINTLP.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__POWER__NAND__VCCPSINTLP.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__POWER__NAND__VCCPSIO.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__POWER__PCIE__VCCPSGTA.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__POWER__PCIE__VCCPSINTFP.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__POWER__PJTAG__VCCPSIO.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__POWER__PMU__VCCPSIO.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__POWER__QSPI__VCCPSINTLP.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__POWER__QSPI__VCCPSIO.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__POWER__RPLL__VCCPSPLL.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__POWER__RPU__VCCPSINTLP.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__POWER__SATA__VCCPSGTA.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__POWER__SATA__VCCPSINTFP.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__POWER__SD0__VCCPSIO.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__POWER__SD1__VCCPSIO.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__POWER__SGMII__VCCPSGTA.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__POWER__SPI0__VCCPSIO.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__POWER__SPI1__VCCPSIO.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__POWER__TRACE__VCCPSIO.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__POWER__TTC0__VCCPSIO.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__POWER__TTC1__VCCPSIO.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__POWER__TTC2__VCCPSIO.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__POWER__TTC3__VCCPSIO.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__POWER__UART0__VCCPSIO.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__POWER__UART1__VCCPSIO.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__POWER__USB0__VCCPSINTLP.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__POWER__USB0__VCCPSIO.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__POWER__USB1__VCCPSINTLP.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__POWER__USB1__VCCPSIO.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__POWER__USB3__VCCPSGTA.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__POWER__VPLL__VCCPSPLL.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__POWER__WDT0__VCCPSIO.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__POWER__WDT1__VCCPSIO.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__PSS_ALT_REF_CLK__FREQMHZ.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__QSPI_COHERENCY.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__RPU_COHERENCY.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__RPU__POWER__ON.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__SATA__LANE0__ENABLE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__SATA__LANE0__IO.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__SD0_COHERENCY.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__SD0__DATA_TRANSFER_MODE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__SD0__GRP_CD__ENABLE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__SD0__GRP_CD__IO.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__SD0__GRP_POW__ENABLE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__SD0__GRP_POW__IO.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__SD0__GRP_WP__ENABLE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__SD0__GRP_WP__IO.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__SD0__PERIPHERAL__ENABLE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__SD0__PERIPHERAL__IO.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__SD0__RESET__ENABLE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__SD0__SLOT_TYPE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__SD1_COHERENCY.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__SD1__RESET__ENABLE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__SPI0_LOOP_SPI1__ENABLE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__SPI0__GRP_SS0__ENABLE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__SPI0__GRP_SS0__IO.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__SPI0__GRP_SS1__ENABLE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__SPI0__GRP_SS1__IO.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__SPI0__GRP_SS2__ENABLE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__SPI0__GRP_SS2__IO.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__SPI0__PERIPHERAL__ENABLE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__SPI0__PERIPHERAL__IO.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__SPI1__GRP_SS0__ENABLE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__SPI1__GRP_SS0__IO.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__SPI1__GRP_SS1__ENABLE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__SPI1__GRP_SS1__IO.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__SPI1__GRP_SS2__ENABLE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__SPI1__GRP_SS2__IO.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__SPI1__PERIPHERAL__ENABLE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__SPI1__PERIPHERAL__IO.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__SWDT0__PERIPHERAL__ENABLE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__SWDT0__PERIPHERAL__IO.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__SWDT1__PERIPHERAL__ENABLE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__SWDT1__PERIPHERAL__IO.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__TCM0A__POWER__ON.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__TCM0B__POWER__ON.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__TCM1A__POWER__ON.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__TCM1B__POWER__ON.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__TESTSCAN__PERIPHERAL__ENABLE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__TRACE__PERIPHERAL__ENABLE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__TRACE__PERIPHERAL__IO.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__TRACE__WIDTH.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__TRISTATE__INVERTED.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__TTC1__PERIPHERAL__ENABLE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__TTC1__PERIPHERAL__IO.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__TTC2__PERIPHERAL__ENABLE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__TTC2__PERIPHERAL__IO.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__TTC3__PERIPHERAL__ENABLE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__TTC3__PERIPHERAL__IO.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__UART0_LOOP_UART1__ENABLE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__UART0__BAUD_RATE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__UART0__MODEM__ENABLE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__UART1__BAUD_RATE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__USB0_COHERENCY.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__USB1_COHERENCY.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__USB1__PERIPHERAL__ENABLE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__USB1__PERIPHERAL__IO.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__USB3_1__PERIPHERAL__ENABLE.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__USB3_1__PERIPHERAL__IO.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__USE__FABRIC__RST.VALUE_SRC {DEFAULT} \ + CONFIG.PSU__VIDEO_REF_CLK__FREQMHZ.VALUE_SRC {DEFAULT} \ +] $sys_ps8 + + +set_property CONFIG.PSU__USE__M_AXI_GP2 {1} $sys_ps8 +set_property CONFIG.PSU__MAXIGP2__DATA_WIDTH {32} $sys_ps8 +set_property CONFIG.PSU__FPGA_PL0_ENABLE {1} $sys_ps8 +set_property CONFIG.PSU__CRL_APB__PL0_REF_CTRL__FREQMHZ {100} $sys_ps8 +set_property CONFIG.PSU__FPGA_PL1_ENABLE {1} $sys_ps8 +set_property CONFIG.PSU__CRL_APB__PL1_REF_CTRL__FREQMHZ {200} $sys_ps8 +set_property CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR0 {3} $sys_ps8 +set_property CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR1 {2} $sys_ps8 +set_property CONFIG.PSU__USE__IRQ0 {1} $sys_ps8 +set_property CONFIG.PSU__USE__IRQ1 {1} $sys_ps8 +set_property CONFIG.PSU__GPIO_EMIO__PERIPHERAL__ENABLE {1} $sys_ps8 + +set_property -dict [list\ + CONFIG.PSU__SPI0__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__SPI0__PERIPHERAL__IO {EMIO} \ + CONFIG.PSU__SPI1__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__SPI1__PERIPHERAL__IO {EMIO} \ +] $sys_ps8 + +set_property -dict [list\ + CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__FREQMHZ {100} \ +] $sys_ps8 + +set sys_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 sys_rstgen] +set_property -dict [list CONFIG.C_EXT_RST_WIDTH {1}] $sys_rstgen + +# system reset/clock definitions + +ad_connect sys_cpu_clk sys_ps8/pl_clk0 +ad_connect sys_200m_clk sys_ps8/pl_clk1 +ad_connect sys_cpu_reset sys_rstgen/peripheral_reset +ad_connect sys_cpu_resetn sys_rstgen/peripheral_aresetn +ad_connect sys_cpu_clk sys_rstgen/slowest_sync_clk +ad_connect sys_ps8/pl_resetn0 sys_rstgen/ext_reset_in + +# gpio + +ad_connect gpio_i sys_ps8/emio_gpio_i +ad_connect gpio_o sys_ps8/emio_gpio_o + +# spi + +ad_connect sys_ps8/emio_spi0_ss_o_n spi0_csn +ad_connect sys_ps8/emio_spi0_sclk_o spi0_sclk +ad_connect sys_ps8/emio_spi0_m_o spi0_mosi +ad_connect sys_ps8/emio_spi0_m_i spi0_miso +ad_connect sys_ps8/emio_spi0_ss_i_n VCC +ad_connect sys_ps8/emio_spi0_sclk_i GND +ad_connect sys_ps8/emio_spi0_s_i GND + +ad_connect sys_ps8/emio_spi1_ss_o_n spi1_csn +ad_connect sys_ps8/emio_spi1_sclk_o spi1_sclk +ad_connect sys_ps8/emio_spi1_m_o spi1_mosi +ad_connect sys_ps8/emio_spi1_m_i spi1_miso +ad_connect sys_ps8/emio_spi1_ss_i_n VCC +ad_connect sys_ps8/emio_spi1_sclk_i GND +ad_connect sys_ps8/emio_spi1_s_i GND + +# interrupts + +set sys_concat_intc_0 [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 sys_concat_intc_0] +set_property -dict [list CONFIG.NUM_PORTS {8}] $sys_concat_intc_0 + +set sys_concat_intc_1 [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 sys_concat_intc_1] +set_property -dict [list CONFIG.NUM_PORTS {8}] $sys_concat_intc_1 + +ad_connect sys_concat_intc_0/dout sys_ps8/pl_ps_irq0 +ad_connect sys_concat_intc_1/dout sys_ps8/pl_ps_irq1 + +ad_connect sys_concat_intc_1/In7 ps_intr_15 +ad_connect sys_concat_intc_1/In6 ps_intr_14 +ad_connect sys_concat_intc_1/In5 ps_intr_13 +ad_connect sys_concat_intc_1/In4 ps_intr_12 +ad_connect sys_concat_intc_1/In3 ps_intr_11 +ad_connect sys_concat_intc_1/In2 ps_intr_10 +ad_connect sys_concat_intc_1/In1 ps_intr_09 +ad_connect sys_concat_intc_1/In0 ps_intr_08 +ad_connect sys_concat_intc_0/In7 ps_intr_07 +ad_connect sys_concat_intc_0/In6 ps_intr_06 +ad_connect sys_concat_intc_0/In5 ps_intr_05 +ad_connect sys_concat_intc_0/In4 ps_intr_04 +ad_connect sys_concat_intc_0/In3 ps_intr_03 +ad_connect sys_concat_intc_0/In2 ps_intr_02 +ad_connect sys_concat_intc_0/In1 ps_intr_01 +ad_connect sys_concat_intc_0/In0 ps_intr_00 + diff --git a/projects/common/zcu102/zcu102_system_constr.xdc b/projects/common/zcu102/zcu102_system_constr.xdc new file mode 100644 index 000000000..19740608b --- /dev/null +++ b/projects/common/zcu102/zcu102_system_constr.xdc @@ -0,0 +1,27 @@ + +# constraints +# gpio (switches, leds and such) + +set_property -dict {PACKAGE_PIN AN14 IOSTANDARD LVCMOS25} [get_ports gpio_bd_i[0]] ; ## GPIO_DIP_SW0 +set_property -dict {PACKAGE_PIN AP14 IOSTANDARD LVCMOS25} [get_ports gpio_bd_i[1]] ; ## GPIO_DIP_SW1 +set_property -dict {PACKAGE_PIN AM14 IOSTANDARD LVCMOS25} [get_ports gpio_bd_i[2]] ; ## GPIO_DIP_SW2 +set_property -dict {PACKAGE_PIN AN13 IOSTANDARD LVCMOS25} [get_ports gpio_bd_i[3]] ; ## GPIO_DIP_SW3 +set_property -dict {PACKAGE_PIN AN12 IOSTANDARD LVCMOS25} [get_ports gpio_bd_i[4]] ; ## GPIO_DIP_SW4 +set_property -dict {PACKAGE_PIN AP12 IOSTANDARD LVCMOS25} [get_ports gpio_bd_i[5]] ; ## GPIO_DIP_SW5 +set_property -dict {PACKAGE_PIN AL13 IOSTANDARD LVCMOS25} [get_ports gpio_bd_i[6]] ; ## GPIO_DIP_SW6 +set_property -dict {PACKAGE_PIN AK13 IOSTANDARD LVCMOS25} [get_ports gpio_bd_i[7]] ; ## GPIO_DIP_SW7 +set_property -dict {PACKAGE_PIN AE14 IOSTANDARD LVCMOS25} [get_ports gpio_bd_i[8]] ; ## GPIO_SW_E +set_property -dict {PACKAGE_PIN AE15 IOSTANDARD LVCMOS25} [get_ports gpio_bd_i[9]] ; ## GPIO_SW_S +set_property -dict {PACKAGE_PIN AG15 IOSTANDARD LVCMOS25} [get_ports gpio_bd_i[10]] ; ## GPIO_SW_N +set_property -dict {PACKAGE_PIN AF15 IOSTANDARD LVCMOS25} [get_ports gpio_bd_i[11]] ; ## GPIO_SW_W +set_property -dict {PACKAGE_PIN AG13 IOSTANDARD LVCMOS25} [get_ports gpio_bd_i[12]] ; ## GPIO_SW_C + +set_property -dict {PACKAGE_PIN AG14 IOSTANDARD LVCMOS25} [get_ports gpio_bd_o[0]] ; ## GPIO_LED_0 +set_property -dict {PACKAGE_PIN AF13 IOSTANDARD LVCMOS25} [get_ports gpio_bd_o[1]] ; ## GPIO_LED_1 +set_property -dict {PACKAGE_PIN AE13 IOSTANDARD LVCMOS25} [get_ports gpio_bd_o[2]] ; ## GPIO_LED_2 +set_property -dict {PACKAGE_PIN AJ14 IOSTANDARD LVCMOS25} [get_ports gpio_bd_o[3]] ; ## GPIO_LED_3 +set_property -dict {PACKAGE_PIN AJ15 IOSTANDARD LVCMOS25} [get_ports gpio_bd_o[4]] ; ## GPIO_LED_4 +set_property -dict {PACKAGE_PIN AH13 IOSTANDARD LVCMOS25} [get_ports gpio_bd_o[5]] ; ## GPIO_LED_5 +set_property -dict {PACKAGE_PIN AH14 IOSTANDARD LVCMOS25} [get_ports gpio_bd_o[6]] ; ## GPIO_LED_6 +set_property -dict {PACKAGE_PIN AL12 IOSTANDARD LVCMOS25} [get_ports gpio_bd_o[7]] ; ## GPIO_LED_7 + diff --git a/projects/common/zed/zed_system_bd.tcl b/projects/common/zed/zed_system_bd.tcl index 57e47c751..25c512ff2 100644 --- a/projects/common/zed/zed_system_bd.tcl +++ b/projects/common/zed/zed_system_bd.tcl @@ -125,7 +125,7 @@ set_property -dict [list CONFIG.C_INCLUDE_S2MM {0}] $axi_hdmi_dma # audio peripherals -set sys_audio_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.2 sys_audio_clkgen] +set sys_audio_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.3 sys_audio_clkgen] set_property -dict [list CONFIG.PRIM_IN_FREQ {200.000}] $sys_audio_clkgen set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {12.288}] $sys_audio_clkgen set_property -dict [list CONFIG.USE_LOCKED {false}] $sys_audio_clkgen diff --git a/projects/daq1/Makefile b/projects/daq1/Makefile index 5b866a1ac..9d9772a62 100644 --- a/projects/daq1/Makefile +++ b/projects/daq1/Makefile @@ -7,14 +7,17 @@ .PHONY: all clean clean-all all: + -make -C a10gx all -make -C zc706 all clean: + make -C a10gx clean make -C zc706 clean clean-all: + make -C a10gx clean-all make -C zc706 clean-all #################################################################################### diff --git a/projects/daq1/a10gx/Makefile b/projects/daq1/a10gx/Makefile new file mode 100644 index 000000000..b0a3e7b0f --- /dev/null +++ b/projects/daq1/a10gx/Makefile @@ -0,0 +1,150 @@ +#################################################################################### +#################################################################################### +## Copyright 2011(c) Analog Devices, Inc. +## Auto-generated, do not modify! +#################################################################################### +#################################################################################### + +ifeq ($(MMU),) + MMU := 1 +endif + +export ALT_NIOS_MMU_ENABLED := $(MMU) + +M_DEPS += system_top.v +M_DEPS += system_qsys.tcl +M_DEPS += system_project.tcl +M_DEPS += system_constr.sdc +M_DEPS += ../common/daq1_spi.v +M_DEPS += ../common/daq1_qsys.tcl +M_DEPS += ../../scripts/adi_tquest.tcl +M_DEPS += ../../scripts/adi_env.tcl +M_DEPS += ../../common/altera/sys_gen.tcl +M_DEPS += ../../common/a10gx/a10gx_system_qsys.tcl +M_DEPS += ../../common/a10gx/a10gx_system_assign.tcl +M_DEPS += ../../../library/altera/common/ad_mul.v +M_DEPS += ../../../library/axi_ad9122/axi_ad9122.v +M_DEPS += ../../../library/axi_ad9122/axi_ad9122_channel.v +M_DEPS += ../../../library/axi_ad9122/axi_ad9122_constr.sdc +M_DEPS += ../../../library/axi_ad9122/axi_ad9122_core.v +M_DEPS += ../../../library/axi_ad9122/axi_ad9122_hw.tcl +M_DEPS += ../../../library/axi_ad9122/axi_ad9122_if.v +M_DEPS += ../../../library/axi_ad9684/axi_ad9684.v +M_DEPS += ../../../library/axi_ad9684/axi_ad9684_channel.v +M_DEPS += ../../../library/axi_ad9684/axi_ad9684_constr.sdc +M_DEPS += ../../../library/axi_ad9684/axi_ad9684_hw.tcl +M_DEPS += ../../../library/axi_ad9684/axi_ad9684_if.v +M_DEPS += ../../../library/axi_ad9684/axi_ad9684_pnmon.v +M_DEPS += ../../../library/axi_dmac/2d_transfer.v +M_DEPS += ../../../library/axi_dmac/address_generator.v +M_DEPS += ../../../library/axi_dmac/axi_dmac.v +M_DEPS += ../../../library/axi_dmac/axi_dmac_constr.sdc +M_DEPS += ../../../library/axi_dmac/axi_dmac_hw.tcl +M_DEPS += ../../../library/axi_dmac/axi_register_slice.v +M_DEPS += ../../../library/axi_dmac/data_mover.v +M_DEPS += ../../../library/axi_dmac/dest_axi_mm.v +M_DEPS += ../../../library/axi_dmac/dest_axi_stream.v +M_DEPS += ../../../library/axi_dmac/dest_fifo_inf.v +M_DEPS += ../../../library/axi_dmac/inc_id.h +M_DEPS += ../../../library/axi_dmac/request_arb.v +M_DEPS += ../../../library/axi_dmac/request_generator.v +M_DEPS += ../../../library/axi_dmac/resp.h +M_DEPS += ../../../library/axi_dmac/response_generator.v +M_DEPS += ../../../library/axi_dmac/response_handler.v +M_DEPS += ../../../library/axi_dmac/splitter.v +M_DEPS += ../../../library/axi_dmac/src_axi_mm.v +M_DEPS += ../../../library/axi_dmac/src_axi_stream.v +M_DEPS += ../../../library/axi_dmac/src_fifo_inf.v +M_DEPS += ../../../library/common/ad_axi_ip_constr.sdc +M_DEPS += ../../../library/common/ad_axis_inf_rx.v +M_DEPS += ../../../library/common/ad_datafmt.v +M_DEPS += ../../../library/common/ad_dds.v +M_DEPS += ../../../library/common/ad_dds_1.v +M_DEPS += ../../../library/common/ad_dds_sine.v +M_DEPS += ../../../library/common/ad_mem_asym.v +M_DEPS += ../../../library/common/ad_pnmon.v +M_DEPS += ../../../library/common/ad_rst.v +M_DEPS += ../../../library/common/sync_bits.v +M_DEPS += ../../../library/common/sync_gray.v +M_DEPS += ../../../library/common/up_adc_channel.v +M_DEPS += ../../../library/common/up_adc_common.v +M_DEPS += ../../../library/common/up_axi.v +M_DEPS += ../../../library/common/up_clock_mon.v +M_DEPS += ../../../library/common/up_dac_channel.v +M_DEPS += ../../../library/common/up_dac_common.v +M_DEPS += ../../../library/common/up_delay_cntrl.v +M_DEPS += ../../../library/common/up_xfer_cntrl.v +M_DEPS += ../../../library/common/up_xfer_status.v +M_DEPS += ../../../library/scripts/adi_env.tcl +M_DEPS += ../../../library/scripts/adi_ip_alt.tcl +M_DEPS += ../../../library/util_adcfifo/util_adcfifo.v +M_DEPS += ../../../library/util_adcfifo/util_adcfifo_constr.sdc +M_DEPS += ../../../library/util_adcfifo/util_adcfifo_hw.tcl +M_DEPS += ../../../library/util_axis_fifo/address_gray.v +M_DEPS += ../../../library/util_axis_fifo/address_gray_pipelined.v +M_DEPS += ../../../library/util_axis_fifo/address_sync.v +M_DEPS += ../../../library/util_axis_fifo/util_axis_fifo.v +M_DEPS += ../../../library/util_axis_resize/util_axis_resize.v +M_DEPS += ../../../library/util_cpack/util_cpack.v +M_DEPS += ../../../library/util_cpack/util_cpack_dsf.v +M_DEPS += ../../../library/util_cpack/util_cpack_hw.tcl +M_DEPS += ../../../library/util_cpack/util_cpack_mux.v +M_DEPS += ../../../library/util_upack/util_upack.v +M_DEPS += ../../../library/util_upack/util_upack_dmx.v +M_DEPS += ../../../library/util_upack/util_upack_dsf.v +M_DEPS += ../../../library/util_upack/util_upack_hw.tcl + + +M_ALTERA := quartus_sh --64bit -t + + +M_FLIST += *.log +M_FLIST += *_INFO.txt +M_FLIST += *_dump.txt +M_FLIST += db +M_FLIST += *.asm.rpt +M_FLIST += *.done +M_FLIST += *.eda.rpt +M_FLIST += *.fit.* +M_FLIST += *.map.* +M_FLIST += *.sta.* +M_FLIST += *.qsf +M_FLIST += *.qpf +M_FLIST += *.qws +M_FLIST += *.sof +M_FLIST += *.cdf +M_FLIST += *.sld +M_FLIST += *.qdf +M_FLIST += hc_output +M_FLIST += system_bd +M_FLIST += hps_isw_handoff +M_FLIST += hps_sdram_*.csv +M_FLIST += *ddr3_*.csv +M_FLIST += incremental_db +M_FLIST += reconfig_mif +M_FLIST += *.sopcinfo +M_FLIST += *.jdi +M_FLIST += *.pin +M_FLIST += *_summary.csv +M_FLIST += *.dpf + + + +.PHONY: all clean clean-all +all: daq1_a10gx.sof + + + +clean:clean-all + + +clean-all: + rm -rf $(M_FLIST) + + +daq1_a10gx.sof: $(M_DEPS) + -rm -rf $(M_FLIST) + $(M_ALTERA) system_project.tcl >> daq1_a10gx_quartus.log 2>&1 + +#################################################################################### +#################################################################################### diff --git a/projects/daq1/a10gx/system_constr.sdc b/projects/daq1/a10gx/system_constr.sdc new file mode 100644 index 000000000..b47af1682 --- /dev/null +++ b/projects/daq1/a10gx/system_constr.sdc @@ -0,0 +1,8 @@ + +create_clock -period "10.000 ns" -name sys_clk_100mhz [get_ports {sys_clk}] +create_clock -period "2.000 ns" -name rx_clk_500mhz [get_ports {adc_clk_in}] +create_clock -period "2.000 ns" -name tx_clk_500mhz [get_ports {dac_clk_in}] + +derive_pll_clocks +derive_clock_uncertainty + diff --git a/projects/daq1/a10gx/system_project.tcl b/projects/daq1/a10gx/system_project.tcl new file mode 100644 index 000000000..8862cc6be --- /dev/null +++ b/projects/daq1/a10gx/system_project.tcl @@ -0,0 +1,137 @@ + +load_package flow + +source ../../scripts/adi_env.tcl +project_new daq1_a10gx -overwrite + +source "../../common/a10gx/a10gx_system_assign.tcl" + +set_global_assignment -name VERILOG_FILE ../common/daq1_spi.v +set_global_assignment -name VERILOG_FILE system_top.v +set_global_assignment -name QSYS_FILE system_bd.qsys + +set_global_assignment -name SDC_FILE system_constr.sdc +set_global_assignment -name TOP_LEVEL_ENTITY system_top + +# physical interface + +set_location_assignment PIN_BA12 -to dac_clk_in ; ## G02 FMC_LPC_CLK1_M2C_P +set_location_assignment PIN_BA13 -to "dac_clk_in(n)" ; ## G03 FMC_LPC_CLK1_M2C_N +set_location_assignment PIN_AY15 -to dac_clk_out ; ## G27 FMC_LPC_LA25_P +set_location_assignment PIN_AY14 -to "dac_clk_out(n)" ; ## G28 FMC_LPC_LA25_N +set_location_assignment PIN_AV20 -to dac_frame_out ; ## H37 FMC_LPC_LA32_P +set_location_assignment PIN_AU20 -to "dac_frame_out(n)" ; ## H38 FMC_LPC_LA32_N +set_location_assignment PIN_AR9 -to dac_data_out[0] ; ## H19 FMC_LPC_LA15_P +set_location_assignment PIN_AT9 -to "dac_data_out[0](n)" ; ## H20 FMC_LPC_LA15_N +set_location_assignment PIN_AU8 -to dac_data_out[1] ; ## G21 FMC_LPC_LA20_P +set_location_assignment PIN_AT8 -to "dac_data_out[1](n)" ; ## G22 FMC_LPC_LA20_N +set_location_assignment PIN_AU11 -to dac_data_out[2] ; ## H22 FMC_LPC_LA19_P +set_location_assignment PIN_AU12 -to "dac_data_out[2](n)" ; ## H23 FMC_LPC_LA19_N +set_location_assignment PIN_AV19 -to dac_data_out[3] ; ## D20 FMC_LPC_LA17_CC_P +set_location_assignment PIN_AW19 -to "dac_data_out[3](n)" ; ## D21 FMC_LPC_LA17_CC_N +set_location_assignment PIN_AU18 -to dac_data_out[4] ; ## D23 FMC_LPC_LA23_P +set_location_assignment PIN_AT18 -to "dac_data_out[4](n)" ; ## D24 FMC_LPC_LA23_N +set_location_assignment PIN_AW12 -to dac_data_out[5] ; ## G24 FMC_LPC_LA22_P +set_location_assignment PIN_AY12 -to "dac_data_out[5](n)" ; ## G25 FMC_LPC_LA22_N +set_location_assignment PIN_AU21 -to dac_data_out[6] ; ## C22 FMC_LPC_LA18_CC_P +set_location_assignment PIN_AV21 -to "dac_data_out[6](n)" ; ## C23 FMC_LPC_LA18_CC_N +set_location_assignment PIN_AY10 -to dac_data_out[7] ; ## H25 FMC_LPC_LA21_P +set_location_assignment PIN_AY11 -to "dac_data_out[7](n)" ; ## H26 FMC_LPC_LA21_N +set_location_assignment PIN_AT19 -to dac_data_out[8] ; ## D26 FMC_LPC_LA26_P +set_location_assignment PIN_AT20 -to "dac_data_out[8](n)" ; ## D27 FMC_LPC_LA26_N +set_location_assignment PIN_BB15 -to dac_data_out[9] ; ## H28 FMC_LPC_LA24_P +set_location_assignment PIN_BC15 -to "dac_data_out[9](n)" ; ## H29 FMC_LPC_LA24_N +set_location_assignment PIN_AP21 -to dac_data_out[10] ; ## C26 FMC_LPC_LA27_P +set_location_assignment PIN_AR21 -to "dac_data_out[10](n)" ; ## C27 FMC_LPC_LA27_N +set_location_assignment PIN_BA15 -to dac_data_out[11] ; ## G30 FMC_LPC_LA29_P +set_location_assignment PIN_BA14 -to "dac_data_out[11](n)" ; ## G31 FMC_LPC_LA29_N +set_location_assignment PIN_AY16 -to dac_data_out[12] ; ## H31 FMC_LPC_LA28_P +set_location_assignment PIN_AW16 -to "dac_data_out[12](n)" ; ## H32 FMC_LPC_LA28_N +set_location_assignment PIN_BB17 -to dac_data_out[13] ; ## G33 FMC_LPC_LA31_P +set_location_assignment PIN_BB18 -to "dac_data_out[13](n)" ; ## G34 FMC_LPC_LA31_N +set_location_assignment PIN_BC18 -to dac_data_out[14] ; ## H34 FMC_LPC_LA30_P +set_location_assignment PIN_BD18 -to "dac_data_out[14](n)" ; ## H35 FMC_LPC_LA30_N +set_location_assignment PIN_AY17 -to dac_data_out[15] ; ## G36 FMC_LPC_LA33_P +set_location_assignment PIN_AW17 -to "dac_data_out[15](n)" ; ## G37 FMC_LPC_LA33_N + +set_location_assignment PIN_AV15 -to adc_clk_in ; ## G06 FMC_LPC_LA00_CC_P +set_location_assignment PIN_AU15 -to "adc_clk_in(n)" ; ## G07 FMC_LPC_LA00_CC_N +set_location_assignment PIN_AR15 -to adc_data_in[0] ; ## C14 FMC_LPC_LA10_P +set_location_assignment PIN_AT15 -to "adc_data_in[0](n)" ; ## C15 FMC_LPC_LA10_N +set_location_assignment PIN_AW18 -to adc_data_in[1] ; ## C18 FMC_LPC_LA14_P +set_location_assignment PIN_AV18 -to "adc_data_in[1](n)" ; ## C19 FMC_LPC_LA14_N +set_location_assignment PIN_AR17 -to adc_data_in[2] ; ## D17 FMC_LPC_LA13_P +set_location_assignment PIN_AP17 -to "adc_data_in[2](n)" ; ## D18 FMC_LPC_LA13_N +set_location_assignment PIN_AT14 -to adc_data_in[3] ; ## H16 FMC_LPC_LA11_P +set_location_assignment PIN_AR14 -to "adc_data_in[3](n)" ; ## H17 FMC_LPC_LA11_N +set_location_assignment PIN_AR16 -to adc_data_in[4] ; ## G15 FMC_LPC_LA12_P +set_location_assignment PIN_AP16 -to "adc_data_in[4](n)" ; ## G16 FMC_LPC_LA12_N +set_location_assignment PIN_AW13 -to adc_data_in[5] ; ## D14 FMC_LPC_LA09_P +set_location_assignment PIN_AV13 -to "adc_data_in[5](n)" ; ## D15 FMC_LPC_LA09_N +set_location_assignment PIN_AT17 -to adc_data_in[6] ; ## H13 FMC_LPC_LA07_P +set_location_assignment PIN_AU17 -to "adc_data_in[6](n)" ; ## H14 FMC_LPC_LA07_N +set_location_assignment PIN_AP18 -to adc_data_in[7] ; ## G12 FMC_LPC_LA08_P +set_location_assignment PIN_AN19 -to "adc_data_in[7](n)" ; ## G13 FMC_LPC_LA08_N +set_location_assignment PIN_AV11 -to adc_data_in[8] ; ## D11 FMC_LPC_LA05_P +set_location_assignment PIN_AW11 -to "adc_data_in[8](n)" ; ## D12 FMC_LPC_LA05_N +set_location_assignment PIN_AN20 -to adc_data_in[9] ; ## H10 FMC_LPC_LA04_P +set_location_assignment PIN_AP19 -to "adc_data_in[9](n)" ; ## H11 FMC_LPC_LA04_N +set_location_assignment PIN_AR20 -to adc_data_in[10] ; ## G09 FMC_LPC_LA03_P +set_location_assignment PIN_AR19 -to "adc_data_in[10](n)" ; ## G10 FMC_LPC_LA03_N +set_location_assignment PIN_AV14 -to adc_data_in[11] ; ## C10 FMC_LPC_LA06_P +set_location_assignment PIN_AW14 -to "adc_data_in[11](n)" ; ## C11 FMC_LPC_LA06_N +set_location_assignment PIN_AR22 -to adc_data_in[12] ; ## H07 FMC_LPC_LA02_P +set_location_assignment PIN_AT22 -to "adc_data_in[12](n)" ; ## H08 FMC_LPC_LA02_N +set_location_assignment PIN_AT10 -to adc_data_in[13] ; ## D08 FMC_LPC_LA01_CC_P +set_location_assignment PIN_AR11 -to "adc_data_in[13](n)" ; ## D09 FMC_LPC_LA01_CC_N + +set_instance_assignment -name IO_STANDARD LVDS -to dac_clk_in +set_instance_assignment -name IO_STANDARD LVDS -to dac_clk_out +set_instance_assignment -name IO_STANDARD LVDS -to dac_frame_out +set_instance_assignment -name IO_STANDARD LVDS -to dac_data_out[0] +set_instance_assignment -name IO_STANDARD LVDS -to dac_data_out[1] +set_instance_assignment -name IO_STANDARD LVDS -to dac_data_out[2] +set_instance_assignment -name IO_STANDARD LVDS -to dac_data_out[3] +set_instance_assignment -name IO_STANDARD LVDS -to dac_data_out[4] +set_instance_assignment -name IO_STANDARD LVDS -to dac_data_out[5] +set_instance_assignment -name IO_STANDARD LVDS -to dac_data_out[6] +set_instance_assignment -name IO_STANDARD LVDS -to dac_data_out[7] +set_instance_assignment -name IO_STANDARD LVDS -to dac_data_out[8] +set_instance_assignment -name IO_STANDARD LVDS -to dac_data_out[9] +set_instance_assignment -name IO_STANDARD LVDS -to dac_data_out[10] +set_instance_assignment -name IO_STANDARD LVDS -to dac_data_out[11] +set_instance_assignment -name IO_STANDARD LVDS -to dac_data_out[12] +set_instance_assignment -name IO_STANDARD LVDS -to dac_data_out[13] +set_instance_assignment -name IO_STANDARD LVDS -to dac_data_out[14] +set_instance_assignment -name IO_STANDARD LVDS -to dac_data_out[15] +set_instance_assignment -name IO_STANDARD LVDS -to adc_clk_in +set_instance_assignment -name IO_STANDARD LVDS -to adc_data_in[0] +set_instance_assignment -name IO_STANDARD LVDS -to adc_data_in[1] +set_instance_assignment -name IO_STANDARD LVDS -to adc_data_in[2] +set_instance_assignment -name IO_STANDARD LVDS -to adc_data_in[3] +set_instance_assignment -name IO_STANDARD LVDS -to adc_data_in[4] +set_instance_assignment -name IO_STANDARD LVDS -to adc_data_in[5] +set_instance_assignment -name IO_STANDARD LVDS -to adc_data_in[6] +set_instance_assignment -name IO_STANDARD LVDS -to adc_data_in[7] +set_instance_assignment -name IO_STANDARD LVDS -to adc_data_in[8] +set_instance_assignment -name IO_STANDARD LVDS -to adc_data_in[9] +set_instance_assignment -name IO_STANDARD LVDS -to adc_data_in[10] +set_instance_assignment -name IO_STANDARD LVDS -to adc_data_in[11] +set_instance_assignment -name IO_STANDARD LVDS -to adc_data_in[12] +set_instance_assignment -name IO_STANDARD LVDS -to adc_data_in[13] +set_instance_assignment -name IO_STANDARD LVDS -to adc_data_in[14] +set_instance_assignment -name IO_STANDARD LVDS -to adc_data_in[15] + +# SPI interface + +set_location_assignment PIN_AY19 -to spi_csn ; ## H05 FMC_LPC_CLK0_M2C_N +set_location_assignment PIN_AY20 -to spi_clk ; ## H04 FMC_LPC_CLK0_M2C_P +set_location_assignment PIN_AT13 -to spi_sdio ; ## G18 FMC_LPC_LA16_P +set_location_assignment PIN_AU13 -to spi_int ; ## G19 FMC_LPC_LA16_N + +set_instance_assignment -name IO_STANDARD "1.8V" -to spi_csn +set_instance_assignment -name IO_STANDARD "1.8V" -to spi_clk +set_instance_assignment -name IO_STANDARD "1.8V" -to spi_sdio +set_instance_assignment -name IO_STANDARD "1.8V" -to spi_int + +execute_flow -compile diff --git a/projects/daq1/a10gx/system_qsys.tcl b/projects/daq1/a10gx/system_qsys.tcl new file mode 100644 index 000000000..03e9d49f3 --- /dev/null +++ b/projects/daq1/a10gx/system_qsys.tcl @@ -0,0 +1,5 @@ + +source $ad_hdl_dir/projects/common/a10gx/a10gx_system_qsys.tcl +source ../common/daq1_qsys.tcl + + diff --git a/projects/daq1/a10gx/system_top.v b/projects/daq1/a10gx/system_top.v new file mode 100644 index 000000000..503691a7d --- /dev/null +++ b/projects/daq1/a10gx/system_top.v @@ -0,0 +1,195 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top ( + + // clock and resets + + input sys_clk, + input sys_resetn, + + // ddr3 + + output ddr3_clk_p, + output ddr3_clk_n, + output [ 14:0] ddr3_a, + output [ 2:0] ddr3_ba, + output ddr3_cke, + output ddr3_cs_n, + output ddr3_odt, + output ddr3_reset_n, + output ddr3_we_n, + output ddr3_ras_n, + output ddr3_cas_n, + inout [ 7:0] ddr3_dqs_p, + inout [ 7:0] ddr3_dqs_n, + inout [ 63:0] ddr3_dq, + output [ 7:0] ddr3_dm, + input ddr3_rzq, + input ddr3_ref_clk, + + // ethernet + + input eth_ref_clk, + input eth_rxd, + output eth_txd, + output eth_mdc, + inout eth_mdio, + output eth_resetn, + input eth_intn, + + // board gpio + + input [ 10:0] gpio_bd_i, + output [ 15:0] gpio_bd_o, + + // daq1 interface + + input dac_clk_in_p, + input dac_clk_in_n, + output dac_clk_out_p, + output dac_clk_out_n, + output dac_frame_out_p, + output dac_frame_out_n, + output [15:0] dac_data_out_p, + output [15:0] dac_data_out_n, + + input adc_clk_in_p, + input adc_clk_in_n, + input [13:0] adc_data_in_p, + input [13:0] adc_data_in_n, + + output spi_clk, + output spi_csn, + inout spi_sdio, + input spi_int); + + // internal signals + + wire [63:0] gpio_i; + wire [63:0] gpio_o; + wire [63:0] gpio_t; + wire spi_mosi; + wire spi_miso; + + // board specific connections + + assign eth_resetn = ~eth_reset; + assign eth_mdio_i = eth_mdio; + assign eth_mdio = (eth_mdio_t == 1'b1) ? 1'bz : eth_mdio_o; + + assign ddr3_a[14:12] = 3'd0; + + assign gpio_i[31:27] = gpio_o[31:27]; + assign gpio_i[26:16] = gpio_bd_i; + assign gpio_i[15: 0] = gpio_o[15:0]; + + assign gpio_bd_o = gpio_o[15:0]; + + // instantiations + + daq1_spi i_spi ( + .spi_csn (spi_csn), + .spi_clk (spi_clk), + .spi_mosi (spi_mosi), + .spi_miso (spi_miso), + .spi_sdio (spi_sdio)); + + system_bd i_system_bd ( + .sys_clk_clk (sys_clk), + .sys_rst_reset_n (sys_resetn), + + .sys_ddr3_cntrl_mem_mem_ck (ddr3_clk_p), + .sys_ddr3_cntrl_mem_mem_ck_n (ddr3_clk_n), + .sys_ddr3_cntrl_mem_mem_a (ddr3_a[11:0]), + .sys_ddr3_cntrl_mem_mem_ba (ddr3_ba), + .sys_ddr3_cntrl_mem_mem_cke (ddr3_cke), + .sys_ddr3_cntrl_mem_mem_cs_n (ddr3_cs_n), + .sys_ddr3_cntrl_mem_mem_odt (ddr3_odt), + .sys_ddr3_cntrl_mem_mem_reset_n (ddr3_reset_n), + .sys_ddr3_cntrl_mem_mem_we_n (ddr3_we_n), + .sys_ddr3_cntrl_mem_mem_ras_n (ddr3_ras_n), + .sys_ddr3_cntrl_mem_mem_cas_n (ddr3_cas_n), + .sys_ddr3_cntrl_mem_mem_dqs (ddr3_dqs_p[7:0]), + .sys_ddr3_cntrl_mem_mem_dqs_n (ddr3_dqs_n[7:0]), + .sys_ddr3_cntrl_mem_mem_dq (ddr3_dq[63:0]), + .sys_ddr3_cntrl_mem_mem_dm (ddr3_dm[7:0]), + .sys_ddr3_cntrl_oct_oct_rzqin (ddr3_rzq), + .sys_ddr3_cntrl_pll_ref_clk_clk (ddr3_ref_clk), + + .sys_ethernet_mdio_mdc (eth_mdc), + .sys_ethernet_mdio_mdio_in (eth_mdio_i), + .sys_ethernet_mdio_mdio_out (eth_mdio_o), + .sys_ethernet_mdio_mdio_oen (eth_mdio_t), + .sys_ethernet_ref_clk_clk (eth_ref_clk), + .sys_ethernet_reset_reset (eth_reset), + .sys_ethernet_sgmii_rxp_0 (eth_rxd), + .sys_ethernet_sgmii_txp_0 (eth_txd), + + .sys_gpio_bd_in_port (gpio_i[31:0]), + .sys_gpio_bd_out_port (gpio_o[31:0]), + .sys_gpio_in_export (gpio_i[63:32]), + .sys_gpio_out_export (gpio_o[63:32]), + + .sys_spi_MISO (spi_miso), + .sys_spi_MOSI (spi_mosi), + .sys_spi_SCLK (spi_clk), + .sys_spi_SS_n (spi_csn), + + .spi_int_irq(spi_int), + + .axi_ad9684_device_if_adc_clk_in_n (adc_clk_in_n), + .axi_ad9684_device_if_adc_clk_in_p (adc_clk_in_p), + .axi_ad9684_device_if_adc_data_in_n (adc_data_in_n), + .axi_ad9684_device_if_adc_data_in_p (adc_data_in_p), + .axi_ad9122_device_if_dac_clk_in_n (dac_clk_in_n), + .axi_ad9122_device_if_dac_clk_in_p (dac_clk_in_p), + .axi_ad9122_device_if_dac_clk_out_n (dac_clk_out_n), + .axi_ad9122_device_if_dac_clk_out_p (dac_clk_out_p), + .axi_ad9122_device_if_dac_data_out_n (dac_data_out_n), + .axi_ad9122_device_if_dac_data_out_p (dac_data_out_p), + .axi_ad9122_device_if_dac_frame_out_n (dac_frame_out_n), + .axi_ad9122_device_if_dac_frame_out_p (dac_frame_out_p) +); + +endmodule + + +// *************************************************************************** +// *************************************************************************** diff --git a/projects/daq1/common/daq1_bd.tcl b/projects/daq1/common/daq1_bd.tcl index 4f2fe6dee..8af27fc59 100644 --- a/projects/daq1/common/daq1_bd.tcl +++ b/projects/daq1/common/daq1_bd.tcl @@ -1,234 +1,143 @@ -# daq1 +# ad9122 interface -create_bd_port -dir I rx_ref_clk -create_bd_port -dir O rx_sync -create_bd_port -dir I rx_sysref -create_bd_port -dir I -from 1 -to 0 rx_data_p -create_bd_port -dir I -from 1 -to 0 rx_data_n +create_bd_port -dir I dac_clk_in_p +create_bd_port -dir I dac_clk_in_n +create_bd_port -dir O dac_clk_out_p +create_bd_port -dir O dac_clk_out_n +create_bd_port -dir O dac_frame_out_p +create_bd_port -dir O dac_frame_out_n +create_bd_port -dir O -from 15 -to 0 dac_data_out_p +create_bd_port -dir O -from 15 -to 0 dac_data_out_n -create_bd_port -dir O dac_clk -create_bd_port -dir O dac_valid_0 -create_bd_port -dir O dac_enable_0 -create_bd_port -dir I -from 63 -to 0 dac_ddata_0 -create_bd_port -dir O dac_valid_1 -create_bd_port -dir O dac_enable_1 -create_bd_port -dir I -from 63 -to 0 dac_ddata_1 -create_bd_port -dir I dac_drd -create_bd_port -dir O -from 127 -to 0 dac_ddata +# ad9684 interface -create_bd_port -dir O adc_clk -create_bd_port -dir O adc_enable_a -create_bd_port -dir O adc_valid_a -create_bd_port -dir O -from 31 -to 0 adc_data_a -create_bd_port -dir O adc_enable_b -create_bd_port -dir O adc_valid_b -create_bd_port -dir O -from 31 -to 0 adc_data_b -create_bd_port -dir I adc_dwr -create_bd_port -dir I adc_dsync -create_bd_port -dir I -from 63 -to 0 adc_ddata +create_bd_port -dir I adc_clk_in_p +create_bd_port -dir I adc_clk_in_n +create_bd_port -dir I -from 13 -to 0 adc_data_in_p +create_bd_port -dir I -from 13 -to 0 adc_data_in_n -create_bd_port -dir I tx_ref_clk_p -create_bd_port -dir I tx_ref_clk_n -create_bd_port -dir O tx_clk_p -create_bd_port -dir O tx_clk_n -create_bd_port -dir O tx_frame_p -create_bd_port -dir O tx_frame_n -create_bd_port -dir O -from 15 -to 0 tx_data_p -create_bd_port -dir O -from 15 -to 0 tx_data_n +# daq1 irq + +create_bd_port -dir I spi_int # dac peripherals -create_bd_cell -type ip -vlnv analog.com:user:axi_ad9122:1.0 axi_ad9122_core +set axi_ad9122_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9122:1.0 axi_ad9122_core] -create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9122_dma -set_property -dict [list CONFIG.C_DMA_TYPE_SRC {0}] [get_bd_cells axi_ad9122_dma] -set_property -dict [list CONFIG.C_DMA_TYPE_DEST {2}] [get_bd_cells axi_ad9122_dma] -set_property -dict [list CONFIG.ID {1}] [get_bd_cells axi_ad9122_dma] -set_property -dict [list CONFIG.C_AXI_SLICE_SRC {0}] [get_bd_cells axi_ad9122_dma] -set_property -dict [list CONFIG.C_AXI_SLICE_DEST {0}] [get_bd_cells axi_ad9122_dma] -set_property -dict [list CONFIG.C_DMA_LENGTH_WIDTH {24}] [get_bd_cells axi_ad9122_dma] -set_property -dict [list CONFIG.C_DMA_2D_TRANSFER {0}] [get_bd_cells axi_ad9122_dma] -set_property -dict [list CONFIG.C_CYCLIC {1}] [get_bd_cells axi_ad9122_dma] -set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {128}] [get_bd_cells axi_ad9122_dma] -set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {128}] [get_bd_cells axi_ad9122_dma] +set axi_ad9122_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9122_dma] +set_property -dict [list CONFIG.DMA_TYPE_SRC {0}] $axi_ad9122_dma +set_property -dict [list CONFIG.DMA_TYPE_DEST {2}] $axi_ad9122_dma +set_property -dict [list CONFIG.ID {0}] $axi_ad9122_dma +set_property -dict [list CONFIG.AXI_SLICE_SRC {0}] $axi_ad9122_dma +set_property -dict [list CONFIG.AXI_SLICE_DEST {0}] $axi_ad9122_dma +set_property -dict [list CONFIG.DMA_LENGTH_WIDTH {24}] $axi_ad9122_dma +set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9122_dma +set_property -dict [list CONFIG.CYCLIC {1}] $axi_ad9122_dma +set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {128}] $axi_ad9122_dma + +set util_upack_ad9122 [create_bd_cell -type ip -vlnv analog.com:user:util_upack:1.0 util_upack_ad9122] +set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {64}] $util_upack_ad9122 +set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $util_upack_ad9122 # adc peripherals -set axi_ad9250_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9250:1.0 axi_ad9250_core] +set axi_ad9684_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9684:1.0 axi_ad9684_core] +set_property -dict [list CONFIG.OR_STATUS {0}] $axi_ad9684_core -set axi_ad9250_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.2 axi_ad9250_jesd] -set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9250_jesd -set_property -dict [list CONFIG.C_LANES {2}] $axi_ad9250_jesd +set axi_ad9684_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9684_dma] +set_property -dict [list CONFIG.DMA_TYPE_SRC {1}] $axi_ad9684_dma +set_property -dict [list CONFIG.DMA_TYPE_DEST {0}] $axi_ad9684_dma +set_property -dict [list CONFIG.ID {1}] $axi_ad9684_dma +set_property -dict [list CONFIG.AXI_SLICE_SRC {0}] $axi_ad9684_dma +set_property -dict [list CONFIG.AXI_SLICE_DEST {0}] $axi_ad9684_dma +set_property -dict [list CONFIG.DMA_LENGTH_WIDTH {24}] $axi_ad9684_dma +set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9684_dma +set_property -dict [list CONFIG.FIFO_SIZE {16}] $axi_ad9684_dma +set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad9684_dma -set axi_ad9250_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9250_dma] -set_property -dict [list CONFIG.C_DMA_TYPE_SRC {2}] $axi_ad9250_dma -set_property -dict [list CONFIG.C_DMA_TYPE_DEST {0}] $axi_ad9250_dma -set_property -dict [list CONFIG.ID {0}] $axi_ad9250_dma -set_property -dict [list CONFIG.C_AXI_SLICE_SRC {0}] $axi_ad9250_dma -set_property -dict [list CONFIG.C_AXI_SLICE_DEST {0}] $axi_ad9250_dma -set_property -dict [list CONFIG.C_SYNC_TRANSFER_START {1}] $axi_ad9250_dma -set_property -dict [list CONFIG.C_DMA_LENGTH_WIDTH {24}] $axi_ad9250_dma -set_property -dict [list CONFIG.C_DMA_2D_TRANSFER {0}] $axi_ad9250_dma -set_property -dict [list CONFIG.C_CYCLIC {0}] $axi_ad9250_dma -set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {64}] $axi_ad9250_dma -set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $axi_ad9250_dma - -# dac/adc common gt/gpio - -set axi_daq1_gt [create_bd_cell -type ip -vlnv analog.com:user:axi_jesd_gt:1.0 axi_daq1_gt] -set_property -dict [list CONFIG.PCORE_NUM_OF_RX_LANES {2}] $axi_daq1_gt -set_property -dict [list CONFIG.PCORE_NUM_OF_TX_LANES {2}] $axi_daq1_gt -set_property -dict [list CONFIG.PCORE_CPLL_FBDIV {2}] $axi_daq1_gt -set_property -dict [list CONFIG.PCORE_RX_OUT_DIV {1}] $axi_daq1_gt -set_property -dict [list CONFIG.PCORE_TX_OUT_DIV {1}] $axi_daq1_gt -set_property -dict [list CONFIG.PCORE_RX_CLK25_DIV {10}] $axi_daq1_gt -set_property -dict [list CONFIG.PCORE_TX_CLK25_DIV {10}] $axi_daq1_gt -set_property -dict [list CONFIG.PCORE_PMA_RSV {0x00018480}] $axi_daq1_gt -set_property -dict [list CONFIG.PCORE_RX_CDR_CFG {0x03000023ff20400020}] $axi_daq1_gt - -# additions to default configuration - -set_property -dict [list CONFIG.PCW_USE_S_AXI_HP1 {1}] $sys_ps7 -set_property -dict [list CONFIG.PCW_USE_S_AXI_HP2 {1}] $sys_ps7 -set_property -dict [list CONFIG.PCW_USE_S_AXI_HP3 {1}] $sys_ps7 -set_property -dict [list CONFIG.PCW_EN_CLK2_PORT {1}] $sys_ps7 -set_property -dict [list CONFIG.PCW_EN_RST2_PORT {1}] $sys_ps7 -set_property -dict [list CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {200.0}] $sys_ps7 - -# connections (gt) - -ad_connect rx_ref_clk axi_daq1_gt/ref_clk_c -ad_connect rx_data_p axi_daq1_gt/rx_data_p -ad_connect rx_data_n axi_daq1_gt/rx_data_n -ad_connect rx_sync axi_daq1_gt/rx_sync -ad_connect rx_sysref axi_daq1_gt/rx_ext_sysref - -ad_connect axi_daq1_gt/tx_clk axi_daq1_gt/tx_clk_g - -# connections (adc) - -ad_connect axi_daq1_gt/rx_clk_g axi_daq1_gt/rx_clk -ad_connect axi_daq1_gt/rx_clk_g axi_ad9250_core/rx_clk -ad_connect axi_daq1_gt/rx_clk_g axi_ad9250_jesd/rx_core_clk - -set util_bsplit_rx_gt_charisk [create_bd_cell -type ip -vlnv analog.com:user:util_bsplit:1.0 util_bsplit_rx_gt_charisk] -set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {4}] [get_bd_cells util_bsplit_rx_gt_charisk] -set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] [get_bd_cells util_bsplit_rx_gt_charisk] -ad_connect util_bsplit_rx_gt_charisk/data axi_daq1_gt/rx_gt_charisk -ad_connect util_bsplit_rx_gt_charisk/split_data_0 axi_ad9250_jesd/gt0_rxcharisk -ad_connect util_bsplit_rx_gt_charisk/split_data_1 axi_ad9250_jesd/gt1_rxcharisk - -set util_bsplit_gt_rxdisperr [create_bd_cell -type ip -vlnv analog.com:user:util_bsplit:1.0 util_bsplit_gt_rxdisperr] -set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {4}] [get_bd_cells util_bsplit_gt_rxdisperr] -set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] [get_bd_cells util_bsplit_gt_rxdisperr] -ad_connect util_bsplit_gt_rxdisperr/data axi_daq1_gt/rx_gt_disperr -ad_connect util_bsplit_gt_rxdisperr/split_data_0 axi_ad9250_jesd/gt0_rxdisperr -ad_connect util_bsplit_gt_rxdisperr/split_data_1 axi_ad9250_jesd/gt1_rxdisperr - -set util_bsplit_rx_gt_notintable [create_bd_cell -type ip -vlnv analog.com:user:util_bsplit:1.0 util_bsplit_rx_gt_notintable] -set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {4}] [get_bd_cells util_bsplit_rx_gt_notintable] -set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] [get_bd_cells util_bsplit_rx_gt_notintable] -ad_connect util_bsplit_rx_gt_notintable/data axi_daq1_gt/rx_gt_notintable -ad_connect util_bsplit_rx_gt_notintable/split_data_0 axi_ad9250_jesd/gt0_rxnotintable -ad_connect util_bsplit_rx_gt_notintable/split_data_1 axi_ad9250_jesd/gt1_rxnotintable - -set util_bsplit_rx_gt_data [create_bd_cell -type ip -vlnv analog.com:user:util_bsplit:1.0 util_bsplit_rx_gt_data] -set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {32}] [get_bd_cells util_bsplit_rx_gt_data] -set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] [get_bd_cells util_bsplit_rx_gt_data] -ad_connect util_bsplit_rx_gt_data/data axi_daq1_gt/rx_gt_data -ad_connect util_bsplit_rx_gt_data/split_data_0 axi_ad9250_jesd/gt0_rxdata -ad_connect util_bsplit_rx_gt_data/split_data_1 axi_ad9250_jesd/gt1_rxdata - -ad_connect axi_daq1_gt/rx_jesd_rst axi_ad9250_jesd/rx_reset -ad_connect axi_daq1_gt/rx_sysref axi_ad9250_jesd/rx_sysref -ad_connect axi_daq1_gt/rx_rst_done axi_ad9250_jesd/rx_reset_done -ad_connect axi_daq1_gt/rx_ip_comma_align axi_ad9250_jesd/rxencommaalign_out -ad_connect axi_daq1_gt/rx_ip_sync axi_ad9250_jesd/rx_sync -ad_connect axi_daq1_gt/rx_ip_sof axi_ad9250_jesd/rx_start_of_frame -ad_connect axi_daq1_gt/rx_ip_data axi_ad9250_jesd/rx_tdata -ad_connect axi_daq1_gt/rx_data axi_ad9250_core/rx_data -ad_connect adc_clk axi_ad9250_core/adc_clk -ad_connect axi_ad9250_core/adc_clk axi_ad9250_dma/fifo_wr_clk -ad_connect adc_enable_a axi_ad9250_core/adc_enable_a -ad_connect adc_valid_a axi_ad9250_core/adc_valid_a -ad_connect adc_data_a axi_ad9250_core/adc_data_a -ad_connect adc_enable_b axi_ad9250_core/adc_enable_b -ad_connect adc_valid_b axi_ad9250_core/adc_valid_b -ad_connect adc_data_b axi_ad9250_core/adc_data_b -ad_connect axi_ad9250_core/adc_dovf axi_ad9250_dma/fifo_wr_overflow -ad_connect adc_dwr axi_ad9250_dma/fifo_wr_en -ad_connect adc_dsync axi_ad9250_dma/fifo_wr_sync -ad_connect adc_ddata axi_ad9250_dma/fifo_wr_din +set util_cpack_ad9684 [create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 util_cpack_ad9684] +set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {32}] $util_cpack_ad9684 +set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $util_cpack_ad9684 # connections (dac) -ad_connect tx_ref_clk_p axi_ad9122_core/dac_clk_in_p -ad_connect tx_ref_clk_n axi_ad9122_core/dac_clk_in_n -ad_connect tx_clk_p axi_ad9122_core/dac_clk_out_p -ad_connect tx_clk_n axi_ad9122_core/dac_clk_out_n -ad_connect tx_frame_p axi_ad9122_core/dac_frame_out_p -ad_connect tx_frame_n axi_ad9122_core/dac_frame_out_n -ad_connect tx_data_p axi_ad9122_core/dac_data_out_p -ad_connect tx_data_n axi_ad9122_core/dac_data_out_n -ad_connect dac_clk axi_ad9122_core/dac_div_clk -ad_connect axi_ad9122_core/dac_div_clk axi_ad9122_dma/fifo_rd_clk -ad_connect dac_valid_0 axi_ad9122_core/dac_valid_0 -ad_connect dac_enable_0 axi_ad9122_core/dac_enable_0 -ad_connect dac_ddata_0 axi_ad9122_core/dac_ddata_0 -ad_connect dac_valid_1 axi_ad9122_core/dac_valid_1 -ad_connect dac_enable_1 axi_ad9122_core/dac_enable_1 -ad_connect dac_ddata_1 axi_ad9122_core/dac_ddata_1 -ad_connect dac_drd axi_ad9122_dma/fifo_rd_en -ad_connect dac_ddata axi_ad9122_dma/fifo_rd_dout -ad_connect axi_ad9122_core/dac_dunf axi_ad9122_dma/fifo_rd_underflow +ad_connect dac_clk axi_ad9122_core/dac_div_clk +ad_connect dac_clk axi_ad9122_dma/fifo_rd_clk +ad_connect dac_clk util_upack_ad9122/dac_clk -ad_connect sys_cpu_resetn axi_ad9122_dma/m_src_axi_aresetn -ad_connect sys_cpu_resetn axi_ad9250_dma/m_dest_axi_aresetn +ad_connect dac_clk_in_p axi_ad9122_core/dac_clk_in_p +ad_connect dac_clk_in_n axi_ad9122_core/dac_clk_in_n +ad_connect dac_clk_out_p axi_ad9122_core/dac_clk_out_p +ad_connect dac_clk_out_n axi_ad9122_core/dac_clk_out_n +ad_connect dac_frame_out_p axi_ad9122_core/dac_frame_out_p +ad_connect dac_frame_out_n axi_ad9122_core/dac_frame_out_n +ad_connect dac_data_out_p axi_ad9122_core/dac_data_out_p +ad_connect dac_data_out_n axi_ad9122_core/dac_data_out_n + +ad_connect axi_ad9122_core/dac_enable_0 util_upack_ad9122/dac_enable_0 +ad_connect axi_ad9122_core/dac_ddata_0 util_upack_ad9122/dac_data_0 +ad_connect axi_ad9122_core/dac_valid_0 util_upack_ad9122/dac_valid_0 +ad_connect axi_ad9122_core/dac_enable_1 util_upack_ad9122/dac_enable_1 +ad_connect axi_ad9122_core/dac_ddata_1 util_upack_ad9122/dac_data_1 +ad_connect axi_ad9122_core/dac_valid_1 util_upack_ad9122/dac_valid_1 +ad_connect axi_ad9122_core/dac_dunf axi_ad9122_dma/fifo_rd_underflow + +ad_connect util_upack_ad9122/dac_valid axi_ad9122_dma/fifo_rd_en +ad_connect util_upack_ad9122/dac_data axi_ad9122_dma/fifo_rd_dout +ad_connect util_upack_ad9122/dac_sync axi_ad9122_core/dac_sync_in + +# connections (adc) + +ad_connect adc_clk axi_ad9684_core/adc_clk +ad_connect sys_200m_clk axi_ad9684_core/delay_clk +ad_connect sys_cpu_clk axi_ad9684_dma/s_axis_aclk +ad_connect adc_clk util_cpack_ad9684/adc_clk + +ad_connect adc_clk_in_p axi_ad9684_core/adc_clk_in_p +ad_connect adc_clk_in_n axi_ad9684_core/adc_clk_in_n +ad_connect axi_ad9684_core/adc_data_or_p GND +ad_connect axi_ad9684_core/adc_data_or_n GND +ad_connect adc_data_in_p axi_ad9684_core/adc_data_in_p +ad_connect adc_data_in_n axi_ad9684_core/adc_data_in_n + +ad_connect axi_ad9684_core/adc_rst util_cpack_ad9684/adc_rst +ad_connect axi_ad9684_core/adc_enable_0 util_cpack_ad9684/adc_enable_0 +ad_connect axi_ad9684_core/adc_valid_0 util_cpack_ad9684/adc_valid_0 +ad_connect axi_ad9684_core/adc_data_0 util_cpack_ad9684/adc_data_0 +ad_connect axi_ad9684_core/adc_enable_1 util_cpack_ad9684/adc_enable_1 +ad_connect axi_ad9684_core/adc_valid_1 util_cpack_ad9684/adc_valid_1 +ad_connect axi_ad9684_core/adc_data_1 util_cpack_ad9684/adc_data_1 +ad_connect axi_ad9684_core/adc_dovf axi_ad9684_fifo/adc_wovf + +ad_connect adc_clk axi_ad9684_fifo/adc_clk +ad_connect sys_cpu_clk axi_ad9684_fifo/dma_clk +ad_connect axi_ad9684_core/adc_rst axi_ad9684_fifo/adc_rst +ad_connect util_cpack_ad9684/adc_valid axi_ad9684_fifo/adc_wr +ad_connect util_cpack_ad9684/adc_data axi_ad9684_fifo/adc_wdata +ad_connect axi_ad9684_fifo/dma_wr axi_ad9684_dma/s_axis_valid +ad_connect axi_ad9684_fifo/dma_wdata axi_ad9684_dma/s_axis_data +ad_connect axi_ad9684_fifo/dma_wready axi_ad9684_dma/s_axis_ready +ad_connect axi_ad9684_fifo/dma_xfer_req axi_ad9684_dma/s_axis_xfer_req -# interconnect (cpu) - -ad_cpu_interconnect 0x44A60000 axi_daq1_gt -ad_cpu_interconnect 0x44A00000 axi_ad9122_core -ad_cpu_interconnect 0x7c400000 axi_ad9122_dma -ad_cpu_interconnect 0x44A10000 axi_ad9250_core -ad_cpu_interconnect 0x7c420000 axi_ad9250_dma -ad_cpu_interconnect 0x44A91000 axi_ad9250_jesd - -# memory interconnects +# memory interconnect +ad_cpu_interconnect 0x44A00000 axi_ad9122_core +ad_cpu_interconnect 0x44A20000 axi_ad9684_core +ad_cpu_interconnect 0x44A40000 axi_ad9122_dma +ad_cpu_interconnect 0x44A60000 axi_ad9684_dma ad_mem_hp1_interconnect sys_200m_clk sys_ps7/S_AXI_HP1 -ad_mem_hp1_interconnect sys_200m_clk axi_ad9122_dma/m_src_axi +ad_mem_hp1_interconnect sys_200m_clk axi_ad9684_dma/m_dest_axi ad_mem_hp2_interconnect sys_200m_clk sys_ps7/S_AXI_HP2 -ad_mem_hp2_interconnect sys_200m_clk axi_ad9250_dma/m_dest_axi -ad_mem_hp3_interconnect sys_cpu_clk sys_ps7/S_AXI_HP3 -ad_mem_hp3_interconnect sys_cpu_clk axi_daq1_gt/m_axi +ad_mem_hp2_interconnect sys_200m_clk axi_ad9122_dma/m_src_axi + +ad_connect sys_cpu_resetn axi_ad9684_dma/m_dest_axi_aresetn +ad_connect sys_cpu_resetn axi_ad9122_dma/m_src_axi_aresetn # interrupts -ad_cpu_interrupt ps-13 mb-12 axi_ad9250_dma/irq -ad_cpu_interrupt ps-12 mb-13 axi_ad9122_dma/irq - -# ila - -set ila_jesd_rx_mon [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:5.0 ila_jesd_rx_mon] -set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_jesd_rx_mon -set_property -dict [list CONFIG.C_NUM_OF_PROBES {7} ] $ila_jesd_rx_mon -set_property -dict [list CONFIG.C_PROBE0_WIDTH {64} ] $ila_jesd_rx_mon -set_property -dict [list CONFIG.C_PROBE1_WIDTH {1} ] $ila_jesd_rx_mon -set_property -dict [list CONFIG.C_PROBE2_WIDTH {1} ] $ila_jesd_rx_mon -set_property -dict [list CONFIG.C_PROBE3_WIDTH {32} ] $ila_jesd_rx_mon -set_property -dict [list CONFIG.C_PROBE4_WIDTH {1} ] $ila_jesd_rx_mon -set_property -dict [list CONFIG.C_PROBE5_WIDTH {1} ] $ila_jesd_rx_mon -set_property -dict [list CONFIG.C_PROBE6_WIDTH {32} ] $ila_jesd_rx_mon - -ad_connect axi_daq1_gt/rx_clk_g ila_jesd_rx_mon/CLK -ad_connect axi_daq1_gt/rx_data ila_jesd_rx_mon/PROBE0 -ad_connect axi_ad9250_core/adc_valid_a ila_jesd_rx_mon/PROBE1 -ad_connect axi_ad9250_core/adc_enable_a ila_jesd_rx_mon/PROBE2 -ad_connect axi_ad9250_core/adc_data_a ila_jesd_rx_mon/PROBE3 -ad_connect axi_ad9250_core/adc_valid_b ila_jesd_rx_mon/PROBE4 -ad_connect axi_ad9250_core/adc_enable_a ila_jesd_rx_mon/PROBE5 -ad_connect axi_ad9250_core/adc_data_a ila_jesd_rx_mon/PROBE6 +ad_cpu_interrupt ps-11 mb-11 spi_int +ad_cpu_interrupt ps-12 mb-12 axi_ad9122_dma/irq +ad_cpu_interrupt ps-13 mb-13 axi_ad9684_dma/irq diff --git a/projects/daq1/common/daq1_qsys.tcl b/projects/daq1/common/daq1_qsys.tcl new file mode 100644 index 000000000..c23a6a97a --- /dev/null +++ b/projects/daq1/common/daq1_qsys.tcl @@ -0,0 +1,139 @@ + +# DAQ1 + +# DAC core + +add_instance axi_ad9122 axi_ad9122 1.0 +set_instance_parameter_value axi_ad9122 {ID} {0} + +add_connection sys_clk.clk_reset axi_ad9122.s_axi_reset +add_connection sys_clk.clk axi_ad9122.s_axi_clock +add_connection sys_cpu.data_master axi_ad9122.s_axi + +# DAC unpack + +add_instance util_ad9122_upack util_upack 1.0 +set_instance_parameter_value util_ad9122_upack {CHANNEL_DATA_WIDTH} {64} +set_instance_parameter_value util_ad9122_upack {NUM_OF_CHANNELS} {2} + +# DAC DMA + +add_instance axi_ad9122_dma axi_dmac 1.0 +set_instance_parameter_value axi_ad9122_dma {DMA_DATA_WIDTH_DEST} {128} +set_instance_parameter_value axi_ad9122_dma {DMA_2D_TRANSFER} {0} +set_instance_parameter_value axi_ad9122_dma {DMA_TYPE_DEST} {2} +set_instance_parameter_value axi_ad9122_dma {DMA_TYPE_SRC} {0} +set_instance_parameter_value axi_ad9122_dma {CYCLIC} {1} +set_instance_parameter_value axi_ad9122_dma {SYNC_TRANSFER_START} {0} +set_instance_parameter_value axi_ad9122_dma {AXI_SLICE_SRC} {0} +set_instance_parameter_value axi_ad9122_dma {AXI_SLICE_DEST} {0} +set_instance_parameter_value axi_ad9122_dma {DMA_LENGTH_WIDTH} {24} + +add_connection sys_clk.clk_reset axi_ad9122_dma.s_axi_reset +add_connection sys_clk.clk axi_ad9122_dma.s_axi_clock +add_connection sys_cpu.data_master axi_ad9122_dma.s_axi +add_connection sys_ddr3_cntrl.emif_usr_reset_n axi_ad9122_dma.m_src_axi_reset +add_connection sys_ddr3_cntrl.emif_usr_clk axi_ad9122_dma.m_src_axi_clock +add_connection axi_ad9122_dma.m_src_axi sys_ddr3_cntrl.ctrl_amm_0 +add_connection sys_cpu.irq axi_ad9122_dma.interrupt_sender +add_connection sys_clk.clk axi_ad9122_dma.if_fifo_rd_clk + +# DAC path + +add_connection axi_ad9122.if_dac_div_clk util_ad9122_upack.if_dac_clk +add_connection util_ad9122_upack.if_dac_valid axi_ad9122_dma.if_fifo_rd_en +add_connection util_ad9122_upack.if_dac_data axi_ad9122_dma.if_fifo_rd_dout +add_connection axi_ad9122_dma.if_fifo_rd_underflow axi_ad9122.if_dac_dunf +add_connection util_ad9122_upack.dac_ch_0 axi_ad9122.dac_ch_0 +add_connection util_ad9122_upack.dac_ch_1 axi_ad9122.dac_ch_1 + +# ADC core + +add_instance axi_ad9684 axi_ad9684 1.0 +set_instance_parameter_value axi_ad9684 {OR_STATUS} {0} + +add_connection sys_clk.clk_reset axi_ad9684.s_axi_reset +add_connection sys_clk.clk axi_ad9684.s_axi_clock +add_connection sys_cpu.data_master axi_ad9684.s_axi + +# ADC pack + +add_instance util_ad9684_cpack util_cpack 1.0 +set_instance_parameter_value util_ad9684_cpack {CHANNEL_DATA_WIDTH} {32} +set_instance_parameter_value util_ad9684_cpack {NUM_OF_CHANNELS} {2} + +add_connection sys_clk.clk_reset util_ad9684_cpack.if_adc_rst +add_connection sys_ddr3_cntrl.emif_usr_reset_n util_ad9684_cpack.if_adc_rst +add_connection axi_ad9684.if_adc_clk util_ad9684_cpack.if_adc_clk +add_connection util_ad9684_cpack.adc_ch_0 axi_ad9684.adc_ch_0 +add_connection util_ad9684_cpack.adc_ch_1 axi_ad9684.adc_ch_1 + +# ADC FIFO + +add_instance ad9684_adcfifo util_adcfifo 1.0 +set_instance_parameter_value ad9684_adcfifo {ADC_DATA_WIDTH} {64} +set_instance_parameter_value ad9684_adcfifo {DMA_DATA_WIDTH} {64} +set_instance_parameter_value ad9684_adcfifo {DMA_ADDRESS_WIDTH} {16} + +add_connection sys_clk.clk_reset ad9684_adcfifo.if_adc_rst +add_connection sys_ddr3_cntrl.emif_usr_reset_n ad9684_adcfifo.if_adc_rst +add_connection axi_ad9684.if_adc_clk ad9684_adcfifo.if_adc_clk +add_connection util_ad9684_cpack.if_adc_valid ad9684_adcfifo.if_adc_wr +add_connection util_ad9684_cpack.if_adc_data ad9684_adcfifo.if_adc_wdata +add_connection sys_ddr3_cntrl.emif_usr_clk ad9684_adcfifo.if_dma_clk + +# ADC DMA + +add_instance axi_ad9684_dma axi_dmac 1.0 +set_instance_parameter_value axi_ad9684_dma {DMA_TYPE_SRC} {1} +set_instance_parameter_value axi_ad9684_dma {DMA_TYPE_DEST} {0} +set_instance_parameter_value axi_ad9684_dma {ID} {1} +set_instance_parameter_value axi_ad9684_dma {AXI_SLICE_SRC} {0} +set_instance_parameter_value axi_ad9684_dma {AXI_SLICE_DEST} {0} +set_instance_parameter_value axi_ad9684_dma {DMA_LENGTH_WIDTH} {24} +set_instance_parameter_value axi_ad9684_dma {DMA_2D_TRANSFER} {0} +set_instance_parameter_value axi_ad9684_dma {FIFO_SIZE} {16} +set_instance_parameter_value axi_ad9684_dma {CYCLIC} {0} + +add_connection sys_ddr3_cntrl.emif_usr_clk axi_ad9684_dma.if_s_axis_aclk +add_connection ad9684_adcfifo.if_dma_wr axi_ad9684_dma.if_s_axis_valid +add_connection ad9684_adcfifo.if_dma_wdata axi_ad9684_dma.if_s_axis_data +add_connection ad9684_adcfifo.if_dma_wready axi_ad9684_dma.if_s_axis_ready +add_connection ad9684_adcfifo.if_dma_xfer_req axi_ad9684_dma.if_s_axis_xfer_req +add_connection sys_clk.clk_reset axi_ad9684_dma.s_axi_reset +add_connection sys_clk.clk axi_ad9684_dma.s_axi_clock +add_connection sys_cpu.data_master axi_ad9684_dma.s_axi +add_connection sys_ddr3_cntrl.emif_usr_reset_n axi_ad9684_dma.m_dest_axi_reset +add_connection sys_ddr3_cntrl.emif_usr_clk axi_ad9684_dma.m_dest_axi_clock +add_connection axi_ad9684_dma.m_dest_axi sys_ddr3_cntrl.ctrl_amm_0 +add_connection sys_cpu.irq axi_ad9684_dma.interrupt_sender + +# setting interface property + +set_interface_property axi_ad9122_device_if EXPORT_OF axi_ad9122.device_if +set_interface_property axi_ad9684_device_if EXPORT_OF axi_ad9684.device_if + +# IRQ bridge for the CPLD IRQ signal + +add_instance irq_bridge altera_irq_bridge 16.0 +set_instance_parameter_value irq_bridge {IRQ_WIDTH} {1} + +add_connection sys_clk.clk_reset irq_bridge.clk_reset +add_connection sys_clk.clk irq_bridge.clk +add_connection sys_cpu.irq irq_bridge.sender0_irq + +set_interface_property spi_int EXPORT_OF irq_bridge.receiver_irq + +# addresses + +set_connection_parameter_value sys_cpu.data_master/axi_ad9122.s_axi baseAddress {0x44A00000} +set_connection_parameter_value sys_cpu.data_master/axi_ad9684.s_axi baseAddress {0x44A20000} +set_connection_parameter_value sys_cpu.data_master/axi_ad9122_dma.s_axi baseAddress {0x44A40000} +set_connection_parameter_value sys_cpu.data_master/axi_ad9684_dma.s_axi baseAddress {0x44A60000} + +# interrupts + +set_connection_parameter_value sys_cpu.irq/irq_bridge.sender0_irq irqNumber {9} +set_connection_parameter_value sys_cpu.irq/axi_ad9122_dma.interrupt_sender irqNumber {10} +set_connection_parameter_value sys_cpu.irq/axi_ad9684_dma.interrupt_sender irqNumber {11} + diff --git a/projects/daq1/common/daq1_spi.v b/projects/daq1/common/daq1_spi.v index 16c953374..449329bbd 100644 --- a/projects/daq1/common/daq1_spi.v +++ b/projects/daq1/common/daq1_spi.v @@ -1,9 +1,9 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2011(c) Analog Devices, Inc. -// +// Copyright 2016(c) Analog Devices, Inc. +// // All rights reserved. -// +// // Redistribution and use in source and binary forms, with or without modification, // are permitted provided that the following conditions are met: // - Redistributions of source code must retain the above copyright @@ -21,16 +21,16 @@ // patent holders to use this software. // - Use of the software either in source or binary form, must be run // on or directly connected to an Analog Devices Inc. component. -// +// // THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, // INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A // PARTICULAR PURPOSE ARE DISCLAIMED. // // IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, // EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY -// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR // BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // *************************************************************************** // *************************************************************************** @@ -48,7 +48,7 @@ module daq1_spi ( // 4 wire - input [ 2:0] spi_csn; + input spi_csn; input spi_clk; input spi_mosi; output spi_miso; @@ -57,53 +57,61 @@ module daq1_spi ( inout spi_sdio; + // device address + + localparam [ 7:0] SPI_SEL_AD9684 = 8'h80; + localparam [ 7:0] SPI_SEL_AD9122 = 8'h81; + localparam [ 7:0] SPI_SEL_AD9523 = 8'h82; + localparam [ 7:0] SPI_SEL_CPLD = 8'h83; + // internal registers - reg [ 5:0] spi_count = 'd0; - reg spi_rd_wr_n = 'd0; - reg spi_enable = 'd0; + reg [ 5:0] spi_count = 6'b0; + reg spi_rd_wr_n = 1'b0; + reg spi_enable = 1'b0; + reg [ 7:0] spi_device_addr = 8'b0; // internal signals - wire spi_csn_s; wire spi_enable_s; // check on rising edge and change on falling edge - assign spi_csn_s = & spi_csn; - assign spi_enable_s = spi_enable & ~spi_csn_s; + assign spi_enable_s = spi_enable & ~spi_csn; - always @(posedge spi_clk or posedge spi_csn_s) begin - if (spi_csn_s == 1'b1) begin - spi_count <= 6'd0; - spi_rd_wr_n <= 1'd0; + always @(posedge spi_clk or posedge spi_csn) begin + if (spi_csn == 1'b1) begin + spi_count <= 6'b0000000; + spi_rd_wr_n <= 1'b0; + spi_device_addr <= 8'b00000000; end else begin spi_count <= (spi_count < 6'h3f) ? spi_count + 1'b1 : spi_count; - if (spi_count == 6'd0) begin + if (spi_count <= 6'd7) begin + spi_device_addr <= {spi_device_addr[6:0], spi_mosi}; + end + if (spi_count == 6'd8) begin spi_rd_wr_n <= spi_mosi; end end end - always @(negedge spi_clk or posedge spi_csn_s) begin - if (spi_csn_s == 1'b1) begin + always @(negedge spi_clk or posedge spi_csn) begin + if (spi_csn == 1'b1) begin spi_enable <= 1'b0; end else begin - if (((spi_count == 6'd16) && (spi_csn[2] == 1'b0)) || - ((spi_count == 6'd8) && (spi_csn[1] == 1'b0)) || - ((spi_count == 6'd16) && (spi_csn[0] == 1'b0))) begin + if (((spi_device_addr == SPI_SEL_AD9684) && (spi_count == 6'd24)) || + ((spi_device_addr == SPI_SEL_AD9122) && (spi_count == 6'd16)) || + ((spi_device_addr == SPI_SEL_AD9523) && (spi_count == 6'd24)) || + ((spi_device_addr == SPI_SEL_CPLD) && (spi_count == 6'd16))) begin spi_enable <= spi_rd_wr_n; end end end - // io butter + // io logic - IOBUF i_iobuf_sdio ( - .T (spi_enable_s), - .I (spi_mosi), - .O (spi_miso), - .IO (spi_sdio)); + assign spi_miso = spi_sdio; + assign spi_sdio = (spi_enable_s == 1'b1) ? 1'bz : spi_mosi; endmodule diff --git a/projects/daq1/cpld/daq1_cpld.ucf b/projects/daq1/cpld/daq1_cpld.ucf new file mode 100644 index 000000000..67a31e5d4 --- /dev/null +++ b/projects/daq1/cpld/daq1_cpld.ucf @@ -0,0 +1,30 @@ +#PACE: Start of Constraints generated by PACE + +#PACE: Start of PACE I/O Pin Assignments +NET "adc_fda" LOC = "P6" | IOSTANDARD = LVCMOS33 ; +NET "adc_fdb" LOC = "P7" | IOSTANDARD = LVCMOS33 ; +NET "adc_pwdn_stby" LOC = "P10" | IOSTANDARD = LVCMOS33 ; +NET "adc_spicsn" LOC = "P13" | IOSTANDARD = LVCMOS33 ; +NET "adc_status_n" LOC = "P9" | IOSTANDARD = LVCMOS33 ; +NET "adc_status_p" LOC = "P8" | IOSTANDARD = LVCMOS33 ; +NET "clk_pwdnn" LOC = "P20" | IOSTANDARD = LVCMOS33 ; +NET "clk_resetn" LOC = "P25" | IOSTANDARD = LVCMOS33 ; +NET "clk_spicsn" LOC = "P15" | IOSTANDARD = LVCMOS33 ; +NET "clk_status1" LOC = "P17" | IOSTANDARD = LVCMOS33 ; +NET "clk_status2" LOC = "P18" | IOSTANDARD = LVCMOS33 ; +NET "clk_syncn" LOC = "P24" | IOSTANDARD = LVCMOS33 ; +NET "dac_irqn" LOC = "P26" | IOSTANDARD = LVCMOS33 ; +NET "dac_resetn" LOC = "P27" | IOSTANDARD = LVCMOS33 ; +NET "dac_spicsn" LOC = "P14" | IOSTANDARD = LVCMOS33 ; +NET "fmc_irq" LOC = "P2" | IOSTANDARD = LVCMOS25; +NET "fmc_spi_csn" LOC = "P5" | IOSTANDARD = LVCMOS25 ; +NET "fmc_spi_sclk" LOC = "P4" | IOSTANDARD = LVCMOS25 ; +NET "fmc_spi_sdio" LOC = "P1" | IOSTANDARD = LVCMOS25 ; +NET "sclk" LOC = "P30" | IOSTANDARD = LVCMOS33 ; +NET "sdio" LOC = "P28" | IOSTANDARD = LVCMOS33 ; + +#PACE: Start of PACE Area Constraints + +#PACE: Start of PACE Prohibit Constraints + +#PACE: End of Constraints generated by PACE diff --git a/projects/daq1/cpld/daq1_cpld.v b/projects/daq1/cpld/daq1_cpld.v new file mode 100644 index 000000000..6671ae029 --- /dev/null +++ b/projects/daq1/cpld/daq1_cpld.v @@ -0,0 +1,289 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module daq1_cpld ( + + // FMC SPI interface + + fmc_spi_sclk, + fmc_spi_csn, + fmc_spi_sdio, + fmc_irq, + + // on board SPI interface + + adc_spicsn, + dac_spicsn, + clk_spicsn, + sclk, + sdio, + + // control and status lines + + adc_fda, + adc_fdb, + adc_status_p, + adc_status_n, + adc_pwdn_stby, + + dac_irqn, + dac_resetn, + + clk_status1, + clk_status2, + clk_pwdnn, + clk_syncn, + clk_resetn + +); + + input fmc_spi_csn; + input fmc_spi_sclk; + inout fmc_spi_sdio; + output fmc_irq; + + output adc_spicsn; + output dac_spicsn; + output clk_spicsn; + output sclk; + inout sdio; + + // control and status lines + + input adc_fda; + input adc_fdb; + input adc_status_p; + input adc_status_n; + output adc_pwdn_stby; + + input dac_irqn; + output dac_resetn; + + input clk_status1; + input clk_status2; + output clk_pwdnn; + output clk_syncn; + output clk_resetn; + + // FMC SPI Selects + + localparam [ 7:0] FMC_SPI_SEL_AD9684 = 8'h80; + localparam [ 7:0] FMC_SPI_SEL_AD9122 = 8'h81; + localparam [ 7:0] FMC_SPI_SEL_AD9523 = 8'h82; + localparam [ 7:0] FMC_SPI_SEL_CPLD = 8'h83; + + // CPLD Register Map Addresses + + localparam [ 6:0] CPLD_VERSION_ADDR = 7'h00; + localparam [ 6:0] ADC_CONTROL_ADDR = 7'h10; + localparam [ 6:0] DAC_CONTROL_ADDR = 7'h11; + localparam [ 6:0] CLK_CONTROL_ADDR = 7'h12; + localparam [ 6:0] IRQ_MASK_ADDR = 7'h13; + localparam [ 6:0] ADC_STATUS_ADDR = 7'h20; + localparam [ 6:0] DAC_STATUS_ADDR = 7'h21; + localparam [ 6:0] CLK_STATUS_ADDR = 7'h22; + + localparam [ 7:0] CPLD_VERSION = 8'h11; + + // Internal Registers/Signals + + reg [ 7:0] fmc_spi_dev_sel = 8'b0; + reg [ 7:0] fmc_cpld_addr = 8'b0; + reg [ 5:0] fmc_spi_counter = 6'b0; + reg fmc_spi_csn_enb = 1'b1; + + reg [ 7:0] adc_control = 8'b0; + reg [ 7:0] dac_control = 8'b0; + reg [ 7:0] clk_control = 8'b0; + + reg [ 7:0] adc_status = 8'b0; + reg [ 7:0] dac_status = 8'b0; + reg [ 7:0] clk_status = 8'b0; + + reg cpld_to_fpga = 1'b0; + reg [ 7:0] cpld_rdata = 8'b0; + reg cpld_rdata_bit = 1'b0; + reg [ 2:0] cpld_rdata_index = 3'h0; + reg [ 7:0] cpld_wdata = 8'b0; + reg [ 7:0] cpld_irq_mask = 8'b0; + reg [ 7:0] cpld_irq = 8'b0; + + wire rdnwr; + wire cpld_rdata_s; + + // SCLK counter for control signals + + always @(posedge fmc_spi_sclk or posedge fmc_spi_csn) begin + if (fmc_spi_csn == 1'b1) begin + fmc_spi_dev_sel <= 8'h0; + fmc_cpld_addr <= 8'h0; + end else begin + if (fmc_spi_counter <= 7) begin + fmc_spi_dev_sel <= {fmc_spi_dev_sel[6:0], fmc_spi_sdio}; + end + if (fmc_spi_counter <= 15) begin + fmc_cpld_addr <= {fmc_cpld_addr[6:0], fmc_spi_sdio}; + end + end + end + + // chip select control + + assign adc_spicsn = (fmc_spi_dev_sel == FMC_SPI_SEL_AD9684) ? (fmc_spi_csn | fmc_spi_csn_enb) : 1'b1; + assign dac_spicsn = (fmc_spi_dev_sel == FMC_SPI_SEL_AD9122) ? (fmc_spi_csn | fmc_spi_csn_enb) : 1'b1; + assign clk_spicsn = (fmc_spi_dev_sel == FMC_SPI_SEL_AD9523) ? (fmc_spi_csn | fmc_spi_csn_enb) : 1'b1; + assign cpld_spicsn = (fmc_spi_dev_sel == FMC_SPI_SEL_CPLD) ? (fmc_spi_csn | fmc_spi_csn_enb) : 1'b1; + + // SPI control and data + + assign sdio = cpld_to_fpga ? 1'bZ : fmc_spi_sdio; + assign fmc_spi_sdio = cpld_to_fpga ? cpld_rdata_s : 1'bZ ; + assign cpld_rdata_s = cpld_spicsn ? sdio : cpld_rdata_bit; + assign rdnwr = fmc_cpld_addr[7]; + + assign sclk = (~(fmc_spi_csn | fmc_spi_csn_enb)) ? fmc_spi_sclk : 1'b0; + + always @(negedge fmc_spi_sclk or posedge fmc_spi_csn) begin + if (fmc_spi_csn == 1'b1) begin + fmc_spi_counter <= 6'h0; + cpld_to_fpga <= 1'b0; + fmc_spi_csn_enb <= 1'b1; + end else begin + fmc_spi_counter <= (fmc_spi_counter <= 6'h3F) ? fmc_spi_counter + 1 : fmc_spi_counter; + fmc_spi_csn_enb <= (fmc_spi_counter < 7) ? 1'b1 : 1'b0; + if (adc_spicsn & clk_spicsn) begin + cpld_to_fpga <= (fmc_spi_counter >= 15) ? rdnwr : 1'b0; + end else begin + cpld_to_fpga <= (fmc_spi_counter >= 23) ? rdnwr : 1'b0; + end + end + end + + // Internal register read access + + always @(fmc_cpld_addr) begin + case (fmc_cpld_addr[6:0]) + CPLD_VERSION_ADDR : + cpld_rdata <= CPLD_VERSION; + ADC_CONTROL_ADDR : + cpld_rdata <= adc_pwdn_stby; + DAC_CONTROL_ADDR : + cpld_rdata <= dac_resetn; + CLK_CONTROL_ADDR : + cpld_rdata <= {clk_syncn, clk_resetn, clk_pwdnn}; + IRQ_MASK_ADDR: + cpld_rdata <= cpld_irq_mask; + ADC_STATUS_ADDR : + cpld_rdata <= {adc_status_p, adc_fdb, adc_fda}; + DAC_STATUS_ADDR : + cpld_rdata <= dac_irqn; + CLK_STATUS_ADDR : + cpld_rdata <= {clk_status2, clk_status1}; + default: + cpld_rdata <= 8'hFA; + endcase + end + + always @(negedge fmc_spi_sclk or posedge fmc_spi_csn) begin + if (fmc_spi_csn == 1'b1) begin + cpld_rdata_bit <= cpld_rdata[7]; + cpld_rdata_index <= 3'h6; + end else begin + if (cpld_to_fpga == 1'b1) begin + cpld_rdata_bit <= cpld_rdata[cpld_rdata_index]; + cpld_rdata_index <= cpld_rdata_index - 1; + end + end + end + + // Internal register write access + + always @(cpld_to_fpga, cpld_spicsn, fmc_spi_counter) begin + if ((cpld_to_fpga == 1'b0) && + (cpld_spicsn == 1'b0) && + (fmc_spi_counter == 8'h18)) begin + case (fmc_cpld_addr[6:0]) + ADC_CONTROL_ADDR : + adc_control <= cpld_wdata; + DAC_CONTROL_ADDR : + dac_control <= cpld_wdata; + CLK_CONTROL_ADDR : + clk_control <= cpld_wdata; + IRQ_MASK_ADDR: + cpld_irq_mask <= cpld_wdata; + endcase + end + end + + always @(posedge fmc_spi_sclk or posedge fmc_spi_csn) begin + if (fmc_spi_csn == 1'b1) begin + cpld_wdata <= 8'h0; + end else begin + if (fmc_spi_counter >= 16) begin + cpld_wdata <= {cpld_wdata[6:0], fmc_spi_sdio}; + end + end + end + + // input/output logic + + // AD9648 + + assign adc_pwdn_stby = adc_control[0]; + + // AD9122 + + assign dac_resetn = dac_control[0]; + + // AD9523-1 + + assign clk_pwdnn = clk_control[0]; + assign clk_resetn = clk_control[1]; + assign clk_syncn = clk_control[2]; + + // interrupt logic + + always @(*) begin + cpld_irq <= {2'b00, dac_irqn, clk_status2, clk_status1, adc_status_p, adc_fdb, adc_fda}; + end + + assign fmc_irq = |(~cpld_irq_mask & cpld_irq); + +endmodule + diff --git a/projects/daq1/cpld/daq1_cpld.xise b/projects/daq1/cpld/daq1_cpld.xise new file mode 100644 index 000000000..883441fe6 --- /dev/null +++ b/projects/daq1/cpld/daq1_cpld.xise @@ -0,0 +1,241 @@ + + + +
+ + + + + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/projects/daq1/zc706/Makefile b/projects/daq1/zc706/Makefile index 8df754906..16bd8a371 100644 --- a/projects/daq1/zc706/Makefile +++ b/projects/daq1/zc706/Makefile @@ -14,17 +14,21 @@ M_DEPS += ../common/daq1_bd.tcl M_DEPS += ../../scripts/adi_project.tcl M_DEPS += ../../scripts/adi_env.tcl M_DEPS += ../../scripts/adi_board.tcl +M_DEPS += ../../common/zc706/zc706_system_plddr3_adcfifo.tcl +M_DEPS += ../../common/zc706/zc706_system_mig_constr.xdc +M_DEPS += ../../common/zc706/zc706_system_mig.prj M_DEPS += ../../common/zc706/zc706_system_constr.xdc M_DEPS += ../../common/zc706/zc706_system_bd.tcl -M_DEPS += ../../../library/common/ad_iobuf.v +M_DEPS += ../../../library/xilinx/common/ad_iobuf.v M_DEPS += ../../../library/axi_ad9122/axi_ad9122.xpr -M_DEPS += ../../../library/axi_ad9250/axi_ad9250.xpr +M_DEPS += ../../../library/axi_ad9684/axi_ad9684.xpr +M_DEPS += ../../../library/xilinx/axi_adcfifo/axi_adcfifo.xpr M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr -M_DEPS += ../../../library/axi_jesd_gt/axi_jesd_gt.xpr M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr -M_DEPS += ../../../library/util_bsplit/util_bsplit.xpr +M_DEPS += ../../../library/util_cpack/util_cpack.xpr +M_DEPS += ../../../library/util_upack/util_upack.xpr M_VIVADO := vivado -mode batch -source @@ -40,6 +44,7 @@ M_FLIST += *.sdk M_FLIST += *.hw M_FLIST += *.sim M_FLIST += .Xil +M_FLIST += *.ip_user_files @@ -53,29 +58,31 @@ clean: clean-all:clean make -C ../../../library/axi_ad9122 clean - make -C ../../../library/axi_ad9250 clean + make -C ../../../library/axi_ad9684 clean + make -C ../../../library/xilinx/axi_adcfifo clean make -C ../../../library/axi_clkgen clean make -C ../../../library/axi_dmac clean make -C ../../../library/axi_hdmi_tx clean - make -C ../../../library/axi_jesd_gt clean make -C ../../../library/axi_spdif_tx clean - make -C ../../../library/util_bsplit clean + make -C ../../../library/util_cpack clean + make -C ../../../library/util_upack clean daq1_zc706.sdk/system_top.hdf: $(M_DEPS) - rm -rf $(M_FLIST) + -rm -rf $(M_FLIST) $(M_VIVADO) system_project.tcl >> daq1_zc706_vivado.log 2>&1 lib: make -C ../../../library/axi_ad9122 - make -C ../../../library/axi_ad9250 + make -C ../../../library/axi_ad9684 + make -C ../../../library/xilinx/axi_adcfifo make -C ../../../library/axi_clkgen make -C ../../../library/axi_dmac make -C ../../../library/axi_hdmi_tx - make -C ../../../library/axi_jesd_gt make -C ../../../library/axi_spdif_tx - make -C ../../../library/util_bsplit + make -C ../../../library/util_cpack + make -C ../../../library/util_upack #################################################################################### #################################################################################### diff --git a/projects/daq1/zc706/system_bd.tcl b/projects/daq1/zc706/system_bd.tcl index 138650de3..5fa45b20a 100644 --- a/projects/daq1/zc706/system_bd.tcl +++ b/projects/daq1/zc706/system_bd.tcl @@ -1,4 +1,23 @@ source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl +source $ad_hdl_dir/projects/common/zc706/zc706_system_plddr3_adcfifo.tcl + +p_plddr3_adcfifo [current_bd_instance .] axi_ad9684_fifo 64 + +create_bd_port -dir I -type rst sys_rst +create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr3 +create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sys_clk + +set_property CONFIG.POLARITY ACTIVE_HIGH [get_bd_ports sys_rst] + +ad_connect sys_rst axi_ad9684_fifo/sys_rst +ad_connect sys_clk axi_ad9684_fifo/sys_clk +ad_connect ddr3 axi_ad9684_fifo/ddr3 + +create_bd_addr_seg -range 0x40000000 -offset 0x80000000 \ + [get_bd_addr_spaces axi_ad9684_fifo/axi_adcfifo/axi] \ + [get_bd_addr_segs axi_ad9684_fifo/axi_ddr_cntrl/memmap/memaddr] \ + SEG_axi_ddr_cntrl_memaddr + source ../common/daq1_bd.tcl diff --git a/projects/daq1/zc706/system_constr.xdc b/projects/daq1/zc706/system_constr.xdc index a4e66106a..6cdaa0e7f 100644 --- a/projects/daq1/zc706/system_constr.xdc +++ b/projects/daq1/zc706/system_constr.xdc @@ -1,77 +1,83 @@ # daq1 -set_property -dict {PACKAGE_PIN AF20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_ref_clk_p] ; ## G06 FMC_HPC_LA00_CC_P -set_property -dict {PACKAGE_PIN AG20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_ref_clk_n] ; ## G07 FMC_HPC_LA00_CC_N +set_property -dict {PACKAGE_PIN AC28 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports dac_clk_in_p] ; ## G02 FMC_LPC_CLK1_M2C_P +set_property -dict {PACKAGE_PIN AD28 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports dac_clk_in_n] ; ## G03 FMC_LPC_CLK1_M2C_N +set_property -dict {PACKAGE_PIN AF29 IOSTANDARD LVDS_25 } [get_ports dac_clk_out_p] ; ## G27 FMC_LPC_LA25_P +set_property -dict {PACKAGE_PIN AG29 IOSTANDARD LVDS_25 } [get_ports dac_clk_out_n] ; ## G28 FMC_LPC_LA25_N +set_property -dict {PACKAGE_PIN Y26 IOSTANDARD LVDS_25 } [get_ports dac_frame_out_p] ; ## H37 FMC_LPC_LA32_P +set_property -dict {PACKAGE_PIN Y27 IOSTANDARD LVDS_25 } [get_ports dac_frame_out_n] ; ## H38 FMC_LPC_LA32_N +set_property -dict {PACKAGE_PIN AB15 IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[0]] ; ## H19 FMC_LPC_LA15_P +set_property -dict {PACKAGE_PIN AB14 IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[0]] ; ## H20 FMC_LPC_LA15_N +set_property -dict {PACKAGE_PIN AG26 IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[1]] ; ## G21 FMC_LPC_LA20_P +set_property -dict {PACKAGE_PIN AG27 IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[1]] ; ## G22 FMC_LPC_LA20_N +set_property -dict {PACKAGE_PIN AH26 IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[2]] ; ## H22 FMC_LPC_LA19_P +set_property -dict {PACKAGE_PIN AH27 IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[2]] ; ## H23 FMC_LPC_LA19_N +set_property -dict {PACKAGE_PIN AB27 IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[3]] ; ## D20 FMC_LPC_LA17_CC_P +set_property -dict {PACKAGE_PIN AC27 IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[3]] ; ## D21 FMC_LPC_LA17_CC_N +set_property -dict {PACKAGE_PIN AJ26 IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[4]] ; ## D23 FMC_LPC_LA23_P +set_property -dict {PACKAGE_PIN AK26 IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[4]] ; ## D24 FMC_LPC_LA23_N +set_property -dict {PACKAGE_PIN AK27 IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[5]] ; ## G24 FMC_LPC_LA22_P +set_property -dict {PACKAGE_PIN AK28 IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[5]] ; ## G25 FMC_LPC_LA22_N +set_property -dict {PACKAGE_PIN AE27 IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[6]] ; ## C22 FMC_LPC_LA18_CC_P +set_property -dict {PACKAGE_PIN AF27 IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[6]] ; ## C23 FMC_LPC_LA18_CC_N +set_property -dict {PACKAGE_PIN AH28 IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[7]] ; ## H25 FMC_LPC_LA21_P +set_property -dict {PACKAGE_PIN AH29 IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[7]] ; ## H26 FMC_LPC_LA21_N +set_property -dict {PACKAGE_PIN AJ30 IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[8]] ; ## D26 FMC_LPC_LA26_P +set_property -dict {PACKAGE_PIN AK30 IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[8]] ; ## D27 FMC_LPC_LA26_N +set_property -dict {PACKAGE_PIN AF30 IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[9]] ; ## H28 FMC_LPC_LA24_P +set_property -dict {PACKAGE_PIN AG30 IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[9]] ; ## H29 FMC_LPC_LA24_N +set_property -dict {PACKAGE_PIN AJ28 IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[10]] ; ## C26 FMC_LPC_LA27_P +set_property -dict {PACKAGE_PIN AJ29 IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[10]] ; ## C27 FMC_LPC_LA27_N +set_property -dict {PACKAGE_PIN AE25 IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[11]] ; ## G30 FMC_LPC_LA29_P +set_property -dict {PACKAGE_PIN AF25 IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[11]] ; ## G31 FMC_LPC_LA29_N +set_property -dict {PACKAGE_PIN AD25 IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[12]] ; ## H31 FMC_LPC_LA28_P +set_property -dict {PACKAGE_PIN AE26 IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[12]] ; ## H32 FMC_LPC_LA28_N +set_property -dict {PACKAGE_PIN AC29 IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[13]] ; ## G33 FMC_LPC_LA31_P +set_property -dict {PACKAGE_PIN AD29 IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[13]] ; ## G34 FMC_LPC_LA31_N +set_property -dict {PACKAGE_PIN AB29 IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[14]] ; ## H34 FMC_LPC_LA30_P +set_property -dict {PACKAGE_PIN AB30 IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[14]] ; ## H35 FMC_LPC_LA30_N +set_property -dict {PACKAGE_PIN Y30 IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[15]] ; ## G36 FMC_LPC_LA33_P +set_property -dict {PACKAGE_PIN AA30 IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[15]] ; ## G37 FMC_LPC_LA33_N -set_property -dict {PACKAGE_PIN V23 IOSTANDARD LVDS_25} [get_ports tx_clk_p] ; ## D20 FMC_HPC_LA17_CC_P -set_property -dict {PACKAGE_PIN W24 IOSTANDARD LVDS_25} [get_ports tx_clk_n] ; ## D21 FMC_HPC_LA17_CC_N -set_property -dict {PACKAGE_PIN W25 IOSTANDARD LVDS_25} [get_ports tx_frame_p] ; ## C22 FMC_HPC_LA18_CC_P -set_property -dict {PACKAGE_PIN W26 IOSTANDARD LVDS_25} [get_ports tx_frame_n] ; ## C23 FMC_HPC_LA18_CC_N -set_property -dict {PACKAGE_PIN AJ20 IOSTANDARD LVDS_25} [get_ports tx_data_p[0]] ; ## H10 FMC_HPC_LA04_P -set_property -dict {PACKAGE_PIN AK20 IOSTANDARD LVDS_25} [get_ports tx_data_n[0]] ; ## H11 FMC_HPC_LA04_N -set_property -dict {PACKAGE_PIN AH23 IOSTANDARD LVDS_25} [get_ports tx_data_p[1]] ; ## D11 FMC_HPC_LA05_P -set_property -dict {PACKAGE_PIN AH24 IOSTANDARD LVDS_25} [get_ports tx_data_n[1]] ; ## D12 FMC_HPC_LA05_N -set_property -dict {PACKAGE_PIN AG22 IOSTANDARD LVDS_25} [get_ports tx_data_p[2]] ; ## C10 FMC_HPC_LA06_P -set_property -dict {PACKAGE_PIN AH22 IOSTANDARD LVDS_25} [get_ports tx_data_n[2]] ; ## C11 FMC_HPC_LA06_N -set_property -dict {PACKAGE_PIN AJ23 IOSTANDARD LVDS_25} [get_ports tx_data_p[3]] ; ## H13 FMC_HPC_LA07_P -set_property -dict {PACKAGE_PIN AJ24 IOSTANDARD LVDS_25} [get_ports tx_data_n[3]] ; ## H14 FMC_HPC_LA07_N -set_property -dict {PACKAGE_PIN AF19 IOSTANDARD LVDS_25} [get_ports tx_data_p[4]] ; ## G12 FMC_HPC_LA08_P -set_property -dict {PACKAGE_PIN AG19 IOSTANDARD LVDS_25} [get_ports tx_data_n[4]] ; ## G13 FMC_HPC_LA08_N -set_property -dict {PACKAGE_PIN AD21 IOSTANDARD LVDS_25} [get_ports tx_data_p[5]] ; ## D14 FMC_HPC_LA09_P -set_property -dict {PACKAGE_PIN AE21 IOSTANDARD LVDS_25} [get_ports tx_data_n[5]] ; ## D15 FMC_HPC_LA09_N -set_property -dict {PACKAGE_PIN AG24 IOSTANDARD LVDS_25} [get_ports tx_data_p[6]] ; ## C14 FMC_HPC_LA10_P -set_property -dict {PACKAGE_PIN AG25 IOSTANDARD LVDS_25} [get_ports tx_data_n[6]] ; ## C15 FMC_HPC_LA10_N -set_property -dict {PACKAGE_PIN AD23 IOSTANDARD LVDS_25} [get_ports tx_data_p[7]] ; ## H16 FMC_HPC_LA11_P -set_property -dict {PACKAGE_PIN AE23 IOSTANDARD LVDS_25} [get_ports tx_data_n[7]] ; ## H17 FMC_HPC_LA11_N -set_property -dict {PACKAGE_PIN AF23 IOSTANDARD LVDS_25} [get_ports tx_data_p[8]] ; ## G15 FMC_HPC_LA12_P -set_property -dict {PACKAGE_PIN AF24 IOSTANDARD LVDS_25} [get_ports tx_data_n[8]] ; ## G16 FMC_HPC_LA12_N -set_property -dict {PACKAGE_PIN AA22 IOSTANDARD LVDS_25} [get_ports tx_data_p[9]] ; ## D17 FMC_HPC_LA13_P -set_property -dict {PACKAGE_PIN AA23 IOSTANDARD LVDS_25} [get_ports tx_data_n[9]] ; ## D18 FMC_HPC_LA13_N -set_property -dict {PACKAGE_PIN AC24 IOSTANDARD LVDS_25} [get_ports tx_data_p[10]] ; ## C18 FMC_HPC_LA14_P -set_property -dict {PACKAGE_PIN AD24 IOSTANDARD LVDS_25} [get_ports tx_data_n[10]] ; ## C19 FMC_HPC_LA14_N -set_property -dict {PACKAGE_PIN Y22 IOSTANDARD LVDS_25} [get_ports tx_data_p[11]] ; ## H19 FMC_HPC_LA15_P -set_property -dict {PACKAGE_PIN Y23 IOSTANDARD LVDS_25} [get_ports tx_data_n[11]] ; ## H20 FMC_HPC_LA15_N -set_property -dict {PACKAGE_PIN AA24 IOSTANDARD LVDS_25} [get_ports tx_data_p[12]] ; ## G18 FMC_HPC_LA16_P -set_property -dict {PACKAGE_PIN AB24 IOSTANDARD LVDS_25} [get_ports tx_data_n[12]] ; ## G19 FMC_HPC_LA16_N -set_property -dict {PACKAGE_PIN AK17 IOSTANDARD LVDS_25} [get_ports tx_data_p[13]] ; ## H07 FMC_HPC_LA02_P -set_property -dict {PACKAGE_PIN AK18 IOSTANDARD LVDS_25} [get_ports tx_data_n[13]] ; ## H08 FMC_HPC_LA02_N -set_property -dict {PACKAGE_PIN AG21 IOSTANDARD LVDS_25} [get_ports tx_data_p[14]] ; ## D08 FMC_HPC_LA01_CC_P -set_property -dict {PACKAGE_PIN AH21 IOSTANDARD LVDS_25} [get_ports tx_data_n[14]] ; ## D09 FMC_HPC_LA01_CC_N -set_property -dict {PACKAGE_PIN AH19 IOSTANDARD LVDS_25} [get_ports tx_data_p[15]] ; ## G09 FMC_HPC_LA03_P -set_property -dict {PACKAGE_PIN AJ19 IOSTANDARD LVDS_25} [get_ports tx_data_n[15]] ; ## G10 FMC_HPC_LA03_N +set_property -dict {PACKAGE_PIN AE13 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_clk_in_p] ; ## G06 FMC_LPC_LA00_CC_P +set_property -dict {PACKAGE_PIN AF13 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_clk_in_n] ; ## G07 FMC_LPC_LA00_CC_N +set_property -dict {PACKAGE_PIN AC14 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[0]] ; ## C14 FMC_LPC_LA10_P +set_property -dict {PACKAGE_PIN AC13 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[0]] ; ## C15 FMC_LPC_LA10_N +set_property -dict {PACKAGE_PIN AF18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[1]] ; ## C18 FMC_LPC_LA14_P +set_property -dict {PACKAGE_PIN AF17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[1]] ; ## C19 FMC_LPC_LA14_N +set_property -dict {PACKAGE_PIN AH17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[2]] ; ## D17 FMC_LPC_LA13_P +set_property -dict {PACKAGE_PIN AH16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[2]] ; ## D18 FMC_LPC_LA13_N +set_property -dict {PACKAGE_PIN AJ16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[3]] ; ## H16 FMC_LPC_LA11_P +set_property -dict {PACKAGE_PIN AK16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[3]] ; ## H17 FMC_LPC_LA11_N +set_property -dict {PACKAGE_PIN AD16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[4]] ; ## G15 FMC_LPC_LA12_P +set_property -dict {PACKAGE_PIN AD15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[4]] ; ## G16 FMC_LPC_LA12_N +set_property -dict {PACKAGE_PIN AH14 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[5]] ; ## D14 FMC_LPC_LA09_P +set_property -dict {PACKAGE_PIN AH13 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[5]] ; ## D15 FMC_LPC_LA09_N +set_property -dict {PACKAGE_PIN AA15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[6]] ; ## H13 FMC_LPC_LA07_P +set_property -dict {PACKAGE_PIN AA14 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[6]] ; ## H14 FMC_LPC_LA07_N +set_property -dict {PACKAGE_PIN AD14 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[7]] ; ## G12 FMC_LPC_LA08_P +set_property -dict {PACKAGE_PIN AD13 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[7]] ; ## G13 FMC_LPC_LA08_N +set_property -dict {PACKAGE_PIN AE16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[8]] ; ## D11 FMC_LPC_LA05_P +set_property -dict {PACKAGE_PIN AE15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[8]] ; ## D12 FMC_LPC_LA05_N +set_property -dict {PACKAGE_PIN AJ15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[9]] ; ## H10 FMC_LPC_LA04_P +set_property -dict {PACKAGE_PIN AK15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[9]] ; ## H11 FMC_LPC_LA04_N +set_property -dict {PACKAGE_PIN AG12 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[10]] ; ## G09 FMC_LPC_LA03_P +set_property -dict {PACKAGE_PIN AH12 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[10]] ; ## G10 FMC_LPC_LA03_N +set_property -dict {PACKAGE_PIN AB12 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[11]] ; ## C10 FMC_LPC_LA06_P +set_property -dict {PACKAGE_PIN AC12 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[11]] ; ## C11 FMC_LPC_LA06_N +set_property -dict {PACKAGE_PIN AE12 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[12]] ; ## H07 FMC_LPC_LA02_P +set_property -dict {PACKAGE_PIN AF12 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[12]] ; ## H08 FMC_LPC_LA02_N +set_property -dict {PACKAGE_PIN AF15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[13]] ; ## D08 FMC_LPC_LA01_CC_P +set_property -dict {PACKAGE_PIN AG15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[13]] ; ## D09 FMC_LPC_LA01_CC_N -set_property -dict {PACKAGE_PIN AD10 } [get_ports rx_ref_clk_p] ; ## D04 FMC_HPC_GBTCLK0_M2C_P -set_property -dict {PACKAGE_PIN AD9 } [get_ports rx_ref_clk_n] ; ## D05 FMC_HPC_GBTCLK0_M2C_N -set_property -dict {PACKAGE_PIN AH10 } [get_ports rx_data_p[0]] ; ## C06 FMC_HPC_DP0_M2C_P -set_property -dict {PACKAGE_PIN AH9 } [get_ports rx_data_n[0]] ; ## C07 FMC_HPC_DP0_M2C_N -set_property -dict {PACKAGE_PIN AJ8 } [get_ports rx_data_p[1]] ; ## A02 FMC_HPC_DP1_M2C_P -set_property -dict {PACKAGE_PIN AJ7 } [get_ports rx_data_n[1]] ; ## A03 FMC_HPC_DP1_M2C_N -set_property -dict {PACKAGE_PIN T24 IOSTANDARD LVDS_25} [get_ports rx_sync_p] ; ## H22 FMC_HPC_LA19_P -set_property -dict {PACKAGE_PIN T25 IOSTANDARD LVDS_25} [get_ports rx_sync_n] ; ## H23 FMC_HPC_LA19_N -set_property -dict {PACKAGE_PIN W29 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_sysref_p] ; ## H25 FMC_HPC_LA21_P -set_property -dict {PACKAGE_PIN W30 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_sysref_n] ; ## H26 FMC_HPC_LA21_N - -set_property -dict {PACKAGE_PIN U29 IOSTANDARD LVCMOS25} [get_ports spi_csn_clk] ; ## G28 FMC_HPC_LA25_N -set_property -dict {PACKAGE_PIN T29 IOSTANDARD LVCMOS25} [get_ports spi_csn_dac] ; ## G27 FMC_HPC_LA25_P -set_property -dict {PACKAGE_PIN U30 IOSTANDARD LVCMOS25} [get_ports spi_csn_adc] ; ## H29 FMC_HPC_LA24_N -set_property -dict {PACKAGE_PIN P26 IOSTANDARD LVCMOS25} [get_ports spi_clk] ; ## D24 FMC_HPC_LA23_N -set_property -dict {PACKAGE_PIN P25 IOSTANDARD LVCMOS25} [get_ports spi_sdio] ; ## D23 FMC_HPC_LA23_P - -set_property -dict {PACKAGE_PIN W28 IOSTANDARD LVCMOS25} [get_ports gpio_resetn] ; ## G25 FMC_HPC_LA22_N -set_property -dict {PACKAGE_PIN R30 IOSTANDARD LVCMOS25} [get_ports gpio_clkd_syncn] ; ## H32 FMC_HPC_LA28_N -set_property -dict {PACKAGE_PIN P30 IOSTANDARD LVCMOS25} [get_ports gpio_clkd_pdn] ; ## H31 FMC_HPC_LA28_P - -set_property -dict {PACKAGE_PIN T28 IOSTANDARD LVCMOS25} [get_ports gpio_clkd_status[1]] ; ## D27 FMC_HPC_LA26_N -set_property -dict {PACKAGE_PIN R28 IOSTANDARD LVCMOS25} [get_ports gpio_clkd_status[0]] ; ## D26 FMC_HPC_LA26_P -set_property -dict {PACKAGE_PIN V27 IOSTANDARD LVCMOS25} [get_ports gpio_dac_irqn] ; ## G24 FMC_HPC_LA22_P -set_property -dict {PACKAGE_PIN V28 IOSTANDARD LVCMOS25} [get_ports gpio_adc_fda] ; ## C26 FMC_HPC_LA27_P -set_property -dict {PACKAGE_PIN V29 IOSTANDARD LVCMOS25} [get_ports gpio_adc_fdb] ; ## C27 FMC_HPC_LA27_N +set_property -dict {PACKAGE_PIN AG16 IOSTANDARD LVCMOS25} [get_ports spi_csn] ; ## H05 FMC_LPC_CLK0_M2C_N +set_property -dict {PACKAGE_PIN AG17 IOSTANDARD LVCMOS25} [get_ports spi_clk] ; ## H04 FMC_LPC_CLK0_M2C_P +set_property -dict {PACKAGE_PIN AE18 IOSTANDARD LVCMOS25} [get_ports spi_sdio] ; ## G18 FMC_LPC_LA16_P +set_property -dict {PACKAGE_PIN AE17 IOSTANDARD LVCMOS25} [get_ports spi_int] ; ## G19 FMC_LPC_LA16_N # clocks -create_clock -name tx_ref_clk -period 2.00 [get_ports tx_ref_clk_p] -create_clock -name rx_ref_clk -period 4.00 [get_ports rx_ref_clk_p] -create_clock -name tx_div_clk -period 8.00 [get_nets i_system_wrapper/system_i/axi_ad9122_dac_div_clk] -create_clock -name rx_div_clk -period 8.00 [get_nets i_system_wrapper/system_i/axi_daq1_gt_rx_clk] +create_clock -name dac_clk_in -period 2.00 [get_ports dac_clk_in_p] +create_clock -name adc_clk_in -period 2.00 [get_ports adc_clk_in_p] diff --git a/projects/daq1/zc706/system_project.tcl b/projects/daq1/zc706/system_project.tcl index 5fb216408..f38fb7b99 100644 --- a/projects/daq1/zc706/system_project.tcl +++ b/projects/daq1/zc706/system_project.tcl @@ -6,10 +6,14 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl adi_project_create daq1_zc706 adi_project_files daq1_zc706 [list \ "../common/daq1_spi.v" \ - "$ad_hdl_dir/library/common/ad_iobuf.v" \ - "system_top.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \ "system_constr.xdc"\ - "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ] + "$ad_hdl_dir/projects/common/zc706/zc706_system_mig_constr.xdc" \ + "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" \ + "system_top.v" ] + +set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc] +set_property PROCESSING_ORDER EARLY [get_files system_constr.xdc] adi_project_run daq1_zc706 diff --git a/projects/daq1/zc706/system_top.v b/projects/daq1/zc706/system_top.v index 08e1d63e8..2741a9b73 100644 --- a/projects/daq1/zc706/system_top.v +++ b/projects/daq1/zc706/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2011(c) Analog Devices, Inc. +// Copyright 2016(c) Analog Devices, Inc. // // All rights reserved. // @@ -34,8 +34,6 @@ // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // *************************************************************************** // *************************************************************************** -// *************************************************************************** -// *************************************************************************** `timescale 1ns/100ps @@ -77,38 +75,45 @@ module system_top ( iic_scl, iic_sda, - rx_ref_clk_p, - rx_ref_clk_n, - rx_sysref_p, - rx_sysref_n, - rx_sync_p, - rx_sync_n, - rx_data_p, - rx_data_n, + dac_clk_in_p, + dac_clk_in_n, + dac_clk_out_p, + dac_clk_out_n, + dac_frame_out_p, + dac_frame_out_n, + dac_data_out_p, + dac_data_out_n, - tx_ref_clk_p, - tx_ref_clk_n, - tx_clk_p, - tx_clk_n, - tx_frame_p, - tx_frame_n, - tx_data_p, - tx_data_n, + adc_clk_in_p, + adc_clk_in_n, + adc_data_in_p, + adc_data_in_n, - gpio_adc_fdb, - gpio_adc_fda, - gpio_dac_irqn, - gpio_clkd_status, - - gpio_clkd_pdn, - gpio_clkd_syncn, - gpio_resetn, - - spi_csn_clk, - spi_csn_dac, - spi_csn_adc, spi_clk, - spi_sdio); + spi_csn, + spi_sdio, + spi_int, + + sys_rst, + sys_clk_p, + sys_clk_n, + + ddr3_addr, + ddr3_ba, + ddr3_cas_n, + ddr3_ck_n, + ddr3_ck_p, + ddr3_cke, + ddr3_cs_n, + ddr3_dm, + ddr3_dq, + ddr3_dqs_n, + ddr3_dqs_p, + ddr3_odt, + ddr3_ras_n, + ddr3_reset_n, + ddr3_we_n +); inout [14:0] ddr_addr; inout [ 2:0] ddr_ba; @@ -146,156 +151,60 @@ module system_top ( inout iic_scl; inout iic_sda; - input rx_ref_clk_p; - input rx_ref_clk_n; - input rx_sysref_p; - input rx_sysref_n; - output rx_sync_p; - output rx_sync_n; - input [ 1:0] rx_data_p; - input [ 1:0] rx_data_n; + input dac_clk_in_p; + input dac_clk_in_n; + output dac_clk_out_p; + output dac_clk_out_n; + output dac_frame_out_p; + output dac_frame_out_n; + output [15:0] dac_data_out_p; + output [15:0] dac_data_out_n; - input tx_ref_clk_p; - input tx_ref_clk_n; - output tx_clk_p; - output tx_clk_n; - output tx_frame_p; - output tx_frame_n; - output [15:0] tx_data_p; - output [15:0] tx_data_n; + input adc_clk_in_p; + input adc_clk_in_n; + input [13:0] adc_data_in_p; + input [13:0] adc_data_in_n; - inout gpio_adc_fdb; - inout gpio_adc_fda; - inout gpio_dac_irqn; - inout [ 1:0] gpio_clkd_status; - - inout gpio_clkd_pdn; - inout gpio_clkd_syncn; - inout gpio_resetn; - - output spi_csn_clk; - output spi_csn_dac; - output spi_csn_adc; output spi_clk; + output spi_csn; inout spi_sdio; + input spi_int; - // internal registers + input sys_rst; + input sys_clk_p; + input sys_clk_n; - reg dac_drd = 'd0; - reg [63:0] dac_ddata_0 = 'd0; - reg [63:0] dac_ddata_1 = 'd0; - reg adc_dwr = 'd0; - reg [63:0] adc_ddata = 'd0; + output [13:0] ddr3_addr; + output [ 2:0] ddr3_ba; + output ddr3_cas_n; + output [ 0:0] ddr3_ck_n; + output [ 0:0] ddr3_ck_p; + output [ 0:0] ddr3_cke; + output [ 0:0] ddr3_cs_n; + output [ 7:0] ddr3_dm; + inout [63:0] ddr3_dq; + inout [ 7:0] ddr3_dqs_n; + inout [ 7:0] ddr3_dqs_p; + output [ 0:0] ddr3_odt; + output ddr3_ras_n; + output ddr3_reset_n; + output ddr3_we_n; // internal signals wire [63:0] gpio_i; wire [63:0] gpio_o; wire [63:0] gpio_t; - wire rx_ref_clk; - wire rx_sysref; - wire rx_sync; - wire [ 2:0] spi_csn; - wire adc_clk; - wire [31:0] adc_data_a; - wire [31:0] adc_data_b; - wire adc_enable_a; - wire adc_enable_b; - wire dac_clk; - wire [127:0] dac_ddata; - wire dac_enable_0; - wire dac_enable_1; - - // pack & unpack data - - always @(posedge dac_clk) begin - case ({dac_enable_1, dac_enable_0}) - 2'b11: begin - dac_drd <= 1'b1; - dac_ddata_1[63:48] <= dac_ddata[127:112]; - dac_ddata_1[47:32] <= dac_ddata[ 95: 80]; - dac_ddata_1[31:16] <= dac_ddata[ 63: 48]; - dac_ddata_1[15: 0] <= dac_ddata[ 31: 16]; - dac_ddata_0[63:48] <= dac_ddata[111: 96]; - dac_ddata_0[47:32] <= dac_ddata[ 79: 64]; - dac_ddata_0[31:16] <= dac_ddata[ 47: 32]; - dac_ddata_0[15: 0] <= dac_ddata[ 15: 0]; - end - 2'b01: begin - dac_drd <= ~dac_drd; - dac_ddata_1 <= 64'd0; - dac_ddata_0 <= (dac_drd == 1'b1) ? dac_ddata[127:64] : dac_ddata[63:0]; - end - 2'b10: begin - dac_drd <= ~dac_drd; - dac_ddata_1 <= (dac_drd == 1'b1) ? dac_ddata[127:64] : dac_ddata[63:0]; - dac_ddata_0 <= 64'd0; - end - default: begin - dac_drd <= 1'b0; - dac_ddata_1 <= 64'd0; - dac_ddata_0 <= 64'd0; - end - endcase - end - - always @(posedge adc_clk) begin - case ({adc_enable_b, adc_enable_a}) - 2'b11: begin - adc_dwr <= 1'b1; - adc_ddata[63:48] <= adc_data_b[31:16]; - adc_ddata[47:32] <= adc_data_a[31:16]; - adc_ddata[31:16] <= adc_data_b[15: 0]; - adc_ddata[15: 0] <= adc_data_a[15: 0]; - end - 2'b10: begin - adc_dwr <= ~adc_dwr; - adc_ddata[63:48] <= adc_data_b[31:16]; - adc_ddata[47:32] <= adc_data_b[15: 0]; - adc_ddata[31:16] <= adc_ddata[63:48]; - adc_ddata[15: 0] <= adc_ddata[47:32]; - end - 2'b01: begin - adc_dwr <= ~adc_dwr; - adc_ddata[63:48] <= adc_data_a[31:16]; - adc_ddata[47:32] <= adc_data_a[15: 0]; - adc_ddata[31:16] <= adc_ddata[63:48]; - adc_ddata[15: 0] <= adc_ddata[47:32]; - end - default: begin - adc_dwr <= 1'b0; - adc_ddata[63:48] <= 16'd0; - adc_ddata[47:32] <= 16'd0; - adc_ddata[31:16] <= 16'd0; - adc_ddata[15: 0] <= 16'd0; - end - endcase - end + wire spi_mosi; + wire spi_miso; // instantiations - assign spi_csn_adc = spi_csn[2]; - assign spi_csn_dac = spi_csn[1]; - assign spi_csn_clk = spi_csn[0]; - - // instantiations - - IBUFDS_GTE2 i_ibufds_rx_ref_clk ( - .CEB (1'd0), - .I (rx_ref_clk_p), - .IB (rx_ref_clk_n), - .O (rx_ref_clk), - .ODIV2 ()); - - IBUFDS i_ibufds_rx_sysref ( - .I (rx_sysref_p), - .IB (rx_sysref_n), - .O (rx_sysref)); - - OBUFDS i_obufds_rx_sync ( - .I (rx_sync), - .O (rx_sync_p), - .OB (rx_sync_n)); + ad_iobuf #(.DATA_WIDTH(15)) i_gpio_bd ( + .dio_t (gpio_t[14:0]), + .dio_i (gpio_o[14:0]), + .dio_o (gpio_i[14:0]), + .dio_p (gpio_bd)); daq1_spi i_spi ( .spi_csn (spi_csn), @@ -304,20 +213,37 @@ module system_top ( .spi_miso (spi_miso), .spi_sdio (spi_sdio)); - ad_iobuf #(.DATA_WIDTH(23)) i_iobuf ( - .dio_t({gpio_t[39:32], gpio_t[14:0]}), - .dio_i({gpio_o[39:32], gpio_o[14:0]}), - .dio_o({gpio_i[39:32], gpio_i[14:0]}), - .dio_p({gpio_adc_fdb, // 39 - gpio_adc_fda, // 38 - gpio_dac_irqn, // 37 - gpio_clkd_status, // 36:35 - gpio_clkd_pdn, // 34 - gpio_clkd_syncn, // 33 - gpio_resetn, // 32 - gpio_bd})); // 14:0 - system_wrapper i_system_wrapper ( + .sys_clk_clk_n (sys_clk_n), + .sys_clk_clk_p (sys_clk_p), + .sys_rst (sys_rst), + .ddr3_addr (ddr3_addr), + .ddr3_ba (ddr3_ba), + .ddr3_cas_n (ddr3_cas_n), + .ddr3_ck_n (ddr3_ck_n), + .ddr3_ck_p (ddr3_ck_p), + .ddr3_cke (ddr3_cke), + .ddr3_cs_n (ddr3_cs_n), + .ddr3_dm (ddr3_dm), + .ddr3_dq (ddr3_dq), + .ddr3_dqs_n (ddr3_dqs_n), + .ddr3_dqs_p (ddr3_dqs_p), + .ddr3_odt (ddr3_odt), + .ddr3_ras_n (ddr3_ras_n), + .ddr3_reset_n (ddr3_reset_n), + .ddr3_we_n (ddr3_we_n), + .adc_clk_in_n (adc_clk_in_n), + .adc_clk_in_p (adc_clk_in_p), + .adc_data_in_n (adc_data_in_n), + .adc_data_in_p (adc_data_in_p), + .dac_clk_in_n (dac_clk_in_n), + .dac_clk_in_p (dac_clk_in_p), + .dac_clk_out_n (dac_clk_out_n), + .dac_clk_out_p (dac_clk_out_p), + .dac_data_out_n (dac_data_out_n), + .dac_data_out_p (dac_data_out_p), + .dac_frame_out_n (dac_frame_out_n), + .dac_frame_out_p (dac_frame_out_p), .ddr_addr (ddr_addr), .ddr_ba (ddr_ba), .ddr_cas_n (ddr_cas_n), @@ -342,25 +268,6 @@ module system_top ( .gpio_i (gpio_i), .gpio_o (gpio_o), .gpio_t (gpio_t), - .adc_clk (adc_clk), - .adc_data_a (adc_data_a), - .adc_data_b (adc_data_b), - .adc_ddata (adc_ddata), - .adc_dsync (1'b1), - .adc_dwr (adc_dwr), - .adc_enable_a (adc_enable_a), - .adc_enable_b (adc_enable_b), - .adc_valid_a (), - .adc_valid_b (), - .dac_clk (dac_clk), - .dac_ddata (dac_ddata), - .dac_ddata_0 (dac_ddata_0), - .dac_ddata_1 (dac_ddata_1), - .dac_drd (dac_drd), - .dac_enable_0 (dac_enable_0), - .dac_enable_1 (dac_enable_1), - .dac_valid_0 (), - .dac_valid_1 (), .hdmi_data (hdmi_data), .hdmi_data_e (hdmi_data_e), .hdmi_hsync (hdmi_hsync), @@ -370,8 +277,6 @@ module system_top ( .iic_main_sda_io (iic_sda), .ps_intr_00 (1'b0), .ps_intr_01 (1'b0), - .ps_intr_10 (1'b0), - .ps_intr_11 (1'b0), .ps_intr_02 (1'b0), .ps_intr_03 (1'b0), .ps_intr_04 (1'b0), @@ -380,29 +285,27 @@ module system_top ( .ps_intr_07 (1'b0), .ps_intr_08 (1'b0), .ps_intr_09 (1'b0), - .rx_data_n (rx_data_n), - .rx_data_p (rx_data_p), - .rx_ref_clk (rx_ref_clk), - .rx_sync (rx_sync), - .rx_sysref (rx_sysref), + .ps_intr_10 (1'b0), .spdif (spdif), .spi0_clk_i (1'b0), .spi0_clk_o (spi_clk), - .spi0_csn_0_o (spi_csn[0]), - .spi0_csn_1_o (spi_csn[1]), - .spi0_csn_2_o (spi_csn[2]), + .spi0_csn_0_o (spi_csn), + .spi0_csn_1_o (), + .spi0_csn_2_o (), .spi0_csn_i (1'b1), .spi0_sdi_i (spi_miso), .spi0_sdo_i (1'b0), .spi0_sdo_o (spi_mosi), - .tx_clk_n (tx_clk_n), - .tx_clk_p (tx_clk_p), - .tx_data_n (tx_data_n), - .tx_data_p (tx_data_p), - .tx_frame_n (tx_frame_n), - .tx_frame_p (tx_frame_p), - .tx_ref_clk_n (tx_ref_clk_n), - .tx_ref_clk_p (tx_ref_clk_p)); + .spi1_clk_i (1'b0), + .spi1_clk_o (), + .spi1_csn_0_o (), + .spi1_csn_1_o (), + .spi1_csn_2_o (), + .spi1_csn_i (1'b1), + .spi1_sdi_i (1'b0), + .spi1_sdo_i (1'b0), + .spi1_sdo_o (), + .spi_int (spi_int)); endmodule diff --git a/projects/daq2/Makefile b/projects/daq2/Makefile index a6441f0c6..337f26381 100644 --- a/projects/daq2/Makefile +++ b/projects/daq2/Makefile @@ -12,6 +12,7 @@ all: -make -C kcu105 all -make -C vc707 all -make -C zc706 all + -make -C zcu102 all clean: @@ -20,6 +21,7 @@ clean: make -C kcu105 clean make -C vc707 clean make -C zc706 clean + make -C zcu102 clean clean-all: @@ -28,6 +30,7 @@ clean-all: make -C kcu105 clean-all make -C vc707 clean-all make -C zc706 clean-all + make -C zcu102 clean-all #################################################################################### #################################################################################### diff --git a/projects/daq2/a10gx/Makefile b/projects/daq2/a10gx/Makefile index 51c24bfef..35c17a9ac 100644 --- a/projects/daq2/a10gx/Makefile +++ b/projects/daq2/a10gx/Makefile @@ -5,16 +5,30 @@ #################################################################################### #################################################################################### +ifeq ($(MMU),) + MMU := 1 +endif + +export ALT_NIOS_MMU_ENABLED := $(MMU) + M_DEPS += system_top.v +M_DEPS += system_qsys.tcl M_DEPS += system_project.tcl M_DEPS += system_constr.sdc -M_DEPS += system_bd.qsys M_DEPS += ../common/daq2_spi.v -M_DEPS += ../common/daq2_bd.qsys +M_DEPS += ../common/daq2_qsys.tcl +M_DEPS += ../../scripts/adi_tquest.tcl M_DEPS += ../../scripts/adi_env.tcl -M_DEPS += ../../common/a10gx/a10gx_system_bd.qsys +M_DEPS += ../../common/altera/sys_gen.tcl +M_DEPS += ../../common/a10gx/a10gx_system_qsys.tcl M_DEPS += ../../common/a10gx/a10gx_system_assign.tcl -M_DEPS += ../../../library/common/ad_iobuf.v +M_DEPS += ../../../library/altera/avl_adxcfg/avl_adxcfg.v +M_DEPS += ../../../library/altera/avl_adxcfg/avl_adxcfg_hw.tcl +M_DEPS += ../../../library/altera/avl_adxcvr/avl_adxcvr_hw.tcl +M_DEPS += ../../../library/altera/axi_adxcvr/axi_adxcvr.v +M_DEPS += ../../../library/altera/axi_adxcvr/axi_adxcvr_hw.tcl +M_DEPS += ../../../library/altera/axi_adxcvr/axi_adxcvr_up.v +M_DEPS += ../../../library/altera/common/ad_mul.v M_DEPS += ../../../library/axi_ad9144/axi_ad9144.v M_DEPS += ../../../library/axi_ad9144/axi_ad9144_channel.v M_DEPS += ../../../library/axi_ad9144/axi_ad9144_core.v @@ -28,6 +42,7 @@ M_DEPS += ../../../library/axi_ad9680/axi_ad9680_pnmon.v M_DEPS += ../../../library/axi_dmac/2d_transfer.v M_DEPS += ../../../library/axi_dmac/address_generator.v M_DEPS += ../../../library/axi_dmac/axi_dmac.v +M_DEPS += ../../../library/axi_dmac/axi_dmac_constr.sdc M_DEPS += ../../../library/axi_dmac/axi_dmac_hw.tcl M_DEPS += ../../../library/axi_dmac/axi_register_slice.v M_DEPS += ../../../library/axi_dmac/data_mover.v @@ -44,17 +59,16 @@ M_DEPS += ../../../library/axi_dmac/splitter.v M_DEPS += ../../../library/axi_dmac/src_axi_mm.v M_DEPS += ../../../library/axi_dmac/src_axi_stream.v M_DEPS += ../../../library/axi_dmac/src_fifo_inf.v -M_DEPS += ../../../library/axi_jesd_xcvr/axi_jesd_xcvr.v -M_DEPS += ../../../library/axi_jesd_xcvr/axi_jesd_xcvr_hw.tcl +M_DEPS += ../../../library/common/ad_axi_ip_constr.sdc +M_DEPS += ../../../library/common/ad_axis_inf_rx.v M_DEPS += ../../../library/common/ad_datafmt.v M_DEPS += ../../../library/common/ad_dds.v M_DEPS += ../../../library/common/ad_dds_1.v M_DEPS += ../../../library/common/ad_dds_sine.v -M_DEPS += ../../../library/common/ad_jesd_align.v -M_DEPS += ../../../library/common/ad_mul.v +M_DEPS += ../../../library/common/ad_mem_asym.v M_DEPS += ../../../library/common/ad_pnmon.v M_DEPS += ../../../library/common/ad_rst.v -M_DEPS += ../../../library/common/altera/MULT_MACRO.v +M_DEPS += ../../../library/common/ad_xcvr_rx_if.v M_DEPS += ../../../library/common/sync_bits.v M_DEPS += ../../../library/common/sync_gray.v M_DEPS += ../../../library/common/up_adc_channel.v @@ -64,12 +78,12 @@ M_DEPS += ../../../library/common/up_clock_mon.v M_DEPS += ../../../library/common/up_dac_channel.v M_DEPS += ../../../library/common/up_dac_common.v M_DEPS += ../../../library/common/up_delay_cntrl.v -M_DEPS += ../../../library/common/up_xcvr.v M_DEPS += ../../../library/common/up_xfer_cntrl.v M_DEPS += ../../../library/common/up_xfer_status.v -M_DEPS += ../../../library/util_adcfifo/../common/ad_axis_inf_rx.v -M_DEPS += ../../../library/util_adcfifo/../common/ad_mem_asym.v +M_DEPS += ../../../library/scripts/adi_env.tcl +M_DEPS += ../../../library/scripts/adi_ip_alt.tcl M_DEPS += ../../../library/util_adcfifo/util_adcfifo.v +M_DEPS += ../../../library/util_adcfifo/util_adcfifo_constr.sdc M_DEPS += ../../../library/util_adcfifo/util_adcfifo_hw.tcl M_DEPS += ../../../library/util_axis_fifo/address_gray.v M_DEPS += ../../../library/util_axis_fifo/address_gray_pipelined.v @@ -116,6 +130,8 @@ M_FLIST += reconfig_mif M_FLIST += *.sopcinfo M_FLIST += *.jdi M_FLIST += *.pin +M_FLIST += *_summary.csv +M_FLIST += *.dpf @@ -132,7 +148,7 @@ clean-all: daq2_a10gx.sof: $(M_DEPS) - rm -rf $(M_FLIST) + -rm -rf $(M_FLIST) $(M_ALTERA) system_project.tcl >> daq2_a10gx_quartus.log 2>&1 #################################################################################### diff --git a/projects/daq2/a10gx/system_bd.qsys b/projects/daq2/a10gx/system_bd.qsys deleted file mode 100755 index fac722018..000000000 --- a/projects/daq2/a10gx/system_bd.qsys +++ /dev/null @@ -1,680 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ]]> - - - - - - - - - $${FILENAME}_a10gx_base - - - ]]> - - ]]> - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/projects/daq2/a10gx/system_constr.sdc b/projects/daq2/a10gx/system_constr.sdc index 7ec6b3f16..dbb02427a 100644 --- a/projects/daq2/a10gx/system_constr.sdc +++ b/projects/daq2/a10gx/system_constr.sdc @@ -7,37 +7,37 @@ derive_pll_clocks derive_clock_uncertainty set_false_path -from [get_clocks {sys_clk_100mhz}] -to [get_clocks {\ - i_system_bd|a10gx_base|sys_ddr3_cntrl_phy_clk_0 \ - i_system_bd|a10gx_base|sys_ddr3_cntrl_phy_clk_1 \ - i_system_bd|a10gx_base|sys_ddr3_cntrl_phy_clk_2 \ - i_system_bd|a10gx_base|sys_ddr3_cntrl_phy_clk_l_0 \ - i_system_bd|a10gx_base|sys_ddr3_cntrl_phy_clk_l_1 \ - i_system_bd|a10gx_base|sys_ddr3_cntrl_phy_clk_l_2}] + i_system_bd|sys_ddr3_cntrl_phy_clk_0 \ + i_system_bd|sys_ddr3_cntrl_phy_clk_1 \ + i_system_bd|sys_ddr3_cntrl_phy_clk_2 \ + i_system_bd|sys_ddr3_cntrl_phy_clk_l_0 \ + i_system_bd|sys_ddr3_cntrl_phy_clk_l_1 \ + i_system_bd|sys_ddr3_cntrl_phy_clk_l_2}] set_false_path -from [get_clocks {sys_clk_100mhz}] -to [get_clocks {\ - i_system_bd|a10gx_base|sys_ddr3_cntrl_core_nios_clk}] + i_system_bd|sys_ddr3_cntrl_core_nios_clk}] set_false_path -from [get_clocks {sys_clk_100mhz}]\ -through [get_nets *altera_jesd204_tx_csr_inst*]\ - -to [get_clocks {i_system_bd|daq2|xcvr_tx_pll|outclk0}] + -to [get_clocks {i_system_bd|avl_ad9144_xcvr|alt_core_pll|outclk0}] set_false_path -from [get_clocks {sys_clk_100mhz}]\ -through [get_nets *altera_jesd204_tx_ctl_inst*]\ - -to [get_clocks {i_system_bd|daq2|xcvr_tx_pll|outclk0}] + -to [get_clocks {i_system_bd|avl_ad9144_xcvr|alt_core_pll|outclk0}] set_false_path -from [get_clocks {sys_clk_100mhz}]\ -through [get_nets *altera_jesd204_rx_csr_inst*]\ - -to [get_clocks {i_system_bd|daq2|xcvr_rx_pll|outclk0}] + -to [get_clocks {i_system_bd|avl_ad9680_xcvr|alt_core_pll|outclk0}] -set_false_path -from [get_clocks {i_system_bd|daq2|xcvr_tx_pll|outclk0}]\ +set_false_path -from [get_clocks {i_system_bd|avl_ad9144_xcvr|alt_core_pll|outclk0}]\ -through [get_nets *altera_jesd204_tx_csr_inst*]\ -to [get_clocks {sys_clk_100mhz}] -set_false_path -from [get_clocks {i_system_bd|daq2|xcvr_tx_pll|outclk0}]\ +set_false_path -from [get_clocks {i_system_bd|avl_ad9144_xcvr|alt_core_pll|outclk0}]\ -through [get_nets *altera_jesd204_tx_ctl_inst*]\ -to [get_clocks {sys_clk_100mhz}] -set_false_path -from [get_clocks {i_system_bd|daq2|xcvr_rx_pll|outclk0}]\ +set_false_path -from [get_clocks {i_system_bd|avl_ad9680_xcvr|alt_core_pll|outclk0}]\ -through [get_nets *altera_jesd204_rx_csr_inst*]\ -to [get_clocks {sys_clk_100mhz}] diff --git a/projects/daq2/a10gx/system_project.tcl b/projects/daq2/a10gx/system_project.tcl index 664f75637..824055fdd 100644 --- a/projects/daq2/a10gx/system_project.tcl +++ b/projects/daq2/a10gx/system_project.tcl @@ -5,13 +5,10 @@ source ../../scripts/adi_env.tcl project_new daq2_a10gx -overwrite source "../../common/a10gx/a10gx_system_assign.tcl" -set_user_option -name USER_IP_SEARCH_PATHS "../common/;../../common/a10gx/;../../../library/**/*" -set_global_assignment -name IP_SEARCH_PATHS "../common/;../../common/a10gx;../../../library/**/*" -set_global_assignment -name QSYS_FILE system_bd.qsys -set_global_assignment -name VERILOG_FILE "../../../library/common/ad_iobuf.v" set_global_assignment -name VERILOG_FILE ../common/daq2_spi.v set_global_assignment -name VERILOG_FILE system_top.v +set_global_assignment -name QSYS_FILE system_bd.qsys set_global_assignment -name SDC_FILE system_constr.sdc set_global_assignment -name TOP_LEVEL_ENTITY system_top @@ -63,6 +60,16 @@ set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to tx_sync set_instance_assignment -name IO_STANDARD LVDS -to tx_sysref set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to tx_sysref +set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_0 -to rx_data[0] +set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_1 -to rx_data[1] +set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_2 -to rx_data[2] +set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_3 -to rx_data[3] + +set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_0 -to tx_data[0] +set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_1 -to tx_data[1] +set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_2 -to tx_data[2] +set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_3 -to tx_data[3] + # gpio set_location_assignment PIN_AT17 -to trig ; ## H13 FMCA_LA07_P diff --git a/projects/daq2/a10gx/system_qsys.tcl b/projects/daq2/a10gx/system_qsys.tcl new file mode 100644 index 000000000..47d33019c --- /dev/null +++ b/projects/daq2/a10gx/system_qsys.tcl @@ -0,0 +1,5 @@ + +source $ad_hdl_dir/projects/common/a10gx/a10gx_system_qsys.tcl +source ../common/daq2_qsys.tcl + + diff --git a/projects/daq2/a10gx/system_top.v b/projects/daq2/a10gx/system_top.v index 49b9ec652..ae7fa023d 100644 --- a/projects/daq2/a10gx/system_top.v +++ b/projects/daq2/a10gx/system_top.v @@ -211,13 +211,20 @@ module system_top ( // gpio in & out are separate cores + assign gpio_i[63:44] = gpio_o[63:44]; + assign gpio_i[43:43] = trig; + + assign gpio_i[42:40] = gpio_o[42:40]; assign adc_pd = gpio_o[42]; assign dac_txen = gpio_o[41]; assign dac_reset = gpio_o[40]; + + assign gpio_i[39:39] = gpio_o[39]; + + assign gpio_i[38:38] = gpio_o[38]; assign clkd_sync = gpio_o[38]; - assign gpio_i[63:38] = gpio_o[63:38]; - assign gpio_i[37:37] = trig; + assign gpio_i[37:37] = gpio_o[37]; assign gpio_i[36:36] = adc_fdb; assign gpio_i[35:35] = adc_fda; assign gpio_i[34:34] = dac_irq; @@ -238,49 +245,55 @@ module system_top ( assign gpio_bd_o = gpio_o[15:0]; system_bd i_system_bd ( - .a10gx_base_sys_ddr3_cntrl_mem_mem_ck (ddr3_clk_p), - .a10gx_base_sys_ddr3_cntrl_mem_mem_ck_n (ddr3_clk_n), - .a10gx_base_sys_ddr3_cntrl_mem_mem_a (ddr3_a[11:0]), - .a10gx_base_sys_ddr3_cntrl_mem_mem_ba (ddr3_ba), - .a10gx_base_sys_ddr3_cntrl_mem_mem_cke (ddr3_cke), - .a10gx_base_sys_ddr3_cntrl_mem_mem_cs_n (ddr3_cs_n), - .a10gx_base_sys_ddr3_cntrl_mem_mem_odt (ddr3_odt), - .a10gx_base_sys_ddr3_cntrl_mem_mem_reset_n (ddr3_reset_n), - .a10gx_base_sys_ddr3_cntrl_mem_mem_we_n (ddr3_we_n), - .a10gx_base_sys_ddr3_cntrl_mem_mem_ras_n (ddr3_ras_n), - .a10gx_base_sys_ddr3_cntrl_mem_mem_cas_n (ddr3_cas_n), - .a10gx_base_sys_ddr3_cntrl_mem_mem_dqs (ddr3_dqs_p[7:0]), - .a10gx_base_sys_ddr3_cntrl_mem_mem_dqs_n (ddr3_dqs_n[7:0]), - .a10gx_base_sys_ddr3_cntrl_mem_mem_dq (ddr3_dq[63:0]), - .a10gx_base_sys_ddr3_cntrl_mem_mem_dm (ddr3_dm[7:0]), - .a10gx_base_sys_ddr3_cntrl_oct_oct_rzqin (ddr3_rzq), - .a10gx_base_sys_ddr3_cntrl_pll_ref_clk_clk (ddr3_ref_clk), - .a10gx_base_sys_ethernet_mdio_mdc (eth_mdc), - .a10gx_base_sys_ethernet_mdio_mdio_in (eth_mdio_i), - .a10gx_base_sys_ethernet_mdio_mdio_out (eth_mdio_o), - .a10gx_base_sys_ethernet_mdio_mdio_oen (eth_mdio_t), - .a10gx_base_sys_ethernet_ref_clk_clk (eth_ref_clk), - .a10gx_base_sys_ethernet_reset_reset (eth_reset), - .a10gx_base_sys_ethernet_sgmii_rxp_0 (eth_rxd), - .a10gx_base_sys_ethernet_sgmii_txp_0 (eth_txd), - .a10gx_base_sys_gpio_in_export (gpio_i[63:32]), - .a10gx_base_sys_gpio_out_export (gpio_o[63:32]), - .a10gx_base_sys_gpio_bd_in_port (gpio_i[31:0]), - .a10gx_base_sys_gpio_bd_out_port (gpio_o[31:0]), - .a10gx_base_sys_spi_MISO (spi_miso_s), - .a10gx_base_sys_spi_MOSI (spi_mosi_s), - .a10gx_base_sys_spi_SCLK (spi_clk), - .a10gx_base_sys_spi_SS_n (spi_csn_s), - .daq2_rx_data_rx_serial_data (rx_data), - .daq2_rx_ref_clk_clk (rx_ref_clk), - .daq2_rx_sync_rx_sync (rx_sync), - .daq2_rx_sysref_rx_ext_sysref_in (rx_sysref), - .daq2_tx_data_tx_serial_data (tx_data), - .daq2_tx_ref_clk_clk (tx_ref_clk), - .daq2_tx_sync_tx_sync (tx_sync), - .daq2_tx_sysref_tx_ext_sysref_in (tx_sysref), + .rx_data_0_rx_serial_data (rx_data[0]), + .rx_data_1_rx_serial_data (rx_data[1]), + .rx_data_2_rx_serial_data (rx_data[2]), + .rx_data_3_rx_serial_data (rx_data[3]), + .rx_ref_clk_clk (rx_ref_clk), + .rx_sync_export (rx_sync), + .rx_sysref_export (rx_sysref), .sys_clk_clk (sys_clk), - .sys_reset_reset_n (sys_resetn)); + .sys_ddr3_cntrl_mem_mem_ck (ddr3_clk_p), + .sys_ddr3_cntrl_mem_mem_ck_n (ddr3_clk_n), + .sys_ddr3_cntrl_mem_mem_a (ddr3_a[11:0]), + .sys_ddr3_cntrl_mem_mem_ba (ddr3_ba), + .sys_ddr3_cntrl_mem_mem_cke (ddr3_cke), + .sys_ddr3_cntrl_mem_mem_cs_n (ddr3_cs_n), + .sys_ddr3_cntrl_mem_mem_odt (ddr3_odt), + .sys_ddr3_cntrl_mem_mem_reset_n (ddr3_reset_n), + .sys_ddr3_cntrl_mem_mem_we_n (ddr3_we_n), + .sys_ddr3_cntrl_mem_mem_ras_n (ddr3_ras_n), + .sys_ddr3_cntrl_mem_mem_cas_n (ddr3_cas_n), + .sys_ddr3_cntrl_mem_mem_dqs (ddr3_dqs_p[7:0]), + .sys_ddr3_cntrl_mem_mem_dqs_n (ddr3_dqs_n[7:0]), + .sys_ddr3_cntrl_mem_mem_dq (ddr3_dq[63:0]), + .sys_ddr3_cntrl_mem_mem_dm (ddr3_dm[7:0]), + .sys_ddr3_cntrl_oct_oct_rzqin (ddr3_rzq), + .sys_ddr3_cntrl_pll_ref_clk_clk (ddr3_ref_clk), + .sys_ethernet_mdio_mdc (eth_mdc), + .sys_ethernet_mdio_mdio_in (eth_mdio_i), + .sys_ethernet_mdio_mdio_out (eth_mdio_o), + .sys_ethernet_mdio_mdio_oen (eth_mdio_t), + .sys_ethernet_ref_clk_clk (eth_ref_clk), + .sys_ethernet_reset_reset (eth_reset), + .sys_ethernet_sgmii_rxp_0 (eth_rxd), + .sys_ethernet_sgmii_txp_0 (eth_txd), + .sys_gpio_bd_in_port (gpio_i[31:0]), + .sys_gpio_bd_out_port (gpio_o[31:0]), + .sys_gpio_in_export (gpio_i[63:32]), + .sys_gpio_out_export (gpio_o[63:32]), + .sys_rst_reset_n (sys_resetn), + .sys_spi_MISO (spi_miso_s), + .sys_spi_MOSI (spi_mosi_s), + .sys_spi_SCLK (spi_clk), + .sys_spi_SS_n (spi_csn_s), + .tx_data_0_tx_serial_data (tx_data[0]), + .tx_data_1_tx_serial_data (tx_data[1]), + .tx_data_2_tx_serial_data (tx_data[2]), + .tx_data_3_tx_serial_data (tx_data[3]), + .tx_ref_clk_clk (tx_ref_clk), + .tx_sync_export (tx_sync), + .tx_sysref_export (tx_sysref)); endmodule diff --git a/projects/daq2/common/daq2_bd.qsys b/projects/daq2/common/daq2_bd.qsys deleted file mode 100755 index d61b9f7ba..000000000 --- a/projects/daq2/common/daq2_bd.qsys +++ /dev/null @@ -1,2416 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Automatic Switchover - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GX clock output buffer - - - - altera_xcvr_atx_pll_a10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Automatic Switchover - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/projects/daq2/common/daq2_bd.tcl b/projects/daq2/common/daq2_bd.tcl index d9c58fdd2..0d6e6627d 100644 --- a/projects/daq2/common/daq2_bd.tcl +++ b/projects/daq2/common/daq2_bd.tcl @@ -1,26 +1,21 @@ -# daq2 - -create_bd_port -dir I rx_ref_clk -create_bd_port -dir O rx_sync -create_bd_port -dir I rx_sysref -create_bd_port -dir I -from 3 -to 0 rx_data_p -create_bd_port -dir I -from 3 -to 0 rx_data_n - -create_bd_port -dir I tx_ref_clk -create_bd_port -dir I tx_sync -create_bd_port -dir I tx_sysref -create_bd_port -dir O -from 3 -to 0 tx_data_p -create_bd_port -dir O -from 3 -to 0 tx_data_n - # dac peripherals +set axi_ad9144_xcvr [create_bd_cell -type ip -vlnv analog.com:user:axi_adxcvr:1.0 axi_ad9144_xcvr] +set_property -dict [list CONFIG.NUM_OF_LANES {4}] $axi_ad9144_xcvr +set_property -dict [list CONFIG.QPLL_ENABLE {1}] $axi_ad9144_xcvr +set_property -dict [list CONFIG.TX_OR_RX_N {1}] $axi_ad9144_xcvr + +set axi_ad9144_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:7.0 axi_ad9144_jesd] +set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {1}] $axi_ad9144_jesd +set_property -dict [list CONFIG.C_LANES {4}] $axi_ad9144_jesd + set axi_ad9144_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9144:1.0 axi_ad9144_core] set_property -dict [list CONFIG.QUAD_OR_DUAL_N {0}] $axi_ad9144_core -set axi_ad9144_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.2 axi_ad9144_jesd] -set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {1}] $axi_ad9144_jesd -set_property -dict [list CONFIG.C_LANES {4}] $axi_ad9144_jesd +set axi_ad9144_upack [create_bd_cell -type ip -vlnv analog.com:user:util_upack:1.0 axi_ad9144_upack] +set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {64}] $axi_ad9144_upack +set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $axi_ad9144_upack set axi_ad9144_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9144_dma] set_property -dict [list CONFIG.DMA_TYPE_SRC {0}] $axi_ad9144_dma @@ -34,17 +29,22 @@ set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad9144_dma set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {128}] $axi_ad9144_dma set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {128}] $axi_ad9144_dma -set axi_ad9144_upack [create_bd_cell -type ip -vlnv analog.com:user:util_upack:1.0 axi_ad9144_upack] -set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {64}] $axi_ad9144_upack -set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $axi_ad9144_upack - # adc peripherals +set axi_ad9680_xcvr [create_bd_cell -type ip -vlnv analog.com:user:axi_adxcvr:1.0 axi_ad9680_xcvr] +set_property -dict [list CONFIG.NUM_OF_LANES {4}] $axi_ad9680_xcvr +set_property -dict [list CONFIG.QPLL_ENABLE {0}] $axi_ad9680_xcvr +set_property -dict [list CONFIG.TX_OR_RX_N {0}] $axi_ad9680_xcvr + +set axi_ad9680_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:7.0 axi_ad9680_jesd] +set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9680_jesd +set_property -dict [list CONFIG.C_LANES {4}] $axi_ad9680_jesd + set axi_ad9680_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9680:1.0 axi_ad9680_core] -set axi_ad9680_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.2 axi_ad9680_jesd] -set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9680_jesd -set_property -dict [list CONFIG.C_LANES {4}] $axi_ad9680_jesd +set axi_ad9680_cpack [create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 axi_ad9680_cpack] +set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {64}] $axi_ad9680_cpack +set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $axi_ad9680_cpack set axi_ad9680_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9680_dma] set_property -dict [list CONFIG.DMA_TYPE_SRC {1}] $axi_ad9680_dma @@ -59,87 +59,42 @@ set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad9680_dma set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {64}] $axi_ad9680_dma set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $axi_ad9680_dma -set axi_ad9680_cpack [create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 axi_ad9680_cpack] -set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {64}] $axi_ad9680_cpack -set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $axi_ad9680_cpack +# shared transceiver core -# dac/adc common gt +set util_daq2_xcvr [create_bd_cell -type ip -vlnv analog.com:user:util_adxcvr:1.0 util_daq2_xcvr] +set_property -dict [list CONFIG.RX_NUM_OF_LANES {4}] $util_daq2_xcvr +set_property -dict [list CONFIG.TX_NUM_OF_LANES {4}] $util_daq2_xcvr -set axi_daq2_gt [create_bd_cell -type ip -vlnv analog.com:user:axi_jesd_gt:1.0 axi_daq2_gt] -set_property -dict [list CONFIG.NUM_OF_LANES {4}] $axi_daq2_gt -set_property -dict [list CONFIG.QPLL1_ENABLE {0}] $axi_daq2_gt -set_property -dict [list CONFIG.RX_NUM_OF_LANES {4}] $axi_daq2_gt -set_property -dict [list CONFIG.TX_NUM_OF_LANES {4}] $axi_daq2_gt -set_property -dict [list CONFIG.RX_CLKBUF_ENABLE_0 {1}] $axi_daq2_gt -set_property -dict [list CONFIG.TX_CLKBUF_ENABLE_0 {1}] $axi_daq2_gt -set_property -dict [list CONFIG.TX_DATA_SEL_0 {0}] $axi_daq2_gt -set_property -dict [list CONFIG.TX_DATA_SEL_1 {3}] $axi_daq2_gt -set_property -dict [list CONFIG.TX_DATA_SEL_2 {1}] $axi_daq2_gt -set_property -dict [list CONFIG.TX_DATA_SEL_3 {2}] $axi_daq2_gt +ad_connect sys_cpu_resetn util_daq2_xcvr/up_rstn +ad_connect sys_cpu_clk util_daq2_xcvr/up_clk -set util_daq2_gt [create_bd_cell -type ip -vlnv analog.com:user:util_jesd_gt:1.0 util_daq2_gt] -set_property -dict [list CONFIG.QPLL0_ENABLE {1}] $util_daq2_gt -set_property -dict [list CONFIG.QPLL1_ENABLE {0}] $util_daq2_gt -set_property -dict [list CONFIG.NUM_OF_LANES {4}] $util_daq2_gt -set_property -dict [list CONFIG.RX_ENABLE {1}] $util_daq2_gt -set_property -dict [list CONFIG.RX_NUM_OF_LANES {4}] $util_daq2_gt -set_property -dict [list CONFIG.TX_ENABLE {1}] $util_daq2_gt -set_property -dict [list CONFIG.TX_NUM_OF_LANES {4}] $util_daq2_gt +# reference clocks & resets -# connections (gt) +create_bd_port -dir I tx_ref_clk_0 +create_bd_port -dir I rx_ref_clk_0 -ad_connect util_daq2_gt/qpll_ref_clk rx_ref_clk -ad_connect util_daq2_gt/cpll_ref_clk tx_ref_clk - -ad_connect axi_daq2_gt/gt_qpll_0 util_daq2_gt/gt_qpll_0 -ad_connect axi_daq2_gt/gt_pll_0 util_daq2_gt/gt_pll_0 -ad_connect axi_daq2_gt/gt_pll_1 util_daq2_gt/gt_pll_1 -ad_connect axi_daq2_gt/gt_pll_2 util_daq2_gt/gt_pll_2 -ad_connect axi_daq2_gt/gt_pll_3 util_daq2_gt/gt_pll_3 -ad_connect axi_daq2_gt/gt_rx_0 util_daq2_gt/gt_rx_0 -ad_connect axi_daq2_gt/gt_rx_1 util_daq2_gt/gt_rx_1 -ad_connect axi_daq2_gt/gt_rx_2 util_daq2_gt/gt_rx_2 -ad_connect axi_daq2_gt/gt_rx_3 util_daq2_gt/gt_rx_3 -ad_connect axi_daq2_gt/gt_rx_ip_0 axi_ad9680_jesd/gt0_rx -ad_connect axi_daq2_gt/gt_rx_ip_1 axi_ad9680_jesd/gt1_rx -ad_connect axi_daq2_gt/gt_rx_ip_2 axi_ad9680_jesd/gt2_rx -ad_connect axi_daq2_gt/gt_rx_ip_3 axi_ad9680_jesd/gt3_rx -ad_connect axi_daq2_gt/rx_gt_comma_align_enb_0 axi_ad9680_jesd/rxencommaalign_out -ad_connect axi_daq2_gt/rx_gt_comma_align_enb_1 axi_ad9680_jesd/rxencommaalign_out -ad_connect axi_daq2_gt/rx_gt_comma_align_enb_2 axi_ad9680_jesd/rxencommaalign_out -ad_connect axi_daq2_gt/rx_gt_comma_align_enb_3 axi_ad9680_jesd/rxencommaalign_out -ad_connect axi_daq2_gt/gt_tx_0 util_daq2_gt/gt_tx_0 -ad_connect axi_daq2_gt/gt_tx_1 util_daq2_gt/gt_tx_1 -ad_connect axi_daq2_gt/gt_tx_2 util_daq2_gt/gt_tx_2 -ad_connect axi_daq2_gt/gt_tx_3 util_daq2_gt/gt_tx_3 -ad_connect axi_daq2_gt/gt_tx_ip_0 axi_ad9144_jesd/gt0_tx -ad_connect axi_daq2_gt/gt_tx_ip_1 axi_ad9144_jesd/gt1_tx -ad_connect axi_daq2_gt/gt_tx_ip_2 axi_ad9144_jesd/gt2_tx -ad_connect axi_daq2_gt/gt_tx_ip_3 axi_ad9144_jesd/gt3_tx +ad_xcvrpll tx_ref_clk_0 util_daq2_xcvr/qpll_ref_clk_* +ad_xcvrpll rx_ref_clk_0 util_daq2_xcvr/cpll_ref_clk_* +ad_xcvrpll axi_ad9144_xcvr/up_pll_rst util_daq2_xcvr/up_qpll_rst_* +ad_xcvrpll axi_ad9680_xcvr/up_pll_rst util_daq2_xcvr/up_cpll_rst_* # connections (dac) -ad_connect util_daq2_gt/tx_sysref tx_sysref -ad_connect util_daq2_gt/tx_p tx_data_p -ad_connect util_daq2_gt/tx_n tx_data_n -ad_connect util_daq2_gt/tx_sync tx_sync -ad_connect util_daq2_gt/tx_out_clk util_daq2_gt/tx_clk -ad_connect util_daq2_gt/tx_out_clk axi_ad9144_jesd/tx_core_clk -ad_connect util_daq2_gt/tx_ip_rst axi_ad9144_jesd/tx_reset -ad_connect util_daq2_gt/tx_ip_rst_done axi_ad9144_jesd/tx_reset_done -ad_connect util_daq2_gt/tx_ip_sysref axi_ad9144_jesd/tx_sysref -ad_connect util_daq2_gt/tx_ip_sync axi_ad9144_jesd/tx_sync -ad_connect util_daq2_gt/tx_ip_data axi_ad9144_jesd/tx_tdata -ad_connect util_daq2_gt/tx_out_clk axi_ad9144_core/tx_clk -ad_connect util_daq2_gt/tx_data axi_ad9144_core/tx_data -ad_connect util_daq2_gt/tx_out_clk axi_ad9144_upack/dac_clk +ad_xcvrcon util_daq2_xcvr axi_ad9144_xcvr axi_ad9144_jesd +ad_reconct util_daq2_xcvr/tx_0 axi_ad9144_jesd/gt0_tx +ad_reconct util_daq2_xcvr/tx_1 axi_ad9144_jesd/gt3_tx +ad_reconct util_daq2_xcvr/tx_2 axi_ad9144_jesd/gt1_tx +ad_reconct util_daq2_xcvr/tx_3 axi_ad9144_jesd/gt2_tx +ad_connect util_daq2_xcvr/tx_out_clk_0 axi_ad9144_core/tx_clk +ad_connect axi_ad9144_jesd/tx_tdata axi_ad9144_core/tx_data +ad_connect util_daq2_xcvr/tx_out_clk_0 axi_ad9144_upack/dac_clk ad_connect axi_ad9144_core/dac_enable_0 axi_ad9144_upack/dac_enable_0 ad_connect axi_ad9144_core/dac_ddata_0 axi_ad9144_upack/dac_data_0 ad_connect axi_ad9144_core/dac_valid_0 axi_ad9144_upack/dac_valid_0 ad_connect axi_ad9144_core/dac_enable_1 axi_ad9144_upack/dac_enable_1 ad_connect axi_ad9144_core/dac_ddata_1 axi_ad9144_upack/dac_data_1 ad_connect axi_ad9144_core/dac_valid_1 axi_ad9144_upack/dac_valid_1 -ad_connect util_daq2_gt/tx_out_clk axi_ad9144_fifo/dac_clk +ad_connect util_daq2_xcvr/tx_out_clk_0 axi_ad9144_fifo/dac_clk ad_connect axi_ad9144_upack/dac_valid axi_ad9144_fifo/dac_valid ad_connect axi_ad9144_upack/dac_data axi_ad9144_fifo/dac_data ad_connect axi_ad9144_upack/dma_xfer_in axi_ad9144_fifo/dac_xfer_out @@ -155,30 +110,20 @@ ad_connect axi_ad9144_fifo/dma_xfer_last axi_ad9144_dma/m_axis_last # connections (adc) -ad_connect util_daq2_gt/rx_sysref rx_sysref -ad_connect util_daq2_gt/rx_p rx_data_p -ad_connect util_daq2_gt/rx_n rx_data_n -ad_connect util_daq2_gt/rx_sync rx_sync -ad_connect util_daq2_gt/rx_out_clk util_daq2_gt/rx_clk -ad_connect util_daq2_gt/rx_out_clk axi_ad9680_jesd/rx_core_clk -ad_connect util_daq2_gt/rx_ip_rst axi_ad9680_jesd/rx_reset -ad_connect util_daq2_gt/rx_ip_rst_done axi_ad9680_jesd/rx_reset_done -ad_connect util_daq2_gt/rx_ip_sysref axi_ad9680_jesd/rx_sysref -ad_connect util_daq2_gt/rx_ip_sync axi_ad9680_jesd/rx_sync -ad_connect util_daq2_gt/rx_ip_sof axi_ad9680_jesd/rx_start_of_frame -ad_connect util_daq2_gt/rx_ip_data axi_ad9680_jesd/rx_tdata -ad_connect util_daq2_gt/rx_out_clk axi_ad9680_core/rx_clk -ad_connect util_daq2_gt/rx_data axi_ad9680_core/rx_data -ad_connect util_daq2_gt/rx_out_clk axi_ad9680_cpack/adc_clk -ad_connect util_daq2_gt/rx_rst axi_ad9680_cpack/adc_rst +ad_xcvrcon util_daq2_xcvr axi_ad9680_xcvr axi_ad9680_jesd +ad_connect util_daq2_xcvr/rx_out_clk_0 axi_ad9680_core/rx_clk +ad_connect axi_ad9680_jesd/rx_start_of_frame axi_ad9680_core/rx_sof +ad_connect axi_ad9680_jesd/rx_tdata axi_ad9680_core/rx_data +ad_connect util_daq2_xcvr/rx_out_clk_0 axi_ad9680_cpack/adc_clk +ad_connect axi_ad9680_jesd_rstgen/peripheral_reset axi_ad9680_cpack/adc_rst ad_connect axi_ad9680_core/adc_enable_0 axi_ad9680_cpack/adc_enable_0 ad_connect axi_ad9680_core/adc_valid_0 axi_ad9680_cpack/adc_valid_0 ad_connect axi_ad9680_core/adc_data_0 axi_ad9680_cpack/adc_data_0 ad_connect axi_ad9680_core/adc_enable_1 axi_ad9680_cpack/adc_enable_1 ad_connect axi_ad9680_core/adc_valid_1 axi_ad9680_cpack/adc_valid_1 ad_connect axi_ad9680_core/adc_data_1 axi_ad9680_cpack/adc_data_1 -ad_connect util_daq2_gt/rx_out_clk axi_ad9680_fifo/adc_clk -ad_connect util_daq2_gt/rx_rst axi_ad9680_fifo/adc_rst +ad_connect util_daq2_xcvr/rx_out_clk_0 axi_ad9680_fifo/adc_clk +ad_connect axi_ad9680_jesd_rstgen/peripheral_reset axi_ad9680_fifo/adc_rst ad_connect axi_ad9680_cpack/adc_valid axi_ad9680_fifo/adc_wr ad_connect axi_ad9680_cpack/adc_data axi_ad9680_fifo/adc_wdata ad_connect sys_cpu_clk axi_ad9680_fifo/dma_clk @@ -192,10 +137,11 @@ ad_connect axi_ad9680_core/adc_dovf axi_ad9680_fifo/adc_wovf # interconnect (cpu) -ad_cpu_interconnect 0x44A60000 axi_daq2_gt +ad_cpu_interconnect 0x44A60000 axi_ad9144_xcvr ad_cpu_interconnect 0x44A00000 axi_ad9144_core ad_cpu_interconnect 0x44A90000 axi_ad9144_jesd ad_cpu_interconnect 0x7c420000 axi_ad9144_dma +ad_cpu_interconnect 0x44A50000 axi_ad9680_xcvr ad_cpu_interconnect 0x44A10000 axi_ad9680_core ad_cpu_interconnect 0x44A91000 axi_ad9680_jesd ad_cpu_interconnect 0x7c400000 axi_ad9680_dma @@ -203,7 +149,7 @@ ad_cpu_interconnect 0x7c400000 axi_ad9680_dma # gt uses hp3, and 100MHz clock for both DRP and AXI4 ad_mem_hp3_interconnect sys_cpu_clk sys_ps7/S_AXI_HP3 -ad_mem_hp3_interconnect sys_cpu_clk axi_daq2_gt/m_axi +ad_mem_hp3_interconnect sys_cpu_clk axi_ad9680_xcvr/m_axi # interconnect (mem/dac) @@ -219,5 +165,5 @@ ad_cpu_interrupt ps-13 mb-12 axi_ad9680_dma/irq ad_connect axi_ad9144_core/dac_ddata_2 GND ad_connect axi_ad9144_core/dac_ddata_3 GND - +ad_connect axi_ad9144_fifo/dac_fifo_bypass GND diff --git a/projects/daq2/common/daq2_qsys.tcl b/projects/daq2/common/daq2_qsys.tcl new file mode 100644 index 000000000..e4207aca3 --- /dev/null +++ b/projects/daq2/common/daq2_qsys.tcl @@ -0,0 +1,257 @@ + +# ad9144-xcvr + +add_instance avl_ad9144_xcvr avl_adxcvr 1.0 +set_instance_parameter_value avl_ad9144_xcvr {ID} {0} +set_instance_parameter_value avl_ad9144_xcvr {TX_OR_RX_N} {1} +set_instance_parameter_value avl_ad9144_xcvr {PCS_CONFIG} {JESD_PCS_CFG2} +set_instance_parameter_value avl_ad9144_xcvr {LANE_RATE} {10000.0} +set_instance_parameter_value avl_ad9144_xcvr {PLLCLK_FREQUENCY} {5000.0} +set_instance_parameter_value avl_ad9144_xcvr {REFCLK_FREQUENCY} {500.0} +set_instance_parameter_value avl_ad9144_xcvr {CORECLK_FREQUENCY} {250.0} +set_instance_parameter_value avl_ad9144_xcvr {NUM_OF_LANES} {4} +set_instance_parameter_value avl_ad9144_xcvr {NUM_OF_CONVS} {2} +set_instance_parameter_value avl_ad9144_xcvr {FRM_BCNT} {1} +set_instance_parameter_value avl_ad9144_xcvr {FRM_SCNT} {1} +set_instance_parameter_value avl_ad9144_xcvr {MF_FCNT} {32} +set_instance_parameter_value avl_ad9144_xcvr {HD} {1} + +add_connection sys_clk.clk avl_ad9144_xcvr.sys_clk +add_connection sys_clk.clk_reset avl_ad9144_xcvr.sys_resetn +add_interface tx_ref_clk clock sink +set_interface_property tx_ref_clk EXPORT_OF avl_ad9144_xcvr.ref_clk +add_interface tx_data_0 conduit end +set_interface_property tx_data_0 EXPORT_OF avl_ad9144_xcvr.tx_data_0 +add_interface tx_data_1 conduit end +set_interface_property tx_data_1 EXPORT_OF avl_ad9144_xcvr.tx_data_1 +add_interface tx_data_2 conduit end +set_interface_property tx_data_2 EXPORT_OF avl_ad9144_xcvr.tx_data_2 +add_interface tx_data_3 conduit end +set_interface_property tx_data_3 EXPORT_OF avl_ad9144_xcvr.tx_data_3 +add_interface tx_sysref conduit end +set_interface_property tx_sysref EXPORT_OF avl_ad9144_xcvr.sysref +add_interface tx_sync conduit end +set_interface_property tx_sync EXPORT_OF avl_ad9144_xcvr.sync +add_connection avl_ad9144_xcvr.tx_phy_s_0 avl_ad9144_xcvr.tx_ip_s_0 +add_connection avl_ad9144_xcvr.tx_phy_s_1 avl_ad9144_xcvr.tx_ip_s_3 +add_connection avl_ad9144_xcvr.tx_phy_s_2 avl_ad9144_xcvr.tx_ip_s_1 +add_connection avl_ad9144_xcvr.tx_phy_s_3 avl_ad9144_xcvr.tx_ip_s_2 +add_connection avl_ad9144_xcvr.tx_ip_d_0 avl_ad9144_xcvr.tx_phy_d_0 +add_connection avl_ad9144_xcvr.tx_ip_d_3 avl_ad9144_xcvr.tx_phy_d_1 +add_connection avl_ad9144_xcvr.tx_ip_d_1 avl_ad9144_xcvr.tx_phy_d_2 +add_connection avl_ad9144_xcvr.tx_ip_d_2 avl_ad9144_xcvr.tx_phy_d_3 + +# ad9144-xcvr + +add_instance axi_ad9144_xcvr axi_adxcvr 1.0 +set_instance_parameter_value axi_ad9144_xcvr {ID} {0} +set_instance_parameter_value axi_ad9144_xcvr {TX_OR_RX_N} {1} +set_instance_parameter_value axi_ad9144_xcvr {NUM_OF_LANES} {4} + +add_connection sys_clk.clk axi_ad9144_xcvr.s_axi_clock +add_connection sys_clk.clk_reset axi_ad9144_xcvr.s_axi_reset +add_connection axi_ad9144_xcvr.if_up_rst avl_ad9144_xcvr.rst +add_connection avl_ad9144_xcvr.ready axi_ad9144_xcvr.ready +add_connection axi_ad9144_xcvr.core_pll_locked avl_ad9144_xcvr.core_pll_locked + +# ad9144-core + +add_instance axi_ad9144_core axi_ad9144 1.0 +set_instance_parameter_value axi_ad9144_core {QUAD_OR_DUAL_N} {0} + +add_connection avl_ad9144_xcvr.core_clk axi_ad9144_core.if_tx_clk +add_connection axi_ad9144_core.if_tx_data avl_ad9144_xcvr.ip_data +add_connection sys_clk.clk_reset axi_ad9144_core.s_axi_reset +add_connection sys_clk.clk axi_ad9144_core.s_axi_clock + +# ad9144-unpack + +add_instance util_ad9144_upack util_upack 1.0 +set_instance_parameter_value util_ad9144_upack {CHANNEL_DATA_WIDTH} {64} +set_instance_parameter_value util_ad9144_upack {NUM_OF_CHANNELS} {2} + +add_connection avl_ad9144_xcvr.core_clk util_ad9144_upack.if_dac_clk +add_connection axi_ad9144_core.dac_ch_0 util_ad9144_upack.dac_ch_0 +add_connection axi_ad9144_core.dac_ch_1 util_ad9144_upack.dac_ch_1 + +# ad9144-dma + +add_instance axi_ad9144_dma axi_dmac 1.0 +set_instance_parameter_value axi_ad9144_dma {DMA_DATA_WIDTH_SRC} {128} +set_instance_parameter_value axi_ad9144_dma {DMA_DATA_WIDTH_DEST} {128} +set_instance_parameter_value axi_ad9144_dma {DMA_2D_TRANSFER} {0} +set_instance_parameter_value axi_ad9144_dma {DMA_TYPE_DEST} {2} +set_instance_parameter_value axi_ad9144_dma {DMA_TYPE_SRC} {0} + +add_connection avl_ad9144_xcvr.core_clk axi_ad9144_dma.if_fifo_rd_clk +add_connection util_ad9144_upack.if_dac_valid axi_ad9144_dma.if_fifo_rd_en +add_connection util_ad9144_upack.if_dac_data axi_ad9144_dma.if_fifo_rd_dout +add_connection axi_ad9144_dma.if_fifo_rd_underflow axi_ad9144_core.if_dac_dunf +add_connection sys_clk.clk_reset axi_ad9144_dma.s_axi_reset +add_connection sys_clk.clk axi_ad9144_dma.s_axi_clock +add_connection sys_ddr3_cntrl.emif_usr_reset_n axi_ad9144_dma.m_src_axi_reset +add_connection sys_ddr3_cntrl.emif_usr_clk axi_ad9144_dma.m_src_axi_clock + +# ad9680-xcvr + +add_instance avl_ad9680_xcvr avl_adxcvr 1.0 +set_instance_parameter_value avl_ad9680_xcvr {ID} {1} +set_instance_parameter_value avl_ad9680_xcvr {TX_OR_RX_N} {0} +set_instance_parameter_value avl_ad9680_xcvr {PCS_CONFIG} {JESD_PCS_CFG2} +set_instance_parameter_value avl_ad9680_xcvr {LANE_RATE} {10000.0} +set_instance_parameter_value avl_ad9680_xcvr {PLLCLK_FREQUENCY} {5000.0} +set_instance_parameter_value avl_ad9680_xcvr {REFCLK_FREQUENCY} {500.0} +set_instance_parameter_value avl_ad9680_xcvr {CORECLK_FREQUENCY} {250.0} +set_instance_parameter_value avl_ad9680_xcvr {NUM_OF_LANES} {4} +set_instance_parameter_value avl_ad9680_xcvr {NUM_OF_CONVS} {2} +set_instance_parameter_value avl_ad9680_xcvr {FRM_BCNT} {1} +set_instance_parameter_value avl_ad9680_xcvr {FRM_SCNT} {1} +set_instance_parameter_value avl_ad9680_xcvr {MF_FCNT} {32} +set_instance_parameter_value avl_ad9680_xcvr {HD} {1} + +add_connection sys_clk.clk avl_ad9680_xcvr.sys_clk +add_connection sys_clk.clk_reset avl_ad9680_xcvr.sys_resetn +add_interface rx_ref_clk clock sink +set_interface_property rx_ref_clk EXPORT_OF avl_ad9680_xcvr.ref_clk +add_interface rx_data_0 conduit end +set_interface_property rx_data_0 EXPORT_OF avl_ad9680_xcvr.rx_data_0 +add_interface rx_data_1 conduit end +set_interface_property rx_data_1 EXPORT_OF avl_ad9680_xcvr.rx_data_1 +add_interface rx_data_2 conduit end +set_interface_property rx_data_2 EXPORT_OF avl_ad9680_xcvr.rx_data_2 +add_interface rx_data_3 conduit end +set_interface_property rx_data_3 EXPORT_OF avl_ad9680_xcvr.rx_data_3 +add_interface rx_sysref conduit end +set_interface_property rx_sysref EXPORT_OF avl_ad9680_xcvr.sysref +add_interface rx_sync conduit end +set_interface_property rx_sync EXPORT_OF avl_ad9680_xcvr.sync + +# ad9680-xcvr + +add_instance axi_ad9680_xcvr axi_adxcvr 1.0 +set_instance_parameter_value axi_ad9680_xcvr {ID} {1} +set_instance_parameter_value axi_ad9680_xcvr {TX_OR_RX_N} {0} +set_instance_parameter_value axi_ad9680_xcvr {NUM_OF_LANES} {4} + +add_connection sys_clk.clk axi_ad9680_xcvr.s_axi_clock +add_connection sys_clk.clk_reset axi_ad9680_xcvr.s_axi_reset +add_connection axi_ad9680_xcvr.if_up_rst avl_ad9680_xcvr.rst +add_connection avl_ad9680_xcvr.ready axi_ad9680_xcvr.ready +add_connection axi_ad9680_xcvr.core_pll_locked avl_ad9680_xcvr.core_pll_locked + +# ad9680 + +add_instance axi_ad9680_core axi_ad9680 1.0 + +add_connection avl_ad9680_xcvr.core_clk axi_ad9680_core.if_rx_clk +add_connection avl_ad9680_xcvr.ip_sof axi_ad9680_core.if_rx_sof +add_connection avl_ad9680_xcvr.ip_data axi_ad9680_core.if_rx_data +add_connection sys_clk.clk_reset axi_ad9680_core.s_axi_reset +add_connection sys_clk.clk axi_ad9680_core.s_axi_clock + +# ad9680-pack + +add_instance util_ad9680_cpack util_cpack 1.0 +set_instance_parameter_value util_ad9680_cpack {CHANNEL_DATA_WIDTH} {64} +set_instance_parameter_value util_ad9680_cpack {NUM_OF_CHANNELS} {2} + +add_connection sys_clk.clk_reset util_ad9680_cpack.if_adc_rst +add_connection sys_ddr3_cntrl.emif_usr_reset_n util_ad9680_cpack.if_adc_rst +add_connection avl_ad9680_xcvr.core_clk util_ad9680_cpack.if_adc_clk +add_connection axi_ad9680_core.adc_ch_0 util_ad9680_cpack.adc_ch_0 +add_connection axi_ad9680_core.adc_ch_1 util_ad9680_cpack.adc_ch_1 + +# ad9680-fifo + +add_instance ad9680_adcfifo util_adcfifo 1.0 +set_instance_parameter_value ad9680_adcfifo {ADC_DATA_WIDTH} {128} +set_instance_parameter_value ad9680_adcfifo {DMA_DATA_WIDTH} {128} +set_instance_parameter_value ad9680_adcfifo {DMA_ADDRESS_WIDTH} {16} + +add_connection sys_clk.clk_reset ad9680_adcfifo.if_adc_rst +add_connection sys_ddr3_cntrl.emif_usr_reset_n ad9680_adcfifo.if_adc_rst +add_connection avl_ad9680_xcvr.core_clk ad9680_adcfifo.if_adc_clk +add_connection util_ad9680_cpack.if_adc_valid ad9680_adcfifo.if_adc_wr +add_connection util_ad9680_cpack.if_adc_data ad9680_adcfifo.if_adc_wdata +add_connection sys_ddr3_cntrl.emif_usr_clk ad9680_adcfifo.if_dma_clk + +# ad9680-dma + +add_instance axi_ad9680_dma axi_dmac 1.0 +set_instance_parameter_value axi_ad9680_dma {DMA_DATA_WIDTH_SRC} {128} +set_instance_parameter_value axi_ad9680_dma {DMA_DATA_WIDTH_DEST} {128} +set_instance_parameter_value axi_ad9680_dma {DMA_LENGTH_WIDTH} {24} +set_instance_parameter_value axi_ad9680_dma {DMA_2D_TRANSFER} {0} +set_instance_parameter_value axi_ad9680_dma {SYNC_TRANSFER_START} {1} +set_instance_parameter_value axi_ad9680_dma {CYCLIC} {0} +set_instance_parameter_value axi_ad9680_dma {DMA_TYPE_DEST} {0} +set_instance_parameter_value axi_ad9680_dma {DMA_TYPE_SRC} {1} + +add_connection sys_ddr3_cntrl.emif_usr_clk axi_ad9680_dma.if_s_axis_aclk +add_connection ad9680_adcfifo.if_dma_wr axi_ad9680_dma.if_s_axis_valid +add_connection ad9680_adcfifo.if_dma_wdata axi_ad9680_dma.if_s_axis_data +add_connection ad9680_adcfifo.if_dma_wready axi_ad9680_dma.if_s_axis_ready +add_connection ad9680_adcfifo.if_dma_xfer_req axi_ad9680_dma.if_s_axis_xfer_req +add_connection ad9680_adcfifo.if_adc_wovf axi_ad9680_core.if_adc_dovf +add_connection sys_clk.clk_reset axi_ad9680_dma.s_axi_reset +add_connection sys_clk.clk axi_ad9680_dma.s_axi_clock +add_connection sys_ddr3_cntrl.emif_usr_reset_n axi_ad9680_dma.m_dest_axi_reset +add_connection sys_ddr3_cntrl.emif_usr_clk axi_ad9680_dma.m_dest_axi_clock + +# reconfig sharing + +add_instance avl_adxcfg_0 avl_adxcfg 1.0 +add_connection sys_clk.clk avl_adxcfg_0.rcfg_clk +add_connection sys_clk.clk_reset avl_adxcfg_0.rcfg_reset_n +add_connection avl_adxcfg_0.rcfg_m0 avl_ad9144_xcvr.phy_reconfig_0 +add_connection avl_adxcfg_0.rcfg_m1 avl_ad9680_xcvr.phy_reconfig_0 + +add_instance avl_adxcfg_1 avl_adxcfg 1.0 +add_connection sys_clk.clk avl_adxcfg_1.rcfg_clk +add_connection sys_clk.clk_reset avl_adxcfg_1.rcfg_reset_n +add_connection avl_adxcfg_1.rcfg_m0 avl_ad9144_xcvr.phy_reconfig_1 +add_connection avl_adxcfg_1.rcfg_m1 avl_ad9680_xcvr.phy_reconfig_1 + +add_instance avl_adxcfg_2 avl_adxcfg 1.0 +add_connection sys_clk.clk avl_adxcfg_2.rcfg_clk +add_connection sys_clk.clk_reset avl_adxcfg_2.rcfg_reset_n +add_connection avl_adxcfg_2.rcfg_m0 avl_ad9144_xcvr.phy_reconfig_2 +add_connection avl_adxcfg_2.rcfg_m1 avl_ad9680_xcvr.phy_reconfig_2 + +add_instance avl_adxcfg_3 avl_adxcfg 1.0 +add_connection sys_clk.clk avl_adxcfg_3.rcfg_clk +add_connection sys_clk.clk_reset avl_adxcfg_3.rcfg_reset_n +add_connection avl_adxcfg_3.rcfg_m0 avl_ad9144_xcvr.phy_reconfig_3 +add_connection avl_adxcfg_3.rcfg_m1 avl_ad9680_xcvr.phy_reconfig_3 + +# addresses + +ad_cpu_interconnect 0x10404000 avl_adxcfg_0.rcfg_s0 +ad_cpu_interconnect 0x10504000 avl_adxcfg_0.rcfg_s1 +ad_cpu_interconnect 0x10405000 avl_adxcfg_1.rcfg_s0 +ad_cpu_interconnect 0x10505000 avl_adxcfg_1.rcfg_s1 +ad_cpu_interconnect 0x10406000 avl_adxcfg_2.rcfg_s0 +ad_cpu_interconnect 0x10506000 avl_adxcfg_2.rcfg_s1 +ad_cpu_interconnect 0x10407000 avl_adxcfg_3.rcfg_s0 +ad_cpu_interconnect 0x10507000 avl_adxcfg_3.rcfg_s1 +ad_cpu_interconnect 0x10400000 avl_ad9144_xcvr.core_pll_reconfig +ad_cpu_interconnect 0x10402000 avl_ad9144_xcvr.lane_pll_reconfig +ad_cpu_interconnect 0x10401000 avl_ad9144_xcvr.ip_reconfig +ad_cpu_interconnect 0x1040c000 axi_ad9144_dma.s_axi +ad_cpu_interconnect 0x10410000 axi_ad9144_xcvr.s_axi +ad_cpu_interconnect 0x10420000 axi_ad9144_core.s_axi +ad_cpu_interconnect 0x10500000 avl_ad9680_xcvr.core_pll_reconfig +ad_cpu_interconnect 0x10501000 avl_ad9680_xcvr.ip_reconfig +ad_cpu_interconnect 0x1050c000 axi_ad9680_dma.s_axi +ad_cpu_interconnect 0x10510000 axi_ad9680_xcvr.s_axi +ad_cpu_interconnect 0x10520000 axi_ad9680_core.s_axi + +# dma interconnects + +ad_dma_interconnect axi_ad9144_dma.m_src_axi +ad_dma_interconnect axi_ad9680_dma.m_dest_axi + +# interrupts + +ad_cpu_interrupt 10 axi_ad9680_dma.interrupt_sender +ad_cpu_interrupt 11 axi_ad9144_dma.interrupt_sender diff --git a/projects/daq2/kc705/Makefile b/projects/daq2/kc705/Makefile index f5349f760..87955d895 100644 --- a/projects/daq2/kc705/Makefile +++ b/projects/daq2/kc705/Makefile @@ -14,19 +14,20 @@ M_DEPS += ../common/daq2_bd.tcl M_DEPS += ../../scripts/adi_project.tcl M_DEPS += ../../scripts/adi_env.tcl M_DEPS += ../../scripts/adi_board.tcl -M_DEPS += ../../common/xilinx/sys_dmafifo.tcl +M_DEPS += ../../common/xilinx/sys_dacfifo.tcl +M_DEPS += ../../common/xilinx/sys_adcfifo.tcl M_DEPS += ../../common/kc705/kc705_system_mig.prj M_DEPS += ../../common/kc705/kc705_system_constr.xdc M_DEPS += ../../common/kc705/kc705_system_bd.tcl -M_DEPS += ../../../library/common/ad_iobuf.v +M_DEPS += ../../../library/xilinx/common/ad_iobuf.v M_DEPS += ../../../library/axi_ad9144/axi_ad9144.xpr M_DEPS += ../../../library/axi_ad9680/axi_ad9680.xpr +M_DEPS += ../../../library/xilinx/axi_adxcvr/axi_adxcvr.xpr M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr -M_DEPS += ../../../library/axi_jesd_gt/axi_jesd_gt.xpr M_DEPS += ../../../library/util_adcfifo/util_adcfifo.xpr +M_DEPS += ../../../library/xilinx/util_adxcvr/util_adxcvr.xpr M_DEPS += ../../../library/util_cpack/util_cpack.xpr M_DEPS += ../../../library/util_dacfifo/util_dacfifo.xpr -M_DEPS += ../../../library/util_jesd_gt/util_jesd_gt.xpr M_DEPS += ../../../library/util_upack/util_upack.xpr M_VIVADO := vivado -mode batch -source @@ -43,6 +44,7 @@ M_FLIST += *.sdk M_FLIST += *.hw M_FLIST += *.sim M_FLIST += .Xil +M_FLIST += *.ip_user_files @@ -57,29 +59,29 @@ clean: clean-all:clean make -C ../../../library/axi_ad9144 clean make -C ../../../library/axi_ad9680 clean + make -C ../../../library/xilinx/axi_adxcvr clean make -C ../../../library/axi_dmac clean - make -C ../../../library/axi_jesd_gt clean make -C ../../../library/util_adcfifo clean + make -C ../../../library/xilinx/util_adxcvr clean make -C ../../../library/util_cpack clean make -C ../../../library/util_dacfifo clean - make -C ../../../library/util_jesd_gt clean make -C ../../../library/util_upack clean daq2_kc705.sdk/system_top.hdf: $(M_DEPS) - rm -rf $(M_FLIST) + -rm -rf $(M_FLIST) $(M_VIVADO) system_project.tcl >> daq2_kc705_vivado.log 2>&1 lib: make -C ../../../library/axi_ad9144 make -C ../../../library/axi_ad9680 + make -C ../../../library/xilinx/axi_adxcvr make -C ../../../library/axi_dmac - make -C ../../../library/axi_jesd_gt make -C ../../../library/util_adcfifo + make -C ../../../library/xilinx/util_adxcvr make -C ../../../library/util_cpack make -C ../../../library/util_dacfifo - make -C ../../../library/util_jesd_gt make -C ../../../library/util_upack #################################################################################### diff --git a/projects/daq2/kc705/system_bd.tcl b/projects/daq2/kc705/system_bd.tcl index a48f1b952..74324936a 100644 --- a/projects/daq2/kc705/system_bd.tcl +++ b/projects/daq2/kc705/system_bd.tcl @@ -1,8 +1,9 @@ source $ad_hdl_dir/projects/common/kc705/kc705_system_bd.tcl -source $ad_hdl_dir/projects/common/xilinx/sys_dmafifo.tcl +source $ad_hdl_dir/projects/common/xilinx/sys_adcfifo.tcl +source $ad_hdl_dir/projects/common/xilinx/sys_dacfifo.tcl -p_sys_dmafifo [current_bd_instance .] axi_ad9680_fifo 128 16 +p_sys_adcfifo [current_bd_instance .] axi_ad9680_fifo 128 16 p_sys_dacfifo [current_bd_instance .] axi_ad9144_fifo 128 10 source ../common/daq2_bd.tcl diff --git a/projects/daq2/kc705/system_constr.xdc b/projects/daq2/kc705/system_constr.xdc index c64d6aff5..841eaf030 100644 --- a/projects/daq2/kc705/system_constr.xdc +++ b/projects/daq2/kc705/system_constr.xdc @@ -56,5 +56,6 @@ set_property -dict {PACKAGE_PIN D28 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_po create_clock -name tx_ref_clk -period 2.00 [get_ports tx_ref_clk_p] create_clock -name rx_ref_clk -period 2.00 [get_ports rx_ref_clk_p] -create_clock -name tx_div_clk -period 4.00 [get_pins i_system_wrapper/system_i/axi_daq2_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/TXOUTCLK] -create_clock -name rx_div_clk -period 4.00 [get_pins i_system_wrapper/system_i/axi_daq2_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK] +create_clock -name tx_div_clk -period 4.00 [get_pins i_system_wrapper/system_i/util_daq2_xcvr/inst/i_xch_0/i_gtxe2_channel/TXOUTCLK] +create_clock -name rx_div_clk -period 4.00 [get_pins i_system_wrapper/system_i/util_daq2_xcvr/inst/i_xch_0/i_gtxe2_channel/RXOUTCLK] + diff --git a/projects/daq2/kc705/system_project.tcl b/projects/daq2/kc705/system_project.tcl index 41d22923e..607b24ec1 100644 --- a/projects/daq2/kc705/system_project.tcl +++ b/projects/daq2/kc705/system_project.tcl @@ -1,6 +1,4 @@ - - source ../../scripts/adi_env.tcl source $ad_hdl_dir/projects/scripts/adi_project.tcl source $ad_hdl_dir/projects/scripts/adi_board.tcl @@ -10,12 +8,9 @@ adi_project_files daq2_kc705 [list \ "../common/daq2_spi.v" \ "system_top.v" \ "system_constr.xdc"\ - "$ad_hdl_dir/library/common/ad_iobuf.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \ "$ad_hdl_dir/projects/common/kc705/kc705_system_constr.xdc" ] -set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/kc705/kc705_system_constr.xdc] -set_property PROCESSING_ORDER EARLY [get_files system_constr.xdc] - adi_project_run daq2_kc705 diff --git a/projects/daq2/kc705/system_top.v b/projects/daq2/kc705/system_top.v index b7595882b..aac500993 100644 --- a/projects/daq2/kc705/system_top.v +++ b/projects/daq2/kc705/system_top.v @@ -34,8 +34,6 @@ // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // *************************************************************************** // *************************************************************************** -// *************************************************************************** -// *************************************************************************** `timescale 1ns/100ps @@ -374,11 +372,17 @@ module system_top ( .mii_tx_clk (mii_tx_clk), .mii_tx_en (mii_tx_en), .mii_txd (mii_txd), - .rx_data_n (rx_data_n), - .rx_data_p (rx_data_p), - .rx_ref_clk (rx_ref_clk), - .rx_sync (rx_sync), - .rx_sysref (rx_sysref), + .rx_data_0_n (rx_data_n[0]), + .rx_data_0_p (rx_data_p[0]), + .rx_data_1_n (rx_data_n[1]), + .rx_data_1_p (rx_data_p[1]), + .rx_data_2_n (rx_data_n[2]), + .rx_data_2_p (rx_data_p[2]), + .rx_data_3_n (rx_data_n[3]), + .rx_data_3_p (rx_data_p[3]), + .rx_ref_clk_0 (rx_ref_clk), + .rx_sync_0 (rx_sync), + .rx_sysref_0 (rx_sysref), .spi_clk_i (spi_clk), .spi_clk_o (spi_clk), .spi_csn_i (spi_csn), @@ -389,11 +393,17 @@ module system_top ( .sys_clk_n (sys_clk_n), .sys_clk_p (sys_clk_p), .sys_rst (sys_rst), - .tx_data_n (tx_data_n), - .tx_data_p (tx_data_p), - .tx_ref_clk (tx_ref_clk), - .tx_sync (tx_sync), - .tx_sysref (tx_sysref), + .tx_data_0_n (tx_data_n[0]), + .tx_data_0_p (tx_data_p[0]), + .tx_data_1_n (tx_data_n[1]), + .tx_data_1_p (tx_data_p[1]), + .tx_data_2_n (tx_data_n[2]), + .tx_data_2_p (tx_data_p[2]), + .tx_data_3_n (tx_data_n[3]), + .tx_data_3_p (tx_data_p[3]), + .tx_ref_clk_0 (tx_ref_clk), + .tx_sync_0 (tx_sync), + .tx_sysref_0 (tx_sysref), .uart_sin (uart_sin), .uart_sout (uart_sout)); diff --git a/projects/daq2/kcu105/Makefile b/projects/daq2/kcu105/Makefile index 82e1efb04..30c090bd7 100644 --- a/projects/daq2/kcu105/Makefile +++ b/projects/daq2/kcu105/Makefile @@ -14,19 +14,19 @@ M_DEPS += ../common/daq2_bd.tcl M_DEPS += ../../scripts/adi_project.tcl M_DEPS += ../../scripts/adi_env.tcl M_DEPS += ../../scripts/adi_board.tcl -M_DEPS += ../../common/xilinx/sys_dmafifo.tcl -M_DEPS += ../../common/kcu105/kcu105_system_mig.tcl +M_DEPS += ../../common/xilinx/sys_dacfifo.tcl +M_DEPS += ../../common/xilinx/sys_adcfifo.tcl M_DEPS += ../../common/kcu105/kcu105_system_constr.xdc M_DEPS += ../../common/kcu105/kcu105_system_bd.tcl -M_DEPS += ../../../library/common/ad_iobuf.v +M_DEPS += ../../../library/xilinx/common/ad_iobuf.v M_DEPS += ../../../library/axi_ad9144/axi_ad9144.xpr M_DEPS += ../../../library/axi_ad9680/axi_ad9680.xpr +M_DEPS += ../../../library/xilinx/axi_adxcvr/axi_adxcvr.xpr M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr -M_DEPS += ../../../library/axi_jesd_gt/axi_jesd_gt.xpr M_DEPS += ../../../library/util_adcfifo/util_adcfifo.xpr +M_DEPS += ../../../library/xilinx/util_adxcvr/util_adxcvr.xpr M_DEPS += ../../../library/util_cpack/util_cpack.xpr M_DEPS += ../../../library/util_dacfifo/util_dacfifo.xpr -M_DEPS += ../../../library/util_jesd_gt/util_jesd_gt.xpr M_DEPS += ../../../library/util_upack/util_upack.xpr M_VIVADO := vivado -mode batch -source @@ -43,6 +43,7 @@ M_FLIST += *.sdk M_FLIST += *.hw M_FLIST += *.sim M_FLIST += .Xil +M_FLIST += *.ip_user_files @@ -57,29 +58,29 @@ clean: clean-all:clean make -C ../../../library/axi_ad9144 clean make -C ../../../library/axi_ad9680 clean + make -C ../../../library/xilinx/axi_adxcvr clean make -C ../../../library/axi_dmac clean - make -C ../../../library/axi_jesd_gt clean make -C ../../../library/util_adcfifo clean + make -C ../../../library/xilinx/util_adxcvr clean make -C ../../../library/util_cpack clean make -C ../../../library/util_dacfifo clean - make -C ../../../library/util_jesd_gt clean make -C ../../../library/util_upack clean daq2_kcu105.sdk/system_top.hdf: $(M_DEPS) - rm -rf $(M_FLIST) + -rm -rf $(M_FLIST) $(M_VIVADO) system_project.tcl >> daq2_kcu105_vivado.log 2>&1 lib: make -C ../../../library/axi_ad9144 make -C ../../../library/axi_ad9680 + make -C ../../../library/xilinx/axi_adxcvr make -C ../../../library/axi_dmac - make -C ../../../library/axi_jesd_gt make -C ../../../library/util_adcfifo + make -C ../../../library/xilinx/util_adxcvr make -C ../../../library/util_cpack make -C ../../../library/util_dacfifo - make -C ../../../library/util_jesd_gt make -C ../../../library/util_upack #################################################################################### diff --git a/projects/daq2/kcu105/system_bd.tcl b/projects/daq2/kcu105/system_bd.tcl index 2a34073a8..4305e3185 100644 --- a/projects/daq2/kcu105/system_bd.tcl +++ b/projects/daq2/kcu105/system_bd.tcl @@ -1,15 +1,16 @@ source $ad_hdl_dir/projects/common/kcu105/kcu105_system_bd.tcl -source $ad_hdl_dir/projects/common/xilinx/sys_dmafifo.tcl +source $ad_hdl_dir/projects/common/xilinx/sys_adcfifo.tcl +source $ad_hdl_dir/projects/common/xilinx/sys_dacfifo.tcl -p_sys_dmafifo [current_bd_instance .] axi_ad9680_fifo 128 16 +p_sys_adcfifo [current_bd_instance .] axi_ad9680_fifo 128 16 p_sys_dacfifo [current_bd_instance .] axi_ad9144_fifo 128 10 source ../common/daq2_bd.tcl -set_property -dict [list CONFIG.GTH_OR_GTX_N {1}] $axi_daq2_gt -set_property -dict [list CONFIG.QPLL0_FBDIV {20}] $axi_daq2_gt -set_property -dict [list CONFIG.QPLL0_REFCLK_DIV {1}] $axi_daq2_gt +set_property -dict [list CONFIG.XCVR_TYPE {1}] $util_daq2_xcvr +set_property -dict [list CONFIG.QPLL_FBDIV {20}] $util_daq2_xcvr +set_property -dict [list CONFIG.QPLL_REFCLK_DIV {1}] $util_daq2_xcvr set_property -dict [list CONFIG.S00_HAS_REGSLICE {4}] [get_bd_cells axi_mem_interconnect] set_property -dict [list CONFIG.S01_HAS_REGSLICE {4}] [get_bd_cells axi_mem_interconnect] diff --git a/projects/daq2/kcu105/system_constr.xdc b/projects/daq2/kcu105/system_constr.xdc index 44a8f125c..3d2bc6a53 100644 --- a/projects/daq2/kcu105/system_constr.xdc +++ b/projects/daq2/kcu105/system_constr.xdc @@ -40,8 +40,8 @@ set_property -dict {PACKAGE_PIN E8 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [g create_clock -name tx_ref_clk -period 2.00 [get_ports tx_ref_clk_p] create_clock -name rx_ref_clk -period 2.00 [get_ports rx_ref_clk_p] -create_clock -name tx_div_clk -period 4.00 [get_pins i_system_wrapper/system_i/axi_daq2_gt/inst/g_lane_1[0].i_channel/i_gt/i_gthe3_channel/TXOUTCLK] -create_clock -name rx_div_clk -period 4.00 [get_pins i_system_wrapper/system_i/axi_daq2_gt/inst/g_lane_1[0].i_channel/i_gt/i_gthe3_channel/RXOUTCLK] +create_clock -name tx_div_clk -period 4.00 [get_pins i_system_wrapper/system_i/util_daq2_xcvr/inst/i_xch_0/i_gthe3_channel/TXOUTCLK] +create_clock -name rx_div_clk -period 4.00 [get_pins i_system_wrapper/system_i/util_daq2_xcvr/inst/i_xch_0/i_gthe3_channel/RXOUTCLK] # gt pin assignments below are for reference only and are ignored by the tool! @@ -62,8 +62,11 @@ create_clock -name rx_div_clk -period 4.00 [get_pins i_system_wrapper/system_ ## set_property -dict {PACKAGE_PIN D6} [get_ports tx_data_p[3]] ; ## A22 FMC_HPC_DP1_C2M_P (tx_data_p[2]) ## set_property -dict {PACKAGE_PIN D5} [get_ports tx_data_n[3]] ; ## A23 FMC_HPC_DP1_C2M_N (tx_data_n[2]) -set_property LOC GTHE3_CHANNEL_X0Y19 [get_cells -hierarchical -filter {NAME =~ *axi_daq2_gt/inst/g_lane_1[0].i_channel/i_gt/i_gthe3_channel}] -set_property LOC GTHE3_CHANNEL_X0Y16 [get_cells -hierarchical -filter {NAME =~ *axi_daq2_gt/inst/g_lane_1[1].i_channel/i_gt/i_gthe3_channel}] -set_property LOC GTHE3_CHANNEL_X0Y18 [get_cells -hierarchical -filter {NAME =~ *axi_daq2_gt/inst/g_lane_1[2].i_channel/i_gt/i_gthe3_channel}] -set_property LOC GTHE3_CHANNEL_X0Y17 [get_cells -hierarchical -filter {NAME =~ *axi_daq2_gt/inst/g_lane_1[3].i_channel/i_gt/i_gthe3_channel}] +set_property LOC GTHE3_CHANNEL_X0Y19 [get_cells -hierarchical -filter {NAME =~ *util_daq2_xcvr/inst/i_xch_0/i_gthe3_channel}] +set_property LOC GTHE3_CHANNEL_X0Y16 [get_cells -hierarchical -filter {NAME =~ *util_daq2_xcvr/inst/i_xch_1/i_gthe3_channel}] +set_property LOC GTHE3_CHANNEL_X0Y18 [get_cells -hierarchical -filter {NAME =~ *util_daq2_xcvr/inst/i_xch_2/i_gthe3_channel}] +set_property LOC GTHE3_CHANNEL_X0Y17 [get_cells -hierarchical -filter {NAME =~ *util_daq2_xcvr/inst/i_xch_3/i_gthe3_channel}] + +set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9144_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]] +set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9680_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]] diff --git a/projects/daq2/kcu105/system_project.tcl b/projects/daq2/kcu105/system_project.tcl index 07f695b59..ad3fad935 100644 --- a/projects/daq2/kcu105/system_project.tcl +++ b/projects/daq2/kcu105/system_project.tcl @@ -1,6 +1,4 @@ - - source ../../scripts/adi_env.tcl source $ad_hdl_dir/projects/scripts/adi_project.tcl source $ad_hdl_dir/projects/scripts/adi_board.tcl @@ -10,7 +8,7 @@ adi_project_files daq2_kcu105 [list \ "../common/daq2_spi.v" \ "system_top.v" \ "system_constr.xdc"\ - "$ad_hdl_dir/library/common/ad_iobuf.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \ "$ad_hdl_dir/projects/common/kcu105/kcu105_system_constr.xdc" ] adi_project_run daq2_kcu105 diff --git a/projects/daq2/kcu105/system_top.v b/projects/daq2/kcu105/system_top.v index fbf439919..46331eaa8 100644 --- a/projects/daq2/kcu105/system_top.v +++ b/projects/daq2/kcu105/system_top.v @@ -34,8 +34,6 @@ // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // *************************************************************************** // *************************************************************************** -// *************************************************************************** -// *************************************************************************** `timescale 1ns/100ps @@ -326,11 +324,17 @@ module system_top ( .phy_clk_clk_p (phy_clk_p), .phy_rst_n (phy_rst_n), .phy_sd (1'b1), - .rx_data_n (rx_data_n), - .rx_data_p (rx_data_p), - .rx_ref_clk (rx_ref_clk), - .rx_sync (rx_sync), - .rx_sysref (rx_sysref), + .rx_data_0_n (rx_data_n[0]), + .rx_data_0_p (rx_data_p[0]), + .rx_data_1_n (rx_data_n[1]), + .rx_data_1_p (rx_data_p[1]), + .rx_data_2_n (rx_data_n[2]), + .rx_data_2_p (rx_data_p[2]), + .rx_data_3_n (rx_data_n[3]), + .rx_data_3_p (rx_data_p[3]), + .rx_ref_clk_0 (rx_ref_clk), + .rx_sync_0 (rx_sync), + .rx_sysref_0 (rx_sysref), .sgmii_rxn (phy_rx_n), .sgmii_rxp (phy_rx_p), .sgmii_txn (phy_tx_n), @@ -345,11 +349,17 @@ module system_top ( .sys_clk_clk_n (sys_clk_n), .sys_clk_clk_p (sys_clk_p), .sys_rst (sys_rst), - .tx_data_n (tx_data_n), - .tx_data_p (tx_data_p), - .tx_ref_clk (tx_ref_clk), - .tx_sync (tx_sync), - .tx_sysref (tx_sysref), + .tx_data_0_n (tx_data_n[0]), + .tx_data_0_p (tx_data_p[0]), + .tx_data_1_n (tx_data_n[1]), + .tx_data_1_p (tx_data_p[1]), + .tx_data_2_n (tx_data_n[2]), + .tx_data_2_p (tx_data_p[2]), + .tx_data_3_n (tx_data_n[3]), + .tx_data_3_p (tx_data_p[3]), + .tx_ref_clk_0 (tx_ref_clk), + .tx_sync_0 (tx_sync), + .tx_sysref_0 (tx_sysref), .uart_sin (uart_sin), .uart_sout (uart_sout)); diff --git a/projects/daq2/vc707/Makefile b/projects/daq2/vc707/Makefile index 879592ecc..d134fec7a 100644 --- a/projects/daq2/vc707/Makefile +++ b/projects/daq2/vc707/Makefile @@ -14,19 +14,20 @@ M_DEPS += ../common/daq2_bd.tcl M_DEPS += ../../scripts/adi_project.tcl M_DEPS += ../../scripts/adi_env.tcl M_DEPS += ../../scripts/adi_board.tcl -M_DEPS += ../../common/xilinx/sys_dmafifo.tcl +M_DEPS += ../../common/xilinx/sys_dacfifo.tcl +M_DEPS += ../../common/xilinx/sys_adcfifo.tcl M_DEPS += ../../common/vc707/vc707_system_mig.prj M_DEPS += ../../common/vc707/vc707_system_constr.xdc M_DEPS += ../../common/vc707/vc707_system_bd.tcl -M_DEPS += ../../../library/common/ad_iobuf.v +M_DEPS += ../../../library/xilinx/common/ad_iobuf.v M_DEPS += ../../../library/axi_ad9144/axi_ad9144.xpr M_DEPS += ../../../library/axi_ad9680/axi_ad9680.xpr +M_DEPS += ../../../library/xilinx/axi_adxcvr/axi_adxcvr.xpr M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr -M_DEPS += ../../../library/axi_jesd_gt/axi_jesd_gt.xpr M_DEPS += ../../../library/util_adcfifo/util_adcfifo.xpr +M_DEPS += ../../../library/xilinx/util_adxcvr/util_adxcvr.xpr M_DEPS += ../../../library/util_cpack/util_cpack.xpr M_DEPS += ../../../library/util_dacfifo/util_dacfifo.xpr -M_DEPS += ../../../library/util_jesd_gt/util_jesd_gt.xpr M_DEPS += ../../../library/util_upack/util_upack.xpr M_VIVADO := vivado -mode batch -source @@ -43,6 +44,7 @@ M_FLIST += *.sdk M_FLIST += *.hw M_FLIST += *.sim M_FLIST += .Xil +M_FLIST += *.ip_user_files @@ -57,29 +59,29 @@ clean: clean-all:clean make -C ../../../library/axi_ad9144 clean make -C ../../../library/axi_ad9680 clean + make -C ../../../library/xilinx/axi_adxcvr clean make -C ../../../library/axi_dmac clean - make -C ../../../library/axi_jesd_gt clean make -C ../../../library/util_adcfifo clean + make -C ../../../library/xilinx/util_adxcvr clean make -C ../../../library/util_cpack clean make -C ../../../library/util_dacfifo clean - make -C ../../../library/util_jesd_gt clean make -C ../../../library/util_upack clean daq2_vc707.sdk/system_top.hdf: $(M_DEPS) - rm -rf $(M_FLIST) + -rm -rf $(M_FLIST) $(M_VIVADO) system_project.tcl >> daq2_vc707_vivado.log 2>&1 lib: make -C ../../../library/axi_ad9144 make -C ../../../library/axi_ad9680 + make -C ../../../library/xilinx/axi_adxcvr make -C ../../../library/axi_dmac - make -C ../../../library/axi_jesd_gt make -C ../../../library/util_adcfifo + make -C ../../../library/xilinx/util_adxcvr make -C ../../../library/util_cpack make -C ../../../library/util_dacfifo - make -C ../../../library/util_jesd_gt make -C ../../../library/util_upack #################################################################################### diff --git a/projects/daq2/vc707/system_bd.tcl b/projects/daq2/vc707/system_bd.tcl index 8c4a257c2..9863621d0 100644 --- a/projects/daq2/vc707/system_bd.tcl +++ b/projects/daq2/vc707/system_bd.tcl @@ -1,8 +1,9 @@ source $ad_hdl_dir/projects/common/vc707/vc707_system_bd.tcl -source $ad_hdl_dir/projects/common/xilinx/sys_dmafifo.tcl +source $ad_hdl_dir/projects/common/xilinx/sys_adcfifo.tcl +source $ad_hdl_dir/projects/common/xilinx/sys_dacfifo.tcl -p_sys_dmafifo [current_bd_instance .] axi_ad9680_fifo 128 16 +p_sys_adcfifo [current_bd_instance .] axi_ad9680_fifo 128 16 p_sys_dacfifo [current_bd_instance .] axi_ad9144_fifo 128 10 source ../common/daq2_bd.tcl diff --git a/projects/daq2/vc707/system_constr.xdc b/projects/daq2/vc707/system_constr.xdc index 3b7af5d89..c667046e4 100644 --- a/projects/daq2/vc707/system_constr.xdc +++ b/projects/daq2/vc707/system_constr.xdc @@ -56,6 +56,6 @@ set_property -dict {PACKAGE_PIN G42 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports create_clock -name tx_ref_clk -period 2.00 [get_ports tx_ref_clk_p] create_clock -name rx_ref_clk -period 2.00 [get_ports rx_ref_clk_p] -create_clock -name tx_div_clk -period 4.00 [get_pins i_system_wrapper/system_i/axi_daq2_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/TXOUTCLK] -create_clock -name rx_div_clk -period 4.00 [get_pins i_system_wrapper/system_i/axi_daq2_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK] +create_clock -name tx_div_clk -period 4.00 [get_pins i_system_wrapper/system_i/util_daq2_xcvr/inst/i_xch_0/i_gtxe2_channel/TXOUTCLK] +create_clock -name rx_div_clk -period 4.00 [get_pins i_system_wrapper/system_i/util_daq2_xcvr/inst/i_xch_0/i_gtxe2_channel/RXOUTCLK] diff --git a/projects/daq2/vc707/system_project.tcl b/projects/daq2/vc707/system_project.tcl index cff763141..1009755ba 100644 --- a/projects/daq2/vc707/system_project.tcl +++ b/projects/daq2/vc707/system_project.tcl @@ -1,6 +1,4 @@ - - source ../../scripts/adi_env.tcl source $ad_hdl_dir/projects/scripts/adi_project.tcl source $ad_hdl_dir/projects/scripts/adi_board.tcl @@ -10,12 +8,9 @@ adi_project_files daq2_vc707 [list \ "../common/daq2_spi.v" \ "system_top.v" \ "system_constr.xdc"\ - "$ad_hdl_dir/library/common/ad_iobuf.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \ "$ad_hdl_dir/projects/common/vc707/vc707_system_constr.xdc" ] -set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/vc707/vc707_system_constr.xdc] -set_property PROCESSING_ORDER EARLY [get_files system_constr.xdc] - adi_project_run daq2_vc707 diff --git a/projects/daq2/vc707/system_top.v b/projects/daq2/vc707/system_top.v index 79de46271..ad633cc7f 100644 --- a/projects/daq2/vc707/system_top.v +++ b/projects/daq2/vc707/system_top.v @@ -354,11 +354,17 @@ module system_top ( .mgt_clk_clk_p (mgt_clk_p), .phy_rstn (phy_rstn), .phy_sd (1'b1), - .rx_data_n (rx_data_n), - .rx_data_p (rx_data_p), - .rx_ref_clk (rx_ref_clk), - .rx_sync (rx_sync), - .rx_sysref (rx_sysref), + .rx_data_0_n (rx_data_n[0]), + .rx_data_0_p (rx_data_p[0]), + .rx_data_1_n (rx_data_n[1]), + .rx_data_1_p (rx_data_p[1]), + .rx_data_2_n (rx_data_n[2]), + .rx_data_2_p (rx_data_p[2]), + .rx_data_3_n (rx_data_n[3]), + .rx_data_3_p (rx_data_p[3]), + .rx_ref_clk_0 (rx_ref_clk), + .rx_sync_0 (rx_sync), + .rx_sysref_0 (rx_sysref), .sgmii_rxn (sgmii_rxn), .sgmii_rxp (sgmii_rxp), .sgmii_txn (sgmii_txn), @@ -373,11 +379,17 @@ module system_top ( .sys_clk_n (sys_clk_n), .sys_clk_p (sys_clk_p), .sys_rst (sys_rst), - .tx_data_n (tx_data_n), - .tx_data_p (tx_data_p), - .tx_ref_clk (tx_ref_clk), - .tx_sync (tx_sync), - .tx_sysref (tx_sysref), + .tx_data_0_n (tx_data_n[0]), + .tx_data_0_p (tx_data_p[0]), + .tx_data_1_n (tx_data_n[1]), + .tx_data_1_p (tx_data_p[1]), + .tx_data_2_n (tx_data_n[2]), + .tx_data_2_p (tx_data_p[2]), + .tx_data_3_n (tx_data_n[3]), + .tx_data_3_p (tx_data_p[3]), + .tx_ref_clk_0 (tx_ref_clk), + .tx_sync_0 (tx_sync), + .tx_sysref_0 (tx_sysref), .uart_sin (uart_sin), .uart_sout (uart_sout)); diff --git a/projects/daq2/zc706/Makefile b/projects/daq2/zc706/Makefile index 14e469a0c..2f5448e0e 100644 --- a/projects/daq2/zc706/Makefile +++ b/projects/daq2/zc706/Makefile @@ -14,25 +14,24 @@ M_DEPS += ../common/daq2_bd.tcl M_DEPS += ../../scripts/adi_project.tcl M_DEPS += ../../scripts/adi_env.tcl M_DEPS += ../../scripts/adi_board.tcl -M_DEPS += ../../common/zc706/zc706_system_plddr3.tcl +M_DEPS += ../../common/zc706/zc706_system_plddr3_adcfifo.tcl M_DEPS += ../../common/zc706/zc706_system_mig_constr.xdc M_DEPS += ../../common/zc706/zc706_system_mig.prj M_DEPS += ../../common/zc706/zc706_system_constr.xdc M_DEPS += ../../common/zc706/zc706_system_bd.tcl -M_DEPS += ../../common/xilinx/sys_dmafifo.tcl -M_DEPS += ../../../library/common/ad_iobuf.v +M_DEPS += ../../common/xilinx/sys_dacfifo.tcl +M_DEPS += ../../../library/xilinx/common/ad_iobuf.v M_DEPS += ../../../library/axi_ad9144/axi_ad9144.xpr M_DEPS += ../../../library/axi_ad9680/axi_ad9680.xpr -M_DEPS += ../../../library/axi_adcfifo/axi_adcfifo.xpr +M_DEPS += ../../../library/xilinx/axi_adcfifo/axi_adcfifo.xpr +M_DEPS += ../../../library/xilinx/axi_adxcvr/axi_adxcvr.xpr M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr -M_DEPS += ../../../library/axi_jesd_gt/axi_jesd_gt.xpr M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr -M_DEPS += ../../../library/util_adcfifo/util_adcfifo.xpr +M_DEPS += ../../../library/xilinx/util_adxcvr/util_adxcvr.xpr M_DEPS += ../../../library/util_cpack/util_cpack.xpr M_DEPS += ../../../library/util_dacfifo/util_dacfifo.xpr -M_DEPS += ../../../library/util_jesd_gt/util_jesd_gt.xpr M_DEPS += ../../../library/util_upack/util_upack.xpr M_VIVADO := vivado -mode batch -source @@ -49,6 +48,7 @@ M_FLIST += *.sdk M_FLIST += *.hw M_FLIST += *.sim M_FLIST += .Xil +M_FLIST += *.ip_user_files @@ -63,37 +63,35 @@ clean: clean-all:clean make -C ../../../library/axi_ad9144 clean make -C ../../../library/axi_ad9680 clean - make -C ../../../library/axi_adcfifo clean + make -C ../../../library/xilinx/axi_adcfifo clean + make -C ../../../library/xilinx/axi_adxcvr clean make -C ../../../library/axi_clkgen clean make -C ../../../library/axi_dmac clean make -C ../../../library/axi_hdmi_tx clean - make -C ../../../library/axi_jesd_gt clean make -C ../../../library/axi_spdif_tx clean - make -C ../../../library/util_adcfifo clean + make -C ../../../library/xilinx/util_adxcvr clean make -C ../../../library/util_cpack clean make -C ../../../library/util_dacfifo clean - make -C ../../../library/util_jesd_gt clean make -C ../../../library/util_upack clean daq2_zc706.sdk/system_top.hdf: $(M_DEPS) - rm -rf $(M_FLIST) + -rm -rf $(M_FLIST) $(M_VIVADO) system_project.tcl >> daq2_zc706_vivado.log 2>&1 lib: make -C ../../../library/axi_ad9144 make -C ../../../library/axi_ad9680 - make -C ../../../library/axi_adcfifo + make -C ../../../library/xilinx/axi_adcfifo + make -C ../../../library/xilinx/axi_adxcvr make -C ../../../library/axi_clkgen make -C ../../../library/axi_dmac make -C ../../../library/axi_hdmi_tx - make -C ../../../library/axi_jesd_gt make -C ../../../library/axi_spdif_tx - make -C ../../../library/util_adcfifo + make -C ../../../library/xilinx/util_adxcvr make -C ../../../library/util_cpack make -C ../../../library/util_dacfifo - make -C ../../../library/util_jesd_gt make -C ../../../library/util_upack #################################################################################### diff --git a/projects/daq2/zc706/system_bd.tcl b/projects/daq2/zc706/system_bd.tcl index 0d7b97711..3e588e70f 100644 --- a/projects/daq2/zc706/system_bd.tcl +++ b/projects/daq2/zc706/system_bd.tcl @@ -1,10 +1,10 @@ source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl -source $ad_hdl_dir/projects/common/zc706/zc706_system_plddr3.tcl -source $ad_hdl_dir/projects/common/xilinx/sys_dmafifo.tcl +source $ad_hdl_dir/projects/common/zc706/zc706_system_plddr3_adcfifo.tcl +source $ad_hdl_dir/projects/common/xilinx/sys_dacfifo.tcl -p_plddr3_fifo [current_bd_instance .] axi_ad9680_fifo 128 -p_sys_dacfifo [current_bd_instance .] axi_ad9144_fifo 128 10 +p_sys_dacfifo [current_bd_instance .] axi_ad9144_fifo 128 16 +p_plddr3_adcfifo [current_bd_instance .] axi_ad9680_fifo 128 create_bd_port -dir I -type rst sys_rst create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr3 diff --git a/projects/daq2/zc706/system_constr.xdc b/projects/daq2/zc706/system_constr.xdc index df68021e6..fd3ddf448 100644 --- a/projects/daq2/zc706/system_constr.xdc +++ b/projects/daq2/zc706/system_constr.xdc @@ -56,6 +56,6 @@ set_property -dict {PACKAGE_PIN AJ24 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ create_clock -name tx_ref_clk -period 2.00 [get_ports tx_ref_clk_p] create_clock -name rx_ref_clk -period 2.00 [get_ports rx_ref_clk_p] -create_clock -name tx_div_clk -period 4.00 [get_pins i_system_wrapper/system_i/axi_daq2_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/TXOUTCLK] -create_clock -name rx_div_clk -period 4.00 [get_pins i_system_wrapper/system_i/axi_daq2_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK] +create_clock -name tx_div_clk -period 4.00 [get_pins i_system_wrapper/system_i/util_daq2_xcvr/inst/i_xch_0/i_gtxe2_channel/TXOUTCLK] +create_clock -name rx_div_clk -period 4.00 [get_pins i_system_wrapper/system_i/util_daq2_xcvr/inst/i_xch_0/i_gtxe2_channel/RXOUTCLK] diff --git a/projects/daq2/zc706/system_project.tcl b/projects/daq2/zc706/system_project.tcl index 8d6209938..b9723d97e 100644 --- a/projects/daq2/zc706/system_project.tcl +++ b/projects/daq2/zc706/system_project.tcl @@ -1,6 +1,4 @@ - - source ../../scripts/adi_env.tcl source $ad_hdl_dir/projects/scripts/adi_project.tcl source $ad_hdl_dir/projects/scripts/adi_board.tcl @@ -10,13 +8,10 @@ adi_project_files daq2_zc706 [list \ "../common/daq2_spi.v" \ "system_top.v" \ "system_constr.xdc"\ - "$ad_hdl_dir/library/common/ad_iobuf.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \ "$ad_hdl_dir/projects/common/zc706/zc706_system_mig_constr.xdc" \ "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ] -set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc] -set_property PROCESSING_ORDER EARLY [get_files system_constr.xdc] - adi_project_run daq2_zc706 diff --git a/projects/daq2/zc706/system_top.v b/projects/daq2/zc706/system_top.v index 071300f3a..e9f01032c 100644 --- a/projects/daq2/zc706/system_top.v +++ b/projects/daq2/zc706/system_top.v @@ -34,8 +34,6 @@ // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // *************************************************************************** // *************************************************************************** -// *************************************************************************** -// *************************************************************************** `timescale 1ns/100ps @@ -386,11 +384,17 @@ module system_top ( .ps_intr_09 (1'b0), .ps_intr_10 (1'b0), .ps_intr_11 (1'b0), - .rx_data_n (rx_data_n), - .rx_data_p (rx_data_p), - .rx_ref_clk (rx_ref_clk), - .rx_sync (rx_sync), - .rx_sysref (rx_sysref), + .rx_data_0_n (rx_data_n[0]), + .rx_data_0_p (rx_data_p[0]), + .rx_data_1_n (rx_data_n[1]), + .rx_data_1_p (rx_data_p[1]), + .rx_data_2_n (rx_data_n[2]), + .rx_data_2_p (rx_data_p[2]), + .rx_data_3_n (rx_data_n[3]), + .rx_data_3_p (rx_data_p[3]), + .rx_ref_clk_0 (rx_ref_clk), + .rx_sync_0 (rx_sync), + .rx_sysref_0 (rx_sysref), .spdif (spdif), .spi0_clk_i (spi0_clk), .spi0_clk_o (spi0_clk), @@ -413,11 +417,17 @@ module system_top ( .sys_clk_clk_n (sys_clk_n), .sys_clk_clk_p (sys_clk_p), .sys_rst (sys_rst), - .tx_data_n (tx_data_n), - .tx_data_p (tx_data_p), - .tx_ref_clk (tx_ref_clk), - .tx_sync (tx_sync), - .tx_sysref (tx_sysref)); + .tx_data_0_n (tx_data_n[0]), + .tx_data_0_p (tx_data_p[0]), + .tx_data_1_n (tx_data_n[1]), + .tx_data_1_p (tx_data_p[1]), + .tx_data_2_n (tx_data_n[2]), + .tx_data_2_p (tx_data_p[2]), + .tx_data_3_n (tx_data_n[3]), + .tx_data_3_p (tx_data_p[3]), + .tx_ref_clk_0 (tx_ref_clk), + .tx_sync_0 (tx_sync), + .tx_sysref_0 (tx_sysref)); endmodule diff --git a/projects/daq2/zcu102/Makefile b/projects/daq2/zcu102/Makefile new file mode 100644 index 000000000..72ff9fbcd --- /dev/null +++ b/projects/daq2/zcu102/Makefile @@ -0,0 +1,87 @@ +#################################################################################### +#################################################################################### +## Copyright 2011(c) Analog Devices, Inc. +## Auto-generated, do not modify! +#################################################################################### +#################################################################################### + +M_DEPS += system_top.v +M_DEPS += system_project.tcl +M_DEPS += system_constr.xdc +M_DEPS += system_bd.tcl +M_DEPS += ../common/daq2_spi.v +M_DEPS += ../common/daq2_bd.tcl +M_DEPS += ../../scripts/adi_project.tcl +M_DEPS += ../../scripts/adi_env.tcl +M_DEPS += ../../scripts/adi_board.tcl +M_DEPS += ../../common/zcu102/zcu102_system_constr.xdc +M_DEPS += ../../common/zcu102/zcu102_system_bd.tcl +M_DEPS += ../../common/xilinx/sys_dacfifo.tcl +M_DEPS += ../../common/xilinx/sys_adcfifo.tcl +M_DEPS += ../../../library/xilinx/common/ad_iobuf.v +M_DEPS += ../../../library/axi_ad9144/axi_ad9144.xpr +M_DEPS += ../../../library/axi_ad9680/axi_ad9680.xpr +M_DEPS += ../../../library/xilinx/axi_adxcvr/axi_adxcvr.xpr +M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr +M_DEPS += ../../../library/util_adcfifo/util_adcfifo.xpr +M_DEPS += ../../../library/xilinx/util_adxcvr/util_adxcvr.xpr +M_DEPS += ../../../library/util_cpack/util_cpack.xpr +M_DEPS += ../../../library/util_dacfifo/util_dacfifo.xpr +M_DEPS += ../../../library/util_upack/util_upack.xpr + +M_VIVADO := vivado -mode batch -source + +M_FLIST := *.cache +M_FLIST += *.data +M_FLIST += *.xpr +M_FLIST += *.log +M_FLIST += *.jou +M_FLIST += xgui +M_FLIST += *.runs +M_FLIST += *.srcs +M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim +M_FLIST += .Xil +M_FLIST += *.ip_user_files + + + +.PHONY: all lib clean clean-all +all: lib daq2_zcu102.sdk/system_top.hdf + + +clean: + rm -rf $(M_FLIST) + + +clean-all:clean + make -C ../../../library/axi_ad9144 clean + make -C ../../../library/axi_ad9680 clean + make -C ../../../library/xilinx/axi_adxcvr clean + make -C ../../../library/axi_dmac clean + make -C ../../../library/util_adcfifo clean + make -C ../../../library/xilinx/util_adxcvr clean + make -C ../../../library/util_cpack clean + make -C ../../../library/util_dacfifo clean + make -C ../../../library/util_upack clean + + +daq2_zcu102.sdk/system_top.hdf: $(M_DEPS) + -rm -rf $(M_FLIST) + $(M_VIVADO) system_project.tcl >> daq2_zcu102_vivado.log 2>&1 + + +lib: + make -C ../../../library/axi_ad9144 + make -C ../../../library/axi_ad9680 + make -C ../../../library/xilinx/axi_adxcvr + make -C ../../../library/axi_dmac + make -C ../../../library/util_adcfifo + make -C ../../../library/xilinx/util_adxcvr + make -C ../../../library/util_cpack + make -C ../../../library/util_dacfifo + make -C ../../../library/util_upack + +#################################################################################### +#################################################################################### diff --git a/projects/daq2/zcu102/system_bd.tcl b/projects/daq2/zcu102/system_bd.tcl new file mode 100644 index 000000000..84f00d318 --- /dev/null +++ b/projects/daq2/zcu102/system_bd.tcl @@ -0,0 +1,14 @@ + +source $ad_hdl_dir/projects/common/zcu102/zcu102_system_bd.tcl +source $ad_hdl_dir/projects/common/xilinx/sys_adcfifo.tcl +source $ad_hdl_dir/projects/common/xilinx/sys_dacfifo.tcl + +p_sys_adcfifo [current_bd_instance .] axi_ad9680_fifo 128 16 +p_sys_dacfifo [current_bd_instance .] axi_ad9144_fifo 128 10 + +source ../common/daq2_bd.tcl + +set_property -dict [list CONFIG.XCVR_TYPE {2}] $util_daq2_xcvr +set_property -dict [list CONFIG.QPLL_FBDIV {20}] $util_daq2_xcvr +set_property -dict [list CONFIG.QPLL_REFCLK_DIV {1}] $util_daq2_xcvr + diff --git a/projects/daq2/zcu102/system_constr.xdc b/projects/daq2/zcu102/system_constr.xdc new file mode 100644 index 000000000..3763f1963 --- /dev/null +++ b/projects/daq2/zcu102/system_constr.xdc @@ -0,0 +1,70 @@ + +# daq2 + +set_property -dict {PACKAGE_PIN L8} [get_ports rx_ref_clk_p] ; ## B20 FMC_HPC_GBTCLK1_M2C_P +set_property -dict {PACKAGE_PIN L7} [get_ports rx_ref_clk_n] ; ## B21 FMC_HPC_GBTCLK1_M2C_N +set_property -dict {PACKAGE_PIN W2 IOSTANDARD LVDS} [get_ports rx_sync_p] ; ## D08 FMC_HPC_LA01_CC_P +set_property -dict {PACKAGE_PIN W1 IOSTANDARD LVDS} [get_ports rx_sync_n] ; ## D09 FMC_HPC_LA01_CC_N +set_property -dict {PACKAGE_PIN Y2 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports rx_sysref_p] ; ## G09 FMC_HPC_LA03_P +set_property -dict {PACKAGE_PIN Y1 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports rx_sysref_n] ; ## G10 FMC_HPC_LA03_N + +set_property -dict {PACKAGE_PIN G8} [get_ports tx_ref_clk_p] ; ## D04 FMC_HPC_GBTCLK0_M2C_P +set_property -dict {PACKAGE_PIN G7} [get_ports tx_ref_clk_n] ; ## D05 FMC_HPC_GBTCLK0_M2C_N +set_property -dict {PACKAGE_PIN V2 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports tx_sync_p] ; ## H07 FMC_HPC_LA02_P +set_property -dict {PACKAGE_PIN V1 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports tx_sync_n] ; ## H08 FMC_HPC_LA02_N +set_property -dict {PACKAGE_PIN AA2 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports tx_sysref_p] ; ## H10 FMC_HPC_LA04_P +set_property -dict {PACKAGE_PIN AA1 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports tx_sysref_n] ; ## H11 FMC_HPC_LA04_N + +set_property -dict {PACKAGE_PIN AB3 IOSTANDARD LVCMOS18} [get_ports spi_csn_clk] ; ## D11 FMC_HPC_LA05_P +set_property -dict {PACKAGE_PIN W5 IOSTANDARD LVCMOS18} [get_ports spi_csn_dac] ; ## C14 FMC_HPC_LA10_P +set_property -dict {PACKAGE_PIN AC4 IOSTANDARD LVCMOS18} [get_ports spi_csn_adc] ; ## D15 FMC_HPC_LA09_N +set_property -dict {PACKAGE_PIN AC3 IOSTANDARD LVCMOS18} [get_ports spi_clk] ; ## D12 FMC_HPC_LA05_N +set_property -dict {PACKAGE_PIN AB4 IOSTANDARD LVCMOS18} [get_ports spi_sdio] ; ## D14 FMC_HPC_LA09_P +set_property -dict {PACKAGE_PIN V3 IOSTANDARD LVCMOS18} [get_ports spi_dir] ; ## G13 FMC_HPC_LA08_N + +set_property -dict {PACKAGE_PIN V4 IOSTANDARD LVCMOS18} [get_ports clkd_sync] ; ## G12 FMC_HPC_LA08_P +set_property -dict {PACKAGE_PIN W4 IOSTANDARD LVCMOS18} [get_ports dac_reset] ; ## C15 FMC_HPC_LA10_N +set_property -dict {PACKAGE_PIN W6 IOSTANDARD LVCMOS18} [get_ports dac_txen] ; ## G16 FMC_HPC_LA12_N +set_property -dict {PACKAGE_PIN AC2 IOSTANDARD LVCMOS18} [get_ports adc_pd] ; ## C10 FMC_HPC_LA06_P + +set_property -dict {PACKAGE_PIN AB8 IOSTANDARD LVCMOS18} [get_ports clkd_status[0]] ; ## D17 FMC_HPC_LA13_P +set_property -dict {PACKAGE_PIN AC8 IOSTANDARD LVCMOS18} [get_ports clkd_status[1]] ; ## D18 FMC_HPC_LA13_N +set_property -dict {PACKAGE_PIN W7 IOSTANDARD LVCMOS18} [get_ports dac_irq] ; ## G15 FMC_HPC_LA12_P +set_property -dict {PACKAGE_PIN AB6 IOSTANDARD LVCMOS18} [get_ports adc_fda] ; ## H16 FMC_HPC_LA11_P +set_property -dict {PACKAGE_PIN AB5 IOSTANDARD LVCMOS18} [get_ports adc_fdb] ; ## H17 FMC_HPC_LA11_N + +set_property -dict {PACKAGE_PIN U5 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports trig_p] ; ## H13 FMC_HPC_LA07_P +set_property -dict {PACKAGE_PIN U4 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports trig_n] ; ## H14 FMC_HPC_LA07_N + +# clocks + +create_clock -name tx_ref_clk -period 2.00 [get_ports tx_ref_clk_p] +create_clock -name rx_ref_clk -period 2.00 [get_ports rx_ref_clk_p] +create_clock -name tx_div_clk -period 4.00 [get_pins i_system_wrapper/system_i/util_daq2_xcvr/inst/i_xch_0/i_gthe4_channel/TXOUTCLK] +create_clock -name rx_div_clk -period 4.00 [get_pins i_system_wrapper/system_i/util_daq2_xcvr/inst/i_xch_0/i_gthe4_channel/RXOUTCLK] + +# gt pin assignments below are for reference only and are ignored by the tool! + +## set_property -dict {PACKAGE_PIN K2} [get_ports rx_data_p[0]] ; ## A10 FMC_HPC_DP3_M2C_P +## set_property -dict {PACKAGE_PIN K1} [get_ports rx_data_n[0]] ; ## A11 FMC_HPC_DP3_M2C_N +## set_property -dict {PACKAGE_PIN H2} [get_ports rx_data_p[1]] ; ## C06 FMC_HPC_DP0_M2C_P +## set_property -dict {PACKAGE_PIN H1} [get_ports rx_data_n[1]] ; ## C07 FMC_HPC_DP0_M2C_N +## set_property -dict {PACKAGE_PIN F2} [get_ports rx_data_p[2]] ; ## A06 FMC_HPC_DP2_M2C_P +## set_property -dict {PACKAGE_PIN F1} [get_ports rx_data_n[2]] ; ## A07 FMC_HPC_DP2_M2C_N +## set_property -dict {PACKAGE_PIN J4} [get_ports rx_data_p[3]] ; ## A02 FMC_HPC_DP1_M2C_P +## set_property -dict {PACKAGE_PIN J3} [get_ports rx_data_n[3]] ; ## A03 FMC_HPC_DP1_M2C_N +## set_property -dict {PACKAGE_PIN K6} [get_ports tx_data_p[0]] ; ## A30 FMC_HPC_DP3_C2M_P (tx_data_p[0]) +## set_property -dict {PACKAGE_PIN K5} [get_ports tx_data_n[0]] ; ## A31 FMC_HPC_DP3_C2M_N (tx_data_n[0]) +## set_property -dict {PACKAGE_PIN G4} [get_ports tx_data_p[1]] ; ## C02 FMC_HPC_DP0_C2M_P (tx_data_p[3]) +## set_property -dict {PACKAGE_PIN G3} [get_ports tx_data_n[1]] ; ## C03 FMC_HPC_DP0_C2M_N (tx_data_n[3]) +## set_property -dict {PACKAGE_PIN F6} [get_ports tx_data_p[2]] ; ## A26 FMC_HPC_DP2_C2M_P (tx_data_p[1]) +## set_property -dict {PACKAGE_PIN F5} [get_ports tx_data_n[2]] ; ## A27 FMC_HPC_DP2_C2M_N (tx_data_n[1]) +## set_property -dict {PACKAGE_PIN H6} [get_ports tx_data_p[3]] ; ## A22 FMC_HPC_DP1_C2M_P (tx_data_p[2]) +## set_property -dict {PACKAGE_PIN H5} [get_ports tx_data_n[3]] ; ## A23 FMC_HPC_DP1_C2M_N (tx_data_n[2]) + +set_property LOC GTHE4_CHANNEL_X1Y8 [get_cells -hierarchical -filter {NAME =~ *util_daq2_xcvr/inst/i_xch_0/i_gthe4_channel}] +set_property LOC GTHE4_CHANNEL_X1Y10 [get_cells -hierarchical -filter {NAME =~ *util_daq2_xcvr/inst/i_xch_1/i_gthe4_channel}] +set_property LOC GTHE4_CHANNEL_X1Y11 [get_cells -hierarchical -filter {NAME =~ *util_daq2_xcvr/inst/i_xch_2/i_gthe4_channel}] +set_property LOC GTHE4_CHANNEL_X1Y9 [get_cells -hierarchical -filter {NAME =~ *util_daq2_xcvr/inst/i_xch_3/i_gthe4_channel}] + + diff --git a/projects/daq2/zcu102/system_project.tcl b/projects/daq2/zcu102/system_project.tcl new file mode 100644 index 000000000..4bb1f028f --- /dev/null +++ b/projects/daq2/zcu102/system_project.tcl @@ -0,0 +1,16 @@ + +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/projects/scripts/adi_project.tcl +source $ad_hdl_dir/projects/scripts/adi_board.tcl + +adi_project_create daq2_zcu102 +adi_project_files daq2_zcu102 [list \ + "../common/daq2_spi.v" \ + "system_top.v" \ + "system_constr.xdc"\ + "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \ + "$ad_hdl_dir/projects/common/zcu102/zcu102_system_constr.xdc" ] + +adi_project_run daq2_zcu102 + + diff --git a/projects/daq2/zcu102/system_top.v b/projects/daq2/zcu102/system_top.v new file mode 100644 index 000000000..f54d5e0de --- /dev/null +++ b/projects/daq2/zcu102/system_top.v @@ -0,0 +1,221 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top ( + + input [12:0] gpio_bd_i, + output [ 7:0] gpio_bd_o, + + input rx_ref_clk_p, + input rx_ref_clk_n, + input rx_sysref_p, + input rx_sysref_n, + output rx_sync_p, + output rx_sync_n, + input [ 3:0] rx_data_p, + input [ 3:0] rx_data_n, + + input tx_ref_clk_p, + input tx_ref_clk_n, + input tx_sysref_p, + input tx_sysref_n, + input tx_sync_p, + input tx_sync_n, + output [ 3:0] tx_data_p, + output [ 3:0] tx_data_n, + + input trig_p, + input trig_n, + + input adc_fdb, + input adc_fda, + input dac_irq, + input [ 1:0] clkd_status, + + output adc_pd, + output dac_txen, + output dac_reset, + output clkd_sync, + + output spi_csn_clk, + output spi_csn_dac, + output spi_csn_adc, + output spi_clk, + inout spi_sdio, + output spi_dir); + + // internal signals + + wire [94:0] gpio_i; + wire [94:0] gpio_o; + wire [ 2:0] spi_csn; + wire spi_mosi; + wire spi_miso; + wire trig; + wire rx_ref_clk; + wire rx_sysref; + wire rx_sync; + wire tx_ref_clk; + wire tx_sysref; + wire tx_sync; + + // spi + + assign spi_csn_adc = spi_csn[2]; + assign spi_csn_dac = spi_csn[1]; + assign spi_csn_clk = spi_csn[0]; + + // instantiations + + IBUFDS_GTE4 i_ibufds_rx_ref_clk ( + .CEB (1'd0), + .I (rx_ref_clk_p), + .IB (rx_ref_clk_n), + .O (rx_ref_clk), + .ODIV2 ()); + + IBUFDS i_ibufds_rx_sysref ( + .I (rx_sysref_p), + .IB (rx_sysref_n), + .O (rx_sysref)); + + OBUFDS i_obufds_rx_sync ( + .I (rx_sync), + .O (rx_sync_p), + .OB (rx_sync_n)); + + IBUFDS_GTE4 i_ibufds_tx_ref_clk ( + .CEB (1'd0), + .I (tx_ref_clk_p), + .IB (tx_ref_clk_n), + .O (tx_ref_clk), + .ODIV2 ()); + + IBUFDS i_ibufds_tx_sysref ( + .I (tx_sysref_p), + .IB (tx_sysref_n), + .O (tx_sysref)); + + IBUFDS i_ibufds_tx_sync ( + .I (tx_sync_p), + .IB (tx_sync_n), + .O (tx_sync)); + + daq2_spi i_spi ( + .spi_csn (spi_csn), + .spi_clk (spi_clk), + .spi_mosi (spi_mosi), + .spi_miso (spi_miso), + .spi_sdio (spi_sdio), + .spi_dir (spi_dir)); + + IBUFDS i_ibufds_trig ( + .I (trig_p), + .IB (trig_n), + .O (trig)); + + assign adc_pd = gpio_o[42]; + assign dac_txen = gpio_o[41]; + assign dac_reset = gpio_o[40]; + assign clkd_sync = gpio_o[38]; + assign gpio_bd_o = gpio_o[7:0]; + + assign gpio_i[94:44] = gpio_o[94:44]; + assign gpio_i[43:43] = trig; + assign gpio_i[42:37] = gpio_o[42:37]; + assign gpio_i[36:36] = adc_fdb; + assign gpio_i[35:35] = adc_fda; + assign gpio_i[34:34] = dac_irq; + assign gpio_i[33:32] = clkd_status; + assign gpio_i[31:21] = gpio_o[31:21]; + assign gpio_i[20: 8] = gpio_bd_i; + assign gpio_i[ 7: 0] = gpio_o[7:0]; + + system_wrapper i_system_wrapper ( + .gpio_i (gpio_i), + .gpio_o (gpio_o), + .ps_intr_00 (1'd0), + .ps_intr_01 (1'd0), + .ps_intr_02 (1'd0), + .ps_intr_03 (1'd0), + .ps_intr_04 (1'd0), + .ps_intr_05 (1'd0), + .ps_intr_06 (1'd0), + .ps_intr_07 (1'd0), + .ps_intr_08 (1'd0), + .ps_intr_09 (1'd0), + .ps_intr_10 (1'd0), + .ps_intr_11 (1'd0), + .ps_intr_14 (1'd0), + .ps_intr_15 (1'd0), + .rx_data_0_n (rx_data_n[0]), + .rx_data_0_p (rx_data_p[0]), + .rx_data_1_n (rx_data_n[1]), + .rx_data_1_p (rx_data_p[1]), + .rx_data_2_n (rx_data_n[2]), + .rx_data_2_p (rx_data_p[2]), + .rx_data_3_n (rx_data_n[3]), + .rx_data_3_p (rx_data_p[3]), + .rx_ref_clk_0 (rx_ref_clk), + .rx_sync_0 (rx_sync), + .rx_sysref_0 (rx_sysref), + .spi0_csn (spi_csn), + .spi0_miso (spi_miso), + .spi0_mosi (spi_mosi), + .spi0_sclk (spi_clk), + .spi1_csn (), + .spi1_miso (1'd0), + .spi1_mosi (), + .spi1_sclk (), + .tx_data_0_n (tx_data_n[0]), + .tx_data_0_p (tx_data_p[0]), + .tx_data_1_n (tx_data_n[1]), + .tx_data_1_p (tx_data_p[1]), + .tx_data_2_n (tx_data_n[2]), + .tx_data_2_p (tx_data_p[2]), + .tx_data_3_n (tx_data_n[3]), + .tx_data_3_p (tx_data_p[3]), + .tx_ref_clk_0 (tx_ref_clk), + .tx_sync_0 (tx_sync), + .tx_sysref_0 (tx_sysref)); + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/projects/daq3/Makefile b/projects/daq3/Makefile index 5b866a1ac..007fae804 100644 --- a/projects/daq3/Makefile +++ b/projects/daq3/Makefile @@ -7,14 +7,20 @@ .PHONY: all clean clean-all all: + -make -C a10gx all + -make -C kcu105 all -make -C zc706 all clean: + make -C a10gx clean + make -C kcu105 clean make -C zc706 clean clean-all: + make -C a10gx clean-all + make -C kcu105 clean-all make -C zc706 clean-all #################################################################################### diff --git a/projects/daq3/a10gx/Makefile b/projects/daq3/a10gx/Makefile index 080656f82..9cd5a1ef9 100755 --- a/projects/daq3/a10gx/Makefile +++ b/projects/daq3/a10gx/Makefile @@ -5,16 +5,30 @@ #################################################################################### #################################################################################### +ifeq ($(MMU),) + MMU := 1 +endif + +export ALT_NIOS_MMU_ENABLED := $(MMU) + M_DEPS += system_top.v +M_DEPS += system_qsys.tcl M_DEPS += system_project.tcl M_DEPS += system_constr.sdc -M_DEPS += system_bd.qsys M_DEPS += ../common/daq3_spi.v -M_DEPS += ../common/daq3_bd.qsys +M_DEPS += ../common/daq3_qsys.tcl +M_DEPS += ../../scripts/adi_tquest.tcl M_DEPS += ../../scripts/adi_env.tcl -M_DEPS += ../../common/a10gx/a10gx_system_bd.qsys +M_DEPS += ../../common/altera/sys_gen.tcl +M_DEPS += ../../common/a10gx/a10gx_system_qsys.tcl M_DEPS += ../../common/a10gx/a10gx_system_assign.tcl -M_DEPS += ../../../library/common/ad_iobuf.v +M_DEPS += ../../../library/altera/avl_adxcfg/avl_adxcfg.v +M_DEPS += ../../../library/altera/avl_adxcfg/avl_adxcfg_hw.tcl +M_DEPS += ../../../library/altera/avl_adxcvr/avl_adxcvr_hw.tcl +M_DEPS += ../../../library/altera/axi_adxcvr/axi_adxcvr.v +M_DEPS += ../../../library/altera/axi_adxcvr/axi_adxcvr_hw.tcl +M_DEPS += ../../../library/altera/axi_adxcvr/axi_adxcvr_up.v +M_DEPS += ../../../library/altera/common/ad_mul.v M_DEPS += ../../../library/axi_ad9152/axi_ad9152.v M_DEPS += ../../../library/axi_ad9152/axi_ad9152_channel.v M_DEPS += ../../../library/axi_ad9152/axi_ad9152_core.v @@ -28,6 +42,7 @@ M_DEPS += ../../../library/axi_ad9680/axi_ad9680_pnmon.v M_DEPS += ../../../library/axi_dmac/2d_transfer.v M_DEPS += ../../../library/axi_dmac/address_generator.v M_DEPS += ../../../library/axi_dmac/axi_dmac.v +M_DEPS += ../../../library/axi_dmac/axi_dmac_constr.sdc M_DEPS += ../../../library/axi_dmac/axi_dmac_hw.tcl M_DEPS += ../../../library/axi_dmac/axi_register_slice.v M_DEPS += ../../../library/axi_dmac/data_mover.v @@ -44,17 +59,16 @@ M_DEPS += ../../../library/axi_dmac/splitter.v M_DEPS += ../../../library/axi_dmac/src_axi_mm.v M_DEPS += ../../../library/axi_dmac/src_axi_stream.v M_DEPS += ../../../library/axi_dmac/src_fifo_inf.v -M_DEPS += ../../../library/axi_jesd_xcvr/axi_jesd_xcvr.v -M_DEPS += ../../../library/axi_jesd_xcvr/axi_jesd_xcvr_hw.tcl +M_DEPS += ../../../library/common/ad_axi_ip_constr.sdc +M_DEPS += ../../../library/common/ad_axis_inf_rx.v M_DEPS += ../../../library/common/ad_datafmt.v M_DEPS += ../../../library/common/ad_dds.v M_DEPS += ../../../library/common/ad_dds_1.v M_DEPS += ../../../library/common/ad_dds_sine.v -M_DEPS += ../../../library/common/ad_jesd_align.v -M_DEPS += ../../../library/common/ad_mul.v +M_DEPS += ../../../library/common/ad_mem_asym.v M_DEPS += ../../../library/common/ad_pnmon.v M_DEPS += ../../../library/common/ad_rst.v -M_DEPS += ../../../library/common/altera/MULT_MACRO.v +M_DEPS += ../../../library/common/ad_xcvr_rx_if.v M_DEPS += ../../../library/common/sync_bits.v M_DEPS += ../../../library/common/sync_gray.v M_DEPS += ../../../library/common/up_adc_channel.v @@ -64,12 +78,12 @@ M_DEPS += ../../../library/common/up_clock_mon.v M_DEPS += ../../../library/common/up_dac_channel.v M_DEPS += ../../../library/common/up_dac_common.v M_DEPS += ../../../library/common/up_delay_cntrl.v -M_DEPS += ../../../library/common/up_xcvr.v M_DEPS += ../../../library/common/up_xfer_cntrl.v M_DEPS += ../../../library/common/up_xfer_status.v -M_DEPS += ../../../library/util_adcfifo/../common/ad_axis_inf_rx.v -M_DEPS += ../../../library/util_adcfifo/../common/ad_mem_asym.v +M_DEPS += ../../../library/scripts/adi_env.tcl +M_DEPS += ../../../library/scripts/adi_ip_alt.tcl M_DEPS += ../../../library/util_adcfifo/util_adcfifo.v +M_DEPS += ../../../library/util_adcfifo/util_adcfifo_constr.sdc M_DEPS += ../../../library/util_adcfifo/util_adcfifo_hw.tcl M_DEPS += ../../../library/util_axis_fifo/address_gray.v M_DEPS += ../../../library/util_axis_fifo/address_gray_pipelined.v @@ -116,6 +130,8 @@ M_FLIST += reconfig_mif M_FLIST += *.sopcinfo M_FLIST += *.jdi M_FLIST += *.pin +M_FLIST += *_summary.csv +M_FLIST += *.dpf @@ -132,7 +148,7 @@ clean-all: daq3_a10gx.sof: $(M_DEPS) - rm -rf $(M_FLIST) + -rm -rf $(M_FLIST) $(M_ALTERA) system_project.tcl >> daq3_a10gx_quartus.log 2>&1 #################################################################################### diff --git a/projects/daq3/a10gx/system_constr.sdc b/projects/daq3/a10gx/system_constr.sdc index 542f5e9d8..c1cfc2afe 100755 --- a/projects/daq3/a10gx/system_constr.sdc +++ b/projects/daq3/a10gx/system_constr.sdc @@ -7,37 +7,37 @@ derive_pll_clocks derive_clock_uncertainty set_false_path -from [get_clocks {sys_clk_100mhz}] -to [get_clocks {\ - i_system_bd|a10gx_base|sys_ddr3_cntrl_phy_clk_0 \ - i_system_bd|a10gx_base|sys_ddr3_cntrl_phy_clk_1 \ - i_system_bd|a10gx_base|sys_ddr3_cntrl_phy_clk_2 \ - i_system_bd|a10gx_base|sys_ddr3_cntrl_phy_clk_l_0 \ - i_system_bd|a10gx_base|sys_ddr3_cntrl_phy_clk_l_1 \ - i_system_bd|a10gx_base|sys_ddr3_cntrl_phy_clk_l_2}] + i_system_bd|sys_ddr3_cntrl_phy_clk_0 \ + i_system_bd|sys_ddr3_cntrl_phy_clk_1 \ + i_system_bd|sys_ddr3_cntrl_phy_clk_2 \ + i_system_bd|sys_ddr3_cntrl_phy_clk_l_0 \ + i_system_bd|sys_ddr3_cntrl_phy_clk_l_1 \ + i_system_bd|sys_ddr3_cntrl_phy_clk_l_2}] set_false_path -from [get_clocks {sys_clk_100mhz}] -to [get_clocks {\ - i_system_bd|a10gx_base|sys_ddr3_cntrl_core_nios_clk}] + i_system_bd|sys_ddr3_cntrl_core_nios_clk}] set_false_path -from [get_clocks {sys_clk_100mhz}]\ -through [get_nets *altera_jesd204_tx_csr_inst*]\ - -to [get_clocks {i_system_bd|daq3|xcvr_tx_pll|outclk0}] + -to [get_clocks {i_system_bd|avl_ad9152_xcvr|alt_core_pll|outclk0}] set_false_path -from [get_clocks {sys_clk_100mhz}]\ -through [get_nets *altera_jesd204_tx_ctl_inst*]\ - -to [get_clocks {i_system_bd|daq3|xcvr_tx_pll|outclk0}] + -to [get_clocks {i_system_bd|avl_ad9152_xcvr|alt_core_pll|outclk0}] set_false_path -from [get_clocks {sys_clk_100mhz}]\ -through [get_nets *altera_jesd204_rx_csr_inst*]\ - -to [get_clocks {i_system_bd|daq3|xcvr_rx_pll|outclk0}] + -to [get_clocks {i_system_bd|avl_ad9680_xcvr|alt_core_pll|outclk0}] -set_false_path -from [get_clocks {i_system_bd|daq3|xcvr_tx_pll|outclk0}]\ +set_false_path -from [get_clocks {i_system_bd|avl_ad9152_xcvr|alt_core_pll|outclk0}]\ -through [get_nets *altera_jesd204_tx_csr_inst*]\ -to [get_clocks {sys_clk_100mhz}] -set_false_path -from [get_clocks {i_system_bd|daq3|xcvr_tx_pll|outclk0}]\ +set_false_path -from [get_clocks {i_system_bd|avl_ad9152_xcvr|alt_core_pll|outclk0}]\ -through [get_nets *altera_jesd204_tx_ctl_inst*]\ -to [get_clocks {sys_clk_100mhz}] -set_false_path -from [get_clocks {i_system_bd|daq3|xcvr_rx_pll|outclk0}]\ +set_false_path -from [get_clocks {i_system_bd|avl_ad9680_xcvr|alt_core_pll|outclk0}]\ -through [get_nets *altera_jesd204_rx_csr_inst*]\ -to [get_clocks {sys_clk_100mhz}] diff --git a/projects/daq3/a10gx/system_project.tcl b/projects/daq3/a10gx/system_project.tcl index a28b59e65..e8487746b 100755 --- a/projects/daq3/a10gx/system_project.tcl +++ b/projects/daq3/a10gx/system_project.tcl @@ -5,12 +5,10 @@ source ../../scripts/adi_env.tcl project_new daq3_a10gx -overwrite source "../../common/a10gx/a10gx_system_assign.tcl" -set_user_option -name USER_IP_SEARCH_PATHS "../common/;../../common/a10gx/;../../../library/**/*" -set_global_assignment -name IP_SEARCH_PATHS "../common/;../../common/a10gx;../../../library/**/*" -set_global_assignment -name QSYS_FILE system_bd.qsys set_global_assignment -name VERILOG_FILE ../common/daq3_spi.v set_global_assignment -name VERILOG_FILE system_top.v +set_global_assignment -name QSYS_FILE system_bd.qsys set_global_assignment -name SDC_FILE system_constr.sdc set_global_assignment -name TOP_LEVEL_ENTITY system_top @@ -62,6 +60,16 @@ set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to tx_sync set_instance_assignment -name IO_STANDARD LVDS -to tx_sysref set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to tx_sysref +set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_0 -to rx_data[0] +set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_1 -to rx_data[1] +set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_2 -to rx_data[2] +set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_3 -to rx_data[3] + +set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_0 -to tx_data[0] +set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_1 -to tx_data[1] +set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_2 -to tx_data[2] +set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_3 -to tx_data[3] + # gpio set_location_assignment PIN_AT17 -to trig ; ## H13 FMCA_LA07_P diff --git a/projects/daq3/a10gx/system_qsys.tcl b/projects/daq3/a10gx/system_qsys.tcl new file mode 100644 index 000000000..9b5d24188 --- /dev/null +++ b/projects/daq3/a10gx/system_qsys.tcl @@ -0,0 +1,6 @@ + + +source $ad_hdl_dir/projects/common/a10gx/a10gx_system_qsys.tcl +source ../common/daq3_qsys.tcl + + diff --git a/projects/daq3/a10gx/system_top.v b/projects/daq3/a10gx/system_top.v index 8524d6ead..488d43065 100755 --- a/projects/daq3/a10gx/system_top.v +++ b/projects/daq3/a10gx/system_top.v @@ -147,8 +147,8 @@ module system_top ( // board gpio - inout [ 10:0] gpio_bd_i; - inout [ 15:0] gpio_bd_o; + input [ 10:0] gpio_bd_i; + output [ 15:0] gpio_bd_o; // lane interface @@ -209,12 +209,14 @@ module system_top ( // gpio in & out are separate cores - assign sysref = gpio_o[36]; - assign adc_pd = gpio_o[35]; - assign dac_txen = gpio_o[34]; + assign gpio_i[63:40] = gpio_o[63:40]; + assign sysref = gpio_o[40]; + assign gpio_i[39:39] = trig; + + assign gpio_i[38:37] = gpio_o[38:37]; + assign adc_pd = gpio_o[38]; + assign dac_txen = gpio_o[37]; - assign gpio_i[63:38] = 26'd0; - assign gpio_i[37:37] = trig; assign gpio_i[36:36] = adc_fdb; assign gpio_i[35:35] = adc_fda; assign gpio_i[34:34] = dac_irq; @@ -235,49 +237,55 @@ module system_top ( assign gpio_bd_o = gpio_o[15:0]; system_bd i_system_bd ( - .a10gx_base_sys_ddr3_cntrl_mem_mem_ck (ddr3_clk_p), - .a10gx_base_sys_ddr3_cntrl_mem_mem_ck_n (ddr3_clk_n), - .a10gx_base_sys_ddr3_cntrl_mem_mem_a (ddr3_a[11:0]), - .a10gx_base_sys_ddr3_cntrl_mem_mem_ba (ddr3_ba), - .a10gx_base_sys_ddr3_cntrl_mem_mem_cke (ddr3_cke), - .a10gx_base_sys_ddr3_cntrl_mem_mem_cs_n (ddr3_cs_n), - .a10gx_base_sys_ddr3_cntrl_mem_mem_odt (ddr3_odt), - .a10gx_base_sys_ddr3_cntrl_mem_mem_reset_n (ddr3_reset_n), - .a10gx_base_sys_ddr3_cntrl_mem_mem_we_n (ddr3_we_n), - .a10gx_base_sys_ddr3_cntrl_mem_mem_ras_n (ddr3_ras_n), - .a10gx_base_sys_ddr3_cntrl_mem_mem_cas_n (ddr3_cas_n), - .a10gx_base_sys_ddr3_cntrl_mem_mem_dqs (ddr3_dqs_p[7:0]), - .a10gx_base_sys_ddr3_cntrl_mem_mem_dqs_n (ddr3_dqs_n[7:0]), - .a10gx_base_sys_ddr3_cntrl_mem_mem_dq (ddr3_dq[63:0]), - .a10gx_base_sys_ddr3_cntrl_mem_mem_dm (ddr3_dm[7:0]), - .a10gx_base_sys_ddr3_cntrl_oct_oct_rzqin (ddr3_rzq), - .a10gx_base_sys_ddr3_cntrl_pll_ref_clk_clk (ddr3_ref_clk), - .a10gx_base_sys_ethernet_mdio_mdc (eth_mdc), - .a10gx_base_sys_ethernet_mdio_mdio_in (eth_mdio_i), - .a10gx_base_sys_ethernet_mdio_mdio_out (eth_mdio_o), - .a10gx_base_sys_ethernet_mdio_mdio_oen (eth_mdio_t), - .a10gx_base_sys_ethernet_ref_clk_clk (eth_ref_clk), - .a10gx_base_sys_ethernet_reset_reset (eth_reset), - .a10gx_base_sys_ethernet_sgmii_rxp_0 (eth_rxd), - .a10gx_base_sys_ethernet_sgmii_txp_0 (eth_txd), - .a10gx_base_sys_gpio_in_export (gpio_i[63:32]), - .a10gx_base_sys_gpio_out_export (gpio_o[63:32]), - .a10gx_base_sys_gpio_bd_in_port (gpio_i[31:0]), - .a10gx_base_sys_gpio_bd_out_port (gpio_o[31:0]), - .a10gx_base_sys_spi_MISO (spi_miso_s), - .a10gx_base_sys_spi_MOSI (spi_mosi_s), - .a10gx_base_sys_spi_SCLK (spi_clk), - .a10gx_base_sys_spi_SS_n (spi_csn_s), - .daq3_rx_data_rx_serial_data (rx_data), - .daq3_rx_ref_clk_clk (rx_ref_clk), - .daq3_rx_sync_rx_sync (rx_sync), - .daq3_rx_sysref_rx_ext_sysref_in (rx_sysref), - .daq3_tx_data_tx_serial_data (tx_data), - .daq3_tx_ref_clk_clk (tx_ref_clk), - .daq3_tx_sync_tx_sync (tx_sync), - .daq3_tx_sysref_tx_ext_sysref_in (tx_sysref), + .sys_ddr3_cntrl_mem_mem_ck (ddr3_clk_p), + .sys_ddr3_cntrl_mem_mem_ck_n (ddr3_clk_n), + .sys_ddr3_cntrl_mem_mem_a (ddr3_a[11:0]), + .sys_ddr3_cntrl_mem_mem_ba (ddr3_ba), + .sys_ddr3_cntrl_mem_mem_cke (ddr3_cke), + .sys_ddr3_cntrl_mem_mem_cs_n (ddr3_cs_n), + .sys_ddr3_cntrl_mem_mem_odt (ddr3_odt), + .sys_ddr3_cntrl_mem_mem_reset_n (ddr3_reset_n), + .sys_ddr3_cntrl_mem_mem_we_n (ddr3_we_n), + .sys_ddr3_cntrl_mem_mem_ras_n (ddr3_ras_n), + .sys_ddr3_cntrl_mem_mem_cas_n (ddr3_cas_n), + .sys_ddr3_cntrl_mem_mem_dqs (ddr3_dqs_p[7:0]), + .sys_ddr3_cntrl_mem_mem_dqs_n (ddr3_dqs_n[7:0]), + .sys_ddr3_cntrl_mem_mem_dq (ddr3_dq[63:0]), + .sys_ddr3_cntrl_mem_mem_dm (ddr3_dm[7:0]), + .sys_ddr3_cntrl_oct_oct_rzqin (ddr3_rzq), + .sys_ddr3_cntrl_pll_ref_clk_clk (ddr3_ref_clk), + .sys_ethernet_mdio_mdc (eth_mdc), + .sys_ethernet_mdio_mdio_in (eth_mdio_i), + .sys_ethernet_mdio_mdio_out (eth_mdio_o), + .sys_ethernet_mdio_mdio_oen (eth_mdio_t), + .sys_ethernet_ref_clk_clk (eth_ref_clk), + .sys_ethernet_reset_reset (eth_reset), + .sys_ethernet_sgmii_rxp_0 (eth_rxd), + .sys_ethernet_sgmii_txp_0 (eth_txd), + .sys_gpio_in_export (gpio_i[63:32]), + .sys_gpio_out_export (gpio_o[63:32]), + .sys_gpio_bd_in_port (gpio_i[31:0]), + .sys_gpio_bd_out_port (gpio_o[31:0]), + .sys_spi_MISO (spi_miso_s), + .sys_spi_MOSI (spi_mosi_s), + .sys_spi_SCLK (spi_clk), + .sys_spi_SS_n (spi_csn_s), + .rx_data_0_rx_serial_data (rx_data[0]), + .rx_data_1_rx_serial_data (rx_data[1]), + .rx_data_2_rx_serial_data (rx_data[2]), + .rx_data_3_rx_serial_data (rx_data[3]), + .rx_ref_clk_clk (rx_ref_clk), + .rx_sync_export (rx_sync), + .rx_sysref_export (rx_sysref), + .tx_data_0_tx_serial_data (tx_data[0]), + .tx_data_1_tx_serial_data (tx_data[1]), + .tx_data_2_tx_serial_data (tx_data[2]), + .tx_data_3_tx_serial_data (tx_data[3]), + .tx_ref_clk_clk (tx_ref_clk), + .tx_sync_export (tx_sync), + .tx_sysref_export (tx_sysref), .sys_clk_clk (sys_clk), - .sys_reset_reset_n (sys_resetn)); + .sys_rst_reset_n (sys_resetn)); endmodule diff --git a/projects/daq3/common/daq3_bd.tcl b/projects/daq3/common/daq3_bd.tcl index 2eb48bf37..543fc4ea5 100644 --- a/projects/daq3/common/daq3_bd.tcl +++ b/projects/daq3/common/daq3_bd.tcl @@ -1,26 +1,21 @@ -# daq3 - -create_bd_port -dir I rx_ref_clk -create_bd_port -dir O rx_sync -create_bd_port -dir I rx_sysref -create_bd_port -dir I -from 3 -to 0 rx_data_p -create_bd_port -dir I -from 3 -to 0 rx_data_n - -create_bd_port -dir I tx_ref_clk -create_bd_port -dir I tx_sync -create_bd_port -dir I tx_sysref -create_bd_port -dir O -from 3 -to 0 tx_data_p -create_bd_port -dir O -from 3 -to 0 tx_data_n - # dac peripherals -set axi_ad9152_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9152:1.0 axi_ad9152_core] +set axi_ad9152_xcvr [create_bd_cell -type ip -vlnv analog.com:user:axi_adxcvr:1.0 axi_ad9152_xcvr] +set_property -dict [list CONFIG.NUM_OF_LANES {4}] $axi_ad9152_xcvr +set_property -dict [list CONFIG.QPLL_ENABLE {1}] $axi_ad9152_xcvr +set_property -dict [list CONFIG.TX_OR_RX_N {1}] $axi_ad9152_xcvr -set axi_ad9152_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.2 axi_ad9152_jesd] +set axi_ad9152_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:7.0 axi_ad9152_jesd] set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {1}] $axi_ad9152_jesd set_property -dict [list CONFIG.C_LANES {4}] $axi_ad9152_jesd +set axi_ad9152_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9152:1.0 axi_ad9152_core] + +set axi_ad9152_upack [create_bd_cell -type ip -vlnv analog.com:user:util_upack:1.0 axi_ad9152_upack] +set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {64}] $axi_ad9152_upack +set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $axi_ad9152_upack + set axi_ad9152_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9152_dma] set_property -dict [list CONFIG.DMA_TYPE_SRC {0}] $axi_ad9152_dma set_property -dict [list CONFIG.DMA_TYPE_DEST {1}] $axi_ad9152_dma @@ -33,17 +28,22 @@ set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad9152_dma set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {128}] $axi_ad9152_dma set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {128}] $axi_ad9152_dma -set axi_ad9152_upack [create_bd_cell -type ip -vlnv analog.com:user:util_upack:1.0 axi_ad9152_upack] -set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {64}] $axi_ad9152_upack -set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $axi_ad9152_upack - # adc peripherals +set axi_ad9680_xcvr [create_bd_cell -type ip -vlnv analog.com:user:axi_adxcvr:1.0 axi_ad9680_xcvr] +set_property -dict [list CONFIG.NUM_OF_LANES {4}] $axi_ad9680_xcvr +set_property -dict [list CONFIG.QPLL_ENABLE {0}] $axi_ad9680_xcvr +set_property -dict [list CONFIG.TX_OR_RX_N {0}] $axi_ad9680_xcvr + +set axi_ad9680_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:7.0 axi_ad9680_jesd] +set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9680_jesd +set_property -dict [list CONFIG.C_LANES {4}] $axi_ad9680_jesd + set axi_ad9680_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9680:1.0 axi_ad9680_core] -set axi_ad9680_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.2 axi_ad9680_jesd] -set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9680_jesd -set_property -dict [list CONFIG.C_LANES {4}] $axi_ad9680_jesd +set axi_ad9680_cpack [create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 axi_ad9680_cpack] +set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {64}] $axi_ad9680_cpack +set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $axi_ad9680_cpack set axi_ad9680_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9680_dma] set_property -dict [list CONFIG.DMA_TYPE_SRC {1}] $axi_ad9680_dma @@ -58,89 +58,45 @@ set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad9680_dma set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {64}] $axi_ad9680_dma set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $axi_ad9680_dma -set axi_ad9680_cpack [create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 axi_ad9680_cpack] -set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {64}] $axi_ad9680_cpack -set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $axi_ad9680_cpack +# shared transceiver core -# dac/adc common gt +set util_daq3_xcvr [create_bd_cell -type ip -vlnv analog.com:user:util_adxcvr:1.0 util_daq3_xcvr] +set_property -dict [list CONFIG.RX_NUM_OF_LANES {4}] $util_daq3_xcvr +set_property -dict [list CONFIG.TX_NUM_OF_LANES {4}] $util_daq3_xcvr -set axi_daq3_gt [create_bd_cell -type ip -vlnv analog.com:user:axi_jesd_gt:1.0 axi_daq3_gt] -set_property -dict [list CONFIG.NUM_OF_LANES {4}] $axi_daq3_gt -set_property -dict [list CONFIG.QPLL1_ENABLE {0}] $axi_daq3_gt -set_property -dict [list CONFIG.RX_NUM_OF_LANES {4}] $axi_daq3_gt -set_property -dict [list CONFIG.TX_NUM_OF_LANES {4}] $axi_daq3_gt -set_property -dict [list CONFIG.RX_CLKBUF_ENABLE_0 {1}] $axi_daq3_gt -set_property -dict [list CONFIG.TX_CLKBUF_ENABLE_0 {1}] $axi_daq3_gt -set_property -dict [list CONFIG.TX_DATA_SEL_0 {0}] $axi_daq3_gt -set_property -dict [list CONFIG.TX_DATA_SEL_1 {3}] $axi_daq3_gt -set_property -dict [list CONFIG.TX_DATA_SEL_2 {1}] $axi_daq3_gt -set_property -dict [list CONFIG.TX_DATA_SEL_3 {2}] $axi_daq3_gt +ad_connect sys_cpu_resetn util_daq3_xcvr/up_rstn +ad_connect sys_cpu_clk util_daq3_xcvr/up_clk -set util_daq3_gt [create_bd_cell -type ip -vlnv analog.com:user:util_jesd_gt:1.0 util_daq3_gt] -set_property -dict [list CONFIG.QPLL0_ENABLE {1}] $util_daq3_gt -set_property -dict [list CONFIG.QPLL1_ENABLE {0}] $util_daq3_gt -set_property -dict [list CONFIG.NUM_OF_LANES {4}] $util_daq3_gt -set_property -dict [list CONFIG.RX_ENABLE {1}] $util_daq3_gt -set_property -dict [list CONFIG.RX_NUM_OF_LANES {4}] $util_daq3_gt -set_property -dict [list CONFIG.TX_ENABLE {1}] $util_daq3_gt -set_property -dict [list CONFIG.TX_NUM_OF_LANES {4}] $util_daq3_gt +# reference clocks & resets -# connections (gt) +create_bd_port -dir I tx_ref_clk_0 +create_bd_port -dir I rx_ref_clk_0 -ad_connect util_daq3_gt/qpll_ref_clk rx_ref_clk -ad_connect util_daq3_gt/cpll_ref_clk tx_ref_clk - -ad_connect axi_daq3_gt/gt_qpll_0 util_daq3_gt/gt_qpll_0 -ad_connect axi_daq3_gt/gt_pll_0 util_daq3_gt/gt_pll_0 -ad_connect axi_daq3_gt/gt_pll_1 util_daq3_gt/gt_pll_1 -ad_connect axi_daq3_gt/gt_pll_2 util_daq3_gt/gt_pll_2 -ad_connect axi_daq3_gt/gt_pll_3 util_daq3_gt/gt_pll_3 -ad_connect axi_daq3_gt/gt_rx_0 util_daq3_gt/gt_rx_0 -ad_connect axi_daq3_gt/gt_rx_1 util_daq3_gt/gt_rx_1 -ad_connect axi_daq3_gt/gt_rx_2 util_daq3_gt/gt_rx_2 -ad_connect axi_daq3_gt/gt_rx_3 util_daq3_gt/gt_rx_3 -ad_connect axi_daq3_gt/gt_rx_ip_0 axi_ad9680_jesd/gt0_rx -ad_connect axi_daq3_gt/gt_rx_ip_1 axi_ad9680_jesd/gt1_rx -ad_connect axi_daq3_gt/gt_rx_ip_2 axi_ad9680_jesd/gt2_rx -ad_connect axi_daq3_gt/gt_rx_ip_3 axi_ad9680_jesd/gt3_rx -ad_connect axi_daq3_gt/rx_gt_comma_align_enb_0 axi_ad9680_jesd/rxencommaalign_out -ad_connect axi_daq3_gt/rx_gt_comma_align_enb_1 axi_ad9680_jesd/rxencommaalign_out -ad_connect axi_daq3_gt/rx_gt_comma_align_enb_2 axi_ad9680_jesd/rxencommaalign_out -ad_connect axi_daq3_gt/rx_gt_comma_align_enb_3 axi_ad9680_jesd/rxencommaalign_out -ad_connect axi_daq3_gt/gt_tx_0 util_daq3_gt/gt_tx_0 -ad_connect axi_daq3_gt/gt_tx_1 util_daq3_gt/gt_tx_1 -ad_connect axi_daq3_gt/gt_tx_2 util_daq3_gt/gt_tx_2 -ad_connect axi_daq3_gt/gt_tx_3 util_daq3_gt/gt_tx_3 -ad_connect axi_daq3_gt/gt_tx_ip_0 axi_ad9152_jesd/gt0_tx -ad_connect axi_daq3_gt/gt_tx_ip_1 axi_ad9152_jesd/gt1_tx -ad_connect axi_daq3_gt/gt_tx_ip_2 axi_ad9152_jesd/gt2_tx -ad_connect axi_daq3_gt/gt_tx_ip_3 axi_ad9152_jesd/gt3_tx +ad_xcvrpll tx_ref_clk_0 util_daq3_xcvr/qpll_ref_clk_* +ad_xcvrpll rx_ref_clk_0 util_daq3_xcvr/cpll_ref_clk_* +ad_xcvrpll axi_ad9152_xcvr/up_pll_rst util_daq3_xcvr/up_qpll_rst_* +ad_xcvrpll axi_ad9680_xcvr/up_pll_rst util_daq3_xcvr/up_cpll_rst_* # connections (dac) -ad_connect util_daq3_gt/tx_sysref tx_sysref -ad_connect util_daq3_gt/tx_p tx_data_p -ad_connect util_daq3_gt/tx_n tx_data_n -ad_connect util_daq3_gt/tx_sync tx_sync -ad_connect util_daq3_gt/tx_out_clk util_daq3_gt/tx_clk -ad_connect util_daq3_gt/tx_out_clk axi_ad9152_jesd/tx_core_clk -ad_connect util_daq3_gt/tx_ip_rst axi_ad9152_jesd/tx_reset -ad_connect util_daq3_gt/tx_ip_rst_done axi_ad9152_jesd/tx_reset_done -ad_connect util_daq3_gt/tx_ip_sysref axi_ad9152_jesd/tx_sysref -ad_connect util_daq3_gt/tx_ip_sync axi_ad9152_jesd/tx_sync -ad_connect util_daq3_gt/tx_ip_data axi_ad9152_jesd/tx_tdata -ad_connect util_daq3_gt/tx_out_clk axi_ad9152_core/tx_clk -ad_connect util_daq3_gt/tx_data axi_ad9152_core/tx_data -ad_connect util_daq3_gt/tx_out_clk axi_ad9152_upack/dac_clk +ad_xcvrcon util_daq3_xcvr axi_ad9152_xcvr axi_ad9152_jesd +ad_reconct util_daq3_xcvr/tx_0 axi_ad9152_jesd/gt0_tx +ad_reconct util_daq3_xcvr/tx_1 axi_ad9152_jesd/gt3_tx +ad_reconct util_daq3_xcvr/tx_2 axi_ad9152_jesd/gt1_tx +ad_reconct util_daq3_xcvr/tx_3 axi_ad9152_jesd/gt2_tx +ad_connect util_daq3_xcvr/tx_out_clk_0 axi_ad9152_core/tx_clk +ad_connect axi_ad9152_jesd/tx_tdata axi_ad9152_core/tx_data +ad_connect util_daq3_xcvr/tx_out_clk_0 axi_ad9152_upack/dac_clk ad_connect axi_ad9152_core/dac_enable_0 axi_ad9152_upack/dac_enable_0 ad_connect axi_ad9152_core/dac_ddata_0 axi_ad9152_upack/dac_data_0 ad_connect axi_ad9152_core/dac_valid_0 axi_ad9152_upack/dac_valid_0 ad_connect axi_ad9152_core/dac_enable_1 axi_ad9152_upack/dac_enable_1 ad_connect axi_ad9152_core/dac_ddata_1 axi_ad9152_upack/dac_data_1 ad_connect axi_ad9152_core/dac_valid_1 axi_ad9152_upack/dac_valid_1 -ad_connect util_daq3_gt/tx_out_clk axi_ad9152_fifo/dac_clk +ad_connect util_daq3_xcvr/tx_out_clk_0 axi_ad9152_fifo/dac_clk ad_connect axi_ad9152_upack/dac_valid axi_ad9152_fifo/dac_valid ad_connect axi_ad9152_upack/dac_data axi_ad9152_fifo/dac_data +ad_connect axi_ad9152_upack/dma_xfer_in axi_ad9152_fifo/dac_xfer_out ad_connect sys_cpu_clk axi_ad9152_fifo/dma_clk ad_connect sys_cpu_reset axi_ad9152_fifo/dma_rst ad_connect sys_cpu_clk axi_ad9152_dma/m_axis_aclk @@ -153,30 +109,20 @@ ad_connect axi_ad9152_fifo/dma_xfer_last axi_ad9152_dma/m_axis_last # connections (adc) -ad_connect util_daq3_gt/rx_sysref rx_sysref -ad_connect util_daq3_gt/rx_p rx_data_p -ad_connect util_daq3_gt/rx_n rx_data_n -ad_connect util_daq3_gt/rx_sync rx_sync -ad_connect util_daq3_gt/rx_out_clk util_daq3_gt/rx_clk -ad_connect util_daq3_gt/rx_out_clk axi_ad9680_jesd/rx_core_clk -ad_connect util_daq3_gt/rx_ip_rst axi_ad9680_jesd/rx_reset -ad_connect util_daq3_gt/rx_ip_rst_done axi_ad9680_jesd/rx_reset_done -ad_connect util_daq3_gt/rx_ip_sysref axi_ad9680_jesd/rx_sysref -ad_connect util_daq3_gt/rx_ip_sync axi_ad9680_jesd/rx_sync -ad_connect util_daq3_gt/rx_ip_sof axi_ad9680_jesd/rx_start_of_frame -ad_connect util_daq3_gt/rx_ip_data axi_ad9680_jesd/rx_tdata -ad_connect util_daq3_gt/rx_out_clk axi_ad9680_core/rx_clk -ad_connect util_daq3_gt/rx_data axi_ad9680_core/rx_data -ad_connect util_daq3_gt/rx_out_clk axi_ad9680_cpack/adc_clk -ad_connect util_daq3_gt/rx_rst axi_ad9680_cpack/adc_rst +ad_xcvrcon util_daq3_xcvr axi_ad9680_xcvr axi_ad9680_jesd +ad_connect util_daq3_xcvr/rx_out_clk_0 axi_ad9680_core/rx_clk +ad_connect axi_ad9680_jesd/rx_start_of_frame axi_ad9680_core/rx_sof +ad_connect axi_ad9680_jesd/rx_tdata axi_ad9680_core/rx_data +ad_connect util_daq3_xcvr/rx_out_clk_0 axi_ad9680_cpack/adc_clk +ad_connect axi_ad9680_jesd_rstgen/peripheral_reset axi_ad9680_cpack/adc_rst ad_connect axi_ad9680_core/adc_enable_0 axi_ad9680_cpack/adc_enable_0 ad_connect axi_ad9680_core/adc_valid_0 axi_ad9680_cpack/adc_valid_0 ad_connect axi_ad9680_core/adc_data_0 axi_ad9680_cpack/adc_data_0 ad_connect axi_ad9680_core/adc_enable_1 axi_ad9680_cpack/adc_enable_1 ad_connect axi_ad9680_core/adc_valid_1 axi_ad9680_cpack/adc_valid_1 ad_connect axi_ad9680_core/adc_data_1 axi_ad9680_cpack/adc_data_1 -ad_connect util_daq3_gt/rx_out_clk axi_ad9680_fifo/adc_clk -ad_connect util_daq3_gt/rx_rst axi_ad9680_fifo/adc_rst +ad_connect util_daq3_xcvr/rx_out_clk_0 axi_ad9680_fifo/adc_clk +ad_connect axi_ad9680_jesd_rstgen/peripheral_reset axi_ad9680_fifo/adc_rst ad_connect axi_ad9680_cpack/adc_valid axi_ad9680_fifo/adc_wr ad_connect axi_ad9680_cpack/adc_data axi_ad9680_fifo/adc_wdata ad_connect sys_cpu_clk axi_ad9680_fifo/dma_clk @@ -190,10 +136,11 @@ ad_connect axi_ad9680_core/adc_dovf axi_ad9680_fifo/adc_wovf # interconnect (cpu) -ad_cpu_interconnect 0x44A60000 axi_daq3_gt +ad_cpu_interconnect 0x44A60000 axi_ad9152_xcvr ad_cpu_interconnect 0x44A00000 axi_ad9152_core ad_cpu_interconnect 0x44A90000 axi_ad9152_jesd ad_cpu_interconnect 0x7c420000 axi_ad9152_dma +ad_cpu_interconnect 0x44A50000 axi_ad9680_xcvr ad_cpu_interconnect 0x44A10000 axi_ad9680_core ad_cpu_interconnect 0x44A91000 axi_ad9680_jesd ad_cpu_interconnect 0x7c400000 axi_ad9680_dma @@ -201,7 +148,7 @@ ad_cpu_interconnect 0x7c400000 axi_ad9680_dma # gt uses hp3, and 100MHz clock for both DRP and AXI4 ad_mem_hp3_interconnect sys_cpu_clk sys_ps7/S_AXI_HP3 -ad_mem_hp3_interconnect sys_cpu_clk axi_daq3_gt/m_axi +ad_mem_hp3_interconnect sys_cpu_clk axi_ad9680_xcvr/m_axi # interconnect (mem/dac) @@ -215,3 +162,5 @@ ad_mem_hp2_interconnect sys_cpu_clk axi_ad9680_dma/m_dest_axi ad_cpu_interrupt ps-12 mb-13 axi_ad9152_dma/irq ad_cpu_interrupt ps-13 mb-12 axi_ad9680_dma/irq +ad_connect axi_ad9152_fifo/dac_fifo_bypass GND + diff --git a/projects/daq3/common/daq3_qsys.tcl b/projects/daq3/common/daq3_qsys.tcl new file mode 100644 index 000000000..14441c9f2 --- /dev/null +++ b/projects/daq3/common/daq3_qsys.tcl @@ -0,0 +1,276 @@ + +# ad9152-xcvr + +add_instance avl_ad9152_xcvr avl_adxcvr 1.0 +set_instance_parameter_value avl_ad9152_xcvr {ID} {0} +set_instance_parameter_value avl_ad9152_xcvr {TX_OR_RX_N} {1} +set_instance_parameter_value avl_ad9152_xcvr {PCS_CONFIG} {JESD_PCS_CFG2} +set_instance_parameter_value avl_ad9152_xcvr {LANE_RATE} {10000.0} +set_instance_parameter_value avl_ad9152_xcvr {PLLCLK_FREQUENCY} {5000.0} +set_instance_parameter_value avl_ad9152_xcvr {REFCLK_FREQUENCY} {500.0} +set_instance_parameter_value avl_ad9152_xcvr {CORECLK_FREQUENCY} {250.0} +set_instance_parameter_value avl_ad9152_xcvr {NUM_OF_LANES} {4} +set_instance_parameter_value avl_ad9152_xcvr {NUM_OF_CONVS} {2} +set_instance_parameter_value avl_ad9152_xcvr {FRM_BCNT} {1} +set_instance_parameter_value avl_ad9152_xcvr {FRM_SCNT} {1} +set_instance_parameter_value avl_ad9152_xcvr {MF_FCNT} {32} +set_instance_parameter_value avl_ad9152_xcvr {HD} {1} + +add_connection sys_clk.clk avl_ad9152_xcvr.sys_clk +add_connection sys_clk.clk_reset avl_ad9152_xcvr.sys_resetn +add_interface tx_ref_clk clock sink +set_interface_property tx_ref_clk EXPORT_OF avl_ad9152_xcvr.ref_clk +add_interface tx_data_0 conduit end +set_interface_property tx_data_0 EXPORT_OF avl_ad9152_xcvr.tx_data_0 +add_interface tx_data_1 conduit end +set_interface_property tx_data_1 EXPORT_OF avl_ad9152_xcvr.tx_data_1 +add_interface tx_data_2 conduit end +set_interface_property tx_data_2 EXPORT_OF avl_ad9152_xcvr.tx_data_2 +add_interface tx_data_3 conduit end +set_interface_property tx_data_3 EXPORT_OF avl_ad9152_xcvr.tx_data_3 +add_interface tx_sysref conduit end +set_interface_property tx_sysref EXPORT_OF avl_ad9152_xcvr.sysref +add_interface tx_sync conduit end +set_interface_property tx_sync EXPORT_OF avl_ad9152_xcvr.sync +add_connection avl_ad9152_xcvr.tx_phy_s_0 avl_ad9152_xcvr.tx_ip_s_0 +add_connection avl_ad9152_xcvr.tx_phy_s_1 avl_ad9152_xcvr.tx_ip_s_3 +add_connection avl_ad9152_xcvr.tx_phy_s_2 avl_ad9152_xcvr.tx_ip_s_1 +add_connection avl_ad9152_xcvr.tx_phy_s_3 avl_ad9152_xcvr.tx_ip_s_2 +add_connection avl_ad9152_xcvr.tx_ip_d_0 avl_ad9152_xcvr.tx_phy_d_0 +add_connection avl_ad9152_xcvr.tx_ip_d_3 avl_ad9152_xcvr.tx_phy_d_1 +add_connection avl_ad9152_xcvr.tx_ip_d_1 avl_ad9152_xcvr.tx_phy_d_2 +add_connection avl_ad9152_xcvr.tx_ip_d_2 avl_ad9152_xcvr.tx_phy_d_3 +add_connection sys_cpu.data_master avl_ad9152_xcvr.core_pll_reconfig +add_connection sys_cpu.data_master avl_ad9152_xcvr.lane_pll_reconfig +add_connection sys_cpu.data_master avl_ad9152_xcvr.ip_reconfig + +add_instance axi_ad9152_xcvr axi_adxcvr 1.0 +set_instance_parameter_value axi_ad9152_xcvr {ID} {0} +set_instance_parameter_value axi_ad9152_xcvr {TX_OR_RX_N} {1} +set_instance_parameter_value axi_ad9152_xcvr {NUM_OF_LANES} {4} + +add_connection sys_clk.clk axi_ad9152_xcvr.s_axi_clock +add_connection sys_clk.clk_reset axi_ad9152_xcvr.s_axi_reset +add_connection axi_ad9152_xcvr.if_up_rst avl_ad9152_xcvr.rst +add_connection avl_ad9152_xcvr.ready axi_ad9152_xcvr.ready +add_connection axi_ad9152_xcvr.core_pll_locked avl_ad9152_xcvr.core_pll_locked +add_connection sys_cpu.data_master axi_ad9152_xcvr.s_axi + +# ad9152-core + +add_instance axi_ad9152_core axi_ad9152 1.0 +set_instance_parameter_value axi_ad9152_core {DEVICE_TYPE} {1} + +add_connection avl_ad9152_xcvr.core_clk axi_ad9152_core.if_tx_clk +add_connection axi_ad9152_core.if_tx_data avl_ad9152_xcvr.ip_data +add_connection sys_clk.clk_reset axi_ad9152_core.s_axi_reset +add_connection sys_clk.clk axi_ad9152_core.s_axi_clock +add_connection sys_cpu.data_master axi_ad9152_core.s_axi + +# ad9152-unpack + +add_instance util_ad9152_upack util_upack 1.0 +set_instance_parameter_value util_ad9152_upack {CHANNEL_DATA_WIDTH} {64} +set_instance_parameter_value util_ad9152_upack {NUM_OF_CHANNELS} {2} + +add_connection avl_ad9152_xcvr.core_clk util_ad9152_upack.if_dac_clk +add_connection axi_ad9152_core.dac_ch_0 util_ad9152_upack.dac_ch_0 +add_connection axi_ad9152_core.dac_ch_1 util_ad9152_upack.dac_ch_1 + +# ad9152-dma + +add_instance axi_ad9152_dma axi_dmac 1.0 +set_instance_parameter_value axi_ad9152_dma {DMA_DATA_WIDTH_SRC} {128} +set_instance_parameter_value axi_ad9152_dma {DMA_DATA_WIDTH_DEST} {128} +set_instance_parameter_value axi_ad9152_dma {DMA_2D_TRANSFER} {0} +set_instance_parameter_value axi_ad9152_dma {DMA_TYPE_DEST} {2} +set_instance_parameter_value axi_ad9152_dma {DMA_TYPE_SRC} {0} + +add_connection avl_ad9152_xcvr.core_clk axi_ad9152_dma.if_fifo_rd_clk +add_connection util_ad9152_upack.if_dac_valid axi_ad9152_dma.if_fifo_rd_en +add_connection util_ad9152_upack.if_dac_data axi_ad9152_dma.if_fifo_rd_dout +add_connection axi_ad9152_dma.if_fifo_rd_underflow axi_ad9152_core.if_dac_dunf +add_connection sys_clk.clk_reset axi_ad9152_dma.s_axi_reset +add_connection sys_clk.clk axi_ad9152_dma.s_axi_clock +add_connection sys_cpu.data_master axi_ad9152_dma.s_axi +add_connection sys_ddr3_cntrl.emif_usr_reset_n axi_ad9152_dma.m_src_axi_reset +add_connection sys_ddr3_cntrl.emif_usr_clk axi_ad9152_dma.m_src_axi_clock +add_connection axi_ad9152_dma.m_src_axi sys_ddr3_cntrl.ctrl_amm_0 +add_connection sys_cpu.irq axi_ad9152_dma.interrupt_sender + +# ad9680-xcvr + +add_instance avl_ad9680_xcvr avl_adxcvr 1.0 +set_instance_parameter_value avl_ad9680_xcvr {ID} {1} +set_instance_parameter_value avl_ad9680_xcvr {TX_OR_RX_N} {0} +set_instance_parameter_value avl_ad9680_xcvr {PCS_CONFIG} {JESD_PCS_CFG2} +set_instance_parameter_value avl_ad9680_xcvr {LANE_RATE} {10000.0} +set_instance_parameter_value avl_ad9680_xcvr {PLLCLK_FREQUENCY} {5000.0} +set_instance_parameter_value avl_ad9680_xcvr {REFCLK_FREQUENCY} {500.0} +set_instance_parameter_value avl_ad9680_xcvr {CORECLK_FREQUENCY} {250.0} +set_instance_parameter_value avl_ad9680_xcvr {NUM_OF_LANES} {4} +set_instance_parameter_value avl_ad9680_xcvr {NUM_OF_CONVS} {2} +set_instance_parameter_value avl_ad9680_xcvr {FRM_BCNT} {1} +set_instance_parameter_value avl_ad9680_xcvr {FRM_SCNT} {1} +set_instance_parameter_value avl_ad9680_xcvr {MF_FCNT} {32} +set_instance_parameter_value avl_ad9680_xcvr {HD} {1} + +add_connection sys_clk.clk avl_ad9680_xcvr.sys_clk +add_connection sys_clk.clk_reset avl_ad9680_xcvr.sys_resetn +add_interface rx_ref_clk clock sink +set_interface_property rx_ref_clk EXPORT_OF avl_ad9680_xcvr.ref_clk +add_interface rx_data_0 conduit end +set_interface_property rx_data_0 EXPORT_OF avl_ad9680_xcvr.rx_data_0 +add_interface rx_data_1 conduit end +set_interface_property rx_data_1 EXPORT_OF avl_ad9680_xcvr.rx_data_1 +add_interface rx_data_2 conduit end +set_interface_property rx_data_2 EXPORT_OF avl_ad9680_xcvr.rx_data_2 +add_interface rx_data_3 conduit end +set_interface_property rx_data_3 EXPORT_OF avl_ad9680_xcvr.rx_data_3 +add_interface rx_sysref conduit end +set_interface_property rx_sysref EXPORT_OF avl_ad9680_xcvr.sysref +add_interface rx_sync conduit end +set_interface_property rx_sync EXPORT_OF avl_ad9680_xcvr.sync +add_connection sys_cpu.data_master avl_ad9680_xcvr.core_pll_reconfig +add_connection sys_cpu.data_master avl_ad9680_xcvr.ip_reconfig + +# ad9680-xcvr + +add_instance axi_ad9680_xcvr axi_adxcvr 1.0 +set_instance_parameter_value axi_ad9680_xcvr {ID} {1} +set_instance_parameter_value axi_ad9680_xcvr {TX_OR_RX_N} {0} +set_instance_parameter_value axi_ad9680_xcvr {NUM_OF_LANES} {4} + +add_connection sys_clk.clk axi_ad9680_xcvr.s_axi_clock +add_connection sys_clk.clk_reset axi_ad9680_xcvr.s_axi_reset +add_connection axi_ad9680_xcvr.if_up_rst avl_ad9680_xcvr.rst +add_connection avl_ad9680_xcvr.ready axi_ad9680_xcvr.ready +add_connection axi_ad9680_xcvr.core_pll_locked avl_ad9680_xcvr.core_pll_locked +add_connection sys_cpu.data_master axi_ad9680_xcvr.s_axi + +# ad9680 + +add_instance axi_ad9680_core axi_ad9680 1.0 + +add_connection avl_ad9680_xcvr.core_clk axi_ad9680_core.if_rx_clk +add_connection avl_ad9680_xcvr.ip_sof axi_ad9680_core.if_rx_sof +add_connection avl_ad9680_xcvr.ip_data axi_ad9680_core.if_rx_data +add_connection sys_clk.clk_reset axi_ad9680_core.s_axi_reset +add_connection sys_clk.clk axi_ad9680_core.s_axi_clock +add_connection sys_cpu.data_master axi_ad9680_core.s_axi + +# ad9680-pack + +add_instance util_ad9680_cpack util_cpack 1.0 +set_instance_parameter_value util_ad9680_cpack {CHANNEL_DATA_WIDTH} {64} +set_instance_parameter_value util_ad9680_cpack {NUM_OF_CHANNELS} {2} + +add_connection sys_clk.clk_reset util_ad9680_cpack.if_adc_rst +add_connection sys_ddr3_cntrl.emif_usr_reset_n util_ad9680_cpack.if_adc_rst +add_connection avl_ad9680_xcvr.core_clk util_ad9680_cpack.if_adc_clk +add_connection axi_ad9680_core.adc_ch_0 util_ad9680_cpack.adc_ch_0 +add_connection axi_ad9680_core.adc_ch_1 util_ad9680_cpack.adc_ch_1 + +# ad9680-fifo + +add_instance ad9680_adcfifo util_adcfifo 1.0 +set_instance_parameter_value ad9680_adcfifo {ADC_DATA_WIDTH} {128} +set_instance_parameter_value ad9680_adcfifo {DMA_DATA_WIDTH} {128} +set_instance_parameter_value ad9680_adcfifo {DMA_ADDRESS_WIDTH} {16} + +add_connection sys_clk.clk_reset ad9680_adcfifo.if_adc_rst +add_connection sys_ddr3_cntrl.emif_usr_reset_n ad9680_adcfifo.if_adc_rst +add_connection avl_ad9680_xcvr.core_clk ad9680_adcfifo.if_adc_clk +add_connection util_ad9680_cpack.if_adc_valid ad9680_adcfifo.if_adc_wr +add_connection util_ad9680_cpack.if_adc_data ad9680_adcfifo.if_adc_wdata +add_connection sys_ddr3_cntrl.emif_usr_clk ad9680_adcfifo.if_dma_clk + +# ad9680-dma + +add_instance axi_ad9680_dma axi_dmac 1.0 +set_instance_parameter_value axi_ad9680_dma {DMA_DATA_WIDTH_SRC} {128} +set_instance_parameter_value axi_ad9680_dma {DMA_DATA_WIDTH_DEST} {128} +set_instance_parameter_value axi_ad9680_dma {DMA_LENGTH_WIDTH} {24} +set_instance_parameter_value axi_ad9680_dma {DMA_2D_TRANSFER} {0} +set_instance_parameter_value axi_ad9680_dma {SYNC_TRANSFER_START} {1} +set_instance_parameter_value axi_ad9680_dma {CYCLIC} {0} +set_instance_parameter_value axi_ad9680_dma {DMA_TYPE_DEST} {0} +set_instance_parameter_value axi_ad9680_dma {DMA_TYPE_SRC} {1} + +add_connection sys_ddr3_cntrl.emif_usr_clk axi_ad9680_dma.if_s_axis_aclk +add_connection ad9680_adcfifo.if_dma_wr axi_ad9680_dma.if_s_axis_valid +add_connection ad9680_adcfifo.if_dma_wdata axi_ad9680_dma.if_s_axis_data +add_connection ad9680_adcfifo.if_dma_wready axi_ad9680_dma.if_s_axis_ready +add_connection ad9680_adcfifo.if_dma_xfer_req axi_ad9680_dma.if_s_axis_xfer_req +add_connection ad9680_adcfifo.if_adc_wovf axi_ad9680_core.if_adc_dovf +add_connection sys_clk.clk_reset axi_ad9680_dma.s_axi_reset +add_connection sys_clk.clk axi_ad9680_dma.s_axi_clock +add_connection sys_cpu.data_master axi_ad9680_dma.s_axi +add_connection sys_ddr3_cntrl.emif_usr_reset_n axi_ad9680_dma.m_dest_axi_reset +add_connection sys_ddr3_cntrl.emif_usr_clk axi_ad9680_dma.m_dest_axi_clock +add_connection axi_ad9680_dma.m_dest_axi sys_ddr3_cntrl.ctrl_amm_0 +add_connection sys_cpu.irq axi_ad9680_dma.interrupt_sender + +# reconfig sharing + +add_instance avl_adxcfg_0 avl_adxcfg 1.0 +add_connection sys_clk.clk avl_adxcfg_0.rcfg_clk +add_connection sys_clk.clk_reset avl_adxcfg_0.rcfg_reset_n +add_connection sys_cpu.data_master avl_adxcfg_0.rcfg_s0 +add_connection sys_cpu.data_master avl_adxcfg_0.rcfg_s1 +add_connection avl_adxcfg_0.rcfg_m0 avl_ad9152_xcvr.phy_reconfig_0 +add_connection avl_adxcfg_0.rcfg_m1 avl_ad9680_xcvr.phy_reconfig_0 + +add_instance avl_adxcfg_1 avl_adxcfg 1.0 +add_connection sys_clk.clk avl_adxcfg_1.rcfg_clk +add_connection sys_clk.clk_reset avl_adxcfg_1.rcfg_reset_n +add_connection sys_cpu.data_master avl_adxcfg_1.rcfg_s0 +add_connection sys_cpu.data_master avl_adxcfg_1.rcfg_s1 +add_connection avl_adxcfg_1.rcfg_m0 avl_ad9152_xcvr.phy_reconfig_1 +add_connection avl_adxcfg_1.rcfg_m1 avl_ad9680_xcvr.phy_reconfig_1 + +add_instance avl_adxcfg_2 avl_adxcfg 1.0 +add_connection sys_clk.clk avl_adxcfg_2.rcfg_clk +add_connection sys_clk.clk_reset avl_adxcfg_2.rcfg_reset_n +add_connection sys_cpu.data_master avl_adxcfg_2.rcfg_s0 +add_connection sys_cpu.data_master avl_adxcfg_2.rcfg_s1 +add_connection avl_adxcfg_2.rcfg_m0 avl_ad9152_xcvr.phy_reconfig_2 +add_connection avl_adxcfg_2.rcfg_m1 avl_ad9680_xcvr.phy_reconfig_2 + +add_instance avl_adxcfg_3 avl_adxcfg 1.0 +add_connection sys_clk.clk avl_adxcfg_3.rcfg_clk +add_connection sys_clk.clk_reset avl_adxcfg_3.rcfg_reset_n +add_connection sys_cpu.data_master avl_adxcfg_3.rcfg_s0 +add_connection sys_cpu.data_master avl_adxcfg_3.rcfg_s1 +add_connection avl_adxcfg_3.rcfg_m0 avl_ad9152_xcvr.phy_reconfig_3 +add_connection avl_adxcfg_3.rcfg_m1 avl_ad9680_xcvr.phy_reconfig_3 + +# addresses + +set_connection_parameter_value sys_cpu.data_master/avl_ad9152_xcvr.core_pll_reconfig baseAddress {0x10400000} +set_connection_parameter_value sys_cpu.data_master/avl_ad9152_xcvr.ip_reconfig baseAddress {0x10401000} +set_connection_parameter_value sys_cpu.data_master/avl_ad9152_xcvr.lane_pll_reconfig baseAddress {0x10402000} +set_connection_parameter_value sys_cpu.data_master/axi_ad9152_dma.s_axi baseAddress {0x1040c000} +set_connection_parameter_value sys_cpu.data_master/axi_ad9152_xcvr.s_axi baseAddress {0x10410000} +set_connection_parameter_value sys_cpu.data_master/axi_ad9152_core.s_axi baseAddress {0x10420000} +set_connection_parameter_value sys_cpu.data_master/avl_ad9680_xcvr.core_pll_reconfig baseAddress {0x10500000} +set_connection_parameter_value sys_cpu.data_master/avl_ad9680_xcvr.ip_reconfig baseAddress {0x10501000} +set_connection_parameter_value sys_cpu.data_master/axi_ad9680_dma.s_axi baseAddress {0x1050c000} +set_connection_parameter_value sys_cpu.data_master/axi_ad9680_xcvr.s_axi baseAddress {0x10510000} +set_connection_parameter_value sys_cpu.data_master/axi_ad9680_core.s_axi baseAddress {0x10520000} +set_connection_parameter_value axi_ad9152_dma.m_src_axi/sys_ddr3_cntrl.ctrl_amm_0 baseAddress {0x00000000} +set_connection_parameter_value axi_ad9680_dma.m_dest_axi/sys_ddr3_cntrl.ctrl_amm_0 baseAddress {0x00000000} +set_connection_parameter_value sys_cpu.data_master/avl_adxcfg_0.rcfg_s0 baseAddress {0x10404000} +set_connection_parameter_value sys_cpu.data_master/avl_adxcfg_1.rcfg_s0 baseAddress {0x10405000} +set_connection_parameter_value sys_cpu.data_master/avl_adxcfg_2.rcfg_s0 baseAddress {0x10406000} +set_connection_parameter_value sys_cpu.data_master/avl_adxcfg_3.rcfg_s0 baseAddress {0x10407000} +set_connection_parameter_value sys_cpu.data_master/avl_adxcfg_0.rcfg_s1 baseAddress {0x10504000} +set_connection_parameter_value sys_cpu.data_master/avl_adxcfg_1.rcfg_s1 baseAddress {0x10505000} +set_connection_parameter_value sys_cpu.data_master/avl_adxcfg_2.rcfg_s1 baseAddress {0x10506000} +set_connection_parameter_value sys_cpu.data_master/avl_adxcfg_3.rcfg_s1 baseAddress {0x10507000} + +# interrupts + +set_connection_parameter_value sys_cpu.irq/axi_ad9680_dma.interrupt_sender irqNumber {10} +set_connection_parameter_value sys_cpu.irq/axi_ad9152_dma.interrupt_sender irqNumber {11} + diff --git a/projects/daq3/common/daq3_spi.v b/projects/daq3/common/daq3_spi.v index 8236ddace..421163489 100644 --- a/projects/daq3/common/daq3_spi.v +++ b/projects/daq3/common/daq3_spi.v @@ -103,6 +103,8 @@ module daq3_spi ( assign spi_miso = spi_sdio; assign spi_sdio = (spi_enable_s == 1'b1) ? 1'bz : spi_mosi; + assign spi_miso = spi_sdio; + assign spi_sdio = (spi_enable_s == 1'b1) ? 1'bz : spi_mosi; endmodule diff --git a/projects/daq3/kcu105/Makefile b/projects/daq3/kcu105/Makefile new file mode 100644 index 000000000..881140d7d --- /dev/null +++ b/projects/daq3/kcu105/Makefile @@ -0,0 +1,87 @@ +#################################################################################### +#################################################################################### +## Copyright 2011(c) Analog Devices, Inc. +## Auto-generated, do not modify! +#################################################################################### +#################################################################################### + +M_DEPS += system_top.v +M_DEPS += system_project.tcl +M_DEPS += system_constr.xdc +M_DEPS += system_bd.tcl +M_DEPS += ../common/daq3_spi.v +M_DEPS += ../common/daq3_bd.tcl +M_DEPS += ../../scripts/adi_project.tcl +M_DEPS += ../../scripts/adi_env.tcl +M_DEPS += ../../scripts/adi_board.tcl +M_DEPS += ../../common/xilinx/sys_dacfifo.tcl +M_DEPS += ../../common/xilinx/sys_adcfifo.tcl +M_DEPS += ../../common/kcu105/kcu105_system_constr.xdc +M_DEPS += ../../common/kcu105/kcu105_system_bd.tcl +M_DEPS += ../../../library/xilinx/common/ad_iobuf.v +M_DEPS += ../../../library/axi_ad9152/axi_ad9152.xpr +M_DEPS += ../../../library/axi_ad9680/axi_ad9680.xpr +M_DEPS += ../../../library/xilinx/axi_adxcvr/axi_adxcvr.xpr +M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr +M_DEPS += ../../../library/util_adcfifo/util_adcfifo.xpr +M_DEPS += ../../../library/xilinx/util_adxcvr/util_adxcvr.xpr +M_DEPS += ../../../library/util_cpack/util_cpack.xpr +M_DEPS += ../../../library/util_dacfifo/util_dacfifo.xpr +M_DEPS += ../../../library/util_upack/util_upack.xpr + +M_VIVADO := vivado -mode batch -source + +M_FLIST := *.cache +M_FLIST += *.data +M_FLIST += *.xpr +M_FLIST += *.log +M_FLIST += *.jou +M_FLIST += xgui +M_FLIST += *.runs +M_FLIST += *.srcs +M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim +M_FLIST += .Xil +M_FLIST += *.ip_user_files + + + +.PHONY: all lib clean clean-all +all: lib daq3_kcu105.sdk/system_top.hdf + + +clean: + rm -rf $(M_FLIST) + + +clean-all:clean + make -C ../../../library/axi_ad9152 clean + make -C ../../../library/axi_ad9680 clean + make -C ../../../library/xilinx/axi_adxcvr clean + make -C ../../../library/axi_dmac clean + make -C ../../../library/util_adcfifo clean + make -C ../../../library/xilinx/util_adxcvr clean + make -C ../../../library/util_cpack clean + make -C ../../../library/util_dacfifo clean + make -C ../../../library/util_upack clean + + +daq3_kcu105.sdk/system_top.hdf: $(M_DEPS) + -rm -rf $(M_FLIST) + $(M_VIVADO) system_project.tcl >> daq3_kcu105_vivado.log 2>&1 + + +lib: + make -C ../../../library/axi_ad9152 + make -C ../../../library/axi_ad9680 + make -C ../../../library/xilinx/axi_adxcvr + make -C ../../../library/axi_dmac + make -C ../../../library/util_adcfifo + make -C ../../../library/xilinx/util_adxcvr + make -C ../../../library/util_cpack + make -C ../../../library/util_dacfifo + make -C ../../../library/util_upack + +#################################################################################### +#################################################################################### diff --git a/projects/daq3/kcu105/system_bd.tcl b/projects/daq3/kcu105/system_bd.tcl new file mode 100644 index 000000000..a4f92f78a --- /dev/null +++ b/projects/daq3/kcu105/system_bd.tcl @@ -0,0 +1,14 @@ + +source $ad_hdl_dir/projects/common/kcu105/kcu105_system_bd.tcl +source $ad_hdl_dir/projects/common/xilinx/sys_adcfifo.tcl +source $ad_hdl_dir/projects/common/xilinx/sys_dacfifo.tcl + +p_sys_adcfifo [current_bd_instance .] axi_ad9680_fifo 128 16 +p_sys_dacfifo [current_bd_instance .] axi_ad9152_fifo 128 10 + +source ../common/daq3_bd.tcl + +set_property -dict [list CONFIG.XCVR_TYPE {1}] $util_daq3_xcvr +set_property -dict [list CONFIG.QPLL_FBDIV {20}] $util_daq3_xcvr +set_property -dict [list CONFIG.QPLL_REFCLK_DIV {1}] $util_daq3_xcvr + diff --git a/projects/daq3/kcu105/system_constr.xdc b/projects/daq3/kcu105/system_constr.xdc new file mode 100644 index 000000000..a04eb88b0 --- /dev/null +++ b/projects/daq3/kcu105/system_constr.xdc @@ -0,0 +1,72 @@ + +# daq3 + +set_property -dict {PACKAGE_PIN H6} [get_ports rx_ref_clk_p] ; ## B20 FMC_HPC_GBTCLK1_M2C_P +set_property -dict {PACKAGE_PIN H5} [get_ports rx_ref_clk_n] ; ## B21 FMC_HPC_GBTCLK1_M2C_N +set_property -dict {PACKAGE_PIN G9 IOSTANDARD LVDS} [get_ports rx_sync_p] ; ## D08 FMC_HPC_LA01_CC_P +set_property -dict {PACKAGE_PIN F9 IOSTANDARD LVDS} [get_ports rx_sync_n] ; ## D09 FMC_HPC_LA01_CC_N +set_property -dict {PACKAGE_PIN A13 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports rx_sysref_p] ; ## G09 FMC_HPC_LA03_P +set_property -dict {PACKAGE_PIN A12 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports rx_sysref_n] ; ## G10 FMC_HPC_LA03_N + +set_property -dict {PACKAGE_PIN K6} [get_ports tx_ref_clk_p] ; ## D04 FMC_HPC_GBTCLK0_M2C_P +set_property -dict {PACKAGE_PIN K5} [get_ports tx_ref_clk_n] ; ## D05 FMC_HPC_GBTCLK0_M2C_N +set_property -dict {PACKAGE_PIN K10 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports tx_sync_p] ; ## H07 FMC_HPC_LA02_P +set_property -dict {PACKAGE_PIN J10 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports tx_sync_n] ; ## H08 FMC_HPC_LA02_N +set_property -dict {PACKAGE_PIN L12 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports tx_sysref_p] ; ## H10 FMC_HPC_LA04_P +set_property -dict {PACKAGE_PIN K12 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports tx_sysref_n] ; ## H11 FMC_HPC_LA04_N + +set_property -dict {PACKAGE_PIN L13 IOSTANDARD LVCMOS18} [get_ports spi_csn_clk] ; ## D11 FMC_HPC_LA05_P +set_property -dict {PACKAGE_PIN L8 IOSTANDARD LVCMOS18} [get_ports spi_csn_dac] ; ## C14 FMC_HPC_LA10_P +set_property -dict {PACKAGE_PIN H9 IOSTANDARD LVCMOS18} [get_ports spi_csn_adc] ; ## D15 FMC_HPC_LA09_N +set_property -dict {PACKAGE_PIN K13 IOSTANDARD LVCMOS18} [get_ports spi_clk] ; ## D12 FMC_HPC_LA05_N +set_property -dict {PACKAGE_PIN J9 IOSTANDARD LVCMOS18} [get_ports spi_sdio] ; ## D14 FMC_HPC_LA09_P +set_property -dict {PACKAGE_PIN C13 IOSTANDARD LVCMOS18} [get_ports spi_dir] ; ## C11 FMC_HPC_LA06_N + +set_property -dict {PACKAGE_PIN D9 IOSTANDARD LVDS} [get_ports sysref_p] ; ## D17 FMC_HPC_LA13_P +set_property -dict {PACKAGE_PIN C9 IOSTANDARD LVDS} [get_ports sysref_n] ; ## D18 FMC_HPC_LA13_N +set_property -dict {PACKAGE_PIN D10 IOSTANDARD LVCMOS18} [get_ports dac_txen] ; ## G16 FMC_HPC_LA12_N +set_property -dict {PACKAGE_PIN D13 IOSTANDARD LVCMOS18} [get_ports adc_pd] ; ## C10 FMC_HPC_LA06_P + +set_property -dict {PACKAGE_PIN J8 IOSTANDARD LVCMOS18} [get_ports clkd_status[0]] ; ## G12 FMC_HPC_LA08_P +set_property -dict {PACKAGE_PIN H8 IOSTANDARD LVCMOS18} [get_ports clkd_status[1]] ; ## G13 FMC_HPC_LA08_N +set_property -dict {PACKAGE_PIN E10 IOSTANDARD LVCMOS18} [get_ports dac_irq] ; ## G15 FMC_HPC_LA12_P +set_property -dict {PACKAGE_PIN K11 IOSTANDARD LVCMOS18} [get_ports adc_fda] ; ## H16 FMC_HPC_LA11_P +set_property -dict {PACKAGE_PIN J11 IOSTANDARD LVCMOS18} [get_ports adc_fdb] ; ## H17 FMC_HPC_LA11_N + +set_property -dict {PACKAGE_PIN F8 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports trig_p] ; ## H13 FMC_HPC_LA07_P +set_property -dict {PACKAGE_PIN E8 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports trig_n] ; ## H14 FMC_HPC_LA07_N + +# clocks + +create_clock -name tx_ref_clk -period 1.60 [get_ports tx_ref_clk_p] +create_clock -name rx_ref_clk -period 1.60 [get_ports rx_ref_clk_p] +create_clock -name tx_div_clk -period 3.20 [get_pins i_system_wrapper/system_i/util_daq3_xcvr/inst/i_xch_0/i_gthe3_channel/TXOUTCLK] +create_clock -name rx_div_clk -period 3.20 [get_pins i_system_wrapper/system_i/util_daq3_xcvr/inst/i_xch_0/i_gthe3_channel/RXOUTCLK] + +# gt pin assignments below are for reference only and are ignored by the tool! + +## set_property -dict {PACKAGE_PIN A4} [get_ports rx_data_p[0]] ; ## A10 FMC_HPC_DP3_M2C_P +## set_property -dict {PACKAGE_PIN A3} [get_ports rx_data_n[0]] ; ## A11 FMC_HPC_DP3_M2C_N +## set_property -dict {PACKAGE_PIN E4} [get_ports rx_data_p[1]] ; ## C06 FMC_HPC_DP0_M2C_P +## set_property -dict {PACKAGE_PIN E3} [get_ports rx_data_n[1]] ; ## C07 FMC_HPC_DP0_M2C_N +## set_property -dict {PACKAGE_PIN B2} [get_ports rx_data_p[2]] ; ## A06 FMC_HPC_DP2_M2C_P +## set_property -dict {PACKAGE_PIN B1} [get_ports rx_data_n[2]] ; ## A07 FMC_HPC_DP2_M2C_N +## set_property -dict {PACKAGE_PIN D2} [get_ports rx_data_p[3]] ; ## A02 FMC_HPC_DP1_M2C_P +## set_property -dict {PACKAGE_PIN D1} [get_ports rx_data_n[3]] ; ## A03 FMC_HPC_DP1_M2C_N +## set_property -dict {PACKAGE_PIN B6} [get_ports tx_data_p[0]] ; ## A30 FMC_HPC_DP3_C2M_P (tx_data_p[0]) +## set_property -dict {PACKAGE_PIN B5} [get_ports tx_data_n[0]] ; ## A31 FMC_HPC_DP3_C2M_N (tx_data_n[0]) +## set_property -dict {PACKAGE_PIN F6} [get_ports tx_data_p[1]] ; ## C02 FMC_HPC_DP0_C2M_P (tx_data_p[3]) +## set_property -dict {PACKAGE_PIN F5} [get_ports tx_data_n[1]] ; ## C03 FMC_HPC_DP0_C2M_N (tx_data_n[3]) +## set_property -dict {PACKAGE_PIN C4} [get_ports tx_data_p[2]] ; ## A26 FMC_HPC_DP2_C2M_P (tx_data_p[1]) +## set_property -dict {PACKAGE_PIN C3} [get_ports tx_data_n[2]] ; ## A27 FMC_HPC_DP2_C2M_N (tx_data_n[1]) +## set_property -dict {PACKAGE_PIN D6} [get_ports tx_data_p[3]] ; ## A22 FMC_HPC_DP1_C2M_P (tx_data_p[2]) +## set_property -dict {PACKAGE_PIN D5} [get_ports tx_data_n[3]] ; ## A23 FMC_HPC_DP1_C2M_N (tx_data_n[2]) + +set_property LOC GTHE3_CHANNEL_X0Y19 [get_cells -hierarchical -filter {NAME =~ *util_daq3_xcvr/inst/i_xch_0/i_gthe3_channel}] +set_property LOC GTHE3_CHANNEL_X0Y16 [get_cells -hierarchical -filter {NAME =~ *util_daq3_xcvr/inst/i_xch_1/i_gthe3_channel}] +set_property LOC GTHE3_CHANNEL_X0Y18 [get_cells -hierarchical -filter {NAME =~ *util_daq3_xcvr/inst/i_xch_2/i_gthe3_channel}] +set_property LOC GTHE3_CHANNEL_X0Y17 [get_cells -hierarchical -filter {NAME =~ *util_daq3_xcvr/inst/i_xch_3/i_gthe3_channel}] + +set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9680_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]*] +set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9152_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]*] + diff --git a/projects/pzsdr/ccfmc/system_project.tcl b/projects/daq3/kcu105/system_project.tcl similarity index 52% rename from projects/pzsdr/ccfmc/system_project.tcl rename to projects/daq3/kcu105/system_project.tcl index 06d99afc3..db5948939 100644 --- a/projects/pzsdr/ccfmc/system_project.tcl +++ b/projects/daq3/kcu105/system_project.tcl @@ -5,16 +5,17 @@ source ../../scripts/adi_env.tcl source $ad_hdl_dir/projects/scripts/adi_project.tcl source $ad_hdl_dir/projects/scripts/adi_board.tcl -adi_project_create ccfmc_pzsdr -adi_project_files ccfmc_pzsdr [list \ +adi_project_create daq3_kcu105 +adi_project_files daq3_kcu105 [list \ + "../common/daq3_spi.v" \ "system_top.v" \ "system_constr.xdc"\ - "$ad_hdl_dir/library/common/ad_iobuf.v" \ - "$ad_hdl_dir/projects/common/pzsdr/pzsdr_system_constr.xdc" ] + "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \ + "$ad_hdl_dir/projects/common/kcu105/kcu105_system_constr.xdc" ] -set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/pzsdr/pzsdr_system_constr.xdc] +set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/kcu105/kcu105_system_constr.xdc] set_property PROCESSING_ORDER EARLY [get_files system_constr.xdc] -adi_project_run ccfmc_pzsdr +adi_project_run daq3_kcu105 diff --git a/projects/daq3/kcu105/system_top.v b/projects/daq3/kcu105/system_top.v new file mode 100644 index 000000000..4396a35bf --- /dev/null +++ b/projects/daq3/kcu105/system_top.v @@ -0,0 +1,374 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top ( + + sys_rst, + sys_clk_p, + sys_clk_n, + + uart_sin, + uart_sout, + + ddr4_act_n, + ddr4_addr, + ddr4_ba, + ddr4_bg, + ddr4_ck_p, + ddr4_ck_n, + ddr4_cke, + ddr4_cs_n, + ddr4_dm_n, + ddr4_dq, + ddr4_dqs_p, + ddr4_dqs_n, + ddr4_odt, + ddr4_reset_n, + + mdio_mdc, + mdio_mdio, + phy_clk_p, + phy_clk_n, + phy_rst_n, + phy_rx_p, + phy_rx_n, + phy_tx_p, + phy_tx_n, + + fan_pwm, + + gpio_bd, + + iic_scl, + iic_sda, + + rx_ref_clk_p, + rx_ref_clk_n, + rx_sysref_p, + rx_sysref_n, + rx_sync_p, + rx_sync_n, + rx_data_p, + rx_data_n, + + tx_ref_clk_p, + tx_ref_clk_n, + tx_sysref_p, + tx_sysref_n, + tx_sync_p, + tx_sync_n, + tx_data_p, + tx_data_n, + + trig_p, + trig_n, + + adc_fdb, + adc_fda, + dac_irq, + clkd_status, + + adc_pd, + dac_txen, + sysref_p, + sysref_n, + + spi_csn_clk, + spi_csn_dac, + spi_csn_adc, + spi_clk, + spi_sdio, + spi_dir); + + input sys_rst; + input sys_clk_p; + input sys_clk_n; + + input uart_sin; + output uart_sout; + + output ddr4_act_n; + output [16:0] ddr4_addr; + output [ 1:0] ddr4_ba; + output [ 0:0] ddr4_bg; + output ddr4_ck_p; + output ddr4_ck_n; + output [ 0:0] ddr4_cke; + output [ 0:0] ddr4_cs_n; + inout [ 7:0] ddr4_dm_n; + inout [63:0] ddr4_dq; + inout [ 7:0] ddr4_dqs_p; + inout [ 7:0] ddr4_dqs_n; + output [ 0:0] ddr4_odt; + output ddr4_reset_n; + + output mdio_mdc; + inout mdio_mdio; + input phy_clk_p; + input phy_clk_n; + output phy_rst_n; + input phy_rx_p; + input phy_rx_n; + output phy_tx_p; + output phy_tx_n; + + output fan_pwm; + + inout [16:0] gpio_bd; + + inout iic_scl; + inout iic_sda; + + input rx_ref_clk_p; + input rx_ref_clk_n; + input rx_sysref_p; + input rx_sysref_n; + output rx_sync_p; + output rx_sync_n; + input [ 3:0] rx_data_p; + input [ 3:0] rx_data_n; + + input tx_ref_clk_p; + input tx_ref_clk_n; + input tx_sysref_p; + input tx_sysref_n; + input tx_sync_p; + input tx_sync_n; + output [ 3:0] tx_data_p; + output [ 3:0] tx_data_n; + + input trig_p; + input trig_n; + + inout adc_fdb; + inout adc_fda; + inout dac_irq; + inout [ 1:0] clkd_status; + + inout adc_pd; + inout dac_txen; + output sysref_p; + output sysref_n; + + output spi_csn_clk; + output spi_csn_dac; + output spi_csn_adc; + output spi_clk; + inout spi_sdio; + output spi_dir; + + // internal signals + + wire [63:0] gpio_i; + wire [63:0] gpio_o; + wire [63:0] gpio_t; + wire [ 7:0] spi_csn; + wire spi_mosi; + wire spi_miso; + wire trig; + wire rx_ref_clk; + wire rx_sysref; + wire rx_sync; + wire tx_ref_clk; + wire tx_sysref; + wire tx_sync; + + // spi + + assign spi_csn_adc = spi_csn[2]; + assign spi_csn_dac = spi_csn[1]; + assign spi_csn_clk = spi_csn[0]; + + // default logic + + assign fan_pwm = 1'b1; + + // instantiations + + IBUFDS_GTE3 i_ibufds_rx_ref_clk ( + .CEB (1'd0), + .I (rx_ref_clk_p), + .IB (rx_ref_clk_n), + .O (rx_ref_clk), + .ODIV2 ()); + + IBUFDS i_ibufds_rx_sysref ( + .I (rx_sysref_p), + .IB (rx_sysref_n), + .O (rx_sysref)); + + OBUFDS i_obufds_rx_sync ( + .I (rx_sync), + .O (rx_sync_p), + .OB (rx_sync_n)); + + IBUFDS_GTE3 i_ibufds_tx_ref_clk ( + .CEB (1'd0), + .I (tx_ref_clk_p), + .IB (tx_ref_clk_n), + .O (tx_ref_clk), + .ODIV2 ()); + + IBUFDS i_ibufds_tx_sysref ( + .I (tx_sysref_p), + .IB (tx_sysref_n), + .O (tx_sysref)); + + IBUFDS i_ibufds_tx_sync ( + .I (tx_sync_p), + .IB (tx_sync_n), + .O (tx_sync)); + + daq3_spi i_spi ( + .spi_csn (spi_csn[2:0]), + .spi_clk (spi_clk), + .spi_mosi (spi_mosi), + .spi_miso (spi_miso), + .spi_sdio (spi_sdio), + .spi_dir (spi_dir)); + + OBUFDS i_obufds_sysref ( + .I (gpio_o[40]), + .O (sysref_p), + .OB (sysref_n)); + + IBUFDS i_ibufds_trig ( + .I (trig_p), + .IB (trig_n), + .O (trig)); + + assign gpio_i[39] = trig; + + ad_iobuf #(.DATA_WIDTH(7)) i_iobuf ( + .dio_t (gpio_t[38:32]), + .dio_i (gpio_o[38:32]), + .dio_o (gpio_i[38:32]), + .dio_p ({ adc_pd, // 38 + dac_txen, // 37 + adc_fdb, // 36 + adc_fda, // 35 + dac_irq, // 34 + clkd_status})); // 32 + + ad_iobuf #(.DATA_WIDTH(17)) i_iobuf_bd ( + .dio_t (gpio_t[16:0]), + .dio_i (gpio_o[16:0]), + .dio_o (gpio_i[16:0]), + .dio_p (gpio_bd)); + + system_wrapper i_system_wrapper ( + .c0_ddr4_act_n (ddr4_act_n), + .c0_ddr4_adr (ddr4_addr), + .c0_ddr4_ba (ddr4_ba), + .c0_ddr4_bg (ddr4_bg), + .c0_ddr4_ck_c (ddr4_ck_n), + .c0_ddr4_ck_t (ddr4_ck_p), + .c0_ddr4_cke (ddr4_cke), + .c0_ddr4_cs_n (ddr4_cs_n), + .c0_ddr4_dm_n (ddr4_dm_n), + .c0_ddr4_dq (ddr4_dq), + .c0_ddr4_dqs_c (ddr4_dqs_n), + .c0_ddr4_dqs_t (ddr4_dqs_p), + .c0_ddr4_odt (ddr4_odt), + .c0_ddr4_reset_n (ddr4_reset_n), + .gpio0_i (gpio_i[31:0]), + .gpio0_o (gpio_o[31:0]), + .gpio0_t (gpio_t[31:0]), + .gpio1_i (gpio_i[63:32]), + .gpio1_o (gpio_o[63:32]), + .gpio1_t (gpio_t[63:32]), + .iic_main_scl_io (iic_scl), + .iic_main_sda_io (iic_sda), + .mb_intr_05 (1'b0), + .mb_intr_06 (1'b0), + .mb_intr_07 (1'b0), + .mb_intr_08 (1'b0), + .mb_intr_14 (1'b0), + .mb_intr_15 (1'b0), + .mdio_mdc (mdio_mdc), + .mdio_mdio_io (mdio_mdio), + .phy_clk_clk_n (phy_clk_n), + .phy_clk_clk_p (phy_clk_p), + .phy_rst_n (phy_rst_n), + .phy_sd (1'b1), + .rx_data_0_n (rx_data_n[0]), + .rx_data_0_p (rx_data_p[0]), + .rx_data_1_n (rx_data_n[1]), + .rx_data_1_p (rx_data_p[1]), + .rx_data_2_n (rx_data_n[2]), + .rx_data_2_p (rx_data_p[2]), + .rx_data_3_n (rx_data_n[3]), + .rx_data_3_p (rx_data_p[3]), + .rx_ref_clk_0 (rx_ref_clk), + .rx_sync_0 (rx_sync), + .rx_sysref_0 (rx_sysref), + .sgmii_rxn (phy_rx_n), + .sgmii_rxp (phy_rx_p), + .sgmii_txn (phy_tx_n), + .sgmii_txp (phy_tx_p), + .spi_clk_i (spi_clk), + .spi_clk_o (spi_clk), + .spi_csn_i (spi_csn), + .spi_csn_o (spi_csn), + .spi_sdi_i (spi_miso), + .spi_sdo_i (spi_mosi), + .spi_sdo_o (spi_mosi), + .sys_clk_clk_n (sys_clk_n), + .sys_clk_clk_p (sys_clk_p), + .sys_rst (sys_rst), + .tx_data_0_n (tx_data_n[0]), + .tx_data_0_p (tx_data_p[0]), + .tx_data_1_n (tx_data_n[1]), + .tx_data_1_p (tx_data_p[1]), + .tx_data_2_n (tx_data_n[2]), + .tx_data_2_p (tx_data_p[2]), + .tx_data_3_n (tx_data_n[3]), + .tx_data_3_p (tx_data_p[3]), + .tx_ref_clk_0 (tx_ref_clk), + .tx_sync_0 (tx_sync), + .tx_sysref_0 (tx_sysref), + .uart_sin (uart_sin), + .uart_sout (uart_sout)); + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/projects/daq3/zc706/Makefile b/projects/daq3/zc706/Makefile index 2e77582c0..61b1853cd 100644 --- a/projects/daq3/zc706/Makefile +++ b/projects/daq3/zc706/Makefile @@ -14,26 +14,24 @@ M_DEPS += ../common/daq3_bd.tcl M_DEPS += ../../scripts/adi_project.tcl M_DEPS += ../../scripts/adi_env.tcl M_DEPS += ../../scripts/adi_board.tcl -M_DEPS += ../../common/zc706/zc706_system_plddr3.tcl +M_DEPS += ../../common/zc706/zc706_system_plddr3_adcfifo.tcl M_DEPS += ../../common/zc706/zc706_system_mig_constr.xdc M_DEPS += ../../common/zc706/zc706_system_mig.prj M_DEPS += ../../common/zc706/zc706_system_constr.xdc M_DEPS += ../../common/zc706/zc706_system_bd.tcl -M_DEPS += ../../common/xilinx/sys_dmafifo.tcl -M_DEPS += ../../../library/common/ad_iobuf.v +M_DEPS += ../../common/xilinx/sys_dacfifo.tcl +M_DEPS += ../../../library/xilinx/common/ad_iobuf.v M_DEPS += ../../../library/axi_ad9152/axi_ad9152.xpr M_DEPS += ../../../library/axi_ad9680/axi_ad9680.xpr -M_DEPS += ../../../library/axi_adcfifo/axi_adcfifo.xpr +M_DEPS += ../../../library/xilinx/axi_adcfifo/axi_adcfifo.xpr +M_DEPS += ../../../library/xilinx/axi_adxcvr/axi_adxcvr.xpr M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr -M_DEPS += ../../../library/axi_jesd_gt/axi_jesd_gt.xpr M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr -M_DEPS += ../../../library/util_adcfifo/util_adcfifo.xpr +M_DEPS += ../../../library/xilinx/util_adxcvr/util_adxcvr.xpr M_DEPS += ../../../library/util_cpack/util_cpack.xpr M_DEPS += ../../../library/util_dacfifo/util_dacfifo.xpr -M_DEPS += ../../../library/util_jesd_gt/util_jesd_gt.xpr -M_DEPS += ../../../library/util_mfifo/util_mfifo.xpr M_DEPS += ../../../library/util_upack/util_upack.xpr M_VIVADO := vivado -mode batch -source @@ -50,6 +48,7 @@ M_FLIST += *.sdk M_FLIST += *.hw M_FLIST += *.sim M_FLIST += .Xil +M_FLIST += *.ip_user_files @@ -64,39 +63,35 @@ clean: clean-all:clean make -C ../../../library/axi_ad9152 clean make -C ../../../library/axi_ad9680 clean - make -C ../../../library/axi_adcfifo clean + make -C ../../../library/xilinx/axi_adcfifo clean + make -C ../../../library/xilinx/axi_adxcvr clean make -C ../../../library/axi_clkgen clean make -C ../../../library/axi_dmac clean make -C ../../../library/axi_hdmi_tx clean - make -C ../../../library/axi_jesd_gt clean make -C ../../../library/axi_spdif_tx clean - make -C ../../../library/util_adcfifo clean + make -C ../../../library/xilinx/util_adxcvr clean make -C ../../../library/util_cpack clean make -C ../../../library/util_dacfifo clean - make -C ../../../library/util_jesd_gt clean - make -C ../../../library/util_mfifo clean make -C ../../../library/util_upack clean daq3_zc706.sdk/system_top.hdf: $(M_DEPS) - rm -rf $(M_FLIST) + -rm -rf $(M_FLIST) $(M_VIVADO) system_project.tcl >> daq3_zc706_vivado.log 2>&1 lib: make -C ../../../library/axi_ad9152 make -C ../../../library/axi_ad9680 - make -C ../../../library/axi_adcfifo + make -C ../../../library/xilinx/axi_adcfifo + make -C ../../../library/xilinx/axi_adxcvr make -C ../../../library/axi_clkgen make -C ../../../library/axi_dmac make -C ../../../library/axi_hdmi_tx - make -C ../../../library/axi_jesd_gt make -C ../../../library/axi_spdif_tx - make -C ../../../library/util_adcfifo + make -C ../../../library/xilinx/util_adxcvr make -C ../../../library/util_cpack make -C ../../../library/util_dacfifo - make -C ../../../library/util_jesd_gt - make -C ../../../library/util_mfifo make -C ../../../library/util_upack #################################################################################### diff --git a/projects/daq3/zc706/system_bd.tcl b/projects/daq3/zc706/system_bd.tcl index 655c77173..17d016d53 100644 --- a/projects/daq3/zc706/system_bd.tcl +++ b/projects/daq3/zc706/system_bd.tcl @@ -1,10 +1,10 @@ source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl -source $ad_hdl_dir/projects/common/zc706/zc706_system_plddr3.tcl -source $ad_hdl_dir/projects/common/xilinx/sys_dmafifo.tcl +source $ad_hdl_dir/projects/common/zc706/zc706_system_plddr3_adcfifo.tcl +source $ad_hdl_dir/projects/common/xilinx/sys_dacfifo.tcl -p_plddr3_fifo [current_bd_instance .] axi_ad9680_fifo 128 p_sys_dacfifo [current_bd_instance .] axi_ad9152_fifo 128 10 +p_plddr3_adcfifo [current_bd_instance .] axi_ad9680_fifo 128 create_bd_port -dir I -type rst sys_rst create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr3 @@ -23,32 +23,3 @@ create_bd_addr_seg -range 0x40000000 -offset 0x80000000 \ source ../common/daq3_bd.tcl -# ila - -set mfifo_adc [create_bd_cell -type ip -vlnv analog.com:user:util_mfifo:1.0 mfifo_adc] -set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $mfifo_adc -set_property -dict [list CONFIG.DIN_DATA_WIDTH {64}] $mfifo_adc -set_property -dict [list CONFIG.ADDRESS_WIDTH {8}] $mfifo_adc - -set ila_adc [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.0 ila_adc] -set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_adc -set_property -dict [list CONFIG.C_TRIGIN_EN {false}] $ila_adc -set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila_adc -set_property -dict [list CONFIG.C_NUM_OF_PROBES {3}] $ila_adc -set_property -dict [list CONFIG.C_PROBE0_WIDTH {1}] $ila_adc -set_property -dict [list CONFIG.C_PROBE1_WIDTH {16}] $ila_adc -set_property -dict [list CONFIG.C_PROBE2_WIDTH {16}] $ila_adc - -ad_connect util_daq3_gt/rx_rst mfifo_adc/din_rst -ad_connect util_daq3_gt/rx_out_clk mfifo_adc/din_clk -ad_connect axi_ad9680_core/adc_valid_0 mfifo_adc/din_valid -ad_connect axi_ad9680_core/adc_data_0 mfifo_adc/din_data_0 -ad_connect axi_ad9680_core/adc_data_1 mfifo_adc/din_data_1 -ad_connect util_daq3_gt/rx_rst mfifo_adc/dout_rst -ad_connect util_daq3_gt/rx_out_clk mfifo_adc/dout_clk -ad_connect util_daq3_gt/rx_out_clk ila_adc/clk -ad_connect mfifo_adc/dout_valid ila_adc/probe0 -ad_connect mfifo_adc/dout_data_0 ila_adc/probe1 -ad_connect mfifo_adc/dout_data_1 ila_adc/probe2 - - diff --git a/projects/daq3/zc706/system_constr.xdc b/projects/daq3/zc706/system_constr.xdc index fd45dcf08..1cfd829a1 100644 --- a/projects/daq3/zc706/system_constr.xdc +++ b/projects/daq3/zc706/system_constr.xdc @@ -1,21 +1,21 @@ -set_property -dict {PACKAGE_PIN AA8 } [get_ports rx_ref_clk_p] ; ## B20 FMC_HPC_GBTCLK1_M2C_P -set_property -dict {PACKAGE_PIN AA7 } [get_ports rx_ref_clk_n] ; ## B21 FMC_HPC_GBTCLK1_M2C_N -set_property -dict {PACKAGE_PIN AE8 } [get_ports rx_data_p[0]] ; ## A10 FMC_HPC_DP3_M2C_P -set_property -dict {PACKAGE_PIN AE7 } [get_ports rx_data_n[0]] ; ## A11 FMC_HPC_DP3_M2C_N -set_property -dict {PACKAGE_PIN AH10} [get_ports rx_data_p[1]] ; ## C06 FMC_HPC_DP0_M2C_P -set_property -dict {PACKAGE_PIN AH9 } [get_ports rx_data_n[1]] ; ## C07 FMC_HPC_DP0_M2C_N -set_property -dict {PACKAGE_PIN AG8 } [get_ports rx_data_p[2]] ; ## A06 FMC_HPC_DP2_M2C_P -set_property -dict {PACKAGE_PIN AG7 } [get_ports rx_data_n[2]] ; ## A07 FMC_HPC_DP2_M2C_N -set_property -dict {PACKAGE_PIN AJ8 } [get_ports rx_data_p[3]] ; ## A02 FMC_HPC_DP1_M2C_P -set_property -dict {PACKAGE_PIN AJ7 } [get_ports rx_data_n[3]] ; ## A03 FMC_HPC_DP1_M2C_N -set_property -dict {PACKAGE_PIN AG21 IOSTANDARD LVDS_25} [get_ports rx_sync_p] ; ## D08 FMC_HPC_LA01_CC_P -set_property -dict {PACKAGE_PIN AH21 IOSTANDARD LVDS_25} [get_ports rx_sync_n] ; ## D09 FMC_HPC_LA01_CC_N -set_property -dict {PACKAGE_PIN AH19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_sysref_p] ; ## G09 FMC_HPC_LA03_P -set_property -dict {PACKAGE_PIN AJ19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_sysref_n] ; ## G10 FMC_HPC_LA03_N +set_property -dict {PACKAGE_PIN AA8 } [get_ports rx_ref_clk_p] ; ## B20 FMC_HPC_GBTCLK1_M2C_P +set_property -dict {PACKAGE_PIN AA7 } [get_ports rx_ref_clk_n] ; ## B21 FMC_HPC_GBTCLK1_M2C_N +set_property -dict {PACKAGE_PIN AE8 } [get_ports rx_data_p[0]] ; ## A10 FMC_HPC_DP3_M2C_P +set_property -dict {PACKAGE_PIN AE7 } [get_ports rx_data_n[0]] ; ## A11 FMC_HPC_DP3_M2C_N +set_property -dict {PACKAGE_PIN AH10} [get_ports rx_data_p[1]] ; ## C06 FMC_HPC_DP0_M2C_P +set_property -dict {PACKAGE_PIN AH9 } [get_ports rx_data_n[1]] ; ## C07 FMC_HPC_DP0_M2C_N +set_property -dict {PACKAGE_PIN AG8 } [get_ports rx_data_p[2]] ; ## A06 FMC_HPC_DP2_M2C_P +set_property -dict {PACKAGE_PIN AG7 } [get_ports rx_data_n[2]] ; ## A07 FMC_HPC_DP2_M2C_N +set_property -dict {PACKAGE_PIN AJ8 } [get_ports rx_data_p[3]] ; ## A02 FMC_HPC_DP1_M2C_P +set_property -dict {PACKAGE_PIN AJ7 } [get_ports rx_data_n[3]] ; ## A03 FMC_HPC_DP1_M2C_N +set_property -dict {PACKAGE_PIN AG21 IOSTANDARD LVDS_25} [get_ports rx_sync_p] ; ## D08 FMC_HPC_LA01_CC_P +set_property -dict {PACKAGE_PIN AH21 IOSTANDARD LVDS_25} [get_ports rx_sync_n] ; ## D09 FMC_HPC_LA01_CC_N +set_property -dict {PACKAGE_PIN AH19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_sysref_p] ; ## G09 FMC_HPC_LA03_P +set_property -dict {PACKAGE_PIN AJ19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_sysref_n] ; ## G10 FMC_HPC_LA03_N -set_property -dict {PACKAGE_PIN AD10} [get_ports tx_ref_clk_p] ; ## D04 FMC_HPC_GBTCLK0_M2C_P -set_property -dict {PACKAGE_PIN AD9 } [get_ports tx_ref_clk_n] ; ## D05 FMC_HPC_GBTCLK0_M2C_N +set_property -dict {PACKAGE_PIN AD10} [get_ports tx_ref_clk_p] ; ## D04 FMC_HPC_GBTCLK0_M2C_P +set_property -dict {PACKAGE_PIN AD9 } [get_ports tx_ref_clk_n] ; ## D05 FMC_HPC_GBTCLK0_M2C_N set_property -dict {PACKAGE_PIN AK2 } [get_ports tx_data_p[0]] ; ## A30 FMC_HPC_DP3_C2M_P (tx_data_p[0]) set_property -dict {PACKAGE_PIN AK1 } [get_ports tx_data_n[0]] ; ## A31 FMC_HPC_DP3_C2M_N (tx_data_n[0]) set_property -dict {PACKAGE_PIN AK10} [get_ports tx_data_p[1]] ; ## C02 FMC_HPC_DP0_C2M_P (tx_data_p[3]) @@ -24,36 +24,39 @@ set_property -dict {PACKAGE_PIN AJ4 } [get_ports tx_data_p[2]] set_property -dict {PACKAGE_PIN AJ3 } [get_ports tx_data_n[2]] ; ## A27 FMC_HPC_DP2_C2M_N (tx_data_n[1]) set_property -dict {PACKAGE_PIN AK6 } [get_ports tx_data_p[3]] ; ## A22 FMC_HPC_DP1_C2M_P (tx_data_p[2]) set_property -dict {PACKAGE_PIN AK5 } [get_ports tx_data_n[3]] ; ## A23 FMC_HPC_DP1_C2M_N (tx_data_n[2]) -set_property -dict {PACKAGE_PIN AK17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sync_p] ; ## H07 FMC_HPC_LA02_P -set_property -dict {PACKAGE_PIN AK18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sync_n] ; ## H08 FMC_HPC_LA02_N -set_property -dict {PACKAGE_PIN AJ20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sysref_p] ; ## H10 FMC_HPC_LA04_P -set_property -dict {PACKAGE_PIN AK20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sysref_n] ; ## H11 FMC_HPC_LA04_N +set_property -dict {PACKAGE_PIN AK17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sync_p] ; ## H07 FMC_HPC_LA02_P +set_property -dict {PACKAGE_PIN AK18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sync_n] ; ## H08 FMC_HPC_LA02_N +set_property -dict {PACKAGE_PIN AJ20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sysref_p] ; ## H10 FMC_HPC_LA04_P +set_property -dict {PACKAGE_PIN AK20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sysref_n] ; ## H11 FMC_HPC_LA04_N -set_property -dict {PACKAGE_PIN AH23 IOSTANDARD LVCMOS25} [get_ports spi_csn_clk] ; ## D11 FMC_HPC_LA05_P -set_property -dict {PACKAGE_PIN AG24 IOSTANDARD LVCMOS25} [get_ports spi_csn_dac] ; ## C14 FMC_HPC_LA10_P -set_property -dict {PACKAGE_PIN AE21 IOSTANDARD LVCMOS25} [get_ports spi_csn_adc] ; ## D15 FMC_HPC_LA09_N -set_property -dict {PACKAGE_PIN AH24 IOSTANDARD LVCMOS25} [get_ports spi_clk] ; ## D12 FMC_HPC_LA05_N -set_property -dict {PACKAGE_PIN AD21 IOSTANDARD LVCMOS25} [get_ports spi_sdio] ; ## D14 FMC_HPC_LA09_P -set_property -dict {PACKAGE_PIN AH22 IOSTANDARD LVCMOS25} [get_ports spi_dir] ; ## C11 FMC_HPC_LA06_N +set_property -dict {PACKAGE_PIN AH23 IOSTANDARD LVCMOS25} [get_ports spi_csn_clk] ; ## D11 FMC_HPC_LA05_P +set_property -dict {PACKAGE_PIN AG24 IOSTANDARD LVCMOS25} [get_ports spi_csn_dac] ; ## C14 FMC_HPC_LA10_P +set_property -dict {PACKAGE_PIN AE21 IOSTANDARD LVCMOS25} [get_ports spi_csn_adc] ; ## D15 FMC_HPC_LA09_N +set_property -dict {PACKAGE_PIN AH24 IOSTANDARD LVCMOS25} [get_ports spi_clk] ; ## D12 FMC_HPC_LA05_N +set_property -dict {PACKAGE_PIN AD21 IOSTANDARD LVCMOS25} [get_ports spi_sdio] ; ## D14 FMC_HPC_LA09_P +set_property -dict {PACKAGE_PIN AH22 IOSTANDARD LVCMOS25} [get_ports spi_dir] ; ## C11 FMC_HPC_LA06_N -set_property -dict {PACKAGE_PIN AA22 IOSTANDARD LVDS_25} [get_ports sysref_p] ; ## D17 FMC_HPC_LA13_P -set_property -dict {PACKAGE_PIN AA23 IOSTANDARD LVDS_25} [get_ports sysref_n] ; ## D18 FMC_HPC_LA13_N -set_property -dict {PACKAGE_PIN AF24 IOSTANDARD LVCMOS25} [get_ports dac_txen] ; ## G16 FMC_HPC_LA12_N -set_property -dict {PACKAGE_PIN AG22 IOSTANDARD LVCMOS25} [get_ports adc_pd] ; ## C10 FMC_HPC_LA06_P +set_property -dict {PACKAGE_PIN AA22 IOSTANDARD LVDS_25} [get_ports sysref_p] ; ## D17 FMC_HPC_LA13_P +set_property -dict {PACKAGE_PIN AA23 IOSTANDARD LVDS_25} [get_ports sysref_n] ; ## D18 FMC_HPC_LA13_N +set_property -dict {PACKAGE_PIN AF24 IOSTANDARD LVCMOS25} [get_ports dac_txen] ; ## G16 FMC_HPC_LA12_N +set_property -dict {PACKAGE_PIN AG22 IOSTANDARD LVCMOS25} [get_ports adc_pd] ; ## C10 FMC_HPC_LA06_P -set_property -dict {PACKAGE_PIN AF19 IOSTANDARD LVCMOS25} [get_ports clkd_status[0]] ; ## G12 FMC_HPC_LA08_P -set_property -dict {PACKAGE_PIN AG19 IOSTANDARD LVCMOS25} [get_ports clkd_status[1]] ; ## G13 FMC_HPC_LA08_N -set_property -dict {PACKAGE_PIN AF23 IOSTANDARD LVCMOS25} [get_ports dac_irq] ; ## G15 FMC_HPC_LA12_P -set_property -dict {PACKAGE_PIN AD23 IOSTANDARD LVCMOS25} [get_ports adc_fda] ; ## H16 FMC_HPC_LA11_P -set_property -dict {PACKAGE_PIN AE23 IOSTANDARD LVCMOS25} [get_ports adc_fdb] ; ## H17 FMC_HPC_LA11_N +set_property -dict {PACKAGE_PIN AF19 IOSTANDARD LVCMOS25} [get_ports clkd_status[0]] ; ## G12 FMC_HPC_LA08_P +set_property -dict {PACKAGE_PIN AG19 IOSTANDARD LVCMOS25} [get_ports clkd_status[1]] ; ## G13 FMC_HPC_LA08_N +set_property -dict {PACKAGE_PIN AF23 IOSTANDARD LVCMOS25} [get_ports dac_irq] ; ## G15 FMC_HPC_LA12_P +set_property -dict {PACKAGE_PIN AD23 IOSTANDARD LVCMOS25} [get_ports adc_fda] ; ## H16 FMC_HPC_LA11_P +set_property -dict {PACKAGE_PIN AE23 IOSTANDARD LVCMOS25} [get_ports adc_fdb] ; ## H17 FMC_HPC_LA11_N -set_property -dict {PACKAGE_PIN AJ23 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports trig_p] ; ## H13 FMC_HPC_LA07_P -set_property -dict {PACKAGE_PIN AJ24 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports trig_n] ; ## H14 FMC_HPC_LA07_N +set_property -dict {PACKAGE_PIN AJ23 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports trig_p] ; ## H13 FMC_HPC_LA07_P +set_property -dict {PACKAGE_PIN AJ24 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports trig_n] ; ## H14 FMC_HPC_LA07_N # clocks -create_clock -name tx_ref_clk -period 2.00 [get_ports tx_ref_clk_p] -create_clock -name rx_ref_clk -period 2.00 [get_ports rx_ref_clk_p] -create_clock -name tx_div_clk -period 4.00 [get_pins i_system_wrapper/system_i/axi_daq3_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/TXOUTCLK] -create_clock -name rx_div_clk -period 4.00 [get_pins i_system_wrapper/system_i/axi_daq3_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK] +create_clock -name tx_ref_clk -period 1.60 [get_ports tx_ref_clk_p] +create_clock -name rx_ref_clk -period 1.60 [get_ports rx_ref_clk_p] +create_clock -name tx_div_clk -period 3.20 [get_pins i_system_wrapper/system_i/util_daq3_xcvr/inst/i_xch_0/i_gtxe2_channel/TXOUTCLK] +create_clock -name rx_div_clk -period 3.20 [get_pins i_system_wrapper/system_i/util_daq3_xcvr/inst/i_xch_0/i_gtxe2_channel/RXOUTCLK] + +set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9680_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]*] +set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9152_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]*] diff --git a/projects/daq3/zc706/system_project.tcl b/projects/daq3/zc706/system_project.tcl index 1d91ac442..281ddab91 100644 --- a/projects/daq3/zc706/system_project.tcl +++ b/projects/daq3/zc706/system_project.tcl @@ -10,13 +10,12 @@ adi_project_files daq3_zc706 [list \ "../common/daq3_spi.v" \ "system_top.v" \ "system_constr.xdc"\ - "$ad_hdl_dir/library/common/ad_iobuf.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \ "$ad_hdl_dir/projects/common/zc706/zc706_system_mig_constr.xdc" \ "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ] -set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc] -set_property PROCESSING_ORDER EARLY [get_files system_constr.xdc] - +set_property part "xc7z045ffg900-3" [get_runs synth_1] +set_property part "xc7z045ffg900-3" [get_runs impl_1] adi_project_run daq3_zc706 diff --git a/projects/daq3/zc706/system_top.v b/projects/daq3/zc706/system_top.v index 1bec5296e..217a9ce2c 100644 --- a/projects/daq3/zc706/system_top.v +++ b/projects/daq3/zc706/system_top.v @@ -34,8 +34,6 @@ // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // *************************************************************************** // *************************************************************************** -// *************************************************************************** -// *************************************************************************** `timescale 1ns/100ps @@ -390,11 +388,17 @@ module system_top ( .ps_intr_09 (1'b0), .ps_intr_10 (1'b0), .ps_intr_11 (1'b0), - .rx_data_n (rx_data_n), - .rx_data_p (rx_data_p), - .rx_ref_clk (rx_ref_clk), - .rx_sync (rx_sync), - .rx_sysref (rx_sysref), + .rx_data_0_n (rx_data_n[0]), + .rx_data_0_p (rx_data_p[0]), + .rx_data_1_n (rx_data_n[1]), + .rx_data_1_p (rx_data_p[1]), + .rx_data_2_n (rx_data_n[2]), + .rx_data_2_p (rx_data_p[2]), + .rx_data_3_n (rx_data_n[3]), + .rx_data_3_p (rx_data_p[3]), + .rx_ref_clk_0 (rx_ref_clk), + .rx_sync_0 (rx_sync), + .rx_sysref_0 (rx_sysref), .spdif (spdif), .spi0_clk_i (spi0_clk), .spi0_clk_o (spi0_clk), @@ -417,11 +421,17 @@ module system_top ( .sys_clk_clk_n (sys_clk_n), .sys_clk_clk_p (sys_clk_p), .sys_rst (sys_rst), - .tx_data_n (tx_data_n), - .tx_data_p (tx_data_p), - .tx_ref_clk (tx_ref_clk), - .tx_sync (tx_sync), - .tx_sysref (tx_sysref)); + .tx_data_0_n (tx_data_n[0]), + .tx_data_0_p (tx_data_p[0]), + .tx_data_1_n (tx_data_n[1]), + .tx_data_1_p (tx_data_p[1]), + .tx_data_2_n (tx_data_n[2]), + .tx_data_2_p (tx_data_p[2]), + .tx_data_3_n (tx_data_n[3]), + .tx_data_3_p (tx_data_p[3]), + .tx_ref_clk_0 (tx_ref_clk), + .tx_sync_0 (tx_sync), + .tx_sysref_0 (tx_sysref)); endmodule diff --git a/projects/fmcadc2/common/fmcadc2_bd.tcl b/projects/fmcadc2/common/fmcadc2_bd.tcl index 7d684044d..0d81a4f6d 100644 --- a/projects/fmcadc2/common/fmcadc2_bd.tcl +++ b/projects/fmcadc2/common/fmcadc2_bd.tcl @@ -1,90 +1,18 @@ - -# ad9625 - -create_bd_port -dir I rx_ref_clk -create_bd_port -dir O rx_sync -create_bd_port -dir O rx_sysref -create_bd_port -dir I -from 7 -to 0 rx_data_p -create_bd_port -dir I -from 7 -to 0 rx_data_n - # adc peripherals set axi_ad9625_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9625:1.0 axi_ad9625_core] -set axi_ad9625_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.2 axi_ad9625_jesd] +set axi_ad9625_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:7.0 axi_ad9625_jesd] set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9625_jesd set_property -dict [list CONFIG.C_LANES {8}] $axi_ad9625_jesd -set axi_ad9625_gt [create_bd_cell -type ip -vlnv analog.com:user:axi_jesd_gt:1.0 axi_ad9625_gt] -set_property -dict [list CONFIG.NUM_OF_LANES {8}] $axi_ad9625_gt -set_property -dict [list CONFIG.QPLL0_ENABLE {0}] $axi_ad9625_gt -set_property -dict [list CONFIG.QPLL1_ENABLE {0}] $axi_ad9625_gt -set_property -dict [list CONFIG.RX_NUM_OF_LANES {8}] $axi_ad9625_gt -set_property -dict [list CONFIG.TX_NUM_OF_LANES {0}] $axi_ad9625_gt -set_property -dict [list CONFIG.CPLL_FBDIV_0 {1}] $axi_ad9625_gt -set_property -dict [list CONFIG.RX_OUT_DIV_0 {1}] $axi_ad9625_gt -set_property -dict [list CONFIG.TX_OUT_DIV_0 {1}] $axi_ad9625_gt -set_property -dict [list CONFIG.RX_CLK25_DIV_0 {25}] $axi_ad9625_gt -set_property -dict [list CONFIG.TX_CLK25_DIV_0 {25}] $axi_ad9625_gt -set_property -dict [list CONFIG.PMA_RSV_0 {0x00018480}] $axi_ad9625_gt -set_property -dict [list CONFIG.RX_CDR_CFG_0 {0x03000023ff20400020}] $axi_ad9625_gt -set_property -dict [list CONFIG.CPLL_FBDIV_1 {1}] $axi_ad9625_gt -set_property -dict [list CONFIG.RX_OUT_DIV_1 {1}] $axi_ad9625_gt -set_property -dict [list CONFIG.TX_OUT_DIV_1 {1}] $axi_ad9625_gt -set_property -dict [list CONFIG.RX_CLK25_DIV_1 {25}] $axi_ad9625_gt -set_property -dict [list CONFIG.TX_CLK25_DIV_1 {25}] $axi_ad9625_gt -set_property -dict [list CONFIG.PMA_RSV_1 {0x00018480}] $axi_ad9625_gt -set_property -dict [list CONFIG.RX_CDR_CFG_1 {0x03000023ff20400020}] $axi_ad9625_gt -set_property -dict [list CONFIG.CPLL_FBDIV_2 {1}] $axi_ad9625_gt -set_property -dict [list CONFIG.RX_OUT_DIV_2 {1}] $axi_ad9625_gt -set_property -dict [list CONFIG.TX_OUT_DIV_2 {1}] $axi_ad9625_gt -set_property -dict [list CONFIG.RX_CLK25_DIV_2 {25}] $axi_ad9625_gt -set_property -dict [list CONFIG.TX_CLK25_DIV_2 {25}] $axi_ad9625_gt -set_property -dict [list CONFIG.PMA_RSV_2 {0x00018480}] $axi_ad9625_gt -set_property -dict [list CONFIG.RX_CDR_CFG_2 {0x03000023ff20400020}] $axi_ad9625_gt -set_property -dict [list CONFIG.CPLL_FBDIV_3 {1}] $axi_ad9625_gt -set_property -dict [list CONFIG.RX_OUT_DIV_3 {1}] $axi_ad9625_gt -set_property -dict [list CONFIG.TX_OUT_DIV_3 {1}] $axi_ad9625_gt -set_property -dict [list CONFIG.RX_CLK25_DIV_3 {25}] $axi_ad9625_gt -set_property -dict [list CONFIG.TX_CLK25_DIV_3 {25}] $axi_ad9625_gt -set_property -dict [list CONFIG.PMA_RSV_3 {0x00018480}] $axi_ad9625_gt -set_property -dict [list CONFIG.RX_CDR_CFG_3 {0x03000023ff20400020}] $axi_ad9625_gt -set_property -dict [list CONFIG.CPLL_FBDIV_4 {1}] $axi_ad9625_gt -set_property -dict [list CONFIG.RX_OUT_DIV_4 {1}] $axi_ad9625_gt -set_property -dict [list CONFIG.TX_OUT_DIV_4 {1}] $axi_ad9625_gt -set_property -dict [list CONFIG.RX_CLK25_DIV_4 {25}] $axi_ad9625_gt -set_property -dict [list CONFIG.TX_CLK25_DIV_4 {25}] $axi_ad9625_gt -set_property -dict [list CONFIG.PMA_RSV_4 {0x00018480}] $axi_ad9625_gt -set_property -dict [list CONFIG.RX_CDR_CFG_4 {0x03000023ff20400020}] $axi_ad9625_gt -set_property -dict [list CONFIG.CPLL_FBDIV_5 {1}] $axi_ad9625_gt -set_property -dict [list CONFIG.RX_OUT_DIV_5 {1}] $axi_ad9625_gt -set_property -dict [list CONFIG.TX_OUT_DIV_5 {1}] $axi_ad9625_gt -set_property -dict [list CONFIG.RX_CLK25_DIV_5 {25}] $axi_ad9625_gt -set_property -dict [list CONFIG.TX_CLK25_DIV_5 {25}] $axi_ad9625_gt -set_property -dict [list CONFIG.PMA_RSV_5 {0x00018480}] $axi_ad9625_gt -set_property -dict [list CONFIG.RX_CDR_CFG_5 {0x03000023ff20400020}] $axi_ad9625_gt -set_property -dict [list CONFIG.CPLL_FBDIV_6 {1}] $axi_ad9625_gt -set_property -dict [list CONFIG.RX_OUT_DIV_6 {1}] $axi_ad9625_gt -set_property -dict [list CONFIG.TX_OUT_DIV_6 {1}] $axi_ad9625_gt -set_property -dict [list CONFIG.RX_CLK25_DIV_6 {25}] $axi_ad9625_gt -set_property -dict [list CONFIG.TX_CLK25_DIV_6 {25}] $axi_ad9625_gt -set_property -dict [list CONFIG.PMA_RSV_6 {0x00018480}] $axi_ad9625_gt -set_property -dict [list CONFIG.RX_CDR_CFG_6 {0x03000023ff20400020}] $axi_ad9625_gt -set_property -dict [list CONFIG.CPLL_FBDIV_7 {1}] $axi_ad9625_gt -set_property -dict [list CONFIG.RX_OUT_DIV_7 {1}] $axi_ad9625_gt -set_property -dict [list CONFIG.TX_OUT_DIV_7 {1}] $axi_ad9625_gt -set_property -dict [list CONFIG.RX_CLK25_DIV_7 {25}] $axi_ad9625_gt -set_property -dict [list CONFIG.TX_CLK25_DIV_7 {25}] $axi_ad9625_gt -set_property -dict [list CONFIG.PMA_RSV_7 {0x00018480}] $axi_ad9625_gt -set_property -dict [list CONFIG.RX_CDR_CFG_7 {0x03000023ff20400020}] $axi_ad9625_gt - -set util_ad9625_gt [create_bd_cell -type ip -vlnv analog.com:user:util_jesd_gt:1.0 util_ad9625_gt] -set_property -dict [list CONFIG.QPLL0_ENABLE {0}] $util_ad9625_gt -set_property -dict [list CONFIG.QPLL1_ENABLE {0}] $util_ad9625_gt -set_property -dict [list CONFIG.NUM_OF_LANES {8}] $util_ad9625_gt -set_property -dict [list CONFIG.RX_ENABLE {1}] $util_ad9625_gt -set_property -dict [list CONFIG.RX_NUM_OF_LANES {8}] $util_ad9625_gt -set_property -dict [list CONFIG.TX_ENABLE {0}] $util_ad9625_gt +set axi_ad9625_xcvr [create_bd_cell -type ip -vlnv analog.com:user:axi_adxcvr:1.0 axi_ad9625_xcvr] +set_property -dict [list CONFIG.NUM_OF_LANES {8}] $axi_ad9625_xcvr +set_property -dict [list CONFIG.QPLL_ENABLE {0}] $axi_ad9625_xcvr +set_property -dict [list CONFIG.TX_OR_RX_N {0}] $axi_ad9625_xcvr +set_property -dict [list CONFIG.LPM_OR_DFE_N {1}] $axi_ad9625_xcvr +set_property -dict [list CONFIG.SYS_CLK_SEL {0}] $axi_ad9625_xcvr +set_property -dict [list CONFIG.OUT_CLK_SEL {2}] $axi_ad9625_xcvr set axi_ad9625_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9625_dma] set_property -dict [list CONFIG.DMA_TYPE_SRC {1}] $axi_ad9625_dma @@ -99,84 +27,53 @@ set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad9625_dma set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {64}] $axi_ad9625_dma set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $axi_ad9625_dma -# connections (gt) +set util_fmcadc2_xcvr [create_bd_cell -type ip -vlnv analog.com:user:util_adxcvr:1.0 util_fmcadc2_xcvr] +set_property -dict [list CONFIG.QPLL_FBDIV {"0010000000"}] $util_fmcadc2_xcvr ;# N = 40 +set_property -dict [list CONFIG.CPLL_FBDIV {1}] $util_fmcadc2_xcvr +set_property -dict [list CONFIG.TX_NUM_OF_LANES {0}] $util_fmcadc2_xcvr +set_property -dict [list CONFIG.TX_OUT_DIV {1}] $util_fmcadc2_xcvr +set_property -dict [list CONFIG.TX_CLK25_DIV {25}] $util_fmcadc2_xcvr +set_property -dict [list CONFIG.RX_NUM_OF_LANES {8}] $util_fmcadc2_xcvr +set_property -dict [list CONFIG.RX_OUT_DIV {1}] $util_fmcadc2_xcvr +set_property -dict [list CONFIG.RX_CLK25_DIV {25}] $util_fmcadc2_xcvr +set_property -dict [list CONFIG.RX_DFE_LPM_CFG {0x0904}] $util_fmcadc2_xcvr +set_property -dict [list CONFIG.RX_CDR_CFG {0x03000023ff20400020}] $util_fmcadc2_xcvr ;# DFE mode refclk +-200 -ad_connect util_ad9625_gt/qpll_ref_clk rx_ref_clk -ad_connect util_ad9625_gt/cpll_ref_clk rx_ref_clk +# reference clocks & resets -ad_connect axi_ad9625_gt/gt_pll_0 util_ad9625_gt/gt_pll_0 -ad_connect axi_ad9625_gt/gt_pll_1 util_ad9625_gt/gt_pll_1 -ad_connect axi_ad9625_gt/gt_pll_2 util_ad9625_gt/gt_pll_2 -ad_connect axi_ad9625_gt/gt_pll_3 util_ad9625_gt/gt_pll_3 -ad_connect axi_ad9625_gt/gt_pll_4 util_ad9625_gt/gt_pll_4 -ad_connect axi_ad9625_gt/gt_pll_5 util_ad9625_gt/gt_pll_5 -ad_connect axi_ad9625_gt/gt_pll_6 util_ad9625_gt/gt_pll_6 -ad_connect axi_ad9625_gt/gt_pll_7 util_ad9625_gt/gt_pll_7 +create_bd_port -dir I rx_ref_clk_0 +create_bd_port -dir O rx_core_clk -ad_connect axi_ad9625_gt/gt_rx_0 util_ad9625_gt/gt_rx_0 -ad_connect axi_ad9625_gt/gt_rx_1 util_ad9625_gt/gt_rx_1 -ad_connect axi_ad9625_gt/gt_rx_2 util_ad9625_gt/gt_rx_2 -ad_connect axi_ad9625_gt/gt_rx_3 util_ad9625_gt/gt_rx_3 -ad_connect axi_ad9625_gt/gt_rx_4 util_ad9625_gt/gt_rx_4 -ad_connect axi_ad9625_gt/gt_rx_5 util_ad9625_gt/gt_rx_5 -ad_connect axi_ad9625_gt/gt_rx_6 util_ad9625_gt/gt_rx_6 -ad_connect axi_ad9625_gt/gt_rx_7 util_ad9625_gt/gt_rx_7 - -ad_connect axi_ad9625_gt/gt_rx_ip_0 axi_ad9625_jesd/gt0_rx -ad_connect axi_ad9625_gt/gt_rx_ip_1 axi_ad9625_jesd/gt1_rx -ad_connect axi_ad9625_gt/gt_rx_ip_2 axi_ad9625_jesd/gt2_rx -ad_connect axi_ad9625_gt/gt_rx_ip_3 axi_ad9625_jesd/gt3_rx -ad_connect axi_ad9625_gt/gt_rx_ip_4 axi_ad9625_jesd/gt4_rx -ad_connect axi_ad9625_gt/gt_rx_ip_5 axi_ad9625_jesd/gt5_rx -ad_connect axi_ad9625_gt/gt_rx_ip_6 axi_ad9625_jesd/gt6_rx -ad_connect axi_ad9625_gt/gt_rx_ip_7 axi_ad9625_jesd/gt7_rx - -ad_connect axi_ad9625_gt/rx_gt_comma_align_enb_0 axi_ad9625_jesd/rxencommaalign_out -ad_connect axi_ad9625_gt/rx_gt_comma_align_enb_1 axi_ad9625_jesd/rxencommaalign_out -ad_connect axi_ad9625_gt/rx_gt_comma_align_enb_2 axi_ad9625_jesd/rxencommaalign_out -ad_connect axi_ad9625_gt/rx_gt_comma_align_enb_3 axi_ad9625_jesd/rxencommaalign_out -ad_connect axi_ad9625_gt/rx_gt_comma_align_enb_4 axi_ad9625_jesd/rxencommaalign_out -ad_connect axi_ad9625_gt/rx_gt_comma_align_enb_5 axi_ad9625_jesd/rxencommaalign_out -ad_connect axi_ad9625_gt/rx_gt_comma_align_enb_6 axi_ad9625_jesd/rxencommaalign_out -ad_connect axi_ad9625_gt/rx_gt_comma_align_enb_7 axi_ad9625_jesd/rxencommaalign_out +ad_xcvrpll rx_ref_clk_0 util_fmcadc2_xcvr/qpll_ref_clk_* +ad_xcvrpll rx_ref_clk_0 util_fmcadc2_xcvr/cpll_ref_clk_* +ad_xcvrpll axi_ad9625_xcvr/up_pll_rst util_fmcadc2_xcvr/up_qpll_rst_* +ad_xcvrpll axi_ad9625_xcvr/up_pll_rst util_fmcadc2_xcvr/up_cpll_rst_* +ad_connect sys_cpu_resetn util_fmcadc2_xcvr/up_rstn +ad_connect sys_cpu_clk util_fmcadc2_xcvr/up_clk # connections (adc) -ad_connect util_ad9625_gt/rx_p rx_data_p -ad_connect util_ad9625_gt/rx_n rx_data_n -ad_connect util_ad9625_gt/rx_sync rx_sync -ad_connect util_ad9625_gt/rx_ip_sysref rx_sysref - -ad_connect util_ad9625_gt/rx_out_clk util_ad9625_gt/rx_clk -ad_connect util_ad9625_gt/rx_out_clk axi_ad9625_jesd/rx_core_clk -ad_connect util_ad9625_gt/rx_ip_rst axi_ad9625_jesd/rx_reset -ad_connect util_ad9625_gt/rx_ip_rst_done axi_ad9625_jesd/rx_reset_done -ad_connect util_ad9625_gt/rx_ip_sysref axi_ad9625_jesd/rx_sysref -ad_connect util_ad9625_gt/rx_ip_sync axi_ad9625_jesd/rx_sync -ad_connect util_ad9625_gt/rx_ip_sof axi_ad9625_jesd/rx_start_of_frame -ad_connect util_ad9625_gt/rx_ip_data axi_ad9625_jesd/rx_tdata - -ad_connect util_ad9625_gt/rx_out_clk axi_ad9625_core/rx_clk -ad_connect util_ad9625_gt/rx_data axi_ad9625_core/rx_data - -ad_connect axi_ad9625_core/adc_clk axi_ad9625_fifo/adc_clk -ad_connect axi_ad9625_fifo/adc_rst axi_ad9625_core/adc_rst -ad_connect axi_ad9625_core/adc_enable axi_ad9625_fifo/adc_wr -ad_connect axi_ad9625_core/adc_data axi_ad9625_fifo/adc_wdata -ad_connect axi_ad9625_core/adc_dovf axi_ad9625_fifo/adc_wovf - -ad_connect sys_cpu_clk axi_ad9625_fifo/dma_clk -ad_connect sys_cpu_clk axi_ad9625_dma/s_axis_aclk -ad_connect sys_cpu_resetn axi_ad9625_dma/m_dest_axi_aresetn - -ad_connect axi_ad9625_fifo/dma_wr axi_ad9625_dma/s_axis_valid -ad_connect axi_ad9625_fifo/dma_wdata axi_ad9625_dma/s_axis_data -ad_connect axi_ad9625_fifo/dma_wready axi_ad9625_dma/s_axis_ready -ad_connect axi_ad9625_fifo/dma_xfer_req axi_ad9625_dma/s_axis_xfer_req +ad_xcvrcon util_fmcadc2_xcvr axi_ad9625_xcvr axi_ad9625_jesd +ad_connect util_fmcadc2_xcvr/rx_out_clk_0 axi_ad9625_core/rx_clk +ad_connect util_fmcadc2_xcvr/rx_out_clk_0 rx_core_clk +ad_connect axi_ad9625_jesd/rx_tdata axi_ad9625_core/rx_data +ad_connect axi_ad9625_jesd/rx_start_of_frame axi_ad9625_core/rx_sof +ad_connect sys_cpu_clk axi_ad9625_fifo/dma_clk +ad_connect sys_cpu_clk axi_ad9625_dma/s_axis_aclk +ad_connect sys_cpu_resetn axi_ad9625_dma/m_dest_axi_aresetn +ad_connect axi_ad9625_core/adc_clk axi_ad9625_fifo/adc_clk +ad_connect axi_ad9625_jesd_rstgen/peripheral_reset axi_ad9625_fifo/adc_rst +ad_connect axi_ad9625_core/adc_enable axi_ad9625_fifo/adc_wr +ad_connect axi_ad9625_core/adc_data axi_ad9625_fifo/adc_wdata +ad_connect axi_ad9625_core/adc_dovf axi_ad9625_fifo/adc_wovf +ad_connect axi_ad9625_fifo/dma_wr axi_ad9625_dma/s_axis_valid +ad_connect axi_ad9625_fifo/dma_wdata axi_ad9625_dma/s_axis_data +ad_connect axi_ad9625_fifo/dma_wready axi_ad9625_dma/s_axis_ready +ad_connect axi_ad9625_fifo/dma_xfer_req axi_ad9625_dma/s_axis_xfer_req # interconnect (cpu) -ad_cpu_interconnect 0x44A60000 axi_ad9625_gt +ad_cpu_interconnect 0x44A60000 axi_ad9625_xcvr ad_cpu_interconnect 0x44A10000 axi_ad9625_core ad_cpu_interconnect 0x44A91000 axi_ad9625_jesd ad_cpu_interconnect 0x7c420000 axi_ad9625_dma @@ -184,7 +81,7 @@ ad_cpu_interconnect 0x7c420000 axi_ad9625_dma # gt uses hp3, and 100MHz clock for both DRP and AXI4 ad_mem_hp3_interconnect sys_cpu_clk sys_ps7/S_AXI_HP3 -ad_mem_hp3_interconnect sys_cpu_clk axi_ad9625_gt/m_axi +ad_mem_hp3_interconnect sys_cpu_clk axi_ad9625_xcvr/m_axi # interconnect (mem/adc) diff --git a/projects/fmcadc2/common/fmcadc2_spi.v b/projects/fmcadc2/common/fmcadc2_spi.v index 3e2e0186c..cb44724cd 100644 --- a/projects/fmcadc2/common/fmcadc2_spi.v +++ b/projects/fmcadc2/common/fmcadc2_spi.v @@ -39,33 +39,47 @@ module fmcadc2_spi ( + spi_adf4355, + spi_adf4355_ce, + spi_clk, - - spi_adc_csn, - spi_ext_csn_0, - spi_ext_csn_1, - + spi_csn, spi_mosi, spi_miso, + spi_adc_csn, + spi_adc_clk, spi_adc_sdio, - spi_ext_sdio); + + spi_adf4355_data_or_csn_0, + spi_adf4355_clk_or_csn_1, + spi_adf4355_le_or_clk, + spi_adf4355_ce_or_sdio); + + // select (adf4355 = 0x1), (normal = 0x0) + + input spi_adf4355; + input spi_adf4355_ce; // 4 wire input spi_clk; - - input spi_adc_csn; - input spi_ext_csn_0; - input spi_ext_csn_1; - + input [ 2:0] spi_csn; input spi_mosi; output spi_miso; - // 3 wire + // adc interface (3 wire) + output spi_adc_csn; + output spi_adc_clk; inout spi_adc_sdio; - inout spi_ext_sdio; + + // adf4355 or normal (AMP/EXT) + + output spi_adf4355_data_or_csn_0; + output spi_adf4355_clk_or_csn_1; + output spi_adf4355_le_or_clk; + inout spi_adf4355_ce_or_sdio; // internal registers @@ -77,12 +91,10 @@ module fmcadc2_spi ( wire spi_csn_s; wire spi_enable_s; - wire spi_adc_miso_s; - wire spi_ext_miso_s; // check on rising edge and change on falling edge - assign spi_csn_s = spi_adc_csn & spi_ext_csn_0 & spi_ext_csn_1; + assign spi_csn_s = & spi_csn; assign spi_enable_s = spi_enable & ~spi_csn_s; always @(posedge spi_clk or posedge spi_csn_s) begin @@ -107,23 +119,22 @@ module fmcadc2_spi ( end end - assign spi_miso = ((spi_adc_miso_s & ~spi_adc_csn) | - (spi_ext_miso_s & ~spi_ext_csn_0) | - (spi_ext_miso_s & ~spi_ext_csn_1)); + assign spi_miso = ((spi_adc_sdio & ~spi_csn[0]) | (~spi_adf4355 & + spi_adf4355_ce_or_sdio & ~(spi_csn[1] & spi_csn[2]))); - // io butter + // adc interface (3 wire) - IOBUF i_iobuf_adc_sdio ( - .T (spi_enable_s), - .I (spi_mosi), - .O (spi_adc_miso_s), - .IO (spi_adc_sdio)); + assign spi_adc_csn = spi_csn[0]; + assign spi_adc_clk = spi_clk; + assign spi_adc_sdio = (spi_enable_s == 1'b0) ? spi_mosi : 1'bz; - IOBUF i_iobuf_clk_sdio ( - .T (spi_enable_s), - .I (spi_mosi), - .O (spi_ext_miso_s), - .IO (spi_ext_sdio)); + // adf4355 or normal (AMP/EXT) + + assign spi_adf4355_data_or_csn_0 = (spi_adf4355 == 1'b1) ? spi_mosi : spi_csn[1]; + assign spi_adf4355_clk_or_csn_1 = (spi_adf4355 == 1'b1) ? spi_clk : spi_csn[2]; + assign spi_adf4355_le_or_clk = (spi_adf4355 == 1'b1) ? spi_csn[1] : spi_clk; + assign spi_adf4355_ce_or_sdio = (spi_adf4355 == 1'b1) ? spi_adf4355_ce : + ((spi_enable_s == 1'b0) ? spi_mosi : 1'bz); endmodule diff --git a/projects/fmcadc2/vc707/Makefile b/projects/fmcadc2/vc707/Makefile index 3ae995270..ab081ce8b 100644 --- a/projects/fmcadc2/vc707/Makefile +++ b/projects/fmcadc2/vc707/Makefile @@ -14,17 +14,17 @@ M_DEPS += ../common/fmcadc2_bd.tcl M_DEPS += ../../scripts/adi_project.tcl M_DEPS += ../../scripts/adi_env.tcl M_DEPS += ../../scripts/adi_board.tcl -M_DEPS += ../../common/xilinx/sys_dmafifo.tcl +M_DEPS += ../../common/xilinx/sys_adcfifo.tcl M_DEPS += ../../common/vc707/vc707_system_mig.prj M_DEPS += ../../common/vc707/vc707_system_constr.xdc M_DEPS += ../../common/vc707/vc707_system_bd.tcl -M_DEPS += ../../../library/common/ad_iobuf.v +M_DEPS += ../../../library/xilinx/common/ad_iobuf.v +M_DEPS += ../../../library/common/ad_sysref_gen.v M_DEPS += ../../../library/axi_ad9625/axi_ad9625.xpr +M_DEPS += ../../../library/xilinx/axi_adxcvr/axi_adxcvr.xpr M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr -M_DEPS += ../../../library/axi_jesd_gt/axi_jesd_gt.xpr M_DEPS += ../../../library/util_adcfifo/util_adcfifo.xpr -M_DEPS += ../../../library/util_dacfifo/util_dacfifo.xpr -M_DEPS += ../../../library/util_jesd_gt/util_jesd_gt.xpr +M_DEPS += ../../../library/xilinx/util_adxcvr/util_adxcvr.xpr M_VIVADO := vivado -mode batch -source @@ -40,6 +40,7 @@ M_FLIST += *.sdk M_FLIST += *.hw M_FLIST += *.sim M_FLIST += .Xil +M_FLIST += *.ip_user_files @@ -53,25 +54,23 @@ clean: clean-all:clean make -C ../../../library/axi_ad9625 clean + make -C ../../../library/xilinx/axi_adxcvr clean make -C ../../../library/axi_dmac clean - make -C ../../../library/axi_jesd_gt clean make -C ../../../library/util_adcfifo clean - make -C ../../../library/util_dacfifo clean - make -C ../../../library/util_jesd_gt clean + make -C ../../../library/xilinx/util_adxcvr clean fmcadc2_vc707.sdk/system_top.hdf: $(M_DEPS) - rm -rf $(M_FLIST) + -rm -rf $(M_FLIST) $(M_VIVADO) system_project.tcl >> fmcadc2_vc707_vivado.log 2>&1 lib: make -C ../../../library/axi_ad9625 + make -C ../../../library/xilinx/axi_adxcvr make -C ../../../library/axi_dmac - make -C ../../../library/axi_jesd_gt make -C ../../../library/util_adcfifo - make -C ../../../library/util_dacfifo - make -C ../../../library/util_jesd_gt + make -C ../../../library/xilinx/util_adxcvr #################################################################################### #################################################################################### diff --git a/projects/fmcadc2/vc707/system_bd.tcl b/projects/fmcadc2/vc707/system_bd.tcl index 437a6f4f6..b92c89f02 100644 --- a/projects/fmcadc2/vc707/system_bd.tcl +++ b/projects/fmcadc2/vc707/system_bd.tcl @@ -1,9 +1,8 @@ source $ad_hdl_dir/projects/common/vc707/vc707_system_bd.tcl -source $ad_hdl_dir/projects/common/xilinx/sys_dmafifo.tcl +source $ad_hdl_dir/projects/common/xilinx/sys_adcfifo.tcl -p_sys_dmafifo [current_bd_instance .] axi_ad9625_fifo 256 18 +p_sys_adcfifo [current_bd_instance .] axi_ad9625_fifo 256 18 source ../common/fmcadc2_bd.tcl - diff --git a/projects/fmcadc2/vc707/system_constr.xdc b/projects/fmcadc2/vc707/system_constr.xdc index 03009a936..f1caf236e 100644 --- a/projects/fmcadc2/vc707/system_constr.xdc +++ b/projects/fmcadc2/vc707/system_constr.xdc @@ -1,41 +1,47 @@ # ad9625 -set_property -dict {PACKAGE_PIN A10 } [get_ports rx_ref_clk_p] ; ## D04 FMC1_HPC_GBTCLK0_M2C_P -set_property -dict {PACKAGE_PIN A9 } [get_ports rx_ref_clk_n] ; ## D05 FMC1_HPC_GBTCLK0_M2C_N -set_property -dict {PACKAGE_PIN D8 } [get_ports rx_data_p[0]] ; ## C06 FMC1_HPC_DP0_M2C_P -set_property -dict {PACKAGE_PIN D7 } [get_ports rx_data_n[0]] ; ## C07 FMC1_HPC_DP0_M2C_N -set_property -dict {PACKAGE_PIN C6 } [get_ports rx_data_p[1]] ; ## A02 FMC1_HPC_DP1_M2C_P -set_property -dict {PACKAGE_PIN C5 } [get_ports rx_data_n[1]] ; ## A03 FMC1_HPC_DP1_M2C_N -set_property -dict {PACKAGE_PIN B8 } [get_ports rx_data_p[2]] ; ## A06 FMC1_HPC_DP2_M2C_P -set_property -dict {PACKAGE_PIN B7 } [get_ports rx_data_n[2]] ; ## A07 FMC1_HPC_DP2_M2C_N -set_property -dict {PACKAGE_PIN A6 } [get_ports rx_data_p[3]] ; ## A10 FMC1_HPC_DP3_M2C_P -set_property -dict {PACKAGE_PIN A5 } [get_ports rx_data_n[3]] ; ## A11 FMC1_HPC_DP3_M2C_N -set_property -dict {PACKAGE_PIN E6 } [get_ports rx_data_p[4]] ; ## B12 FMC1_HPC_DP7_M2C_P -set_property -dict {PACKAGE_PIN E5 } [get_ports rx_data_n[4]] ; ## B13 FMC1_HPC_DP7_M2C_N -set_property -dict {PACKAGE_PIN H8 } [get_ports rx_data_p[5]] ; ## A14 FMC1_HPC_DP4_M2C_P -set_property -dict {PACKAGE_PIN H7 } [get_ports rx_data_n[5]] ; ## A15 FMC1_HPC_DP4_M2C_N -set_property -dict {PACKAGE_PIN F8 } [get_ports rx_data_p[6]] ; ## B16 FMC1_HPC_DP6_M2C_P -set_property -dict {PACKAGE_PIN F7 } [get_ports rx_data_n[6]] ; ## B17 FMC1_HPC_DP6_M2C_N -set_property -dict {PACKAGE_PIN G6 } [get_ports rx_data_p[7]] ; ## A18 FMC1_HPC_DP5_M2C_P -set_property -dict {PACKAGE_PIN G5 } [get_ports rx_data_n[7]] ; ## A19 FMC1_HPC_DP5_M2C_N -set_property -dict {PACKAGE_PIN H40 IOSTANDARD LVDS} [get_ports rx_sync_p] ; ## H10 FMC1_HPC_LA04_P -set_property -dict {PACKAGE_PIN H41 IOSTANDARD LVDS} [get_ports rx_sync_n] ; ## H11 FMC1_HPC_LA04_N -set_property -dict {PACKAGE_PIN M41 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_sysref_p] ; ## D11 FMC1_HPC_LA05_P -set_property -dict {PACKAGE_PIN L41 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_sysref_n] ; ## D12 FMC1_HPC_LA05_N +set_property -dict {PACKAGE_PIN A10 } [get_ports rx_ref_clk_p] ; ## D04 FMC1_HPC_GBTCLK0_M2C_P +set_property -dict {PACKAGE_PIN A9 } [get_ports rx_ref_clk_n] ; ## D05 FMC1_HPC_GBTCLK0_M2C_N +set_property -dict {PACKAGE_PIN D8 } [get_ports rx_data_p[0]] ; ## C06 FMC1_HPC_DP0_M2C_P +set_property -dict {PACKAGE_PIN D7 } [get_ports rx_data_n[0]] ; ## C07 FMC1_HPC_DP0_M2C_N +set_property -dict {PACKAGE_PIN C6 } [get_ports rx_data_p[1]] ; ## A02 FMC1_HPC_DP1_M2C_P +set_property -dict {PACKAGE_PIN C5 } [get_ports rx_data_n[1]] ; ## A03 FMC1_HPC_DP1_M2C_N +set_property -dict {PACKAGE_PIN B8 } [get_ports rx_data_p[2]] ; ## A06 FMC1_HPC_DP2_M2C_P +set_property -dict {PACKAGE_PIN B7 } [get_ports rx_data_n[2]] ; ## A07 FMC1_HPC_DP2_M2C_N +set_property -dict {PACKAGE_PIN A6 } [get_ports rx_data_p[3]] ; ## A10 FMC1_HPC_DP3_M2C_P +set_property -dict {PACKAGE_PIN A5 } [get_ports rx_data_n[3]] ; ## A11 FMC1_HPC_DP3_M2C_N +set_property -dict {PACKAGE_PIN E6 } [get_ports rx_data_p[4]] ; ## B12 FMC1_HPC_DP7_M2C_P +set_property -dict {PACKAGE_PIN E5 } [get_ports rx_data_n[4]] ; ## B13 FMC1_HPC_DP7_M2C_N +set_property -dict {PACKAGE_PIN H8 } [get_ports rx_data_p[5]] ; ## A14 FMC1_HPC_DP4_M2C_P +set_property -dict {PACKAGE_PIN H7 } [get_ports rx_data_n[5]] ; ## A15 FMC1_HPC_DP4_M2C_N +set_property -dict {PACKAGE_PIN F8 } [get_ports rx_data_p[6]] ; ## B16 FMC1_HPC_DP6_M2C_P +set_property -dict {PACKAGE_PIN F7 } [get_ports rx_data_n[6]] ; ## B17 FMC1_HPC_DP6_M2C_N +set_property -dict {PACKAGE_PIN G6 } [get_ports rx_data_p[7]] ; ## A18 FMC1_HPC_DP5_M2C_P +set_property -dict {PACKAGE_PIN G5 } [get_ports rx_data_n[7]] ; ## A19 FMC1_HPC_DP5_M2C_N +set_property -dict {PACKAGE_PIN H40 IOSTANDARD LVDS} [get_ports rx_sync_p] ; ## H10 FMC1_HPC_LA04_P +set_property -dict {PACKAGE_PIN H41 IOSTANDARD LVDS} [get_ports rx_sync_n] ; ## H11 FMC1_HPC_LA04_N +set_property -dict {PACKAGE_PIN M41 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_sysref_p] ; ## D11 FMC1_HPC_LA05_P +set_property -dict {PACKAGE_PIN L41 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_sysref_n] ; ## D12 FMC1_HPC_LA05_N -set_property -dict {PACKAGE_PIN N41 IOSTANDARD LVCMOS18} [get_ports spi_adc_csn] ; ## H08 FMC1_HPC_LA02_N -set_property -dict {PACKAGE_PIN J40 IOSTANDARD LVCMOS18} [get_ports spi_adc_clk] ; ## D08 FMC1_HPC_LA01_CC_P -set_property -dict {PACKAGE_PIN J41 IOSTANDARD LVCMOS18} [get_ports spi_adc_sdio] ; ## D09 FMC1_HPC_LA01_CC_N -set_property -dict {PACKAGE_PIN P41 IOSTANDARD LVCMOS18} [get_ports spi_ext_csn_0] ; ## H07 FMC1_HPC_LA02_P -set_property -dict {PACKAGE_PIN K42 IOSTANDARD LVCMOS18} [get_ports spi_ext_csn_1] ; ## C10 FMC1_HPC_LA06_P -set_property -dict {PACKAGE_PIN K39 IOSTANDARD LVCMOS18} [get_ports spi_ext_clk] ; ## G06 FMC1_HPC_LA00_CC_P -set_property -dict {PACKAGE_PIN K40 IOSTANDARD LVCMOS18} [get_ports spi_ext_sdio] ; ## G07 FMC1_HPC_LA00_CC_N +set_property -dict {PACKAGE_PIN N41 IOSTANDARD LVCMOS18} [get_ports spi_adc_csn] ; ## H08 FMC1_HPC_LA02_N +set_property -dict {PACKAGE_PIN J40 IOSTANDARD LVCMOS18} [get_ports spi_adc_clk] ; ## D08 FMC1_HPC_LA01_CC_P +set_property -dict {PACKAGE_PIN J41 IOSTANDARD LVCMOS18} [get_ports spi_adc_sdio] ; ## D09 FMC1_HPC_LA01_CC_N +set_property -dict {PACKAGE_PIN P41 IOSTANDARD LVCMOS18} [get_ports spi_adf4355_data_or_csn_0] ; ## H07 FMC1_HPC_LA02_P +set_property -dict {PACKAGE_PIN K42 IOSTANDARD LVCMOS18} [get_ports spi_adf4355_clk_or_csn_1] ; ## C10 FMC1_HPC_LA06_P +set_property -dict {PACKAGE_PIN K39 IOSTANDARD LVCMOS18} [get_ports spi_adf4355_le_or_clk] ; ## G06 FMC1_HPC_LA00_CC_P +set_property -dict {PACKAGE_PIN K40 IOSTANDARD LVCMOS18} [get_ports spi_adf4355_ce_or_sdio] ; ## G07 FMC1_HPC_LA00_CC_N -set_property -dict {PACKAGE_PIN M42 IOSTANDARD LVCMOS18} [get_ports adc_irq] ; ## G09 FMC1_HPC_LA03_P -set_property -dict {PACKAGE_PIN L42 IOSTANDARD LVCMOS18} [get_ports adc_fd] ; ## G10 FMC1_HPC_LA03_N +set_property -dict {PACKAGE_PIN M42 IOSTANDARD LVCMOS18} [get_ports adc_irq] ; ## G09 FMC1_HPC_LA03_P +set_property -dict {PACKAGE_PIN L42 IOSTANDARD LVCMOS18} [get_ports adc_fd] ; ## G10 FMC1_HPC_LA03_N # clocks create_clock -name rx_ref_clk -period 1.60 [get_ports rx_ref_clk_p] -create_clock -name rx_div_clk -period 6.40 [get_pins i_system_wrapper/system_i/axi_ad9625_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK] +create_clock -name rx_div_clk -period 6.40 [get_pins i_system_wrapper/system_i/util_fmcadc2_xcvr/inst/i_xch_0/i_gtxe2_channel/RXOUTCLK] + +set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9625_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]] + +set_property shreg_extract no [get_cells -hier -filter {name =~ *sysref_en_m*}] +set_false_path -to [get_cells -hier -filter {name =~ *sysref_en_m1* && IS_SEQUENTIAL}] + diff --git a/projects/fmcadc2/vc707/system_project.tcl b/projects/fmcadc2/vc707/system_project.tcl index 7941890e5..2d69eb87d 100644 --- a/projects/fmcadc2/vc707/system_project.tcl +++ b/projects/fmcadc2/vc707/system_project.tcl @@ -10,11 +10,11 @@ adi_project_files fmcadc2_vc707 [list \ "../common/fmcadc2_spi.v" \ "system_top.v" \ "system_constr.xdc" \ - "$ad_hdl_dir/library/common/ad_iobuf.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \ + "$ad_hdl_dir/library/common/ad_sysref_gen.v" \ "$ad_hdl_dir/projects/common/vc707/vc707_system_constr.xdc" ] -set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/vc707/vc707_system_constr.xdc] -set_property PROCESSING_ORDER EARLY [get_files system_constr.xdc] +set_property is_enabled false [get_files *system_axi*_spi*.xdc] adi_project_run fmcadc2_vc707 diff --git a/projects/fmcadc2/vc707/system_top.v b/projects/fmcadc2/vc707/system_top.v index e00f5dc61..be9a8bf87 100644 --- a/projects/fmcadc2/vc707/system_top.v +++ b/projects/fmcadc2/vc707/system_top.v @@ -104,10 +104,11 @@ module system_top ( spi_adc_csn, spi_adc_clk, spi_adc_sdio, - spi_ext_csn_0, - spi_ext_csn_1, - spi_ext_clk, - spi_ext_sdio); + + spi_adf4355_data_or_csn_0, + spi_adf4355_clk_or_csn_1, + spi_adf4355_le_or_clk, + spi_adf4355_ce_or_sdio); input sys_rst; input sys_clk_p; @@ -174,10 +175,11 @@ module system_top ( output spi_adc_csn; output spi_adc_clk; inout spi_adc_sdio; - output spi_ext_csn_0; - output spi_ext_csn_1; - output spi_ext_clk; - inout spi_ext_sdio; + + output spi_adf4355_data_or_csn_0; + output spi_adf4355_clk_or_csn_1; + output spi_adf4355_le_or_clk; + inout spi_adf4355_ce_or_sdio; // internal signals @@ -188,22 +190,16 @@ module system_top ( wire spi_mosi; wire spi_miso; wire rx_ref_clk; - wire rx_sysref; wire rx_sync; - - // spi - - assign spi_adc_csn = spi_csn[0]; - assign spi_adc_clk = spi_clk; - assign spi_ext_csn_0 = spi_csn[1]; - assign spi_ext_csn_1 = spi_csn[2]; - assign spi_ext_clk = spi_clk; + wire rx_sysref; + wire rx_clk; // default logic assign fan_pwm = 1'b1; assign iic_rstn = 1'b1; + // instantiations IBUFDS_GTE2 i_ibufds_rx_ref_clk ( @@ -224,21 +220,25 @@ module system_top ( .OB (rx_sync_n)); fmcadc2_spi i_fmcadc2_spi ( - .spi_adc_csn (spi_adc_csn), - .spi_ext_csn_0 (spi_ext_csn_0), - .spi_ext_csn_1 (spi_ext_csn_1), + .spi_adf4355 (gpio_o[36]), + .spi_adf4355_ce (gpio_o[37]), .spi_clk (spi_clk), + .spi_csn (spi_csn), .spi_mosi (spi_mosi), .spi_miso (spi_miso), + .spi_adc_csn (spi_adc_csn), + .spi_adc_clk (spi_adc_clk), .spi_adc_sdio (spi_adc_sdio), - .spi_ext_sdio (spi_ext_sdio)); + .spi_adf4355_data_or_csn_0 (spi_adf4355_data_or_csn_0), + .spi_adf4355_clk_or_csn_1 (spi_adf4355_clk_or_csn_1), + .spi_adf4355_le_or_clk (spi_adf4355_le_or_clk), + .spi_adf4355_ce_or_sdio (spi_adf4355_ce_or_sdio)); - ad_iobuf #(.DATA_WIDTH(3)) i_iobuf ( + ad_iobuf #(.DATA_WIDTH(2)) i_iobuf ( .dio_t (gpio_t[33:32]), .dio_i (gpio_o[33:32]), .dio_o (gpio_i[33:32]), - .dio_p ({ adc_irq, // 33 - adc_fd})); // 32 + .dio_p ({adc_irq, adc_fd})); ad_iobuf #(.DATA_WIDTH(21)) i_iobuf_bd ( .dio_t (gpio_t[20:0]), @@ -246,6 +246,11 @@ module system_top ( .dio_o (gpio_i[20:0]), .dio_p (gpio_bd)); + ad_sysref_gen i_sysref ( + .core_clk (rx_clk), + .sysref_en (gpio_o[34]), + .sysref_out (rx_sysref)); + system_wrapper i_system_wrapper ( .ddr3_addr (ddr3_addr), .ddr3_ba (ddr3_ba), @@ -288,11 +293,26 @@ module system_top ( .mgt_clk_clk_p (mgt_clk_p), .phy_rstn (phy_rstn), .phy_sd (1'b1), - .rx_data_n (rx_data_n), - .rx_data_p (rx_data_p), - .rx_ref_clk (rx_ref_clk), - .rx_sync (rx_sync), - .rx_sysref (rx_sysref), + .rx_data_0_n (rx_data_n[0]), + .rx_data_0_p (rx_data_p[0]), + .rx_data_1_n (rx_data_n[1]), + .rx_data_1_p (rx_data_p[1]), + .rx_data_2_n (rx_data_n[2]), + .rx_data_2_p (rx_data_p[2]), + .rx_data_3_n (rx_data_n[3]), + .rx_data_3_p (rx_data_p[3]), + .rx_data_4_n (rx_data_n[4]), + .rx_data_4_p (rx_data_p[4]), + .rx_data_5_n (rx_data_n[5]), + .rx_data_5_p (rx_data_p[5]), + .rx_data_6_n (rx_data_n[6]), + .rx_data_6_p (rx_data_p[6]), + .rx_data_7_n (rx_data_n[7]), + .rx_data_7_p (rx_data_p[7]), + .rx_ref_clk_0 (rx_ref_clk), + .rx_sync_0 (rx_sync), + .rx_sysref_0 (rx_sysref), + .rx_core_clk (rx_clk), .sgmii_rxn (sgmii_rxn), .sgmii_rxp (sgmii_rxp), .sgmii_txn (sgmii_txn), diff --git a/projects/fmcadc2/zc706/Makefile b/projects/fmcadc2/zc706/Makefile index 352efb7bc..f90b83008 100644 --- a/projects/fmcadc2/zc706/Makefile +++ b/projects/fmcadc2/zc706/Makefile @@ -14,20 +14,22 @@ M_DEPS += ../common/fmcadc2_bd.tcl M_DEPS += ../../scripts/adi_project.tcl M_DEPS += ../../scripts/adi_env.tcl M_DEPS += ../../scripts/adi_board.tcl -M_DEPS += ../../common/zc706/zc706_system_plddr3.tcl +M_DEPS += ../../common/zc706/zc706_system_plddr3_adcfifo.tcl M_DEPS += ../../common/zc706/zc706_system_mig_constr.xdc M_DEPS += ../../common/zc706/zc706_system_mig.prj M_DEPS += ../../common/zc706/zc706_system_constr.xdc M_DEPS += ../../common/zc706/zc706_system_bd.tcl -M_DEPS += ../../../library/common/ad_iobuf.v +M_DEPS += ../../../library/xilinx/common/ad_lvds_out.v +M_DEPS += ../../../library/xilinx/common/ad_iobuf.v +M_DEPS += ../../../library/common/ad_sysref_gen.v M_DEPS += ../../../library/axi_ad9625/axi_ad9625.xpr -M_DEPS += ../../../library/axi_adcfifo/axi_adcfifo.xpr +M_DEPS += ../../../library/xilinx/axi_adcfifo/axi_adcfifo.xpr +M_DEPS += ../../../library/xilinx/axi_adxcvr/axi_adxcvr.xpr M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr -M_DEPS += ../../../library/axi_jesd_gt/axi_jesd_gt.xpr M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr -M_DEPS += ../../../library/util_jesd_gt/util_jesd_gt.xpr +M_DEPS += ../../../library/xilinx/util_adxcvr/util_adxcvr.xpr M_VIVADO := vivado -mode batch -source @@ -43,6 +45,7 @@ M_FLIST += *.sdk M_FLIST += *.hw M_FLIST += *.sim M_FLIST += .Xil +M_FLIST += *.ip_user_files @@ -56,29 +59,29 @@ clean: clean-all:clean make -C ../../../library/axi_ad9625 clean - make -C ../../../library/axi_adcfifo clean + make -C ../../../library/xilinx/axi_adcfifo clean + make -C ../../../library/xilinx/axi_adxcvr clean make -C ../../../library/axi_clkgen clean make -C ../../../library/axi_dmac clean make -C ../../../library/axi_hdmi_tx clean - make -C ../../../library/axi_jesd_gt clean make -C ../../../library/axi_spdif_tx clean - make -C ../../../library/util_jesd_gt clean + make -C ../../../library/xilinx/util_adxcvr clean fmcadc2_zc706.sdk/system_top.hdf: $(M_DEPS) - rm -rf $(M_FLIST) + -rm -rf $(M_FLIST) $(M_VIVADO) system_project.tcl >> fmcadc2_zc706_vivado.log 2>&1 lib: make -C ../../../library/axi_ad9625 - make -C ../../../library/axi_adcfifo + make -C ../../../library/xilinx/axi_adcfifo + make -C ../../../library/xilinx/axi_adxcvr make -C ../../../library/axi_clkgen make -C ../../../library/axi_dmac make -C ../../../library/axi_hdmi_tx - make -C ../../../library/axi_jesd_gt make -C ../../../library/axi_spdif_tx - make -C ../../../library/util_jesd_gt + make -C ../../../library/xilinx/util_adxcvr #################################################################################### #################################################################################### diff --git a/projects/fmcadc2/zc706/system_bd.tcl b/projects/fmcadc2/zc706/system_bd.tcl index 26f3c6a89..f7567d53a 100644 --- a/projects/fmcadc2/zc706/system_bd.tcl +++ b/projects/fmcadc2/zc706/system_bd.tcl @@ -1,8 +1,8 @@ source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl -source $ad_hdl_dir/projects/common/zc706/zc706_system_plddr3.tcl +source $ad_hdl_dir/projects/common/zc706/zc706_system_plddr3_adcfifo.tcl -p_plddr3_fifo [current_bd_instance .] axi_ad9625_fifo 256 +p_plddr3_adcfifo [current_bd_instance .] axi_ad9625_fifo 256 create_bd_port -dir I -type rst sys_rst create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr3 diff --git a/projects/fmcadc2/zc706/system_constr.xdc b/projects/fmcadc2/zc706/system_constr.xdc index 2b3a2b136..1b4c18f41 100644 --- a/projects/fmcadc2/zc706/system_constr.xdc +++ b/projects/fmcadc2/zc706/system_constr.xdc @@ -27,10 +27,10 @@ set_property -dict {PACKAGE_PIN AH24 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ set_property -dict {PACKAGE_PIN AK18 IOSTANDARD LVCMOS25} [get_ports spi_adc_csn] ; ## H08 FMC_HPC_LA02_N set_property -dict {PACKAGE_PIN AG21 IOSTANDARD LVCMOS25} [get_ports spi_adc_clk] ; ## D08 FMC_HPC_LA01_CC_P set_property -dict {PACKAGE_PIN AH21 IOSTANDARD LVCMOS25} [get_ports spi_adc_sdio] ; ## D09 FMC_HPC_LA01_CC_N -set_property -dict {PACKAGE_PIN AK17 IOSTANDARD LVCMOS25} [get_ports spi_ext_csn_0] ; ## H07 FMC_HPC_LA02_P -set_property -dict {PACKAGE_PIN AG22 IOSTANDARD LVCMOS25} [get_ports spi_ext_csn_1] ; ## C10 FMC_HPC_LA06_P -set_property -dict {PACKAGE_PIN AF20 IOSTANDARD LVCMOS25} [get_ports spi_ext_clk] ; ## G06 FMC_HPC_LA00_CC_P -set_property -dict {PACKAGE_PIN AG20 IOSTANDARD LVCMOS25} [get_ports spi_ext_sdio] ; ## G07 FMC_HPC_LA00_CC_N +set_property -dict {PACKAGE_PIN AK17 IOSTANDARD LVCMOS25} [get_ports spi_adf4355_data_or_csn_0] ; ## H07 FMC_HPC_LA02_P +set_property -dict {PACKAGE_PIN AG22 IOSTANDARD LVCMOS25} [get_ports spi_adf4355_clk_or_csn_1] ; ## C10 FMC_HPC_LA06_P +set_property -dict {PACKAGE_PIN AF20 IOSTANDARD LVCMOS25} [get_ports spi_adf4355_le_or_clk] ; ## G06 FMC_HPC_LA00_CC_P +set_property -dict {PACKAGE_PIN AG20 IOSTANDARD LVCMOS25} [get_ports spi_adf4355_ce_or_sdio] ; ## G07 FMC_HPC_LA00_CC_N set_property -dict {PACKAGE_PIN AH19 IOSTANDARD LVCMOS25} [get_ports adc_irq] ; ## G09 FMC_HPC_LA03_P set_property -dict {PACKAGE_PIN AJ19 IOSTANDARD LVCMOS25} [get_ports adc_fd] ; ## G10 FMC_HPC_LA03_N @@ -38,4 +38,10 @@ set_property -dict {PACKAGE_PIN AJ19 IOSTANDARD LVCMOS25} [get_ports adc_fd] # clocks create_clock -name rx_ref_clk -period 1.60 [get_ports rx_ref_clk_p] -create_clock -name rx_div_clk -period 6.40 [get_pins i_system_wrapper/system_i/axi_ad9625_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK] +create_clock -name rx_div_clk -period 6.40 [get_pins i_system_wrapper/system_i/util_fmcadc2_xcvr/inst/i_xch_0/i_gtxe2_channel/RXOUTCLK] + +set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9625_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]] + +set_property shreg_extract no [get_cells -hier -filter {name =~ *sysref_en_m*}] +set_false_path -to [get_cells -hier -filter {name =~ *sysref_en_m1* && IS_SEQUENTIAL}] + diff --git a/projects/fmcadc2/zc706/system_project.tcl b/projects/fmcadc2/zc706/system_project.tcl index 029d6c139..777034487 100644 --- a/projects/fmcadc2/zc706/system_project.tcl +++ b/projects/fmcadc2/zc706/system_project.tcl @@ -1,6 +1,4 @@ - - source ../../scripts/adi_env.tcl source $ad_hdl_dir/projects/scripts/adi_project.tcl source $ad_hdl_dir/projects/scripts/adi_board.tcl @@ -10,13 +8,26 @@ adi_project_files fmcadc2_zc706 [list \ "../common/fmcadc2_spi.v" \ "system_top.v" \ "system_constr.xdc" \ - "$ad_hdl_dir/library/common/ad_iobuf.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_lvds_out.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \ + "$ad_hdl_dir/library/common/ad_sysref_gen.v" \ "$ad_hdl_dir/projects/common/zc706/zc706_system_mig_constr.xdc" \ "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ] -set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc] -set_property PROCESSING_ORDER EARLY [get_files system_constr.xdc] - adi_project_run fmcadc2_zc706 +set ila_core [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.1 ila_core] +set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_core +set_property -dict [list CONFIG.C_TRIGIN_EN {false}] $ila_core +set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila_core +set_property -dict [list CONFIG.C_NUM_OF_PROBES {4}] $ila_core +set_property -dict [list CONFIG.C_PROBE0_WIDTH {1}] $ila_core +set_property -dict [list CONFIG.C_PROBE1_WIDTH {1}] $ila_core +set_property -dict [list CONFIG.C_PROBE2_WIDTH {1}] $ila_core +set_property -dict [list CONFIG.C_PROBE3_WIDTH {256}] $ila_core +ad_connect axi_ad9625_core/adc_clk ila_core/clk +ad_connect axi_ad9625_core/adc_rst ila_core/probe0 +ad_connect axi_ad9625_core/adc_valid ila_core/probe1 +ad_connect axi_ad9625_core/rx_ready ila_core/probe2 +ad_connect axi_ad9625_core/adc_data ila_core/probe3 diff --git a/projects/fmcadc2/zc706/system_top.v b/projects/fmcadc2/zc706/system_top.v index f85bab7d4..714fdd451 100644 --- a/projects/fmcadc2/zc706/system_top.v +++ b/projects/fmcadc2/zc706/system_top.v @@ -112,10 +112,11 @@ module system_top ( spi_adc_csn, spi_adc_clk, spi_adc_sdio, - spi_ext_csn_0, - spi_ext_csn_1, - spi_ext_clk, - spi_ext_sdio); + + spi_adf4355_data_or_csn_0, + spi_adf4355_clk_or_csn_1, + spi_adf4355_le_or_clk, + spi_adf4355_ce_or_sdio); inout [14:0] ddr_addr; inout [ 2:0] ddr_ba; @@ -188,10 +189,11 @@ module system_top ( output spi_adc_csn; output spi_adc_clk; inout spi_adc_sdio; - output spi_ext_csn_0; - output spi_ext_csn_1; - output spi_ext_clk; - inout spi_ext_sdio; + + output spi_adf4355_data_or_csn_0; + output spi_adf4355_clk_or_csn_1; + output spi_adf4355_le_or_clk; + inout spi_adf4355_ce_or_sdio; // internal signals @@ -207,16 +209,9 @@ module system_top ( wire spi1_mosi; wire spi1_miso; wire rx_ref_clk; - wire rx_sysref; wire rx_sync; - - // spi - - assign spi_adc_csn = spi0_csn[0]; - assign spi_adc_clk = spi0_clk; - assign spi_ext_csn_0 = spi0_csn[1]; - assign spi_ext_csn_1 = spi0_csn[2]; - assign spi_ext_clk = spi0_clk; + wire rx_clk; + wire rx_sysref; // instantiations @@ -237,22 +232,28 @@ module system_top ( .O (rx_sync_p), .OB (rx_sync_n)); + // spi + fmcadc2_spi i_fmcadc2_spi ( - .spi_adc_csn (spi_adc_csn), - .spi_ext_csn_0 (spi_ext_csn_0), - .spi_ext_csn_1 (spi_ext_csn_1), + .spi_adf4355 (gpio_o[36]), + .spi_adf4355_ce (gpio_o[37]), .spi_clk (spi0_clk), + .spi_csn (spi0_csn), .spi_mosi (spi0_mosi), .spi_miso (spi0_miso), + .spi_adc_csn (spi_adc_csn), + .spi_adc_clk (spi_adc_clk), .spi_adc_sdio (spi_adc_sdio), - .spi_ext_sdio (spi_ext_sdio)); + .spi_adf4355_data_or_csn_0 (spi_adf4355_data_or_csn_0), + .spi_adf4355_clk_or_csn_1 (spi_adf4355_clk_or_csn_1), + .spi_adf4355_le_or_clk (spi_adf4355_le_or_clk), + .spi_adf4355_ce_or_sdio (spi_adf4355_ce_or_sdio)); ad_iobuf #(.DATA_WIDTH(2)) i_iobuf ( .dio_t (gpio_t[33:32]), .dio_i (gpio_o[33:32]), .dio_o (gpio_i[33:32]), - .dio_p ({ adc_irq, // 33 - adc_fd})); // 32 + .dio_p ({adc_irq, adc_fd})); ad_iobuf #(.DATA_WIDTH(15)) i_iobuf_bd ( .dio_t (gpio_t[14:0]), @@ -260,6 +261,11 @@ module system_top ( .dio_o (gpio_i[14:0]), .dio_p (gpio_bd)); + ad_sysref_gen i_sysref ( + .core_clk (rx_clk), + .sysref_en (gpio_o[34]), + .sysref_out (rx_sysref)); + system_wrapper i_system_wrapper ( .ddr3_addr (ddr3_addr), .ddr3_ba (ddr3_ba), @@ -320,11 +326,26 @@ module system_top ( .ps_intr_10 (1'b0), .ps_intr_11 (1'b0), .ps_intr_12 (1'b0), - .rx_data_n (rx_data_n), - .rx_data_p (rx_data_p), - .rx_ref_clk (rx_ref_clk), - .rx_sync (rx_sync), - .rx_sysref (rx_sysref), + .rx_data_0_n (rx_data_n[0]), + .rx_data_0_p (rx_data_p[0]), + .rx_data_1_n (rx_data_n[1]), + .rx_data_1_p (rx_data_p[1]), + .rx_data_2_n (rx_data_n[2]), + .rx_data_2_p (rx_data_p[2]), + .rx_data_3_n (rx_data_n[3]), + .rx_data_3_p (rx_data_p[3]), + .rx_data_4_n (rx_data_n[4]), + .rx_data_4_p (rx_data_p[4]), + .rx_data_5_n (rx_data_n[5]), + .rx_data_5_p (rx_data_p[5]), + .rx_data_6_n (rx_data_n[6]), + .rx_data_6_p (rx_data_p[6]), + .rx_data_7_n (rx_data_n[7]), + .rx_data_7_p (rx_data_p[7]), + .rx_ref_clk_0 (rx_ref_clk), + .rx_sync_0 (rx_sync), + .rx_sysref_0 (rx_sysref), + .rx_core_clk (rx_clk), .spdif (spdif), .spi0_clk_i (spi0_clk), .spi0_clk_o (spi0_clk), diff --git a/projects/fmcadc4/common/fmcadc4_bd.tcl b/projects/fmcadc4/common/fmcadc4_bd.tcl index 8077399da..8397df8d0 100644 --- a/projects/fmcadc4/common/fmcadc4_bd.tcl +++ b/projects/fmcadc4/common/fmcadc4_bd.tcl @@ -1,12 +1,6 @@ # fmcadc4 -create_bd_port -dir I rx_ref_clk -create_bd_port -dir O rx_sync -create_bd_port -dir I rx_sysref -create_bd_port -dir I -from 7 -to 0 rx_data_p -create_bd_port -dir I -from 7 -to 0 rx_data_n - # adc peripherals set axi_ad9680_core_0 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9680:1.0 axi_ad9680_core_0] @@ -14,7 +8,12 @@ set_property -dict [list CONFIG.ID {0}] $axi_ad9680_core_0 set axi_ad9680_core_1 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9680:1.0 axi_ad9680_core_1] set_property -dict [list CONFIG.ID {1}] $axi_ad9680_core_1 -set axi_ad9680_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.2 axi_ad9680_jesd] +set axi_ad9680_xcvr [create_bd_cell -type ip -vlnv analog.com:user:axi_adxcvr:1.0 axi_ad9680_xcvr] +set_property -dict [list CONFIG.NUM_OF_LANES {8}] $axi_ad9680_xcvr +set_property -dict [list CONFIG.QPLL_ENABLE {1}] $axi_ad9680_xcvr +set_property -dict [list CONFIG.TX_OR_RX_N {0}] $axi_ad9680_xcvr + +set axi_ad9680_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:7.0 axi_ad9680_jesd] set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9680_jesd set_property -dict [list CONFIG.C_LANES {8}] $axi_ad9680_jesd @@ -37,86 +36,38 @@ set_property -dict [list CONFIG.NUM_OF_CHANNELS {4}] $axi_ad9680_cpack # adc common gt -set axi_fmcadc4_gt [create_bd_cell -type ip -vlnv analog.com:user:axi_jesd_gt:1.0 axi_fmcadc4_gt] -set_property -dict [list CONFIG.NUM_OF_LANES {8}] $axi_fmcadc4_gt -set_property -dict [list CONFIG.QPLL0_ENABLE {1}] $axi_fmcadc4_gt -set_property -dict [list CONFIG.QPLL1_ENABLE {1}] $axi_fmcadc4_gt -set_property -dict [list CONFIG.RX_NUM_OF_LANES {8}] $axi_fmcadc4_gt -set_property -dict [list CONFIG.TX_NUM_OF_LANES {0}] $axi_fmcadc4_gt -set_property -dict [list CONFIG.RX_CLKBUF_ENABLE_0 {1}] $axi_fmcadc4_gt - -set util_fmcadc4_gt [create_bd_cell -type ip -vlnv analog.com:user:util_jesd_gt:1.0 util_fmcadc4_gt] -set_property -dict [list CONFIG.QPLL0_ENABLE {1}] $util_fmcadc4_gt -set_property -dict [list CONFIG.QPLL1_ENABLE {1}] $util_fmcadc4_gt -set_property -dict [list CONFIG.NUM_OF_LANES {8}] $util_fmcadc4_gt -set_property -dict [list CONFIG.RX_ENABLE {1}] $util_fmcadc4_gt -set_property -dict [list CONFIG.RX_NUM_OF_LANES {8}] $util_fmcadc4_gt -set_property -dict [list CONFIG.TX_ENABLE {0}] $util_fmcadc4_gt +set util_fmcadc4_xcvr [create_bd_cell -type ip -vlnv analog.com:user:util_adxcvr:1.0 util_fmcadc4_xcvr] +set_property -dict [list CONFIG.RX_NUM_OF_LANES {8}] $util_fmcadc4_xcvr +set_property -dict [list CONFIG.TX_NUM_OF_LANES {0}] $util_fmcadc4_xcvr create_bd_cell -type ip -vlnv analog.com:user:util_bsplit:1.0 util_bsplit_rx_data set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {128}] [get_bd_cells util_bsplit_rx_data] set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] [get_bd_cells util_bsplit_rx_data] +# reference clocks & resets + +create_bd_port -dir I rx_ref_clk_0 + +ad_xcvrpll rx_ref_clk_0 util_fmcadc4_xcvr/qpll_ref_clk_* +ad_xcvrpll rx_ref_clk_0 util_fmcadc4_xcvr/cpll_ref_clk_* +ad_xcvrpll axi_ad9680_xcvr/up_pll_rst util_fmcadc4_xcvr/up_qpll_rst_* +ad_xcvrpll axi_ad9680_xcvr/up_pll_rst util_fmcadc4_xcvr/up_cpll_rst_* + # connections (gt) -ad_connect util_fmcadc4_gt/qpll_ref_clk rx_ref_clk - -ad_connect axi_fmcadc4_gt/gt_qpll_0 util_fmcadc4_gt/gt_qpll_0 -ad_connect axi_fmcadc4_gt/gt_qpll_1 util_fmcadc4_gt/gt_qpll_1 -ad_connect axi_fmcadc4_gt/gt_pll_0 util_fmcadc4_gt/gt_pll_0 -ad_connect axi_fmcadc4_gt/gt_pll_1 util_fmcadc4_gt/gt_pll_1 -ad_connect axi_fmcadc4_gt/gt_pll_2 util_fmcadc4_gt/gt_pll_2 -ad_connect axi_fmcadc4_gt/gt_pll_3 util_fmcadc4_gt/gt_pll_3 -ad_connect axi_fmcadc4_gt/gt_pll_4 util_fmcadc4_gt/gt_pll_4 -ad_connect axi_fmcadc4_gt/gt_pll_5 util_fmcadc4_gt/gt_pll_5 -ad_connect axi_fmcadc4_gt/gt_pll_6 util_fmcadc4_gt/gt_pll_6 -ad_connect axi_fmcadc4_gt/gt_pll_7 util_fmcadc4_gt/gt_pll_7 -ad_connect axi_fmcadc4_gt/gt_rx_0 util_fmcadc4_gt/gt_rx_0 -ad_connect axi_fmcadc4_gt/gt_rx_1 util_fmcadc4_gt/gt_rx_1 -ad_connect axi_fmcadc4_gt/gt_rx_2 util_fmcadc4_gt/gt_rx_2 -ad_connect axi_fmcadc4_gt/gt_rx_3 util_fmcadc4_gt/gt_rx_3 -ad_connect axi_fmcadc4_gt/gt_rx_4 util_fmcadc4_gt/gt_rx_4 -ad_connect axi_fmcadc4_gt/gt_rx_5 util_fmcadc4_gt/gt_rx_5 -ad_connect axi_fmcadc4_gt/gt_rx_6 util_fmcadc4_gt/gt_rx_6 -ad_connect axi_fmcadc4_gt/gt_rx_7 util_fmcadc4_gt/gt_rx_7 -ad_connect axi_fmcadc4_gt/gt_rx_ip_0 axi_ad9680_jesd/gt0_rx -ad_connect axi_fmcadc4_gt/gt_rx_ip_1 axi_ad9680_jesd/gt1_rx -ad_connect axi_fmcadc4_gt/gt_rx_ip_2 axi_ad9680_jesd/gt2_rx -ad_connect axi_fmcadc4_gt/gt_rx_ip_3 axi_ad9680_jesd/gt3_rx -ad_connect axi_fmcadc4_gt/gt_rx_ip_4 axi_ad9680_jesd/gt4_rx -ad_connect axi_fmcadc4_gt/gt_rx_ip_5 axi_ad9680_jesd/gt5_rx -ad_connect axi_fmcadc4_gt/gt_rx_ip_6 axi_ad9680_jesd/gt6_rx -ad_connect axi_fmcadc4_gt/gt_rx_ip_7 axi_ad9680_jesd/gt7_rx -ad_connect axi_fmcadc4_gt/rx_gt_comma_align_enb_0 axi_ad9680_jesd/rxencommaalign_out -ad_connect axi_fmcadc4_gt/rx_gt_comma_align_enb_1 axi_ad9680_jesd/rxencommaalign_out -ad_connect axi_fmcadc4_gt/rx_gt_comma_align_enb_2 axi_ad9680_jesd/rxencommaalign_out -ad_connect axi_fmcadc4_gt/rx_gt_comma_align_enb_3 axi_ad9680_jesd/rxencommaalign_out -ad_connect axi_fmcadc4_gt/rx_gt_comma_align_enb_4 axi_ad9680_jesd/rxencommaalign_out -ad_connect axi_fmcadc4_gt/rx_gt_comma_align_enb_5 axi_ad9680_jesd/rxencommaalign_out -ad_connect axi_fmcadc4_gt/rx_gt_comma_align_enb_6 axi_ad9680_jesd/rxencommaalign_out -ad_connect axi_fmcadc4_gt/rx_gt_comma_align_enb_7 axi_ad9680_jesd/rxencommaalign_out +ad_xcvrcon util_fmcadc4_xcvr axi_ad9680_xcvr axi_ad9680_jesd +ad_connect util_fmcadc4_xcvr/rx_out_clk_0 axi_ad9680_cpack/adc_clk +ad_connect util_fmcadc4_xcvr/rx_out_clk_0 axi_ad9680_core_0/rx_clk +ad_connect util_fmcadc4_xcvr/rx_out_clk_0 axi_ad9680_core_1/rx_clk +ad_connect axi_ad9680_jesd/rx_start_of_frame axi_ad9680_core_0/rx_sof +ad_connect axi_ad9680_jesd/rx_start_of_frame axi_ad9680_core_1/rx_sof +ad_connect axi_ad9680_jesd/rx_tdata util_bsplit_rx_data/data +ad_connect axi_ad9680_jesd_rstgen/peripheral_reset axi_ad9680_cpack/adc_rst # connections (adc) -ad_connect util_fmcadc4_gt/rx_p rx_data_p -ad_connect util_fmcadc4_gt/rx_n rx_data_n -ad_connect util_fmcadc4_gt/rx_sysref rx_sysref -ad_connect util_fmcadc4_gt/rx_sync rx_sync -ad_connect util_fmcadc4_gt/rx_out_clk util_fmcadc4_gt/rx_clk -ad_connect util_fmcadc4_gt/rx_out_clk axi_ad9680_jesd/rx_core_clk -ad_connect util_fmcadc4_gt/rx_ip_rst axi_ad9680_jesd/rx_reset -ad_connect util_fmcadc4_gt/rx_ip_rst_done axi_ad9680_jesd/rx_reset_done -ad_connect util_fmcadc4_gt/rx_ip_sysref axi_ad9680_jesd/rx_sysref -ad_connect util_fmcadc4_gt/rx_ip_sync axi_ad9680_jesd/rx_sync -ad_connect util_fmcadc4_gt/rx_ip_sof axi_ad9680_jesd/rx_start_of_frame -ad_connect util_fmcadc4_gt/rx_ip_data axi_ad9680_jesd/rx_tdata -ad_connect util_fmcadc4_gt/rx_data util_bsplit_rx_data/data -ad_connect util_fmcadc4_gt/rx_out_clk axi_ad9680_core_0/rx_clk -ad_connect util_fmcadc4_gt/rx_out_clk axi_ad9680_core_1/rx_clk ad_connect util_bsplit_rx_data/split_data_0 axi_ad9680_core_0/rx_data ad_connect util_bsplit_rx_data/split_data_1 axi_ad9680_core_1/rx_data -ad_connect util_fmcadc4_gt/rx_out_clk axi_ad9680_cpack/adc_clk -ad_connect util_fmcadc4_gt/rx_rst axi_ad9680_cpack/adc_rst ad_connect axi_ad9680_core_0/adc_enable_0 axi_ad9680_cpack/adc_enable_0 ad_connect axi_ad9680_core_0/adc_valid_0 axi_ad9680_cpack/adc_valid_0 ad_connect axi_ad9680_core_0/adc_data_0 axi_ad9680_cpack/adc_data_0 @@ -129,8 +80,8 @@ ad_connect axi_ad9680_core_1/adc_data_0 axi_ad9680_cpack/adc_data_2 ad_connect axi_ad9680_core_1/adc_enable_1 axi_ad9680_cpack/adc_enable_3 ad_connect axi_ad9680_core_1/adc_valid_1 axi_ad9680_cpack/adc_valid_3 ad_connect axi_ad9680_core_1/adc_data_1 axi_ad9680_cpack/adc_data_3 -ad_connect util_fmcadc4_gt/rx_out_clk axi_ad9680_fifo/adc_clk -ad_connect util_fmcadc4_gt/rx_rst axi_ad9680_fifo/adc_rst +ad_connect util_fmcadc4_xcvr/rx_out_clk_0 axi_ad9680_fifo/adc_clk +ad_connect axi_ad9680_jesd_rstgen/peripheral_reset axi_ad9680_fifo/adc_rst ad_connect axi_ad9680_cpack/adc_valid axi_ad9680_fifo/adc_wr ad_connect axi_ad9680_cpack/adc_data axi_ad9680_fifo/adc_wdata ad_connect sys_cpu_clk axi_ad9680_fifo/dma_clk @@ -142,9 +93,12 @@ ad_connect axi_ad9680_fifo/dma_wready axi_ad9680_dma/s_axis_ready ad_connect axi_ad9680_fifo/dma_xfer_req axi_ad9680_dma/s_axis_xfer_req ad_connect axi_ad9680_core_0/adc_dovf axi_ad9680_fifo/adc_wovf +ad_connect sys_cpu_clk util_fmcadc4_xcvr/up_clk +ad_connect sys_cpu_resetn util_fmcadc4_xcvr/up_rstn + # interconnect (cpu) -ad_cpu_interconnect 0x44A60000 axi_fmcadc4_gt +ad_cpu_interconnect 0x44A60000 axi_ad9680_xcvr ad_cpu_interconnect 0x44A00000 axi_ad9680_core_0 ad_cpu_interconnect 0x44A10000 axi_ad9680_core_1 ad_cpu_interconnect 0x44A91000 axi_ad9680_jesd @@ -153,7 +107,7 @@ ad_cpu_interconnect 0x7c400000 axi_ad9680_dma # gt uses hp3, and 100MHz clock for both DRP and AXI4 ad_mem_hp3_interconnect sys_cpu_clk sys_ps7/S_AXI_HP3 -ad_mem_hp3_interconnect sys_cpu_clk axi_fmcadc4_gt/m_axi +ad_mem_hp3_interconnect sys_cpu_clk axi_ad9680_xcvr/m_axi # interconnect (mem/adc) diff --git a/projects/fmcadc4/zc706/Makefile b/projects/fmcadc4/zc706/Makefile index e3d0a21a2..a4aa9799c 100644 --- a/projects/fmcadc4/zc706/Makefile +++ b/projects/fmcadc4/zc706/Makefile @@ -14,23 +14,22 @@ M_DEPS += ../common/fmcadc4_bd.tcl M_DEPS += ../../scripts/adi_project.tcl M_DEPS += ../../scripts/adi_env.tcl M_DEPS += ../../scripts/adi_board.tcl -M_DEPS += ../../common/zc706/zc706_system_plddr3.tcl +M_DEPS += ../../common/zc706/zc706_system_plddr3_adcfifo.tcl M_DEPS += ../../common/zc706/zc706_system_mig_constr.xdc M_DEPS += ../../common/zc706/zc706_system_mig.prj M_DEPS += ../../common/zc706/zc706_system_constr.xdc M_DEPS += ../../common/zc706/zc706_system_bd.tcl -M_DEPS += ../../../library/common/ad_iobuf.v +M_DEPS += ../../../library/xilinx/common/ad_iobuf.v M_DEPS += ../../../library/axi_ad9680/axi_ad9680.xpr -M_DEPS += ../../../library/axi_adcfifo/axi_adcfifo.xpr +M_DEPS += ../../../library/xilinx/axi_adcfifo/axi_adcfifo.xpr +M_DEPS += ../../../library/xilinx/axi_adxcvr/axi_adxcvr.xpr M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr -M_DEPS += ../../../library/axi_jesd_gt/axi_jesd_gt.xpr M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr +M_DEPS += ../../../library/xilinx/util_adxcvr/util_adxcvr.xpr M_DEPS += ../../../library/util_bsplit/util_bsplit.xpr M_DEPS += ../../../library/util_cpack/util_cpack.xpr -M_DEPS += ../../../library/util_jesd_gt/util_jesd_gt.xpr -M_DEPS += ../../../library/util_mfifo/util_mfifo.xpr M_VIVADO := vivado -mode batch -source @@ -46,6 +45,7 @@ M_FLIST += *.sdk M_FLIST += *.hw M_FLIST += *.sim M_FLIST += .Xil +M_FLIST += *.ip_user_files @@ -59,35 +59,33 @@ clean: clean-all:clean make -C ../../../library/axi_ad9680 clean - make -C ../../../library/axi_adcfifo clean + make -C ../../../library/xilinx/axi_adcfifo clean + make -C ../../../library/xilinx/axi_adxcvr clean make -C ../../../library/axi_clkgen clean make -C ../../../library/axi_dmac clean make -C ../../../library/axi_hdmi_tx clean - make -C ../../../library/axi_jesd_gt clean make -C ../../../library/axi_spdif_tx clean + make -C ../../../library/xilinx/util_adxcvr clean make -C ../../../library/util_bsplit clean make -C ../../../library/util_cpack clean - make -C ../../../library/util_jesd_gt clean - make -C ../../../library/util_mfifo clean fmcadc4_zc706.sdk/system_top.hdf: $(M_DEPS) - rm -rf $(M_FLIST) + -rm -rf $(M_FLIST) $(M_VIVADO) system_project.tcl >> fmcadc4_zc706_vivado.log 2>&1 lib: make -C ../../../library/axi_ad9680 - make -C ../../../library/axi_adcfifo + make -C ../../../library/xilinx/axi_adcfifo + make -C ../../../library/xilinx/axi_adxcvr make -C ../../../library/axi_clkgen make -C ../../../library/axi_dmac make -C ../../../library/axi_hdmi_tx - make -C ../../../library/axi_jesd_gt make -C ../../../library/axi_spdif_tx + make -C ../../../library/xilinx/util_adxcvr make -C ../../../library/util_bsplit make -C ../../../library/util_cpack - make -C ../../../library/util_jesd_gt - make -C ../../../library/util_mfifo #################################################################################### #################################################################################### diff --git a/projects/fmcadc4/zc706/system_bd.tcl b/projects/fmcadc4/zc706/system_bd.tcl index 06ae1973f..91e5cfa22 100644 --- a/projects/fmcadc4/zc706/system_bd.tcl +++ b/projects/fmcadc4/zc706/system_bd.tcl @@ -1,8 +1,8 @@ source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl -source $ad_hdl_dir/projects/common/zc706/zc706_system_plddr3.tcl +source $ad_hdl_dir/projects/common/zc706/zc706_system_plddr3_adcfifo.tcl -p_plddr3_fifo [current_bd_instance .] axi_ad9680_fifo 256 +p_plddr3_adcfifo [current_bd_instance .] axi_ad9680_fifo 256 create_bd_port -dir I -type rst sys_rst create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr3 @@ -20,39 +20,3 @@ create_bd_addr_seg -range 0x40000000 -offset 0x80000000 \ SEG_axi_ddr_cntrl_memaddr source ../common/fmcadc4_bd.tcl - -# ila - -set mfifo_adc [create_bd_cell -type ip -vlnv analog.com:user:util_mfifo:1.0 mfifo_adc] -set_property -dict [list CONFIG.NUM_OF_CHANNELS {4}] $mfifo_adc -set_property -dict [list CONFIG.DIN_DATA_WIDTH {64}] $mfifo_adc -set_property -dict [list CONFIG.ADDRESS_WIDTH {8}] $mfifo_adc - -set ila_adc [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.0 ila_adc] -set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_adc -set_property -dict [list CONFIG.C_TRIGIN_EN {false}] $ila_adc -set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila_adc -set_property -dict [list CONFIG.C_NUM_OF_PROBES {5}] $ila_adc -set_property -dict [list CONFIG.C_PROBE0_WIDTH {1}] $ila_adc -set_property -dict [list CONFIG.C_PROBE1_WIDTH {16}] $ila_adc -set_property -dict [list CONFIG.C_PROBE2_WIDTH {16}] $ila_adc -set_property -dict [list CONFIG.C_PROBE3_WIDTH {16}] $ila_adc -set_property -dict [list CONFIG.C_PROBE4_WIDTH {16}] $ila_adc - -ad_connect util_fmcadc4_gt/rx_rst mfifo_adc/din_rst -ad_connect util_fmcadc4_gt/rx_out_clk mfifo_adc/din_clk -ad_connect axi_ad9680_core_0/adc_valid_0 mfifo_adc/din_valid -ad_connect axi_ad9680_core_0/adc_data_0 mfifo_adc/din_data_0 -ad_connect axi_ad9680_core_0/adc_data_1 mfifo_adc/din_data_1 -ad_connect axi_ad9680_core_1/adc_data_0 mfifo_adc/din_data_2 -ad_connect axi_ad9680_core_1/adc_data_1 mfifo_adc/din_data_3 -ad_connect util_fmcadc4_gt/rx_rst mfifo_adc/dout_rst -ad_connect util_fmcadc4_gt/rx_out_clk mfifo_adc/dout_clk -ad_connect util_fmcadc4_gt/rx_out_clk ila_adc/clk -ad_connect mfifo_adc/dout_valid ila_adc/probe0 -ad_connect mfifo_adc/dout_data_0 ila_adc/probe1 -ad_connect mfifo_adc/dout_data_1 ila_adc/probe2 -ad_connect mfifo_adc/dout_data_2 ila_adc/probe3 -ad_connect mfifo_adc/dout_data_3 ila_adc/probe4 - - diff --git a/projects/fmcadc4/zc706/system_constr.xdc b/projects/fmcadc4/zc706/system_constr.xdc index 4f8607ec8..a3486e1e2 100644 --- a/projects/fmcadc4/zc706/system_constr.xdc +++ b/projects/fmcadc4/zc706/system_constr.xdc @@ -46,5 +46,4 @@ set_property -dict {PACKAGE_PIN AE23 IOSTANDARD LVCMOS25} [get_ports ad9680_2 # clocks create_clock -name rx_ref_clk -period 2.00 [get_ports rx_ref_clk_p] -create_clock -name rx_div_clk -period 4.00 [get_pins i_system_wrapper/system_i/axi_fmcadc4_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK] - +create_clock -name rx_div_clk -period 4.00 [get_pins i_system_wrapper/system_i/util_fmcadc4_xcvr/inst/i_xch_0/i_gtxe2_channel/RXOUTCLK] diff --git a/projects/fmcadc4/zc706/system_project.tcl b/projects/fmcadc4/zc706/system_project.tcl index 6c4b2df86..63fe133b5 100644 --- a/projects/fmcadc4/zc706/system_project.tcl +++ b/projects/fmcadc4/zc706/system_project.tcl @@ -10,13 +10,10 @@ adi_project_files fmcadc4_zc706 [list \ "../common/fmcadc4_spi.v" \ "system_top.v" \ "system_constr.xdc"\ - "$ad_hdl_dir/library/common/ad_iobuf.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \ "$ad_hdl_dir/projects/common/zc706/zc706_system_mig_constr.xdc" \ "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ] -set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc] -set_property PROCESSING_ORDER EARLY [get_files system_constr.xdc] - adi_project_run fmcadc4_zc706 diff --git a/projects/fmcadc4/zc706/system_top.v b/projects/fmcadc4/zc706/system_top.v index 77be2f7b0..2f89d49b9 100644 --- a/projects/fmcadc4/zc706/system_top.v +++ b/projects/fmcadc4/zc706/system_top.v @@ -345,11 +345,25 @@ module system_top ( .ps_intr_10 (1'b0), .ps_intr_11 (1'b0), .ps_intr_12 (1'b0), - .rx_data_n (rx_data_n), - .rx_data_p (rx_data_p), - .rx_ref_clk (rx_ref_clk), - .rx_sync (rx_sync), - .rx_sysref (rx_sysref), + .rx_data_0_n (rx_data_n[0]), + .rx_data_0_p (rx_data_p[0]), + .rx_data_1_n (rx_data_n[1]), + .rx_data_1_p (rx_data_p[1]), + .rx_data_2_n (rx_data_n[2]), + .rx_data_2_p (rx_data_p[2]), + .rx_data_3_n (rx_data_n[3]), + .rx_data_3_p (rx_data_p[3]), + .rx_data_4_n (rx_data_n[4]), + .rx_data_4_p (rx_data_p[4]), + .rx_data_5_n (rx_data_n[5]), + .rx_data_5_p (rx_data_p[5]), + .rx_data_6_n (rx_data_n[6]), + .rx_data_6_p (rx_data_p[6]), + .rx_data_7_n (rx_data_n[7]), + .rx_data_7_p (rx_data_p[7]), + .rx_ref_clk_0 (rx_ref_clk), + .rx_sync_0 (rx_sync), + .rx_sysref_0 (rx_sysref), .spdif (spdif), .spi0_clk_i (spi0_clk), .spi0_clk_o (spi0_clk), diff --git a/projects/fmcadc5/common/fmcadc5_bd.tcl b/projects/fmcadc5/common/fmcadc5_bd.tcl index 4b3d0c793..bb5f8d6d2 100644 --- a/projects/fmcadc5/common/fmcadc5_bd.tcl +++ b/projects/fmcadc5/common/fmcadc5_bd.tcl @@ -1,30 +1,61 @@ - -# ad9625 - -create_bd_port -dir I rx_ref_clk_0 -create_bd_port -dir I -from 7 -to 0 rx_data_0_p -create_bd_port -dir I -from 7 -to 0 rx_data_0_n -create_bd_port -dir O rx_sync_0 -create_bd_port -dir I rx_ref_clk_1 -create_bd_port -dir I -from 7 -to 0 rx_data_1_p -create_bd_port -dir I -from 7 -to 0 rx_data_1_n -create_bd_port -dir O rx_sync_1 -create_bd_port -dir O rx_sysref -create_bd_port -dir O rx_clk - # adc peripherals +set util_fmcadc5_0_xcvr [create_bd_cell -type ip -vlnv analog.com:user:util_adxcvr:1.0 util_fmcadc5_0_xcvr] +set_property -dict [list CONFIG.QPLL_FBDIV {"0010000000"}] $util_fmcadc5_0_xcvr +set_property -dict [list CONFIG.CPLL_FBDIV {1}] $util_fmcadc5_0_xcvr +set_property -dict [list CONFIG.TX_NUM_OF_LANES {0}] $util_fmcadc5_0_xcvr +set_property -dict [list CONFIG.TX_OUT_DIV {2}] $util_fmcadc5_0_xcvr +set_property -dict [list CONFIG.TX_CLK25_DIV {10}] $util_fmcadc5_0_xcvr +set_property -dict [list CONFIG.RX_NUM_OF_LANES {8}] $util_fmcadc5_0_xcvr +set_property -dict [list CONFIG.RX_OUT_DIV {1}] $util_fmcadc5_0_xcvr +set_property -dict [list CONFIG.RX_CLK25_DIV {25}] $util_fmcadc5_0_xcvr +set_property -dict [list CONFIG.RX_DFE_LPM_CFG {0x0954}] $util_fmcadc5_0_xcvr +set_property -dict [list CONFIG.RX_CDR_CFG {0x03000023ff20400020}] $util_fmcadc5_0_xcvr +set_property -dict [list CONFIG.RX_PMA_CFG {0x00018480}] $util_fmcadc5_0_xcvr +set util_fmcadc5_1_xcvr [create_bd_cell -type ip -vlnv analog.com:user:util_adxcvr:1.0 util_fmcadc5_1_xcvr] +set_property -dict [list CONFIG.QPLL_FBDIV {"0010000000"}] $util_fmcadc5_1_xcvr +set_property -dict [list CONFIG.CPLL_FBDIV {1}] $util_fmcadc5_1_xcvr +set_property -dict [list CONFIG.TX_NUM_OF_LANES {0}] $util_fmcadc5_1_xcvr +set_property -dict [list CONFIG.TX_OUT_DIV {2}] $util_fmcadc5_1_xcvr +set_property -dict [list CONFIG.TX_CLK25_DIV {10}] $util_fmcadc5_1_xcvr +set_property -dict [list CONFIG.RX_NUM_OF_LANES {8}] $util_fmcadc5_1_xcvr +set_property -dict [list CONFIG.RX_OUT_DIV {1}] $util_fmcadc5_1_xcvr +set_property -dict [list CONFIG.RX_CLK25_DIV {25}] $util_fmcadc5_1_xcvr +set_property -dict [list CONFIG.RX_DFE_LPM_CFG {0x0954}] $util_fmcadc5_1_xcvr +set_property -dict [list CONFIG.RX_CDR_CFG {0x03000023ff20400020}] $util_fmcadc5_1_xcvr +set_property -dict [list CONFIG.RX_PMA_CFG {0x00018480}] $util_fmcadc5_1_xcvr + +set axi_ad9625_0_xcvr [create_bd_cell -type ip -vlnv analog.com:user:axi_adxcvr:1.0 axi_ad9625_0_xcvr] +set_property -dict [list CONFIG.NUM_OF_LANES {8}] $axi_ad9625_0_xcvr +set_property -dict [list CONFIG.QPLL_ENABLE {0}] $axi_ad9625_0_xcvr +set_property -dict [list CONFIG.TX_OR_RX_N {0}] $axi_ad9625_0_xcvr +set_property -dict [list CONFIG.LPM_OR_DFE_N {0}] $axi_ad9625_0_xcvr +set_property -dict [list CONFIG.SYS_CLK_SEL {"00"}] $axi_ad9625_0_xcvr +set_property -dict [list CONFIG.OUT_CLK_SEL {"010"}] $axi_ad9625_0_xcvr + +set axi_ad9625_1_xcvr [create_bd_cell -type ip -vlnv analog.com:user:axi_adxcvr:1.0 axi_ad9625_1_xcvr] +set_property -dict [list CONFIG.NUM_OF_LANES {8}] $axi_ad9625_1_xcvr +set_property -dict [list CONFIG.QPLL_ENABLE {0}] $axi_ad9625_1_xcvr +set_property -dict [list CONFIG.TX_OR_RX_N {0}] $axi_ad9625_1_xcvr +set_property -dict [list CONFIG.LPM_OR_DFE_N {0}] $axi_ad9625_1_xcvr +set_property -dict [list CONFIG.SYS_CLK_SEL {"00"}] $axi_ad9625_1_xcvr +set_property -dict [list CONFIG.OUT_CLK_SEL {"010"}] $axi_ad9625_1_xcvr + +set axi_ad9625_0_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:7.0 axi_ad9625_0_jesd] +set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9625_0_jesd +set_property -dict [list CONFIG.C_LANES {8}] $axi_ad9625_0_jesd +set axi_ad9625_1_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:7.0 axi_ad9625_1_jesd] +set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9625_1_jesd +set_property -dict [list CONFIG.C_LANES {8}] $axi_ad9625_1_jesd + set axi_ad9625_0_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9625:1.0 axi_ad9625_0_core] set_property -dict [list CONFIG.ID {0}] $axi_ad9625_0_core set axi_ad9625_1_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9625:1.0 axi_ad9625_1_core] set_property -dict [list CONFIG.ID {1}] $axi_ad9625_1_core -set axi_ad9625_0_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.2 axi_ad9625_0_jesd] -set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9625_0_jesd -set_property -dict [list CONFIG.C_LANES {8}] $axi_ad9625_0_jesd -set axi_ad9625_1_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.2 axi_ad9625_1_jesd] -set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9625_1_jesd -set_property -dict [list CONFIG.C_LANES {8}] $axi_ad9625_1_jesd +set util_ad9625_cpack [create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 util_ad9625_cpack] +set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {256}] $util_ad9625_cpack +set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $util_ad9625_cpack set axi_ad9625_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9625_dma] set_property -dict [list CONFIG.DMA_TYPE_SRC {1}] $axi_ad9625_dma @@ -39,223 +70,55 @@ set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad9625_dma set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {64}] $axi_ad9625_dma set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $axi_ad9625_dma -p_sys_dmafifo [current_bd_instance .] axi_ad9625_fifo 512 18 +p_sys_adcfifo [current_bd_instance .] axi_ad9625_fifo 512 18 -# adc common gt +# reference clocks & resets -set axi_fmcadc5_0_gt [create_bd_cell -type ip -vlnv analog.com:user:axi_jesd_gt:1.0 axi_fmcadc5_0_gt] -set_property -dict [list CONFIG.ID {0}] $axi_fmcadc5_0_gt -set_property -dict [list CONFIG.NUM_OF_LANES {8}] $axi_fmcadc5_0_gt -set_property -dict [list CONFIG.PMA_RSV_0 {0x00018480}] $axi_fmcadc5_0_gt -set_property -dict [list CONFIG.CPLL_FBDIV_0 {1}] $axi_fmcadc5_0_gt -set_property -dict [list CONFIG.PMA_RSV_1 {0x00018480}] $axi_fmcadc5_0_gt -set_property -dict [list CONFIG.CPLL_FBDIV_1 {1}] $axi_fmcadc5_0_gt -set_property -dict [list CONFIG.PMA_RSV_2 {0x00018480}] $axi_fmcadc5_0_gt -set_property -dict [list CONFIG.CPLL_FBDIV_2 {1}] $axi_fmcadc5_0_gt -set_property -dict [list CONFIG.PMA_RSV_3 {0x00018480}] $axi_fmcadc5_0_gt -set_property -dict [list CONFIG.CPLL_FBDIV_3 {1}] $axi_fmcadc5_0_gt -set_property -dict [list CONFIG.PMA_RSV_4 {0x00018480}] $axi_fmcadc5_0_gt -set_property -dict [list CONFIG.CPLL_FBDIV_4 {1}] $axi_fmcadc5_0_gt -set_property -dict [list CONFIG.PMA_RSV_5 {0x00018480}] $axi_fmcadc5_0_gt -set_property -dict [list CONFIG.CPLL_FBDIV_5 {1}] $axi_fmcadc5_0_gt -set_property -dict [list CONFIG.PMA_RSV_6 {0x00018480}] $axi_fmcadc5_0_gt -set_property -dict [list CONFIG.CPLL_FBDIV_6 {1}] $axi_fmcadc5_0_gt -set_property -dict [list CONFIG.PMA_RSV_7 {0x00018480}] $axi_fmcadc5_0_gt -set_property -dict [list CONFIG.CPLL_FBDIV_7 {1}] $axi_fmcadc5_0_gt -set_property -dict [list CONFIG.RX_NUM_OF_LANES {8}] $axi_fmcadc5_0_gt -set_property -dict [list CONFIG.TX_NUM_OF_LANES {0}] $axi_fmcadc5_0_gt -set_property -dict [list CONFIG.RX_CLK25_DIV_0 {25}] $axi_fmcadc5_0_gt -set_property -dict [list CONFIG.RX_CDR_CFG_0 {0x03000023ff20400020}] $axi_fmcadc5_0_gt -set_property -dict [list CONFIG.RX_CLK25_DIV_1 {25}] $axi_fmcadc5_0_gt -set_property -dict [list CONFIG.RX_CDR_CFG_1 {0x03000023ff20400020}] $axi_fmcadc5_0_gt -set_property -dict [list CONFIG.RX_CLK25_DIV_2 {25}] $axi_fmcadc5_0_gt -set_property -dict [list CONFIG.RX_CDR_CFG_2 {0x03000023ff20400020}] $axi_fmcadc5_0_gt -set_property -dict [list CONFIG.RX_CLK25_DIV_3 {25}] $axi_fmcadc5_0_gt -set_property -dict [list CONFIG.RX_CDR_CFG_3 {0x03000023ff20400020}] $axi_fmcadc5_0_gt -set_property -dict [list CONFIG.RX_CLK25_DIV_4 {25}] $axi_fmcadc5_0_gt -set_property -dict [list CONFIG.RX_CDR_CFG_4 {0x03000023ff20400020}] $axi_fmcadc5_0_gt -set_property -dict [list CONFIG.RX_CLK25_DIV_5 {25}] $axi_fmcadc5_0_gt -set_property -dict [list CONFIG.RX_CDR_CFG_5 {0x03000023ff20400020}] $axi_fmcadc5_0_gt -set_property -dict [list CONFIG.RX_CLK25_DIV_6 {25}] $axi_fmcadc5_0_gt -set_property -dict [list CONFIG.RX_CDR_CFG_6 {0x03000023ff20400020}] $axi_fmcadc5_0_gt -set_property -dict [list CONFIG.RX_CLK25_DIV_7 {25}] $axi_fmcadc5_0_gt -set_property -dict [list CONFIG.RX_CDR_CFG_7 {0x03000023ff20400020}] $axi_fmcadc5_0_gt +create_bd_port -dir I rx_ref_clk_0 +create_bd_port -dir I rx_ref_clk_1 -set axi_fmcadc5_1_gt [create_bd_cell -type ip -vlnv analog.com:user:axi_jesd_gt:1.0 axi_fmcadc5_1_gt] -set_property -dict [list CONFIG.ID {1}] $axi_fmcadc5_1_gt -set_property -dict [list CONFIG.NUM_OF_LANES {8}] $axi_fmcadc5_1_gt -set_property -dict [list CONFIG.PMA_RSV_0 {0x00018480}] $axi_fmcadc5_1_gt -set_property -dict [list CONFIG.CPLL_FBDIV_0 {1}] $axi_fmcadc5_1_gt -set_property -dict [list CONFIG.PMA_RSV_1 {0x00018480}] $axi_fmcadc5_1_gt -set_property -dict [list CONFIG.CPLL_FBDIV_1 {1}] $axi_fmcadc5_1_gt -set_property -dict [list CONFIG.PMA_RSV_2 {0x00018480}] $axi_fmcadc5_1_gt -set_property -dict [list CONFIG.CPLL_FBDIV_2 {1}] $axi_fmcadc5_1_gt -set_property -dict [list CONFIG.PMA_RSV_3 {0x00018480}] $axi_fmcadc5_1_gt -set_property -dict [list CONFIG.CPLL_FBDIV_3 {1}] $axi_fmcadc5_1_gt -set_property -dict [list CONFIG.PMA_RSV_4 {0x00018480}] $axi_fmcadc5_1_gt -set_property -dict [list CONFIG.CPLL_FBDIV_4 {1}] $axi_fmcadc5_1_gt -set_property -dict [list CONFIG.PMA_RSV_5 {0x00018480}] $axi_fmcadc5_1_gt -set_property -dict [list CONFIG.CPLL_FBDIV_5 {1}] $axi_fmcadc5_1_gt -set_property -dict [list CONFIG.PMA_RSV_6 {0x00018480}] $axi_fmcadc5_1_gt -set_property -dict [list CONFIG.CPLL_FBDIV_6 {1}] $axi_fmcadc5_1_gt -set_property -dict [list CONFIG.PMA_RSV_7 {0x00018480}] $axi_fmcadc5_1_gt -set_property -dict [list CONFIG.CPLL_FBDIV_7 {1}] $axi_fmcadc5_1_gt -set_property -dict [list CONFIG.RX_NUM_OF_LANES {8}] $axi_fmcadc5_1_gt -set_property -dict [list CONFIG.TX_NUM_OF_LANES {0}] $axi_fmcadc5_1_gt -set_property -dict [list CONFIG.RX_CLK25_DIV_0 {25}] $axi_fmcadc5_1_gt -set_property -dict [list CONFIG.RX_CDR_CFG_0 {0x03000023ff20400020}] $axi_fmcadc5_1_gt -set_property -dict [list CONFIG.RX_CLK25_DIV_1 {25}] $axi_fmcadc5_1_gt -set_property -dict [list CONFIG.RX_CDR_CFG_1 {0x03000023ff20400020}] $axi_fmcadc5_1_gt -set_property -dict [list CONFIG.RX_CLK25_DIV_2 {25}] $axi_fmcadc5_1_gt -set_property -dict [list CONFIG.RX_CDR_CFG_2 {0x03000023ff20400020}] $axi_fmcadc5_1_gt -set_property -dict [list CONFIG.RX_CLK25_DIV_3 {25}] $axi_fmcadc5_1_gt -set_property -dict [list CONFIG.RX_CDR_CFG_3 {0x03000023ff20400020}] $axi_fmcadc5_1_gt -set_property -dict [list CONFIG.RX_CLK25_DIV_4 {25}] $axi_fmcadc5_1_gt -set_property -dict [list CONFIG.RX_CDR_CFG_4 {0x03000023ff20400020}] $axi_fmcadc5_1_gt -set_property -dict [list CONFIG.RX_CLK25_DIV_5 {25}] $axi_fmcadc5_1_gt -set_property -dict [list CONFIG.RX_CDR_CFG_5 {0x03000023ff20400020}] $axi_fmcadc5_1_gt -set_property -dict [list CONFIG.RX_CLK25_DIV_6 {25}] $axi_fmcadc5_1_gt -set_property -dict [list CONFIG.RX_CDR_CFG_6 {0x03000023ff20400020}] $axi_fmcadc5_1_gt -set_property -dict [list CONFIG.RX_CLK25_DIV_7 {25}] $axi_fmcadc5_1_gt -set_property -dict [list CONFIG.RX_CDR_CFG_7 {0x03000023ff20400020}] $axi_fmcadc5_1_gt - -set util_fmcadc5_0_gt [create_bd_cell -type ip -vlnv analog.com:user:util_jesd_gt:1.0 util_fmcadc5_0_gt] -set_property -dict [list CONFIG.NUM_OF_LANES {8}] $util_fmcadc5_0_gt -set_property -dict [list CONFIG.RX_ENABLE {1}] $util_fmcadc5_0_gt -set_property -dict [list CONFIG.RX_NUM_OF_LANES {8}] $util_fmcadc5_0_gt -set_property -dict [list CONFIG.TX_ENABLE {0}] $util_fmcadc5_0_gt - -set util_fmcadc5_1_gt [create_bd_cell -type ip -vlnv analog.com:user:util_jesd_gt:1.0 util_fmcadc5_1_gt] -set_property -dict [list CONFIG.NUM_OF_LANES {8}] $util_fmcadc5_1_gt -set_property -dict [list CONFIG.RX_ENABLE {1}] $util_fmcadc5_1_gt -set_property -dict [list CONFIG.RX_NUM_OF_LANES {8}] $util_fmcadc5_1_gt -set_property -dict [list CONFIG.TX_ENABLE {0}] $util_fmcadc5_1_gt - -set axi_fmcadc5_cpack [create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 axi_fmcadc5_cpack] -set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {256}] $axi_fmcadc5_cpack -set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $axi_fmcadc5_cpack - -# connections (gt) - -ad_connect util_fmcadc5_0_gt/cpll_ref_clk rx_ref_clk_0 -ad_connect util_fmcadc5_1_gt/cpll_ref_clk rx_ref_clk_1 - -ad_connect axi_fmcadc5_0_gt/gt_qpll_0 util_fmcadc5_0_gt/gt_qpll_0 -ad_connect axi_fmcadc5_0_gt/gt_qpll_1 util_fmcadc5_0_gt/gt_qpll_1 -ad_connect axi_fmcadc5_0_gt/gt_pll_0 util_fmcadc5_0_gt/gt_pll_0 -ad_connect axi_fmcadc5_0_gt/gt_pll_1 util_fmcadc5_0_gt/gt_pll_1 -ad_connect axi_fmcadc5_0_gt/gt_pll_2 util_fmcadc5_0_gt/gt_pll_2 -ad_connect axi_fmcadc5_0_gt/gt_pll_3 util_fmcadc5_0_gt/gt_pll_3 -ad_connect axi_fmcadc5_0_gt/gt_pll_4 util_fmcadc5_0_gt/gt_pll_4 -ad_connect axi_fmcadc5_0_gt/gt_pll_5 util_fmcadc5_0_gt/gt_pll_5 -ad_connect axi_fmcadc5_0_gt/gt_pll_6 util_fmcadc5_0_gt/gt_pll_6 -ad_connect axi_fmcadc5_0_gt/gt_pll_7 util_fmcadc5_0_gt/gt_pll_7 -ad_connect axi_fmcadc5_1_gt/gt_qpll_0 util_fmcadc5_1_gt/gt_qpll_0 -ad_connect axi_fmcadc5_1_gt/gt_qpll_1 util_fmcadc5_1_gt/gt_qpll_1 -ad_connect axi_fmcadc5_1_gt/gt_pll_0 util_fmcadc5_1_gt/gt_pll_0 -ad_connect axi_fmcadc5_1_gt/gt_pll_1 util_fmcadc5_1_gt/gt_pll_1 -ad_connect axi_fmcadc5_1_gt/gt_pll_2 util_fmcadc5_1_gt/gt_pll_2 -ad_connect axi_fmcadc5_1_gt/gt_pll_3 util_fmcadc5_1_gt/gt_pll_3 -ad_connect axi_fmcadc5_1_gt/gt_pll_4 util_fmcadc5_1_gt/gt_pll_4 -ad_connect axi_fmcadc5_1_gt/gt_pll_5 util_fmcadc5_1_gt/gt_pll_5 -ad_connect axi_fmcadc5_1_gt/gt_pll_6 util_fmcadc5_1_gt/gt_pll_6 -ad_connect axi_fmcadc5_1_gt/gt_pll_7 util_fmcadc5_1_gt/gt_pll_7 -ad_connect axi_fmcadc5_0_gt/gt_rx_0 util_fmcadc5_0_gt/gt_rx_0 -ad_connect axi_fmcadc5_0_gt/gt_rx_1 util_fmcadc5_0_gt/gt_rx_1 -ad_connect axi_fmcadc5_0_gt/gt_rx_2 util_fmcadc5_0_gt/gt_rx_2 -ad_connect axi_fmcadc5_0_gt/gt_rx_3 util_fmcadc5_0_gt/gt_rx_3 -ad_connect axi_fmcadc5_0_gt/gt_rx_4 util_fmcadc5_0_gt/gt_rx_4 -ad_connect axi_fmcadc5_0_gt/gt_rx_5 util_fmcadc5_0_gt/gt_rx_5 -ad_connect axi_fmcadc5_0_gt/gt_rx_6 util_fmcadc5_0_gt/gt_rx_6 -ad_connect axi_fmcadc5_0_gt/gt_rx_7 util_fmcadc5_0_gt/gt_rx_7 -ad_connect axi_fmcadc5_1_gt/gt_rx_0 util_fmcadc5_1_gt/gt_rx_0 -ad_connect axi_fmcadc5_1_gt/gt_rx_1 util_fmcadc5_1_gt/gt_rx_1 -ad_connect axi_fmcadc5_1_gt/gt_rx_2 util_fmcadc5_1_gt/gt_rx_2 -ad_connect axi_fmcadc5_1_gt/gt_rx_3 util_fmcadc5_1_gt/gt_rx_3 -ad_connect axi_fmcadc5_1_gt/gt_rx_4 util_fmcadc5_1_gt/gt_rx_4 -ad_connect axi_fmcadc5_1_gt/gt_rx_5 util_fmcadc5_1_gt/gt_rx_5 -ad_connect axi_fmcadc5_1_gt/gt_rx_6 util_fmcadc5_1_gt/gt_rx_6 -ad_connect axi_fmcadc5_1_gt/gt_rx_7 util_fmcadc5_1_gt/gt_rx_7 -ad_connect axi_fmcadc5_0_gt/gt_rx_ip_0 axi_ad9625_0_jesd/gt0_rx -ad_connect axi_fmcadc5_0_gt/gt_rx_ip_1 axi_ad9625_0_jesd/gt1_rx -ad_connect axi_fmcadc5_0_gt/gt_rx_ip_2 axi_ad9625_0_jesd/gt2_rx -ad_connect axi_fmcadc5_0_gt/gt_rx_ip_3 axi_ad9625_0_jesd/gt3_rx -ad_connect axi_fmcadc5_0_gt/gt_rx_ip_4 axi_ad9625_0_jesd/gt4_rx -ad_connect axi_fmcadc5_0_gt/gt_rx_ip_5 axi_ad9625_0_jesd/gt5_rx -ad_connect axi_fmcadc5_0_gt/gt_rx_ip_6 axi_ad9625_0_jesd/gt6_rx -ad_connect axi_fmcadc5_0_gt/gt_rx_ip_7 axi_ad9625_0_jesd/gt7_rx -ad_connect axi_fmcadc5_1_gt/gt_rx_ip_0 axi_ad9625_1_jesd/gt0_rx -ad_connect axi_fmcadc5_1_gt/gt_rx_ip_1 axi_ad9625_1_jesd/gt1_rx -ad_connect axi_fmcadc5_1_gt/gt_rx_ip_2 axi_ad9625_1_jesd/gt2_rx -ad_connect axi_fmcadc5_1_gt/gt_rx_ip_3 axi_ad9625_1_jesd/gt3_rx -ad_connect axi_fmcadc5_1_gt/gt_rx_ip_4 axi_ad9625_1_jesd/gt4_rx -ad_connect axi_fmcadc5_1_gt/gt_rx_ip_5 axi_ad9625_1_jesd/gt5_rx -ad_connect axi_fmcadc5_1_gt/gt_rx_ip_6 axi_ad9625_1_jesd/gt6_rx -ad_connect axi_fmcadc5_1_gt/gt_rx_ip_7 axi_ad9625_1_jesd/gt7_rx -ad_connect axi_fmcadc5_0_gt/rx_gt_comma_align_enb_0 axi_ad9625_0_jesd/rxencommaalign_out -ad_connect axi_fmcadc5_0_gt/rx_gt_comma_align_enb_1 axi_ad9625_0_jesd/rxencommaalign_out -ad_connect axi_fmcadc5_0_gt/rx_gt_comma_align_enb_2 axi_ad9625_0_jesd/rxencommaalign_out -ad_connect axi_fmcadc5_0_gt/rx_gt_comma_align_enb_3 axi_ad9625_0_jesd/rxencommaalign_out -ad_connect axi_fmcadc5_0_gt/rx_gt_comma_align_enb_4 axi_ad9625_0_jesd/rxencommaalign_out -ad_connect axi_fmcadc5_0_gt/rx_gt_comma_align_enb_5 axi_ad9625_0_jesd/rxencommaalign_out -ad_connect axi_fmcadc5_0_gt/rx_gt_comma_align_enb_6 axi_ad9625_0_jesd/rxencommaalign_out -ad_connect axi_fmcadc5_0_gt/rx_gt_comma_align_enb_7 axi_ad9625_0_jesd/rxencommaalign_out -ad_connect axi_fmcadc5_1_gt/rx_gt_comma_align_enb_0 axi_ad9625_1_jesd/rxencommaalign_out -ad_connect axi_fmcadc5_1_gt/rx_gt_comma_align_enb_1 axi_ad9625_1_jesd/rxencommaalign_out -ad_connect axi_fmcadc5_1_gt/rx_gt_comma_align_enb_2 axi_ad9625_1_jesd/rxencommaalign_out -ad_connect axi_fmcadc5_1_gt/rx_gt_comma_align_enb_3 axi_ad9625_1_jesd/rxencommaalign_out -ad_connect axi_fmcadc5_1_gt/rx_gt_comma_align_enb_4 axi_ad9625_1_jesd/rxencommaalign_out -ad_connect axi_fmcadc5_1_gt/rx_gt_comma_align_enb_5 axi_ad9625_1_jesd/rxencommaalign_out -ad_connect axi_fmcadc5_1_gt/rx_gt_comma_align_enb_6 axi_ad9625_1_jesd/rxencommaalign_out -ad_connect axi_fmcadc5_1_gt/rx_gt_comma_align_enb_7 axi_ad9625_1_jesd/rxencommaalign_out +ad_xcvrpll rx_ref_clk_0 util_fmcadc5_0_xcvr/qpll_ref_clk_* +ad_xcvrpll rx_ref_clk_0 util_fmcadc5_0_xcvr/cpll_ref_clk_* +ad_xcvrpll axi_ad9625_0_xcvr/up_pll_rst util_fmcadc5_0_xcvr/up_qpll_rst_* +ad_xcvrpll axi_ad9625_0_xcvr/up_pll_rst util_fmcadc5_0_xcvr/up_cpll_rst_* +ad_xcvrpll rx_ref_clk_1 util_fmcadc5_1_xcvr/qpll_ref_clk_* +ad_xcvrpll rx_ref_clk_1 util_fmcadc5_1_xcvr/cpll_ref_clk_* +ad_xcvrpll axi_ad9625_1_xcvr/up_pll_rst util_fmcadc5_1_xcvr/up_qpll_rst_* +ad_xcvrpll axi_ad9625_1_xcvr/up_pll_rst util_fmcadc5_1_xcvr/up_cpll_rst_* +ad_connect sys_cpu_resetn util_fmcadc5_0_xcvr/up_rstn +ad_connect sys_cpu_resetn util_fmcadc5_1_xcvr/up_rstn +ad_connect sys_cpu_clk util_fmcadc5_0_xcvr/up_clk +ad_connect sys_cpu_clk util_fmcadc5_1_xcvr/up_clk # connections (adc) -ad_connect util_fmcadc5_0_gt/rx_p rx_data_0_p -ad_connect util_fmcadc5_0_gt/rx_n rx_data_0_n -ad_connect util_fmcadc5_0_gt/rx_sysref GND -ad_connect util_fmcadc5_0_gt/rx_sync rx_sync_0 -ad_connect util_fmcadc5_1_gt/rx_p rx_data_1_p -ad_connect util_fmcadc5_1_gt/rx_n rx_data_1_n -ad_connect util_fmcadc5_1_gt/rx_sysref GND -ad_connect util_fmcadc5_1_gt/rx_sync rx_sync_1 -ad_connect util_fmcadc5_0_gt/rx_ip_sysref rx_sysref -ad_connect util_fmcadc5_0_gt/rx_out_clk rx_clk -ad_connect util_fmcadc5_0_gt/rx_out_clk util_fmcadc5_0_gt/rx_clk -ad_connect util_fmcadc5_0_gt/rx_out_clk axi_ad9625_0_jesd/rx_core_clk -ad_connect util_fmcadc5_0_gt/rx_ip_rst axi_ad9625_0_jesd/rx_reset -ad_connect util_fmcadc5_0_gt/rx_ip_rst_done axi_ad9625_0_jesd/rx_reset_done -ad_connect util_fmcadc5_0_gt/rx_ip_sysref axi_ad9625_0_jesd/rx_sysref -ad_connect util_fmcadc5_0_gt/rx_ip_sync axi_ad9625_0_jesd/rx_sync -ad_connect util_fmcadc5_0_gt/rx_ip_sof axi_ad9625_0_jesd/rx_start_of_frame -ad_connect util_fmcadc5_0_gt/rx_ip_data axi_ad9625_0_jesd/rx_tdata -ad_connect util_fmcadc5_0_gt/rx_out_clk axi_ad9625_0_core/rx_clk -ad_connect util_fmcadc5_0_gt/rx_data axi_ad9625_0_core/rx_data -ad_connect util_fmcadc5_0_gt/rx_out_clk util_fmcadc5_1_gt/rx_clk -ad_connect util_fmcadc5_0_gt/rx_out_clk axi_ad9625_1_jesd/rx_core_clk -ad_connect util_fmcadc5_1_gt/rx_ip_rst axi_ad9625_1_jesd/rx_reset -ad_connect util_fmcadc5_1_gt/rx_ip_rst_done axi_ad9625_1_jesd/rx_reset_done -ad_connect util_fmcadc5_0_gt/rx_ip_sysref axi_ad9625_1_jesd/rx_sysref -ad_connect util_fmcadc5_1_gt/rx_ip_sync axi_ad9625_1_jesd/rx_sync -ad_connect util_fmcadc5_1_gt/rx_ip_sof axi_ad9625_1_jesd/rx_start_of_frame -ad_connect util_fmcadc5_1_gt/rx_ip_data axi_ad9625_1_jesd/rx_tdata -ad_connect util_fmcadc5_0_gt/rx_out_clk axi_ad9625_1_core/rx_clk -ad_connect util_fmcadc5_1_gt/rx_data axi_ad9625_1_core/rx_data -ad_connect util_fmcadc5_0_gt/rx_out_clk axi_fmcadc5_cpack/adc_clk -ad_connect util_fmcadc5_0_gt/rx_rst axi_fmcadc5_cpack/adc_rst +ad_xcvrcon util_fmcadc5_0_xcvr axi_ad9625_0_xcvr axi_ad9625_0_jesd +ad_xcvrcon util_fmcadc5_1_xcvr axi_ad9625_1_xcvr axi_ad9625_1_jesd + +delete_bd_objs [get_bd_cells axi_ad9625_1_jesd_rstgen] + +ad_connect util_fmcadc5_0_xcvr/rx_out_clk_0 axi_ad9625_0_core/rx_clk +ad_connect axi_ad9625_0_jesd/rx_start_of_frame axi_ad9625_0_core/rx_sof +ad_connect axi_ad9625_0_jesd/rx_tdata axi_ad9625_0_core/rx_data +ad_connect util_fmcadc5_0_xcvr/rx_out_clk_0 axi_ad9625_1_core/rx_clk +ad_connect axi_ad9625_0_jesd/rx_start_of_frame axi_ad9625_1_core/rx_sof +ad_connect axi_ad9625_1_jesd/rx_tdata axi_ad9625_1_core/rx_data ad_connect axi_ad9625_0_core/adc_raddr_out axi_ad9625_0_core/adc_raddr_in ad_connect axi_ad9625_0_core/adc_raddr_out axi_ad9625_1_core/adc_raddr_in -ad_connect axi_ad9625_0_core/adc_enable axi_fmcadc5_cpack/adc_enable_0 -ad_connect axi_ad9625_0_core/adc_valid axi_fmcadc5_cpack/adc_valid_0 -ad_connect axi_ad9625_0_core/adc_data axi_fmcadc5_cpack/adc_data_0 -ad_connect axi_ad9625_1_core/adc_enable axi_fmcadc5_cpack/adc_enable_1 -ad_connect axi_ad9625_1_core/adc_valid axi_fmcadc5_cpack/adc_valid_1 -ad_connect axi_ad9625_1_core/adc_data axi_fmcadc5_cpack/adc_data_1 -ad_connect util_fmcadc5_0_gt/rx_out_clk axi_ad9625_fifo/adc_clk -ad_connect util_fmcadc5_0_gt/rx_rst axi_ad9625_fifo/adc_rst -ad_connect axi_fmcadc5_cpack/adc_valid axi_ad9625_fifo/adc_wr -ad_connect axi_fmcadc5_cpack/adc_data axi_ad9625_fifo/adc_wdata -ad_connect axi_ad9625_0_core/adc_dovf axi_ad9625_fifo/adc_wovf +ad_connect util_fmcadc5_0_xcvr/rx_out_clk_0 util_ad9625_cpack/adc_clk +ad_connect axi_ad9625_0_jesd_rstgen/peripheral_reset util_ad9625_cpack/adc_rst +ad_connect axi_ad9625_0_core/adc_enable util_ad9625_cpack/adc_enable_0 +ad_connect axi_ad9625_0_core/adc_valid util_ad9625_cpack/adc_valid_0 +ad_connect axi_ad9625_0_core/adc_data util_ad9625_cpack/adc_data_0 +ad_connect axi_ad9625_1_core/adc_enable util_ad9625_cpack/adc_enable_1 +ad_connect axi_ad9625_1_core/adc_valid util_ad9625_cpack/adc_valid_1 +ad_connect axi_ad9625_1_core/adc_data util_ad9625_cpack/adc_data_1 +ad_connect util_fmcadc5_0_xcvr/rx_out_clk_0 axi_ad9625_fifo/adc_clk +ad_connect axi_ad9625_0_jesd_rstgen/peripheral_reset axi_ad9625_fifo/adc_rst +ad_connect util_ad9625_cpack/adc_valid axi_ad9625_fifo/adc_wr +ad_connect util_ad9625_cpack/adc_data axi_ad9625_fifo/adc_wdata +ad_connect axi_ad9625_fifo/adc_wovf axi_ad9625_0_core/adc_dovf +ad_connect axi_ad9625_fifo/adc_wovf axi_ad9625_1_core/adc_dovf ad_connect sys_cpu_clk axi_ad9625_fifo/dma_clk ad_connect sys_cpu_clk axi_ad9625_dma/s_axis_aclk ad_connect sys_cpu_resetn axi_ad9625_dma/m_dest_axi_aresetn @@ -266,8 +129,8 @@ ad_connect axi_ad9625_fifo/dma_xfer_req axi_ad9625_dma/s_axis_xfer_req # interconnect (cpu) -ad_cpu_interconnect 0x44a60000 axi_fmcadc5_0_gt -ad_cpu_interconnect 0x44b60000 axi_fmcadc5_1_gt +ad_cpu_interconnect 0x44a60000 axi_ad9625_0_xcvr +ad_cpu_interconnect 0x44b60000 axi_ad9625_1_xcvr ad_cpu_interconnect 0x44a10000 axi_ad9625_0_core ad_cpu_interconnect 0x44b10000 axi_ad9625_1_core ad_cpu_interconnect 0x44a91000 axi_ad9625_0_jesd @@ -276,21 +139,23 @@ ad_cpu_interconnect 0x7c420000 axi_ad9625_dma # interconnect (gt/adc) -ad_mem_hp0_interconnect sys_cpu_clk axi_fmcadc5_0_gt/m_axi -ad_mem_hp0_interconnect sys_cpu_clk axi_fmcadc5_1_gt/m_axi +ad_mem_hp0_interconnect sys_cpu_clk axi_ad9625_0_xcvr/m_axi +ad_mem_hp0_interconnect sys_cpu_clk axi_ad9625_1_xcvr/m_axi ad_mem_hp0_interconnect sys_cpu_clk axi_ad9625_dma/m_dest_axi # interrupts -ad_cpu_interrupt ps-13 mb-12 axi_ad9625_dma/irq +ad_cpu_interrupt ps-12 mb-12 axi_ad9625_dma/irq # sync +create_bd_port -dir O rx_clk create_bd_port -dir O up_clk create_bd_port -dir O up_rstn create_bd_port -dir O delay_clk create_bd_port -dir O delay_rst +ad_connect util_fmcadc5_0_xcvr/rx_out_clk_0 rx_clk ad_connect sys_cpu_clk up_clk ad_connect sys_cpu_resetn up_rstn ad_connect sys_200m_clk delay_clk diff --git a/projects/fmcadc5/vc707/Makefile b/projects/fmcadc5/vc707/Makefile index 38905f714..99f2911e2 100644 --- a/projects/fmcadc5/vc707/Makefile +++ b/projects/fmcadc5/vc707/Makefile @@ -15,19 +15,19 @@ M_DEPS += ../common/fmcadc5_bd.tcl M_DEPS += ../../scripts/adi_project.tcl M_DEPS += ../../scripts/adi_env.tcl M_DEPS += ../../scripts/adi_board.tcl -M_DEPS += ../../common/xilinx/sys_dmafifo.tcl +M_DEPS += ../../common/xilinx/sys_adcfifo.tcl M_DEPS += ../../common/vc707/vc707_system_mig.prj M_DEPS += ../../common/vc707/vc707_system_constr.xdc M_DEPS += ../../common/vc707/vc707_system_bd.tcl -M_DEPS += ../../../library/common/ad_lvds_out.v -M_DEPS += ../../../library/common/ad_iobuf.v +M_DEPS += ../../../library/xilinx/common/ad_lvds_out.v +M_DEPS += ../../../library/xilinx/common/ad_iobuf.v +M_DEPS += ../../../library/common/ad_sysref_gen.v M_DEPS += ../../../library/axi_ad9625/axi_ad9625.xpr +M_DEPS += ../../../library/xilinx/axi_adxcvr/axi_adxcvr.xpr M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr -M_DEPS += ../../../library/axi_jesd_gt/axi_jesd_gt.xpr M_DEPS += ../../../library/util_adcfifo/util_adcfifo.xpr +M_DEPS += ../../../library/xilinx/util_adxcvr/util_adxcvr.xpr M_DEPS += ../../../library/util_cpack/util_cpack.xpr -M_DEPS += ../../../library/util_dacfifo/util_dacfifo.xpr -M_DEPS += ../../../library/util_jesd_gt/util_jesd_gt.xpr M_DEPS += ../../../library/util_mfifo/util_mfifo.xpr M_VIVADO := vivado -mode batch -source @@ -44,6 +44,7 @@ M_FLIST += *.sdk M_FLIST += *.hw M_FLIST += *.sim M_FLIST += .Xil +M_FLIST += *.ip_user_files @@ -57,28 +58,26 @@ clean: clean-all:clean make -C ../../../library/axi_ad9625 clean + make -C ../../../library/xilinx/axi_adxcvr clean make -C ../../../library/axi_dmac clean - make -C ../../../library/axi_jesd_gt clean make -C ../../../library/util_adcfifo clean + make -C ../../../library/xilinx/util_adxcvr clean make -C ../../../library/util_cpack clean - make -C ../../../library/util_dacfifo clean - make -C ../../../library/util_jesd_gt clean make -C ../../../library/util_mfifo clean fmcadc5_vc707.sdk/system_top.hdf: $(M_DEPS) - rm -rf $(M_FLIST) + -rm -rf $(M_FLIST) $(M_VIVADO) system_project.tcl >> fmcadc5_vc707_vivado.log 2>&1 lib: make -C ../../../library/axi_ad9625 + make -C ../../../library/xilinx/axi_adxcvr make -C ../../../library/axi_dmac - make -C ../../../library/axi_jesd_gt make -C ../../../library/util_adcfifo + make -C ../../../library/xilinx/util_adxcvr make -C ../../../library/util_cpack - make -C ../../../library/util_dacfifo - make -C ../../../library/util_jesd_gt make -C ../../../library/util_mfifo #################################################################################### diff --git a/projects/fmcadc5/vc707/system_bd.tcl b/projects/fmcadc5/vc707/system_bd.tcl index 6ca32626b..282184189 100644 --- a/projects/fmcadc5/vc707/system_bd.tcl +++ b/projects/fmcadc5/vc707/system_bd.tcl @@ -1,6 +1,6 @@ source $ad_hdl_dir/projects/common/vc707/vc707_system_bd.tcl -source $ad_hdl_dir/projects/common/xilinx/sys_dmafifo.tcl +source $ad_hdl_dir/projects/common/xilinx/sys_adcfifo.tcl source ../common/fmcadc5_bd.tcl # ila @@ -10,7 +10,7 @@ set_property -dict [list CONFIG.NUM_OF_CHANNELS {1}] $mfifo_adc set_property -dict [list CONFIG.DIN_DATA_WIDTH {512}] $mfifo_adc set_property -dict [list CONFIG.ADDRESS_WIDTH {6}] $mfifo_adc -set ila_adc [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.0 ila_adc] +set ila_adc [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.1 ila_adc] set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_adc set_property -dict [list CONFIG.C_TRIGIN_EN {false}] $ila_adc set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila_adc @@ -18,13 +18,13 @@ set_property -dict [list CONFIG.C_NUM_OF_PROBES {2}] $ila_adc set_property -dict [list CONFIG.C_PROBE0_WIDTH {1}] $ila_adc set_property -dict [list CONFIG.C_PROBE1_WIDTH {16}] $ila_adc -ad_connect util_fmcadc5_0_gt/rx_rst mfifo_adc/din_rst -ad_connect util_fmcadc5_0_gt/rx_out_clk mfifo_adc/din_clk -ad_connect axi_fmcadc5_cpack/adc_valid mfifo_adc/din_valid -ad_connect axi_fmcadc5_cpack/adc_data mfifo_adc/din_data_0 -ad_connect util_fmcadc5_0_gt/rx_rst mfifo_adc/dout_rst -ad_connect util_fmcadc5_0_gt/rx_out_clk mfifo_adc/dout_clk -ad_connect util_fmcadc5_0_gt/rx_out_clk ila_adc/clk +ad_connect util_fmcadc5_0_xcvr/rx_out_clk_0 mfifo_adc/din_clk +ad_connect axi_ad9625_0_jesd_rstgen/peripheral_reset mfifo_adc/din_rst +ad_connect util_ad9625_cpack/adc_valid mfifo_adc/din_valid +ad_connect util_ad9625_cpack/adc_data mfifo_adc/din_data_0 +ad_connect axi_ad9625_0_jesd_rstgen/peripheral_reset mfifo_adc/dout_rst +ad_connect util_fmcadc5_0_xcvr/rx_out_clk_0 mfifo_adc/dout_clk +ad_connect util_fmcadc5_0_xcvr/rx_out_clk_0 ila_adc/clk ad_connect mfifo_adc/dout_valid ila_adc/probe0 ad_connect mfifo_adc/dout_data_0 ila_adc/probe1 diff --git a/projects/fmcadc5/vc707/system_constr.xdc b/projects/fmcadc5/vc707/system_constr.xdc index cb7e3c5e7..7bdafaed4 100644 --- a/projects/fmcadc5/vc707/system_constr.xdc +++ b/projects/fmcadc5/vc707/system_constr.xdc @@ -84,6 +84,10 @@ set_property -dict {PACKAGE_PIN P40 IOSTANDARD LVCMOS18} [get_ports psync_1] create_clock -name rx_ref_clk_0 -period 1.60 [get_ports rx_ref_clk_0_p] create_clock -name rx_ref_clk_1 -period 1.60 [get_ports rx_ref_clk_1_p] -create_clock -name rx_div_clk -period 6.40 [get_pins i_system_wrapper/system_i/axi_fmcadc5_0_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK] +create_clock -name rx_div_clk -period 6.40 [get_pins i_system_wrapper/system_i/util_fmcadc5_0_xcvr/inst/i_xch_0/i_gtxe2_channel/RXOUTCLK] +set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9625_0_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]*] + +set_property shreg_extract no [get_cells -hier -filter {name =~ *sysref_en_m*}] +set_false_path -to [get_cells -hier -filter {name =~ *sysref_en_m1* && IS_SEQUENTIAL}] diff --git a/projects/fmcadc5/vc707/system_project.tcl b/projects/fmcadc5/vc707/system_project.tcl index b3c7ab290..fddee061b 100644 --- a/projects/fmcadc5/vc707/system_project.tcl +++ b/projects/fmcadc5/vc707/system_project.tcl @@ -7,16 +7,14 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl adi_project_create fmcadc5_vc707 adi_project_files fmcadc5_vc707 [list \ + "$ad_hdl_dir/projects/common/vc707/vc707_system_constr.xdc" \ + "$ad_hdl_dir/library/xilinx/common/ad_lvds_out.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \ + "$ad_hdl_dir/library/common/ad_sysref_gen.v" \ "../common/fmcadc5_spi.v" \ "../common/fmcadc5_psync.v" \ - "system_top.v" \ "system_constr.xdc"\ - "$ad_hdl_dir/library/common/ad_iobuf.v" \ - "$ad_hdl_dir/library/common/ad_lvds_out.v" \ - "$ad_hdl_dir/projects/common/vc707/vc707_system_constr.xdc" ] - -set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/vc707/vc707_system_constr.xdc] -set_property PROCESSING_ORDER EARLY [get_files system_constr.xdc] + "system_top.v"] adi_project_run fmcadc5_vc707 diff --git a/projects/fmcadc5/vc707/system_top.v b/projects/fmcadc5/vc707/system_top.v index 0173d9e80..0a2d6bcb5 100644 --- a/projects/fmcadc5/vc707/system_top.v +++ b/projects/fmcadc5/vc707/system_top.v @@ -34,202 +34,105 @@ // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // *************************************************************************** // *************************************************************************** -// *************************************************************************** -// *************************************************************************** `timescale 1ns/100ps module system_top ( - sys_rst, - sys_clk_p, - sys_clk_n, + input sys_rst, + input sys_clk_p, + input sys_clk_n, - uart_sin, - uart_sout, + input uart_sin, + output uart_sout, - ddr3_addr, - ddr3_ba, - ddr3_cas_n, - ddr3_ck_n, - ddr3_ck_p, - ddr3_cke, - ddr3_cs_n, - ddr3_dm, - ddr3_dq, - ddr3_dqs_n, - ddr3_dqs_p, - ddr3_odt, - ddr3_ras_n, - ddr3_reset_n, - ddr3_we_n, + output [ 13:0] ddr3_addr, + output [ 2:0] ddr3_ba, + output ddr3_cas_n, + output [ 0:0] ddr3_ck_n, + output [ 0:0] ddr3_ck_p, + output [ 0:0] ddr3_cke, + output [ 0:0] ddr3_cs_n, + output [ 7:0] ddr3_dm, + inout [ 63:0] ddr3_dq, + inout [ 7:0] ddr3_dqs_n, + inout [ 7:0] ddr3_dqs_p, + output [ 0:0] ddr3_odt, + output ddr3_ras_n, + output ddr3_reset_n, + output ddr3_we_n, - sgmii_rxp, - sgmii_rxn, - sgmii_txp, - sgmii_txn, + input sgmii_rxp, + input sgmii_rxn, + output sgmii_txp, + output sgmii_txn, - phy_rstn, - mgt_clk_p, - mgt_clk_n, - mdio_mdc, - mdio_mdio, + output phy_rstn, + input mgt_clk_p, + input mgt_clk_n, + output mdio_mdc, + inout mdio_mdio, - fan_pwm, + output fan_pwm, - linear_flash_addr, - linear_flash_adv_ldn, - linear_flash_ce_n, - linear_flash_oen, - linear_flash_wen, - linear_flash_dq_io, + output [26:1] linear_flash_addr, + output linear_flash_adv_ldn, + output linear_flash_ce_n, + output linear_flash_oen, + output linear_flash_wen, + inout [15:0] linear_flash_dq_io, - gpio_lcd, - gpio_bd, + inout [ 6:0] gpio_lcd, + inout [ 20:0] gpio_bd, - iic_rstn, - iic_scl, - iic_sda, + output iic_rstn, + inout iic_scl, + inout iic_sda, - rx_ref_clk_0_p, - rx_ref_clk_0_n, - rx_data_0_p, - rx_data_0_n, - rx_ref_clk_1_p, - rx_ref_clk_1_n, - rx_data_1_p, - rx_data_1_n, - rx_sysref_p, - rx_sysref_n, - rx_sync_0_p, - rx_sync_0_n, - rx_sync_1_p, - rx_sync_1_n, + input rx_ref_clk_0_p, + input rx_ref_clk_0_n, + input [ 7:0] rx_data_0_p, + input [ 7:0] rx_data_0_n, + input rx_ref_clk_1_p, + input rx_ref_clk_1_n, + input [ 7:0] rx_data_1_p, + input [ 7:0] rx_data_1_n, + output rx_sysref_p, + output rx_sysref_n, + output rx_sync_0_p, + output rx_sync_0_n, + output rx_sync_1_p, + output rx_sync_1_n, - spi_csn_0, - spi_csn_1, - spi_clk, - spi_sdio, - spi_dirn, + output spi_csn_0, + output spi_csn_1, + output spi_clk, + inout spi_sdio, + output spi_dirn, + output dac_clk, + output dac_data, + output dac_sync_0, + output dac_sync_1, - psync_0, - psync_1, - trig_p, - trig_n, - vdither_p, - vdither_n, - pwr_good, - dac_clk, - dac_data, - dac_sync_0, - dac_sync_1, - fd_1, - irq_1, - fd_0, - irq_0, - pwdn_1, - rst_1, - drst_1, - arst_1, - pwdn_0, - rst_0, - drst_0, - arst_0); - - input sys_rst; - input sys_clk_p; - input sys_clk_n; - - input uart_sin; - output uart_sout; - - output [ 13:0] ddr3_addr; - output [ 2:0] ddr3_ba; - output ddr3_cas_n; - output [ 0:0] ddr3_ck_n; - output [ 0:0] ddr3_ck_p; - output [ 0:0] ddr3_cke; - output [ 0:0] ddr3_cs_n; - output [ 7:0] ddr3_dm; - inout [ 63:0] ddr3_dq; - inout [ 7:0] ddr3_dqs_n; - inout [ 7:0] ddr3_dqs_p; - output [ 0:0] ddr3_odt; - output ddr3_ras_n; - output ddr3_reset_n; - output ddr3_we_n; - - input sgmii_rxp; - input sgmii_rxn; - output sgmii_txp; - output sgmii_txn; - - output phy_rstn; - input mgt_clk_p; - input mgt_clk_n; - output mdio_mdc; - inout mdio_mdio; - - output fan_pwm; - - output [26:1] linear_flash_addr; - output linear_flash_adv_ldn; - output linear_flash_ce_n; - output linear_flash_oen; - output linear_flash_wen; - inout [15:0] linear_flash_dq_io; - - inout [ 6:0] gpio_lcd; - inout [ 20:0] gpio_bd; - - output iic_rstn; - inout iic_scl; - inout iic_sda; - - input rx_ref_clk_0_p; - input rx_ref_clk_0_n; - input [ 7:0] rx_data_0_p; - input [ 7:0] rx_data_0_n; - input rx_ref_clk_1_p; - input rx_ref_clk_1_n; - input [ 7:0] rx_data_1_p; - input [ 7:0] rx_data_1_n; - output rx_sysref_p; - output rx_sysref_n; - output rx_sync_0_p; - output rx_sync_0_n; - output rx_sync_1_p; - output rx_sync_1_n; - - output spi_csn_0; - output spi_csn_1; - output spi_clk; - inout spi_sdio; - output spi_dirn; - output dac_clk; - output dac_data; - output dac_sync_0; - output dac_sync_1; - - output psync_0; - output psync_1; - input trig_p; - input trig_n; - output vdither_p; - output vdither_n; - inout pwr_good; - inout fd_1; - inout irq_1; - inout fd_0; - inout irq_0; - inout pwdn_1; - inout rst_1; - output drst_1; - output arst_1; - inout pwdn_0; - inout rst_0; - output drst_0; - output arst_0; + output psync_0, + output psync_1, + input trig_p, + input trig_n, + output vdither_p, + output vdither_n, + inout pwr_good, + inout fd_1, + inout irq_1, + inout fd_0, + inout irq_0, + inout pwdn_1, + inout rst_1, + output drst_1, + output arst_1, + inout pwdn_0, + inout rst_0, + output drst_0, + output arst_0); // internal registers @@ -250,11 +153,11 @@ module system_top ( wire rx_clk; wire rx_ref_clk_0; wire rx_ref_clk_1; - wire rx_sysref_s; wire rx_sync_0; wire rx_sync_1; wire up_rstn; wire up_clk; + wire rx_sysref_int; // spi @@ -287,6 +190,13 @@ module system_top ( end end + // sysref internal + + ad_sysref_gen i_sysref ( + .core_clk (rx_clk), + .sysref_en (gpio_o[32]), + .sysref_out (rx_sysref_int)); + // instantiations ad_lvds_out #( @@ -297,8 +207,8 @@ module system_top ( .IODELAY_GROUP ("FMCADC5_SYSREF_IODELAY_GROUP")) i_rx_sysref ( .tx_clk (rx_clk), - .tx_data_p (rx_sysref_s), - .tx_data_n (rx_sysref_s), + .tx_data_p (rx_sysref_int), + .tx_data_n (rx_sysref_int), .tx_data_out_p (rx_sysref_p), .tx_data_out_n (rx_sysref_n), .up_clk (up_clk), @@ -424,15 +334,44 @@ module system_top ( .phy_rstn (phy_rstn), .phy_sd (1'b1), .rx_clk (rx_clk), - .rx_data_0_n (rx_data_0_n), - .rx_data_0_p (rx_data_0_p), - .rx_data_1_n (rx_data_1_n), - .rx_data_1_p (rx_data_1_p), + .rx_data_0_n (rx_data_0_n[0]), + .rx_data_0_p (rx_data_0_p[0]), + .rx_data_1_0_n (rx_data_1_n[0]), + .rx_data_1_0_p (rx_data_1_p[0]), + .rx_data_1_1_n (rx_data_1_n[1]), + .rx_data_1_1_p (rx_data_1_p[1]), + .rx_data_1_2_n (rx_data_1_n[2]), + .rx_data_1_2_p (rx_data_1_p[2]), + .rx_data_1_3_n (rx_data_1_n[3]), + .rx_data_1_3_p (rx_data_1_p[3]), + .rx_data_1_4_n (rx_data_1_n[4]), + .rx_data_1_4_p (rx_data_1_p[4]), + .rx_data_1_5_n (rx_data_1_n[5]), + .rx_data_1_5_p (rx_data_1_p[5]), + .rx_data_1_6_n (rx_data_1_n[6]), + .rx_data_1_6_p (rx_data_1_p[6]), + .rx_data_1_7_n (rx_data_1_n[7]), + .rx_data_1_7_p (rx_data_1_p[7]), + .rx_data_1_n (rx_data_0_n[1]), + .rx_data_1_p (rx_data_0_p[1]), + .rx_data_2_n (rx_data_0_n[2]), + .rx_data_2_p (rx_data_0_p[2]), + .rx_data_3_n (rx_data_0_n[3]), + .rx_data_3_p (rx_data_0_p[3]), + .rx_data_4_n (rx_data_0_n[4]), + .rx_data_4_p (rx_data_0_p[4]), + .rx_data_5_n (rx_data_0_n[5]), + .rx_data_5_p (rx_data_0_p[5]), + .rx_data_6_n (rx_data_0_n[6]), + .rx_data_6_p (rx_data_0_p[6]), + .rx_data_7_n (rx_data_0_n[7]), + .rx_data_7_p (rx_data_0_p[7]), .rx_ref_clk_0 (rx_ref_clk_0), .rx_ref_clk_1 (rx_ref_clk_1), .rx_sync_0 (rx_sync_0), - .rx_sync_1 (rx_sync_1), - .rx_sysref (rx_sysref_s), + .rx_sync_1_0 (rx_sync_1), + .rx_sysref_0 (rx_sysref_int), + .rx_sysref_1_0 (rx_sysref_int), .sgmii_rxn (sgmii_rxn), .sgmii_rxp (sgmii_rxp), .sgmii_txn (sgmii_txn), diff --git a/projects/fmcjesdadc1/a5gt/Makefile b/projects/fmcjesdadc1/a5gt/Makefile index ef4b1eefb..4b7a52062 100644 --- a/projects/fmcjesdadc1/a5gt/Makefile +++ b/projects/fmcjesdadc1/a5gt/Makefile @@ -5,16 +5,28 @@ #################################################################################### #################################################################################### +ifeq ($(MMU),) + MMU := 1 +endif + +export ALT_NIOS_MMU_ENABLED := $(MMU) + M_DEPS += system_top.v +M_DEPS += system_qsys.tcl M_DEPS += system_project.tcl M_DEPS += system_constr.sdc -M_DEPS += system_bd.qsys M_DEPS += ../common/fmcjesdadc1_spi.v -M_DEPS += ../common/fmcjesdadc1_bd.qsys +M_DEPS += ../common/fmcjesdadc1_qsys.tcl +M_DEPS += ../../scripts/adi_tquest.tcl M_DEPS += ../../scripts/adi_env.tcl -M_DEPS += ../../common/a5gt/a5gt_system_bd.qsys +M_DEPS += ../../common/altera/sys_gen.tcl +M_DEPS += ../../common/a5gt/a5gt_system_qsys.tcl M_DEPS += ../../common/a5gt/a5gt_system_assign.tcl -M_DEPS += ../../../library/common/ad_iobuf.v +M_DEPS += ../../../library/common/ad_sysref_gen.v +M_DEPS += ../../../library/altera/avl_adxcvr/avl_adxcvr_hw.tcl +M_DEPS += ../../../library/altera/axi_adxcvr/axi_adxcvr.v +M_DEPS += ../../../library/altera/axi_adxcvr/axi_adxcvr_hw.tcl +M_DEPS += ../../../library/altera/axi_adxcvr/axi_adxcvr_up.v M_DEPS += ../../../library/axi_ad9250/axi_ad9250.v M_DEPS += ../../../library/axi_ad9250/axi_ad9250_channel.v M_DEPS += ../../../library/axi_ad9250/axi_ad9250_hw.tcl @@ -23,6 +35,7 @@ M_DEPS += ../../../library/axi_ad9250/axi_ad9250_pnmon.v M_DEPS += ../../../library/axi_dmac/2d_transfer.v M_DEPS += ../../../library/axi_dmac/address_generator.v M_DEPS += ../../../library/axi_dmac/axi_dmac.v +M_DEPS += ../../../library/axi_dmac/axi_dmac_constr.sdc M_DEPS += ../../../library/axi_dmac/axi_dmac_hw.tcl M_DEPS += ../../../library/axi_dmac/axi_register_slice.v M_DEPS += ../../../library/axi_dmac/data_mover.v @@ -39,12 +52,11 @@ M_DEPS += ../../../library/axi_dmac/splitter.v M_DEPS += ../../../library/axi_dmac/src_axi_mm.v M_DEPS += ../../../library/axi_dmac/src_axi_stream.v M_DEPS += ../../../library/axi_dmac/src_fifo_inf.v -M_DEPS += ../../../library/axi_jesd_xcvr/axi_jesd_xcvr.v -M_DEPS += ../../../library/axi_jesd_xcvr/axi_jesd_xcvr_hw.tcl +M_DEPS += ../../../library/common/ad_axi_ip_constr.sdc M_DEPS += ../../../library/common/ad_datafmt.v -M_DEPS += ../../../library/common/ad_jesd_align.v M_DEPS += ../../../library/common/ad_pnmon.v M_DEPS += ../../../library/common/ad_rst.v +M_DEPS += ../../../library/common/ad_xcvr_rx_if.v M_DEPS += ../../../library/common/sync_bits.v M_DEPS += ../../../library/common/sync_gray.v M_DEPS += ../../../library/common/up_adc_channel.v @@ -52,16 +64,15 @@ M_DEPS += ../../../library/common/up_adc_common.v M_DEPS += ../../../library/common/up_axi.v M_DEPS += ../../../library/common/up_clock_mon.v M_DEPS += ../../../library/common/up_delay_cntrl.v -M_DEPS += ../../../library/common/up_xcvr.v M_DEPS += ../../../library/common/up_xfer_cntrl.v M_DEPS += ../../../library/common/up_xfer_status.v +M_DEPS += ../../../library/scripts/adi_env.tcl +M_DEPS += ../../../library/scripts/adi_ip_alt.tcl M_DEPS += ../../../library/util_axis_fifo/address_gray.v M_DEPS += ../../../library/util_axis_fifo/address_gray_pipelined.v M_DEPS += ../../../library/util_axis_fifo/address_sync.v M_DEPS += ../../../library/util_axis_fifo/util_axis_fifo.v M_DEPS += ../../../library/util_axis_resize/util_axis_resize.v -M_DEPS += ../../../library/util_bsplit/util_bsplit.v -M_DEPS += ../../../library/util_bsplit/util_bsplit_hw.tcl M_DEPS += ../../../library/util_cpack/util_cpack.v M_DEPS += ../../../library/util_cpack/util_cpack_dsf.v M_DEPS += ../../../library/util_cpack/util_cpack_hw.tcl @@ -98,6 +109,8 @@ M_FLIST += reconfig_mif M_FLIST += *.sopcinfo M_FLIST += *.jdi M_FLIST += *.pin +M_FLIST += *_summary.csv +M_FLIST += *.dpf @@ -114,7 +127,7 @@ clean-all: fmcjesdadc1_a5gt.sof: $(M_DEPS) - rm -rf $(M_FLIST) + -rm -rf $(M_FLIST) $(M_ALTERA) system_project.tcl >> fmcjesdadc1_a5gt_quartus.log 2>&1 #################################################################################### diff --git a/projects/fmcjesdadc1/a5gt/system_bd.qsys b/projects/fmcjesdadc1/a5gt/system_bd.qsys deleted file mode 100644 index 482a3db95..000000000 --- a/projects/fmcjesdadc1/a5gt/system_bd.qsys +++ /dev/null @@ -1,462 +0,0 @@ - - - - - - - - - - - - - - - - - fmcjesdadc1_a5gt.qpf - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ]]> - - - - - - - - - $${FILENAME}_a5gt_base - - - ]]> - - ]]> - - - - - - - - - - - - - - - $${FILENAME}_fmcjesdadc1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/projects/fmcjesdadc1/a5gt/system_constr.sdc b/projects/fmcjesdadc1/a5gt/system_constr.sdc index ce12d1393..d9369ae46 100644 --- a/projects/fmcjesdadc1/a5gt/system_constr.sdc +++ b/projects/fmcjesdadc1/a5gt/system_constr.sdc @@ -1,17 +1,34 @@ -create_clock -period "10.000 ns" -name sys_clk_100mhz [get_ports {sys_clk}] -create_clock -period "4.000 ns" -name ref_clk_250mhz [get_ports {ref_clk}] -create_clock -period "8.000 ns" -name eth_rx_clk_125mhz [get_ports {eth_rx_clk}] +create_clock -period "10.000 ns" -name sys_clk [get_ports {sys_clk}] +create_clock -period "4.000 ns" -name ref_clk [get_ports {ref_clk}] +create_clock -period "8.000 ns" -name eth_rx_clk [get_ports {eth_rx_clk}] derive_pll_clocks derive_clock_uncertainty set_clock_groups -exclusive \ - -group [get_clocks {i_system_bd|a5gt_base|sys_pll|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] \ - -group [get_clocks {i_system_bd|a5gt_base|sys_pll|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] \ - -group [get_clocks {i_system_bd|a5gt_base|sys_pll|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk}] + -group [get_clocks {i_system_bd|sys_pll|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] \ + -group [get_clocks {i_system_bd|sys_pll|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] \ + -group [get_clocks {i_system_bd|sys_pll|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk}] + +set_false_path -to [get_registers *sysref_en_m1*] + +set_false_path -from [get_clocks {i_system_bd|sys_ddr3_cntrl|pll0|pll6~PLL_OUTPUT_COUNTER|divclk}] -through [get_nets *altera_jesd204_rx_ctl_inst*] \ + -to [get_clocks {i_system_bd|avl_ad9250_xcvr|alt_core_pll|altera_pll_i|arriav_pll|counter[0].output_counter|divclk}] + +set_false_path -from [get_clocks {i_system_bd|avl_ad9250_xcvr|alt_core_pll|altera_pll_i|arriav_pll|counter[0].output_counter|divclk}] \ + -through [get_nets *altera_jesd204_rx_ctl_inst*] -to [get_clocks {i_system_bd|sys_ddr3_cntrl|pll0|pll6~PLL_OUTPUT_COUNTER|divclk}] + +set_false_path -from [get_clocks {i_system_bd|sys_ddr3_cntrl|pll0|pll6~PLL_OUTPUT_COUNTER|divclk}] -through [get_nets *altera_jesd204_rx_csr_inst*] \ + -to [get_clocks {i_system_bd|avl_ad9250_xcvr|alt_core_pll|altera_pll_i|arriav_pll|counter[0].output_counter|divclk}] + +set_false_path -from [get_clocks {i_system_bd|avl_ad9250_xcvr|alt_core_pll|altera_pll_i|arriav_pll|counter[0].output_counter|divclk}] \ + -through [get_nets *altera_jesd204_rx_csr_inst*] -to [get_clocks {i_system_bd|sys_ddr3_cntrl|pll0|pll6~PLL_OUTPUT_COUNTER|divclk}] + +if {[string equal "quartus_fit" $::TimeQuestInfo(nameofexecutable)]} { + set_max_delay -from [get_clocks {i_system_bd|sys_ddr3_cntrl|pll0|pll8~PLL_OUTPUT_COUNTER|divclk}] \ + -to [get_clocks {i_system_bd|sys_ddr3_cntrl|pll0|pll4~PLL_OUTPUT_COUNTER|divclk}] 0.150 + set_min_delay -from [get_clocks {i_system_bd|sys_ddr3_cntrl|pll0|pll8~PLL_OUTPUT_COUNTER|divclk}] \ + -to [get_clocks {i_system_bd|sys_ddr3_cntrl|pll0|pll4~PLL_OUTPUT_COUNTER|divclk}] 0.000 +} -set_clock_groups -asynchronous \ - -group {ref_clk_250mhz} \ - -group [get_clocks {i_system_bd|fmcjesdadc1|xcvr_rx_pll|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] \ - -group [get_clocks {i_system_bd|a5gt_base|sys_pll|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] diff --git a/projects/fmcjesdadc1/a5gt/system_project.tcl b/projects/fmcjesdadc1/a5gt/system_project.tcl index d554fce31..7259c58f5 100755 --- a/projects/fmcjesdadc1/a5gt/system_project.tcl +++ b/projects/fmcjesdadc1/a5gt/system_project.tcl @@ -5,13 +5,11 @@ source ../../scripts/adi_env.tcl project_new fmcjesdadc1_a5gt -overwrite source "../../common/a5gt/a5gt_system_assign.tcl" -set_global_assignment -name IP_SEARCH_PATHS "../common/;../../common/**/*;../../../library/**/*" -set_user_option -name USER_IP_SEARCH_PATHS "../common/;../../common/**/*;../../../library/**/*" -set_global_assignment -name QSYS_FILE system_bd.qsys -set_global_assignment -name VERILOG_FILE "../../../library/common/ad_iobuf.v" set_global_assignment -name VERILOG_FILE ../common/fmcjesdadc1_spi.v +set_global_assignment -name VERILOG_FILE ../../../library/common/ad_sysref_gen.v set_global_assignment -name VERILOG_FILE system_top.v +set_global_assignment -name QSYS_FILE system_bd.qsys set_global_assignment -name SDC_FILE system_constr.sdc set_global_assignment -name TOP_LEVEL_ENTITY system_top @@ -63,9 +61,9 @@ set_instance_assignment -name IO_STANDARD "2.5 V" -to spi_sdio # disable auto-pack -set_instance_assignment -name QII_AUTO_PACKED_REGISTERS OFF -to * -entity up_xfer_cntrl -set_instance_assignment -name QII_AUTO_PACKED_REGISTERS OFF -to * -entity up_xfer_status -set_instance_assignment -name QII_AUTO_PACKED_REGISTERS OFF -to * -entity up_xcvr +set_global_assignment -name OPTIMIZATION_MODE "AGGRESSIVE PERFORMANCE" +set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF +set_global_assignment -name QII_AUTO_PACKED_REGISTERS OFF execute_flow -compile diff --git a/projects/fmcjesdadc1/a5gt/system_qsys.tcl b/projects/fmcjesdadc1/a5gt/system_qsys.tcl new file mode 100644 index 000000000..deb2e98ce --- /dev/null +++ b/projects/fmcjesdadc1/a5gt/system_qsys.tcl @@ -0,0 +1,5 @@ + +source $ad_hdl_dir/projects/common/a5gt/a5gt_system_qsys.tcl +source ../common/fmcjesdadc1_qsys.tcl + + diff --git a/projects/fmcjesdadc1/a5gt/system_top.v b/projects/fmcjesdadc1/a5gt/system_top.v index 07a150ddb..f19bf1b10 100644 --- a/projects/fmcjesdadc1/a5gt/system_top.v +++ b/projects/fmcjesdadc1/a5gt/system_top.v @@ -1,9 +1,9 @@ // *************************************************************************** // *************************************************************************** // Copyright 2011(c) Analog Devices, Inc. -// +// // All rights reserved. -// +// // Redistribution and use in source and binary forms, with or without modification, // are permitted provided that the following conditions are met: // - Redistributions of source code must retain the above copyright @@ -21,16 +21,16 @@ // patent holders to use this software. // - Use of the software either in source or binary form, must be run // on or directly connected to an Analog Devices Inc. component. -// +// // THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, // INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A // PARTICULAR PURPOSE ARE DISCLAIMED. // // IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, // EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY -// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR // BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // *************************************************************************** // *************************************************************************** @@ -41,136 +41,89 @@ module system_top ( // clock and resets - sys_clk, - sys_resetn, + input sys_clk, + input sys_resetn, // ddr3 - ddr3_clk_p, - ddr3_clk_n, - ddr3_a, - ddr3_ba, - ddr3_cke, - ddr3_cs_n, - ddr3_odt, - ddr3_reset_n, - ddr3_we_n, - ddr3_ras_n, - ddr3_cas_n, - ddr3_dqs_p, - ddr3_dqs_n, - ddr3_dq, - ddr3_dm, - ddr3_rzq, + output ddr3_clk_p, + output ddr3_clk_n, + output [ 13:0] ddr3_a, + output [ 2:0] ddr3_ba, + output ddr3_cke, + output ddr3_cs_n, + output ddr3_odt, + output ddr3_reset_n, + output ddr3_we_n, + output ddr3_ras_n, + output ddr3_cas_n, + inout [ 7:0] ddr3_dqs_p, + inout [ 7:0] ddr3_dqs_n, + inout [ 63:0] ddr3_dq, + output [ 7:0] ddr3_dm, + input ddr3_rzq, // ethernet - eth_rx_clk, - eth_rx_data, - eth_rx_cntrl, - eth_tx_clk_out, - eth_tx_data, - eth_tx_cntrl, - eth_mdc, - eth_mdio_i, - eth_mdio_o, - eth_mdio_t, - eth_phy_resetn, + input eth_rx_clk, + input [ 3:0] eth_rx_data, + input eth_rx_cntrl, + output eth_tx_clk_out, + output [ 3:0] eth_tx_data, + output eth_tx_cntrl, + output eth_mdc, + input eth_mdio_i, + output eth_mdio_o, + output eth_mdio_t, + output eth_phy_resetn, // board gpio - gpio_bd, + output [ 15:0] gpio_bd_o, + input [ 10:0] gpio_bd_i, // lane interface - ref_clk, - rx_data, - rx_sync, - rx_sysref, + input ref_clk, + input [ 3:0] rx_data, + output rx_sync, + output rx_sysref, // spi - spi_csn, - spi_clk, - spi_sdio); - - // clock and resets - - input sys_clk; - input sys_resetn; - - // ddr3 - - output ddr3_clk_p; - output ddr3_clk_n; - output [ 13:0] ddr3_a; - output [ 2:0] ddr3_ba; - output ddr3_cke; - output ddr3_cs_n; - output ddr3_odt; - output ddr3_reset_n; - output ddr3_we_n; - output ddr3_ras_n; - output ddr3_cas_n; - inout [ 7:0] ddr3_dqs_p; - inout [ 7:0] ddr3_dqs_n; - inout [ 63:0] ddr3_dq; - output [ 7:0] ddr3_dm; - input ddr3_rzq; - - // ethernet - - input eth_rx_clk; - input [ 3:0] eth_rx_data; - input eth_rx_cntrl; - output eth_tx_clk_out; - output [ 3:0] eth_tx_data; - output eth_tx_cntrl; - output eth_mdc; - input eth_mdio_i; - output eth_mdio_o; - output eth_mdio_t; - output eth_phy_resetn; - - // board gpio - - output [ 26:0] gpio_bd; - - // lane interface - - input ref_clk; - input [ 3:0] rx_data; - output rx_sync; - output rx_sysref; - - // spi - - output spi_csn; - output spi_clk; - inout spi_sdio; + output spi_csn, + output spi_clk, + inout spi_sdio); // internal registers reg [ 3:0] phy_rst_cnt = 0; reg phy_rst_reg = 0; - // internal clocks and resets + // internal signals wire sys_125m_clk; wire sys_25m_clk; wire sys_2m5_clk; - wire eth_tx_clk; - wire rx_clk; - - // internal signals - + wire sys_cpu_clk; + wire sys_cpu_mem_resetn; + wire sys_cpu_resetn; wire sys_pll_locked; + wire eth_tx_clk; wire eth_tx_mode_1g; wire eth_tx_mode_10m_100m_n; + wire rx_clk; + wire [ 3:0] rx_ip_sof; + wire [127:0] rx_ip_data; wire spi_mosi; wire spi_miso; wire [ 63:0] gpio_i; wire [ 63:0] gpio_o; + wire [ 7:0] spi_csn_s; + + // sys reset + + assign sys_cpu_resetn = sys_resetn & sys_cpu_mem_resetn & sys_pll_locked; // ethernet transmit clock @@ -186,19 +139,31 @@ module system_top ( end end + // gpio + + assign gpio_i[63:11] = gpio_o[63:11]; + assign gpio_i[10: 0] = gpio_bd_i; + + assign gpio_bd_o = gpio_o[26:11]; + + // sysref + + ad_sysref_gen #(.SYSREF_PERIOD(64)) i_sysref ( + .core_clk (rx_clk), + .sysref_en (gpio_o[32]), + .sysref_out (rx_sysref)); + + // instantiations + + assign spi_csn = spi_csn_s[0]; + fmcjesdadc1_spi i_fmcjesdadc1_spi ( - .spi_csn (spi_csn), + .spi_csn (spi_csn_s[0]), .spi_clk (spi_clk), .spi_mosi (spi_mosi), .spi_miso (spi_miso), .spi_sdio (spi_sdio)); - ad_iobuf #(.DATA_WIDTH(27)) i_iobuf_bd ( - .dio_t ({11'h7ff, 16'h0}), - .dio_i (gpio_o[26:0]), - .dio_o (gpio_i[26:0]), - .dio_p (gpio_bd)); - altddio_out #(.width(1)) i_eth_tx_clk_out ( .aset (1'b0), .sset (1'b0), @@ -213,54 +178,74 @@ module system_top ( .dataout (eth_tx_clk_out)); system_bd i_system_bd ( - .a5gt_base_sys_ddr3_oct_rzqin (ddr3_rzq), - .a5gt_base_sys_ddr3_phy_mem_a (ddr3_a), - .a5gt_base_sys_ddr3_phy_mem_ba (ddr3_ba), - .a5gt_base_sys_ddr3_phy_mem_ck (ddr3_clk_p), - .a5gt_base_sys_ddr3_phy_mem_ck_n (ddr3_clk_n), - .a5gt_base_sys_ddr3_phy_mem_cke (ddr3_cke), - .a5gt_base_sys_ddr3_phy_mem_cs_n (ddr3_cs_n), - .a5gt_base_sys_ddr3_phy_mem_dm (ddr3_dm), - .a5gt_base_sys_ddr3_phy_mem_ras_n (ddr3_ras_n), - .a5gt_base_sys_ddr3_phy_mem_cas_n (ddr3_cas_n), - .a5gt_base_sys_ddr3_phy_mem_we_n (ddr3_we_n), - .a5gt_base_sys_ddr3_phy_mem_reset_n (ddr3_reset_n), - .a5gt_base_sys_ddr3_phy_mem_dq (ddr3_dq), - .a5gt_base_sys_ddr3_phy_mem_dqs (ddr3_dqs_p), - .a5gt_base_sys_ddr3_phy_mem_dqs_n (ddr3_dqs_n), - .a5gt_base_sys_ddr3_phy_mem_odt (ddr3_odt), - .a5gt_base_sys_125m_clk_clk (sys_125m_clk), - .a5gt_base_sys_25m_clk_clk (sys_25m_clk), - .a5gt_base_sys_2m5_clk_clk (sys_2m5_clk), - .a5gt_base_sys_ethernet_mdio_mdc (eth_mdc), - .a5gt_base_sys_ethernet_mdio_mdio_in (eth_mdio_i), - .a5gt_base_sys_ethernet_mdio_mdio_out (eth_mdio_o), - .a5gt_base_sys_ethernet_mdio_mdio_oen (eth_mdio_t), - .a5gt_base_sys_ethernet_rgmii_rgmii_in (eth_rx_data), - .a5gt_base_sys_ethernet_rgmii_rgmii_out (eth_tx_data), - .a5gt_base_sys_ethernet_rgmii_rx_control (eth_rx_cntrl), - .a5gt_base_sys_ethernet_rgmii_tx_control (eth_tx_cntrl), - .a5gt_base_sys_ethernet_rx_clk_clk (eth_rx_clk), - .a5gt_base_sys_ethernet_status_set_10 (), - .a5gt_base_sys_ethernet_status_set_1000 (), - .a5gt_base_sys_ethernet_status_eth_mode (eth_tx_mode_1g), - .a5gt_base_sys_ethernet_status_ena_10 (eth_tx_mode_10m_100m_n), - .a5gt_base_sys_ethernet_tx_clk_clk (eth_tx_clk), - .a5gt_base_sys_gpio_in_port (gpio_i[63:32]), - .a5gt_base_sys_gpio_out_port (gpio_o[63:32]), - .a5gt_base_sys_gpio_bd_in_port (gpio_i[31:0]), - .a5gt_base_sys_gpio_bd_out_port (gpio_o[31:0]), - .a5gt_base_sys_pll_locked_export (sys_pll_locked), - .a5gt_base_sys_spi_MISO (spi_miso), - .a5gt_base_sys_spi_MOSI (spi_mosi), - .a5gt_base_sys_spi_SCLK (spi_clk), - .a5gt_base_sys_spi_SS_n (spi_csn), - .rx_data_rx_serial_data (rx_data), + .rx_core_clk_clk (rx_clk), + .rx_data_0_rx_serial_data (rx_data[0]), + .rx_data_1_rx_serial_data (rx_data[1]), + .rx_data_2_rx_serial_data (rx_data[2]), + .rx_data_3_rx_serial_data (rx_data[3]), + .rx_ip_data_data (rx_ip_data), + .rx_ip_data_valid (), + .rx_ip_data_ready (1'b1), + .rx_ip_data_0_data (rx_ip_data[63:0]), + .rx_ip_data_0_valid (1'b1), + .rx_ip_data_0_ready (), + .rx_ip_data_1_data (rx_ip_data[127:64]), + .rx_ip_data_1_valid (1'b1), + .rx_ip_data_1_ready (), + .rx_ip_sof_export (rx_ip_sof), + .rx_ip_sof_0_export (rx_ip_sof), + .rx_ip_sof_1_export (rx_ip_sof), .rx_ref_clk_clk (ref_clk), - .rx_sync_rx_sync (rx_sync), - .rx_sysref_rx_ext_sysref_out (rx_sysref), - .sys_clk_clk (sys_clk), - .sys_reset_reset_n (sys_resetn)); + .rx_sync_export (rx_sync), + .rx_sysref_export (rx_sysref), + .sys_125m_clk_clk (sys_125m_clk), + .sys_25m_clk_clk (sys_25m_clk), + .sys_2m5_clk_clk (sys_2m5_clk), + .sys_clk_clk (sys_cpu_clk), + .sys_cpu_clk_clk (sys_cpu_clk), + .sys_cpu_reset_reset_n (sys_cpu_mem_resetn), + .sys_ddr3_cntrl_mem_mem_a (ddr3_a), + .sys_ddr3_cntrl_mem_mem_ba (ddr3_ba), + .sys_ddr3_cntrl_mem_mem_ck (ddr3_clk_p), + .sys_ddr3_cntrl_mem_mem_ck_n (ddr3_clk_n), + .sys_ddr3_cntrl_mem_mem_cke (ddr3_cke), + .sys_ddr3_cntrl_mem_mem_cs_n (ddr3_cs_n), + .sys_ddr3_cntrl_mem_mem_dm (ddr3_dm), + .sys_ddr3_cntrl_mem_mem_ras_n (ddr3_ras_n), + .sys_ddr3_cntrl_mem_mem_cas_n (ddr3_cas_n), + .sys_ddr3_cntrl_mem_mem_we_n (ddr3_we_n), + .sys_ddr3_cntrl_mem_mem_reset_n (ddr3_reset_n), + .sys_ddr3_cntrl_mem_mem_dq (ddr3_dq), + .sys_ddr3_cntrl_mem_mem_dqs (ddr3_dqs_p), + .sys_ddr3_cntrl_mem_mem_dqs_n (ddr3_dqs_n), + .sys_ddr3_cntrl_mem_mem_odt (ddr3_odt), + .sys_ddr3_cntrl_oct_rzqin (ddr3_rzq), + .sys_ethernet_mdio_mdc (eth_mdc), + .sys_ethernet_mdio_mdio_in (eth_mdio_i), + .sys_ethernet_mdio_mdio_out (eth_mdio_o), + .sys_ethernet_mdio_mdio_oen (eth_mdio_t), + .sys_ethernet_rgmii_rgmii_in (eth_rx_data), + .sys_ethernet_rgmii_rgmii_out (eth_tx_data), + .sys_ethernet_rgmii_rx_control (eth_rx_cntrl), + .sys_ethernet_rgmii_tx_control (eth_tx_cntrl), + .sys_ethernet_rx_clk_clk (eth_rx_clk), + .sys_ethernet_status_set_10 (), + .sys_ethernet_status_set_1000 (), + .sys_ethernet_status_eth_mode (eth_tx_mode_1g), + .sys_ethernet_status_ena_10 (eth_tx_mode_10m_100m_n), + .sys_ethernet_tx_clk_clk (eth_tx_clk), + .sys_gpio_bd_in_port (gpio_i[31:0]), + .sys_gpio_bd_out_port (gpio_o[31:0]), + .sys_gpio_in_export (gpio_i[63:32]), + .sys_gpio_out_export (gpio_o[63:32]), + .sys_pll_locked_export (sys_pll_locked), + .sys_ref_clk_clk (sys_clk), + .sys_ref_rst_reset_n (sys_resetn), + .sys_rst_reset_n (sys_cpu_resetn), + .sys_spi_MISO (spi_miso), + .sys_spi_MOSI (spi_mosi), + .sys_spi_SCLK (spi_clk), + .sys_spi_SS_n (spi_csn_s)); endmodule diff --git a/projects/fmcjesdadc1/a5soc/Makefile b/projects/fmcjesdadc1/a5soc/Makefile index d40337cda..a66d9d27c 100644 --- a/projects/fmcjesdadc1/a5soc/Makefile +++ b/projects/fmcjesdadc1/a5soc/Makefile @@ -5,16 +5,28 @@ #################################################################################### #################################################################################### +ifeq ($(MMU),) + MMU := 1 +endif + +export ALT_NIOS_MMU_ENABLED := $(MMU) + M_DEPS += system_top.v +M_DEPS += system_qsys.tcl M_DEPS += system_project.tcl M_DEPS += system_constr.sdc -M_DEPS += system_bd.qsys M_DEPS += ../common/fmcjesdadc1_spi.v -M_DEPS += ../common/fmcjesdadc1_bd.qsys +M_DEPS += ../common/fmcjesdadc1_qsys.tcl +M_DEPS += ../../scripts/adi_tquest.tcl M_DEPS += ../../scripts/adi_env.tcl -M_DEPS += ../../common/a5soc/a5soc_system_bd.qsys +M_DEPS += ../../common/altera/sys_gen.tcl +M_DEPS += ../../common/a5soc/a5soc_system_qsys.tcl M_DEPS += ../../common/a5soc/a5soc_system_assign.tcl -M_DEPS += ../../../library/common/ad_iobuf.v +M_DEPS += ../../../library/common/ad_sysref_gen.v +M_DEPS += ../../../library/altera/avl_adxcvr/avl_adxcvr_hw.tcl +M_DEPS += ../../../library/altera/axi_adxcvr/axi_adxcvr.v +M_DEPS += ../../../library/altera/axi_adxcvr/axi_adxcvr_hw.tcl +M_DEPS += ../../../library/altera/axi_adxcvr/axi_adxcvr_up.v M_DEPS += ../../../library/axi_ad9250/axi_ad9250.v M_DEPS += ../../../library/axi_ad9250/axi_ad9250_channel.v M_DEPS += ../../../library/axi_ad9250/axi_ad9250_hw.tcl @@ -23,6 +35,7 @@ M_DEPS += ../../../library/axi_ad9250/axi_ad9250_pnmon.v M_DEPS += ../../../library/axi_dmac/2d_transfer.v M_DEPS += ../../../library/axi_dmac/address_generator.v M_DEPS += ../../../library/axi_dmac/axi_dmac.v +M_DEPS += ../../../library/axi_dmac/axi_dmac_constr.sdc M_DEPS += ../../../library/axi_dmac/axi_dmac_hw.tcl M_DEPS += ../../../library/axi_dmac/axi_register_slice.v M_DEPS += ../../../library/axi_dmac/data_mover.v @@ -39,12 +52,11 @@ M_DEPS += ../../../library/axi_dmac/splitter.v M_DEPS += ../../../library/axi_dmac/src_axi_mm.v M_DEPS += ../../../library/axi_dmac/src_axi_stream.v M_DEPS += ../../../library/axi_dmac/src_fifo_inf.v -M_DEPS += ../../../library/axi_jesd_xcvr/axi_jesd_xcvr.v -M_DEPS += ../../../library/axi_jesd_xcvr/axi_jesd_xcvr_hw.tcl +M_DEPS += ../../../library/common/ad_axi_ip_constr.sdc M_DEPS += ../../../library/common/ad_datafmt.v -M_DEPS += ../../../library/common/ad_jesd_align.v M_DEPS += ../../../library/common/ad_pnmon.v M_DEPS += ../../../library/common/ad_rst.v +M_DEPS += ../../../library/common/ad_xcvr_rx_if.v M_DEPS += ../../../library/common/sync_bits.v M_DEPS += ../../../library/common/sync_gray.v M_DEPS += ../../../library/common/up_adc_channel.v @@ -52,16 +64,15 @@ M_DEPS += ../../../library/common/up_adc_common.v M_DEPS += ../../../library/common/up_axi.v M_DEPS += ../../../library/common/up_clock_mon.v M_DEPS += ../../../library/common/up_delay_cntrl.v -M_DEPS += ../../../library/common/up_xcvr.v M_DEPS += ../../../library/common/up_xfer_cntrl.v M_DEPS += ../../../library/common/up_xfer_status.v +M_DEPS += ../../../library/scripts/adi_env.tcl +M_DEPS += ../../../library/scripts/adi_ip_alt.tcl M_DEPS += ../../../library/util_axis_fifo/address_gray.v M_DEPS += ../../../library/util_axis_fifo/address_gray_pipelined.v M_DEPS += ../../../library/util_axis_fifo/address_sync.v M_DEPS += ../../../library/util_axis_fifo/util_axis_fifo.v M_DEPS += ../../../library/util_axis_resize/util_axis_resize.v -M_DEPS += ../../../library/util_bsplit/util_bsplit.v -M_DEPS += ../../../library/util_bsplit/util_bsplit_hw.tcl M_DEPS += ../../../library/util_cpack/util_cpack.v M_DEPS += ../../../library/util_cpack/util_cpack_dsf.v M_DEPS += ../../../library/util_cpack/util_cpack_hw.tcl @@ -98,6 +109,8 @@ M_FLIST += reconfig_mif M_FLIST += *.sopcinfo M_FLIST += *.jdi M_FLIST += *.pin +M_FLIST += *_summary.csv +M_FLIST += *.dpf @@ -114,7 +127,7 @@ clean-all: fmcjesdadc1_a5soc.sof: $(M_DEPS) - rm -rf $(M_FLIST) + -rm -rf $(M_FLIST) $(M_ALTERA) system_project.tcl >> fmcjesdadc1_a5soc_quartus.log 2>&1 #################################################################################### diff --git a/projects/fmcjesdadc1/a5soc/system_bd.qsys b/projects/fmcjesdadc1/a5soc/system_bd.qsys deleted file mode 100644 index af46dfc16..000000000 --- a/projects/fmcjesdadc1/a5soc/system_bd.qsys +++ /dev/null @@ -1,305 +0,0 @@ - - - - - - - - - - - - - - - - - fmcjesdadc1_a5soc.qpf - - - - - - - - - - - - - - - - - - - - - - - - - ]]> - - - - - - $${FILENAME}_a5soc_base - - - ]]> - - ]]> - - - - - - - - - - - - - - - $${FILENAME}_fmcjesdadc1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/projects/fmcjesdadc1/a5soc/system_constr.sdc b/projects/fmcjesdadc1/a5soc/system_constr.sdc index e01240f42..e2cc1a715 100644 --- a/projects/fmcjesdadc1/a5soc/system_constr.sdc +++ b/projects/fmcjesdadc1/a5soc/system_constr.sdc @@ -1,8 +1,22 @@ -create_clock -period "4.000 ns" -name clk_250m [get_ports {ref_clk}] +create_clock -period "4.000 ns" -name ref_clk [get_ports {ref_clk}] +create_clock -period "20.000 ns" -name sys_cpu_clk [get_pins {i_system_bd|sys_hps|fpga_interfaces|clocks_resets|h2f_user0_clk}] +create_clock -period "10.000 ns" -name sys_dma_clk [get_pins {i_system_bd|sys_hps|fpga_interfaces|clocks_resets|h2f_user1_clk}] derive_pll_clocks derive_clock_uncertainty +set_false_path -to [get_registers *sysref_en_m1*] +set_false_path -from [get_clocks {sys_cpu_clk}] -through [get_nets *altera_jesd204_rx_ctl_inst*]\ + -to [get_clocks {i_system_bd|avl_ad9250_xcvr|alt_core_pll|altera_pll_i|arriav_pll|counter[0].output_counter|divclk}] + +set_false_path -from [get_clocks {i_system_bd|avl_ad9250_xcvr|alt_core_pll|altera_pll_i|arriav_pll|counter[0].output_counter|divclk}]\ + -through [get_nets *altera_jesd204_rx_ctl_inst*] -to [get_clocks {sys_cpu_clk}] + +set_false_path -from [get_clocks {sys_cpu_clk}] -through [get_nets *altera_jesd204_rx_csr_inst*]\ + -to [get_clocks {i_system_bd|avl_ad9250_xcvr|alt_core_pll|altera_pll_i|arriav_pll|counter[0].output_counter|divclk}] + +set_false_path -from [get_clocks {i_system_bd|avl_ad9250_xcvr|alt_core_pll|altera_pll_i|arriav_pll|counter[0].output_counter|divclk}]\ + -through [get_nets *altera_jesd204_rx_csr_inst*] -to [get_clocks {sys_cpu_clk}] diff --git a/projects/fmcjesdadc1/a5soc/system_project.tcl b/projects/fmcjesdadc1/a5soc/system_project.tcl index a94a42fa0..015be89c1 100755 --- a/projects/fmcjesdadc1/a5soc/system_project.tcl +++ b/projects/fmcjesdadc1/a5soc/system_project.tcl @@ -5,13 +5,11 @@ source ../../scripts/adi_env.tcl project_new fmcjesdadc1_a5soc -overwrite source "../../common/a5soc/a5soc_system_assign.tcl" -set_global_assignment -name IP_SEARCH_PATHS "../common/;../../common/a5soc;../../../library/**/*" -set_user_option -name USER_IP_SEARCH_PATHS "../common/;../../common/a5soc/;../../../library/**/*" -set_global_assignment -name QSYS_FILE system_bd.qsys -set_global_assignment -name VERILOG_FILE "../../../library/common/ad_iobuf.v" set_global_assignment -name VERILOG_FILE ../common/fmcjesdadc1_spi.v +set_global_assignment -name VERILOG_FILE ../../../library/common/ad_sysref_gen.v set_global_assignment -name VERILOG_FILE system_top.v +set_global_assignment -name QSYS_FILE system_bd.qsys set_global_assignment -name SDC_FILE system_constr.sdc set_global_assignment -name TOP_LEVEL_ENTITY system_top @@ -63,9 +61,8 @@ set_instance_assignment -name IO_STANDARD "2.5 V" -to spi_sdio # disable auto-pack -set_instance_assignment -name QII_AUTO_PACKED_REGISTERS OFF -to * -entity up_xfer_cntrl -set_instance_assignment -name QII_AUTO_PACKED_REGISTERS OFF -to * -entity up_xfer_status -set_instance_assignment -name QII_AUTO_PACKED_REGISTERS OFF -to * -entity up_xcvr +set_instance_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -to * -entity ad_sysref_gen +set_instance_assignment -name QII_AUTO_PACKED_REGISTERS OFF -to * -entity ad_sysref_gen execute_flow -compile diff --git a/projects/fmcjesdadc1/a5soc/system_qsys.tcl b/projects/fmcjesdadc1/a5soc/system_qsys.tcl new file mode 100644 index 000000000..bcc3f2550 --- /dev/null +++ b/projects/fmcjesdadc1/a5soc/system_qsys.tcl @@ -0,0 +1,5 @@ + +source $ad_hdl_dir/projects/common/a5soc/a5soc_system_qsys.tcl +source ../common/fmcjesdadc1_qsys.tcl + + diff --git a/projects/fmcjesdadc1/a5soc/system_top.v b/projects/fmcjesdadc1/a5soc/system_top.v index 161b9c694..2520c8e36 100644 --- a/projects/fmcjesdadc1/a5soc/system_top.v +++ b/projects/fmcjesdadc1/a5soc/system_top.v @@ -1,9 +1,9 @@ // *************************************************************************** // *************************************************************************** // Copyright 2011(c) Analog Devices, Inc. -// +// // All rights reserved. -// +// // Redistribution and use in source and binary forms, with or without modification, // are permitted provided that the following conditions are met: // - Redistributions of source code must retain the above copyright @@ -21,16 +21,16 @@ // patent holders to use this software. // - Use of the software either in source or binary form, must be run // on or directly connected to an Analog Devices Inc. component. -// +// // THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, // INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A // PARTICULAR PURPOSE ARE DISCLAIMED. // // IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, // EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY -// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR // BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // *************************************************************************** // *************************************************************************** @@ -41,179 +41,119 @@ module system_top ( // hps - ddr3_a, - ddr3_ba, - ddr3_ck_p, - ddr3_ck_n, - ddr3_cke, - ddr3_cs_n, - ddr3_ras_n, - ddr3_cas_n, - ddr3_we_n, - ddr3_reset_n, - ddr3_dq, - ddr3_dqs_p, - ddr3_dqs_n, - ddr3_odt, - ddr3_dm, - ddr3_oct_rzqin, - eth1_tx_clk, - eth1_tx_ctl, - eth1_txd0, - eth1_txd1, - eth1_txd2, - eth1_txd3, - eth1_rx_clk, - eth1_rx_ctl, - eth1_rxd0, - eth1_rxd1, - eth1_rxd2, - eth1_rxd3, - eth1_mdc, - eth1_mdio, - qspi_ss0, - qspi_clk, - qspi_io0, - qspi_io1, - qspi_io2, - qspi_io3, - sdio_clk, - sdio_cmd, - sdio_d0, - sdio_d1, - sdio_d2, - sdio_d3, - usb1_clk, - usb1_stp, - usb1_dir, - usb1_nxt, - usb1_d0, - usb1_d1, - usb1_d2, - usb1_d3, - usb1_d4, - usb1_d5, - usb1_d6, - usb1_d7, - uart0_rx, - uart0_tx, + output [ 14:0] ddr3_a, + output [ 2:0] ddr3_ba, + output ddr3_ck_p, + output ddr3_ck_n, + output ddr3_cke, + output ddr3_cs_n, + output ddr3_ras_n, + output ddr3_cas_n, + output ddr3_we_n, + output ddr3_reset_n, + inout [ 39:0] ddr3_dq, + inout [ 4:0] ddr3_dqs_p, + inout [ 4:0] ddr3_dqs_n, + output ddr3_odt, + output [ 4:0] ddr3_dm, + input ddr3_oct_rzqin, + output eth1_tx_clk, + output eth1_tx_ctl, + output eth1_txd0, + output eth1_txd1, + output eth1_txd2, + output eth1_txd3, + input eth1_rx_clk, + input eth1_rx_ctl, + input eth1_rxd0, + input eth1_rxd1, + input eth1_rxd2, + input eth1_rxd3, + output eth1_mdc, + inout eth1_mdio, + output qspi_ss0, + output qspi_clk, + inout qspi_io0, + inout qspi_io1, + inout qspi_io2, + inout qspi_io3, + output sdio_clk, + inout sdio_cmd, + inout sdio_d0, + inout sdio_d1, + inout sdio_d2, + inout sdio_d3, + input usb1_clk, + output usb1_stp, + input usb1_dir, + input usb1_nxt, + inout usb1_d0, + inout usb1_d1, + inout usb1_d2, + inout usb1_d3, + inout usb1_d4, + inout usb1_d5, + inout usb1_d6, + inout usb1_d7, + input uart0_rx, + output uart0_tx, // board gpio - gpio_bd, + output [ 3:0] gpio_bd_o, + input [ 7:0] gpio_bd_i, // i2c - fmc_a_scl, - fmc_a_sda, + inout fmca_scl, + inout fmca_sda, // lane interface - ref_clk, - rx_data, - rx_sync, - rx_sysref, + input ref_clk, + input [ 3:0] rx_data, + output rx_sync, + output rx_sysref, // spi - spi_csn, - spi_clk, - spi_sdio); - - // hps - - output [ 14:0] ddr3_a; - output [ 2:0] ddr3_ba; - output ddr3_ck_p; - output ddr3_ck_n; - output ddr3_cke; - output ddr3_cs_n; - output ddr3_ras_n; - output ddr3_cas_n; - output ddr3_we_n; - output ddr3_reset_n; - inout [ 39:0] ddr3_dq; - inout [ 4:0] ddr3_dqs_p; - inout [ 4:0] ddr3_dqs_n; - output ddr3_odt; - output [ 4:0] ddr3_dm; - input ddr3_oct_rzqin; - output eth1_tx_clk; - output eth1_tx_ctl; - output eth1_txd0; - output eth1_txd1; - output eth1_txd2; - output eth1_txd3; - input eth1_rx_clk; - input eth1_rx_ctl; - input eth1_rxd0; - input eth1_rxd1; - input eth1_rxd2; - input eth1_rxd3; - output eth1_mdc; - inout eth1_mdio; - output qspi_ss0; - output qspi_clk; - inout qspi_io0; - inout qspi_io1; - inout qspi_io2; - inout qspi_io3; - output sdio_clk; - inout sdio_cmd; - inout sdio_d0; - inout sdio_d1; - inout sdio_d2; - inout sdio_d3; - input usb1_clk; - output usb1_stp; - input usb1_dir; - input usb1_nxt; - inout usb1_d0; - inout usb1_d1; - inout usb1_d2; - inout usb1_d3; - inout usb1_d4; - inout usb1_d5; - inout usb1_d6; - inout usb1_d7; - input uart0_rx; - output uart0_tx; - - // board gpio - - inout [ 11:0] gpio_bd; - - // i2c - - inout fmc_a_scl; - inout fmc_a_sda; - - // lane interface - - input ref_clk; - input [ 3:0] rx_data; - output rx_sync; - output rx_sysref; - - // spi - - output spi_csn; - output spi_clk; - inout spi_sdio; + output spi_csn, + output spi_clk, + inout spi_sdio); // internal signals + wire sys_cpu_clk; + wire sys_dma_clk; + wire sys_rstn; + wire rx_clk; + wire [ 3:0] rx_ip_sof; + wire [127:0] rx_ip_data; wire [ 63:0] gpio_i; wire [ 63:0] gpio_o; wire spi_mosi; wire spi_miso; - wire fmc_a_scl_oe; - wire fmc_a_sda_oe; + wire fmca_scl_oe; + wire fmca_sda_oe; // i2c - assign fmc_a_scl = (fmc_a_scl_oe == 1'b1) ? 1'b0 : 1'bz; - assign fmc_a_sda = (fmc_a_sda_oe == 1'b1) ? 1'b0 : 1'bz; + assign fmca_scl = (fmca_scl_oe == 1'b1) ? 1'b0 : 1'bz; + assign fmca_sda = (fmca_sda_oe == 1'b1) ? 1'b0 : 1'bz; + + // gpio + + assign gpio_i[63: 8] = gpio_o[63:8]; + assign gpio_i[ 7: 0] = gpio_bd_i; + + assign gpio_bd_o = gpio_o[11:8]; + + // sysref + + ad_sysref_gen #(.SYSREF_PERIOD(64)) i_sysref ( + .core_clk (rx_clk), + .sysref_en (gpio_o[32]), + .sysref_out (rx_sysref)); // instantiations @@ -224,90 +164,107 @@ module system_top ( .spi_miso (spi_miso), .spi_sdio (spi_sdio)); - ad_iobuf #(.DATA_WIDTH(12)) i_iobuf_bd ( - .dio_t ({8'hff, 4'h0}), - .dio_i (gpio_o[11:0]), - .dio_o (gpio_i[11:0]), - .dio_p (gpio_bd)); - system_bd i_system_bd ( - .a5soc_base_sys_gpio_bd_external_connection_in_port (gpio_i[63:32]), - .a5soc_base_sys_gpio_bd_external_connection_out_port (gpio_o[63:32]), - .a5soc_base_sys_gpio_external_connection_in_port (gpio_i[31:0]), - .a5soc_base_sys_gpio_external_connection_out_port (gpio_o[31:0]), - .a5soc_base_sys_hps_i2c0_out_data (fmc_a_sda_oe), - .a5soc_base_sys_hps_i2c0_sda (fmc_a_sda), - .a5soc_base_sys_hps_i2c0_clk_clk (fmc_a_scl_oe), - .a5soc_base_sys_hps_i2c0_scl_in_clk (fmc_a_scl), - .a5soc_base_sys_hps_io_hps_io_emac1_inst_TX_CLK (eth1_tx_clk), - .a5soc_base_sys_hps_io_hps_io_emac1_inst_TXD0 (eth1_txd0), - .a5soc_base_sys_hps_io_hps_io_emac1_inst_TXD1 (eth1_txd1), - .a5soc_base_sys_hps_io_hps_io_emac1_inst_TX_CTL (eth1_tx_ctl), - .a5soc_base_sys_hps_io_hps_io_emac1_inst_RXD0 (eth1_rxd0), - .a5soc_base_sys_hps_io_hps_io_emac1_inst_RXD1 (eth1_rxd1), - .a5soc_base_sys_hps_io_hps_io_emac1_inst_TXD2 (eth1_txd2), - .a5soc_base_sys_hps_io_hps_io_emac1_inst_TXD3 (eth1_txd3), - .a5soc_base_sys_hps_io_hps_io_emac1_inst_MDIO (eth1_mdio), - .a5soc_base_sys_hps_io_hps_io_emac1_inst_MDC (eth1_mdc), - .a5soc_base_sys_hps_io_hps_io_emac1_inst_RX_CTL (eth1_rx_ctl), - .a5soc_base_sys_hps_io_hps_io_emac1_inst_RX_CLK (eth1_rx_clk), - .a5soc_base_sys_hps_io_hps_io_emac1_inst_RXD2 (eth1_rxd2), - .a5soc_base_sys_hps_io_hps_io_emac1_inst_RXD3 (eth1_rxd3), - .a5soc_base_sys_hps_io_hps_io_qspi_inst_IO0 (qspi_io0), - .a5soc_base_sys_hps_io_hps_io_qspi_inst_IO1 (qspi_io1), - .a5soc_base_sys_hps_io_hps_io_qspi_inst_IO2 (qspi_io2), - .a5soc_base_sys_hps_io_hps_io_qspi_inst_IO3 (qspi_io3), - .a5soc_base_sys_hps_io_hps_io_qspi_inst_SS0 (qspi_ss0), - .a5soc_base_sys_hps_io_hps_io_qspi_inst_CLK (qspi_clk), - .a5soc_base_sys_hps_io_hps_io_sdio_inst_CMD (sdio_cmd), - .a5soc_base_sys_hps_io_hps_io_sdio_inst_D0 (sdio_d0), - .a5soc_base_sys_hps_io_hps_io_sdio_inst_D1 (sdio_d1), - .a5soc_base_sys_hps_io_hps_io_sdio_inst_CLK (sdio_clk), - .a5soc_base_sys_hps_io_hps_io_sdio_inst_D2 (sdio_d2), - .a5soc_base_sys_hps_io_hps_io_sdio_inst_D3 (sdio_d3), - .a5soc_base_sys_hps_io_hps_io_usb1_inst_D0 (usb1_d0), - .a5soc_base_sys_hps_io_hps_io_usb1_inst_D1 (usb1_d1), - .a5soc_base_sys_hps_io_hps_io_usb1_inst_D2 (usb1_d2), - .a5soc_base_sys_hps_io_hps_io_usb1_inst_D3 (usb1_d3), - .a5soc_base_sys_hps_io_hps_io_usb1_inst_D4 (usb1_d4), - .a5soc_base_sys_hps_io_hps_io_usb1_inst_D5 (usb1_d5), - .a5soc_base_sys_hps_io_hps_io_usb1_inst_D6 (usb1_d6), - .a5soc_base_sys_hps_io_hps_io_usb1_inst_D7 (usb1_d7), - .a5soc_base_sys_hps_io_hps_io_usb1_inst_CLK (usb1_clk), - .a5soc_base_sys_hps_io_hps_io_usb1_inst_STP (usb1_stp), - .a5soc_base_sys_hps_io_hps_io_usb1_inst_DIR (usb1_dir), - .a5soc_base_sys_hps_io_hps_io_usb1_inst_NXT (usb1_nxt), - .a5soc_base_sys_hps_io_hps_io_uart0_inst_RX (uart0_rx), - .a5soc_base_sys_hps_io_hps_io_uart0_inst_TX (uart0_tx), - .a5soc_base_sys_hps_memory_mem_a (ddr3_a), - .a5soc_base_sys_hps_memory_mem_ba (ddr3_ba), - .a5soc_base_sys_hps_memory_mem_ck (ddr3_ck_p), - .a5soc_base_sys_hps_memory_mem_ck_n (ddr3_ck_n), - .a5soc_base_sys_hps_memory_mem_cke (ddr3_cke), - .a5soc_base_sys_hps_memory_mem_cs_n (ddr3_cs_n), - .a5soc_base_sys_hps_memory_mem_ras_n (ddr3_ras_n), - .a5soc_base_sys_hps_memory_mem_cas_n (ddr3_cas_n), - .a5soc_base_sys_hps_memory_mem_we_n (ddr3_we_n), - .a5soc_base_sys_hps_memory_mem_reset_n (ddr3_reset_n), - .a5soc_base_sys_hps_memory_mem_dq (ddr3_dq), - .a5soc_base_sys_hps_memory_mem_dqs (ddr3_dqs_p), - .a5soc_base_sys_hps_memory_mem_dqs_n (ddr3_dqs_n), - .a5soc_base_sys_hps_memory_mem_odt (ddr3_odt), - .a5soc_base_sys_hps_memory_mem_dm (ddr3_dm), - .a5soc_base_sys_hps_memory_oct_rzqin (ddr3_oct_rzqin), - .a5soc_base_sys_hps_spim0_txd (spi_mosi), - .a5soc_base_sys_hps_spim0_rxd (spi_miso), - .a5soc_base_sys_hps_spim0_ss_in_n (1'b1), - .a5soc_base_sys_hps_spim0_ssi_oe_n (spi_csn), - .a5soc_base_sys_hps_spim0_ss_0_n (), - .a5soc_base_sys_hps_spim0_ss_1_n (), - .a5soc_base_sys_hps_spim0_ss_2_n (), - .a5soc_base_sys_hps_spim0_ss_3_n (), - .a5soc_base_sys_hps_spim0_sclk_out_clk (spi_clk), - .fmcjesdadc1_rx_data_rx_serial_data (rx_data), - .fmcjesdadc1_rx_ref_clk_clk (ref_clk), - .fmcjesdadc1_rx_sync_rx_sync (rx_sync), - .fmcjesdadc1_rx_sysref_rx_ext_sysref_out (rx_sysref)); + .rx_core_clk_clk (rx_clk), + .rx_data_0_rx_serial_data (rx_data[0]), + .rx_data_1_rx_serial_data (rx_data[1]), + .rx_data_2_rx_serial_data (rx_data[2]), + .rx_data_3_rx_serial_data (rx_data[3]), + .rx_ip_data_data (rx_ip_data), + .rx_ip_data_valid (), + .rx_ip_data_ready (1'b1), + .rx_ip_data_0_data (rx_ip_data[63:0]), + .rx_ip_data_0_valid (1'b1), + .rx_ip_data_0_ready (), + .rx_ip_data_1_data (rx_ip_data[127:64]), + .rx_ip_data_1_valid (1'b1), + .rx_ip_data_1_ready (), + .rx_ip_sof_export (rx_ip_sof), + .rx_ip_sof_0_export (rx_ip_sof), + .rx_ip_sof_1_export (rx_ip_sof), + .rx_ref_clk_clk (ref_clk), + .rx_sync_export (rx_sync), + .rx_sysref_export (rx_sysref), + .sys_clk_clk (sys_cpu_clk), + .sys_dma_clk_clk (sys_dma_clk), + .sys_dma_rst_reset_n (sys_rstn), + .sys_gpio_bd_in_port (gpio_i[31:0]), + .sys_gpio_bd_out_port (gpio_o[31:0]), + .sys_gpio_in_export (gpio_i[63:32]), + .sys_gpio_out_export (gpio_o[63:32]), + .sys_hps_cpu_clk_clk (sys_cpu_clk), + .sys_hps_ddr3_mem_a (ddr3_a), + .sys_hps_ddr3_mem_ba (ddr3_ba), + .sys_hps_ddr3_mem_ck (ddr3_ck_p), + .sys_hps_ddr3_mem_ck_n (ddr3_ck_n), + .sys_hps_ddr3_mem_cke (ddr3_cke), + .sys_hps_ddr3_mem_cs_n (ddr3_cs_n), + .sys_hps_ddr3_mem_ras_n (ddr3_ras_n), + .sys_hps_ddr3_mem_cas_n (ddr3_cas_n), + .sys_hps_ddr3_mem_we_n (ddr3_we_n), + .sys_hps_ddr3_mem_reset_n (ddr3_reset_n), + .sys_hps_ddr3_mem_dq (ddr3_dq), + .sys_hps_ddr3_mem_dqs (ddr3_dqs_p), + .sys_hps_ddr3_mem_dqs_n (ddr3_dqs_n), + .sys_hps_ddr3_mem_odt (ddr3_odt), + .sys_hps_ddr3_mem_dm (ddr3_dm), + .sys_hps_ddr3_oct_rzqin (ddr3_oct_rzqin), + .sys_hps_dma_clk_clk (sys_dma_clk), + .sys_hps_i2c0_out_data (fmca_sda_oe), + .sys_hps_i2c0_sda (fmca_sda), + .sys_hps_i2c0_clk_clk (fmca_scl_oe), + .sys_hps_i2c0_scl_clk (fmca_scl), + .sys_hps_io_hps_io_emac1_inst_TX_CLK (eth1_tx_clk), + .sys_hps_io_hps_io_emac1_inst_TXD0 (eth1_txd0), + .sys_hps_io_hps_io_emac1_inst_TXD1 (eth1_txd1), + .sys_hps_io_hps_io_emac1_inst_TX_CTL (eth1_tx_ctl), + .sys_hps_io_hps_io_emac1_inst_RXD0 (eth1_rxd0), + .sys_hps_io_hps_io_emac1_inst_RXD1 (eth1_rxd1), + .sys_hps_io_hps_io_emac1_inst_TXD2 (eth1_txd2), + .sys_hps_io_hps_io_emac1_inst_TXD3 (eth1_txd3), + .sys_hps_io_hps_io_emac1_inst_MDIO (eth1_mdio), + .sys_hps_io_hps_io_emac1_inst_MDC (eth1_mdc), + .sys_hps_io_hps_io_emac1_inst_RX_CTL (eth1_rx_ctl), + .sys_hps_io_hps_io_emac1_inst_RX_CLK (eth1_rx_clk), + .sys_hps_io_hps_io_emac1_inst_RXD2 (eth1_rxd2), + .sys_hps_io_hps_io_emac1_inst_RXD3 (eth1_rxd3), + .sys_hps_io_hps_io_qspi_inst_IO0 (qspi_io0), + .sys_hps_io_hps_io_qspi_inst_IO1 (qspi_io1), + .sys_hps_io_hps_io_qspi_inst_IO2 (qspi_io2), + .sys_hps_io_hps_io_qspi_inst_IO3 (qspi_io3), + .sys_hps_io_hps_io_qspi_inst_SS0 (qspi_ss0), + .sys_hps_io_hps_io_qspi_inst_CLK (qspi_clk), + .sys_hps_io_hps_io_sdio_inst_CMD (sdio_cmd), + .sys_hps_io_hps_io_sdio_inst_D0 (sdio_d0), + .sys_hps_io_hps_io_sdio_inst_D1 (sdio_d1), + .sys_hps_io_hps_io_sdio_inst_CLK (sdio_clk), + .sys_hps_io_hps_io_sdio_inst_D2 (sdio_d2), + .sys_hps_io_hps_io_sdio_inst_D3 (sdio_d3), + .sys_hps_io_hps_io_usb1_inst_D0 (usb1_d0), + .sys_hps_io_hps_io_usb1_inst_D1 (usb1_d1), + .sys_hps_io_hps_io_usb1_inst_D2 (usb1_d2), + .sys_hps_io_hps_io_usb1_inst_D3 (usb1_d3), + .sys_hps_io_hps_io_usb1_inst_D4 (usb1_d4), + .sys_hps_io_hps_io_usb1_inst_D5 (usb1_d5), + .sys_hps_io_hps_io_usb1_inst_D6 (usb1_d6), + .sys_hps_io_hps_io_usb1_inst_D7 (usb1_d7), + .sys_hps_io_hps_io_usb1_inst_CLK (usb1_clk), + .sys_hps_io_hps_io_usb1_inst_STP (usb1_stp), + .sys_hps_io_hps_io_usb1_inst_DIR (usb1_dir), + .sys_hps_io_hps_io_usb1_inst_NXT (usb1_nxt), + .sys_hps_io_hps_io_uart0_inst_RX (uart0_rx), + .sys_hps_io_hps_io_uart0_inst_TX (uart0_tx), + .sys_hps_rstn_reset_n (sys_rstn), + .sys_hps_spim0_txd (spi_mosi), + .sys_hps_spim0_rxd (spi_miso), + .sys_hps_spim0_ss_in_n (1'b1), + .sys_hps_spim0_ssi_oe_n (spi_csn), + .sys_hps_spim0_ss_0_n (), + .sys_hps_spim0_ss_1_n (), + .sys_hps_spim0_ss_2_n (), + .sys_hps_spim0_ss_3_n (), + .sys_hps_spim0_sclk_clk (spi_clk), + .sys_rst_reset_n (sys_rstn)); endmodule diff --git a/projects/fmcjesdadc1/common/fmcjesdadc1_bd.qsys b/projects/fmcjesdadc1/common/fmcjesdadc1_bd.qsys deleted file mode 100644 index 780a3c68b..000000000 --- a/projects/fmcjesdadc1/common/fmcjesdadc1_bd.qsys +++ /dev/null @@ -1,1284 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Create an adjpllin signal to connect with an upstream PLL - - - - - - - - - - - - - - - - - - - - - - - - Automatic Switchover - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/projects/fmcjesdadc1/common/fmcjesdadc1_bd.tcl b/projects/fmcjesdadc1/common/fmcjesdadc1_bd.tcl index 098001461..e9321934a 100644 --- a/projects/fmcjesdadc1/common/fmcjesdadc1_bd.tcl +++ b/projects/fmcjesdadc1/common/fmcjesdadc1_bd.tcl @@ -1,63 +1,29 @@ -# ad9250 - -create_bd_port -dir I rx_ref_clk -create_bd_port -dir O rx_sync -create_bd_port -dir O rx_sysref -create_bd_port -dir I -from 3 -to 0 rx_data_p -create_bd_port -dir I -from 3 -to 0 rx_data_n - # adc peripherals +set axi_ad9250_xcvr [create_bd_cell -type ip -vlnv analog.com:user:axi_adxcvr:1.0 axi_ad9250_xcvr] +set_property -dict [list CONFIG.NUM_OF_LANES {4}] $axi_ad9250_xcvr +set_property -dict [list CONFIG.QPLL_ENABLE {0}] $axi_ad9250_xcvr +set_property -dict [list CONFIG.TX_OR_RX_N {0}] $axi_ad9250_xcvr +set_property -dict [list CONFIG.LPM_OR_DFE_N {0}] $axi_ad9250_xcvr +set_property -dict [list CONFIG.OUT_CLK_SEL {"010"}] $axi_ad9250_xcvr +set_property -dict [list CONFIG.SYS_CLK_SEL {"00"}] $axi_ad9250_xcvr + +set axi_ad9250_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:7.0 axi_ad9250_jesd] +set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9250_jesd +set_property -dict [list CONFIG.C_LANES {4}] $axi_ad9250_jesd + +set data_bsplit [create_bd_cell -type ip -vlnv analog.com:user:util_bsplit:1.0 data_bsplit] +set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {64} ] $data_bsplit +set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $data_bsplit + set axi_ad9250_0_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9250:1.0 axi_ad9250_0_core] set axi_ad9250_1_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9250:1.0 axi_ad9250_1_core] -set axi_ad9250_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.2 axi_ad9250_jesd] -set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9250_jesd -set_property -dict [list CONFIG.C_LANES {4}] $axi_ad9250_jesd - -set axi_ad9250_gt [create_bd_cell -type ip -vlnv analog.com:user:axi_jesd_gt:1.0 axi_ad9250_gt] -set_property -dict [list CONFIG.NUM_OF_LANES {4}] $axi_ad9250_gt -set_property -dict [list CONFIG.QPLL0_ENABLE {0}] $axi_ad9250_gt -set_property -dict [list CONFIG.QPLL1_ENABLE {0}] $axi_ad9250_gt -set_property -dict [list CONFIG.RX_NUM_OF_LANES {4}] $axi_ad9250_gt -set_property -dict [list CONFIG.TX_NUM_OF_LANES {0}] $axi_ad9250_gt -set_property -dict [list CONFIG.CPLL_FBDIV_0 {2}] $axi_ad9250_gt -set_property -dict [list CONFIG.RX_OUT_DIV_0 {1}] $axi_ad9250_gt -set_property -dict [list CONFIG.TX_OUT_DIV_0 {1}] $axi_ad9250_gt -set_property -dict [list CONFIG.RX_CLK25_DIV_0 {10}] $axi_ad9250_gt -set_property -dict [list CONFIG.TX_CLK25_DIV_0 {10}] $axi_ad9250_gt -set_property -dict [list CONFIG.PMA_RSV_0 {0x00018480}] $axi_ad9250_gt -set_property -dict [list CONFIG.RX_CDR_CFG_0 {0x03000023ff20400020}] $axi_ad9250_gt -set_property -dict [list CONFIG.CPLL_FBDIV_1 {2}] $axi_ad9250_gt -set_property -dict [list CONFIG.RX_OUT_DIV_1 {1}] $axi_ad9250_gt -set_property -dict [list CONFIG.TX_OUT_DIV_1 {1}] $axi_ad9250_gt -set_property -dict [list CONFIG.RX_CLK25_DIV_1 {10}] $axi_ad9250_gt -set_property -dict [list CONFIG.TX_CLK25_DIV_1 {10}] $axi_ad9250_gt -set_property -dict [list CONFIG.PMA_RSV_1 {0x00018480}] $axi_ad9250_gt -set_property -dict [list CONFIG.RX_CDR_CFG_1 {0x03000023ff20400020}] $axi_ad9250_gt -set_property -dict [list CONFIG.CPLL_FBDIV_2 {2}] $axi_ad9250_gt -set_property -dict [list CONFIG.RX_OUT_DIV_2 {1}] $axi_ad9250_gt -set_property -dict [list CONFIG.TX_OUT_DIV_2 {1}] $axi_ad9250_gt -set_property -dict [list CONFIG.RX_CLK25_DIV_2 {10}] $axi_ad9250_gt -set_property -dict [list CONFIG.TX_CLK25_DIV_2 {10}] $axi_ad9250_gt -set_property -dict [list CONFIG.PMA_RSV_2 {0x00018480}] $axi_ad9250_gt -set_property -dict [list CONFIG.RX_CDR_CFG_2 {0x03000023ff20400020}] $axi_ad9250_gt -set_property -dict [list CONFIG.CPLL_FBDIV_3 {2}] $axi_ad9250_gt -set_property -dict [list CONFIG.RX_OUT_DIV_3 {1}] $axi_ad9250_gt -set_property -dict [list CONFIG.TX_OUT_DIV_3 {1}] $axi_ad9250_gt -set_property -dict [list CONFIG.RX_CLK25_DIV_3 {10}] $axi_ad9250_gt -set_property -dict [list CONFIG.TX_CLK25_DIV_3 {10}] $axi_ad9250_gt -set_property -dict [list CONFIG.PMA_RSV_3 {0x00018480}] $axi_ad9250_gt -set_property -dict [list CONFIG.RX_CDR_CFG_3 {0x03000023ff20400020}] $axi_ad9250_gt - -set util_fmcjesdadc1_gt [create_bd_cell -type ip -vlnv analog.com:user:util_jesd_gt:1.0 util_fmcjesdadc1_gt] -set_property -dict [list CONFIG.QPLL0_ENABLE {0}] $util_fmcjesdadc1_gt -set_property -dict [list CONFIG.QPLL1_ENABLE {0}] $util_fmcjesdadc1_gt -set_property -dict [list CONFIG.NUM_OF_LANES {4}] $util_fmcjesdadc1_gt -set_property -dict [list CONFIG.RX_ENABLE {1}] $util_fmcjesdadc1_gt -set_property -dict [list CONFIG.RX_NUM_OF_LANES {4}] $util_fmcjesdadc1_gt -set_property -dict [list CONFIG.TX_ENABLE {0}] $util_fmcjesdadc1_gt +set axi_ad9250_0_cpack [create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 axi_ad9250_0_cpack] +set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $axi_ad9250_0_cpack +set axi_ad9250_1_cpack [create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 axi_ad9250_1_cpack] +set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $axi_ad9250_1_cpack set axi_ad9250_0_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9250_0_dma] set_property -dict [list CONFIG.DMA_TYPE_SRC {2}] $axi_ad9250_0_dma @@ -85,111 +51,99 @@ set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad9250_1_dma set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {64}] $axi_ad9250_1_dma set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $axi_ad9250_1_dma -set data_bsplit [create_bd_cell -type ip -vlnv analog.com:user:util_bsplit:1.0 data_bsplit] -set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {64} ] $data_bsplit -set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $data_bsplit +# transceiver core -set data_pack_0 [create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 data_pack_0] -set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $data_pack_0 +set util_fmcjesdadc1_xcvr [create_bd_cell -type ip -vlnv analog.com:user:util_adxcvr:1.0 util_fmcjesdadc1_xcvr] +set_property -dict [list CONFIG.QPLL_FBDIV {"0010000000"}] $util_fmcjesdadc1_xcvr +set_property -dict [list CONFIG.CPLL_FBDIV {2}] $util_fmcjesdadc1_xcvr +set_property -dict [list CONFIG.TX_NUM_OF_LANES {0}] $util_fmcjesdadc1_xcvr +set_property -dict [list CONFIG.TX_OUT_DIV {1}] $util_fmcjesdadc1_xcvr +set_property -dict [list CONFIG.TX_CLK25_DIV {10}] $util_fmcjesdadc1_xcvr +set_property -dict [list CONFIG.RX_NUM_OF_LANES {4}] $util_fmcjesdadc1_xcvr +set_property -dict [list CONFIG.RX_OUT_DIV {1}] $util_fmcjesdadc1_xcvr +set_property -dict [list CONFIG.RX_CLK25_DIV {10}] $util_fmcjesdadc1_xcvr +set_property -dict [list CONFIG.RX_DFE_LPM_CFG {0x0904}] $util_fmcjesdadc1_xcvr +set_property -dict [list CONFIG.RX_PMA_CFG {0x00018480}] $util_fmcjesdadc1_xcvr +set_property -dict [list CONFIG.RX_CDR_CFG {0x03000023ff10200020}] $util_fmcjesdadc1_xcvr -set data_pack_1 [create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 data_pack_1] -set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $data_pack_1 +# reference clocks & resets -# connections (gt) +create_bd_port -dir I rx_ref_clk_0 -ad_connect util_fmcjesdadc1_gt/qpll_ref_clk rx_ref_clk -ad_connect util_fmcjesdadc1_gt/cpll_ref_clk rx_ref_clk +ad_xcvrpll rx_ref_clk_0 util_fmcjesdadc1_xcvr/qpll_ref_clk_* +ad_xcvrpll rx_ref_clk_0 util_fmcjesdadc1_xcvr/cpll_ref_clk_* +ad_xcvrpll axi_ad9250_xcvr/up_pll_rst util_fmcjesdadc1_xcvr/up_qpll_rst_* +ad_xcvrpll axi_ad9250_xcvr/up_pll_rst util_fmcjesdadc1_xcvr/up_cpll_rst_* +ad_connect sys_cpu_resetn util_fmcjesdadc1_xcvr/up_rstn +ad_connect sys_cpu_clk util_fmcjesdadc1_xcvr/up_clk -ad_connect axi_ad9250_gt/gt_pll_0 util_fmcjesdadc1_gt/gt_pll_0 -ad_connect axi_ad9250_gt/gt_pll_1 util_fmcjesdadc1_gt/gt_pll_1 -ad_connect axi_ad9250_gt/gt_pll_2 util_fmcjesdadc1_gt/gt_pll_2 -ad_connect axi_ad9250_gt/gt_pll_3 util_fmcjesdadc1_gt/gt_pll_3 - -ad_connect axi_ad9250_gt/gt_rx_0 util_fmcjesdadc1_gt/gt_rx_0 -ad_connect axi_ad9250_gt/gt_rx_1 util_fmcjesdadc1_gt/gt_rx_1 -ad_connect axi_ad9250_gt/gt_rx_2 util_fmcjesdadc1_gt/gt_rx_2 -ad_connect axi_ad9250_gt/gt_rx_3 util_fmcjesdadc1_gt/gt_rx_3 - -ad_connect axi_ad9250_gt/gt_rx_ip_0 axi_ad9250_jesd/gt0_rx -ad_connect axi_ad9250_gt/gt_rx_ip_1 axi_ad9250_jesd/gt1_rx -ad_connect axi_ad9250_gt/gt_rx_ip_2 axi_ad9250_jesd/gt2_rx -ad_connect axi_ad9250_gt/gt_rx_ip_3 axi_ad9250_jesd/gt3_rx - -ad_connect axi_ad9250_gt/rx_gt_comma_align_enb_0 axi_ad9250_jesd/rxencommaalign_out -ad_connect axi_ad9250_gt/rx_gt_comma_align_enb_1 axi_ad9250_jesd/rxencommaalign_out -ad_connect axi_ad9250_gt/rx_gt_comma_align_enb_2 axi_ad9250_jesd/rxencommaalign_out -ad_connect axi_ad9250_gt/rx_gt_comma_align_enb_3 axi_ad9250_jesd/rxencommaalign_out +create_bd_port -dir O rx_core_clk # connections (adc) -ad_connect util_fmcjesdadc1_gt/rx_ip_sysref rx_sysref -ad_connect util_fmcjesdadc1_gt/rx_p rx_data_p -ad_connect util_fmcjesdadc1_gt/rx_n rx_data_n -ad_connect util_fmcjesdadc1_gt/rx_sync rx_sync +ad_xcvrcon util_fmcjesdadc1_xcvr axi_ad9250_xcvr axi_ad9250_jesd +ad_connect util_fmcjesdadc1_xcvr/rx_out_clk_0 axi_ad9250_0_core/rx_clk +ad_connect util_fmcjesdadc1_xcvr/rx_out_clk_0 rx_core_clk +ad_connect axi_ad9250_jesd/rx_start_of_frame axi_ad9250_0_core/rx_sof +ad_connect util_fmcjesdadc1_xcvr/rx_out_clk_0 axi_ad9250_1_core/rx_clk +ad_connect axi_ad9250_jesd/rx_start_of_frame axi_ad9250_1_core/rx_sof -ad_connect util_fmcjesdadc1_gt/rx_out_clk util_fmcjesdadc1_gt/rx_clk -ad_connect util_fmcjesdadc1_gt/rx_out_clk axi_ad9250_jesd/rx_core_clk -ad_connect util_fmcjesdadc1_gt/rx_ip_rst axi_ad9250_jesd/rx_reset -ad_connect util_fmcjesdadc1_gt/rx_ip_rst_done axi_ad9250_jesd/rx_reset_done -ad_connect util_fmcjesdadc1_gt/rx_ip_sysref axi_ad9250_jesd/rx_sysref -ad_connect util_fmcjesdadc1_gt/rx_ip_sync axi_ad9250_jesd/rx_sync -ad_connect util_fmcjesdadc1_gt/rx_ip_sof axi_ad9250_jesd/rx_start_of_frame -ad_connect util_fmcjesdadc1_gt/rx_ip_data axi_ad9250_jesd/rx_tdata +ad_connect axi_ad9250_jesd/rx_tdata data_bsplit/data +ad_connect axi_ad9250_0_core/rx_data data_bsplit/split_data_0 +ad_connect axi_ad9250_1_core/rx_data data_bsplit/split_data_1 -ad_connect data_bsplit/data util_fmcjesdadc1_gt/rx_data +ad_connect util_fmcjesdadc1_xcvr/rx_out_clk_0 axi_ad9250_0_cpack/adc_clk +ad_connect util_fmcjesdadc1_xcvr/rx_out_clk_0 axi_ad9250_1_cpack/adc_clk +ad_connect axi_ad9250_jesd_rstgen/peripheral_reset axi_ad9250_0_cpack/adc_rst +ad_connect axi_ad9250_jesd_rstgen/peripheral_reset axi_ad9250_1_cpack/adc_rst -ad_connect axi_ad9250_0_core/adc_clk data_pack_0/adc_clk -ad_connect axi_ad9250_0_core/adc_rst data_pack_0/adc_rst -ad_connect util_fmcjesdadc1_gt/rx_out_clk axi_ad9250_0_core/rx_clk -ad_connect data_bsplit/split_data_0 axi_ad9250_0_core/rx_data -ad_connect axi_ad9250_0_core/adc_enable_a data_pack_0/adc_enable_0 -ad_connect axi_ad9250_0_core/adc_valid_a data_pack_0/adc_valid_0 -ad_connect axi_ad9250_0_core/adc_data_a data_pack_0/adc_data_0 -ad_connect axi_ad9250_0_core/adc_enable_b data_pack_0/adc_enable_1 -ad_connect axi_ad9250_0_core/adc_valid_b data_pack_0/adc_valid_1 -ad_connect axi_ad9250_0_core/adc_data_b data_pack_0/adc_data_1 -ad_connect axi_ad9250_0_core/adc_clk axi_ad9250_0_dma/fifo_wr_clk -ad_connect axi_ad9250_0_dma/fifo_wr_en data_pack_0/adc_valid -ad_connect axi_ad9250_0_dma/fifo_wr_sync data_pack_0/adc_sync -ad_connect axi_ad9250_0_dma/fifo_wr_din data_pack_0/adc_data -ad_connect axi_ad9250_0_core/adc_dovf axi_ad9250_0_dma/fifo_wr_overflow +ad_connect axi_ad9250_0_core/adc_enable_a axi_ad9250_0_cpack/adc_enable_0 +ad_connect axi_ad9250_0_core/adc_valid_a axi_ad9250_0_cpack/adc_valid_0 +ad_connect axi_ad9250_0_core/adc_data_a axi_ad9250_0_cpack/adc_data_0 +ad_connect axi_ad9250_0_core/adc_enable_b axi_ad9250_0_cpack/adc_enable_1 +ad_connect axi_ad9250_0_core/adc_valid_b axi_ad9250_0_cpack/adc_valid_1 +ad_connect axi_ad9250_0_core/adc_data_b axi_ad9250_0_cpack/adc_data_1 +ad_connect axi_ad9250_1_core/adc_enable_a axi_ad9250_1_cpack/adc_enable_0 +ad_connect axi_ad9250_1_core/adc_valid_a axi_ad9250_1_cpack/adc_valid_0 +ad_connect axi_ad9250_1_core/adc_data_a axi_ad9250_1_cpack/adc_data_0 +ad_connect axi_ad9250_1_core/adc_enable_b axi_ad9250_1_cpack/adc_enable_1 +ad_connect axi_ad9250_1_core/adc_valid_b axi_ad9250_1_cpack/adc_valid_1 +ad_connect axi_ad9250_1_core/adc_data_b axi_ad9250_1_cpack/adc_data_1 -ad_connect axi_ad9250_1_core/adc_clk data_pack_1/adc_clk -ad_connect axi_ad9250_1_core/adc_rst data_pack_1/adc_rst -ad_connect util_fmcjesdadc1_gt/rx_out_clk axi_ad9250_1_core/rx_clk -ad_connect data_bsplit/split_data_1 axi_ad9250_1_core/rx_data -ad_connect axi_ad9250_1_core/adc_enable_a data_pack_1/adc_enable_0 -ad_connect axi_ad9250_1_core/adc_valid_a data_pack_1/adc_valid_0 -ad_connect axi_ad9250_1_core/adc_data_a data_pack_1/adc_data_0 -ad_connect axi_ad9250_1_core/adc_enable_b data_pack_1/adc_enable_1 -ad_connect axi_ad9250_1_core/adc_valid_b data_pack_1/adc_valid_1 -ad_connect axi_ad9250_1_core/adc_data_b data_pack_1/adc_data_1 +ad_connect axi_ad9250_0_core/adc_clk axi_ad9250_0_dma/fifo_wr_clk +ad_connect axi_ad9250_0_dma/fifo_wr_en axi_ad9250_0_cpack/adc_valid +ad_connect axi_ad9250_0_dma/fifo_wr_sync axi_ad9250_0_cpack/adc_sync +ad_connect axi_ad9250_0_dma/fifo_wr_din axi_ad9250_0_cpack/adc_data +ad_connect axi_ad9250_0_core/adc_dovf axi_ad9250_0_dma/fifo_wr_overflow +ad_connect axi_ad9250_1_core/adc_clk axi_ad9250_1_dma/fifo_wr_clk +ad_connect axi_ad9250_1_dma/fifo_wr_en axi_ad9250_1_cpack/adc_valid +ad_connect axi_ad9250_1_dma/fifo_wr_sync axi_ad9250_1_cpack/adc_sync +ad_connect axi_ad9250_1_dma/fifo_wr_din axi_ad9250_1_cpack/adc_data +ad_connect axi_ad9250_1_core/adc_dovf axi_ad9250_1_dma/fifo_wr_overflow -ad_connect axi_ad9250_1_core/adc_clk axi_ad9250_1_dma/fifo_wr_clk +# interconnect (cpu) -ad_connect axi_ad9250_1_dma/fifo_wr_en data_pack_1/adc_valid -ad_connect axi_ad9250_1_dma/fifo_wr_sync data_pack_1/adc_sync -ad_connect axi_ad9250_1_dma/fifo_wr_din data_pack_1/adc_data -ad_connect axi_ad9250_1_core/adc_dovf axi_ad9250_1_dma/fifo_wr_overflow +ad_cpu_interconnect 0x44A60000 axi_ad9250_xcvr +ad_cpu_interconnect 0x44A10000 axi_ad9250_0_core +ad_cpu_interconnect 0x44A20000 axi_ad9250_1_core +ad_cpu_interconnect 0x44A91000 axi_ad9250_jesd +ad_cpu_interconnect 0x7c420000 axi_ad9250_0_dma +ad_cpu_interconnect 0x7c430000 axi_ad9250_1_dma -# interconnects +# xcvr uses hp3, and 100MHz clock for both DRP and AXI4 -ad_cpu_interconnect 0x44A10000 axi_ad9250_0_core -ad_cpu_interconnect 0x44A20000 axi_ad9250_1_core -ad_cpu_interconnect 0x44A60000 axi_ad9250_gt -ad_cpu_interconnect 0x44A91000 axi_ad9250_jesd -ad_cpu_interconnect 0x7c420000 axi_ad9250_0_dma -ad_cpu_interconnect 0x7c430000 axi_ad9250_1_dma +ad_mem_hp3_interconnect sys_cpu_clk sys_ps7/S_AXI_HP3 +ad_mem_hp3_interconnect sys_cpu_clk axi_ad9250_xcvr/m_axi + +# interconnect (adc) ad_mem_hp2_interconnect sys_200m_clk sys_ps7/S_AXI_HP2 ad_mem_hp2_interconnect sys_200m_clk axi_ad9250_0_dma/m_dest_axi ad_mem_hp2_interconnect sys_200m_clk axi_ad9250_1_dma/m_dest_axi + ad_connect sys_cpu_resetn axi_ad9250_0_dma/m_dest_axi_aresetn ad_connect sys_cpu_resetn axi_ad9250_1_dma/m_dest_axi_aresetn -ad_mem_hp3_interconnect sys_cpu_clk sys_ps7/S_AXI_HP3 -ad_mem_hp3_interconnect sys_cpu_clk axi_ad9250_gt/m_axi - #interrupts ad_cpu_interrupt ps-13 mb-13 axi_ad9250_0_dma/irq diff --git a/projects/fmcjesdadc1/common/fmcjesdadc1_qsys.tcl b/projects/fmcjesdadc1/common/fmcjesdadc1_qsys.tcl new file mode 100644 index 000000000..dc0cada5e --- /dev/null +++ b/projects/fmcjesdadc1/common/fmcjesdadc1_qsys.tcl @@ -0,0 +1,187 @@ + +# ad9250-xcvr + +add_instance avl_ad9250_xcvr avl_adxcvr 1.0 +set_instance_parameter_value avl_ad9250_xcvr {ID} {1} +set_instance_parameter_value avl_ad9250_xcvr {TX_OR_RX_N} {0} +set_instance_parameter_value avl_ad9250_xcvr {PCS_CONFIG} {JESD_PCS_CFG1} +set_instance_parameter_value avl_ad9250_xcvr {LANE_RATE} {5000.0} +set_instance_parameter_value avl_ad9250_xcvr {SYSCLK_FREQUENCY} {50.0} +set_instance_parameter_value avl_ad9250_xcvr {PLLCLK_FREQUENCY} {2500.0} +set_instance_parameter_value avl_ad9250_xcvr {REFCLK_FREQUENCY} {250.0} +set_instance_parameter_value avl_ad9250_xcvr {CORECLK_FREQUENCY} {125.0} +set_instance_parameter_value avl_ad9250_xcvr {NUM_OF_LANES} {4} +set_instance_parameter_value avl_ad9250_xcvr {NUM_OF_CONVS} {4} +set_instance_parameter_value avl_ad9250_xcvr {FRM_BCNT} {4} +set_instance_parameter_value avl_ad9250_xcvr {FRM_SCNT} {1} +set_instance_parameter_value avl_ad9250_xcvr {MF_FCNT} {32} +set_instance_parameter_value avl_ad9250_xcvr {HD} {0} + +add_connection sys_clk.clk avl_ad9250_xcvr.sys_clk +add_connection sys_clk.clk_reset avl_ad9250_xcvr.sys_resetn +add_interface rx_ref_clk clock sink +set_interface_property rx_ref_clk EXPORT_OF avl_ad9250_xcvr.ref_clk +add_interface rx_data_0 conduit end +set_interface_property rx_data_0 EXPORT_OF avl_ad9250_xcvr.rx_data_0 +add_interface rx_data_1 conduit end +set_interface_property rx_data_1 EXPORT_OF avl_ad9250_xcvr.rx_data_1 +add_interface rx_data_2 conduit end +set_interface_property rx_data_2 EXPORT_OF avl_ad9250_xcvr.rx_data_2 +add_interface rx_data_3 conduit end +set_interface_property rx_data_3 EXPORT_OF avl_ad9250_xcvr.rx_data_3 +add_interface rx_sysref conduit end +set_interface_property rx_sysref EXPORT_OF avl_ad9250_xcvr.sysref +add_interface rx_sync conduit end +set_interface_property rx_sync EXPORT_OF avl_ad9250_xcvr.sync +add_interface rx_ip_sof conduit end +set_interface_property rx_ip_sof EXPORT_OF avl_ad9250_xcvr.ip_sof +add_interface rx_ip_data avalon_streaming source +set_interface_property rx_ip_data EXPORT_OF avl_ad9250_xcvr.ip_data + +# ad9250-xcvr + +add_instance axi_ad9250_xcvr axi_adxcvr 1.0 +set_instance_parameter_value axi_ad9250_xcvr {ID} {1} +set_instance_parameter_value axi_ad9250_xcvr {TX_OR_RX_N} {0} +set_instance_parameter_value axi_ad9250_xcvr {NUM_OF_LANES} {4} + +add_connection sys_clk.clk axi_ad9250_xcvr.s_axi_clock +add_connection sys_clk.clk_reset axi_ad9250_xcvr.s_axi_reset +add_connection axi_ad9250_xcvr.if_up_rst avl_ad9250_xcvr.rst +add_connection avl_ad9250_xcvr.ready axi_ad9250_xcvr.ready +add_connection axi_ad9250_xcvr.core_pll_locked avl_ad9250_xcvr.core_pll_locked + +# ad9250 + +add_instance axi_ad9250_core_0 axi_ad9250 1.0 + +add_connection avl_ad9250_xcvr.core_clk axi_ad9250_core_0.if_rx_clk +add_interface rx_ip_sof_0 conduit end +set_interface_property rx_ip_sof_0 EXPORT_OF axi_ad9250_core_0.if_rx_sof +add_interface rx_ip_data_0 avalon_streaming sink +set_interface_property rx_ip_data_0 EXPORT_OF axi_ad9250_core_0.if_rx_data +add_connection sys_clk.clk_reset axi_ad9250_core_0.s_axi_reset +add_connection sys_clk.clk axi_ad9250_core_0.s_axi_clock + +add_instance axi_ad9250_core_1 axi_ad9250 1.0 + +add_connection avl_ad9250_xcvr.core_clk axi_ad9250_core_1.if_rx_clk +add_interface rx_ip_sof_1 conduit end +set_interface_property rx_ip_sof_1 EXPORT_OF axi_ad9250_core_1.if_rx_sof +add_interface rx_ip_data_1 avalon_streaming sink +set_interface_property rx_ip_data_1 EXPORT_OF axi_ad9250_core_1.if_rx_data +add_connection sys_clk.clk_reset axi_ad9250_core_1.s_axi_reset +add_connection sys_clk.clk axi_ad9250_core_1.s_axi_clock + +# ad9250-pack + +add_instance util_ad9250_cpack_0 util_cpack 1.0 +set_instance_parameter_value util_ad9250_cpack_0 {CHANNEL_DATA_WIDTH} {32} +set_instance_parameter_value util_ad9250_cpack_0 {NUM_OF_CHANNELS} {2} + +add_connection sys_clk.clk_reset util_ad9250_cpack_0.if_adc_rst +add_connection avl_ad9250_xcvr.core_clk util_ad9250_cpack_0.if_adc_clk +add_connection axi_ad9250_core_0.adc_ch_0 util_ad9250_cpack_0.adc_ch_0 +add_connection axi_ad9250_core_0.adc_ch_1 util_ad9250_cpack_0.adc_ch_1 + +add_instance util_ad9250_cpack_1 util_cpack 1.0 +set_instance_parameter_value util_ad9250_cpack_1 {CHANNEL_DATA_WIDTH} {32} +set_instance_parameter_value util_ad9250_cpack_1 {NUM_OF_CHANNELS} {2} + +add_connection sys_clk.clk_reset util_ad9250_cpack_1.if_adc_rst +add_connection avl_ad9250_xcvr.core_clk util_ad9250_cpack_1.if_adc_clk +add_connection axi_ad9250_core_1.adc_ch_0 util_ad9250_cpack_1.adc_ch_0 +add_connection axi_ad9250_core_1.adc_ch_1 util_ad9250_cpack_1.adc_ch_1 + +# ad9250-dma + +add_instance axi_ad9250_dma_0 axi_dmac 1.0 +set_instance_parameter_value axi_ad9250_dma_0 {DMA_TYPE_SRC} {2} +set_instance_parameter_value axi_ad9250_dma_0 {DMA_TYPE_DEST} {0} +set_instance_parameter_value axi_ad9250_dma_0 {ID} {0} +set_instance_parameter_value axi_ad9250_dma_0 {AXI_SLICE_SRC} {0} +set_instance_parameter_value axi_ad9250_dma_0 {AXI_SLICE_DEST} {0} +set_instance_parameter_value axi_ad9250_dma_0 {SYNC_TRANSFER_START} {1} +set_instance_parameter_value axi_ad9250_dma_0 {DMA_LENGTH_WIDTH} {24} +set_instance_parameter_value axi_ad9250_dma_0 {DMA_2D_TRANSFER} {0} +set_instance_parameter_value axi_ad9250_dma_0 {CYCLIC} {0} +set_instance_parameter_value axi_ad9250_dma_0 {DMA_DATA_WIDTH_SRC} {64} +set_instance_parameter_value axi_ad9250_dma_0 {DMA_DATA_WIDTH_DEST} {64} + +add_connection avl_ad9250_xcvr.core_clk axi_ad9250_dma_0.if_fifo_wr_clk +add_connection util_ad9250_cpack_0.if_adc_valid axi_ad9250_dma_0.if_fifo_wr_en +add_connection util_ad9250_cpack_0.if_adc_sync axi_ad9250_dma_0.if_fifo_wr_sync +add_connection util_ad9250_cpack_0.if_adc_data axi_ad9250_dma_0.if_fifo_wr_din +add_connection axi_ad9250_dma_0.if_fifo_wr_overflow axi_ad9250_core_0.if_adc_dovf +add_connection sys_clk.clk_reset axi_ad9250_dma_0.s_axi_reset +add_connection sys_clk.clk axi_ad9250_dma_0.s_axi_clock +add_connection sys_dma_clk.clk_reset axi_ad9250_dma_0.m_dest_axi_reset +add_connection sys_dma_clk.clk axi_ad9250_dma_0.m_dest_axi_clock + +add_instance axi_ad9250_dma_1 axi_dmac 1.0 +set_instance_parameter_value axi_ad9250_dma_1 {DMA_TYPE_SRC} {2} +set_instance_parameter_value axi_ad9250_dma_1 {DMA_TYPE_DEST} {0} +set_instance_parameter_value axi_ad9250_dma_1 {ID} {0} +set_instance_parameter_value axi_ad9250_dma_1 {AXI_SLICE_SRC} {0} +set_instance_parameter_value axi_ad9250_dma_1 {AXI_SLICE_DEST} {0} +set_instance_parameter_value axi_ad9250_dma_1 {SYNC_TRANSFER_START} {1} +set_instance_parameter_value axi_ad9250_dma_1 {DMA_LENGTH_WIDTH} {24} +set_instance_parameter_value axi_ad9250_dma_1 {DMA_2D_TRANSFER} {0} +set_instance_parameter_value axi_ad9250_dma_1 {CYCLIC} {0} +set_instance_parameter_value axi_ad9250_dma_1 {DMA_DATA_WIDTH_SRC} {64} +set_instance_parameter_value axi_ad9250_dma_1 {DMA_DATA_WIDTH_DEST} {64} + +add_connection avl_ad9250_xcvr.core_clk axi_ad9250_dma_1.if_fifo_wr_clk +add_connection util_ad9250_cpack_1.if_adc_valid axi_ad9250_dma_1.if_fifo_wr_en +add_connection util_ad9250_cpack_1.if_adc_sync axi_ad9250_dma_1.if_fifo_wr_sync +add_connection util_ad9250_cpack_1.if_adc_data axi_ad9250_dma_1.if_fifo_wr_din +add_connection axi_ad9250_dma_1.if_fifo_wr_overflow axi_ad9250_core_1.if_adc_dovf +add_connection sys_clk.clk_reset axi_ad9250_dma_1.s_axi_reset +add_connection sys_clk.clk axi_ad9250_dma_1.s_axi_clock +add_connection sys_dma_clk.clk_reset axi_ad9250_dma_1.m_dest_axi_reset +add_connection sys_dma_clk.clk axi_ad9250_dma_1.m_dest_axi_clock + +# core-clock + +add_instance rx_core_clk altera_clock_bridge 16.0 +add_connection avl_ad9250_xcvr.core_clk rx_core_clk.in_clk +add_interface rx_core_clk clock source +set_interface_property rx_core_clk EXPORT_OF rx_core_clk.out_clk + +# phy reconfiguration + +add_instance avl_phy_reconfig alt_xcvr_reconfig 16.0 +set_instance_parameter_value avl_phy_reconfig {number_of_reconfig_interfaces} {4} +set_instance_parameter_value avl_phy_reconfig {gui_split_sizes} {1,1,1,1} +add_connection avl_phy_reconfig.ch0_0_to_xcvr avl_ad9250_xcvr.phy_reconfig_to_xcvr_0 +add_connection avl_ad9250_xcvr.phy_reconfig_from_xcvr_0 avl_phy_reconfig.ch0_0_from_xcvr +add_connection avl_phy_reconfig.ch1_1_to_xcvr avl_ad9250_xcvr.phy_reconfig_to_xcvr_1 +add_connection avl_ad9250_xcvr.phy_reconfig_from_xcvr_1 avl_phy_reconfig.ch1_1_from_xcvr +add_connection avl_phy_reconfig.ch2_2_to_xcvr avl_ad9250_xcvr.phy_reconfig_to_xcvr_2 +add_connection avl_ad9250_xcvr.phy_reconfig_from_xcvr_2 avl_phy_reconfig.ch2_2_from_xcvr +add_connection avl_phy_reconfig.ch3_3_to_xcvr avl_ad9250_xcvr.phy_reconfig_to_xcvr_3 +add_connection avl_ad9250_xcvr.phy_reconfig_from_xcvr_3 avl_phy_reconfig.ch3_3_from_xcvr +add_connection sys_clk.clk_reset avl_phy_reconfig.mgmt_rst_reset +add_connection sys_clk.clk avl_phy_reconfig.mgmt_clk_clk + +# addresses + +ad_cpu_interconnect 0x00010000 avl_phy_reconfig.reconfig_mgmt +ad_cpu_interconnect 0x00018000 avl_ad9250_xcvr.core_pll_reconfig +ad_cpu_interconnect 0x00019000 avl_ad9250_xcvr.ip_reconfig +ad_cpu_interconnect 0x00020000 axi_ad9250_xcvr.s_axi +ad_cpu_interconnect 0x00050000 axi_ad9250_core_0.s_axi +ad_cpu_interconnect 0x00060000 axi_ad9250_core_1.s_axi +ad_cpu_interconnect 0x00070000 axi_ad9250_dma_0.s_axi +ad_cpu_interconnect 0x00080000 axi_ad9250_dma_1.s_axi + +# dma interconnects + +ad_dma_interconnect axi_ad9250_dma_0.m_dest_axi +ad_dma_interconnect axi_ad9250_dma_1.m_dest_axi + +# interrupts + +ad_cpu_interrupt 11 axi_ad9250_dma_0.interrupt_sender +ad_cpu_interrupt 12 axi_ad9250_dma_1.interrupt_sender + diff --git a/projects/fmcjesdadc1/kc705/Makefile b/projects/fmcjesdadc1/kc705/Makefile index 7050c879e..356fcc60a 100644 --- a/projects/fmcjesdadc1/kc705/Makefile +++ b/projects/fmcjesdadc1/kc705/Makefile @@ -17,13 +17,14 @@ M_DEPS += ../../scripts/adi_board.tcl M_DEPS += ../../common/kc705/kc705_system_mig.prj M_DEPS += ../../common/kc705/kc705_system_constr.xdc M_DEPS += ../../common/kc705/kc705_system_bd.tcl -M_DEPS += ../../../library/common/ad_iobuf.v +M_DEPS += ../../../library/xilinx/common/ad_iobuf.v +M_DEPS += ../../../library/common/ad_sysref_gen.v M_DEPS += ../../../library/axi_ad9250/axi_ad9250.xpr +M_DEPS += ../../../library/xilinx/axi_adxcvr/axi_adxcvr.xpr M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr -M_DEPS += ../../../library/axi_jesd_gt/axi_jesd_gt.xpr +M_DEPS += ../../../library/xilinx/util_adxcvr/util_adxcvr.xpr M_DEPS += ../../../library/util_bsplit/util_bsplit.xpr M_DEPS += ../../../library/util_cpack/util_cpack.xpr -M_DEPS += ../../../library/util_jesd_gt/util_jesd_gt.xpr M_VIVADO := vivado -mode batch -source @@ -39,6 +40,7 @@ M_FLIST += *.sdk M_FLIST += *.hw M_FLIST += *.sim M_FLIST += .Xil +M_FLIST += *.ip_user_files @@ -52,25 +54,25 @@ clean: clean-all:clean make -C ../../../library/axi_ad9250 clean + make -C ../../../library/xilinx/axi_adxcvr clean make -C ../../../library/axi_dmac clean - make -C ../../../library/axi_jesd_gt clean + make -C ../../../library/xilinx/util_adxcvr clean make -C ../../../library/util_bsplit clean make -C ../../../library/util_cpack clean - make -C ../../../library/util_jesd_gt clean fmcjesdadc1_kc705.sdk/system_top.hdf: $(M_DEPS) - rm -rf $(M_FLIST) + -rm -rf $(M_FLIST) $(M_VIVADO) system_project.tcl >> fmcjesdadc1_kc705_vivado.log 2>&1 lib: make -C ../../../library/axi_ad9250 + make -C ../../../library/xilinx/axi_adxcvr make -C ../../../library/axi_dmac - make -C ../../../library/axi_jesd_gt + make -C ../../../library/xilinx/util_adxcvr make -C ../../../library/util_bsplit make -C ../../../library/util_cpack - make -C ../../../library/util_jesd_gt #################################################################################### #################################################################################### diff --git a/projects/fmcjesdadc1/kc705/system_constr.xdc b/projects/fmcjesdadc1/kc705/system_constr.xdc index 66d941e14..ba04189fa 100644 --- a/projects/fmcjesdadc1/kc705/system_constr.xdc +++ b/projects/fmcjesdadc1/kc705/system_constr.xdc @@ -21,4 +21,10 @@ set_property -dict {PACKAGE_PIN D21 IOSTANDARD LVCMOS25} [get_ports spi_sdio # clocks create_clock -name rx_ref_clk -period 4.00 [get_ports rx_ref_clk_p] -create_clock -name rx_div_clk -period 6.40 [get_pins i_system_wrapper/system_i/axi_ad9250_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK] +create_clock -name rx_div_clk -period 6.40 [get_pins i_system_wrapper/system_i/util_fmcjesdadc1_xcvr/inst/i_xch_0/i_gtxe2_channel/RXOUTCLK] + +set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9250_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]] + +set_property shreg_extract no [get_cells -hier -filter {name =~ *sysref_en_m*}] +set_false_path -to [get_cells -hier -filter {name =~ *sysref_en_m1* && IS_SEQUENTIAL}] + diff --git a/projects/fmcjesdadc1/kc705/system_project.tcl b/projects/fmcjesdadc1/kc705/system_project.tcl index c8bb0ab9c..e31aa0af4 100644 --- a/projects/fmcjesdadc1/kc705/system_project.tcl +++ b/projects/fmcjesdadc1/kc705/system_project.tcl @@ -8,7 +8,9 @@ adi_project_files fmcjesdadc1_kc705 [list \ "../common/fmcjesdadc1_spi.v" \ "system_top.v" \ "system_constr.xdc" \ - "$ad_hdl_dir/library/common/ad_iobuf.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \ + "$ad_hdl_dir/library/common/ad_sysref_gen.v" \ "$ad_hdl_dir/projects/common/kc705/kc705_system_constr.xdc" ] adi_project_run fmcjesdadc1_kc705 + diff --git a/projects/fmcjesdadc1/kc705/system_top.v b/projects/fmcjesdadc1/kc705/system_top.v index cac2d30e7..60fd19c76 100644 --- a/projects/fmcjesdadc1/kc705/system_top.v +++ b/projects/fmcjesdadc1/kc705/system_top.v @@ -180,6 +180,8 @@ module system_top ( wire spi_mosi; wire spi_miso; wire rx_ref_clk; + wire rx_clk; + wire rx_sysref; assign ddr3_1_p = 2'b11; assign ddr3_1_n = 3'b000; @@ -209,6 +211,11 @@ module system_top ( .spi_miso (spi_miso), .spi_sdio (spi_sdio)); + ad_sysref_gen #(.SYSREF_PERIOD(64)) i_sysref ( + .core_clk (rx_clk), + .sysref_en (gpio_o[32]), + .sysref_out (rx_sysref)); + // instantiations system_wrapper i_system_wrapper ( @@ -266,11 +273,18 @@ module system_top ( .sys_rst (sys_rst), .uart_sin (uart_sin), .uart_sout (uart_sout), - .rx_data_n (rx_data_n), - .rx_data_p (rx_data_p), - .rx_ref_clk (rx_ref_clk), - .rx_sync (rx_sync), - .rx_sysref (rx_sysref), + .rx_data_0_n (rx_data_n[0]), + .rx_data_0_p (rx_data_p[0]), + .rx_data_1_n (rx_data_n[1]), + .rx_data_1_p (rx_data_p[1]), + .rx_data_2_n (rx_data_n[2]), + .rx_data_2_p (rx_data_p[2]), + .rx_data_3_n (rx_data_n[3]), + .rx_data_3_p (rx_data_p[3]), + .rx_ref_clk_0 (rx_ref_clk), + .rx_sync_0 (rx_sync), + .rx_sysref_0 (rx_sysref), + .rx_core_clk (rx_clk), .spi_clk_i (spi_clk), .spi_clk_o (spi_clk), .spi_csn_i (spi_csn), diff --git a/projects/fmcjesdadc1/vc707/Makefile b/projects/fmcjesdadc1/vc707/Makefile index 379caa28b..34966231f 100644 --- a/projects/fmcjesdadc1/vc707/Makefile +++ b/projects/fmcjesdadc1/vc707/Makefile @@ -17,13 +17,14 @@ M_DEPS += ../../scripts/adi_board.tcl M_DEPS += ../../common/vc707/vc707_system_mig.prj M_DEPS += ../../common/vc707/vc707_system_constr.xdc M_DEPS += ../../common/vc707/vc707_system_bd.tcl -M_DEPS += ../../../library/common/ad_iobuf.v +M_DEPS += ../../../library/xilinx/common/ad_iobuf.v +M_DEPS += ../../../library/common/ad_sysref_gen.v M_DEPS += ../../../library/axi_ad9250/axi_ad9250.xpr +M_DEPS += ../../../library/xilinx/axi_adxcvr/axi_adxcvr.xpr M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr -M_DEPS += ../../../library/axi_jesd_gt/axi_jesd_gt.xpr +M_DEPS += ../../../library/xilinx/util_adxcvr/util_adxcvr.xpr M_DEPS += ../../../library/util_bsplit/util_bsplit.xpr M_DEPS += ../../../library/util_cpack/util_cpack.xpr -M_DEPS += ../../../library/util_jesd_gt/util_jesd_gt.xpr M_VIVADO := vivado -mode batch -source @@ -39,6 +40,7 @@ M_FLIST += *.sdk M_FLIST += *.hw M_FLIST += *.sim M_FLIST += .Xil +M_FLIST += *.ip_user_files @@ -52,25 +54,25 @@ clean: clean-all:clean make -C ../../../library/axi_ad9250 clean + make -C ../../../library/xilinx/axi_adxcvr clean make -C ../../../library/axi_dmac clean - make -C ../../../library/axi_jesd_gt clean + make -C ../../../library/xilinx/util_adxcvr clean make -C ../../../library/util_bsplit clean make -C ../../../library/util_cpack clean - make -C ../../../library/util_jesd_gt clean fmcjesdadc1_vc707.sdk/system_top.hdf: $(M_DEPS) - rm -rf $(M_FLIST) + -rm -rf $(M_FLIST) $(M_VIVADO) system_project.tcl >> fmcjesdadc1_vc707_vivado.log 2>&1 lib: make -C ../../../library/axi_ad9250 + make -C ../../../library/xilinx/axi_adxcvr make -C ../../../library/axi_dmac - make -C ../../../library/axi_jesd_gt + make -C ../../../library/xilinx/util_adxcvr make -C ../../../library/util_bsplit make -C ../../../library/util_cpack - make -C ../../../library/util_jesd_gt #################################################################################### #################################################################################### diff --git a/projects/fmcjesdadc1/vc707/system_constr.xdc b/projects/fmcjesdadc1/vc707/system_constr.xdc index 89ae7c053..8bc97de97 100644 --- a/projects/fmcjesdadc1/vc707/system_constr.xdc +++ b/projects/fmcjesdadc1/vc707/system_constr.xdc @@ -21,4 +21,10 @@ set_property -dict {PACKAGE_PIN V29 IOSTANDARD LVCMOS18} [get_ports spi_sdio # clocks create_clock -name rx_ref_clk -period 4.00 [get_ports rx_ref_clk_p] -create_clock -name rx_div_clk -period 6.40 [get_pins i_system_wrapper/system_i/axi_ad9250_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK] +create_clock -name rx_div_clk -period 6.40 [get_pins i_system_wrapper/system_i/util_fmcjesdadc1_xcvr/inst/i_xch_0/i_gtxe2_channel/RXOUTCLK] + +set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9250_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]] + +set_property shreg_extract no [get_cells -hier -filter {name =~ *sysref_en_m*}] +set_false_path -to [get_cells -hier -filter {name =~ *sysref_en_m1* && IS_SEQUENTIAL}] + diff --git a/projects/fmcjesdadc1/vc707/system_project.tcl b/projects/fmcjesdadc1/vc707/system_project.tcl index 49573956e..f07155002 100644 --- a/projects/fmcjesdadc1/vc707/system_project.tcl +++ b/projects/fmcjesdadc1/vc707/system_project.tcl @@ -5,7 +5,8 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl adi_project_create fmcjesdadc1_vc707 adi_project_files fmcjesdadc1_vc707 [list \ - "$ad_hdl_dir/library/common/ad_iobuf.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \ + "$ad_hdl_dir/library/common/ad_sysref_gen.v" \ "../common/fmcjesdadc1_spi.v" \ "system_top.v" \ "system_constr.xdc" \ diff --git a/projects/fmcjesdadc1/vc707/system_top.v b/projects/fmcjesdadc1/vc707/system_top.v index 5bbc6ab0b..5fabc10d3 100644 --- a/projects/fmcjesdadc1/vc707/system_top.v +++ b/projects/fmcjesdadc1/vc707/system_top.v @@ -174,6 +174,8 @@ module system_top ( wire spi_miso; wire rx_ref_clk; wire [31:0] mb_intrs; + wire rx_clk; + wire rx_sysref; assign ddr3_1_p = 2'b11; assign ddr3_1_n = 3'b000; @@ -203,6 +205,11 @@ module system_top ( .spi_miso (spi_miso), .spi_sdio (spi_sdio)); + ad_sysref_gen #(.SYSREF_PERIOD(64)) i_sysref ( + .core_clk (rx_clk), + .sysref_en (gpio_o[32]), + .sysref_out (rx_sysref)); + // instantiations system_wrapper i_system_wrapper ( @@ -256,11 +263,18 @@ module system_top ( .sys_rst (sys_rst), .uart_sin (uart_sin), .uart_sout (uart_sout), - .rx_data_n (rx_data_n), - .rx_data_p (rx_data_p), - .rx_ref_clk (rx_ref_clk), - .rx_sync (rx_sync), - .rx_sysref (rx_sysref), + .rx_data_0_n (rx_data_n[0]), + .rx_data_0_p (rx_data_p[0]), + .rx_data_1_n (rx_data_n[1]), + .rx_data_1_p (rx_data_p[1]), + .rx_data_2_n (rx_data_n[2]), + .rx_data_2_p (rx_data_p[2]), + .rx_data_3_n (rx_data_n[3]), + .rx_data_3_p (rx_data_p[3]), + .rx_ref_clk_0 (rx_ref_clk), + .rx_sync_0 (rx_sync), + .rx_sysref_0 (rx_sysref), + .rx_core_clk (rx_clk), .spi_clk_i (1'b0), .spi_clk_o (spi_clk), .spi_csn_i (8'hff), diff --git a/projects/fmcjesdadc1/zc706/Makefile b/projects/fmcjesdadc1/zc706/Makefile index e3c623304..86be56155 100644 --- a/projects/fmcjesdadc1/zc706/Makefile +++ b/projects/fmcjesdadc1/zc706/Makefile @@ -16,16 +16,17 @@ M_DEPS += ../../scripts/adi_env.tcl M_DEPS += ../../scripts/adi_board.tcl M_DEPS += ../../common/zc706/zc706_system_constr.xdc M_DEPS += ../../common/zc706/zc706_system_bd.tcl -M_DEPS += ../../../library/common/ad_iobuf.v +M_DEPS += ../../../library/xilinx/common/ad_iobuf.v +M_DEPS += ../../../library/common/ad_sysref_gen.v M_DEPS += ../../../library/axi_ad9250/axi_ad9250.xpr +M_DEPS += ../../../library/xilinx/axi_adxcvr/axi_adxcvr.xpr M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr -M_DEPS += ../../../library/axi_jesd_gt/axi_jesd_gt.xpr M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr +M_DEPS += ../../../library/xilinx/util_adxcvr/util_adxcvr.xpr M_DEPS += ../../../library/util_bsplit/util_bsplit.xpr M_DEPS += ../../../library/util_cpack/util_cpack.xpr -M_DEPS += ../../../library/util_jesd_gt/util_jesd_gt.xpr M_VIVADO := vivado -mode batch -source @@ -41,6 +42,7 @@ M_FLIST += *.sdk M_FLIST += *.hw M_FLIST += *.sim M_FLIST += .Xil +M_FLIST += *.ip_user_files @@ -54,31 +56,31 @@ clean: clean-all:clean make -C ../../../library/axi_ad9250 clean + make -C ../../../library/xilinx/axi_adxcvr clean make -C ../../../library/axi_clkgen clean make -C ../../../library/axi_dmac clean make -C ../../../library/axi_hdmi_tx clean - make -C ../../../library/axi_jesd_gt clean make -C ../../../library/axi_spdif_tx clean + make -C ../../../library/xilinx/util_adxcvr clean make -C ../../../library/util_bsplit clean make -C ../../../library/util_cpack clean - make -C ../../../library/util_jesd_gt clean fmcjesdadc1_zc706.sdk/system_top.hdf: $(M_DEPS) - rm -rf $(M_FLIST) + -rm -rf $(M_FLIST) $(M_VIVADO) system_project.tcl >> fmcjesdadc1_zc706_vivado.log 2>&1 lib: make -C ../../../library/axi_ad9250 + make -C ../../../library/xilinx/axi_adxcvr make -C ../../../library/axi_clkgen make -C ../../../library/axi_dmac make -C ../../../library/axi_hdmi_tx - make -C ../../../library/axi_jesd_gt make -C ../../../library/axi_spdif_tx + make -C ../../../library/xilinx/util_adxcvr make -C ../../../library/util_bsplit make -C ../../../library/util_cpack - make -C ../../../library/util_jesd_gt #################################################################################### #################################################################################### diff --git a/projects/fmcjesdadc1/zc706/system_constr.xdc b/projects/fmcjesdadc1/zc706/system_constr.xdc index 71b03d0fb..963178e90 100644 --- a/projects/fmcjesdadc1/zc706/system_constr.xdc +++ b/projects/fmcjesdadc1/zc706/system_constr.xdc @@ -11,14 +11,20 @@ set_property -dict {PACKAGE_PIN AG8 } [get_ports rx_data_p[2]] set_property -dict {PACKAGE_PIN AG7 } [get_ports rx_data_n[2]] ; ## A07 FMC_HPC_DP2_M2C_N set_property -dict {PACKAGE_PIN AE8 } [get_ports rx_data_p[3]] ; ## A10 FMC_HPC_DP3_M2C_P set_property -dict {PACKAGE_PIN AE7 } [get_ports rx_data_n[3]] ; ## A11 FMC_HPC_DP3_M2C_N -set_property -dict {PACKAGE_PIN N26 IOSTANDARD LVCMOS25} [get_ports rx_sync] ; ## G36 FMC_HPC_LA33_P -set_property -dict {PACKAGE_PIN N27 IOSTANDARD LVCMOS25} [get_ports rx_sysref] ; ## G37 FMC_HPC_LA33_N +set_property -dict {PACKAGE_PIN N26 IOSTANDARD LVCMOS25} [get_ports rx_sync] ; ## G36 FMC_HPC_LA33_P +set_property -dict {PACKAGE_PIN N27 IOSTANDARD LVCMOS25} [get_ports rx_sysref] ; ## G37 FMC_HPC_LA33_N -set_property -dict {PACKAGE_PIN P29 IOSTANDARD LVCMOS25} [get_ports spi_csn] ; ## G34 FMC_HPC_LA31_N -set_property -dict {PACKAGE_PIN N29 IOSTANDARD LVCMOS25} [get_ports spi_clk] ; ## G33 FMC_HPC_LA31_P -set_property -dict {PACKAGE_PIN P21 IOSTANDARD LVCMOS25} [get_ports spi_sdio] ; ## H37 FMC_HPC_LA32_P +set_property -dict {PACKAGE_PIN P29 IOSTANDARD LVCMOS25} [get_ports spi_csn] ; ## G34 FMC_HPC_LA31_N +set_property -dict {PACKAGE_PIN N29 IOSTANDARD LVCMOS25} [get_ports spi_clk] ; ## G33 FMC_HPC_LA31_P +set_property -dict {PACKAGE_PIN P21 IOSTANDARD LVCMOS25} [get_ports spi_sdio] ; ## H37 FMC_HPC_LA32_P # clocks create_clock -name rx_ref_clk -period 4.00 [get_ports rx_ref_clk_p] -create_clock -name rx_div_clk -period 6.40 [get_pins i_system_wrapper/system_i/axi_ad9250_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK] +create_clock -name rx_div_clk -period 6.40 [get_pins i_system_wrapper/system_i/util_fmcjesdadc1_xcvr/inst/i_xch_0/i_gtxe2_channel/RXOUTCLK] + +set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9250_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]] + +set_property shreg_extract no [get_cells -hier -filter {name =~ *sysref_en_m*}] +set_false_path -to [get_cells -hier -filter {name =~ *sysref_en_m1* && IS_SEQUENTIAL}] + diff --git a/projects/fmcjesdadc1/zc706/system_project.tcl b/projects/fmcjesdadc1/zc706/system_project.tcl index 3177a47eb..35c69f7bb 100644 --- a/projects/fmcjesdadc1/zc706/system_project.tcl +++ b/projects/fmcjesdadc1/zc706/system_project.tcl @@ -1,13 +1,12 @@ - - source ../../scripts/adi_env.tcl source $ad_hdl_dir/projects/scripts/adi_project.tcl source $ad_hdl_dir/projects/scripts/adi_board.tcl adi_project_create fmcjesdadc1_zc706 adi_project_files fmcjesdadc1_zc706 [list \ - "$ad_hdl_dir/library/common/ad_iobuf.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \ + "$ad_hdl_dir/library/common/ad_sysref_gen.v" \ "../common/fmcjesdadc1_spi.v" \ "system_top.v" \ "system_constr.xdc" \ @@ -15,4 +14,3 @@ adi_project_files fmcjesdadc1_zc706 [list \ adi_project_run fmcjesdadc1_zc706 - diff --git a/projects/fmcjesdadc1/zc706/system_top.v b/projects/fmcjesdadc1/zc706/system_top.v index 6037cc59c..d41fc4b96 100644 --- a/projects/fmcjesdadc1/zc706/system_top.v +++ b/projects/fmcjesdadc1/zc706/system_top.v @@ -149,6 +149,8 @@ module system_top ( wire spi1_clk; wire spi1_mosi; wire spi1_miso; + wire rx_clk; + wire rx_sysref; assign spi_csn = spi0_csn[0]; assign spi_clk = spi0_clk; @@ -180,6 +182,11 @@ module system_top ( .spi_miso (spi_miso), .spi_sdio (spi_sdio)); + ad_sysref_gen #(.SYSREF_PERIOD(64)) i_sysref ( + .core_clk (rx_clk), + .sysref_en (gpio_o[32]), + .sysref_out (rx_sysref)); + system_wrapper i_system_wrapper ( .ddr_addr (ddr_addr), .ddr_ba (ddr_ba), @@ -224,11 +231,18 @@ module system_top ( .ps_intr_09 (1'b0), .ps_intr_10 (1'b0), .ps_intr_11 (1'b0), - .rx_data_n (rx_data_n), - .rx_data_p (rx_data_p), - .rx_ref_clk (rx_ref_clk), - .rx_sync (rx_sync), - .rx_sysref (rx_sysref), + .rx_data_0_n (rx_data_n[0]), + .rx_data_0_p (rx_data_p[0]), + .rx_data_1_n (rx_data_n[1]), + .rx_data_1_p (rx_data_p[1]), + .rx_data_2_n (rx_data_n[2]), + .rx_data_2_p (rx_data_p[2]), + .rx_data_3_n (rx_data_n[3]), + .rx_data_3_p (rx_data_p[3]), + .rx_ref_clk_0 (rx_ref_clk), + .rx_sync_0 (rx_sync), + .rx_sysref_0 (rx_sysref), + .rx_core_clk (rx_clk), .spdif (spdif), .spi0_clk_i (spi0_clk), .spi0_clk_o (spi0_clk), diff --git a/projects/fmcomms1/ac701/system_bd.tcl b/projects/fmcomms1/ac701/system_bd.tcl deleted file mode 100644 index e398e9ada..000000000 --- a/projects/fmcomms1/ac701/system_bd.tcl +++ /dev/null @@ -1,5 +0,0 @@ - - source $ad_hdl_dir/projects/common/ac701/ac701_system_bd.tcl - source ../common/fmcomms1_bd.tcl - set_property -dict [list CONFIG.FIFO_SIZE {8}] $axi_ad9643_dma - diff --git a/projects/fmcomms1/ac701/system_constr.xdc b/projects/fmcomms1/ac701/system_constr.xdc deleted file mode 100644 index 64006bbeb..000000000 --- a/projects/fmcomms1/ac701/system_constr.xdc +++ /dev/null @@ -1,158 +0,0 @@ - -# reference - -set_property IOSTANDARD LVDS_25 [get_ports ref_clk_out_p] -set_property DIFF_TERM TRUE [get_ports ref_clk_out_p] -set_property PACKAGE_PIN J21 [get_ports ref_clk_out_n] -set_property IOSTANDARD LVDS_25 [get_ports ref_clk_out_n] -set_property DIFF_TERM TRUE [get_ports ref_clk_out_n] - -# dac - -set_property IOSTANDARD LVDS_25 [get_ports dac_clk_in_p] -set_property DIFF_TERM TRUE [get_ports dac_clk_in_p] -set_property PACKAGE_PIN C19 [get_ports dac_clk_in_n] -set_property IOSTANDARD LVDS_25 [get_ports dac_clk_in_n] -set_property DIFF_TERM TRUE [get_ports dac_clk_in_n] -set_property IOSTANDARD LVDS_25 [get_ports dac_clk_out_p] -set_property PACKAGE_PIN H19 [get_ports dac_clk_out_n] -set_property IOSTANDARD LVDS_25 [get_ports dac_clk_out_n] -set_property IOSTANDARD LVDS_25 [get_ports dac_frame_out_p] -set_property PACKAGE_PIN A19 [get_ports dac_frame_out_n] -set_property IOSTANDARD LVDS_25 [get_ports dac_frame_out_n] -set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_p[0]}] -set_property PACKAGE_PIN G26 [get_ports {dac_data_out_n[0]}] -set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_n[0]}] -set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_p[1]}] -set_property PACKAGE_PIN F25 [get_ports {dac_data_out_n[1]}] -set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_n[1]}] -set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_p[2]}] -set_property PACKAGE_PIN D25 [get_ports {dac_data_out_n[2]}] -set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_n[2]}] -set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_p[3]}] -set_property PACKAGE_PIN K23 [get_ports {dac_data_out_n[3]}] -set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_n[3]}] -set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_p[4]}] -set_property PACKAGE_PIN D26 [get_ports {dac_data_out_n[4]}] -set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_n[4]}] -set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_p[5]}] -set_property PACKAGE_PIN F24 [get_ports {dac_data_out_n[5]}] -set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_n[5]}] -set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_p[6]}] -set_property PACKAGE_PIN H18 [get_ports {dac_data_out_n[6]}] -set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_n[6]}] -set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_p[7]}] -set_property PACKAGE_PIN F22 [get_ports {dac_data_out_n[7]}] -set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_n[7]}] -set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_p[8]}] -set_property PACKAGE_PIN L18 [get_ports {dac_data_out_n[8]}] -set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_n[8]}] -set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_p[9]}] -set_property PACKAGE_PIN E23 [get_ports {dac_data_out_n[9]}] -set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_n[9]}] -set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_p[10]}] -set_property PACKAGE_PIN H24 [get_ports {dac_data_out_n[10]}] -set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_n[10]}] -set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_p[11]}] -set_property PACKAGE_PIN J20 [get_ports {dac_data_out_n[11]}] -set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_n[11]}] -set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_p[12]}] -set_property PACKAGE_PIN L14 [get_ports {dac_data_out_n[12]}] -set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_n[12]}] -set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_p[13]}] -set_property PACKAGE_PIN M17 [get_ports {dac_data_out_n[13]}] -set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_n[13]}] -set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_p[14]}] -set_property PACKAGE_PIN A22 [get_ports {dac_data_out_n[14]}] -set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_n[14]}] -set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_p[15]}] -set_property PACKAGE_PIN D21 [get_ports {dac_data_out_n[15]}] -set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_n[15]}] - -# adc - -set_property IOSTANDARD LVDS_25 [get_ports adc_clk_in_p] -set_property DIFF_TERM TRUE [get_ports adc_clk_in_p] -set_property PACKAGE_PIN H22 [get_ports adc_clk_in_n] -set_property IOSTANDARD LVDS_25 [get_ports adc_clk_in_n] -set_property DIFF_TERM TRUE [get_ports adc_clk_in_n] -set_property IOSTANDARD LVDS_25 [get_ports adc_or_in_p] -set_property DIFF_TERM TRUE [get_ports adc_or_in_p] -set_property PACKAGE_PIN C18 [get_ports adc_or_in_n] -set_property IOSTANDARD LVDS_25 [get_ports adc_or_in_n] -set_property DIFF_TERM TRUE [get_ports adc_or_in_n] -set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_p[0]}] -set_property DIFF_TERM TRUE [get_ports {adc_data_in_p[0]}] -set_property PACKAGE_PIN G21 [get_ports {adc_data_in_n[0]}] -set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_n[0]}] -set_property DIFF_TERM TRUE [get_ports {adc_data_in_n[0]}] -set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_p[1]}] -set_property DIFF_TERM TRUE [get_ports {adc_data_in_p[1]}] -set_property PACKAGE_PIN B21 [get_ports {adc_data_in_n[1]}] -set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_n[1]}] -set_property DIFF_TERM TRUE [get_ports {adc_data_in_n[1]}] -set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_p[2]}] -set_property DIFF_TERM TRUE [get_ports {adc_data_in_p[2]}] -set_property PACKAGE_PIN A20 [get_ports {adc_data_in_n[2]}] -set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_n[2]}] -set_property DIFF_TERM TRUE [get_ports {adc_data_in_n[2]}] -set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_p[3]}] -set_property DIFF_TERM TRUE [get_ports {adc_data_in_p[3]}] -set_property PACKAGE_PIN F17 [get_ports {adc_data_in_n[3]}] -set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_n[3]}] -set_property DIFF_TERM TRUE [get_ports {adc_data_in_n[3]}] -set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_p[4]}] -set_property DIFF_TERM TRUE [get_ports {adc_data_in_p[4]}] -set_property PACKAGE_PIN F15 [get_ports {adc_data_in_n[4]}] -set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_n[4]}] -set_property DIFF_TERM TRUE [get_ports {adc_data_in_n[4]}] -set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_p[5]}] -set_property DIFF_TERM TRUE [get_ports {adc_data_in_p[5]}] -set_property PACKAGE_PIN A18 [get_ports {adc_data_in_n[5]}] -set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_n[5]}] -set_property DIFF_TERM TRUE [get_ports {adc_data_in_n[5]}] -set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_p[6]}] -set_property DIFF_TERM TRUE [get_ports {adc_data_in_p[6]}] -set_property PACKAGE_PIN D20 [get_ports {adc_data_in_n[6]}] -set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_n[6]}] -set_property DIFF_TERM TRUE [get_ports {adc_data_in_n[6]}] -set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_p[7]}] -set_property DIFF_TERM TRUE [get_ports {adc_data_in_p[7]}] -set_property PACKAGE_PIN G16 [get_ports {adc_data_in_n[7]}] -set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_n[7]}] -set_property DIFF_TERM TRUE [get_ports {adc_data_in_n[7]}] -set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_p[8]}] -set_property DIFF_TERM TRUE [get_ports {adc_data_in_p[8]}] -set_property PACKAGE_PIN H15 [get_ports {adc_data_in_n[8]}] -set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_n[8]}] -set_property DIFF_TERM TRUE [get_ports {adc_data_in_n[8]}] -set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_p[9]}] -set_property DIFF_TERM TRUE [get_ports {adc_data_in_p[9]}] -set_property PACKAGE_PIN F19 [get_ports {adc_data_in_n[9]}] -set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_n[9]}] -set_property DIFF_TERM TRUE [get_ports {adc_data_in_n[9]}] -set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_p[10]}] -set_property DIFF_TERM TRUE [get_ports {adc_data_in_p[10]}] -set_property PACKAGE_PIN D16 [get_ports {adc_data_in_n[10]}] -set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_n[10]}] -set_property DIFF_TERM TRUE [get_ports {adc_data_in_n[10]}] -set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_p[11]}] -set_property DIFF_TERM TRUE [get_ports {adc_data_in_p[11]}] -set_property PACKAGE_PIN B17 [get_ports {adc_data_in_n[11]}] -set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_n[11]}] -set_property DIFF_TERM TRUE [get_ports {adc_data_in_n[11]}] -set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_p[12]}] -set_property DIFF_TERM TRUE [get_ports {adc_data_in_p[12]}] -set_property PACKAGE_PIN F20 [get_ports {adc_data_in_n[12]}] -set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_n[12]}] -set_property DIFF_TERM TRUE [get_ports {adc_data_in_n[12]}] -set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_p[13]}] -set_property DIFF_TERM TRUE [get_ports {adc_data_in_p[13]}] -set_property PACKAGE_PIN E18 [get_ports {adc_data_in_n[13]}] -set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_n[13]}] -set_property DIFF_TERM TRUE [get_ports {adc_data_in_n[13]}] - -# clocks - -create_clock -period 2.000 -name dac_clk_in [get_ports dac_clk_in_p] -create_clock -period 4.000 -name adc_clk_in [get_ports adc_clk_in_p] diff --git a/projects/fmcomms1/ac701/system_project.tcl b/projects/fmcomms1/ac701/system_project.tcl deleted file mode 100644 index 6ee52d1ad..000000000 --- a/projects/fmcomms1/ac701/system_project.tcl +++ /dev/null @@ -1,18 +0,0 @@ - -source ../../scripts/adi_env.tcl -source $ad_hdl_dir/projects/scripts/adi_project.tcl -source $ad_hdl_dir/projects/scripts/adi_board.tcl - -adi_project_create fmcomms1_ac701 -adi_project_files fmcomms1_ac701 [list \ - "system_top.v" \ - "system_constr.xdc"\ - "$ad_hdl_dir/library/common/ad_iobuf.v" \ - "$ad_hdl_dir/projects/common/ac701/ac701_system_constr.xdc" ] - -set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/ac701/ac701_system_constr.xdc] -set_property PROCESSING_ORDER EARLY [get_files system_constr.xdc] - -adi_project_run fmcomms1_ac701 - - diff --git a/projects/fmcomms1/ac701/system_top.v b/projects/fmcomms1/ac701/system_top.v deleted file mode 100644 index de6f0517e..000000000 --- a/projects/fmcomms1/ac701/system_top.v +++ /dev/null @@ -1,268 +0,0 @@ -// *************************************************************************** -// *************************************************************************** -// Copyright 2011(c) Analog Devices, Inc. -// -// All rights reserved. -// -// Redistribution and use in source and binary forms, with or without modification, -// are permitted provided that the following conditions are met: -// - Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// - Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in -// the documentation and/or other materials provided with the -// distribution. -// - Neither the name of Analog Devices, Inc. nor the names of its -// contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// - The use of this software may or may not infringe the patent rights -// of one or more patent holders. This license does not release you -// from the requirement that you obtain separate licenses from these -// patent holders to use this software. -// - Use of the software either in source or binary form, must be run -// on or directly connected to an Analog Devices Inc. component. -// -// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, -// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A -// PARTICULAR PURPOSE ARE DISCLAIMED. -// -// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY -// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF -// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// *************************************************************************** -// *************************************************************************** -// *************************************************************************** -// *************************************************************************** - -`timescale 1ns/100ps - -module system_top ( - - sys_rst, - sys_clk_p, - sys_clk_n, - - uart_sin, - uart_sout, - - ddr3_addr, - ddr3_ba, - ddr3_cas_n, - ddr3_ck_n, - ddr3_ck_p, - ddr3_cke, - ddr3_cs_n, - ddr3_dm, - ddr3_dq, - ddr3_dqs_n, - ddr3_dqs_p, - ddr3_odt, - ddr3_ras_n, - ddr3_reset_n, - ddr3_we_n, - - phy_reset_n, - phy_mdc, - phy_mdio, - phy_tx_clk, - phy_tx_ctrl, - phy_tx_data, - phy_rx_clk, - phy_rx_ctrl, - phy_rx_data, - - fan_pwm, - - gpio_lcd, - gpio_bd, - - iic_rstn, - iic_scl, - iic_sda, - - dac_clk_in_p, - dac_clk_in_n, - dac_clk_out_p, - dac_clk_out_n, - dac_frame_out_p, - dac_frame_out_n, - dac_data_out_p, - dac_data_out_n, - - adc_clk_in_p, - adc_clk_in_n, - adc_or_in_p, - adc_or_in_n, - adc_data_in_p, - adc_data_in_n, - - ref_clk_out_p, - ref_clk_out_n); - - input sys_rst; - input sys_clk_p; - input sys_clk_n; - - input uart_sin; - output uart_sout; - - output [13:0] ddr3_addr; - output [ 2:0] ddr3_ba; - output ddr3_cas_n; - output [ 0:0] ddr3_ck_n; - output [ 0:0] ddr3_ck_p; - output [ 0:0] ddr3_cke; - output [ 0:0] ddr3_cs_n; - output [ 7:0] ddr3_dm; - inout [63:0] ddr3_dq; - inout [ 7:0] ddr3_dqs_n; - inout [ 7:0] ddr3_dqs_p; - output [ 0:0] ddr3_odt; - output ddr3_ras_n; - output ddr3_reset_n; - output ddr3_we_n; - - output phy_reset_n; - output phy_mdc; - inout phy_mdio; - output phy_tx_clk; - output phy_tx_ctrl; - output [ 3:0] phy_tx_data; - input phy_rx_clk; - input phy_rx_ctrl; - input [ 3:0] phy_rx_data; - - output fan_pwm; - - inout [ 6:0] gpio_lcd; - inout [12:0] gpio_bd; - - output iic_rstn; - inout iic_scl; - inout iic_sda; - - input dac_clk_in_p; - input dac_clk_in_n; - output dac_clk_out_p; - output dac_clk_out_n; - output dac_frame_out_p; - output dac_frame_out_n; - output [15:0] dac_data_out_p; - output [15:0] dac_data_out_n; - - input adc_clk_in_p; - input adc_clk_in_n; - input adc_or_in_p; - input adc_or_in_n; - input [13:0] adc_data_in_p; - input [13:0] adc_data_in_n; - - output ref_clk_out_p; - output ref_clk_out_n; - - // internal signals - - wire [63:0] gpio_i; - wire [63:0] gpio_o; - wire [63:0] gpio_t; - wire ref_clk; - wire oddr_ref_clk; - - // assignments - - assign mgt_clk_sel = 2'd0; - assign fan_pwm = 1'b1; - assign iic_rstn = 1'b1; - - // instantiations - - ad_iobuf #(.DATA_WIDTH(13)) i_iobuf_sw_led ( - .dio_t (gpio_t[12:0]), - .dio_i (gpio_o[12:0]), - .dio_o (gpio_i[12:0]), - .dio_p (gpio_bd)); - - ODDR #( - .DDR_CLK_EDGE ("SAME_EDGE"), - .INIT (1'b0), - .SRTYPE ("ASYNC")) - i_oddr_ref_clk ( - .S (1'b0), - .CE (1'b1), - .R (1'b0), - .C (ref_clk), - .D1 (1'b1), - .D2 (1'b0), - .Q (oddr_ref_clk)); - - OBUFDS i_obufds_ref_clk ( - .I (oddr_ref_clk), - .O (ref_clk_out_p), - .OB (ref_clk_out_n)); - - system_wrapper i_system_wrapper ( - .ddr3_addr (ddr3_addr), - .ddr3_ba (ddr3_ba), - .ddr3_cas_n (ddr3_cas_n), - .ddr3_ck_n (ddr3_ck_n), - .ddr3_ck_p (ddr3_ck_p), - .ddr3_cke (ddr3_cke), - .ddr3_cs_n (ddr3_cs_n), - .ddr3_dm (ddr3_dm), - .ddr3_dq (ddr3_dq), - .ddr3_dqs_n (ddr3_dqs_n), - .ddr3_dqs_p (ddr3_dqs_p), - .ddr3_odt (ddr3_odt), - .ddr3_ras_n (ddr3_ras_n), - .ddr3_reset_n (ddr3_reset_n), - .ddr3_we_n (ddr3_we_n), - .gpio_lcd_tri_io (gpio_lcd), - .gpio0_o (gpio_o[31:0]), - .gpio0_t (gpio_t[31:0]), - .gpio0_i (gpio_i[31:0]), - .gpio1_o (gpio_o[63:32]), - .gpio1_t (gpio_t[63:32]), - .gpio1_i (gpio_i[63:32]), - .iic_main_scl_io (iic_scl), - .iic_main_sda_io (iic_sda), - .mb_intr_06 (1'b0), - .mb_intr_07 (1'b0), - .mb_intr_08 (1'b0), - .mb_intr_14 (1'b0), - .mb_intr_15 (1'b0), - .adc_clk_in_n (adc_clk_in_n), - .adc_clk_in_p (adc_clk_in_p), - .adc_data_in_n (adc_data_in_n), - .adc_data_in_p (adc_data_in_p), - .adc_or_in_n (adc_or_in_n), - .adc_or_in_p (adc_or_in_p), - .dac_clk_in_n (dac_clk_in_n), - .dac_clk_in_p (dac_clk_in_p), - .dac_clk_out_n (dac_clk_out_n), - .dac_clk_out_p (dac_clk_out_p), - .dac_data_out_n (dac_data_out_n), - .dac_data_out_p (dac_data_out_p), - .dac_frame_out_n (dac_frame_out_n), - .dac_frame_out_p (dac_frame_out_p), - .ref_clk (ref_clk), - .mdio_mdio_io (phy_mdio), - .mdio_mdc (phy_mdc), - .phy_rst_n (phy_reset_n), - .rgmii_rd (phy_rx_data), - .rgmii_rx_ctl (phy_rx_ctrl), - .rgmii_rxc (phy_rx_clk), - .rgmii_td (phy_tx_data), - .rgmii_tx_ctl (phy_tx_ctrl), - .rgmii_txc (phy_tx_clk), - .sys_clk_n (sys_clk_n), - .sys_clk_p (sys_clk_p), - .sys_rst (sys_rst), - .uart_sin (uart_sin), - .uart_sout (uart_sout)); -endmodule - -// *************************************************************************** -// *************************************************************************** diff --git a/projects/fmcomms1/common/fmcomms1_bd.tcl b/projects/fmcomms1/common/fmcomms1_bd.tcl deleted file mode 100644 index 826ecaaf8..000000000 --- a/projects/fmcomms1/common/fmcomms1_bd.tcl +++ /dev/null @@ -1,169 +0,0 @@ - - # dac interface - - create_bd_port -dir I dac_clk_in_p - create_bd_port -dir I dac_clk_in_n - create_bd_port -dir O dac_clk_out_p - create_bd_port -dir O dac_clk_out_n - create_bd_port -dir O dac_frame_out_p - create_bd_port -dir O dac_frame_out_n - create_bd_port -dir O -from 15 -to 0 dac_data_out_p - create_bd_port -dir O -from 15 -to 0 dac_data_out_n - - # adc interface - - create_bd_port -dir I adc_clk_in_p - create_bd_port -dir I adc_clk_in_n - create_bd_port -dir I adc_or_in_p - create_bd_port -dir I adc_or_in_n - create_bd_port -dir I -from 13 -to 0 adc_data_in_p - create_bd_port -dir I -from 13 -to 0 adc_data_in_n - - # reference clock - - create_bd_port -dir O ref_clk - - # dac peripherals - - set axi_ad9122 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9122:1.0 axi_ad9122] - - set axi_ad9122_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9122_dma] - set_property -dict [list CONFIG.DMA_TYPE_SRC {0}] $axi_ad9122_dma - set_property -dict [list CONFIG.DMA_TYPE_DEST {2}] $axi_ad9122_dma - set_property -dict [list CONFIG.FIFO_SIZE {16}] $axi_ad9122_dma - set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9122_dma - set_property -dict [list CONFIG.CYCLIC {1}] $axi_ad9122_dma - set_property -dict [list CONFIG.AXI_SLICE_DEST {1}] $axi_ad9122_dma - set_property -dict [list CONFIG.AXI_SLICE_SRC {1}] $axi_ad9122_dma - set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {128}] $axi_ad9122_dma - - set util_upack_ad9122 [create_bd_cell -type ip -vlnv analog.com:user:util_upack:1.0 util_upack_ad9122] - set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {64}] $util_upack_ad9122 - set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $util_upack_ad9122 - - # adc peripherals - - set axi_ad9643 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9643:1.0 axi_ad9643] - - set axi_ad9643_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9643_dma] - set_property -dict [list CONFIG.DMA_TYPE_SRC {2}] $axi_ad9643_dma - set_property -dict [list CONFIG.DMA_TYPE_DEST {0}] $axi_ad9643_dma - set_property -dict [list CONFIG.FIFO_SIZE {16}] $axi_ad9643_dma - set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9643_dma - set_property -dict [list CONFIG.SYNC_TRANSFER_START {1}] $axi_ad9643_dma - set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad9643_dma - set_property -dict [list CONFIG.AXI_SLICE_DEST {1}] $axi_ad9643_dma - set_property -dict [list CONFIG.AXI_SLICE_SRC {1}] $axi_ad9643_dma - set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $axi_ad9643_dma - - set util_cpack_ad9643 [create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 util_cpack_ad9643] - set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {32}] $util_cpack_ad9643 - set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $util_cpack_ad9643 - - set util_ad9643_adc_fifo [create_bd_cell -type ip -vlnv analog.com:user:util_wfifo:1.0 util_ad9643_adc_fifo] - set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $util_ad9643_adc_fifo - set_property -dict [list CONFIG.DIN_ADDRESS_WIDTH {4}] $util_ad9643_adc_fifo - set_property -dict [list CONFIG.DIN_DATA_WIDTH {16}] $util_ad9643_adc_fifo - set_property -dict [list CONFIG.DOUT_DATA_WIDTH {32}] $util_ad9643_adc_fifo - - # reference clock - - set refclk_clkgen [ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.2 refclk_clkgen] - set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {30} ] $refclk_clkgen - set_property -dict [list CONFIG.USE_PHASE_ALIGNMENT {false} ] $refclk_clkgen - set_property -dict [list CONFIG.JITTER_SEL {Min_O_Jitter} ] $refclk_clkgen - set_property -dict [list CONFIG.USE_LOCKED {false} ] $refclk_clkgen - set_property -dict [list CONFIG.USE_RESET {false} ] $refclk_clkgen - - # reference clock connections - - ad_connect sys_200m_clk refclk_clkgen/clk_in1 - ad_connect ref_clk refclk_clkgen/clk_out1 - - # connections (dac) - - ad_connect dac_clk axi_ad9122/dac_div_clk - ad_connect dac_clk axi_ad9122_dma/fifo_rd_clk - ad_connect dac_clk util_upack_ad9122/dac_clk - - ad_connect dac_clk_in_p axi_ad9122/dac_clk_in_p - ad_connect dac_clk_in_n axi_ad9122/dac_clk_in_n - ad_connect dac_clk_out_p axi_ad9122/dac_clk_out_p - ad_connect dac_clk_out_n axi_ad9122/dac_clk_out_n - ad_connect dac_frame_out_p axi_ad9122/dac_frame_out_p - ad_connect dac_frame_out_n axi_ad9122/dac_frame_out_n - ad_connect dac_data_out_p axi_ad9122/dac_data_out_p - ad_connect dac_data_out_n axi_ad9122/dac_data_out_n - - ad_connect axi_ad9122/dac_valid_0 util_upack_ad9122/dac_valid_0 - ad_connect axi_ad9122/dac_enable_0 util_upack_ad9122/dac_enable_0 - ad_connect axi_ad9122/dac_ddata_0 util_upack_ad9122/dac_data_0 - ad_connect axi_ad9122/dac_valid_1 util_upack_ad9122/dac_valid_1 - ad_connect axi_ad9122/dac_enable_1 util_upack_ad9122/dac_enable_1 - ad_connect axi_ad9122/dac_ddata_1 util_upack_ad9122/dac_data_1 - ad_connect axi_ad9122/dac_dunf axi_ad9122_dma/fifo_rd_underflow - - ad_connect util_upack_ad9122/dac_valid axi_ad9122_dma/fifo_rd_en - ad_connect util_upack_ad9122/dac_data axi_ad9122_dma/fifo_rd_dout - ad_connect util_upack_ad9122/dac_sync axi_ad9122/dac_sync_in - - # connections (adc) - - ad_connect adc_clk axi_ad9643/adc_clk - ad_connect adc_clk util_ad9643_adc_fifo/din_clk - ad_connect sys_200m_clk util_cpack_ad9643/adc_clk - ad_connect sys_200m_clk axi_ad9643/delay_clk - ad_connect sys_200m_clk axi_ad9643_dma/fifo_wr_clk - ad_connect sys_200m_clk util_ad9643_adc_fifo/dout_clk - ad_connect adc_rst axi_ad9643/adc_rst - ad_connect adc_rst util_ad9643_adc_fifo/din_rst - ad_connect sys_cpu_resetn util_ad9643_adc_fifo/dout_rstn - ad_connect sys_cpu_reset util_cpack_ad9643/adc_rst - - ad_connect adc_clk_in_p axi_ad9643/adc_clk_in_p - ad_connect adc_clk_in_n axi_ad9643/adc_clk_in_n - ad_connect adc_or_in_p axi_ad9643/adc_or_in_p - ad_connect adc_or_in_n axi_ad9643/adc_or_in_n - ad_connect adc_data_in_p axi_ad9643/adc_data_in_p - ad_connect adc_data_in_n axi_ad9643/adc_data_in_n - - ad_connect axi_ad9643/adc_valid_0 util_ad9643_adc_fifo/din_valid_0 - ad_connect axi_ad9643/adc_enable_0 util_ad9643_adc_fifo/din_enable_0 - ad_connect axi_ad9643/adc_data_0 util_ad9643_adc_fifo/din_data_0 - ad_connect axi_ad9643/adc_valid_1 util_ad9643_adc_fifo/din_valid_1 - ad_connect axi_ad9643/adc_enable_1 util_ad9643_adc_fifo/din_enable_1 - ad_connect axi_ad9643/adc_data_1 util_ad9643_adc_fifo/din_data_1 - - ad_connect util_ad9643_adc_fifo/dout_valid_0 util_cpack_ad9643/adc_valid_0 - ad_connect util_ad9643_adc_fifo/dout_enable_0 util_cpack_ad9643/adc_enable_0 - ad_connect util_ad9643_adc_fifo/dout_data_0 util_cpack_ad9643/adc_data_0 - ad_connect util_ad9643_adc_fifo/dout_valid_1 util_cpack_ad9643/adc_valid_1 - ad_connect util_ad9643_adc_fifo/dout_enable_1 util_cpack_ad9643/adc_enable_1 - ad_connect util_ad9643_adc_fifo/dout_data_1 util_cpack_ad9643/adc_data_1 - - ad_connect util_ad9643_adc_fifo/din_ovf axi_ad9643/adc_dovf - - ad_connect util_cpack_ad9643/adc_valid axi_ad9643_dma/fifo_wr_en - ad_connect util_cpack_ad9643/adc_sync axi_ad9643_dma/fifo_wr_sync - ad_connect util_cpack_ad9643/adc_data axi_ad9643_dma/fifo_wr_din - ad_connect util_ad9643_adc_fifo/dout_ovf axi_ad9643_dma/fifo_wr_overflow - - ad_connect sys_cpu_resetn axi_ad9122_dma/m_src_axi_aresetn - ad_connect sys_cpu_resetn axi_ad9643_dma/m_dest_axi_aresetn - - # address map - - ad_cpu_interconnect 0x74200000 axi_ad9122 - ad_cpu_interconnect 0x79020000 axi_ad9643 - ad_cpu_interconnect 0x7c400000 axi_ad9643_dma - ad_cpu_interconnect 0x7c420000 axi_ad9122_dma - ad_mem_hp1_interconnect sys_200m_clk sys_ps7/S_AXI_HP1 - ad_mem_hp1_interconnect sys_200m_clk axi_ad9643_dma/m_dest_axi - ad_mem_hp2_interconnect sys_200m_clk sys_ps7/S_AXI_HP2 - ad_mem_hp2_interconnect sys_200m_clk axi_ad9122_dma/m_src_axi - - # interrupts - - ad_cpu_interrupt ps-12 mb-12 axi_ad9122_dma/irq - ad_cpu_interrupt ps-13 mb-13 axi_ad9643_dma/irq - diff --git a/projects/fmcomms1/kc705/system_bd.tcl b/projects/fmcomms1/kc705/system_bd.tcl deleted file mode 100644 index 5790fe398..000000000 --- a/projects/fmcomms1/kc705/system_bd.tcl +++ /dev/null @@ -1,4 +0,0 @@ - - source $ad_hdl_dir/projects/common/kc705/kc705_system_bd.tcl - source ../common/fmcomms1_bd.tcl - diff --git a/projects/fmcomms1/kc705/system_constr.xdc b/projects/fmcomms1/kc705/system_constr.xdc deleted file mode 100644 index ccdbcaffe..000000000 --- a/projects/fmcomms1/kc705/system_constr.xdc +++ /dev/null @@ -1,86 +0,0 @@ - -# reference - -set_property -dict {PACKAGE_PIN AB27 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports ref_clk_out_p] ; ## FMC_LPC_LA17_CC_P -set_property -dict {PACKAGE_PIN AC27 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports ref_clk_out_n] ; ## FMC_LPC_LA17_CC_N - -# dac - -set_property -dict {PACKAGE_PIN AF22 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports dac_clk_in_p] ; ## FMC_LPC_CLK0_M2C_P -set_property -dict {PACKAGE_PIN AG23 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports dac_clk_in_n] ; ## FMC_LPC_CLK0_M2C_N -set_property -dict {PACKAGE_PIN AG27 IOSTANDARD LVDS_25} [get_ports dac_clk_out_p] ; ## FMC_LPC_LA21_P -set_property -dict {PACKAGE_PIN AG28 IOSTANDARD LVDS_25} [get_ports dac_clk_out_n] ; ## FMC_LPC_LA21_N -set_property -dict {PACKAGE_PIN AE25 IOSTANDARD LVDS_25} [get_ports dac_frame_out_p] ; ## FMC_LPC_LA11_P -set_property -dict {PACKAGE_PIN AF25 IOSTANDARD LVDS_25} [get_ports dac_frame_out_n] ; ## FMC_LPC_LA11_N -set_property -dict {PACKAGE_PIN Y30 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[0]] ; ## FMC_LPC_LA32_P -set_property -dict {PACKAGE_PIN AA30 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[0]] ; ## FMC_LPC_LA32_N -set_property -dict {PACKAGE_PIN AC29 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[1]] ; ## FMC_LPC_LA33_P -set_property -dict {PACKAGE_PIN AC30 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[1]] ; ## FMC_LPC_LA33_N -set_property -dict {PACKAGE_PIN AB29 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[2]] ; ## FMC_LPC_LA30_P -set_property -dict {PACKAGE_PIN AB30 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[2]] ; ## FMC_LPC_LA30_N -set_property -dict {PACKAGE_PIN AE30 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[3]] ; ## FMC_LPC_LA28_P -set_property -dict {PACKAGE_PIN AF30 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[3]] ; ## FMC_LPC_LA28_N -set_property -dict {PACKAGE_PIN AD29 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[4]] ; ## FMC_LPC_LA31_P -set_property -dict {PACKAGE_PIN AE29 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[4]] ; ## FMC_LPC_LA31_N -set_property -dict {PACKAGE_PIN AE28 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[5]] ; ## FMC_LPC_LA29_P -set_property -dict {PACKAGE_PIN AF28 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[5]] ; ## FMC_LPC_LA29_N -set_property -dict {PACKAGE_PIN AG30 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[6]] ; ## FMC_LPC_LA24_P -set_property -dict {PACKAGE_PIN AH30 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[6]] ; ## FMC_LPC_LA24_N -set_property -dict {PACKAGE_PIN AC26 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[7]] ; ## FMC_LPC_LA25_P -set_property -dict {PACKAGE_PIN AD26 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[7]] ; ## FMC_LPC_LA25_N -set_property -dict {PACKAGE_PIN AJ27 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[8]] ; ## FMC_LPC_LA22_P -set_property -dict {PACKAGE_PIN AK28 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[8]] ; ## FMC_LPC_LA22_N -set_property -dict {PACKAGE_PIN AJ28 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[9]] ; ## FMC_LPC_LA27_P -set_property -dict {PACKAGE_PIN AJ29 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[9]] ; ## FMC_LPC_LA27_N -set_property -dict {PACKAGE_PIN AK29 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[10]] ; ## FMC_LPC_LA26_P -set_property -dict {PACKAGE_PIN AK30 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[10]] ; ## FMC_LPC_LA26_N -set_property -dict {PACKAGE_PIN AH26 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[11]] ; ## FMC_LPC_LA23_P -set_property -dict {PACKAGE_PIN AH27 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[11]] ; ## FMC_LPC_LA23_N -set_property -dict {PACKAGE_PIN AJ26 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[12]] ; ## FMC_LPC_LA19_P -set_property -dict {PACKAGE_PIN AK26 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[12]] ; ## FMC_LPC_LA19_N -set_property -dict {PACKAGE_PIN AF26 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[13]] ; ## FMC_LPC_LA20_P -set_property -dict {PACKAGE_PIN AF27 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[13]] ; ## FMC_LPC_LA20_N -set_property -dict {PACKAGE_PIN AC24 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[14]] ; ## FMC_LPC_LA15_P -set_property -dict {PACKAGE_PIN AD24 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[14]] ; ## FMC_LPC_LA15_N -set_property -dict {PACKAGE_PIN AC22 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[15]] ; ## FMC_LPC_LA16_P -set_property -dict {PACKAGE_PIN AD22 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[15]] ; ## FMC_LPC_LA16_N - -# adc - -set_property -dict {PACKAGE_PIN AG29 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_clk_in_p] ; ## FMC_LPC_CLK1_M2C_P -set_property -dict {PACKAGE_PIN AH29 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_clk_in_n] ; ## FMC_LPC_CLK1_M2C_N -set_property -dict {PACKAGE_PIN AD23 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_or_in_p] ; ## FMC_LPC_LA00_CC_P -set_property -dict {PACKAGE_PIN AE24 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_or_in_n] ; ## FMC_LPC_LA00_CC_N -set_property -dict {PACKAGE_PIN AD27 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[0]] ; ## FMC_LPC_LA18_CC_P -set_property -dict {PACKAGE_PIN AD28 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[0]] ; ## FMC_LPC_LA18_CC_N -set_property -dict {PACKAGE_PIN AD21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[1]] ; ## FMC_LPC_LA14_P -set_property -dict {PACKAGE_PIN AE21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[1]] ; ## FMC_LPC_LA14_N -set_property -dict {PACKAGE_PIN AB24 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[2]] ; ## FMC_LPC_LA13_P -set_property -dict {PACKAGE_PIN AC25 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[2]] ; ## FMC_LPC_LA13_N -set_property -dict {PACKAGE_PIN AG20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[3]] ; ## FMC_LPC_LA03_P -set_property -dict {PACKAGE_PIN AH20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[3]] ; ## FMC_LPC_LA03_N -set_property -dict {PACKAGE_PIN AG22 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[4]] ; ## FMC_LPC_LA05_P -set_property -dict {PACKAGE_PIN AH22 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[4]] ; ## FMC_LPC_LA05_N -set_property -dict {PACKAGE_PIN AJ24 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[5]] ; ## FMC_LPC_LA10_P -set_property -dict {PACKAGE_PIN AK25 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[5]] ; ## FMC_LPC_LA10_N -set_property -dict {PACKAGE_PIN AA20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[6]] ; ## FMC_LPC_LA12_P -set_property -dict {PACKAGE_PIN AB20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[6]] ; ## FMC_LPC_LA12_N -set_property -dict {PACKAGE_PIN AG25 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[7]] ; ## FMC_LPC_LA07_P -set_property -dict {PACKAGE_PIN AH25 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[7]] ; ## FMC_LPC_LA07_N -set_property -dict {PACKAGE_PIN AF20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[8]] ; ## FMC_LPC_LA02_P -set_property -dict {PACKAGE_PIN AF21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[8]] ; ## FMC_LPC_LA02_N -set_property -dict {PACKAGE_PIN AH21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[9]] ; ## FMC_LPC_LA04_P -set_property -dict {PACKAGE_PIN AJ21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[9]] ; ## FMC_LPC_LA04_N -set_property -dict {PACKAGE_PIN AK23 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[10]] ; ## FMC_LPC_LA09_P -set_property -dict {PACKAGE_PIN AK24 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[10]] ; ## FMC_LPC_LA09_N -set_property -dict {PACKAGE_PIN AJ22 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[11]] ; ## FMC_LPC_LA08_P -set_property -dict {PACKAGE_PIN AJ23 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[11]] ; ## FMC_LPC_LA08_N -set_property -dict {PACKAGE_PIN AK20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[12]] ; ## FMC_LPC_LA06_P -set_property -dict {PACKAGE_PIN AK21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[12]] ; ## FMC_LPC_LA06_N -set_property -dict {PACKAGE_PIN AE23 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[13]] ; ## FMC_LPC_LA01_CC_P -set_property -dict {PACKAGE_PIN AF23 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[13]] ; ## FMC_LPC_LA01_CC_N - -# clocks - -create_clock -name dac_clk_in -period 2.00 [get_ports dac_clk_in_p] -create_clock -name adc_clk_in -period 4.00 [get_ports adc_clk_in_p] diff --git a/projects/fmcomms1/kc705/system_project.tcl b/projects/fmcomms1/kc705/system_project.tcl deleted file mode 100644 index 1c30388e3..000000000 --- a/projects/fmcomms1/kc705/system_project.tcl +++ /dev/null @@ -1,18 +0,0 @@ - -source ../../scripts/adi_env.tcl -source $ad_hdl_dir/projects/scripts/adi_project.tcl -source $ad_hdl_dir/projects/scripts/adi_board.tcl - -adi_project_create fmcomms1_kc705 -adi_project_files fmcomms1_kc705 [list \ - "system_top.v" \ - "system_constr.xdc"\ - "$ad_hdl_dir/library/common/ad_iobuf.v" \ - "$ad_hdl_dir/projects/common/kc705/kc705_system_constr.xdc" ] - -set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/kc705/kc705_system_constr.xdc] -set_property PROCESSING_ORDER EARLY [get_files system_constr.xdc] - -adi_project_run fmcomms1_kc705 - - diff --git a/projects/fmcomms1/kc705/system_top.v b/projects/fmcomms1/kc705/system_top.v deleted file mode 100644 index b0a73e89c..000000000 --- a/projects/fmcomms1/kc705/system_top.v +++ /dev/null @@ -1,316 +0,0 @@ -// *************************************************************************** -// *************************************************************************** -// Copyright 2011(c) Analog Devices, Inc. -// -// All rights reserved. -// -// Redistribution and use in source and binary forms, with or without modification, -// are permitted provided that the following conditions are met: -// - Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// - Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in -// the documentation and/or other materials provided with the -// distribution. -// - Neither the name of Analog Devices, Inc. nor the names of its -// contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// - The use of this software may or may not infringe the patent rights -// of one or more patent holders. This license does not release you -// from the requirement that you obtain separate licenses from these -// patent holders to use this software. -// - Use of the software either in source or binary form, must be run -// on or directly connected to an Analog Devices Inc. component. -// -// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, -// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A -// PARTICULAR PURPOSE ARE DISCLAIMED. -// -// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY -// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF -// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// *************************************************************************** -// *************************************************************************** -// *************************************************************************** -// *************************************************************************** - -`timescale 1ns/100ps - -module system_top ( - - sys_rst, - sys_clk_p, - sys_clk_n, - - uart_sin, - uart_sout, - - ddr3_1_n, - ddr3_1_p, - ddr3_reset_n, - ddr3_addr, - ddr3_ba, - ddr3_cas_n, - ddr3_ras_n, - ddr3_we_n, - ddr3_ck_n, - ddr3_ck_p, - ddr3_cke, - ddr3_cs_n, - ddr3_dm, - ddr3_dq, - ddr3_dqs_n, - ddr3_dqs_p, - ddr3_odt, - - mdio_mdc, - mdio_mdio, - mii_rst_n, - mii_col, - mii_crs, - mii_rx_clk, - mii_rx_er, - mii_rx_dv, - mii_rxd, - mii_tx_clk, - mii_tx_en, - mii_txd, - - linear_flash_addr, - linear_flash_adv_ldn, - linear_flash_ce_n, - linear_flash_dq_io, - linear_flash_oen, - linear_flash_wen, - - fan_pwm, - - gpio_lcd, - gpio_bd, - - iic_rstn, - iic_scl, - iic_sda, - - dac_clk_in_p, - dac_clk_in_n, - dac_clk_out_p, - dac_clk_out_n, - dac_frame_out_p, - dac_frame_out_n, - dac_data_out_p, - dac_data_out_n, - - adc_clk_in_p, - adc_clk_in_n, - adc_or_in_p, - adc_or_in_n, - adc_data_in_p, - adc_data_in_n, - - ref_clk_out_p, - ref_clk_out_n); - - input sys_rst; - input sys_clk_p; - input sys_clk_n; - - input uart_sin; - output uart_sout; - - output [ 2:0] ddr3_1_n; - output [ 1:0] ddr3_1_p; - output ddr3_reset_n; - output [13:0] ddr3_addr; - output [ 2:0] ddr3_ba; - output ddr3_cas_n; - output ddr3_ras_n; - output ddr3_we_n; - output [ 0:0] ddr3_ck_n; - output [ 0:0] ddr3_ck_p; - output [ 0:0] ddr3_cke; - output [ 0:0] ddr3_cs_n; - output [ 7:0] ddr3_dm; - inout [63:0] ddr3_dq; - inout [ 7:0] ddr3_dqs_n; - inout [ 7:0] ddr3_dqs_p; - output [ 0:0] ddr3_odt; - - output mdio_mdc; - inout mdio_mdio; - output mii_rst_n; - input mii_col; - input mii_crs; - input mii_rx_clk; - input mii_rx_er; - input mii_rx_dv; - input [ 3:0] mii_rxd; - input mii_tx_clk; - output mii_tx_en; - output [ 3:0] mii_txd; - - output [26:1] linear_flash_addr; - output linear_flash_adv_ldn; - output linear_flash_ce_n; - inout [15:0] linear_flash_dq_io; - output linear_flash_oen; - output linear_flash_wen; - - output fan_pwm; - - inout [ 6:0] gpio_lcd; - inout [16:0] gpio_bd; - - output iic_rstn; - inout iic_scl; - inout iic_sda; - - input dac_clk_in_p; - input dac_clk_in_n; - output dac_clk_out_p; - output dac_clk_out_n; - output dac_frame_out_p; - output dac_frame_out_n; - output [15:0] dac_data_out_p; - output [15:0] dac_data_out_n; - - input adc_clk_in_p; - input adc_clk_in_n; - input adc_or_in_p; - input adc_or_in_n; - input [13:0] adc_data_in_p; - input [13:0] adc_data_in_n; - - output ref_clk_out_p; - output ref_clk_out_n; - - // internal signals - - wire [63:0] gpio_i; - wire [63:0] gpio_o; - wire [63:0] gpio_t; - wire [ 7:0] spi_csn; - wire spi_clk; - wire spi_mosi; - wire spi_miso; - wire ref_clk; - wire oddr_ref_clk; - - // default logic - - assign ddr3_1_p = 2'b11; - assign ddr3_1_n = 3'b000; - assign fan_pwm = 1'b1; - assign iic_rstn = 1'b1; - - // instantiations - - ODDR #( - .DDR_CLK_EDGE ("SAME_EDGE"), - .INIT (1'b0), - .SRTYPE ("ASYNC")) - i_oddr_ref_clk ( - .S (1'b0), - .CE (1'b1), - .R (1'b0), - .C (ref_clk), - .D1 (1'b1), - .D2 (1'b0), - .Q (oddr_ref_clk)); - - OBUFDS i_obufds_ref_clk ( - .I (oddr_ref_clk), - .O (ref_clk_out_p), - .OB (ref_clk_out_n)); - - ad_iobuf #(.DATA_WIDTH(17)) i_iobuf_bd ( - .dio_t (gpio_t[16:0]), - .dio_i (gpio_o[16:0]), - .dio_o (gpio_i[16:0]), - .dio_p (gpio_bd)); - - system_wrapper i_system_wrapper ( - .ddr3_addr (ddr3_addr), - .ddr3_ba (ddr3_ba), - .ddr3_cas_n (ddr3_cas_n), - .ddr3_ck_n (ddr3_ck_n), - .ddr3_ck_p (ddr3_ck_p), - .ddr3_cke (ddr3_cke), - .ddr3_cs_n (ddr3_cs_n), - .ddr3_dm (ddr3_dm), - .ddr3_dq (ddr3_dq), - .ddr3_dqs_n (ddr3_dqs_n), - .ddr3_dqs_p (ddr3_dqs_p), - .ddr3_odt (ddr3_odt), - .ddr3_ras_n (ddr3_ras_n), - .ddr3_reset_n (ddr3_reset_n), - .ddr3_we_n (ddr3_we_n), - .gpio0_i (gpio_i[31:0]), - .gpio0_o (gpio_o[31:0]), - .gpio0_t (gpio_t[31:0]), - .gpio1_i (gpio_i[63:32]), - .gpio1_o (gpio_o[63:32]), - .gpio1_t (gpio_t[63:32]), - .gpio_lcd_tri_io (gpio_lcd), - .adc_clk_in_n (adc_clk_in_n), - .adc_clk_in_p (adc_clk_in_p), - .adc_data_in_n (adc_data_in_n), - .adc_data_in_p (adc_data_in_p), - .adc_or_in_n (adc_or_in_n), - .adc_or_in_p (adc_or_in_p), - .dac_clk_in_n (dac_clk_in_n), - .dac_clk_in_p (dac_clk_in_p), - .dac_clk_out_n (dac_clk_out_n), - .dac_clk_out_p (dac_clk_out_p), - .dac_data_out_n (dac_data_out_n), - .dac_data_out_p (dac_data_out_p), - .dac_frame_out_n (dac_frame_out_n), - .dac_frame_out_p (dac_frame_out_p), - .ref_clk (ref_clk), - .iic_main_scl_io (iic_scl), - .iic_main_sda_io (iic_sda), - .mb_intr_02 (1'd0), - .mb_intr_03 (1'd0), - .mb_intr_06 (1'd0), - .mb_intr_07 (1'd0), - .mb_intr_08 (1'd0), - .mb_intr_14 (1'd0), - .mb_intr_15 (1'd0), - .mdio_mdc (mdio_mdc), - .mdio_mdio_io (mdio_mdio), - .mii_col (mii_col), - .mii_crs (mii_crs), - .mii_rst_n (mii_rst_n), - .mii_rx_clk (mii_rx_clk), - .mii_rx_dv (mii_rx_dv), - .mii_rx_er (mii_rx_er), - .mii_rxd (mii_rxd), - .mii_tx_clk (mii_tx_clk), - .mii_tx_en (mii_tx_en), - .mii_txd (mii_txd), - .linear_flash_addr (linear_flash_addr), - .linear_flash_adv_ldn (linear_flash_adv_ldn), - .linear_flash_ce_n (linear_flash_ce_n), - .linear_flash_dq_io (linear_flash_dq_io), - .linear_flash_oen (linear_flash_oen), - .linear_flash_wen (linear_flash_wen), - .spi_clk_i (spi_clk), - .spi_clk_o (spi_clk), - .spi_csn_i (spi_csn), - .spi_csn_o (spi_csn), - .spi_sdi_i (spi_miso), - .spi_sdo_i (spi_mosi), - .spi_sdo_o (spi_mosi), - .sys_clk_n (sys_clk_n), - .sys_clk_p (sys_clk_p), - .sys_rst (sys_rst), - .uart_sin (uart_sin), - .uart_sout (uart_sout)); - -endmodule - -// *************************************************************************** -// *************************************************************************** diff --git a/projects/fmcomms1/vc707/system_bd.tcl b/projects/fmcomms1/vc707/system_bd.tcl deleted file mode 100644 index 4fd21b543..000000000 --- a/projects/fmcomms1/vc707/system_bd.tcl +++ /dev/null @@ -1,4 +0,0 @@ - - source $ad_hdl_dir/projects/common/vc707/vc707_system_bd.tcl - source ../common/fmcomms1_bd.tcl - diff --git a/projects/fmcomms1/vc707/system_constr.xdc b/projects/fmcomms1/vc707/system_constr.xdc deleted file mode 100644 index 083d2f1a1..000000000 --- a/projects/fmcomms1/vc707/system_constr.xdc +++ /dev/null @@ -1,86 +0,0 @@ - -# reference - -set_property -dict {PACKAGE_PIN U37 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports ref_clk_out_p] ; ## FMC_LPC_LA17_CC_P -set_property -dict {PACKAGE_PIN U38 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports ref_clk_out_n] ; ## FMC_LPC_LA17_CC_N - -# dac - -set_property -dict {PACKAGE_PIN AF39 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports dac_clk_in_p] ; ## FMC_LPC_CLK0_M2C_P -set_property -dict {PACKAGE_PIN AF40 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports dac_clk_in_n] ; ## FMC_LPC_CLK0_M2C_N -set_property -dict {PACKAGE_PIN P35 IOSTANDARD LVDS} [get_ports dac_clk_out_p] ; ## FMC_LPC_LA21_P -set_property -dict {PACKAGE_PIN P36 IOSTANDARD LVDS} [get_ports dac_clk_out_n] ; ## FMC_LPC_LA21_N -set_property -dict {PACKAGE_PIN Y42 IOSTANDARD LVDS} [get_ports dac_frame_out_p] ; ## FMC_LPC_LA11_P -set_property -dict {PACKAGE_PIN AA42 IOSTANDARD LVDS} [get_ports dac_frame_out_n] ; ## FMC_LPC_LA11_N -set_property -dict {PACKAGE_PIN P37 IOSTANDARD LVDS} [get_ports dac_data_out_p[0]] ; ## FMC_LPC_LA32_P -set_property -dict {PACKAGE_PIN P38 IOSTANDARD LVDS} [get_ports dac_data_out_n[0]] ; ## FMC_LPC_LA32_N -set_property -dict {PACKAGE_PIN T36 IOSTANDARD LVDS} [get_ports dac_data_out_p[1]] ; ## FMC_LPC_LA33_P -set_property -dict {PACKAGE_PIN R37 IOSTANDARD LVDS} [get_ports dac_data_out_n[1]] ; ## FMC_LPC_LA33_N -set_property -dict {PACKAGE_PIN T32 IOSTANDARD LVDS} [get_ports dac_data_out_p[2]] ; ## FMC_LPC_LA30_P -set_property -dict {PACKAGE_PIN R32 IOSTANDARD LVDS} [get_ports dac_data_out_n[2]] ; ## FMC_LPC_LA30_N -set_property -dict {PACKAGE_PIN V35 IOSTANDARD LVDS} [get_ports dac_data_out_p[3]] ; ## FMC_LPC_LA28_P -set_property -dict {PACKAGE_PIN V36 IOSTANDARD LVDS} [get_ports dac_data_out_n[3]] ; ## FMC_LPC_LA28_N -set_property -dict {PACKAGE_PIN V39 IOSTANDARD LVDS} [get_ports dac_data_out_p[4]] ; ## FMC_LPC_LA31_P -set_property -dict {PACKAGE_PIN V40 IOSTANDARD LVDS} [get_ports dac_data_out_n[4]] ; ## FMC_LPC_LA31_N -set_property -dict {PACKAGE_PIN W36 IOSTANDARD LVDS} [get_ports dac_data_out_p[5]] ; ## FMC_LPC_LA29_P -set_property -dict {PACKAGE_PIN W37 IOSTANDARD LVDS} [get_ports dac_data_out_n[5]] ; ## FMC_LPC_LA29_N -set_property -dict {PACKAGE_PIN U34 IOSTANDARD LVDS} [get_ports dac_data_out_p[6]] ; ## FMC_LPC_LA24_P -set_property -dict {PACKAGE_PIN T35 IOSTANDARD LVDS} [get_ports dac_data_out_n[6]] ; ## FMC_LPC_LA24_N -set_property -dict {PACKAGE_PIN R33 IOSTANDARD LVDS} [get_ports dac_data_out_p[7]] ; ## FMC_LPC_LA25_P -set_property -dict {PACKAGE_PIN R34 IOSTANDARD LVDS} [get_ports dac_data_out_n[7]] ; ## FMC_LPC_LA25_N -set_property -dict {PACKAGE_PIN W32 IOSTANDARD LVDS} [get_ports dac_data_out_p[8]] ; ## FMC_LPC_LA22_P -set_property -dict {PACKAGE_PIN W33 IOSTANDARD LVDS} [get_ports dac_data_out_n[8]] ; ## FMC_LPC_LA22_N -set_property -dict {PACKAGE_PIN P32 IOSTANDARD LVDS} [get_ports dac_data_out_p[9]] ; ## FMC_LPC_LA27_P -set_property -dict {PACKAGE_PIN P33 IOSTANDARD LVDS} [get_ports dac_data_out_n[9]] ; ## FMC_LPC_LA27_N -set_property -dict {PACKAGE_PIN N33 IOSTANDARD LVDS} [get_ports dac_data_out_p[10]] ; ## FMC_LPC_LA26_P -set_property -dict {PACKAGE_PIN N34 IOSTANDARD LVDS} [get_ports dac_data_out_n[10]] ; ## FMC_LPC_LA26_N -set_property -dict {PACKAGE_PIN R38 IOSTANDARD LVDS} [get_ports dac_data_out_p[11]] ; ## FMC_LPC_LA23_P -set_property -dict {PACKAGE_PIN R39 IOSTANDARD LVDS} [get_ports dac_data_out_n[11]] ; ## FMC_LPC_LA23_N -set_property -dict {PACKAGE_PIN U32 IOSTANDARD LVDS} [get_ports dac_data_out_p[12]] ; ## FMC_LPC_LA19_P -set_property -dict {PACKAGE_PIN U33 IOSTANDARD LVDS} [get_ports dac_data_out_n[12]] ; ## FMC_LPC_LA19_N -set_property -dict {PACKAGE_PIN V33 IOSTANDARD LVDS} [get_ports dac_data_out_p[13]] ; ## FMC_LPC_LA20_P -set_property -dict {PACKAGE_PIN V34 IOSTANDARD LVDS} [get_ports dac_data_out_n[13]] ; ## FMC_LPC_LA20_N -set_property -dict {PACKAGE_PIN AC38 IOSTANDARD LVDS} [get_ports dac_data_out_p[14]] ; ## FMC_LPC_LA15_P -set_property -dict {PACKAGE_PIN AC39 IOSTANDARD LVDS} [get_ports dac_data_out_n[14]] ; ## FMC_LPC_LA15_N -set_property -dict {PACKAGE_PIN AJ40 IOSTANDARD LVDS} [get_ports dac_data_out_p[15]] ; ## FMC_LPC_LA16_P -set_property -dict {PACKAGE_PIN AJ41 IOSTANDARD LVDS} [get_ports dac_data_out_n[15]] ; ## FMC_LPC_LA16_N - -# adc - -set_property -dict {PACKAGE_PIN U39 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_clk_in_p] ; ## FMC_LPC_CLK1_M2C_P -set_property -dict {PACKAGE_PIN T39 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_clk_in_n] ; ## FMC_LPC_CLK1_M2C_N -set_property -dict {PACKAGE_PIN AD40 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_or_in_p] ; ## FMC_LPC_LA00_CC_P -set_property -dict {PACKAGE_PIN AD41 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_or_in_n] ; ## FMC_LPC_LA00_CC_N -set_property -dict {PACKAGE_PIN U36 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_p[0]] ; ## FMC_LPC_LA18_CC_P -set_property -dict {PACKAGE_PIN T37 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_n[0]] ; ## FMC_LPC_LA18_CC_N -set_property -dict {PACKAGE_PIN AB38 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_p[1]] ; ## FMC_LPC_LA14_P -set_property -dict {PACKAGE_PIN AB39 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_n[1]] ; ## FMC_LPC_LA14_N -set_property -dict {PACKAGE_PIN W40 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_p[2]] ; ## FMC_LPC_LA13_P -set_property -dict {PACKAGE_PIN Y40 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_n[2]] ; ## FMC_LPC_LA13_N -set_property -dict {PACKAGE_PIN AJ42 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_p[3]] ; ## FMC_LPC_LA03_P -set_property -dict {PACKAGE_PIN AK42 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_n[3]] ; ## FMC_LPC_LA03_N -set_property -dict {PACKAGE_PIN AF42 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_p[4]] ; ## FMC_LPC_LA05_P -set_property -dict {PACKAGE_PIN AG42 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_n[4]] ; ## FMC_LPC_LA05_N -set_property -dict {PACKAGE_PIN AB41 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_p[5]] ; ## FMC_LPC_LA10_P -set_property -dict {PACKAGE_PIN AB42 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_n[5]] ; ## FMC_LPC_LA10_N -set_property -dict {PACKAGE_PIN Y39 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_p[6]] ; ## FMC_LPC_LA12_P -set_property -dict {PACKAGE_PIN AA39 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_n[6]] ; ## FMC_LPC_LA12_N -set_property -dict {PACKAGE_PIN AC40 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_p[7]] ; ## FMC_LPC_LA07_P -set_property -dict {PACKAGE_PIN AC41 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_n[7]] ; ## FMC_LPC_LA07_N -set_property -dict {PACKAGE_PIN AK39 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_p[8]] ; ## FMC_LPC_LA02_P -set_property -dict {PACKAGE_PIN AL39 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_n[8]] ; ## FMC_LPC_LA02_N -set_property -dict {PACKAGE_PIN AL41 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_p[9]] ; ## FMC_LPC_LA04_P -set_property -dict {PACKAGE_PIN AL42 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_n[9]] ; ## FMC_LPC_LA04_N -set_property -dict {PACKAGE_PIN AJ38 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_p[10]] ; ## FMC_LPC_LA09_P -set_property -dict {PACKAGE_PIN AK38 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_n[10]] ; ## FMC_LPC_LA09_N -set_property -dict {PACKAGE_PIN AD42 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_p[11]] ; ## FMC_LPC_LA08_P -set_property -dict {PACKAGE_PIN AE42 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_n[11]] ; ## FMC_LPC_LA08_N -set_property -dict {PACKAGE_PIN AD38 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_p[12]] ; ## FMC_LPC_LA06_P -set_property -dict {PACKAGE_PIN AE38 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_n[12]] ; ## FMC_LPC_LA06_N -set_property -dict {PACKAGE_PIN AF41 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_p[13]] ; ## FMC_LPC_LA01_CC_P -set_property -dict {PACKAGE_PIN AG41 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_n[13]] ; ## FMC_LPC_LA01_CC_N - -# clocks - -create_clock -name dac_clk_in -period 2.00 [get_ports dac_clk_in_p] -create_clock -name adc_clk_in -period 4.00 [get_ports adc_clk_in_p] diff --git a/projects/fmcomms1/vc707/system_project.tcl b/projects/fmcomms1/vc707/system_project.tcl deleted file mode 100644 index bebf0029a..000000000 --- a/projects/fmcomms1/vc707/system_project.tcl +++ /dev/null @@ -1,18 +0,0 @@ - -source ../../scripts/adi_env.tcl -source $ad_hdl_dir/projects/scripts/adi_project.tcl -source $ad_hdl_dir/projects/scripts/adi_board.tcl - -adi_project_create fmcomms1_vc707 -adi_project_files fmcomms1_vc707 [list \ - "system_top.v" \ - "system_constr.xdc"\ - "$ad_hdl_dir/library/common/ad_iobuf.v" \ - "$ad_hdl_dir/projects/common/vc707/vc707_system_constr.xdc" ] - -set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/vc707/vc707_system_constr.xdc] -set_property PROCESSING_ORDER EARLY [get_files system_constr.xdc] - -adi_project_run fmcomms1_vc707 - - diff --git a/projects/fmcomms1/vc707/system_top.v b/projects/fmcomms1/vc707/system_top.v deleted file mode 100644 index 23d006bfe..000000000 --- a/projects/fmcomms1/vc707/system_top.v +++ /dev/null @@ -1,302 +0,0 @@ -// *************************************************************************** -// *************************************************************************** -// Copyright 2011(c) Analog Devices, Inc. -// -// All rights reserved. -// -// Redistribution and use in source and binary forms, with or without modification, -// are permitted provided that the following conditions are met: -// - Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// - Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in -// the documentation and/or other materials provided with the -// distribution. -// - Neither the name of Analog Devices, Inc. nor the names of its -// contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// - The use of this software may or may not infringe the patent rights -// of one or more patent holders. This license does not release you -// from the requirement that you obtain separate licenses from these -// patent holders to use this software. -// - Use of the software either in source or binary form, must be run -// on or directly connected to an Analog Devices Inc. component. -// -// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, -// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A -// PARTICULAR PURPOSE ARE DISCLAIMED. -// -// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY -// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF -// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// *************************************************************************** -// *************************************************************************** -// *************************************************************************** -// *************************************************************************** - -`timescale 1ns/100ps - -module system_top ( - - sys_rst, - sys_clk_p, - sys_clk_n, - - uart_sin, - uart_sout, - - ddr3_addr, - ddr3_ba, - ddr3_cas_n, - ddr3_ck_n, - ddr3_ck_p, - ddr3_cke, - ddr3_cs_n, - ddr3_dm, - ddr3_dq, - ddr3_dqs_n, - ddr3_dqs_p, - ddr3_odt, - ddr3_ras_n, - ddr3_reset_n, - ddr3_we_n, - - sgmii_rxp, - sgmii_rxn, - sgmii_txp, - sgmii_txn, - - phy_rstn, - mgt_clk_p, - mgt_clk_n, - mdio_mdc, - mdio_mdio, - - fan_pwm, - - linear_flash_addr, - linear_flash_adv_ldn, - linear_flash_ce_n, - linear_flash_oen, - linear_flash_wen, - linear_flash_dq_io, - - gpio_lcd, - gpio_bd, - - iic_rstn, - iic_scl, - iic_sda, - - dac_clk_in_p, - dac_clk_in_n, - dac_clk_out_p, - dac_clk_out_n, - dac_frame_out_p, - dac_frame_out_n, - dac_data_out_p, - dac_data_out_n, - - adc_clk_in_p, - adc_clk_in_n, - adc_or_in_p, - adc_or_in_n, - adc_data_in_p, - adc_data_in_n, - - ref_clk_out_p, - ref_clk_out_n ); - - input sys_rst; - input sys_clk_p; - input sys_clk_n; - - input uart_sin; - output uart_sout; - - output [13:0] ddr3_addr; - output [ 2:0] ddr3_ba; - output ddr3_cas_n; - output [ 0:0] ddr3_ck_n; - output [ 0:0] ddr3_ck_p; - output [ 0:0] ddr3_cke; - output [ 0:0] ddr3_cs_n; - output [ 7:0] ddr3_dm; - inout [63:0] ddr3_dq; - inout [ 7:0] ddr3_dqs_n; - inout [ 7:0] ddr3_dqs_p; - output [ 0:0] ddr3_odt; - output ddr3_ras_n; - output ddr3_reset_n; - output ddr3_we_n; - - input sgmii_rxp; - input sgmii_rxn; - output sgmii_txp; - output sgmii_txn; - - output phy_rstn; - input mgt_clk_p; - input mgt_clk_n; - output mdio_mdc; - inout mdio_mdio; - - output fan_pwm; - - output [26:1] linear_flash_addr; - output linear_flash_adv_ldn; - output linear_flash_ce_n; - output linear_flash_oen; - output linear_flash_wen; - inout [15:0] linear_flash_dq_io; - - inout [ 6:0] gpio_lcd; - inout [20:0] gpio_bd; - - output iic_rstn; - inout iic_scl; - inout iic_sda; - - input dac_clk_in_p; - input dac_clk_in_n; - output dac_clk_out_p; - output dac_clk_out_n; - output dac_frame_out_p; - output dac_frame_out_n; - output [15:0] dac_data_out_p; - output [15:0] dac_data_out_n; - - input adc_clk_in_p; - input adc_clk_in_n; - input adc_or_in_p; - input adc_or_in_n; - input [13:0] adc_data_in_p; - input [13:0] adc_data_in_n; - - output ref_clk_out_p; - output ref_clk_out_n; - - // internal signals - - wire [63:0] gpio_i; - wire [63:0] gpio_o; - wire [63:0] gpio_t; - wire [ 7:0] spi_csn; - wire spi_clk; - wire spi_mosi; - wire spi_miso; - wire ref_clk; - wire oddr_ref_clk; - - // assignments - - assign fan_pwm = 1'b1; - assign iic_rstn = 1'b1; - - // instantiations - - ODDR #( - .DDR_CLK_EDGE ("SAME_EDGE"), - .INIT (1'b0), - .SRTYPE ("ASYNC")) - i_oddr_ref_clk ( - .S (1'b0), - .CE (1'b1), - .R (1'b0), - .C (ref_clk), - .D1 (1'b1), - .D2 (1'b0), - .Q (oddr_ref_clk)); - - OBUFDS i_obufds_ref_clk ( - .I (oddr_ref_clk), - .O (ref_clk_out_p), - .OB (ref_clk_out_n)); - - ad_iobuf #(.DATA_WIDTH(21)) i_iobuf_sw_led ( - .dio_t (gpio_t[20:0]), - .dio_i (gpio_o[20:0]), - .dio_o (gpio_i[20:0]), - .dio_p (gpio_bd)); - - system_wrapper i_system_wrapper ( - .ddr3_addr (ddr3_addr), - .ddr3_ba (ddr3_ba), - .ddr3_cas_n (ddr3_cas_n), - .ddr3_ck_n (ddr3_ck_n), - .ddr3_ck_p (ddr3_ck_p), - .ddr3_cke (ddr3_cke), - .ddr3_cs_n (ddr3_cs_n), - .ddr3_dm (ddr3_dm), - .ddr3_dq (ddr3_dq), - .ddr3_dqs_n (ddr3_dqs_n), - .ddr3_dqs_p (ddr3_dqs_p), - .ddr3_odt (ddr3_odt), - .ddr3_ras_n (ddr3_ras_n), - .ddr3_reset_n (ddr3_reset_n), - .ddr3_we_n (ddr3_we_n), - .iic_main_scl_io (iic_scl), - .iic_main_sda_io (iic_sda), - .linear_flash_addr (linear_flash_addr), - .linear_flash_adv_ldn (linear_flash_adv_ldn), - .linear_flash_ce_n (linear_flash_ce_n), - .linear_flash_oen (linear_flash_oen), - .linear_flash_wen (linear_flash_wen), - .linear_flash_dq_io(linear_flash_dq_io), - .gpio0_i (gpio_i[31:0]), - .gpio0_o (gpio_o[31:0]), - .gpio0_t (gpio_t[31:0]), - .gpio1_i (gpio_i[63:32]), - .gpio1_o (gpio_o[63:32]), - .gpio1_t (gpio_t[63:32]), - .gpio_lcd_tri_io (gpio_lcd), - .adc_clk_in_n (adc_clk_in_n), - .adc_clk_in_p (adc_clk_in_p), - .adc_data_in_n (adc_data_in_n), - .adc_data_in_p (adc_data_in_p), - .adc_or_in_n (adc_or_in_n), - .adc_or_in_p (adc_or_in_p), - .dac_clk_in_n (dac_clk_in_n), - .dac_clk_in_p (dac_clk_in_p), - .dac_clk_out_n (dac_clk_out_n), - .dac_clk_out_p (dac_clk_out_p), - .dac_data_out_n (dac_data_out_n), - .dac_data_out_p (dac_data_out_p), - .dac_frame_out_n (dac_frame_out_n), - .dac_frame_out_p (dac_frame_out_p), - .ref_clk (ref_clk), - .mb_intr_06 (1'b0), - .mb_intr_07 (1'b0), - .mb_intr_08 (1'b0), - .mb_intr_14 (1'b0), - .mb_intr_15 (1'b0), - .mdio_mdc (mdio_mdc), - .mdio_mdio_io (mdio_mdio), - .mgt_clk_clk_n (mgt_clk_n), - .mgt_clk_clk_p (mgt_clk_p), - .phy_rstn (phy_rstn), - .phy_sd (1'b1), - .sgmii_rxn (sgmii_rxn), - .sgmii_rxp (sgmii_rxp), - .sgmii_txn (sgmii_txn), - .sgmii_txp (sgmii_txp), - .spi_clk_i (1'b0), - .spi_clk_o (spi_clk), - .spi_csn_i (8'hff), - .spi_csn_o (spi_csn), - .spi_sdi_i (spi_miso), - .spi_sdo_i (1'b0), - .spi_sdo_o (spi_mosi), - .sys_clk_n (sys_clk_n), - .sys_clk_p (sys_clk_p), - .sys_rst (sys_rst), - .uart_sin (uart_sin), - .uart_sout (uart_sout)); - -endmodule - -// *************************************************************************** -// *************************************************************************** diff --git a/projects/fmcomms1/zc702/system_bd.tcl b/projects/fmcomms1/zc702/system_bd.tcl deleted file mode 100644 index 053c55f62..000000000 --- a/projects/fmcomms1/zc702/system_bd.tcl +++ /dev/null @@ -1,5 +0,0 @@ - - source $ad_hdl_dir/projects/common/zc702/zc702_system_bd.tcl - source ../common/fmcomms1_bd.tcl - - diff --git a/projects/fmcomms1/zc702/system_constr.xdc b/projects/fmcomms1/zc702/system_constr.xdc deleted file mode 100644 index 594ec0d6a..000000000 --- a/projects/fmcomms1/zc702/system_constr.xdc +++ /dev/null @@ -1,86 +0,0 @@ - -# reference - -set_property -dict {PACKAGE_PIN B19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports ref_clk_out_p] ; ## FMC1_LPC_LA17_CC_P -set_property -dict {PACKAGE_PIN B20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports ref_clk_out_n] ; ## FMC1_LPC_LA17_CC_N - -# dac - -set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports dac_clk_in_p] ; ## FMC1_LPC_CLK0_M2C_P -set_property -dict {PACKAGE_PIN L19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports dac_clk_in_n] ; ## FMC1_LPC_CLK0_M2C_N -set_property -dict {PACKAGE_PIN F21 IOSTANDARD LVDS_25} [get_ports dac_clk_out_p] ; ## FMC1_LPC_LA21_P -set_property -dict {PACKAGE_PIN F22 IOSTANDARD LVDS_25} [get_ports dac_clk_out_n] ; ## FMC1_LPC_LA21_N -set_property -dict {PACKAGE_PIN R20 IOSTANDARD LVDS_25} [get_ports dac_frame_out_p] ; ## FMC1_LPC_LA11_P -set_property -dict {PACKAGE_PIN R21 IOSTANDARD LVDS_25} [get_ports dac_frame_out_n] ; ## FMC1_LPC_LA11_N -set_property -dict {PACKAGE_PIN B21 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[0]] ; ## FMC1_LPC_LA32_P -set_property -dict {PACKAGE_PIN B22 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[0]] ; ## FMC1_LPC_LA32_N -set_property -dict {PACKAGE_PIN A18 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[1]] ; ## FMC1_LPC_LA33_P -set_property -dict {PACKAGE_PIN A19 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[1]] ; ## FMC1_LPC_LA33_N -set_property -dict {PACKAGE_PIN E21 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[2]] ; ## FMC1_LPC_LA30_P -set_property -dict {PACKAGE_PIN D21 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[2]] ; ## FMC1_LPC_LA30_N -set_property -dict {PACKAGE_PIN D22 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[3]] ; ## FMC1_LPC_LA28_P -set_property -dict {PACKAGE_PIN C22 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[3]] ; ## FMC1_LPC_LA28_N -set_property -dict {PACKAGE_PIN A16 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[4]] ; ## FMC1_LPC_LA31_P -set_property -dict {PACKAGE_PIN A17 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[4]] ; ## FMC1_LPC_LA31_N -set_property -dict {PACKAGE_PIN B16 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[5]] ; ## FMC1_LPC_LA29_P -set_property -dict {PACKAGE_PIN B17 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[5]] ; ## FMC1_LPC_LA29_N -set_property -dict {PACKAGE_PIN A21 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[6]] ; ## FMC1_LPC_LA24_P -set_property -dict {PACKAGE_PIN A22 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[6]] ; ## FMC1_LPC_LA24_N -set_property -dict {PACKAGE_PIN C15 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[7]] ; ## FMC1_LPC_LA25_P -set_property -dict {PACKAGE_PIN B15 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[7]] ; ## FMC1_LPC_LA25_N -set_property -dict {PACKAGE_PIN G17 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[8]] ; ## FMC1_LPC_LA22_P -set_property -dict {PACKAGE_PIN F17 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[8]] ; ## FMC1_LPC_LA22_N -set_property -dict {PACKAGE_PIN C17 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[9]] ; ## FMC1_LPC_LA27_P -set_property -dict {PACKAGE_PIN C18 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[9]] ; ## FMC1_LPC_LA27_N -set_property -dict {PACKAGE_PIN F18 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[10]] ; ## FMC1_LPC_LA26_P -set_property -dict {PACKAGE_PIN E18 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[10]] ; ## FMC1_LPC_LA26_N -set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[11]] ; ## FMC1_LPC_LA23_P -set_property -dict {PACKAGE_PIN G16 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[11]] ; ## FMC1_LPC_LA23_N -set_property -dict {PACKAGE_PIN E19 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[12]] ; ## FMC1_LPC_LA19_P -set_property -dict {PACKAGE_PIN E20 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[12]] ; ## FMC1_LPC_LA19_N -set_property -dict {PACKAGE_PIN G20 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[13]] ; ## FMC1_LPC_LA20_P -set_property -dict {PACKAGE_PIN G21 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[13]] ; ## FMC1_LPC_LA20_N -set_property -dict {PACKAGE_PIN P20 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[14]] ; ## FMC1_LPC_LA15_P -set_property -dict {PACKAGE_PIN P21 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[14]] ; ## FMC1_LPC_LA15_N -set_property -dict {PACKAGE_PIN N15 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[15]] ; ## FMC1_LPC_LA16_P -set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[15]] ; ## FMC1_LPC_LA16_N - -# adc - -set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_clk_in_p] ; ## FMC1_LPC_CLK1_M2C_P -set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_clk_in_n] ; ## FMC1_LPC_CLK1_M2C_N -set_property -dict {PACKAGE_PIN K19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_or_in_p] ; ## FMC1_LPC_LA00_CC_P -set_property -dict {PACKAGE_PIN K20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_or_in_n] ; ## FMC1_LPC_LA00_CC_N -set_property -dict {PACKAGE_PIN D20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[0]] ; ## FMC1_LPC_LA18_CC_P -set_property -dict {PACKAGE_PIN C20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[0]] ; ## FMC1_LPC_LA18_CC_N -set_property -dict {PACKAGE_PIN J16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[1]] ; ## FMC1_LPC_LA14_P -set_property -dict {PACKAGE_PIN J17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[1]] ; ## FMC1_LPC_LA14_N -set_property -dict {PACKAGE_PIN P16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[2]] ; ## FMC1_LPC_LA13_P -set_property -dict {PACKAGE_PIN R16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[2]] ; ## FMC1_LPC_LA13_N -set_property -dict {PACKAGE_PIN J20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[3]] ; ## FMC1_LPC_LA03_P -set_property -dict {PACKAGE_PIN K21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[3]] ; ## FMC1_LPC_LA03_N -set_property -dict {PACKAGE_PIN N17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[4]] ; ## FMC1_LPC_LA05_P -set_property -dict {PACKAGE_PIN N18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[4]] ; ## FMC1_LPC_LA05_N -set_property -dict {PACKAGE_PIN L17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[5]] ; ## FMC1_LPC_LA10_P -set_property -dict {PACKAGE_PIN M17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[5]] ; ## FMC1_LPC_LA10_N -set_property -dict {PACKAGE_PIN N22 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[6]] ; ## FMC1_LPC_LA12_P -set_property -dict {PACKAGE_PIN P22 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[6]] ; ## FMC1_LPC_LA12_N -set_property -dict {PACKAGE_PIN J15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[7]] ; ## FMC1_LPC_LA07_P -set_property -dict {PACKAGE_PIN K15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[7]] ; ## FMC1_LPC_LA07_N -set_property -dict {PACKAGE_PIN L21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[8]] ; ## FMC1_LPC_LA02_P -set_property -dict {PACKAGE_PIN L22 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[8]] ; ## FMC1_LPC_LA02_N -set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[9]] ; ## FMC1_LPC_LA04_P -set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[9]] ; ## FMC1_LPC_LA04_N -set_property -dict {PACKAGE_PIN M15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[10]] ; ## FMC1_LPC_LA09_P -set_property -dict {PACKAGE_PIN M16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[10]] ; ## FMC1_LPC_LA09_N -set_property -dict {PACKAGE_PIN J21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[11]] ; ## FMC1_LPC_LA08_P -set_property -dict {PACKAGE_PIN J22 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[11]] ; ## FMC1_LPC_LA08_N -set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[12]] ; ## FMC1_LPC_LA06_P -set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[12]] ; ## FMC1_LPC_LA06_N -set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[13]] ; ## FMC1_LPC_LA01_CC_P -set_property -dict {PACKAGE_PIN N20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[13]] ; ## FMC1_LPC_LA01_CC_N - -# clocks - -create_clock -name dac_clk_in -period 2.16 [get_ports dac_clk_in_p] -create_clock -name adc_clk_in -period 4.00 [get_ports adc_clk_in_p] diff --git a/projects/fmcomms1/zc702/system_project.tcl b/projects/fmcomms1/zc702/system_project.tcl deleted file mode 100644 index 2f78a58d1..000000000 --- a/projects/fmcomms1/zc702/system_project.tcl +++ /dev/null @@ -1,18 +0,0 @@ - -source ../../scripts/adi_env.tcl -source $ad_hdl_dir/projects/scripts/adi_project.tcl -source $ad_hdl_dir/projects/scripts/adi_board.tcl - -adi_project_create fmcomms1_zc702 -adi_project_files fmcomms1_zc702 [list \ - "system_top.v" \ - "system_constr.xdc"\ - "$ad_hdl_dir/library/common/ad_iobuf.v" \ - "$ad_hdl_dir/projects/common/zc702/zc702_system_constr.xdc" ] - -set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/zc702/zc702_system_constr.xdc] -set_property PROCESSING_ORDER EARLY [get_files system_constr.xdc] - -adi_project_run fmcomms1_zc702 - - diff --git a/projects/fmcomms1/zc706/system_bd.tcl b/projects/fmcomms1/zc706/system_bd.tcl deleted file mode 100644 index dca59af34..000000000 --- a/projects/fmcomms1/zc706/system_bd.tcl +++ /dev/null @@ -1,4 +0,0 @@ - - source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl - source ../common/fmcomms1_bd.tcl - diff --git a/projects/fmcomms1/zc706/system_constr.xdc b/projects/fmcomms1/zc706/system_constr.xdc deleted file mode 100644 index c93d464d3..000000000 --- a/projects/fmcomms1/zc706/system_constr.xdc +++ /dev/null @@ -1,86 +0,0 @@ - -# reference - -set_property -dict {PACKAGE_PIN AB27 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports ref_clk_out_p] ; ## FMC1_LPC_LA17_CC_P -set_property -dict {PACKAGE_PIN AC27 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports ref_clk_out_n] ; ## FMC1_LPC_LA17_CC_N - -# dac - -set_property -dict {PACKAGE_PIN AG17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports dac_clk_in_p] ; ## FMC1_LPC_CLK0_M2C_P -set_property -dict {PACKAGE_PIN AG16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports dac_clk_in_n] ; ## FMC1_LPC_CLK0_M2C_N -set_property -dict {PACKAGE_PIN AH28 IOSTANDARD LVDS_25} [get_ports dac_clk_out_p] ; ## FMC1_LPC_LA21_P -set_property -dict {PACKAGE_PIN AH29 IOSTANDARD LVDS_25} [get_ports dac_clk_out_n] ; ## FMC1_LPC_LA21_N -set_property -dict {PACKAGE_PIN AJ16 IOSTANDARD LVDS_25} [get_ports dac_frame_out_p] ; ## FMC1_LPC_LA11_P -set_property -dict {PACKAGE_PIN AK16 IOSTANDARD LVDS_25} [get_ports dac_frame_out_n] ; ## FMC1_LPC_LA11_N -set_property -dict {PACKAGE_PIN Y26 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[0]] ; ## FMC1_LPC_LA32_P -set_property -dict {PACKAGE_PIN Y27 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[0]] ; ## FMC1_LPC_LA32_N -set_property -dict {PACKAGE_PIN Y30 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[1]] ; ## FMC1_LPC_LA33_P -set_property -dict {PACKAGE_PIN AA30 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[1]] ; ## FMC1_LPC_LA33_N -set_property -dict {PACKAGE_PIN AB29 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[2]] ; ## FMC1_LPC_LA30_P -set_property -dict {PACKAGE_PIN AB30 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[2]] ; ## FMC1_LPC_LA30_N -set_property -dict {PACKAGE_PIN AD25 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[3]] ; ## FMC1_LPC_LA28_P -set_property -dict {PACKAGE_PIN AE26 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[3]] ; ## FMC1_LPC_LA28_N -set_property -dict {PACKAGE_PIN AC29 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[4]] ; ## FMC1_LPC_LA31_P -set_property -dict {PACKAGE_PIN AD29 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[4]] ; ## FMC1_LPC_LA31_N -set_property -dict {PACKAGE_PIN AE25 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[5]] ; ## FMC1_LPC_LA29_P -set_property -dict {PACKAGE_PIN AF25 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[5]] ; ## FMC1_LPC_LA29_N -set_property -dict {PACKAGE_PIN AF30 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[6]] ; ## FMC1_LPC_LA24_P -set_property -dict {PACKAGE_PIN AG30 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[6]] ; ## FMC1_LPC_LA24_N -set_property -dict {PACKAGE_PIN AF29 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[7]] ; ## FMC1_LPC_LA25_P -set_property -dict {PACKAGE_PIN AG29 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[7]] ; ## FMC1_LPC_LA25_N -set_property -dict {PACKAGE_PIN AK27 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[8]] ; ## FMC1_LPC_LA22_P -set_property -dict {PACKAGE_PIN AK28 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[8]] ; ## FMC1_LPC_LA22_N -set_property -dict {PACKAGE_PIN AJ28 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[9]] ; ## FMC1_LPC_LA27_P -set_property -dict {PACKAGE_PIN AJ29 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[9]] ; ## FMC1_LPC_LA27_N -set_property -dict {PACKAGE_PIN AJ30 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[10]] ; ## FMC1_LPC_LA26_P -set_property -dict {PACKAGE_PIN AK30 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[10]] ; ## FMC1_LPC_LA26_N -set_property -dict {PACKAGE_PIN AJ26 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[11]] ; ## FMC1_LPC_LA23_P -set_property -dict {PACKAGE_PIN AK26 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[11]] ; ## FMC1_LPC_LA23_N -set_property -dict {PACKAGE_PIN AH26 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[12]] ; ## FMC1_LPC_LA19_P -set_property -dict {PACKAGE_PIN AH27 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[12]] ; ## FMC1_LPC_LA19_N -set_property -dict {PACKAGE_PIN AG26 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[13]] ; ## FMC1_LPC_LA20_P -set_property -dict {PACKAGE_PIN AG27 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[13]] ; ## FMC1_LPC_LA20_N -set_property -dict {PACKAGE_PIN AB15 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[14]] ; ## FMC1_LPC_LA15_P -set_property -dict {PACKAGE_PIN AB14 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[14]] ; ## FMC1_LPC_LA15_N -set_property -dict {PACKAGE_PIN AE18 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[15]] ; ## FMC1_LPC_LA16_P -set_property -dict {PACKAGE_PIN AE17 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[15]] ; ## FMC1_LPC_LA16_N - -# adc - -set_property -dict {PACKAGE_PIN AC28 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_clk_in_p] ; ## FMC1_LPC_CLK1_M2C_P -set_property -dict {PACKAGE_PIN AD28 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_clk_in_n] ; ## FMC1_LPC_CLK1_M2C_N -set_property -dict {PACKAGE_PIN AE13 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_or_in_p] ; ## FMC1_LPC_LA00_CC_P -set_property -dict {PACKAGE_PIN AF13 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_or_in_n] ; ## FMC1_LPC_LA00_CC_N -set_property -dict {PACKAGE_PIN AE27 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[0]] ; ## FMC1_LPC_LA18_CC_P -set_property -dict {PACKAGE_PIN AF27 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[0]] ; ## FMC1_LPC_LA18_CC_N -set_property -dict {PACKAGE_PIN AF18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[1]] ; ## FMC1_LPC_LA14_P -set_property -dict {PACKAGE_PIN AF17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[1]] ; ## FMC1_LPC_LA14_N -set_property -dict {PACKAGE_PIN AH17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[2]] ; ## FMC1_LPC_LA13_P -set_property -dict {PACKAGE_PIN AH16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[2]] ; ## FMC1_LPC_LA13_N -set_property -dict {PACKAGE_PIN AG12 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[3]] ; ## FMC1_LPC_LA03_P -set_property -dict {PACKAGE_PIN AH12 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[3]] ; ## FMC1_LPC_LA03_N -set_property -dict {PACKAGE_PIN AE16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[4]] ; ## FMC1_LPC_LA05_P -set_property -dict {PACKAGE_PIN AE15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[4]] ; ## FMC1_LPC_LA05_N -set_property -dict {PACKAGE_PIN AC14 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[5]] ; ## FMC1_LPC_LA10_P -set_property -dict {PACKAGE_PIN AC13 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[5]] ; ## FMC1_LPC_LA10_N -set_property -dict {PACKAGE_PIN AD16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[6]] ; ## FMC1_LPC_LA12_P -set_property -dict {PACKAGE_PIN AD15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[6]] ; ## FMC1_LPC_LA12_N -set_property -dict {PACKAGE_PIN AA15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[7]] ; ## FMC1_LPC_LA07_P -set_property -dict {PACKAGE_PIN AA14 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[7]] ; ## FMC1_LPC_LA07_N -set_property -dict {PACKAGE_PIN AE12 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[8]] ; ## FMC1_LPC_LA02_P -set_property -dict {PACKAGE_PIN AF12 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[8]] ; ## FMC1_LPC_LA02_N -set_property -dict {PACKAGE_PIN AJ15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[9]] ; ## FMC1_LPC_LA04_P -set_property -dict {PACKAGE_PIN AK15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[9]] ; ## FMC1_LPC_LA04_N -set_property -dict {PACKAGE_PIN AH14 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[10]] ; ## FMC1_LPC_LA09_P -set_property -dict {PACKAGE_PIN AH13 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[10]] ; ## FMC1_LPC_LA09_N -set_property -dict {PACKAGE_PIN AD14 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[11]] ; ## FMC1_LPC_LA08_P -set_property -dict {PACKAGE_PIN AD13 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[11]] ; ## FMC1_LPC_LA08_N -set_property -dict {PACKAGE_PIN AB12 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[12]] ; ## FMC1_LPC_LA06_P -set_property -dict {PACKAGE_PIN AC12 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[12]] ; ## FMC1_LPC_LA06_N -set_property -dict {PACKAGE_PIN AF15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[13]] ; ## FMC1_LPC_LA01_CC_P -set_property -dict {PACKAGE_PIN AG15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[13]] ; ## FMC1_LPC_LA01_CC_N - -# clocks - -create_clock -name dac_clk_in -period 2.00 [get_ports dac_clk_in_p] -create_clock -name adc_clk_in -period 4.00 [get_ports adc_clk_in_p] diff --git a/projects/fmcomms1/zc706/system_project.tcl b/projects/fmcomms1/zc706/system_project.tcl deleted file mode 100644 index fcfd9048d..000000000 --- a/projects/fmcomms1/zc706/system_project.tcl +++ /dev/null @@ -1,18 +0,0 @@ - -source ../../scripts/adi_env.tcl -source $ad_hdl_dir/projects/scripts/adi_project.tcl -source $ad_hdl_dir/projects/scripts/adi_board.tcl - -adi_project_create fmcomms1_zc706 -adi_project_files fmcomms1_zc706 [list \ - "system_top.v" \ - "system_constr.xdc"\ - "$ad_hdl_dir/library/common/ad_iobuf.v" \ - "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ] - -set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc] -set_property PROCESSING_ORDER EARLY [get_files system_constr.xdc] - -adi_project_run fmcomms1_zc706 - - diff --git a/projects/fmcomms1/zed/system_bd.tcl b/projects/fmcomms1/zed/system_bd.tcl deleted file mode 100644 index 4032107bf..000000000 --- a/projects/fmcomms1/zed/system_bd.tcl +++ /dev/null @@ -1,13 +0,0 @@ - - source $ad_hdl_dir/projects/common/zed/zed_system_bd.tcl - source ../common/fmcomms1_bd.tcl - - # Add extra register slice between ADC DMA and HP1 to meet timing - #delete_bd_objs [get_bd_intf_nets axi_ad9643_dma_axi] - #create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 axi_register_slice_0 - #set_property -dict [list CONFIG.REG_AW {0} CONFIG.REG_AR {0} CONFIG.REG_W {1} CONFIG.REG_R {0} CONFIG.REG_B {0}] [get_bd_cells axi_register_slice_0] - #ad_connect [get_bd_intf_pins axi_register_slice_0/S_AXI] [get_bd_intf_pins axi_ad9643_dma/m_dest_axi] - #connect_bd_intf_net [get_bd_intf_pins sys_ps7/S_AXI_HP1] [get_bd_intf_pins axi_register_slice_0/M_AXI] - #connect_bd_net -net [get_bd_nets sys_200m_clk] [get_bd_pins axi_register_slice_0/aclk] [get_bd_pins sys_ps7/FCLK_CLK1] - #connect_bd_net -net [get_bd_nets sys_100m_resetn] [get_bd_pins axi_register_slice_0/aresetn] [get_bd_pins sys_rstgen/peripheral_aresetn] - #assign_bd_address [get_bd_addr_segs {sys_ps7/S_AXI_HP1/HP1_DDR_LOWOCM }] diff --git a/projects/fmcomms1/zed/system_constr.xdc b/projects/fmcomms1/zed/system_constr.xdc deleted file mode 100644 index e2a84680e..000000000 --- a/projects/fmcomms1/zed/system_constr.xdc +++ /dev/null @@ -1,86 +0,0 @@ - -# reference - -set_property -dict {PACKAGE_PIN B19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports ref_clk_out_p] ; ## FMC1_LPC_LA17_CC_P -set_property -dict {PACKAGE_PIN B20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports ref_clk_out_n] ; ## FMC1_LPC_LA17_CC_N - -# dac - -set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports dac_clk_in_p] ; ## FMC1_LPC_CLK0_M2C_P -set_property -dict {PACKAGE_PIN L19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports dac_clk_in_n] ; ## FMC1_LPC_CLK0_M2C_N -set_property -dict {PACKAGE_PIN E19 IOSTANDARD LVDS_25} [get_ports dac_clk_out_p] ; ## FMC1_LPC_LA21_P -set_property -dict {PACKAGE_PIN E20 IOSTANDARD LVDS_25} [get_ports dac_clk_out_n] ; ## FMC1_LPC_LA21_N -set_property -dict {PACKAGE_PIN N17 IOSTANDARD LVDS_25} [get_ports dac_frame_out_p] ; ## FMC1_LPC_LA11_P -set_property -dict {PACKAGE_PIN N18 IOSTANDARD LVDS_25} [get_ports dac_frame_out_n] ; ## FMC1_LPC_LA11_N -set_property -dict {PACKAGE_PIN A21 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[0]] ; ## FMC1_LPC_LA32_P -set_property -dict {PACKAGE_PIN A22 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[0]] ; ## FMC1_LPC_LA32_N -set_property -dict {PACKAGE_PIN B21 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[1]] ; ## FMC1_LPC_LA33_P -set_property -dict {PACKAGE_PIN B22 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[1]] ; ## FMC1_LPC_LA33_N -set_property -dict {PACKAGE_PIN C15 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[2]] ; ## FMC1_LPC_LA30_P -set_property -dict {PACKAGE_PIN B15 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[2]] ; ## FMC1_LPC_LA30_N -set_property -dict {PACKAGE_PIN A16 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[3]] ; ## FMC1_LPC_LA28_P -set_property -dict {PACKAGE_PIN A17 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[3]] ; ## FMC1_LPC_LA28_N -set_property -dict {PACKAGE_PIN B16 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[4]] ; ## FMC1_LPC_LA31_P -set_property -dict {PACKAGE_PIN B17 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[4]] ; ## FMC1_LPC_LA31_N -set_property -dict {PACKAGE_PIN C17 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[5]] ; ## FMC1_LPC_LA29_P -set_property -dict {PACKAGE_PIN C18 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[5]] ; ## FMC1_LPC_LA29_N -set_property -dict {PACKAGE_PIN A18 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[6]] ; ## FMC1_LPC_LA24_P -set_property -dict {PACKAGE_PIN A19 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[6]] ; ## FMC1_LPC_LA24_N -set_property -dict {PACKAGE_PIN D22 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[7]] ; ## FMC1_LPC_LA25_P -set_property -dict {PACKAGE_PIN C22 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[7]] ; ## FMC1_LPC_LA25_N -set_property -dict {PACKAGE_PIN G19 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[8]] ; ## FMC1_LPC_LA22_P -set_property -dict {PACKAGE_PIN F19 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[8]] ; ## FMC1_LPC_LA22_N -set_property -dict {PACKAGE_PIN E21 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[9]] ; ## FMC1_LPC_LA27_P -set_property -dict {PACKAGE_PIN D21 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[9]] ; ## FMC1_LPC_LA27_N -set_property -dict {PACKAGE_PIN F18 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[10]] ; ## FMC1_LPC_LA26_P -set_property -dict {PACKAGE_PIN E18 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[10]] ; ## FMC1_LPC_LA26_N -set_property -dict {PACKAGE_PIN E15 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[11]] ; ## FMC1_LPC_LA23_P -set_property -dict {PACKAGE_PIN D15 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[11]] ; ## FMC1_LPC_LA23_N -set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[12]] ; ## FMC1_LPC_LA19_P -set_property -dict {PACKAGE_PIN G16 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[12]] ; ## FMC1_LPC_LA19_N -set_property -dict {PACKAGE_PIN G20 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[13]] ; ## FMC1_LPC_LA20_P -set_property -dict {PACKAGE_PIN G21 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[13]] ; ## FMC1_LPC_LA20_N -set_property -dict {PACKAGE_PIN J16 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[14]] ; ## FMC1_LPC_LA15_P -set_property -dict {PACKAGE_PIN J17 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[14]] ; ## FMC1_LPC_LA15_N -set_property -dict {PACKAGE_PIN J20 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[15]] ; ## FMC1_LPC_LA16_P -set_property -dict {PACKAGE_PIN K21 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[15]] ; ## FMC1_LPC_LA16_N - -# adc - -set_property -dict {PACKAGE_PIN D18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_clk_in_p] ; ## FMC1_LPC_CLK1_M2C_P -set_property -dict {PACKAGE_PIN C19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_clk_in_n] ; ## FMC1_LPC_CLK1_M2C_N -set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_or_in_p] ; ## FMC1_LPC_LA00_CC_P -set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_or_in_n] ; ## FMC1_LPC_LA00_CC_N -set_property -dict {PACKAGE_PIN D20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[0]] ; ## FMC1_LPC_LA18_CC_P -set_property -dict {PACKAGE_PIN C20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[0]] ; ## FMC1_LPC_LA18_CC_N -set_property -dict {PACKAGE_PIN K19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[1]] ; ## FMC1_LPC_LA14_P -set_property -dict {PACKAGE_PIN K20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[1]] ; ## FMC1_LPC_LA14_N -set_property -dict {PACKAGE_PIN L17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[2]] ; ## FMC1_LPC_LA13_P -set_property -dict {PACKAGE_PIN M17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[2]] ; ## FMC1_LPC_LA13_N -set_property -dict {PACKAGE_PIN N22 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[3]] ; ## FMC1_LPC_LA03_P -set_property -dict {PACKAGE_PIN P22 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[3]] ; ## FMC1_LPC_LA03_N -set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[4]] ; ## FMC1_LPC_LA05_P -set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[4]] ; ## FMC1_LPC_LA05_N -set_property -dict {PACKAGE_PIN R19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[5]] ; ## FMC1_LPC_LA10_P -set_property -dict {PACKAGE_PIN T19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[5]] ; ## FMC1_LPC_LA10_N -set_property -dict {PACKAGE_PIN P20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[6]] ; ## FMC1_LPC_LA12_P -set_property -dict {PACKAGE_PIN P21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[6]] ; ## FMC1_LPC_LA12_N -set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[7]] ; ## FMC1_LPC_LA07_P -set_property -dict {PACKAGE_PIN T17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[7]] ; ## FMC1_LPC_LA07_N -set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[8]] ; ## FMC1_LPC_LA02_P -set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[8]] ; ## FMC1_LPC_LA02_N -set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[9]] ; ## FMC1_LPC_LA04_P -set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[9]] ; ## FMC1_LPC_LA04_N -set_property -dict {PACKAGE_PIN R20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[10]] ; ## FMC1_LPC_LA09_P -set_property -dict {PACKAGE_PIN R21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[10]] ; ## FMC1_LPC_LA09_N -set_property -dict {PACKAGE_PIN J21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[11]] ; ## FMC1_LPC_LA08_P -set_property -dict {PACKAGE_PIN J22 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[11]] ; ## FMC1_LPC_LA08_N -set_property -dict {PACKAGE_PIN L21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[12]] ; ## FMC1_LPC_LA06_P -set_property -dict {PACKAGE_PIN L22 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[12]] ; ## FMC1_LPC_LA06_N -set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[13]] ; ## FMC1_LPC_LA01_CC_P -set_property -dict {PACKAGE_PIN N20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[13]] ; ## FMC1_LPC_LA01_CC_N - -# clocks - -create_clock -name dac_clk_in -period 2.16 [get_ports dac_clk_in_p] -create_clock -name adc_clk_in -period 4.00 [get_ports adc_clk_in_p] diff --git a/projects/fmcomms1/zed/system_project.tcl b/projects/fmcomms1/zed/system_project.tcl deleted file mode 100644 index 5bf10f8dc..000000000 --- a/projects/fmcomms1/zed/system_project.tcl +++ /dev/null @@ -1,18 +0,0 @@ - -source ../../scripts/adi_env.tcl -source $ad_hdl_dir/projects/scripts/adi_project.tcl -source $ad_hdl_dir/projects/scripts/adi_board.tcl - -adi_project_create fmcomms1_zed -adi_project_files fmcomms1_zed [list \ - "system_top.v" \ - "system_constr.xdc"\ - "$ad_hdl_dir/library/common/ad_iobuf.v" \ - "$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc" ] - -set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/zed/zed_system_constr.xdc] -set_property PROCESSING_ORDER EARLY [get_files system_constr.xdc] - -adi_project_run fmcomms1_zed - - diff --git a/projects/fmcomms6/Makefile b/projects/fmcomms11/Makefile similarity index 100% rename from projects/fmcomms6/Makefile rename to projects/fmcomms11/Makefile diff --git a/projects/fmcomms11/common/fmcomms11_bd.tcl b/projects/fmcomms11/common/fmcomms11_bd.tcl new file mode 100644 index 000000000..11c1ee9ea --- /dev/null +++ b/projects/fmcomms11/common/fmcomms11_bd.tcl @@ -0,0 +1,145 @@ + +# dac peripherals + +set axi_ad9162_xcvr [create_bd_cell -type ip -vlnv analog.com:user:axi_adxcvr:1.0 axi_ad9162_xcvr] +set_property -dict [list CONFIG.NUM_OF_LANES {8}] $axi_ad9162_xcvr +set_property -dict [list CONFIG.QPLL_ENABLE {1}] $axi_ad9162_xcvr +set_property -dict [list CONFIG.TX_OR_RX_N {1}] $axi_ad9162_xcvr + +set axi_ad9162_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9162:1.0 axi_ad9162_core] + +set axi_ad9162_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:7.0 axi_ad9162_jesd] +set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {1}] $axi_ad9162_jesd +set_property -dict [list CONFIG.C_LANES {8}] $axi_ad9162_jesd + +set axi_ad9162_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9162_dma] +set_property -dict [list CONFIG.DMA_TYPE_SRC {0}] $axi_ad9162_dma +set_property -dict [list CONFIG.DMA_TYPE_DEST {1}] $axi_ad9162_dma +set_property -dict [list CONFIG.ID {1}] $axi_ad9162_dma +set_property -dict [list CONFIG.AXI_SLICE_SRC {0}] $axi_ad9162_dma +set_property -dict [list CONFIG.AXI_SLICE_DEST {0}] $axi_ad9162_dma +set_property -dict [list CONFIG.DMA_LENGTH_WIDTH {24}] $axi_ad9162_dma +set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9162_dma +set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad9162_dma +set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {256}] $axi_ad9162_dma +set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {256}] $axi_ad9162_dma + +# adc peripherals + +set axi_ad9625_xcvr [create_bd_cell -type ip -vlnv analog.com:user:axi_adxcvr:1.0 axi_ad9625_xcvr] +set_property -dict [list CONFIG.NUM_OF_LANES {8}] $axi_ad9625_xcvr +set_property -dict [list CONFIG.QPLL_ENABLE {0}] $axi_ad9625_xcvr +set_property -dict [list CONFIG.TX_OR_RX_N {0}] $axi_ad9625_xcvr + +set axi_ad9625_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9625:1.0 axi_ad9625_core] + +set axi_ad9625_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:7.0 axi_ad9625_jesd] +set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9625_jesd +set_property -dict [list CONFIG.C_LANES {8}] $axi_ad9625_jesd + +set axi_ad9625_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9625_dma] +set_property -dict [list CONFIG.DMA_TYPE_SRC {1}] $axi_ad9625_dma +set_property -dict [list CONFIG.DMA_TYPE_DEST {0}] $axi_ad9625_dma +set_property -dict [list CONFIG.ID {0}] $axi_ad9625_dma +set_property -dict [list CONFIG.AXI_SLICE_SRC {0}] $axi_ad9625_dma +set_property -dict [list CONFIG.AXI_SLICE_DEST {0}] $axi_ad9625_dma +set_property -dict [list CONFIG.SYNC_TRANSFER_START {0}] $axi_ad9625_dma +set_property -dict [list CONFIG.DMA_LENGTH_WIDTH {24}] $axi_ad9625_dma +set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9625_dma +set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad9625_dma +set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {64}] $axi_ad9625_dma +set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $axi_ad9625_dma + +# shared transceiver core + +set util_fmcomms11_xcvr [create_bd_cell -type ip -vlnv analog.com:user:util_adxcvr:1.0 util_fmcomms11_xcvr] +set_property -dict [list CONFIG.QPLL_FBDIV {"0100100000"}] $util_fmcomms11_xcvr +set_property -dict [list CONFIG.CPLL_FBDIV {4}] $util_fmcomms11_xcvr +set_property -dict [list CONFIG.TX_NUM_OF_LANES {8}] $util_fmcomms11_xcvr +set_property -dict [list CONFIG.TX_CLK25_DIV {7}] $util_fmcomms11_xcvr +set_property -dict [list CONFIG.RX_NUM_OF_LANES {8}] $util_fmcomms11_xcvr +set_property -dict [list CONFIG.RX_CLK25_DIV {7}] $util_fmcomms11_xcvr +set_property -dict [list CONFIG.RX_DFE_LPM_CFG {0x0904}] $util_fmcomms11_xcvr +set_property -dict [list CONFIG.RX_CDR_CFG {0x03000023ff10400020}] $util_fmcomms11_xcvr + +# reference clocks & resets + +create_bd_port -dir I tx_ref_clk_0 +create_bd_port -dir I rx_ref_clk_0 + +ad_xcvrpll tx_ref_clk_0 util_fmcomms11_xcvr/qpll_ref_clk_* +ad_xcvrpll rx_ref_clk_0 util_fmcomms11_xcvr/cpll_ref_clk_* +ad_xcvrpll axi_ad9162_xcvr/up_pll_rst util_fmcomms11_xcvr/up_qpll_rst_* +ad_xcvrpll axi_ad9625_xcvr/up_pll_rst util_fmcomms11_xcvr/up_cpll_rst_* +ad_connect sys_cpu_resetn util_fmcomms11_xcvr/up_rstn +ad_connect sys_cpu_clk util_fmcomms11_xcvr/up_clk + +# connections (dac) + +ad_xcvrcon util_fmcomms11_xcvr axi_ad9162_xcvr axi_ad9162_jesd +ad_connect util_fmcomms11_xcvr/tx_out_clk_0 axi_ad9162_core/tx_clk +ad_connect axi_ad9162_jesd/tx_tdata axi_ad9162_core/tx_data +ad_connect util_fmcomms11_xcvr/tx_out_clk_0 axi_ad9162_fifo/dac_clk +ad_connect axi_ad9162_core/dac_valid axi_ad9162_fifo/dac_valid +ad_connect axi_ad9162_core/dac_ddata axi_ad9162_fifo/dac_data +ad_connect sys_cpu_clk axi_ad9162_fifo/dma_clk +ad_connect sys_cpu_reset axi_ad9162_fifo/dma_rst +ad_connect sys_cpu_clk axi_ad9162_dma/m_axis_aclk +ad_connect sys_cpu_resetn axi_ad9162_dma/m_src_axi_aresetn +ad_connect axi_ad9162_fifo/dma_xfer_req axi_ad9162_dma/m_axis_xfer_req +ad_connect axi_ad9162_fifo/dma_ready axi_ad9162_dma/m_axis_ready +ad_connect axi_ad9162_fifo/dma_data axi_ad9162_dma/m_axis_data +ad_connect axi_ad9162_fifo/dma_valid axi_ad9162_dma/m_axis_valid +ad_connect axi_ad9162_fifo/dma_xfer_last axi_ad9162_dma/m_axis_last + +# connections (adc) + +ad_xcvrcon util_fmcomms11_xcvr axi_ad9625_xcvr axi_ad9625_jesd +ad_connect util_fmcomms11_xcvr/rx_out_clk_0 axi_ad9625_core/rx_clk +ad_connect axi_ad9625_jesd/rx_start_of_frame axi_ad9625_core/rx_sof +ad_connect axi_ad9625_jesd/rx_tdata axi_ad9625_core/rx_data +ad_connect util_fmcomms11_xcvr/rx_out_clk_0 axi_ad9625_fifo/adc_clk +ad_connect axi_ad9625_jesd_rstgen/peripheral_reset axi_ad9625_fifo/adc_rst +ad_connect axi_ad9625_core/adc_valid axi_ad9625_fifo/adc_wr +ad_connect axi_ad9625_core/adc_data axi_ad9625_fifo/adc_wdata +ad_connect sys_cpu_clk axi_ad9625_fifo/dma_clk +ad_connect sys_cpu_clk axi_ad9625_dma/s_axis_aclk +ad_connect sys_cpu_resetn axi_ad9625_dma/m_dest_axi_aresetn +ad_connect axi_ad9625_fifo/dma_wr axi_ad9625_dma/s_axis_valid +ad_connect axi_ad9625_fifo/dma_wdata axi_ad9625_dma/s_axis_data +ad_connect axi_ad9625_fifo/dma_wready axi_ad9625_dma/s_axis_ready +ad_connect axi_ad9625_fifo/dma_xfer_req axi_ad9625_dma/s_axis_xfer_req +ad_connect axi_ad9625_core/adc_dovf axi_ad9625_fifo/adc_wovf + +# interconnect (cpu) + +ad_cpu_interconnect 0x44A60000 axi_ad9162_xcvr +ad_cpu_interconnect 0x44A00000 axi_ad9162_core +ad_cpu_interconnect 0x44A90000 axi_ad9162_jesd +ad_cpu_interconnect 0x7c420000 axi_ad9162_dma +ad_cpu_interconnect 0x44A50000 axi_ad9625_xcvr +ad_cpu_interconnect 0x44A10000 axi_ad9625_core +ad_cpu_interconnect 0x44A91000 axi_ad9625_jesd +ad_cpu_interconnect 0x7c400000 axi_ad9625_dma + +# gt uses hp3, and 100MHz clock for both DRP and AXI4 + +ad_mem_hp3_interconnect sys_cpu_clk sys_ps7/S_AXI_HP3 +ad_mem_hp3_interconnect sys_cpu_clk axi_ad9625_xcvr/m_axi + +# interconnect (mem/dac) + +ad_mem_hp1_interconnect sys_cpu_clk sys_ps7/S_AXI_HP1 +ad_mem_hp1_interconnect sys_cpu_clk axi_ad9162_dma/m_src_axi +ad_mem_hp2_interconnect sys_cpu_clk sys_ps7/S_AXI_HP2 +ad_mem_hp2_interconnect sys_cpu_clk axi_ad9625_dma/m_dest_axi + +# interrupts + +ad_cpu_interrupt ps-12 mb-12 axi_ad9162_dma/irq +ad_cpu_interrupt ps-13 mb-13 axi_ad9625_dma/irq + +# unused + +ad_connect axi_ad9162_fifo/dac_fifo_bypass GND + diff --git a/projects/fmcomms11/common/fmcomms11_spi.v b/projects/fmcomms11/common/fmcomms11_spi.v new file mode 100644 index 000000000..0a154cfd5 --- /dev/null +++ b/projects/fmcomms11/common/fmcomms11_spi.v @@ -0,0 +1,122 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module fmcomms11_spi ( + + // 4 wire + + input [ 2:0] spi_csn, + input spi_clk, + input spi_mosi, + output spi_miso, + + // 3 wire + + output spi_csn_ad9625, + output spi_csn_ad9162, + output spi_csn_ad9508, + output spi_csn_adl5240, + output spi_csn_adf4355, + output spi_csn_hmc1119, + inout spi_sdio, + output spi_dir); + + // internal registers + + reg [ 5:0] spi_count = 'd0; + reg spi_rd_wr_n = 'd0; + reg spi_enable = 'd0; + + // internal signals + + wire [ 5:0] spi_csn6_s; + wire spi_csn_s; + wire spi_enable_s; + + // check on rising edge and change on falling edge + + assign spi_csn_ad9625 = spi_csn6_s[0]; + assign spi_csn_ad9162 = spi_csn6_s[1]; + assign spi_csn_ad9508 = spi_csn6_s[2]; + assign spi_csn_adl5240 = spi_csn6_s[3]; + assign spi_csn_adf4355 = spi_csn6_s[4]; + assign spi_csn_hmc1119 = spi_csn6_s[5]; + + assign spi_csn6_s[0] = (spi_csn == 3'b001) ? 1'b0 : 1'b1; + assign spi_csn6_s[1] = (spi_csn == 3'b010) ? 1'b0 : 1'b1; + assign spi_csn6_s[2] = (spi_csn == 3'b011) ? 1'b0 : 1'b1; + assign spi_csn6_s[3] = (spi_csn == 3'b100) ? 1'b0 : 1'b1; + assign spi_csn6_s[4] = (spi_csn == 3'b101) ? 1'b0 : 1'b1; + assign spi_csn6_s[5] = (spi_csn == 3'b110) ? 1'b0 : 1'b1; + + assign spi_csn_s = & spi_csn6_s; + assign spi_dir = ~spi_enable_s; + assign spi_enable_s = spi_enable & ~spi_csn_s; + + always @(posedge spi_clk or posedge spi_csn_s) begin + if (spi_csn_s == 1'b1) begin + spi_count <= 6'd0; + spi_rd_wr_n <= 1'd0; + end else begin + spi_count <= (spi_count < 6'h3f) ? spi_count + 1'b1 : spi_count; + if (spi_count == 6'd0) begin + spi_rd_wr_n <= spi_mosi; + end + end + end + + always @(negedge spi_clk or posedge spi_csn_s) begin + if (spi_csn_s == 1'b1) begin + spi_enable <= 1'b0; + end else begin + if (spi_count == 6'd16) begin + spi_enable <= spi_rd_wr_n; + end + end + end + + // io buffer + + assign spi_miso = spi_sdio; + assign spi_sdio = (spi_enable_s == 1'b1) ? 1'bz : spi_mosi; + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/projects/fmcomms11/zc706/Makefile b/projects/fmcomms11/zc706/Makefile new file mode 100644 index 000000000..2fe7881e4 --- /dev/null +++ b/projects/fmcomms11/zc706/Makefile @@ -0,0 +1,92 @@ +#################################################################################### +#################################################################################### +## Copyright 2011(c) Analog Devices, Inc. +## Auto-generated, do not modify! +#################################################################################### +#################################################################################### + +M_DEPS += system_top.v +M_DEPS += system_project.tcl +M_DEPS += system_constr.xdc +M_DEPS += system_bd.tcl +M_DEPS += ../common/fmcomms11_spi.v +M_DEPS += ../common/fmcomms11_bd.tcl +M_DEPS += ../../scripts/adi_project.tcl +M_DEPS += ../../scripts/adi_env.tcl +M_DEPS += ../../scripts/adi_board.tcl +M_DEPS += ../../common/zc706/zc706_system_plddr3_adcfifo.tcl +M_DEPS += ../../common/zc706/zc706_system_mig_constr.xdc +M_DEPS += ../../common/zc706/zc706_system_mig.prj +M_DEPS += ../../common/zc706/zc706_system_constr.xdc +M_DEPS += ../../common/zc706/zc706_system_bd.tcl +M_DEPS += ../../common/xilinx/sys_dacfifo.tcl +M_DEPS += ../../../library/xilinx/common/ad_iobuf.v +M_DEPS += ../../../library/axi_ad9162/axi_ad9162.xpr +M_DEPS += ../../../library/axi_ad9625/axi_ad9625.xpr +M_DEPS += ../../../library/xilinx/axi_adcfifo/axi_adcfifo.xpr +M_DEPS += ../../../library/xilinx/axi_adxcvr/axi_adxcvr.xpr +M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr +M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr +M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr +M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr +M_DEPS += ../../../library/xilinx/util_adxcvr/util_adxcvr.xpr +M_DEPS += ../../../library/util_dacfifo/util_dacfifo.xpr + +M_VIVADO := vivado -mode batch -source + +M_FLIST := *.cache +M_FLIST += *.data +M_FLIST += *.xpr +M_FLIST += *.log +M_FLIST += *.jou +M_FLIST += xgui +M_FLIST += *.runs +M_FLIST += *.srcs +M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim +M_FLIST += .Xil +M_FLIST += *.ip_user_files + + + +.PHONY: all lib clean clean-all +all: lib fmcomms11_zc706.sdk/system_top.hdf + + +clean: + rm -rf $(M_FLIST) + + +clean-all:clean + make -C ../../../library/axi_ad9162 clean + make -C ../../../library/axi_ad9625 clean + make -C ../../../library/xilinx/axi_adcfifo clean + make -C ../../../library/xilinx/axi_adxcvr clean + make -C ../../../library/axi_clkgen clean + make -C ../../../library/axi_dmac clean + make -C ../../../library/axi_hdmi_tx clean + make -C ../../../library/axi_spdif_tx clean + make -C ../../../library/xilinx/util_adxcvr clean + make -C ../../../library/util_dacfifo clean + + +fmcomms11_zc706.sdk/system_top.hdf: $(M_DEPS) + -rm -rf $(M_FLIST) + $(M_VIVADO) system_project.tcl >> fmcomms11_zc706_vivado.log 2>&1 + + +lib: + make -C ../../../library/axi_ad9162 + make -C ../../../library/axi_ad9625 + make -C ../../../library/xilinx/axi_adcfifo + make -C ../../../library/xilinx/axi_adxcvr + make -C ../../../library/axi_clkgen + make -C ../../../library/axi_dmac + make -C ../../../library/axi_hdmi_tx + make -C ../../../library/axi_spdif_tx + make -C ../../../library/xilinx/util_adxcvr + make -C ../../../library/util_dacfifo + +#################################################################################### +#################################################################################### diff --git a/projects/fmcomms11/zc706/system_bd.tcl b/projects/fmcomms11/zc706/system_bd.tcl new file mode 100644 index 000000000..e85adf8c4 --- /dev/null +++ b/projects/fmcomms11/zc706/system_bd.tcl @@ -0,0 +1,25 @@ + +source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl +source $ad_hdl_dir/projects/common/zc706/zc706_system_plddr3_adcfifo.tcl +source $ad_hdl_dir/projects/common/xilinx/sys_dacfifo.tcl + +p_sys_dacfifo [current_bd_instance .] axi_ad9162_fifo 256 10 +p_plddr3_adcfifo [current_bd_instance .] axi_ad9625_fifo 256 + +create_bd_port -dir I -type rst sys_rst +create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr3 +create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sys_clk + +set_property CONFIG.POLARITY ACTIVE_HIGH [get_bd_ports sys_rst] + +ad_connect sys_rst axi_ad9625_fifo/sys_rst +ad_connect sys_clk axi_ad9625_fifo/sys_clk +ad_connect ddr3 axi_ad9625_fifo/ddr3 + +create_bd_addr_seg -range 0x40000000 -offset 0x80000000 \ + [get_bd_addr_spaces axi_ad9625_fifo/axi_adcfifo/axi] \ + [get_bd_addr_segs axi_ad9625_fifo/axi_ddr_cntrl/memmap/memaddr] \ + SEG_axi_ddr_cntrl_memaddr + +source ../common/fmcomms11_bd.tcl + diff --git a/projects/fmcomms11/zc706/system_constr.xdc b/projects/fmcomms11/zc706/system_constr.xdc new file mode 100644 index 000000000..a219f9335 --- /dev/null +++ b/projects/fmcomms11/zc706/system_constr.xdc @@ -0,0 +1,75 @@ + +# fmcomms11 + +set_property -dict {PACKAGE_PIN AA8 } [get_ports rx_ref_clk_p] ; ## B20 FMC_HPC_GBTCLK1_M2C_P +set_property -dict {PACKAGE_PIN AA7 } [get_ports rx_ref_clk_n] ; ## B21 FMC_HPC_GBTCLK1_M2C_N +set_property -dict {PACKAGE_PIN AH10} [get_ports rx_data_p[0]] ; ## C06 FMC_HPC_DP0_M2C_P +set_property -dict {PACKAGE_PIN AH9 } [get_ports rx_data_n[0]] ; ## C07 FMC_HPC_DP0_M2C_N +set_property -dict {PACKAGE_PIN AJ8 } [get_ports rx_data_p[1]] ; ## A02 FMC_HPC_DP1_M2C_P +set_property -dict {PACKAGE_PIN AJ7 } [get_ports rx_data_n[1]] ; ## A03 FMC_HPC_DP1_M2C_N +set_property -dict {PACKAGE_PIN AG8 } [get_ports rx_data_p[2]] ; ## A06 FMC_HPC_DP2_M2C_P +set_property -dict {PACKAGE_PIN AG7 } [get_ports rx_data_n[2]] ; ## A07 FMC_HPC_DP2_M2C_N +set_property -dict {PACKAGE_PIN AE8 } [get_ports rx_data_p[3]] ; ## A10 FMC_HPC_DP3_M2C_P +set_property -dict {PACKAGE_PIN AE7 } [get_ports rx_data_n[3]] ; ## A11 FMC_HPC_DP3_M2C_N +set_property -dict {PACKAGE_PIN AD6 } [get_ports rx_data_p[4]] ; ## B12 FMC_HPC_DP7_M2C_P +set_property -dict {PACKAGE_PIN AD5 } [get_ports rx_data_n[4]] ; ## B13 FMC_HPC_DP7_M2C_N +set_property -dict {PACKAGE_PIN AH6 } [get_ports rx_data_p[5]] ; ## A14 FMC_HPC_DP4_M2C_P +set_property -dict {PACKAGE_PIN AH5 } [get_ports rx_data_n[5]] ; ## A15 FMC_HPC_DP4_M2C_N +set_property -dict {PACKAGE_PIN AF6 } [get_ports rx_data_p[6]] ; ## B16 FMC_HPC_DP6_M2C_P +set_property -dict {PACKAGE_PIN AF5 } [get_ports rx_data_n[6]] ; ## B17 FMC_HPC_DP6_M2C_N +set_property -dict {PACKAGE_PIN AG4 } [get_ports rx_data_p[7]] ; ## A18 FMC_HPC_DP5_M2C_P +set_property -dict {PACKAGE_PIN AG3 } [get_ports rx_data_n[7]] ; ## A19 FMC_HPC_DP5_M2C_N +set_property -dict {PACKAGE_PIN AK17 IOSTANDARD LVDS_25} [get_ports rx_sync_p] ; ## H07 FMC_HPC_LA02_P +set_property -dict {PACKAGE_PIN AK18 IOSTANDARD LVDS_25} [get_ports rx_sync_n] ; ## H08 FMC_HPC_LA02_N + +set_property -dict {PACKAGE_PIN AD10} [get_ports tx_ref_clk_p] ; ## D04 FMC_HPC_GBTCLK0_M2C_P +set_property -dict {PACKAGE_PIN AD9 } [get_ports tx_ref_clk_n] ; ## D05 FMC_HPC_GBTCLK0_M2C_N +set_property -dict {PACKAGE_PIN AK10} [get_ports tx_data_p[0]] ; ## C02 FMC_HPC_DP0_C2M_P +set_property -dict {PACKAGE_PIN AK9 } [get_ports tx_data_n[0]] ; ## C03 FMC_HPC_DP0_C2M_N +set_property -dict {PACKAGE_PIN AK6 } [get_ports tx_data_p[1]] ; ## A22 FMC_HPC_DP1_C2M_P +set_property -dict {PACKAGE_PIN AK5 } [get_ports tx_data_n[1]] ; ## A23 FMC_HPC_DP1_C2M_N +set_property -dict {PACKAGE_PIN AJ4 } [get_ports tx_data_p[2]] ; ## A26 FMC_HPC_DP2_C2M_P +set_property -dict {PACKAGE_PIN AJ3 } [get_ports tx_data_n[2]] ; ## A27 FMC_HPC_DP2_C2M_N +set_property -dict {PACKAGE_PIN AK2 } [get_ports tx_data_p[3]] ; ## A30 FMC_HPC_DP3_C2M_P +set_property -dict {PACKAGE_PIN AK1 } [get_ports tx_data_n[3]] ; ## A31 FMC_HPC_DP3_C2M_N +set_property -dict {PACKAGE_PIN AD2 } [get_ports tx_data_p[4]] ; ## B32 FMC_HPC_DP7_C2M_P +set_property -dict {PACKAGE_PIN AD1 } [get_ports tx_data_n[4]] ; ## B33 FMC_HPC_DP7_C2M_N +set_property -dict {PACKAGE_PIN AH2 } [get_ports tx_data_p[5]] ; ## A34 FMC_HPC_DP4_C2M_P +set_property -dict {PACKAGE_PIN AH1 } [get_ports tx_data_n[5]] ; ## A35 FMC_HPC_DP4_C2M_N +set_property -dict {PACKAGE_PIN AE4 } [get_ports tx_data_p[6]] ; ## B36 FMC_HPC_DP6_C2M_P +set_property -dict {PACKAGE_PIN AE3 } [get_ports tx_data_n[6]] ; ## B37 FMC_HPC_DP6_C2M_N +set_property -dict {PACKAGE_PIN AF2 } [get_ports tx_data_p[7]] ; ## A38 FMC_HPC_DP5_C2M_P +set_property -dict {PACKAGE_PIN AF1 } [get_ports tx_data_n[7]] ; ## A39 FMC_HPC_DP5_C2M_N +set_property -dict {PACKAGE_PIN AH19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sync_p] ; ## G09 FMC_HPC_LA03_P +set_property -dict {PACKAGE_PIN AJ19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sync_n] ; ## G10 FMC_HPC_LA03_N + +set_property -dict {PACKAGE_PIN AF20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports usr_clk_p] ; ## G06 FMC_HPC_LA00_CC_P +set_property -dict {PACKAGE_PIN AG20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports usr_clk_n] ; ## G07 FMC_HPC_LA00_CC_N +set_property -dict {PACKAGE_PIN AJ20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports sysref_p] ; ## H10 FMC_HPC_LA04_P +set_property -dict {PACKAGE_PIN AK20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports sysref_n] ; ## H11 FMC_HPC_LA04_N + +set_property -dict {PACKAGE_PIN AH22 IOSTANDARD LVCMOS25} [get_ports spi_csn_ad9625] ; ## C11 FMC_HPC_LA06_N +set_property -dict {PACKAGE_PIN AF19 IOSTANDARD LVCMOS25} [get_ports spi_csn_ad9162] ; ## G12 FMC_HPC_LA08_P +set_property -dict {PACKAGE_PIN AJ24 IOSTANDARD LVCMOS25} [get_ports spi_csn_ad9508] ; ## H14 FMC_HPC_LA07_N +set_property -dict {PACKAGE_PIN AG22 IOSTANDARD LVCMOS25} [get_ports spi_csn_adl5240] ; ## C10 FMC_HPC_LA06_P +set_property -dict {PACKAGE_PIN AH24 IOSTANDARD LVCMOS25} [get_ports spi_csn_adf4355] ; ## D12 FMC_HPC_LA05_N +set_property -dict {PACKAGE_PIN AH23 IOSTANDARD LVCMOS25} [get_ports spi_csn_hmc1119] ; ## D11 FMC_HPC_LA05_P +set_property -dict {PACKAGE_PIN AG24 IOSTANDARD LVCMOS25} [get_ports spi_clk] ; ## C14 FMC_HPC_LA10_P +set_property -dict {PACKAGE_PIN AG25 IOSTANDARD LVCMOS25} [get_ports spi_sdio] ; ## C15 FMC_HPC_LA10_N +set_property -dict {PACKAGE_PIN AJ23 IOSTANDARD LVCMOS25} [get_ports spi_dir] ; ## H13 FMC_HPC_LA07_P + +set_property -dict {PACKAGE_PIN AD21 IOSTANDARD LVCMOS25} [get_ports adf4355_muxout] ; ## D14 FMC_HPC_LA09_P +set_property -dict {PACKAGE_PIN AG19 IOSTANDARD LVCMOS25} [get_ports ad9162_txen] ; ## G13 FMC_HPC_LA08_N +set_property -dict {PACKAGE_PIN AE21 IOSTANDARD LVCMOS25} [get_ports ad9625_irq] ; ## D15 FMC_HPC_LA09_N +set_property -dict {PACKAGE_PIN AD23 IOSTANDARD LVCMOS25} [get_ports ad9162_irq] ; ## H16 FMC_HPC_LA11_P + +# clocks + +create_clock -name tx_ref_clk -period 6.40 [get_ports tx_ref_clk_p] +create_clock -name rx_ref_clk -period 6.40 [get_ports rx_ref_clk_p] +create_clock -name tx_div_clk -period 3.20 [get_pins i_system_wrapper/system_i/util_fmcomms11_xcvr/inst/i_xch_0/i_gtxe2_channel/TXOUTCLK] +create_clock -name rx_div_clk -period 6.40 [get_pins i_system_wrapper/system_i/util_fmcomms11_xcvr/inst/i_xch_0/i_gtxe2_channel/RXOUTCLK] + +set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9162_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]*] +set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9625_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]*] + diff --git a/projects/fmcomms11/zc706/system_project.tcl b/projects/fmcomms11/zc706/system_project.tcl new file mode 100644 index 000000000..cdf235a0d --- /dev/null +++ b/projects/fmcomms11/zc706/system_project.tcl @@ -0,0 +1,18 @@ + +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/projects/scripts/adi_project.tcl +source $ad_hdl_dir/projects/scripts/adi_board.tcl + +adi_project_create fmcomms11_zc706 + +set_property part xc7z045ffg900-3 [current_project] +adi_project_files fmcomms11_zc706 [list \ + "../common/fmcomms11_spi.v" \ + "system_top.v" \ + "system_constr.xdc"\ + "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \ + "$ad_hdl_dir/projects/common/zc706/zc706_system_mig_constr.xdc" \ + "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ] + +adi_project_run fmcomms11_zc706 + diff --git a/projects/fmcomms11/zc706/system_top.v b/projects/fmcomms11/zc706/system_top.v new file mode 100644 index 000000000..adc00d9b2 --- /dev/null +++ b/projects/fmcomms11/zc706/system_top.v @@ -0,0 +1,346 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top ( + + inout [14:0] ddr_addr, + inout [ 2:0] ddr_ba, + inout ddr_cas_n, + inout ddr_ck_n, + inout ddr_ck_p, + inout ddr_cke, + inout ddr_cs_n, + inout [ 3:0] ddr_dm, + inout [31:0] ddr_dq, + inout [ 3:0] ddr_dqs_n, + inout [ 3:0] ddr_dqs_p, + inout ddr_odt, + inout ddr_ras_n, + inout ddr_reset_n, + inout ddr_we_n, + + inout fixed_io_ddr_vrn, + inout fixed_io_ddr_vrp, + inout [53:0] fixed_io_mio, + inout fixed_io_ps_clk, + inout fixed_io_ps_porb, + inout fixed_io_ps_srstb, + + inout [14:0] gpio_bd, + + output hdmi_out_clk, + output hdmi_vsync, + output hdmi_hsync, + output hdmi_data_e, + output [23:0] hdmi_data, + + output spdif, + + input sys_rst, + input sys_clk_p, + input sys_clk_n, + + output [13:0] ddr3_addr, + output [ 2:0] ddr3_ba, + output ddr3_cas_n, + output [ 0:0] ddr3_ck_n, + output [ 0:0] ddr3_ck_p, + output [ 0:0] ddr3_cke, + output [ 0:0] ddr3_cs_n, + output [ 7:0] ddr3_dm, + inout [63:0] ddr3_dq, + inout [ 7:0] ddr3_dqs_n, + inout [ 7:0] ddr3_dqs_p, + output [ 0:0] ddr3_odt, + output ddr3_ras_n, + output ddr3_reset_n, + output ddr3_we_n, + + inout iic_scl, + inout iic_sda, + + input rx_ref_clk_p, + input rx_ref_clk_n, + output rx_sync_p, + output rx_sync_n, + input [ 7:0] rx_data_p, + input [ 7:0] rx_data_n, + + input tx_ref_clk_p, + input tx_ref_clk_n, + input tx_sync_p, + input tx_sync_n, + output [ 7:0] tx_data_p, + output [ 7:0] tx_data_n, + + input sysref_p, + input sysref_n, + input usr_clk_p, + input usr_clk_n, + + inout adf4355_muxout, + inout ad9162_txen, + inout ad9625_irq, + inout ad9162_irq, + + output spi_csn_ad9625, + output spi_csn_ad9162, + output spi_csn_ad9508, + output spi_csn_adl5240, + output spi_csn_adf4355, + output spi_csn_hmc1119, + output spi_clk, + inout spi_sdio, + output spi_dir); + + // internal signals + + wire [63:0] gpio_i; + wire [63:0] gpio_o; + wire [63:0] gpio_t; + wire [ 2:0] spi0_csn; + wire spi0_clk; + wire spi0_mosi; + wire spi0_miso; + wire [ 2:0] spi1_csn; + wire spi1_clk; + wire spi1_mosi; + wire spi1_miso; + wire rx_ref_clk; + wire rx_sync; + wire tx_ref_clk; + wire tx_sync; + wire sysref; + wire usr_clk; + + // instantiations + + IBUFDS_GTE2 i_ibufds_rx_ref_clk ( + .CEB (1'd0), + .I (rx_ref_clk_p), + .IB (rx_ref_clk_n), + .O (rx_ref_clk), + .ODIV2 ()); + + OBUFDS i_obufds_rx_sync ( + .I (rx_sync), + .O (rx_sync_p), + .OB (rx_sync_n)); + + IBUFDS_GTE2 i_ibufds_tx_ref_clk ( + .CEB (1'd0), + .I (tx_ref_clk_p), + .IB (tx_ref_clk_n), + .O (tx_ref_clk), + .ODIV2 ()); + + IBUFDS i_ibufds_tx_sync ( + .I (tx_sync_p), + .IB (tx_sync_n), + .O (tx_sync)); + + IBUFDS i_ibufds_sysref ( + .I (sysref_p), + .IB (sysref_n), + .O (sysref)); + + IBUFDS i_ibufds_usr_clk ( + .I (usr_clk_p), + .IB (usr_clk_n), + .O (usr_clk)); + + fmcomms11_spi i_spi ( + .spi_csn (spi0_csn), + .spi_clk (spi_clk), + .spi_mosi (spi0_mosi), + .spi_miso (spi0_miso), + .spi_csn_ad9625 (spi_csn_ad9625), + .spi_csn_ad9162 (spi_csn_ad9162), + .spi_csn_ad9508 (spi_csn_ad9508), + .spi_csn_adl5240 (spi_csn_adl5240), + .spi_csn_adf4355 (spi_csn_adf4355), + .spi_csn_hmc1119 (spi_csn_hmc1119), + .spi_sdio (spi_sdio), + .spi_dir (spi_dir)); + + assign spi_clk = spi0_clk; + + assign gpio_i[63:36] = gpio_o[63:36]; + + ad_iobuf #(.DATA_WIDTH(4)) i_iobuf ( + .dio_t ({gpio_t[35:32]}), + .dio_i ({gpio_o[35:32]}), + .dio_o ({gpio_i[35:32]}), + .dio_p ({ adf4355_muxout, // 35 + ad9162_txen, // 34 + ad9625_irq, // 33 + ad9162_irq})); // 32 + + assign gpio_i[31:15] = gpio_o[31:15]; + + ad_iobuf #(.DATA_WIDTH(15)) i_iobuf_bd ( + .dio_t (gpio_t[14:0]), + .dio_i (gpio_o[14:0]), + .dio_o (gpio_i[14:0]), + .dio_p (gpio_bd)); + + system_wrapper i_system_wrapper ( + .ddr3_addr (ddr3_addr), + .ddr3_ba (ddr3_ba), + .ddr3_cas_n (ddr3_cas_n), + .ddr3_ck_n (ddr3_ck_n), + .ddr3_ck_p (ddr3_ck_p), + .ddr3_cke (ddr3_cke), + .ddr3_cs_n (ddr3_cs_n), + .ddr3_dm (ddr3_dm), + .ddr3_dq (ddr3_dq), + .ddr3_dqs_n (ddr3_dqs_n), + .ddr3_dqs_p (ddr3_dqs_p), + .ddr3_odt (ddr3_odt), + .ddr3_ras_n (ddr3_ras_n), + .ddr3_reset_n (ddr3_reset_n), + .ddr3_we_n (ddr3_we_n), + .ddr_addr (ddr_addr), + .ddr_ba (ddr_ba), + .ddr_cas_n (ddr_cas_n), + .ddr_ck_n (ddr_ck_n), + .ddr_ck_p (ddr_ck_p), + .ddr_cke (ddr_cke), + .ddr_cs_n (ddr_cs_n), + .ddr_dm (ddr_dm), + .ddr_dq (ddr_dq), + .ddr_dqs_n (ddr_dqs_n), + .ddr_dqs_p (ddr_dqs_p), + .ddr_odt (ddr_odt), + .ddr_ras_n (ddr_ras_n), + .ddr_reset_n (ddr_reset_n), + .ddr_we_n (ddr_we_n), + .fixed_io_ddr_vrn (fixed_io_ddr_vrn), + .fixed_io_ddr_vrp (fixed_io_ddr_vrp), + .fixed_io_mio (fixed_io_mio), + .fixed_io_ps_clk (fixed_io_ps_clk), + .fixed_io_ps_porb (fixed_io_ps_porb), + .fixed_io_ps_srstb (fixed_io_ps_srstb), + .gpio_i (gpio_i), + .gpio_o (gpio_o), + .gpio_t (gpio_t), + .hdmi_data (hdmi_data), + .hdmi_data_e (hdmi_data_e), + .hdmi_hsync (hdmi_hsync), + .hdmi_out_clk (hdmi_out_clk), + .hdmi_vsync (hdmi_vsync), + .iic_main_scl_io (iic_scl), + .iic_main_sda_io (iic_sda), + .ps_intr_00 (1'b0), + .ps_intr_01 (1'b0), + .ps_intr_02 (1'b0), + .ps_intr_03 (1'b0), + .ps_intr_04 (1'b0), + .ps_intr_05 (1'b0), + .ps_intr_06 (1'b0), + .ps_intr_07 (1'b0), + .ps_intr_08 (1'b0), + .ps_intr_09 (1'b0), + .ps_intr_10 (1'b0), + .ps_intr_11 (1'b0), + .rx_data_0_n (rx_data_n[0]), + .rx_data_0_p (rx_data_p[0]), + .rx_data_1_n (rx_data_n[1]), + .rx_data_1_p (rx_data_p[1]), + .rx_data_2_n (rx_data_n[2]), + .rx_data_2_p (rx_data_p[2]), + .rx_data_3_n (rx_data_n[3]), + .rx_data_3_p (rx_data_p[3]), + .rx_data_4_n (rx_data_n[4]), + .rx_data_4_p (rx_data_p[4]), + .rx_data_5_n (rx_data_n[5]), + .rx_data_5_p (rx_data_p[5]), + .rx_data_6_n (rx_data_n[6]), + .rx_data_6_p (rx_data_p[6]), + .rx_data_7_n (rx_data_n[7]), + .rx_data_7_p (rx_data_p[7]), + .rx_ref_clk_0 (tx_ref_clk), + .rx_sync_0 (rx_sync), + .rx_sysref_0 (sysref), + .spdif (spdif), + .spi0_clk_i (spi0_clk), + .spi0_clk_o (spi0_clk), + .spi0_csn_0_o (spi0_csn[0]), + .spi0_csn_1_o (spi0_csn[1]), + .spi0_csn_2_o (spi0_csn[2]), + .spi0_csn_i (1'b1), + .spi0_sdi_i (spi0_miso), + .spi0_sdo_i (spi0_mosi), + .spi0_sdo_o (spi0_mosi), + .spi1_clk_i (spi1_clk), + .spi1_clk_o (spi1_clk), + .spi1_csn_0_o (spi1_csn[0]), + .spi1_csn_1_o (spi1_csn[1]), + .spi1_csn_2_o (spi1_csn[2]), + .spi1_csn_i (1'b1), + .spi1_sdi_i (1'b1), + .spi1_sdo_i (spi1_mosi), + .spi1_sdo_o (spi1_mosi), + .sys_clk_clk_n (sys_clk_n), + .sys_clk_clk_p (sys_clk_p), + .sys_rst (sys_rst), + .tx_data_0_n (tx_data_n[0]), + .tx_data_0_p (tx_data_p[0]), + .tx_data_1_n (tx_data_n[1]), + .tx_data_1_p (tx_data_p[1]), + .tx_data_2_n (tx_data_n[2]), + .tx_data_2_p (tx_data_p[2]), + .tx_data_3_n (tx_data_n[3]), + .tx_data_3_p (tx_data_p[3]), + .tx_data_4_n (tx_data_n[4]), + .tx_data_4_p (tx_data_p[4]), + .tx_data_5_n (tx_data_n[5]), + .tx_data_5_p (tx_data_p[5]), + .tx_data_6_n (tx_data_n[6]), + .tx_data_6_p (tx_data_p[6]), + .tx_data_7_n (tx_data_n[7]), + .tx_data_7_p (tx_data_p[7]), + .tx_ref_clk_0 (tx_ref_clk), + .tx_sync_0 (tx_sync), + .tx_sysref_0 (sysref)); + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/projects/fmcomms2/Makefile b/projects/fmcomms2/Makefile index 9e2211814..765002323 100644 --- a/projects/fmcomms2/Makefile +++ b/projects/fmcomms2/Makefile @@ -7,32 +7,41 @@ .PHONY: all clean clean-all all: + -make -C a10gx all -make -C ac701 all -make -C kc705 all -make -C mitx045 all -make -C vc707 all -make -C zc702 all -make -C zc706 all + -make -C zc706pr all + -make -C zcu102 all -make -C zed all clean: + make -C a10gx clean make -C ac701 clean make -C kc705 clean make -C mitx045 clean make -C vc707 clean make -C zc702 clean make -C zc706 clean + make -C zc706pr clean + make -C zcu102 clean make -C zed clean clean-all: + make -C a10gx clean-all make -C ac701 clean-all make -C kc705 clean-all make -C mitx045 clean-all make -C vc707 clean-all make -C zc702 clean-all make -C zc706 clean-all + make -C zc706pr clean-all + make -C zcu102 clean-all make -C zed clean-all #################################################################################### diff --git a/projects/fmcomms2/a10gx/Makefile b/projects/fmcomms2/a10gx/Makefile new file mode 100644 index 000000000..17d0a9aca --- /dev/null +++ b/projects/fmcomms2/a10gx/Makefile @@ -0,0 +1,156 @@ +#################################################################################### +#################################################################################### +## Copyright 2011(c) Analog Devices, Inc. +## Auto-generated, do not modify! +#################################################################################### +#################################################################################### + +ifeq ($(MMU),) + MMU := 1 +endif + +export ALT_NIOS_MMU_ENABLED := $(MMU) + +M_DEPS += system_top.v +M_DEPS += system_qsys.tcl +M_DEPS += system_project.tcl +M_DEPS += system_constr.sdc +M_DEPS += ../common/fmcomms2_qsys.tcl +M_DEPS += ../../scripts/adi_tquest.tcl +M_DEPS += ../../scripts/adi_env.tcl +M_DEPS += ../../common/altera/sys_gen.tcl +M_DEPS += ../../common/a10gx/a10gx_system_qsys.tcl +M_DEPS += ../../common/a10gx/a10gx_system_assign.tcl +M_DEPS += ../../../library/altera/common/ad_cmos_out_core_c5.v +M_DEPS += ../../../library/altera/common/ad_dcfilter.v +M_DEPS += ../../../library/altera/common/ad_mul.v +M_DEPS += ../../../library/altera/common/ad_serdes_in_core_c5.v +M_DEPS += ../../../library/altera/common/ad_serdes_out_core_c5.v +M_DEPS += ../../../library/axi_ad9361/altera/axi_ad9361_cmos_if.v +M_DEPS += ../../../library/axi_ad9361/altera/axi_ad9361_lvds_if.v +M_DEPS += ../../../library/axi_ad9361/axi_ad9361.v +M_DEPS += ../../../library/axi_ad9361/axi_ad9361_constr.sdc +M_DEPS += ../../../library/axi_ad9361/axi_ad9361_hw.tcl +M_DEPS += ../../../library/axi_ad9361/axi_ad9361_rx.v +M_DEPS += ../../../library/axi_ad9361/axi_ad9361_rx_channel.v +M_DEPS += ../../../library/axi_ad9361/axi_ad9361_rx_pnmon.v +M_DEPS += ../../../library/axi_ad9361/axi_ad9361_tdd.v +M_DEPS += ../../../library/axi_ad9361/axi_ad9361_tdd_if.v +M_DEPS += ../../../library/axi_ad9361/axi_ad9361_tx.v +M_DEPS += ../../../library/axi_ad9361/axi_ad9361_tx_channel.v +M_DEPS += ../../../library/axi_dmac/2d_transfer.v +M_DEPS += ../../../library/axi_dmac/address_generator.v +M_DEPS += ../../../library/axi_dmac/axi_dmac.v +M_DEPS += ../../../library/axi_dmac/axi_dmac_constr.sdc +M_DEPS += ../../../library/axi_dmac/axi_dmac_hw.tcl +M_DEPS += ../../../library/axi_dmac/axi_register_slice.v +M_DEPS += ../../../library/axi_dmac/data_mover.v +M_DEPS += ../../../library/axi_dmac/dest_axi_mm.v +M_DEPS += ../../../library/axi_dmac/dest_axi_stream.v +M_DEPS += ../../../library/axi_dmac/dest_fifo_inf.v +M_DEPS += ../../../library/axi_dmac/inc_id.h +M_DEPS += ../../../library/axi_dmac/request_arb.v +M_DEPS += ../../../library/axi_dmac/request_generator.v +M_DEPS += ../../../library/axi_dmac/resp.h +M_DEPS += ../../../library/axi_dmac/response_generator.v +M_DEPS += ../../../library/axi_dmac/response_handler.v +M_DEPS += ../../../library/axi_dmac/splitter.v +M_DEPS += ../../../library/axi_dmac/src_axi_mm.v +M_DEPS += ../../../library/axi_dmac/src_axi_stream.v +M_DEPS += ../../../library/axi_dmac/src_fifo_inf.v +M_DEPS += ../../../library/common/ad_addsub.v +M_DEPS += ../../../library/common/ad_axi_ip_constr.sdc +M_DEPS += ../../../library/common/ad_datafmt.v +M_DEPS += ../../../library/common/ad_dds.v +M_DEPS += ../../../library/common/ad_dds_1.v +M_DEPS += ../../../library/common/ad_dds_sine.v +M_DEPS += ../../../library/common/ad_iqcor.v +M_DEPS += ../../../library/common/ad_mem.v +M_DEPS += ../../../library/common/ad_pnmon.v +M_DEPS += ../../../library/common/ad_rst.v +M_DEPS += ../../../library/common/ad_tdd_control.v +M_DEPS += ../../../library/common/sync_bits.v +M_DEPS += ../../../library/common/sync_gray.v +M_DEPS += ../../../library/common/up_adc_channel.v +M_DEPS += ../../../library/common/up_adc_common.v +M_DEPS += ../../../library/common/up_axi.v +M_DEPS += ../../../library/common/up_clock_mon.v +M_DEPS += ../../../library/common/up_dac_channel.v +M_DEPS += ../../../library/common/up_dac_common.v +M_DEPS += ../../../library/common/up_delay_cntrl.v +M_DEPS += ../../../library/common/up_tdd_cntrl.v +M_DEPS += ../../../library/common/up_xfer_cntrl.v +M_DEPS += ../../../library/common/up_xfer_status.v +M_DEPS += ../../../library/scripts/adi_env.tcl +M_DEPS += ../../../library/scripts/adi_ip_alt.tcl +M_DEPS += ../../../library/util_axis_fifo/address_gray.v +M_DEPS += ../../../library/util_axis_fifo/address_gray_pipelined.v +M_DEPS += ../../../library/util_axis_fifo/address_sync.v +M_DEPS += ../../../library/util_axis_fifo/util_axis_fifo.v +M_DEPS += ../../../library/util_axis_resize/util_axis_resize.v +M_DEPS += ../../../library/util_cpack/util_cpack.v +M_DEPS += ../../../library/util_cpack/util_cpack_dsf.v +M_DEPS += ../../../library/util_cpack/util_cpack_hw.tcl +M_DEPS += ../../../library/util_cpack/util_cpack_mux.v +M_DEPS += ../../../library/util_upack/util_upack.v +M_DEPS += ../../../library/util_upack/util_upack_dmx.v +M_DEPS += ../../../library/util_upack/util_upack_dsf.v +M_DEPS += ../../../library/util_upack/util_upack_hw.tcl +M_DEPS += ../../../library/util_wfifo/util_wfifo.v +M_DEPS += ../../../library/util_wfifo/util_wfifo_constr.sdc +M_DEPS += ../../../library/util_wfifo/util_wfifo_hw.tcl + + +M_ALTERA := quartus_sh --64bit -t + + +M_FLIST += *.log +M_FLIST += *_INFO.txt +M_FLIST += *_dump.txt +M_FLIST += db +M_FLIST += *.asm.rpt +M_FLIST += *.done +M_FLIST += *.eda.rpt +M_FLIST += *.fit.* +M_FLIST += *.map.* +M_FLIST += *.sta.* +M_FLIST += *.qsf +M_FLIST += *.qpf +M_FLIST += *.qws +M_FLIST += *.sof +M_FLIST += *.cdf +M_FLIST += *.sld +M_FLIST += *.qdf +M_FLIST += hc_output +M_FLIST += system_bd +M_FLIST += hps_isw_handoff +M_FLIST += hps_sdram_*.csv +M_FLIST += *ddr3_*.csv +M_FLIST += incremental_db +M_FLIST += reconfig_mif +M_FLIST += *.sopcinfo +M_FLIST += *.jdi +M_FLIST += *.pin +M_FLIST += *_summary.csv +M_FLIST += *.dpf + + + +.PHONY: all clean clean-all +all: fmcomms2_a10gx.sof + + + +clean:clean-all + + +clean-all: + rm -rf $(M_FLIST) + + +fmcomms2_a10gx.sof: $(M_DEPS) + -rm -rf $(M_FLIST) + $(M_ALTERA) system_project.tcl >> fmcomms2_a10gx_quartus.log 2>&1 + +#################################################################################### +#################################################################################### diff --git a/projects/fmcomms2/a10gx/system_constr.sdc b/projects/fmcomms2/a10gx/system_constr.sdc new file mode 100644 index 000000000..6274154c7 --- /dev/null +++ b/projects/fmcomms2/a10gx/system_constr.sdc @@ -0,0 +1,17 @@ + +create_clock -period "10.000 ns" -name sys_clk_100mhz [get_ports {sys_clk}] +create_clock -period "4.000 ns" -name rx_clk_250mhz [get_ports {rx_clk}] + +derive_pll_clocks +derive_clock_uncertainty + +set_false_path -from [get_clocks {sys_clk_100mhz}] -to [get_clocks {\ + i_system_bd|sys_ddr3_cntrl_phy_clk_0 \ + i_system_bd|sys_ddr3_cntrl_phy_clk_1 \ + i_system_bd|sys_ddr3_cntrl_phy_clk_2 \ + i_system_bd|sys_ddr3_cntrl_phy_clk_l_0 \ + i_system_bd|sys_ddr3_cntrl_phy_clk_l_1 \ + i_system_bd|sys_ddr3_cntrl_phy_clk_l_2}] + +set_false_path -from [get_clocks {sys_clk_100mhz}] -to [get_clocks {\ + i_system_bd|sys_ddr3_cntrl_core_nios_clk}] diff --git a/projects/fmcomms2/a10gx/system_project.tcl b/projects/fmcomms2/a10gx/system_project.tcl new file mode 100644 index 000000000..5a2fb02c5 --- /dev/null +++ b/projects/fmcomms2/a10gx/system_project.tcl @@ -0,0 +1,119 @@ + +load_package flow + +source ../../scripts/adi_env.tcl +project_new fmcomms2_a10gx -overwrite + +source "../../common/a10gx/a10gx_system_assign.tcl" + +set_global_assignment -name VERILOG_FILE system_top.v +set_global_assignment -name QSYS_FILE system_bd.qsys + +set_global_assignment -name SDC_FILE system_constr.sdc +set_global_assignment -name TOP_LEVEL_ENTITY system_top + +# lane interface + +set_location_assignment PIN_AV15 -to rx_clk_in ; ## G6 FMC_LPC_LA00_CC_P (3B) +set_location_assignment PIN_AU15 -to "rx_clk_in(n)" ; ## G7 FMC_LPC_LA00_CC_N (3B) +set_location_assignment PIN_AV19 -to rx_frame_in ; ## D20 FMC_LPC_LA17_CC_P (3B) ## D8 FMC_LPC_LA01_CC_P (3C) PIN_AT10 +set_location_assignment PIN_AW19 -to "rx_frame_in(n)" ; ## D21 FMC_LPC_LA17_CC_N (3B) ## D9 FMC_LPC_LA01_CC_N (3C) PIN_AR11 +set_location_assignment PIN_AR22 -to rx_data_in[0] ; ## H7 FMC_LPC_LA02_P (3B) +set_location_assignment PIN_AT22 -to "rx_data_in[0](n)" ; ## H8 FMC_LPC_LA02_N (3B) +set_location_assignment PIN_AR20 -to rx_data_in[1] ; ## G9 FMC_LPC_LA03_P (3B) +set_location_assignment PIN_AR19 -to "rx_data_in[1](n)" ; ## G10 FMC_LPC_LA03_N (3B) +set_location_assignment PIN_AN20 -to rx_data_in[2] ; ## H10 FMC_LPC_LA04_P (3B) +set_location_assignment PIN_AP19 -to "rx_data_in[2](n)" ; ## H11 FMC_LPC_LA04_N (3B) +set_location_assignment PIN_AU21 -to rx_data_in[3] ; ## C22 FMC_LPC_LA18_CC_P (3B) ## D11 FMC_LPC_LA05_P (3C) PIN_AV11 +set_location_assignment PIN_AV21 -to "rx_data_in[3](n)" ; ## C23 FMC_LPC_LA18_CC_N (3B) ## D12 FMC_LPC_LA05_N (3C) PIN_AW11 +set_location_assignment PIN_AV14 -to rx_data_in[4] ; ## C10 FMC_LPC_LA06_P (3B) +set_location_assignment PIN_AW14 -to "rx_data_in[4](n)" ; ## C11 FMC_LPC_LA06_N (3B) +set_location_assignment PIN_AT17 -to rx_data_in[5] ; ## H13 FMC_LPC_LA07_P (3B) +set_location_assignment PIN_AU17 -to "rx_data_in[5](n)" ; ## H14 FMC_LPC_LA07_N (3B) +set_location_assignment PIN_AP18 -to tx_clk_out ; ## G12 FMC_LPC_LA08_P (3B) +set_location_assignment PIN_AN19 -to "tx_clk_out(n)" ; ## G13 FMC_LPC_LA08_N (3B) +set_location_assignment PIN_AV20 -to tx_frame_out ; ## H37 FMC_LPC_LA32_P (3B) ## D14 FMC_LPC_LA09_P (3C) PIN_AW13 +set_location_assignment PIN_AU20 -to "tx_frame_out(n)" ; ## H38 FMC_LPC_LA32_N (3B) ## D15 FMC_LPC_LA09_N (3C) PIN_AV13 +set_location_assignment PIN_AT14 -to tx_data_out[0] ; ## H16 FMC_LPC_LA11_P (3B) +set_location_assignment PIN_AR14 -to "tx_data_out[0](n)" ; ## H17 FMC_LPC_LA11_N (3B) +set_location_assignment PIN_AR16 -to tx_data_out[1] ; ## G15 FMC_LPC_LA12_P (3B) +set_location_assignment PIN_AP16 -to "tx_data_out[1](n)" ; ## G16 FMC_LPC_LA12_N (3B) +set_location_assignment PIN_AR17 -to tx_data_out[2] ; ## D17 FMC_LPC_LA13_P (3B) +set_location_assignment PIN_AP17 -to "tx_data_out[2](n)" ; ## D18 FMC_LPC_LA13_N (3B) +set_location_assignment PIN_AR15 -to tx_data_out[3] ; ## C14 FMC_LPC_LA10_P (3B) +set_location_assignment PIN_AT15 -to "tx_data_out[3](n)" ; ## C15 FMC_LPC_LA10_N (3B) +set_location_assignment PIN_AW18 -to tx_data_out[4] ; ## C18 FMC_LPC_LA14_P (3B) +set_location_assignment PIN_AV18 -to "tx_data_out[4](n)" ; ## C19 FMC_LPC_LA14_N (3B) +set_location_assignment PIN_AY17 -to tx_data_out[5] ; ## G36 FMC_LPC_LA33_P (3B) ## H19 FMC_LPC_LA15_P (3C) PIN_AR9 +set_location_assignment PIN_AW17 -to "tx_data_out[5](n)" ; ## G37 FMC_LPC_LA33_N (3B) ## H20 FMC_LPC_LA15_N (3C) PIN_AT9 + +set_instance_assignment -name IO_STANDARD LVDS -to rx_clk_in +set_instance_assignment -name IO_STANDARD LVDS -to rx_frame_in +set_instance_assignment -name IO_STANDARD LVDS -to rx_data_in[0] +set_instance_assignment -name IO_STANDARD LVDS -to rx_data_in[1] +set_instance_assignment -name IO_STANDARD LVDS -to rx_data_in[2] +set_instance_assignment -name IO_STANDARD LVDS -to rx_data_in[3] +set_instance_assignment -name IO_STANDARD LVDS -to rx_data_in[4] +set_instance_assignment -name IO_STANDARD LVDS -to rx_data_in[5] +set_instance_assignment -name IO_STANDARD LVDS -to tx_clk_out +set_instance_assignment -name IO_STANDARD LVDS -to tx_frame_out +set_instance_assignment -name IO_STANDARD LVDS -to tx_data_out[0] +set_instance_assignment -name IO_STANDARD LVDS -to tx_data_out[1] +set_instance_assignment -name IO_STANDARD LVDS -to tx_data_out[2] +set_instance_assignment -name IO_STANDARD LVDS -to tx_data_out[3] +set_instance_assignment -name IO_STANDARD LVDS -to tx_data_out[4] +set_instance_assignment -name IO_STANDARD LVDS -to tx_data_out[5] + +set_location_assignment PIN_AT13 -to enable] ; ## G18 FMC_LPC_LA16_P +set_location_assignment PIN_AU13 -to txnrx] ; ## G19 FMC_LPC_LA16_N + +set_instance_assignment -name IO_STANDARD "1.8 V" -to enable +set_instance_assignment -name IO_STANDARD "1.8 V" -to txnrx + +# gpio + +set_location_assignment PIN_AU8 -to gpio_status[0] ; ## G21 FMC_LPC_LA20_P +set_location_assignment PIN_AT8 -to gpio_status[1] ; ## G22 FMC_LPC_LA20_N +set_location_assignment PIN_AY10 -to gpio_status[2] ; ## H25 FMC_LPC_LA21_P +set_location_assignment PIN_AY11 -to gpio_status[3] ; ## H26 FMC_LPC_LA21_N +set_location_assignment PIN_AW12 -to gpio_status[4] ; ## G24 FMC_LPC_LA22_P +set_location_assignment PIN_AY12 -to gpio_status[5] ; ## G25 FMC_LPC_LA22_N +set_location_assignment PIN_AU18 -to gpio_status[6] ; ## D23 FMC_LPC_LA23_P +set_location_assignment PIN_AT18 -to gpio_status[7] ; ## D24 FMC_LPC_LA23_N +set_location_assignment PIN_BB15 -to gpio_ctl[0] ; ## H28 FMC_LPC_LA24_P +set_location_assignment PIN_BC15 -to gpio_ctl[1] ; ## H29 FMC_LPC_LA24_N +set_location_assignment PIN_AY15 -to gpio_ctl[2] ; ## G27 FMC_LPC_LA25_P +set_location_assignment PIN_AY14 -to gpio_ctl[3] ; ## G28 FMC_LPC_LA25_N +set_location_assignment PIN_AU11 -to gpio_en_agc ; ## H22 FMC_LPC_LA19_P +set_location_assignment PIN_AU12 -to gpio_sync ; ## H23 FMC_LPC_LA19_N +set_location_assignment PIN_AY16 -to gpio_resetb ; ## H31 FMC_LPC_LA28_P + +set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_status[0] +set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_status[1] +set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_status[2] +set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_status[3] +set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_status[4] +set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_status[5] +set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_status[6] +set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_status[7] +set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_ctl[0] +set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_ctl[1] +set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_ctl[2] +set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_ctl[3] +set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_en_agc +set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_sync +set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_resetb + +# spi + +set_location_assignment PIN_AT19 -to spi_csn ; ## D26 FMC_LPC_LA26_P +set_location_assignment PIN_AT20 -to spi_clk ; ## D27 FMC_LPC_LA26_N +set_location_assignment PIN_AP21 -to spi_mosi ; ## C26 FMC_LPC_LA27_P +set_location_assignment PIN_AR21 -to spi_miso ; ## C27 FMC_LPC_LA27_N + +set_instance_assignment -name IO_STANDARD "1.8 V" -to spi_csn +set_instance_assignment -name IO_STANDARD "1.8 V" -to spi_clk +set_instance_assignment -name IO_STANDARD "1.8 V" -to spi_mosi +set_instance_assignment -name IO_STANDARD "1.8 V" -to spi_miso + +execute_flow -compile diff --git a/projects/fmcomms2/a10gx/system_qsys.tcl b/projects/fmcomms2/a10gx/system_qsys.tcl new file mode 100644 index 000000000..0e76976f5 --- /dev/null +++ b/projects/fmcomms2/a10gx/system_qsys.tcl @@ -0,0 +1,5 @@ + +source $ad_hdl_dir/projects/common/a10gx/a10gx_system_qsys.tcl +source ../common/fmcomms2_qsys.tcl + + diff --git a/projects/fmcomms2/a10gx/system_top.v b/projects/fmcomms2/a10gx/system_top.v new file mode 100644 index 000000000..b326ff43a --- /dev/null +++ b/projects/fmcomms2/a10gx/system_top.v @@ -0,0 +1,250 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top ( + + // clock and resets + + sys_clk, + sys_resetn, + + // ddr3 + + ddr3_clk_p, + ddr3_clk_n, + ddr3_a, + ddr3_ba, + ddr3_cke, + ddr3_cs_n, + ddr3_odt, + ddr3_reset_n, + ddr3_we_n, + ddr3_ras_n, + ddr3_cas_n, + ddr3_dqs_p, + ddr3_dqs_n, + ddr3_dq, + ddr3_dm, + ddr3_rzq, + ddr3_ref_clk, + + // ethernet + + eth_ref_clk, + eth_rxd, + eth_txd, + eth_mdc, + eth_mdio, + eth_resetn, + eth_intn, + + // board gpio + + gpio_bd_i, + gpio_bd_o, + + // ad9361-interface + + rx_clk_in, + rx_frame_in, + rx_data_in, + tx_clk_out, + tx_frame_out, + tx_data_out, + + enable, + txnrx, + + gpio_resetb, + gpio_sync, + gpio_en_agc, + gpio_ctl, + gpio_status, + + spi_csn, + spi_clk, + spi_mosi, + spi_miso); + + + // clock and resets + + input sys_clk; + input sys_resetn; + + // ddr3 + + output ddr3_clk_p; + output ddr3_clk_n; + output [ 14:0] ddr3_a; + output [ 2:0] ddr3_ba; + output ddr3_cke; + output ddr3_cs_n; + output ddr3_odt; + output ddr3_reset_n; + output ddr3_we_n; + output ddr3_ras_n; + output ddr3_cas_n; + inout [ 7:0] ddr3_dqs_p; + inout [ 7:0] ddr3_dqs_n; + inout [ 63:0] ddr3_dq; + output [ 7:0] ddr3_dm; + input ddr3_rzq; + input ddr3_ref_clk; + + // ethernet + + input eth_ref_clk; + input eth_rxd; + output eth_txd; + output eth_mdc; + inout eth_mdio; + output eth_resetn; + input eth_intn; + + // board gpio + + input [ 10:0] gpio_bd_i; + output [ 15:0] gpio_bd_o; + + // ad9361-interface + + input rx_clk_in; + input rx_frame_in; + input [ 5:0] rx_data_in; + output tx_clk_out; + output tx_frame_out; + output [ 5:0] tx_data_out; + output enable; + output txnrx; + + output gpio_resetb; + output gpio_sync; + output gpio_en_agc; + output [ 3:0] gpio_ctl; + input [ 7:0] gpio_status; + + output spi_csn; + output spi_clk; + output spi_mosi; + input spi_miso; + + // internal signals + + wire [63:0] gpio_i; + wire [63:0] gpio_o; + wire [63:0] gpio_t; + + // conections + + assign gpio_resetb = gpio_o[46]; + assign gpio_sync = gpio_o[45]; + assign gpio_en_agc = gpio_o[44]; + assign gpio_ctl = gpio_o[43:40]; + assign gpio_i[39:32] = gpio_status; + + assign gpio_bd_o = gpio_o[15:0]; + + assign gpio_i[31:27] = gpio_o[31:27]; + assign gpio_i[15: 0] = gpio_o[15:0]; + assign gpio_i[26:16] = gpio_bd_i; + + // instantiations + + system_bd i_system_bd ( + .sys_clk_clk (sys_clk), + .sys_rst_reset_n (sys_resetn), + + .sys_ddr3_cntrl_mem_mem_ck (ddr3_clk_p), + .sys_ddr3_cntrl_mem_mem_ck_n (ddr3_clk_n), + .sys_ddr3_cntrl_mem_mem_a (ddr3_a[11:0]), + .sys_ddr3_cntrl_mem_mem_ba (ddr3_ba), + .sys_ddr3_cntrl_mem_mem_cke (ddr3_cke), + .sys_ddr3_cntrl_mem_mem_cs_n (ddr3_cs_n), + .sys_ddr3_cntrl_mem_mem_odt (ddr3_odt), + .sys_ddr3_cntrl_mem_mem_reset_n (ddr3_reset_n), + .sys_ddr3_cntrl_mem_mem_we_n (ddr3_we_n), + .sys_ddr3_cntrl_mem_mem_ras_n (ddr3_ras_n), + .sys_ddr3_cntrl_mem_mem_cas_n (ddr3_cas_n), + .sys_ddr3_cntrl_mem_mem_dqs (ddr3_dqs_p[7:0]), + .sys_ddr3_cntrl_mem_mem_dqs_n (ddr3_dqs_n[7:0]), + .sys_ddr3_cntrl_mem_mem_dq (ddr3_dq[63:0]), + .sys_ddr3_cntrl_mem_mem_dm (ddr3_dm[7:0]), + .sys_ddr3_cntrl_oct_oct_rzqin (ddr3_rzq), + .sys_ddr3_cntrl_pll_ref_clk_clk (ddr3_ref_clk), + + .sys_ethernet_mdio_mdc (eth_mdc), + .sys_ethernet_mdio_mdio_in (eth_mdio_i), + .sys_ethernet_mdio_mdio_out (eth_mdio_o), + .sys_ethernet_mdio_mdio_oen (eth_mdio_t), + .sys_ethernet_ref_clk_clk (eth_ref_clk), + .sys_ethernet_reset_reset (eth_reset), + .sys_ethernet_sgmii_rxp_0 (eth_rxd), + .sys_ethernet_sgmii_txp_0 (eth_txd), + + .sys_gpio_bd_in_port (gpio_i[31:0]), + .sys_gpio_bd_out_port (gpio_o[31:0]), + .sys_gpio_in_export (gpio_i[63:32]), + .sys_gpio_out_export (gpio_o[63:32]), + + .axi_ad9361_device_if_enable (enable), + .axi_ad9361_device_if_rx_clk_in_p (rx_clk_in), + .axi_ad9361_device_if_rx_clk_in_n (1'b0), + .axi_ad9361_device_if_rx_data_in_p (rx_data_in), + .axi_ad9361_device_if_rx_data_in_n (6'd0), + .axi_ad9361_device_if_rx_frame_in_p (rx_frame_in), + .axi_ad9361_device_if_rx_frame_in_n (1'b0), + .axi_ad9361_device_if_tx_clk_out_p (tx_clk_out), + .axi_ad9361_device_if_tx_clk_out_n (1'b0), + .axi_ad9361_device_if_tx_data_out_p (tx_data_out), + .axi_ad9361_device_if_tx_data_out_n (6'd0), + .axi_ad9361_device_if_tx_frame_out_p (tx_frame_out), + .axi_ad9361_device_if_tx_frame_out_n (1'b0), + .axi_ad9361_device_if_txnrx (txnrx), + + .delay_clk_clk (1'b0), + + .up_enable_up_enable (gpio_o[47]), + .up_txnrx_up_txnrx (gpio_o[48])); + +endmodule + + +// *************************************************************************** +// *************************************************************************** diff --git a/projects/fmcomms2/ac701/Makefile b/projects/fmcomms2/ac701/Makefile index 03282725e..7c6e6a2fd 100644 --- a/projects/fmcomms2/ac701/Makefile +++ b/projects/fmcomms2/ac701/Makefile @@ -17,10 +17,12 @@ M_DEPS += ../../common/xilinx/sys_wfifo.tcl M_DEPS += ../../common/ac701/ac701_system_mig.prj M_DEPS += ../../common/ac701/ac701_system_constr.xdc M_DEPS += ../../common/ac701/ac701_system_bd.tcl -M_DEPS += ../../../library/common/ad_iobuf.v +M_DEPS += ../../../library/xilinx/common/ad_iobuf.v M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr +M_DEPS += ../../../library/util_clkdiv/util_clkdiv.xpr M_DEPS += ../../../library/util_cpack/util_cpack.xpr +M_DEPS += ../../../library/util_rfifo/util_rfifo.xpr M_DEPS += ../../../library/util_tdd_sync/util_tdd_sync.xpr M_DEPS += ../../../library/util_upack/util_upack.xpr M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr @@ -39,6 +41,7 @@ M_FLIST += *.sdk M_FLIST += *.hw M_FLIST += *.sim M_FLIST += .Xil +M_FLIST += *.ip_user_files @@ -53,21 +56,25 @@ clean: clean-all:clean make -C ../../../library/axi_ad9361 clean make -C ../../../library/axi_dmac clean + make -C ../../../library/util_clkdiv clean make -C ../../../library/util_cpack clean + make -C ../../../library/util_rfifo clean make -C ../../../library/util_tdd_sync clean make -C ../../../library/util_upack clean make -C ../../../library/util_wfifo clean fmcomms2_ac701.sdk/system_top.hdf: $(M_DEPS) - rm -rf $(M_FLIST) + -rm -rf $(M_FLIST) $(M_VIVADO) system_project.tcl >> fmcomms2_ac701_vivado.log 2>&1 lib: make -C ../../../library/axi_ad9361 make -C ../../../library/axi_dmac + make -C ../../../library/util_clkdiv make -C ../../../library/util_cpack + make -C ../../../library/util_rfifo make -C ../../../library/util_tdd_sync make -C ../../../library/util_upack make -C ../../../library/util_wfifo diff --git a/projects/fmcomms2/ac701/system_project.tcl b/projects/fmcomms2/ac701/system_project.tcl index b7a5bf4cd..9338fd190 100644 --- a/projects/fmcomms2/ac701/system_project.tcl +++ b/projects/fmcomms2/ac701/system_project.tcl @@ -7,7 +7,7 @@ adi_project_create fmcomms2_ac701 adi_project_files fmcomms2_ac701 [list \ "system_top.v" \ "system_constr.xdc"\ - "$ad_hdl_dir/library/common/ad_iobuf.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \ "$ad_hdl_dir/projects/common/ac701/ac701_system_constr.xdc" ] adi_project_run fmcomms2_ac701 diff --git a/projects/fmcomms2/common/fmcomms2_bd.tcl b/projects/fmcomms2/common/fmcomms2_bd.tcl index 6741c7c8b..bfecb54ad 100644 --- a/projects/fmcomms2/common/fmcomms2_bd.tcl +++ b/projects/fmcomms2/common/fmcomms2_bd.tcl @@ -64,90 +64,129 @@ set_property -dict [list CONFIG.DIN_DATA_WIDTH {16}] $util_ad9361_adc_fifo set_property -dict [list CONFIG.DOUT_DATA_WIDTH {16}] $util_ad9361_adc_fifo set util_ad9361_tdd_sync [create_bd_cell -type ip -vlnv analog.com:user:util_tdd_sync:1.0 util_ad9361_tdd_sync] +set_property -dict [list CONFIG.TDD_SYNC_PERIOD {10000000}] $util_ad9361_tdd_sync + +set clkdiv [ create_bd_cell -type ip -vlnv analog.com:user:util_clkdiv:1.0 clkdiv ] + +set clkdiv_reset [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 clkdiv_reset] + +set dac_fifo [create_bd_cell -type ip -vlnv analog.com:user:util_rfifo:1.0 dac_fifo] +set_property -dict [list CONFIG.DIN_DATA_WIDTH {16}] $dac_fifo +set_property -dict [list CONFIG.DOUT_DATA_WIDTH {16}] $dac_fifo +set_property -dict [list CONFIG.DIN_ADDRESS_WIDTH {4}] $dac_fifo + +set clkdiv_sel_logic [create_bd_cell -type ip -vlnv xilinx.com:ip:util_reduced_logic:2.0 clkdiv_sel_logic] +set_property -dict [list CONFIG.C_SIZE {2}] $clkdiv_sel_logic + +set concat_logic [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 concat_logic] +set_property -dict [list CONFIG.NUM_PORTS {2}] $concat_logic # connections -ad_connect sys_200m_clk axi_ad9361/delay_clk -ad_connect axi_ad9361_clk axi_ad9361/l_clk -ad_connect axi_ad9361_clk axi_ad9361/clk -ad_connect rx_clk_in_p axi_ad9361/rx_clk_in_p -ad_connect rx_clk_in_n axi_ad9361/rx_clk_in_n -ad_connect rx_frame_in_p axi_ad9361/rx_frame_in_p -ad_connect rx_frame_in_n axi_ad9361/rx_frame_in_n -ad_connect rx_data_in_p axi_ad9361/rx_data_in_p -ad_connect rx_data_in_n axi_ad9361/rx_data_in_n -ad_connect tx_clk_out_p axi_ad9361/tx_clk_out_p -ad_connect tx_clk_out_n axi_ad9361/tx_clk_out_n -ad_connect tx_frame_out_p axi_ad9361/tx_frame_out_p -ad_connect tx_frame_out_n axi_ad9361/tx_frame_out_n -ad_connect tx_data_out_p axi_ad9361/tx_data_out_p -ad_connect tx_data_out_n axi_ad9361/tx_data_out_n -ad_connect enable axi_ad9361/enable -ad_connect txnrx axi_ad9361/txnrx -ad_connect up_enable axi_ad9361/up_enable -ad_connect up_txnrx axi_ad9361/up_txnrx -ad_connect axi_ad9361_clk util_ad9361_adc_fifo/din_clk -ad_connect axi_ad9361/rst util_ad9361_adc_fifo/din_rst -ad_connect sys_cpu_clk util_ad9361_adc_fifo/dout_clk -ad_connect sys_cpu_resetn util_ad9361_adc_fifo/dout_rstn -ad_connect sys_cpu_clk util_ad9361_adc_pack/adc_clk -ad_connect sys_cpu_reset util_ad9361_adc_pack/adc_rst -ad_connect sys_cpu_clk axi_ad9361_adc_dma/fifo_wr_clk -ad_connect axi_ad9361/adc_enable_i0 util_ad9361_adc_fifo/din_enable_0 -ad_connect axi_ad9361/adc_valid_i0 util_ad9361_adc_fifo/din_valid_0 -ad_connect axi_ad9361/adc_data_i0 util_ad9361_adc_fifo/din_data_0 -ad_connect axi_ad9361/adc_enable_q0 util_ad9361_adc_fifo/din_enable_1 -ad_connect axi_ad9361/adc_valid_q0 util_ad9361_adc_fifo/din_valid_1 -ad_connect axi_ad9361/adc_data_q0 util_ad9361_adc_fifo/din_data_1 -ad_connect axi_ad9361/adc_enable_i1 util_ad9361_adc_fifo/din_enable_2 -ad_connect axi_ad9361/adc_valid_i1 util_ad9361_adc_fifo/din_valid_2 -ad_connect axi_ad9361/adc_data_i1 util_ad9361_adc_fifo/din_data_2 -ad_connect axi_ad9361/adc_enable_q1 util_ad9361_adc_fifo/din_enable_3 -ad_connect axi_ad9361/adc_valid_q1 util_ad9361_adc_fifo/din_valid_3 -ad_connect axi_ad9361/adc_data_q1 util_ad9361_adc_fifo/din_data_3 -ad_connect util_ad9361_adc_fifo/dout_enable_0 util_ad9361_adc_pack/adc_enable_0 -ad_connect util_ad9361_adc_fifo/dout_valid_0 util_ad9361_adc_pack/adc_valid_0 -ad_connect util_ad9361_adc_fifo/dout_data_0 util_ad9361_adc_pack/adc_data_0 -ad_connect util_ad9361_adc_fifo/dout_enable_1 util_ad9361_adc_pack/adc_enable_1 -ad_connect util_ad9361_adc_fifo/dout_valid_1 util_ad9361_adc_pack/adc_valid_1 -ad_connect util_ad9361_adc_fifo/dout_data_1 util_ad9361_adc_pack/adc_data_1 -ad_connect util_ad9361_adc_fifo/dout_enable_2 util_ad9361_adc_pack/adc_enable_2 -ad_connect util_ad9361_adc_fifo/dout_valid_2 util_ad9361_adc_pack/adc_valid_2 -ad_connect util_ad9361_adc_fifo/dout_data_2 util_ad9361_adc_pack/adc_data_2 -ad_connect util_ad9361_adc_fifo/dout_enable_3 util_ad9361_adc_pack/adc_enable_3 -ad_connect util_ad9361_adc_fifo/dout_valid_3 util_ad9361_adc_pack/adc_valid_3 -ad_connect util_ad9361_adc_fifo/dout_data_3 util_ad9361_adc_pack/adc_data_3 -ad_connect util_ad9361_adc_pack/adc_valid axi_ad9361_adc_dma/fifo_wr_en -ad_connect util_ad9361_adc_pack/adc_sync axi_ad9361_adc_dma/fifo_wr_sync -ad_connect util_ad9361_adc_pack/adc_data axi_ad9361_adc_dma/fifo_wr_din -ad_connect axi_ad9361_adc_dma/fifo_wr_overflow util_ad9361_adc_fifo/dout_ovf -ad_connect util_ad9361_adc_fifo/din_ovf axi_ad9361/adc_dovf -ad_connect axi_ad9361_clk util_ad9361_dac_upack/dac_clk -ad_connect axi_ad9361_clk axi_ad9361_dac_dma/fifo_rd_clk -ad_connect util_ad9361_dac_upack/dac_enable_0 axi_ad9361/dac_enable_i0 -ad_connect util_ad9361_dac_upack/dac_valid_0 axi_ad9361/dac_valid_i0 -ad_connect util_ad9361_dac_upack/dac_data_0 axi_ad9361/dac_data_i0 -ad_connect util_ad9361_dac_upack/dac_enable_1 axi_ad9361/dac_enable_q0 -ad_connect util_ad9361_dac_upack/dac_valid_1 axi_ad9361/dac_valid_q0 -ad_connect util_ad9361_dac_upack/dac_data_1 axi_ad9361/dac_data_q0 -ad_connect util_ad9361_dac_upack/dac_enable_2 axi_ad9361/dac_enable_i1 -ad_connect util_ad9361_dac_upack/dac_valid_2 axi_ad9361/dac_valid_i1 -ad_connect util_ad9361_dac_upack/dac_data_2 axi_ad9361/dac_data_i1 -ad_connect util_ad9361_dac_upack/dac_enable_3 axi_ad9361/dac_enable_q1 -ad_connect util_ad9361_dac_upack/dac_valid_3 axi_ad9361/dac_valid_q1 -ad_connect util_ad9361_dac_upack/dac_data_3 axi_ad9361/dac_data_q1 -ad_connect util_ad9361_dac_upack/dac_valid axi_ad9361_dac_dma/fifo_rd_en -ad_connect util_ad9361_dac_upack/dac_data axi_ad9361_dac_dma/fifo_rd_dout -ad_connect axi_ad9361_dac_dma/fifo_rd_underflow axi_ad9361/dac_dunf +ad_connect sys_200m_clk axi_ad9361/delay_clk +ad_connect axi_ad9361_clk axi_ad9361/l_clk +ad_connect axi_ad9361_clk axi_ad9361/clk +ad_connect rx_clk_in_p axi_ad9361/rx_clk_in_p +ad_connect rx_clk_in_n axi_ad9361/rx_clk_in_n +ad_connect rx_frame_in_p axi_ad9361/rx_frame_in_p +ad_connect rx_frame_in_n axi_ad9361/rx_frame_in_n +ad_connect rx_data_in_p axi_ad9361/rx_data_in_p +ad_connect rx_data_in_n axi_ad9361/rx_data_in_n +ad_connect tx_clk_out_p axi_ad9361/tx_clk_out_p +ad_connect tx_clk_out_n axi_ad9361/tx_clk_out_n +ad_connect tx_frame_out_p axi_ad9361/tx_frame_out_p +ad_connect tx_frame_out_n axi_ad9361/tx_frame_out_n +ad_connect tx_data_out_p axi_ad9361/tx_data_out_p +ad_connect tx_data_out_n axi_ad9361/tx_data_out_n +ad_connect enable axi_ad9361/enable +ad_connect txnrx axi_ad9361/txnrx +ad_connect up_enable axi_ad9361/up_enable +ad_connect up_txnrx axi_ad9361/up_txnrx +ad_connect axi_ad9361_clk util_ad9361_adc_fifo/din_clk +ad_connect axi_ad9361/rst util_ad9361_adc_fifo/din_rst +ad_connect axi_ad9361/adc_enable_i0 util_ad9361_adc_fifo/din_enable_0 +ad_connect axi_ad9361/adc_valid_i0 util_ad9361_adc_fifo/din_valid_0 +ad_connect axi_ad9361/adc_data_i0 util_ad9361_adc_fifo/din_data_0 +ad_connect axi_ad9361/adc_enable_q0 util_ad9361_adc_fifo/din_enable_1 +ad_connect axi_ad9361/adc_valid_q0 util_ad9361_adc_fifo/din_valid_1 +ad_connect axi_ad9361/adc_data_q0 util_ad9361_adc_fifo/din_data_1 +ad_connect axi_ad9361/adc_enable_i1 util_ad9361_adc_fifo/din_enable_2 +ad_connect axi_ad9361/adc_valid_i1 util_ad9361_adc_fifo/din_valid_2 +ad_connect axi_ad9361/adc_data_i1 util_ad9361_adc_fifo/din_data_2 +ad_connect axi_ad9361/adc_enable_q1 util_ad9361_adc_fifo/din_enable_3 +ad_connect axi_ad9361/adc_valid_q1 util_ad9361_adc_fifo/din_valid_3 +ad_connect axi_ad9361/adc_data_q1 util_ad9361_adc_fifo/din_data_3 +ad_connect util_ad9361_adc_fifo/dout_enable_0 util_ad9361_adc_pack/adc_enable_0 +ad_connect util_ad9361_adc_fifo/dout_valid_0 util_ad9361_adc_pack/adc_valid_0 +ad_connect util_ad9361_adc_fifo/dout_data_0 util_ad9361_adc_pack/adc_data_0 +ad_connect util_ad9361_adc_fifo/dout_enable_1 util_ad9361_adc_pack/adc_enable_1 +ad_connect util_ad9361_adc_fifo/dout_valid_1 util_ad9361_adc_pack/adc_valid_1 +ad_connect util_ad9361_adc_fifo/dout_data_1 util_ad9361_adc_pack/adc_data_1 +ad_connect util_ad9361_adc_fifo/dout_enable_2 util_ad9361_adc_pack/adc_enable_2 +ad_connect util_ad9361_adc_fifo/dout_valid_2 util_ad9361_adc_pack/adc_valid_2 +ad_connect util_ad9361_adc_fifo/dout_data_2 util_ad9361_adc_pack/adc_data_2 +ad_connect util_ad9361_adc_fifo/dout_enable_3 util_ad9361_adc_pack/adc_enable_3 +ad_connect util_ad9361_adc_fifo/dout_valid_3 util_ad9361_adc_pack/adc_valid_3 +ad_connect util_ad9361_adc_fifo/dout_data_3 util_ad9361_adc_pack/adc_data_3 +ad_connect util_ad9361_adc_pack/adc_valid axi_ad9361_adc_dma/fifo_wr_en +ad_connect util_ad9361_adc_pack/adc_sync axi_ad9361_adc_dma/fifo_wr_sync +ad_connect util_ad9361_adc_pack/adc_data axi_ad9361_adc_dma/fifo_wr_din +ad_connect axi_ad9361_adc_dma/fifo_wr_overflow util_ad9361_adc_fifo/dout_ovf +ad_connect util_ad9361_adc_fifo/din_ovf axi_ad9361/adc_dovf +ad_connect axi_ad9361_clk clkdiv/clk -ad_connect sys_cpu_clk util_ad9361_tdd_sync/clk -ad_connect sys_cpu_resetn util_ad9361_tdd_sync/rstn -ad_connect util_ad9361_tdd_sync/sync_out axi_ad9361/tdd_sync -ad_connect util_ad9361_tdd_sync/sync_en axi_ad9361/tdd_sync_en -ad_connect util_ad9361_tdd_sync/sync_type axi_ad9361/tdd_terminal_type -ad_connect tdd_sync_t axi_ad9361/tdd_terminal_type -ad_connect tdd_sync_o util_ad9361_tdd_sync/sync_out -ad_connect tdd_sync_i util_ad9361_tdd_sync/sync_in +ad_connect axi_ad9361/adc_r1_mode concat_logic/In0 +ad_connect axi_ad9361/dac_r1_mode concat_logic/In1 +ad_connect concat_logic/dout clkdiv_sel_logic/Op1 +ad_connect clkdiv/clk_sel clkdiv_sel_logic/Res + +ad_connect clkdiv/clk_out axi_ad9361_adc_dma/fifo_wr_clk +ad_connect clkdiv/clk_out util_ad9361_adc_fifo/dout_clk +ad_connect clkdiv/clk_out util_ad9361_adc_pack/adc_clk +ad_connect clkdiv_reset/ext_reset_in sys_rstgen/peripheral_aresetn +ad_connect clkdiv_reset/slowest_sync_clk clkdiv/clk_out +ad_connect util_ad9361_adc_pack/adc_rst clkdiv_reset/peripheral_reset +ad_connect util_ad9361_adc_fifo/dout_rstn clkdiv_reset/peripheral_aresetn +ad_connect util_ad9361_dac_upack/dac_valid axi_ad9361_dac_dma/fifo_rd_en +ad_connect util_ad9361_dac_upack/dac_data axi_ad9361_dac_dma/fifo_rd_dout +ad_connect clkdiv/clk_out axi_ad9361_dac_dma/fifo_rd_clk +ad_connect axi_ad9361/dac_dunf dac_fifo/dout_unf +ad_connect dac_fifo/din_clk clkdiv/clk_out +ad_connect dac_fifo/din_rstn clkdiv_reset/peripheral_aresetn +ad_connect axi_ad9361_clk dac_fifo/dout_clk +ad_connect dac_fifo/dout_rst axi_ad9361/rst +ad_connect util_ad9361_dac_upack/dac_clk clkdiv/clk_out +ad_connect dac_fifo/din_enable_0 util_ad9361_dac_upack/dac_enable_0 +ad_connect dac_fifo/din_valid_0 util_ad9361_dac_upack/dac_valid_0 +ad_connect dac_fifo/din_enable_1 util_ad9361_dac_upack/dac_enable_1 +ad_connect dac_fifo/din_valid_1 util_ad9361_dac_upack/dac_valid_1 +ad_connect dac_fifo/din_enable_2 util_ad9361_dac_upack/dac_enable_2 +ad_connect dac_fifo/din_valid_2 util_ad9361_dac_upack/dac_valid_2 +ad_connect dac_fifo/din_enable_3 util_ad9361_dac_upack/dac_enable_3 +ad_connect dac_fifo/din_valid_3 util_ad9361_dac_upack/dac_valid_3 +ad_connect util_ad9361_dac_upack/dac_data_0 dac_fifo/din_data_0 +ad_connect util_ad9361_dac_upack/dac_data_1 dac_fifo/din_data_1 +ad_connect util_ad9361_dac_upack/dac_data_2 dac_fifo/din_data_2 +ad_connect util_ad9361_dac_upack/dac_data_3 dac_fifo/din_data_3 +ad_connect axi_ad9361/dac_enable_i0 dac_fifo/dout_enable_0 +ad_connect axi_ad9361/dac_valid_i0 dac_fifo/dout_valid_0 +ad_connect axi_ad9361/dac_enable_q0 dac_fifo/dout_enable_1 +ad_connect axi_ad9361/dac_valid_q0 dac_fifo/dout_valid_1 +ad_connect axi_ad9361/dac_enable_i1 dac_fifo/dout_enable_2 +ad_connect axi_ad9361/dac_valid_i1 dac_fifo/dout_valid_2 +ad_connect axi_ad9361/dac_enable_q1 dac_fifo/dout_enable_3 +ad_connect axi_ad9361/dac_valid_q1 dac_fifo/dout_valid_3 +ad_connect dac_fifo/dout_data_0 axi_ad9361/dac_data_i0 +ad_connect dac_fifo/dout_data_1 axi_ad9361/dac_data_q0 +ad_connect dac_fifo/dout_data_2 axi_ad9361/dac_data_i1 +ad_connect dac_fifo/dout_data_3 axi_ad9361/dac_data_q1 +ad_connect sys_cpu_clk util_ad9361_tdd_sync/clk +ad_connect sys_cpu_resetn util_ad9361_tdd_sync/rstn +ad_connect util_ad9361_tdd_sync/sync_out axi_ad9361/tdd_sync +ad_connect util_ad9361_tdd_sync/sync_mode axi_ad9361/tdd_sync_cntr +ad_connect tdd_sync_t axi_ad9361/tdd_sync_cntr +ad_connect tdd_sync_o util_ad9361_tdd_sync/sync_out +ad_connect tdd_sync_i util_ad9361_tdd_sync/sync_in # interconnects @@ -166,35 +205,3 @@ ad_connect sys_cpu_resetn axi_ad9361_dac_dma/m_src_axi_aresetn ad_cpu_interrupt ps-13 mb-12 axi_ad9361_adc_dma/irq ad_cpu_interrupt ps-12 mb-13 axi_ad9361_dac_dma/irq -# ila (adc) - -set ila_adc [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.0 ila_adc] -set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_adc -set_property -dict [list CONFIG.C_TRIGIN_EN {false}] $ila_adc -set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila_adc -set_property -dict [list CONFIG.C_NUM_OF_PROBES {5}] $ila_adc -set_property -dict [list CONFIG.C_PROBE0_WIDTH {16}] $ila_adc -set_property -dict [list CONFIG.C_PROBE1_WIDTH {16}] $ila_adc -set_property -dict [list CONFIG.C_PROBE2_WIDTH {16}] $ila_adc -set_property -dict [list CONFIG.C_PROBE3_WIDTH {16}] $ila_adc -set_property -dict [list CONFIG.C_PROBE4_WIDTH {1}] $ila_adc - -ad_connect util_ad9361_adc_fifo/dout_data_0 ila_adc/probe0 -ad_connect util_ad9361_adc_fifo/dout_data_1 ila_adc/probe1 -ad_connect util_ad9361_adc_fifo/dout_data_2 ila_adc/probe2 -ad_connect util_ad9361_adc_fifo/dout_data_3 ila_adc/probe3 -ad_connect util_ad9361_adc_fifo/dout_valid_0 ila_adc/probe4 -ad_connect sys_cpu_clk ila_adc/clk - -# ila (tdd) - -set ila_tdd [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.0 ila_tdd] -set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_tdd -set_property -dict [list CONFIG.C_TRIGIN_EN {false}] $ila_tdd -set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila_tdd -set_property -dict [list CONFIG.C_NUM_OF_PROBES {1}] $ila_tdd -set_property -dict [list CONFIG.C_PROBE0_WIDTH {42}] $ila_tdd - -ad_connect axi_ad9361_clk ila_tdd/clk -ad_connect axi_ad9361/tdd_dbg ila_tdd/probe0 - diff --git a/projects/fmcomms2/common/fmcomms2_qsys.tcl b/projects/fmcomms2/common/fmcomms2_qsys.tcl new file mode 100644 index 000000000..77b96aa51 --- /dev/null +++ b/projects/fmcomms2/common/fmcomms2_qsys.tcl @@ -0,0 +1,136 @@ + +# fmcomms2 + +# ad9361 core + +add_instance axi_ad9361 axi_ad9361 1.0 +set_instance_parameter_value axi_ad9361 {ID} {0} +set_instance_parameter_value axi_ad9361 {DEVICE_TYPE} {0} + +add_connection sys_clk.clk_reset axi_ad9361.s_axi_reset +add_connection sys_clk.clk axi_ad9361.s_axi_clock +add_connection sys_cpu.data_master axi_ad9361.s_axi +add_connection axi_ad9361.if_l_clk axi_ad9361.if_clk + +# ad9361-unpack (dac) + +add_instance util_ad9361_dac_upack util_upack 1.0 +set_instance_parameter_value util_ad9361_dac_upack {CHANNEL_DATA_WIDTH} {16} +set_instance_parameter_value util_ad9361_dac_upack {NUM_OF_CHANNELS} {4} + +add_connection axi_ad9361.if_l_clk util_ad9361_dac_upack.if_dac_clk + +# ad9361-dma (dac) + +add_instance axi_ad9361_dac_dma axi_dmac 1.0 +set_instance_parameter_value axi_ad9361_dac_dma {DMA_DATA_WIDTH_DEST} {64} +set_instance_parameter_value axi_ad9361_dac_dma {DMA_2D_TRANSFER} {0} +set_instance_parameter_value axi_ad9361_dac_dma {DMA_TYPE_DEST} {2} +set_instance_parameter_value axi_ad9361_dac_dma {DMA_TYPE_SRC} {0} +set_instance_parameter_value axi_ad9361_dac_dma {CYCLIC} {1} +set_instance_parameter_value axi_ad9361_dac_dma {SYNC_TRANSFER_START} {0} +set_instance_parameter_value axi_ad9361_dac_dma {AXI_SLICE_SRC} {0} +set_instance_parameter_value axi_ad9361_dac_dma {AXI_SLICE_DEST} {1} + +add_connection sys_clk.clk_reset axi_ad9361_dac_dma.s_axi_reset +add_connection sys_clk.clk axi_ad9361_dac_dma.s_axi_clock +add_connection sys_ddr3_cntrl.emif_usr_reset_n axi_ad9361_dac_dma.m_src_axi_reset +add_connection sys_ddr3_cntrl.emif_usr_clk axi_ad9361_dac_dma.m_src_axi_clock +add_connection axi_ad9361_dac_dma.m_src_axi sys_ddr3_cntrl.ctrl_amm_0 +add_connection sys_cpu.irq axi_ad9361_dac_dma.interrupt_sender + +# dac path connections + +add_connection sys_cpu.data_master axi_ad9361_dac_dma.s_axi +add_connection util_ad9361_dac_upack.if_dac_valid axi_ad9361_dac_dma.if_fifo_rd_en +add_connection util_ad9361_dac_upack.if_dac_data axi_ad9361_dac_dma.if_fifo_rd_dout +add_connection axi_ad9361_dac_dma.if_fifo_rd_underflow axi_ad9361.if_dac_dunf +add_connection util_ad9361_dac_upack.dac_ch_0 axi_ad9361.dac_ch_0 +add_connection util_ad9361_dac_upack.dac_ch_1 axi_ad9361.dac_ch_1 +add_connection util_ad9361_dac_upack.dac_ch_2 axi_ad9361.dac_ch_2 +add_connection util_ad9361_dac_upack.dac_ch_3 axi_ad9361.dac_ch_3 +add_connection axi_ad9361.if_l_clk axi_ad9361_dac_dma.if_fifo_rd_clk + +# ad9361-adc-fifo + +add_instance util_ad9361_adc_fifo util_wfifo 1.0 +set_instance_parameter_value util_ad9361_adc_fifo {NUM_OF_CHANNELS} {4} +set_instance_parameter_value util_ad9361_adc_fifo {DIN_ADDRESS_WIDTH} {4} +set_instance_parameter_value util_ad9361_adc_fifo {DIN_DATA_WIDTH} {16} +set_instance_parameter_value util_ad9361_adc_fifo {DOUT_DATA_WIDTH} {16} + +add_connection axi_ad9361.if_l_clk util_ad9361_adc_fifo.if_din_clk +add_connection axi_ad9361.if_rst util_ad9361_adc_fifo.if_din_rst +add_connection sys_clk.clk_reset util_ad9361_adc_fifo.if_dout_rstn +add_connection sys_clk.clk util_ad9361_adc_fifo.if_dout_clk + +# ad9361-pack (adc) + +add_instance util_ad9361_adc_cpack util_cpack 1.0 +set_instance_parameter_value util_ad9361_adc_cpack {CHANNEL_DATA_WIDTH} {16} +set_instance_parameter_value util_ad9361_adc_cpack {NUM_OF_CHANNELS} {4} + +add_connection sys_clk.clk util_ad9361_adc_cpack.if_adc_clk +add_connection sys_clk.clk_reset util_ad9361_adc_cpack.if_adc_rst + +# ad9361-dma (adc) + +add_instance axi_ad9361_adc_dma axi_dmac 1.0 +set_instance_parameter_value axi_ad9361_adc_dma {DMA_DATA_WIDTH_SRC} {64} +set_instance_parameter_value axi_ad9361_adc_dma {DMA_2D_TRANSFER} {0} +set_instance_parameter_value axi_ad9361_adc_dma {AXI_SLICE_SRC} {0} +set_instance_parameter_value axi_ad9361_adc_dma {SYNC_TRANSFER_START} {1} +set_instance_parameter_value axi_ad9361_adc_dma {CYCLIC} {0} +set_instance_parameter_value axi_ad9361_adc_dma {DMA_TYPE_DEST} {0} +set_instance_parameter_value axi_ad9361_adc_dma {DMA_TYPE_SRC} {2} + +add_connection sys_clk.clk_reset axi_ad9361_adc_dma.s_axi_reset +add_connection sys_clk.clk axi_ad9361_adc_dma.s_axi_clock +add_connection sys_ddr3_cntrl.emif_usr_reset_n axi_ad9361_adc_dma.m_dest_axi_reset +add_connection sys_ddr3_cntrl.emif_usr_clk axi_ad9361_adc_dma.m_dest_axi_clock +add_connection sys_clk.clk axi_ad9361_adc_dma.if_fifo_wr_clk +add_connection sys_cpu.irq axi_ad9361_adc_dma.interrupt_sender +add_connection axi_ad9361_adc_dma.if_fifo_wr_overflow util_ad9361_adc_fifo.if_dout_ovf +add_connection axi_ad9361_adc_dma.m_dest_axi sys_ddr3_cntrl.ctrl_amm_0 + +# adc path connections + +add_connection axi_ad9361.adc_ch_0 util_ad9361_adc_fifo.din_0 +add_connection axi_ad9361.adc_ch_1 util_ad9361_adc_fifo.din_1 +add_connection axi_ad9361.adc_ch_2 util_ad9361_adc_fifo.din_2 +add_connection axi_ad9361.adc_ch_3 util_ad9361_adc_fifo.din_3 +add_connection util_ad9361_adc_fifo.if_din_ovf axi_ad9361.if_adc_dovf +add_connection util_ad9361_adc_fifo.dout_0 util_ad9361_adc_cpack.adc_ch_0 +add_connection util_ad9361_adc_fifo.dout_1 util_ad9361_adc_cpack.adc_ch_1 +add_connection util_ad9361_adc_fifo.dout_2 util_ad9361_adc_cpack.adc_ch_2 +add_connection util_ad9361_adc_fifo.dout_3 util_ad9361_adc_cpack.adc_ch_3 +add_connection util_ad9361_adc_cpack.if_adc_valid axi_ad9361_adc_dma.if_fifo_wr_en +add_connection util_ad9361_adc_cpack.if_adc_sync axi_ad9361_adc_dma.if_fifo_wr_sync +add_connection util_ad9361_adc_cpack.if_adc_data axi_ad9361_adc_dma.if_fifo_wr_din +add_connection sys_cpu.data_master axi_ad9361_adc_dma.s_axi +add_interface up_enable conduit end +add_interface up_txnrx conduit end +add_interface delay_clk conduit end + +# setting interface propriety + +set_interface_property axi_ad9361_device_if EXPORT_OF axi_ad9361.device_if +set_interface_property up_enable EXPORT_OF axi_ad9361.if_up_enable +set_interface_property up_txnrx EXPORT_OF axi_ad9361.if_up_txnrx +set_interface_property delay_clk EXPORT_OF axi_ad9361.if_delay_clk + +# addresses + +set_connection_parameter_value sys_cpu.data_master/axi_ad9361.s_axi baseAddress {0x10000000} +set_connection_parameter_value sys_cpu.data_master/axi_ad9361_dac_dma.s_axi baseAddress {0x10034000} +set_connection_parameter_value sys_cpu.data_master/axi_ad9361_adc_dma.s_axi baseAddress {0x10010000} + +set_connection_parameter_value axi_ad9361_adc_dma.m_dest_axi/sys_ddr3_cntrl.ctrl_amm_0 baseAddress {0x00000000} +set_connection_parameter_value axi_ad9361_dac_dma.m_src_axi/sys_ddr3_cntrl.ctrl_amm_0 baseAddress {0x00000000} + + +# interrupts + +set_connection_parameter_value sys_cpu.irq/axi_ad9361_adc_dma.interrupt_sender irqNumber {10} +set_connection_parameter_value sys_cpu.irq/axi_ad9361_dac_dma.interrupt_sender irqNumber {11} + diff --git a/projects/fmcomms2/common/prcfg_bd.tcl b/projects/fmcomms2/common/prcfg_bd.tcl index d7313adcc..daf296b9c 100644 --- a/projects/fmcomms2/common/prcfg_bd.tcl +++ b/projects/fmcomms2/common/prcfg_bd.tcl @@ -3,238 +3,119 @@ create_bd_port -dir O clk -create_bd_port -dir I dma_dac_i0_enable -create_bd_port -dir O dma_dac_i0_data -create_bd_port -dir I dma_dac_i0_valid -create_bd_port -dir I dma_dac_q0_enable -create_bd_port -dir O dma_dac_q0_data -create_bd_port -dir I dma_dac_q0_valid -create_bd_port -dir I dma_dac_i1_enable -create_bd_port -dir O dma_dac_i1_data -create_bd_port -dir I dma_dac_i1_valid -create_bd_port -dir I dma_dac_q1_enable -create_bd_port -dir O dma_dac_q1_data -create_bd_port -dir I dma_dac_q1_valid create_bd_port -dir O core_dac_i0_enable -create_bd_port -dir I core_dac_i0_data -create_bd_port -dir O core_dac_i0_valid create_bd_port -dir O core_dac_q0_enable -create_bd_port -dir I core_dac_q0_data -create_bd_port -dir O core_dac_q0_valid create_bd_port -dir O core_dac_i1_enable -create_bd_port -dir I core_dac_i1_data -create_bd_port -dir O core_dac_i1_valid create_bd_port -dir O core_dac_q1_enable -create_bd_port -dir I core_dac_q1_data +create_bd_port -dir O core_dac_i0_valid +create_bd_port -dir O core_dac_q0_valid +create_bd_port -dir O core_dac_i1_valid create_bd_port -dir O core_dac_q1_valid -create_bd_port -dir I dma_adc_i0_enable -create_bd_port -dir I dma_adc_i0_data -create_bd_port -dir I dma_adc_i0_valid -create_bd_port -dir I dma_adc_q0_enable -create_bd_port -dir I dma_adc_q0_data -create_bd_port -dir I dma_adc_q0_valid -create_bd_port -dir I dma_adc_i1_enable -create_bd_port -dir I dma_adc_i1_data -create_bd_port -dir I dma_adc_i1_valid -create_bd_port -dir I dma_adc_q1_enable -create_bd_port -dir I dma_adc_q1_data -create_bd_port -dir I dma_adc_q1_valid +create_bd_port -dir I -from 15 -to 0 core_dac_i0_data +create_bd_port -dir I -from 15 -to 0 core_dac_q0_data +create_bd_port -dir I -from 15 -to 0 core_dac_i1_data +create_bd_port -dir I -from 15 -to 0 core_dac_q1_data + +create_bd_port -dir I dma_dac_i0_enable +create_bd_port -dir I dma_dac_q0_enable +create_bd_port -dir I dma_dac_i1_enable +create_bd_port -dir I dma_dac_q1_enable +create_bd_port -dir I dma_dac_i0_valid +create_bd_port -dir I dma_dac_q0_valid +create_bd_port -dir I dma_dac_i1_valid +create_bd_port -dir I dma_dac_q1_valid +create_bd_port -dir O -from 15 -to 0 dma_dac_i0_data +create_bd_port -dir O -from 15 -to 0 dma_dac_q0_data +create_bd_port -dir O -from 15 -to 0 dma_dac_i1_data +create_bd_port -dir O -from 15 -to 0 dma_dac_q1_data + create_bd_port -dir O core_adc_i0_enable -create_bd_port -dir O core_adc_i0_data -create_bd_port -dir O core_adc_i0_valid create_bd_port -dir O core_adc_q0_enable -create_bd_port -dir O core_adc_q0_data -create_bd_port -dir O core_adc_q0_valid create_bd_port -dir O core_adc_i1_enable -create_bd_port -dir O core_adc_i1_data -create_bd_port -dir O core_adc_i1_valid create_bd_port -dir O core_adc_q1_enable -create_bd_port -dir O core_adc_q1_data +create_bd_port -dir O core_adc_i0_valid +create_bd_port -dir O core_adc_q0_valid +create_bd_port -dir O core_adc_i1_valid create_bd_port -dir O core_adc_q1_valid +create_bd_port -dir O -from 15 -to 0 core_adc_i0_data +create_bd_port -dir O -from 15 -to 0 core_adc_q0_data +create_bd_port -dir O -from 15 -to 0 core_adc_i1_data +create_bd_port -dir O -from 15 -to 0 core_adc_q1_data -create_bd_port -dir I -from 31 -to 0 up_dac_gpio_in -create_bd_port -dir I -from 31 -to 0 up_adc_gpio_in -create_bd_port -dir O -from 31 -to 0 up_dac_gpio_out -create_bd_port -dir O -from 31 -to 0 up_adc_gpio_out +create_bd_port -dir I dma_adc_i0_enable +create_bd_port -dir I dma_adc_q0_enable +create_bd_port -dir I dma_adc_i1_enable +create_bd_port -dir I dma_adc_q1_enable +create_bd_port -dir I dma_adc_i0_valid +create_bd_port -dir I dma_adc_q0_valid +create_bd_port -dir I dma_adc_i1_valid +create_bd_port -dir I dma_adc_q1_valid +create_bd_port -dir I -from 15 -to 0 dma_adc_i0_data +create_bd_port -dir I -from 15 -to 0 dma_adc_q0_data +create_bd_port -dir I -from 15 -to 0 dma_adc_i1_data +create_bd_port -dir I -from 15 -to 0 dma_adc_q1_data -# re-wiring +create_bd_port -dir I -from 31 -to 0 up_dac_gpio_in +create_bd_port -dir I -from 31 -to 0 up_adc_gpio_in +create_bd_port -dir O -from 31 -to 0 up_dac_gpio_out +create_bd_port -dir O -from 31 -to 0 up_adc_gpio_out -disconnect_bd_net [get_bd_nets -of_objects [get_bd_pins util_ad9361_dac_upack/dac_enable_0]] [get_bd_pins util_ad9361_dac_upack/dac_enable_0] -disconnect_bd_net [get_bd_nets -of_objects [get_bd_pins util_ad9361_dac_upack/dac_valid_0]] [get_bd_pins util_ad9361_dac_upack/dac_valid_0] -disconnect_bd_net [get_bd_nets -of_objects [get_bd_pins util_ad9361_dac_upack/dac_data_0]] [get_bd_pins util_ad9361_dac_upack/dac_data_0] -disconnect_bd_net [get_bd_nets -of_objects [get_bd_pins util_ad9361_dac_upack/dac_enable_1]] [get_bd_pins util_ad9361_dac_upack/dac_enable_1] -disconnect_bd_net [get_bd_nets -of_objects [get_bd_pins util_ad9361_dac_upack/dac_valid_1]] [get_bd_pins util_ad9361_dac_upack/dac_valid_1] -disconnect_bd_net [get_bd_nets -of_objects [get_bd_pins util_ad9361_dac_upack/dac_data_1]] [get_bd_pins util_ad9361_dac_upack/dac_data_1] -disconnect_bd_net [get_bd_nets -of_objects [get_bd_pins util_ad9361_dac_upack/dac_enable_2]] [get_bd_pins util_ad9361_dac_upack/dac_enable_2] -disconnect_bd_net [get_bd_nets -of_objects [get_bd_pins util_ad9361_dac_upack/dac_valid_2]] [get_bd_pins util_ad9361_dac_upack/dac_valid_2] -disconnect_bd_net [get_bd_nets -of_objects [get_bd_pins util_ad9361_dac_upack/dac_data_2]] [get_bd_pins util_ad9361_dac_upack/dac_data_2] -disconnect_bd_net [get_bd_nets -of_objects [get_bd_pins util_ad9361_dac_upack/dac_enable_3]] [get_bd_pins util_ad9361_dac_upack/dac_enable_3] -disconnect_bd_net [get_bd_nets -of_objects [get_bd_pins util_ad9361_dac_upack/dac_valid_3]] [get_bd_pins util_ad9361_dac_upack/dac_valid_3] -disconnect_bd_net [get_bd_nets -of_objects [get_bd_pins util_ad9361_dac_upack/dac_data_3]] [get_bd_pins util_ad9361_dac_upack/dac_data_3] +# re-wiring, split between ad9361 core & upack/cpack modules -disconnect_bd_net [get_bd_nets -of_objects [get_bd_pins util_ad9361_adc_pack/adc_enable_0]] [get_bd_pins util_ad9361_adc_pack/adc_enable_0] -disconnect_bd_net [get_bd_nets -of_objects [get_bd_pins util_ad9361_adc_pack/adc_valid_0]] [get_bd_pins util_ad9361_adc_pack/adc_valid_0] -disconnect_bd_net [get_bd_nets -of_objects [get_bd_pins util_ad9361_adc_pack/adc_data_0]] [get_bd_pins util_ad9361_adc_pack/adc_data_0] -disconnect_bd_net [get_bd_nets -of_objects [get_bd_pins util_ad9361_adc_pack/adc_enable_1]] [get_bd_pins util_ad9361_adc_pack/adc_enable_1] -disconnect_bd_net [get_bd_nets -of_objects [get_bd_pins util_ad9361_adc_pack/adc_valid_1]] [get_bd_pins util_ad9361_adc_pack/adc_valid_1] -disconnect_bd_net [get_bd_nets -of_objects [get_bd_pins util_ad9361_adc_pack/adc_data_1]] [get_bd_pins util_ad9361_adc_pack/adc_data_1] -disconnect_bd_net [get_bd_nets -of_objects [get_bd_pins util_ad9361_adc_pack/adc_enable_2]] [get_bd_pins util_ad9361_adc_pack/adc_enable_2] -disconnect_bd_net [get_bd_nets -of_objects [get_bd_pins util_ad9361_adc_pack/adc_valid_2]] [get_bd_pins util_ad9361_adc_pack/adc_valid_2] -disconnect_bd_net [get_bd_nets -of_objects [get_bd_pins util_ad9361_adc_pack/adc_data_2]] [get_bd_pins util_ad9361_adc_pack/adc_data_2] -disconnect_bd_net [get_bd_nets -of_objects [get_bd_pins util_ad9361_adc_pack/adc_enable_3]] [get_bd_pins util_ad9361_adc_pack/adc_enable_3] -disconnect_bd_net [get_bd_nets -of_objects [get_bd_pins util_ad9361_adc_pack/adc_valid_3]] [get_bd_pins util_ad9361_adc_pack/adc_valid_3] -disconnect_bd_net [get_bd_nets -of_objects [get_bd_pins util_ad9361_adc_pack/adc_data_3]] [get_bd_pins util_ad9361_adc_pack/adc_data_3] +ad_connect axi_ad9361_clk clk -ad_connect clk axi_ad9361/clk +ad_reconct util_ad9361_dac_upack/dac_enable_0 dma_dac_i0_enable +ad_reconct util_ad9361_dac_upack/dac_enable_1 dma_dac_q0_enable +ad_reconct util_ad9361_dac_upack/dac_enable_2 dma_dac_i1_enable +ad_reconct util_ad9361_dac_upack/dac_enable_3 dma_dac_q1_enable +ad_reconct util_ad9361_dac_upack/dac_valid_0 dma_dac_i0_valid +ad_reconct util_ad9361_dac_upack/dac_valid_1 dma_dac_q0_valid +ad_reconct util_ad9361_dac_upack/dac_valid_2 dma_dac_i1_valid +ad_reconct util_ad9361_dac_upack/dac_valid_3 dma_dac_q1_valid +ad_reconct util_ad9361_dac_upack/dac_data_0 dma_dac_i0_data +ad_reconct util_ad9361_dac_upack/dac_data_1 dma_dac_q0_data +ad_reconct util_ad9361_dac_upack/dac_data_2 dma_dac_i1_data +ad_reconct util_ad9361_dac_upack/dac_data_3 dma_dac_q1_data +ad_reconct axi_ad9361/dac_enable_i0 core_dac_i0_enable +ad_reconct axi_ad9361/dac_enable_q0 core_dac_q0_enable +ad_reconct axi_ad9361/dac_enable_i1 core_dac_i1_enable +ad_reconct axi_ad9361/dac_enable_q1 core_dac_q1_enable +ad_reconct axi_ad9361/dac_valid_i0 core_dac_i0_valid +ad_reconct axi_ad9361/dac_valid_q0 core_dac_q0_valid +ad_reconct axi_ad9361/dac_valid_i1 core_dac_i1_valid +ad_reconct axi_ad9361/dac_valid_q1 core_dac_q1_valid +ad_reconct axi_ad9361/dac_data_i0 core_dac_i0_data +ad_reconct axi_ad9361/dac_data_q0 core_dac_q0_data +ad_reconct axi_ad9361/dac_data_i1 core_dac_i1_data +ad_reconct axi_ad9361/dac_data_q1 core_dac_q1_data -# tx data path -ad_connect dma_dac_i0_enable util_ad9361_dac_upack/dac_enable_0 -ad_connect dma_dac_i0_data util_ad9361_dac_upack/dac_data_0 -ad_connect dma_dac_i0_valid util_ad9361_dac_upack/dac_valid_0 -ad_connect dma_dac_q0_enable util_ad9361_dac_upack/dac_enable_1 -ad_connect dma_dac_q0_data util_ad9361_dac_upack/dac_data_1 -ad_connect dma_dac_q0_valid util_ad9361_dac_upack/dac_valid_1 -ad_connect dma_dac_i1_enable util_ad9361_dac_upack/dac_enable_2 -ad_connect dma_dac_i1_data util_ad9361_dac_upack/dac_data_2 -ad_connect dma_dac_i1_valid util_ad9361_dac_upack/dac_valid_2 -ad_connect dma_dac_q1_enable util_ad9361_dac_upack/dac_enable_3 -ad_connect dma_dac_q1_data util_ad9361_dac_upack/dac_data_3 -ad_connect dma_dac_q1_valid util_ad9361_dac_upack/dac_valid_3 +ad_reconct util_ad9361_adc_fifo/din_enable_0 dma_adc_i0_enable +ad_reconct util_ad9361_adc_fifo/din_enable_1 dma_adc_q0_enable +ad_reconct util_ad9361_adc_fifo/din_enable_2 dma_adc_i1_enable +ad_reconct util_ad9361_adc_fifo/din_enable_3 dma_adc_q1_enable +ad_reconct util_ad9361_adc_fifo/din_valid_0 dma_adc_i0_valid +ad_reconct util_ad9361_adc_fifo/din_valid_1 dma_adc_q0_valid +ad_reconct util_ad9361_adc_fifo/din_valid_2 dma_adc_i1_valid +ad_reconct util_ad9361_adc_fifo/din_valid_3 dma_adc_q1_valid +ad_reconct util_ad9361_adc_fifo/din_data_0 dma_adc_i0_data +ad_reconct util_ad9361_adc_fifo/din_data_1 dma_adc_q0_data +ad_reconct util_ad9361_adc_fifo/din_data_2 dma_adc_i1_data +ad_reconct util_ad9361_adc_fifo/din_data_3 dma_adc_q1_data +ad_reconct axi_ad9361/adc_enable_i0 core_adc_i0_enable +ad_reconct axi_ad9361/adc_enable_q0 core_adc_q0_enable +ad_reconct axi_ad9361/adc_enable_i1 core_adc_i1_enable +ad_reconct axi_ad9361/adc_enable_q1 core_adc_q1_enable +ad_reconct axi_ad9361/adc_valid_i0 core_adc_i0_valid +ad_reconct axi_ad9361/adc_valid_q0 core_adc_q0_valid +ad_reconct axi_ad9361/adc_valid_i1 core_adc_i1_valid +ad_reconct axi_ad9361/adc_valid_q1 core_adc_q1_valid +ad_reconct axi_ad9361/adc_data_i0 core_adc_i0_data +ad_reconct axi_ad9361/adc_data_q0 core_adc_q0_data +ad_reconct axi_ad9361/adc_data_i1 core_adc_i1_data +ad_reconct axi_ad9361/adc_data_q1 core_adc_q1_data -ad_connect core_dac_i0_enable axi_ad9361/dac_enable_i0 -ad_connect core_dac_i0_data axi_ad9361/dac_data_i0 -ad_connect core_dac_i0_valid axi_ad9361/dac_valid_i0 -ad_connect core_dac_q0_enable axi_ad9361/dac_enable_q0 -ad_connect core_dac_q0_data axi_ad9361/dac_data_q0 -ad_connect core_dac_q0_valid axi_ad9361/dac_valid_q0 -ad_connect core_dac_i1_enable axi_ad9361/dac_enable_i1 -ad_connect core_dac_i1_data axi_ad9361/dac_data_i1 -ad_connect core_dac_i1_valid axi_ad9361/dac_valid_i1 -ad_connect core_dac_q1_enable axi_ad9361/dac_enable_q1 -ad_connect core_dac_q1_data axi_ad9361/dac_data_q1 -ad_connect core_dac_q1_valid axi_ad9361/dac_valid_q1 - -# rx data path -ad_connect dma_adc_i0_enable util_ad9361_adc_pack/adc_enable_0 -ad_connect dma_adc_i0_data util_ad9361_adc_pack/adc_data_0 -ad_connect dma_adc_i0_valid util_ad9361_adc_pack/adc_valid_0 -ad_connect dma_adc_q0_enable util_ad9361_adc_pack/adc_enable_1 -ad_connect dma_adc_q0_data util_ad9361_adc_pack/adc_data_1 -ad_connect dma_adc_q0_valid util_ad9361_adc_pack/adc_valid_1 -ad_connect dma_adc_i1_enable util_ad9361_adc_pack/adc_enable_2 -ad_connect dma_adc_i1_data util_ad9361_adc_pack/adc_data_2 -ad_connect dma_adc_i1_valid util_ad9361_adc_pack/adc_valid_2 -ad_connect dma_adc_q1_enable util_ad9361_adc_pack/adc_enable_3 -ad_connect dma_adc_q1_data util_ad9361_adc_pack/adc_data_3 -ad_connect dma_adc_q1_valid util_ad9361_adc_pack/adc_valid_3 - -ad_connect core_adc_i0_enable util_ad9361_adc_fifo/dout_enable_0 -ad_connect core_adc_i0_data util_ad9361_adc_fifo/dout_data_0 -ad_connect core_adc_i0_valid util_ad9361_adc_fifo/dout_valid_0 -ad_connect core_adc_q0_enable util_ad9361_adc_fifo/dout_enable_1 -ad_connect core_adc_q0_data util_ad9361_adc_fifo/dout_data_1 -ad_connect core_adc_q0_valid util_ad9361_adc_fifo/dout_valid_1 -ad_connect core_adc_i1_enable util_ad9361_adc_fifo/dout_enable_2 -ad_connect core_adc_i1_data util_ad9361_adc_fifo/dout_data_2 -ad_connect core_adc_i1_valid util_ad9361_adc_fifo/dout_valid_2 -ad_connect core_adc_q1_enable util_ad9361_adc_fifo/dout_enable_3 -ad_connect core_adc_q1_data util_ad9361_adc_fifo/dout_data_3 -ad_connect core_adc_q1_valid util_ad9361_adc_fifo/dout_valid_3 - -ad_connect up_dac_gpio_in axi_ad9361/up_dac_gpio_in -ad_connect up_adc_gpio_in axi_ad9361/up_adc_gpio_in -ad_connect up_dac_gpio_out axi_ad9361/up_dac_gpio_out -ad_connect up_adc_gpio_out axi_ad9361/up_adc_gpio_out - -# rx side monitoring - -set ila_rx_0 [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.0 ila_rx_0] -set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_rx_0 -set_property -dict [list CONFIG.C_NUM_OF_PROBES {2}] $ila_rx_0 -set_property -dict [list CONFIG.C_PROBE0_WIDTH {1}] $ila_rx_0 -set_property -dict [list CONFIG.C_PROBE1_WIDTH {16}] $ila_rx_0 -set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila_rx_0 - -ad_connect sys_cpu_clk ila_rx_0/clk -ad_connect util_ad9361_adc_pack/adc_valid_0 ila_rx_0/probe0 -ad_connect util_ad9361_adc_pack/adc_data_0 ila_rx_0/probe1 - -set ila_rx_1 [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.0 ila_rx_1] -set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_rx_1 -set_property -dict [list CONFIG.C_NUM_OF_PROBES {2}] $ila_rx_1 -set_property -dict [list CONFIG.C_PROBE0_WIDTH {1}] $ila_rx_1 -set_property -dict [list CONFIG.C_PROBE1_WIDTH {16}] $ila_rx_1 -set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila_rx_1 - -ad_connect sys_cpu_clk ila_rx_1/clk -ad_connect util_ad9361_adc_pack/adc_valid_0 ila_rx_1/probe0 -ad_connect util_ad9361_adc_pack/adc_data_0 ila_rx_1/probe1 - -set ila_rx_2 [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:5.1 ila_rx_2] -set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_rx_2 -set_property -dict [list CONFIG.C_NUM_OF_PROBES {2}] $ila_rx_2 -set_property -dict [list CONFIG.C_PROBE0_WIDTH {1}] $ila_rx_2 -set_property -dict [list CONFIG.C_PROBE1_WIDTH {16}] $ila_rx_2 -set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila_rx_2 - -ad_connect sys_cpu_clk ila_rx_2/clk -ad_connect util_ad9361_adc_pack/adc_valid_0 ila_rx_2/probe0 -ad_connect util_ad9361_adc_pack/adc_data_0 ila_rx_2/probe1 - -set ila_rx_3 [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:5.1 ila_rx_3] -set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_rx_3 -set_property -dict [list CONFIG.C_NUM_OF_PROBES {2}] $ila_rx_3 -set_property -dict [list CONFIG.C_PROBE0_WIDTH {1}] $ila_rx_3 -set_property -dict [list CONFIG.C_PROBE1_WIDTH {16}] $ila_rx_3 -set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila_rx_3 - -ad_connect sys_cpu_clk ila_rx_3/clk -ad_connect util_ad9361_adc_pack/adc_valid_0 ila_rx_3/probe0 -ad_connect util_ad9361_adc_pack/adc_data_0 ila_rx_3/probe1 - -# rx side monitoring - -set ila_tx_0 [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:5.1 ila_tx_0] -set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_tx_0 -set_property -dict [list CONFIG.C_NUM_OF_PROBES {2}] $ila_tx_0 -set_property -dict [list CONFIG.C_PROBE0_WIDTH {1}] $ila_tx_0 -set_property -dict [list CONFIG.C_PROBE1_WIDTH {16}] $ila_tx_0 -set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila_tx_0 - -ad_connect axi_ad9361/l_clk ila_tx_0/clk -ad_connect util_ad9361_adc_fifo/dout_valid_0 ila_tx_0/probe0 -ad_connect util_ad9361_adc_fifo/dout_data_0 ila_tx_0/probe1 - -set ila_tx_1 [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.0 ila_tx_1] -set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_tx_1 -set_property -dict [list CONFIG.C_NUM_OF_PROBES {2}] $ila_tx_1 -set_property -dict [list CONFIG.C_PROBE0_WIDTH {1}] $ila_tx_1 -set_property -dict [list CONFIG.C_PROBE1_WIDTH {16}] $ila_tx_1 -set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila_tx_1 - -ad_connect axi_ad9361/l_clk ila_tx_1/clk -ad_connect util_ad9361_adc_fifo/dout_valid_1 ila_tx_1/probe0 -ad_connect util_ad9361_adc_fifo/dout_data_1 ila_tx_1/probe1 - -set ila_tx_2 [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.0 ila_tx_2] -set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_tx_2 -set_property -dict [list CONFIG.C_NUM_OF_PROBES {2}] $ila_tx_2 -set_property -dict [list CONFIG.C_PROBE0_WIDTH {1}] $ila_tx_2 -set_property -dict [list CONFIG.C_PROBE1_WIDTH {16}] $ila_tx_2 -set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila_tx_2 - -ad_connect axi_ad9361/l_clk ila_tx_2/clk -ad_connect util_ad9361_adc_fifo/dout_valid_2 ila_tx_2/probe0 -ad_connect util_ad9361_adc_fifo/dout_data_2 ila_tx_2/probe1 - -set ila_tx_3 [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.0 ila_tx_3] -set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_tx_3 -set_property -dict [list CONFIG.C_NUM_OF_PROBES {2}] $ila_tx_3 -set_property -dict [list CONFIG.C_PROBE0_WIDTH {1}] $ila_tx_3 -set_property -dict [list CONFIG.C_PROBE1_WIDTH {16}] $ila_tx_3 -set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila_tx_3 - -ad_connect axi_ad9361/l_clk ila_tx_3/clk -ad_connect util_ad9361_adc_fifo/dout_valid_3 ila_tx_3/probe0 -ad_connect util_ad9361_adc_fifo/dout_data_3 ila_tx_3/probe1 +ad_reconct axi_ad9361/up_dac_gpio_in up_dac_gpio_in +ad_reconct axi_ad9361/up_adc_gpio_in up_adc_gpio_in +ad_reconct axi_ad9361/up_dac_gpio_out up_dac_gpio_out +ad_reconct axi_ad9361/up_adc_gpio_out up_adc_gpio_out diff --git a/projects/fmcomms2/kc705/Makefile b/projects/fmcomms2/kc705/Makefile index ab24ca35e..4e9485043 100644 --- a/projects/fmcomms2/kc705/Makefile +++ b/projects/fmcomms2/kc705/Makefile @@ -17,10 +17,12 @@ M_DEPS += ../../common/xilinx/sys_wfifo.tcl M_DEPS += ../../common/kc705/kc705_system_mig.prj M_DEPS += ../../common/kc705/kc705_system_constr.xdc M_DEPS += ../../common/kc705/kc705_system_bd.tcl -M_DEPS += ../../../library/common/ad_iobuf.v +M_DEPS += ../../../library/xilinx/common/ad_iobuf.v M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr +M_DEPS += ../../../library/util_clkdiv/util_clkdiv.xpr M_DEPS += ../../../library/util_cpack/util_cpack.xpr +M_DEPS += ../../../library/util_rfifo/util_rfifo.xpr M_DEPS += ../../../library/util_tdd_sync/util_tdd_sync.xpr M_DEPS += ../../../library/util_upack/util_upack.xpr M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr @@ -39,6 +41,7 @@ M_FLIST += *.sdk M_FLIST += *.hw M_FLIST += *.sim M_FLIST += .Xil +M_FLIST += *.ip_user_files @@ -53,21 +56,25 @@ clean: clean-all:clean make -C ../../../library/axi_ad9361 clean make -C ../../../library/axi_dmac clean + make -C ../../../library/util_clkdiv clean make -C ../../../library/util_cpack clean + make -C ../../../library/util_rfifo clean make -C ../../../library/util_tdd_sync clean make -C ../../../library/util_upack clean make -C ../../../library/util_wfifo clean fmcomms2_kc705.sdk/system_top.hdf: $(M_DEPS) - rm -rf $(M_FLIST) + -rm -rf $(M_FLIST) $(M_VIVADO) system_project.tcl >> fmcomms2_kc705_vivado.log 2>&1 lib: make -C ../../../library/axi_ad9361 make -C ../../../library/axi_dmac + make -C ../../../library/util_clkdiv make -C ../../../library/util_cpack + make -C ../../../library/util_rfifo make -C ../../../library/util_tdd_sync make -C ../../../library/util_upack make -C ../../../library/util_wfifo diff --git a/projects/fmcomms2/kc705/system_project.tcl b/projects/fmcomms2/kc705/system_project.tcl index aef268c03..aaf3ee949 100644 --- a/projects/fmcomms2/kc705/system_project.tcl +++ b/projects/fmcomms2/kc705/system_project.tcl @@ -7,7 +7,7 @@ adi_project_create fmcomms2_kc705 adi_project_files fmcomms2_kc705 [list \ "system_top.v" \ "system_constr.xdc"\ - "$ad_hdl_dir/library/common/ad_iobuf.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \ "$ad_hdl_dir/projects/common/kc705/kc705_system_constr.xdc" ] adi_project_run fmcomms2_kc705 diff --git a/projects/fmcomms2/mitx045/Makefile b/projects/fmcomms2/mitx045/Makefile index ca53855ce..c946394d1 100644 --- a/projects/fmcomms2/mitx045/Makefile +++ b/projects/fmcomms2/mitx045/Makefile @@ -17,14 +17,16 @@ M_DEPS += ../../common/xilinx/sys_wfifo.tcl M_DEPS += ../../common/mitx045/mitx045_system_ps7.tcl M_DEPS += ../../common/mitx045/mitx045_system_constr.xdc M_DEPS += ../../common/mitx045/mitx045_system_bd.tcl -M_DEPS += ../../../library/common/ad_iobuf.v +M_DEPS += ../../../library/xilinx/common/ad_iobuf.v M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr M_DEPS += ../../../library/axi_i2s_adi/axi_i2s_adi.xpr M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr +M_DEPS += ../../../library/util_clkdiv/util_clkdiv.xpr M_DEPS += ../../../library/util_cpack/util_cpack.xpr +M_DEPS += ../../../library/util_rfifo/util_rfifo.xpr M_DEPS += ../../../library/util_tdd_sync/util_tdd_sync.xpr M_DEPS += ../../../library/util_upack/util_upack.xpr M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr @@ -43,6 +45,7 @@ M_FLIST += *.sdk M_FLIST += *.hw M_FLIST += *.sim M_FLIST += .Xil +M_FLIST += *.ip_user_files @@ -61,14 +64,16 @@ clean-all:clean make -C ../../../library/axi_hdmi_tx clean make -C ../../../library/axi_i2s_adi clean make -C ../../../library/axi_spdif_tx clean + make -C ../../../library/util_clkdiv clean make -C ../../../library/util_cpack clean + make -C ../../../library/util_rfifo clean make -C ../../../library/util_tdd_sync clean make -C ../../../library/util_upack clean make -C ../../../library/util_wfifo clean fmcomms2_mitx045.sdk/system_top.hdf: $(M_DEPS) - rm -rf $(M_FLIST) + -rm -rf $(M_FLIST) $(M_VIVADO) system_project.tcl >> fmcomms2_mitx045_vivado.log 2>&1 @@ -79,7 +84,9 @@ lib: make -C ../../../library/axi_hdmi_tx make -C ../../../library/axi_i2s_adi make -C ../../../library/axi_spdif_tx + make -C ../../../library/util_clkdiv make -C ../../../library/util_cpack + make -C ../../../library/util_rfifo make -C ../../../library/util_tdd_sync make -C ../../../library/util_upack make -C ../../../library/util_wfifo diff --git a/projects/fmcomms2/mitx045/system_project.tcl b/projects/fmcomms2/mitx045/system_project.tcl index 405d74069..4a6eeeb60 100755 --- a/projects/fmcomms2/mitx045/system_project.tcl +++ b/projects/fmcomms2/mitx045/system_project.tcl @@ -7,7 +7,7 @@ adi_project_create fmcomms2_mitx045 adi_project_files fmcomms2_mitx045 [list \ "system_top.v" \ "system_constr.xdc"\ - "$ad_hdl_dir/library/common/ad_iobuf.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \ "$ad_hdl_dir/projects/common/mitx045/mitx045_system_constr.xdc" ] adi_project_run fmcomms2_mitx045 diff --git a/projects/fmcomms2/vc707/Makefile b/projects/fmcomms2/vc707/Makefile index 46327e71d..85de2aff5 100644 --- a/projects/fmcomms2/vc707/Makefile +++ b/projects/fmcomms2/vc707/Makefile @@ -16,10 +16,12 @@ M_DEPS += ../../scripts/adi_board.tcl M_DEPS += ../../common/vc707/vc707_system_mig.prj M_DEPS += ../../common/vc707/vc707_system_constr.xdc M_DEPS += ../../common/vc707/vc707_system_bd.tcl -M_DEPS += ../../../library/common/ad_iobuf.v +M_DEPS += ../../../library/xilinx/common/ad_iobuf.v M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr +M_DEPS += ../../../library/util_clkdiv/util_clkdiv.xpr M_DEPS += ../../../library/util_cpack/util_cpack.xpr +M_DEPS += ../../../library/util_rfifo/util_rfifo.xpr M_DEPS += ../../../library/util_tdd_sync/util_tdd_sync.xpr M_DEPS += ../../../library/util_upack/util_upack.xpr M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr @@ -38,6 +40,7 @@ M_FLIST += *.sdk M_FLIST += *.hw M_FLIST += *.sim M_FLIST += .Xil +M_FLIST += *.ip_user_files @@ -52,21 +55,25 @@ clean: clean-all:clean make -C ../../../library/axi_ad9361 clean make -C ../../../library/axi_dmac clean + make -C ../../../library/util_clkdiv clean make -C ../../../library/util_cpack clean + make -C ../../../library/util_rfifo clean make -C ../../../library/util_tdd_sync clean make -C ../../../library/util_upack clean make -C ../../../library/util_wfifo clean fmcomms2_vc707.sdk/system_top.hdf: $(M_DEPS) - rm -rf $(M_FLIST) + -rm -rf $(M_FLIST) $(M_VIVADO) system_project.tcl >> fmcomms2_vc707_vivado.log 2>&1 lib: make -C ../../../library/axi_ad9361 make -C ../../../library/axi_dmac + make -C ../../../library/util_clkdiv make -C ../../../library/util_cpack + make -C ../../../library/util_rfifo make -C ../../../library/util_tdd_sync make -C ../../../library/util_upack make -C ../../../library/util_wfifo diff --git a/projects/fmcomms2/vc707/system_project.tcl b/projects/fmcomms2/vc707/system_project.tcl index 1176ef25b..40d68552c 100644 --- a/projects/fmcomms2/vc707/system_project.tcl +++ b/projects/fmcomms2/vc707/system_project.tcl @@ -9,7 +9,7 @@ adi_project_create fmcomms2_vc707 adi_project_files fmcomms2_vc707 [list \ "system_top.v" \ "system_constr.xdc"\ - "$ad_hdl_dir/library/common/ad_iobuf.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \ "$ad_hdl_dir/projects/common/vc707/vc707_system_constr.xdc" ] set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/vc707/vc707_system_constr.xdc] diff --git a/projects/fmcomms2/zc702/Makefile b/projects/fmcomms2/zc702/Makefile index 439cfe22c..4bc0b073d 100644 --- a/projects/fmcomms2/zc702/Makefile +++ b/projects/fmcomms2/zc702/Makefile @@ -16,13 +16,15 @@ M_DEPS += ../../scripts/adi_board.tcl M_DEPS += ../../common/zc702/zc702_system_constr.xdc M_DEPS += ../../common/zc702/zc702_system_bd.tcl M_DEPS += ../../common/xilinx/sys_wfifo.tcl -M_DEPS += ../../../library/common/ad_iobuf.v +M_DEPS += ../../../library/xilinx/common/ad_iobuf.v M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr +M_DEPS += ../../../library/util_clkdiv/util_clkdiv.xpr M_DEPS += ../../../library/util_cpack/util_cpack.xpr +M_DEPS += ../../../library/util_rfifo/util_rfifo.xpr M_DEPS += ../../../library/util_tdd_sync/util_tdd_sync.xpr M_DEPS += ../../../library/util_upack/util_upack.xpr M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr @@ -41,6 +43,7 @@ M_FLIST += *.sdk M_FLIST += *.hw M_FLIST += *.sim M_FLIST += .Xil +M_FLIST += *.ip_user_files @@ -58,14 +61,16 @@ clean-all:clean make -C ../../../library/axi_dmac clean make -C ../../../library/axi_hdmi_tx clean make -C ../../../library/axi_spdif_tx clean + make -C ../../../library/util_clkdiv clean make -C ../../../library/util_cpack clean + make -C ../../../library/util_rfifo clean make -C ../../../library/util_tdd_sync clean make -C ../../../library/util_upack clean make -C ../../../library/util_wfifo clean fmcomms2_zc702.sdk/system_top.hdf: $(M_DEPS) - rm -rf $(M_FLIST) + -rm -rf $(M_FLIST) $(M_VIVADO) system_project.tcl >> fmcomms2_zc702_vivado.log 2>&1 @@ -75,7 +80,9 @@ lib: make -C ../../../library/axi_dmac make -C ../../../library/axi_hdmi_tx make -C ../../../library/axi_spdif_tx + make -C ../../../library/util_clkdiv make -C ../../../library/util_cpack + make -C ../../../library/util_rfifo make -C ../../../library/util_tdd_sync make -C ../../../library/util_upack make -C ../../../library/util_wfifo diff --git a/projects/fmcomms2/zc702/system_constr.xdc b/projects/fmcomms2/zc702/system_constr.xdc index 2e9fc432f..f48e3319e 100644 --- a/projects/fmcomms2/zc702/system_constr.xdc +++ b/projects/fmcomms2/zc702/system_constr.xdc @@ -62,6 +62,13 @@ set_property -dict {PACKAGE_PIN C18 IOSTANDARD LVCMOS25} [get_ports spi_miso] create_clock -name rx_clk -period 4 [get_ports rx_clk_in_p] +# disconnect gpio_bd 8-11 + +set_property package_pin "" [get_ports [list gpio_bd[8]]] +set_property package_pin "" [get_ports [list gpio_bd[9]]] +set_property package_pin "" [get_ports [list gpio_bd[10]]] +set_property package_pin "" [get_ports [list gpio_bd[11]]] + # spi pmod J63 set_property -dict {PACKAGE_PIN E15 IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports spi_udc_csn_tx] ; ## PMOD1_0_LS diff --git a/projects/fmcomms2/zc702/system_project.tcl b/projects/fmcomms2/zc702/system_project.tcl index 485686110..e3a8db3af 100644 --- a/projects/fmcomms2/zc702/system_project.tcl +++ b/projects/fmcomms2/zc702/system_project.tcl @@ -6,9 +6,9 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl adi_project_create fmcomms2_zc702 adi_project_files fmcomms2_zc702 [list \ "system_top.v" \ - "system_constr.xdc"\ - "$ad_hdl_dir/library/common/ad_iobuf.v" \ - "$ad_hdl_dir/projects/common/zc702/zc702_system_constr.xdc" ] + "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \ + "$ad_hdl_dir/projects/common/zc702/zc702_system_constr.xdc" \ + "system_constr.xdc" ] adi_project_run fmcomms2_zc702 diff --git a/projects/fmcomms2/zc706/Makefile b/projects/fmcomms2/zc706/Makefile index d3c52de44..0c6fab01c 100644 --- a/projects/fmcomms2/zc706/Makefile +++ b/projects/fmcomms2/zc706/Makefile @@ -15,13 +15,15 @@ M_DEPS += ../../scripts/adi_env.tcl M_DEPS += ../../scripts/adi_board.tcl M_DEPS += ../../common/zc706/zc706_system_constr.xdc M_DEPS += ../../common/zc706/zc706_system_bd.tcl -M_DEPS += ../../../library/common/ad_iobuf.v +M_DEPS += ../../../library/xilinx/common/ad_iobuf.v M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr +M_DEPS += ../../../library/util_clkdiv/util_clkdiv.xpr M_DEPS += ../../../library/util_cpack/util_cpack.xpr +M_DEPS += ../../../library/util_rfifo/util_rfifo.xpr M_DEPS += ../../../library/util_tdd_sync/util_tdd_sync.xpr M_DEPS += ../../../library/util_upack/util_upack.xpr M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr @@ -40,6 +42,7 @@ M_FLIST += *.sdk M_FLIST += *.hw M_FLIST += *.sim M_FLIST += .Xil +M_FLIST += *.ip_user_files @@ -57,14 +60,16 @@ clean-all:clean make -C ../../../library/axi_dmac clean make -C ../../../library/axi_hdmi_tx clean make -C ../../../library/axi_spdif_tx clean + make -C ../../../library/util_clkdiv clean make -C ../../../library/util_cpack clean + make -C ../../../library/util_rfifo clean make -C ../../../library/util_tdd_sync clean make -C ../../../library/util_upack clean make -C ../../../library/util_wfifo clean fmcomms2_zc706.sdk/system_top.hdf: $(M_DEPS) - rm -rf $(M_FLIST) + -rm -rf $(M_FLIST) $(M_VIVADO) system_project.tcl >> fmcomms2_zc706_vivado.log 2>&1 @@ -74,7 +79,9 @@ lib: make -C ../../../library/axi_dmac make -C ../../../library/axi_hdmi_tx make -C ../../../library/axi_spdif_tx + make -C ../../../library/util_clkdiv make -C ../../../library/util_cpack + make -C ../../../library/util_rfifo make -C ../../../library/util_tdd_sync make -C ../../../library/util_upack make -C ../../../library/util_wfifo diff --git a/projects/fmcomms2/zc706/system_project.tcl b/projects/fmcomms2/zc706/system_project.tcl index 68b41d86f..09b56d4c5 100755 --- a/projects/fmcomms2/zc706/system_project.tcl +++ b/projects/fmcomms2/zc706/system_project.tcl @@ -9,7 +9,7 @@ adi_project_create fmcomms2_zc706 adi_project_files fmcomms2_zc706 [list \ "system_top.v" \ "system_constr.xdc"\ - "$ad_hdl_dir/library/common/ad_iobuf.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \ "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ] adi_project_run fmcomms2_zc706 diff --git a/projects/fmcomms2/zc706pr/Makefile b/projects/fmcomms2/zc706pr/Makefile index 755bcedba..f4d14bac4 100644 --- a/projects/fmcomms2/zc706pr/Makefile +++ b/projects/fmcomms2/zc706pr/Makefile @@ -5,20 +5,48 @@ #################################################################################### #################################################################################### -M_DEPS := system_project.tcl -M_DEPS += ../../scripts/adi_env.tcl -M_DEPS += ../../scripts/adi_project.tcl -M_DEPS += ../../scripts/adi_board.tcl +M_DEPS += system_top.v +M_DEPS += system_project.tcl +M_DEPS += system_constr.xdc M_DEPS += system_bd.tcl +M_DEPS += ../zc706/system_constr.xdc M_DEPS += ../zc706/system_bd.tcl -M_DEPS += ../../common/zc706/zc706_system_bd.tcl +M_DEPS += ../common/prcfg_bd.tcl +M_DEPS += ../common/prcfg_bb.v +M_DEPS += ../common/prcfg.xdc +M_DEPS += ../common/prcfg.v M_DEPS += ../common/fmcomms2_bd.tcl +M_DEPS += ../../scripts/adi_project.tcl +M_DEPS += ../../scripts/adi_env.tcl +M_DEPS += ../../scripts/adi_board.tcl +M_DEPS += ../../common/zc706/zc706_system_constr.xdc +M_DEPS += ../../common/zc706/zc706_system_bd.tcl +M_DEPS += ../../../library/xilinx/common/ad_iobuf.v +M_DEPS += ../../../library/prcfg/qpsk/qpsk_mod.v +M_DEPS += ../../../library/prcfg/qpsk/qpsk_demod.v +M_DEPS += ../../../library/prcfg/qpsk/prcfg_dac.v +M_DEPS += ../../../library/prcfg/qpsk/prcfg_adc.v +M_DEPS += ../../../library/prcfg/qpsk/Raised_Cosine_Transmit_Filter.v +M_DEPS += ../../../library/prcfg/qpsk/Raised_Cosine_Receive_Filter.v +M_DEPS += ../../../library/prcfg/qpsk/QPSK_Modulator_Baseband.v +M_DEPS += ../../../library/prcfg/qpsk/QPSK_Demodulator_Baseband.v +M_DEPS += ../../../library/prcfg/qpsk/FIR_Interpolation.v +M_DEPS += ../../../library/prcfg/qpsk/FIR_Decimation.v +M_DEPS += ../../../library/prcfg/default/prcfg_dac.v +M_DEPS += ../../../library/prcfg/default/prcfg_adc.v +M_DEPS += ../../../library/prcfg/common/prcfg_top.v +M_DEPS += ../../../library/prcfg/bist/prcfg_dac.v +M_DEPS += ../../../library/prcfg/bist/prcfg_adc.v +M_DEPS += ../../../library/common/ad_pnmon.v M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr +M_DEPS += ../../../library/util_clkdiv/util_clkdiv.xpr M_DEPS += ../../../library/util_cpack/util_cpack.xpr +M_DEPS += ../../../library/util_rfifo/util_rfifo.xpr +M_DEPS += ../../../library/util_tdd_sync/util_tdd_sync.xpr M_DEPS += ../../../library/util_upack/util_upack.xpr M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr @@ -33,12 +61,15 @@ M_FLIST += xgui M_FLIST += *.runs M_FLIST += *.srcs M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim M_FLIST += .Xil +M_FLIST += *.ip_user_files .PHONY: all lib clean clean-all -all: lib fmcomms2_zc706pr.sdk/system_top.hdf +all: lib fmcomms2_zc706.sdk/system_top.hdf clean: @@ -51,14 +82,17 @@ clean-all:clean make -C ../../../library/axi_dmac clean make -C ../../../library/axi_hdmi_tx clean make -C ../../../library/axi_spdif_tx clean + make -C ../../../library/util_clkdiv clean make -C ../../../library/util_cpack clean + make -C ../../../library/util_rfifo clean + make -C ../../../library/util_tdd_sync clean make -C ../../../library/util_upack clean make -C ../../../library/util_wfifo clean -fmcomms2_zc706pr.sdk/system_top.hdf: $(M_DEPS) - rm -rf $(M_FLIST) - $(M_VIVADO) system_project.tcl >> fmcomms2_zc706pr_vivado.log 2>&1 +fmcomms2_zc706.sdk/system_top.hdf: $(M_DEPS) + -rm -rf $(M_FLIST) + $(M_VIVADO) system_project.tcl >> fmcomms2_zc706_vivado.log 2>&1 lib: @@ -67,7 +101,10 @@ lib: make -C ../../../library/axi_dmac make -C ../../../library/axi_hdmi_tx make -C ../../../library/axi_spdif_tx + make -C ../../../library/util_clkdiv make -C ../../../library/util_cpack + make -C ../../../library/util_rfifo + make -C ../../../library/util_tdd_sync make -C ../../../library/util_upack make -C ../../../library/util_wfifo diff --git a/projects/fmcomms2/zc706pr/system_constr.xdc b/projects/fmcomms2/zc706pr/system_constr.xdc index 53377ada7..e69de29bb 100644 --- a/projects/fmcomms2/zc706pr/system_constr.xdc +++ b/projects/fmcomms2/zc706pr/system_constr.xdc @@ -1,44 +0,0 @@ - -set_false_path -from [get_cells -hierarchical -filter {name =~ i_prcfg* && IS_SEQUENTIAL}] \ - -to [get_cells -hierarchical -filter {name =~ i_system* && IS_SEQUENTIAL}] -set_false_path -from [get_cells -hierarchical -filter {name =~ i_system* && IS_SEQUENTIAL}] \ - -to [get_cells -hierarchical -filter {name =~ i_prcfg* && IS_SEQUENTIAL}] - -set_false_path -from [get_cells -hierarchical -filter {name =~ i_prcfg* && IS_SEQUENTIAL}] \ - -to [get_cells -hierarchical -filter {name =~ i_prcfg*i_pn_mon* && IS_SEQUENTIAL}] - -set_false_path -from [get_cells -hierarchical -filter {name =~ i_prcfg*input_pipeline_phase* && IS_SEQUENTIAL}] \ - -to [get_cells -hierarchical -filter {name =~ i_prcfg*ddata_reg* && IS_SEQUENTIAL}] - -set_false_path -from [get_cells -hierarchical -filter {name =~ i_prcfg*FIR_Decimation* && IS_SEQUENTIAL}] \ - -to [get_cells -hierarchical -filter {name =~ i_prcfg*dst_adc_ddata_reg*}] -set_false_path -from [get_cells -hierarchical -filter {name =~ i_prcfg*FIR_Interpolation* && IS_SEQUENTIAL}] \ - -to [get_cells -hierarchical -filter {name =~ i_prcfg*dst_dac_ddata_reg*}] - -set_false_path -from [get_cells -hierarchical -filter {name =~ i_prcfg*FIR_Decimation*}] \ - -to [get_cells -hierarchical -filter {name =~ i_prcfg*FIR_Decimation*regout_re_reg* && IS_SEQUENTIAL}] -set_false_path -from [get_cells -hierarchical -filter {name =~ i_prcfg*FIR_Decimation*}] \ - -to [get_cells -hierarchical -filter {name =~ i_prcfg*FIR_Decimation*regout_im_reg* && IS_SEQUENTIAL}] - -set_false_path -from [get_cells -hierarchical -filter {name =~ i_prcfg*FIR_Interpolation*cur_count_reg*}] \ - -to [get_cells -hierarchical -filter {name =~ i_prcfg*FIR_Interpolation*regout_re_reg* && IS_SEQUENTIAL}] -set_false_path -from [get_cells -hierarchical -filter {name =~ i_prcfg*FIR_Interpolation*cur_count_reg*}] \ - -to [get_cells -hierarchical -filter {name =~ i_prcfg*FIR_Interpolation*regout_im_reg* && IS_SEQUENTIAL}] - -set_false_path -from [get_cells -hierarchical -filter {name =~ i_prcfg*prcfg_dac*mode_reg*}] \ - -to [get_cells -hierarchical -filter {name =~ i_prcfg*FIR_Interpolation* && IS_SEQUENTIAL}] -set_false_path -from [get_cells -hierarchical -filter {name =~ i_prcfg*prcfg_dac*mode_reg*}] \ - -to [get_cells -hierarchical -filter {name =~ i_prcfg*dst_dac_ddata_reg* && IS_SEQUENTIAL}] - -set_false_path -from [get_cells -hierarchical -filter {name =~ i_prcfg*pn_data_reg*}] \ - -to [get_cells -hierarchical -filter {name =~ i_prcfg*FIR_Interpolation*regout_re_reg* && IS_SEQUENTIAL}] -set_false_path -from [get_cells -hierarchical -filter {name =~ i_prcfg*pn_data_reg*}] \ - -to [get_cells -hierarchical -filter {name =~ i_prcfg*FIR_Interpolation*regout_im_reg* && IS_SEQUENTIAL}] -set_false_path -from [get_cells -hierarchical -filter {name =~ i_prcfg*pn_data_reg*}] \ - -to [get_cells -hierarchical -filter {name =~ i_prcfg*dst_dac_ddata_reg* && IS_SEQUENTIAL}] - -set_false_path -from [get_cells -hierarchical -filter {name =~ i_prcfg*FIR_Interpolation*delay_pipeline_re_reg*}] \ - -to [get_cells -hierarchical -filter {name =~ i_prcfg*FIR_Interpolation*regout_re_reg* && IS_SEQUENTIAL}] -set_false_path -from [get_cells -hierarchical -filter {name =~ i_prcfg*FIR_Interpolation*delay_pipeline_im_reg*}] \ - -to [get_cells -hierarchical -filter {name =~ i_prcfg*FIR_Interpolation*regout_im_reg* && IS_SEQUENTIAL}] - diff --git a/projects/fmcomms2/zc706pr/system_project.tcl b/projects/fmcomms2/zc706pr/system_project.tcl index 89e9c90c5..f73f3d4a7 100755 --- a/projects/fmcomms2/zc706pr/system_project.tcl +++ b/projects/fmcomms2/zc706pr/system_project.tcl @@ -1,15 +1,37 @@ - - +## requires partial reconfiguration license source ../../scripts/adi_env.tcl source $ad_hdl_dir/projects/scripts/adi_project.tcl source $ad_hdl_dir/projects/scripts/adi_board.tcl +set mode 1 +if {$::argc > 0} { + set mode [lindex $argv 0] +} + +if {$mode == 0} { + + adi_project_create fmcomms2_zc706 + adi_project_files fmcomms2_zc706 [list \ + "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" \ + "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \ + "$ad_hdl_dir/library/prcfg/common/prcfg_top.v" \ + "$ad_hdl_dir/library/prcfg/default/prcfg_dac.v" \ + "$ad_hdl_dir/library/prcfg/default/prcfg_adc.v" \ + "../common/prcfg.v" \ + "../zc706/system_constr.xdc" \ + "system_top.v" ] + + adi_project_run fmcomms2_zc706 + + return +} + adi_project_create fmcomms2_zc706 1 adi_project_synth fmcomms2_zc706 "" \ [list "system_top.v" \ "../common/prcfg_bb.v" \ - "$ad_hdl_dir/library/common/ad_iobuf.v"] \ + "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v"] \ [list "../zc706/system_constr.xdc" \ "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc"] diff --git a/projects/fmcomms2/zc706pr/system_top.v b/projects/fmcomms2/zc706pr/system_top.v index 2a8fff688..8ebbb1671 100644 --- a/projects/fmcomms2/zc706pr/system_top.v +++ b/projects/fmcomms2/zc706pr/system_top.v @@ -88,8 +88,13 @@ module system_top ( tx_data_out_p, tx_data_out_n, - gpio_txnrx, - gpio_enable, + enable, + txnrx, + + tdd_sync, + + gpio_muxout_tx, + gpio_muxout_rx, gpio_resetb, gpio_sync, gpio_en_agc, @@ -99,7 +104,12 @@ module system_top ( spi_csn, spi_clk, spi_mosi, - spi_miso); + spi_miso, + + spi_udc_csn_tx, + spi_udc_csn_rx, + spi_udc_sclk, + spi_udc_data); inout [14:0] ddr_addr; inout [ 2:0] ddr_ba; @@ -150,8 +160,13 @@ module system_top ( output [ 5:0] tx_data_out_p; output [ 5:0] tx_data_out_n; - inout gpio_txnrx; - inout gpio_enable; + output enable; + output txnrx; + + inout tdd_sync; + + inout gpio_muxout_tx; + inout gpio_muxout_rx; inout gpio_resetb; inout gpio_sync; inout gpio_en_agc; @@ -163,12 +178,16 @@ module system_top ( output spi_mosi; input spi_miso; + output spi_udc_csn_tx; + output spi_udc_csn_rx; + output spi_udc_sclk; + output spi_udc_data; + // internal signals wire [63:0] gpio_i; wire [63:0] gpio_o; wire [63:0] gpio_t; - wire clk; wire dma_dac_i0_enable; wire [15:0] dma_dac_i0_data; @@ -218,7 +237,6 @@ module system_top ( wire core_adc_q1_enable; wire [15:0] core_adc_q1_data; wire core_adc_q1_valid; - wire [31:0] adc_gpio_input; wire [31:0] adc_gpio_output; wire [31:0] dac_gpio_input; @@ -254,6 +272,7 @@ module system_top ( .dio_p (tdd_sync)); // prcfg instance + prcfg i_prcfg ( .clk (clk), .adc_gpio_input (adc_gpio_input), @@ -307,8 +326,7 @@ module system_top ( .core_adc_i1_valid (core_adc_i1_valid), .core_adc_q1_enable (core_adc_q1_enable), .core_adc_q1_data (core_adc_q1_data), - .core_adc_q1_valid (core_adc_q1_valid) - ); + .core_adc_q1_valid (core_adc_q1_valid)); system_wrapper i_system_wrapper ( .ddr_addr (ddr_addr), @@ -371,13 +389,27 @@ module system_top ( .spi0_sdi_i (spi_miso), .spi0_sdo_i (1'b0), .spi0_sdo_o (spi_mosi), + .spi1_clk_i (1'b0), + .spi1_clk_o (spi_udc_sclk), + .spi1_csn_0_o (spi_udc_csn_tx), + .spi1_csn_1_o (spi_udc_csn_rx), + .spi1_csn_2_o (), + .spi1_csn_i (1'b1), + .spi1_sdi_i (1'b0), + .spi1_sdo_i (spi_udc_data), + .spi1_sdo_o (spi_udc_data), + .tdd_sync_i (tdd_sync_i), + .tdd_sync_o (tdd_sync_o), + .tdd_sync_t (tdd_sync_t), .tx_clk_out_n (tx_clk_out_n), .tx_clk_out_p (tx_clk_out_p), .tx_data_out_n (tx_data_out_n), .tx_data_out_p (tx_data_out_p), .tx_frame_out_n (tx_frame_out_n), .tx_frame_out_p (tx_frame_out_p), - // pr related ports + .txnrx (txnrx), + .up_enable (gpio_o[47]), + .up_txnrx (gpio_o[48]), .clk (clk), .up_adc_gpio_in (adc_gpio_input), .up_adc_gpio_out (adc_gpio_output), @@ -430,8 +462,7 @@ module system_top ( .core_adc_i1_valid (core_adc_i1_valid), .core_adc_q1_enable (core_adc_q1_enable), .core_adc_q1_data (core_adc_q1_data), - .core_adc_q1_valid (core_adc_q1_valid) - ); + .core_adc_q1_valid (core_adc_q1_valid)); endmodule diff --git a/projects/pzsdr/ccpci/Makefile b/projects/fmcomms2/zcu102/Makefile similarity index 74% rename from projects/pzsdr/ccpci/Makefile rename to projects/fmcomms2/zcu102/Makefile index fafebeaaa..ffbf73b78 100644 --- a/projects/pzsdr/ccpci/Makefile +++ b/projects/fmcomms2/zcu102/Makefile @@ -9,19 +9,18 @@ M_DEPS += system_top.v M_DEPS += system_project.tcl M_DEPS += system_constr.xdc M_DEPS += system_bd.tcl -M_DEPS += ../common/ccpci_bd.tcl +M_DEPS += ../common/fmcomms2_bd.tcl M_DEPS += ../../scripts/adi_project.tcl M_DEPS += ../../scripts/adi_env.tcl M_DEPS += ../../scripts/adi_board.tcl -M_DEPS += ../../fmcomms2/common/fmcomms2_bd.tcl -M_DEPS += ../../common/xilinx/sys_wfifo.tcl -M_DEPS += ../../common/pzsdr/pzsdr_system_ps7.tcl -M_DEPS += ../../common/pzsdr/pzsdr_system_constr.xdc -M_DEPS += ../../common/pzsdr/pzsdr_system_bd.tcl -M_DEPS += ../../../library/common/ad_iobuf.v +M_DEPS += ../../common/zcu102/zcu102_system_constr.xdc +M_DEPS += ../../common/zcu102/zcu102_system_bd.tcl +M_DEPS += ../../../library/xilinx/common/ad_iobuf.v M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr +M_DEPS += ../../../library/util_clkdiv/util_clkdiv.xpr M_DEPS += ../../../library/util_cpack/util_cpack.xpr +M_DEPS += ../../../library/util_rfifo/util_rfifo.xpr M_DEPS += ../../../library/util_tdd_sync/util_tdd_sync.xpr M_DEPS += ../../../library/util_upack/util_upack.xpr M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr @@ -40,11 +39,12 @@ M_FLIST += *.sdk M_FLIST += *.hw M_FLIST += *.sim M_FLIST += .Xil +M_FLIST += *.ip_user_files .PHONY: all lib clean clean-all -all: lib ccpci_pzsdr.sdk/system_top.hdf +all: lib fmcomms2_zcu102.sdk/system_top.hdf clean: @@ -54,21 +54,25 @@ clean: clean-all:clean make -C ../../../library/axi_ad9361 clean make -C ../../../library/axi_dmac clean + make -C ../../../library/util_clkdiv clean make -C ../../../library/util_cpack clean + make -C ../../../library/util_rfifo clean make -C ../../../library/util_tdd_sync clean make -C ../../../library/util_upack clean make -C ../../../library/util_wfifo clean -ccpci_pzsdr.sdk/system_top.hdf: $(M_DEPS) - rm -rf $(M_FLIST) - $(M_VIVADO) system_project.tcl >> ccpci_pzsdr_vivado.log 2>&1 +fmcomms2_zcu102.sdk/system_top.hdf: $(M_DEPS) + -rm -rf $(M_FLIST) + $(M_VIVADO) system_project.tcl >> fmcomms2_zcu102_vivado.log 2>&1 lib: make -C ../../../library/axi_ad9361 make -C ../../../library/axi_dmac + make -C ../../../library/util_clkdiv make -C ../../../library/util_cpack + make -C ../../../library/util_rfifo make -C ../../../library/util_tdd_sync make -C ../../../library/util_upack make -C ../../../library/util_wfifo diff --git a/projects/fmcomms2/zcu102/system_bd.tcl b/projects/fmcomms2/zcu102/system_bd.tcl new file mode 100755 index 000000000..5bcd5220a --- /dev/null +++ b/projects/fmcomms2/zcu102/system_bd.tcl @@ -0,0 +1,8 @@ + +source $ad_hdl_dir/projects/common/zcu102/zcu102_system_bd.tcl +source ../common/fmcomms2_bd.tcl + +set_property -dict [list CONFIG.SIM_DEVICE {ULTRASCALE}] $clkdiv + +set_property CONFIG.DEVICE_TYPE 2 [get_bd_cells axi_ad9361] + diff --git a/projects/fmcomms2/zcu102/system_constr.xdc b/projects/fmcomms2/zcu102/system_constr.xdc new file mode 100644 index 000000000..921dc981b --- /dev/null +++ b/projects/fmcomms2/zcu102/system_constr.xdc @@ -0,0 +1,64 @@ + +# constraints +# ad9361 + +set_property -dict {PACKAGE_PIN Y4 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_clk_in_p] ; ## G6 FMC_LPC_LA00_CC_P +set_property -dict {PACKAGE_PIN Y3 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_clk_in_n] ; ## G7 FMC_LPC_LA00_CC_N +set_property -dict {PACKAGE_PIN W2 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_frame_in_p] ; ## D8 FMC_LPC_LA01_CC_P +set_property -dict {PACKAGE_PIN W1 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_frame_in_n] ; ## D9 FMC_LPC_LA01_CC_N +set_property -dict {PACKAGE_PIN V2 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_p[0]] ; ## H7 FMC_LPC_LA02_P +set_property -dict {PACKAGE_PIN V1 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_n[0]] ; ## H8 FMC_LPC_LA02_N +set_property -dict {PACKAGE_PIN Y2 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_p[1]] ; ## G9 FMC_LPC_LA03_P +set_property -dict {PACKAGE_PIN Y1 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_n[1]] ; ## G10 FMC_LPC_LA03_N +set_property -dict {PACKAGE_PIN AA2 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_p[2]] ; ## H10 FMC_LPC_LA04_P +set_property -dict {PACKAGE_PIN AA1 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_n[2]] ; ## H11 FMC_LPC_LA04_N +set_property -dict {PACKAGE_PIN AB3 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_p[3]] ; ## D11 FMC_LPC_LA05_P +set_property -dict {PACKAGE_PIN AC3 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_n[3]] ; ## D12 FMC_LPC_LA05_N +set_property -dict {PACKAGE_PIN AC2 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_p[4]] ; ## C10 FMC_LPC_LA06_P +set_property -dict {PACKAGE_PIN AC1 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_n[4]] ; ## C11 FMC_LPC_LA06_N +set_property -dict {PACKAGE_PIN U5 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_p[5]] ; ## H13 FMC_LPC_LA07_P +set_property -dict {PACKAGE_PIN U4 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_n[5]] ; ## H14 FMC_LPC_LA07_N +set_property -dict {PACKAGE_PIN V4 IOSTANDARD LVDS} [get_ports tx_clk_out_p] ; ## G12 FMC_LPC_LA08_P +set_property -dict {PACKAGE_PIN V3 IOSTANDARD LVDS} [get_ports tx_clk_out_n] ; ## G13 FMC_LPC_LA08_N +set_property -dict {PACKAGE_PIN AB4 IOSTANDARD LVDS} [get_ports tx_frame_out_p] ; ## D14 FMC_LPC_LA09_P +set_property -dict {PACKAGE_PIN AC4 IOSTANDARD LVDS} [get_ports tx_frame_out_n] ; ## D15 FMC_LPC_LA09_N +set_property -dict {PACKAGE_PIN AB6 IOSTANDARD LVDS} [get_ports tx_data_out_p[0]] ; ## H16 FMC_LPC_LA11_P +set_property -dict {PACKAGE_PIN AB5 IOSTANDARD LVDS} [get_ports tx_data_out_n[0]] ; ## H17 FMC_LPC_LA11_N +set_property -dict {PACKAGE_PIN W7 IOSTANDARD LVDS} [get_ports tx_data_out_p[1]] ; ## G15 FMC_LPC_LA12_P +set_property -dict {PACKAGE_PIN W6 IOSTANDARD LVDS} [get_ports tx_data_out_n[1]] ; ## G16 FMC_LPC_LA12_N +set_property -dict {PACKAGE_PIN AB8 IOSTANDARD LVDS} [get_ports tx_data_out_p[2]] ; ## D17 FMC_LPC_LA13_P +set_property -dict {PACKAGE_PIN AC8 IOSTANDARD LVDS} [get_ports tx_data_out_n[2]] ; ## D18 FMC_LPC_LA13_N +set_property -dict {PACKAGE_PIN W5 IOSTANDARD LVDS} [get_ports tx_data_out_p[3]] ; ## C14 FMC_LPC_LA10_P +set_property -dict {PACKAGE_PIN W4 IOSTANDARD LVDS} [get_ports tx_data_out_n[3]] ; ## C15 FMC_LPC_LA10_N +set_property -dict {PACKAGE_PIN AC7 IOSTANDARD LVDS} [get_ports tx_data_out_p[4]] ; ## C18 FMC_LPC_LA14_P +set_property -dict {PACKAGE_PIN AC6 IOSTANDARD LVDS} [get_ports tx_data_out_n[4]] ; ## C19 FMC_LPC_LA14_N +set_property -dict {PACKAGE_PIN Y10 IOSTANDARD LVDS} [get_ports tx_data_out_p[5]] ; ## H19 FMC_LPC_LA15_P +set_property -dict {PACKAGE_PIN Y9 IOSTANDARD LVDS} [get_ports tx_data_out_n[5]] ; ## H20 FMC_LPC_LA15_N +set_property -dict {PACKAGE_PIN Y12 IOSTANDARD LVCMOS18} [get_ports enable] ; ## G18 FMC_LPC_LA16_P +set_property -dict {PACKAGE_PIN AA12 IOSTANDARD LVCMOS18} [get_ports txnrx] ; ## G19 FMC_LPC_LA16_N + +set_property -dict {PACKAGE_PIN N13 IOSTANDARD LVCMOS18} [get_ports gpio_status[0]] ; ## G21 FMC_LPC_LA20_P +set_property -dict {PACKAGE_PIN M13 IOSTANDARD LVCMOS18} [get_ports gpio_status[1]] ; ## G22 FMC_LPC_LA20_N +set_property -dict {PACKAGE_PIN P12 IOSTANDARD LVCMOS18} [get_ports gpio_status[2]] ; ## H25 FMC_LPC_LA21_P +set_property -dict {PACKAGE_PIN N12 IOSTANDARD LVCMOS18} [get_ports gpio_status[3]] ; ## H26 FMC_LPC_LA21_N +set_property -dict {PACKAGE_PIN M15 IOSTANDARD LVCMOS18} [get_ports gpio_status[4]] ; ## G24 FMC_LPC_LA22_P +set_property -dict {PACKAGE_PIN M14 IOSTANDARD LVCMOS18} [get_ports gpio_status[5]] ; ## G25 FMC_LPC_LA22_N +set_property -dict {PACKAGE_PIN L16 IOSTANDARD LVCMOS18} [get_ports gpio_status[6]] ; ## D23 FMC_LPC_LA23_P +set_property -dict {PACKAGE_PIN K16 IOSTANDARD LVCMOS18} [get_ports gpio_status[7]] ; ## D24 FMC_LPC_LA23_N +set_property -dict {PACKAGE_PIN L12 IOSTANDARD LVCMOS18} [get_ports gpio_ctl[0]] ; ## H28 FMC_LPC_LA24_P +set_property -dict {PACKAGE_PIN K12 IOSTANDARD LVCMOS18} [get_ports gpio_ctl[1]] ; ## H29 FMC_LPC_LA24_N +set_property -dict {PACKAGE_PIN M11 IOSTANDARD LVCMOS18} [get_ports gpio_ctl[2]] ; ## G27 FMC_LPC_LA25_P +set_property -dict {PACKAGE_PIN L11 IOSTANDARD LVCMOS18} [get_ports gpio_ctl[3]] ; ## G28 FMC_LPC_LA25_N +set_property -dict {PACKAGE_PIN L13 IOSTANDARD LVCMOS18} [get_ports gpio_en_agc] ; ## H22 FMC_LPC_LA19_P +set_property -dict {PACKAGE_PIN K13 IOSTANDARD LVCMOS18} [get_ports gpio_sync] ; ## H23 FMC_LPC_LA19_N +set_property -dict {PACKAGE_PIN T7 IOSTANDARD LVCMOS18} [get_ports gpio_resetb] ; ## H31 FMC_LPC_LA28_P + +set_property -dict {PACKAGE_PIN N9 IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports spi_csn] ; ## D26 FMC_LPC_LA26_P +set_property -dict {PACKAGE_PIN N8 IOSTANDARD LVCMOS18} [get_ports spi_clk] ; ## D27 FMC_LPC_LA26_N +set_property -dict {PACKAGE_PIN M10 IOSTANDARD LVCMOS18} [get_ports spi_mosi] ; ## C26 FMC_LPC_LA27_P +set_property -dict {PACKAGE_PIN L10 IOSTANDARD LVCMOS18} [get_ports spi_miso] ; ## C27 FMC_LPC_LA27_N + +# clocks + +create_clock -name rx_clk -period 4.00 [get_ports rx_clk_in_p] + diff --git a/projects/fmcomms2/zcu102/system_project.tcl b/projects/fmcomms2/zcu102/system_project.tcl new file mode 100755 index 000000000..b11579292 --- /dev/null +++ b/projects/fmcomms2/zcu102/system_project.tcl @@ -0,0 +1,17 @@ + + + +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/projects/scripts/adi_project.tcl +source $ad_hdl_dir/projects/scripts/adi_board.tcl + +adi_project_create fmcomms2_zcu102 +adi_project_files fmcomms2_zcu102 [list \ + "system_top.v" \ + "system_constr.xdc"\ + "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \ + "$ad_hdl_dir/projects/common/zcu102/zcu102_system_constr.xdc" ] + +adi_project_run fmcomms2_zcu102 + + diff --git a/projects/fmcomms2/zcu102/system_top.v b/projects/fmcomms2/zcu102/system_top.v new file mode 100644 index 000000000..4ae6455bb --- /dev/null +++ b/projects/fmcomms2/zcu102/system_top.v @@ -0,0 +1,143 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top ( + + input [12:0] gpio_bd_i, + output [ 7:0] gpio_bd_o, + + input rx_clk_in_p, + input rx_clk_in_n, + input rx_frame_in_p, + input rx_frame_in_n, + input [ 5:0] rx_data_in_p, + input [ 5:0] rx_data_in_n, + output tx_clk_out_p, + output tx_clk_out_n, + output tx_frame_out_p, + output tx_frame_out_n, + output [ 5:0] tx_data_out_p, + output [ 5:0] tx_data_out_n, + + output enable, + output txnrx, + + output gpio_resetb, + output gpio_sync, + output gpio_en_agc, + output [ 3:0] gpio_ctl, + input [ 7:0] gpio_status, + + output spi_csn, + output spi_clk, + output spi_mosi, + input spi_miso); + + // internal signals + + wire [95:0] gpio_i; + wire [95:0] gpio_o; + wire [ 2:0] spi0_csn; + + // defaults + + assign gpio_resetb = gpio_o[46:46]; + assign gpio_sync = gpio_o[45:45]; + assign gpio_en_agc = gpio_o[44:44]; + assign gpio_ctl = gpio_o[43:40]; + assign gpio_bd_o = gpio_o[20:13]; + + assign gpio_i[95:40] = gpio_o[95:40]; + assign gpio_i[39:32] = gpio_status; + assign gpio_i[31:13] = gpio_o[31:13]; + assign gpio_i[12: 0] = gpio_bd_i; + + assign spi_csn = spi0_csn[0]; + + // instantiations + + system_wrapper i_system_wrapper ( + .enable (enable), + .gpio_i (gpio_i), + .gpio_o (gpio_o), + .ps_intr_00 (1'b0), + .ps_intr_01 (1'b0), + .ps_intr_02 (1'b0), + .ps_intr_03 (1'b0), + .ps_intr_04 (1'b0), + .ps_intr_05 (1'b0), + .ps_intr_06 (1'b0), + .ps_intr_07 (1'b0), + .ps_intr_08 (1'b0), + .ps_intr_09 (1'b0), + .ps_intr_10 (1'b0), + .ps_intr_11 (1'b0), + .ps_intr_14 (1'b0), + .ps_intr_15 (1'b0), + .rx_clk_in_n (rx_clk_in_n), + .rx_clk_in_p (rx_clk_in_p), + .rx_data_in_n (rx_data_in_n), + .rx_data_in_p (rx_data_in_p), + .rx_frame_in_n (rx_frame_in_n), + .rx_frame_in_p (rx_frame_in_p), + .spi0_csn (spi0_csn), + .spi0_miso (spi_miso), + .spi0_mosi (spi_mosi), + .spi0_sclk (spi_clk), + .spi1_csn (), + .spi1_miso (1'b0), + .spi1_mosi (), + .spi1_sclk (), + .tdd_sync_i (1'b0), + .tdd_sync_o (), + .tdd_sync_t (), + .tx_clk_out_n (tx_clk_out_n), + .tx_clk_out_p (tx_clk_out_p), + .tx_data_out_n (tx_data_out_n), + .tx_data_out_p (tx_data_out_p), + .tx_frame_out_n (tx_frame_out_n), + .tx_frame_out_p (tx_frame_out_p), + .txnrx (txnrx), + .up_enable (gpio_o[47]), + .up_txnrx (gpio_o[48])); + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/projects/fmcomms2/zed/Makefile b/projects/fmcomms2/zed/Makefile index 9fd8dcfc5..c6cca6d96 100644 --- a/projects/fmcomms2/zed/Makefile +++ b/projects/fmcomms2/zed/Makefile @@ -16,15 +16,17 @@ M_DEPS += ../../scripts/adi_board.tcl M_DEPS += ../../common/zed/zed_system_constr.xdc M_DEPS += ../../common/zed/zed_system_bd.tcl M_DEPS += ../../common/xilinx/sys_wfifo.tcl -M_DEPS += ../../../library/common/ad_iobuf.v +M_DEPS += ../../../library/xilinx/common/ad_iobuf.v M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr M_DEPS += ../../../library/axi_i2s_adi/axi_i2s_adi.xpr M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr +M_DEPS += ../../../library/util_clkdiv/util_clkdiv.xpr M_DEPS += ../../../library/util_cpack/util_cpack.xpr M_DEPS += ../../../library/util_i2c_mixer/util_i2c_mixer.xpr +M_DEPS += ../../../library/util_rfifo/util_rfifo.xpr M_DEPS += ../../../library/util_tdd_sync/util_tdd_sync.xpr M_DEPS += ../../../library/util_upack/util_upack.xpr M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr @@ -43,6 +45,7 @@ M_FLIST += *.sdk M_FLIST += *.hw M_FLIST += *.sim M_FLIST += .Xil +M_FLIST += *.ip_user_files @@ -61,15 +64,17 @@ clean-all:clean make -C ../../../library/axi_hdmi_tx clean make -C ../../../library/axi_i2s_adi clean make -C ../../../library/axi_spdif_tx clean + make -C ../../../library/util_clkdiv clean make -C ../../../library/util_cpack clean make -C ../../../library/util_i2c_mixer clean + make -C ../../../library/util_rfifo clean make -C ../../../library/util_tdd_sync clean make -C ../../../library/util_upack clean make -C ../../../library/util_wfifo clean fmcomms2_zed.sdk/system_top.hdf: $(M_DEPS) - rm -rf $(M_FLIST) + -rm -rf $(M_FLIST) $(M_VIVADO) system_project.tcl >> fmcomms2_zed_vivado.log 2>&1 @@ -80,8 +85,10 @@ lib: make -C ../../../library/axi_hdmi_tx make -C ../../../library/axi_i2s_adi make -C ../../../library/axi_spdif_tx + make -C ../../../library/util_clkdiv make -C ../../../library/util_cpack make -C ../../../library/util_i2c_mixer + make -C ../../../library/util_rfifo make -C ../../../library/util_tdd_sync make -C ../../../library/util_upack make -C ../../../library/util_wfifo diff --git a/projects/fmcomms2/zed/system_project.tcl b/projects/fmcomms2/zed/system_project.tcl index 330fca68a..a5e387142 100644 --- a/projects/fmcomms2/zed/system_project.tcl +++ b/projects/fmcomms2/zed/system_project.tcl @@ -7,7 +7,7 @@ adi_project_create fmcomms2_zed adi_project_files fmcomms2_zed [list \ "system_top.v" \ "system_constr.xdc"\ - "$ad_hdl_dir/library/common/ad_iobuf.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \ "$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc" ] adi_project_run fmcomms2_zed diff --git a/projects/fmcomms5/Makefile b/projects/fmcomms5/Makefile index 1aadef09e..f7de0659c 100644 --- a/projects/fmcomms5/Makefile +++ b/projects/fmcomms5/Makefile @@ -9,16 +9,19 @@ all: -make -C zc702 all -make -C zc706 all + -make -C zcu102 all clean: make -C zc702 clean make -C zc706 clean + make -C zcu102 clean clean-all: make -C zc702 clean-all make -C zc706 clean-all + make -C zcu102 clean-all #################################################################################### #################################################################################### diff --git a/projects/fmcomms5/common/fmcomms5_bd.tcl b/projects/fmcomms5/common/fmcomms5_bd.tcl index 3150ebe0c..ba8720273 100644 --- a/projects/fmcomms5/common/fmcomms5_bd.tcl +++ b/projects/fmcomms5/common/fmcomms5_bd.tcl @@ -16,6 +16,11 @@ create_bd_port -dir O tx_frame_out_0_n create_bd_port -dir O -from 5 -to 0 tx_data_out_0_p create_bd_port -dir O -from 5 -to 0 tx_data_out_0_n +create_bd_port -dir O enable_0 +create_bd_port -dir O txnrx_0 +create_bd_port -dir I up_enable_0 +create_bd_port -dir I up_txnrx_0 + # slave create_bd_port -dir I rx_clk_in_1_p @@ -31,6 +36,11 @@ create_bd_port -dir O tx_frame_out_1_n create_bd_port -dir O -from 5 -to 0 tx_data_out_1_p create_bd_port -dir O -from 5 -to 0 tx_data_out_1_n +create_bd_port -dir O enable_1 +create_bd_port -dir O txnrx_1 +create_bd_port -dir I up_enable_1 +create_bd_port -dir I up_txnrx_1 + create_bd_port -dir O sys_100m_resetn # instances @@ -89,60 +99,90 @@ set_property -dict [list CONFIG.DIN_DATA_WIDTH {16} ] $adc_wfifo set_property -dict [list CONFIG.DOUT_DATA_WIDTH {16} ] $adc_wfifo set_property -dict [list CONFIG.DIN_ADDRESS_WIDTH {4}] $adc_wfifo +set clkdiv [ create_bd_cell -type ip -vlnv analog.com:user:util_clkdiv:1.0 clkdiv ] + +set clkdiv_reset [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 clkdiv_reset] + +set dac_fifo [create_bd_cell -type ip -vlnv analog.com:user:util_rfifo:1.0 dac_fifo] +set_property -dict [list CONFIG.DIN_DATA_WIDTH {16}] $dac_fifo +set_property -dict [list CONFIG.DOUT_DATA_WIDTH {16}] $dac_fifo +set_property -dict [list CONFIG.DIN_ADDRESS_WIDTH {4}] $dac_fifo +set_property -dict [list CONFIG.NUM_OF_CHANNELS {8}] $dac_fifo + +set clkdiv_sel_logic [create_bd_cell -type ip -vlnv xilinx.com:ip:util_reduced_logic:2.0 clkdiv_sel_logic] +set_property -dict [list CONFIG.C_SIZE {4}] $clkdiv_sel_logic + +set concat_logic [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 concat_logic] +set_property -dict [list CONFIG.NUM_PORTS {4}] $concat_logic + # connections (ad9361) -ad_connect sys_200m_clk axi_ad9361_0/delay_clk -ad_connect sys_200m_clk axi_ad9361_1/delay_clk -ad_connect axi_ad9361_0_clk axi_ad9361_0/l_clk -ad_connect axi_ad9361_1_clk axi_ad9361_1/l_clk -ad_connect axi_ad9361_0_clk axi_ad9361_0/clk -ad_connect axi_ad9361_0_clk axi_ad9361_1/clk -ad_connect axi_ad9361_0/rst adc_wfifo/din_rst -ad_connect axi_ad9361_0_clk adc_wfifo/din_clk -ad_connect sys_cpu_clk adc_wfifo/dout_clk -ad_connect sys_cpu_resetn adc_wfifo/dout_rstn -ad_connect sys_cpu_clk util_cpack_adc/adc_clk -ad_connect sys_cpu_clk axi_ad9361_adc_dma/fifo_wr_clk -ad_connect axi_ad9361_0_clk util_upack_dac/dac_clk -ad_connect axi_ad9361_0_clk axi_ad9361_dac_dma/fifo_rd_clk -ad_connect sys_cpu_resetn sys_100m_resetn -ad_connect sys_cpu_resetn axi_ad9361_adc_dma/m_dest_axi_aresetn -ad_connect sys_cpu_resetn axi_ad9361_dac_dma/m_src_axi_aresetn -ad_connect sys_cpu_reset util_cpack_adc/adc_rst +ad_connect sys_200m_clk axi_ad9361_0/delay_clk +ad_connect sys_200m_clk axi_ad9361_1/delay_clk +ad_connect axi_ad9361_0_clk axi_ad9361_0/l_clk +ad_connect axi_ad9361_1_clk axi_ad9361_1/l_clk +ad_connect axi_ad9361_0_clk axi_ad9361_0/clk +ad_connect axi_ad9361_0_clk axi_ad9361_1/clk +ad_connect axi_ad9361_0_clk adc_wfifo/din_clk +ad_connect axi_ad9361_0_clk clkdiv/clk +ad_connect axi_ad9361_0_clk dac_fifo/dout_clk +ad_connect axi_ad9361_0/rst adc_wfifo/din_rst +ad_connect axi_ad9361_0/rst dac_fifo/dout_rst +ad_connect clkdiv/clk_out axi_ad9361_adc_dma/fifo_wr_clk +ad_connect clkdiv/clk_out adc_wfifo/dout_clk +ad_connect clkdiv/clk_out util_cpack_adc/adc_clk +ad_connect clkdiv/clk_out axi_ad9361_dac_dma/fifo_rd_clk +ad_connect clkdiv/clk_out dac_fifo/din_clk +ad_connect clkdiv/clk_out clkdiv_reset/slowest_sync_clk +ad_connect clkdiv/clk_out util_upack_dac/dac_clk +ad_connect sys_cpu_resetn sys_100m_resetn +ad_connect sys_cpu_resetn axi_ad9361_adc_dma/m_dest_axi_aresetn +ad_connect sys_cpu_resetn axi_ad9361_dac_dma/m_src_axi_aresetn +ad_connect clkdiv_reset/ext_reset_in sys_rstgen/peripheral_aresetn +ad_connect clkdiv_reset/peripheral_reset util_cpack_adc/adc_rst +ad_connect clkdiv_reset/peripheral_aresetn dac_fifo/din_rstn +ad_connect clkdiv_reset/peripheral_aresetn adc_wfifo/dout_rstn -ad_connect axi_ad9361_0_dac_sync axi_ad9361_0/dac_sync_out -ad_connect axi_ad9361_0_dac_sync axi_ad9361_0/dac_sync_in -ad_connect axi_ad9361_0_dac_sync axi_ad9361_1/dac_sync_in +ad_connect axi_ad9361_0_dac_sync axi_ad9361_0/dac_sync_out +ad_connect axi_ad9361_0_dac_sync axi_ad9361_0/dac_sync_in +ad_connect axi_ad9361_0_dac_sync axi_ad9361_1/dac_sync_in -ad_connect rx_clk_in_0_p axi_ad9361_0/rx_clk_in_p -ad_connect rx_clk_in_0_n axi_ad9361_0/rx_clk_in_n -ad_connect rx_frame_in_0_p axi_ad9361_0/rx_frame_in_p -ad_connect rx_frame_in_0_n axi_ad9361_0/rx_frame_in_n -ad_connect rx_data_in_0_p axi_ad9361_0/rx_data_in_p -ad_connect rx_data_in_0_n axi_ad9361_0/rx_data_in_n -ad_connect tx_clk_out_0_p axi_ad9361_0/tx_clk_out_p -ad_connect tx_clk_out_0_n axi_ad9361_0/tx_clk_out_n -ad_connect tx_frame_out_0_p axi_ad9361_0/tx_frame_out_p -ad_connect tx_frame_out_0_n axi_ad9361_0/tx_frame_out_n -ad_connect tx_data_out_0_p axi_ad9361_0/tx_data_out_p -ad_connect tx_data_out_0_n axi_ad9361_0/tx_data_out_n -ad_connect rx_clk_in_1_p axi_ad9361_1/rx_clk_in_p -ad_connect rx_clk_in_1_n axi_ad9361_1/rx_clk_in_n -ad_connect rx_frame_in_1_p axi_ad9361_1/rx_frame_in_p -ad_connect rx_frame_in_1_n axi_ad9361_1/rx_frame_in_n -ad_connect rx_data_in_1_p axi_ad9361_1/rx_data_in_p -ad_connect rx_data_in_1_n axi_ad9361_1/rx_data_in_n -ad_connect tx_clk_out_1_p axi_ad9361_1/tx_clk_out_p -ad_connect tx_clk_out_1_n axi_ad9361_1/tx_clk_out_n -ad_connect tx_frame_out_1_p axi_ad9361_1/tx_frame_out_p -ad_connect tx_frame_out_1_n axi_ad9361_1/tx_frame_out_n -ad_connect tx_data_out_1_p axi_ad9361_1/tx_data_out_p -ad_connect tx_data_out_1_n axi_ad9361_1/tx_data_out_n +ad_connect rx_clk_in_0_p axi_ad9361_0/rx_clk_in_p +ad_connect rx_clk_in_0_n axi_ad9361_0/rx_clk_in_n +ad_connect rx_frame_in_0_p axi_ad9361_0/rx_frame_in_p +ad_connect rx_frame_in_0_n axi_ad9361_0/rx_frame_in_n +ad_connect rx_data_in_0_p axi_ad9361_0/rx_data_in_p +ad_connect rx_data_in_0_n axi_ad9361_0/rx_data_in_n +ad_connect tx_clk_out_0_p axi_ad9361_0/tx_clk_out_p +ad_connect tx_clk_out_0_n axi_ad9361_0/tx_clk_out_n +ad_connect tx_frame_out_0_p axi_ad9361_0/tx_frame_out_p +ad_connect tx_frame_out_0_n axi_ad9361_0/tx_frame_out_n +ad_connect tx_data_out_0_p axi_ad9361_0/tx_data_out_p +ad_connect tx_data_out_0_n axi_ad9361_0/tx_data_out_n +ad_connect rx_clk_in_1_p axi_ad9361_1/rx_clk_in_p +ad_connect rx_clk_in_1_n axi_ad9361_1/rx_clk_in_n +ad_connect rx_frame_in_1_p axi_ad9361_1/rx_frame_in_p +ad_connect rx_frame_in_1_n axi_ad9361_1/rx_frame_in_n +ad_connect rx_data_in_1_p axi_ad9361_1/rx_data_in_p +ad_connect rx_data_in_1_n axi_ad9361_1/rx_data_in_n +ad_connect tx_clk_out_1_p axi_ad9361_1/tx_clk_out_p +ad_connect tx_clk_out_1_n axi_ad9361_1/tx_clk_out_n +ad_connect tx_frame_out_1_p axi_ad9361_1/tx_frame_out_p +ad_connect tx_frame_out_1_n axi_ad9361_1/tx_frame_out_n +ad_connect tx_data_out_1_p axi_ad9361_1/tx_data_out_p +ad_connect tx_data_out_1_n axi_ad9361_1/tx_data_out_n +ad_connect concat_logic/In0 axi_ad9361_0/adc_r1_mode +ad_connect concat_logic/In1 axi_ad9361_0/dac_r1_mode +ad_connect concat_logic/In2 axi_ad9361_1/adc_r1_mode +ad_connect concat_logic/In3 axi_ad9361_1/dac_r1_mode +ad_connect concat_logic/dout clkdiv_sel_logic/Op1 +ad_connect clkdiv_sel_logic/Res clkdiv/clk_sel - -ad_connect axi_ad9361_0/adc_enable_i0 adc_wfifo/din_enable_0 +ad_connect axi_ad9361_adc_dma/fifo_wr_overflow adc_wfifo/dout_ovf +ad_connect adc_wfifo/din_ovf axi_ad9361_0/adc_dovf +ad_connect axi_ad9361_0/adc_enable_i0 adc_wfifo/din_enable_0 ad_connect axi_ad9361_0/adc_valid_i0 adc_wfifo/din_valid_0 ad_connect axi_ad9361_0/adc_data_i0 adc_wfifo/din_data_0 ad_connect axi_ad9361_0/adc_enable_q0 adc_wfifo/din_enable_1 @@ -165,64 +205,102 @@ ad_connect axi_ad9361_1/adc_valid_i1 adc_wfifo/din_valid_6 ad_connect axi_ad9361_1/adc_data_i1 adc_wfifo/din_data_6 ad_connect axi_ad9361_1/adc_enable_q1 adc_wfifo/din_enable_7 ad_connect axi_ad9361_1/adc_valid_q1 adc_wfifo/din_valid_7 -ad_connect axi_ad9361_1/adc_data_q1 adc_wfifo/din_data_7 +ad_connect axi_ad9361_1/adc_data_q1 adc_wfifo/din_data_7 -ad_connect util_cpack_adc/adc_enable_0 adc_wfifo/dout_enable_0 -ad_connect util_cpack_adc/adc_valid_0 adc_wfifo/dout_valid_0 -ad_connect util_cpack_adc/adc_data_0 adc_wfifo/dout_data_0 -ad_connect util_cpack_adc/adc_enable_1 adc_wfifo/dout_enable_1 -ad_connect util_cpack_adc/adc_valid_1 adc_wfifo/dout_valid_1 -ad_connect util_cpack_adc/adc_data_1 adc_wfifo/dout_data_1 -ad_connect util_cpack_adc/adc_enable_2 adc_wfifo/dout_enable_2 -ad_connect util_cpack_adc/adc_valid_2 adc_wfifo/dout_valid_2 -ad_connect util_cpack_adc/adc_data_2 adc_wfifo/dout_data_2 -ad_connect util_cpack_adc/adc_enable_3 adc_wfifo/dout_enable_3 -ad_connect util_cpack_adc/adc_valid_3 adc_wfifo/dout_valid_3 -ad_connect util_cpack_adc/adc_data_3 adc_wfifo/dout_data_3 -ad_connect util_cpack_adc/adc_enable_4 adc_wfifo/dout_enable_4 -ad_connect util_cpack_adc/adc_valid_4 adc_wfifo/dout_valid_4 -ad_connect util_cpack_adc/adc_data_4 adc_wfifo/dout_data_4 -ad_connect util_cpack_adc/adc_enable_5 adc_wfifo/dout_enable_5 -ad_connect util_cpack_adc/adc_valid_5 adc_wfifo/dout_valid_5 -ad_connect util_cpack_adc/adc_data_5 adc_wfifo/dout_data_5 -ad_connect util_cpack_adc/adc_enable_6 adc_wfifo/dout_enable_6 -ad_connect util_cpack_adc/adc_valid_6 adc_wfifo/dout_valid_6 -ad_connect util_cpack_adc/adc_data_6 adc_wfifo/dout_data_6 -ad_connect util_cpack_adc/adc_enable_7 adc_wfifo/dout_enable_7 -ad_connect util_cpack_adc/adc_valid_7 adc_wfifo/dout_valid_7 -ad_connect util_cpack_adc/adc_data_7 adc_wfifo/dout_data_7 +ad_connect util_cpack_adc/adc_enable_0 adc_wfifo/dout_enable_0 +ad_connect util_cpack_adc/adc_valid_0 adc_wfifo/dout_valid_0 +ad_connect util_cpack_adc/adc_data_0 adc_wfifo/dout_data_0 +ad_connect util_cpack_adc/adc_enable_1 adc_wfifo/dout_enable_1 +ad_connect util_cpack_adc/adc_valid_1 adc_wfifo/dout_valid_1 +ad_connect util_cpack_adc/adc_data_1 adc_wfifo/dout_data_1 +ad_connect util_cpack_adc/adc_enable_2 adc_wfifo/dout_enable_2 +ad_connect util_cpack_adc/adc_valid_2 adc_wfifo/dout_valid_2 +ad_connect util_cpack_adc/adc_data_2 adc_wfifo/dout_data_2 +ad_connect util_cpack_adc/adc_enable_3 adc_wfifo/dout_enable_3 +ad_connect util_cpack_adc/adc_valid_3 adc_wfifo/dout_valid_3 +ad_connect util_cpack_adc/adc_data_3 adc_wfifo/dout_data_3 +ad_connect util_cpack_adc/adc_enable_4 adc_wfifo/dout_enable_4 +ad_connect util_cpack_adc/adc_valid_4 adc_wfifo/dout_valid_4 +ad_connect util_cpack_adc/adc_data_4 adc_wfifo/dout_data_4 +ad_connect util_cpack_adc/adc_enable_5 adc_wfifo/dout_enable_5 +ad_connect util_cpack_adc/adc_valid_5 adc_wfifo/dout_valid_5 +ad_connect util_cpack_adc/adc_data_5 adc_wfifo/dout_data_5 +ad_connect util_cpack_adc/adc_enable_6 adc_wfifo/dout_enable_6 +ad_connect util_cpack_adc/adc_valid_6 adc_wfifo/dout_valid_6 +ad_connect util_cpack_adc/adc_data_6 adc_wfifo/dout_data_6 +ad_connect util_cpack_adc/adc_enable_7 adc_wfifo/dout_enable_7 +ad_connect util_cpack_adc/adc_valid_7 adc_wfifo/dout_valid_7 +ad_connect util_cpack_adc/adc_data_7 adc_wfifo/dout_data_7 ad_connect util_cpack_adc/adc_valid axi_ad9361_adc_dma/fifo_wr_en ad_connect util_cpack_adc/adc_sync axi_ad9361_adc_dma/fifo_wr_sync ad_connect util_cpack_adc/adc_data axi_ad9361_adc_dma/fifo_wr_din -ad_connect axi_ad9361_0/dac_enable_i0 util_upack_dac/dac_enable_0 -ad_connect axi_ad9361_0/dac_valid_i0 util_upack_dac/dac_valid_0 -ad_connect axi_ad9361_0/dac_data_i0 util_upack_dac/dac_data_0 -ad_connect axi_ad9361_0/dac_enable_q0 util_upack_dac/dac_enable_1 -ad_connect axi_ad9361_0/dac_valid_q0 util_upack_dac/dac_valid_1 -ad_connect axi_ad9361_0/dac_data_q0 util_upack_dac/dac_data_1 -ad_connect axi_ad9361_0/dac_enable_i1 util_upack_dac/dac_enable_2 -ad_connect axi_ad9361_0/dac_valid_i1 util_upack_dac/dac_valid_2 -ad_connect axi_ad9361_0/dac_data_i1 util_upack_dac/dac_data_2 -ad_connect axi_ad9361_0/dac_enable_q1 util_upack_dac/dac_enable_3 -ad_connect axi_ad9361_0/dac_valid_q1 util_upack_dac/dac_valid_3 -ad_connect axi_ad9361_0/dac_data_q1 util_upack_dac/dac_data_3 -ad_connect axi_ad9361_1/dac_enable_i0 util_upack_dac/dac_enable_4 -ad_connect axi_ad9361_1/dac_valid_i0 util_upack_dac/dac_valid_4 -ad_connect axi_ad9361_1/dac_data_i0 util_upack_dac/dac_data_4 -ad_connect axi_ad9361_1/dac_enable_q0 util_upack_dac/dac_enable_5 -ad_connect axi_ad9361_1/dac_valid_q0 util_upack_dac/dac_valid_5 -ad_connect axi_ad9361_1/dac_data_q0 util_upack_dac/dac_data_5 -ad_connect axi_ad9361_1/dac_enable_i1 util_upack_dac/dac_enable_6 -ad_connect axi_ad9361_1/dac_valid_i1 util_upack_dac/dac_valid_6 -ad_connect axi_ad9361_1/dac_data_i1 util_upack_dac/dac_data_6 -ad_connect axi_ad9361_1/dac_enable_q1 util_upack_dac/dac_enable_7 -ad_connect axi_ad9361_1/dac_valid_q1 util_upack_dac/dac_valid_7 -ad_connect axi_ad9361_1/dac_data_q1 util_upack_dac/dac_data_7 -ad_connect util_upack_dac/dac_valid axi_ad9361_dac_dma/fifo_rd_en -ad_connect util_upack_dac/dac_data axi_ad9361_dac_dma/fifo_rd_dout -ad_connect axi_ad9361_0/adc_dovf axi_ad9361_adc_dma/fifo_wr_overflow -ad_connect axi_ad9361_0/dac_dunf axi_ad9361_dac_dma/fifo_rd_underflow + +ad_connect dac_fifo/din_enable_0 util_upack_dac/dac_enable_0 +ad_connect dac_fifo/din_valid_0 util_upack_dac/dac_valid_0 +ad_connect dac_fifo/din_data_0 util_upack_dac/dac_data_0 +ad_connect dac_fifo/din_enable_1 util_upack_dac/dac_enable_1 +ad_connect dac_fifo/din_valid_1 util_upack_dac/dac_valid_1 +ad_connect dac_fifo/din_data_1 util_upack_dac/dac_data_1 +ad_connect dac_fifo/din_enable_2 util_upack_dac/dac_enable_2 +ad_connect dac_fifo/din_valid_2 util_upack_dac/dac_valid_2 +ad_connect dac_fifo/din_data_2 util_upack_dac/dac_data_2 +ad_connect dac_fifo/din_enable_3 util_upack_dac/dac_enable_3 +ad_connect dac_fifo/din_valid_3 util_upack_dac/dac_valid_3 +ad_connect dac_fifo/din_data_3 util_upack_dac/dac_data_3 +ad_connect dac_fifo/din_enable_4 util_upack_dac/dac_enable_4 +ad_connect dac_fifo/din_valid_4 util_upack_dac/dac_valid_4 +ad_connect dac_fifo/din_data_4 util_upack_dac/dac_data_4 +ad_connect dac_fifo/din_enable_5 util_upack_dac/dac_enable_5 +ad_connect dac_fifo/din_valid_5 util_upack_dac/dac_valid_5 +ad_connect dac_fifo/din_data_5 util_upack_dac/dac_data_5 +ad_connect dac_fifo/din_enable_6 util_upack_dac/dac_enable_6 +ad_connect dac_fifo/din_valid_6 util_upack_dac/dac_valid_6 +ad_connect dac_fifo/din_data_6 util_upack_dac/dac_data_6 +ad_connect dac_fifo/din_enable_7 util_upack_dac/dac_enable_7 +ad_connect dac_fifo/din_valid_7 util_upack_dac/dac_valid_7 +ad_connect dac_fifo/din_data_7 util_upack_dac/dac_data_7 + +ad_connect util_upack_dac/dac_valid axi_ad9361_dac_dma/fifo_rd_en +ad_connect util_upack_dac/dac_data axi_ad9361_dac_dma/fifo_rd_dout + +ad_connect axi_ad9361_0/dac_enable_i0 dac_fifo/dout_enable_0 +ad_connect axi_ad9361_0/dac_valid_i0 dac_fifo/dout_valid_0 +ad_connect axi_ad9361_0/dac_data_i0 dac_fifo/dout_data_0 +ad_connect axi_ad9361_0/dac_enable_q0 dac_fifo/dout_enable_1 +ad_connect axi_ad9361_0/dac_valid_q0 dac_fifo/dout_valid_1 +ad_connect axi_ad9361_0/dac_data_q0 dac_fifo/dout_data_1 +ad_connect axi_ad9361_0/dac_enable_i1 dac_fifo/dout_enable_2 +ad_connect axi_ad9361_0/dac_valid_i1 dac_fifo/dout_valid_2 +ad_connect axi_ad9361_0/dac_data_i1 dac_fifo/dout_data_2 +ad_connect axi_ad9361_0/dac_enable_q1 dac_fifo/dout_enable_3 +ad_connect axi_ad9361_0/dac_valid_q1 dac_fifo/dout_valid_3 +ad_connect axi_ad9361_0/dac_data_q1 dac_fifo/dout_data_3 +ad_connect axi_ad9361_1/dac_enable_i0 dac_fifo/dout_enable_4 +ad_connect axi_ad9361_1/dac_valid_i0 dac_fifo/dout_valid_4 +ad_connect axi_ad9361_1/dac_data_i0 dac_fifo/dout_data_4 +ad_connect axi_ad9361_1/dac_enable_q0 dac_fifo/dout_enable_5 +ad_connect axi_ad9361_1/dac_valid_q0 dac_fifo/dout_valid_5 +ad_connect axi_ad9361_1/dac_data_q0 dac_fifo/dout_data_5 +ad_connect axi_ad9361_1/dac_enable_i1 dac_fifo/dout_enable_6 +ad_connect axi_ad9361_1/dac_valid_i1 dac_fifo/dout_valid_6 +ad_connect axi_ad9361_1/dac_data_i1 dac_fifo/dout_data_6 +ad_connect axi_ad9361_1/dac_enable_q1 dac_fifo/dout_enable_7 +ad_connect axi_ad9361_1/dac_valid_q1 dac_fifo/dout_valid_7 +ad_connect axi_ad9361_1/dac_data_q1 dac_fifo/dout_data_7 + +ad_connect axi_ad9361_0/dac_dunf dac_fifo/dout_unf +ad_connect axi_ad9361_1/dac_dunf dac_fifo/dout_unf + +ad_connect axi_ad9361_0/up_enable up_enable_0 +ad_connect axi_ad9361_0/up_txnrx up_txnrx_0 +ad_connect axi_ad9361_1/up_enable up_enable_1 +ad_connect axi_ad9361_1/up_txnrx up_txnrx_1 + +ad_connect axi_ad9361_0/enable enable_0 +ad_connect axi_ad9361_0/txnrx txnrx_0 +ad_connect axi_ad9361_1/enable enable_1 +ad_connect axi_ad9361_1/txnrx txnrx_1 # address map diff --git a/projects/fmcomms5/zc702/Makefile b/projects/fmcomms5/zc702/Makefile index bba74f74a..86ae994b5 100644 --- a/projects/fmcomms5/zc702/Makefile +++ b/projects/fmcomms5/zc702/Makefile @@ -15,13 +15,15 @@ M_DEPS += ../../scripts/adi_env.tcl M_DEPS += ../../scripts/adi_board.tcl M_DEPS += ../../common/zc702/zc702_system_constr.xdc M_DEPS += ../../common/zc702/zc702_system_bd.tcl -M_DEPS += ../../../library/common/ad_iobuf.v +M_DEPS += ../../../library/xilinx/common/ad_iobuf.v M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr +M_DEPS += ../../../library/util_clkdiv/util_clkdiv.xpr M_DEPS += ../../../library/util_cpack/util_cpack.xpr +M_DEPS += ../../../library/util_rfifo/util_rfifo.xpr M_DEPS += ../../../library/util_upack/util_upack.xpr M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr @@ -39,6 +41,7 @@ M_FLIST += *.sdk M_FLIST += *.hw M_FLIST += *.sim M_FLIST += .Xil +M_FLIST += *.ip_user_files @@ -56,13 +59,15 @@ clean-all:clean make -C ../../../library/axi_dmac clean make -C ../../../library/axi_hdmi_tx clean make -C ../../../library/axi_spdif_tx clean + make -C ../../../library/util_clkdiv clean make -C ../../../library/util_cpack clean + make -C ../../../library/util_rfifo clean make -C ../../../library/util_upack clean make -C ../../../library/util_wfifo clean fmcomms5_zc702.sdk/system_top.hdf: $(M_DEPS) - rm -rf $(M_FLIST) + -rm -rf $(M_FLIST) $(M_VIVADO) system_project.tcl >> fmcomms5_zc702_vivado.log 2>&1 @@ -72,7 +77,9 @@ lib: make -C ../../../library/axi_dmac make -C ../../../library/axi_hdmi_tx make -C ../../../library/axi_spdif_tx + make -C ../../../library/util_clkdiv make -C ../../../library/util_cpack + make -C ../../../library/util_rfifo make -C ../../../library/util_upack make -C ../../../library/util_wfifo diff --git a/projects/fmcomms5/zc702/system_constr.xdc b/projects/fmcomms5/zc702/system_constr.xdc index 243ead1a6..914a94303 100755 --- a/projects/fmcomms5/zc702/system_constr.xdc +++ b/projects/fmcomms5/zc702/system_constr.xdc @@ -54,8 +54,8 @@ set_property -dict {PACKAGE_PIN A22 IOSTANDARD LVCMOS25} [get_ports gpio_ct set_property -dict {PACKAGE_PIN C15 IOSTANDARD LVCMOS25} [get_ports gpio_en_agc_0] ; ## G27 FMC1_LPC_LA25_P set_property -dict {PACKAGE_PIN D20 IOSTANDARD LVCMOS25} [get_ports mcs_sync] ; ## C22 FMC1_LPC_LA18_CC_P set_property -dict {PACKAGE_PIN C20 IOSTANDARD LVCMOS25} [get_ports gpio_resetb_0] ; ## C23 FMC1_LPC_LA18_CC_N -set_property -dict {PACKAGE_PIN N15 IOSTANDARD LVCMOS25} [get_ports gpio_enable_0] ; ## G18 FMC1_LPC_LA16_P -set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS25} [get_ports gpio_txnrx_0] ; ## G19 FMC1_LPC_LA16_N +set_property -dict {PACKAGE_PIN N15 IOSTANDARD LVCMOS25} [get_ports enable_0] ; ## G18 FMC1_LPC_LA16_P +set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS25} [get_ports txnrx_0] ; ## G19 FMC1_LPC_LA16_N set_property -dict {PACKAGE_PIN C17 IOSTANDARD LVCMOS25} [get_ports gpio_debug_1_0] ; ## C26 FMC1_LPC_LA27_P set_property -dict {PACKAGE_PIN C18 IOSTANDARD LVCMOS25} [get_ports gpio_debug_2_0] ; ## C27 FMC1_LPC_LA27_N set_property -dict {PACKAGE_PIN F18 IOSTANDARD LVCMOS25} [get_ports gpio_calsw_1_0] ; ## D26 FMC1_LPC_LA26_P @@ -121,8 +121,8 @@ set_property -dict {PACKAGE_PIN U6 IOSTANDARD LVCMOS25} [get_ports gpio_ct set_property -dict {PACKAGE_PIN U5 IOSTANDARD LVCMOS25} [get_ports gpio_ctl_1[3]] ; ## H29 FMC2_LPC_LA24_N set_property -dict {PACKAGE_PIN AA12 IOSTANDARD LVCMOS25} [get_ports gpio_en_agc_1] ; ## G27 FMC2_LPC_LA25_P set_property -dict {PACKAGE_PIN AA11 IOSTANDARD LVCMOS25} [get_ports gpio_resetb_1] ; ## G30 FMC2_LPC_LA29_P -set_property -dict {PACKAGE_PIN AB14 IOSTANDARD LVCMOS25} [get_ports gpio_enable_1] ; ## G18 FMC2_LPC_LA16_P -set_property -dict {PACKAGE_PIN AB15 IOSTANDARD LVCMOS25} [get_ports gpio_txnrx_1] ; ## G19 FMC2_LPC_LA16_N +set_property -dict {PACKAGE_PIN AB14 IOSTANDARD LVCMOS25} [get_ports enable_1] ; ## G18 FMC2_LPC_LA16_P +set_property -dict {PACKAGE_PIN AB15 IOSTANDARD LVCMOS25} [get_ports txnrx_1] ; ## G19 FMC2_LPC_LA16_N set_property -dict {PACKAGE_PIN AB2 IOSTANDARD LVCMOS25} [get_ports gpio_debug_3_1] ; ## C26 FMC2_LPC_LA27_P set_property -dict {PACKAGE_PIN AB1 IOSTANDARD LVCMOS25} [get_ports gpio_debug_4_1] ; ## C27 FMC2_LPC_LA27_N set_property -dict {PACKAGE_PIN U12 IOSTANDARD LVCMOS25} [get_ports gpio_calsw_3_1] ; ## D26 FMC2_LPC_LA26_P diff --git a/projects/fmcomms5/zc702/system_project.tcl b/projects/fmcomms5/zc702/system_project.tcl index f56d13e91..6f65a412b 100644 --- a/projects/fmcomms5/zc702/system_project.tcl +++ b/projects/fmcomms5/zc702/system_project.tcl @@ -7,7 +7,7 @@ adi_project_create fmcomms5_zc702 adi_project_files fmcomms5_zc702 [list \ "system_top.v" \ "system_constr.xdc"\ - "$ad_hdl_dir/library/common/ad_iobuf.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \ "$ad_hdl_dir/projects/common/zc702/zc702_system_constr.xdc" ] adi_project_run fmcomms5_zc702 diff --git a/projects/fmcomms5/zc702/system_top.v b/projects/fmcomms5/zc702/system_top.v index b65ee8c61..5be51a548 100644 --- a/projects/fmcomms5/zc702/system_top.v +++ b/projects/fmcomms5/zc702/system_top.v @@ -94,8 +94,8 @@ module system_top ( gpio_en_agc_0, mcs_sync, gpio_resetb_0, - gpio_enable_0, - gpio_txnrx_0, + enable_0, + txnrx_0, gpio_debug_1_0, gpio_debug_2_0, gpio_calsw_1_0, @@ -119,8 +119,8 @@ module system_top ( gpio_ctl_1, gpio_en_agc_1, gpio_resetb_1, - gpio_enable_1, - gpio_txnrx_1, + enable_1, + txnrx_1, gpio_debug_3_1, gpio_debug_4_1, gpio_calsw_3_1, @@ -189,8 +189,8 @@ module system_top ( inout gpio_en_agc_0; output mcs_sync; inout gpio_resetb_0; - inout gpio_enable_0; - inout gpio_txnrx_0; + output enable_0; + output txnrx_0; inout gpio_debug_1_0; inout gpio_debug_2_0; inout gpio_calsw_1_0; @@ -214,8 +214,8 @@ module system_top ( inout [ 3:0] gpio_ctl_1; inout gpio_en_agc_1; inout gpio_resetb_1; - inout gpio_enable_1; - inout gpio_txnrx_1; + output enable_1; + output txnrx_1; inout gpio_debug_3_1; inout gpio_debug_4_1; inout gpio_calsw_3_1; @@ -254,6 +254,10 @@ module system_top ( wire spi1_clk; wire spi1_mosi; wire spi1_miso; + wire txnrx_0; + wire enable_0; + wire txnrx_1; + wire enable_1; // multi-chip synchronization @@ -404,7 +408,15 @@ module system_top ( .tx_frame_out_0_n (tx_frame_out_0_n), .tx_frame_out_0_p (tx_frame_out_0_p), .tx_frame_out_1_n (tx_frame_out_1_n), - .tx_frame_out_1_p (tx_frame_out_1_p)); + .tx_frame_out_1_p (tx_frame_out_1_p), + .txnrx_0 (txnrx_0), + .enable_0 (enable_0), + .up_enable_0 (gpio_enable_0), + .up_txnrx_0 (gpio_txnrx_0), + .txnrx_1 (txnrx_1), + .enable_1 (enable_1), + .up_enable_1 (gpio_enable_1), + .up_txnrx_1 (gpio_txnrx_1)); endmodule diff --git a/projects/fmcomms5/zc706/Makefile b/projects/fmcomms5/zc706/Makefile index 5aee574f5..d58052759 100644 --- a/projects/fmcomms5/zc706/Makefile +++ b/projects/fmcomms5/zc706/Makefile @@ -15,13 +15,15 @@ M_DEPS += ../../scripts/adi_env.tcl M_DEPS += ../../scripts/adi_board.tcl M_DEPS += ../../common/zc706/zc706_system_constr.xdc M_DEPS += ../../common/zc706/zc706_system_bd.tcl -M_DEPS += ../../../library/common/ad_iobuf.v +M_DEPS += ../../../library/xilinx/common/ad_iobuf.v M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr +M_DEPS += ../../../library/util_clkdiv/util_clkdiv.xpr M_DEPS += ../../../library/util_cpack/util_cpack.xpr +M_DEPS += ../../../library/util_rfifo/util_rfifo.xpr M_DEPS += ../../../library/util_upack/util_upack.xpr M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr @@ -39,6 +41,7 @@ M_FLIST += *.sdk M_FLIST += *.hw M_FLIST += *.sim M_FLIST += .Xil +M_FLIST += *.ip_user_files @@ -56,13 +59,15 @@ clean-all:clean make -C ../../../library/axi_dmac clean make -C ../../../library/axi_hdmi_tx clean make -C ../../../library/axi_spdif_tx clean + make -C ../../../library/util_clkdiv clean make -C ../../../library/util_cpack clean + make -C ../../../library/util_rfifo clean make -C ../../../library/util_upack clean make -C ../../../library/util_wfifo clean fmcomms5_zc706.sdk/system_top.hdf: $(M_DEPS) - rm -rf $(M_FLIST) + -rm -rf $(M_FLIST) $(M_VIVADO) system_project.tcl >> fmcomms5_zc706_vivado.log 2>&1 @@ -72,7 +77,9 @@ lib: make -C ../../../library/axi_dmac make -C ../../../library/axi_hdmi_tx make -C ../../../library/axi_spdif_tx + make -C ../../../library/util_clkdiv make -C ../../../library/util_cpack + make -C ../../../library/util_rfifo make -C ../../../library/util_upack make -C ../../../library/util_wfifo diff --git a/projects/fmcomms5/zc706/system_constr.xdc b/projects/fmcomms5/zc706/system_constr.xdc index 1a6fc5f46..6dd3aa01e 100644 --- a/projects/fmcomms5/zc706/system_constr.xdc +++ b/projects/fmcomms5/zc706/system_constr.xdc @@ -54,8 +54,8 @@ set_property -dict {PACKAGE_PIN U30 IOSTANDARD LVCMOS25} [get_ports gpio_ct set_property -dict {PACKAGE_PIN T29 IOSTANDARD LVCMOS25} [get_ports gpio_en_agc_0] ; ## G27 FMC_HPC_LA25_P set_property -dict {PACKAGE_PIN W25 IOSTANDARD LVCMOS25} [get_ports mcs_sync] ; ## C22 FMC_HPC_LA18_CC_P set_property -dict {PACKAGE_PIN W26 IOSTANDARD LVCMOS25} [get_ports gpio_resetb_0] ; ## C23 FMC_HPC_LA18_CC_N -set_property -dict {PACKAGE_PIN AA24 IOSTANDARD LVCMOS25} [get_ports gpio_enable_0] ; ## G18 FMC_HPC_LA16_P -set_property -dict {PACKAGE_PIN AB24 IOSTANDARD LVCMOS25} [get_ports gpio_txnrx_0] ; ## G19 FMC_HPC_LA16_N +set_property -dict {PACKAGE_PIN AA24 IOSTANDARD LVCMOS25} [get_ports enable_0] ; ## G18 FMC_HPC_LA16_P +set_property -dict {PACKAGE_PIN AB24 IOSTANDARD LVCMOS25} [get_ports txnrx_0] ; ## G19 FMC_HPC_LA16_N set_property -dict {PACKAGE_PIN V28 IOSTANDARD LVCMOS25} [get_ports gpio_debug_1_0] ; ## C26 FMC_HPC_LA27_P set_property -dict {PACKAGE_PIN V29 IOSTANDARD LVCMOS25} [get_ports gpio_debug_2_0] ; ## C27 FMC_HPC_LA27_N set_property -dict {PACKAGE_PIN R28 IOSTANDARD LVCMOS25} [get_ports gpio_calsw_1_0] ; ## D26 FMC_HPC_LA26_P @@ -121,8 +121,8 @@ set_property -dict {PACKAGE_PIN AF30 IOSTANDARD LVCMOS25} [get_ports gpio_ct set_property -dict {PACKAGE_PIN AG30 IOSTANDARD LVCMOS25} [get_ports gpio_ctl_1[3]] ; ## H29 FMC_LPC_LA24_N set_property -dict {PACKAGE_PIN AF29 IOSTANDARD LVCMOS25} [get_ports gpio_en_agc_1] ; ## G27 FMC_LPC_LA25_P set_property -dict {PACKAGE_PIN AE25 IOSTANDARD LVCMOS25} [get_ports gpio_resetb_1] ; ## G30 FMC_LPC_29_P -set_property -dict {PACKAGE_PIN AE18 IOSTANDARD LVCMOS25} [get_ports gpio_enable_1] ; ## G18 FMC_LPC_LA16_P -set_property -dict {PACKAGE_PIN AE17 IOSTANDARD LVCMOS25} [get_ports gpio_txnrx_1] ; ## G19 FMC_LPC_LA16_N +set_property -dict {PACKAGE_PIN AE18 IOSTANDARD LVCMOS25} [get_ports enable_1] ; ## G18 FMC_LPC_LA16_P +set_property -dict {PACKAGE_PIN AE17 IOSTANDARD LVCMOS25} [get_ports txnrx_1] ; ## G19 FMC_LPC_LA16_N set_property -dict {PACKAGE_PIN AJ28 IOSTANDARD LVCMOS25} [get_ports gpio_debug_3_1] ; ## C26 FMC_LPC_LA27_P set_property -dict {PACKAGE_PIN AJ29 IOSTANDARD LVCMOS25} [get_ports gpio_debug_4_1] ; ## C27 FMC_LPC_LA27_N set_property -dict {PACKAGE_PIN AJ30 IOSTANDARD LVCMOS25} [get_ports gpio_calsw_3_1] ; ## D26 FMC_LPC_LA26_P diff --git a/projects/fmcomms5/zc706/system_project.tcl b/projects/fmcomms5/zc706/system_project.tcl index a791c0266..169ab7abb 100644 --- a/projects/fmcomms5/zc706/system_project.tcl +++ b/projects/fmcomms5/zc706/system_project.tcl @@ -9,7 +9,7 @@ adi_project_create fmcomms5_zc706 adi_project_files fmcomms5_zc706 [list \ "system_top.v" \ "system_constr.xdc"\ - "$ad_hdl_dir/library/common/ad_iobuf.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \ "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ] adi_project_run fmcomms5_zc706 diff --git a/projects/fmcomms5/zc706/system_top.v b/projects/fmcomms5/zc706/system_top.v index d6766bad1..a708788d5 100644 --- a/projects/fmcomms5/zc706/system_top.v +++ b/projects/fmcomms5/zc706/system_top.v @@ -94,8 +94,8 @@ module system_top ( gpio_en_agc_0, mcs_sync, gpio_resetb_0, - gpio_enable_0, - gpio_txnrx_0, + enable_0, + txnrx_0, gpio_debug_1_0, gpio_debug_2_0, gpio_calsw_1_0, @@ -119,8 +119,8 @@ module system_top ( gpio_ctl_1, gpio_en_agc_1, gpio_resetb_1, - gpio_enable_1, - gpio_txnrx_1, + enable_1, + txnrx_1, gpio_debug_3_1, gpio_debug_4_1, gpio_calsw_3_1, @@ -189,8 +189,8 @@ module system_top ( inout gpio_en_agc_0; output mcs_sync; inout gpio_resetb_0; - inout gpio_enable_0; - inout gpio_txnrx_0; + output enable_0; + output txnrx_0; inout gpio_debug_1_0; inout gpio_debug_2_0; inout gpio_calsw_1_0; @@ -214,8 +214,8 @@ module system_top ( inout [ 3:0] gpio_ctl_1; inout gpio_en_agc_1; inout gpio_resetb_1; - inout gpio_enable_1; - inout gpio_txnrx_1; + output enable_1; + output txnrx_1; inout gpio_debug_3_1; inout gpio_debug_4_1; inout gpio_calsw_3_1; @@ -255,6 +255,10 @@ module system_top ( wire spi1_clk; wire spi1_mosi; wire spi1_miso; + wire txnrx_0; + wire enable_0; + wire txnrx_1; + wire enable_1; // multi-chip synchronization @@ -406,7 +410,15 @@ module system_top ( .tx_frame_out_0_n (tx_frame_out_0_n), .tx_frame_out_0_p (tx_frame_out_0_p), .tx_frame_out_1_n (tx_frame_out_1_n), - .tx_frame_out_1_p (tx_frame_out_1_p)); + .tx_frame_out_1_p (tx_frame_out_1_p), + .txnrx_0 (txnrx_0), + .enable_0 (enable_0), + .up_enable_0 (gpio_enable_0), + .up_txnrx_0 (gpio_txnrx_0), + .txnrx_1 (txnrx_1), + .enable_1 (enable_1), + .up_enable_1 (gpio_enable_1), + .up_txnrx_1 (gpio_txnrx_1)); endmodule diff --git a/projects/fmcomms1/ac701/Makefile b/projects/fmcomms5/zcu102/Makefile similarity index 67% rename from projects/fmcomms1/ac701/Makefile rename to projects/fmcomms5/zcu102/Makefile index 9c8a6771c..f5d102359 100644 --- a/projects/fmcomms1/ac701/Makefile +++ b/projects/fmcomms5/zcu102/Makefile @@ -9,18 +9,18 @@ M_DEPS += system_top.v M_DEPS += system_project.tcl M_DEPS += system_constr.xdc M_DEPS += system_bd.tcl -M_DEPS += ../common/fmcomms1_bd.tcl +M_DEPS += ../common/fmcomms5_bd.tcl M_DEPS += ../../scripts/adi_project.tcl M_DEPS += ../../scripts/adi_env.tcl M_DEPS += ../../scripts/adi_board.tcl -M_DEPS += ../../common/ac701/ac701_system_mig.prj -M_DEPS += ../../common/ac701/ac701_system_constr.xdc -M_DEPS += ../../common/ac701/ac701_system_bd.tcl -M_DEPS += ../../../library/common/ad_iobuf.v -M_DEPS += ../../../library/axi_ad9122/axi_ad9122.xpr -M_DEPS += ../../../library/axi_ad9643/axi_ad9643.xpr +M_DEPS += ../../common/zcu102/zcu102_system_constr.xdc +M_DEPS += ../../common/zcu102/zcu102_system_bd.tcl +M_DEPS += ../../../library/xilinx/common/ad_iobuf.v +M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr +M_DEPS += ../../../library/util_clkdiv/util_clkdiv.xpr M_DEPS += ../../../library/util_cpack/util_cpack.xpr +M_DEPS += ../../../library/util_rfifo/util_rfifo.xpr M_DEPS += ../../../library/util_upack/util_upack.xpr M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr @@ -38,11 +38,12 @@ M_FLIST += *.sdk M_FLIST += *.hw M_FLIST += *.sim M_FLIST += .Xil +M_FLIST += *.ip_user_files .PHONY: all lib clean clean-all -all: lib fmcomms1_ac701.sdk/system_top.hdf +all: lib fmcomms5_zcu102.sdk/system_top.hdf clean: @@ -50,24 +51,26 @@ clean: clean-all:clean - make -C ../../../library/axi_ad9122 clean - make -C ../../../library/axi_ad9643 clean + make -C ../../../library/axi_ad9361 clean make -C ../../../library/axi_dmac clean + make -C ../../../library/util_clkdiv clean make -C ../../../library/util_cpack clean + make -C ../../../library/util_rfifo clean make -C ../../../library/util_upack clean make -C ../../../library/util_wfifo clean -fmcomms1_ac701.sdk/system_top.hdf: $(M_DEPS) - rm -rf $(M_FLIST) - $(M_VIVADO) system_project.tcl >> fmcomms1_ac701_vivado.log 2>&1 +fmcomms5_zcu102.sdk/system_top.hdf: $(M_DEPS) + -rm -rf $(M_FLIST) + $(M_VIVADO) system_project.tcl >> fmcomms5_zcu102_vivado.log 2>&1 lib: - make -C ../../../library/axi_ad9122 - make -C ../../../library/axi_ad9643 + make -C ../../../library/axi_ad9361 make -C ../../../library/axi_dmac + make -C ../../../library/util_clkdiv make -C ../../../library/util_cpack + make -C ../../../library/util_rfifo make -C ../../../library/util_upack make -C ../../../library/util_wfifo diff --git a/projects/fmcomms5/zcu102/system_bd.tcl b/projects/fmcomms5/zcu102/system_bd.tcl new file mode 100644 index 000000000..1d61e5e87 --- /dev/null +++ b/projects/fmcomms5/zcu102/system_bd.tcl @@ -0,0 +1,14 @@ + +source $ad_hdl_dir/projects/common/zcu102/zcu102_system_bd.tcl + +set_property CONFIG.PSU__FPGA_PL2_ENABLE {1} $sys_ps8 +set_property CONFIG.PSU__CRL_APB__PL2_REF_CTRL__FREQMHZ {200} $sys_ps8 +set_property CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR0 {3} $sys_ps8 +set_property CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR1 {2} $sys_ps8 +ad_connect sys_dma_clk sys_ps8/pl_clk2 +source ../common/fmcomms5_bd.tcl + +set_property CONFIG.DEVICE_TYPE 2 [get_bd_cells axi_ad9361_0] +set_property CONFIG.DEVICE_TYPE 2 [get_bd_cells axi_ad9361_1] + +set_property -dict [list CONFIG.SIM_DEVICE {ULTRASCALE}] $clkdiv diff --git a/projects/fmcomms5/zcu102/system_constr.xdc b/projects/fmcomms5/zcu102/system_constr.xdc new file mode 100644 index 000000000..137c1a62d --- /dev/null +++ b/projects/fmcomms5/zcu102/system_constr.xdc @@ -0,0 +1,135 @@ + +# constraints + +# ad9361 master + +set_property -dict {PACKAGE_PIN P11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports ref_clk_p] ; ## D20 FMC_HPC0_LA17_CC_P +set_property -dict {PACKAGE_PIN N11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports ref_clk_n] ; ## D21 FMC_HPC0_LA17_CC_N + +set_property -dict {PACKAGE_PIN Y4 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_clk_in_0_p] ; ## G06 FMC_HPC0_LA00_CC_P +set_property -dict {PACKAGE_PIN Y3 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_clk_in_0_n] ; ## G07 FMC_HPC0_LA00_CC_N +set_property -dict {PACKAGE_PIN W2 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_frame_in_0_p] ; ## D08 FMC_HPC0_LA01_CC_P +set_property -dict {PACKAGE_PIN W1 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_frame_in_0_n] ; ## D09 FMC_HPC0_LA01_CC_N +set_property -dict {PACKAGE_PIN V2 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_0_p[0]] ; ## H07 FMC_HPC0_LA02_P +set_property -dict {PACKAGE_PIN V1 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_0_n[0]] ; ## H08 FMC_HPC0_LA02_N +set_property -dict {PACKAGE_PIN Y2 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_0_p[1]] ; ## G09 FMC_HPC0_LA03_P +set_property -dict {PACKAGE_PIN Y1 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_0_n[1]] ; ## G10 FMC_HPC0_LA03_N +set_property -dict {PACKAGE_PIN AA2 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_0_p[2]] ; ## H10 FMC_HPC0_LA04_P +set_property -dict {PACKAGE_PIN AA1 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_0_n[2]] ; ## H11 FMC_HPC0_LA04_N +set_property -dict {PACKAGE_PIN AB3 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_0_p[3]] ; ## D11 FMC_HPC0_LA05_P +set_property -dict {PACKAGE_PIN AC3 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_0_n[3]] ; ## D12 FMC_HPC0_LA05_N +set_property -dict {PACKAGE_PIN AC2 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_0_p[4]] ; ## C10 FMC_HPC0_LA06_P +set_property -dict {PACKAGE_PIN AC1 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_0_n[4]] ; ## C11 FMC_HPC0_LA06_N +set_property -dict {PACKAGE_PIN U5 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_0_p[5]] ; ## H13 FMC_HPC0_LA07_P +set_property -dict {PACKAGE_PIN U4 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_0_n[5]] ; ## H14 FMC_HPC0_LA07_N +set_property -dict {PACKAGE_PIN V4 IOSTANDARD LVDS} [get_ports tx_clk_out_0_p] ; ## G12 FMC_HPC0_LA08_P +set_property -dict {PACKAGE_PIN V3 IOSTANDARD LVDS} [get_ports tx_clk_out_0_n] ; ## G13 FMC_HPC0_LA08_N +set_property -dict {PACKAGE_PIN AB4 IOSTANDARD LVDS} [get_ports tx_frame_out_0_p] ; ## D14 FMC_HPC0_LA09_P +set_property -dict {PACKAGE_PIN AC4 IOSTANDARD LVDS} [get_ports tx_frame_out_0_n] ; ## D15 FMC_HPC0_LA09_N +set_property -dict {PACKAGE_PIN W5 IOSTANDARD LVDS} [get_ports tx_data_out_0_p[0]] ; ## C14 FMC_HPC0_LA10_P +set_property -dict {PACKAGE_PIN W4 IOSTANDARD LVDS} [get_ports tx_data_out_0_n[0]] ; ## C15 FMC_HPC0_LA10_N +set_property -dict {PACKAGE_PIN AB6 IOSTANDARD LVDS} [get_ports tx_data_out_0_p[1]] ; ## H16 FMC_HPC0_LA11_P +set_property -dict {PACKAGE_PIN AB5 IOSTANDARD LVDS} [get_ports tx_data_out_0_n[1]] ; ## H17 FMC_HPC0_LA11_N +set_property -dict {PACKAGE_PIN W7 IOSTANDARD LVDS} [get_ports tx_data_out_0_p[2]] ; ## G15 FMC_HPC0_LA12_P +set_property -dict {PACKAGE_PIN W6 IOSTANDARD LVDS} [get_ports tx_data_out_0_n[2]] ; ## G16 FMC_HPC0_LA12_N +set_property -dict {PACKAGE_PIN AB8 IOSTANDARD LVDS} [get_ports tx_data_out_0_p[3]] ; ## D17 FMC_HPC0_LA13_P +set_property -dict {PACKAGE_PIN AC8 IOSTANDARD LVDS} [get_ports tx_data_out_0_n[3]] ; ## D18 FMC_HPC0_LA13_N +set_property -dict {PACKAGE_PIN AC7 IOSTANDARD LVDS} [get_ports tx_data_out_0_p[4]] ; ## C18 FMC_HPC0_LA14_P +set_property -dict {PACKAGE_PIN AC6 IOSTANDARD LVDS} [get_ports tx_data_out_0_n[4]] ; ## C19 FMC_HPC0_LA14_N +set_property -dict {PACKAGE_PIN Y10 IOSTANDARD LVDS} [get_ports tx_data_out_0_p[5]] ; ## H19 FMC_HPC0_LA15_P +set_property -dict {PACKAGE_PIN Y9 IOSTANDARD LVDS} [get_ports tx_data_out_0_n[5]] ; ## H20 FMC_HPC0_LA15_N + +set_property -dict {PACKAGE_PIN L13 IOSTANDARD LVCMOS18} [get_ports gpio_status_0[0]] ; ## H22 FMC_HPC0_LA19_P +set_property -dict {PACKAGE_PIN K13 IOSTANDARD LVCMOS18} [get_ports gpio_status_0[1]] ; ## H23 FMC_HPC0_LA19_N +set_property -dict {PACKAGE_PIN N13 IOSTANDARD LVCMOS18} [get_ports gpio_status_0[2]] ; ## G21 FMC_HPC0_LA20_P +set_property -dict {PACKAGE_PIN M13 IOSTANDARD LVCMOS18} [get_ports gpio_status_0[3]] ; ## G22 FMC_HPC0_LA20_N +set_property -dict {PACKAGE_PIN P12 IOSTANDARD LVCMOS18} [get_ports gpio_status_0[4]] ; ## H25 FMC_HPC0_LA21_P +set_property -dict {PACKAGE_PIN N12 IOSTANDARD LVCMOS18} [get_ports gpio_status_0[5]] ; ## H26 FMC_HPC0_LA21_N +set_property -dict {PACKAGE_PIN M15 IOSTANDARD LVCMOS18} [get_ports gpio_status_0[6]] ; ## G24 FMC_HPC0_LA22_P +set_property -dict {PACKAGE_PIN M14 IOSTANDARD LVCMOS18} [get_ports gpio_status_0[7]] ; ## G25 FMC_HPC0_LA22_N +set_property -dict {PACKAGE_PIN L16 IOSTANDARD LVCMOS18} [get_ports gpio_ctl_0[0]] ; ## D23 FMC_HPC0_LA23_P +set_property -dict {PACKAGE_PIN K16 IOSTANDARD LVCMOS18} [get_ports gpio_ctl_0[1]] ; ## D24 FMC_HPC0_LA23_N +set_property -dict {PACKAGE_PIN L12 IOSTANDARD LVCMOS18} [get_ports gpio_ctl_0[2]] ; ## H28 FMC_HPC0_LA24_P +set_property -dict {PACKAGE_PIN K12 IOSTANDARD LVCMOS18} [get_ports gpio_ctl_0[3]] ; ## H29 FMC_HPC0_LA24_N +set_property -dict {PACKAGE_PIN M11 IOSTANDARD LVCMOS18} [get_ports gpio_en_agc_0] ; ## G27 FMC_HPC0_LA25_P +set_property -dict {PACKAGE_PIN L15 IOSTANDARD LVCMOS18} [get_ports mcs_sync] ; ## C22 FMC_HPC0_LA18_CC_P +set_property -dict {PACKAGE_PIN K15 IOSTANDARD LVCMOS18} [get_ports gpio_resetb_0] ; ## C23 FMC_HPC0_LA18_CC_N +set_property -dict {PACKAGE_PIN Y12 IOSTANDARD LVCMOS18} [get_ports enable_0] ; ## G18 FMC_HPC0_LA16_P +set_property -dict {PACKAGE_PIN AA12 IOSTANDARD LVCMOS18} [get_ports txnrx_0] ; ## G19 FMC_HPC0_LA16_N +set_property -dict {PACKAGE_PIN M10 IOSTANDARD LVCMOS18} [get_ports gpio_debug_1_0] ; ## C26 FMC_HPC0_LA27_P +set_property -dict {PACKAGE_PIN L10 IOSTANDARD LVCMOS18} [get_ports gpio_debug_2_0] ; ## C27 FMC_HPC0_LA27_N +set_property -dict {PACKAGE_PIN N9 IOSTANDARD LVCMOS18} [get_ports gpio_calsw_1_0] ; ## D26 FMC_HPC0_LA26_P +set_property -dict {PACKAGE_PIN N8 IOSTANDARD LVCMOS18} [get_ports gpio_calsw_2_0] ; ## D27 FMC_HPC0_LA26_N +set_property -dict {PACKAGE_PIN T7 IOSTANDARD LVCMOS18} [get_ports gpio_ad5355_rfen] ; ## H31 FMC_HPC0_LA28_P +set_property -dict {PACKAGE_PIN T6 IOSTANDARD LVCMOS18} [get_ports gpio_ad5355_lock] ; ## H37 FMC_HPC0_LA32_P + +# spi + +set_property -dict {PACKAGE_PIN U9 IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports spi_ad9361_0] ; ## G30 FMC_HPC0_LA29_P +set_property -dict {PACKAGE_PIN U8 IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports spi_ad9361_1] ; ## G31 FMC_HPC0_LA29_N +set_property -dict {PACKAGE_PIN V6 IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports spi_ad5355] ; ## H34 FMC_HPC0_LA30_P +set_property -dict {PACKAGE_PIN U6 IOSTANDARD LVCMOS18} [get_ports spi_clk] ; ## H35 FMC_HPC0_LA30_N +set_property -dict {PACKAGE_PIN V8 IOSTANDARD LVCMOS18} [get_ports spi_mosi] ; ## G33 FMC_HPC0_LA31_P +set_property -dict {PACKAGE_PIN V7 IOSTANDARD LVCMOS18} [get_ports spi_miso] ; ## G34 FMC_HPC0_LA31_N + +# ad9361 slave + +set_property -dict {PACKAGE_PIN AE5 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_clk_in_1_p] ; ## G06 FMC_HPC1_LA00_CC_P +set_property -dict {PACKAGE_PIN AF5 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_clk_in_1_n] ; ## G07 FMC_HPC1_LA00_CC_N +set_property -dict {PACKAGE_PIN AE2 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_frame_in_1_p] ; ## D08 FMC_HPC1_LA01_CC_P +set_property -dict {PACKAGE_PIN AE1 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_frame_in_1_n] ; ## D09 FMC_HPC1_LA01_CC_N +set_property -dict {PACKAGE_PIN AD2 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_1_p[0]] ; ## H07 FMC_HPC1_LA02_P +set_property -dict {PACKAGE_PIN AD1 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_1_n[0]] ; ## H08 FMC_HPC1_LA02_N +set_property -dict {PACKAGE_PIN AH1 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_1_p[1]] ; ## G09 FMC_HPC1_LA03_P +set_property -dict {PACKAGE_PIN AJ1 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_1_n[1]] ; ## G10 FMC_HPC1_LA03_N +set_property -dict {PACKAGE_PIN AF2 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_1_p[2]] ; ## H10 FMC_HPC1_LA04_P +set_property -dict {PACKAGE_PIN AF1 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_1_n[2]] ; ## H11 FMC_HPC1_LA04_N +set_property -dict {PACKAGE_PIN AG3 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_1_p[3]] ; ## D11 FMC_HPC1_LA05_P +set_property -dict {PACKAGE_PIN AH3 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_1_n[3]] ; ## D12 FMC_HPC1_LA05_N +set_property -dict {PACKAGE_PIN AH2 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_1_p[4]] ; ## C10 FMC_HPC1_LA06_P +set_property -dict {PACKAGE_PIN AJ2 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_1_n[4]] ; ## C11 FMC_HPC1_LA06_N +set_property -dict {PACKAGE_PIN AD4 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_1_p[5]] ; ## H13 FMC_HPC1_LA07_P +set_property -dict {PACKAGE_PIN AE4 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_1_n[5]] ; ## H14 FMC_HPC1_LA07_N +set_property -dict {PACKAGE_PIN AE3 IOSTANDARD LVDS} [get_ports tx_clk_out_1_p] ; ## G12 FMC_HPC1_LA08_P +set_property -dict {PACKAGE_PIN AF3 IOSTANDARD LVDS} [get_ports tx_clk_out_1_n] ; ## G13 FMC_HPC1_LA08_N +set_property -dict {PACKAGE_PIN AJ6 IOSTANDARD LVDS} [get_ports tx_frame_out_1_p] ; ## D14 FMC_HPC1_LA09_P +set_property -dict {PACKAGE_PIN AJ5 IOSTANDARD LVDS} [get_ports tx_frame_out_1_n] ; ## D15 FMC_HPC1_LA09_N +set_property -dict {PACKAGE_PIN AH4 IOSTANDARD LVDS} [get_ports tx_data_out_1_p[0]] ; ## C14 FMC_HPC1_LA10_P +set_property -dict {PACKAGE_PIN AJ4 IOSTANDARD LVDS} [get_ports tx_data_out_1_n[0]] ; ## C15 FMC_HPC1_LA10_N +set_property -dict {PACKAGE_PIN AE8 IOSTANDARD LVDS} [get_ports tx_data_out_1_p[1]] ; ## H16 FMC_HPC1_LA11_P +set_property -dict {PACKAGE_PIN AF8 IOSTANDARD LVDS} [get_ports tx_data_out_1_n[1]] ; ## H17 FMC_HPC1_LA11_N +set_property -dict {PACKAGE_PIN AD7 IOSTANDARD LVDS} [get_ports tx_data_out_1_p[2]] ; ## G15 FMC_HPC1_LA12_P +set_property -dict {PACKAGE_PIN AD6 IOSTANDARD LVDS} [get_ports tx_data_out_1_n[2]] ; ## G16 FMC_HPC1_LA12_N +set_property -dict {PACKAGE_PIN AG8 IOSTANDARD LVDS} [get_ports tx_data_out_1_p[3]] ; ## D17 FMC_HPC1_LA13_P +set_property -dict {PACKAGE_PIN AH8 IOSTANDARD LVDS} [get_ports tx_data_out_1_n[3]] ; ## D18 FMC_HPC1_LA13_N +set_property -dict {PACKAGE_PIN AH7 IOSTANDARD LVDS} [get_ports tx_data_out_1_p[4]] ; ## C18 FMC_HPC1_LA14_P +set_property -dict {PACKAGE_PIN AH6 IOSTANDARD LVDS} [get_ports tx_data_out_1_n[4]] ; ## C19 FMC_HPC1_LA14_N +set_property -dict {PACKAGE_PIN AD10 IOSTANDARD LVDS} [get_ports tx_data_out_1_p[5]] ; ## H19 FMC_HPC1_LA15_P +set_property -dict {PACKAGE_PIN AE9 IOSTANDARD LVDS} [get_ports tx_data_out_1_n[5]] ; ## H20 FMC_HPC1_LA15_N + +set_property -dict {PACKAGE_PIN AA11 IOSTANDARD LVCMOS18} [get_ports gpio_status_1[0]] ; ## H22 FMC_HPC1_LA19_P +set_property -dict {PACKAGE_PIN AA10 IOSTANDARD LVCMOS18} [get_ports gpio_status_1[1]] ; ## H23 FMC_HPC1_LA19_N +set_property -dict {PACKAGE_PIN AB11 IOSTANDARD LVCMOS18} [get_ports gpio_status_1[2]] ; ## G21 FMC_HPC1_LA20_P +set_property -dict {PACKAGE_PIN AB10 IOSTANDARD LVCMOS18} [get_ports gpio_status_1[3]] ; ## G22 FMC_HPC1_LA20_N +set_property -dict {PACKAGE_PIN AC12 IOSTANDARD LVCMOS18} [get_ports gpio_status_1[4]] ; ## H25 FMC_HPC1_LA21_P +set_property -dict {PACKAGE_PIN AC11 IOSTANDARD LVCMOS18} [get_ports gpio_status_1[5]] ; ## H26 FMC_HPC1_LA21_N +set_property -dict {PACKAGE_PIN AF11 IOSTANDARD LVCMOS18} [get_ports gpio_status_1[6]] ; ## G24 FMC_HPC1_LA22_P +set_property -dict {PACKAGE_PIN AG11 IOSTANDARD LVCMOS18} [get_ports gpio_status_1[7]] ; ## G25 FMC_HPC1_LA22_N +set_property -dict {PACKAGE_PIN AE12 IOSTANDARD LVCMOS18} [get_ports gpio_ctl_1[0]] ; ## D23 FMC_HPC1_LA23_P +set_property -dict {PACKAGE_PIN AF12 IOSTANDARD LVCMOS18} [get_ports gpio_ctl_1[1]] ; ## D24 FMC_HPC1_LA23_N +set_property -dict {PACKAGE_PIN AH12 IOSTANDARD LVCMOS18} [get_ports gpio_ctl_1[2]] ; ## H28 FMC_HPC1_LA24_P +set_property -dict {PACKAGE_PIN AH11 IOSTANDARD LVCMOS18} [get_ports gpio_ctl_1[3]] ; ## H29 FMC_HPC1_LA24_N +set_property -dict {PACKAGE_PIN AE10 IOSTANDARD LVCMOS18} [get_ports gpio_en_agc_1] ; ## G27 FMC_HPC1_LA25_P +set_property -dict {PACKAGE_PIN W12 IOSTANDARD LVCMOS18} [get_ports gpio_resetb_1] ; ## G30 FMC_HPC1_LA29_P +set_property -dict {PACKAGE_PIN AG10 IOSTANDARD LVCMOS18} [get_ports enable_1] ; ## G18 FMC_HPC1_LA16_P +set_property -dict {PACKAGE_PIN AG9 IOSTANDARD LVCMOS18} [get_ports txnrx_1] ; ## G19 FMC_HPC1_LA16_N +set_property -dict {PACKAGE_PIN U10 IOSTANDARD LVCMOS18} [get_ports gpio_debug_3_1] ; ## C26 FMC_HPC1_LA27_P +set_property -dict {PACKAGE_PIN T10 IOSTANDARD LVCMOS18} [get_ports gpio_debug_4_1] ; ## C27 FMC_HPC1_LA27_N +set_property -dict {PACKAGE_PIN T12 IOSTANDARD LVCMOS18} [get_ports gpio_calsw_3_1] ; ## D26 FMC_HPC1_LA26_P +set_property -dict {PACKAGE_PIN R12 IOSTANDARD LVCMOS18} [get_ports gpio_calsw_4_1] ; ## D27 FMC_HPC1_LA26_N + +# clocks + +create_clock -name rx_0_clk -period 4.00 [get_ports rx_clk_in_0_p] +create_clock -name rx_1_clk -period 4.00 [get_ports rx_clk_in_1_p] +create_clock -name ad9361_clk -period 4.00 [get_pins i_system_wrapper/system_i/axi_ad9361_0/clk] diff --git a/projects/fmcomms5/zcu102/system_project.tcl b/projects/fmcomms5/zcu102/system_project.tcl new file mode 100644 index 000000000..053a7b985 --- /dev/null +++ b/projects/fmcomms5/zcu102/system_project.tcl @@ -0,0 +1,17 @@ + + + +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/projects/scripts/adi_project.tcl +source $ad_hdl_dir/projects/scripts/adi_board.tcl + +adi_project_create fmcomms5_zcu102 +adi_project_files fmcomms5_zcu102 [list \ + "system_top.v" \ + "system_constr.xdc"\ + "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \ + "$ad_hdl_dir/projects/common/zcu102/zcu102_system_constr.xdc" ] + +adi_project_run fmcomms5_zcu102 + + diff --git a/projects/fmcomms5/zcu102/system_top.v b/projects/fmcomms5/zcu102/system_top.v new file mode 100644 index 000000000..5c665f94e --- /dev/null +++ b/projects/fmcomms5/zcu102/system_top.v @@ -0,0 +1,323 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top ( + + gpio_bd_i, + gpio_bd_o, + + rx_clk_in_0_p, + rx_clk_in_0_n, + rx_frame_in_0_p, + rx_frame_in_0_n, + rx_data_in_0_p, + rx_data_in_0_n, + tx_clk_out_0_p, + tx_clk_out_0_n, + tx_frame_out_0_p, + tx_frame_out_0_n, + tx_data_out_0_p, + tx_data_out_0_n, + gpio_status_0, + gpio_ctl_0, + gpio_en_agc_0, + mcs_sync, + gpio_resetb_0, + enable_0, + txnrx_0, + gpio_debug_1_0, + gpio_debug_2_0, + gpio_calsw_1_0, + gpio_calsw_2_0, + gpio_ad5355_rfen, + gpio_ad5355_lock, + + rx_clk_in_1_p, + rx_clk_in_1_n, + rx_frame_in_1_p, + rx_frame_in_1_n, + rx_data_in_1_p, + rx_data_in_1_n, + tx_clk_out_1_p, + tx_clk_out_1_n, + tx_frame_out_1_p, + tx_frame_out_1_n, + tx_data_out_1_p, + tx_data_out_1_n, + gpio_status_1, + gpio_ctl_1, + gpio_en_agc_1, + gpio_resetb_1, + enable_1, + txnrx_1, + gpio_debug_3_1, + gpio_debug_4_1, + gpio_calsw_3_1, + gpio_calsw_4_1, + + spi_ad9361_0, + spi_ad9361_1, + spi_ad5355, + spi_clk, + spi_mosi, + spi_miso, + + ref_clk_p, + ref_clk_n); + + input [12:0] gpio_bd_i; + output [ 7:0] gpio_bd_o; + + input rx_clk_in_0_p; + input rx_clk_in_0_n; + input rx_frame_in_0_p; + input rx_frame_in_0_n; + input [ 5:0] rx_data_in_0_p; + input [ 5:0] rx_data_in_0_n; + output tx_clk_out_0_p; + output tx_clk_out_0_n; + output tx_frame_out_0_p; + output tx_frame_out_0_n; + output [ 5:0] tx_data_out_0_p; + output [ 5:0] tx_data_out_0_n; + input [ 7:0] gpio_status_0; + output [ 3:0] gpio_ctl_0; + output gpio_en_agc_0; + output mcs_sync; + output gpio_resetb_0; + output enable_0; + output txnrx_0; + output gpio_debug_1_0; + output gpio_debug_2_0; + output gpio_calsw_1_0; + output gpio_calsw_2_0; + output gpio_ad5355_rfen; + input gpio_ad5355_lock; + + input rx_clk_in_1_p; + input rx_clk_in_1_n; + input rx_frame_in_1_p; + input rx_frame_in_1_n; + input [ 5:0] rx_data_in_1_p; + input [ 5:0] rx_data_in_1_n; + output tx_clk_out_1_p; + output tx_clk_out_1_n; + output tx_frame_out_1_p; + output tx_frame_out_1_n; + output [ 5:0] tx_data_out_1_p; + output [ 5:0] tx_data_out_1_n; + input [ 7:0] gpio_status_1; + output [ 3:0] gpio_ctl_1; + output gpio_en_agc_1; + output gpio_resetb_1; + output enable_1; + output txnrx_1; + output gpio_debug_3_1; + output gpio_debug_4_1; + output gpio_calsw_3_1; + output gpio_calsw_4_1; + + output spi_ad9361_0; + output spi_ad9361_1; + output spi_ad5355; + output spi_clk; + output spi_mosi; + input spi_miso; + + input ref_clk_p; + input ref_clk_n; + + // internal registers + + reg [ 2:0] mcs_sync_m = 'd0; + reg mcs_sync = 'd0; + + // internal signals + + wire sys_100m_resetn; + wire ref_clk_s; + wire ref_clk; + wire [ 94:0] gpio_i; + wire [ 94:0] gpio_o; + wire gpio_sync; + wire gpio_open_44_44; + wire gpio_open_15_15; + wire [ 2:0] spi0_csn; + wire spi0_clk; + wire spi0_mosi; + wire spi0_miso; + wire [ 2:0] spi1_csn; + wire spi1_clk; + wire spi1_mosi; + wire spi1_miso; + wire txnrx_0; + wire enable_0; + wire txnrx_1; + wire enable_1; + + // multi-chip synchronization + + always @(posedge ref_clk or negedge sys_100m_resetn) begin + if (sys_100m_resetn == 1'b0) begin + mcs_sync_m <= 3'd0; + mcs_sync <= 1'd0; + end else begin + mcs_sync_m <= {mcs_sync_m[1:0], gpio_sync}; + mcs_sync <= mcs_sync_m[2] & ~mcs_sync_m[1]; + end + end + + // instantiations + + IBUFGDS i_ref_clk_ibuf ( + .I (ref_clk_p), + .IB (ref_clk_n), + .O (ref_clk_s)); + + BUFR #(.BUFR_DIVIDE("BYPASS")) i_ref_clk_rbuf ( + .CLR (1'b0), + .CE (1'b1), + .I (ref_clk_s), + .O (ref_clk)); + + assign gpio_resetb_1 = gpio_o[65]; + assign gpio_i[64] = gpio_ad5355_lock; + assign gpio_ad5355_rfen = gpio_o[63]; + assign gpio_calsw_4_1 = gpio_o[62]; + assign gpio_calsw_3_1 = gpio_o[61]; + assign gpio_calsw_2_0 = gpio_o[60]; + assign gpio_calsw_1_0 = gpio_o[59]; + assign gpio_txnrx_1 = gpio_o[58]; + assign gpio_enable_1 = gpio_o[57]; + assign gpio_en_agc_1 = gpio_o[56]; + assign gpio_txnrx_0 = gpio_o[55]; + assign gpio_enable_0 = gpio_o[54]; + assign gpio_en_agc_0 = gpio_o[53]; + assign gpio_resetb_0 = gpio_o[52]; + assign gpio_sync = gpio_o[51]; + assign gpio_open_44_44 = gpio_o[50]; + assign gpio_debug_4_0 = gpio_o[49]; + assign gpio_debug_3_0 = gpio_o[48]; + assign gpio_debug_2_0 = gpio_o[47]; + assign gpio_debug_1_0 = gpio_o[46]; + assign gpio_ctl_1 = gpio_o[45:42]; + assign gpio_ctl_0 = gpio_o[41:38]; + assign gpio_i[37:30] = gpio_status_1; + assign gpio_i[29:22] = gpio_status_0; + assign gpio_open_15_15 = gpio_o[21]; + assign gpio_bd_o = gpio_o[20:13]; + assign gpio_i[12: 0] = gpio_bd_i; + + assign gpio_i[94:65] = gpio_o[94:65]; + assign gpio_i[63:38] = gpio_o[63:38]; + assign gpio_i[21:14] = gpio_o[21:14]; + + assign spi_ad9361_0 = spi0_csn[0]; + assign spi_ad9361_1 = spi0_csn[1]; + assign spi_ad5355 = spi0_csn[2]; + assign spi_clk = spi0_clk; + assign spi_mosi = spi0_mosi; + assign spi0_miso = spi_miso; + assign spi1_miso = 1'b0; + + system_wrapper i_system_wrapper ( + .gpio_i (gpio_i), + .gpio_o (gpio_o), + .ps_intr_00 (1'b0), + .ps_intr_01 (1'b0), + .ps_intr_02 (1'b0), + .ps_intr_03 (1'b0), + .ps_intr_04 (1'b0), + .ps_intr_05 (1'b0), + .ps_intr_06 (1'b0), + .ps_intr_07 (1'b0), + .ps_intr_08 (1'b0), + .ps_intr_09 (1'b0), + .ps_intr_10 (1'b0), + .ps_intr_11 (1'b0), + .ps_intr_14 (1'b0), + .ps_intr_15 (1'b0), + .rx_clk_in_0_n (rx_clk_in_0_n), + .rx_clk_in_0_p (rx_clk_in_0_p), + .rx_clk_in_1_n (rx_clk_in_1_n), + .rx_clk_in_1_p (rx_clk_in_1_p), + .rx_data_in_0_n (rx_data_in_0_n), + .rx_data_in_0_p (rx_data_in_0_p), + .rx_data_in_1_n (rx_data_in_1_n), + .rx_data_in_1_p (rx_data_in_1_p), + .rx_frame_in_0_n (rx_frame_in_0_n), + .rx_frame_in_0_p (rx_frame_in_0_p), + .rx_frame_in_1_n (rx_frame_in_1_n), + .rx_frame_in_1_p (rx_frame_in_1_p), + .spi0_csn (spi0_csn), + .spi0_miso (spi0_miso), + .spi0_mosi (spi0_mosi), + .spi0_sclk (spi0_clk), + .spi1_csn (spi1_csn), + .spi1_miso (spi1_miso), + .spi1_mosi (spi1_mosi), + .spi1_sclk (spi1_clk), + .sys_100m_resetn (sys_100m_resetn), + .tx_clk_out_0_n (tx_clk_out_0_n), + .tx_clk_out_0_p (tx_clk_out_0_p), + .tx_clk_out_1_n (tx_clk_out_1_n), + .tx_clk_out_1_p (tx_clk_out_1_p), + .tx_data_out_0_n (tx_data_out_0_n), + .tx_data_out_0_p (tx_data_out_0_p), + .tx_data_out_1_n (tx_data_out_1_n), + .tx_data_out_1_p (tx_data_out_1_p), + .tx_frame_out_0_n (tx_frame_out_0_n), + .tx_frame_out_0_p (tx_frame_out_0_p), + .tx_frame_out_1_n (tx_frame_out_1_n), + .tx_frame_out_1_p (tx_frame_out_1_p), + .txnrx_0 (txnrx_0), + .enable_0 (enable_0), + .up_enable_0 (gpio_enable_0), + .up_txnrx_0 (gpio_txnrx_0), + .txnrx_1 (txnrx_1), + .enable_1 (enable_1), + .up_enable_1 (gpio_enable_1), + .up_txnrx_1 (gpio_txnrx_1)); + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/projects/fmcomms6/common/fmcomms6_bd.tcl b/projects/fmcomms6/common/fmcomms6_bd.tcl deleted file mode 100644 index f5349d378..000000000 --- a/projects/fmcomms6/common/fmcomms6_bd.tcl +++ /dev/null @@ -1,88 +0,0 @@ - -# adc interface - -create_bd_port -dir I adc_clk_in_p -create_bd_port -dir I adc_clk_in_n -create_bd_port -dir I adc_or_in_p -create_bd_port -dir I adc_or_in_n -create_bd_port -dir I -from 15 -to 0 adc_data_in_p -create_bd_port -dir I -from 15 -to 0 adc_data_in_n - -# adc peripherals - -set axi_ad9652 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9652:1.0 axi_ad9652] - -set axi_ad9652_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9652_dma] -set_property -dict [list CONFIG.DMA_TYPE_SRC {2}] $axi_ad9652_dma -set_property -dict [list CONFIG.DMA_TYPE_DEST {0}] $axi_ad9652_dma -set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9652_dma -set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad9652_dma -set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $axi_ad9652_dma -set_property -dict [list CONFIG.FIFO_SIZE {8}] $axi_ad9652_dma - -set axi_ad9652_adc_fifo [create_bd_cell -type ip -vlnv analog.com:user:util_wfifo:1.0 axi_ad9652_adc_fifo] -set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $axi_ad9652_adc_fifo -set_property -dict [list CONFIG.DIN_ADDRESS_WIDTH {4}] $axi_ad9652_adc_fifo -set_property -dict [list CONFIG.DIN_DATA_WIDTH {16}] $axi_ad9652_adc_fifo -set_property -dict [list CONFIG.DOUT_DATA_WIDTH {32}] $axi_ad9652_adc_fifo - -set data_pack [create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 data_pack] -set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $data_pack - -# connections (adc) - -ad_connect adc_clk_in_p axi_ad9652/adc_clk_in_p -ad_connect adc_clk_in_n axi_ad9652/adc_clk_in_n -ad_connect adc_or_in_p axi_ad9652/adc_or_in_p -ad_connect adc_or_in_n axi_ad9652/adc_or_in_n -ad_connect adc_data_in_p axi_ad9652/adc_data_in_p -ad_connect adc_data_in_n axi_ad9652/adc_data_in_n - -ad_connect axi_ad9652/adc_clk axi_ad9652_adc_fifo/din_clk -ad_connect axi_ad9652/adc_rst axi_ad9652_adc_fifo/din_rst - -ad_connect sys_200m_clk axi_ad9652/delay_clk -ad_connect sys_200m_clk axi_ad9652_dma/fifo_wr_clk - -ad_connect sys_200m_clk data_pack/adc_clk -ad_connect sys_cpu_reset data_pack/adc_rst - -ad_connect axi_ad9652/adc_enable_0 axi_ad9652_adc_fifo/din_enable_0 -ad_connect axi_ad9652/adc_valid_0 axi_ad9652_adc_fifo/din_valid_0 -ad_connect axi_ad9652/adc_data_0 axi_ad9652_adc_fifo/din_data_0 -ad_connect axi_ad9652/adc_enable_1 axi_ad9652_adc_fifo/din_enable_1 -ad_connect axi_ad9652/adc_valid_1 axi_ad9652_adc_fifo/din_valid_1 -ad_connect axi_ad9652/adc_data_1 axi_ad9652_adc_fifo/din_data_1 - -ad_connect sys_200m_clk axi_ad9652_adc_fifo/dout_clk -ad_connect sys_cpu_resetn axi_ad9652_adc_fifo/dout_rstn - -ad_connect axi_ad9652_adc_fifo/dout_valid_0 data_pack/adc_valid_0 -ad_connect axi_ad9652_adc_fifo/dout_enable_0 data_pack/adc_enable_0 -ad_connect axi_ad9652_adc_fifo/dout_data_0 data_pack/adc_data_0 -ad_connect axi_ad9652_adc_fifo/dout_valid_1 data_pack/adc_valid_1 -ad_connect axi_ad9652_adc_fifo/dout_enable_1 data_pack/adc_enable_1 -ad_connect axi_ad9652_adc_fifo/dout_data_1 data_pack/adc_data_1 - -ad_connect axi_ad9652_adc_fifo/din_ovf axi_ad9652/adc_dovf - -ad_connect data_pack/adc_valid axi_ad9652_dma/fifo_wr_en -ad_connect data_pack/adc_sync axi_ad9652_dma/fifo_wr_sync -ad_connect data_pack/adc_data axi_ad9652_dma/fifo_wr_din -ad_connect axi_ad9652_adc_fifo/dout_ovf axi_ad9652_dma/fifo_wr_overflow - -# interconnect (cpu) - -ad_cpu_interconnect 0x79020000 axi_ad9652 -ad_cpu_interconnect 0x7c420000 axi_ad9652_dma - -# interconnect (mem/adc) - -ad_mem_hp1_interconnect sys_200m_clk sys_ps7/S_AXI_HP1 -ad_mem_hp1_interconnect sys_200m_clk axi_ad9652_dma/m_dest_axi -ad_connect sys_cpu_resetn axi_ad9652_dma/m_dest_axi_aresetn - -# interrupts - -ad_cpu_interrupt ps-13 mb-13 axi_ad9652_dma/irq - diff --git a/projects/fmcomms6/zc706/system_constr.xdc b/projects/fmcomms6/zc706/system_constr.xdc deleted file mode 100644 index e310f9cdb..000000000 --- a/projects/fmcomms6/zc706/system_constr.xdc +++ /dev/null @@ -1,57 +0,0 @@ - - -# adc - -set_property -dict {PACKAGE_PIN AE13 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_clk_in_p] ; ## G06 FMC_LPC_LA00_CC_P -set_property -dict {PACKAGE_PIN AF13 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_clk_in_n] ; ## G07 FMC_LPC_LA00_CC_N -set_property -dict {PACKAGE_PIN AH26 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_or_in_p] ; ## H22 FMC_LPC_LA19_P -set_property -dict {PACKAGE_PIN AH27 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_or_in_n] ; ## H23 FMC_LPC_LA19_N -set_property -dict {PACKAGE_PIN AF15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[0]] ; ## D08 FMC_LPC_LA01_CC_P -set_property -dict {PACKAGE_PIN AG15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[0]] ; ## D09 FMC_LPC_LA01_CC_N -set_property -dict {PACKAGE_PIN AE12 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[1]] ; ## H07 FMC_LPC_LA02_P -set_property -dict {PACKAGE_PIN AF12 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[1]] ; ## H08 FMC_LPC_LA02_N -set_property -dict {PACKAGE_PIN AG12 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[2]] ; ## G09 FMC_LPC_LA03_P -set_property -dict {PACKAGE_PIN AH12 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[2]] ; ## G10 FMC_LPC_LA03_N -set_property -dict {PACKAGE_PIN AJ15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[3]] ; ## H10 FMC_LPC_LA04_P -set_property -dict {PACKAGE_PIN AK15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[3]] ; ## H11 FMC_LPC_LA04_N -set_property -dict {PACKAGE_PIN AE16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[4]] ; ## D11 FMC_LPC_LA05_P -set_property -dict {PACKAGE_PIN AE15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[4]] ; ## D12 FMC_LPC_LA05_N -set_property -dict {PACKAGE_PIN AB12 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[5]] ; ## C10 FMC_LPC_LA06_P -set_property -dict {PACKAGE_PIN AC12 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[5]] ; ## C11 FMC_LPC_LA06_N -set_property -dict {PACKAGE_PIN AA15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[6]] ; ## H13 FMC_LPC_LA07_P -set_property -dict {PACKAGE_PIN AA14 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[6]] ; ## H14 FMC_LPC_LA07_N -set_property -dict {PACKAGE_PIN AD14 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[7]] ; ## G12 FMC_LPC_LA08_P -set_property -dict {PACKAGE_PIN AD13 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[7]] ; ## G13 FMC_LPC_LA08_N -set_property -dict {PACKAGE_PIN AH14 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[8]] ; ## D14 FMC_LPC_LA09_P -set_property -dict {PACKAGE_PIN AH13 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[8]] ; ## D15 FMC_LPC_LA09_N -set_property -dict {PACKAGE_PIN AC14 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[9]] ; ## C14 FMC_LPC_LA10_P -set_property -dict {PACKAGE_PIN AC13 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[9]] ; ## C15 FMC_LPC_LA10_N -set_property -dict {PACKAGE_PIN AJ16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[10]] ; ## H16 FMC_LPC_LA11_P -set_property -dict {PACKAGE_PIN AK16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[10]] ; ## H17 FMC_LPC_LA11_N -set_property -dict {PACKAGE_PIN AD16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[11]] ; ## G15 FMC_LPC_LA12_P -set_property -dict {PACKAGE_PIN AD15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[11]] ; ## G16 FMC_LPC_LA12_N -set_property -dict {PACKAGE_PIN AH17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[12]] ; ## D17 FMC_LPC_LA13_P -set_property -dict {PACKAGE_PIN AH16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[12]] ; ## D18 FMC_LPC_LA13_N -set_property -dict {PACKAGE_PIN AF18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[13]] ; ## C18 FMC_LPC_LA14_P -set_property -dict {PACKAGE_PIN AF17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[13]] ; ## C19 FMC_LPC_LA14_N -set_property -dict {PACKAGE_PIN AB15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[14]] ; ## H19 FMC_LPC_LA15_P -set_property -dict {PACKAGE_PIN AB14 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[14]] ; ## H20 FMC_LPC_LA15_N -set_property -dict {PACKAGE_PIN AE18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[15]] ; ## G18 FMC_LPC_LA16_P -set_property -dict {PACKAGE_PIN AE17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[15]] ; ## G19 FMC_LPC_LA16_N - -# spi - -set_property -dict {PACKAGE_PIN AK27 IOSTANDARD LVCMOS25} [get_ports spi_ad9517_csn] ; ## G24 FMC_LPC_LA22_P -set_property -dict {PACKAGE_PIN AH28 IOSTANDARD LVCMOS25} [get_ports spi_ad9652_csn] ; ## H25 FMC_LPC_LA21_P -set_property -dict {PACKAGE_PIN AH29 IOSTANDARD LVCMOS25} [get_ports spi_adf4351_csn] ; ## H26 FMC_LPC_LA21_N -set_property -dict {PACKAGE_PIN AJ26 IOSTANDARD LVCMOS25} [get_ports spi_clk] ; ## D23 FMC_LPC_LA23_P -set_property -dict {PACKAGE_PIN AK28 IOSTANDARD LVCMOS25} [get_ports spi_sdio] ; ## G25 FMC_LPC_LA22_N - -# gpio - -set_property -dict {PACKAGE_PIN AK26 IOSTANDARD LVCMOS25} [get_ports adf4351_ld] ; ## D24 FMC_LPC_LA23_N - -# clocks - -create_clock -name adc_clk_in -period 3.22 [get_ports adc_clk_in_p] - diff --git a/projects/fmcomms7/common/fmcomms7_bd.tcl b/projects/fmcomms7/common/fmcomms7_bd.tcl index 59e3cce66..9f82d1522 100644 --- a/projects/fmcomms7/common/fmcomms7_bd.tcl +++ b/projects/fmcomms7/common/fmcomms7_bd.tcl @@ -1,17 +1,12 @@ -# fmcomms7 +# spi2 -create_bd_port -dir I rx_ref_clk -create_bd_port -dir O rx_sync -create_bd_port -dir I rx_sysref -create_bd_port -dir I -from 3 -to 0 rx_data_p -create_bd_port -dir I -from 3 -to 0 rx_data_n +set axi_fmcomms7_spi [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_quad_spi:3.2 axi_fmcomms7_spi] +set_property -dict [list CONFIG.C_USE_STARTUP {0}] $axi_fmcomms7_spi +set_property -dict [list CONFIG.C_NUM_SS_BITS {12}] $axi_fmcomms7_spi +set_property -dict [list CONFIG.C_SCK_RATIO {8}] $axi_fmcomms7_spi -create_bd_port -dir I tx_ref_clk -create_bd_port -dir I tx_sync -create_bd_port -dir I tx_sysref -create_bd_port -dir O -from 7 -to 0 tx_data_p -create_bd_port -dir O -from 7 -to 0 tx_data_n +# connections (spi2) create_bd_port -dir O -from 11 -to 0 spi2_csn_o create_bd_port -dir I -from 11 -to 0 spi2_csn_i @@ -21,15 +16,29 @@ create_bd_port -dir I spi2_sdo_i create_bd_port -dir O spi2_sdo_o create_bd_port -dir I spi2_sdi_i +ad_connect spi2_csn_i axi_fmcomms7_spi/ss_i +ad_connect spi2_csn_o axi_fmcomms7_spi/ss_o +ad_connect spi2_clk_i axi_fmcomms7_spi/sck_i +ad_connect spi2_clk_o axi_fmcomms7_spi/sck_o +ad_connect spi2_sdo_i axi_fmcomms7_spi/io0_i +ad_connect spi2_sdo_o axi_fmcomms7_spi/io0_o +ad_connect spi2_sdi_i axi_fmcomms7_spi/io1_i +ad_connect sys_cpu_clk axi_fmcomms7_spi/ext_spi_clk + # dac peripherals +set axi_ad9144_xcvr [create_bd_cell -type ip -vlnv analog.com:user:axi_adxcvr:1.0 axi_ad9144_xcvr] +set_property -dict [list CONFIG.NUM_OF_LANES {8}] $axi_ad9144_xcvr +set_property -dict [list CONFIG.QPLL_ENABLE {1}] $axi_ad9144_xcvr +set_property -dict [list CONFIG.TX_OR_RX_N {1}] $axi_ad9144_xcvr + +set axi_ad9144_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:7.0 axi_ad9144_jesd] +set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {1}] $axi_ad9144_jesd +set_property -dict [list CONFIG.C_LANES {8}] $axi_ad9144_jesd + set axi_ad9144_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9144:1.0 axi_ad9144_core] set_property -dict [list CONFIG.QUAD_OR_DUAL_N {1}] $axi_ad9144_core -set axi_ad9144_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.2 axi_ad9144_jesd] -set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {1}] $axi_ad9144_jesd -set_property -dict [list CONFIG.C_LANES {8}] $axi_ad9144_jesd - set axi_ad9144_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9144_dma] set_property -dict [list CONFIG.DMA_TYPE_SRC {0}] $axi_ad9144_dma set_property -dict [list CONFIG.DMA_TYPE_DEST {1}] $axi_ad9144_dma @@ -48,12 +57,17 @@ set_property -dict [list CONFIG.NUM_OF_CHANNELS {4}] $axi_ad9144_upack # adc peripherals -set axi_ad9680_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9680:1.0 axi_ad9680_core] +set axi_ad9680_xcvr [create_bd_cell -type ip -vlnv analog.com:user:axi_adxcvr:1.0 axi_ad9680_xcvr] +set_property -dict [list CONFIG.NUM_OF_LANES {4}] $axi_ad9680_xcvr +set_property -dict [list CONFIG.QPLL_ENABLE {0}] $axi_ad9680_xcvr +set_property -dict [list CONFIG.TX_OR_RX_N {0}] $axi_ad9680_xcvr -set axi_ad9680_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.2 axi_ad9680_jesd] +set axi_ad9680_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:7.0 axi_ad9680_jesd] set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9680_jesd set_property -dict [list CONFIG.C_LANES {4}] $axi_ad9680_jesd +set axi_ad9680_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9680:1.0 axi_ad9680_core] + set axi_ad9680_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9680_dma] set_property -dict [list CONFIG.DMA_TYPE_SRC {1}] $axi_ad9680_dma set_property -dict [list CONFIG.DMA_TYPE_DEST {0}] $axi_ad9680_dma @@ -73,102 +87,38 @@ set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $axi_ad9680_cpack # dac/adc common gt -set axi_fmcomms7_gt [create_bd_cell -type ip -vlnv analog.com:user:axi_jesd_gt:1.0 axi_fmcomms7_gt] -set_property -dict [list CONFIG.QPLL1_ENABLE {0}] $axi_fmcomms7_gt -set_property -dict [list CONFIG.TX_NUM_OF_LANES {8}] $axi_fmcomms7_gt -set_property -dict [list CONFIG.RX_NUM_OF_LANES {4}] $axi_fmcomms7_gt -set_property -dict [list CONFIG.TX_DATA_SEL_0 {5}] $axi_fmcomms7_gt -set_property -dict [list CONFIG.TX_DATA_SEL_1 {3}] $axi_fmcomms7_gt -set_property -dict [list CONFIG.TX_DATA_SEL_2 {6}] $axi_fmcomms7_gt -set_property -dict [list CONFIG.TX_DATA_SEL_3 {7}] $axi_fmcomms7_gt -set_property -dict [list CONFIG.TX_DATA_SEL_4 {2}] $axi_fmcomms7_gt -set_property -dict [list CONFIG.TX_DATA_SEL_5 {0}] $axi_fmcomms7_gt -set_property -dict [list CONFIG.TX_DATA_SEL_6 {1}] $axi_fmcomms7_gt -set_property -dict [list CONFIG.TX_DATA_SEL_7 {4}] $axi_fmcomms7_gt +set util_fmcomms7_xcvr [create_bd_cell -type ip -vlnv analog.com:user:util_adxcvr:1.0 util_fmcomms7_xcvr] +set_property -dict [list CONFIG.RX_NUM_OF_LANES {4}] $util_fmcomms7_xcvr +set_property -dict [list CONFIG.TX_NUM_OF_LANES {8}] $util_fmcomms7_xcvr -set util_fmcomms7_gt [create_bd_cell -type ip -vlnv analog.com:user:util_jesd_gt:1.0 util_fmcomms7_gt] -set_property -dict [list CONFIG.QPLL1_ENABLE {0}] $util_fmcomms7_gt -set_property -dict [list CONFIG.NUM_OF_LANES {8}] $util_fmcomms7_gt -set_property -dict [list CONFIG.RX_ENABLE {1}] $util_fmcomms7_gt -set_property -dict [list CONFIG.RX_NUM_OF_LANES {4}] $util_fmcomms7_gt -set_property -dict [list CONFIG.TX_ENABLE {1}] $util_fmcomms7_gt -set_property -dict [list CONFIG.TX_NUM_OF_LANES {8}] $util_fmcomms7_gt +# reference clocks & resets -set axi_fmcomms7_spi [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_quad_spi:3.2 axi_fmcomms7_spi] -set_property -dict [list CONFIG.C_USE_STARTUP {0}] $axi_fmcomms7_spi -set_property -dict [list CONFIG.C_NUM_SS_BITS {12}] $axi_fmcomms7_spi -set_property -dict [list CONFIG.C_SCK_RATIO {8}] $axi_fmcomms7_spi +create_bd_port -dir I tx_ref_clk_0 +create_bd_port -dir I rx_ref_clk_0 -# connections (spi2) - -ad_connect spi2_csn_i axi_fmcomms7_spi/ss_i -ad_connect spi2_csn_o axi_fmcomms7_spi/ss_o -ad_connect spi2_clk_i axi_fmcomms7_spi/sck_i -ad_connect spi2_clk_o axi_fmcomms7_spi/sck_o -ad_connect spi2_sdo_i axi_fmcomms7_spi/io0_i -ad_connect spi2_sdo_o axi_fmcomms7_spi/io0_o -ad_connect spi2_sdi_i axi_fmcomms7_spi/io1_i -ad_connect sys_cpu_clk axi_fmcomms7_spi/ext_spi_clk - -# connections (gt) - -ad_connect util_fmcomms7_gt/qpll_ref_clk rx_ref_clk -ad_connect util_fmcomms7_gt/cpll_ref_clk tx_ref_clk - -ad_connect axi_fmcomms7_gt/gt_qpll_0 util_fmcomms7_gt/gt_qpll_0 -ad_connect axi_fmcomms7_gt/gt_pll_0 util_fmcomms7_gt/gt_pll_0 -ad_connect axi_fmcomms7_gt/gt_pll_1 util_fmcomms7_gt/gt_pll_1 -ad_connect axi_fmcomms7_gt/gt_pll_2 util_fmcomms7_gt/gt_pll_2 -ad_connect axi_fmcomms7_gt/gt_pll_3 util_fmcomms7_gt/gt_pll_3 -ad_connect axi_fmcomms7_gt/gt_pll_4 util_fmcomms7_gt/gt_pll_4 -ad_connect axi_fmcomms7_gt/gt_pll_5 util_fmcomms7_gt/gt_pll_5 -ad_connect axi_fmcomms7_gt/gt_pll_6 util_fmcomms7_gt/gt_pll_6 -ad_connect axi_fmcomms7_gt/gt_pll_7 util_fmcomms7_gt/gt_pll_7 -ad_connect axi_fmcomms7_gt/gt_rx_0 util_fmcomms7_gt/gt_rx_0 -ad_connect axi_fmcomms7_gt/gt_rx_1 util_fmcomms7_gt/gt_rx_1 -ad_connect axi_fmcomms7_gt/gt_rx_2 util_fmcomms7_gt/gt_rx_2 -ad_connect axi_fmcomms7_gt/gt_rx_3 util_fmcomms7_gt/gt_rx_3 -ad_connect axi_fmcomms7_gt/gt_rx_ip_0 axi_ad9680_jesd/gt0_rx -ad_connect axi_fmcomms7_gt/gt_rx_ip_1 axi_ad9680_jesd/gt1_rx -ad_connect axi_fmcomms7_gt/gt_rx_ip_2 axi_ad9680_jesd/gt2_rx -ad_connect axi_fmcomms7_gt/gt_rx_ip_3 axi_ad9680_jesd/gt3_rx -ad_connect axi_fmcomms7_gt/rx_gt_comma_align_enb_0 axi_ad9680_jesd/rxencommaalign_out -ad_connect axi_fmcomms7_gt/rx_gt_comma_align_enb_1 axi_ad9680_jesd/rxencommaalign_out -ad_connect axi_fmcomms7_gt/rx_gt_comma_align_enb_2 axi_ad9680_jesd/rxencommaalign_out -ad_connect axi_fmcomms7_gt/rx_gt_comma_align_enb_3 axi_ad9680_jesd/rxencommaalign_out -ad_connect axi_fmcomms7_gt/gt_tx_0 util_fmcomms7_gt/gt_tx_0 -ad_connect axi_fmcomms7_gt/gt_tx_1 util_fmcomms7_gt/gt_tx_1 -ad_connect axi_fmcomms7_gt/gt_tx_2 util_fmcomms7_gt/gt_tx_2 -ad_connect axi_fmcomms7_gt/gt_tx_3 util_fmcomms7_gt/gt_tx_3 -ad_connect axi_fmcomms7_gt/gt_tx_4 util_fmcomms7_gt/gt_tx_4 -ad_connect axi_fmcomms7_gt/gt_tx_5 util_fmcomms7_gt/gt_tx_5 -ad_connect axi_fmcomms7_gt/gt_tx_6 util_fmcomms7_gt/gt_tx_6 -ad_connect axi_fmcomms7_gt/gt_tx_7 util_fmcomms7_gt/gt_tx_7 -ad_connect axi_fmcomms7_gt/gt_tx_ip_0 axi_ad9144_jesd/gt0_tx -ad_connect axi_fmcomms7_gt/gt_tx_ip_1 axi_ad9144_jesd/gt1_tx -ad_connect axi_fmcomms7_gt/gt_tx_ip_2 axi_ad9144_jesd/gt2_tx -ad_connect axi_fmcomms7_gt/gt_tx_ip_3 axi_ad9144_jesd/gt3_tx -ad_connect axi_fmcomms7_gt/gt_tx_ip_4 axi_ad9144_jesd/gt4_tx -ad_connect axi_fmcomms7_gt/gt_tx_ip_5 axi_ad9144_jesd/gt5_tx -ad_connect axi_fmcomms7_gt/gt_tx_ip_6 axi_ad9144_jesd/gt6_tx -ad_connect axi_fmcomms7_gt/gt_tx_ip_7 axi_ad9144_jesd/gt7_tx +ad_xcvrpll tx_ref_clk_0 util_fmcomms7_xcvr/qpll_ref_clk_* +ad_xcvrpll rx_ref_clk_0 util_fmcomms7_xcvr/cpll_ref_clk_* +ad_xcvrpll axi_ad9144_xcvr/up_pll_rst util_fmcomms7_xcvr/up_qpll_rst_* +ad_xcvrpll axi_ad9680_xcvr/up_pll_rst util_fmcomms7_xcvr/up_cpll_rst_* +ad_connect sys_cpu_resetn util_fmcomms7_xcvr/up_rstn +ad_connect sys_cpu_clk util_fmcomms7_xcvr/up_clk # connections (dac) -ad_connect util_fmcomms7_gt/tx_sysref tx_sysref -ad_connect util_fmcomms7_gt/tx_p tx_data_p -ad_connect util_fmcomms7_gt/tx_n tx_data_n -ad_connect util_fmcomms7_gt/tx_sync tx_sync -ad_connect util_fmcomms7_gt/tx_out_clk util_fmcomms7_gt/tx_clk -ad_connect util_fmcomms7_gt/tx_out_clk axi_ad9144_jesd/tx_core_clk -ad_connect util_fmcomms7_gt/tx_ip_rst axi_ad9144_jesd/tx_reset -ad_connect util_fmcomms7_gt/tx_ip_rst_done axi_ad9144_jesd/tx_reset_done -ad_connect util_fmcomms7_gt/tx_ip_sysref axi_ad9144_jesd/tx_sysref -ad_connect util_fmcomms7_gt/tx_ip_sync axi_ad9144_jesd/tx_sync -ad_connect util_fmcomms7_gt/tx_ip_data axi_ad9144_jesd/tx_tdata -ad_connect util_fmcomms7_gt/tx_out_clk axi_ad9144_core/tx_clk -ad_connect util_fmcomms7_gt/tx_data axi_ad9144_core/tx_data -ad_connect util_fmcomms7_gt/tx_out_clk axi_ad9144_upack/dac_clk +ad_xcvrcon util_fmcomms7_xcvr axi_ad9144_xcvr axi_ad9144_jesd +ad_reconct util_fmcomms7_xcvr/tx_0 axi_ad9144_jesd/gt5_tx +ad_reconct util_fmcomms7_xcvr/tx_1 axi_ad9144_jesd/gt3_tx +ad_reconct util_fmcomms7_xcvr/tx_2 axi_ad9144_jesd/gt6_tx +ad_reconct util_fmcomms7_xcvr/tx_3 axi_ad9144_jesd/gt7_tx +ad_reconct util_fmcomms7_xcvr/tx_4 axi_ad9144_jesd/gt2_tx +ad_reconct util_fmcomms7_xcvr/tx_5 axi_ad9144_jesd/gt0_tx +ad_reconct util_fmcomms7_xcvr/tx_6 axi_ad9144_jesd/gt1_tx +ad_reconct util_fmcomms7_xcvr/tx_7 axi_ad9144_jesd/gt4_tx + +ad_connect util_fmcomms7_xcvr/tx_out_clk_0 axi_ad9144_core/tx_clk +ad_connect axi_ad9144_jesd/tx_tdata axi_ad9144_core/tx_data + +ad_connect util_fmcomms7_xcvr/tx_out_clk_0 axi_ad9144_upack/dac_clk ad_connect axi_ad9144_core/dac_enable_0 axi_ad9144_upack/dac_enable_0 ad_connect axi_ad9144_core/dac_ddata_0 axi_ad9144_upack/dac_data_0 ad_connect axi_ad9144_core/dac_valid_0 axi_ad9144_upack/dac_valid_0 @@ -181,7 +131,7 @@ ad_connect axi_ad9144_core/dac_valid_2 axi_ad9144_upack/dac_valid_2 ad_connect axi_ad9144_core/dac_enable_3 axi_ad9144_upack/dac_enable_3 ad_connect axi_ad9144_core/dac_ddata_3 axi_ad9144_upack/dac_data_3 ad_connect axi_ad9144_core/dac_valid_3 axi_ad9144_upack/dac_valid_3 -ad_connect util_fmcomms7_gt/tx_out_clk axi_ad9144_fifo/dac_clk +ad_connect util_fmcomms7_xcvr/tx_out_clk_0 axi_ad9144_fifo/dac_clk ad_connect axi_ad9144_upack/dac_valid axi_ad9144_fifo/dac_valid ad_connect axi_ad9144_upack/dac_data axi_ad9144_fifo/dac_data ad_connect sys_cpu_clk axi_ad9144_fifo/dma_clk @@ -196,30 +146,21 @@ ad_connect axi_ad9144_fifo/dma_xfer_last axi_ad9144_dma/m_axis_last # connections (adc) -ad_connect util_fmcomms7_gt/rx_sysref rx_sysref -ad_connect util_fmcomms7_gt/rx_p rx_data_p -ad_connect util_fmcomms7_gt/rx_n rx_data_n -ad_connect util_fmcomms7_gt/rx_sync rx_sync -ad_connect util_fmcomms7_gt/rx_out_clk util_fmcomms7_gt/rx_clk -ad_connect util_fmcomms7_gt/rx_out_clk axi_ad9680_jesd/rx_core_clk -ad_connect util_fmcomms7_gt/rx_ip_rst axi_ad9680_jesd/rx_reset -ad_connect util_fmcomms7_gt/rx_ip_rst_done axi_ad9680_jesd/rx_reset_done -ad_connect util_fmcomms7_gt/rx_ip_sysref axi_ad9680_jesd/rx_sysref -ad_connect util_fmcomms7_gt/rx_ip_sync axi_ad9680_jesd/rx_sync -ad_connect util_fmcomms7_gt/rx_ip_sof axi_ad9680_jesd/rx_start_of_frame -ad_connect util_fmcomms7_gt/rx_ip_data axi_ad9680_jesd/rx_tdata -ad_connect util_fmcomms7_gt/rx_out_clk axi_ad9680_core/rx_clk -ad_connect util_fmcomms7_gt/rx_data axi_ad9680_core/rx_data -ad_connect util_fmcomms7_gt/rx_out_clk axi_ad9680_cpack/adc_clk -ad_connect util_fmcomms7_gt/rx_rst axi_ad9680_cpack/adc_rst +ad_xcvrcon util_fmcomms7_xcvr axi_ad9680_xcvr axi_ad9680_jesd +ad_connect util_fmcomms7_xcvr/rx_out_clk_0 axi_ad9680_core/rx_clk +ad_connect axi_ad9680_jesd/rx_start_of_frame axi_ad9680_core/rx_sof +ad_connect axi_ad9680_jesd/rx_tdata axi_ad9680_core/rx_data + +ad_connect util_fmcomms7_xcvr/rx_out_clk_0 axi_ad9680_cpack/adc_clk +ad_connect axi_ad9680_jesd_rstgen/peripheral_reset axi_ad9680_cpack/adc_rst ad_connect axi_ad9680_core/adc_enable_0 axi_ad9680_cpack/adc_enable_0 ad_connect axi_ad9680_core/adc_valid_0 axi_ad9680_cpack/adc_valid_0 ad_connect axi_ad9680_core/adc_data_0 axi_ad9680_cpack/adc_data_0 ad_connect axi_ad9680_core/adc_enable_1 axi_ad9680_cpack/adc_enable_1 ad_connect axi_ad9680_core/adc_valid_1 axi_ad9680_cpack/adc_valid_1 ad_connect axi_ad9680_core/adc_data_1 axi_ad9680_cpack/adc_data_1 -ad_connect util_fmcomms7_gt/rx_out_clk axi_ad9680_fifo/adc_clk -ad_connect util_fmcomms7_gt/rx_rst axi_ad9680_fifo/adc_rst +ad_connect util_fmcomms7_xcvr/rx_out_clk_0 axi_ad9680_fifo/adc_clk +ad_connect axi_ad9680_jesd_rstgen/peripheral_reset axi_ad9680_fifo/adc_rst ad_connect axi_ad9680_cpack/adc_valid axi_ad9680_fifo/adc_wr ad_connect axi_ad9680_cpack/adc_data axi_ad9680_fifo/adc_wdata ad_connect sys_cpu_clk axi_ad9680_fifo/dma_clk @@ -233,10 +174,11 @@ ad_connect axi_ad9680_core/adc_dovf axi_ad9680_fifo/adc_wovf # interconnect (cpu) -ad_cpu_interconnect 0x44A60000 axi_fmcomms7_gt +ad_cpu_interconnect 0x44A60000 axi_ad9144_xcvr ad_cpu_interconnect 0x44A00000 axi_ad9144_core ad_cpu_interconnect 0x44A90000 axi_ad9144_jesd ad_cpu_interconnect 0x7c420000 axi_ad9144_dma +ad_cpu_interconnect 0x44A50000 axi_ad9680_xcvr ad_cpu_interconnect 0x44A10000 axi_ad9680_core ad_cpu_interconnect 0x44A91000 axi_ad9680_jesd ad_cpu_interconnect 0x7c400000 axi_ad9680_dma @@ -245,7 +187,7 @@ ad_cpu_interconnect 0x44A80000 axi_fmcomms7_spi # gt uses hp3, and 100MHz clock for both DRP and AXI4 ad_mem_hp3_interconnect sys_cpu_clk sys_ps7/S_AXI_HP3 -ad_mem_hp3_interconnect sys_cpu_clk axi_fmcomms7_gt/m_axi +ad_mem_hp3_interconnect sys_cpu_clk axi_ad9680_xcvr/m_axi # interconnect (mem/dac) @@ -260,3 +202,4 @@ ad_cpu_interrupt ps-9 mb-9 axi_ad9144_dma/irq ad_cpu_interrupt ps-10 mb-10 axi_ad9680_dma/irq ad_cpu_interrupt ps-12 mb-12 axi_fmcomms7_spi/ip2intc_irpt +ad_connect axi_ad9144_fifo/dac_fifo_bypass GND diff --git a/projects/fmcomms7/zc706/Makefile b/projects/fmcomms7/zc706/Makefile index 2caa37ee7..f51629899 100644 --- a/projects/fmcomms7/zc706/Makefile +++ b/projects/fmcomms7/zc706/Makefile @@ -14,25 +14,24 @@ M_DEPS += ../common/fmcomms7_bd.tcl M_DEPS += ../../scripts/adi_project.tcl M_DEPS += ../../scripts/adi_env.tcl M_DEPS += ../../scripts/adi_board.tcl -M_DEPS += ../../common/zc706/zc706_system_plddr3.tcl +M_DEPS += ../../common/zc706/zc706_system_plddr3_adcfifo.tcl M_DEPS += ../../common/zc706/zc706_system_mig_constr.xdc M_DEPS += ../../common/zc706/zc706_system_mig.prj M_DEPS += ../../common/zc706/zc706_system_constr.xdc M_DEPS += ../../common/zc706/zc706_system_bd.tcl -M_DEPS += ../../common/xilinx/sys_dmafifo.tcl -M_DEPS += ../../../library/common/ad_iobuf.v +M_DEPS += ../../common/xilinx/sys_dacfifo.tcl +M_DEPS += ../../../library/xilinx/common/ad_iobuf.v M_DEPS += ../../../library/axi_ad9144/axi_ad9144.xpr M_DEPS += ../../../library/axi_ad9680/axi_ad9680.xpr -M_DEPS += ../../../library/axi_adcfifo/axi_adcfifo.xpr +M_DEPS += ../../../library/xilinx/axi_adcfifo/axi_adcfifo.xpr +M_DEPS += ../../../library/xilinx/axi_adxcvr/axi_adxcvr.xpr M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr -M_DEPS += ../../../library/axi_jesd_gt/axi_jesd_gt.xpr M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr -M_DEPS += ../../../library/util_adcfifo/util_adcfifo.xpr +M_DEPS += ../../../library/xilinx/util_adxcvr/util_adxcvr.xpr M_DEPS += ../../../library/util_cpack/util_cpack.xpr M_DEPS += ../../../library/util_dacfifo/util_dacfifo.xpr -M_DEPS += ../../../library/util_jesd_gt/util_jesd_gt.xpr M_DEPS += ../../../library/util_upack/util_upack.xpr M_VIVADO := vivado -mode batch -source @@ -49,6 +48,7 @@ M_FLIST += *.sdk M_FLIST += *.hw M_FLIST += *.sim M_FLIST += .Xil +M_FLIST += *.ip_user_files @@ -63,37 +63,35 @@ clean: clean-all:clean make -C ../../../library/axi_ad9144 clean make -C ../../../library/axi_ad9680 clean - make -C ../../../library/axi_adcfifo clean + make -C ../../../library/xilinx/axi_adcfifo clean + make -C ../../../library/xilinx/axi_adxcvr clean make -C ../../../library/axi_clkgen clean make -C ../../../library/axi_dmac clean make -C ../../../library/axi_hdmi_tx clean - make -C ../../../library/axi_jesd_gt clean make -C ../../../library/axi_spdif_tx clean - make -C ../../../library/util_adcfifo clean + make -C ../../../library/xilinx/util_adxcvr clean make -C ../../../library/util_cpack clean make -C ../../../library/util_dacfifo clean - make -C ../../../library/util_jesd_gt clean make -C ../../../library/util_upack clean fmcomms7_zc706.sdk/system_top.hdf: $(M_DEPS) - rm -rf $(M_FLIST) + -rm -rf $(M_FLIST) $(M_VIVADO) system_project.tcl >> fmcomms7_zc706_vivado.log 2>&1 lib: make -C ../../../library/axi_ad9144 make -C ../../../library/axi_ad9680 - make -C ../../../library/axi_adcfifo + make -C ../../../library/xilinx/axi_adcfifo + make -C ../../../library/xilinx/axi_adxcvr make -C ../../../library/axi_clkgen make -C ../../../library/axi_dmac make -C ../../../library/axi_hdmi_tx - make -C ../../../library/axi_jesd_gt make -C ../../../library/axi_spdif_tx - make -C ../../../library/util_adcfifo + make -C ../../../library/xilinx/util_adxcvr make -C ../../../library/util_cpack make -C ../../../library/util_dacfifo - make -C ../../../library/util_jesd_gt make -C ../../../library/util_upack #################################################################################### diff --git a/projects/fmcomms7/zc706/system_bd.tcl b/projects/fmcomms7/zc706/system_bd.tcl index 3206d6a58..e2fd79784 100644 --- a/projects/fmcomms7/zc706/system_bd.tcl +++ b/projects/fmcomms7/zc706/system_bd.tcl @@ -1,9 +1,9 @@ source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl -source $ad_hdl_dir/projects/common/zc706/zc706_system_plddr3.tcl -source $ad_hdl_dir/projects/common/xilinx/sys_dmafifo.tcl +source $ad_hdl_dir/projects/common/zc706/zc706_system_plddr3_adcfifo.tcl +source $ad_hdl_dir/projects/common/xilinx/sys_dacfifo.tcl -p_plddr3_fifo [current_bd_instance .] axi_ad9680_fifo 128 +p_plddr3_adcfifo [current_bd_instance .] axi_ad9680_fifo 128 p_sys_dacfifo [current_bd_instance .] axi_ad9144_fifo 256 10 create_bd_port -dir I -type rst sys_rst @@ -22,4 +22,3 @@ create_bd_addr_seg -range 0x40000000 -offset 0x80000000 \ SEG_axi_ddr_cntrl_memaddr source ../common/fmcomms7_bd.tcl - diff --git a/projects/fmcomms7/zc706/system_constr.xdc b/projects/fmcomms7/zc706/system_constr.xdc index 998181c81..ec16a9a01 100644 --- a/projects/fmcomms7/zc706/system_constr.xdc +++ b/projects/fmcomms7/zc706/system_constr.xdc @@ -1,22 +1,22 @@ # fmcomms7 -set_property -dict {PACKAGE_PIN AA8 } [get_ports rx_ref_clk_p] ; ## B20 FMC_HPC_GBTCLK1_M2C_P -set_property -dict {PACKAGE_PIN AA7 } [get_ports rx_ref_clk_n] ; ## B21 FMC_HPC_GBTCLK1_M2C_N -set_property -dict {PACKAGE_PIN AE8 } [get_ports rx_data_p[0]] ; ## A10 FMC_HPC_DP3_M2C_P -set_property -dict {PACKAGE_PIN AE7 } [get_ports rx_data_n[0]] ; ## A11 FMC_HPC_DP3_M2C_N -set_property -dict {PACKAGE_PIN AH10} [get_ports rx_data_p[1]] ; ## C06 FMC_HPC_DP0_M2C_P -set_property -dict {PACKAGE_PIN AH9 } [get_ports rx_data_n[1]] ; ## C07 FMC_HPC_DP0_M2C_N -set_property -dict {PACKAGE_PIN AG8 } [get_ports rx_data_p[2]] ; ## A06 FMC_HPC_DP2_M2C_P -set_property -dict {PACKAGE_PIN AG7 } [get_ports rx_data_n[2]] ; ## A07 FMC_HPC_DP2_M2C_N -set_property -dict {PACKAGE_PIN AJ8 } [get_ports rx_data_p[3]] ; ## A02 FMC_HPC_DP1_M2C_P -set_property -dict {PACKAGE_PIN AJ7 } [get_ports rx_data_n[3]] ; ## A03 FMC_HPC_DP1_M2C_N -set_property -dict {PACKAGE_PIN AG21 IOSTANDARD LVDS_25} [get_ports rx_sync_p] ; ## D08 FMC_HPC_LA01_CC_P -set_property -dict {PACKAGE_PIN AH21 IOSTANDARD LVDS_25} [get_ports rx_sync_n] ; ## D09 FMC_HPC_LA01_CC_N -set_property -dict {PACKAGE_PIN AH19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_sysref_p] ; ## G09 FMC_HPC_LA03_P -set_property -dict {PACKAGE_PIN AJ19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_sysref_n] ; ## G10 FMC_HPC_LA03_N +set_property -dict {PACKAGE_PIN AA8 } [get_ports rx_ref_clk_p] ; ## B20 FMC_HPC_GBTCLK1_M2C_P +set_property -dict {PACKAGE_PIN AA7 } [get_ports rx_ref_clk_n] ; ## B21 FMC_HPC_GBTCLK1_M2C_N +set_property -dict {PACKAGE_PIN AE8 } [get_ports rx_data_p[0]] ; ## A10 FMC_HPC_DP3_M2C_P +set_property -dict {PACKAGE_PIN AE7 } [get_ports rx_data_n[0]] ; ## A11 FMC_HPC_DP3_M2C_N +set_property -dict {PACKAGE_PIN AH10} [get_ports rx_data_p[1]] ; ## C06 FMC_HPC_DP0_M2C_P +set_property -dict {PACKAGE_PIN AH9 } [get_ports rx_data_n[1]] ; ## C07 FMC_HPC_DP0_M2C_N +set_property -dict {PACKAGE_PIN AG8 } [get_ports rx_data_p[2]] ; ## A06 FMC_HPC_DP2_M2C_P +set_property -dict {PACKAGE_PIN AG7 } [get_ports rx_data_n[2]] ; ## A07 FMC_HPC_DP2_M2C_N +set_property -dict {PACKAGE_PIN AJ8 } [get_ports rx_data_p[3]] ; ## A02 FMC_HPC_DP1_M2C_P +set_property -dict {PACKAGE_PIN AJ7 } [get_ports rx_data_n[3]] ; ## A03 FMC_HPC_DP1_M2C_N +set_property -dict {PACKAGE_PIN AG21 IOSTANDARD LVDS_25} [get_ports rx_sync_p] ; ## D08 FMC_HPC_LA01_CC_P +set_property -dict {PACKAGE_PIN AH21 IOSTANDARD LVDS_25} [get_ports rx_sync_n] ; ## D09 FMC_HPC_LA01_CC_N +set_property -dict {PACKAGE_PIN AH19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_sysref_p] ; ## G09 FMC_HPC_LA03_P +set_property -dict {PACKAGE_PIN AJ19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_sysref_n] ; ## G10 FMC_HPC_LA03_N -set_property -dict {PACKAGE_PIN AD10} [get_ports tx_ref_clk_p] ; ## D04 FMC_HPC_GBTCLK0_M2C_P -set_property -dict {PACKAGE_PIN AD9 } [get_ports tx_ref_clk_n] ; ## D05 FMC_HPC_GBTCLK0_M2C_N +set_property -dict {PACKAGE_PIN AD10} [get_ports tx_ref_clk_p] ; ## D04 FMC_HPC_GBTCLK0_M2C_P +set_property -dict {PACKAGE_PIN AD9 } [get_ports tx_ref_clk_n] ; ## D05 FMC_HPC_GBTCLK0_M2C_N set_property -dict {PACKAGE_PIN AK2 } [get_ports tx_data_p[0]] ; ## A30 FMC_HPC_DP3_C2M_P (tx_data_p[5]) set_property -dict {PACKAGE_PIN AK1 } [get_ports tx_data_n[0]] ; ## A31 FMC_HPC_DP3_C2M_N (tx_data_n[5]) set_property -dict {PACKAGE_PIN AK10} [get_ports tx_data_p[1]] ; ## C02 FMC_HPC_DP0_C2M_P (tx_data_p[3]) @@ -51,24 +51,24 @@ set_property -dict {PACKAGE_PIN AG22 IOSTANDARD LVCMOS25} [get_ports spi_dir] # spi (others, sdi and/or sdo) -set_property -dict {PACKAGE_PIN T24 IOSTANDARD LVCMOS25} [get_ports spi2_csn_adf4355_1] ; ## H22 FMC_HPC_LA19_P -set_property -dict {PACKAGE_PIN T25 IOSTANDARD LVCMOS25} [get_ports spi2_csn_adf4355_2] ; ## H23 FMC_HPC_LA19_N -set_property -dict {PACKAGE_PIN W29 IOSTANDARD LVCMOS25} [get_ports spi2_csn_hmc1044_1] ; ## H25 FMC_HPC_LA21_P -set_property -dict {PACKAGE_PIN W30 IOSTANDARD LVCMOS25} [get_ports spi2_csn_hmc1044_2] ; ## H26 FMC_HPC_LA21_N -set_property -dict {PACKAGE_PIN AB24 IOSTANDARD LVCMOS25} [get_ports spi2_csn_hmc1044_3] ; ## G19 FMC_HPC_LA16_N -set_property -dict {PACKAGE_PIN V23 IOSTANDARD LVCMOS25} [get_ports spi2_csn_adl5240_1] ; ## D20 FMC_HPC_LA17_CC_P -set_property -dict {PACKAGE_PIN W24 IOSTANDARD LVCMOS25} [get_ports spi2_csn_adl5240_2] ; ## D21 FMC_HPC_LA17_CC_N -set_property -dict {PACKAGE_PIN U25 IOSTANDARD LVCMOS25} [get_ports spi2_csn_hmc271_1] ; ## G21 FMC_HPC_LA20_P -set_property -dict {PACKAGE_PIN V26 IOSTANDARD LVCMOS25} [get_ports spi2_csn_hmc271_2] ; ## G22 FMC_HPC_LA20_N -set_property -dict {PACKAGE_PIN V28 IOSTANDARD LVCMOS25} [get_ports spi2_clk] ; ## C26 FMC_HPC_LA27_P -set_property -dict {PACKAGE_PIN V29 IOSTANDARD LVCMOS25} [get_ports spi2_sdo] ; ## C27 FMC_HPC_LA27_N -set_property -dict {PACKAGE_PIN AA22 IOSTANDARD LVCMOS25} [get_ports spi2_sdi_hmc271_1] ; ## D17 FMC_HPC_LA13_P -set_property -dict {PACKAGE_PIN AA23 IOSTANDARD LVCMOS25} [get_ports spi2_sdi_hmc271_2] ; ## D18 FMC_HPC_LA13_N +set_property -dict {PACKAGE_PIN T24 IOSTANDARD LVCMOS25} [get_ports spi2_csn_adf4355_1] ; ## H22 FMC_HPC_LA19_P +set_property -dict {PACKAGE_PIN T25 IOSTANDARD LVCMOS25} [get_ports spi2_csn_adf4355_2] ; ## H23 FMC_HPC_LA19_N +set_property -dict {PACKAGE_PIN W29 IOSTANDARD LVCMOS25} [get_ports spi2_csn_hmc1044_1] ; ## H25 FMC_HPC_LA21_P +set_property -dict {PACKAGE_PIN W30 IOSTANDARD LVCMOS25} [get_ports spi2_csn_hmc1044_2] ; ## H26 FMC_HPC_LA21_N +set_property -dict {PACKAGE_PIN AB24 IOSTANDARD LVCMOS25} [get_ports spi2_csn_hmc1044_3] ; ## G19 FMC_HPC_LA16_N +set_property -dict {PACKAGE_PIN V23 IOSTANDARD LVCMOS25} [get_ports spi2_csn_adl5240_1] ; ## D20 FMC_HPC_LA17_CC_P +set_property -dict {PACKAGE_PIN W24 IOSTANDARD LVCMOS25} [get_ports spi2_csn_adl5240_2] ; ## D21 FMC_HPC_LA17_CC_N +set_property -dict {PACKAGE_PIN U25 IOSTANDARD LVCMOS25} [get_ports spi2_csn_hmc271_1] ; ## G21 FMC_HPC_LA20_P +set_property -dict {PACKAGE_PIN V26 IOSTANDARD LVCMOS25} [get_ports spi2_csn_hmc271_2] ; ## G22 FMC_HPC_LA20_N +set_property -dict {PACKAGE_PIN V28 IOSTANDARD LVCMOS25} [get_ports spi2_clk] ; ## C26 FMC_HPC_LA27_P +set_property -dict {PACKAGE_PIN V29 IOSTANDARD LVCMOS25} [get_ports spi2_sdo] ; ## C27 FMC_HPC_LA27_N +set_property -dict {PACKAGE_PIN AA22 IOSTANDARD LVCMOS25} [get_ports spi2_sdi_hmc271_1] ; ## D17 FMC_HPC_LA13_P +set_property -dict {PACKAGE_PIN AA23 IOSTANDARD LVCMOS25} [get_ports spi2_sdi_hmc271_2] ; ## D18 FMC_HPC_LA13_N # external trigger -set_property -dict {PACKAGE_PIN AJ23 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports trig_p] ; ## H13 FMC_HPC_LA07_P -set_property -dict {PACKAGE_PIN AJ24 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports trig_n] ; ## H14 FMC_HPC_LA07_N +set_property -dict {PACKAGE_PIN AJ23 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports trig_p] ; ## H13 FMC_HPC_LA07_P +set_property -dict {PACKAGE_PIN AJ24 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports trig_n] ; ## H14 FMC_HPC_LA07_N # clock gpio @@ -77,7 +77,7 @@ set_property -dict {PACKAGE_PIN U29 IOSTANDARD LVCMOS25} [get_ports clk_gpio set_property -dict {PACKAGE_PIN T30 IOSTANDARD LVCMOS25} [get_ports clk_gpio[2]] ; ## H28 FMC_HPC_LA24_P set_property -dict {PACKAGE_PIN U30 IOSTANDARD LVCMOS25} [get_ports clk_gpio[3]] ; ## H29 FMC_HPC_LA24_N -# status +# status set_property -dict {PACKAGE_PIN AD23 IOSTANDARD LVCMOS25} [get_ports adc_fda] ; ## H16 FMC_HPC_LA11_P set_property -dict {PACKAGE_PIN AE23 IOSTANDARD LVCMOS25} [get_ports adc_fdb] ; ## H17 FMC_HPC_LA11_N @@ -85,23 +85,23 @@ set_property -dict {PACKAGE_PIN AG19 IOSTANDARD LVCMOS25} [get_ports dac_irq] set_property -dict {PACKAGE_PIN R28 IOSTANDARD LVCMOS25} [get_ports adf4355_1_ld] ; ## D26 FMC_HPC_LA26_P set_property -dict {PACKAGE_PIN T28 IOSTANDARD LVCMOS25} [get_ports adf4355_2_ld] ; ## D27 FMC_HPC_LA26_N -# control +# control -set_property -dict {PACKAGE_PIN AA24 IOSTANDARD LVCMOS25} [get_ports xo_en] ; ## G18 FMC_HPC_LA16_P -set_property -dict {PACKAGE_PIN AF19 IOSTANDARD LVCMOS25} [get_ports clk_sync] ; ## G12 FMC_HPC_LA08_P -set_property -dict {PACKAGE_PIN W25 IOSTANDARD LVCMOS25} [get_ports adf4355_2_pd] ; ## C22 FMC_HPC_LA18_CC_P -set_property -dict {PACKAGE_PIN AF23 IOSTANDARD LVCMOS25} [get_ports dac_txen0] ; ## G15 FMC_HPC_LA12_P -set_property -dict {PACKAGE_PIN AF24 IOSTANDARD LVCMOS25} [get_ports dac_txen1] ; ## G16 FMC_HPC_LA12_N -set_property -dict {PACKAGE_PIN V27 IOSTANDARD LVCMOS25} [get_ports hmc271_1_reset] ; ## G24 FMC_HPC_LA22_P -set_property -dict {PACKAGE_PIN W28 IOSTANDARD LVCMOS25} [get_ports hmc271_2_reset] ; ## G25 FMC_HPC_LA22_N -set_property -dict {PACKAGE_PIN W26 IOSTANDARD LVCMOS25} [get_ports hmc349_sel] ; ## C23 FMC_HPC_LA18_CC_N -set_property -dict {PACKAGE_PIN P25 IOSTANDARD LVCMOS25} [get_ports hmc922_a] ; ## D23 FMC_HPC_LA23_P -set_property -dict {PACKAGE_PIN P26 IOSTANDARD LVCMOS25} [get_ports hmc922_b] ; ## D24 FMC_HPC_LA23_N +set_property -dict {PACKAGE_PIN AA24 IOSTANDARD LVCMOS25} [get_ports xo_en] ; ## G18 FMC_HPC_LA16_P +set_property -dict {PACKAGE_PIN AF19 IOSTANDARD LVCMOS25} [get_ports clk_sync] ; ## G12 FMC_HPC_LA08_P +set_property -dict {PACKAGE_PIN W25 IOSTANDARD LVCMOS25} [get_ports adf4355_2_pd] ; ## C22 FMC_HPC_LA18_CC_P +set_property -dict {PACKAGE_PIN AF23 IOSTANDARD LVCMOS25} [get_ports dac_txen0] ; ## G15 FMC_HPC_LA12_P +set_property -dict {PACKAGE_PIN AF24 IOSTANDARD LVCMOS25} [get_ports dac_txen1] ; ## G16 FMC_HPC_LA12_N +set_property -dict {PACKAGE_PIN V27 IOSTANDARD LVCMOS25} [get_ports hmc271_1_reset] ; ## G24 FMC_HPC_LA22_P +set_property -dict {PACKAGE_PIN W28 IOSTANDARD LVCMOS25} [get_ports hmc271_2_reset] ; ## G25 FMC_HPC_LA22_N +set_property -dict {PACKAGE_PIN W26 IOSTANDARD LVCMOS25} [get_ports hmc349_sel] ; ## C23 FMC_HPC_LA18_CC_N +set_property -dict {PACKAGE_PIN P25 IOSTANDARD LVCMOS25} [get_ports hmc922_a] ; ## D23 FMC_HPC_LA23_P +set_property -dict {PACKAGE_PIN P26 IOSTANDARD LVCMOS25} [get_ports hmc922_b] ; ## D24 FMC_HPC_LA23_N # clocks create_clock -name tx_ref_clk -period 2.00 [get_ports tx_ref_clk_p] create_clock -name rx_ref_clk -period 2.00 [get_ports rx_ref_clk_p] -create_clock -name tx_div_clk -period 4.00 [get_pins i_system_wrapper/system_i/axi_fmcomms7_gt/inst/g_lane_1[0].i_gt_channel_1/i_gtxe2_channel/TXOUTCLK] -create_clock -name rx_div_clk -period 4.00 [get_pins i_system_wrapper/system_i/axi_fmcomms7_gt/inst/g_lane_1[0].i_gt_channel_1/i_gtxe2_channel/RXOUTCLK] +create_clock -name tx_div_clk -period 4.00 [get_pins i_system_wrapper/system_i/util_fmcomms7_xcvr/inst/i_xch_0/i_gtxe2_channel/TXOUTCLK] +create_clock -name rx_div_clk -period 4.00 [get_pins i_system_wrapper/system_i/util_fmcomms7_xcvr/inst/i_xch_0/i_gtxe2_channel/RXOUTCLK] diff --git a/projects/fmcomms7/zc706/system_project.tcl b/projects/fmcomms7/zc706/system_project.tcl index 06c3ab354..e82dc8160 100644 --- a/projects/fmcomms7/zc706/system_project.tcl +++ b/projects/fmcomms7/zc706/system_project.tcl @@ -10,12 +10,13 @@ adi_project_files fmcomms7_zc706 [list \ "../common/fmcomms7_spi.v" \ "system_top.v" \ "system_constr.xdc"\ - "$ad_hdl_dir/library/common/ad_iobuf.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \ "$ad_hdl_dir/projects/common/zc706/zc706_system_mig_constr.xdc" \ "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ] set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc] set_property PROCESSING_ORDER EARLY [get_files system_constr.xdc] +set_property is_enabled false [get_files *system_axi*_spi*.xdc] adi_project_run fmcomms7_zc706 diff --git a/projects/fmcomms7/zc706/system_top.v b/projects/fmcomms7/zc706/system_top.v index 3dffcd50b..2bd1e4b40 100644 --- a/projects/fmcomms7/zc706/system_top.v +++ b/projects/fmcomms7/zc706/system_top.v @@ -477,11 +477,17 @@ module system_top ( .ps_intr_07 (1'b0), .ps_intr_08 (1'b0), .ps_intr_11 (1'b0), - .rx_data_n (rx_data_n), - .rx_data_p (rx_data_p), - .rx_ref_clk (rx_ref_clk), - .rx_sync (rx_sync), - .rx_sysref (rx_sysref), + .rx_data_0_n (rx_data_n[0]), + .rx_data_0_p (rx_data_p[0]), + .rx_data_1_n (rx_data_n[1]), + .rx_data_1_p (rx_data_p[1]), + .rx_data_2_n (rx_data_n[2]), + .rx_data_2_p (rx_data_p[2]), + .rx_data_3_n (rx_data_n[3]), + .rx_data_3_p (rx_data_p[3]), + .rx_ref_clk_0 (rx_ref_clk), + .rx_sync_0 (rx_sync), + .rx_sysref_0 (rx_sysref), .spdif (spdif), .spi0_clk_i (spi0_clk), .spi0_clk_o (spi0_clk), @@ -511,11 +517,25 @@ module system_top ( .sys_clk_clk_n (sys_clk_n), .sys_clk_clk_p (sys_clk_p), .sys_rst (sys_rst), - .tx_data_n (tx_data_n), - .tx_data_p (tx_data_p), - .tx_ref_clk (tx_ref_clk), - .tx_sync (tx_sync), - .tx_sysref (tx_sysref)); + .tx_data_0_n (tx_data_n[0]), + .tx_data_0_p (tx_data_p[0]), + .tx_data_1_n (tx_data_n[1]), + .tx_data_1_p (tx_data_p[1]), + .tx_data_2_n (tx_data_n[2]), + .tx_data_2_p (tx_data_p[2]), + .tx_data_3_n (tx_data_n[3]), + .tx_data_3_p (tx_data_p[3]), + .tx_data_4_n (tx_data_n[4]), + .tx_data_4_p (tx_data_p[4]), + .tx_data_5_n (tx_data_n[5]), + .tx_data_5_p (tx_data_p[5]), + .tx_data_6_n (tx_data_n[6]), + .tx_data_6_p (tx_data_p[6]), + .tx_data_7_n (tx_data_n[7]), + .tx_data_7_p (tx_data_p[7]), + .tx_ref_clk_0 (tx_ref_clk), + .tx_sync_0 (tx_sync), + .tx_sysref_0 (tx_sysref)); endmodule diff --git a/projects/imageon/common/imageon_bd.tcl b/projects/imageon/common/imageon_bd.tcl index 412705ab3..4c0caa36c 100644 --- a/projects/imageon/common/imageon_bd.tcl +++ b/projects/imageon/common/imageon_bd.tcl @@ -1,33 +1,29 @@ -# define additional ports - -create_bd_port -dir I spdif_rx - # adv7511 (reconfigure base design) -set_property CONFIG.EMBEDDED_SYNC {1} [get_bd_cells axi_hdmi_core] +delete_bd_objs [get_bd_nets -of_objects [find_bd_objs -relation connected_to [get_bd_ports hdmi_out_clk]]] +delete_bd_objs [get_bd_nets -of_objects [find_bd_objs -relation connected_to [get_bd_ports hdmi_vsync]]] +delete_bd_objs [get_bd_nets -of_objects [find_bd_objs -relation connected_to [get_bd_ports hdmi_hsync]]] +delete_bd_objs [get_bd_nets -of_objects [find_bd_objs -relation connected_to [get_bd_ports hdmi_data_e]]] +delete_bd_objs [get_bd_nets -of_objects [find_bd_objs -relation connected_to [get_bd_ports hdmi_data]]] -create_bd_port -dir O -from 15 -to 0 hdmi_es_data -ad_connect hdmi_es_data axi_hdmi_core/hdmi_16_es_data +delete_bd_objs [get_bd_ports hdmi_out_clk] +delete_bd_objs [get_bd_ports hdmi_vsync] +delete_bd_objs [get_bd_ports hdmi_hsync] +delete_bd_objs [get_bd_ports hdmi_data_e] +delete_bd_objs [get_bd_ports hdmi_data] + +set_property CONFIG.EMBEDDED_SYNC {1} [get_bd_cells axi_hdmi_core] +set_property CONFIG.OUT_CLK_POLARITY {1} [get_bd_cells axi_hdmi_core] + +create_bd_port -dir O hdmi_tx_clk +create_bd_port -dir O -from 15 -to 0 hdmi_tx_data + +ad_connect hdmi_tx_clk axi_hdmi_core/hdmi_out_clk +ad_connect hdmi_tx_data axi_hdmi_core/hdmi_16_es_data # adv7611 -create_bd_port -dir I hdmi_rx_clk -create_bd_port -dir I -from 15 -to 0 hdmi_rx_data - -# iic interface - -set axi_iic_imageon [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_iic:2.0 axi_iic_imageon] -set_property -dict [list CONFIG.USE_BOARD_FLOW {true}] $axi_iic_imageon -set_property -dict [list CONFIG.IIC_BOARD_INTERFACE {Custom}] $axi_iic_imageon - -create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 iic_imageon -ad_connect iic_imageon axi_iic_imageon/iic -ad_cpu_interconnect 0x43C40000 axi_iic_imageon -ad_cpu_interrupt ps-11 mb-11 axi_iic_imageon/iic2intc_irpt - -# hdmi peripherals - set axi_hdmi_rx_core [create_bd_cell -type ip -vlnv analog.com:user:axi_hdmi_rx:1.0 axi_hdmi_rx_core] set axi_hdmi_rx_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_hdmi_rx_dma] @@ -41,15 +37,41 @@ set_property -dict [list CONFIG.SYNC_TRANSFER_START {1}] $axi_hdmi_rx_dma set_property -dict [list CONFIG.DMA_LENGTH_WIDTH {14}] $axi_hdmi_rx_dma set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {64}] $axi_hdmi_rx_dma set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $axi_hdmi_rx_dma +set_property -dict [list CONFIG.FIFO_SIZE {16}] $axi_hdmi_rx_dma + +create_bd_port -dir I hdmi_rx_clk +create_bd_port -dir I -from 15 -to 0 hdmi_rx_data ad_connect hdmi_rx_clk axi_hdmi_rx_core/hdmi_rx_clk ad_connect hdmi_rx_data axi_hdmi_rx_core/hdmi_rx_data -ad_connect hdmi_clk axi_hdmi_rx_core/hdmi_clk -ad_connect hdmi_clk axi_hdmi_rx_dma/fifo_wr_clk + +ad_connect axi_hdmi_rx_core/hdmi_clk axi_hdmi_rx_dma/fifo_wr_clk ad_connect axi_hdmi_rx_core/hdmi_dma_sof axi_hdmi_rx_dma/fifo_wr_sync ad_connect axi_hdmi_rx_core/hdmi_dma_de axi_hdmi_rx_dma/fifo_wr_en ad_connect axi_hdmi_rx_core/hdmi_dma_data axi_hdmi_rx_dma/fifo_wr_din ad_connect axi_hdmi_rx_core/hdmi_dma_ovf axi_hdmi_rx_dma/fifo_wr_overflow +ad_connect axi_hdmi_rx_core/hdmi_dma_unf GND +ad_connect sys_cpu_resetn axi_hdmi_rx_dma/m_dest_axi_aresetn + +ad_cpu_interconnect 0x43100000 axi_hdmi_rx_core +ad_cpu_interconnect 0x43C20000 axi_hdmi_rx_dma + +ad_mem_hp2_interconnect sys_cpu_clk sys_ps7/S_AXI_HP2 +ad_mem_hp2_interconnect sys_cpu_clk axi_hdmi_rx_dma/m_dest_axi + +ad_cpu_interrupt ps-12 mb-12 axi_hdmi_rx_dma/irq + +# spdif tx + +delete_bd_objs [get_bd_nets -of_objects [find_bd_objs -relation connected_to [get_bd_ports spdif]]] +delete_bd_objs [get_bd_ports spdif] + +create_bd_port -dir O spdif_tx +ad_connect spdif_tx axi_spdif_tx_core/spdif_tx_o + +# spdif rx + +create_bd_port -dir I spdif_rx set axi_spdif_rx_core [create_bd_cell -type ip -vlnv analog.com:user:axi_spdif_rx:1.0 axi_spdif_rx_core] set_property -dict [list CONFIG.C_S_AXI_ADDR_WIDTH {16}] $axi_spdif_rx_core @@ -64,31 +86,16 @@ ad_connect sys_ps7/DMA3_REQ axi_spdif_rx_core/DMA_REQ ad_connect sys_ps7/DMA3_ACK axi_spdif_rx_core/DMA_ACK ad_connect spdif_rx axi_spdif_rx_core/spdif_rx_i -ad_cpu_interconnect 0x43100000 axi_hdmi_rx_core -ad_cpu_interconnect 0x43C20000 axi_hdmi_rx_dma ad_cpu_interconnect 0x75C20000 axi_spdif_rx_core -ad_mem_hp2_interconnect sys_cpu_clk sys_ps7/S_AXI_HP2 -ad_mem_hp2_interconnect sys_cpu_clk axi_hdmi_rx_dma/m_dest_axi -ad_connect sys_cpu_resetn axi_hdmi_rx_dma/m_dest_axi_aresetn +# iic interface -ad_cpu_interrupt ps-12 mb-12 axi_hdmi_rx_dma/irq +set axi_iic_imageon [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_iic:2.0 axi_iic_imageon] +set_property -dict [list CONFIG.USE_BOARD_FLOW {true}] $axi_iic_imageon +set_property -dict [list CONFIG.IIC_BOARD_INTERFACE {Custom}] $axi_iic_imageon -# debug - -set ila_fifo_dma_rx [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.0 ila_fifo_dma_rx] -set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_fifo_dma_rx -set_property -dict [list CONFIG.C_NUM_OF_PROBES {4}] $ila_fifo_dma_rx -set_property -dict [list CONFIG.C_DATA_DEPTH {4096}] $ila_fifo_dma_rx -set_property -dict [list CONFIG.C_PROBE0_WIDTH {1}] $ila_fifo_dma_rx -set_property -dict [list CONFIG.C_PROBE1_WIDTH {1}] $ila_fifo_dma_rx -set_property -dict [list CONFIG.C_PROBE2_WIDTH {64}] $ila_fifo_dma_rx -set_property -dict [list CONFIG.C_PROBE3_WIDTH {1}] $ila_fifo_dma_rx - -ad_connect hdmi_rx_clk ila_fifo_dma_rx/clk - -ad_connect ila_fifo_dma_rx/probe0 axi_hdmi_rx_dma/fifo_wr_sync -ad_connect ila_fifo_dma_rx/probe1 axi_hdmi_rx_dma/fifo_wr_en -ad_connect ila_fifo_dma_rx/probe2 axi_hdmi_rx_dma/fifo_wr_din -ad_connect ila_fifo_dma_rx/probe3 axi_hdmi_rx_dma/fifo_wr_overflow +create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 iic_imageon +ad_connect iic_imageon axi_iic_imageon/iic +ad_cpu_interconnect 0x43C40000 axi_iic_imageon +ad_cpu_interrupt ps-11 mb-11 axi_iic_imageon/iic2intc_irpt diff --git a/projects/imageon/zc706/Makefile b/projects/imageon/zc706/Makefile index c4981bb84..a01d63ffa 100644 --- a/projects/imageon/zc706/Makefile +++ b/projects/imageon/zc706/Makefile @@ -13,9 +13,8 @@ M_DEPS += ../common/imageon_bd.tcl M_DEPS += ../../scripts/adi_project.tcl M_DEPS += ../../scripts/adi_env.tcl M_DEPS += ../../scripts/adi_board.tcl -M_DEPS += ../../common/zc706/zc706_system_constr.xdc M_DEPS += ../../common/zc706/zc706_system_bd.tcl -M_DEPS += ../../../library/common/ad_iobuf.v +M_DEPS += ../../../library/xilinx/common/ad_iobuf.v M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr M_DEPS += ../../../library/axi_hdmi_rx/axi_hdmi_rx.xpr @@ -37,6 +36,7 @@ M_FLIST += *.sdk M_FLIST += *.hw M_FLIST += *.sim M_FLIST += .Xil +M_FLIST += *.ip_user_files @@ -58,7 +58,7 @@ clean-all:clean imageon_zc706.sdk/system_top.hdf: $(M_DEPS) - rm -rf $(M_FLIST) + -rm -rf $(M_FLIST) $(M_VIVADO) system_project.tcl >> imageon_zc706_vivado.log 2>&1 diff --git a/projects/imageon/zc706/system_constr.xdc b/projects/imageon/zc706/system_constr.xdc index 8ad9c0346..9b1b1257d 100644 --- a/projects/imageon/zc706/system_constr.xdc +++ b/projects/imageon/zc706/system_constr.xdc @@ -50,4 +50,32 @@ set_property -dict {PACKAGE_PIN AG15 IOSTANDARD LVCMOS25} [get_ports hd # clock definition -create_clock -period 6.66667 -name hdmi_rx_clk [get_ports hdmi_rx_clk] +create_clock -period 6.000 -name hdmi_rx_clk [get_ports hdmi_rx_clk] + +# default constraints + +# iic + +set_property -dict {PACKAGE_PIN AJ14 IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports iic_scl] +set_property -dict {PACKAGE_PIN AJ18 IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports iic_sda] + +# gpio (switches, leds and such) + +set_property -dict {PACKAGE_PIN AB17 IOSTANDARD LVCMOS25} [get_ports gpio_bd[0]] ; ## GPIO_DIP_SW0 +set_property -dict {PACKAGE_PIN AC16 IOSTANDARD LVCMOS25} [get_ports gpio_bd[1]] ; ## GPIO_DIP_SW1 +set_property -dict {PACKAGE_PIN AC17 IOSTANDARD LVCMOS25} [get_ports gpio_bd[2]] ; ## GPIO_DIP_SW2 +set_property -dict {PACKAGE_PIN AJ13 IOSTANDARD LVCMOS25} [get_ports gpio_bd[3]] ; ## GPIO_DIP_SW3 +set_property -dict {PACKAGE_PIN AK25 IOSTANDARD LVCMOS25} [get_ports gpio_bd[4]] ; ## GPIO_SW_LEFT +set_property -dict {PACKAGE_PIN K15 IOSTANDARD LVCMOS15} [get_ports gpio_bd[5]] ; ## GPIO_SW_CENTER +set_property -dict {PACKAGE_PIN R27 IOSTANDARD LVCMOS25} [get_ports gpio_bd[6]] ; ## GPIO_SW_RIGHT + +set_property -dict {PACKAGE_PIN Y21 IOSTANDARD LVCMOS25} [get_ports gpio_bd[7]] ; ## GPIO_LED_LEFT +set_property -dict {PACKAGE_PIN G2 IOSTANDARD LVCMOS15} [get_ports gpio_bd[8]] ; ## GPIO_LED_CENTER +set_property -dict {PACKAGE_PIN W21 IOSTANDARD LVCMOS25} [get_ports gpio_bd[9]] ; ## GPIO_LED_RIGHT +set_property -dict {PACKAGE_PIN A17 IOSTANDARD LVCMOS15} [get_ports gpio_bd[10]] ; ## GPIO_LED_0 + +set_property -dict {PACKAGE_PIN H14 IOSTANDARD LVCMOS15} [get_ports gpio_bd[11]] ; ## XADC_GPIO_0 +set_property -dict {PACKAGE_PIN J15 IOSTANDARD LVCMOS15} [get_ports gpio_bd[12]] ; ## XADC_GPIO_1 +set_property -dict {PACKAGE_PIN J16 IOSTANDARD LVCMOS15} [get_ports gpio_bd[13]] ; ## XADC_GPIO_2 +set_property -dict {PACKAGE_PIN J14 IOSTANDARD LVCMOS15} [get_ports gpio_bd[14]] ; ## XADC_GPIO_3 + diff --git a/projects/imageon/zc706/system_project.tcl b/projects/imageon/zc706/system_project.tcl index 18329559e..6f00db4d7 100644 --- a/projects/imageon/zc706/system_project.tcl +++ b/projects/imageon/zc706/system_project.tcl @@ -7,12 +7,8 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl adi_project_create imageon_zc706 adi_project_files imageon_zc706 [list \ "system_top.v" \ - "$ad_hdl_dir/library/common/ad_iobuf.v" \ - "system_constr.xdc" \ - "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc"] - -set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc] -set_property PROCESSING_ORDER EARLY [get_files system_constr.xdc] + "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \ + "system_constr.xdc" ] adi_project_run imageon_zc706 diff --git a/projects/imageon/zc706/system_top.v b/projects/imageon/zc706/system_top.v index f8a26049e..6d3b3318e 100644 --- a/projects/imageon/zc706/system_top.v +++ b/projects/imageon/zc706/system_top.v @@ -34,8 +34,6 @@ // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // *************************************************************************** // *************************************************************************** -// *************************************************************************** -// *************************************************************************** `timescale 1ns/100ps @@ -66,14 +64,6 @@ module system_top ( gpio_bd, - hdmi_out_clk, - hdmi_vsync, - hdmi_hsync, - hdmi_data_e, - hdmi_data, - - spdif, - iic_scl, iic_sda, @@ -115,14 +105,6 @@ module system_top ( inout [14:0] gpio_bd; - output hdmi_out_clk; - output hdmi_vsync; - output hdmi_hsync; - output hdmi_data_e; - output [23:0] hdmi_data; - - output spdif; - inout iic_scl; inout iic_sda; @@ -145,28 +127,16 @@ module system_top ( wire [63:0] gpio_o; wire [63:0] gpio_t; - // base hdmi - - assign hdmi_out_clk = 1'd0; - assign hdmi_vsync = 1'd0; - assign hdmi_hsync = 1'd0; - assign hdmi_data_e = 1'd0; - assign hdmi_data = 24'd0; - assign spdif = 1'd0; + assign gpio_i[63:34] = gpio_o[63:34]; + assign gpio_i[31:15] = gpio_o[31:15]; // instantiations - ad_iobuf #(.DATA_WIDTH(1)) i_gpio_hdmi_iic_rstn ( - .dio_t (gpio_t[33]), - .dio_i (gpio_o[33]), - .dio_o (gpio_i[33]), - .dio_p (hdmi_iic_rstn)); - - ad_iobuf #(.DATA_WIDTH(1)) i_gpio_hdmi ( - .dio_t (gpio_t[32]), - .dio_i (gpio_o[32]), - .dio_o (gpio_i[32]), - .dio_p (hdmi_rx_int)); + ad_iobuf #(.DATA_WIDTH(2)) i_gpio ( + .dio_t (gpio_t[33:32]), + .dio_i (gpio_o[33:32]), + .dio_o (gpio_i[33:32]), + .dio_p ({hdmi_iic_rstn, hdmi_rx_int})); ad_iobuf #(.DATA_WIDTH(15)) i_gpio_bd ( .dio_t (gpio_t[14:0]), @@ -199,14 +169,10 @@ module system_top ( .gpio_i (gpio_i), .gpio_o (gpio_o), .gpio_t (gpio_t), - .hdmi_data (), - .hdmi_data_e (), - .hdmi_es_data (hdmi_tx_data), - .hdmi_hsync (), - .hdmi_out_clk (hdmi_tx_clk), .hdmi_rx_clk (hdmi_rx_clk), .hdmi_rx_data (hdmi_rx_data), - .hdmi_vsync (), + .hdmi_tx_clk (hdmi_tx_clk), + .hdmi_tx_data (hdmi_tx_data), .iic_imageon_scl_io (hdmi_iic_scl), .iic_imageon_sda_io (hdmi_iic_sda), .iic_main_scl_io (iic_scl), @@ -223,14 +189,14 @@ module system_top ( .ps_intr_09 (1'b0), .ps_intr_10 (1'b0), .ps_intr_13 (1'b0), - .spdif (hdmi_tx_spdif), .spdif_rx (hdmi_rx_spdif), + .spdif_tx (hdmi_tx_spdif), .spi0_clk_i (1'b0), .spi0_clk_o (), .spi0_csn_0_o (), .spi0_csn_1_o (), .spi0_csn_2_o (), - .spi0_csn_i (1'b0), + .spi0_csn_i (1'b1), .spi0_sdi_i (1'b0), .spi0_sdo_i (1'b0), .spi0_sdo_o (), @@ -239,7 +205,7 @@ module system_top ( .spi1_csn_0_o (), .spi1_csn_1_o (), .spi1_csn_2_o (), - .spi1_csn_i (1'b0), + .spi1_csn_i (1'b1), .spi1_sdi_i (1'b0), .spi1_sdo_i (1'b0), .spi1_sdo_o ()); diff --git a/projects/imageon/zed/Makefile b/projects/imageon/zed/Makefile index 1148228ee..29e292c86 100644 --- a/projects/imageon/zed/Makefile +++ b/projects/imageon/zed/Makefile @@ -13,9 +13,8 @@ M_DEPS += ../common/imageon_bd.tcl M_DEPS += ../../scripts/adi_project.tcl M_DEPS += ../../scripts/adi_env.tcl M_DEPS += ../../scripts/adi_board.tcl -M_DEPS += ../../common/zed/zed_system_constr.xdc M_DEPS += ../../common/zed/zed_system_bd.tcl -M_DEPS += ../../../library/common/ad_iobuf.v +M_DEPS += ../../../library/xilinx/common/ad_iobuf.v M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr M_DEPS += ../../../library/axi_hdmi_rx/axi_hdmi_rx.xpr @@ -39,6 +38,7 @@ M_FLIST += *.sdk M_FLIST += *.hw M_FLIST += *.sim M_FLIST += .Xil +M_FLIST += *.ip_user_files @@ -62,7 +62,7 @@ clean-all:clean imageon_zed.sdk/system_top.hdf: $(M_DEPS) - rm -rf $(M_FLIST) + -rm -rf $(M_FLIST) $(M_VIVADO) system_project.tcl >> imageon_zed_vivado.log 2>&1 diff --git a/projects/imageon/zed/system_constr.xdc b/projects/imageon/zed/system_constr.xdc index 124112969..f483e514e 100644 --- a/projects/imageon/zed/system_constr.xdc +++ b/projects/imageon/zed/system_constr.xdc @@ -2,6 +2,7 @@ # fmc hdmi rx (adv7611) set_property -dict {PACKAGE_PIN D18 IOSTANDARD LVCMOS25} [get_ports hdmi_rx_clk] ; ## G2 FMC_LPC_CLK1_M2C_P +set_property -dict {PACKAGE_PIN A19 IOSTANDARD LVCMOS25} [get_ports hdmi_rx_spdif] ; ## H29 FMC_LPC_LA24_N set_property -dict {PACKAGE_PIN A17 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports hdmi_rx_data[0]] ; ## H32 FMC_LPC_LA28_N set_property -dict {PACKAGE_PIN A16 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports hdmi_rx_data[1]] ; ## H31 FMC_LPC_LA28_P set_property -dict {PACKAGE_PIN C18 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports hdmi_rx_data[2]] ; ## G31 FMC_LPC_LA29_N @@ -49,5 +50,65 @@ set_property -dict {PACKAGE_PIN N20 IOSTANDARD LVCMOS25} [get_ports hd # clock definition -create_clock -period 6.66667 -name hdmi_rx_clk [get_ports hdmi_rx_clk] +create_clock -period 6.000 -name hdmi_rx_clk [get_ports hdmi_rx_clk] + +# i2s + +set_property -dict {PACKAGE_PIN AB2 IOSTANDARD LVCMOS33} [get_ports i2s_mclk] +set_property -dict {PACKAGE_PIN AA6 IOSTANDARD LVCMOS33} [get_ports i2s_bclk] +set_property -dict {PACKAGE_PIN Y6 IOSTANDARD LVCMOS33} [get_ports i2s_lrclk] +set_property -dict {PACKAGE_PIN Y8 IOSTANDARD LVCMOS33} [get_ports i2s_sdata_out] +set_property -dict {PACKAGE_PIN AA7 IOSTANDARD LVCMOS33} [get_ports i2s_sdata_in] + +# iic + +set_property -dict {PACKAGE_PIN R7 IOSTANDARD LVCMOS33} [get_ports iic_scl] +set_property -dict {PACKAGE_PIN U7 IOSTANDARD LVCMOS33} [get_ports iic_sda] +set_property -dict {PACKAGE_PIN AA18 IOSTANDARD LVCMOS33 PULLTYPE PULLUP} [get_ports iic_mux_scl[1]] +set_property -dict {PACKAGE_PIN Y16 IOSTANDARD LVCMOS33 PULLTYPE PULLUP} [get_ports iic_mux_sda[1]] +set_property -dict {PACKAGE_PIN AB4 IOSTANDARD LVCMOS33 PULLTYPE PULLUP} [get_ports iic_mux_scl[0]] +set_property -dict {PACKAGE_PIN AB5 IOSTANDARD LVCMOS33 PULLTYPE PULLUP} [get_ports iic_mux_sda[0]] + +# otg + +set_property -dict {PACKAGE_PIN L16 IOSTANDARD LVCMOS25} [get_ports otg_vbusoc] + +# gpio (switches, leds and such) + +set_property -dict {PACKAGE_PIN P16 IOSTANDARD LVCMOS25} [get_ports gpio_bd[0]] ; ## BTNC +set_property -dict {PACKAGE_PIN R16 IOSTANDARD LVCMOS25} [get_ports gpio_bd[1]] ; ## BTND +set_property -dict {PACKAGE_PIN N15 IOSTANDARD LVCMOS25} [get_ports gpio_bd[2]] ; ## BTNL +set_property -dict {PACKAGE_PIN R18 IOSTANDARD LVCMOS25} [get_ports gpio_bd[3]] ; ## BTNR +set_property -dict {PACKAGE_PIN T18 IOSTANDARD LVCMOS25} [get_ports gpio_bd[4]] ; ## BTNU +set_property -dict {PACKAGE_PIN U10 IOSTANDARD LVCMOS33} [get_ports gpio_bd[5]] ; ## OLED-DC +set_property -dict {PACKAGE_PIN U9 IOSTANDARD LVCMOS33} [get_ports gpio_bd[6]] ; ## OLED-RES +set_property -dict {PACKAGE_PIN AB12 IOSTANDARD LVCMOS33} [get_ports gpio_bd[7]] ; ## OLED-SCLK +set_property -dict {PACKAGE_PIN AA12 IOSTANDARD LVCMOS33} [get_ports gpio_bd[8]] ; ## OLED-SDIN +set_property -dict {PACKAGE_PIN U11 IOSTANDARD LVCMOS33} [get_ports gpio_bd[9]] ; ## OLED-VBAT +set_property -dict {PACKAGE_PIN U12 IOSTANDARD LVCMOS33} [get_ports gpio_bd[10]] ; ## OLED-VDD + +set_property -dict {PACKAGE_PIN F22 IOSTANDARD LVCMOS25} [get_ports gpio_bd[11]] ; ## SW0 +set_property -dict {PACKAGE_PIN G22 IOSTANDARD LVCMOS25} [get_ports gpio_bd[12]] ; ## SW1 +set_property -dict {PACKAGE_PIN H22 IOSTANDARD LVCMOS25} [get_ports gpio_bd[13]] ; ## SW2 +set_property -dict {PACKAGE_PIN F21 IOSTANDARD LVCMOS25} [get_ports gpio_bd[14]] ; ## SW3 +set_property -dict {PACKAGE_PIN H19 IOSTANDARD LVCMOS25} [get_ports gpio_bd[15]] ; ## SW4 +set_property -dict {PACKAGE_PIN H18 IOSTANDARD LVCMOS25} [get_ports gpio_bd[16]] ; ## SW5 +set_property -dict {PACKAGE_PIN H17 IOSTANDARD LVCMOS25} [get_ports gpio_bd[17]] ; ## SW6 +set_property -dict {PACKAGE_PIN M15 IOSTANDARD LVCMOS25} [get_ports gpio_bd[18]] ; ## SW7 + +set_property -dict {PACKAGE_PIN T22 IOSTANDARD LVCMOS33} [get_ports gpio_bd[19]] ; ## LD0 +set_property -dict {PACKAGE_PIN T21 IOSTANDARD LVCMOS33} [get_ports gpio_bd[20]] ; ## LD1 +set_property -dict {PACKAGE_PIN U22 IOSTANDARD LVCMOS33} [get_ports gpio_bd[21]] ; ## LD2 +set_property -dict {PACKAGE_PIN U21 IOSTANDARD LVCMOS33} [get_ports gpio_bd[22]] ; ## LD3 +set_property -dict {PACKAGE_PIN V22 IOSTANDARD LVCMOS33} [get_ports gpio_bd[23]] ; ## LD4 +set_property -dict {PACKAGE_PIN W22 IOSTANDARD LVCMOS33} [get_ports gpio_bd[24]] ; ## LD5 +set_property -dict {PACKAGE_PIN U19 IOSTANDARD LVCMOS33} [get_ports gpio_bd[25]] ; ## LD6 +set_property -dict {PACKAGE_PIN U14 IOSTANDARD LVCMOS33} [get_ports gpio_bd[26]] ; ## LD7 + +set_property -dict {PACKAGE_PIN H15 IOSTANDARD LVCMOS25} [get_ports gpio_bd[27]] ; ## XADC-GIO0 +set_property -dict {PACKAGE_PIN R15 IOSTANDARD LVCMOS25} [get_ports gpio_bd[28]] ; ## XADC-GIO1 +set_property -dict {PACKAGE_PIN K15 IOSTANDARD LVCMOS25} [get_ports gpio_bd[29]] ; ## XADC-GIO2 +set_property -dict {PACKAGE_PIN J15 IOSTANDARD LVCMOS25} [get_ports gpio_bd[30]] ; ## XADC-GIO3 + +set_property -dict {PACKAGE_PIN G17 IOSTANDARD LVCMOS25} [get_ports gpio_bd[31]] ; ## OTG-RESETN diff --git a/projects/imageon/zed/system_project.tcl b/projects/imageon/zed/system_project.tcl index b33d46487..52944cc17 100644 --- a/projects/imageon/zed/system_project.tcl +++ b/projects/imageon/zed/system_project.tcl @@ -7,12 +7,8 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl adi_project_create imageon_zed adi_project_files imageon_zed [list \ "system_top.v" \ - "$ad_hdl_dir/library/common/ad_iobuf.v" \ - "system_constr.xdc" \ - "$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc"] - -set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/zed/zed_system_constr.xdc] -set_property PROCESSING_ORDER EARLY [get_files system_constr.xdc] + "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \ + "system_constr.xdc"] adi_project_run imageon_zed diff --git a/projects/imageon/zed/system_top.v b/projects/imageon/zed/system_top.v index 80b6e87b0..79a80762d 100644 --- a/projects/imageon/zed/system_top.v +++ b/projects/imageon/zed/system_top.v @@ -66,20 +66,12 @@ module system_top ( gpio_bd, - hdmi_out_clk, - hdmi_vsync, - hdmi_hsync, - hdmi_data_e, - hdmi_data, - i2s_mclk, i2s_bclk, i2s_lrclk, i2s_sdata_out, i2s_sdata_in, - spdif, - iic_scl, iic_sda, iic_mux_scl, @@ -88,6 +80,7 @@ module system_top ( hdmi_rx_clk, hdmi_rx_data, hdmi_rx_int, + hdmi_rx_spdif, hdmi_tx_clk, hdmi_tx_data, @@ -124,14 +117,6 @@ module system_top ( inout [31:0] gpio_bd; - output hdmi_out_clk; - output hdmi_vsync; - output hdmi_hsync; - output hdmi_data_e; - output [15:0] hdmi_data; - - output spdif; - output i2s_mclk; output i2s_bclk; output i2s_lrclk; @@ -147,6 +132,7 @@ module system_top ( input hdmi_rx_clk; input [15:0] hdmi_rx_data; inout hdmi_rx_int; + input hdmi_rx_spdif; output hdmi_tx_clk; output [15:0] hdmi_tx_data; @@ -170,28 +156,15 @@ module system_top ( wire [ 1:0] iic_mux_sda_o_s; wire iic_mux_sda_t_s; - // base hdmi - - assign hdmi_out_clk = 1'd0; - assign hdmi_vsync = 1'd0; - assign hdmi_hsync = 1'd0; - assign hdmi_data_e = 1'd0; - assign hdmi_data = 24'd0; - assign spdif = 1'd0; + assign gpio_i[63:34] = gpio_o[63:34]; // instantiations - ad_iobuf #(.DATA_WIDTH(1)) i_gpio_hdmi_iic_rstn ( - .dio_t (gpio_t[33]), - .dio_i (gpio_o[33]), - .dio_o (gpio_i[33]), - .dio_p (hdmi_iic_rstn)); - - ad_iobuf #(.DATA_WIDTH(1)) i_gpio_hdmi ( - .dio_t (gpio_t[32]), - .dio_i (gpio_o[32]), - .dio_o (gpio_i[32]), - .dio_p (hdmi_rx_int)); + ad_iobuf #(.DATA_WIDTH(2)) i_gpio ( + .dio_t (gpio_t[33:32]), + .dio_i (gpio_o[33:32]), + .dio_o (gpio_i[33:32]), + .dio_p ({hdmi_iic_rstn, hdmi_rx_int})); ad_iobuf #( .DATA_WIDTH(32) @@ -242,14 +215,10 @@ module system_top ( .gpio_i (gpio_i), .gpio_o (gpio_o), .gpio_t (gpio_t), - .hdmi_data (), - .hdmi_data_e (), - .hdmi_es_data (hdmi_tx_data), - .hdmi_hsync (), - .hdmi_out_clk (hdmi_tx_clk), .hdmi_rx_clk (hdmi_rx_clk), .hdmi_rx_data (hdmi_rx_data), - .hdmi_vsync (), + .hdmi_tx_clk (hdmi_tx_clk), + .hdmi_tx_data (hdmi_tx_data), .iic_imageon_scl_io (hdmi_iic_scl), .iic_imageon_sda_io (hdmi_iic_sda), .i2s_bclk (i2s_bclk), @@ -278,13 +247,14 @@ module system_top ( .ps_intr_10 (1'b0), .ps_intr_13 (1'b0), .otg_vbusoc (otg_vbusoc), - .spdif (hdmi_tx_spdif), + .spdif_rx (hdmi_rx_spdif), + .spdif_tx (hdmi_tx_spdif), .spi0_clk_i (1'b0), .spi0_clk_o (), .spi0_csn_0_o (), .spi0_csn_1_o (), .spi0_csn_2_o (), - .spi0_csn_i (1'b0), + .spi0_csn_i (1'b1), .spi0_sdi_i (1'b0), .spi0_sdo_i (1'b0), .spi0_sdo_o (), @@ -293,7 +263,7 @@ module system_top ( .spi1_csn_0_o (), .spi1_csn_1_o (), .spi1_csn_2_o (), - .spi1_csn_i (1'b0), + .spi1_csn_i (1'b1), .spi1_sdi_i (1'b0), .spi1_sdo_i (1'b0), .spi1_sdo_o ()); diff --git a/projects/m2k/Makefile b/projects/m2k/Makefile new file mode 100644 index 000000000..882e9f2ee --- /dev/null +++ b/projects/m2k/Makefile @@ -0,0 +1,24 @@ +#################################################################################### +#################################################################################### +## Copyright 2011(c) Analog Devices, Inc. +## Auto-generated, do not modify! +#################################################################################### +#################################################################################### + +.PHONY: all clean clean-all +all: + -make -C standalone all + -make -C zed all + + +clean: + make -C standalone clean + make -C zed clean + + +clean-all: + make -C standalone clean-all + make -C zed clean-all + +#################################################################################### +#################################################################################### diff --git a/projects/m2k/common/m2k_bd.tcl b/projects/m2k/common/m2k_bd.tcl new file mode 100644 index 000000000..9ced421ff --- /dev/null +++ b/projects/m2k/common/m2k_bd.tcl @@ -0,0 +1,231 @@ + +create_bd_port -dir I -from 15 -to 0 data_i +create_bd_port -dir I -from 1 -to 0 trigger_i + +create_bd_port -dir O -from 15 -to 0 data_o +create_bd_port -dir O -from 15 -to 0 data_t +create_bd_port -dir O -from 1 -to 0 trigger_o +create_bd_port -dir O -from 1 -to 0 trigger_t + +create_bd_port -dir I rx_clk +create_bd_port -dir I rxiq +create_bd_port -dir I -from 11 -to 0 rxd +create_bd_port -dir O tx_clk +create_bd_port -dir O txiq +create_bd_port -dir O -from 11 -to 0 txd + +set clk_generator [create_bd_cell -type ip -vlnv analog.com:user:axi_clkgen:1.0 clk_generator] +set_property -dict [list CONFIG.VCO_DIV {1}] $clk_generator +set_property -dict [list CONFIG.VCO_MUL {8}] $clk_generator +set_property -dict [list CONFIG.CLK0_DIV {10}] $clk_generator +set_property -dict [list CONFIG.CLK1_DIV {5}] $clk_generator +set_property -dict [list CONFIG.CLK0_PHASE {180}] $clk_generator +set_property -dict [list CONFIG.CLK1_PHASE {180}] $clk_generator +set_property -dict [list CONFIG.CLKIN_PERIOD {10}] $clk_generator +set_property -dict [list CONFIG.CLKIN2_PERIOD {12.5}] $clk_generator + +set logic_analyzer [create_bd_cell -type ip -vlnv analog.com:user:axi_logic_analyzer:1.0 logic_analyzer] + +set la_trigger_fifo [create_bd_cell -type ip -vlnv analog.com:user:util_var_fifo:1.0 la_trigger_fifo] +set_property -dict [list CONFIG.DATA_WIDTH {16} ] $la_trigger_fifo +set_property -dict [list CONFIG.ADDRESS_WIDTH {13} ] $la_trigger_fifo + +set logic_analyzer_dmac [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 logic_analyzer_dmac] +set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {16} ] $logic_analyzer_dmac +set_property -dict [list CONFIG.DMA_AXI_PROTOCOL_DEST {1} ] $logic_analyzer_dmac +set_property -dict [list CONFIG.SYNC_TRANSFER_START {true} ] $logic_analyzer_dmac + +set pattern_generator_dmac [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 pattern_generator_dmac] +set_property -dict [list CONFIG.DMA_TYPE_DEST {2} ] $pattern_generator_dmac +set_property -dict [list CONFIG.DMA_TYPE_SRC {0}] $pattern_generator_dmac +set_property -dict [list CONFIG.MAX_BYTES_PER_BURST {32}] $pattern_generator_dmac +set_property -dict [list CONFIG.DMA_AXI_PROTOCOL_SRC {1}] $pattern_generator_dmac +set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {16} ] $pattern_generator_dmac +set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {32}] $pattern_generator_dmac +set_property -dict [list CONFIG.CYCLIC {true}] $pattern_generator_dmac + +set axi_ad9963 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9963:1.0 axi_ad9963] + +set adc_trigger_fifo [create_bd_cell -type ip -vlnv analog.com:user:util_var_fifo:1.0 adc_trigger_fifo] +set_property -dict [list CONFIG.DATA_WIDTH {32} ] $adc_trigger_fifo +set_property -dict [list CONFIG.ADDRESS_WIDTH {13} ] $adc_trigger_fifo + +set adc_trigger_extract [create_bd_cell -type ip -vlnv analog.com:user:util_extract:1.0 adc_trigger_extract] + +set util_cpack_ad9963 [create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 util_cpack_ad9963] +set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $util_cpack_ad9963 +set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {16}] $util_cpack_ad9963 + +set ad9963_adc_dmac [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 ad9963_adc_dmac] +set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {32}] $ad9963_adc_dmac +set_property -dict [list CONFIG.DMA_AXI_PROTOCOL_DEST {1}] $ad9963_adc_dmac +set_property -dict [list CONFIG.SYNC_TRANSFER_START {true}] $ad9963_adc_dmac + +set ad9963_dac_dmac_a [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 ad9963_dac_dmac_a] +set_property -dict [list CONFIG.DMA_TYPE_DEST {2}] $ad9963_dac_dmac_a +set_property -dict [list CONFIG.DMA_TYPE_SRC {0}] $ad9963_dac_dmac_a +set_property -dict [list CONFIG.DMA_AXI_PROTOCOL_SRC {1}] $ad9963_dac_dmac_a +set_property -dict [list CONFIG.MAX_BYTES_PER_BURST {64}] $ad9963_dac_dmac_a +set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {16}] $ad9963_dac_dmac_a +set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {32}] $ad9963_dac_dmac_a +set_property -dict [list CONFIG.CYCLIC {true}] $ad9963_dac_dmac_a + +set ad9963_dac_dmac_b [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 ad9963_dac_dmac_b] +set_property -dict [list CONFIG.DMA_TYPE_DEST {2}] $ad9963_dac_dmac_b +set_property -dict [list CONFIG.DMA_TYPE_SRC {0}] $ad9963_dac_dmac_b +set_property -dict [list CONFIG.DMA_AXI_PROTOCOL_SRC {1}] $ad9963_dac_dmac_b +set_property -dict [list CONFIG.MAX_BYTES_PER_BURST {64}] $ad9963_dac_dmac_b +set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {16}] $ad9963_dac_dmac_b +set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {32}] $ad9963_dac_dmac_a +set_property -dict [list CONFIG.CYCLIC {true}] $ad9963_dac_dmac_b + +set adc_trigger [create_bd_cell -type ip -vlnv analog.com:user:axi_adc_trigger:1.0 adc_trigger] + +set axi_adc_decimate [create_bd_cell -type ip -vlnv analog.com:user:axi_adc_decimate:1.0 axi_adc_decimate] +set axi_dac_interpolate [create_bd_cell -type ip -vlnv analog.com:user:axi_dac_interpolate:1.0 axi_dac_interpolate] + +set logic_analyzer_reset [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 logic_analyzer_reset] + + +ad_connect data_i logic_analyzer/data_i +ad_connect trigger_i logic_analyzer/trigger_i +ad_connect data_o logic_analyzer/data_o +ad_connect data_t logic_analyzer/data_t + +ad_connect sys_cpu_clk clk_generator/clk +#ad_connect logic_analyzer/clk_out clk_generator/clk2 + +ad_connect logic_analyzer/clk clk_generator/clk_0 + +ad_connect pattern_generator_dmac/fifo_rd_clk clk_generator/clk_0 + +ad_connect clk_generator/clk_0 la_trigger_fifo/clk +ad_connect logic_analyzer_dmac/fifo_wr_clk clk_generator/clk_0 +ad_connect logic_analyzer_reset/slowest_sync_clk clk_generator/clk_0 +ad_connect logic_analyzer_reset/ext_reset_in sys_rstgen/peripheral_aresetn +ad_connect logic_analyzer_reset/bus_struct_reset la_trigger_fifo/rst + +ad_connect la_trigger_fifo/data_in logic_analyzer/adc_data +ad_connect la_trigger_fifo/data_in_valid logic_analyzer/adc_valid + +ad_connect logic_analyzer_dmac/fifo_wr_din la_trigger_fifo/data_out +ad_connect logic_analyzer_dmac/fifo_wr_en la_trigger_fifo/data_out_valid + +ad_connect logic_analyzer/trigger_offset la_trigger_fifo/depth + +ad_connect logic_analyzer/trigger_out logic_analyzer_dmac/fifo_wr_sync + +ad_connect pattern_generator_dmac/fifo_rd_en logic_analyzer/dac_read +ad_connect pattern_generator_dmac/fifo_rd_dout logic_analyzer/dac_data +ad_connect pattern_generator_dmac/fifo_rd_valid logic_analyzer/dac_valid + + +ad_connect sys_cpu_clk logic_analyzer/s_axi_aclk +ad_connect sys_cpu_resetn logic_analyzer/s_axi_aresetn + +ad_connect sys_200m_clk axi_ad9963/delay_clk + +ad_connect axi_ad9963/l_clk adc_trigger_fifo/clk +ad_connect axi_ad9963/l_clk util_cpack_ad9963/adc_clk +ad_connect axi_adc_decimate/adc_clk axi_ad9963/l_clk +ad_connect adc_trigger_extract/clk axi_ad9963/l_clk +ad_connect ad9963_adc_dmac/fifo_wr_clk axi_ad9963/l_clk + +ad_connect axi_ad9963/rst util_cpack_ad9963/adc_rst +ad_connect axi_ad9963/rst adc_trigger_fifo/rst + +ad_connect axi_adc_decimate/adc_data_a axi_ad9963/adc_data_i +ad_connect axi_adc_decimate/adc_data_b axi_ad9963/adc_data_q +ad_connect axi_adc_decimate/adc_valid_a axi_ad9963/adc_valid_i +ad_connect axi_adc_decimate/adc_valid_b axi_ad9963/adc_valid_q + +ad_connect axi_ad9963/adc_enable_i util_cpack_ad9963/adc_enable_0 +ad_connect adc_trigger/data_valid_a_trig util_cpack_ad9963/adc_valid_0 +ad_connect adc_trigger/data_a_trig util_cpack_ad9963/adc_data_0 +ad_connect axi_ad9963/adc_enable_q util_cpack_ad9963/adc_enable_1 +ad_connect adc_trigger/data_valid_b_trig util_cpack_ad9963/adc_valid_1 +ad_connect adc_trigger/data_b_trig util_cpack_ad9963/adc_data_1 + +ad_connect adc_trigger_fifo/data_in util_cpack_ad9963/adc_data +ad_connect adc_trigger_fifo/data_in_valid util_cpack_ad9963/adc_valid +ad_connect adc_trigger_fifo/depth adc_trigger/trigger_offset + +ad_connect adc_trigger_fifo/data_out adc_trigger_extract/data_in +ad_connect adc_trigger_fifo/data_out_valid adc_trigger_extract/data_valid +ad_connect util_cpack_ad9963/adc_data adc_trigger_extract/data_in_trigger + +ad_connect adc_trigger_extract/data_out ad9963_adc_dmac/fifo_wr_din +ad_connect adc_trigger_extract/trigger_out ad9963_adc_dmac/fifo_wr_sync +ad_connect adc_trigger_fifo/data_out_valid ad9963_adc_dmac/fifo_wr_en + +ad_connect axi_dac_interpolate/dac_clk axi_ad9963/dac_clk + +ad_connect axi_dac_interpolate/dac_valid_a axi_ad9963/dac_valid_i +ad_connect axi_dac_interpolate/dac_valid_b axi_ad9963/dac_valid_q +ad_connect axi_dac_interpolate/dac_int_data_a axi_ad9963/dac_data_i +ad_connect axi_dac_interpolate/dac_int_data_b axi_ad9963/dac_data_q + +ad_connect ad9963_dac_dmac_a/fifo_rd_clk axi_ad9963/dac_clk +ad_connect ad9963_dac_dmac_b/fifo_rd_clk axi_ad9963/dac_clk + +ad_connect axi_dac_interpolate/dac_data_a ad9963_dac_dmac_a/fifo_rd_dout +ad_connect axi_dac_interpolate/dac_int_valid_a ad9963_dac_dmac_a/fifo_rd_en +ad_connect axi_dac_interpolate/dac_data_b ad9963_dac_dmac_b/fifo_rd_dout +ad_connect axi_dac_interpolate/dac_int_valid_b ad9963_dac_dmac_b/fifo_rd_en + +ad_connect /axi_ad9963/tx_data txd +ad_connect /axi_ad9963/tx_iq txiq +ad_connect /axi_ad9963/tx_clk tx_clk +ad_connect /axi_ad9963/trx_data rxd +ad_connect /axi_ad9963/trx_clk rx_clk +ad_connect /axi_ad9963/trx_iq rxiq + +ad_connect adc_trigger/data_a axi_adc_decimate/adc_dec_data_a +ad_connect adc_trigger/data_valid_a axi_adc_decimate/adc_dec_valid_a +ad_connect adc_trigger/data_b axi_adc_decimate/adc_dec_data_b +ad_connect adc_trigger/data_valid_b axi_adc_decimate/adc_dec_valid_b + +ad_connect adc_trigger/clk axi_ad9963/l_clk +ad_connect trigger_i adc_trigger/trigger_i +ad_connect trigger_o adc_trigger/trigger_o +ad_connect trigger_t adc_trigger/trigger_t + +ad_connect axi_ad9963/dac_sync_in axi_ad9963/dac_sync_out +ad_connect axi_ad9963/adc_dovf ad9963_adc_dmac/fifo_wr_overflow +ad_connect axi_ad9963/dac_dunf ad9963_dac_dmac_a/fifo_rd_underflow + +# interconnects + +ad_cpu_interconnect 0x70000000 clk_generator +ad_cpu_interconnect 0x70100000 logic_analyzer +ad_cpu_interconnect 0x70200000 axi_ad9963 +ad_cpu_interconnect 0x7C400000 logic_analyzer_dmac +ad_cpu_interconnect 0x7C420000 pattern_generator_dmac +ad_cpu_interconnect 0x7C440000 ad9963_adc_dmac +ad_cpu_interconnect 0x7C460000 ad9963_dac_dmac_b +ad_cpu_interconnect 0x7C480000 ad9963_dac_dmac_a +ad_cpu_interconnect 0x7C4c0000 adc_trigger +ad_cpu_interconnect 0x7C500000 axi_adc_decimate +ad_cpu_interconnect 0x7C5a0000 axi_dac_interpolate + +ad_mem_hp1_interconnect sys_cpu_clk sys_ps7/S_AXI_HP1 +ad_mem_hp1_interconnect sys_cpu_clk logic_analyzer_dmac/m_dest_axi +ad_mem_hp1_interconnect sys_cpu_clk pattern_generator_dmac/m_src_axi +ad_mem_hp2_interconnect sys_cpu_clk sys_ps7/S_AXI_HP2 +ad_mem_hp2_interconnect sys_cpu_clk ad9963_adc_dmac/m_dest_axi +ad_mem_hp2_interconnect sys_cpu_clk ad9963_dac_dmac_a/m_src_axi +ad_mem_hp2_interconnect sys_cpu_clk ad9963_dac_dmac_b/m_src_axi +ad_connect sys_cpu_resetn logic_analyzer_dmac/m_dest_axi_aresetn +ad_connect sys_cpu_resetn pattern_generator_dmac/m_src_axi_aresetn +ad_connect sys_cpu_resetn ad9963_adc_dmac/m_dest_axi_aresetn +ad_connect sys_cpu_resetn ad9963_dac_dmac_a/m_src_axi_aresetn +ad_connect sys_cpu_resetn ad9963_dac_dmac_b/m_src_axi_aresetn + +# interrupts + +ad_cpu_interrupt ps-13 mb-12 logic_analyzer_dmac/irq +ad_cpu_interrupt ps-12 mb-13 pattern_generator_dmac/irq +ad_cpu_interrupt ps-10 mb-14 ad9963_adc_dmac/irq +ad_cpu_interrupt ps-9 mb-15 ad9963_dac_dmac_a/irq +ad_cpu_interrupt ps-8 mb-16 ad9963_dac_dmac_b/irq + diff --git a/projects/fmcomms6/common/fmcomms6_spi.v b/projects/m2k/common/m2k_spi.v similarity index 76% rename from projects/fmcomms6/common/fmcomms6_spi.v rename to projects/m2k/common/m2k_spi.v index bc1fd2cd1..d7bcc9280 100644 --- a/projects/fmcomms6/common/fmcomms6_spi.v +++ b/projects/m2k/common/m2k_spi.v @@ -1,9 +1,9 @@ // *************************************************************************** // *************************************************************************** // Copyright 2011(c) Analog Devices, Inc. -// +// // All rights reserved. -// +// // Redistribution and use in source and binary forms, with or without modification, // are permitted provided that the following conditions are met: // - Redistributions of source code must retain the above copyright @@ -21,41 +21,35 @@ // patent holders to use this software. // - Use of the software either in source or binary form, must be run // on or directly connected to an Analog Devices Inc. component. -// +// // THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, // INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A // PARTICULAR PURPOSE ARE DISCLAIMED. // // IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, // EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY -// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR // BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // *************************************************************************** // *************************************************************************** `timescale 1ns/100ps -module fmcomms6_spi ( +module m2k_spi ( - spi_csn, - spi_clk, - spi_mosi, - spi_miso, + // 4-wire - spi_sdio); + input ad9963_csn, + input adf4360_cs, + input spi_clk, + input spi_mosi, + output spi_miso, - // 4 wire + // 3-wire - input [ 2:0] spi_csn; - input spi_clk; - input spi_mosi; - output spi_miso; - - // 3 wire - - inout spi_sdio; + inout spi_sdio); // internal registers @@ -63,45 +57,34 @@ module fmcomms6_spi ( reg spi_rd_wr_n = 'd0; reg spi_enable = 'd0; - // internal signals - - wire spi_csn_s; - wire spi_enable_s; - // check on rising edge and change on falling edge - assign spi_csn_s = & spi_csn; - assign spi_enable_s = spi_enable & ~spi_csn_s; - - always @(posedge spi_clk or posedge spi_csn_s) begin - if (spi_csn_s == 1'b1) begin + always @(posedge spi_clk or posedge ad9963_csn) begin + if (ad9963_csn == 1'b1) begin spi_count <= 6'd0; spi_rd_wr_n <= 1'd0; end else begin - spi_count <= (spi_count < 6'h3f) ? spi_count + 1'b1 : spi_count; + spi_count <= spi_count + 1'b1; if (spi_count == 6'd0) begin spi_rd_wr_n <= spi_mosi; end end end - always @(negedge spi_clk or posedge spi_csn_s) begin - if (spi_csn_s == 1'b1) begin + always @(negedge spi_clk or posedge ad9963_csn) begin + if (ad9963_csn == 1'b1) begin spi_enable <= 1'b0; end else begin - if ((spi_count == 6'd16) && (spi_csn[2] == 1'b1)) begin + if ((spi_count == 6'd16) && (ad9963_csn == 1'b0)) begin spi_enable <= spi_rd_wr_n; end end end - // io butter + // io buffers - IOBUF i_iobuf_sdio ( - .T (spi_enable_s), - .I (spi_mosi), - .O (spi_miso), - .IO (spi_sdio)); + assign spi_miso = spi_sdio; + assign spi_sdio = (spi_enable == 1'b1) ? 1'bz : spi_mosi; endmodule diff --git a/projects/m2k/standalone/Makefile b/projects/m2k/standalone/Makefile new file mode 100644 index 000000000..3caeff064 --- /dev/null +++ b/projects/m2k/standalone/Makefile @@ -0,0 +1,86 @@ +#################################################################################### +#################################################################################### +## Copyright 2011(c) Analog Devices, Inc. +## Auto-generated, do not modify! +#################################################################################### +#################################################################################### + +M_DEPS += system_top.v +M_DEPS += system_project.tcl +M_DEPS += system_constr.xdc +M_DEPS += system_bd.tcl +M_DEPS += ../common/m2k_spi.v +M_DEPS += ../common/m2k_bd.tcl +M_DEPS += ../../scripts/adi_project.tcl +M_DEPS += ../../scripts/adi_env.tcl +M_DEPS += ../../scripts/adi_board.tcl +M_DEPS += ../../../library/xilinx/common/ad_iobuf.v +M_DEPS += ../../../library/axi_ad9963/axi_ad9963.xpr +M_DEPS += ../../../library/axi_adc_decimate/axi_adc_decimate.xpr +M_DEPS += ../../../library/axi_adc_trigger/axi_adc_trigger.xpr +M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr +M_DEPS += ../../../library/axi_dac_interpolate/axi_dac_interpolate.xpr +M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr +M_DEPS += ../../../library/axi_logic_analyzer/axi_logic_analyzer.xpr +M_DEPS += ../../../library/util_cpack/util_cpack.xpr +M_DEPS += ../../../library/util_extract/util_extract.xpr +M_DEPS += ../../../library/util_var_fifo/util_var_fifo.xpr + +M_VIVADO := vivado -mode batch -source + +M_FLIST := *.cache +M_FLIST += *.data +M_FLIST += *.xpr +M_FLIST += *.log +M_FLIST += *.jou +M_FLIST += xgui +M_FLIST += *.runs +M_FLIST += *.srcs +M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim +M_FLIST += .Xil +M_FLIST += *.ip_user_files + + + +.PHONY: all lib clean clean-all +all: lib m2k.sdk/system_top.hdf + + +clean: + rm -rf $(M_FLIST) + + +clean-all:clean + make -C ../../../library/axi_ad9963 clean + make -C ../../../library/axi_adc_decimate clean + make -C ../../../library/axi_adc_trigger clean + make -C ../../../library/axi_clkgen clean + make -C ../../../library/axi_dac_interpolate clean + make -C ../../../library/axi_dmac clean + make -C ../../../library/axi_logic_analyzer clean + make -C ../../../library/util_cpack clean + make -C ../../../library/util_extract clean + make -C ../../../library/util_var_fifo clean + + +m2k.sdk/system_top.hdf: $(M_DEPS) + -rm -rf $(M_FLIST) + $(M_VIVADO) system_project.tcl >> m2k_vivado.log 2>&1 + + +lib: + make -C ../../../library/axi_ad9963 + make -C ../../../library/axi_adc_decimate + make -C ../../../library/axi_adc_trigger + make -C ../../../library/axi_clkgen + make -C ../../../library/axi_dac_interpolate + make -C ../../../library/axi_dmac + make -C ../../../library/axi_logic_analyzer + make -C ../../../library/util_cpack + make -C ../../../library/util_extract + make -C ../../../library/util_var_fifo + +#################################################################################### +#################################################################################### diff --git a/projects/common/pzsdr/pzsdr_system_bd.tcl b/projects/m2k/standalone/system_bd.tcl similarity index 63% rename from projects/common/pzsdr/pzsdr_system_bd.tcl rename to projects/m2k/standalone/system_bd.tcl index 6c442708f..93f2236af 100644 --- a/projects/common/pzsdr/pzsdr_system_bd.tcl +++ b/projects/m2k/standalone/system_bd.tcl @@ -16,23 +16,9 @@ create_bd_port -dir I spi0_sdo_i create_bd_port -dir O spi0_sdo_o create_bd_port -dir I spi0_sdi_i -create_bd_port -dir O spi1_csn_2_o -create_bd_port -dir O spi1_csn_1_o -create_bd_port -dir O spi1_csn_0_o -create_bd_port -dir I spi1_csn_i -create_bd_port -dir I spi1_clk_i -create_bd_port -dir O spi1_clk_o -create_bd_port -dir I spi1_sdo_i -create_bd_port -dir O spi1_sdo_o -create_bd_port -dir I spi1_sdi_i - -create_bd_port -dir I -from 63 -to 0 gpio_i -create_bd_port -dir O -from 63 -to 0 gpio_o -create_bd_port -dir O -from 63 -to 0 gpio_t - -# otg - -set otg_vbusoc [create_bd_port -dir I otg_vbusoc] +create_bd_port -dir I -from 16 -to 0 gpio_i +create_bd_port -dir O -from 16 -to 0 gpio_o +create_bd_port -dir O -from 16 -to 0 gpio_t # interrupts @@ -55,28 +41,53 @@ create_bd_port -dir I -type intr ps_intr_15 # instance: sys_ps7 set sys_ps7 [create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 sys_ps7] -source $ad_hdl_dir/projects/common/pzsdr/pzsdr_system_ps7.tcl + +set_property -dict [list CONFIG.PCW_PRESET_BANK0_VOLTAGE {LVCMOS 1.8V}] $sys_ps7 +set_property -dict [list CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 1.8V}] $sys_ps7 set_property -dict [list CONFIG.PCW_TTC0_PERIPHERAL_ENABLE {0}] $sys_ps7 +set_property -dict [list CONFIG.PCW_PACKAGE_NAME {clg225}] $sys_ps7 +set_property -dict [list CONFIG.PCW_USE_S_AXI_HP1 {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_USE_S_AXI_HP2 {1}] $sys_ps7 set_property -dict [list CONFIG.PCW_EN_CLK1_PORT {1}] $sys_ps7 set_property -dict [list CONFIG.PCW_EN_RST1_PORT {1}] $sys_ps7 -set_property -dict [list CONFIG.PCW_EN_CLK2_PORT {1}] $sys_ps7 -set_property -dict [list CONFIG.PCW_EN_RST2_PORT {1}] $sys_ps7 set_property -dict [list CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100.0}] $sys_ps7 set_property -dict [list CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ {200.0}] $sys_ps7 -set_property -dict [list CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {200.0}] $sys_ps7 -set_property -dict [list CONFIG.PCW_USE_FABRIC_INTERRUPT {1}] $sys_ps7 -set_property -dict [list CONFIG.PCW_IRQ_F2P_INTR {1}] $sys_ps7 set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {1}] $sys_ps7 -set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_IO {64}] $sys_ps7 -set_property -dict [list CONFIG.PCW_IRQ_F2P_MODE {REVERSE}] $sys_ps7 +set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_IO {17}] $sys_ps7 +set_property -dict [list CONFIG.PCW_SPI1_PERIPHERAL_ENABLE {0}] $sys_ps7 +set_property -dict [list CONFIG.PCW_I2C0_PERIPHERAL_ENABLE {0}] $sys_ps7 +set_property -dict [list CONFIG.PCW_UART1_PERIPHERAL_ENABLE {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_UART1_UART1_IO {MIO 12 .. 13}] $sys_ps7 +set_property -dict [list CONFIG.PCW_I2C1_PERIPHERAL_ENABLE {0}] $sys_ps7 +set_property -dict [list CONFIG.PCW_QSPI_PERIPHERAL_ENABLE {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_SD0_PERIPHERAL_ENABLE {0}] $sys_ps7 set_property -dict [list CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {1}] $sys_ps7 set_property -dict [list CONFIG.PCW_SPI0_SPI0_IO {EMIO}] $sys_ps7 -set_property -dict [list CONFIG.PCW_SPI1_PERIPHERAL_ENABLE {1}] $sys_ps7 -set_property -dict [list CONFIG.PCW_SPI1_SPI1_IO {EMIO}] $sys_ps7 +set_property -dict [list CONFIG.PCW_TTC0_PERIPHERAL_ENABLE {0}] $sys_ps7 +set_property -dict [list CONFIG.PCW_USE_FABRIC_INTERRUPT {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_USB0_PERIPHERAL_ENABLE {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_GPIO_MIO_GPIO_IO {MIO}] $sys_ps7 +set_property -dict [list CONFIG.PCW_USB0_RESET_IO {MIO 52}] $sys_ps7 +set_property -dict [list CONFIG.PCW_USB0_RESET_ENABLE {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_IRQ_F2P_INTR {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_IRQ_F2P_MODE {REVERSE}] $sys_ps7 + +# DDR MT41K256M16 HA-125 (32M, 16bit, 8banks) + +set_property -dict [list CONFIG.PCW_UIPARAM_DDR_PARTNO {MT41K256M16 RE-125}] $sys_ps7 +set_property -dict [list CONFIG.PCW_UIPARAM_DDR_BUS_WIDTH {16 Bit}] $sys_ps7 +set_property -dict [list CONFIG.PCW_UIPARAM_DDR_USE_INTERNAL_VREF {0}] $sys_ps7 +set_property -dict [list CONFIG.PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_UIPARAM_DDR_TRAIN_READ_GATE {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_UIPARAM_DDR_TRAIN_DATA_EYE {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 {0.048}] $sys_ps7 +set_property -dict [list CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 {0.050}] $sys_ps7 +set_property -dict [list CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0 {0.241}] $sys_ps7 +set_property -dict [list CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1 {0.240}] $sys_ps7 set axi_iic_main [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_iic:2.0 axi_iic_main] -set_property -dict [list CONFIG.USE_BOARD_FLOW {true}] $axi_iic_main -set_property -dict [list CONFIG.IIC_BOARD_INTERFACE {Custom}] $axi_iic_main set sys_concat_intc [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 sys_concat_intc] set_property -dict [list CONFIG.NUM_PORTS {16}] $sys_concat_intc @@ -84,10 +95,6 @@ set_property -dict [list CONFIG.NUM_PORTS {16}] $sys_concat_intc set sys_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 sys_rstgen] set_property -dict [list CONFIG.C_EXT_RST_WIDTH {1}] $sys_rstgen -set sys_logic_inv [create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 sys_logic_inv] -set_property -dict [list CONFIG.C_SIZE {1}] $sys_logic_inv -set_property -dict [list CONFIG.C_OPERATION {not}] $sys_logic_inv - # system reset/clock definitions ad_connect sys_cpu_clk sys_ps7/FCLK_CLK0 @@ -105,8 +112,6 @@ ad_connect gpio_o sys_ps7/GPIO_O ad_connect gpio_t sys_ps7/GPIO_T ad_connect fixed_io sys_ps7/FIXED_IO ad_connect iic_main axi_iic_main/iic -ad_connect sys_logic_inv/Res sys_ps7/USB0_VBUS_PWRFAULT -ad_connect sys_logic_inv/Op1 otg_vbusoc # spi connections @@ -120,16 +125,6 @@ ad_connect spi0_sdo_i sys_ps7/SPI0_MOSI_I ad_connect spi0_sdo_o sys_ps7/SPI0_MOSI_O ad_connect spi0_sdi_i sys_ps7/SPI0_MISO_I -ad_connect spi1_csn_2_o sys_ps7/SPI1_SS2_O -ad_connect spi1_csn_1_o sys_ps7/SPI1_SS1_O -ad_connect spi1_csn_0_o sys_ps7/SPI1_SS_O -ad_connect spi1_csn_i sys_ps7/SPI1_SS_I -ad_connect spi1_clk_i sys_ps7/SPI1_SCLK_I -ad_connect spi1_clk_o sys_ps7/SPI1_SCLK_O -ad_connect spi1_sdo_i sys_ps7/SPI1_MOSI_I -ad_connect spi1_sdo_o sys_ps7/SPI1_MOSI_O -ad_connect spi1_sdi_i sys_ps7/SPI1_MISO_I - # interrupts ad_connect sys_concat_intc/dout sys_ps7/IRQ_F2P @@ -154,10 +149,7 @@ ad_connect sys_concat_intc/In0 ps_intr_00 ad_cpu_interconnect 0x41600000 axi_iic_main -# module ad9361 - -source $ad_hdl_dir/projects/common/xilinx/sys_wfifo.tcl -source $ad_hdl_dir/projects/fmcomms2/common/fmcomms2_bd.tcl - -set_property -dict [list CONFIG.DAC_IODELAY_ENABLE {1}] $axi_ad9361 +source ../common/m2k_bd.tcl +set_property -dict [list CONFIG.DAC_DATAPATH_DISABLE {1}] $axi_ad9963 +set_property -dict [list CONFIG.ADC_DATAPATH_DISABLE {1}] $axi_ad9963 diff --git a/projects/m2k/standalone/system_constr.xdc b/projects/m2k/standalone/system_constr.xdc new file mode 100644 index 000000000..ab5624d7c --- /dev/null +++ b/projects/m2k/standalone/system_constr.xdc @@ -0,0 +1,199 @@ + +set_property -dict {PACKAGE_PIN F14 IOSTANDARD LVCMOS33 PULLTYPE PULLUP} [get_ports iic_scl] +set_property -dict {PACKAGE_PIN F13 IOSTANDARD LVCMOS33 PULLTYPE PULLUP} [get_ports iic_sda] + +set_property -dict {PACKAGE_PIN E12 IOSTANDARD LVCMOS33 } [get_ports ad9963_resetn] + +set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVCMOS33} [get_ports adf4360_cs] +set_property -dict {PACKAGE_PIN E11 IOSTANDARD LVCMOS33} [get_ports ad9963_csn] +set_property -dict {PACKAGE_PIN E13 IOSTANDARD LVCMOS33} [get_ports spi_clk] +set_property -dict {PACKAGE_PIN F12 IOSTANDARD LVCMOS33} [get_ports spi_sdio] + +set_property -dict {PACKAGE_PIN F15 IOSTANDARD LVCMOS33} [get_ports en_power_analog] + +set_property -dict {PACKAGE_PIN M12 IOSTANDARD LVCMOS33} [get_ports trigger_bd[0]] +set_property -dict {PACKAGE_PIN N12 IOSTANDARD LVCMOS33} [get_ports trigger_bd[1]] + +set_property -dict {PACKAGE_PIN K11 IOSTANDARD LVCMOS33} [get_ports data_bd[0]] +set_property -dict {PACKAGE_PIN K12 IOSTANDARD LVCMOS33} [get_ports data_bd[1]] +set_property -dict {PACKAGE_PIN K13 IOSTANDARD LVCMOS33} [get_ports data_bd[2]] +set_property -dict {PACKAGE_PIN L13 IOSTANDARD LVCMOS33} [get_ports data_bd[3]] +set_property -dict {PACKAGE_PIN L14 IOSTANDARD LVCMOS33} [get_ports data_bd[4]] +set_property -dict {PACKAGE_PIN M14 IOSTANDARD LVCMOS33} [get_ports data_bd[5]] +set_property -dict {PACKAGE_PIN L15 IOSTANDARD LVCMOS33} [get_ports data_bd[6]] +set_property -dict {PACKAGE_PIN M15 IOSTANDARD LVCMOS33} [get_ports data_bd[7]] +set_property -dict {PACKAGE_PIN N13 IOSTANDARD LVCMOS33} [get_ports data_bd[8]] +set_property -dict {PACKAGE_PIN P14 IOSTANDARD LVCMOS33} [get_ports data_bd[9]] +set_property -dict {PACKAGE_PIN R12 IOSTANDARD LVCMOS33} [get_ports data_bd[10]] +set_property -dict {PACKAGE_PIN R13 IOSTANDARD LVCMOS33} [get_ports data_bd[11]] +set_property -dict {PACKAGE_PIN P11 IOSTANDARD LVCMOS33} [get_ports data_bd[12]] +set_property -dict {PACKAGE_PIN R11 IOSTANDARD LVCMOS33} [get_ports data_bd[13]] +set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS33} [get_ports data_bd[14]] +set_property -dict {PACKAGE_PIN R15 IOSTANDARD LVCMOS33} [get_ports data_bd[15]] + +set_property -dict {PACKAGE_PIN N11 IOSTANDARD LVCMOS33} [get_ports rx_clk] +set_property -dict {PACKAGE_PIN P13 IOSTANDARD LVCMOS33} [get_ports rxiq] +set_property -dict {PACKAGE_PIN P10 IOSTANDARD LVCMOS33} [get_ports rxd[0]] +set_property -dict {PACKAGE_PIN R10 IOSTANDARD LVCMOS33} [get_ports rxd[1]] +set_property -dict {PACKAGE_PIN P8 IOSTANDARD LVCMOS33} [get_ports rxd[2]] +set_property -dict {PACKAGE_PIN P9 IOSTANDARD LVCMOS33} [get_ports rxd[3]] +set_property -dict {PACKAGE_PIN N7 IOSTANDARD LVCMOS33} [get_ports rxd[4]] +set_property -dict {PACKAGE_PIN N8 IOSTANDARD LVCMOS33} [get_ports rxd[5]] +set_property -dict {PACKAGE_PIN M10 IOSTANDARD LVCMOS33} [get_ports rxd[6]] +set_property -dict {PACKAGE_PIN M11 IOSTANDARD LVCMOS33} [get_ports rxd[7]] +set_property -dict {PACKAGE_PIN R7 IOSTANDARD LVCMOS33} [get_ports rxd[8]] +set_property -dict {PACKAGE_PIN R8 IOSTANDARD LVCMOS33} [get_ports rxd[9]] +set_property -dict {PACKAGE_PIN M9 IOSTANDARD LVCMOS33} [get_ports rxd[10]] +set_property -dict {PACKAGE_PIN N9 IOSTANDARD LVCMOS33} [get_ports rxd[11]] + +set_property -dict {PACKAGE_PIN L12 IOSTANDARD LVCMOS33} [get_ports tx_clk] +set_property -dict {PACKAGE_PIN N14 IOSTANDARD LVCMOS33} [get_ports txiq] +set_property -dict {PACKAGE_PIN H12 IOSTANDARD LVCMOS33} [get_ports txd[0]] +set_property -dict {PACKAGE_PIN G11 IOSTANDARD LVCMOS33} [get_ports txd[1]] +set_property -dict {PACKAGE_PIN H13 IOSTANDARD LVCMOS33} [get_ports txd[2]] +set_property -dict {PACKAGE_PIN G12 IOSTANDARD LVCMOS33} [get_ports txd[3]] +set_property -dict {PACKAGE_PIN H14 IOSTANDARD LVCMOS33} [get_ports txd[4]] +set_property -dict {PACKAGE_PIN G14 IOSTANDARD LVCMOS33} [get_ports txd[5]] +set_property -dict {PACKAGE_PIN K15 IOSTANDARD LVCMOS33} [get_ports txd[6]] +set_property -dict {PACKAGE_PIN J15 IOSTANDARD LVCMOS33} [get_ports txd[7]] +set_property -dict {PACKAGE_PIN J14 IOSTANDARD LVCMOS33} [get_ports txd[8]] +set_property -dict {PACKAGE_PIN J13 IOSTANDARD LVCMOS33} [get_ports txd[9]] +set_property -dict {PACKAGE_PIN J11 IOSTANDARD LVCMOS33} [get_ports txd[10]] +set_property -dict {PACKAGE_PIN H11 IOSTANDARD LVCMOS33} [get_ports txd[11]] + +create_clock -period 10.000 -name rx_clk [get_ports rx_clk] +create_clock -period 12.500 -name trigger_clk [get_ports {trigger_bd[0]}] +create_clock -period 12.500 -name data_clk [get_ports {data_bd[0]}] + +create_clock -name clk_fpga_0 -period 10 [get_pins "i_system_wrapper/system_i/sys_ps7/inst/PS7_i/FCLKCLK[0]"] +create_clock -name clk_fpga_1 -period 5 [get_pins "i_system_wrapper/system_i/sys_ps7/inst/PS7_i/FCLKCLK[1]"] + +set_input_jitter clk_fpga_0 0.3 +set_input_jitter clk_fpga_1 0.15 + +set_property IOSTANDARD LVCMOS18 [get_ports *fixed_io_mio*] +set_property SLEW SLOW [get_ports *fixed_io_mio*] +set_property DRIVE 8 [get_ports *fixed_io_mio*] +set_property -dict {PACKAGE_PIN D8 PULLTYPE PULLUP} [get_ports fixed_io_mio[ 0]] +set_property -dict {PACKAGE_PIN A5 PULLTYPE PULLUP} [get_ports fixed_io_mio[ 1]] +set_property -dict {PACKAGE_PIN A8 } [get_ports fixed_io_mio[ 2]] +set_property -dict {PACKAGE_PIN A7 } [get_ports fixed_io_mio[ 3]] +set_property -dict {PACKAGE_PIN C8 } [get_ports fixed_io_mio[ 4]] +set_property -dict {PACKAGE_PIN A9 } [get_ports fixed_io_mio[ 5]] +set_property -dict {PACKAGE_PIN A10 } [get_ports fixed_io_mio[ 6]] +set_property -dict {PACKAGE_PIN D9 } [get_ports fixed_io_mio[ 7]] +set_property -dict {PACKAGE_PIN B6 } [get_ports fixed_io_mio[ 8]] +set_property -dict {PACKAGE_PIN B5 PULLTYPE PULLUP} [get_ports fixed_io_mio[ 9]] +set_property -dict {PACKAGE_PIN D6 PULLTYPE PULLUP} [get_ports fixed_io_mio[10]] +set_property -dict {PACKAGE_PIN B10 PULLTYPE PULLUP} [get_ports fixed_io_mio[11]] +set_property -dict {PACKAGE_PIN B7 PULLTYPE PULLUP} [get_ports fixed_io_mio[12]] +set_property -dict {PACKAGE_PIN C6 PULLTYPE PULLUP} [get_ports fixed_io_mio[13]] +set_property -dict {PACKAGE_PIN B9 PULLTYPE PULLUP} [get_ports fixed_io_mio[14]] +set_property -dict {PACKAGE_PIN D10 PULLTYPE PULLUP} [get_ports fixed_io_mio[15]] +set_property -dict {PACKAGE_PIN A15 PULLTYPE PULLUP} [get_ports fixed_io_mio[16]] +set_property -dict {PACKAGE_PIN D11 PULLTYPE PULLUP} [get_ports fixed_io_mio[17]] +set_property -dict {PACKAGE_PIN B15 PULLTYPE PULLUP} [get_ports fixed_io_mio[18]] +set_property -dict {PACKAGE_PIN C12 PULLTYPE PULLUP} [get_ports fixed_io_mio[19]] +set_property -dict {PACKAGE_PIN E15 PULLTYPE PULLUP} [get_ports fixed_io_mio[20]] +set_property -dict {PACKAGE_PIN C11 PULLTYPE PULLUP} [get_ports fixed_io_mio[21]] +set_property -dict {PACKAGE_PIN D15 PULLTYPE PULLUP} [get_ports fixed_io_mio[22]] +set_property -dict {PACKAGE_PIN A14 PULLTYPE PULLUP} [get_ports fixed_io_mio[23]] +set_property -dict {PACKAGE_PIN B14 PULLTYPE PULLUP} [get_ports fixed_io_mio[24]] +set_property -dict {PACKAGE_PIN C14 PULLTYPE PULLUP} [get_ports fixed_io_mio[25]] +set_property -dict {PACKAGE_PIN A13 PULLTYPE PULLUP} [get_ports fixed_io_mio[26]] +set_property -dict {PACKAGE_PIN D14 PULLTYPE PULLUP} [get_ports fixed_io_mio[27]] +set_property -dict {PACKAGE_PIN B12 PULLTYPE PULLUP} [get_ports fixed_io_mio[28]] +set_property -dict {PACKAGE_PIN D13 PULLTYPE PULLUP} [get_ports fixed_io_mio[29]] +set_property -dict {PACKAGE_PIN A12 PULLTYPE PULLUP} [get_ports fixed_io_mio[30]] +set_property -dict {PACKAGE_PIN C13 PULLTYPE PULLUP} [get_ports fixed_io_mio[31]] + +set_property IOSTANDARD LVCMOS18 [get_ports *fixed_io_ps*] +set_property SLEW SLOW [get_ports *fixed_io_ps*] +set_property DRIVE 8 [get_ports *fixed_io_ps*] +set_property PACKAGE_PIN C7 [get_ports fixed_io_ps_clk] +set_property PACKAGE_PIN C9 [get_ports fixed_io_ps_porb] + +set_property IOSTANDARD SSTL15_T_DCI [get_ports *fixed_io_ddr_vr*] +set_property SLEW FAST [get_ports *fixed_io_ddr_vr*] +set_property PACKAGE_PIN H3 [get_ports fixed_io_ddr_vrp] +set_property PACKAGE_PIN J3 [get_ports fixed_io_ddr_vrn] + +set_property IOSTANDARD DIFF_SSTL15 [get_ports *ddr_ck*] +set_property SLEW FAST [get_ports *ddr_ck*] +set_property PACKAGE_PIN N3 [get_ports ddr_ck_p] +set_property PACKAGE_PIN N2 [get_ports ddr_ck_n] + +set_property IOSTANDARD SSTL15 [get_ports *ddr_addr*] +set_property SLEW SLOW [get_ports *ddr_addr*] +set_property PACKAGE_PIN P1 [get_ports ddr_addr[0]] +set_property PACKAGE_PIN N1 [get_ports ddr_addr[1]] +set_property PACKAGE_PIN M1 [get_ports ddr_addr[2]] +set_property PACKAGE_PIN M4 [get_ports ddr_addr[3]] +set_property PACKAGE_PIN P3 [get_ports ddr_addr[4]] +set_property PACKAGE_PIN P4 [get_ports ddr_addr[5]] +set_property PACKAGE_PIN P5 [get_ports ddr_addr[6]] +set_property PACKAGE_PIN M5 [get_ports ddr_addr[7]] +set_property PACKAGE_PIN P6 [get_ports ddr_addr[8]] +set_property PACKAGE_PIN N4 [get_ports ddr_addr[9]] +set_property PACKAGE_PIN J1 [get_ports ddr_addr[10]] +set_property PACKAGE_PIN L2 [get_ports ddr_addr[11]] +set_property PACKAGE_PIN M2 [get_ports ddr_addr[12]] +set_property PACKAGE_PIN K2 [get_ports ddr_addr[13]] +set_property PACKAGE_PIN K1 [get_ports ddr_addr[14]] + +set_property IOSTANDARD SSTL15 [get_ports *ddr_ba*] +set_property SLEW SLOW [get_ports *ddr_ba*] +set_property PACKAGE_PIN M6 [get_ports ddr_ba[0]] +set_property PACKAGE_PIN R1 [get_ports ddr_ba[1]] +set_property PACKAGE_PIN N6 [get_ports ddr_ba[2]] + +set_property IOSTANDARD SSTL15 [get_ports ddr_reset_n] +set_property SLEW FAST [get_ports ddr_reset_n] +set_property PACKAGE_PIN L4 [get_ports ddr_reset_n] +set_property IOSTANDARD SSTL15 [get_ports ddr_cs_n] +set_property SLEW SLOW [get_ports ddr_cs_n] +set_property PACKAGE_PIN R2 [get_ports ddr_cs_n] +set_property IOSTANDARD SSTL15 [get_ports ddr_ras_n] +set_property SLEW SLOW [get_ports ddr_ras_n] +set_property PACKAGE_PIN R6 [get_ports ddr_ras_n] +set_property IOSTANDARD SSTL15 [get_ports ddr_cas_n] +set_property SLEW SLOW [get_ports ddr_cas_n] +set_property PACKAGE_PIN R5 [get_ports ddr_cas_n] +set_property IOSTANDARD SSTL15 [get_ports ddr_we_n] +set_property SLEW SLOW [get_ports ddr_we_n] +set_property PACKAGE_PIN R3 [get_ports ddr_we_n] +set_property IOSTANDARD SSTL15 [get_ports ddr_cke] +set_property SLEW SLOW [get_ports ddr_cke] +set_property PACKAGE_PIN L3 [get_ports ddr_cke] +set_property IOSTANDARD SSTL15 [get_ports ddr_odt] +set_property SLEW SLOW [get_ports ddr_odt] +set_property PACKAGE_PIN K3 [get_ports ddr_odt] + +set_property IOSTANDARD SSTL15_T_DCI [get_ports *ddr_dq[*]] +set_property SLEW FAST [get_ports *ddr_dq[*]] +set_property PACKAGE_PIN D4 [get_ports ddr_dq[0]] +set_property PACKAGE_PIN A2 [get_ports ddr_dq[1]] +set_property PACKAGE_PIN C4 [get_ports ddr_dq[2]] +set_property PACKAGE_PIN C1 [get_ports ddr_dq[3]] +set_property PACKAGE_PIN B4 [get_ports ddr_dq[4]] +set_property PACKAGE_PIN A4 [get_ports ddr_dq[5]] +set_property PACKAGE_PIN C3 [get_ports ddr_dq[6]] +set_property PACKAGE_PIN A3 [get_ports ddr_dq[7]] +set_property PACKAGE_PIN E1 [get_ports ddr_dq[8]] +set_property PACKAGE_PIN D1 [get_ports ddr_dq[9]] +set_property PACKAGE_PIN E2 [get_ports ddr_dq[10]] +set_property PACKAGE_PIN E3 [get_ports ddr_dq[11]] +set_property PACKAGE_PIN F3 [get_ports ddr_dq[12]] +set_property PACKAGE_PIN G1 [get_ports ddr_dq[13]] +set_property PACKAGE_PIN H1 [get_ports ddr_dq[14]] +set_property PACKAGE_PIN H2 [get_ports ddr_dq[15]] +set_property IOSTANDARD SSTL15_T_DCI [get_ports *ddr_dm[*]] +set_property SLEW FAST [get_ports *ddr_dm[*]] +set_property PACKAGE_PIN B1 [get_ports ddr_dm[0]] +set_property PACKAGE_PIN D3 [get_ports ddr_dm[1]] +set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports *ddr_dqs*] +set_property SLEW FAST [get_ports *ddr_dqs*] +set_property PACKAGE_PIN C2 [get_ports ddr_dqs_p[0]] +set_property PACKAGE_PIN B2 [get_ports ddr_dqs_n[0]] +set_property PACKAGE_PIN G2 [get_ports ddr_dqs_p[1]] +set_property PACKAGE_PIN F2 [get_ports ddr_dqs_n[1]] diff --git a/projects/m2k/standalone/system_project.tcl b/projects/m2k/standalone/system_project.tcl new file mode 100644 index 000000000..6e349259a --- /dev/null +++ b/projects/m2k/standalone/system_project.tcl @@ -0,0 +1,17 @@ + +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/projects/scripts/adi_project.tcl +source $ad_hdl_dir/projects/scripts/adi_board.tcl + +set p_device "xc7z010clg225-1" +adi_project_create m2k + +adi_project_files m2k [list \ + "../common/m2k_spi.v" \ + "system_top.v" \ + "system_constr.xdc" \ + "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v"] + +set_property is_enabled false [get_files *system_sys_ps7_0.xdc] +adi_project_run m2k + diff --git a/projects/m2k/standalone/system_top.v b/projects/m2k/standalone/system_top.v new file mode 100644 index 000000000..166c06e95 --- /dev/null +++ b/projects/m2k/standalone/system_top.v @@ -0,0 +1,205 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top ( + + inout [14:0] ddr_addr, + inout [ 2:0] ddr_ba, + inout ddr_cas_n, + inout ddr_ck_n, + inout ddr_ck_p, + inout ddr_cke, + inout ddr_cs_n, + inout [ 1:0] ddr_dm, + inout [15:0] ddr_dq, + inout [ 1:0] ddr_dqs_n, + inout [ 1:0] ddr_dqs_p, + inout ddr_odt, + inout ddr_ras_n, + inout ddr_reset_n, + inout ddr_we_n, + + inout fixed_io_ddr_vrn, + inout fixed_io_ddr_vrp, + inout [31:0] fixed_io_mio, + inout fixed_io_ps_clk, + inout fixed_io_ps_porb, + inout fixed_io_ps_srstb, + + inout [15:0] data_bd, + inout [ 1:0] trigger_bd, + + input rx_clk, + input rxiq, + input [11:0] rxd, + output tx_clk, + output txiq, + output [11:0] txd, + + output ad9963_resetn, + output ad9963_csn, + output adf4360_cs, + output spi_clk, + inout spi_sdio, + + output en_power_analog, + + inout iic_scl, + inout iic_sda); + + // internal signals + + wire [16:0] gpio_i; + wire [16:0] gpio_o; + wire [16:0] gpio_t; + + wire [15:0] data_i; + wire [15:0] data_o; + wire [15:0] data_t; + + wire [ 1:0] trigger_i; + wire [ 1:0] trigger_o; + wire [ 1:0] trigger_t; + + wire [ 1:0] spi0_csn; + wire spi0_clk; + wire spi0_mosi; + wire spi0_miso; + + assign ad9963_csn = spi0_csn[0]; + assign adf4360_cs = spi0_csn[1]; + assign spi_clk = spi0_clk; + assign spi_mosi = spi0_mosi; + assign spi0_miso = spi_miso; + + // instantiations + + ad_iobuf #(.DATA_WIDTH(2)) i_iobuf ( + .dio_t (gpio_t[ 1:0]), + .dio_i (gpio_o[ 1:0]), + .dio_o (gpio_i[ 1:0]), + .dio_p ({ en_power_analog, + ad9963_resetn})); + + ad_iobuf #( + .DATA_WIDTH(16) + ) i_data_bd ( + .dio_t(data_t[15:0]), + .dio_i(data_o[15:0]), + .dio_o(data_i[15:0]), + .dio_p(data_bd)); + + ad_iobuf #( + .DATA_WIDTH(2) + ) i_trigger_bd ( + .dio_t(trigger_t[1:0]), + .dio_i(trigger_o[1:0]), + .dio_o(trigger_i[1:0]), + .dio_p(trigger_bd)); + + m2k_spi i_m2k_spi ( + .ad9963_csn (ad9963_csn), + .adf4360_cs (adf4360_cs), + .spi_clk (spi_clk), + .spi_mosi (spi_mosi), + .spi_miso (spi_miso), + .spi_sdio (spi_sdio)); + + system_wrapper i_system_wrapper ( + .ddr_addr (ddr_addr), + .ddr_ba (ddr_ba), + .ddr_cas_n (ddr_cas_n), + .ddr_ck_n (ddr_ck_n), + .ddr_ck_p (ddr_ck_p), + .ddr_cke (ddr_cke), + .ddr_cs_n (ddr_cs_n), + .ddr_dm (ddr_dm), + .ddr_dq (ddr_dq), + .ddr_dqs_n (ddr_dqs_n), + .ddr_dqs_p (ddr_dqs_p), + .ddr_odt (ddr_odt), + .ddr_ras_n (ddr_ras_n), + .ddr_reset_n (ddr_reset_n), + .ddr_we_n (ddr_we_n), + .fixed_io_ddr_vrn (fixed_io_ddr_vrn), + .fixed_io_ddr_vrp (fixed_io_ddr_vrp), + .fixed_io_mio (fixed_io_mio), + .fixed_io_ps_clk (fixed_io_ps_clk), + .fixed_io_ps_porb (fixed_io_ps_porb), + .fixed_io_ps_srstb (fixed_io_ps_srstb), + .gpio_i (gpio_i), + .gpio_o (gpio_o), + .gpio_t (gpio_t), + .iic_main_scl_io (iic_scl), + .iic_main_sda_io (iic_sda), + .data_i(data_i), + .data_o(data_o), + .data_t(data_t), + .trigger_i(trigger_i), + .trigger_o(trigger_o), + .trigger_t(trigger_t), + .rx_clk(rx_clk), + .rxiq(rxiq), + .rxd(rxd), + .tx_clk(tx_clk), + .txiq(txiq), + .txd(txd), + .ps_intr_00 (1'b0), + .ps_intr_01 (1'b0), + .ps_intr_02 (1'b0), + .ps_intr_03 (1'b0), + .ps_intr_04 (1'b0), + .ps_intr_05 (1'b0), + .ps_intr_06 (1'b0), + .ps_intr_07 (1'b0), + .ps_intr_11 (1'b0), + .ps_intr_15 (1'b0), + .spi0_clk_i (spi0_clk), + .spi0_clk_o (spi0_clk), + .spi0_csn_0_o (spi0_csn[0]), + .spi0_csn_1_o (spi0_csn[1]), + .spi0_csn_i (1'b1), + .spi0_sdi_i (spi0_miso), + .spi0_sdo_i (spi0_mosi), + .spi0_sdo_o (spi0_mosi)); + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/projects/m2k/zed/Makefile b/projects/m2k/zed/Makefile new file mode 100644 index 000000000..e249888ad --- /dev/null +++ b/projects/m2k/zed/Makefile @@ -0,0 +1,100 @@ +#################################################################################### +#################################################################################### +## Copyright 2011(c) Analog Devices, Inc. +## Auto-generated, do not modify! +#################################################################################### +#################################################################################### + +M_DEPS += system_top.v +M_DEPS += system_project.tcl +M_DEPS += system_constr.xdc +M_DEPS += system_bd.tcl +M_DEPS += ../common/m2k_spi.v +M_DEPS += ../common/m2k_bd.tcl +M_DEPS += ../../scripts/adi_project.tcl +M_DEPS += ../../scripts/adi_env.tcl +M_DEPS += ../../scripts/adi_board.tcl +M_DEPS += ../../common/zed/zed_system_constr.xdc +M_DEPS += ../../common/zed/zed_system_bd.tcl +M_DEPS += ../../../library/xilinx/common/ad_iobuf.v +M_DEPS += ../../../library/axi_ad9963/axi_ad9963.xpr +M_DEPS += ../../../library/axi_adc_decimate/axi_adc_decimate.xpr +M_DEPS += ../../../library/axi_adc_trigger/axi_adc_trigger.xpr +M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr +M_DEPS += ../../../library/axi_dac_interpolate/axi_dac_interpolate.xpr +M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr +M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr +M_DEPS += ../../../library/axi_i2s_adi/axi_i2s_adi.xpr +M_DEPS += ../../../library/axi_logic_analyzer/axi_logic_analyzer.xpr +M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr +M_DEPS += ../../../library/util_cpack/util_cpack.xpr +M_DEPS += ../../../library/util_extract/util_extract.xpr +M_DEPS += ../../../library/util_i2c_mixer/util_i2c_mixer.xpr +M_DEPS += ../../../library/util_var_fifo/util_var_fifo.xpr + +M_VIVADO := vivado -mode batch -source + +M_FLIST := *.cache +M_FLIST += *.data +M_FLIST += *.xpr +M_FLIST += *.log +M_FLIST += *.jou +M_FLIST += xgui +M_FLIST += *.runs +M_FLIST += *.srcs +M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim +M_FLIST += .Xil +M_FLIST += *.ip_user_files + + + +.PHONY: all lib clean clean-all +all: lib m2k_fmc_zed.sdk/system_top.hdf + + +clean: + rm -rf $(M_FLIST) + + +clean-all:clean + make -C ../../../library/axi_ad9963 clean + make -C ../../../library/axi_adc_decimate clean + make -C ../../../library/axi_adc_trigger clean + make -C ../../../library/axi_clkgen clean + make -C ../../../library/axi_dac_interpolate clean + make -C ../../../library/axi_dmac clean + make -C ../../../library/axi_hdmi_tx clean + make -C ../../../library/axi_i2s_adi clean + make -C ../../../library/axi_logic_analyzer clean + make -C ../../../library/axi_spdif_tx clean + make -C ../../../library/util_cpack clean + make -C ../../../library/util_extract clean + make -C ../../../library/util_i2c_mixer clean + make -C ../../../library/util_var_fifo clean + + +m2k_fmc_zed.sdk/system_top.hdf: $(M_DEPS) + -rm -rf $(M_FLIST) + $(M_VIVADO) system_project.tcl >> m2k_fmc_zed_vivado.log 2>&1 + + +lib: + make -C ../../../library/axi_ad9963 + make -C ../../../library/axi_adc_decimate + make -C ../../../library/axi_adc_trigger + make -C ../../../library/axi_clkgen + make -C ../../../library/axi_dac_interpolate + make -C ../../../library/axi_dmac + make -C ../../../library/axi_hdmi_tx + make -C ../../../library/axi_i2s_adi + make -C ../../../library/axi_logic_analyzer + make -C ../../../library/axi_spdif_tx + make -C ../../../library/util_cpack + make -C ../../../library/util_extract + make -C ../../../library/util_i2c_mixer + make -C ../../../library/util_var_fifo + +#################################################################################### +#################################################################################### diff --git a/projects/m2k/zed/system_bd.tcl b/projects/m2k/zed/system_bd.tcl new file mode 100644 index 000000000..dc673a39d --- /dev/null +++ b/projects/m2k/zed/system_bd.tcl @@ -0,0 +1,4 @@ + +source ../../common/zed/zed_system_bd.tcl +source ../common/m2k_bd.tcl + diff --git a/projects/m2k/zed/system_constr.xdc b/projects/m2k/zed/system_constr.xdc new file mode 100644 index 000000000..5266b1090 --- /dev/null +++ b/projects/m2k/zed/system_constr.xdc @@ -0,0 +1,85 @@ +set_property -dict {PACKAGE_PIN L16 IOSTANDARD LVCMOS33} [get_ports otg_vbusoc] + +set_property -dict {PACKAGE_PIN P16 IOSTANDARD LVCMOS33} [get_ports gpio_bd[0]] ; ## BTNC +set_property -dict {PACKAGE_PIN R16 IOSTANDARD LVCMOS33} [get_ports gpio_bd[1]] ; ## BTND +set_property -dict {PACKAGE_PIN N15 IOSTANDARD LVCMOS33} [get_ports gpio_bd[2]] ; ## BTNL +set_property -dict {PACKAGE_PIN R18 IOSTANDARD LVCMOS33} [get_ports gpio_bd[3]] ; ## BTNR +set_property -dict {PACKAGE_PIN T18 IOSTANDARD LVCMOS33} [get_ports gpio_bd[4]] ; ## BTNU + +set_property -dict {PACKAGE_PIN F22 IOSTANDARD LVCMOS33} [get_ports gpio_bd[11]] ; ## SW0 +set_property -dict {PACKAGE_PIN G22 IOSTANDARD LVCMOS33} [get_ports gpio_bd[12]] ; ## SW1 +set_property -dict {PACKAGE_PIN H22 IOSTANDARD LVCMOS33} [get_ports gpio_bd[13]] ; ## SW2 +set_property -dict {PACKAGE_PIN F21 IOSTANDARD LVCMOS33} [get_ports gpio_bd[14]] ; ## SW3 +set_property -dict {PACKAGE_PIN H19 IOSTANDARD LVCMOS33} [get_ports gpio_bd[15]] ; ## SW4 +set_property -dict {PACKAGE_PIN H18 IOSTANDARD LVCMOS33} [get_ports gpio_bd[16]] ; ## SW5 +set_property -dict {PACKAGE_PIN H17 IOSTANDARD LVCMOS33} [get_ports gpio_bd[17]] ; ## SW6 +set_property -dict {PACKAGE_PIN M15 IOSTANDARD LVCMOS33} [get_ports gpio_bd[18]] ; ## SW7 + +set_property -dict {PACKAGE_PIN H15 IOSTANDARD LVCMOS33} [get_ports gpio_bd[27]] ; ## XADC-GIO0 +set_property -dict {PACKAGE_PIN R15 IOSTANDARD LVCMOS33} [get_ports gpio_bd[28]] ; ## XADC-GIO1 +set_property -dict {PACKAGE_PIN K15 IOSTANDARD LVCMOS33} [get_ports gpio_bd[29]] ; ## XADC-GIO2 +set_property -dict {PACKAGE_PIN J15 IOSTANDARD LVCMOS33} [get_ports gpio_bd[30]] ; ## XADC-GIO3 + +set_property -dict {PACKAGE_PIN G17 IOSTANDARD LVCMOS33} [get_ports gpio_bd[31]] ; ## OTG-RESETN + +set_property -dict {PACKAGE_PIN A16 IOSTANDARD LVCMOS33} [get_ports en_power_analog] ; ## A16 FMC_LPC_LA28_P +set_property -dict {PACKAGE_PIN B16 IOSTANDARD LVCMOS33} [get_ports ad9963_resetn] ; ## G33 FMC_LPC_LA31_P + +set_property -dict {PACKAGE_PIN B21 IOSTANDARD LVCMOS33} [get_ports adf4360_cs] ; ## G36 FMC_LPC_LA33_P +set_property -dict {PACKAGE_PIN B17 IOSTANDARD LVCMOS33} [get_ports ad9963_csn] ; ## G34 FMC_LPC_LA31_N +set_property -dict {PACKAGE_PIN C17 IOSTANDARD LVCMOS33} [get_ports spi_clk] ; ## G30 FMC_LPC_LA29_P +set_property -dict {PACKAGE_PIN C18 IOSTANDARD LVCMOS33} [get_ports spi_sdio] ; ## G31 FMC_LPC_LA29_N + +set_property -dict {PACKAGE_PIN D20 IOSTANDARD LVCMOS33 } [get_ports trigger_bd[0]] ; ## C22 FMC_LPC_LA18_CC_P +set_property -dict {PACKAGE_PIN C20 IOSTANDARD LVCMOS33 } [get_ports trigger_bd[1]] ; ## C23 FMC_LPC_LA18_CC_N + +set_property -dict {PACKAGE_PIN B19 IOSTANDARD LVCMOS33 } [get_ports data_bd[0]] ; ## D20 FMC_LPC_LA17_CC_P +set_property -dict {PACKAGE_PIN B20 IOSTANDARD LVCMOS33 } [get_ports data_bd[1]] ; ## D21 FMC_LPC_LA17_CC_N +set_property -dict {PACKAGE_PIN D22 IOSTANDARD LVCMOS33 } [get_ports data_bd[2]] ; ## D17 FMC_LPC_LA13_P +set_property -dict {PACKAGE_PIN C22 IOSTANDARD LVCMOS33 } [get_ports data_bd[3]] ; ## D18 FMC_LPC_LA13_N +set_property -dict {PACKAGE_PIN E15 IOSTANDARD LVCMOS33 } [get_ports data_bd[4]] ; ## D23 FMC_LPC_LA23_P +set_property -dict {PACKAGE_PIN D15 IOSTANDARD LVCMOS33 } [get_ports data_bd[5]] ; ## D24 FMC_LPC_LA23_N +set_property -dict {PACKAGE_PIN F18 IOSTANDARD LVCMOS33 } [get_ports data_bd[6]] ; ## D26 FMC_LPC_LA26_P +set_property -dict {PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports data_bd[7]] ; ## D27 FMC_LPC_LA26_N +set_property -dict {PACKAGE_PIN G20 IOSTANDARD LVCMOS33 } [get_ports data_bd[8]] ; ## C10 FMC_LPC_LA06_P +set_property -dict {PACKAGE_PIN G21 IOSTANDARD LVCMOS33 } [get_ports data_bd[9]] ; ## C11 FMC_LPC_LA06_N +set_property -dict {PACKAGE_PIN G19 IOSTANDARD LVCMOS33 } [get_ports data_bd[10]] ; ## C14 FMC_LPC_LA10_P +set_property -dict {PACKAGE_PIN F19 IOSTANDARD LVCMOS33 } [get_ports data_bd[11]] ; ## C15 FMC_LPC_LA10_N +set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVCMOS33 } [get_ports data_bd[12]] ; ## C18 FMC_LPC_LA14_P +set_property -dict {PACKAGE_PIN G16 IOSTANDARD LVCMOS33 } [get_ports data_bd[13]] ; ## C19 FMC_LPC_LA14_N +set_property -dict {PACKAGE_PIN E21 IOSTANDARD LVCMOS33 } [get_ports data_bd[14]] ; ## C26 FMC_LPC_LA27_P +set_property -dict {PACKAGE_PIN D21 IOSTANDARD LVCMOS33 } [get_ports data_bd[15]] ; ## C27 FMC_LPC_LA27_P + +set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVCMOS33} [get_ports rx_clk] ; ## G07 FMC_LPC_LA01_CC_P +set_property -dict {PACKAGE_PIN L17 IOSTANDARD LVCMOS33} [get_ports rxiq] ; ## G27 FMC_LPC_LA25_P +set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS33} [get_ports rxd[0]] ; ## H07 FMC_LPC_LA02_P +set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS33} [get_ports rxd[1]] ; ## H08 FMC_LPC_LA02_N +set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVCMOS33} [get_ports rxd[2]] ; ## H10 FMC_LPC_LA04_P +set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVCMOS33} [get_ports rxd[3]] ; ## H11 FMC_LPC_LA04_N +set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVCMOS33} [get_ports rxd[4]] ; ## H13 FMC_LPC_LA07_P +set_property -dict {PACKAGE_PIN T17 IOSTANDARD LVCMOS33} [get_ports rxd[5]] ; ## H14 FMC_LPC_LA07_N +set_property -dict {PACKAGE_PIN N17 IOSTANDARD LVCMOS33} [get_ports rxd[6]] ; ## H16 FMC_LPC_LA11_P +set_property -dict {PACKAGE_PIN N18 IOSTANDARD LVCMOS33} [get_ports rxd[7]] ; ## H17 FMC_LPC_LA11_N +set_property -dict {PACKAGE_PIN J16 IOSTANDARD LVCMOS33} [get_ports rxd[8]] ; ## H19 FMC_LPC_LA15_P +set_property -dict {PACKAGE_PIN J17 IOSTANDARD LVCMOS33} [get_ports rxd[9]] ; ## H20 FMC_LPC_LA15_N +set_property -dict {PACKAGE_PIN K19 IOSTANDARD LVCMOS33} [get_ports rxd[10]] ; ## H22 FMC_LPC_LA19_P +set_property -dict {PACKAGE_PIN K20 IOSTANDARD LVCMOS33} [get_ports rxd[11]] ; ## H23 FMC_LPC_LA19_N + +set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVCMOS33} [get_ports tx_clk] ; ## G06 FMC_LPC_LA00_CC_P +set_property -dict {PACKAGE_PIN M17 IOSTANDARD LVCMOS33} [get_ports txiq] ; ## G28 FMC_LPC_LA25_N +set_property -dict {PACKAGE_PIN N22 IOSTANDARD LVCMOS33} [get_ports txd[0]] ; ## G09 FMC_LPC_LA03_P +set_property -dict {PACKAGE_PIN P22 IOSTANDARD LVCMOS33} [get_ports txd[1]] ; ## G10 FMC_LPC_LA03_N +set_property -dict {PACKAGE_PIN J21 IOSTANDARD LVCMOS33} [get_ports txd[2]] ; ## G12 FMC_LPC_LA08_P +set_property -dict {PACKAGE_PIN J22 IOSTANDARD LVCMOS33} [get_ports txd[3]] ; ## G13 FMC_LPC_LA08_N +set_property -dict {PACKAGE_PIN P20 IOSTANDARD LVCMOS33} [get_ports txd[4]] ; ## G15 FMC_LPC_LA12_P +set_property -dict {PACKAGE_PIN P21 IOSTANDARD LVCMOS33} [get_ports txd[5]] ; ## G16 FMC_LPC_LA12_N +set_property -dict {PACKAGE_PIN J20 IOSTANDARD LVCMOS33} [get_ports txd[6]] ; ## G18 FMC_LPC_LA16_P +set_property -dict {PACKAGE_PIN K21 IOSTANDARD LVCMOS33} [get_ports txd[7]] ; ## G19 FMC_LPC_LA16_N +set_property -dict {PACKAGE_PIN L21 IOSTANDARD LVCMOS33} [get_ports txd[8]] ; ## G21 FMC_LPC_LA20_P +set_property -dict {PACKAGE_PIN L22 IOSTANDARD LVCMOS33} [get_ports txd[9]] ; ## G22 FMC_LPC_LA20_N +set_property -dict {PACKAGE_PIN R19 IOSTANDARD LVCMOS33} [get_ports txd[10]] ; ## G24 FMC_LPC_LA22_P +set_property -dict {PACKAGE_PIN T19 IOSTANDARD LVCMOS33} [get_ports txd[11]] ; ## G25 FMC_LPC_LA22_N + +create_clock -name rx_clk -period 10.00 [get_ports rx_clk] +create_clock -name trigger_clk -period 12.5 [get_ports trigger_bd[0]] +create_clock -name data_clk -period 12.5 [get_ports data_bd[0]] diff --git a/projects/m2k/zed/system_project.tcl b/projects/m2k/zed/system_project.tcl new file mode 100644 index 000000000..698017bb5 --- /dev/null +++ b/projects/m2k/zed/system_project.tcl @@ -0,0 +1,17 @@ + +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/projects/scripts/adi_project.tcl +source $ad_hdl_dir/projects/scripts/adi_board.tcl + +adi_project_create m2k_fmc_zed +adi_project_files m2k_fmc_zed [list \ + "../common/m2k_spi.v" \ + "system_top.v" \ + "system_constr.xdc" \ + "$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc" \ + "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v"] + +set_property PROCESSING_ORDER EARLY [get_files "$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc"] + +adi_project_run m2k_fmc_zed + diff --git a/projects/m2k/zed/system_top.v b/projects/m2k/zed/system_top.v new file mode 100644 index 000000000..c3ac220f0 --- /dev/null +++ b/projects/m2k/zed/system_top.v @@ -0,0 +1,276 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top ( + + inout [14:0] ddr_addr, + inout [ 2:0] ddr_ba, + inout ddr_cas_n, + inout ddr_ck_n, + inout ddr_ck_p, + inout ddr_cke, + inout ddr_cs_n, + inout [ 3:0] ddr_dm, + inout [31:0] ddr_dq, + inout [ 3:0] ddr_dqs_n, + inout [ 3:0] ddr_dqs_p, + inout ddr_odt, + inout ddr_ras_n, + inout ddr_reset_n, + inout ddr_we_n, + + inout fixed_io_ddr_vrn, + inout fixed_io_ddr_vrp, + inout [53:0] fixed_io_mio, + inout fixed_io_ps_clk, + inout fixed_io_ps_porb, + inout fixed_io_ps_srstb, + + inout [31:0] gpio_bd, + + output hdmi_out_clk, + output hdmi_vsync, + output hdmi_hsync, + output hdmi_data_e, + output [15:0] hdmi_data, + + output i2s_mclk, + output i2s_bclk, + output i2s_lrclk, + output i2s_sdata_out, + input i2s_sdata_in, + + output spdif, + + inout [ 1:0] iic_mux_scl, + inout [ 1:0] iic_mux_sda, + + input otg_vbusoc, + + inout [15:0] data_bd, + inout [ 1:0] trigger_bd, + + input rx_clk, + input rxiq, + input [11:0] rxd, + output tx_clk, + output txiq, + output [11:0] txd, + + output ad9963_resetn, + output ad9963_csn, + output adf4360_cs, + output spi_clk, + inout spi_sdio, + + output en_power_analog, + + inout iic_scl, + inout iic_sda); + + // internal signals + + wire [63:0] gpio_i; + wire [63:0] gpio_o; + wire [63:0] gpio_t; + wire [ 1:0] iic_mux_scl_i_s; + wire [ 1:0] iic_mux_scl_o_s; + wire iic_mux_scl_t_s; + wire [ 1:0] iic_mux_sda_i_s; + wire [ 1:0] iic_mux_sda_o_s; + wire iic_mux_sda_t_s; + + wire [15:0] data_i; + wire [15:0] data_o; + wire [15:0] data_t; + + wire [ 1:0] trigger_i; + wire [ 1:0] trigger_o; + wire [ 1:0] trigger_t; + + wire [ 1:0] spi0_csn; + wire spi0_clk; + wire spi0_mosi; + wire spi0_miso; + + assign ad9963_resetn = gpio_o[32]; + assign en_power_analog = gpio_o[33]; + + assign ad9963_csn = spi0_csn[0]; + assign adf4360_cs = spi0_csn[1]; + assign spi_clk = spi0_clk; + assign spi_mosi = spi0_mosi; + assign spi0_miso = spi_miso; + + // instantiations + + ad_iobuf #( + .DATA_WIDTH(32) + ) i_iobuf ( + .dio_t(gpio_t[31:0]), + .dio_i(gpio_o[31:0]), + .dio_o(gpio_i[31:0]), + .dio_p(gpio_bd)); + + ad_iobuf #( + .DATA_WIDTH(2) + ) i_iic_mux_scl ( + .dio_t({iic_mux_scl_t_s, iic_mux_scl_t_s}), + .dio_i(iic_mux_scl_o_s), + .dio_o(iic_mux_scl_i_s), + .dio_p(iic_mux_scl)); + + ad_iobuf #( + .DATA_WIDTH(2) + ) i_iic_mux_sda ( + .dio_t({iic_mux_sda_t_s, iic_mux_sda_t_s}), + .dio_i(iic_mux_sda_o_s), + .dio_o(iic_mux_sda_i_s), + .dio_p(iic_mux_sda)); + + ad_iobuf #( + .DATA_WIDTH(16) + ) i_data_bd ( + .dio_t(data_t[15:0]), + .dio_i(data_o[15:0]), + .dio_o(data_i[15:0]), + .dio_p(data_bd)); + + ad_iobuf #( + .DATA_WIDTH(2) + ) i_trigger_bd ( + .dio_t(trigger_t[1:0]), + .dio_i(trigger_o[1:0]), + .dio_o(trigger_i[1:0]), + .dio_p(trigger_bd)); + + m2k_spi i_m2k_spi ( + .ad9963_csn (ad9963_csn), + .adf4360_cs (adf4360_cs), + .spi_clk (spi_clk), + .spi_mosi (spi_mosi), + .spi_miso (spi_miso), + .spi_sdio (spi_sdio)); + + system_wrapper i_system_wrapper ( + .ddr_addr (ddr_addr), + .ddr_ba (ddr_ba), + .ddr_cas_n (ddr_cas_n), + .ddr_ck_n (ddr_ck_n), + .ddr_ck_p (ddr_ck_p), + .ddr_cke (ddr_cke), + .ddr_cs_n (ddr_cs_n), + .ddr_dm (ddr_dm), + .ddr_dq (ddr_dq), + .ddr_dqs_n (ddr_dqs_n), + .ddr_dqs_p (ddr_dqs_p), + .ddr_odt (ddr_odt), + .ddr_ras_n (ddr_ras_n), + .ddr_reset_n (ddr_reset_n), + .ddr_we_n (ddr_we_n), + .fixed_io_ddr_vrn (fixed_io_ddr_vrn), + .fixed_io_ddr_vrp (fixed_io_ddr_vrp), + .fixed_io_mio (fixed_io_mio), + .fixed_io_ps_clk (fixed_io_ps_clk), + .fixed_io_ps_porb (fixed_io_ps_porb), + .fixed_io_ps_srstb (fixed_io_ps_srstb), + .gpio_i (gpio_i), + .gpio_o (gpio_o), + .gpio_t (gpio_t), + .hdmi_data (hdmi_data), + .hdmi_data_e (hdmi_data_e), + .hdmi_hsync (hdmi_hsync), + .hdmi_out_clk (hdmi_out_clk), + .hdmi_vsync (hdmi_vsync), + .i2s_bclk (i2s_bclk), + .i2s_lrclk (i2s_lrclk), + .i2s_mclk (i2s_mclk), + .i2s_sdata_in (i2s_sdata_in), + .i2s_sdata_out (i2s_sdata_out), + .iic_fmc_scl_io (iic_scl), + .iic_fmc_sda_io (iic_sda), + .iic_mux_scl_i (iic_mux_scl_i_s), + .iic_mux_scl_o (iic_mux_scl_o_s), + .iic_mux_scl_t (iic_mux_scl_t_s), + .iic_mux_sda_i (iic_mux_sda_i_s), + .iic_mux_sda_o (iic_mux_sda_o_s), + .iic_mux_sda_t (iic_mux_sda_t_s), + .data_i(data_i), + .data_o(data_o), + .data_t(data_t), + .trigger_i(trigger_i), + .trigger_o(trigger_o), + .trigger_t(trigger_t), + .rx_clk(rx_clk), + .rxiq(rxiq), + .rxd(rxd), + .tx_clk(tx_clk), + .txiq(txiq), + .txd(txd), + .ps_intr_00 (1'b0), + .ps_intr_01 (1'b0), + .ps_intr_02 (1'b0), + .ps_intr_03 (1'b0), + .ps_intr_04 (1'b0), + .ps_intr_05 (1'b0), + .ps_intr_06 (1'b0), + .ps_intr_07 (1'b0), + .spi0_clk_i (spi0_clk), + .spi0_clk_o (spi0_clk), + .spi0_csn_0_o (spi0_csn[0]), + .spi0_csn_1_o (spi0_csn[1]), + .spi0_csn_i (1'b1), + .spi0_sdi_i (spi0_miso), + .spi0_sdo_i (spi0_mosi), + .spi0_sdo_o (spi0_mosi), + .spi1_clk_i (1'b0), + .spi1_clk_o (), + .spi1_csn_0_o (), + .spi1_csn_1_o (), + .spi1_csn_i (1'b1), + .spi1_sdi_i (1'b0), + .spi1_sdo_i (1'b0), + .spi1_sdo_o (), + .otg_vbusoc (otg_vbusoc), + .spdif (spdif)); + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/projects/motcon2_fmc/common/motcon2_fmc_bd.tcl b/projects/motcon2_fmc/common/motcon2_fmc_bd.tcl index 58800d076..a3b8e0bd4 100644 --- a/projects/motcon2_fmc/common/motcon2_fmc_bd.tcl +++ b/projects/motcon2_fmc/common/motcon2_fmc_bd.tcl @@ -162,7 +162,7 @@ set iic_ee2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_iic:2.0 iic_ee2 ] # xadc - set xadc_core [ create_bd_cell -type ip -vlnv xilinx.com:ip:xadc_wiz:3.2 xadc_core ] + set xadc_core [ create_bd_cell -type ip -vlnv xilinx.com:ip:xadc_wiz:3.3 xadc_core ] set_property -dict [ list CONFIG.XADC_STARUP_SELECTION {simultaneous_sampling} ] $xadc_core set_property -dict [ list CONFIG.ENABLE_EXTERNAL_MUX {true} ] $xadc_core set_property -dict [ list CONFIG.EXTERNAL_MUX_CHANNEL {VAUXP0_VAUXN0} ] $xadc_core @@ -224,6 +224,10 @@ ad_connect current_monitor_m1_pack/adc_valid current_monitor_m1_dma/fifo_wr_en ad_connect current_monitor_m1_dma/fifo_wr_sync current_monitor_m1_pack/adc_sync + ad_connect current_monitor_m1_pack/adc_enable_3 GND + ad_connect current_monitor_m1_pack/adc_valid_3 GND + ad_connect current_monitor_m1_pack/adc_data_3 GND + # motor 2 ad_connect sys_cpu_clk current_monitor_m2/ref_clk @@ -250,6 +254,10 @@ ad_connect current_monitor_m2_pack/adc_data current_monitor_m2_dma/fifo_wr_din ad_connect current_monitor_m2_dma/fifo_wr_sync current_monitor_m2_pack/adc_sync + ad_connect current_monitor_m2_pack/adc_enable_3 GND + ad_connect current_monitor_m2_pack/adc_valid_3 GND + ad_connect current_monitor_m2_pack/adc_data_3 GND + #controller # motor 1 ad_connect sys_cpu_clk controller_m1/ref_clk @@ -266,6 +274,13 @@ ad_connect controller_m1/sensors_o speed_detector_m1/hall_bemf_i ad_connect controller_m1/position_i speed_detector_m1/position_o + ad_connect controller_m1/pwm_a_i GND + ad_connect controller_m1/pwm_b_i GND + ad_connect controller_m1/pwm_c_i GND + ad_connect controller_m2/pwm_a_i GND + ad_connect controller_m2/pwm_b_i GND + ad_connect controller_m2/pwm_c_i GND + # motor 2 ad_connect sys_cpu_clk controller_m2/ref_clk ad_connect controller_m2/ctrl_data_clk sys_audio_clkgen/clk_out5 diff --git a/projects/motcon2_fmc/zed/Makefile b/projects/motcon2_fmc/zed/Makefile index e214e56d0..c4177d1a4 100644 --- a/projects/motcon2_fmc/zed/Makefile +++ b/projects/motcon2_fmc/zed/Makefile @@ -15,7 +15,7 @@ M_DEPS += ../../scripts/adi_env.tcl M_DEPS += ../../scripts/adi_board.tcl M_DEPS += ../../common/zed/zed_system_constr.xdc M_DEPS += ../../common/zed/zed_system_bd.tcl -M_DEPS += ../../../library/common/ad_iobuf.v +M_DEPS += ../../../library/xilinx/common/ad_iobuf.v M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr @@ -42,6 +42,7 @@ M_FLIST += *.sdk M_FLIST += *.hw M_FLIST += *.sim M_FLIST += .Xil +M_FLIST += *.ip_user_files @@ -68,7 +69,7 @@ clean-all:clean motcon2_fmc_zed.sdk/system_top.hdf: $(M_DEPS) - rm -rf $(M_FLIST) + -rm -rf $(M_FLIST) $(M_VIVADO) system_project.tcl >> motcon2_fmc_zed_vivado.log 2>&1 diff --git a/projects/motcon2_fmc/zed/system_project.tcl b/projects/motcon2_fmc/zed/system_project.tcl index 65d0b6233..7772b1862 100755 --- a/projects/motcon2_fmc/zed/system_project.tcl +++ b/projects/motcon2_fmc/zed/system_project.tcl @@ -7,7 +7,7 @@ adi_project_create motcon2_fmc_zed adi_project_files motcon2_fmc_zed [list \ "system_top.v" \ "system_constr.xdc" \ - "$ad_hdl_dir/library/common/ad_iobuf.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \ "$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc" ] set_property PROCESSING_ORDER LATE [get_files system_constr.xdc] diff --git a/projects/pluto/Makefile b/projects/pluto/Makefile new file mode 100644 index 000000000..c7fd953ff --- /dev/null +++ b/projects/pluto/Makefile @@ -0,0 +1,66 @@ +#################################################################################### +#################################################################################### +## Copyright 2011(c) Analog Devices, Inc. +## Auto-generated, do not modify! +#################################################################################### +#################################################################################### + +M_DEPS += system_top.v +M_DEPS += system_project.tcl +M_DEPS += system_constr.xdc +M_DEPS += system_bd.tcl +M_DEPS += ../scripts/adi_project.tcl +M_DEPS += ../scripts/adi_env.tcl +M_DEPS += ../scripts/adi_board.tcl +M_DEPS += ../../library/xilinx/common/ad_iobuf.v +M_DEPS += ../../library/axi_ad9361/axi_ad9361.xpr +M_DEPS += ../../library/axi_dmac/axi_dmac.xpr +M_DEPS += ../../library/util_fir_dec/util_fir_dec.xpr +M_DEPS += ../../library/util_fir_int/util_fir_int.xpr + +M_VIVADO := vivado -mode batch -source + +M_FLIST := *.cache +M_FLIST += *.data +M_FLIST += *.xpr +M_FLIST += *.log +M_FLIST += *.jou +M_FLIST += xgui +M_FLIST += *.runs +M_FLIST += *.srcs +M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim +M_FLIST += .Xil +M_FLIST += *.ip_user_files + + + +.PHONY: all lib clean clean-all +all: lib pluto.sdk/system_top.hdf + + +clean: + rm -rf $(M_FLIST) + + +clean-all:clean + make -C ../../library/axi_ad9361 clean + make -C ../../library/axi_dmac clean + make -C ../../library/util_fir_dec clean + make -C ../../library/util_fir_int clean + + +pluto.sdk/system_top.hdf: $(M_DEPS) + -rm -rf $(M_FLIST) + $(M_VIVADO) system_project.tcl >> pluto_vivado.log 2>&1 + + +lib: + make -C ../../library/axi_ad9361 + make -C ../../library/axi_dmac + make -C ../../library/util_fir_dec + make -C ../../library/util_fir_int + +#################################################################################### +#################################################################################### diff --git a/projects/pluto/system_bd.tcl b/projects/pluto/system_bd.tcl new file mode 100644 index 000000000..2708403a4 --- /dev/null +++ b/projects/pluto/system_bd.tcl @@ -0,0 +1,263 @@ +# create board design +# default ports + +create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr +create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 fixed_io + +create_bd_port -dir O spi0_csn_2_o +create_bd_port -dir O spi0_csn_1_o +create_bd_port -dir O spi0_csn_0_o +create_bd_port -dir I spi0_csn_i +create_bd_port -dir I spi0_clk_i +create_bd_port -dir O spi0_clk_o +create_bd_port -dir I spi0_sdo_i +create_bd_port -dir O spi0_sdo_o +create_bd_port -dir I spi0_sdi_i + +create_bd_port -dir I -from 16 -to 0 gpio_i +create_bd_port -dir O -from 16 -to 0 gpio_o +create_bd_port -dir O -from 16 -to 0 gpio_t + +# interrupts + +create_bd_port -dir I -type intr ps_intr_00 +create_bd_port -dir I -type intr ps_intr_01 +create_bd_port -dir I -type intr ps_intr_02 +create_bd_port -dir I -type intr ps_intr_03 +create_bd_port -dir I -type intr ps_intr_04 +create_bd_port -dir I -type intr ps_intr_05 +create_bd_port -dir I -type intr ps_intr_06 +create_bd_port -dir I -type intr ps_intr_07 +create_bd_port -dir I -type intr ps_intr_08 +create_bd_port -dir I -type intr ps_intr_09 +create_bd_port -dir I -type intr ps_intr_10 +create_bd_port -dir I -type intr ps_intr_11 +create_bd_port -dir I -type intr ps_intr_12 +create_bd_port -dir I -type intr ps_intr_13 +create_bd_port -dir I -type intr ps_intr_14 +create_bd_port -dir I -type intr ps_intr_15 + +# instance: sys_ps7 + +set sys_ps7 [create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 sys_ps7] + +# ps7 settings + +set_property -dict [list CONFIG.PCW_PRESET_BANK0_VOLTAGE {LVCMOS 1.8V}] $sys_ps7 +set_property -dict [list CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 1.8V}] $sys_ps7 +set_property -dict [list CONFIG.PCW_PACKAGE_NAME {clg225}] $sys_ps7 +set_property -dict [list CONFIG.PCW_USE_S_AXI_HP1 {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_USE_S_AXI_HP2 {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_EN_CLK1_PORT {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_EN_RST1_PORT {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100.0}] $sys_ps7 +set_property -dict [list CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ {200.0}] $sys_ps7 +set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_IO {17}] $sys_ps7 +set_property -dict [list CONFIG.PCW_SPI1_PERIPHERAL_ENABLE {0}] $sys_ps7 +set_property -dict [list CONFIG.PCW_I2C0_PERIPHERAL_ENABLE {0}] $sys_ps7 +set_property -dict [list CONFIG.PCW_UART1_PERIPHERAL_ENABLE {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_UART1_UART1_IO {MIO 12 .. 13}] $sys_ps7 +set_property -dict [list CONFIG.PCW_I2C1_PERIPHERAL_ENABLE {0}] $sys_ps7 +set_property -dict [list CONFIG.PCW_QSPI_PERIPHERAL_ENABLE {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_SD0_PERIPHERAL_ENABLE {0}] $sys_ps7 +set_property -dict [list CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_SPI0_SPI0_IO {EMIO}] $sys_ps7 +set_property -dict [list CONFIG.PCW_TTC0_PERIPHERAL_ENABLE {0}] $sys_ps7 +set_property -dict [list CONFIG.PCW_USE_FABRIC_INTERRUPT {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_USB0_PERIPHERAL_ENABLE {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_GPIO_MIO_GPIO_IO {MIO}] $sys_ps7 +set_property -dict [list CONFIG.PCW_USB0_RESET_IO {MIO 52}] $sys_ps7 +set_property -dict [list CONFIG.PCW_USB0_RESET_ENABLE {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_IRQ_F2P_INTR {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_IRQ_F2P_MODE {REVERSE}] $sys_ps7 + +# DDR MT41K256M16 HA-125 (32M, 16bit, 8banks) + +set_property -dict [list CONFIG.PCW_UIPARAM_DDR_PARTNO {MT41K256M16 RE-125}] $sys_ps7 +set_property -dict [list CONFIG.PCW_UIPARAM_DDR_BUS_WIDTH {16 Bit}] $sys_ps7 +set_property -dict [list CONFIG.PCW_UIPARAM_DDR_USE_INTERNAL_VREF {0}] $sys_ps7 +set_property -dict [list CONFIG.PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_UIPARAM_DDR_TRAIN_READ_GATE {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_UIPARAM_DDR_TRAIN_DATA_EYE {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 {0.048}] $sys_ps7 +set_property -dict [list CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 {0.050}] $sys_ps7 +set_property -dict [list CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0 {0.241}] $sys_ps7 +set_property -dict [list CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1 {0.240}] $sys_ps7 + +set sys_concat_intc [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 sys_concat_intc] +set_property -dict [list CONFIG.NUM_PORTS {16}] $sys_concat_intc + +set sys_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 sys_rstgen] +set_property -dict [list CONFIG.C_EXT_RST_WIDTH {1}] $sys_rstgen + +# system reset/clock definitions + +ad_connect sys_cpu_clk sys_ps7/FCLK_CLK0 +ad_connect sys_200m_clk sys_ps7/FCLK_CLK1 +ad_connect sys_cpu_reset sys_rstgen/peripheral_reset +ad_connect sys_cpu_resetn sys_rstgen/peripheral_aresetn +ad_connect sys_cpu_clk sys_rstgen/slowest_sync_clk +ad_connect sys_rstgen/ext_reset_in sys_ps7/FCLK_RESET0_N + +# interface connections + +ad_connect ddr sys_ps7/DDR +ad_connect gpio_i sys_ps7/GPIO_I +ad_connect gpio_o sys_ps7/GPIO_O +ad_connect gpio_t sys_ps7/GPIO_T +ad_connect fixed_io sys_ps7/FIXED_IO + +# spi connections + +ad_connect spi0_csn_2_o sys_ps7/SPI0_SS2_O +ad_connect spi0_csn_1_o sys_ps7/SPI0_SS1_O +ad_connect spi0_csn_0_o sys_ps7/SPI0_SS_O +ad_connect spi0_csn_i sys_ps7/SPI0_SS_I +ad_connect spi0_clk_i sys_ps7/SPI0_SCLK_I +ad_connect spi0_clk_o sys_ps7/SPI0_SCLK_O +ad_connect spi0_sdo_i sys_ps7/SPI0_MOSI_I +ad_connect spi0_sdo_o sys_ps7/SPI0_MOSI_O +ad_connect spi0_sdi_i sys_ps7/SPI0_MISO_I + +# interrupts + +ad_connect sys_concat_intc/dout sys_ps7/IRQ_F2P +ad_connect sys_concat_intc/In15 ps_intr_15 +ad_connect sys_concat_intc/In14 ps_intr_14 +ad_connect sys_concat_intc/In13 ps_intr_13 +ad_connect sys_concat_intc/In12 ps_intr_12 +ad_connect sys_concat_intc/In11 ps_intr_11 +ad_connect sys_concat_intc/In10 ps_intr_10 +ad_connect sys_concat_intc/In9 ps_intr_09 +ad_connect sys_concat_intc/In8 ps_intr_08 +ad_connect sys_concat_intc/In7 ps_intr_07 +ad_connect sys_concat_intc/In6 ps_intr_06 +ad_connect sys_concat_intc/In5 ps_intr_05 +ad_connect sys_concat_intc/In4 ps_intr_04 +ad_connect sys_concat_intc/In3 ps_intr_03 +ad_connect sys_concat_intc/In2 ps_intr_02 +ad_connect sys_concat_intc/In1 ps_intr_01 +ad_connect sys_concat_intc/In0 ps_intr_00 + +# iic + +create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 iic_main + +set axi_iic_main [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_iic:2.0 axi_iic_main] + +ad_connect iic_main axi_iic_main/iic +ad_cpu_interconnect 0x41600000 axi_iic_main +ad_cpu_interrupt ps-15 mb-15 axi_iic_main/iic2intc_irpt + +# ad9361 + +create_bd_port -dir I rx_clk_in +create_bd_port -dir I rx_frame_in +create_bd_port -dir I -from 11 -to 0 rx_data_in + +create_bd_port -dir O tx_clk_out +create_bd_port -dir O tx_frame_out +create_bd_port -dir O -from 11 -to 0 tx_data_out + +create_bd_port -dir O enable +create_bd_port -dir O txnrx +create_bd_port -dir I up_enable +create_bd_port -dir I up_txnrx + +# ad9361 core(s) + +set axi_ad9361 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9361:1.0 axi_ad9361] +set_property -dict [list CONFIG.ID {0}] $axi_ad9361 +set_property -dict [list CONFIG.CMOS_OR_LVDS_N {1}] $axi_ad9361 +set_property -dict [list CONFIG.MODE_1R1T {1}] $axi_ad9361 + +set axi_ad9361_dac_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9361_dac_dma] +set_property -dict [list CONFIG.DMA_TYPE_SRC {0}] $axi_ad9361_dac_dma +set_property -dict [list CONFIG.DMA_TYPE_DEST {2}] $axi_ad9361_dac_dma +set_property -dict [list CONFIG.CYCLIC {1}] $axi_ad9361_dac_dma +set_property -dict [list CONFIG.SYNC_TRANSFER_START {0}] $axi_ad9361_dac_dma +set_property -dict [list CONFIG.AXI_SLICE_SRC {0}] $axi_ad9361_dac_dma +set_property -dict [list CONFIG.AXI_SLICE_DEST {0}] $axi_ad9361_dac_dma +set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9361_dac_dma +set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {32}] $axi_ad9361_dac_dma + +set fir_interpolator [ create_bd_cell -type ip -vlnv analog.com:user:util_fir_int:1.0 fir_interpolator ] +set interp_slice [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 interp_slice ] + +set axi_ad9361_adc_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9361_adc_dma] +set_property -dict [list CONFIG.DMA_TYPE_SRC {2}] $axi_ad9361_adc_dma +set_property -dict [list CONFIG.DMA_TYPE_DEST {0}] $axi_ad9361_adc_dma +set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad9361_adc_dma +set_property -dict [list CONFIG.SYNC_TRANSFER_START {0}] $axi_ad9361_adc_dma +set_property -dict [list CONFIG.AXI_SLICE_SRC {0}] $axi_ad9361_adc_dma +set_property -dict [list CONFIG.AXI_SLICE_DEST {0}] $axi_ad9361_adc_dma +set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9361_adc_dma +set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {32}] $axi_ad9361_adc_dma + +set fir_decimator [ create_bd_cell -type ip -vlnv analog.com:user:util_fir_dec:1.0 fir_decimator ] +set decim_slice [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 decim_slice ] + +# connections + +ad_connect rx_clk_in axi_ad9361/rx_clk_in +ad_connect rx_frame_in axi_ad9361/rx_frame_in +ad_connect rx_data_in axi_ad9361/rx_data_in +ad_connect tx_clk_out axi_ad9361/tx_clk_out +ad_connect tx_frame_out axi_ad9361/tx_frame_out +ad_connect tx_data_out axi_ad9361/tx_data_out +ad_connect enable axi_ad9361/enable +ad_connect txnrx axi_ad9361/txnrx +ad_connect up_enable axi_ad9361/up_enable +ad_connect up_txnrx axi_ad9361/up_txnrx + +ad_connect axi_ad9361/tdd_sync GND +ad_connect sys_200m_clk axi_ad9361/delay_clk +ad_connect axi_ad9361/l_clk axi_ad9361/clk + +ad_connect axi_ad9361/l_clk fir_decimator/aclk +ad_connect axi_ad9361/adc_data_i0 fir_decimator/channel_0 +ad_connect axi_ad9361/adc_data_q0 fir_decimator/channel_1 +ad_connect axi_ad9361/adc_valid_i0 fir_decimator/s_axis_data_tvalid +ad_connect axi_ad9361_adc_dma/fifo_wr_din fir_decimator/m_axis_data_tdata +ad_connect axi_ad9361_adc_dma/fifo_wr_en fir_decimator/m_axis_data_tvalid +ad_connect axi_ad9361/up_adc_gpio_out decim_slice/Din +ad_connect fir_decimator/decimate decim_slice/Dout + +ad_connect axi_ad9361/l_clk fir_interpolator/aclk +ad_connect axi_ad9361_dac_dma/fifo_rd_dout fir_interpolator/s_axis_data_tdata +ad_connect axi_ad9361_dac_dma/fifo_rd_valid fir_interpolator/s_axis_data_tvalid +ad_connect axi_ad9361/dac_valid_i0 fir_interpolator/dac_read +ad_connect axi_ad9361_dac_dma/fifo_rd_en fir_interpolator/s_axis_data_tready +ad_connect axi_ad9361/dac_data_i0 fir_interpolator/channel_0 +ad_connect axi_ad9361/dac_data_q0 fir_interpolator/channel_1 +ad_connect axi_ad9361/up_dac_gpio_out interp_slice/Din +ad_connect fir_interpolator/interpolate interp_slice/Dout + +ad_connect axi_ad9361/l_clk axi_ad9361_adc_dma/fifo_wr_clk +ad_connect axi_ad9361_adc_dma/fifo_wr_overflow axi_ad9361/adc_dovf +ad_connect axi_ad9361/l_clk axi_ad9361_dac_dma/fifo_rd_clk +ad_connect axi_ad9361_dac_dma/fifo_rd_underflow axi_ad9361/dac_dunf +ad_connect axi_ad9361/dac_data_i1 GND +ad_connect axi_ad9361/dac_data_q1 GND + +# interconnects + +ad_cpu_interconnect 0x79020000 axi_ad9361 +ad_cpu_interconnect 0x7C400000 axi_ad9361_adc_dma +ad_cpu_interconnect 0x7C420000 axi_ad9361_dac_dma +ad_mem_hp1_interconnect sys_cpu_clk sys_ps7/S_AXI_HP1 +ad_mem_hp1_interconnect sys_cpu_clk axi_ad9361_adc_dma/m_dest_axi +ad_mem_hp2_interconnect sys_cpu_clk sys_ps7/S_AXI_HP2 +ad_mem_hp2_interconnect sys_cpu_clk axi_ad9361_dac_dma/m_src_axi +ad_connect sys_cpu_resetn axi_ad9361_adc_dma/m_dest_axi_aresetn +ad_connect sys_cpu_resetn axi_ad9361_dac_dma/m_src_axi_aresetn + +# interrupts + +ad_cpu_interrupt ps-13 mb-13 axi_ad9361_adc_dma/irq +ad_cpu_interrupt ps-12 mb-12 axi_ad9361_dac_dma/irq + + diff --git a/projects/pluto/system_constr.xdc b/projects/pluto/system_constr.xdc new file mode 100644 index 000000000..5659c6cff --- /dev/null +++ b/projects/pluto/system_constr.xdc @@ -0,0 +1,204 @@ +# constraints +# ad9361 (SWAP == 0x1) + +set_property -dict {PACKAGE_PIN L12 IOSTANDARD LVCMOS18 } [get_ports rx_clk_in] +set_property -dict {PACKAGE_PIN N13 IOSTANDARD LVCMOS18 } [get_ports rx_frame_in] +set_property -dict {PACKAGE_PIN H14 IOSTANDARD LVCMOS18 } [get_ports rx_data_in[0]] +set_property -dict {PACKAGE_PIN J13 IOSTANDARD LVCMOS18 } [get_ports rx_data_in[1]] +set_property -dict {PACKAGE_PIN G14 IOSTANDARD LVCMOS18 } [get_ports rx_data_in[2]] +set_property -dict {PACKAGE_PIN H13 IOSTANDARD LVCMOS18 } [get_ports rx_data_in[3]] +set_property -dict {PACKAGE_PIN G12 IOSTANDARD LVCMOS18 } [get_ports rx_data_in[4]] +set_property -dict {PACKAGE_PIN H12 IOSTANDARD LVCMOS18 } [get_ports rx_data_in[5]] +set_property -dict {PACKAGE_PIN G11 IOSTANDARD LVCMOS18 } [get_ports rx_data_in[6]] +set_property -dict {PACKAGE_PIN J14 IOSTANDARD LVCMOS18 } [get_ports rx_data_in[7]] +set_property -dict {PACKAGE_PIN J15 IOSTANDARD LVCMOS18 } [get_ports rx_data_in[8]] +set_property -dict {PACKAGE_PIN K15 IOSTANDARD LVCMOS18 } [get_ports rx_data_in[9]] +set_property -dict {PACKAGE_PIN H11 IOSTANDARD LVCMOS18 } [get_ports rx_data_in[10]] +set_property -dict {PACKAGE_PIN J11 IOSTANDARD LVCMOS18 } [get_ports rx_data_in[11]] + +set_property -dict {PACKAGE_PIN P10 IOSTANDARD LVCMOS18} [get_ports tx_clk_out] +set_property -dict {PACKAGE_PIN L14 IOSTANDARD LVCMOS18} [get_ports tx_frame_out] +set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS18} [get_ports tx_data_out[0]] +set_property -dict {PACKAGE_PIN R13 IOSTANDARD LVCMOS18} [get_ports tx_data_out[1]] +set_property -dict {PACKAGE_PIN R15 IOSTANDARD LVCMOS18} [get_ports tx_data_out[2]] +set_property -dict {PACKAGE_PIN P11 IOSTANDARD LVCMOS18} [get_ports tx_data_out[3]] +set_property -dict {PACKAGE_PIN R11 IOSTANDARD LVCMOS18} [get_ports tx_data_out[4]] +set_property -dict {PACKAGE_PIN R12 IOSTANDARD LVCMOS18} [get_ports tx_data_out[5]] +set_property -dict {PACKAGE_PIN P14 IOSTANDARD LVCMOS18} [get_ports tx_data_out[6]] +set_property -dict {PACKAGE_PIN P13 IOSTANDARD LVCMOS18} [get_ports tx_data_out[7]] +set_property -dict {PACKAGE_PIN N9 IOSTANDARD LVCMOS18} [get_ports tx_data_out[8]] +set_property -dict {PACKAGE_PIN M9 IOSTANDARD LVCMOS18} [get_ports tx_data_out[9]] +set_property -dict {PACKAGE_PIN R8 IOSTANDARD LVCMOS18} [get_ports tx_data_out[10]] +set_property -dict {PACKAGE_PIN R7 IOSTANDARD LVCMOS18} [get_ports tx_data_out[11]] + +set_property -dict {PACKAGE_PIN L15 IOSTANDARD LVCMOS18} [get_ports gpio_status[0]] +set_property -dict {PACKAGE_PIN M15 IOSTANDARD LVCMOS18} [get_ports gpio_status[1]] +set_property -dict {PACKAGE_PIN N11 IOSTANDARD LVCMOS18} [get_ports gpio_status[2]] +set_property -dict {PACKAGE_PIN N12 IOSTANDARD LVCMOS18} [get_ports gpio_status[3]] +set_property -dict {PACKAGE_PIN M10 IOSTANDARD LVCMOS18} [get_ports gpio_status[4]] +set_property -dict {PACKAGE_PIN M11 IOSTANDARD LVCMOS18} [get_ports gpio_status[5]] +set_property -dict {PACKAGE_PIN N7 IOSTANDARD LVCMOS18} [get_ports gpio_status[6]] +set_property -dict {PACKAGE_PIN N8 IOSTANDARD LVCMOS18} [get_ports gpio_status[7]] + +set_property -dict {PACKAGE_PIN F13 IOSTANDARD LVCMOS18} [get_ports gpio_ctl[0]] +set_property -dict {PACKAGE_PIN F14 IOSTANDARD LVCMOS18} [get_ports gpio_ctl[1]] +set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVCMOS18} [get_ports gpio_ctl[2]] +set_property -dict {PACKAGE_PIN F15 IOSTANDARD LVCMOS18} [get_ports gpio_ctl[3]] + +set_property -dict {PACKAGE_PIN L13 IOSTANDARD LVCMOS18} [get_ports gpio_en_agc] +set_property -dict {PACKAGE_PIN P9 IOSTANDARD LVCMOS18} [get_ports gpio_resetb] + +set_property -dict {PACKAGE_PIN K12 IOSTANDARD LVCMOS18} [get_ports enable] +set_property -dict {PACKAGE_PIN K11 IOSTANDARD LVCMOS18} [get_ports txnrx] + +set_property -dict {PACKAGE_PIN M14 IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports iic_scl] +set_property -dict {PACKAGE_PIN N14 IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports iic_sda] + +set_property -dict {PACKAGE_PIN E12 IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports spi_csn] +set_property -dict {PACKAGE_PIN E11 IOSTANDARD LVCMOS18} [get_ports spi_clk] +set_property -dict {PACKAGE_PIN E13 IOSTANDARD LVCMOS18} [get_ports spi_mosi] +set_property -dict {PACKAGE_PIN F12 IOSTANDARD LVCMOS18} [get_ports spi_miso] + +set_property -dict {PACKAGE_PIN K13 IOSTANDARD LVCMOS18} [get_ports gpio_bd] +set_property -dict {PACKAGE_PIN P8 IOSTANDARD LVCMOS18} [get_ports clk_out] + +create_clock -name rx_clk -period 16.27 [get_ports rx_clk_in] + +# probably gone in 2016.4 + +create_clock -name clk_fpga_0 -period 10 [get_pins "i_system_wrapper/system_i/sys_ps7/inst/PS7_i/FCLKCLK[0]"] +create_clock -name clk_fpga_1 -period 5 [get_pins "i_system_wrapper/system_i/sys_ps7/inst/PS7_i/FCLKCLK[1]"] + +set_input_jitter clk_fpga_0 0.3 +set_input_jitter clk_fpga_1 0.15 + +set_property IOSTANDARD LVCMOS18 [get_ports *fixed_io_mio*] +set_property SLEW SLOW [get_ports *fixed_io_mio*] +set_property DRIVE 8 [get_ports *fixed_io_mio*] +set_property -dict {PACKAGE_PIN D8 PULLTYPE PULLUP} [get_ports fixed_io_mio[ 0]] +set_property -dict {PACKAGE_PIN A5 PULLTYPE PULLUP} [get_ports fixed_io_mio[ 1]] +set_property -dict {PACKAGE_PIN A8 } [get_ports fixed_io_mio[ 2]] +set_property -dict {PACKAGE_PIN A7 } [get_ports fixed_io_mio[ 3]] +set_property -dict {PACKAGE_PIN C8 } [get_ports fixed_io_mio[ 4]] +set_property -dict {PACKAGE_PIN A9 } [get_ports fixed_io_mio[ 5]] +set_property -dict {PACKAGE_PIN A10 } [get_ports fixed_io_mio[ 6]] +set_property -dict {PACKAGE_PIN D9 } [get_ports fixed_io_mio[ 7]] +set_property -dict {PACKAGE_PIN B6 } [get_ports fixed_io_mio[ 8]] +set_property -dict {PACKAGE_PIN B5 PULLTYPE PULLUP} [get_ports fixed_io_mio[ 9]] +set_property -dict {PACKAGE_PIN D6 PULLTYPE PULLUP} [get_ports fixed_io_mio[10]] +set_property -dict {PACKAGE_PIN B10 PULLTYPE PULLUP} [get_ports fixed_io_mio[11]] +set_property -dict {PACKAGE_PIN B7 PULLTYPE PULLUP} [get_ports fixed_io_mio[12]] +set_property -dict {PACKAGE_PIN C6 PULLTYPE PULLUP} [get_ports fixed_io_mio[13]] +set_property -dict {PACKAGE_PIN B9 PULLTYPE PULLUP} [get_ports fixed_io_mio[14]] +set_property -dict {PACKAGE_PIN D10 PULLTYPE PULLUP} [get_ports fixed_io_mio[15]] +set_property -dict {PACKAGE_PIN A15 PULLTYPE PULLUP} [get_ports fixed_io_mio[16]] +set_property -dict {PACKAGE_PIN D11 PULLTYPE PULLUP} [get_ports fixed_io_mio[17]] +set_property -dict {PACKAGE_PIN B15 PULLTYPE PULLUP} [get_ports fixed_io_mio[18]] +set_property -dict {PACKAGE_PIN C12 PULLTYPE PULLUP} [get_ports fixed_io_mio[19]] +set_property -dict {PACKAGE_PIN E15 PULLTYPE PULLUP} [get_ports fixed_io_mio[20]] +set_property -dict {PACKAGE_PIN C11 PULLTYPE PULLUP} [get_ports fixed_io_mio[21]] +set_property -dict {PACKAGE_PIN D15 PULLTYPE PULLUP} [get_ports fixed_io_mio[22]] +set_property -dict {PACKAGE_PIN A14 PULLTYPE PULLUP} [get_ports fixed_io_mio[23]] +set_property -dict {PACKAGE_PIN B14 PULLTYPE PULLUP} [get_ports fixed_io_mio[24]] +set_property -dict {PACKAGE_PIN C14 PULLTYPE PULLUP} [get_ports fixed_io_mio[25]] +set_property -dict {PACKAGE_PIN A13 PULLTYPE PULLUP} [get_ports fixed_io_mio[26]] +set_property -dict {PACKAGE_PIN D14 PULLTYPE PULLUP} [get_ports fixed_io_mio[27]] +set_property -dict {PACKAGE_PIN B12 PULLTYPE PULLUP} [get_ports fixed_io_mio[28]] +set_property -dict {PACKAGE_PIN D13 PULLTYPE PULLUP} [get_ports fixed_io_mio[29]] +set_property -dict {PACKAGE_PIN A12 PULLTYPE PULLUP} [get_ports fixed_io_mio[30]] +set_property -dict {PACKAGE_PIN C13 PULLTYPE PULLUP} [get_ports fixed_io_mio[31]] + +set_property IOSTANDARD LVCMOS18 [get_ports *fixed_io_ps*] +set_property SLEW SLOW [get_ports *fixed_io_ps*] +set_property DRIVE 8 [get_ports *fixed_io_ps*] +set_property PACKAGE_PIN C7 [get_ports fixed_io_ps_clk] +set_property PACKAGE_PIN C9 [get_ports fixed_io_ps_porb] + +set_property IOSTANDARD SSTL15_T_DCI [get_ports *fixed_io_ddr_vr*] +set_property SLEW FAST [get_ports *fixed_io_ddr_vr*] +set_property PACKAGE_PIN H3 [get_ports fixed_io_ddr_vrp] +set_property PACKAGE_PIN J3 [get_ports fixed_io_ddr_vrn] + +set_property IOSTANDARD DIFF_SSTL15 [get_ports *ddr_ck*] +set_property SLEW FAST [get_ports *ddr_ck*] +set_property PACKAGE_PIN N3 [get_ports ddr_ck_p] +set_property PACKAGE_PIN N2 [get_ports ddr_ck_n] + +set_property IOSTANDARD SSTL15 [get_ports *ddr_addr*] +set_property SLEW SLOW [get_ports *ddr_addr*] +set_property PACKAGE_PIN P1 [get_ports ddr_addr[0]] +set_property PACKAGE_PIN N1 [get_ports ddr_addr[1]] +set_property PACKAGE_PIN M1 [get_ports ddr_addr[2]] +set_property PACKAGE_PIN M4 [get_ports ddr_addr[3]] +set_property PACKAGE_PIN P3 [get_ports ddr_addr[4]] +set_property PACKAGE_PIN P4 [get_ports ddr_addr[5]] +set_property PACKAGE_PIN P5 [get_ports ddr_addr[6]] +set_property PACKAGE_PIN M5 [get_ports ddr_addr[7]] +set_property PACKAGE_PIN P6 [get_ports ddr_addr[8]] +set_property PACKAGE_PIN N4 [get_ports ddr_addr[9]] +set_property PACKAGE_PIN J1 [get_ports ddr_addr[10]] +set_property PACKAGE_PIN L2 [get_ports ddr_addr[11]] +set_property PACKAGE_PIN M2 [get_ports ddr_addr[12]] +set_property PACKAGE_PIN K2 [get_ports ddr_addr[13]] +set_property PACKAGE_PIN K1 [get_ports ddr_addr[14]] + +set_property IOSTANDARD SSTL15 [get_ports *ddr_ba*] +set_property SLEW SLOW [get_ports *ddr_ba*] +set_property PACKAGE_PIN M6 [get_ports ddr_ba[0]] +set_property PACKAGE_PIN R1 [get_ports ddr_ba[1]] +set_property PACKAGE_PIN N6 [get_ports ddr_ba[2]] + +set_property IOSTANDARD SSTL15 [get_ports ddr_reset_n] +set_property SLEW FAST [get_ports ddr_reset_n] +set_property PACKAGE_PIN L4 [get_ports ddr_reset_n] +set_property IOSTANDARD SSTL15 [get_ports ddr_cs_n] +set_property SLEW SLOW [get_ports ddr_cs_n] +set_property PACKAGE_PIN R2 [get_ports ddr_cs_n] +set_property IOSTANDARD SSTL15 [get_ports ddr_ras_n] +set_property SLEW SLOW [get_ports ddr_ras_n] +set_property PACKAGE_PIN R6 [get_ports ddr_ras_n] +set_property IOSTANDARD SSTL15 [get_ports ddr_cas_n] +set_property SLEW SLOW [get_ports ddr_cas_n] +set_property PACKAGE_PIN R5 [get_ports ddr_cas_n] +set_property IOSTANDARD SSTL15 [get_ports ddr_we_n] +set_property SLEW SLOW [get_ports ddr_we_n] +set_property PACKAGE_PIN R3 [get_ports ddr_we_n] +set_property IOSTANDARD SSTL15 [get_ports ddr_cke] +set_property SLEW SLOW [get_ports ddr_cke] +set_property PACKAGE_PIN L3 [get_ports ddr_cke] +set_property IOSTANDARD SSTL15 [get_ports ddr_odt] +set_property SLEW SLOW [get_ports ddr_odt] +set_property PACKAGE_PIN K3 [get_ports ddr_odt] + +set_property IOSTANDARD SSTL15_T_DCI [get_ports *ddr_dq[*]] +set_property SLEW FAST [get_ports *ddr_dq[*]] +set_property PACKAGE_PIN D4 [get_ports ddr_dq[0]] +set_property PACKAGE_PIN A2 [get_ports ddr_dq[1]] +set_property PACKAGE_PIN C4 [get_ports ddr_dq[2]] +set_property PACKAGE_PIN C1 [get_ports ddr_dq[3]] +set_property PACKAGE_PIN B4 [get_ports ddr_dq[4]] +set_property PACKAGE_PIN A4 [get_ports ddr_dq[5]] +set_property PACKAGE_PIN C3 [get_ports ddr_dq[6]] +set_property PACKAGE_PIN A3 [get_ports ddr_dq[7]] +set_property PACKAGE_PIN E1 [get_ports ddr_dq[8]] +set_property PACKAGE_PIN D1 [get_ports ddr_dq[9]] +set_property PACKAGE_PIN E2 [get_ports ddr_dq[10]] +set_property PACKAGE_PIN E3 [get_ports ddr_dq[11]] +set_property PACKAGE_PIN F3 [get_ports ddr_dq[12]] +set_property PACKAGE_PIN G1 [get_ports ddr_dq[13]] +set_property PACKAGE_PIN H1 [get_ports ddr_dq[14]] +set_property PACKAGE_PIN H2 [get_ports ddr_dq[15]] +set_property IOSTANDARD SSTL15_T_DCI [get_ports *ddr_dm[*]] +set_property SLEW FAST [get_ports *ddr_dm[*]] +set_property PACKAGE_PIN B1 [get_ports ddr_dm[0]] +set_property PACKAGE_PIN D3 [get_ports ddr_dm[1]] +set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports *ddr_dqs*] +set_property SLEW FAST [get_ports *ddr_dqs*] +set_property PACKAGE_PIN C2 [get_ports ddr_dqs_p[0]] +set_property PACKAGE_PIN B2 [get_ports ddr_dqs_n[0]] +set_property PACKAGE_PIN G2 [get_ports ddr_dqs_p[1]] +set_property PACKAGE_PIN F2 [get_ports ddr_dqs_n[1]] + +set_false_path -from [get_pins {i_system_wrapper/system_i/axi_ad9361/inst/i_rx/i_up_adc_common/up_adc_gpio_out_int_reg[0]/C}] +set_false_path -from [get_pins {i_system_wrapper/system_i/axi_ad9361/inst/i_tx/i_up_dac_common/up_dac_gpio_out_int_reg[0]/C}] + diff --git a/projects/pluto/system_project.tcl b/projects/pluto/system_project.tcl new file mode 100644 index 000000000..e2dc6281e --- /dev/null +++ b/projects/pluto/system_project.tcl @@ -0,0 +1,17 @@ + +source ../scripts/adi_env.tcl +source $ad_hdl_dir/projects/scripts/adi_project.tcl +source $ad_hdl_dir/projects/scripts/adi_board.tcl + +set p_device "xc7z010clg225-1" +adi_project_create pluto + +adi_project_files pluto [list \ + "system_top.v" \ + "system_constr.xdc" \ + "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v"] + +set_property is_enabled false [get_files *system_sys_ps7_0.xdc] +adi_project_run pluto + + diff --git a/projects/pluto/system_top.v b/projects/pluto/system_top.v new file mode 100644 index 000000000..c74269645 --- /dev/null +++ b/projects/pluto/system_top.v @@ -0,0 +1,172 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top ( + + inout [14:0] ddr_addr, + inout [ 2:0] ddr_ba, + inout ddr_cas_n, + inout ddr_ck_n, + inout ddr_ck_p, + inout ddr_cke, + inout ddr_cs_n, + inout [ 1:0] ddr_dm, + inout [15:0] ddr_dq, + inout [ 1:0] ddr_dqs_n, + inout [ 1:0] ddr_dqs_p, + inout ddr_odt, + inout ddr_ras_n, + inout ddr_reset_n, + inout ddr_we_n, + + inout fixed_io_ddr_vrn, + inout fixed_io_ddr_vrp, + inout [31:0] fixed_io_mio, + inout fixed_io_ps_clk, + inout fixed_io_ps_porb, + inout fixed_io_ps_srstb, + + inout iic_scl, + inout iic_sda, + + inout gpio_bd, + + input rx_clk_in, + input rx_frame_in, + input [11:0] rx_data_in, + output tx_clk_out, + output tx_frame_out, + output [11:0] tx_data_out, + + output enable, + output txnrx, + input clk_out, + + inout gpio_resetb, + inout gpio_en_agc, + inout [ 3:0] gpio_ctl, + inout [ 7:0] gpio_status, + + output spi_csn, + output spi_clk, + output spi_mosi, + input spi_miso); + + // internal signals + + wire [16:0] gpio_i; + wire [16:0] gpio_o; + wire [16:0] gpio_t; + + // instantiations + + ad_iobuf #(.DATA_WIDTH(15)) i_iobuf ( + .dio_t (gpio_t[14:0]), + .dio_i (gpio_o[14:0]), + .dio_o (gpio_i[14:0]), + .dio_p ({ gpio_bd, // 14:14 + gpio_resetb, // 13:13 + gpio_en_agc, // 12:12 + gpio_ctl, // 11: 8 + gpio_status})); // 7: 0 + + system_wrapper i_system_wrapper ( + .ddr_addr (ddr_addr), + .ddr_ba (ddr_ba), + .ddr_cas_n (ddr_cas_n), + .ddr_ck_n (ddr_ck_n), + .ddr_ck_p (ddr_ck_p), + .ddr_cke (ddr_cke), + .ddr_cs_n (ddr_cs_n), + .ddr_dm (ddr_dm), + .ddr_dq (ddr_dq), + .ddr_dqs_n (ddr_dqs_n), + .ddr_dqs_p (ddr_dqs_p), + .ddr_odt (ddr_odt), + .ddr_ras_n (ddr_ras_n), + .ddr_reset_n (ddr_reset_n), + .ddr_we_n (ddr_we_n), + .enable (enable), + .fixed_io_ddr_vrn (fixed_io_ddr_vrn), + .fixed_io_ddr_vrp (fixed_io_ddr_vrp), + .fixed_io_mio (fixed_io_mio), + .fixed_io_ps_clk (fixed_io_ps_clk), + .fixed_io_ps_porb (fixed_io_ps_porb), + .fixed_io_ps_srstb (fixed_io_ps_srstb), + .gpio_i (gpio_i), + .gpio_o (gpio_o), + .gpio_t (gpio_t), + .iic_main_scl_io (iic_scl), + .iic_main_sda_io (iic_sda), + .ps_intr_00 (1'b0), + .ps_intr_01 (1'b0), + .ps_intr_02 (1'b0), + .ps_intr_03 (1'b0), + .ps_intr_04 (1'b0), + .ps_intr_05 (1'b0), + .ps_intr_06 (1'b0), + .ps_intr_07 (1'b0), + .ps_intr_08 (1'b0), + .ps_intr_09 (1'b0), + .ps_intr_10 (1'b0), + .ps_intr_11 (1'b0), + .ps_intr_14 (1'b0), + .rx_clk_in (rx_clk_in), + .rx_data_in (rx_data_in), + .rx_frame_in (rx_frame_in), + .spi0_clk_i (1'b0), + .spi0_clk_o (spi_clk), + .spi0_csn_0_o (spi_csn), + .spi0_csn_1_o (), + .spi0_csn_2_o (), + .spi0_csn_i (1'b1), + .spi0_sdi_i (spi_miso), + .spi0_sdo_i (1'b0), + .spi0_sdo_o (spi_mosi), + .tx_clk_out (tx_clk_out), + .tx_data_out (tx_data_out), + .tx_frame_out (tx_frame_out), + .txnrx (txnrx), + .up_enable (gpio_o[15]), + .up_txnrx (gpio_o[16])); + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/projects/pzsdr/ccbrk/system_bd.tcl b/projects/pzsdr/ccbrk/system_bd.tcl deleted file mode 100644 index 4907eef1b..000000000 --- a/projects/pzsdr/ccbrk/system_bd.tcl +++ /dev/null @@ -1,4 +0,0 @@ - -source $ad_hdl_dir/projects/common/pzsdr/pzsdr_system_bd.tcl -source ../common/ccbrk_bd.tcl - diff --git a/projects/pzsdr/ccbrk/system_constr.xdc b/projects/pzsdr/ccbrk/system_constr.xdc deleted file mode 100644 index 05083fdc9..000000000 --- a/projects/pzsdr/ccbrk/system_constr.xdc +++ /dev/null @@ -1,258 +0,0 @@ - -## constraints -## loopback -## p4 - -set_property -dict {PACKAGE_PIN D4 IOSTANDARD LVCMOS18} [get_ports gp_out[0]] ; ## IO_L2P_T0_33 -set_property -dict {PACKAGE_PIN G4 IOSTANDARD LVCMOS18} [get_ports gp_in[0]] ; ## IO_L1P_T0_33 -set_property -dict {PACKAGE_PIN D3 IOSTANDARD LVCMOS18} [get_ports gp_out[1]] ; ## IO_L2N_T0_33 -set_property -dict {PACKAGE_PIN F4 IOSTANDARD LVCMOS18} [get_ports gp_in[1]] ; ## IO_L1N_T0_33 -set_property -dict {PACKAGE_PIN D1 IOSTANDARD LVCMOS18} [get_ports gp_out[2]] ; ## IO_L4P_T0_33 -set_property -dict {PACKAGE_PIN G2 IOSTANDARD LVCMOS18} [get_ports gp_in[2]] ; ## IO_L3P_T0_DQS_33 -set_property -dict {PACKAGE_PIN C1 IOSTANDARD LVCMOS18} [get_ports gp_out[3]] ; ## IO_L4N_T0_33 -set_property -dict {PACKAGE_PIN F2 IOSTANDARD LVCMOS18} [get_ports gp_in[3]] ; ## IO_L3N_T0_DQS_33 -set_property -dict {PACKAGE_PIN F3 IOSTANDARD LVCMOS18} [get_ports gp_out[4]] ; ## IO_L6P_T0_33 -set_property -dict {PACKAGE_PIN E2 IOSTANDARD LVCMOS18} [get_ports gp_in[4]] ; ## IO_L5P_T0_33 -set_property -dict {PACKAGE_PIN E3 IOSTANDARD LVCMOS18} [get_ports gp_out[5]] ; ## IO_L6N_T0_VREF_33 -set_property -dict {PACKAGE_PIN E1 IOSTANDARD LVCMOS18} [get_ports gp_in[5]] ; ## IO_L5N_T0_33 -set_property -dict {PACKAGE_PIN H4 IOSTANDARD LVCMOS18} [get_ports gp_out[6]] ; ## IO_L8P_T1_33 -set_property -dict {PACKAGE_PIN J1 IOSTANDARD LVCMOS18} [get_ports gp_in[6]] ; ## IO_L7P_T1_33 -set_property -dict {PACKAGE_PIN H3 IOSTANDARD LVCMOS18} [get_ports gp_out[7]] ; ## IO_L8N_T1_33 -set_property -dict {PACKAGE_PIN H1 IOSTANDARD LVCMOS18} [get_ports gp_in[7]] ; ## IO_L7N_T1_33 -set_property -dict {PACKAGE_PIN H2 IOSTANDARD LVCMOS18} [get_ports gp_out[8]] ; ## IO_L10P_T1_33 -set_property -dict {PACKAGE_PIN K2 IOSTANDARD LVCMOS18} [get_ports gp_in[8]] ; ## IO_L9P_T1_DQS_33 -set_property -dict {PACKAGE_PIN G1 IOSTANDARD LVCMOS18} [get_ports gp_out[9]] ; ## IO_L10N_T1_33 -set_property -dict {PACKAGE_PIN K1 IOSTANDARD LVCMOS18} [get_ports gp_in[9]] ; ## IO_L9N_T1_DQS_33 -set_property -dict {PACKAGE_PIN J4 IOSTANDARD LVCMOS18} [get_ports gp_out[10]] ; ## IO_L12P_T1_MRCC_33 -set_property -dict {PACKAGE_PIN L3 IOSTANDARD LVCMOS18} [get_ports gp_in[10]] ; ## IO_L11P_T1_SRCC_33 - -## p5 - -set_property -dict {PACKAGE_PIN N4 IOSTANDARD LVCMOS18} [get_ports gp_out[11]] ; ## IO_L17P_T2_33 -set_property -dict {PACKAGE_PIN M2 IOSTANDARD LVCMOS18} [get_ports gp_in[11]] ; ## IO_L16P_T2_33 -set_property -dict {PACKAGE_PIN M4 IOSTANDARD LVCMOS18} [get_ports gp_out[12]] ; ## IO_L17N_T2_33 -set_property -dict {PACKAGE_PIN L2 IOSTANDARD LVCMOS18} [get_ports gp_in[12]] ; ## IO_L16N_T2_33 -set_property -dict {PACKAGE_PIN M7 IOSTANDARD LVCMOS18} [get_ports gp_out[13]] ; ## IO_L19P_T3_33 -set_property -dict {PACKAGE_PIN N1 IOSTANDARD LVCMOS18} [get_ports gp_in[13]] ; ## IO_L18P_T2_33 -set_property -dict {PACKAGE_PIN L7 IOSTANDARD LVCMOS18} [get_ports gp_out[14]] ; ## IO_L19N_T3_VREF_33 -set_property -dict {PACKAGE_PIN M1 IOSTANDARD LVCMOS18} [get_ports gp_in[14]] ; ## IO_L18N_T2_33 -set_property -dict {PACKAGE_PIN K5 IOSTANDARD LVCMOS18} [get_ports gp_out[15]] ; ## IO_L20P_T3_33 -set_property -dict {PACKAGE_PIN M8 IOSTANDARD LVCMOS18} [get_ports gp_in[15]] ; ## IO_L21P_T3_DQS_33 -set_property -dict {PACKAGE_PIN J5 IOSTANDARD LVCMOS18} [get_ports gp_out[16]] ; ## IO_L20N_T3_33 -set_property -dict {PACKAGE_PIN L8 IOSTANDARD LVCMOS18} [get_ports gp_in[16]] ; ## IO_L21N_T3_DQS_33 -set_property -dict {PACKAGE_PIN K6 IOSTANDARD LVCMOS18} [get_ports gp_out[17]] ; ## IO_L22P_T3_33 -set_property -dict {PACKAGE_PIN N7 IOSTANDARD LVCMOS18} [get_ports gp_in[17]] ; ## IO_L23P_T3_33 -set_property -dict {PACKAGE_PIN J6 IOSTANDARD LVCMOS18} [get_ports gp_out[18]] ; ## IO_L22N_T3_33 -set_property -dict {PACKAGE_PIN N6 IOSTANDARD LVCMOS18} [get_ports gp_in[18]] ; ## IO_L23N_T3_33 -set_property -dict {PACKAGE_PIN K10 IOSTANDARD LVCMOS18} [get_ports gp_out[19]] ; ## IO_25_VRP_34 -set_property -dict {PACKAGE_PIN D5 IOSTANDARD LVCMOS18} [get_ports gp_in[19]] ; ## IO_L10N_T1_34 -set_property -dict {PACKAGE_PIN L5 IOSTANDARD LVCMOS18} [get_ports gp_out[20]] ; ## IO_L14P_T2_SRCC_33 -set_property -dict {PACKAGE_PIN K8 IOSTANDARD LVCMOS18} [get_ports gp_in[20]] ; ## IO_L24P_T3_33 -set_property -dict {PACKAGE_PIN L4 IOSTANDARD LVCMOS18} [get_ports gp_out[21]] ; ## IO_L14N_T2_SRCC_33 -set_property -dict {PACKAGE_PIN K7 IOSTANDARD LVCMOS18} [get_ports gp_in[21]] ; ## IO_L24N_T3_33 -set_property -dict {PACKAGE_PIN M6 IOSTANDARD LVCMOS18} [get_ports gp_out[22]] ; ## IO_L13P_T2_MRCC_33 -set_property -dict {PACKAGE_PIN N3 IOSTANDARD LVCMOS18} [get_ports gp_in[22]] ; ## IO_L15P_T2_DQS_33 -set_property -dict {PACKAGE_PIN M5 IOSTANDARD LVCMOS18} [get_ports gp_out[23]] ; ## IO_L13N_T2_MRCC_33 -set_property -dict {PACKAGE_PIN N2 IOSTANDARD LVCMOS18} [get_ports gp_in[23]] ; ## IO_L15N_T2_DQS_33 - -## p6 - -set_property -dict {PACKAGE_PIN G6 IOSTANDARD LVCMOS18} [get_ports gp_out[24]] ; ## IO_L2P_T0_34 -set_property -dict {PACKAGE_PIN J11 IOSTANDARD LVCMOS18} [get_ports gp_in[24]] ; ## IO_L1P_T0_34 -set_property -dict {PACKAGE_PIN G5 IOSTANDARD LVCMOS18} [get_ports gp_out[25]] ; ## IO_L2N_T0_34 -set_property -dict {PACKAGE_PIN H11 IOSTANDARD LVCMOS18} [get_ports gp_in[25]] ; ## IO_L1N_T0_34 -set_property -dict {PACKAGE_PIN H7 IOSTANDARD LVCMOS18} [get_ports gp_out[26]] ; ## IO_L4P_T0_34 -set_property -dict {PACKAGE_PIN H9 IOSTANDARD LVCMOS18} [get_ports gp_in[26]] ; ## IO_L3P_T0_DQS_PUDC_B_34 -set_property -dict {PACKAGE_PIN H6 IOSTANDARD LVCMOS18} [get_ports gp_out[27]] ; ## IO_L4N_T0_34 -set_property -dict {PACKAGE_PIN G9 IOSTANDARD LVCMOS18} [get_ports gp_in[27]] ; ## IO_L3N_T0_DQS_34 -set_property -dict {PACKAGE_PIN J8 IOSTANDARD LVCMOS18} [get_ports gp_out[28]] ; ## IO_L6P_T0_34 -set_property -dict {PACKAGE_PIN J10 IOSTANDARD LVCMOS18} [get_ports gp_in[28]] ; ## IO_L5P_T0_34 -set_property -dict {PACKAGE_PIN H8 IOSTANDARD LVCMOS18} [get_ports gp_out[29]] ; ## IO_L6N_T0_VREF_34 -set_property -dict {PACKAGE_PIN J9 IOSTANDARD LVCMOS18} [get_ports gp_in[29]] ; ## IO_L5N_T0_34 -set_property -dict {PACKAGE_PIN D9 IOSTANDARD LVCMOS18} [get_ports gp_out[30]] ; ## IO_L8P_T1_34 -set_property -dict {PACKAGE_PIN F5 IOSTANDARD LVCMOS18} [get_ports gp_in[30]] ; ## IO_L7P_T1_34 -set_property -dict {PACKAGE_PIN G7 IOSTANDARD LVCMOS18} [get_ports gp_out[31]] ; ## IO_L12P_T1_MRCC_34 -set_property -dict {PACKAGE_PIN F8 IOSTANDARD LVCMOS18} [get_ports gp_in[31]] ; ## IO_L11P_T1_SRCC_34 -set_property -dict {PACKAGE_PIN F7 IOSTANDARD LVCMOS18} [get_ports gp_out[32]] ; ## IO_L12N_T1_MRCC_34 -set_property -dict {PACKAGE_PIN E7 IOSTANDARD LVCMOS18} [get_ports gp_in[32]] ; ## IO_L11N_T1_SRCC_34 - -## p7 - -set_property -dict {PACKAGE_PIN D6 IOSTANDARD LVCMOS18} [get_ports gp_out[33]] ; ## IO_L14P_T2_SRCC_34 -set_property -dict {PACKAGE_PIN C8 IOSTANDARD LVCMOS18} [get_ports gp_in[33]] ; ## IO_L13P_T2_MRCC_34 -set_property -dict {PACKAGE_PIN C6 IOSTANDARD LVCMOS18} [get_ports gp_out[34]] ; ## IO_L14N_T2_SRCC_34 -set_property -dict {PACKAGE_PIN C7 IOSTANDARD LVCMOS18} [get_ports gp_in[34]] ; ## IO_L13N_T2_MRCC_34 -set_property -dict {PACKAGE_PIN B10 IOSTANDARD LVCMOS18} [get_ports gp_out[35]] ; ## IO_L16P_T2_34 -set_property -dict {PACKAGE_PIN C9 IOSTANDARD LVCMOS18} [get_ports gp_in[35]] ; ## IO_L15P_T2_DQS_34 -set_property -dict {PACKAGE_PIN A10 IOSTANDARD LVCMOS18} [get_ports gp_out[36]] ; ## IO_L16N_T2_34 -set_property -dict {PACKAGE_PIN B9 IOSTANDARD LVCMOS18} [get_ports gp_in[36]] ; ## IO_L15N_T2_DQS_34 -set_property -dict {PACKAGE_PIN B5 IOSTANDARD LVCMOS18} [get_ports gp_out[37]] ; ## IO_L20P_T3_34 -set_property -dict {PACKAGE_PIN C4 IOSTANDARD LVCMOS18} [get_ports gp_in[37]] ; ## IO_L19P_T3_34 -set_property -dict {PACKAGE_PIN B4 IOSTANDARD LVCMOS18} [get_ports gp_out[38]] ; ## IO_L20N_T3_34 -set_property -dict {PACKAGE_PIN C3 IOSTANDARD LVCMOS18} [get_ports gp_in[38]] ; ## IO_L19N_T3_VREF_34 -set_property -dict {PACKAGE_PIN A4 IOSTANDARD LVCMOS18} [get_ports gp_out[39]] ; ## IO_L22P_T3_34 -set_property -dict {PACKAGE_PIN B6 IOSTANDARD LVCMOS18} [get_ports gp_in[39]] ; ## IO_L21P_T3_DQS_34 -set_property -dict {PACKAGE_PIN A3 IOSTANDARD LVCMOS18} [get_ports gp_out[40]] ; ## IO_L22N_T3_34 -set_property -dict {PACKAGE_PIN A5 IOSTANDARD LVCMOS18} [get_ports gp_in[40]] ; ## IO_L21N_T3_DQS_34 -set_property -dict {PACKAGE_PIN L9 IOSTANDARD LVCMOS18} [get_ports gp_out[41]] ; ## IO_0_VRN_33 -set_property -dict {PACKAGE_PIN B7 IOSTANDARD LVCMOS18} [get_ports gp_in[41]] ; ## IO_L18P_T2_34 -set_property -dict {PACKAGE_PIN A7 IOSTANDARD LVCMOS18} [get_ports gp_out[42]] ; ## IO_L18N_T2_34 -set_property -dict {PACKAGE_PIN N8 IOSTANDARD LVCMOS18} [get_ports gp_in[42]] ; ## IO_25_VRP_33 - -## p13 - -set_property -dict {PACKAGE_PIN AF15 IOSTANDARD LVCMOS25} [get_ports gp_out[43]] ; ## IO_L16P_T2_12 -set_property -dict {PACKAGE_PIN AD16 IOSTANDARD LVCMOS25} [get_ports gp_in[43]] ; ## IO_L15P_T2_DQS_12 -set_property -dict {PACKAGE_PIN AF14 IOSTANDARD LVCMOS25} [get_ports gp_out[44]] ; ## IO_L16N_T2_12 -set_property -dict {PACKAGE_PIN AD15 IOSTANDARD LVCMOS25} [get_ports gp_in[44]] ; ## IO_L15N_T2_DQS_12 -set_property -dict {PACKAGE_PIN AB15 IOSTANDARD LVCMOS25} [get_ports gp_out[45]] ; ## IO_L14P_T2_SRCC_12 -set_property -dict {PACKAGE_PIN AC14 IOSTANDARD LVCMOS25} [get_ports gp_in[45]] ; ## IO_L13P_T2_MRCC_12 -set_property -dict {PACKAGE_PIN AB14 IOSTANDARD LVCMOS25} [get_ports gp_out[46]] ; ## IO_L14N_T2_SRCC_12 -set_property -dict {PACKAGE_PIN AD14 IOSTANDARD LVCMOS25} [get_ports gp_in[46]] ; ## IO_L13N_T2_MRCC_12 -set_property -dict {PACKAGE_PIN AC13 IOSTANDARD LVCMOS25} [get_ports gp_out[47]] ; ## IO_L12P_T1_MRCC_12 -set_property -dict {PACKAGE_PIN AC12 IOSTANDARD LVCMOS25} [get_ports gp_in[47]] ; ## IO_L11P_T1_SRCC_12 -set_property -dict {PACKAGE_PIN AD13 IOSTANDARD LVCMOS25} [get_ports gp_out[48]] ; ## IO_L12N_T1_MRCC_12 -set_property -dict {PACKAGE_PIN AD11 IOSTANDARD LVCMOS25} [get_ports gp_in[48]] ; ## IO_L11N_T1_SRCC_12 -set_property -dict {PACKAGE_PIN AE13 IOSTANDARD LVCMOS25} [get_ports gp_out[49]] ; ## IO_L10P_T1_12 -set_property -dict {PACKAGE_PIN AE11 IOSTANDARD LVCMOS25} [get_ports gp_in[49]] ; ## IO_L9P_T1_DQS_12 -set_property -dict {PACKAGE_PIN AF13 IOSTANDARD LVCMOS25} [get_ports gp_out[50]] ; ## IO_L10N_T1_12 -set_property -dict {PACKAGE_PIN AF10 IOSTANDARD LVCMOS25} [get_ports gp_in[50]] ; ## IO_L9N_T1_DQS_12 -set_property -dict {PACKAGE_PIN AE12 IOSTANDARD LVCMOS25} [get_ports gp_out[51]] ; ## IO_L8P_T1_12 -set_property -dict {PACKAGE_PIN AE10 IOSTANDARD LVCMOS25} [get_ports gp_in[51]] ; ## IO_L7P_T1_12 -set_property -dict {PACKAGE_PIN AF12 IOSTANDARD LVCMOS25} [get_ports gp_out[52]] ; ## IO_L8N_T1_12 -set_property -dict {PACKAGE_PIN AD10 IOSTANDARD LVCMOS25} [get_ports gp_in[52]] ; ## IO_L7N_T1_12 -set_property -dict {PACKAGE_PIN AA13 IOSTANDARD LVCMOS25} [get_ports gp_out[53]] ; ## IO_L6P_T0_12 -set_property -dict {PACKAGE_PIN W13 IOSTANDARD LVCMOS25} [get_ports gp_in[53]] ; ## IO_L5P_T0_12 -set_property -dict {PACKAGE_PIN AA12 IOSTANDARD LVCMOS25} [get_ports gp_out[54]] ; ## IO_L6N_T0_VREF_12 -set_property -dict {PACKAGE_PIN Y13 IOSTANDARD LVCMOS25} [get_ports gp_in[54]] ; ## IO_L5N_T0_12 -set_property -dict {PACKAGE_PIN AB11 IOSTANDARD LVCMOS25} [get_ports gp_out[55]] ; ## IO_L4P_T0_12 -set_property -dict {PACKAGE_PIN Y10 IOSTANDARD LVCMOS25} [get_ports gp_in[55]] ; ## IO_L3P_T0_DQS_12 -set_property -dict {PACKAGE_PIN AB10 IOSTANDARD LVCMOS25} [get_ports gp_out[56]] ; ## IO_L4N_T0_12 -set_property -dict {PACKAGE_PIN AA10 IOSTANDARD LVCMOS25} [get_ports gp_in[56]] ; ## IO_L3N_T0_DQS_12 -set_property -dict {PACKAGE_PIN AB12 IOSTANDARD LVCMOS25} [get_ports gp_out[57]] ; ## IO_L2P_T0_12 -set_property -dict {PACKAGE_PIN Y12 IOSTANDARD LVCMOS25} [get_ports gp_in[57]] ; ## IO_L1P_T0_12 -set_property -dict {PACKAGE_PIN AC11 IOSTANDARD LVCMOS25} [get_ports gp_out[58]] ; ## IO_L2N_T0_12 -set_property -dict {PACKAGE_PIN Y11 IOSTANDARD LVCMOS25} [get_ports gp_in[58]] ; ## IO_L1N_T0_12 -set_property -dict {PACKAGE_PIN AE17 IOSTANDARD LVCMOS25} [get_ports gp_out[59]] ; ## IO_L18P_T2_12 -set_property -dict {PACKAGE_PIN AE16 IOSTANDARD LVCMOS25} [get_ports gp_in[59]] ; ## IO_L17P_T2_12 -set_property -dict {PACKAGE_PIN AF17 IOSTANDARD LVCMOS25} [get_ports gp_out[60]] ; ## IO_L18N_T2_12 -set_property -dict {PACKAGE_PIN AE15 IOSTANDARD LVCMOS25} [get_ports gp_in[60]] ; ## IO_L17N_T2_12 -set_property -dict {PACKAGE_PIN AB17 IOSTANDARD LVCMOS25} [get_ports gp_out[61]] ; ## IO_L20P_T3_12 -set_property -dict {PACKAGE_PIN Y17 IOSTANDARD LVCMOS25} [get_ports gp_in[61]] ; ## IO_L19P_T3_12 -set_property -dict {PACKAGE_PIN AB16 IOSTANDARD LVCMOS25} [get_ports gp_out[62]] ; ## IO_L20N_T3_12 -set_property -dict {PACKAGE_PIN AA17 IOSTANDARD LVCMOS25} [get_ports gp_in[62]] ; ## IO_L19N_T3_VREF_12 -set_property -dict {PACKAGE_PIN AA15 IOSTANDARD LVCMOS25} [get_ports gp_out[63]] ; ## IO_L22P_T3_12 -set_property -dict {PACKAGE_PIN AC17 IOSTANDARD LVCMOS25} [get_ports gp_in[63]] ; ## IO_L21P_T3_DQS_12 -set_property -dict {PACKAGE_PIN AA14 IOSTANDARD LVCMOS25} [get_ports gp_out[64]] ; ## IO_L22N_T3_12 -set_property -dict {PACKAGE_PIN AC16 IOSTANDARD LVCMOS25} [get_ports gp_in[64]] ; ## IO_L21N_T3_DQS_12 - -## p2 - -set_property -dict {PACKAGE_PIN V18 IOSTANDARD LVCMOS25} [get_ports gp_out[65]] ; ## IO_25_13 -set_property -dict {PACKAGE_PIN AA24 IOSTANDARD LVCMOS25} [get_ports gp_in[65]] ; ## IO_L6P_T0_13 -set_property -dict {PACKAGE_PIN AB26 IOSTANDARD LVCMOS25} [get_ports gp_out[66]] ; ## IO_L2P_T0_13 -set_property -dict {PACKAGE_PIN AA25 IOSTANDARD LVCMOS25} [get_ports gp_in[66]] ; ## IO_L1P_T0_13 -set_property -dict {PACKAGE_PIN AC26 IOSTANDARD LVCMOS25} [get_ports gp_out[67]] ; ## IO_L2N_T0_13 -set_property -dict {PACKAGE_PIN AB25 IOSTANDARD LVCMOS25} [get_ports gp_in[67]] ; ## IO_L1N_T0_13 -set_property -dict {PACKAGE_PIN AD25 IOSTANDARD LVCMOS25} [get_ports gp_out[68]] ; ## IO_L4P_T0_13 -set_property -dict {PACKAGE_PIN AE25 IOSTANDARD LVCMOS25} [get_ports gp_in[68]] ; ## IO_L3P_T0_DQS_13 -set_property -dict {PACKAGE_PIN AD26 IOSTANDARD LVCMOS25} [get_ports gp_out[69]] ; ## IO_L4N_T0_13 -set_property -dict {PACKAGE_PIN AE26 IOSTANDARD LVCMOS25} [get_ports gp_in[69]] ; ## IO_L3N_T0_DQS_13 -set_property -dict {PACKAGE_PIN AE23 IOSTANDARD LVCMOS25} [get_ports gp_out[70]] ; ## IO_L8P_T1_13 -set_property -dict {PACKAGE_PIN AE22 IOSTANDARD LVCMOS25} [get_ports gp_in[70]] ; ## IO_L7P_T1_13 -set_property -dict {PACKAGE_PIN AF23 IOSTANDARD LVCMOS25} [get_ports gp_out[71]] ; ## IO_L8N_T1_13 -set_property -dict {PACKAGE_PIN AF22 IOSTANDARD LVCMOS25} [get_ports gp_in[71]] ; ## IO_L7N_T1_13 -set_property -dict {PACKAGE_PIN AA22 IOSTANDARD LVCMOS25} [get_ports gp_out[72]] ; ## IO_L10P_T1_13 -set_property -dict {PACKAGE_PIN AB21 IOSTANDARD LVCMOS25} [get_ports gp_in[72]] ; ## IO_L9P_T1_DQS_13 -set_property -dict {PACKAGE_PIN AA23 IOSTANDARD LVCMOS25} [get_ports gp_out[73]] ; ## IO_L10N_T1_13 -set_property -dict {PACKAGE_PIN AB22 IOSTANDARD LVCMOS25} [get_ports gp_in[73]] ; ## IO_L9N_T1_DQS_13 -set_property -dict {PACKAGE_PIN AC23 IOSTANDARD LVCMOS25} [get_ports gp_out[74]] ; ## IO_L12P_T1_MRCC_13 -set_property -dict {PACKAGE_PIN AD23 IOSTANDARD LVCMOS25} [get_ports gp_in[74]] ; ## IO_L11P_T1_SRCC_13 -set_property -dict {PACKAGE_PIN AC24 IOSTANDARD LVCMOS25} [get_ports gp_out[75]] ; ## IO_L12N_T1_MRCC_13 -set_property -dict {PACKAGE_PIN AD24 IOSTANDARD LVCMOS25} [get_ports gp_in[75]] ; ## IO_L11N_T1_SRCC_13 -set_property -dict {PACKAGE_PIN AC21 IOSTANDARD LVCMOS25} [get_ports gp_out[76]] ; ## IO_L14P_T2_SRCC_13 -set_property -dict {PACKAGE_PIN AD20 IOSTANDARD LVCMOS25} [get_ports gp_in[76]] ; ## IO_L13P_T2_MRCC_13 -set_property -dict {PACKAGE_PIN AC22 IOSTANDARD LVCMOS25} [get_ports gp_out[77]] ; ## IO_L14N_T2_SRCC_13 -set_property -dict {PACKAGE_PIN AD21 IOSTANDARD LVCMOS25} [get_ports gp_in[77]] ; ## IO_L13N_T2_MRCC_13 -set_property -dict {PACKAGE_PIN AE20 IOSTANDARD LVCMOS25} [get_ports gp_out[78]] ; ## IO_L16P_T2_13 -set_property -dict {PACKAGE_PIN AF19 IOSTANDARD LVCMOS25} [get_ports gp_in[78]] ; ## IO_L15P_T2_DQS_13 -set_property -dict {PACKAGE_PIN AE21 IOSTANDARD LVCMOS25} [get_ports gp_out[79]] ; ## IO_L16N_T2_13 -set_property -dict {PACKAGE_PIN AF20 IOSTANDARD LVCMOS25} [get_ports gp_in[79]] ; ## IO_L15N_T2_DQS_13 -set_property -dict {PACKAGE_PIN AE18 IOSTANDARD LVCMOS25} [get_ports gp_out[80]] ; ## IO_L18P_T2_13 -set_property -dict {PACKAGE_PIN AD18 IOSTANDARD LVCMOS25} [get_ports gp_in[80]] ; ## IO_L17P_T2_13 -set_property -dict {PACKAGE_PIN AF18 IOSTANDARD LVCMOS25} [get_ports gp_out[81]] ; ## IO_L18N_T2_13 -set_property -dict {PACKAGE_PIN AD19 IOSTANDARD LVCMOS25} [get_ports gp_in[81]] ; ## IO_L17N_T2_13 -set_property -dict {PACKAGE_PIN AA20 IOSTANDARD LVCMOS25} [get_ports gp_out[82]] ; ## IO_L20P_T3_13 -set_property -dict {PACKAGE_PIN W20 IOSTANDARD LVCMOS25} [get_ports gp_in[82]] ; ## IO_L19P_T3_13 -set_property -dict {PACKAGE_PIN AB20 IOSTANDARD LVCMOS25} [get_ports gp_out[83]] ; ## IO_L20N_T3_13 -set_property -dict {PACKAGE_PIN Y20 IOSTANDARD LVCMOS25} [get_ports gp_in[83]] ; ## IO_L19N_T3_VREF_13 -set_property -dict {PACKAGE_PIN AA19 IOSTANDARD LVCMOS25} [get_ports gp_out[84]] ; ## IO_L22P_T3_13 -set_property -dict {PACKAGE_PIN AC18 IOSTANDARD LVCMOS25} [get_ports gp_in[84]] ; ## IO_L21P_T3_DQS_13 -set_property -dict {PACKAGE_PIN AB19 IOSTANDARD LVCMOS25} [get_ports gp_out[85]] ; ## IO_L22N_T3_13 -set_property -dict {PACKAGE_PIN AC19 IOSTANDARD LVCMOS25} [get_ports gp_in[85]] ; ## IO_L21N_T3_DQS_13 -set_property -dict {PACKAGE_PIN Y18 IOSTANDARD LVCMOS25} [get_ports gp_out[86]] ; ## IO_L24P_T3_13 -set_property -dict {PACKAGE_PIN W18 IOSTANDARD LVCMOS25} [get_ports gp_in[86]] ; ## IO_L23P_T3_13 -set_property -dict {PACKAGE_PIN AA18 IOSTANDARD LVCMOS25} [get_ports gp_out[87]] ; ## IO_L24N_T3_13 -set_property -dict {PACKAGE_PIN W19 IOSTANDARD LVCMOS25} [get_ports gp_in[87]] ; ## IO_L23N_T3_13 - -## vcc - -set_property -dict {PACKAGE_PIN AB24 IOSTANDARD LVCMOS25} [get_ports gp_in_1] ; ## IO_L6N_T0_VREF_13 - -## on board - -set_property -dict {PACKAGE_PIN W6} [get_ports gt_ref_clk_p] ; ## MGTREFCLK0P_111 -set_property -dict {PACKAGE_PIN W5} [get_ports gt_ref_clk_n] ; ## MGTREFCLK0N_111 -set_property -dict {PACKAGE_PIN AD8} [get_ports gt_rx_p[0]] ; ## MGTXRXP0_111 -set_property -dict {PACKAGE_PIN AD7} [get_ports gt_rx_n[0]] ; ## MGTXRXN0_111 -set_property -dict {PACKAGE_PIN AE6} [get_ports gt_rx_p[1]] ; ## MGTXRXP1_111 -set_property -dict {PACKAGE_PIN AE5} [get_ports gt_rx_n[1]] ; ## MGTXRXN1_111 -set_property -dict {PACKAGE_PIN AC6} [get_ports gt_rx_p[2]] ; ## MGTXRXP2_111 -set_property -dict {PACKAGE_PIN AC5} [get_ports gt_rx_n[2]] ; ## MGTXRXN2_111 -set_property -dict {PACKAGE_PIN AD4} [get_ports gt_rx_p[3]] ; ## MGTXRXP3_111 -set_property -dict {PACKAGE_PIN AD3} [get_ports gt_rx_n[3]] ; ## MGTXRXN3_111 -set_property -dict {PACKAGE_PIN AF8} [get_ports gt_tx_p[0]] ; ## MGTXTXP0_111 -set_property -dict {PACKAGE_PIN AF7} [get_ports gt_tx_n[0]] ; ## MGTXTXN0_111 -set_property -dict {PACKAGE_PIN AF4} [get_ports gt_tx_p[1]] ; ## MGTXTXP1_111 -set_property -dict {PACKAGE_PIN AF3} [get_ports gt_tx_n[1]] ; ## MGTXTXN1_111 -set_property -dict {PACKAGE_PIN AE2} [get_ports gt_tx_p[2]] ; ## MGTXTXP2_111 -set_property -dict {PACKAGE_PIN AE1} [get_ports gt_tx_n[2]] ; ## MGTXTXN2_111 -set_property -dict {PACKAGE_PIN AC2} [get_ports gt_tx_p[3]] ; ## MGTXTXP3_111 -set_property -dict {PACKAGE_PIN AC1} [get_ports gt_tx_n[3]] ; ## MGTXTXN3_111 - -## clocks - -create_clock -name ref_clk -period 4.00 [get_ports gt_ref_clk_p] -create_clock -name tx_div_clk -period 8.00 [get_pins i_system_wrapper/system_i/axi_pzslb_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/TXOUTCLK] -create_clock -name rx_div_clk -period 8.00 [get_pins i_system_wrapper/system_i/axi_pzslb_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK] -create_clock -name tx_div_clk -period 8.00 [get_pins i_system_wrapper/system_i/axi_pzslb_gt/inst/g_lane_1[1].i_channel/i_gt/i_gtxe2_channel/TXOUTCLK] -create_clock -name rx_div_clk -period 8.00 [get_pins i_system_wrapper/system_i/axi_pzslb_gt/inst/g_lane_1[1].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK] -create_clock -name tx_div_clk -period 8.00 [get_pins i_system_wrapper/system_i/axi_pzslb_gt/inst/g_lane_1[2].i_channel/i_gt/i_gtxe2_channel/TXOUTCLK] -create_clock -name rx_div_clk -period 8.00 [get_pins i_system_wrapper/system_i/axi_pzslb_gt/inst/g_lane_1[2].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK] -create_clock -name tx_div_clk -period 8.00 [get_pins i_system_wrapper/system_i/axi_pzslb_gt/inst/g_lane_1[3].i_channel/i_gt/i_gtxe2_channel/TXOUTCLK] -create_clock -name rx_div_clk -period 8.00 [get_pins i_system_wrapper/system_i/axi_pzslb_gt/inst/g_lane_1[3].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK] - -## MIO loopbacks (fixed-io) -## the following are connected to AD9361 GPIO - -## JX4.86 A23 PS_MIO12_500_JX4 <==> JX4.2 NA AD9361_GPO1 -## JX4.88 B26 PS_MIO11_500_JX4 <==> JX4.1 NA AD9361_GPO0 -## JX4.91 B25 PS_MIO13_500_JX4 <==> JX4.3 NA AD9361_GPO2 -## JX4.93 D23 PS_MIO14_500_JX4 <==> JX4.4 NA AD9361_GPO3 - -## the following are mio-to-mio loopback (excluding Push-Buttons to LED) - -## JX4.92 E17 PS_MIO46_501_JX4 <==> JX4.94 B19 PS_MIO47_501_JX4 - -## the following are mio-to-pl loopback - -## JX4.97 E26 PS_MIO00_500_JX4 <==> JX1.76 K3 IO_L11N_T1_SRCC_33 -## JX4.100 B20 PS_MIO51_501_JX4 <==> JX4.67 A9 IO_L17P_T2_34 -## JX4.85 C24 PS_MIO15_500_JX4 <==> JX4.37 E5 IO_L7N_T1_34 -## JX4.87 A25 PS_MIO10_500_JX4 <==> JX4.42 E6 IO_L10P_T1_34 - -set_property -dict {PACKAGE_PIN K3 IOSTANDARD LVCMOS18} [get_ports gp_in_mio[0]] ; ## IO_L11N_T1_SRCC_33 -set_property -dict {PACKAGE_PIN A9 IOSTANDARD LVCMOS18} [get_ports gp_in_mio[1]] ; ## IO_L17P_T2_34 -set_property -dict {PACKAGE_PIN E5 IOSTANDARD LVCMOS18} [get_ports gp_in_mio[2]] ; ## IO_L7N_T1_34 -set_property -dict {PACKAGE_PIN E6 IOSTANDARD LVCMOS18} [get_ports gp_in_mio[3]] ; ## IO_L10P_T1_34 - diff --git a/projects/pzsdr/ccbrk/system_project.tcl b/projects/pzsdr/ccbrk/system_project.tcl deleted file mode 100644 index 3d182ce37..000000000 --- a/projects/pzsdr/ccbrk/system_project.tcl +++ /dev/null @@ -1,20 +0,0 @@ - - - -source ../../scripts/adi_env.tcl -source $ad_hdl_dir/projects/scripts/adi_project.tcl -source $ad_hdl_dir/projects/scripts/adi_board.tcl - -adi_project_create ccbrk_pzsdr -adi_project_files ccbrk_pzsdr [list \ - "system_top.v" \ - "system_constr.xdc"\ - "$ad_hdl_dir/library/common/ad_iobuf.v" \ - "$ad_hdl_dir/projects/common/pzsdr/pzsdr_system_constr.xdc" ] - -set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/pzsdr/pzsdr_system_constr.xdc] -set_property PROCESSING_ORDER EARLY [get_files system_constr.xdc] - -adi_project_run ccbrk_pzsdr - - diff --git a/projects/pzsdr/ccfmc/system_bd.tcl b/projects/pzsdr/ccfmc/system_bd.tcl deleted file mode 100644 index c71d9cd75..000000000 --- a/projects/pzsdr/ccfmc/system_bd.tcl +++ /dev/null @@ -1,4 +0,0 @@ - -source $ad_hdl_dir/projects/common/pzsdr/pzsdr_system_bd.tcl -source ../common/ccfmc_bd.tcl - diff --git a/projects/pzsdr/ccfmc/system_constr.xdc b/projects/pzsdr/ccfmc/system_constr.xdc deleted file mode 100644 index 114de9c10..000000000 --- a/projects/pzsdr/ccfmc/system_constr.xdc +++ /dev/null @@ -1,246 +0,0 @@ - -# rf-board - -set_property -dict {PACKAGE_PIN K10 IOSTANDARD LVCMOS18} [get_ports gpio_rfpwr_enable] ; ## IO_25_VRP_34 -set_property -dict {PACKAGE_PIN AA20 IOSTANDARD LVCMOS25} [get_ports gpio_rf0] ; ## IO_L20_13_JX2_P -set_property -dict {PACKAGE_PIN AB20 IOSTANDARD LVCMOS25} [get_ports gpio_rf1] ; ## IO_L20_13_JX2_N -set_property -dict {PACKAGE_PIN AA14 IOSTANDARD LVCMOS25} [get_ports gpio_rf2] ; ## IO_L22_12_JX2_N -set_property -dict {PACKAGE_PIN J9 IOSTANDARD LVCMOS18} [get_ports gpio_rf3] ; ## IO_L05_34_JX4_N - -# ethernet-1 - -set_property -dict {PACKAGE_PIN B10 IOSTANDARD LVCMOS18} [get_ports eth1_mdc] ; ## IO_L16P_T2_34 -set_property -dict {PACKAGE_PIN A10 IOSTANDARD LVCMOS18} [get_ports eth1_mdio] ; ## IO_L16N_T2_34 -set_property -dict {PACKAGE_PIN G7 IOSTANDARD LVCMOS18} [get_ports eth1_rgmii_rxclk] ; ## IO_L12P_T1_MRCC_34 -set_property -dict {PACKAGE_PIN F7 IOSTANDARD LVCMOS18} [get_ports eth1_rgmii_rxctl] ; ## IO_L12N_T1_MRCC_34 -set_property -dict {PACKAGE_PIN E6 IOSTANDARD LVCMOS18} [get_ports eth1_rgmii_rxdata[0]] ; ## IO_L10P_T1_34 -set_property -dict {PACKAGE_PIN D5 IOSTANDARD LVCMOS18} [get_ports eth1_rgmii_rxdata[1]] ; ## IO_L10N_T1_34 -set_property -dict {PACKAGE_PIN F8 IOSTANDARD LVCMOS18} [get_ports eth1_rgmii_rxdata[2]] ; ## IO_L11P_T1_SRCC_34 -set_property -dict {PACKAGE_PIN E7 IOSTANDARD LVCMOS18} [get_ports eth1_rgmii_rxdata[3]] ; ## IO_L11N_T1_SRCC_34 -set_property -dict {PACKAGE_PIN C8 IOSTANDARD LVCMOS18} [get_ports eth1_rgmii_txclk] ; ## IO_L13P_T2_MRCC_34 -set_property -dict {PACKAGE_PIN C7 IOSTANDARD LVCMOS18} [get_ports eth1_rgmii_txctl] ; ## IO_L13N_T2_MRCC_34 -set_property -dict {PACKAGE_PIN D6 IOSTANDARD LVCMOS18} [get_ports eth1_rgmii_txdata[0]] ; ## IO_L14P_T2_SRCC_34 -set_property -dict {PACKAGE_PIN C6 IOSTANDARD LVCMOS18} [get_ports eth1_rgmii_txdata[1]] ; ## IO_L14N_T2_SRCC_34 -set_property -dict {PACKAGE_PIN C9 IOSTANDARD LVCMOS18} [get_ports eth1_rgmii_txdata[2]] ; ## IO_L15P_T2_DQS_34 -set_property -dict {PACKAGE_PIN B9 IOSTANDARD LVCMOS18} [get_ports eth1_rgmii_txdata[3]] ; ## IO_L15N_T2_DQS_34 - -# hdmi - -set_property -dict {PACKAGE_PIN L3 IOSTANDARD LVCMOS18} [get_ports hdmi_out_clk] ; ## IO_L11P_T1_SRCC_33 -set_property -dict {PACKAGE_PIN D4 IOSTANDARD LVCMOS18 IOB TRUE} [get_ports hdmi_vsync] ; ## IO_L2P_T0_33 -set_property -dict {PACKAGE_PIN D3 IOSTANDARD LVCMOS18 IOB TRUE} [get_ports hdmi_hsync] ; ## IO_L2N_T0_33 -set_property -dict {PACKAGE_PIN K3 IOSTANDARD LVCMOS18 IOB TRUE} [get_ports hdmi_data_e] ; ## IO_L11N_T1_SRCC_33 -set_property -dict {PACKAGE_PIN G2 IOSTANDARD LVCMOS18 IOB TRUE} [get_ports hdmi_data[0]] ; ## IO_L3P_T0_DQS_33 -set_property -dict {PACKAGE_PIN F2 IOSTANDARD LVCMOS18 IOB TRUE} [get_ports hdmi_data[1]] ; ## IO_L3N_T0_DQS_33 -set_property -dict {PACKAGE_PIN D1 IOSTANDARD LVCMOS18 IOB TRUE} [get_ports hdmi_data[2]] ; ## IO_L4P_T0_33 -set_property -dict {PACKAGE_PIN C1 IOSTANDARD LVCMOS18 IOB TRUE} [get_ports hdmi_data[3]] ; ## IO_L4N_T0_33 -set_property -dict {PACKAGE_PIN E2 IOSTANDARD LVCMOS18 IOB TRUE} [get_ports hdmi_data[4]] ; ## IO_L5P_T0_33 -set_property -dict {PACKAGE_PIN E1 IOSTANDARD LVCMOS18 IOB TRUE} [get_ports hdmi_data[5]] ; ## IO_L5N_T0_33 -set_property -dict {PACKAGE_PIN F3 IOSTANDARD LVCMOS18 IOB TRUE} [get_ports hdmi_data[6]] ; ## IO_L6P_T0_33 -set_property -dict {PACKAGE_PIN E3 IOSTANDARD LVCMOS18 IOB TRUE} [get_ports hdmi_data[7]] ; ## IO_L6N_T0_VREF_33 -set_property -dict {PACKAGE_PIN J1 IOSTANDARD LVCMOS18 IOB TRUE} [get_ports hdmi_data[8]] ; ## IO_L7P_T1_33 -set_property -dict {PACKAGE_PIN H1 IOSTANDARD LVCMOS18 IOB TRUE} [get_ports hdmi_data[9]] ; ## IO_L7N_T1_33 -set_property -dict {PACKAGE_PIN H4 IOSTANDARD LVCMOS18 IOB TRUE} [get_ports hdmi_data[10]] ; ## IO_L8P_T1_33 -set_property -dict {PACKAGE_PIN H3 IOSTANDARD LVCMOS18 IOB TRUE} [get_ports hdmi_data[11]] ; ## IO_L8N_T1_33 -set_property -dict {PACKAGE_PIN K2 IOSTANDARD LVCMOS18 IOB TRUE} [get_ports hdmi_data[12]] ; ## IO_L9P_T1_DQS_33 -set_property -dict {PACKAGE_PIN K1 IOSTANDARD LVCMOS18 IOB TRUE} [get_ports hdmi_data[13]] ; ## IO_L9N_T1_DQS_33 -set_property -dict {PACKAGE_PIN H2 IOSTANDARD LVCMOS18 IOB TRUE} [get_ports hdmi_data[14]] ; ## IO_L10P_T1_33 -set_property -dict {PACKAGE_PIN G1 IOSTANDARD LVCMOS18 IOB TRUE} [get_ports hdmi_data[15]] ; ## IO_L10N_T1_33 -set_property -dict {PACKAGE_PIN L9 IOSTANDARD LVCMOS18} [get_ports hdmi_pd] ; ## IO_0_VRN_33 -set_property -dict {PACKAGE_PIN N8 IOSTANDARD LVCMOS18} [get_ports hdmi_intn] ; ## IO_25_VRP_33 - -# hdmi-spdif - -set_property -dict {PACKAGE_PIN G4 IOSTANDARD LVCMOS18} [get_ports spdif] ; ## IO_L1P_T0_33 -set_property -dict {PACKAGE_PIN F4 IOSTANDARD LVCMOS18} [get_ports spdif_in] ; ## IO_L1N_T0_33 - -# audio - -set_property -dict {PACKAGE_PIN J8 IOSTANDARD LVCMOS18} [get_ports i2s_mclk] ; ## IO_L6P_T0_34 -set_property -dict {PACKAGE_PIN H8 IOSTANDARD LVCMOS18} [get_ports i2s_bclk] ; ## IO_L6N_T0_VREF_34 -set_property -dict {PACKAGE_PIN F5 IOSTANDARD LVCMOS18} [get_ports i2s_lrclk] ; ## IO_L7P_T1_34 -set_property -dict {PACKAGE_PIN E5 IOSTANDARD LVCMOS18} [get_ports i2s_sdata_out] ; ## IO_L7N_T1_34 -set_property -dict {PACKAGE_PIN D9 IOSTANDARD LVCMOS18} [get_ports i2s_sdata_in] ; ## IO_L8P_T1_34 - -# ad9517 - -set_property -dict {PACKAGE_PIN B4 IOSTANDARD LVCMOS18} [get_ports ad9517_csn] ; ## IO_L20N_T3_34 -set_property -dict {PACKAGE_PIN C4 IOSTANDARD LVCMOS18} [get_ports ad9517_clk] ; ## IO_L19P_T3_34 -set_property -dict {PACKAGE_PIN C3 IOSTANDARD LVCMOS18} [get_ports ad9517_mosi] ; ## IO_L19N_T3_VREF_34 -set_property -dict {PACKAGE_PIN B5 IOSTANDARD LVCMOS18} [get_ports ad9517_miso] ; ## IO_L20P_T3_34 -set_property -dict {PACKAGE_PIN B6 IOSTANDARD LVCMOS18} [get_ports ad9517_pdn] ; ## IO_L21P_T3_DQS_34 -set_property -dict {PACKAGE_PIN A5 IOSTANDARD LVCMOS18} [get_ports ad9517_ref_sel] ; ## IO_L21N_T3_DQS_34 -set_property -dict {PACKAGE_PIN A4 IOSTANDARD LVCMOS18} [get_ports ad9517_ld] ; ## IO_L22P_T3_34 -set_property -dict {PACKAGE_PIN A3 IOSTANDARD LVCMOS18} [get_ports ad9517_status] ; ## IO_L22N_T3_34 - -# clocks - -create_clock -period 8.000 -name eth1_rgmii_rxclk [get_ports eth1_rgmii_rxclk] - -# bad ip- we have to do this - -set_property IDELAY_VALUE 16 \ - [get_cells -hier -filter {name =~ *delay_rgmii_rxd*}] \ - [get_cells -hier -filter {name =~ *delay_rgmii_rx_ctl}] - -set_property IODELAY_GROUP gmii2rgmii_iodelay_group\ - [get_cells -hier -filter {name =~ *idelayctrl}] \ - [get_cells -hier -filter {name =~ *delay_rgmii_rxd*}] \ - [get_cells -hier -filter {name =~ *delay_rgmii_rx_ctl}] - - -# unused io (gpio/gt) - -set_property -dict {PACKAGE_PIN AC14 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports clk_0_p] ; ## IO_L13P_T2_MRCC_12 (fmc_clk0_p) -set_property -dict {PACKAGE_PIN AD14 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports clk_0_n] ; ## IO_L13N_T2_MRCC_12 (fmc_clk0_n) -set_property -dict {PACKAGE_PIN AD20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports clk_1_p] ; ## IO_L13P_T2_MRCC_13 (fmc_clk1_p) -set_property -dict {PACKAGE_PIN AD21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports clk_1_n] ; ## IO_L13N_T2_MRCC_13 (fmc_clk1_n) - -set_property -dict {PACKAGE_PIN W6} [get_ports gt_ref_clk_0_p] ; ## MGTREFCLK0P_111 (fmc_gt_ref_clk_p) -set_property -dict {PACKAGE_PIN W5} [get_ports gt_ref_clk_0_n] ; ## MGTREFCLK0N_111 (fmc_gt_ref_clk_n) -set_property -dict {PACKAGE_PIN AF8} [get_ports gt_tx_0_p] ; ## MGTXTXP0_111 (fmc_gt_tx_p) -set_property -dict {PACKAGE_PIN AF7} [get_ports gt_tx_0_n] ; ## MGTXTXN0_111 (fmc_gt_tx_n) -set_property -dict {PACKAGE_PIN AD8} [get_ports gt_rx_0_p] ; ## MGTXRXP0_111 (fmc_gt_rx_p) -set_property -dict {PACKAGE_PIN AD7} [get_ports gt_rx_0_n] ; ## MGTXRXN0_111 (fmc_gt_rx_n) - -set_property -dict {PACKAGE_PIN V18 IOSTANDARD LVCMOS25} [get_ports gp_in_0] ; ## IO_25_13 (fmc_prstn) - -set_property -dict {PACKAGE_PIN AC13 IOSTANDARD LVCMOS25} [get_ports gp_out[0]] ; ## IO_L12P_T1_MRCC_12 (fmc_la_p[ 0]) -set_property -dict {PACKAGE_PIN AD13 IOSTANDARD LVCMOS25} [get_ports gp_out[1]] ; ## IO_L12N_T1_MRCC_12 (fmc_la_n[ 0]) -set_property -dict {PACKAGE_PIN AC12 IOSTANDARD LVCMOS25} [get_ports gp_out[2]] ; ## IO_L11P_T1_SRCC_12 (fmc_la_p[ 1]) -set_property -dict {PACKAGE_PIN AD11 IOSTANDARD LVCMOS25} [get_ports gp_out[3]] ; ## IO_L11N_T1_SRCC_12 (fmc_la_n[ 1]) -set_property -dict {PACKAGE_PIN Y12 IOSTANDARD LVCMOS25} [get_ports gp_out[4]] ; ## IO_L1P_T0_12 (fmc_la_p[ 2]) -set_property -dict {PACKAGE_PIN Y11 IOSTANDARD LVCMOS25} [get_ports gp_out[5]] ; ## IO_L1N_T0_12 (fmc_la_n[ 2]) -set_property -dict {PACKAGE_PIN AB12 IOSTANDARD LVCMOS25} [get_ports gp_out[6]] ; ## IO_L2P_T0_12 (fmc_la_p[ 3]) -set_property -dict {PACKAGE_PIN AC11 IOSTANDARD LVCMOS25} [get_ports gp_out[7]] ; ## IO_L2N_T0_12 (fmc_la_n[ 3]) -set_property -dict {PACKAGE_PIN Y10 IOSTANDARD LVCMOS25} [get_ports gp_out[8]] ; ## IO_L3P_T0_DQS_12 (fmc_la_p[ 4]) -set_property -dict {PACKAGE_PIN AA10 IOSTANDARD LVCMOS25} [get_ports gp_out[9]] ; ## IO_L3N_T0_DQS_12 (fmc_la_n[ 4]) -set_property -dict {PACKAGE_PIN AB11 IOSTANDARD LVCMOS25} [get_ports gp_out[10]] ; ## IO_L4P_T0_12 (fmc_la_p[ 5]) -set_property -dict {PACKAGE_PIN AB10 IOSTANDARD LVCMOS25} [get_ports gp_out[11]] ; ## IO_L4N_T0_12 (fmc_la_n[ 5]) -set_property -dict {PACKAGE_PIN W13 IOSTANDARD LVCMOS25} [get_ports gp_out[12]] ; ## IO_L5P_T0_12 (fmc_la_p[ 6]) -set_property -dict {PACKAGE_PIN Y13 IOSTANDARD LVCMOS25} [get_ports gp_out[13]] ; ## IO_L5N_T0_12 (fmc_la_n[ 6]) -set_property -dict {PACKAGE_PIN AA13 IOSTANDARD LVCMOS25} [get_ports gp_out[14]] ; ## IO_L6P_T0_12 (fmc_la_p[ 7]) -set_property -dict {PACKAGE_PIN AA12 IOSTANDARD LVCMOS25} [get_ports gp_out[15]] ; ## IO_L6N_T0_VREF_12 (fmc_la_n[ 7]) -set_property -dict {PACKAGE_PIN AE10 IOSTANDARD LVCMOS25} [get_ports gp_out[16]] ; ## IO_L7P_T1_12 (fmc_la_p[ 8]) -set_property -dict {PACKAGE_PIN AD10 IOSTANDARD LVCMOS25} [get_ports gp_out[17]] ; ## IO_L7N_T1_12 (fmc_la_n[ 8]) -set_property -dict {PACKAGE_PIN AE12 IOSTANDARD LVCMOS25} [get_ports gp_out[18]] ; ## IO_L8P_T1_12 (fmc_la_p[ 9]) -set_property -dict {PACKAGE_PIN AF12 IOSTANDARD LVCMOS25} [get_ports gp_out[19]] ; ## IO_L8N_T1_12 (fmc_la_n[ 9]) -set_property -dict {PACKAGE_PIN AE11 IOSTANDARD LVCMOS25} [get_ports gp_out[20]] ; ## IO_L9P_T1_DQS_12 (fmc_la_p[10]) -set_property -dict {PACKAGE_PIN AF10 IOSTANDARD LVCMOS25} [get_ports gp_out[21]] ; ## IO_L9N_T1_DQS_12 (fmc_la_n[10]) -set_property -dict {PACKAGE_PIN AE13 IOSTANDARD LVCMOS25} [get_ports gp_out[22]] ; ## IO_L10P_T1_12 (fmc_la_p[11]) -set_property -dict {PACKAGE_PIN AF13 IOSTANDARD LVCMOS25} [get_ports gp_out[23]] ; ## IO_L10N_T1_12 (fmc_la_n[11]) -set_property -dict {PACKAGE_PIN AB15 IOSTANDARD LVCMOS25} [get_ports gp_out[24]] ; ## IO_L14P_T2_SRCC_12 (fmc_la_p[12]) -set_property -dict {PACKAGE_PIN AB14 IOSTANDARD LVCMOS25} [get_ports gp_out[25]] ; ## IO_L14N_T2_SRCC_12 (fmc_la_n[12]) -set_property -dict {PACKAGE_PIN AD16 IOSTANDARD LVCMOS25} [get_ports gp_out[26]] ; ## IO_L15P_T2_DQS_12 (fmc_la_p[13]) -set_property -dict {PACKAGE_PIN AD15 IOSTANDARD LVCMOS25} [get_ports gp_out[27]] ; ## IO_L15N_T2_DQS_12 (fmc_la_n[13]) -set_property -dict {PACKAGE_PIN AF15 IOSTANDARD LVCMOS25} [get_ports gp_out[28]] ; ## IO_L16P_T2_12 (fmc_la_p[14]) -set_property -dict {PACKAGE_PIN AF14 IOSTANDARD LVCMOS25} [get_ports gp_out[29]] ; ## IO_L16N_T2_12 (fmc_la_n[14]) -set_property -dict {PACKAGE_PIN AE16 IOSTANDARD LVCMOS25} [get_ports gp_out[30]] ; ## IO_L17P_T2_12 (fmc_la_p[15]) -set_property -dict {PACKAGE_PIN AE15 IOSTANDARD LVCMOS25} [get_ports gp_out[31]] ; ## IO_L17N_T2_12 (fmc_la_n[15]) -set_property -dict {PACKAGE_PIN AE17 IOSTANDARD LVCMOS25} [get_ports gp_out[32]] ; ## IO_L18P_T2_12 (fmc_la_p[16]) -set_property -dict {PACKAGE_PIN AF17 IOSTANDARD LVCMOS25} [get_ports gp_out[33]] ; ## IO_L18N_T2_12 (fmc_la_n[16]) - -set_property -dict {PACKAGE_PIN AC23 IOSTANDARD LVCMOS25} [get_ports gp_in[0]] ; ## IO_L12P_T1_MRCC_13 (fmc_la_p[17]) -set_property -dict {PACKAGE_PIN AC24 IOSTANDARD LVCMOS25} [get_ports gp_in[1]] ; ## IO_L12N_T1_MRCC_13 (fmc_la_n[17]) -set_property -dict {PACKAGE_PIN AD23 IOSTANDARD LVCMOS25} [get_ports gp_in[2]] ; ## IO_L11P_T1_SRCC_13 (fmc_la_p[18]) -set_property -dict {PACKAGE_PIN AD24 IOSTANDARD LVCMOS25} [get_ports gp_in[3]] ; ## IO_L11N_T1_SRCC_13 (fmc_la_n[18]) -set_property -dict {PACKAGE_PIN AA25 IOSTANDARD LVCMOS25} [get_ports gp_in[4]] ; ## IO_L1P_T0_13 (fmc_la_p[19]) -set_property -dict {PACKAGE_PIN AB25 IOSTANDARD LVCMOS25} [get_ports gp_in[5]] ; ## IO_L1N_T0_13 (fmc_la_n[19]) -set_property -dict {PACKAGE_PIN AB26 IOSTANDARD LVCMOS25} [get_ports gp_in[6]] ; ## IO_L2P_T0_13 (fmc_la_p[20]) -set_property -dict {PACKAGE_PIN AC26 IOSTANDARD LVCMOS25} [get_ports gp_in[7]] ; ## IO_L2N_T0_13 (fmc_la_n[20]) -set_property -dict {PACKAGE_PIN AE25 IOSTANDARD LVCMOS25} [get_ports gp_in[8]] ; ## IO_L3P_T0_DQS_13 (fmc_la_p[21]) -set_property -dict {PACKAGE_PIN AE26 IOSTANDARD LVCMOS25} [get_ports gp_in[9]] ; ## IO_L3N_T0_DQS_13 (fmc_la_n[21]) -set_property -dict {PACKAGE_PIN AD25 IOSTANDARD LVCMOS25} [get_ports gp_in[10]] ; ## IO_L4P_T0_13 (fmc_la_p[22]) -set_property -dict {PACKAGE_PIN AD26 IOSTANDARD LVCMOS25} [get_ports gp_in[11]] ; ## IO_L4N_T0_13 (fmc_la_n[22]) -set_property -dict {PACKAGE_PIN AA24 IOSTANDARD LVCMOS25} [get_ports gp_in[12]] ; ## IO_L6P_T0_13 (fmc_la_p[23]) -set_property -dict {PACKAGE_PIN AB24 IOSTANDARD LVCMOS25} [get_ports gp_in[13]] ; ## IO_L6N_T0_VREF_13 (fmc_la_n[23]) -set_property -dict {PACKAGE_PIN AE22 IOSTANDARD LVCMOS25} [get_ports gp_in[14]] ; ## IO_L7P_T1_13 (fmc_la_p[24]) -set_property -dict {PACKAGE_PIN AF22 IOSTANDARD LVCMOS25} [get_ports gp_in[15]] ; ## IO_L7N_T1_13 (fmc_la_n[24]) -set_property -dict {PACKAGE_PIN AE23 IOSTANDARD LVCMOS25} [get_ports gp_in[16]] ; ## IO_L8P_T1_13 (fmc_la_p[25]) -set_property -dict {PACKAGE_PIN AF23 IOSTANDARD LVCMOS25} [get_ports gp_in[17]] ; ## IO_L8N_T1_13 (fmc_la_n[25]) -set_property -dict {PACKAGE_PIN AB21 IOSTANDARD LVCMOS25} [get_ports gp_in[18]] ; ## IO_L9P_T1_DQS_13 (fmc_la_p[26]) -set_property -dict {PACKAGE_PIN AB22 IOSTANDARD LVCMOS25} [get_ports gp_in[19]] ; ## IO_L9N_T1_DQS_13 (fmc_la_n[26]) -set_property -dict {PACKAGE_PIN AA22 IOSTANDARD LVCMOS25} [get_ports gp_in[20]] ; ## IO_L10P_T1_13 (fmc_la_p[27]) -set_property -dict {PACKAGE_PIN AA23 IOSTANDARD LVCMOS25} [get_ports gp_in[21]] ; ## IO_L10N_T1_13 (fmc_la_n[27]) -set_property -dict {PACKAGE_PIN AC21 IOSTANDARD LVCMOS25} [get_ports gp_in[22]] ; ## IO_L14P_T2_SRCC_13 (fmc_la_p[28]) -set_property -dict {PACKAGE_PIN AC22 IOSTANDARD LVCMOS25} [get_ports gp_in[23]] ; ## IO_L14N_T2_SRCC_13 (fmc_la_n[28]) -set_property -dict {PACKAGE_PIN AF19 IOSTANDARD LVCMOS25} [get_ports gp_in[24]] ; ## IO_L15P_T2_DQS_13 (fmc_la_p[29]) -set_property -dict {PACKAGE_PIN AF20 IOSTANDARD LVCMOS25} [get_ports gp_in[25]] ; ## IO_L15N_T2_DQS_13 (fmc_la_n[29]) -set_property -dict {PACKAGE_PIN AE20 IOSTANDARD LVCMOS25} [get_ports gp_in[26]] ; ## IO_L16P_T2_13 (fmc_la_p[30]) -set_property -dict {PACKAGE_PIN AE21 IOSTANDARD LVCMOS25} [get_ports gp_in[27]] ; ## IO_L16N_T2_13 (fmc_la_n[30]) -set_property -dict {PACKAGE_PIN AD18 IOSTANDARD LVCMOS25} [get_ports gp_in[28]] ; ## IO_L17P_T2_13 (fmc_la_p[31]) -set_property -dict {PACKAGE_PIN AD19 IOSTANDARD LVCMOS25} [get_ports gp_in[29]] ; ## IO_L17N_T2_13 (fmc_la_n[31]) -set_property -dict {PACKAGE_PIN AE18 IOSTANDARD LVCMOS25} [get_ports gp_in[30]] ; ## IO_L18P_T2_13 (fmc_la_p[32]) -set_property -dict {PACKAGE_PIN AF18 IOSTANDARD LVCMOS25} [get_ports gp_in[31]] ; ## IO_L18N_T2_13 (fmc_la_n[32]) -set_property -dict {PACKAGE_PIN W20 IOSTANDARD LVCMOS25} [get_ports gp_in[32]] ; ## IO_L19P_T3_13 (fmc_la_p[33]) -set_property -dict {PACKAGE_PIN Y20 IOSTANDARD LVCMOS25} [get_ports gp_in[33]] ; ## IO_L19N_T3_VREF_13 (fmc_la_n[33]) - -set_property -dict {PACKAGE_PIN AC18 IOSTANDARD LVCMOS25} [get_ports gp_out[34]] ; ## IO_L21P_T3_DQS_13 (pmod0[0]) -set_property -dict {PACKAGE_PIN AC19 IOSTANDARD LVCMOS25} [get_ports gp_inout_0] ; ## IO_L21N_T3_DQS_13 (pmod0[1]) -set_property -dict {PACKAGE_PIN AA19 IOSTANDARD LVCMOS25} [get_ports gp_out[35]] ; ## IO_L22P_T3_13 (pmod0[2]) -set_property -dict {PACKAGE_PIN AB19 IOSTANDARD LVCMOS25} [get_ports gp_out[36]] ; ## IO_L22N_T3_13 (pmod0[3]) -set_property -dict {PACKAGE_PIN W18 IOSTANDARD LVCMOS25} [get_ports gp_in[34]] ; ## IO_L23P_T3_13 (pmod0[4]) -set_property -dict {PACKAGE_PIN W19 IOSTANDARD LVCMOS25} [get_ports gp_inout_1] ; ## IO_L23N_T3_13 (pmod0[5]) + (TDD_SYNC) -set_property -dict {PACKAGE_PIN Y18 IOSTANDARD LVCMOS25} [get_ports gp_in[35]] ; ## IO_L24P_T3_13 (pmod0[6]) -set_property -dict {PACKAGE_PIN AA18 IOSTANDARD LVCMOS25} [get_ports gp_in[36]] ; ## IO_L24N_T3_13 (pmod0[7]) - -set_property -dict {PACKAGE_PIN AA6} [get_ports gt_ref_clk_1_p] ; ## MGTREFCLK1P_111 (ad9517_gt_ref_clk_p) -set_property -dict {PACKAGE_PIN AA5} [get_ports gt_ref_clk_1_n] ; ## MGTREFCLK1N_111 (ad9517_gt_ref_clk_n) -set_property -dict {PACKAGE_PIN AF4} [get_ports gt_tx_1_p] ; ## MGTXTXP1_111 (sfp_gt_tx_p) -set_property -dict {PACKAGE_PIN AF3} [get_ports gt_tx_1_n] ; ## MGTXTXN1_111 (sfp_gt_tx_n) -set_property -dict {PACKAGE_PIN AE6} [get_ports gt_rx_1_p] ; ## MGTXRXP1_111 (sfp_gt_rx_p) -set_property -dict {PACKAGE_PIN AE5} [get_ports gt_rx_1_n] ; ## MGTXRXN1_111 (sfp_gt_rx_n) - -set_property -dict {PACKAGE_PIN M6 IOSTANDARD LVCMOS18} [get_ports gp_out[37]] ; ## IO_L13P_T2_MRCC_33 (cam_gpio[ 0]) -set_property -dict {PACKAGE_PIN M5 IOSTANDARD LVCMOS18} [get_ports gp_out[38]] ; ## IO_L13N_T2_MRCC_33 (cam_gpio[ 1]) -set_property -dict {PACKAGE_PIN L5 IOSTANDARD LVCMOS18} [get_ports gp_out[39]] ; ## IO_L14P_T2_SRCC_33 (cam_gpio[ 2]) -set_property -dict {PACKAGE_PIN L4 IOSTANDARD LVCMOS18} [get_ports gp_out[40]] ; ## IO_L14N_T2_SRCC_33 (cam_gpio[ 3]) -set_property -dict {PACKAGE_PIN N3 IOSTANDARD LVCMOS18} [get_ports gp_out[41]] ; ## IO_L15P_T2_DQS_33 (cam_gpio[ 4]) -set_property -dict {PACKAGE_PIN N2 IOSTANDARD LVCMOS18} [get_ports gp_out[42]] ; ## IO_L15N_T2_DQS_33 (cam_gpio[ 5]) -set_property -dict {PACKAGE_PIN M2 IOSTANDARD LVCMOS18} [get_ports gp_out[43]] ; ## IO_L16P_T2_33 (cam_gpio[ 6]) -set_property -dict {PACKAGE_PIN L2 IOSTANDARD LVCMOS18} [get_ports gp_out[44]] ; ## IO_L16N_T2_33 (cam_gpio[ 7]) -set_property -dict {PACKAGE_PIN N4 IOSTANDARD LVCMOS18} [get_ports gp_out[45]] ; ## IO_L17P_T2_33 (cam_gpio[ 8]) -set_property -dict {PACKAGE_PIN M4 IOSTANDARD LVCMOS18} [get_ports gp_out[46]] ; ## IO_L17N_T2_33 (cam_gpio[ 9]) -set_property -dict {PACKAGE_PIN N1 IOSTANDARD LVCMOS18} [get_ports gp_out[47]] ; ## IO_L18P_T2_33 (cam_gpio[10]) -set_property -dict {PACKAGE_PIN M1 IOSTANDARD LVCMOS18} [get_ports gp_out[48]] ; ## IO_L18N_T2_33 (cam_gpio[11]) -set_property -dict {PACKAGE_PIN M7 IOSTANDARD LVCMOS18} [get_ports gp_out[49]] ; ## IO_L19P_T3_33 (cam_gpio[12]) -set_property -dict {PACKAGE_PIN L7 IOSTANDARD LVCMOS18} [get_ports gp_out[50]] ; ## IO_L19N_T3_VREF_33 (cam_gpio[13]) -set_property -dict {PACKAGE_PIN K5 IOSTANDARD LVCMOS18} [get_ports gp_out[51]] ; ## IO_L20P_T3_33 (cam_gpio[14]) -set_property -dict {PACKAGE_PIN J5 IOSTANDARD LVCMOS18} [get_ports gp_out[52]] ; ## IO_L20N_T3_33 (cam_gpio[15]) -set_property -dict {PACKAGE_PIN M8 IOSTANDARD LVCMOS18} [get_ports gp_out[53]] ; ## IO_L21P_T3_DQS_33 (cam_gpio[16]) -set_property -dict {PACKAGE_PIN L8 IOSTANDARD LVCMOS18} [get_ports gp_in[37]] ; ## IO_L21N_T3_DQS_33 (cam_gpio[17]) -set_property -dict {PACKAGE_PIN K6 IOSTANDARD LVCMOS18} [get_ports gp_in[38]] ; ## IO_L22P_T3_33 (cam_gpio[18]) -set_property -dict {PACKAGE_PIN J6 IOSTANDARD LVCMOS18} [get_ports gp_in[39]] ; ## IO_L22N_T3_33 (cam_gpio[19]) -set_property -dict {PACKAGE_PIN N7 IOSTANDARD LVCMOS18} [get_ports gp_in[40]] ; ## IO_L23P_T3_33 (cam_gpio[20]) -set_property -dict {PACKAGE_PIN N6 IOSTANDARD LVCMOS18} [get_ports gp_in[41]] ; ## IO_L23N_T3_33 (cam_gpio[21]) -set_property -dict {PACKAGE_PIN K8 IOSTANDARD LVCMOS18} [get_ports gp_in[42]] ; ## IO_L24P_T3_33 (cam_gpio[22]) -set_property -dict {PACKAGE_PIN K7 IOSTANDARD LVCMOS18} [get_ports gp_in[43]] ; ## IO_L24N_T3_33 (cam_gpio[23]) -set_property -dict {PACKAGE_PIN J11 IOSTANDARD LVCMOS18} [get_ports gp_in[44]] ; ## IO_L1P_T0_34 (cam_gpio[24]) -set_property -dict {PACKAGE_PIN H11 IOSTANDARD LVCMOS18} [get_ports gp_in[45]] ; ## IO_L1N_T0_34 (cam_gpio[25]) -set_property -dict {PACKAGE_PIN G6 IOSTANDARD LVCMOS18} [get_ports gp_in[46]] ; ## IO_L2P_T0_34 (cam_gpio[26]) -set_property -dict {PACKAGE_PIN G5 IOSTANDARD LVCMOS18} [get_ports gp_in[47]] ; ## IO_L2N_T0_34 (cam_gpio[27]) -set_property -dict {PACKAGE_PIN H9 IOSTANDARD LVCMOS18} [get_ports gp_in[48]] ; ## IO_L3P_T0_DQS_PUDC_B_34 (cam_gpio[28]) -set_property -dict {PACKAGE_PIN G9 IOSTANDARD LVCMOS18} [get_ports gp_in[49]] ; ## IO_L3N_T0_DQS_34 (cam_gpio[29]) -set_property -dict {PACKAGE_PIN H7 IOSTANDARD LVCMOS18} [get_ports gp_in[50]] ; ## IO_L4P_T0_34 (cam_gpio[30]) -set_property -dict {PACKAGE_PIN H6 IOSTANDARD LVCMOS18} [get_ports gp_in[51]] ; ## IO_L4N_T0_34 (cam_gpio[31]) -set_property -dict {PACKAGE_PIN J10 IOSTANDARD LVCMOS18} [get_ports gp_in[52]] ; ## IO_L5P_T0_34 (cam_gpio[32]) -set_property -dict {PACKAGE_PIN J4 IOSTANDARD LVCMOS18} [get_ports gp_in[53]] ; ## IO_L12P_T1_MRCC_33 (cam_gpio[33]) - -set_property -dict {PACKAGE_PIN Y17 IOSTANDARD LVCMOS25} [get_ports gp_out[54]] ; ## IO_L19P_T3_12 (sfp_gpio[0]) -set_property -dict {PACKAGE_PIN AA17 IOSTANDARD LVCMOS25} [get_ports gp_out[55]] ; ## IO_L19N_T3_VREF_12 (sfp_gpio[1]) -set_property -dict {PACKAGE_PIN AB17 IOSTANDARD LVCMOS25} [get_ports gp_out[56]] ; ## IO_L20P_T3_12 (sfp_gpio[2]) -set_property -dict {PACKAGE_PIN AB16 IOSTANDARD LVCMOS25} [get_ports gp_out_0] ; ## IO_L20N_T3_12 (sfp_gpio[3]) -set_property -dict {PACKAGE_PIN AC17 IOSTANDARD LVCMOS25} [get_ports gp_in[54]] ; ## IO_L21P_T3_DQS_12 (sfp_gpio[4]) -set_property -dict {PACKAGE_PIN AC16 IOSTANDARD LVCMOS25} [get_ports gp_in[55]] ; ## IO_L21N_T3_DQS_12 (sfp_gpio[5]) -set_property -dict {PACKAGE_PIN AA15 IOSTANDARD LVCMOS25} [get_ports gp_in[56]] ; ## IO_L22P_T3_12 (sfp_gpio[6]) - -# clocks - -create_clock -name ref_clk_0 -period 4.00 [get_ports gt_ref_clk_0_p] -create_clock -name ref_clk_1 -period 4.00 [get_ports gt_ref_clk_1_p] -create_clock -name tx_div_clk_0 -period 8.00 [get_pins i_system_wrapper/system_i/axi_pzslb_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/TXOUTCLK] -create_clock -name rx_div_clk_0 -period 8.00 [get_pins i_system_wrapper/system_i/axi_pzslb_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK] -create_clock -name tx_div_clk_1 -period 8.00 [get_pins i_system_wrapper/system_i/axi_pzslb_gt/inst/g_lane_1[1].i_channel/i_gt/i_gtxe2_channel/TXOUTCLK] -create_clock -name rx_div_clk_1 -period 8.00 [get_pins i_system_wrapper/system_i/axi_pzslb_gt/inst/g_lane_1[1].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK] - - diff --git a/projects/pzsdr/ccpci/system_bd.tcl b/projects/pzsdr/ccpci/system_bd.tcl deleted file mode 100644 index c3d58daac..000000000 --- a/projects/pzsdr/ccpci/system_bd.tcl +++ /dev/null @@ -1,10 +0,0 @@ - -source $ad_hdl_dir/projects/common/pzsdr/pzsdr_system_bd.tcl -source ../common/ccpci_bd.tcl - -## temporary -## ila - -delete_bd_objs [get_bd_cells ila_adc] -delete_bd_objs [get_bd_nets axi_ad9361_tdd_dbg] [get_bd_cells ila_tdd] - diff --git a/projects/pzsdr/ccpci/system_constr.xdc b/projects/pzsdr/ccpci/system_constr.xdc deleted file mode 100644 index 0f21e007d..000000000 --- a/projects/pzsdr/ccpci/system_constr.xdc +++ /dev/null @@ -1,36 +0,0 @@ - -# constraints - -set_property -dict {PACKAGE_PIN AA6} [get_ports pcie_ref_clk_p] ; ## MGTREFCLK1P_111 -set_property -dict {PACKAGE_PIN AA5} [get_ports pcie_ref_clk_n] ; ## MGTREFCLK1N_111 -set_property -dict {PACKAGE_PIN AD8} [get_ports pcie_data_rx_p[0]] ; ## MGTXRXP0_111 -set_property -dict {PACKAGE_PIN AD7} [get_ports pcie_data_rx_n[0]] ; ## MGTXRXN0_111 -set_property -dict {PACKAGE_PIN AE6} [get_ports pcie_data_rx_p[1]] ; ## MGTXRXP1_111 -set_property -dict {PACKAGE_PIN AE5} [get_ports pcie_data_rx_n[1]] ; ## MGTXRXN1_111 -set_property -dict {PACKAGE_PIN AC6} [get_ports pcie_data_rx_p[2]] ; ## MGTXRXP2_111 -set_property -dict {PACKAGE_PIN AC5} [get_ports pcie_data_rx_n[2]] ; ## MGTXRXN2_111 -set_property -dict {PACKAGE_PIN AD4} [get_ports pcie_data_rx_p[3]] ; ## MGTXRXP3_111 -set_property -dict {PACKAGE_PIN AD3} [get_ports pcie_data_rx_n[3]] ; ## MGTXRXN3_111 -set_property -dict {PACKAGE_PIN AF8} [get_ports pcie_data_tx_p[0]] ; ## MGTXTXP0_111 -set_property -dict {PACKAGE_PIN AF7} [get_ports pcie_data_tx_n[0]] ; ## MGTXTXN0_111 -set_property -dict {PACKAGE_PIN AF4} [get_ports pcie_data_tx_p[1]] ; ## MGTXTXP1_111 -set_property -dict {PACKAGE_PIN AF3} [get_ports pcie_data_tx_n[1]] ; ## MGTXTXN1_111 -set_property -dict {PACKAGE_PIN AE2} [get_ports pcie_data_tx_p[2]] ; ## MGTXTXP2_111 -set_property -dict {PACKAGE_PIN AE1} [get_ports pcie_data_tx_n[2]] ; ## MGTXTXN2_111 -set_property -dict {PACKAGE_PIN AC2} [get_ports pcie_data_tx_p[3]] ; ## MGTXTXP3_111 -set_property -dict {PACKAGE_PIN AC1} [get_ports pcie_data_tx_n[3]] ; ## MGTXTXN3_111 -set_property -dict {PACKAGE_PIN W20 IOSTANDARD LVCMOS25} [get_ports pcie_rstn] ; ## IO_L19P_T3_13 -set_property -dict {PACKAGE_PIN Y20 IOSTANDARD LVCMOS25} [get_ports pcie_prsntn] ; ## IO_L19N_T3_VREF_13 -set_property -dict {PACKAGE_PIN AC18 IOSTANDARD LVCMOS25} [get_ports pcie_prsnt1n] ; ## IO_L21P_T3_DQS_13 -set_property -dict {PACKAGE_PIN AC19 IOSTANDARD LVCMOS25} [get_ports pcie_prsnt4n] ; ## IO_L21N_T3_DQS_13 -set_property -dict {PACKAGE_PIN AB20 IOSTANDARD LVCMOS25} [get_ports pcie_waken] ; ## IO_L20N_T3_13 - -set_property PULLUP true [get_ports pcie_rstn] -set_property LOC IBUFDS_GTE2_X0Y5 [get_cells i_ibufds_pcie_ref_clk] -create_clock -name pcie_ref_clock -period 10 [get_ports pcie_ref_clk_p] - -set_property LOC GTXE2_CHANNEL_X0Y8 [get_cells -hierarchical -filter {NAME =~ *comp_axi_enhanced_pcie/comp_enhanced_core_top_wrap/axi_pcie_enhanced_core_top_i/pcie_7x_v2_0_2_inst/pcie_top_with_gt_top.gt_ges.gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gtx_channel.gtxe2_channel_i}] -set_property LOC GTXE2_CHANNEL_X0Y9 [get_cells -hierarchical -filter {NAME =~ *comp_axi_enhanced_pcie/comp_enhanced_core_top_wrap/axi_pcie_enhanced_core_top_i/pcie_7x_v2_0_2_inst/pcie_top_with_gt_top.gt_ges.gt_top_i/pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/gtx_channel.gtxe2_channel_i}] -set_property LOC GTXE2_CHANNEL_X0Y10 [get_cells -hierarchical -filter {NAME =~ *comp_axi_enhanced_pcie/comp_enhanced_core_top_wrap/axi_pcie_enhanced_core_top_i/pcie_7x_v2_0_2_inst/pcie_top_with_gt_top.gt_ges.gt_top_i/pipe_wrapper_i/pipe_lane[2].gt_wrapper_i/gtx_channel.gtxe2_channel_i}] -set_property LOC GTXE2_CHANNEL_X0Y11 [get_cells -hierarchical -filter {NAME =~ *comp_axi_enhanced_pcie/comp_enhanced_core_top_wrap/axi_pcie_enhanced_core_top_i/pcie_7x_v2_0_2_inst/pcie_top_with_gt_top.gt_ges.gt_top_i/pipe_wrapper_i/pipe_lane[3].gt_wrapper_i/gtx_channel.gtxe2_channel_i}] - diff --git a/projects/pzsdr/ccpci/system_project.tcl b/projects/pzsdr/ccpci/system_project.tcl deleted file mode 100644 index e09c5a1d0..000000000 --- a/projects/pzsdr/ccpci/system_project.tcl +++ /dev/null @@ -1,20 +0,0 @@ - - - -source ../../scripts/adi_env.tcl -source $ad_hdl_dir/projects/scripts/adi_project.tcl -source $ad_hdl_dir/projects/scripts/adi_board.tcl - -adi_project_create ccpci_pzsdr -adi_project_files ccpci_pzsdr [list \ - "system_top.v" \ - "system_constr.xdc"\ - "$ad_hdl_dir/library/common/ad_iobuf.v" \ - "$ad_hdl_dir/projects/common/pzsdr/pzsdr_system_constr.xdc" ] - -set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/pzsdr/pzsdr_system_constr.xdc] -set_property PROCESSING_ORDER LATE [get_files system_constr.xdc] - -adi_project_run ccpci_pzsdr - - diff --git a/projects/pzsdr/common/ccbrk_bd.tcl b/projects/pzsdr/common/ccbrk_bd.tcl deleted file mode 100644 index a91b0dafe..000000000 --- a/projects/pzsdr/common/ccbrk_bd.tcl +++ /dev/null @@ -1,191 +0,0 @@ - -# lbfmc - -ad_connect sys_ps7/ENET1_GMII_RX_CLK GND -ad_connect sys_ps7/ENET1_GMII_TX_CLK GND - -# un-used io (gt) - -set axi_pzslb_gt [create_bd_cell -type ip -vlnv analog.com:user:axi_jesd_gt:1.0 axi_pzslb_gt] -set_property -dict [list CONFIG.NUM_OF_LANES {4}] $axi_pzslb_gt -set_property -dict [list CONFIG.QPLL1_ENABLE {0}] $axi_pzslb_gt -set_property -dict [list CONFIG.RX_NUM_OF_LANES {4}] $axi_pzslb_gt -set_property -dict [list CONFIG.TX_NUM_OF_LANES {4}] $axi_pzslb_gt -set_property -dict [list CONFIG.RX_CLKBUF_ENABLE_0 {1}] $axi_pzslb_gt -set_property -dict [list CONFIG.TX_CLKBUF_ENABLE_0 {1}] $axi_pzslb_gt -set_property -dict [list CONFIG.TX_DATA_SEL_0 {0}] $axi_pzslb_gt -set_property -dict [list CONFIG.CPLL_FBDIV_0 {2}] $axi_pzslb_gt -set_property -dict [list CONFIG.RX_OUT_DIV_0 {1}] $axi_pzslb_gt -set_property -dict [list CONFIG.TX_OUT_DIV_0 {1}] $axi_pzslb_gt -set_property -dict [list CONFIG.RX_CLK25_DIV_0 {10}] $axi_pzslb_gt -set_property -dict [list CONFIG.TX_CLK25_DIV_0 {10}] $axi_pzslb_gt -set_property -dict [list CONFIG.PMA_RSV_0 {0x00018480}] $axi_pzslb_gt -set_property -dict [list CONFIG.RX_CDR_CFG_0 {0x03000023ff20400020}] $axi_pzslb_gt -set_property -dict [list CONFIG.RX_CLKBUF_ENABLE_1 {1}] $axi_pzslb_gt -set_property -dict [list CONFIG.TX_CLKBUF_ENABLE_1 {1}] $axi_pzslb_gt -set_property -dict [list CONFIG.TX_DATA_SEL_1 {1}] $axi_pzslb_gt -set_property -dict [list CONFIG.CPLL_FBDIV_1 {2}] $axi_pzslb_gt -set_property -dict [list CONFIG.RX_OUT_DIV_1 {1}] $axi_pzslb_gt -set_property -dict [list CONFIG.TX_OUT_DIV_1 {1}] $axi_pzslb_gt -set_property -dict [list CONFIG.RX_CLK25_DIV_1 {10}] $axi_pzslb_gt -set_property -dict [list CONFIG.TX_CLK25_DIV_1 {10}] $axi_pzslb_gt -set_property -dict [list CONFIG.PMA_RSV_1 {0x00018480}] $axi_pzslb_gt -set_property -dict [list CONFIG.RX_CDR_CFG_1 {0x03000023ff20400020}] $axi_pzslb_gt -set_property -dict [list CONFIG.RX_CLKBUF_ENABLE_2 {1}] $axi_pzslb_gt -set_property -dict [list CONFIG.TX_CLKBUF_ENABLE_2 {1}] $axi_pzslb_gt -set_property -dict [list CONFIG.TX_DATA_SEL_2 {2}] $axi_pzslb_gt -set_property -dict [list CONFIG.CPLL_FBDIV_2 {2}] $axi_pzslb_gt -set_property -dict [list CONFIG.RX_OUT_DIV_2 {1}] $axi_pzslb_gt -set_property -dict [list CONFIG.TX_OUT_DIV_2 {1}] $axi_pzslb_gt -set_property -dict [list CONFIG.RX_CLK25_DIV_2 {10}] $axi_pzslb_gt -set_property -dict [list CONFIG.TX_CLK25_DIV_2 {10}] $axi_pzslb_gt -set_property -dict [list CONFIG.PMA_RSV_2 {0x00018480}] $axi_pzslb_gt -set_property -dict [list CONFIG.RX_CDR_CFG_2 {0x03000023ff20400020}] $axi_pzslb_gt -set_property -dict [list CONFIG.RX_CLKBUF_ENABLE_3 {1}] $axi_pzslb_gt -set_property -dict [list CONFIG.TX_CLKBUF_ENABLE_3 {1}] $axi_pzslb_gt -set_property -dict [list CONFIG.TX_DATA_SEL_3 {3}] $axi_pzslb_gt -set_property -dict [list CONFIG.CPLL_FBDIV_3 {2}] $axi_pzslb_gt -set_property -dict [list CONFIG.RX_OUT_DIV_3 {1}] $axi_pzslb_gt -set_property -dict [list CONFIG.TX_OUT_DIV_3 {1}] $axi_pzslb_gt -set_property -dict [list CONFIG.RX_CLK25_DIV_3 {10}] $axi_pzslb_gt -set_property -dict [list CONFIG.TX_CLK25_DIV_3 {10}] $axi_pzslb_gt -set_property -dict [list CONFIG.PMA_RSV_3 {0x00018480}] $axi_pzslb_gt -set_property -dict [list CONFIG.RX_CDR_CFG_3 {0x03000023ff20400020}] $axi_pzslb_gt - -set util_pzslb_gtlb_0 [create_bd_cell -type ip -vlnv analog.com:user:util_gtlb:1.0 util_pzslb_gtlb_0] -set util_pzslb_gtlb_1 [create_bd_cell -type ip -vlnv analog.com:user:util_gtlb:1.0 util_pzslb_gtlb_1] -set util_pzslb_gtlb_2 [create_bd_cell -type ip -vlnv analog.com:user:util_gtlb:1.0 util_pzslb_gtlb_2] -set util_pzslb_gtlb_3 [create_bd_cell -type ip -vlnv analog.com:user:util_gtlb:1.0 util_pzslb_gtlb_3] - -ad_cpu_interconnect 0x44A60000 axi_pzslb_gt -ad_mem_hp3_interconnect sys_cpu_clk sys_ps7/S_AXI_HP3 -ad_mem_hp3_interconnect sys_cpu_clk axi_pzslb_gt/m_axi - -create_bd_port -dir I gt_ref_clk -create_bd_port -dir I gt_rx_0_p -create_bd_port -dir I gt_rx_0_n -create_bd_port -dir O gt_tx_0_p -create_bd_port -dir O gt_tx_0_n -create_bd_port -dir I gt_rx_1_p -create_bd_port -dir I gt_rx_1_n -create_bd_port -dir O gt_tx_1_p -create_bd_port -dir O gt_tx_1_n -create_bd_port -dir I gt_rx_2_p -create_bd_port -dir I gt_rx_2_n -create_bd_port -dir O gt_tx_2_p -create_bd_port -dir O gt_tx_2_n -create_bd_port -dir I gt_rx_3_p -create_bd_port -dir I gt_rx_3_n -create_bd_port -dir O gt_tx_3_p -create_bd_port -dir O gt_tx_3_n - -ad_connect sys_cpu_clk util_pzslb_gtlb_0/up_clk -ad_connect sys_cpu_resetn util_pzslb_gtlb_0/up_rstn -ad_connect util_pzslb_gtlb_0/qpll_ref_clk gt_ref_clk -ad_connect util_pzslb_gtlb_0/cpll_ref_clk gt_ref_clk -ad_connect util_pzslb_gtlb_0/rx_p gt_rx_0_p -ad_connect util_pzslb_gtlb_0/rx_n gt_rx_0_n -ad_connect util_pzslb_gtlb_0/tx_p gt_tx_0_p -ad_connect util_pzslb_gtlb_0/tx_n gt_tx_0_n -ad_connect sys_cpu_clk util_pzslb_gtlb_1/up_clk -ad_connect sys_cpu_resetn util_pzslb_gtlb_1/up_rstn -ad_connect util_pzslb_gtlb_1/qpll_ref_clk gt_ref_clk -ad_connect util_pzslb_gtlb_1/cpll_ref_clk gt_ref_clk -ad_connect util_pzslb_gtlb_1/rx_p gt_rx_1_p -ad_connect util_pzslb_gtlb_1/rx_n gt_rx_1_n -ad_connect util_pzslb_gtlb_1/tx_p gt_tx_1_p -ad_connect util_pzslb_gtlb_1/tx_n gt_tx_1_n -ad_connect sys_cpu_clk util_pzslb_gtlb_2/up_clk -ad_connect sys_cpu_resetn util_pzslb_gtlb_2/up_rstn -ad_connect util_pzslb_gtlb_2/qpll_ref_clk gt_ref_clk -ad_connect util_pzslb_gtlb_2/cpll_ref_clk gt_ref_clk -ad_connect util_pzslb_gtlb_2/rx_p gt_rx_2_p -ad_connect util_pzslb_gtlb_2/rx_n gt_rx_2_n -ad_connect util_pzslb_gtlb_2/tx_p gt_tx_2_p -ad_connect util_pzslb_gtlb_2/tx_n gt_tx_2_n -ad_connect sys_cpu_clk util_pzslb_gtlb_3/up_clk -ad_connect sys_cpu_resetn util_pzslb_gtlb_3/up_rstn -ad_connect util_pzslb_gtlb_3/qpll_ref_clk gt_ref_clk -ad_connect util_pzslb_gtlb_3/cpll_ref_clk gt_ref_clk -ad_connect util_pzslb_gtlb_3/rx_p gt_rx_3_p -ad_connect util_pzslb_gtlb_3/rx_n gt_rx_3_n -ad_connect util_pzslb_gtlb_3/tx_p gt_tx_3_p -ad_connect util_pzslb_gtlb_3/tx_n gt_tx_3_n -ad_connect axi_pzslb_gt/gt_qpll_0 util_pzslb_gtlb_0/gt_qpll_0 -ad_connect axi_pzslb_gt/gt_pll_0 util_pzslb_gtlb_0/gt_pll_0 -ad_connect axi_pzslb_gt/gt_rx_0 util_pzslb_gtlb_0/gt_rx_0 -ad_connect axi_pzslb_gt/gt_tx_0 util_pzslb_gtlb_0/gt_tx_0 -ad_connect axi_pzslb_gt/gt_rx_ip_0 util_pzslb_gtlb_0/gt_rx_ip_0 -ad_connect axi_pzslb_gt/gt_tx_ip_0 util_pzslb_gtlb_0/gt_tx_ip_0 -ad_connect axi_pzslb_gt/rx_gt_comma_align_enb_0 util_pzslb_gtlb_0/rx_gt_comma_align_enb_0 -ad_connect axi_pzslb_gt/gt_pll_1 util_pzslb_gtlb_1/gt_pll_0 -ad_connect axi_pzslb_gt/gt_rx_1 util_pzslb_gtlb_1/gt_rx_0 -ad_connect axi_pzslb_gt/gt_tx_1 util_pzslb_gtlb_1/gt_tx_0 -ad_connect axi_pzslb_gt/gt_rx_ip_1 util_pzslb_gtlb_1/gt_rx_ip_0 -ad_connect axi_pzslb_gt/gt_tx_ip_1 util_pzslb_gtlb_1/gt_tx_ip_0 -ad_connect axi_pzslb_gt/rx_gt_comma_align_enb_1 util_pzslb_gtlb_1/rx_gt_comma_align_enb_0 -ad_connect axi_pzslb_gt/gt_pll_2 util_pzslb_gtlb_2/gt_pll_0 -ad_connect axi_pzslb_gt/gt_rx_2 util_pzslb_gtlb_2/gt_rx_0 -ad_connect axi_pzslb_gt/gt_tx_2 util_pzslb_gtlb_2/gt_tx_0 -ad_connect axi_pzslb_gt/gt_rx_ip_2 util_pzslb_gtlb_2/gt_rx_ip_0 -ad_connect axi_pzslb_gt/gt_tx_ip_2 util_pzslb_gtlb_2/gt_tx_ip_0 -ad_connect axi_pzslb_gt/rx_gt_comma_align_enb_2 util_pzslb_gtlb_2/rx_gt_comma_align_enb_0 -ad_connect axi_pzslb_gt/gt_pll_3 util_pzslb_gtlb_3/gt_pll_0 -ad_connect axi_pzslb_gt/gt_rx_3 util_pzslb_gtlb_3/gt_rx_0 -ad_connect axi_pzslb_gt/gt_tx_3 util_pzslb_gtlb_3/gt_tx_0 -ad_connect axi_pzslb_gt/gt_rx_ip_3 util_pzslb_gtlb_3/gt_rx_ip_0 -ad_connect axi_pzslb_gt/gt_tx_ip_3 util_pzslb_gtlb_3/gt_tx_ip_0 -ad_connect axi_pzslb_gt/rx_gt_comma_align_enb_3 util_pzslb_gtlb_3/rx_gt_comma_align_enb_0 - -# un-used io (regular) - -set axi_gpreg [create_bd_cell -type ip -vlnv analog.com:user:axi_gpreg:1.0 axi_gpreg] -set_property -dict [list CONFIG.NUM_OF_CLK_MONS {8}] $axi_gpreg -set_property -dict [list CONFIG.BUF_ENABLE_0 {0}] $axi_gpreg -set_property -dict [list CONFIG.BUF_ENABLE_1 {0}] $axi_gpreg -set_property -dict [list CONFIG.BUF_ENABLE_2 {0}] $axi_gpreg -set_property -dict [list CONFIG.BUF_ENABLE_3 {0}] $axi_gpreg -set_property -dict [list CONFIG.BUF_ENABLE_4 {0}] $axi_gpreg -set_property -dict [list CONFIG.BUF_ENABLE_5 {0}] $axi_gpreg -set_property -dict [list CONFIG.BUF_ENABLE_6 {0}] $axi_gpreg -set_property -dict [list CONFIG.BUF_ENABLE_7 {0}] $axi_gpreg -set_property -dict [list CONFIG.NUM_OF_IO {7}] $axi_gpreg - -ad_cpu_interconnect 0x41200000 axi_gpreg - -ad_connect util_pzslb_gtlb_0/rx_clk axi_gpreg/d_clk_0 -ad_connect util_pzslb_gtlb_0/tx_clk axi_gpreg/d_clk_1 -ad_connect util_pzslb_gtlb_1/rx_clk axi_gpreg/d_clk_2 -ad_connect util_pzslb_gtlb_1/tx_clk axi_gpreg/d_clk_3 -ad_connect util_pzslb_gtlb_2/rx_clk axi_gpreg/d_clk_4 -ad_connect util_pzslb_gtlb_2/tx_clk axi_gpreg/d_clk_5 -ad_connect util_pzslb_gtlb_3/rx_clk axi_gpreg/d_clk_6 -ad_connect util_pzslb_gtlb_3/tx_clk axi_gpreg/d_clk_7 - -create_bd_port -dir I -from 31 -to 0 gp_in_0 -create_bd_port -dir I -from 31 -to 0 gp_in_1 -create_bd_port -dir I -from 31 -to 0 gp_in_2 -create_bd_port -dir O -from 31 -to 0 gp_out_0 -create_bd_port -dir O -from 31 -to 0 gp_out_1 -create_bd_port -dir O -from 31 -to 0 gp_out_2 - -ad_connect gp_in_0 axi_gpreg/up_gp_in_0 -ad_connect gp_in_1 axi_gpreg/up_gp_in_1 -ad_connect gp_in_2 axi_gpreg/up_gp_in_2 -ad_connect gp_out_0 axi_gpreg/up_gp_out_0 -ad_connect gp_out_1 axi_gpreg/up_gp_out_1 -ad_connect gp_out_2 axi_gpreg/up_gp_out_2 -ad_connect axi_gpreg/up_gp_in_3 util_pzslb_gtlb_0/up_gp_out -ad_connect axi_gpreg/up_gp_out_3 util_pzslb_gtlb_0/up_gp_in -ad_connect axi_gpreg/up_gp_in_4 util_pzslb_gtlb_1/up_gp_out -ad_connect axi_gpreg/up_gp_out_4 util_pzslb_gtlb_1/up_gp_in -ad_connect axi_gpreg/up_gp_in_5 util_pzslb_gtlb_2/up_gp_out -ad_connect axi_gpreg/up_gp_out_5 util_pzslb_gtlb_2/up_gp_in -ad_connect axi_gpreg/up_gp_in_6 util_pzslb_gtlb_3/up_gp_out -ad_connect axi_gpreg/up_gp_out_6 util_pzslb_gtlb_3/up_gp_in - -## temporary (remove ila indirectly) - -delete_bd_objs [get_bd_cells ila_adc] -delete_bd_objs [get_bd_nets axi_ad9361_tdd_dbg] [get_bd_cells ila_tdd] - diff --git a/projects/pzsdr1/Makefile b/projects/pzsdr1/Makefile new file mode 100644 index 000000000..a7e5f4320 --- /dev/null +++ b/projects/pzsdr1/Makefile @@ -0,0 +1,30 @@ +#################################################################################### +#################################################################################### +## Copyright 2011(c) Analog Devices, Inc. +## Auto-generated, do not modify! +#################################################################################### +#################################################################################### + +.PHONY: all clean clean-all +all: + -make -C ccbox_lvds all + -make -C ccbrk_cmos all + -make -C ccbrk_lvds all + -make -C ccusb_lvds all + + +clean: + make -C ccbox_lvds clean + make -C ccbrk_cmos clean + make -C ccbrk_lvds clean + make -C ccusb_lvds clean + + +clean-all: + make -C ccbox_lvds clean-all + make -C ccbrk_cmos clean-all + make -C ccbrk_lvds clean-all + make -C ccusb_lvds clean-all + +#################################################################################### +#################################################################################### diff --git a/projects/pzsdr1/README.md b/projects/pzsdr1/README.md new file mode 100644 index 000000000..e59185903 --- /dev/null +++ b/projects/pzsdr1/README.md @@ -0,0 +1,48 @@ +# PicoZed SDR SOM (PZSDR2) + +This folder contains the PZSDR2 SOM projects for each of the carrier boards. + +## Board Design Files + +| Directory/File | Description | +|----------------------|----------------------------------------| +| common/pzsdr2_bd.tcl | pzsdr2 SOM module board design file. | +| common/ccbrk_bd.tcl | carrier, break out board design file. | +| common/ccfmc_bd.tcl | carrier, fmc board design file. | +| common/ccpci_bd.tcl | carrier, pci-e board design file. | +| common/ccusb_bd.tcl | carrier, usb board design file. | + +FMC & BRK carrier designs includes loopback daughtercards for connectivity testing. + +## Board Constraint Files + +| Directory/File | Description | +|-------------------------------|-----------------------------------------------| +| common/pzsdr2_constr.xdc | pzsdr2 SOM base constraints file. | +| common/pzsdr2_constr_cmos.xdc | pzsdr2 SOM CMOS mode constraints file. | +| common/pzsdr2_constr_lvds.xdc | pzsdr2 SOM LVDS mode constraints file. | +| common/ccbrk_constr.xdc | carrier, break out board constraints file. | +| common/ccfmc_constr.xdc | carrier, fmc board constraints file. | +| common/ccpci_constr.xdc | carrier, pci-e board constraints file. | +| common/ccusb_constr.xdc | carrier, usb board constraints file. | + +FMC & BRK carrier designs includes loopback daughtercards for connectivity testing. + +## Building, Generating Bit Files + +[pzsdr2] cd ccbrk_cmos + +[pzsdr2/ccbrk_cmos] make + +The make in each carrier directory builds the corresponding project. The above example builds PZSDR2-CCBRK hardware bit files in CMOS mode. + +## Documentation + + * [HDL Design User Guide] + * [IP User Guide] + * [PZSDR2 Wiki page] + +[HDL Design User Guide]:http://wiki.analog.com/resources/fpga/docs/hdl +[IP User Guide]:http://wiki.analog.com/resources/fpga/docs/axi_ad9361 +[PZSDR2 Wiki page]:https://wiki.analog.com/resources/eval/user-guides/picozed_sdr + diff --git a/projects/pzsdr1/ccbox_lvds/Makefile b/projects/pzsdr1/ccbox_lvds/Makefile new file mode 100644 index 000000000..4f99f1cef --- /dev/null +++ b/projects/pzsdr1/ccbox_lvds/Makefile @@ -0,0 +1,85 @@ +#################################################################################### +#################################################################################### +## Copyright 2011(c) Analog Devices, Inc. +## Auto-generated, do not modify! +#################################################################################### +#################################################################################### + +M_DEPS += system_top.v +M_DEPS += system_project.tcl +M_DEPS += system_bd.tcl +M_DEPS += ../common/pzsdr1_constr_lvds.xdc +M_DEPS += ../common/pzsdr1_constr.xdc +M_DEPS += ../common/pzsdr1_bd.tcl +M_DEPS += ../common/ccbox_constr.xdc +M_DEPS += ../common/ccbox_bd.tcl +M_DEPS += ../../scripts/adi_project.tcl +M_DEPS += ../../scripts/adi_env.tcl +M_DEPS += ../../scripts/adi_board.tcl +M_DEPS += ../../../library/xilinx/common/ad_iobuf.v +M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr +M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr +M_DEPS += ../../../library/axi_i2s_adi/axi_i2s_adi.xpr +M_DEPS += ../../../library/util_clkdiv/util_clkdiv.xpr +M_DEPS += ../../../library/util_cpack/util_cpack.xpr +M_DEPS += ../../../library/util_rfifo/util_rfifo.xpr +M_DEPS += ../../../library/util_tdd_sync/util_tdd_sync.xpr +M_DEPS += ../../../library/util_upack/util_upack.xpr +M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr + +M_VIVADO := vivado -mode batch -source + +M_FLIST := *.cache +M_FLIST += *.data +M_FLIST += *.xpr +M_FLIST += *.log +M_FLIST += *.jou +M_FLIST += xgui +M_FLIST += *.runs +M_FLIST += *.srcs +M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim +M_FLIST += .Xil +M_FLIST += *.ip_user_files + + + +.PHONY: all lib clean clean-all +all: lib pzsdr1_ccbox_lvds.sdk/system_top.hdf + + +clean: + rm -rf $(M_FLIST) + + +clean-all:clean + make -C ../../../library/axi_ad9361 clean + make -C ../../../library/axi_dmac clean + make -C ../../../library/axi_i2s_adi clean + make -C ../../../library/util_clkdiv clean + make -C ../../../library/util_cpack clean + make -C ../../../library/util_rfifo clean + make -C ../../../library/util_tdd_sync clean + make -C ../../../library/util_upack clean + make -C ../../../library/util_wfifo clean + + +pzsdr1_ccbox_lvds.sdk/system_top.hdf: $(M_DEPS) + -rm -rf $(M_FLIST) + $(M_VIVADO) system_project.tcl >> pzsdr1_ccbox_lvds_vivado.log 2>&1 + + +lib: + make -C ../../../library/axi_ad9361 + make -C ../../../library/axi_dmac + make -C ../../../library/axi_i2s_adi + make -C ../../../library/util_clkdiv + make -C ../../../library/util_cpack + make -C ../../../library/util_rfifo + make -C ../../../library/util_tdd_sync + make -C ../../../library/util_upack + make -C ../../../library/util_wfifo + +#################################################################################### +#################################################################################### diff --git a/projects/pzsdr1/ccbox_lvds/system_bd.tcl b/projects/pzsdr1/ccbox_lvds/system_bd.tcl new file mode 100644 index 000000000..a870f5764 --- /dev/null +++ b/projects/pzsdr1/ccbox_lvds/system_bd.tcl @@ -0,0 +1,6 @@ + +source ../common/pzsdr1_bd.tcl +source ../common/ccbox_bd.tcl + +cfg_ad9361_interface LVDS + diff --git a/projects/pzsdr1/ccbox_lvds/system_project.tcl b/projects/pzsdr1/ccbox_lvds/system_project.tcl new file mode 100644 index 000000000..61ed874fb --- /dev/null +++ b/projects/pzsdr1/ccbox_lvds/system_project.tcl @@ -0,0 +1,17 @@ + +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/projects/scripts/adi_project.tcl +source $ad_hdl_dir/projects/scripts/adi_board.tcl + +set p_device "xc7z020clg400-1" +adi_project_create pzsdr1_ccbox_lvds +adi_project_files pzsdr1_ccbox_lvds [list \ + "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \ + "../common/pzsdr1_constr.xdc" \ + "../common/pzsdr1_constr_lvds.xdc" \ + "../common/ccbox_constr.xdc" \ + "system_top.v" ] + +adi_project_run pzsdr1_ccbox_lvds + + diff --git a/projects/pzsdr1/ccbox_lvds/system_top.v b/projects/pzsdr1/ccbox_lvds/system_top.v new file mode 100644 index 000000000..2c806a77e --- /dev/null +++ b/projects/pzsdr1/ccbox_lvds/system_top.v @@ -0,0 +1,319 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top ( + + inout [14:0] ddr_addr, + inout [ 2:0] ddr_ba, + inout ddr_cas_n, + inout ddr_ck_n, + inout ddr_ck_p, + inout ddr_cke, + inout ddr_cs_n, + inout [ 3:0] ddr_dm, + inout [31:0] ddr_dq, + inout [ 3:0] ddr_dqs_n, + inout [ 3:0] ddr_dqs_p, + inout ddr_odt, + inout ddr_ras_n, + inout ddr_reset_n, + inout ddr_we_n, + + inout fixed_io_ddr_vrn, + inout fixed_io_ddr_vrp, + inout [53:0] fixed_io_mio, + inout fixed_io_ps_clk, + inout fixed_io_ps_porb, + inout fixed_io_ps_srstb, + + inout iic_scl, + inout iic_sda, + + output i2s_mclk, + output i2s_bclk, + output i2s_lrclk, + output i2s_sdata_out, + input i2s_sdata_in, + + output imu_csn, + output imu_clk, + output imu_mosi, + input imu_miso, + input imu_ready, + output imu_rstn, + inout imu_sync, + + output oled_csn, + output oled_clk, + output oled_mosi, + output oled_rst, + output oled_dc, + + output switch_led_r, + output switch_led_g, + output switch_led_b, + + output gps_reset, + output gps_force_on, + output gps_standby, + input gps_pps, + + input [ 2:0] pss_valid_n, + inout [ 2:0] adp5061_io, + + inout ltc2955_kill_n, + inout ltc2955_int_n, + inout mic_present_n, + inout ts3a227_int_n, + + input rx_clk_in_p, + input rx_clk_in_n, + input rx_frame_in_p, + input rx_frame_in_n, + input [ 5:0] rx_data_in_p, + input [ 5:0] rx_data_in_n, + output tx_clk_out_p, + output tx_clk_out_n, + output tx_frame_out_p, + output tx_frame_out_n, + output [ 5:0] tx_data_out_p, + output [ 5:0] tx_data_out_n, + + output enable, + output txnrx, + input clkout_in, + + inout gpio_rf0, + inout gpio_rf1, + inout gpio_rf2, + inout gpio_rf3, + inout gpio_rf4, + inout gpio_rfpwr_enable, + inout gpio_clksel, + inout gpio_resetb, + inout gpio_sync, + inout gpio_en_agc, + inout [ 3:0] gpio_ctl, + inout [ 7:0] gpio_status, + + output spi_csn, + output spi_clk, + output spi_mosi, + input spi_miso); + + // internal signals + + wire [63:0] gpio_i; + wire [63:0] gpio_o; + wire [63:0] gpio_t; + + // assignments + + assign oled_clk = spi_clk; + assign oled_mosi = spi_mosi; + + // gpio[31:20] controls misc stuff (keep as io) + + assign gpio_i[31:29] = gpio_o[31:29]; + assign gpio_i[28:28] = imu_ready; + assign gpio_i[27:24] = gpio_o[27:24]; + + ad_iobuf #(.DATA_WIDTH(4)) i_iobuf_misc ( + .dio_t (gpio_t[23:20]), + .dio_i (gpio_o[23:20]), + .dio_o (gpio_i[23:20]), + .dio_p ({ ltc2955_kill_n, + ltc2955_int_n, + ts3a227_int_n, + mic_present_n})); + + // gpio[19:16] controls adp5061 (keep as io) + + assign gpio_i[19] = gpio_o[19]; + + ad_iobuf #(.DATA_WIDTH(3)) i_iobuf_adp5061 ( + .dio_t (gpio_t[18:16]), + .dio_i (gpio_o[18:16]), + .dio_o (gpio_i[18:16]), + .dio_p (adp5061_io)); + + // gpio[15:12] reads power source select valids + + assign gpio_i[15:12] = {gpio_o[15], pss_valid_n}; + + // gpio[11:8] controls the imu/oled reset & such. + + assign oled_dc = gpio_o[11]; + assign oled_rst = gpio_o[10]; + assign imu_rstn = gpio_o[9]; + assign gpio_i[11:9] = gpio_o[11:9]; + + ad_iobuf #(.DATA_WIDTH(1)) i_iobuf_imu_sync ( + .dio_t (gpio_t[8]), + .dio_i (gpio_o[8]), + .dio_o (gpio_i[8]), + .dio_p (imu_sync)); + + // gpio[7:4] controls the gps + + assign gps_reset = gpio_o[6]; + assign gps_force_on = gpio_o[5]; + assign gps_standby = gpio_o[4]; + assign gpio_i[7:4] = {gps_pps, gpio_o[6:4]}; + + // gpio[3:0] controls the power switch led colors + + assign switch_led_r = gpio_o[2]; + assign switch_led_g = gpio_o[1]; + assign switch_led_b = gpio_o[0]; + assign gpio_i[3:0] = gpio_o[3:0]; + + // ad9361 gpio - 63-32 + + assign gpio_i[63:62] = gpio_o[63:62]; + assign gpio_i[60:57] = gpio_o[60:57]; + assign gpio_i[50:47] = gpio_o[50:47]; + + ad_iobuf #(.DATA_WIDTH(22)) i_iobuf ( + .dio_t ({gpio_t[61:61], gpio_t[56:51], gpio_t[46:32]}), + .dio_i ({gpio_o[61:61], gpio_o[56:51], gpio_o[46:32]}), + .dio_o ({gpio_i[61:61], gpio_i[56:51], gpio_i[46:32]}), + .dio_p ({ gpio_rf4, // 61:61 + gpio_rf0, // 56:56 + gpio_rf1, // 55:55 + gpio_rf2, // 54:54 + gpio_rf3, // 53:53 + gpio_rfpwr_enable, // 52:52 + gpio_clksel, // 51:51 + gpio_resetb, // 46:46 + gpio_sync, // 45:45 + gpio_en_agc, // 44:44 + gpio_ctl, // 43:40 + gpio_status})); // 39:32 + + // instantiations + + system_wrapper i_system_wrapper ( + .ddr_addr (ddr_addr), + .ddr_ba (ddr_ba), + .ddr_cas_n (ddr_cas_n), + .ddr_ck_n (ddr_ck_n), + .ddr_ck_p (ddr_ck_p), + .ddr_cke (ddr_cke), + .ddr_cs_n (ddr_cs_n), + .ddr_dm (ddr_dm), + .ddr_dq (ddr_dq), + .ddr_dqs_n (ddr_dqs_n), + .ddr_dqs_p (ddr_dqs_p), + .ddr_odt (ddr_odt), + .ddr_ras_n (ddr_ras_n), + .ddr_reset_n (ddr_reset_n), + .ddr_we_n (ddr_we_n), + .enable (enable), + .fixed_io_ddr_vrn (fixed_io_ddr_vrn), + .fixed_io_ddr_vrp (fixed_io_ddr_vrp), + .fixed_io_mio (fixed_io_mio), + .fixed_io_ps_clk (fixed_io_ps_clk), + .fixed_io_ps_porb (fixed_io_ps_porb), + .fixed_io_ps_srstb (fixed_io_ps_srstb), + .gpio_i (gpio_i), + .gpio_o (gpio_o), + .gpio_t (gpio_t), + .i2s_bclk (i2s_bclk), + .i2s_lrclk (i2s_lrclk), + .i2s_mclk (i2s_mclk), + .i2s_sdata_in (i2s_sdata_in), + .i2s_sdata_out (i2s_sdata_out), + .iic_main_scl_io (iic_scl), + .iic_main_sda_io (iic_sda), + .otg_vbusoc (1'b0), + .ps_intr_00 (1'b0), + .ps_intr_01 (1'b0), + .ps_intr_02 (1'b0), + .ps_intr_03 (1'b0), + .ps_intr_04 (1'b0), + .ps_intr_05 (1'b0), + .ps_intr_06 (1'b0), + .ps_intr_07 (1'b0), + .ps_intr_08 (1'b0), + .ps_intr_09 (1'b0), + .ps_intr_10 (1'b0), + .ps_intr_11 (1'b0), + .ps_intr_15 (1'b0), + .rx_clk_in_n (rx_clk_in_n), + .rx_clk_in_p (rx_clk_in_p), + .rx_data_in_n (rx_data_in_n), + .rx_data_in_p (rx_data_in_p), + .rx_frame_in_n (rx_frame_in_n), + .rx_frame_in_p (rx_frame_in_p), + .spi0_clk_i (1'b0), + .spi0_clk_o (spi_clk), + .spi0_csn_0_o (spi_csn), + .spi0_csn_1_o (oled_csn), + .spi0_csn_2_o (), + .spi0_csn_i (1'b1), + .spi0_sdi_i (spi_miso), + .spi0_sdo_i (1'b0), + .spi0_sdo_o (spi_mosi), + .spi1_clk_i (1'b0), + .spi1_clk_o (imu_clk), + .spi1_csn_0_o (imu_csn), + .spi1_csn_1_o (), + .spi1_csn_2_o (), + .spi1_csn_i (1'b1), + .spi1_sdi_i (imu_miso), + .spi1_sdo_i (1'b0), + .spi1_sdo_o (imu_mosi), + .tdd_sync_i (gps_pps), + .tdd_sync_o (), + .tdd_sync_t (), + .tx_clk_out_n (tx_clk_out_n), + .tx_clk_out_p (tx_clk_out_p), + .tx_data_out_n (tx_data_out_n), + .tx_data_out_p (tx_data_out_p), + .tx_frame_out_n (tx_frame_out_n), + .tx_frame_out_p (tx_frame_out_p), + .txnrx (txnrx), + .up_enable (gpio_o[47]), + .up_txnrx (gpio_o[48])); + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/projects/pzsdr/ccbrk/Makefile b/projects/pzsdr1/ccbrk_cmos/Makefile similarity index 73% rename from projects/pzsdr/ccbrk/Makefile rename to projects/pzsdr1/ccbrk_cmos/Makefile index 001dbd654..77e805b1b 100644 --- a/projects/pzsdr/ccbrk/Makefile +++ b/projects/pzsdr1/ccbrk_cmos/Makefile @@ -7,24 +7,22 @@ M_DEPS += system_top.v M_DEPS += system_project.tcl -M_DEPS += system_constr.xdc M_DEPS += system_bd.tcl +M_DEPS += ../common/pzsdr1_constr_cmos.xdc +M_DEPS += ../common/pzsdr1_constr.xdc +M_DEPS += ../common/pzsdr1_bd.tcl +M_DEPS += ../common/ccbrk_constr.xdc M_DEPS += ../common/ccbrk_bd.tcl M_DEPS += ../../scripts/adi_project.tcl M_DEPS += ../../scripts/adi_env.tcl M_DEPS += ../../scripts/adi_board.tcl -M_DEPS += ../../fmcomms2/common/fmcomms2_bd.tcl -M_DEPS += ../../common/xilinx/sys_wfifo.tcl -M_DEPS += ../../common/pzsdr/pzsdr_system_ps7.tcl -M_DEPS += ../../common/pzsdr/pzsdr_system_constr.xdc -M_DEPS += ../../common/pzsdr/pzsdr_system_bd.tcl -M_DEPS += ../../../library/common/ad_iobuf.v +M_DEPS += ../../../library/xilinx/common/ad_iobuf.v M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr M_DEPS += ../../../library/axi_gpreg/axi_gpreg.xpr -M_DEPS += ../../../library/axi_jesd_gt/axi_jesd_gt.xpr +M_DEPS += ../../../library/util_clkdiv/util_clkdiv.xpr M_DEPS += ../../../library/util_cpack/util_cpack.xpr -M_DEPS += ../../../library/util_gtlb/util_gtlb.xpr +M_DEPS += ../../../library/util_rfifo/util_rfifo.xpr M_DEPS += ../../../library/util_tdd_sync/util_tdd_sync.xpr M_DEPS += ../../../library/util_upack/util_upack.xpr M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr @@ -43,11 +41,12 @@ M_FLIST += *.sdk M_FLIST += *.hw M_FLIST += *.sim M_FLIST += .Xil +M_FLIST += *.ip_user_files .PHONY: all lib clean clean-all -all: lib ccbrk_pzsdr.sdk/system_top.hdf +all: lib pzsdr1_ccbrk_cmos.sdk/system_top.hdf clean: @@ -58,26 +57,26 @@ clean-all:clean make -C ../../../library/axi_ad9361 clean make -C ../../../library/axi_dmac clean make -C ../../../library/axi_gpreg clean - make -C ../../../library/axi_jesd_gt clean + make -C ../../../library/util_clkdiv clean make -C ../../../library/util_cpack clean - make -C ../../../library/util_gtlb clean + make -C ../../../library/util_rfifo clean make -C ../../../library/util_tdd_sync clean make -C ../../../library/util_upack clean make -C ../../../library/util_wfifo clean -ccbrk_pzsdr.sdk/system_top.hdf: $(M_DEPS) - rm -rf $(M_FLIST) - $(M_VIVADO) system_project.tcl >> ccbrk_pzsdr_vivado.log 2>&1 +pzsdr1_ccbrk_cmos.sdk/system_top.hdf: $(M_DEPS) + -rm -rf $(M_FLIST) + $(M_VIVADO) system_project.tcl >> pzsdr1_ccbrk_cmos_vivado.log 2>&1 lib: make -C ../../../library/axi_ad9361 make -C ../../../library/axi_dmac make -C ../../../library/axi_gpreg - make -C ../../../library/axi_jesd_gt + make -C ../../../library/util_clkdiv make -C ../../../library/util_cpack - make -C ../../../library/util_gtlb + make -C ../../../library/util_rfifo make -C ../../../library/util_tdd_sync make -C ../../../library/util_upack make -C ../../../library/util_wfifo diff --git a/projects/pzsdr1/ccbrk_cmos/system_bd.tcl b/projects/pzsdr1/ccbrk_cmos/system_bd.tcl new file mode 100644 index 000000000..52356bdca --- /dev/null +++ b/projects/pzsdr1/ccbrk_cmos/system_bd.tcl @@ -0,0 +1,9 @@ + +source ../common/pzsdr1_bd.tcl +source ../common/ccbrk_bd.tcl + +set_property -dict [list CONFIG.SEL_0_DIV {2}] $clkdiv +set_property -dict [list CONFIG.SEL_1_DIV {1}] $clkdiv + +cfg_ad9361_interface CMOS + diff --git a/projects/pzsdr1/ccbrk_cmos/system_project.tcl b/projects/pzsdr1/ccbrk_cmos/system_project.tcl new file mode 100644 index 000000000..43da2c3f4 --- /dev/null +++ b/projects/pzsdr1/ccbrk_cmos/system_project.tcl @@ -0,0 +1,18 @@ + +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/projects/scripts/adi_project.tcl +source $ad_hdl_dir/projects/scripts/adi_board.tcl + +set p_device "xc7z020clg400-1" +adi_project_create pzsdr1_ccbrk_cmos +adi_project_files pzsdr1_ccbrk_cmos [list \ + "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \ + "../common/pzsdr1_constr.xdc" \ + "../common/pzsdr1_constr_cmos.xdc" \ + "../common/ccbrk_constr.xdc" \ + "system_top.v" ] + +set_property is_enabled false [get_files *axi_gpreg_constr.xdc] +adi_project_run pzsdr1_ccbrk_cmos + + diff --git a/projects/pzsdr1/ccbrk_cmos/system_top.v b/projects/pzsdr1/ccbrk_cmos/system_top.v new file mode 100644 index 000000000..52fb7cd66 --- /dev/null +++ b/projects/pzsdr1/ccbrk_cmos/system_top.v @@ -0,0 +1,221 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top ( + + inout [14:0] ddr_addr, + inout [ 2:0] ddr_ba, + inout ddr_cas_n, + inout ddr_ck_n, + inout ddr_ck_p, + inout ddr_cke, + inout ddr_cs_n, + inout [ 3:0] ddr_dm, + inout [31:0] ddr_dq, + inout [ 3:0] ddr_dqs_n, + inout [ 3:0] ddr_dqs_p, + inout ddr_odt, + inout ddr_ras_n, + inout ddr_reset_n, + inout ddr_we_n, + + inout fixed_io_ddr_vrn, + inout fixed_io_ddr_vrp, + inout [53:0] fixed_io_mio, + inout fixed_io_ps_clk, + inout fixed_io_ps_porb, + inout fixed_io_ps_srstb, + + inout iic_scl, + inout iic_sda, + + inout [10:0] gpio_bd, + + input rx_clk_in, + input rx_frame_in, + input [11:0] rx_data_in, + output tx_clk_out, + output tx_frame_out, + output [11:0] tx_data_out, + output [ 1:0] tx_gnd, + + output enable, + output txnrx, + input clkout_in, + output clkout_out, + + inout gpio_clksel, + inout gpio_resetb, + inout gpio_sync, + inout gpio_en_agc, + inout [ 3:0] gpio_ctl, + inout [ 7:0] gpio_status, + + output spi_csn, + output spi_clk, + output spi_mosi, + input spi_miso, + + output [27:0] gp_out, + input [27:0] gp_in); + + + // internal signals + + wire [31:0] gp_out_s; + wire [31:0] gp_in_s; + wire [63:0] gpio_i; + wire [63:0] gpio_o; + wire [63:0] gpio_t; + + // assignments + + assign tx_gnd = 2'd0; + assign clkout_out = clkout_in; + assign gp_out[27:0] = gp_out_s[27:0]; + assign gp_in_s[31:28] = gp_out_s[31:28]; + assign gp_in_s[27: 0] = gp_in[27:0]; + + // board gpio - 31-0 + + assign gpio_i[31:11] = gpio_o[31:11]; + + ad_iobuf #(.DATA_WIDTH(11)) i_iobuf_bd ( + .dio_t (gpio_t[10:0]), + .dio_i (gpio_o[10:0]), + .dio_o (gpio_i[10:0]), + .dio_p (gpio_bd)); + + // ad9361 gpio - 63-32 + + assign gpio_i[63:52] = gpio_o[63:52]; + assign gpio_i[50:47] = gpio_o[50:47]; + + ad_iobuf #(.DATA_WIDTH(16)) i_iobuf ( + .dio_t ({gpio_t[51], gpio_t[46:32]}), + .dio_i ({gpio_o[51], gpio_o[46:32]}), + .dio_o ({gpio_i[51], gpio_i[46:32]}), + .dio_p ({ gpio_clksel, // 51:51 + gpio_resetb, // 46:46 + gpio_sync, // 45:45 + gpio_en_agc, // 44:44 + gpio_ctl, // 43:40 + gpio_status})); // 39:32 + + // instantiations + + system_wrapper i_system_wrapper ( + .ddr_addr (ddr_addr), + .ddr_ba (ddr_ba), + .ddr_cas_n (ddr_cas_n), + .ddr_ck_n (ddr_ck_n), + .ddr_ck_p (ddr_ck_p), + .ddr_cke (ddr_cke), + .ddr_cs_n (ddr_cs_n), + .ddr_dm (ddr_dm), + .ddr_dq (ddr_dq), + .ddr_dqs_n (ddr_dqs_n), + .ddr_dqs_p (ddr_dqs_p), + .ddr_odt (ddr_odt), + .ddr_ras_n (ddr_ras_n), + .ddr_reset_n (ddr_reset_n), + .ddr_we_n (ddr_we_n), + .enable (enable), + .fixed_io_ddr_vrn (fixed_io_ddr_vrn), + .fixed_io_ddr_vrp (fixed_io_ddr_vrp), + .fixed_io_mio (fixed_io_mio), + .fixed_io_ps_clk (fixed_io_ps_clk), + .fixed_io_ps_porb (fixed_io_ps_porb), + .fixed_io_ps_srstb (fixed_io_ps_srstb), + .gp_in_0 (gp_in_s[31:0]), + .gp_out_0 (gp_out_s[31:0]), + .gpio_i (gpio_i), + .gpio_o (gpio_o), + .gpio_t (gpio_t), + .iic_main_scl_io (iic_scl), + .iic_main_sda_io (iic_sda), + .otg_vbusoc (1'b0), + .ps_intr_00 (1'b0), + .ps_intr_01 (1'b0), + .ps_intr_02 (1'b0), + .ps_intr_03 (1'b0), + .ps_intr_04 (1'b0), + .ps_intr_05 (1'b0), + .ps_intr_06 (1'b0), + .ps_intr_07 (1'b0), + .ps_intr_08 (1'b0), + .ps_intr_09 (1'b0), + .ps_intr_10 (1'b0), + .ps_intr_11 (1'b0), + .ps_intr_15 (1'b0), + .rx_clk_in (rx_clk_in), + .rx_data_in (rx_data_in), + .rx_frame_in (rx_frame_in), + .spi0_clk_i (1'b0), + .spi0_clk_o (spi_clk), + .spi0_csn_0_o (spi_csn), + .spi0_csn_1_o (), + .spi0_csn_2_o (), + .spi0_csn_i (1'b1), + .spi0_sdi_i (spi_miso), + .spi0_sdo_i (1'b0), + .spi0_sdo_o (spi_mosi), + .spi1_clk_i (1'b0), + .spi1_clk_o (), + .spi1_csn_0_o (), + .spi1_csn_1_o (), + .spi1_csn_2_o (), + .spi1_csn_i (1'b1), + .spi1_sdi_i (1'b0), + .spi1_sdo_i (1'b0), + .spi1_sdo_o (), + .tdd_sync_i (1'b0), + .tdd_sync_o (), + .tdd_sync_t (), + .tx_clk_out (tx_clk_out), + .tx_data_out (tx_data_out), + .tx_frame_out (tx_frame_out), + .txnrx (txnrx), + .up_enable (gpio_o[47]), + .up_txnrx (gpio_o[48])); + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/projects/pzsdr1/ccbrk_lvds/Makefile b/projects/pzsdr1/ccbrk_lvds/Makefile new file mode 100644 index 000000000..02c1d8180 --- /dev/null +++ b/projects/pzsdr1/ccbrk_lvds/Makefile @@ -0,0 +1,85 @@ +#################################################################################### +#################################################################################### +## Copyright 2011(c) Analog Devices, Inc. +## Auto-generated, do not modify! +#################################################################################### +#################################################################################### + +M_DEPS += system_top.v +M_DEPS += system_project.tcl +M_DEPS += system_bd.tcl +M_DEPS += ../common/pzsdr1_constr_lvds.xdc +M_DEPS += ../common/pzsdr1_constr.xdc +M_DEPS += ../common/pzsdr1_bd.tcl +M_DEPS += ../common/ccbrk_constr.xdc +M_DEPS += ../common/ccbrk_bd.tcl +M_DEPS += ../../scripts/adi_project.tcl +M_DEPS += ../../scripts/adi_env.tcl +M_DEPS += ../../scripts/adi_board.tcl +M_DEPS += ../../../library/xilinx/common/ad_iobuf.v +M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr +M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr +M_DEPS += ../../../library/axi_gpreg/axi_gpreg.xpr +M_DEPS += ../../../library/util_clkdiv/util_clkdiv.xpr +M_DEPS += ../../../library/util_cpack/util_cpack.xpr +M_DEPS += ../../../library/util_rfifo/util_rfifo.xpr +M_DEPS += ../../../library/util_tdd_sync/util_tdd_sync.xpr +M_DEPS += ../../../library/util_upack/util_upack.xpr +M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr + +M_VIVADO := vivado -mode batch -source + +M_FLIST := *.cache +M_FLIST += *.data +M_FLIST += *.xpr +M_FLIST += *.log +M_FLIST += *.jou +M_FLIST += xgui +M_FLIST += *.runs +M_FLIST += *.srcs +M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim +M_FLIST += .Xil +M_FLIST += *.ip_user_files + + + +.PHONY: all lib clean clean-all +all: lib pzsdr1_ccbrk_lvds.sdk/system_top.hdf + + +clean: + rm -rf $(M_FLIST) + + +clean-all:clean + make -C ../../../library/axi_ad9361 clean + make -C ../../../library/axi_dmac clean + make -C ../../../library/axi_gpreg clean + make -C ../../../library/util_clkdiv clean + make -C ../../../library/util_cpack clean + make -C ../../../library/util_rfifo clean + make -C ../../../library/util_tdd_sync clean + make -C ../../../library/util_upack clean + make -C ../../../library/util_wfifo clean + + +pzsdr1_ccbrk_lvds.sdk/system_top.hdf: $(M_DEPS) + -rm -rf $(M_FLIST) + $(M_VIVADO) system_project.tcl >> pzsdr1_ccbrk_lvds_vivado.log 2>&1 + + +lib: + make -C ../../../library/axi_ad9361 + make -C ../../../library/axi_dmac + make -C ../../../library/axi_gpreg + make -C ../../../library/util_clkdiv + make -C ../../../library/util_cpack + make -C ../../../library/util_rfifo + make -C ../../../library/util_tdd_sync + make -C ../../../library/util_upack + make -C ../../../library/util_wfifo + +#################################################################################### +#################################################################################### diff --git a/projects/pzsdr1/ccbrk_lvds/system_bd.tcl b/projects/pzsdr1/ccbrk_lvds/system_bd.tcl new file mode 100644 index 000000000..40c65fd14 --- /dev/null +++ b/projects/pzsdr1/ccbrk_lvds/system_bd.tcl @@ -0,0 +1,6 @@ + +source ../common/pzsdr1_bd.tcl +source ../common/ccbrk_bd.tcl + +cfg_ad9361_interface LVDS + diff --git a/projects/pzsdr1/ccbrk_lvds/system_project.tcl b/projects/pzsdr1/ccbrk_lvds/system_project.tcl new file mode 100644 index 000000000..1a40648ef --- /dev/null +++ b/projects/pzsdr1/ccbrk_lvds/system_project.tcl @@ -0,0 +1,18 @@ + +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/projects/scripts/adi_project.tcl +source $ad_hdl_dir/projects/scripts/adi_board.tcl + +set p_device "xc7z020clg400-1" +adi_project_create pzsdr1_ccbrk_lvds +adi_project_files pzsdr1_ccbrk_lvds [list \ + "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \ + "../common/pzsdr1_constr.xdc" \ + "../common/pzsdr1_constr_lvds.xdc" \ + "../common/ccbrk_constr.xdc" \ + "system_top.v" ] + +set_property is_enabled false [get_files *axi_gpreg_constr.xdc] +adi_project_run pzsdr1_ccbrk_lvds + + diff --git a/projects/pzsdr1/ccbrk_lvds/system_top.v b/projects/pzsdr1/ccbrk_lvds/system_top.v new file mode 100644 index 000000000..a0032c451 --- /dev/null +++ b/projects/pzsdr1/ccbrk_lvds/system_top.v @@ -0,0 +1,231 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top ( + + inout [14:0] ddr_addr, + inout [ 2:0] ddr_ba, + inout ddr_cas_n, + inout ddr_ck_n, + inout ddr_ck_p, + inout ddr_cke, + inout ddr_cs_n, + inout [ 3:0] ddr_dm, + inout [31:0] ddr_dq, + inout [ 3:0] ddr_dqs_n, + inout [ 3:0] ddr_dqs_p, + inout ddr_odt, + inout ddr_ras_n, + inout ddr_reset_n, + inout ddr_we_n, + + inout fixed_io_ddr_vrn, + inout fixed_io_ddr_vrp, + inout [53:0] fixed_io_mio, + inout fixed_io_ps_clk, + inout fixed_io_ps_porb, + inout fixed_io_ps_srstb, + + inout iic_scl, + inout iic_sda, + + inout [10:0] gpio_bd, + + input rx_clk_in_p, + input rx_clk_in_n, + input rx_frame_in_p, + input rx_frame_in_n, + input [ 5:0] rx_data_in_p, + input [ 5:0] rx_data_in_n, + output tx_clk_out_p, + output tx_clk_out_n, + output tx_frame_out_p, + output tx_frame_out_n, + output [ 5:0] tx_data_out_p, + output [ 5:0] tx_data_out_n, + + output enable, + output txnrx, + input clkout_in, + output clkout_out, + + inout gpio_clksel, + inout gpio_resetb, + inout gpio_sync, + inout gpio_en_agc, + inout [ 3:0] gpio_ctl, + inout [ 7:0] gpio_status, + + output spi_csn, + output spi_clk, + output spi_mosi, + input spi_miso, + + output [27:0] gp_out, + input [27:0] gp_in); + + + // internal signals + + wire [31:0] gp_out_s; + wire [31:0] gp_in_s; + wire [63:0] gpio_i; + wire [63:0] gpio_o; + wire [63:0] gpio_t; + + // assignments + + assign clkout_out = clkout_in; + assign gp_out[27:0] = gp_out_s[27:0]; + assign gp_in_s[31:28] = gp_out_s[31:28]; + assign gp_in_s[27: 0] = gp_in[27:0]; + + // board gpio - 31-0 + + assign gpio_i[31:11] = gpio_o[31:11]; + + ad_iobuf #(.DATA_WIDTH(11)) i_iobuf_bd ( + .dio_t (gpio_t[10:0]), + .dio_i (gpio_o[10:0]), + .dio_o (gpio_i[10:0]), + .dio_p (gpio_bd)); + + // ad9361 gpio - 63-32 + + assign gpio_i[63:52] = gpio_o[63:52]; + assign gpio_i[50:47] = gpio_o[50:47]; + + ad_iobuf #(.DATA_WIDTH(16)) i_iobuf ( + .dio_t ({gpio_t[51], gpio_t[46:32]}), + .dio_i ({gpio_o[51], gpio_o[46:32]}), + .dio_o ({gpio_i[51], gpio_i[46:32]}), + .dio_p ({ gpio_clksel, // 51:51 + gpio_resetb, // 46:46 + gpio_sync, // 45:45 + gpio_en_agc, // 44:44 + gpio_ctl, // 43:40 + gpio_status})); // 39:32 + + // instantiations + + system_wrapper i_system_wrapper ( + .ddr_addr (ddr_addr), + .ddr_ba (ddr_ba), + .ddr_cas_n (ddr_cas_n), + .ddr_ck_n (ddr_ck_n), + .ddr_ck_p (ddr_ck_p), + .ddr_cke (ddr_cke), + .ddr_cs_n (ddr_cs_n), + .ddr_dm (ddr_dm), + .ddr_dq (ddr_dq), + .ddr_dqs_n (ddr_dqs_n), + .ddr_dqs_p (ddr_dqs_p), + .ddr_odt (ddr_odt), + .ddr_ras_n (ddr_ras_n), + .ddr_reset_n (ddr_reset_n), + .ddr_we_n (ddr_we_n), + .enable (enable), + .fixed_io_ddr_vrn (fixed_io_ddr_vrn), + .fixed_io_ddr_vrp (fixed_io_ddr_vrp), + .fixed_io_mio (fixed_io_mio), + .fixed_io_ps_clk (fixed_io_ps_clk), + .fixed_io_ps_porb (fixed_io_ps_porb), + .fixed_io_ps_srstb (fixed_io_ps_srstb), + .gp_in_0 (gp_in_s[31:0]), + .gp_out_0 (gp_out_s[31:0]), + .gpio_i (gpio_i), + .gpio_o (gpio_o), + .gpio_t (gpio_t), + .iic_main_scl_io (iic_scl), + .iic_main_sda_io (iic_sda), + .otg_vbusoc (1'b0), + .ps_intr_00 (1'b0), + .ps_intr_01 (1'b0), + .ps_intr_02 (1'b0), + .ps_intr_03 (1'b0), + .ps_intr_04 (1'b0), + .ps_intr_05 (1'b0), + .ps_intr_06 (1'b0), + .ps_intr_07 (1'b0), + .ps_intr_08 (1'b0), + .ps_intr_09 (1'b0), + .ps_intr_10 (1'b0), + .ps_intr_11 (1'b0), + .ps_intr_15 (1'b0), + .rx_clk_in_n (rx_clk_in_n), + .rx_clk_in_p (rx_clk_in_p), + .rx_data_in_n (rx_data_in_n), + .rx_data_in_p (rx_data_in_p), + .rx_frame_in_n (rx_frame_in_n), + .rx_frame_in_p (rx_frame_in_p), + .spi0_clk_i (1'b0), + .spi0_clk_o (spi_clk), + .spi0_csn_0_o (spi_csn), + .spi0_csn_1_o (), + .spi0_csn_2_o (), + .spi0_csn_i (1'b1), + .spi0_sdi_i (spi_miso), + .spi0_sdo_i (1'b0), + .spi0_sdo_o (spi_mosi), + .spi1_clk_i (1'b0), + .spi1_clk_o (), + .spi1_csn_0_o (), + .spi1_csn_1_o (), + .spi1_csn_2_o (), + .spi1_csn_i (1'b1), + .spi1_sdi_i (1'b0), + .spi1_sdo_i (1'b0), + .spi1_sdo_o (), + .tdd_sync_i (1'b0), + .tdd_sync_o (), + .tdd_sync_t (), + .tx_clk_out_n (tx_clk_out_n), + .tx_clk_out_p (tx_clk_out_p), + .tx_data_out_n (tx_data_out_n), + .tx_data_out_p (tx_data_out_p), + .tx_frame_out_n (tx_frame_out_n), + .tx_frame_out_p (tx_frame_out_p), + .txnrx (txnrx), + .up_enable (gpio_o[47]), + .up_txnrx (gpio_o[48])); + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/projects/fmcomms1/vc707/Makefile b/projects/pzsdr1/ccusb_lvds/Makefile similarity index 59% rename from projects/fmcomms1/vc707/Makefile rename to projects/pzsdr1/ccusb_lvds/Makefile index 8b7b14948..04479da8d 100644 --- a/projects/fmcomms1/vc707/Makefile +++ b/projects/pzsdr1/ccusb_lvds/Makefile @@ -7,20 +7,23 @@ M_DEPS += system_top.v M_DEPS += system_project.tcl -M_DEPS += system_constr.xdc M_DEPS += system_bd.tcl -M_DEPS += ../common/fmcomms1_bd.tcl +M_DEPS += ../common/pzsdr1_constr_lvds.xdc +M_DEPS += ../common/pzsdr1_constr.xdc +M_DEPS += ../common/pzsdr1_bd.tcl +M_DEPS += ../common/ccusb_constr.xdc +M_DEPS += ../common/ccusb_bd.tcl M_DEPS += ../../scripts/adi_project.tcl M_DEPS += ../../scripts/adi_env.tcl M_DEPS += ../../scripts/adi_board.tcl -M_DEPS += ../../common/vc707/vc707_system_mig.prj -M_DEPS += ../../common/vc707/vc707_system_constr.xdc -M_DEPS += ../../common/vc707/vc707_system_bd.tcl -M_DEPS += ../../../library/common/ad_iobuf.v -M_DEPS += ../../../library/axi_ad9122/axi_ad9122.xpr -M_DEPS += ../../../library/axi_ad9643/axi_ad9643.xpr +M_DEPS += ../../../library/xilinx/common/ad_iobuf.v +M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr +M_DEPS += ../../../library/axi_usb_fx3/axi_usb_fx3.xpr +M_DEPS += ../../../library/util_clkdiv/util_clkdiv.xpr M_DEPS += ../../../library/util_cpack/util_cpack.xpr +M_DEPS += ../../../library/util_rfifo/util_rfifo.xpr +M_DEPS += ../../../library/util_tdd_sync/util_tdd_sync.xpr M_DEPS += ../../../library/util_upack/util_upack.xpr M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr @@ -38,11 +41,12 @@ M_FLIST += *.sdk M_FLIST += *.hw M_FLIST += *.sim M_FLIST += .Xil +M_FLIST += *.ip_user_files .PHONY: all lib clean clean-all -all: lib fmcomms1_vc707.sdk/system_top.hdf +all: lib pzsdr1_ccusb_lvds.sdk/system_top.hdf clean: @@ -50,24 +54,30 @@ clean: clean-all:clean - make -C ../../../library/axi_ad9122 clean - make -C ../../../library/axi_ad9643 clean + make -C ../../../library/axi_ad9361 clean make -C ../../../library/axi_dmac clean + make -C ../../../library/axi_usb_fx3 clean + make -C ../../../library/util_clkdiv clean make -C ../../../library/util_cpack clean + make -C ../../../library/util_rfifo clean + make -C ../../../library/util_tdd_sync clean make -C ../../../library/util_upack clean make -C ../../../library/util_wfifo clean -fmcomms1_vc707.sdk/system_top.hdf: $(M_DEPS) - rm -rf $(M_FLIST) - $(M_VIVADO) system_project.tcl >> fmcomms1_vc707_vivado.log 2>&1 +pzsdr1_ccusb_lvds.sdk/system_top.hdf: $(M_DEPS) + -rm -rf $(M_FLIST) + $(M_VIVADO) system_project.tcl >> pzsdr1_ccusb_lvds_vivado.log 2>&1 lib: - make -C ../../../library/axi_ad9122 - make -C ../../../library/axi_ad9643 + make -C ../../../library/axi_ad9361 make -C ../../../library/axi_dmac + make -C ../../../library/axi_usb_fx3 + make -C ../../../library/util_clkdiv make -C ../../../library/util_cpack + make -C ../../../library/util_rfifo + make -C ../../../library/util_tdd_sync make -C ../../../library/util_upack make -C ../../../library/util_wfifo diff --git a/projects/pzsdr1/ccusb_lvds/system_bd.tcl b/projects/pzsdr1/ccusb_lvds/system_bd.tcl new file mode 100644 index 000000000..4b0e97a6d --- /dev/null +++ b/projects/pzsdr1/ccusb_lvds/system_bd.tcl @@ -0,0 +1,6 @@ + +source ../common/pzsdr1_bd.tcl +source ../common/ccusb_bd.tcl + +cfg_ad9361_interface LVDS + diff --git a/projects/pzsdr1/ccusb_lvds/system_project.tcl b/projects/pzsdr1/ccusb_lvds/system_project.tcl new file mode 100644 index 000000000..5567bd97b --- /dev/null +++ b/projects/pzsdr1/ccusb_lvds/system_project.tcl @@ -0,0 +1,20 @@ + +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/projects/scripts/adi_project.tcl +source $ad_hdl_dir/projects/scripts/adi_board.tcl + +set p_device "xc7z020clg400-1" +adi_project_create pzsdr1_ccusb_lvds +adi_project_files pzsdr1_ccusb_lvds [list \ + "system_top.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \ + "../common/pzsdr1_constr.xdc" \ + "../common/pzsdr1_constr_lvds.xdc" \ + "../common/ccusb_constr.xdc" ] + +set_property PROCESSING_ORDER EARLY [get_files ../common/pzsdr1_constr.xdc] +set_property PROCESSING_ORDER LATE [get_files ../common/ccusb_constr.xdc] + +adi_project_run pzsdr1_ccusb_lvds + + diff --git a/projects/pzsdr1/ccusb_lvds/system_top.v b/projects/pzsdr1/ccusb_lvds/system_top.v new file mode 100644 index 000000000..77536b9da --- /dev/null +++ b/projects/pzsdr1/ccusb_lvds/system_top.v @@ -0,0 +1,241 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top ( + + inout [14:0] ddr_addr, + inout [ 2:0] ddr_ba, + inout ddr_cas_n, + inout ddr_ck_n, + inout ddr_ck_p, + inout ddr_cke, + inout ddr_cs_n, + inout [ 3:0] ddr_dm, + inout [31:0] ddr_dq, + inout [ 3:0] ddr_dqs_n, + inout [ 3:0] ddr_dqs_p, + inout ddr_odt, + inout ddr_ras_n, + inout ddr_reset_n, + inout ddr_we_n, + + inout fixed_io_ddr_vrn, + inout fixed_io_ddr_vrp, + inout [53:0] fixed_io_mio, + inout fixed_io_ps_clk, + inout fixed_io_ps_porb, + inout fixed_io_ps_srstb, + + inout iic_scl, + inout iic_sda, + + input rx_clk_in_p, + input rx_clk_in_n, + input rx_frame_in_p, + input rx_frame_in_n, + input [ 5:0] rx_data_in_p, + input [ 5:0] rx_data_in_n, + output tx_clk_out_p, + output tx_clk_out_n, + output tx_frame_out_p, + output tx_frame_out_n, + output [ 5:0] tx_data_out_p, + output [ 5:0] tx_data_out_n, + + output enable, + output txnrx, + input clkout_in, + + inout gpio_clksel, + inout gpio_resetb, + inout gpio_sync, + inout gpio_en_agc, + inout [ 3:0] gpio_ctl, + inout [ 7:0] gpio_status, + + input usb_fx3_uart_tx, + output usb_fx3_uart_rx, + + input [ 7:0] fifo_rdy, + + inout [31:0] data, + output [ 4:0] addr, + output pclk, + output slcs_n, + output slrd_n, + output sloe_n, + output slwr_n, + output pktend_n, + output epswitch_n, + + input flag_a, + input flag_b, + + output reset_n, + + output [ 2:0] pmode, + + output spi_csn, + output spi_clk, + output spi_mosi, + input spi_miso); + + // internal signals + + wire [63:0] gpio_i; + wire [63:0] gpio_o; + wire [63:0] gpio_t; + + // assignments + + assign pmode = 3'b111; + assign addr[4:2] = 3'b000; + + assign epswitch_n = 1'b1; + assign reset_n = 1'b1; + + // instantiations + + ad_iobuf #(.DATA_WIDTH(16)) i_iobuf ( + .dio_t ({gpio_t[51], gpio_t[46:32]}), + .dio_i ({gpio_o[51], gpio_o[46:32]}), + .dio_o ({gpio_i[51], gpio_i[46:32]}), + .dio_p ({ gpio_clksel, // 51:51 + gpio_resetb, // 46:46 + gpio_sync, // 45:45 + gpio_en_agc, // 44:44 + gpio_ctl, // 43:40 + gpio_status})); // 39:32 + + system_wrapper i_system_wrapper ( + .ddr_addr (ddr_addr), + .ddr_ba (ddr_ba), + .ddr_cas_n (ddr_cas_n), + .ddr_ck_n (ddr_ck_n), + .ddr_ck_p (ddr_ck_p), + .ddr_cke (ddr_cke), + .ddr_cs_n (ddr_cs_n), + .ddr_dm (ddr_dm), + .ddr_dq (ddr_dq), + .ddr_dqs_n (ddr_dqs_n), + .ddr_dqs_p (ddr_dqs_p), + .ddr_odt (ddr_odt), + .ddr_ras_n (ddr_ras_n), + .ddr_reset_n (ddr_reset_n), + .ddr_we_n (ddr_we_n), + .enable (enable), + .fixed_io_ddr_vrn (fixed_io_ddr_vrn), + .fixed_io_ddr_vrp (fixed_io_ddr_vrp), + .fixed_io_mio (fixed_io_mio), + .fixed_io_ps_clk (fixed_io_ps_clk), + .fixed_io_ps_porb (fixed_io_ps_porb), + .fixed_io_ps_srstb (fixed_io_ps_srstb), + .gpio_i (gpio_i), + .gpio_o (gpio_o), + .gpio_t (gpio_t), + .iic_main_scl_io (iic_scl), + .iic_main_sda_io (iic_sda), + .otg_vbusoc (1'b0), + .ps_intr_00 (1'b0), + .ps_intr_01 (1'b0), + .ps_intr_02 (1'b0), + .ps_intr_03 (1'b0), + .ps_intr_04 (1'b0), + .ps_intr_05 (1'b0), + .ps_intr_06 (1'b0), + .ps_intr_07 (1'b0), + .ps_intr_08 (1'b0), + .ps_intr_09 (1'b0), + .ps_intr_15 (1'b0), + .rx_clk_in_n (rx_clk_in_n), + .rx_clk_in_p (rx_clk_in_p), + .rx_data_in_n (rx_data_in_n), + .rx_data_in_p (rx_data_in_p), + .rx_frame_in_n (rx_frame_in_n), + .rx_frame_in_p (rx_frame_in_p), + .spi0_clk_i (1'b0), + .spi0_clk_o (spi_clk), + .spi0_csn_0_o (spi_csn), + .spi0_csn_1_o (), + .spi0_csn_2_o (), + .spi0_csn_i (1'b1), + .spi0_sdi_i (spi_miso), + .spi0_sdo_i (1'b0), + .spi0_sdo_o (spi_mosi), + .spi1_clk_i (1'b0), + .spi1_clk_o (), + .spi1_csn_0_o (), + .spi1_csn_1_o (), + .spi1_csn_2_o (), + .spi1_csn_i (1'b1), + .spi1_sdi_i (1'b0), + .spi1_sdo_i (1'b0), + .spi1_sdo_o (), + .tdd_sync_i (1'b0), + .tdd_sync_o (), + .tdd_sync_t (), + .tx_clk_out_n (tx_clk_out_n), + .tx_clk_out_p (tx_clk_out_p), + .tx_data_out_n (tx_data_out_n), + .tx_data_out_p (tx_data_out_p), + .tx_frame_out_n (tx_frame_out_n), + .tx_frame_out_p (tx_frame_out_p), + .txnrx (txnrx), + .up_enable (gpio_o[47]), + .up_txnrx (gpio_o[48]), + .usb_fx3_uart_tx(usb_fx3_uart_tx), + .usb_fx3_uart_rx(usb_fx3_uart_rx), + .dma_rdy(), + .dma_wmk(), + .fifo_rdy(fifo_rdy[3:0]), + .pclk(pclk), + .data(data), + .addr(addr[1:0]), + .slcs_n(slcs_n), + .slrd_n(slrd_n), + .sloe_n(sloe_n), + .slwr_n(slwr_n), + // .epswitch_n(epswitch_n), + .pktend_n(pktend_n) + ); + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/projects/pzsdr1/common/ccbox_bd.tcl b/projects/pzsdr1/common/ccbox_bd.tcl new file mode 100644 index 000000000..0b2c89ea0 --- /dev/null +++ b/projects/pzsdr1/common/ccbox_bd.tcl @@ -0,0 +1,46 @@ + +# unused + +ad_connect sys_ps7/ENET1_GMII_RX_CLK GND +ad_connect sys_ps7/ENET1_GMII_TX_CLK GND + +# GPS-UART + +set_property CONFIG.PCW_UART0_PERIPHERAL_ENABLE {1} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_UART0_UART0_IO {MIO 14 .. 15} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_USE_DMA0 1 [get_bd_cells sys_ps7] +set_property CONFIG.PCW_USE_DMA1 1 [get_bd_cells sys_ps7] + +# i2s + +create_bd_port -dir O -type clk i2s_mclk +create_bd_intf_port -mode Master -vlnv analog.com:interface:i2s_rtl:1.0 i2s + +set sys_audio_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.3 sys_audio_clkgen] +set_property -dict [list CONFIG.PRIM_IN_FREQ {200.000}] $sys_audio_clkgen +set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {12.288}] $sys_audio_clkgen +set_property -dict [list CONFIG.USE_LOCKED {false}] $sys_audio_clkgen +set_property -dict [list CONFIG.USE_RESET {true} CONFIG.RESET_TYPE {ACTIVE_LOW}] $sys_audio_clkgen + +set axi_i2s_adi [create_bd_cell -type ip -vlnv analog.com:user:axi_i2s_adi:1.0 axi_i2s_adi] +set_property -dict [list CONFIG.DMA_TYPE {1}] $axi_i2s_adi +set_property -dict [list CONFIG.S_AXI_ADDRESS_WIDTH {16}] $axi_i2s_adi + +ad_connect sys_200m_clk sys_audio_clkgen/clk_in1 +ad_connect sys_cpu_resetn sys_audio_clkgen/resetn +ad_connect sys_cpu_clk axi_i2s_adi/DMA_REQ_RX_ACLK +ad_connect sys_cpu_clk axi_i2s_adi/DMA_REQ_TX_ACLK +ad_connect sys_cpu_clk sys_ps7/DMA0_ACLK +ad_connect sys_cpu_clk sys_ps7/DMA1_ACLK +ad_connect sys_cpu_resetn axi_i2s_adi/DMA_REQ_RX_RSTN +ad_connect sys_cpu_resetn axi_i2s_adi/DMA_REQ_TX_RSTN +ad_connect sys_ps7/DMA0_REQ axi_i2s_adi/DMA_REQ_TX +ad_connect sys_ps7/DMA0_ACK axi_i2s_adi/DMA_ACK_TX +ad_connect sys_ps7/DMA1_REQ axi_i2s_adi/DMA_REQ_RX +ad_connect sys_ps7/DMA1_ACK axi_i2s_adi/DMA_ACK_RX +ad_connect sys_audio_clkgen/clk_out1 i2s_mclk +ad_connect sys_audio_clkgen/clk_out1 axi_i2s_adi/DATA_CLK_I +ad_connect i2s axi_i2s_adi/I2S + +ad_cpu_interconnect 0x77600000 axi_i2s_adi + diff --git a/projects/pzsdr1/common/ccbox_constr.xdc b/projects/pzsdr1/common/ccbox_constr.xdc new file mode 100644 index 000000000..a21d62099 --- /dev/null +++ b/projects/pzsdr1/common/ccbox_constr.xdc @@ -0,0 +1,72 @@ + +## constraints (ccbox.a) +## rf-gpio + +set_property -dict {PACKAGE_PIN Y16 IOSTANDARD LVCMOS25} [get_ports gpio_rfpwr_enable] ; ## U1,Y16,IO_L07_34_JX4_P,JX4,35,RF_GPIO4_BANK34 +set_property -dict {PACKAGE_PIN U12 IOSTANDARD LVCMOS25} [get_ports gpio_rf0] ; ## U1,U12,IO_L02_34_JX4_N,JX4,22,RF_GPIO0_BANK34 +set_property -dict {PACKAGE_PIN U13 IOSTANDARD LVCMOS25} [get_ports gpio_rf1] ; ## U1,U13,IO_L03_34_JX4_P,JX4,25,RF_GPIO1_BANK34 +set_property -dict {PACKAGE_PIN T15 IOSTANDARD LVCMOS25} [get_ports gpio_rf2] ; ## U1,T15,IO_L05_34_JX4_N,JX4,33,RF_GPIO2_BANK34 +set_property -dict {PACKAGE_PIN R14 IOSTANDARD LVCMOS25} [get_ports gpio_rf3] ; ## U1,R14,IO_L06_34_JX4_N,JX4,34,RF_GPIO3_BANK34 +set_property -dict {PACKAGE_PIN W14 IOSTANDARD LVCMOS25} [get_ports gpio_rf4] ; ## U1,W14,IO_L08_34_JX4_P,JX4,36,RF_GPIO5_BANK34 + +## push-button + +set_property -dict {PACKAGE_PIN P14 IOSTANDARD LVCMOS25} [get_ports ltc2955_kill_n] ; ## U1,P14,IO_L06_34_JX4_P,JX4,32,LTC2955_KILL_N +set_property -dict {PACKAGE_PIN T14 IOSTANDARD LVCMOS25} [get_ports ltc2955_int_n] ; ## U1,T14,IO_L05_34_JX4_P,JX4,31,LTC2955_INT_N + +## oled + +set_property -dict {PACKAGE_PIN V5 IOSTANDARD LVCMOS25} [get_ports oled_csn] ; ## U1,V5,IO_L06_13_JX2_P,JX2,18,OLED_CS# +set_property -dict {PACKAGE_PIN V7 IOSTANDARD LVCMOS25} [get_ports oled_clk] ; ## U1,V7,IO_L11_SRCC_13_JX2_N,JX2,37,OLED_SCL +set_property -dict {PACKAGE_PIN T9 IOSTANDARD LVCMOS25} [get_ports oled_mosi] ; ## U1,T9,IO_L12_MRCC_13_JX2_P,JX2,36,OLED_SDI +set_property -dict {PACKAGE_PIN U7 IOSTANDARD LVCMOS25} [get_ports oled_rst] ; ## U1,U7,IO_L11_SRCC_13_JX2_P,JX2,35,OLED_/RES +set_property -dict {PACKAGE_PIN U10 IOSTANDARD LVCMOS25} [get_ports oled_dc] ; ## U1,U10,IO_L12_MRCC_13_JX2_N,JX2,38,OLED_D/C + +## adp5061 + +set_property -dict {PACKAGE_PIN T11 IOSTANDARD LVCMOS25} [get_ports adp5061_io[0]] ; ## U1,T11,IO_L01_34_JX4_P,JX4,19,ADP5061_IO1 +set_property -dict {PACKAGE_PIN T10 IOSTANDARD LVCMOS25} [get_ports adp5061_io[1]] ; ## U1,T10,IO_L01_34_JX4_N,JX4,21,ADP5061_IO2 +set_property -dict {PACKAGE_PIN T12 IOSTANDARD LVCMOS25} [get_ports adp5061_io[2]] ; ## U1,T12,IO_L02_34_JX4_P,JX4,20,ADP5061_IO3 + +## GPS (DATA-UART) +## U1,C5,PS_MIO14_500_JX4,JX4,93,GPS_TXD1_1V8 +## U1,C8,PS_MIO15_500_JX4,JX4,85,GPS_RXD1_1V8 + +set_property -dict {PACKAGE_PIN U5 IOSTANDARD LVCMOS25} [get_ports gps_reset] ; ## U1,U5,IO_L19_13_JX2_N,JX2,63,GPS_RESET +set_property -dict {PACKAGE_PIN Y12 IOSTANDARD LVCMOS25} [get_ports gps_force_on] ; ## U1,Y12,IO_L20_13_JX2_P,JX2,62,GPS_FORCE_ON +set_property -dict {PACKAGE_PIN Y13 IOSTANDARD LVCMOS25} [get_ports gps_standby] ; ## U1,Y13,IO_L20_13_JX2_N,JX2,64,GPS_STANDBY +set_property -dict {PACKAGE_PIN T5 IOSTANDARD LVCMOS25} [get_ports gps_pps] ; ## U1,T5,IO_L19_13_JX2_P,JX2,61,GPS_PPS + +## imu + +set_property -dict {PACKAGE_PIN W10 IOSTANDARD LVCMOS25} [get_ports imu_csn] ; ## U1,W10,IO_L16_13_JX2_P,JX2,48,IMU_CS_N +set_property -dict {PACKAGE_PIN W9 IOSTANDARD LVCMOS25} [get_ports imu_clk] ; ## U1,W9,IO_L16_13_JX2_N,JX2,50,IMU_SCLK +set_property -dict {PACKAGE_PIN U9 IOSTANDARD LVCMOS25} [get_ports imu_mosi] ; ## U1,U9,IO_L17_13_JX2_P,JX2,53,IMU_DIN +set_property -dict {PACKAGE_PIN Y11 IOSTANDARD LVCMOS25} [get_ports imu_miso] ; ## U1,Y11,IO_L18_13_JX2_N,JX2,56,IMU_DOUT +set_property -dict {PACKAGE_PIN W8 IOSTANDARD LVCMOS25} [get_ports imu_rstn] ; ## U1,W8,IO_L15_13_JX2_N,JX2,49,IMU_RST_N +set_property -dict {PACKAGE_PIN W11 IOSTANDARD LVCMOS25} [get_ports imu_sync] ; ## U1,W11,IO_L18_13_JX2_P,JX2,54,IMU_SYNC +set_property -dict {PACKAGE_PIN U8 IOSTANDARD LVCMOS25} [get_ports imu_ready] ; ## U1,U8,IO_L17_13_JX2_N,JX2,55,IMU_DR + +## audio + +set_property -dict {PACKAGE_PIN Y6 IOSTANDARD LVCMOS25} [get_ports i2s_bclk] ; ## U1,Y6,IO_L13_MRCC_13_JX2_N,JX2,43,AUD_BCLK +set_property -dict {PACKAGE_PIN Y9 IOSTANDARD LVCMOS25} [get_ports i2s_lrclk] ; ## U1,Y9,IO_L14_SRCC_13_JX2_P,JX2,42,AUD_LRCLK +set_property -dict {PACKAGE_PIN Y7 IOSTANDARD LVCMOS25} [get_ports i2s_mclk] ; ## U1,Y7,IO_L13_MRCC_13_JX2_P,JX2,41,AUD_MCLK +set_property -dict {PACKAGE_PIN Y8 IOSTANDARD LVCMOS25} [get_ports i2s_sdata_in] ; ## U1,Y8,IO_L14_SRCC_13_JX2_N,JX2,44,AUD_SDATA_IN +set_property -dict {PACKAGE_PIN V8 IOSTANDARD LVCMOS25} [get_ports i2s_sdata_out] ; ## U1,V8,IO_L15_13_JX2_P,JX2,47,AUD_SDATA_OUT + +set_property -dict {PACKAGE_PIN U17 IOSTANDARD LVCMOS25} [get_ports mic_present_n] ; ## U1,U17,IO_L09_34_JX4_N,JX4,43,MIC_PRESENT_N_1V8 +set_property -dict {PACKAGE_PIN Y17 IOSTANDARD LVCMOS25} [get_ports ts3a227_int_n] ; ## U1,Y17,IO_L07_34_JX4_N,JX4,37,TS3A227_INT_N + +## switch-led + +set_property -dict {PACKAGE_PIN Y14 IOSTANDARD LVCMOS25} [get_ports switch_led_r] ; ## U1,Y14,IO_L08_34_JX4_N,JX4,38,SWITCH_LED_R +set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVCMOS25} [get_ports switch_led_g] ; ## U1,T16,IO_L09_34_JX4_P,JX4,41,SWITCH_LED_G +set_property -dict {PACKAGE_PIN V15 IOSTANDARD LVCMOS25} [get_ports switch_led_b] ; ## U1,V15,IO_L10_34_JX4_P,JX4,42,SWITCH_LED_B + +## power source + +set_property -dict {PACKAGE_PIN V13 IOSTANDARD LVCMOS25} [get_ports pss_valid_n[0]] ; ## U1,V13,IO_L03_34_JX4_N,JX4,27,PSS_VALID1_N +set_property -dict {PACKAGE_PIN V12 IOSTANDARD LVCMOS25} [get_ports pss_valid_n[1]] ; ## U1,V12,IO_L04_34_JX4_P,JX4,26,PSS_VALID2_N +set_property -dict {PACKAGE_PIN W13 IOSTANDARD LVCMOS25} [get_ports pss_valid_n[2]] ; ## U1,W13,IO_L04_34_JX4_N,JX4,28,PSS_VALID3_N + diff --git a/projects/pzsdr1/common/ccbrk_bd.tcl b/projects/pzsdr1/common/ccbrk_bd.tcl new file mode 100644 index 000000000..940a3869f --- /dev/null +++ b/projects/pzsdr1/common/ccbrk_bd.tcl @@ -0,0 +1,19 @@ + +# lbfmc + +ad_connect sys_ps7/ENET1_GMII_RX_CLK GND +ad_connect sys_ps7/ENET1_GMII_TX_CLK GND + +# un-used io (regular) + +set axi_gpreg [create_bd_cell -type ip -vlnv analog.com:user:axi_gpreg:1.0 axi_gpreg] +set_property -dict [list CONFIG.NUM_OF_CLK_MONS {0}] $axi_gpreg +set_property -dict [list CONFIG.NUM_OF_IO {1}] $axi_gpreg + +create_bd_port -dir I -from 31 -to 0 gp_in_0 +create_bd_port -dir O -from 31 -to 0 gp_out_0 + +ad_connect gp_in_0 axi_gpreg/up_gp_in_0 +ad_connect gp_out_0 axi_gpreg/up_gp_out_0 +ad_cpu_interconnect 0x41200000 axi_gpreg + diff --git a/projects/pzsdr1/common/ccbrk_constr.xdc b/projects/pzsdr1/common/ccbrk_constr.xdc new file mode 100644 index 000000000..950509512 --- /dev/null +++ b/projects/pzsdr1/common/ccbrk_constr.xdc @@ -0,0 +1,95 @@ + +## constraints (ccbrk.c + ccbrk_lb.a) +## ad9361 clkout forward + +set_property -dict {PACKAGE_PIN W16 IOSTANDARD LVCMOS25} [get_ports clkout_out] ; ## (lb: none) U1,W16,IO_L18_34_JX4_N,JX4,70,IO_L18_34_JX4_N,P7,32 + +## push-buttons- led- dip-switches- loopbacks- (ps7 gpio) + +set_property -dict {PACKAGE_PIN Y14 IOSTANDARD LVCMOS25} [get_ports gpio_bd[0]] ; ## (lb: none) U1,Y14,IO_L08_34_JX4_N,JX4,38,PB_GPIO_1,P6,19 +set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVCMOS25} [get_ports gpio_bd[1]] ; ## (lb: none) U1,T16,IO_L09_34_JX4_P,JX4,41,PB_GPIO_2,P6,26 +set_property -dict {PACKAGE_PIN U17 IOSTANDARD LVCMOS25} [get_ports gpio_bd[2]] ; ## (lb: none) U1,U17,IO_L09_34_JX4_N,JX4,43,PB_GPIO_3,P6,28 +set_property -dict {PACKAGE_PIN Y19 IOSTANDARD LVCMOS25} [get_ports gpio_bd[3]] ; ## (lb: none) U1,Y19,IO_L17_34_JX4_N,JX4,69,LED_GPIO_0,P7,16 + +## orphans- io- (ps7 gpio) + +set_property -dict {PACKAGE_PIN V5 IOSTANDARD LVCMOS25} [get_ports gpio_bd[4]] ; ## (lb: none) U1,V5,IO_L06_13_JX2_P,JX2,18,IO_L06_13_JX2_P +set_property -dict {PACKAGE_PIN V11 IOSTANDARD LVCMOS25} [get_ports gpio_bd[5]] ; ## (lb: none) U1,V11,IO_L21_13_JX2_P,JX2,67,IO_L21_13_JX2_P,P2,52 +set_property -dict {PACKAGE_PIN V10 IOSTANDARD LVCMOS25} [get_ports gpio_bd[6]] ; ## (lb: none) U1,V10,IO_L21_13_JX2_N,JX2,69,IO_L21_13_JX2_N,P2,54 +set_property -dict {PACKAGE_PIN V16 IOSTANDARD LVCMOS25} [get_ports gpio_bd[7]] ; ## (lb: none) U1,V16,IO_L18_34_JX4_P,JX4,68,IO_L18_34_JX4_P,P7,30 + +## ps7- fixed io- to- fpga regular io (ps7 gpio) + +set_property -dict {PACKAGE_PIN V15 IOSTANDARD LVCMOS25} [get_ports gpio_bd[8]] ; ## U1,V15,IO_L10_34_JX4_P,JX4,42,IO_L10_34_JX4_P,P6,25 (U1,E9,PS_MIO10_500_JX4,JX4,87,PS_MIO10_500_JX4,P6,23) +set_property -dict {PACKAGE_PIN Y18 IOSTANDARD LVCMOS25} [get_ports gpio_bd[9]] ; ## U1,Y18,IO_L17_34_JX4_P,JX4,67,IO_L17_34_JX4_P,P6,9 (U1,B9,PS_MIO51_501_JX4,JX4,100,PS_MIO51_501_JX4,P6,11) +set_property -dict {PACKAGE_PIN Y17 IOSTANDARD LVCMOS25} [get_ports gpio_bd[10]] ; ## U1,Y17,IO_L07_34_JX4_N,JX4,37,IO_L07_34_JX4_N,P6,20 (U1,C8,PS_MIO15_500_JX4,JX4,85,PS_MIO15_500_JX4,P6,21) + +## ps7- fixed io- to- ps7- fixed io (reference only) +## U1,B14,PS_MIO47_501_JX4,JX4,94,PS_MIO47_501_JX4,P7,24 == U1,D16,PS_MIO46_501_JX4,JX4,92,PS_MIO46_501_JX4,P7,22 + +## ps7- fixed io- orphans (reference only) +## U1,E6,PS_MIO00_500_JX4,JX4,97,PS_MIO00_500_JX4,P5,21 +## U1,E8,PS_MIO13_500_JX4,JX4,91,PS_MIO13_500_JX4,P5,9 +## U1,C5,PS_MIO14_500_JX4,JX4,93,PS_MIO14_500_JX4,P5,11 +## U1,D9,PS_MIO12_500_JX4,JX4,86,PS_MIO12_500_JX4,P7,10 +## U1,C6,PS_MIO11_500_JX4,JX4,88,PS_MIO11_500_JX4,P7,12 + +## fpga- regular io + +set_property -dict {PACKAGE_PIN U7 IOSTANDARD LVCMOS25} [get_ports gp_out[0]] ; ## U1,U7,IO_L11_SRCC_13_JX2_P,JX2,35,IO_L11_SRCC_13_JX2_P,P2,28 +set_property -dict {PACKAGE_PIN T9 IOSTANDARD LVCMOS25} [get_ports gp_in[0]] ; ## U1,T9,IO_L12_MRCC_13_JX2_P,JX2,36,IO_L12_MRCC_13_JX2_P,P2,27 +set_property -dict {PACKAGE_PIN V7 IOSTANDARD LVCMOS25} [get_ports gp_out[1]] ; ## U1,V7,IO_L11_SRCC_13_JX2_N,JX2,37,IO_L11_SRCC_13_JX2_N,P2,30 +set_property -dict {PACKAGE_PIN U10 IOSTANDARD LVCMOS25} [get_ports gp_in[1]] ; ## U1,U10,IO_L12_MRCC_13_JX2_N,JX2,38,IO_L12_MRCC_13_JX2_N,P2,29 +set_property -dict {PACKAGE_PIN Y7 IOSTANDARD LVCMOS25} [get_ports gp_out[2]] ; ## U1,Y7,IO_L13_MRCC_13_JX2_P,JX2,41,IO_L13_MRCC_13_JX2_P,P2,32 +set_property -dict {PACKAGE_PIN Y9 IOSTANDARD LVCMOS25} [get_ports gp_in[2]] ; ## U1,Y9,IO_L14_SRCC_13_JX2_P,JX2,42,IO_L14_SRCC_13_JX2_P,P2,31 +set_property -dict {PACKAGE_PIN Y6 IOSTANDARD LVCMOS25} [get_ports gp_out[3]] ; ## U1,Y6,IO_L13_MRCC_13_JX2_N,JX2,43,IO_L13_MRCC_13_JX2_N,P2,34 +set_property -dict {PACKAGE_PIN Y8 IOSTANDARD LVCMOS25} [get_ports gp_in[3]] ; ## U1,Y8,IO_L14_SRCC_13_JX2_N,JX2,44,IO_L14_SRCC_13_JX2_N,P2,33 +set_property -dict {PACKAGE_PIN V8 IOSTANDARD LVCMOS25} [get_ports gp_out[4]] ; ## U1,V8,IO_L15_13_JX2_P,JX2,47,IO_L15_13_JX2_P,P2,38 +set_property -dict {PACKAGE_PIN W10 IOSTANDARD LVCMOS25} [get_ports gp_in[4]] ; ## U1,W10,IO_L16_13_JX2_P,JX2,48,IO_L16_13_JX2_P,P2,37 +set_property -dict {PACKAGE_PIN W8 IOSTANDARD LVCMOS25} [get_ports gp_out[5]] ; ## U1,W8,IO_L15_13_JX2_N,JX2,49,IO_L15_13_JX2_N,P2,40 +set_property -dict {PACKAGE_PIN W9 IOSTANDARD LVCMOS25} [get_ports gp_in[5]] ; ## U1,W9,IO_L16_13_JX2_N,JX2,50,IO_L16_13_JX2_N,P2,39 +set_property -dict {PACKAGE_PIN U9 IOSTANDARD LVCMOS25} [get_ports gp_out[6]] ; ## U1,U9,IO_L17_13_JX2_P,JX2,53,IO_L17_13_JX2_P,P2,42 +set_property -dict {PACKAGE_PIN W11 IOSTANDARD LVCMOS25} [get_ports gp_in[6]] ; ## U1,W11,IO_L18_13_JX2_P,JX2,54,IO_L18_13_JX2_P,P2,41 +set_property -dict {PACKAGE_PIN U8 IOSTANDARD LVCMOS25} [get_ports gp_out[7]] ; ## U1,U8,IO_L17_13_JX2_N,JX2,55,IO_L17_13_JX2_N,P2,44 +set_property -dict {PACKAGE_PIN Y11 IOSTANDARD LVCMOS25} [get_ports gp_in[7]] ; ## U1,Y11,IO_L18_13_JX2_N,JX2,56,IO_L18_13_JX2_N,P2,43 +set_property -dict {PACKAGE_PIN T5 IOSTANDARD LVCMOS25} [get_ports gp_out[8]] ; ## U1,T5,IO_L19_13_JX2_P,JX2,61,IO_L19_13_JX2_P,P2,46 +set_property -dict {PACKAGE_PIN Y12 IOSTANDARD LVCMOS25} [get_ports gp_in[8]] ; ## U1,Y12,IO_L20_13_JX2_P,JX2,62,IO_L20_13_JX2_P,P2,45 +set_property -dict {PACKAGE_PIN U5 IOSTANDARD LVCMOS25} [get_ports gp_out[9]] ; ## U1,U5,IO_L19_13_JX2_N,JX2,63,IO_L19_13_JX2_N,P2,48 +set_property -dict {PACKAGE_PIN Y13 IOSTANDARD LVCMOS25} [get_ports gp_in[9]] ; ## U1,Y13,IO_L20_13_JX2_N,JX2,64,IO_L20_13_JX2_N,P2,47 +set_property -dict {PACKAGE_PIN W15 IOSTANDARD LVCMOS25} [get_ports gp_out[10]] ; ## U1,W15,IO_L10_34_JX4_N,JX4,44,IO_L10_34_JX4_N,P6,27 +set_property -dict {PACKAGE_PIN T19 IOSTANDARD LVCMOS25} [get_ports gp_in[10]] ; ## U1,T19,IO_25_34_JX4,JX4,64,IO_25_34_JX4,P5,23 +set_property -dict {PACKAGE_PIN T11 IOSTANDARD LVCMOS25} [get_ports gp_out[11]] ; ## U1,T11,IO_L01_34_JX4_P,JX4,19,IO_L01_34_JX4_P,P6,2 +set_property -dict {PACKAGE_PIN T12 IOSTANDARD LVCMOS25} [get_ports gp_in[11]] ; ## U1,T12,IO_L02_34_JX4_P,JX4,20,IO_L02_34_JX4_P,P6,1 +set_property -dict {PACKAGE_PIN T10 IOSTANDARD LVCMOS25} [get_ports gp_out[12]] ; ## U1,T10,IO_L01_34_JX4_N,JX4,21,IO_L01_34_JX4_N,P6,4 +set_property -dict {PACKAGE_PIN U12 IOSTANDARD LVCMOS25} [get_ports gp_in[12]] ; ## U1,U12,IO_L02_34_JX4_N,JX4,22,IO_L02_34_JX4_N,P6,3 +set_property -dict {PACKAGE_PIN U13 IOSTANDARD LVCMOS25} [get_ports gp_out[13]] ; ## U1,U13,IO_L03_34_JX4_P,JX4,25,IO_L03_34_JX4_P,P6,6 +set_property -dict {PACKAGE_PIN V12 IOSTANDARD LVCMOS25} [get_ports gp_in[13]] ; ## U1,V12,IO_L04_34_JX4_P,JX4,26,IO_L04_34_JX4_P,P6,5 +set_property -dict {PACKAGE_PIN V13 IOSTANDARD LVCMOS25} [get_ports gp_out[14]] ; ## U1,V13,IO_L03_34_JX4_N,JX4,27,IO_L03_34_JX4_N,P6,8 +set_property -dict {PACKAGE_PIN W13 IOSTANDARD LVCMOS25} [get_ports gp_in[14]] ; ## U1,W13,IO_L04_34_JX4_N,JX4,28,IO_L04_34_JX4_N,P6,7 +set_property -dict {PACKAGE_PIN T14 IOSTANDARD LVCMOS25} [get_ports gp_out[15]] ; ## U1,T14,IO_L05_34_JX4_P,JX4,31,IO_L05_34_JX4_P,P6,14 +set_property -dict {PACKAGE_PIN P14 IOSTANDARD LVCMOS25} [get_ports gp_in[15]] ; ## U1,P14,IO_L06_34_JX4_P,JX4,32,IO_L06_34_JX4_P,P6,13 +set_property -dict {PACKAGE_PIN T15 IOSTANDARD LVCMOS25} [get_ports gp_out[16]] ; ## U1,T15,IO_L05_34_JX4_N,JX4,33,IO_L05_34_JX4_N,P6,16 +set_property -dict {PACKAGE_PIN R14 IOSTANDARD LVCMOS25} [get_ports gp_in[16]] ; ## U1,R14,IO_L06_34_JX4_N,JX4,34,IO_L06_34_JX4_N,P6,15 +set_property -dict {PACKAGE_PIN Y16 IOSTANDARD LVCMOS25} [get_ports gp_out[17]] ; ## U1,Y16,IO_L07_34_JX4_P,JX4,35,IO_L07_34_JX4_P,P6,18 +set_property -dict {PACKAGE_PIN W14 IOSTANDARD LVCMOS25} [get_ports gp_in[17]] ; ## U1,W14,IO_L08_34_JX4_P,JX4,36,IO_L08_34_JX4_P,P6,17 +set_property -dict {PACKAGE_PIN U14 IOSTANDARD LVCMOS25} [get_ports gp_out[18]] ; ## U1,U14,IO_L11_SRCC_34_JX4_P,JX4,45,IO_L11_SRCC_34_JX4_P,P6,30 +set_property -dict {PACKAGE_PIN U18 IOSTANDARD LVCMOS25} [get_ports gp_in[18]] ; ## U1,U18,IO_L12_MRCC_34_JX4_P,JX4,46,IO_L12_MRCC_34_JX4_P,P6,29 +set_property -dict {PACKAGE_PIN U15 IOSTANDARD LVCMOS25} [get_ports gp_out[19]] ; ## U1,U15,IO_L11_SRCC_34_JX4_N,JX4,47,IO_L11_SRCC_34_JX4_N,P6,32 +set_property -dict {PACKAGE_PIN U19 IOSTANDARD LVCMOS25} [get_ports gp_in[19]] ; ## U1,U19,IO_L12_MRCC_34_JX4_N,JX4,48,IO_L12_MRCC_34_JX4_N,P6,31 +set_property -dict {PACKAGE_PIN N18 IOSTANDARD LVCMOS25} [get_ports gp_out[20]] ; ## U1,N18,IO_L13_MRCC_34_JX4_P,JX4,51,IO_L13_MRCC_34_JX4_P,P7,2 +set_property -dict {PACKAGE_PIN N20 IOSTANDARD LVCMOS25} [get_ports gp_in[20]] ; ## U1,N20,IO_L14_SRCC_34_JX4_P,JX4,52,IO_L14_SRCC_34_JX4_P,P7,1 +set_property -dict {PACKAGE_PIN P19 IOSTANDARD LVCMOS25} [get_ports gp_out[21]] ; ## U1,P19,IO_L13_MRCC_34_JX4_N,JX4,53,IO_L13_MRCC_34_JX4_N,P7,4 +set_property -dict {PACKAGE_PIN P20 IOSTANDARD LVCMOS25} [get_ports gp_in[21]] ; ## U1,P20,IO_L14_SRCC_34_JX4_N,JX4,54,IO_L14_SRCC_34_JX4_N,P7,3 +set_property -dict {PACKAGE_PIN T20 IOSTANDARD LVCMOS25} [get_ports gp_out[22]] ; ## U1,T20,IO_L15_34_JX4_P,JX4,57,IO_L15_34_JX4_P,P7,6 +set_property -dict {PACKAGE_PIN V20 IOSTANDARD LVCMOS25} [get_ports gp_in[22]] ; ## U1,V20,IO_L16_34_JX4_P,JX4,58,IO_L16_34_JX4_P,P7,5 +set_property -dict {PACKAGE_PIN U20 IOSTANDARD LVCMOS25} [get_ports gp_out[23]] ; ## U1,U20,IO_L15_34_JX4_N,JX4,59,IO_L15_34_JX4_N,P7,8 +set_property -dict {PACKAGE_PIN W20 IOSTANDARD LVCMOS25} [get_ports gp_in[23]] ; ## U1,W20,IO_L16_34_JX4_N,JX4,60,IO_L16_34_JX4_N,P7,7 +set_property -dict {PACKAGE_PIN R16 IOSTANDARD LVCMOS25} [get_ports gp_out[24]] ; ## U1,R16,IO_L19_34_JX4_P,JX4,73,IO_L19_34_JX4_P,P7,18 +set_property -dict {PACKAGE_PIN T17 IOSTANDARD LVCMOS25} [get_ports gp_in[24]] ; ## U1,T17,IO_L20_34_JX4_P,JX4,74,IO_L20_34_JX4_P,P7,17 +set_property -dict {PACKAGE_PIN R17 IOSTANDARD LVCMOS25} [get_ports gp_out[25]] ; ## U1,R17,IO_L19_34_JX4_N,JX4,75,IO_L19_34_JX4_N,P7,20 +set_property -dict {PACKAGE_PIN R18 IOSTANDARD LVCMOS25} [get_ports gp_in[25]] ; ## U1,R18,IO_L20_34_JX4_N,JX4,76,IO_L20_34_JX4_N,P7,19 +set_property -dict {PACKAGE_PIN V17 IOSTANDARD LVCMOS25} [get_ports gp_out[26]] ; ## U1,V17,IO_L21_34_JX4_P,JX4,77,IO_L21_34_JX4_P,P7,26 +set_property -dict {PACKAGE_PIN W18 IOSTANDARD LVCMOS25} [get_ports gp_in[26]] ; ## U1,W18,IO_L22_34_JX4_P,JX4,78,IO_L22_34_JX4_P,P7,25 +set_property -dict {PACKAGE_PIN V18 IOSTANDARD LVCMOS25} [get_ports gp_out[27]] ; ## U1,V18,IO_L21_34_JX4_N,JX4,79,IO_L21_34_JX4_N,P7,28 +set_property -dict {PACKAGE_PIN W19 IOSTANDARD LVCMOS25} [get_ports gp_in[27]] ; ## U1,W19,IO_L22_34_JX4_N,JX4,80,IO_L22_34_JX4_N,P7,27 + diff --git a/projects/pzsdr1/common/ccusb_bd.tcl b/projects/pzsdr1/common/ccusb_bd.tcl new file mode 100644 index 000000000..c656a53dd --- /dev/null +++ b/projects/pzsdr1/common/ccusb_bd.tcl @@ -0,0 +1,74 @@ + +ad_connect sys_ps7/ENET1_GMII_RX_CLK GND +ad_connect sys_ps7/ENET1_GMII_TX_CLK GND + +create_bd_port -dir I usb_fx3_uart_tx +create_bd_port -dir O usb_fx3_uart_rx + +create_bd_port -dir I dma_rdy +create_bd_port -dir I dma_wmk +create_bd_port -dir I -from 3 -to 0 fifo_rdy +create_bd_port -dir O pclk +create_bd_port -dir IO -from 31 -to 0 data +create_bd_port -dir O -from 1 -to 0 addr +create_bd_port -dir O slcs_n +create_bd_port -dir O slrd_n +create_bd_port -dir O sloe_n +create_bd_port -dir O slwr_n +create_bd_port -dir O pktend_n +create_bd_port -dir O epswitch_n + +set axi_uart [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_uartlite:2.0 axi_uart] +set_property -dict [list CONFIG.C_BAUDRATE {115200}] $axi_uart + +set axi_usb_fx3 [create_bd_cell -type ip -vlnv analog.com:user:axi_usb_fx3:1.0 axi_usb_fx3] + +set axi_usb_fx3_dma [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_usb_fx3_dma] +set_property -dict [list CONFIG.c_sg_include_stscntrl_strm {0}] $axi_usb_fx3_dma +set_property -dict [list CONFIG.c_mm2s_burst_size {256}] $axi_usb_fx3_dma +set_property -dict [list CONFIG.c_s2mm_burst_size {256}] $axi_usb_fx3_dma +set_property -dict [list CONFIG.c_sg_length_width {16}] $axi_usb_fx3_dma + +set usb_fx3_rx_axis_fifo [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:1.1 usb_fx3_rx_axis_fifo ] + +ad_connect axi_usb_fx3/s_axis axi_usb_fx3_dma/M_AXIS_MM2S + +ad_connect sys_cpu_clk usb_fx3_rx_axis_fifo/s_axis_aclk +ad_connect sys_cpu_resetn usb_fx3_rx_axis_fifo/s_axis_aresetn + +ad_connect axi_usb_fx3/m_axis usb_fx3_rx_axis_fifo/S_AXIS +ad_connect axi_usb_fx3_dma/S_AXIS_S2MM usb_fx3_rx_axis_fifo/M_AXIS + +ad_connect axi_uart/rx usb_fx3_uart_tx +ad_connect axi_uart/tx usb_fx3_uart_rx + +ad_connect sys_cpu_clk axi_usb_fx3/s_axi_aclk +ad_connect sys_cpu_resetn axi_usb_fx3/s_axi_aresetn + +ad_connect axi_usb_fx3/dma_rdy dma_rdy +ad_connect axi_usb_fx3/dma_wmk dma_wmk +ad_connect axi_usb_fx3/fifo_rdy fifo_rdy +ad_connect axi_usb_fx3/pclk pclk +ad_connect axi_usb_fx3/data data +ad_connect axi_usb_fx3/addr addr +ad_connect axi_usb_fx3/slcs_n slcs_n +ad_connect axi_usb_fx3/slrd_n slrd_n +ad_connect axi_usb_fx3/sloe_n sloe_n +ad_connect axi_usb_fx3/slwr_n slwr_n +ad_connect axi_usb_fx3/pktend_n pktend_n +ad_connect axi_usb_fx3/epswitch_n epswitch_n + + +ad_cpu_interrupt ps-13 mb-12 axi_usb_fx3/irq +ad_cpu_interrupt ps-12 mb-13 axi_usb_fx3_dma/mm2s_introut +ad_cpu_interrupt ps-11 mb-14 axi_usb_fx3_dma/s2mm_introut +ad_cpu_interrupt ps-10 mb-15 axi_uart/interrupt + +ad_cpu_interconnect 0x50000000 axi_usb_fx3 +ad_cpu_interconnect 0x40400000 axi_usb_fx3_dma +ad_cpu_interconnect 0x40600000 axi_uart + +ad_mem_hp3_interconnect sys_cpu_clk sys_ps7/S_AXI_HP3 +ad_mem_hp3_interconnect sys_cpu_clk axi_usb_fx3_dma/M_AXI_SG +ad_mem_hp3_interconnect sys_cpu_clk axi_usb_fx3_dma/M_AXI_MM2S +ad_mem_hp3_interconnect sys_cpu_clk axi_usb_fx3_dma/M_AXI_S2MM diff --git a/projects/pzsdr1/common/ccusb_constr.xdc b/projects/pzsdr1/common/ccusb_constr.xdc new file mode 100644 index 000000000..fb06ba3ec --- /dev/null +++ b/projects/pzsdr1/common/ccusb_constr.xdc @@ -0,0 +1,75 @@ +# Default constraints have LVCMOS25, overwite it +#set_property -dict {IOSTANDARD LVCMOS18} [get_ports iic_scl] ; +#set_property -dict {IOSTANDARD LVCMOS18} [get_ports iic_sda] ; + +# USB_FX3 + +set_property -dict {PACKAGE_PIN T11 IOSTANDARD LVCMOS25} [get_ports data[30]] ; +set_property -dict {PACKAGE_PIN T10 IOSTANDARD LVCMOS25} [get_ports data[31]] ; +set_property -dict {PACKAGE_PIN U13 IOSTANDARD LVCMOS25} [get_ports data[24]] ; +set_property -dict {PACKAGE_PIN V13 IOSTANDARD LVCMOS25} [get_ports data[27]] ; +set_property -dict {PACKAGE_PIN T14 IOSTANDARD LVCMOS25} [get_ports data[26]] ; +set_property -dict {PACKAGE_PIN T15 IOSTANDARD LVCMOS25} [get_ports data[21]] ; +set_property -dict {PACKAGE_PIN Y16 IOSTANDARD LVCMOS25} [get_ports data[18]] ; +set_property -dict {PACKAGE_PIN Y17 IOSTANDARD LVCMOS25} [get_ports data[19]] ; +set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVCMOS25} [get_ports data[23]] ; +set_property -dict {PACKAGE_PIN U17 IOSTANDARD LVCMOS25} [get_ports data[20]] ; +set_property -dict {PACKAGE_PIN U15 IOSTANDARD LVCMOS25} [get_ports data[2]] ; +set_property -dict {PACKAGE_PIN N18 IOSTANDARD LVCMOS25} [get_ports data[14]] ; +set_property -dict {PACKAGE_PIN P19 IOSTANDARD LVCMOS25} [get_ports data[13]] ; +set_property -dict {PACKAGE_PIN T20 IOSTANDARD LVCMOS25} [get_ports data[9]] ; +set_property -dict {PACKAGE_PIN U20 IOSTANDARD LVCMOS25} [get_ports data[12]] ; +set_property -dict {PACKAGE_PIN Y18 IOSTANDARD LVCMOS25} [get_ports data[8]] ; +set_property -dict {PACKAGE_PIN Y19 IOSTANDARD LVCMOS25} [get_ports data[7]] ; +set_property -dict {PACKAGE_PIN R16 IOSTANDARD LVCMOS25} [get_ports data[3]] ; +set_property -dict {PACKAGE_PIN R17 IOSTANDARD LVCMOS25} [get_ports data[0]] ; +set_property -dict {PACKAGE_PIN V17 IOSTANDARD LVCMOS25} [get_ports data[4]] ; +set_property -dict {PACKAGE_PIN V18 IOSTANDARD LVCMOS25} [get_ports data[5]] ; +set_property -dict {PACKAGE_PIN T12 IOSTANDARD LVCMOS25} [get_ports data[28]] ; +set_property -dict {PACKAGE_PIN V12 IOSTANDARD LVCMOS25} [get_ports data[29]] ; +set_property -dict {PACKAGE_PIN P14 IOSTANDARD LVCMOS25} [get_ports data[25]] ; +set_property -dict {PACKAGE_PIN W14 IOSTANDARD LVCMOS25} [get_ports data[22]] ; +set_property -dict {PACKAGE_PIN V15 IOSTANDARD LVCMOS25} [get_ports data[16]] ; +set_property -dict {PACKAGE_PIN U18 IOSTANDARD LVCMOS25} [get_ports data[17]] ; +set_property -dict {PACKAGE_PIN N20 IOSTANDARD LVCMOS25} [get_ports data[15]] ; +set_property -dict {PACKAGE_PIN V20 IOSTANDARD LVCMOS25} [get_ports data[11]] ; +set_property -dict {PACKAGE_PIN V16 IOSTANDARD LVCMOS25} [get_ports data[10]] ; +set_property -dict {PACKAGE_PIN T17 IOSTANDARD LVCMOS25} [get_ports data[6]] ; +set_property -dict {PACKAGE_PIN W18 IOSTANDARD LVCMOS25} [get_ports data[1]] ; + +set_property -dict {PACKAGE_PIN U14 IOSTANDARD LVCMOS25} [get_ports pclk] ; + +set_property -dict {PACKAGE_PIN W16 IOSTANDARD LVCMOS25} [get_ports addr[0]] ; +set_property -dict {PACKAGE_PIN W19 IOSTANDARD LVCMOS25} [get_ports addr[1]] ; +set_property -dict {PACKAGE_PIN U8 IOSTANDARD LVCMOS25} [get_ports addr[2]] ; +set_property -dict {PACKAGE_PIN Y7 IOSTANDARD LVCMOS25} [get_ports addr[3]] ; +set_property -dict {PACKAGE_PIN Y8 IOSTANDARD LVCMOS25} [get_ports addr[4]] ; + +set_property -dict {PACKAGE_PIN Y6 IOSTANDARD LVCMOS25} [get_ports slcs_n] ; +set_property -dict {PACKAGE_PIN W8 IOSTANDARD LVCMOS25} [get_ports slwr_n] ; +set_property -dict {PACKAGE_PIN V7 IOSTANDARD LVCMOS25} [get_ports sloe_n] ; +set_property -dict {PACKAGE_PIN U7 IOSTANDARD LVCMOS25} [get_ports slrd_n] ; +set_property -dict {PACKAGE_PIN W11 IOSTANDARD LVCMOS25} [get_ports pktend_n] ; + +set_property -dict {PACKAGE_PIN R14 IOSTANDARD LVCMOS25} [get_ports usb_fx3_uart_tx] ; +set_property -dict {PACKAGE_PIN U10 IOSTANDARD LVCMOS25} [get_ports usb_fx3_uart_rx] ; + +set_property -dict {PACKAGE_PIN V8 IOSTANDARD LVCMOS25} [get_ports fifo_rdy[0]] ; +set_property -dict {PACKAGE_PIN Y9 IOSTANDARD LVCMOS25} [get_ports fifo_rdy[1]] ; +set_property -dict {PACKAGE_PIN U12 IOSTANDARD LVCMOS25} [get_ports fifo_rdy[2]] ; +set_property -dict {PACKAGE_PIN W13 IOSTANDARD LVCMOS25} [get_ports fifo_rdy[3]] ; +set_property -dict {PACKAGE_PIN Y14 IOSTANDARD LVCMOS25} [get_ports fifo_rdy[4]] ; +set_property -dict {PACKAGE_PIN W15 IOSTANDARD LVCMOS25} [get_ports fifo_rdy[5]] ; +set_property -dict {PACKAGE_PIN U19 IOSTANDARD LVCMOS25} [get_ports fifo_rdy[6]] ; +set_property -dict {PACKAGE_PIN P20 IOSTANDARD LVCMOS25} [get_ports fifo_rdy[7]] ; + +set_property -dict {PACKAGE_PIN W10 IOSTANDARD LVCMOS25} [get_ports flag_a] ; +set_property -dict {PACKAGE_PIN W9 IOSTANDARD LVCMOS25} [get_ports flag_b] ; + + +set_property -dict {PACKAGE_PIN W20 IOSTANDARD LVCMOS25} [get_ports pmode[0]] ; +set_property -dict {PACKAGE_PIN T19 IOSTANDARD LVCMOS25} [get_ports pmode[1]] ; +set_property -dict {PACKAGE_PIN R18 IOSTANDARD LVCMOS25} [get_ports pmode[2]] ; + +set_property -dict {PACKAGE_PIN T9 IOSTANDARD LVCMOS25} [get_ports reset_n] ; +set_property -dict {PACKAGE_PIN U9 IOSTANDARD LVCMOS25} [get_ports epswitch_n] ; diff --git a/projects/pzsdr1/common/pzsdr1_bd.tcl b/projects/pzsdr1/common/pzsdr1_bd.tcl new file mode 100644 index 000000000..e99c558b4 --- /dev/null +++ b/projects/pzsdr1/common/pzsdr1_bd.tcl @@ -0,0 +1,464 @@ + +# create board design +# default ports + +create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr +create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 iic_main +create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 fixed_io + +create_bd_port -dir O spi0_csn_2_o +create_bd_port -dir O spi0_csn_1_o +create_bd_port -dir O spi0_csn_0_o +create_bd_port -dir I spi0_csn_i +create_bd_port -dir I spi0_clk_i +create_bd_port -dir O spi0_clk_o +create_bd_port -dir I spi0_sdo_i +create_bd_port -dir O spi0_sdo_o +create_bd_port -dir I spi0_sdi_i + +create_bd_port -dir O spi1_csn_2_o +create_bd_port -dir O spi1_csn_1_o +create_bd_port -dir O spi1_csn_0_o +create_bd_port -dir I spi1_csn_i +create_bd_port -dir I spi1_clk_i +create_bd_port -dir O spi1_clk_o +create_bd_port -dir I spi1_sdo_i +create_bd_port -dir O spi1_sdo_o +create_bd_port -dir I spi1_sdi_i + +create_bd_port -dir I -from 63 -to 0 gpio_i +create_bd_port -dir O -from 63 -to 0 gpio_o +create_bd_port -dir O -from 63 -to 0 gpio_t + +# otg + +set otg_vbusoc [create_bd_port -dir I otg_vbusoc] + +# interrupts + +create_bd_port -dir I -type intr ps_intr_00 +create_bd_port -dir I -type intr ps_intr_01 +create_bd_port -dir I -type intr ps_intr_02 +create_bd_port -dir I -type intr ps_intr_03 +create_bd_port -dir I -type intr ps_intr_04 +create_bd_port -dir I -type intr ps_intr_05 +create_bd_port -dir I -type intr ps_intr_06 +create_bd_port -dir I -type intr ps_intr_07 +create_bd_port -dir I -type intr ps_intr_08 +create_bd_port -dir I -type intr ps_intr_09 +create_bd_port -dir I -type intr ps_intr_10 +create_bd_port -dir I -type intr ps_intr_11 +create_bd_port -dir I -type intr ps_intr_12 +create_bd_port -dir I -type intr ps_intr_13 +create_bd_port -dir I -type intr ps_intr_15 + +# instance: sys_ps7 + +set sys_ps7 [create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 sys_ps7] +set_property -dict [list CONFIG.PCW_PRESET_BANK0_VOLTAGE {LVCMOS 1.8V}] $sys_ps7 +set_property -dict [list CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 1.8V}] $sys_ps7 +set_property -dict [list CONFIG.PCW_PACKAGE_NAME {fbg676}] $sys_ps7 +set_property -dict [list CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_ENET0_PERIPHERAL_ENABLE {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_ENET0_ENET0_IO {MIO 16 .. 27}] $sys_ps7 +set_property -dict [list CONFIG.PCW_ENET0_GRP_MDIO_ENABLE {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_ENET1_PERIPHERAL_ENABLE {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_ENET_RESET_SELECT {Separate reset pins}] $sys_ps7 +set_property -dict [list CONFIG.PCW_ENET0_RESET_ENABLE {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_ENET0_RESET_IO {MIO 8}] $sys_ps7 +set_property -dict [list CONFIG.PCW_ENET1_RESET_ENABLE {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_ENET1_RESET_IO {MIO 51}] $sys_ps7 +set_property -dict [list CONFIG.PCW_SD0_PERIPHERAL_ENABLE {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_SD0_GRP_CD_ENABLE {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_SD0_GRP_CD_IO {MIO 50}] $sys_ps7 +set_property -dict [list CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ {50}] $sys_ps7 +set_property -dict [list CONFIG.PCW_UART1_PERIPHERAL_ENABLE {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_USB0_PERIPHERAL_ENABLE {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_USB0_RESET_ENABLE {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_USB0_RESET_IO {MIO 7}] $sys_ps7 +set_property -dict [list CONFIG.PCW_QSPI_PERIPHERAL_ENABLE {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_UIPARAM_DDR_PARTNO {MT41K256M16 RE-125}] $sys_ps7 +set_property -dict [list CONFIG.PCW_UIPARAM_DDR_BUS_WIDTH {32 Bit}] $sys_ps7 +set_property -dict [list CONFIG.PCW_UIPARAM_DDR_USE_INTERNAL_VREF {0}] $sys_ps7 +set_property -dict [list CONFIG.PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_UIPARAM_DDR_TRAIN_READ_GATE {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_UIPARAM_DDR_TRAIN_DATA_EYE {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 {0.110}] $sys_ps7 +set_property -dict [list CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 {0.095}] $sys_ps7 +set_property -dict [list CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 {0.249}] $sys_ps7 +set_property -dict [list CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 {0.249}] $sys_ps7 +set_property -dict [list CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0 {0.202}] $sys_ps7 +set_property -dict [list CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1 {0.217}] $sys_ps7 +set_property -dict [list CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2 {0.216}] $sys_ps7 +set_property -dict [list CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3 {0.217}] $sys_ps7 +set_property -dict [list CONFIG.PCW_TTC0_PERIPHERAL_ENABLE {0}] $sys_ps7 +set_property -dict [list CONFIG.PCW_EN_CLK1_PORT {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_EN_RST1_PORT {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_EN_CLK2_PORT {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_EN_RST2_PORT {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100.0}] $sys_ps7 +set_property -dict [list CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ {200.0}] $sys_ps7 +set_property -dict [list CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {200.0}] $sys_ps7 +set_property -dict [list CONFIG.PCW_USE_FABRIC_INTERRUPT {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_IRQ_F2P_INTR {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_IO {64}] $sys_ps7 +set_property -dict [list CONFIG.PCW_IRQ_F2P_MODE {REVERSE}] $sys_ps7 +set_property -dict [list CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_SPI0_SPI0_IO {EMIO}] $sys_ps7 +set_property -dict [list CONFIG.PCW_SPI1_PERIPHERAL_ENABLE {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_SPI1_SPI1_IO {EMIO}] $sys_ps7 + +set axi_iic_main [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_iic:2.0 axi_iic_main] +set_property -dict [list CONFIG.USE_BOARD_FLOW {true}] $axi_iic_main +set_property -dict [list CONFIG.IIC_BOARD_INTERFACE {Custom}] $axi_iic_main + +set sys_concat_intc [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 sys_concat_intc] +set_property -dict [list CONFIG.NUM_PORTS {16}] $sys_concat_intc + +set sys_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 sys_rstgen] +set_property -dict [list CONFIG.C_EXT_RST_WIDTH {1}] $sys_rstgen + +set sys_logic_inv [create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 sys_logic_inv] +set_property -dict [list CONFIG.C_SIZE {1}] $sys_logic_inv +set_property -dict [list CONFIG.C_OPERATION {not}] $sys_logic_inv + +# system reset/clock definitions + +ad_connect sys_cpu_clk sys_ps7/FCLK_CLK0 +ad_connect sys_200m_clk sys_ps7/FCLK_CLK1 +ad_connect sys_cpu_reset sys_rstgen/peripheral_reset +ad_connect sys_cpu_resetn sys_rstgen/peripheral_aresetn +ad_connect sys_cpu_clk sys_rstgen/slowest_sync_clk +ad_connect sys_rstgen/ext_reset_in sys_ps7/FCLK_RESET0_N + +# interface connections + +ad_connect ddr sys_ps7/DDR +ad_connect gpio_i sys_ps7/GPIO_I +ad_connect gpio_o sys_ps7/GPIO_O +ad_connect gpio_t sys_ps7/GPIO_T +ad_connect fixed_io sys_ps7/FIXED_IO +ad_connect iic_main axi_iic_main/iic +ad_connect sys_logic_inv/Res sys_ps7/USB0_VBUS_PWRFAULT +ad_connect sys_logic_inv/Op1 otg_vbusoc + +# spi connections + +ad_connect spi0_csn_2_o sys_ps7/SPI0_SS2_O +ad_connect spi0_csn_1_o sys_ps7/SPI0_SS1_O +ad_connect spi0_csn_0_o sys_ps7/SPI0_SS_O +ad_connect spi0_csn_i sys_ps7/SPI0_SS_I +ad_connect spi0_clk_i sys_ps7/SPI0_SCLK_I +ad_connect spi0_clk_o sys_ps7/SPI0_SCLK_O +ad_connect spi0_sdo_i sys_ps7/SPI0_MOSI_I +ad_connect spi0_sdo_o sys_ps7/SPI0_MOSI_O +ad_connect spi0_sdi_i sys_ps7/SPI0_MISO_I + +ad_connect spi1_csn_2_o sys_ps7/SPI1_SS2_O +ad_connect spi1_csn_1_o sys_ps7/SPI1_SS1_O +ad_connect spi1_csn_0_o sys_ps7/SPI1_SS_O +ad_connect spi1_csn_i sys_ps7/SPI1_SS_I +ad_connect spi1_clk_i sys_ps7/SPI1_SCLK_I +ad_connect spi1_clk_o sys_ps7/SPI1_SCLK_O +ad_connect spi1_sdo_i sys_ps7/SPI1_MOSI_I +ad_connect spi1_sdo_o sys_ps7/SPI1_MOSI_O +ad_connect spi1_sdi_i sys_ps7/SPI1_MISO_I + +# interrupts + +ad_connect sys_concat_intc/dout sys_ps7/IRQ_F2P +ad_connect sys_concat_intc/In15 ps_intr_15 +ad_connect sys_concat_intc/In14 axi_iic_main/iic2intc_irpt +ad_connect sys_concat_intc/In13 ps_intr_13 +ad_connect sys_concat_intc/In12 ps_intr_12 +ad_connect sys_concat_intc/In11 ps_intr_11 +ad_connect sys_concat_intc/In10 ps_intr_10 +ad_connect sys_concat_intc/In9 ps_intr_09 +ad_connect sys_concat_intc/In8 ps_intr_08 +ad_connect sys_concat_intc/In7 ps_intr_07 +ad_connect sys_concat_intc/In6 ps_intr_06 +ad_connect sys_concat_intc/In5 ps_intr_05 +ad_connect sys_concat_intc/In4 ps_intr_04 +ad_connect sys_concat_intc/In3 ps_intr_03 +ad_connect sys_concat_intc/In2 ps_intr_02 +ad_connect sys_concat_intc/In1 ps_intr_01 +ad_connect sys_concat_intc/In0 ps_intr_00 + +# interconnects + +ad_cpu_interconnect 0x41600000 axi_iic_main + +# ad9361 + +create_bd_port -dir O enable +create_bd_port -dir O txnrx +create_bd_port -dir I up_enable +create_bd_port -dir I up_txnrx +create_bd_port -dir O tdd_sync_o +create_bd_port -dir I tdd_sync_i +create_bd_port -dir O tdd_sync_t + +# ad9361 core + +set axi_ad9361 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9361:1.0 axi_ad9361] +set_property -dict [list CONFIG.ID {0}] $axi_ad9361 +set_property -dict [list CONFIG.DAC_IODELAY_ENABLE {0}] $axi_ad9361 + +set axi_ad9361_dac_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9361_dac_dma] +set_property -dict [list CONFIG.DMA_TYPE_SRC {0}] $axi_ad9361_dac_dma +set_property -dict [list CONFIG.DMA_TYPE_DEST {2}] $axi_ad9361_dac_dma +set_property -dict [list CONFIG.CYCLIC {1}] $axi_ad9361_dac_dma +set_property -dict [list CONFIG.AXI_SLICE_SRC {0}] $axi_ad9361_dac_dma +set_property -dict [list CONFIG.AXI_SLICE_DEST {1}] $axi_ad9361_dac_dma +set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9361_dac_dma +set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $axi_ad9361_dac_dma + +set util_ad9361_dac_upack [create_bd_cell -type ip -vlnv analog.com:user:util_upack:1.0 util_ad9361_dac_upack] +set_property -dict [list CONFIG.NUM_OF_CHANNELS {4}] $util_ad9361_dac_upack +set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {16}] $util_ad9361_dac_upack + +set axi_ad9361_adc_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9361_adc_dma] +set_property -dict [list CONFIG.DMA_TYPE_SRC {2}] $axi_ad9361_adc_dma +set_property -dict [list CONFIG.DMA_TYPE_DEST {0}] $axi_ad9361_adc_dma +set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad9361_adc_dma +set_property -dict [list CONFIG.SYNC_TRANSFER_START {1}] $axi_ad9361_adc_dma +set_property -dict [list CONFIG.AXI_SLICE_SRC {0}] $axi_ad9361_adc_dma +set_property -dict [list CONFIG.AXI_SLICE_DEST {0}] $axi_ad9361_adc_dma +set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9361_adc_dma +set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {64}] $axi_ad9361_adc_dma + +set util_ad9361_adc_pack [create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 util_ad9361_adc_pack] +set_property -dict [list CONFIG.NUM_OF_CHANNELS {4}] $util_ad9361_adc_pack +set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {16}] $util_ad9361_adc_pack + +set util_ad9361_adc_fifo [create_bd_cell -type ip -vlnv analog.com:user:util_wfifo:1.0 util_ad9361_adc_fifo] +set_property -dict [list CONFIG.NUM_OF_CHANNELS {4}] $util_ad9361_adc_fifo +set_property -dict [list CONFIG.DIN_ADDRESS_WIDTH {4}] $util_ad9361_adc_fifo +set_property -dict [list CONFIG.DIN_DATA_WIDTH {16}] $util_ad9361_adc_fifo +set_property -dict [list CONFIG.DOUT_DATA_WIDTH {16}] $util_ad9361_adc_fifo + +set util_ad9361_tdd_sync [create_bd_cell -type ip -vlnv analog.com:user:util_tdd_sync:1.0 util_ad9361_tdd_sync] +set_property -dict [list CONFIG.TDD_SYNC_PERIOD {10000000}] $util_ad9361_tdd_sync + +set clkdiv [ create_bd_cell -type ip -vlnv analog.com:user:util_clkdiv:1.0 clkdiv ] + +set clkdiv_reset [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 clkdiv_reset] + +set dac_fifo [create_bd_cell -type ip -vlnv analog.com:user:util_rfifo:1.0 dac_fifo] +set_property -dict [list CONFIG.DIN_DATA_WIDTH {16}] $dac_fifo +set_property -dict [list CONFIG.DOUT_DATA_WIDTH {16}] $dac_fifo +set_property -dict [list CONFIG.DIN_ADDRESS_WIDTH {4}] $dac_fifo + +set clkdiv_sel_logic [create_bd_cell -type ip -vlnv xilinx.com:ip:util_reduced_logic:2.0 clkdiv_sel_logic] +set_property -dict [list CONFIG.C_SIZE {2}] $clkdiv_sel_logic + +set concat_logic [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 concat_logic] +set_property -dict [list CONFIG.NUM_PORTS {2}] $concat_logic + +# connections + +ad_connect sys_200m_clk axi_ad9361/delay_clk +ad_connect axi_ad9361_clk axi_ad9361/l_clk +ad_connect axi_ad9361_clk axi_ad9361/clk +ad_connect enable axi_ad9361/enable +ad_connect txnrx axi_ad9361/txnrx +ad_connect up_enable axi_ad9361/up_enable +ad_connect up_txnrx axi_ad9361/up_txnrx +ad_connect axi_ad9361_clk util_ad9361_adc_fifo/din_clk +ad_connect axi_ad9361/rst util_ad9361_adc_fifo/din_rst +ad_connect axi_ad9361_clk clkdiv/clk +ad_connect clkdiv/clk_out axi_ad9361_adc_dma/fifo_wr_clk +ad_connect clkdiv/clk_out util_ad9361_adc_fifo/dout_clk +ad_connect clkdiv/clk_out util_ad9361_adc_pack/adc_clk +ad_connect clkdiv_reset/ext_reset_in sys_rstgen/peripheral_aresetn +ad_connect clkdiv_reset/slowest_sync_clk clkdiv/clk_out +ad_connect util_ad9361_adc_pack/adc_rst clkdiv_reset/peripheral_reset +ad_connect util_ad9361_adc_fifo/dout_rstn clkdiv_reset/peripheral_aresetn +ad_connect axi_ad9361/adc_enable_i0 util_ad9361_adc_fifo/din_enable_0 +ad_connect axi_ad9361/adc_valid_i0 util_ad9361_adc_fifo/din_valid_0 +ad_connect axi_ad9361/adc_data_i0 util_ad9361_adc_fifo/din_data_0 +ad_connect axi_ad9361/adc_enable_q0 util_ad9361_adc_fifo/din_enable_1 +ad_connect axi_ad9361/adc_valid_q0 util_ad9361_adc_fifo/din_valid_1 +ad_connect axi_ad9361/adc_data_q0 util_ad9361_adc_fifo/din_data_1 +ad_connect axi_ad9361/adc_enable_i1 util_ad9361_adc_fifo/din_enable_2 +ad_connect axi_ad9361/adc_valid_i1 util_ad9361_adc_fifo/din_valid_2 +ad_connect axi_ad9361/adc_data_i1 util_ad9361_adc_fifo/din_data_2 +ad_connect axi_ad9361/adc_enable_q1 util_ad9361_adc_fifo/din_enable_3 +ad_connect axi_ad9361/adc_valid_q1 util_ad9361_adc_fifo/din_valid_3 +ad_connect axi_ad9361/adc_data_q1 util_ad9361_adc_fifo/din_data_3 +ad_connect util_ad9361_adc_fifo/dout_enable_0 util_ad9361_adc_pack/adc_enable_0 +ad_connect util_ad9361_adc_fifo/dout_valid_0 util_ad9361_adc_pack/adc_valid_0 +ad_connect util_ad9361_adc_fifo/dout_data_0 util_ad9361_adc_pack/adc_data_0 +ad_connect util_ad9361_adc_fifo/dout_enable_1 util_ad9361_adc_pack/adc_enable_1 +ad_connect util_ad9361_adc_fifo/dout_valid_1 util_ad9361_adc_pack/adc_valid_1 +ad_connect util_ad9361_adc_fifo/dout_data_1 util_ad9361_adc_pack/adc_data_1 +ad_connect util_ad9361_adc_fifo/dout_enable_2 util_ad9361_adc_pack/adc_enable_2 +ad_connect util_ad9361_adc_fifo/dout_valid_2 util_ad9361_adc_pack/adc_valid_2 +ad_connect util_ad9361_adc_fifo/dout_data_2 util_ad9361_adc_pack/adc_data_2 +ad_connect util_ad9361_adc_fifo/dout_enable_3 util_ad9361_adc_pack/adc_enable_3 +ad_connect util_ad9361_adc_fifo/dout_valid_3 util_ad9361_adc_pack/adc_valid_3 +ad_connect util_ad9361_adc_fifo/dout_data_3 util_ad9361_adc_pack/adc_data_3 +ad_connect util_ad9361_adc_pack/adc_valid axi_ad9361_adc_dma/fifo_wr_en +ad_connect util_ad9361_adc_pack/adc_sync axi_ad9361_adc_dma/fifo_wr_sync +ad_connect util_ad9361_adc_pack/adc_data axi_ad9361_adc_dma/fifo_wr_din +ad_connect axi_ad9361_adc_dma/fifo_wr_overflow util_ad9361_adc_fifo/dout_ovf +ad_connect util_ad9361_adc_fifo/din_ovf axi_ad9361/adc_dovf +ad_connect axi_ad9361/adc_r1_mode concat_logic/In0 +ad_connect axi_ad9361/dac_r1_mode concat_logic/In1 +ad_connect concat_logic/dout clkdiv_sel_logic/Op1 +ad_connect clkdiv/clk_sel clkdiv_sel_logic/Res +ad_connect util_ad9361_dac_upack/dac_valid axi_ad9361_dac_dma/fifo_rd_en +ad_connect util_ad9361_dac_upack/dac_data axi_ad9361_dac_dma/fifo_rd_dout +ad_connect clkdiv/clk_out axi_ad9361_dac_dma/fifo_rd_clk +ad_connect axi_ad9361/dac_dunf dac_fifo/dout_unf +ad_connect dac_fifo/din_clk clkdiv/clk_out +ad_connect dac_fifo/din_rstn clkdiv_reset/peripheral_aresetn +ad_connect axi_ad9361_clk dac_fifo/dout_clk +ad_connect dac_fifo/dout_rst axi_ad9361/rst +ad_connect util_ad9361_dac_upack/dac_clk clkdiv/clk_out +ad_connect dac_fifo/din_enable_0 util_ad9361_dac_upack/dac_enable_0 +ad_connect dac_fifo/din_valid_0 util_ad9361_dac_upack/dac_valid_0 +ad_connect dac_fifo/din_data_0 util_ad9361_dac_upack/dac_data_0 +ad_connect dac_fifo/din_enable_1 util_ad9361_dac_upack/dac_enable_1 +ad_connect dac_fifo/din_valid_1 util_ad9361_dac_upack/dac_valid_1 +ad_connect dac_fifo/din_data_1 util_ad9361_dac_upack/dac_data_1 +ad_connect dac_fifo/din_enable_2 util_ad9361_dac_upack/dac_enable_2 +ad_connect dac_fifo/din_valid_2 util_ad9361_dac_upack/dac_valid_2 +ad_connect dac_fifo/din_data_2 util_ad9361_dac_upack/dac_data_2 +ad_connect dac_fifo/din_enable_3 util_ad9361_dac_upack/dac_enable_3 +ad_connect dac_fifo/din_valid_3 util_ad9361_dac_upack/dac_valid_3 +ad_connect dac_fifo/din_data_3 util_ad9361_dac_upack/dac_data_3 +ad_connect axi_ad9361/dac_enable_i0 dac_fifo/dout_enable_0 +ad_connect axi_ad9361/dac_valid_i0 dac_fifo/dout_valid_0 +ad_connect axi_ad9361/dac_data_i0 dac_fifo/dout_data_0 +ad_connect axi_ad9361/dac_enable_q0 dac_fifo/dout_enable_1 +ad_connect axi_ad9361/dac_valid_q0 dac_fifo/dout_valid_1 +ad_connect axi_ad9361/dac_data_q0 dac_fifo/dout_data_1 +ad_connect axi_ad9361/dac_enable_i1 dac_fifo/dout_enable_2 +ad_connect axi_ad9361/dac_valid_i1 dac_fifo/dout_valid_2 +ad_connect axi_ad9361/dac_data_i1 dac_fifo/dout_data_2 +ad_connect axi_ad9361/dac_enable_q1 dac_fifo/dout_enable_3 +ad_connect axi_ad9361/dac_valid_q1 dac_fifo/dout_valid_3 +ad_connect axi_ad9361/dac_data_q1 dac_fifo/dout_data_3 +ad_connect sys_cpu_clk util_ad9361_tdd_sync/clk +ad_connect sys_cpu_resetn util_ad9361_tdd_sync/rstn +ad_connect util_ad9361_tdd_sync/sync_out axi_ad9361/tdd_sync +ad_connect util_ad9361_tdd_sync/sync_mode axi_ad9361/tdd_sync_cntr +ad_connect tdd_sync_t axi_ad9361/tdd_sync_cntr +ad_connect tdd_sync_o util_ad9361_tdd_sync/sync_out +ad_connect tdd_sync_i util_ad9361_tdd_sync/sync_in + +# interconnects + +ad_cpu_interconnect 0x79020000 axi_ad9361 +ad_cpu_interconnect 0x7C400000 axi_ad9361_adc_dma +ad_cpu_interconnect 0x7C420000 axi_ad9361_dac_dma +ad_mem_hp1_interconnect sys_cpu_clk sys_ps7/S_AXI_HP1 +ad_mem_hp1_interconnect sys_cpu_clk axi_ad9361_adc_dma/m_dest_axi +ad_mem_hp2_interconnect sys_cpu_clk sys_ps7/S_AXI_HP2 +ad_mem_hp2_interconnect sys_cpu_clk axi_ad9361_dac_dma/m_src_axi +ad_connect sys_cpu_resetn axi_ad9361_adc_dma/m_dest_axi_aresetn +ad_connect sys_cpu_resetn axi_ad9361_dac_dma/m_src_axi_aresetn + +# interrupts + +ad_cpu_interrupt ps-13 mb-13 axi_ad9361_adc_dma/irq +ad_cpu_interrupt ps-12 mb-12 axi_ad9361_dac_dma/irq + +## customization of core to disable data path logic (less resources) +## interface type - 1R1T (1) or 2R2T (0) (default is 2R2T) +## 2R2T supports 1R1T as a run time option. +## 1R1T allows core to run at a lower rate (1/2 of 2R2T) + +set_property CONFIG.MODE_1R1T 1 [get_bd_cells axi_ad9361] + +## interface type - CMOS (1) or LVDS (0) (default is LVDS) +## CMOS allows core to run at a lower rate (1/2 of LVDS) + +set_property CONFIG.CMOS_OR_LVDS_N 0 [get_bd_cells axi_ad9361] + +## data-path disable (global control)- allows removal of DSP functions within the core. +## also removes the corresponding AXI control interface registers + +set_property CONFIG.ADC_DATAPATH_DISABLE 0 [get_bd_cells axi_ad9361] +set_property CONFIG.DAC_DATAPATH_DISABLE 0 [get_bd_cells axi_ad9361] + +## data-path disable (individual control)- effective ONLY if DATAPATH_DISABLE is 0x0. + +set_property CONFIG.ADC_DATAFORMAT_DISABLE 0 [get_bd_cells axi_ad9361] +set_property CONFIG.ADC_DCFILTER_DISABLE 0 [get_bd_cells axi_ad9361] +set_property CONFIG.ADC_IQCORRECTION_DISABLE 0 [get_bd_cells axi_ad9361] +set_property CONFIG.ADC_USERPORTS_DISABLE 0 [get_bd_cells axi_ad9361] + +set_property CONFIG.DAC_DDS_DISABLE 0 [get_bd_cells axi_ad9361] +set_property CONFIG.DAC_IQCORRECTION_DISABLE 0 [get_bd_cells axi_ad9361] +set_property CONFIG.DAC_USERPORTS_DISABLE 0 [get_bd_cells axi_ad9361] + +## tdd-disable (control is moved exclusively to GPIO) + +set_property CONFIG.TDD_DISABLE 0 [get_bd_cells axi_ad9361] + +## lvds/cmos configuration +## core digital interface -- cmos (1) or lvds (0) + +proc cfg_ad9361_interface {cmos_or_lvds} { + + if {$cmos_or_lvds eq "LVDS"} { + + set_property CONFIG.CMOS_OR_LVDS_N 0 [get_bd_cells axi_ad9361] + + create_bd_port -dir I rx_clk_in_p + create_bd_port -dir I rx_clk_in_n + create_bd_port -dir I rx_frame_in_p + create_bd_port -dir I rx_frame_in_n + create_bd_port -dir I -from 5 -to 0 rx_data_in_p + create_bd_port -dir I -from 5 -to 0 rx_data_in_n + + create_bd_port -dir O tx_clk_out_p + create_bd_port -dir O tx_clk_out_n + create_bd_port -dir O tx_frame_out_p + create_bd_port -dir O tx_frame_out_n + create_bd_port -dir O -from 5 -to 0 tx_data_out_p + create_bd_port -dir O -from 5 -to 0 tx_data_out_n + + ad_connect rx_clk_in_p axi_ad9361/rx_clk_in_p + ad_connect rx_clk_in_n axi_ad9361/rx_clk_in_n + ad_connect rx_frame_in_p axi_ad9361/rx_frame_in_p + ad_connect rx_frame_in_n axi_ad9361/rx_frame_in_n + ad_connect rx_data_in_p axi_ad9361/rx_data_in_p + ad_connect rx_data_in_n axi_ad9361/rx_data_in_n + ad_connect tx_clk_out_p axi_ad9361/tx_clk_out_p + ad_connect tx_clk_out_n axi_ad9361/tx_clk_out_n + ad_connect tx_frame_out_p axi_ad9361/tx_frame_out_p + ad_connect tx_frame_out_n axi_ad9361/tx_frame_out_n + ad_connect tx_data_out_p axi_ad9361/tx_data_out_p + ad_connect tx_data_out_n axi_ad9361/tx_data_out_n + + return + } + + if {$cmos_or_lvds eq "CMOS"} { + + set_property CONFIG.CMOS_OR_LVDS_N 1 [get_bd_cells axi_ad9361] + + create_bd_port -dir I rx_clk_in + create_bd_port -dir I rx_frame_in + create_bd_port -dir I -from 11 -to 0 rx_data_in + create_bd_port -dir O tx_clk_out + create_bd_port -dir O tx_frame_out + create_bd_port -dir O -from 11 -to 0 tx_data_out + + ad_connect rx_clk_in axi_ad9361/rx_clk_in + ad_connect rx_frame_in axi_ad9361/rx_frame_in + ad_connect rx_data_in axi_ad9361/rx_data_in + ad_connect tx_clk_out axi_ad9361/tx_clk_out + ad_connect tx_frame_out axi_ad9361/tx_frame_out + ad_connect tx_data_out axi_ad9361/tx_data_out + + return + } + +} + + diff --git a/projects/pzsdr1/common/pzsdr1_constr.xdc b/projects/pzsdr1/common/pzsdr1_constr.xdc new file mode 100644 index 000000000..a334553a2 --- /dev/null +++ b/projects/pzsdr1/common/pzsdr1_constr.xdc @@ -0,0 +1,188 @@ + +# constraints (pzsdr1.b) +# ad9361 + +set_property -dict {PACKAGE_PIN K19 IOSTANDARD LVCMOS25} [get_ports enable] ; ## IO_L10P_T1_AD11P_35 U1,L16,IO_L11_35_ENABLE +set_property -dict {PACKAGE_PIN L17 IOSTANDARD LVCMOS25} [get_ports txnrx] ; ## IO_L11N_T1_SRCC_35 U1,L17,IO_L11_35_TXNRX + +set_property -dict {PACKAGE_PIN H15 IOSTANDARD LVCMOS25} [get_ports gpio_status[0]] ; ## IO_L19P_T3_35 U1,H15,IO_L19_35_CTRL_OUT0 +set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVCMOS25} [get_ports gpio_status[1]] ; ## IO_L19N_T3_VREF_35 U1,G15,IO_L19_35_CTRL_OUT1 +set_property -dict {PACKAGE_PIN K14 IOSTANDARD LVCMOS25} [get_ports gpio_status[2]] ; ## IO_L20P_T3_AD6P_35 U1,K14,IO_L20_35_CTRL_OUT2 +set_property -dict {PACKAGE_PIN J14 IOSTANDARD LVCMOS25} [get_ports gpio_status[3]] ; ## IO_L20N_T3_AD6N_35 U1,J14,IO_L20_35_CTRL_OUT3 +set_property -dict {PACKAGE_PIN N15 IOSTANDARD LVCMOS25} [get_ports gpio_status[4]] ; ## IO_L21P_T3_DQS_AD14P_35 U1,N15,IO_L21_35_CTRL_OUT4 +set_property -dict {PACKAGE_PIN N16 IOSTANDARD LVCMOS25} [get_ports gpio_status[5]] ; ## IO_L21N_T3_DQS_AD14N_35 U1,N16,IO_L21_35_CTRL_OUT5 +set_property -dict {PACKAGE_PIN L14 IOSTANDARD LVCMOS25} [get_ports gpio_status[6]] ; ## IO_L22P_T3_AD7P_35 U1,L14,IO_L22_35_CTRL_OUT6 +set_property -dict {PACKAGE_PIN L15 IOSTANDARD LVCMOS25} [get_ports gpio_status[7]] ; ## IO_L22N_T3_AD7N_35 U1,L15,IO_L22_35_CTRL_OUT7 +set_property -dict {PACKAGE_PIN N17 IOSTANDARD LVCMOS25} [get_ports gpio_ctl[0]] ; ## IO_L23P_T3_34 U1,N17,IO_L23_34_CTRL_IN0 +set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS25} [get_ports gpio_ctl[1]] ; ## IO_L23N_T3_34 U1,P18,IO_L23_34_CTRL_IN1 +set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS25} [get_ports gpio_ctl[2]] ; ## IO_L24P_T3_34 U1,P15,IO_L24_34_CTRL_IN2 +set_property -dict {PACKAGE_PIN P16 IOSTANDARD LVCMOS25} [get_ports gpio_ctl[3]] ; ## IO_L24N_T3_34 U1,P16,IO_L24_34_CTRL_IN3 +set_property -dict {PACKAGE_PIN L16 IOSTANDARD LVCMOS25} [get_ports gpio_en_agc] ; ## IO_L11P_T1_SRCC_35 U1,K19,IO_L10_35_EN_AGC +set_property -dict {PACKAGE_PIN J19 IOSTANDARD LVCMOS25} [get_ports gpio_sync] ; ## IO_L10N_T1_AD11N_35 U1,J19,IO_L10_35_SYNC_IN +set_property -dict {PACKAGE_PIN G14 IOSTANDARD LVCMOS25} [get_ports gpio_resetb] ; ## IO_0_35 U1,G14,IO_00_35_AD9364_RST +set_property -dict {PACKAGE_PIN R19 IOSTANDARD LVCMOS25} [get_ports gpio_clksel] ; ## IO_0_34 U1,R19,IO_00_34_AD9364_CLKSEL + +set_property -dict {PACKAGE_PIN M14 IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports spi_csn] ; ## IO_L23P_T3_35 U1,M14,IO_L23_35_SPI_ENB +set_property -dict {PACKAGE_PIN M15 IOSTANDARD LVCMOS25} [get_ports spi_clk] ; ## IO_L23N_T3_35 U1,M15,IO_L23_35_SPI_CLK +set_property -dict {PACKAGE_PIN K16 IOSTANDARD LVCMOS25} [get_ports spi_mosi] ; ## IO_L24P_T3_AD15P_35 U1,K16,IO_L24_35_SPI_DI +set_property -dict {PACKAGE_PIN J16 IOSTANDARD LVCMOS25} [get_ports spi_miso] ; ## IO_L24N_T3_AD15N_35 U1,J16,IO_L24_35_SPI_DO + +set_property -dict {PACKAGE_PIN J15 IOSTANDARD LVCMOS25} [get_ports clkout_in] ; ## IO_25_35 U1,J15,IO_25_35_AD9364_CLKOUT + +# iic + +set_property -dict {PACKAGE_PIN W6 IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports iic_scl] ; ## IO_L22N_T3_13 U1,W6,SCL,JX2,17,I2C_SCL +set_property -dict {PACKAGE_PIN V6 IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports iic_sda] ; ## IO_L22P_T3_13 U1,V6,SDA,JX2,19,I2C_SDA + +## reference-only +## -------------- +## ad9361 (optional rf-card) +## -------------------------- +## JX4,1,GPO0 +## JX4,2,GPO1 +## JX4,3,GPO2 +## JX4,4,GPO3 +## JX4,7,AUXADC +## JX4,8,AUXDAC1 +## JX4,10,AUXDAC2 +## JX4,63,AD9364_CLK + +## fixed-io (ps7) (som only, others are carrier specific) +## ------------------------------------------------------ +## U1,A7,PS_MIO01_500_QSPI0_SS_B +## U1,A5,PS_MIO06_500_QSPI0_SCLK +## U1,B8,PS_MIO02_500_QSPI0_IO0 +## U1,D6,PS_MIO03_500_QSPI0_IO1 +## U1,B7,PS_MIO04_500_QSPI0_IO2 +## U1,A6,PS_MIO05_500_QSPI0_IO3 +## U1,D5,PS_MIO08_500_ETH0_RESETN (magnetics-RJ45- JX3,47,ETH_PHY_LED0) +## U1,C11,PS_MIO53_501_ETH0_MDIO (magnetics-RJ45- JX3,48,ETH_PHY_LED1) +## U1,C10,PS_MIO52_501_ETH0_MDC (magnetics-RJ45- JX3,51,ETH_MD1_P) +## U1,B17,PS_MIO22_501_ETH0_RX_CLK (magnetics-RJ45- JX3,53,ETH_MD1_N) +## U1,D13,PS_MIO27_501_ETH0_RX_CTL (magnetics-RJ45- JX3,52,ETH_MD2_P) +## U1,D11,PS_MIO23_501_ETH0_RX_D0 (magnetics-RJ45- JX3,54,ETH_MD2_N) +## U1,A16,PS_MIO24_501_ETH0_RX_D1 (magnetics-RJ45- JX3,57,ETH_MD3_P) +## U1,F15,PS_MIO25_501_ETH0_RX_D2 (magnetics-RJ45- JX3,59,ETH_MD3_P) +## U1,A15,PS_MIO26_501_ETH0_RX_D3 (magnetics-RJ45- JX3,58,ETH_MD4_P) +## U1,A19,PS_MIO16_501_ETH0_TX_CLK (magnetics-RJ45- JX3,60,ETH_MD4_P) +## U1,F14,PS_MIO21_501_ETH0_TX_CTL +## U1,E14,PS_MIO17_501_ETH0_TX_D0 +## U1,B18,PS_MIO18_501_ETH0_TX_D1 +## U1,D10,PS_MIO19_501_ETH0_TX_D2 +## U1,A17,PS_MIO20_501_ETH0_TX_D3 +## U1,B12,PS_MIO48_501_JX4,JX4,99,USB_UART_RXD +## U1,C12,PS_MIO49_501_JX4,JX4,98,USB_UART_TXD +## U1,D14,PS_MIO40_501_SD0_CLK (off-board- JX3,43,SDIO_CLKB1) +## U1,C17,PS_MIO41_501_SD0_CMD (off-board- JX3,34,SDIO_CMDB1) +## U1,E12,PS_MIO42_501_SD0_DATA0 (off-board- JX3,37,SDIO_DAT0B1) +## U1,A9,PS_MIO43_501_SD0_DATA1 (off-board- JX3,36,SDIO_DAT1B1) +## U1,F13,PS_MIO44_501_SD0_DATA2 (off-board- JX3,39,SDIO_DAT2B1) +## U1,B15,PS_MIO45_501_SD0_DATA3 (off-board- JX3,38,SDIO_DAT3B1) +## U1,B13,PS_MIO50_501_SD0_CD (off-board- JX3,41,JX3_SD1_CDN) +## U1,D8,PS_MIO07_500_USB_RESET_B (usb- JX3,63,USB_ID) +## U1,B5,PS_MIO09_500_USB_CLK_PD (usb- JX3,67,USB_OTG_P) +## U1,C13,PS_MIO29_501_USB0_DIR (usb- JX3,69,USB_OTG_N) +## U1,C15,PS_MIO30_501_USB0_STP (usb- JX3,68,USB_VBUS_OTG) +## U1,E16,PS_MIO31_501_USB0_NXT (usb- JX3,70,USB_OTG_CPEN) +## U1,A11,PS_MIO36_501_USB0_CLK +## U1,A14,PS_MIO32_501_USB0_D0 +## U1,D15,PS_MIO33_501_USB0_D1 +## U1,A12,PS_MIO34_501_USB0_D2 +## U1,F12,PS_MIO35_501_USB0_D3 +## U1,C16,PS_MIO28_501_USB0_D4 +## U1,A10,PS_MIO37_501_USB0_D5 +## U1,E13,PS_MIO38_501_USB0_D6 +## U1,C18,PS_MIO39_501_USB0_D7 + +## ddr (fixed-io) +## -------------- +## U1,C2,DDR3_DQS0_P +## U1,B2,DDR3_DQS0_N +## U1,G2,DDR3_DQS1_P +## U1,F2,DDR3_DQS1_N +## U1,R2,DDR3_DQS2_P +## U1,T2,DDR3_DQS2_N +## U1,W5,DDR3_DQS3_P +## U1,W4,DDR3_DQS3_N +## U1,C3,DDR3_DQ0 +## U1,B3,DDR3_DQ1 +## U1,A2,DDR3_DQ2 +## U1,A4,DDR3_DQ3 +## U1,D3,DDR3_DQ4 +## U1,D1,DDR3_DQ5 +## U1,C1,DDR3_DQ6 +## U1,E1,DDR3_DQ7 +## U1,E2,DDR3_DQ8 +## U1,E3,DDR3_DQ9 +## U1,G3,DDR3_DQ10 +## U1,H3,DDR3_DQ11 +## U1,J3,DDR3_DQ12 +## U1,H2,DDR3_DQ13 +## U1,H1,DDR3_DQ14 +## U1,J1,DDR3_DQ15 +## U1,P1,DDR3_DQ16 +## U1,P3,DDR3_DQ17 +## U1,R3,DDR3_DQ18 +## U1,R1,DDR3_DQ19 +## U1,T4,DDR3_DQ20 +## U1,U4,DDR3_DQ21 +## U1,U2,DDR3_DQ22 +## U1,U3,DDR3_DQ23 +## U1,V1,DDR3_DQ24 +## U1,Y3,DDR3_DQ25 +## U1,W1,DDR3_DQ26 +## U1,Y4,DDR3_DQ27 +## U1,Y2,DDR3_DQ28 +## U1,W3,DDR3_DQ29 +## U1,V2,DDR3_DQ30 +## U1,V3,DDR3_DQ31 +## U1,A1,DDR3_DM0 +## U1,F1,DDR3_DM1 +## U1,T1,DDR3_DM2 +## U1,Y1,DDR3_DM3 +## U1,N2,DDR3_A0 +## U1,K2,DDR3_A1 +## U1,M3,DDR3_A2 +## U1,K3,DDR3_A3 +## U1,M4,DDR3_A4 +## U1,L1,DDR3_A5 +## U1,L4,DDR3_A6 +## U1,K4,DDR3_A7 +## U1,K1,DDR3_A8 +## U1,J4,DDR3_A9 +## U1,F5,DDR3_A10 +## U1,G4,DDR3_A11 +## U1,E4,DDR3_A12 +## U1,D4,DDR3_A13 +## U1,F4,DDR3_A14 +## U1,L5,DDR3_BA0 +## U1,R4,DDR3_BA1 +## U1,J5,DDR3_BA2 +## U1,L2,DDR3_CK_P +## U1,M2,DDR3_CK_N +## U1,N3,DDR3_CKE +## U1,B4,DDR3_RST# +## U1,N1,DDR3_CS# +## U1,M5,DDR3_WE# +## U1,P4,DDR3_RAS# +## U1,P5,DDR3_CAS# +## U1,N5,DDR3_ODT + +## resets, clock and power controls +## -------------------------------- +## U1,E7,UNNAMED_3_ICXC7Z20_I217_PSCLK50,33.33MEGHZ +## U1,B10,PS-SRST# +## U1,C7,PWR_GD_1.35V +## JX2,10,PG_1P8V +## JX2,11,PG_MODULE +## JX1,5,PWR_ENABLE +## JX1,6,CARRIER_RESET + +## JTAG +## ---- +## U1,J6,JTAG_TMS,JX1,2,JTAG_TMS +## U1,F9,JTAG_TCK,JX1,1,JTAG_TCK +## U1,F6,JTAG_TDO,JX1,3,JTAG_TDO +## U1,G6,JTAG_TDI,JX1,4,JTAG_TDI +## U1,R11,FPGA_DONE,JX1,8,CFG_DONE + diff --git a/projects/pzsdr1/common/pzsdr1_constr_cmos.xdc b/projects/pzsdr1/common/pzsdr1_constr_cmos.xdc new file mode 100644 index 000000000..1b2d85586 --- /dev/null +++ b/projects/pzsdr1/common/pzsdr1_constr_cmos.xdc @@ -0,0 +1,42 @@ + +# constraints (pzsdr1.b) +# ad9361 (SWAP == 0x0) + +set_property -dict {PACKAGE_PIN K17 IOSTANDARD LVCMOS25} [get_ports rx_clk_in] ; ## IO_L12P_T1_MRCC_35 U1,K17,IO_L12_MRCC_35_DATA_CLK_P +set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVCMOS25} [get_ports rx_frame_in] ; ## IO_L7P_T1_AD2P_35 U1,M19,IO_L07_35_RX_FRAME_P +set_property -dict {PACKAGE_PIN H17 IOSTANDARD LVCMOS25} [get_ports rx_data_in[0]] ; ## IO_L13N_T2_MRCC_35 U1,H17,IO_L13_35_TX_D0_N +set_property -dict {PACKAGE_PIN H16 IOSTANDARD LVCMOS25} [get_ports rx_data_in[1]] ; ## IO_L13P_T2_MRCC_35 U1,H16,IO_L13_35_TX_D0_P +set_property -dict {PACKAGE_PIN H18 IOSTANDARD LVCMOS25} [get_ports rx_data_in[2]] ; ## IO_L14N_T2_AD4N_SRCC_35 U1,H18,IO_L14_35_TX_D1_N +set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS25} [get_ports rx_data_in[3]] ; ## IO_L14P_T2_AD4P_SRCC_35 U1,J18,IO_L14_35_TX_D1_P +set_property -dict {PACKAGE_PIN F20 IOSTANDARD LVCMOS25} [get_ports rx_data_in[4]] ; ## IO_L15N_T2_DQS_AD12N_35 U1,F20,IO_L15_35_TX_D2_N +set_property -dict {PACKAGE_PIN F19 IOSTANDARD LVCMOS25} [get_ports rx_data_in[5]] ; ## IO_L15P_T2_DQS_AD12P_35 U1,F19,IO_L15_35_TX_D2_P +set_property -dict {PACKAGE_PIN G18 IOSTANDARD LVCMOS25} [get_ports rx_data_in[6]] ; ## IO_L16N_T2_35 U1,G18,IO_L16_35_TX_D3_N +set_property -dict {PACKAGE_PIN G17 IOSTANDARD LVCMOS25} [get_ports rx_data_in[7]] ; ## IO_L16P_T2_35 U1,G17,IO_L16_35_TX_D3_P +set_property -dict {PACKAGE_PIN H20 IOSTANDARD LVCMOS25} [get_ports rx_data_in[8]] ; ## IO_L17N_T2_AD5N_35 U1,H20,IO_L17_35_TX_D4_N +set_property -dict {PACKAGE_PIN J20 IOSTANDARD LVCMOS25} [get_ports rx_data_in[9]] ; ## IO_L17P_T2_AD5P_35 U1,J20,IO_L17_35_TX_D4_P +set_property -dict {PACKAGE_PIN G20 IOSTANDARD LVCMOS25} [get_ports rx_data_in[10]] ; ## IO_L18N_T2_AD13N_35 U1,G20,IO_L18_35_TX_D5_N +set_property -dict {PACKAGE_PIN G19 IOSTANDARD LVCMOS25} [get_ports rx_data_in[11]] ; ## IO_L18P_T2_AD13P_35 U1,G19,IO_L18_35_TX_D5_P + +set_property -dict {PACKAGE_PIN M17 IOSTANDARD LVCMOS25} [get_ports tx_clk_out] ; ## IO_L8P_T1_AD10P_35 U1,M17,IO_L08_35_FB_CLK_P +set_property -dict {PACKAGE_PIN L19 IOSTANDARD LVCMOS25} [get_ports tx_frame_out] ; ## IO_L9P_T1_DQS_AD3P_35 U1,L19,IO_L09_35_TX_FRAME_P +set_property -dict {PACKAGE_PIN B20 IOSTANDARD LVCMOS25} [get_ports tx_data_out[0]] ; ## IO_L1N_T0_AD0N_35 U1,B20,IO_L01_35_RX_D0_N +set_property -dict {PACKAGE_PIN C20 IOSTANDARD LVCMOS25} [get_ports tx_data_out[1]] ; ## IO_L1P_T0_AD0P_35 U1,C20,IO_L01_35_RX_D0_P +set_property -dict {PACKAGE_PIN A20 IOSTANDARD LVCMOS25} [get_ports tx_data_out[2]] ; ## IO_L2N_T0_AD8N_35 U1,A20,IO_L02_35_RX_D1_N +set_property -dict {PACKAGE_PIN B19 IOSTANDARD LVCMOS25} [get_ports tx_data_out[3]] ; ## IO_L2P_T0_AD8P_35 U1,B19,IO_L02_35_RX_D1_P +set_property -dict {PACKAGE_PIN D18 IOSTANDARD LVCMOS25} [get_ports tx_data_out[4]] ; ## IO_L3N_T0_DQS_AD1N_35 U1,D18,IO_L03_35_RX_D2_N +set_property -dict {PACKAGE_PIN E17 IOSTANDARD LVCMOS25} [get_ports tx_data_out[5]] ; ## IO_L3P_T0_DQS_AD1P_35 U1,E17,IO_L03_35_RX_D2_P +set_property -dict {PACKAGE_PIN D20 IOSTANDARD LVCMOS25} [get_ports tx_data_out[6]] ; ## IO_L4N_T0_35 U1,D20,IO_L04_35_RX_D3_N +set_property -dict {PACKAGE_PIN D19 IOSTANDARD LVCMOS25} [get_ports tx_data_out[7]] ; ## IO_L4P_T0_35 U1,D19,IO_L04_35_RX_D3_P +set_property -dict {PACKAGE_PIN E19 IOSTANDARD LVCMOS25} [get_ports tx_data_out[8]] ; ## IO_L5N_T0_AD9N_35 U1,E19,IO_L05_35_RX_D4_N +set_property -dict {PACKAGE_PIN E18 IOSTANDARD LVCMOS25} [get_ports tx_data_out[9]] ; ## IO_L5P_T0_AD9P_35 U1,E18,IO_L05_35_RX_D4_P +set_property -dict {PACKAGE_PIN F17 IOSTANDARD LVCMOS25} [get_ports tx_data_out[10]] ; ## IO_L6N_T0_VREF_35 U1,F17,IO_L06_35_RX_D5_N +set_property -dict {PACKAGE_PIN F16 IOSTANDARD LVCMOS25} [get_ports tx_data_out[11]] ; ## IO_L6P_T0_35 U1,F16,IO_L06_35_RX_D5_P + +set_property -dict {PACKAGE_PIN M18 IOSTANDARD LVCMOS25} [get_ports tx_gnd[0]] ; ## IO_L8N_T1_AD10N_35 U1,M18,IO_L08_35_FB_CLK_N +set_property -dict {PACKAGE_PIN L20 IOSTANDARD LVCMOS25} [get_ports tx_gnd[1]] ; ## IO_L9N_T1_DQS_AD3N_35 U1,L20,IO_L09_35_TX_FRAME_N + +# clocks + +create_clock -name rx_clk -period 8 [get_ports rx_clk_in] +create_clock -name ad9361_clk -period 8 [get_pins i_system_wrapper/system_i/axi_ad9361/clk] + diff --git a/projects/pzsdr1/common/pzsdr1_constr_lvds.xdc b/projects/pzsdr1/common/pzsdr1_constr_lvds.xdc new file mode 100644 index 000000000..da996fea6 --- /dev/null +++ b/projects/pzsdr1/common/pzsdr1_constr_lvds.xdc @@ -0,0 +1,42 @@ + +# constraints (pzsdr1.b) +# ad9361 + +set_property -dict {PACKAGE_PIN K17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_clk_in_p] ; ## IO_L12P_T1_MRCC_35 U1,K17,IO_L12_MRCC_35_DATA_CLK_P +set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_clk_in_n] ; ## IO_L12N_T1_MRCC_35 U1,K18,IO_L12_MRCC_35_DATA_CLK_N +set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_frame_in_p] ; ## IO_L7P_T1_AD2P_35 U1,M19,IO_L07_35_RX_FRAME_P +set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_frame_in_n] ; ## IO_L7N_T1_AD2N_35 U1,M20,IO_L07_35_RX_FRAME_N +set_property -dict {PACKAGE_PIN C20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_p[0]] ; ## IO_L1P_T0_AD0P_35 U1,C20,IO_L01_35_RX_D0_P +set_property -dict {PACKAGE_PIN B20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_n[0]] ; ## IO_L1N_T0_AD0N_35 U1,B20,IO_L01_35_RX_D0_N +set_property -dict {PACKAGE_PIN B19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_p[1]] ; ## IO_L2P_T0_AD8P_35 U1,B19,IO_L02_35_RX_D1_P +set_property -dict {PACKAGE_PIN A20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_n[1]] ; ## IO_L2N_T0_AD8N_35 U1,A20,IO_L02_35_RX_D1_N +set_property -dict {PACKAGE_PIN E17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_p[2]] ; ## IO_L3P_T0_DQS_AD1P_35 U1,E17,IO_L03_35_RX_D2_P +set_property -dict {PACKAGE_PIN D18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_n[2]] ; ## IO_L3N_T0_DQS_AD1N_35 U1,D18,IO_L03_35_RX_D2_N +set_property -dict {PACKAGE_PIN D19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_p[3]] ; ## IO_L4P_T0_35 U1,D19,IO_L04_35_RX_D3_P +set_property -dict {PACKAGE_PIN D20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_n[3]] ; ## IO_L4N_T0_35 U1,D20,IO_L04_35_RX_D3_N +set_property -dict {PACKAGE_PIN E18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_p[4]] ; ## IO_L5P_T0_AD9P_35 U1,E18,IO_L05_35_RX_D4_P +set_property -dict {PACKAGE_PIN E19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_n[4]] ; ## IO_L5N_T0_AD9N_35 U1,E19,IO_L05_35_RX_D4_N +set_property -dict {PACKAGE_PIN F16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_p[5]] ; ## IO_L6P_T0_35 U1,F16,IO_L06_35_RX_D5_P +set_property -dict {PACKAGE_PIN F17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_n[5]] ; ## IO_L6N_T0_VREF_35 U1,F17,IO_L06_35_RX_D5_N +set_property -dict {PACKAGE_PIN M17 IOSTANDARD LVDS_25} [get_ports tx_clk_out_p] ; ## IO_L8P_T1_AD10P_35 U1,M17,IO_L08_35_FB_CLK_P +set_property -dict {PACKAGE_PIN M18 IOSTANDARD LVDS_25} [get_ports tx_clk_out_n] ; ## IO_L8N_T1_AD10N_35 U1,M18,IO_L08_35_FB_CLK_N +set_property -dict {PACKAGE_PIN L19 IOSTANDARD LVDS_25} [get_ports tx_frame_out_p] ; ## IO_L9P_T1_DQS_AD3P_35 U1,L19,IO_L09_35_TX_FRAME_P +set_property -dict {PACKAGE_PIN L20 IOSTANDARD LVDS_25} [get_ports tx_frame_out_n] ; ## IO_L9N_T1_DQS_AD3N_35 U1,L20,IO_L09_35_TX_FRAME_N +set_property -dict {PACKAGE_PIN H16 IOSTANDARD LVDS_25} [get_ports tx_data_out_p[0]] ; ## IO_L13P_T2_MRCC_35 U1,H16,IO_L13_35_TX_D0_P +set_property -dict {PACKAGE_PIN H17 IOSTANDARD LVDS_25} [get_ports tx_data_out_n[0]] ; ## IO_L13N_T2_MRCC_35 U1,H17,IO_L13_35_TX_D0_N +set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVDS_25} [get_ports tx_data_out_p[1]] ; ## IO_L14P_T2_AD4P_SRCC_35 U1,J18,IO_L14_35_TX_D1_P +set_property -dict {PACKAGE_PIN H18 IOSTANDARD LVDS_25} [get_ports tx_data_out_n[1]] ; ## IO_L14N_T2_AD4N_SRCC_35 U1,H18,IO_L14_35_TX_D1_N +set_property -dict {PACKAGE_PIN F19 IOSTANDARD LVDS_25} [get_ports tx_data_out_p[2]] ; ## IO_L15P_T2_DQS_AD12P_35 U1,F19,IO_L15_35_TX_D2_P +set_property -dict {PACKAGE_PIN F20 IOSTANDARD LVDS_25} [get_ports tx_data_out_n[2]] ; ## IO_L15N_T2_DQS_AD12N_35 U1,F20,IO_L15_35_TX_D2_N +set_property -dict {PACKAGE_PIN G17 IOSTANDARD LVDS_25} [get_ports tx_data_out_p[3]] ; ## IO_L16P_T2_35 U1,G17,IO_L16_35_TX_D3_P +set_property -dict {PACKAGE_PIN G18 IOSTANDARD LVDS_25} [get_ports tx_data_out_n[3]] ; ## IO_L16N_T2_35 U1,G18,IO_L16_35_TX_D3_N +set_property -dict {PACKAGE_PIN J20 IOSTANDARD LVDS_25} [get_ports tx_data_out_p[4]] ; ## IO_L17P_T2_AD5P_35 U1,J20,IO_L17_35_TX_D4_P +set_property -dict {PACKAGE_PIN H20 IOSTANDARD LVDS_25} [get_ports tx_data_out_n[4]] ; ## IO_L17N_T2_AD5N_35 U1,H20,IO_L17_35_TX_D4_N +set_property -dict {PACKAGE_PIN G19 IOSTANDARD LVDS_25} [get_ports tx_data_out_p[5]] ; ## IO_L18P_T2_AD13P_35 U1,G19,IO_L18_35_TX_D5_P +set_property -dict {PACKAGE_PIN G20 IOSTANDARD LVDS_25} [get_ports tx_data_out_n[5]] ; ## IO_L18N_T2_AD13N_35 U1,G20,IO_L18_35_TX_D5_N + +# clocks + +create_clock -name rx_clk -period 8 [get_ports rx_clk_in_p] +create_clock -name ad9361_clk -period 8 [get_pins i_system_wrapper/system_i/axi_ad9361/clk] + diff --git a/projects/pzsdr2/Makefile b/projects/pzsdr2/Makefile new file mode 100644 index 000000000..bd4b8e2da --- /dev/null +++ b/projects/pzsdr2/Makefile @@ -0,0 +1,36 @@ +#################################################################################### +#################################################################################### +## Copyright 2011(c) Analog Devices, Inc. +## Auto-generated, do not modify! +#################################################################################### +#################################################################################### + +.PHONY: all clean clean-all +all: + -make -C ccbox_lvds all + -make -C ccbrk_cmos all + -make -C ccbrk_lvds all + -make -C ccfmc_lvds all + -make -C ccpci_lvds all + -make -C ccusb_lvds all + + +clean: + make -C ccbox_lvds clean + make -C ccbrk_cmos clean + make -C ccbrk_lvds clean + make -C ccfmc_lvds clean + make -C ccpci_lvds clean + make -C ccusb_lvds clean + + +clean-all: + make -C ccbox_lvds clean-all + make -C ccbrk_cmos clean-all + make -C ccbrk_lvds clean-all + make -C ccfmc_lvds clean-all + make -C ccpci_lvds clean-all + make -C ccusb_lvds clean-all + +#################################################################################### +#################################################################################### diff --git a/projects/pzsdr2/README.md b/projects/pzsdr2/README.md new file mode 100644 index 000000000..e59185903 --- /dev/null +++ b/projects/pzsdr2/README.md @@ -0,0 +1,48 @@ +# PicoZed SDR SOM (PZSDR2) + +This folder contains the PZSDR2 SOM projects for each of the carrier boards. + +## Board Design Files + +| Directory/File | Description | +|----------------------|----------------------------------------| +| common/pzsdr2_bd.tcl | pzsdr2 SOM module board design file. | +| common/ccbrk_bd.tcl | carrier, break out board design file. | +| common/ccfmc_bd.tcl | carrier, fmc board design file. | +| common/ccpci_bd.tcl | carrier, pci-e board design file. | +| common/ccusb_bd.tcl | carrier, usb board design file. | + +FMC & BRK carrier designs includes loopback daughtercards for connectivity testing. + +## Board Constraint Files + +| Directory/File | Description | +|-------------------------------|-----------------------------------------------| +| common/pzsdr2_constr.xdc | pzsdr2 SOM base constraints file. | +| common/pzsdr2_constr_cmos.xdc | pzsdr2 SOM CMOS mode constraints file. | +| common/pzsdr2_constr_lvds.xdc | pzsdr2 SOM LVDS mode constraints file. | +| common/ccbrk_constr.xdc | carrier, break out board constraints file. | +| common/ccfmc_constr.xdc | carrier, fmc board constraints file. | +| common/ccpci_constr.xdc | carrier, pci-e board constraints file. | +| common/ccusb_constr.xdc | carrier, usb board constraints file. | + +FMC & BRK carrier designs includes loopback daughtercards for connectivity testing. + +## Building, Generating Bit Files + +[pzsdr2] cd ccbrk_cmos + +[pzsdr2/ccbrk_cmos] make + +The make in each carrier directory builds the corresponding project. The above example builds PZSDR2-CCBRK hardware bit files in CMOS mode. + +## Documentation + + * [HDL Design User Guide] + * [IP User Guide] + * [PZSDR2 Wiki page] + +[HDL Design User Guide]:http://wiki.analog.com/resources/fpga/docs/hdl +[IP User Guide]:http://wiki.analog.com/resources/fpga/docs/axi_ad9361 +[PZSDR2 Wiki page]:https://wiki.analog.com/resources/eval/user-guides/picozed_sdr + diff --git a/projects/pzsdr2/ccbox_lvds/Makefile b/projects/pzsdr2/ccbox_lvds/Makefile new file mode 100644 index 000000000..d799a33e0 --- /dev/null +++ b/projects/pzsdr2/ccbox_lvds/Makefile @@ -0,0 +1,85 @@ +#################################################################################### +#################################################################################### +## Copyright 2011(c) Analog Devices, Inc. +## Auto-generated, do not modify! +#################################################################################### +#################################################################################### + +M_DEPS += system_top.v +M_DEPS += system_project.tcl +M_DEPS += system_bd.tcl +M_DEPS += ../common/pzsdr2_constr_lvds.xdc +M_DEPS += ../common/pzsdr2_constr.xdc +M_DEPS += ../common/pzsdr2_bd.tcl +M_DEPS += ../common/ccbox_constr.xdc +M_DEPS += ../common/ccbox_bd.tcl +M_DEPS += ../../scripts/adi_project.tcl +M_DEPS += ../../scripts/adi_env.tcl +M_DEPS += ../../scripts/adi_board.tcl +M_DEPS += ../../../library/xilinx/common/ad_iobuf.v +M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr +M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr +M_DEPS += ../../../library/axi_i2s_adi/axi_i2s_adi.xpr +M_DEPS += ../../../library/util_clkdiv/util_clkdiv.xpr +M_DEPS += ../../../library/util_cpack/util_cpack.xpr +M_DEPS += ../../../library/util_rfifo/util_rfifo.xpr +M_DEPS += ../../../library/util_tdd_sync/util_tdd_sync.xpr +M_DEPS += ../../../library/util_upack/util_upack.xpr +M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr + +M_VIVADO := vivado -mode batch -source + +M_FLIST := *.cache +M_FLIST += *.data +M_FLIST += *.xpr +M_FLIST += *.log +M_FLIST += *.jou +M_FLIST += xgui +M_FLIST += *.runs +M_FLIST += *.srcs +M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim +M_FLIST += .Xil +M_FLIST += *.ip_user_files + + + +.PHONY: all lib clean clean-all +all: lib pzsdr2_ccbox_lvds.sdk/system_top.hdf + + +clean: + rm -rf $(M_FLIST) + + +clean-all:clean + make -C ../../../library/axi_ad9361 clean + make -C ../../../library/axi_dmac clean + make -C ../../../library/axi_i2s_adi clean + make -C ../../../library/util_clkdiv clean + make -C ../../../library/util_cpack clean + make -C ../../../library/util_rfifo clean + make -C ../../../library/util_tdd_sync clean + make -C ../../../library/util_upack clean + make -C ../../../library/util_wfifo clean + + +pzsdr2_ccbox_lvds.sdk/system_top.hdf: $(M_DEPS) + -rm -rf $(M_FLIST) + $(M_VIVADO) system_project.tcl >> pzsdr2_ccbox_lvds_vivado.log 2>&1 + + +lib: + make -C ../../../library/axi_ad9361 + make -C ../../../library/axi_dmac + make -C ../../../library/axi_i2s_adi + make -C ../../../library/util_clkdiv + make -C ../../../library/util_cpack + make -C ../../../library/util_rfifo + make -C ../../../library/util_tdd_sync + make -C ../../../library/util_upack + make -C ../../../library/util_wfifo + +#################################################################################### +#################################################################################### diff --git a/projects/pzsdr2/ccbox_lvds/system_bd.tcl b/projects/pzsdr2/ccbox_lvds/system_bd.tcl new file mode 100644 index 000000000..739e5a097 --- /dev/null +++ b/projects/pzsdr2/ccbox_lvds/system_bd.tcl @@ -0,0 +1,6 @@ + +source ../common/pzsdr2_bd.tcl +source ../common/ccbox_bd.tcl + +cfg_ad9361_interface LVDS + diff --git a/projects/pzsdr2/ccbox_lvds/system_project.tcl b/projects/pzsdr2/ccbox_lvds/system_project.tcl new file mode 100644 index 000000000..8211b8ea2 --- /dev/null +++ b/projects/pzsdr2/ccbox_lvds/system_project.tcl @@ -0,0 +1,17 @@ + +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/projects/scripts/adi_project.tcl +source $ad_hdl_dir/projects/scripts/adi_board.tcl + +set p_device "xc7z035ifbg676-2L" +adi_project_create pzsdr2_ccbox_lvds +adi_project_files pzsdr2_ccbox_lvds [list \ + "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \ + "../common/pzsdr2_constr.xdc" \ + "../common/pzsdr2_constr_lvds.xdc" \ + "../common/ccbox_constr.xdc" \ + "system_top.v" ] + +adi_project_run pzsdr2_ccbox_lvds + + diff --git a/projects/pzsdr2/ccbox_lvds/system_top.v b/projects/pzsdr2/ccbox_lvds/system_top.v new file mode 100644 index 000000000..a7ab38b4e --- /dev/null +++ b/projects/pzsdr2/ccbox_lvds/system_top.v @@ -0,0 +1,323 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top ( + + inout [14:0] ddr_addr, + inout [ 2:0] ddr_ba, + inout ddr_cas_n, + inout ddr_ck_n, + inout ddr_ck_p, + inout ddr_cke, + inout ddr_cs_n, + inout [ 3:0] ddr_dm, + inout [31:0] ddr_dq, + inout [ 3:0] ddr_dqs_n, + inout [ 3:0] ddr_dqs_p, + inout ddr_odt, + inout ddr_ras_n, + inout ddr_reset_n, + inout ddr_we_n, + + inout fixed_io_ddr_vrn, + inout fixed_io_ddr_vrp, + inout [53:0] fixed_io_mio, + inout fixed_io_ps_clk, + inout fixed_io_ps_porb, + inout fixed_io_ps_srstb, + + inout iic_scl, + inout iic_sda, + + output i2s_mclk, + output i2s_bclk, + output i2s_lrclk, + output i2s_sdata_out, + input i2s_sdata_in, + + output imu_csn, + output imu_clk, + output imu_mosi, + input imu_miso, + input imu_ready, + output imu_rstn, + inout imu_sync, + + output oled_csn, + output oled_clk, + output oled_mosi, + output oled_rst, + output oled_dc, + + output switch_led_r, + output switch_led_g, + output switch_led_b, + + output gps_reset, + output gps_force_on, + output gps_standby, + input gps_pps, + + input [ 2:0] pss_valid_n, + inout [ 2:0] adp5061_io, + + inout otg_ctrl, + inout adp1614_en, + inout ltc2955_kill_n, + inout ltc2955_int_n, + inout mic_present_n, + inout ts3a227_int_n, + + input rx_clk_in_p, + input rx_clk_in_n, + input rx_frame_in_p, + input rx_frame_in_n, + input [ 5:0] rx_data_in_p, + input [ 5:0] rx_data_in_n, + output tx_clk_out_p, + output tx_clk_out_n, + output tx_frame_out_p, + output tx_frame_out_n, + output [ 5:0] tx_data_out_p, + output [ 5:0] tx_data_out_n, + + output enable, + output txnrx, + input clkout_in, + + inout gpio_rf0, + inout gpio_rf1, + inout gpio_rf2, + inout gpio_rf3, + inout gpio_rf4, + inout gpio_rfpwr_enable, + inout gpio_clksel, + inout gpio_resetb, + inout gpio_sync, + inout gpio_en_agc, + inout [ 3:0] gpio_ctl, + inout [ 7:0] gpio_status, + + output spi_csn, + output spi_clk, + output spi_mosi, + input spi_miso); + + // internal signals + + wire [63:0] gpio_i; + wire [63:0] gpio_o; + wire [63:0] gpio_t; + + // assignments + + assign oled_clk = spi_clk; + assign oled_mosi = spi_mosi; + + // gpio[31:20] controls misc stuff (keep as io) + + assign gpio_i[31:29] = gpio_o[31:29]; + assign gpio_i[28:28] = imu_ready; + assign gpio_i[27:26] = gpio_o[27:26]; + + ad_iobuf #(.DATA_WIDTH(6)) i_iobuf_misc ( + .dio_t (gpio_t[25:20]), + .dio_i (gpio_o[25:20]), + .dio_o (gpio_i[25:20]), + .dio_p ({ adp1614_en, + otg_ctrl, + ltc2955_kill_n, + ltc2955_int_n, + ts3a227_int_n, + mic_present_n})); + + // gpio[19:16] controls adp5061 (keep as io) + + assign gpio_i[19] = gpio_o[19]; + + ad_iobuf #(.DATA_WIDTH(3)) i_iobuf_adp5061 ( + .dio_t (gpio_t[18:16]), + .dio_i (gpio_o[18:16]), + .dio_o (gpio_i[18:16]), + .dio_p (adp5061_io)); + + // gpio[15:12] reads power source select valids + + assign gpio_i[15:12] = {gpio_o[15], pss_valid_n}; + + // gpio[11:8] controls the imu/oled reset & such. + + assign oled_dc = gpio_o[11]; + assign oled_rst = gpio_o[10]; + assign imu_rstn = gpio_o[9]; + assign gpio_i[11:9] = gpio_o[11:9]; + + ad_iobuf #(.DATA_WIDTH(1)) i_iobuf_imu_sync ( + .dio_t (gpio_t[8]), + .dio_i (gpio_o[8]), + .dio_o (gpio_i[8]), + .dio_p (imu_sync)); + + // gpio[7:4] controls the gps + + assign gps_reset = gpio_o[6]; + assign gps_force_on = gpio_o[5]; + assign gps_standby = gpio_o[4]; + assign gpio_i[7:4] = {gps_pps, gpio_o[6:4]}; + + // gpio[3:0] controls the power switch led colors + + assign switch_led_r = gpio_o[2]; + assign switch_led_g = gpio_o[1]; + assign switch_led_b = gpio_o[0]; + assign gpio_i[3:0] = gpio_o[3:0]; + + // ad9361 gpio - 63-32 + + assign gpio_i[63:62] = gpio_o[63:62]; + assign gpio_i[60:57] = gpio_o[60:57]; + assign gpio_i[50:47] = gpio_o[50:47]; + + ad_iobuf #(.DATA_WIDTH(22)) i_iobuf ( + .dio_t ({gpio_t[61:61], gpio_t[56:51], gpio_t[46:32]}), + .dio_i ({gpio_o[61:61], gpio_o[56:51], gpio_o[46:32]}), + .dio_o ({gpio_i[61:61], gpio_i[56:51], gpio_i[46:32]}), + .dio_p ({ gpio_rf4, // 61:61 + gpio_rf0, // 56:56 + gpio_rf1, // 55:55 + gpio_rf2, // 54:54 + gpio_rf3, // 53:53 + gpio_rfpwr_enable, // 52:52 + gpio_clksel, // 51:51 + gpio_resetb, // 46:46 + gpio_sync, // 45:45 + gpio_en_agc, // 44:44 + gpio_ctl, // 43:40 + gpio_status})); // 39:32 + + // instantiations + + system_wrapper i_system_wrapper ( + .ddr_addr (ddr_addr), + .ddr_ba (ddr_ba), + .ddr_cas_n (ddr_cas_n), + .ddr_ck_n (ddr_ck_n), + .ddr_ck_p (ddr_ck_p), + .ddr_cke (ddr_cke), + .ddr_cs_n (ddr_cs_n), + .ddr_dm (ddr_dm), + .ddr_dq (ddr_dq), + .ddr_dqs_n (ddr_dqs_n), + .ddr_dqs_p (ddr_dqs_p), + .ddr_odt (ddr_odt), + .ddr_ras_n (ddr_ras_n), + .ddr_reset_n (ddr_reset_n), + .ddr_we_n (ddr_we_n), + .enable (enable), + .fixed_io_ddr_vrn (fixed_io_ddr_vrn), + .fixed_io_ddr_vrp (fixed_io_ddr_vrp), + .fixed_io_mio (fixed_io_mio), + .fixed_io_ps_clk (fixed_io_ps_clk), + .fixed_io_ps_porb (fixed_io_ps_porb), + .fixed_io_ps_srstb (fixed_io_ps_srstb), + .gpio_i (gpio_i), + .gpio_o (gpio_o), + .gpio_t (gpio_t), + .i2s_bclk (i2s_bclk), + .i2s_lrclk (i2s_lrclk), + .i2s_mclk (i2s_mclk), + .i2s_sdata_in (i2s_sdata_in), + .i2s_sdata_out (i2s_sdata_out), + .iic_main_scl_io (iic_scl), + .iic_main_sda_io (iic_sda), + .otg_vbusoc (1'b0), + .ps_intr_00 (1'b0), + .ps_intr_01 (1'b0), + .ps_intr_02 (1'b0), + .ps_intr_03 (1'b0), + .ps_intr_04 (1'b0), + .ps_intr_05 (1'b0), + .ps_intr_06 (1'b0), + .ps_intr_07 (1'b0), + .ps_intr_08 (1'b0), + .ps_intr_09 (1'b0), + .ps_intr_10 (1'b0), + .ps_intr_11 (1'b0), + .ps_intr_15 (1'b0), + .rx_clk_in_n (rx_clk_in_n), + .rx_clk_in_p (rx_clk_in_p), + .rx_data_in_n (rx_data_in_n), + .rx_data_in_p (rx_data_in_p), + .rx_frame_in_n (rx_frame_in_n), + .rx_frame_in_p (rx_frame_in_p), + .spi0_clk_i (1'b0), + .spi0_clk_o (spi_clk), + .spi0_csn_0_o (spi_csn), + .spi0_csn_1_o (oled_csn), + .spi0_csn_2_o (), + .spi0_csn_i (1'b1), + .spi0_sdi_i (spi_miso), + .spi0_sdo_i (1'b0), + .spi0_sdo_o (spi_mosi), + .spi1_clk_i (1'b0), + .spi1_clk_o (imu_clk), + .spi1_csn_0_o (imu_csn), + .spi1_csn_1_o (), + .spi1_csn_2_o (), + .spi1_csn_i (1'b1), + .spi1_sdi_i (imu_miso), + .spi1_sdo_i (1'b0), + .spi1_sdo_o (imu_mosi), + .tdd_sync_i (gps_pps), + .tdd_sync_o (), + .tdd_sync_t (), + .tx_clk_out_n (tx_clk_out_n), + .tx_clk_out_p (tx_clk_out_p), + .tx_data_out_n (tx_data_out_n), + .tx_data_out_p (tx_data_out_p), + .tx_frame_out_n (tx_frame_out_n), + .tx_frame_out_p (tx_frame_out_p), + .txnrx (txnrx), + .up_enable (gpio_o[47]), + .up_txnrx (gpio_o[48])); + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/projects/pzsdr2/ccbrk_cmos/Makefile b/projects/pzsdr2/ccbrk_cmos/Makefile new file mode 100644 index 000000000..6825ac058 --- /dev/null +++ b/projects/pzsdr2/ccbrk_cmos/Makefile @@ -0,0 +1,88 @@ +#################################################################################### +#################################################################################### +## Copyright 2011(c) Analog Devices, Inc. +## Auto-generated, do not modify! +#################################################################################### +#################################################################################### + +M_DEPS += system_top.v +M_DEPS += system_project.tcl +M_DEPS += system_bd.tcl +M_DEPS += ../common/pzsdr2_constr_cmos.xdc +M_DEPS += ../common/pzsdr2_constr.xdc +M_DEPS += ../common/pzsdr2_bd.tcl +M_DEPS += ../common/ccbrk_constr.xdc +M_DEPS += ../common/ccbrk_bd.tcl +M_DEPS += ../../scripts/adi_project.tcl +M_DEPS += ../../scripts/adi_env.tcl +M_DEPS += ../../scripts/adi_board.tcl +M_DEPS += ../../../library/xilinx/common/ad_iobuf.v +M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr +M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr +M_DEPS += ../../../library/axi_gpreg/axi_gpreg.xpr +M_DEPS += ../../../library/xilinx/axi_xcvrlb/axi_xcvrlb.xpr +M_DEPS += ../../../library/util_clkdiv/util_clkdiv.xpr +M_DEPS += ../../../library/util_cpack/util_cpack.xpr +M_DEPS += ../../../library/util_rfifo/util_rfifo.xpr +M_DEPS += ../../../library/util_tdd_sync/util_tdd_sync.xpr +M_DEPS += ../../../library/util_upack/util_upack.xpr +M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr + +M_VIVADO := vivado -mode batch -source + +M_FLIST := *.cache +M_FLIST += *.data +M_FLIST += *.xpr +M_FLIST += *.log +M_FLIST += *.jou +M_FLIST += xgui +M_FLIST += *.runs +M_FLIST += *.srcs +M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim +M_FLIST += .Xil +M_FLIST += *.ip_user_files + + + +.PHONY: all lib clean clean-all +all: lib pzsdr2_ccbrk_cmos.sdk/system_top.hdf + + +clean: + rm -rf $(M_FLIST) + + +clean-all:clean + make -C ../../../library/axi_ad9361 clean + make -C ../../../library/axi_dmac clean + make -C ../../../library/axi_gpreg clean + make -C ../../../library/xilinx/axi_xcvrlb clean + make -C ../../../library/util_clkdiv clean + make -C ../../../library/util_cpack clean + make -C ../../../library/util_rfifo clean + make -C ../../../library/util_tdd_sync clean + make -C ../../../library/util_upack clean + make -C ../../../library/util_wfifo clean + + +pzsdr2_ccbrk_cmos.sdk/system_top.hdf: $(M_DEPS) + -rm -rf $(M_FLIST) + $(M_VIVADO) system_project.tcl >> pzsdr2_ccbrk_cmos_vivado.log 2>&1 + + +lib: + make -C ../../../library/axi_ad9361 + make -C ../../../library/axi_dmac + make -C ../../../library/axi_gpreg + make -C ../../../library/xilinx/axi_xcvrlb + make -C ../../../library/util_clkdiv + make -C ../../../library/util_cpack + make -C ../../../library/util_rfifo + make -C ../../../library/util_tdd_sync + make -C ../../../library/util_upack + make -C ../../../library/util_wfifo + +#################################################################################### +#################################################################################### diff --git a/projects/pzsdr2/ccbrk_cmos/system_bd.tcl b/projects/pzsdr2/ccbrk_cmos/system_bd.tcl new file mode 100644 index 000000000..f89be6423 --- /dev/null +++ b/projects/pzsdr2/ccbrk_cmos/system_bd.tcl @@ -0,0 +1,9 @@ + +source ../common/pzsdr2_bd.tcl +source ../common/ccbrk_bd.tcl + +set_property -dict [list CONFIG.SEL_0_DIV {2}] $clkdiv +set_property -dict [list CONFIG.SEL_1_DIV {1}] $clkdiv + +cfg_ad9361_interface CMOS + diff --git a/projects/pzsdr2/ccbrk_cmos/system_project.tcl b/projects/pzsdr2/ccbrk_cmos/system_project.tcl new file mode 100644 index 000000000..9d8f3dfbb --- /dev/null +++ b/projects/pzsdr2/ccbrk_cmos/system_project.tcl @@ -0,0 +1,18 @@ + +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/projects/scripts/adi_project.tcl +source $ad_hdl_dir/projects/scripts/adi_board.tcl + +set p_device "xc7z035ifbg676-2L" +adi_project_create pzsdr2_ccbrk_cmos +adi_project_files pzsdr2_ccbrk_cmos [list \ + "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \ + "../common/pzsdr2_constr.xdc" \ + "../common/pzsdr2_constr_cmos.xdc" \ + "../common/ccbrk_constr.xdc" \ + "system_top.v" ] + +set_property is_enabled false [get_files *axi_gpreg_constr.xdc] +adi_project_run pzsdr2_ccbrk_cmos + + diff --git a/projects/pzsdr2/ccbrk_cmos/system_top.v b/projects/pzsdr2/ccbrk_cmos/system_top.v new file mode 100644 index 000000000..56fecd808 --- /dev/null +++ b/projects/pzsdr2/ccbrk_cmos/system_top.v @@ -0,0 +1,248 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top ( + + inout [14:0] ddr_addr, + inout [ 2:0] ddr_ba, + inout ddr_cas_n, + inout ddr_ck_n, + inout ddr_ck_p, + inout ddr_cke, + inout ddr_cs_n, + inout [ 3:0] ddr_dm, + inout [31:0] ddr_dq, + inout [ 3:0] ddr_dqs_n, + inout [ 3:0] ddr_dqs_p, + inout ddr_odt, + inout ddr_ras_n, + inout ddr_reset_n, + inout ddr_we_n, + + inout fixed_io_ddr_vrn, + inout fixed_io_ddr_vrp, + inout [53:0] fixed_io_mio, + inout fixed_io_ps_clk, + inout fixed_io_ps_porb, + inout fixed_io_ps_srstb, + + inout iic_scl, + inout iic_sda, + + inout [19:0] gpio_bd, + + input rx_clk_in, + input rx_frame_in, + input [11:0] rx_data_in, + output tx_clk_out, + output tx_frame_out, + output [11:0] tx_data_out, + output [ 1:0] tx_gnd, + + output enable, + output txnrx, + input clkout_in, + output clkout_out, + + inout gpio_clksel, + inout gpio_resetb, + inout gpio_sync, + inout gpio_en_agc, + inout [ 3:0] gpio_ctl, + inout [ 7:0] gpio_status, + + output spi_csn, + output spi_clk, + output spi_mosi, + input spi_miso, + + output [85:0] gp_out, + input [85:0] gp_in, + + input gt_ref_clk_p, + input gt_ref_clk_n, + output [ 3:0] gt_tx_p, + output [ 3:0] gt_tx_n, + input [ 3:0] gt_rx_p, + input [ 3:0] gt_rx_n); + + // internal signals + + wire gt_ref_clk; + wire [95:0] gp_out_s; + wire [95:0] gp_in_s; + wire [63:0] gpio_i; + wire [63:0] gpio_o; + wire [63:0] gpio_t; + + // assignments + + assign tx_gnd = 2'd0; + assign clkout_out = clkout_in; + assign gp_out[85:0] = gp_out_s[85:0]; + assign gp_in_s[95:86] = gp_out_s[95:86]; + assign gp_in_s[85: 0] = gp_in[85:0]; + + // instantiations + + IBUFDS_GTE2 i_ibufds_gt_ref_clk ( + .CEB (1'd0), + .I (gt_ref_clk_p), + .IB (gt_ref_clk_n), + .O (gt_ref_clk), + .ODIV2 ()); + + // board gpio - 31-0 + + assign gpio_i[31:20] = gpio_o[31:20]; + + ad_iobuf #(.DATA_WIDTH(20)) i_iobuf_bd ( + .dio_t (gpio_t[19:0]), + .dio_i (gpio_o[19:0]), + .dio_o (gpio_i[19:0]), + .dio_p (gpio_bd)); + + // ad9361 gpio - 63-32 + + assign gpio_i[63:52] = gpio_o[63:52]; + assign gpio_i[50:47] = gpio_o[50:47]; + + ad_iobuf #(.DATA_WIDTH(16)) i_iobuf ( + .dio_t ({gpio_t[51], gpio_t[46:32]}), + .dio_i ({gpio_o[51], gpio_o[46:32]}), + .dio_o ({gpio_i[51], gpio_i[46:32]}), + .dio_p ({ gpio_clksel, // 51:51 + gpio_resetb, // 46:46 + gpio_sync, // 45:45 + gpio_en_agc, // 44:44 + gpio_ctl, // 43:40 + gpio_status})); // 39:32 + + // instantiations + + system_wrapper i_system_wrapper ( + .ddr_addr (ddr_addr), + .ddr_ba (ddr_ba), + .ddr_cas_n (ddr_cas_n), + .ddr_ck_n (ddr_ck_n), + .ddr_ck_p (ddr_ck_p), + .ddr_cke (ddr_cke), + .ddr_cs_n (ddr_cs_n), + .ddr_dm (ddr_dm), + .ddr_dq (ddr_dq), + .ddr_dqs_n (ddr_dqs_n), + .ddr_dqs_p (ddr_dqs_p), + .ddr_odt (ddr_odt), + .ddr_ras_n (ddr_ras_n), + .ddr_reset_n (ddr_reset_n), + .ddr_we_n (ddr_we_n), + .enable (enable), + .fixed_io_ddr_vrn (fixed_io_ddr_vrn), + .fixed_io_ddr_vrp (fixed_io_ddr_vrp), + .fixed_io_mio (fixed_io_mio), + .fixed_io_ps_clk (fixed_io_ps_clk), + .fixed_io_ps_porb (fixed_io_ps_porb), + .fixed_io_ps_srstb (fixed_io_ps_srstb), + .gp_in_0 (gp_in_s[31:0]), + .gp_in_1 (gp_in_s[63:32]), + .gp_in_2 (gp_in_s[95:64]), + .gp_in_3 (32'd0), + .gp_out_0 (gp_out_s[31:0]), + .gp_out_1 (gp_out_s[63:32]), + .gp_out_2 (gp_out_s[95:64]), + .gp_out_3 (), + .gpio_i (gpio_i), + .gpio_o (gpio_o), + .gpio_t (gpio_t), + .gt_ref_clk (gt_ref_clk), + .gt_rx_n (gt_rx_n), + .gt_rx_p (gt_rx_p), + .gt_tx_n (gt_tx_n), + .gt_tx_p (gt_tx_p), + .iic_main_scl_io (iic_scl), + .iic_main_sda_io (iic_sda), + .otg_vbusoc (1'b0), + .ps_intr_00 (1'b0), + .ps_intr_01 (1'b0), + .ps_intr_02 (1'b0), + .ps_intr_03 (1'b0), + .ps_intr_04 (1'b0), + .ps_intr_05 (1'b0), + .ps_intr_06 (1'b0), + .ps_intr_07 (1'b0), + .ps_intr_08 (1'b0), + .ps_intr_09 (1'b0), + .ps_intr_10 (1'b0), + .ps_intr_11 (1'b0), + .ps_intr_15 (1'b0), + .rx_clk_in (rx_clk_in), + .rx_data_in (rx_data_in), + .rx_frame_in (rx_frame_in), + .spi0_clk_i (1'b0), + .spi0_clk_o (spi_clk), + .spi0_csn_0_o (spi_csn), + .spi0_csn_1_o (), + .spi0_csn_2_o (), + .spi0_csn_i (1'b1), + .spi0_sdi_i (spi_miso), + .spi0_sdo_i (1'b0), + .spi0_sdo_o (spi_mosi), + .spi1_clk_i (1'b0), + .spi1_clk_o (), + .spi1_csn_0_o (), + .spi1_csn_1_o (), + .spi1_csn_2_o (), + .spi1_csn_i (1'b1), + .spi1_sdi_i (1'b0), + .spi1_sdo_i (1'b0), + .spi1_sdo_o (), + .tdd_sync_i (1'b0), + .tdd_sync_o (), + .tdd_sync_t (), + .tx_clk_out (tx_clk_out), + .tx_data_out (tx_data_out), + .tx_frame_out (tx_frame_out), + .txnrx (txnrx), + .up_enable (gpio_o[47]), + .up_txnrx (gpio_o[48])); + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/projects/pzsdr2/ccbrk_lvds/Makefile b/projects/pzsdr2/ccbrk_lvds/Makefile new file mode 100644 index 000000000..39c09c96f --- /dev/null +++ b/projects/pzsdr2/ccbrk_lvds/Makefile @@ -0,0 +1,88 @@ +#################################################################################### +#################################################################################### +## Copyright 2011(c) Analog Devices, Inc. +## Auto-generated, do not modify! +#################################################################################### +#################################################################################### + +M_DEPS += system_top.v +M_DEPS += system_project.tcl +M_DEPS += system_bd.tcl +M_DEPS += ../common/pzsdr2_constr_lvds.xdc +M_DEPS += ../common/pzsdr2_constr.xdc +M_DEPS += ../common/pzsdr2_bd.tcl +M_DEPS += ../common/ccbrk_constr.xdc +M_DEPS += ../common/ccbrk_bd.tcl +M_DEPS += ../../scripts/adi_project.tcl +M_DEPS += ../../scripts/adi_env.tcl +M_DEPS += ../../scripts/adi_board.tcl +M_DEPS += ../../../library/xilinx/common/ad_iobuf.v +M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr +M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr +M_DEPS += ../../../library/axi_gpreg/axi_gpreg.xpr +M_DEPS += ../../../library/xilinx/axi_xcvrlb/axi_xcvrlb.xpr +M_DEPS += ../../../library/util_clkdiv/util_clkdiv.xpr +M_DEPS += ../../../library/util_cpack/util_cpack.xpr +M_DEPS += ../../../library/util_rfifo/util_rfifo.xpr +M_DEPS += ../../../library/util_tdd_sync/util_tdd_sync.xpr +M_DEPS += ../../../library/util_upack/util_upack.xpr +M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr + +M_VIVADO := vivado -mode batch -source + +M_FLIST := *.cache +M_FLIST += *.data +M_FLIST += *.xpr +M_FLIST += *.log +M_FLIST += *.jou +M_FLIST += xgui +M_FLIST += *.runs +M_FLIST += *.srcs +M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim +M_FLIST += .Xil +M_FLIST += *.ip_user_files + + + +.PHONY: all lib clean clean-all +all: lib pzsdr2_ccbrk_lvds.sdk/system_top.hdf + + +clean: + rm -rf $(M_FLIST) + + +clean-all:clean + make -C ../../../library/axi_ad9361 clean + make -C ../../../library/axi_dmac clean + make -C ../../../library/axi_gpreg clean + make -C ../../../library/xilinx/axi_xcvrlb clean + make -C ../../../library/util_clkdiv clean + make -C ../../../library/util_cpack clean + make -C ../../../library/util_rfifo clean + make -C ../../../library/util_tdd_sync clean + make -C ../../../library/util_upack clean + make -C ../../../library/util_wfifo clean + + +pzsdr2_ccbrk_lvds.sdk/system_top.hdf: $(M_DEPS) + -rm -rf $(M_FLIST) + $(M_VIVADO) system_project.tcl >> pzsdr2_ccbrk_lvds_vivado.log 2>&1 + + +lib: + make -C ../../../library/axi_ad9361 + make -C ../../../library/axi_dmac + make -C ../../../library/axi_gpreg + make -C ../../../library/xilinx/axi_xcvrlb + make -C ../../../library/util_clkdiv + make -C ../../../library/util_cpack + make -C ../../../library/util_rfifo + make -C ../../../library/util_tdd_sync + make -C ../../../library/util_upack + make -C ../../../library/util_wfifo + +#################################################################################### +#################################################################################### diff --git a/projects/pzsdr2/ccbrk_lvds/system_bd.tcl b/projects/pzsdr2/ccbrk_lvds/system_bd.tcl new file mode 100644 index 000000000..3c050c45d --- /dev/null +++ b/projects/pzsdr2/ccbrk_lvds/system_bd.tcl @@ -0,0 +1,6 @@ + +source ../common/pzsdr2_bd.tcl +source ../common/ccbrk_bd.tcl + +cfg_ad9361_interface LVDS + diff --git a/projects/pzsdr2/ccbrk_lvds/system_project.tcl b/projects/pzsdr2/ccbrk_lvds/system_project.tcl new file mode 100644 index 000000000..8dc9a290f --- /dev/null +++ b/projects/pzsdr2/ccbrk_lvds/system_project.tcl @@ -0,0 +1,18 @@ + +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/projects/scripts/adi_project.tcl +source $ad_hdl_dir/projects/scripts/adi_board.tcl + +set p_device "xc7z035ifbg676-2L" +adi_project_create pzsdr2_ccbrk_lvds +adi_project_files pzsdr2_ccbrk_lvds [list \ + "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \ + "../common/pzsdr2_constr.xdc" \ + "../common/pzsdr2_constr_lvds.xdc" \ + "../common/ccbrk_constr.xdc" \ + "system_top.v" ] + +set_property is_enabled false [get_files *axi_gpreg_constr.xdc] +adi_project_run pzsdr2_ccbrk_lvds + + diff --git a/projects/pzsdr/ccbrk/system_top.v b/projects/pzsdr2/ccbrk_lvds/system_top.v similarity index 62% rename from projects/pzsdr/ccbrk/system_top.v rename to projects/pzsdr2/ccbrk_lvds/system_top.v index 585b2022d..4abf4b607 100644 --- a/projects/pzsdr/ccbrk/system_top.v +++ b/projects/pzsdr2/ccbrk_lvds/system_top.v @@ -39,143 +39,73 @@ module system_top ( - ddr_addr, - ddr_ba, - ddr_cas_n, - ddr_ck_n, - ddr_ck_p, - ddr_cke, - ddr_cs_n, - ddr_dm, - ddr_dq, - ddr_dqs_n, - ddr_dqs_p, - ddr_odt, - ddr_ras_n, - ddr_reset_n, - ddr_we_n, + inout [14:0] ddr_addr, + inout [ 2:0] ddr_ba, + inout ddr_cas_n, + inout ddr_ck_n, + inout ddr_ck_p, + inout ddr_cke, + inout ddr_cs_n, + inout [ 3:0] ddr_dm, + inout [31:0] ddr_dq, + inout [ 3:0] ddr_dqs_n, + inout [ 3:0] ddr_dqs_p, + inout ddr_odt, + inout ddr_ras_n, + inout ddr_reset_n, + inout ddr_we_n, - fixed_io_ddr_vrn, - fixed_io_ddr_vrp, - fixed_io_mio, - fixed_io_ps_clk, - fixed_io_ps_porb, - fixed_io_ps_srstb, + inout fixed_io_ddr_vrn, + inout fixed_io_ddr_vrp, + inout [53:0] fixed_io_mio, + inout fixed_io_ps_clk, + inout fixed_io_ps_porb, + inout fixed_io_ps_srstb, - iic_scl, - iic_sda, + inout iic_scl, + inout iic_sda, - gpio_bd, + inout [19:0] gpio_bd, - rx_clk_in_p, - rx_clk_in_n, - rx_frame_in_p, - rx_frame_in_n, - rx_data_in_p, - rx_data_in_n, - tx_clk_out_p, - tx_clk_out_n, - tx_frame_out_p, - tx_frame_out_n, - tx_data_out_p, - tx_data_out_n, + input rx_clk_in_p, + input rx_clk_in_n, + input rx_frame_in_p, + input rx_frame_in_n, + input [ 5:0] rx_data_in_p, + input [ 5:0] rx_data_in_n, + output tx_clk_out_p, + output tx_clk_out_n, + output tx_frame_out_p, + output tx_frame_out_n, + output [ 5:0] tx_data_out_p, + output [ 5:0] tx_data_out_n, - enable, - txnrx, - clk_out, + output enable, + output txnrx, + input clkout_in, + output clkout_out, - gpio_clksel, - gpio_resetb, - gpio_sync, - gpio_en_agc, - gpio_ctl, - gpio_status, + inout gpio_clksel, + inout gpio_resetb, + inout gpio_sync, + inout gpio_en_agc, + inout [ 3:0] gpio_ctl, + inout [ 7:0] gpio_status, - spi_csn, - spi_clk, - spi_mosi, - spi_miso, + output spi_csn, + output spi_clk, + output spi_mosi, + input spi_miso, - gp_out, - gp_in, - gp_in_mio, - gp_in_1, + output [85:0] gp_out, + input [85:0] gp_in, - gt_ref_clk_p, - gt_ref_clk_n, - gt_tx_p, - gt_tx_n, - gt_rx_p, - gt_rx_n); - - inout [14:0] ddr_addr; - inout [ 2:0] ddr_ba; - inout ddr_cas_n; - inout ddr_ck_n; - inout ddr_ck_p; - inout ddr_cke; - inout ddr_cs_n; - inout [ 3:0] ddr_dm; - inout [31:0] ddr_dq; - inout [ 3:0] ddr_dqs_n; - inout [ 3:0] ddr_dqs_p; - inout ddr_odt; - inout ddr_ras_n; - inout ddr_reset_n; - inout ddr_we_n; - - inout fixed_io_ddr_vrn; - inout fixed_io_ddr_vrp; - inout [53:0] fixed_io_mio; - inout fixed_io_ps_clk; - inout fixed_io_ps_porb; - inout fixed_io_ps_srstb; - - inout iic_scl; - inout iic_sda; - - inout [11:0] gpio_bd; - - input rx_clk_in_p; - input rx_clk_in_n; - input rx_frame_in_p; - input rx_frame_in_n; - input [ 5:0] rx_data_in_p; - input [ 5:0] rx_data_in_n; - output tx_clk_out_p; - output tx_clk_out_n; - output tx_frame_out_p; - output tx_frame_out_n; - output [ 5:0] tx_data_out_p; - output [ 5:0] tx_data_out_n; - - output enable; - output txnrx; - input clk_out; - - inout gpio_clksel; - inout gpio_resetb; - inout gpio_sync; - inout gpio_en_agc; - inout [ 3:0] gpio_ctl; - inout [ 7:0] gpio_status; - - output spi_csn; - output spi_clk; - output spi_mosi; - input spi_miso; - - output [87:0] gp_out; - input [87:0] gp_in; - input [ 3:0] gp_in_mio; - input gp_in_1; - - input gt_ref_clk_p; - input gt_ref_clk_n; - output [ 3:0] gt_tx_p; - output [ 3:0] gt_tx_n; - input [ 3:0] gt_rx_p; - input [ 3:0] gt_rx_n; + input gt_ref_clk_p, + input gt_ref_clk_n, + output [ 3:0] gt_tx_p, + output [ 3:0] gt_tx_n, + input [ 3:0] gt_rx_p, + input [ 3:0] gt_rx_n); // internal signals @@ -188,14 +118,10 @@ module system_top ( // assignments - assign gp_out[87:43] = gp_out_s[87:43]; - assign gp_out[42:42] = (gpio_o[61] == 1'b1) ? clk_out : gp_out_s[42:42]; - assign gp_out[41: 0] = gp_out_s[41: 0]; - - assign gp_in_s[95:93] = 3'd0; - assign gp_in_s[92:92] = gp_in_1; - assign gp_in_s[91:88] = gp_in_mio; - assign gp_in_s[87: 0] = gp_in; + assign clkout_out = clkout_in; + assign gp_out[85:0] = gp_out_s[85:0]; + assign gp_in_s[95:86] = gp_out_s[95:86]; + assign gp_in_s[85: 0] = gp_in[85:0]; // instantiations @@ -206,6 +132,21 @@ module system_top ( .O (gt_ref_clk), .ODIV2 ()); + // board gpio - 31-0 + + assign gpio_i[31:20] = gpio_o[31:20]; + + ad_iobuf #(.DATA_WIDTH(20)) i_iobuf_bd ( + .dio_t (gpio_t[19:0]), + .dio_i (gpio_o[19:0]), + .dio_o (gpio_i[19:0]), + .dio_p (gpio_bd)); + + // ad9361 gpio - 63-32 + + assign gpio_i[63:52] = gpio_o[63:52]; + assign gpio_i[50:47] = gpio_o[50:47]; + ad_iobuf #(.DATA_WIDTH(16)) i_iobuf ( .dio_t ({gpio_t[51], gpio_t[46:32]}), .dio_i ({gpio_o[51], gpio_o[46:32]}), @@ -217,11 +158,7 @@ module system_top ( gpio_ctl, // 43:40 gpio_status})); // 39:32 - ad_iobuf #(.DATA_WIDTH(12)) i_iobuf_bd ( - .dio_t (gpio_t[11:0]), - .dio_i (gpio_o[11:0]), - .dio_o (gpio_i[11:0]), - .dio_p (gpio_bd)); + // instantiations system_wrapper i_system_wrapper ( .ddr_addr (ddr_addr), @@ -249,29 +186,19 @@ module system_top ( .gp_in_0 (gp_in_s[31:0]), .gp_in_1 (gp_in_s[63:32]), .gp_in_2 (gp_in_s[95:64]), + .gp_in_3 (32'd0), .gp_out_0 (gp_out_s[31:0]), .gp_out_1 (gp_out_s[63:32]), .gp_out_2 (gp_out_s[95:64]), + .gp_out_3 (), .gpio_i (gpio_i), .gpio_o (gpio_o), .gpio_t (gpio_t), .gt_ref_clk (gt_ref_clk), - .gt_rx_0_n (gt_rx_n[0]), - .gt_rx_0_p (gt_rx_p[0]), - .gt_rx_1_n (gt_rx_n[1]), - .gt_rx_1_p (gt_rx_p[1]), - .gt_rx_2_n (gt_rx_n[2]), - .gt_rx_2_p (gt_rx_p[2]), - .gt_rx_3_n (gt_rx_n[3]), - .gt_rx_3_p (gt_rx_p[3]), - .gt_tx_0_n (gt_tx_n[0]), - .gt_tx_0_p (gt_tx_p[0]), - .gt_tx_1_n (gt_tx_n[1]), - .gt_tx_1_p (gt_tx_p[1]), - .gt_tx_2_n (gt_tx_n[2]), - .gt_tx_2_p (gt_tx_p[2]), - .gt_tx_3_n (gt_tx_n[3]), - .gt_tx_3_p (gt_tx_p[3]), + .gt_rx_n (gt_rx_n), + .gt_rx_p (gt_rx_p), + .gt_tx_n (gt_tx_n), + .gt_tx_p (gt_tx_p), .iic_main_scl_io (iic_scl), .iic_main_sda_io (iic_sda), .otg_vbusoc (1'b0), diff --git a/projects/pzsdr/ccfmc/Makefile b/projects/pzsdr2/ccfmc_lvds/Makefile similarity index 75% rename from projects/pzsdr/ccfmc/Makefile rename to projects/pzsdr2/ccfmc_lvds/Makefile index aa9dfe4fb..4e53bec3e 100644 --- a/projects/pzsdr/ccfmc/Makefile +++ b/projects/pzsdr2/ccfmc_lvds/Makefile @@ -7,28 +7,27 @@ M_DEPS += system_top.v M_DEPS += system_project.tcl -M_DEPS += system_constr.xdc M_DEPS += system_bd.tcl +M_DEPS += ../common/pzsdr2_constr_lvds.xdc +M_DEPS += ../common/pzsdr2_constr.xdc +M_DEPS += ../common/pzsdr2_bd.tcl +M_DEPS += ../common/ccfmc_constr.xdc M_DEPS += ../common/ccfmc_bd.tcl M_DEPS += ../../scripts/adi_project.tcl M_DEPS += ../../scripts/adi_env.tcl M_DEPS += ../../scripts/adi_board.tcl -M_DEPS += ../../fmcomms2/common/fmcomms2_bd.tcl -M_DEPS += ../../common/xilinx/sys_wfifo.tcl -M_DEPS += ../../common/pzsdr/pzsdr_system_ps7.tcl -M_DEPS += ../../common/pzsdr/pzsdr_system_constr.xdc -M_DEPS += ../../common/pzsdr/pzsdr_system_bd.tcl -M_DEPS += ../../../library/common/ad_iobuf.v +M_DEPS += ../../../library/xilinx/common/ad_iobuf.v M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr M_DEPS += ../../../library/axi_gpreg/axi_gpreg.xpr M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr M_DEPS += ../../../library/axi_i2s_adi/axi_i2s_adi.xpr -M_DEPS += ../../../library/axi_jesd_gt/axi_jesd_gt.xpr M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr +M_DEPS += ../../../library/xilinx/axi_xcvrlb/axi_xcvrlb.xpr +M_DEPS += ../../../library/util_clkdiv/util_clkdiv.xpr M_DEPS += ../../../library/util_cpack/util_cpack.xpr -M_DEPS += ../../../library/util_gtlb/util_gtlb.xpr +M_DEPS += ../../../library/util_rfifo/util_rfifo.xpr M_DEPS += ../../../library/util_tdd_sync/util_tdd_sync.xpr M_DEPS += ../../../library/util_upack/util_upack.xpr M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr @@ -47,11 +46,12 @@ M_FLIST += *.sdk M_FLIST += *.hw M_FLIST += *.sim M_FLIST += .Xil +M_FLIST += *.ip_user_files .PHONY: all lib clean clean-all -all: lib ccfmc_pzsdr.sdk/system_top.hdf +all: lib pzsdr2_ccfmc_lvds.sdk/system_top.hdf clean: @@ -65,18 +65,19 @@ clean-all:clean make -C ../../../library/axi_gpreg clean make -C ../../../library/axi_hdmi_tx clean make -C ../../../library/axi_i2s_adi clean - make -C ../../../library/axi_jesd_gt clean make -C ../../../library/axi_spdif_tx clean + make -C ../../../library/xilinx/axi_xcvrlb clean + make -C ../../../library/util_clkdiv clean make -C ../../../library/util_cpack clean - make -C ../../../library/util_gtlb clean + make -C ../../../library/util_rfifo clean make -C ../../../library/util_tdd_sync clean make -C ../../../library/util_upack clean make -C ../../../library/util_wfifo clean -ccfmc_pzsdr.sdk/system_top.hdf: $(M_DEPS) - rm -rf $(M_FLIST) - $(M_VIVADO) system_project.tcl >> ccfmc_pzsdr_vivado.log 2>&1 +pzsdr2_ccfmc_lvds.sdk/system_top.hdf: $(M_DEPS) + -rm -rf $(M_FLIST) + $(M_VIVADO) system_project.tcl >> pzsdr2_ccfmc_lvds_vivado.log 2>&1 lib: @@ -86,10 +87,11 @@ lib: make -C ../../../library/axi_gpreg make -C ../../../library/axi_hdmi_tx make -C ../../../library/axi_i2s_adi - make -C ../../../library/axi_jesd_gt make -C ../../../library/axi_spdif_tx + make -C ../../../library/xilinx/axi_xcvrlb + make -C ../../../library/util_clkdiv make -C ../../../library/util_cpack - make -C ../../../library/util_gtlb + make -C ../../../library/util_rfifo make -C ../../../library/util_tdd_sync make -C ../../../library/util_upack make -C ../../../library/util_wfifo diff --git a/projects/pzsdr2/ccfmc_lvds/system_bd.tcl b/projects/pzsdr2/ccfmc_lvds/system_bd.tcl new file mode 100644 index 000000000..536e84f12 --- /dev/null +++ b/projects/pzsdr2/ccfmc_lvds/system_bd.tcl @@ -0,0 +1,6 @@ + +source ../common/pzsdr2_bd.tcl +source ../common/ccfmc_bd.tcl + +cfg_ad9361_interface LVDS + diff --git a/projects/pzsdr2/ccfmc_lvds/system_project.tcl b/projects/pzsdr2/ccfmc_lvds/system_project.tcl new file mode 100644 index 000000000..12d00b4ab --- /dev/null +++ b/projects/pzsdr2/ccfmc_lvds/system_project.tcl @@ -0,0 +1,17 @@ + +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/projects/scripts/adi_project.tcl +source $ad_hdl_dir/projects/scripts/adi_board.tcl + +set p_device "xc7z035ifbg676-2L" +adi_project_create pzsdr2_ccfmc_lvds +adi_project_files pzsdr2_ccfmc_lvds [list \ + "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \ + "../common/pzsdr2_constr.xdc" \ + "../common/pzsdr2_constr_lvds.xdc" \ + "../common/ccfmc_constr.xdc" \ + "system_top.v" ] + +adi_project_run pzsdr2_ccfmc_lvds + + diff --git a/projects/pzsdr/ccfmc/system_top.v b/projects/pzsdr2/ccfmc_lvds/system_top.v similarity index 54% rename from projects/pzsdr/ccfmc/system_top.v rename to projects/pzsdr2/ccfmc_lvds/system_top.v index 7283406a5..8c8c9f891 100644 --- a/projects/pzsdr/ccfmc/system_top.v +++ b/projects/pzsdr2/ccfmc_lvds/system_top.v @@ -39,248 +39,123 @@ module system_top ( - ddr_addr, - ddr_ba, - ddr_cas_n, - ddr_ck_n, - ddr_ck_p, - ddr_cke, - ddr_cs_n, - ddr_dm, - ddr_dq, - ddr_dqs_n, - ddr_dqs_p, - ddr_odt, - ddr_ras_n, - ddr_reset_n, - ddr_we_n, + inout [14:0] ddr_addr, + inout [ 2:0] ddr_ba, + inout ddr_cas_n, + inout ddr_ck_n, + inout ddr_ck_p, + inout ddr_cke, + inout ddr_cs_n, + inout [ 3:0] ddr_dm, + inout [31:0] ddr_dq, + inout [ 3:0] ddr_dqs_n, + inout [ 3:0] ddr_dqs_p, + inout ddr_odt, + inout ddr_ras_n, + inout ddr_reset_n, + inout ddr_we_n, - eth1_mdc, - eth1_mdio, - eth1_rgmii_rxclk, - eth1_rgmii_rxctl, - eth1_rgmii_rxdata, - eth1_rgmii_txclk, - eth1_rgmii_txctl, - eth1_rgmii_txdata, + output eth1_mdc, + inout eth1_mdio, + input eth1_rgmii_rxclk, + input eth1_rgmii_rxctl, + input [ 3:0] eth1_rgmii_rxdata, + output eth1_rgmii_txclk, + output eth1_rgmii_txctl, + output [ 3:0] eth1_rgmii_txdata, - fixed_io_ddr_vrn, - fixed_io_ddr_vrp, - fixed_io_mio, - fixed_io_ps_clk, - fixed_io_ps_porb, - fixed_io_ps_srstb, + inout fixed_io_ddr_vrn, + inout fixed_io_ddr_vrp, + inout [53:0] fixed_io_mio, + inout fixed_io_ps_clk, + inout fixed_io_ps_porb, + inout fixed_io_ps_srstb, - hdmi_out_clk, - hdmi_vsync, - hdmi_hsync, - hdmi_data_e, - hdmi_data, - hdmi_pd, - hdmi_intn, + output hdmi_out_clk, + output hdmi_vsync, + output hdmi_hsync, + output hdmi_data_e, + output [15:0] hdmi_data, + output hdmi_pd, + input hdmi_intn, - spdif, - spdif_in, + output spdif, + input spdif_in, - i2s_mclk, - i2s_bclk, - i2s_lrclk, - i2s_sdata_out, - i2s_sdata_in, + output i2s_mclk, + output i2s_bclk, + output i2s_lrclk, + output i2s_sdata_out, + input i2s_sdata_in, - iic_scl, - iic_sda, + inout iic_scl, + inout iic_sda, - gpio_bd, + inout [20:0] gpio_bd, - clk_0_p, - clk_0_n, - clk_1_p, - clk_1_n, - gp_in_0, - gp_out_0, - gp_inout_0, - gp_inout_1, - gp_out, - gp_in, + output fan_pwm, + input fan_tach, - gt_ref_clk_0_p, - gt_ref_clk_0_n, - gt_ref_clk_1_p, - gt_ref_clk_1_n, - gt_tx_0_p, - gt_tx_0_n, - gt_rx_0_p, - gt_rx_0_n, - gt_tx_1_p, - gt_tx_1_n, - gt_rx_1_p, - gt_rx_1_n, + input clk_0_p, + input clk_0_n, + input clk_1_p, + input clk_1_n, + output [53:0] gp_out, + input [53:0] gp_in, - ad9517_csn, - ad9517_clk, - ad9517_mosi, - ad9517_miso, - ad9517_pdn, - ad9517_ref_sel, - ad9517_ld, - ad9517_status, + input gt_ref_clk_0_p, + input gt_ref_clk_0_n, + input gt_ref_clk_1_p, + input gt_ref_clk_1_n, + output [ 1:0] gt_tx_p, + output [ 1:0] gt_tx_n, + input [ 1:0] gt_rx_p, + input [ 1:0] gt_rx_n, - rx_clk_in_p, - rx_clk_in_n, - rx_frame_in_p, - rx_frame_in_n, - rx_data_in_p, - rx_data_in_n, - tx_clk_out_p, - tx_clk_out_n, - tx_frame_out_p, - tx_frame_out_n, - tx_data_out_p, - tx_data_out_n, + output ad9517_csn, + output ad9517_clk, + output ad9517_mosi, + input ad9517_miso, + inout ad9517_pdn, + inout ad9517_ref_sel, + inout ad9517_ld, + inout ad9517_status, - enable, - txnrx, - clk_out, + input rx_clk_in_p, + input rx_clk_in_n, + input rx_frame_in_p, + input rx_frame_in_n, + input [ 5:0] rx_data_in_p, + input [ 5:0] rx_data_in_n, + output tx_clk_out_p, + output tx_clk_out_n, + output tx_frame_out_p, + output tx_frame_out_n, + output [ 5:0] tx_data_out_p, + output [ 5:0] tx_data_out_n, - gpio_rf0, - gpio_rf1, - gpio_rf2, - gpio_rf3, - gpio_rfpwr_enable, - gpio_clksel, - gpio_resetb, - gpio_sync, - gpio_en_agc, - gpio_ctl, - gpio_status, + output enable, + output txnrx, + input clkout_in, + inout tdd_sync, - spi_csn, - spi_clk, - spi_mosi, - spi_miso); + inout gpio_rf0, + inout gpio_rf1, + inout gpio_rf2, + inout gpio_rf3, + inout gpio_rf4, + inout gpio_rfpwr_enable, + inout gpio_clksel, + inout gpio_resetb, + inout gpio_sync, + inout gpio_en_agc, + inout [ 3:0] gpio_ctl, + inout [ 7:0] gpio_status, - - inout [14:0] ddr_addr; - inout [ 2:0] ddr_ba; - inout ddr_cas_n; - inout ddr_ck_n; - inout ddr_ck_p; - inout ddr_cke; - inout ddr_cs_n; - inout [ 3:0] ddr_dm; - inout [31:0] ddr_dq; - inout [ 3:0] ddr_dqs_n; - inout [ 3:0] ddr_dqs_p; - inout ddr_odt; - inout ddr_ras_n; - inout ddr_reset_n; - inout ddr_we_n; - - output eth1_mdc; - inout eth1_mdio; - input eth1_rgmii_rxclk; - input eth1_rgmii_rxctl; - input [ 3:0] eth1_rgmii_rxdata; - output eth1_rgmii_txclk; - output eth1_rgmii_txctl; - output [ 3:0] eth1_rgmii_txdata; - - inout fixed_io_ddr_vrn; - inout fixed_io_ddr_vrp; - inout [53:0] fixed_io_mio; - inout fixed_io_ps_clk; - inout fixed_io_ps_porb; - inout fixed_io_ps_srstb; - - output hdmi_out_clk; - output hdmi_vsync; - output hdmi_hsync; - output hdmi_data_e; - output [15:0] hdmi_data; - output hdmi_pd; - input hdmi_intn; - - output spdif; - input spdif_in; - - output i2s_mclk; - output i2s_bclk; - output i2s_lrclk; - output i2s_sdata_out; - input i2s_sdata_in; - - inout iic_scl; - inout iic_sda; - - inout [11:0] gpio_bd; - - input clk_0_p; - input clk_0_n; - input clk_1_p; - input clk_1_n; - input gp_in_0; - output gp_out_0; - inout gp_inout_0; - inout gp_inout_1; - output [56:0] gp_out; - input [56:0] gp_in; - - input gt_ref_clk_0_p; - input gt_ref_clk_0_n; - input gt_ref_clk_1_p; - input gt_ref_clk_1_n; - output gt_tx_0_p; - output gt_tx_0_n; - input gt_rx_0_p; - input gt_rx_0_n; - output gt_tx_1_p; - output gt_tx_1_n; - input gt_rx_1_p; - input gt_rx_1_n; - - output ad9517_csn; - output ad9517_clk; - output ad9517_mosi; - input ad9517_miso; - inout ad9517_pdn; - inout ad9517_ref_sel; - inout ad9517_ld; - inout ad9517_status; - - input rx_clk_in_p; - input rx_clk_in_n; - input rx_frame_in_p; - input rx_frame_in_n; - input [ 5:0] rx_data_in_p; - input [ 5:0] rx_data_in_n; - output tx_clk_out_p; - output tx_clk_out_n; - output tx_frame_out_p; - output tx_frame_out_n; - output [ 5:0] tx_data_out_p; - output [ 5:0] tx_data_out_n; - - output enable; - output txnrx; - input clk_out; - - inout gpio_rf0; - inout gpio_rf1; - inout gpio_rf2; - inout gpio_rf3; - inout gpio_rfpwr_enable; - inout gpio_clksel; - inout gpio_resetb; - inout gpio_sync; - inout gpio_en_agc; - inout [ 3:0] gpio_ctl; - inout [ 7:0] gpio_status; - - output spi_csn; - output spi_clk; - output spi_mosi; - input spi_miso; + output spi_csn, + output spi_clk, + output spi_mosi, + input spi_miso); // internal signals @@ -290,8 +165,8 @@ module system_top ( wire spi_miso_s; wire clk_0; wire clk_1; - wire gt_ref_clk_0; wire gt_ref_clk_1; + wire gt_ref_clk_0; wire [63:0] gp_out_s; wire [63:0] gp_in_s; wire [63:0] gpio_i; @@ -303,6 +178,7 @@ module system_top ( // assignments + assign fan_pwm = 1'b1; assign hdmi_pd = 1'b0; assign spi_csn = spi_csn_s[0]; assign spi_clk = spi_clk_s; @@ -312,6 +188,12 @@ module system_top ( assign ad9517_mosi = spi_mosi_s; assign spi_miso_s = (~spi_csn_s[0] & spi_miso) | (~spi_csn_s[1] & ad9517_miso); + // loopback signals + + assign gp_out[53:0] = gp_out_s[53:0]; + assign gp_in_s[63:54] = gp_out_s[63:54]; + assign gp_in_s[53:0] = gp_in[53:0]; + // instantiations IBUFDS i_ibufds_clk_0 ( @@ -338,37 +220,33 @@ module system_top ( .O (gt_ref_clk_1), .ODIV2 ()); - assign gp_out_0 = gp_out_s[58:58]; - assign gp_out[56:35] = gp_out_s[57:36]; - assign gp_out[34: 0] = gp_out_s[34: 0]; + ad_iobuf #(.DATA_WIDTH(1)) i_iobuf_tdd_sync ( + .dio_t (tdd_sync_t), + .dio_i (tdd_sync_o), + .dio_o (tdd_sync_i), + .dio_p (tdd_sync)); - assign gp_in_s[63:63] = gp_in_0; - assign gp_in_s[58:58] = 1'd0; - assign gp_in_s[57:36] = gp_in[56:35]; - assign gp_in_s[35:35] = gp_out_s[62] & gpio_tdd_sync_i; - assign gp_in_s[34: 0] = gp_in[34: 0]; + // board gpio - 31-0 - ad_iobuf #(.DATA_WIDTH(1)) i_iobuf_35_0 ( - .dio_t (1'b0), - .dio_i (gp_out_s[35]), - .dio_o (), - .dio_p (gp_inout_0)); + assign gpio_i[31:21] = gpio_o[31:21]; - ad_iobuf #(.DATA_WIDTH(1)) i_iobuf_35_1 ( - .dio_t (gpio_tdd_sync_t), - .dio_i (gpio_tdd_sync_o), - .dio_o (gpio_tdd_sync_i), - .dio_p (gp_inout_1)); + ad_iobuf #(.DATA_WIDTH(21)) i_iobuf_bd ( + .dio_t (gpio_t[20:0]), + .dio_i (gpio_o[20:0]), + .dio_o (gpio_i[20:0]), + .dio_p (gpio_bd)); - assign gpio_tdd_sync_t = gp_out_s[62] | tdd_sync_t; - assign gpio_tdd_sync_o = gp_out_s[62] | tdd_sync_o; - assign tdd_sync_i = ~gp_out_s[62] & gpio_tdd_sync_i; + // ad9361 gpio - 63-32 - ad_iobuf #(.DATA_WIDTH(25)) i_iobuf ( - .dio_t ({gpio_t[60:51], gpio_t[46:32]}), - .dio_i ({gpio_o[60:51], gpio_o[46:32]}), - .dio_o ({gpio_i[60:51], gpio_i[46:32]}), - .dio_p ({ ad9517_pdn, // 60:60 + assign gpio_i[63:62] = gpio_o[63:62]; + assign gpio_i[50:47] = gpio_o[50:47]; + + ad_iobuf #(.DATA_WIDTH(26)) i_iobuf ( + .dio_t ({gpio_t[61:51], gpio_t[46:32]}), + .dio_i ({gpio_o[61:51], gpio_o[46:32]}), + .dio_o ({gpio_i[61:51], gpio_i[46:32]}), + .dio_p ({ gpio_rf4, // 61:61 + ad9517_pdn, // 60:60 ad9517_ref_sel, // 59:59 ad9517_ld, // 58:58 ad9517_status, // 57:57 @@ -384,11 +262,7 @@ module system_top ( gpio_ctl, // 43:40 gpio_status})); // 39:32 - ad_iobuf #(.DATA_WIDTH(12)) i_iobuf_bd ( - .dio_t (gpio_t[11:0]), - .dio_i (gpio_o[11:0]), - .dio_o (gpio_i[11:0]), - .dio_p (gpio_bd)); + // instantiations system_wrapper i_system_wrapper ( .clk_0 (clk_0), @@ -409,23 +283,15 @@ module system_top ( .ddr_reset_n (ddr_reset_n), .ddr_we_n (ddr_we_n), .enable (enable), - .eth1_125mclk (), - .eth1_25mclk (), - .eth1_2m5clk (), - .eth1_clock_speed (), - .eth1_duplex_status (), .eth1_intn (1'b1), - .eth1_link_status (), .eth1_mdio_mdc (eth1_mdc), .eth1_mdio_mdio_io (eth1_mdio), - .eth1_refclk (), .eth1_rgmii_rd (eth1_rgmii_rxdata), .eth1_rgmii_rx_ctl (eth1_rgmii_rxctl), .eth1_rgmii_rxc (eth1_rgmii_rxclk), .eth1_rgmii_td (eth1_rgmii_txdata), .eth1_rgmii_tx_ctl (eth1_rgmii_txctl), .eth1_rgmii_txc (eth1_rgmii_txclk), - .eth1_speed_mode (), .fixed_io_ddr_vrn (fixed_io_ddr_vrn), .fixed_io_ddr_vrp (fixed_io_ddr_vrp), .fixed_io_mio (fixed_io_mio), @@ -441,14 +307,10 @@ module system_top ( .gpio_t (gpio_t), .gt_ref_clk_0 (gt_ref_clk_0), .gt_ref_clk_1 (gt_ref_clk_1), - .gt_rx_0_n (gt_rx_0_n), - .gt_rx_0_p (gt_rx_0_p), - .gt_rx_1_n (gt_rx_1_n), - .gt_rx_1_p (gt_rx_1_p), - .gt_tx_0_n (gt_tx_0_n), - .gt_tx_0_p (gt_tx_0_p), - .gt_tx_1_n (gt_tx_1_n), - .gt_tx_1_p (gt_tx_1_p), + .gt_rx_n (gt_rx_n), + .gt_rx_p (gt_rx_p), + .gt_tx_n (gt_tx_n), + .gt_tx_p (gt_tx_p), .hdmi_data (hdmi_data), .hdmi_data_e (hdmi_data_e), .hdmi_hsync (hdmi_hsync), diff --git a/projects/fmcomms1/kc705/Makefile b/projects/pzsdr2/ccpci_lvds/Makefile similarity index 62% rename from projects/fmcomms1/kc705/Makefile rename to projects/pzsdr2/ccpci_lvds/Makefile index 5d00e2573..593b2cd47 100644 --- a/projects/fmcomms1/kc705/Makefile +++ b/projects/pzsdr2/ccpci_lvds/Makefile @@ -7,20 +7,22 @@ M_DEPS += system_top.v M_DEPS += system_project.tcl -M_DEPS += system_constr.xdc M_DEPS += system_bd.tcl -M_DEPS += ../common/fmcomms1_bd.tcl +M_DEPS += ../common/pzsdr2_constr_lvds.xdc +M_DEPS += ../common/pzsdr2_constr.xdc +M_DEPS += ../common/pzsdr2_bd.tcl +M_DEPS += ../common/ccpci_constr.xdc +M_DEPS += ../common/ccpci_bd.tcl M_DEPS += ../../scripts/adi_project.tcl M_DEPS += ../../scripts/adi_env.tcl M_DEPS += ../../scripts/adi_board.tcl -M_DEPS += ../../common/kc705/kc705_system_mig.prj -M_DEPS += ../../common/kc705/kc705_system_constr.xdc -M_DEPS += ../../common/kc705/kc705_system_bd.tcl -M_DEPS += ../../../library/common/ad_iobuf.v -M_DEPS += ../../../library/axi_ad9122/axi_ad9122.xpr -M_DEPS += ../../../library/axi_ad9643/axi_ad9643.xpr +M_DEPS += ../../../library/xilinx/common/ad_iobuf.v +M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr +M_DEPS += ../../../library/util_clkdiv/util_clkdiv.xpr M_DEPS += ../../../library/util_cpack/util_cpack.xpr +M_DEPS += ../../../library/util_rfifo/util_rfifo.xpr +M_DEPS += ../../../library/util_tdd_sync/util_tdd_sync.xpr M_DEPS += ../../../library/util_upack/util_upack.xpr M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr @@ -38,11 +40,12 @@ M_FLIST += *.sdk M_FLIST += *.hw M_FLIST += *.sim M_FLIST += .Xil +M_FLIST += *.ip_user_files .PHONY: all lib clean clean-all -all: lib fmcomms1_kc705.sdk/system_top.hdf +all: lib pzsdr2_ccpci_lvds.sdk/system_top.hdf clean: @@ -50,24 +53,28 @@ clean: clean-all:clean - make -C ../../../library/axi_ad9122 clean - make -C ../../../library/axi_ad9643 clean + make -C ../../../library/axi_ad9361 clean make -C ../../../library/axi_dmac clean + make -C ../../../library/util_clkdiv clean make -C ../../../library/util_cpack clean + make -C ../../../library/util_rfifo clean + make -C ../../../library/util_tdd_sync clean make -C ../../../library/util_upack clean make -C ../../../library/util_wfifo clean -fmcomms1_kc705.sdk/system_top.hdf: $(M_DEPS) - rm -rf $(M_FLIST) - $(M_VIVADO) system_project.tcl >> fmcomms1_kc705_vivado.log 2>&1 +pzsdr2_ccpci_lvds.sdk/system_top.hdf: $(M_DEPS) + -rm -rf $(M_FLIST) + $(M_VIVADO) system_project.tcl >> pzsdr2_ccpci_lvds_vivado.log 2>&1 lib: - make -C ../../../library/axi_ad9122 - make -C ../../../library/axi_ad9643 + make -C ../../../library/axi_ad9361 make -C ../../../library/axi_dmac + make -C ../../../library/util_clkdiv make -C ../../../library/util_cpack + make -C ../../../library/util_rfifo + make -C ../../../library/util_tdd_sync make -C ../../../library/util_upack make -C ../../../library/util_wfifo diff --git a/projects/pzsdr2/ccpci_lvds/system_bd.tcl b/projects/pzsdr2/ccpci_lvds/system_bd.tcl new file mode 100644 index 000000000..fba5d9aa3 --- /dev/null +++ b/projects/pzsdr2/ccpci_lvds/system_bd.tcl @@ -0,0 +1,36 @@ + +source ../common/pzsdr2_bd.tcl +source ../common/ccpci_bd.tcl + +## core digital interface -- cmos (1) or lvds (0) + +set_property CONFIG.CMOS_OR_LVDS_N 0 [get_bd_cells axi_ad9361] + +create_bd_port -dir I rx_clk_in_p +create_bd_port -dir I rx_clk_in_n +create_bd_port -dir I rx_frame_in_p +create_bd_port -dir I rx_frame_in_n +create_bd_port -dir I -from 5 -to 0 rx_data_in_p +create_bd_port -dir I -from 5 -to 0 rx_data_in_n + +create_bd_port -dir O tx_clk_out_p +create_bd_port -dir O tx_clk_out_n +create_bd_port -dir O tx_frame_out_p +create_bd_port -dir O tx_frame_out_n +create_bd_port -dir O -from 5 -to 0 tx_data_out_p +create_bd_port -dir O -from 5 -to 0 tx_data_out_n + +ad_connect rx_clk_in_p axi_ad9361/rx_clk_in_p +ad_connect rx_clk_in_n axi_ad9361/rx_clk_in_n +ad_connect rx_frame_in_p axi_ad9361/rx_frame_in_p +ad_connect rx_frame_in_n axi_ad9361/rx_frame_in_n +ad_connect rx_data_in_p axi_ad9361/rx_data_in_p +ad_connect rx_data_in_n axi_ad9361/rx_data_in_n +ad_connect tx_clk_out_p axi_ad9361/tx_clk_out_p +ad_connect tx_clk_out_n axi_ad9361/tx_clk_out_n +ad_connect tx_frame_out_p axi_ad9361/tx_frame_out_p +ad_connect tx_frame_out_n axi_ad9361/tx_frame_out_n +ad_connect tx_data_out_p axi_ad9361/tx_data_out_p +ad_connect tx_data_out_n axi_ad9361/tx_data_out_n + + diff --git a/projects/pzsdr2/ccpci_lvds/system_project.tcl b/projects/pzsdr2/ccpci_lvds/system_project.tcl new file mode 100644 index 000000000..7922fb931 --- /dev/null +++ b/projects/pzsdr2/ccpci_lvds/system_project.tcl @@ -0,0 +1,17 @@ + +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/projects/scripts/adi_project.tcl +source $ad_hdl_dir/projects/scripts/adi_board.tcl + +set p_device "xc7z035ifbg676-2L" +adi_project_create pzsdr2_ccpci_lvds +adi_project_files pzsdr2_ccpci_lvds [list \ + "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \ + "../common/pzsdr2_constr.xdc" \ + "../common/pzsdr2_constr_lvds.xdc" \ + "../common/ccpci_constr.xdc" \ + "system_top.v" ] + +adi_project_run pzsdr2_ccpci_lvds + + diff --git a/projects/pzsdr/ccpci/system_top.v b/projects/pzsdr2/ccpci_lvds/system_top.v similarity index 63% rename from projects/pzsdr/ccpci/system_top.v rename to projects/pzsdr2/ccpci_lvds/system_top.v index d3ebba2ff..aa610357b 100644 --- a/projects/pzsdr/ccpci/system_top.v +++ b/projects/pzsdr2/ccpci_lvds/system_top.v @@ -39,147 +39,81 @@ module system_top ( - ddr_addr, - ddr_ba, - ddr_cas_n, - ddr_ck_n, - ddr_ck_p, - ddr_cke, - ddr_cs_n, - ddr_dm, - ddr_dq, - ddr_dqs_n, - ddr_dqs_p, - ddr_odt, - ddr_ras_n, - ddr_reset_n, - ddr_we_n, + inout [14:0] ddr_addr, + inout [ 2:0] ddr_ba, + inout ddr_cas_n, + inout ddr_ck_n, + inout ddr_ck_p, + inout ddr_cke, + inout ddr_cs_n, + inout [ 3:0] ddr_dm, + inout [31:0] ddr_dq, + inout [ 3:0] ddr_dqs_n, + inout [ 3:0] ddr_dqs_p, + inout ddr_odt, + inout ddr_ras_n, + inout ddr_reset_n, + inout ddr_we_n, - fixed_io_ddr_vrn, - fixed_io_ddr_vrp, - fixed_io_mio, - fixed_io_ps_clk, - fixed_io_ps_porb, - fixed_io_ps_srstb, + inout fixed_io_ddr_vrn, + inout fixed_io_ddr_vrp, + inout [53:0] fixed_io_mio, + inout fixed_io_ps_clk, + inout fixed_io_ps_porb, + inout fixed_io_ps_srstb, - iic_scl, - iic_sda, + inout iic_scl, + inout iic_sda, - gpio_bd, + input rx_clk_in_p, + input rx_clk_in_n, + input rx_frame_in_p, + input rx_frame_in_n, + input [ 5:0] rx_data_in_p, + input [ 5:0] rx_data_in_n, + output tx_clk_out_p, + output tx_clk_out_n, + output tx_frame_out_p, + output tx_frame_out_n, + output [ 5:0] tx_data_out_p, + output [ 5:0] tx_data_out_n, - rx_clk_in_p, - rx_clk_in_n, - rx_frame_in_p, - rx_frame_in_n, - rx_data_in_p, - rx_data_in_n, - tx_clk_out_p, - tx_clk_out_n, - tx_frame_out_p, - tx_frame_out_n, - tx_data_out_p, - tx_data_out_n, + output enable, + output txnrx, + input clkout_in, - enable, - txnrx, - clk_out, + inout gpio_clksel, + inout gpio_resetb, + inout gpio_sync, + inout gpio_en_agc, + inout [ 3:0] gpio_ctl, + inout [ 7:0] gpio_status, - gpio_clksel, - gpio_resetb, - gpio_sync, - gpio_en_agc, - gpio_ctl, - gpio_status, + output spi_csn, + output spi_clk, + output spi_mosi, + input spi_miso, - spi_csn, - spi_clk, - spi_mosi, - spi_miso, + input pcie_rstn, + inout pcie_waken, + input pcie_ref_clk_p, + input pcie_ref_clk_n, + input [ 3:0] pcie_data_rx_p, + input [ 3:0] pcie_data_rx_n, + output [ 3:0] pcie_data_tx_p, + output [ 3:0] pcie_data_tx_n, - pcie_rstn, - pcie_prsntn, - pcie_prsnt1n, - pcie_prsnt4n, - pcie_waken, - pcie_ref_clk_p, - pcie_ref_clk_n, - pcie_data_rx_p, - pcie_data_rx_n, - pcie_data_tx_p, - pcie_data_tx_n); + output pcie_reset_done); - inout [14:0] ddr_addr; - inout [ 2:0] ddr_ba; - inout ddr_cas_n; - inout ddr_ck_n; - inout ddr_ck_p; - inout ddr_cke; - inout ddr_cs_n; - inout [ 3:0] ddr_dm; - inout [31:0] ddr_dq; - inout [ 3:0] ddr_dqs_n; - inout [ 3:0] ddr_dqs_p; - inout ddr_odt; - inout ddr_ras_n; - inout ddr_reset_n; - inout ddr_we_n; + // internal registers - inout fixed_io_ddr_vrn; - inout fixed_io_ddr_vrp; - inout [53:0] fixed_io_mio; - inout fixed_io_ps_clk; - inout fixed_io_ps_porb; - inout fixed_io_ps_srstb; - - inout iic_scl; - inout iic_sda; - - inout [11:0] gpio_bd; - - input rx_clk_in_p; - input rx_clk_in_n; - input rx_frame_in_p; - input rx_frame_in_n; - input [ 5:0] rx_data_in_p; - input [ 5:0] rx_data_in_n; - output tx_clk_out_p; - output tx_clk_out_n; - output tx_frame_out_p; - output tx_frame_out_n; - output [ 5:0] tx_data_out_p; - output [ 5:0] tx_data_out_n; - - output enable; - output txnrx; - input clk_out; - - inout gpio_clksel; - inout gpio_resetb; - inout gpio_sync; - inout gpio_en_agc; - inout [ 3:0] gpio_ctl; - inout [ 7:0] gpio_status; - - output spi_csn; - output spi_clk; - output spi_mosi; - input spi_miso; - - input pcie_rstn; - input pcie_prsntn; - output pcie_prsnt1n; - output pcie_prsnt4n; - inout pcie_waken; - input pcie_ref_clk_p; - input pcie_ref_clk_n; - input [ 3:0] pcie_data_rx_p; - input [ 3:0] pcie_data_rx_n; - output [ 3:0] pcie_data_tx_p; - output [ 3:0] pcie_data_tx_n; + reg pcie_reset_done_int = 1'b0; // internal signals wire pcie_ref_clk; + wire pcie_clk; + wire pcie_rst; wire [63:0] gpio_i; wire [63:0] gpio_o; wire [63:0] gpio_t; @@ -187,8 +121,17 @@ module system_top ( // assignments assign pcie_waken = 1'bz; - assign pcie_prsnt1n = 1'b1; - assign pcie_prsnt4n = pcie_prsntn; + assign pcie_reset_done = pcie_reset_done_int; + + // PCIe reset monitor + + always @(posedge pcie_clk or posedge pcie_rst) begin + if (pcie_rst == 1'b1) begin + pcie_reset_done_int <= 1'b0; + end else begin + pcie_reset_done_int <= 1'b1; + end + end // instantiations @@ -210,12 +153,6 @@ module system_top ( gpio_ctl, // 43:40 gpio_status})); // 39:32 - ad_iobuf #(.DATA_WIDTH(12)) i_iobuf_bd ( - .dio_t (gpio_t[11:0]), - .dio_i (gpio_o[11:0]), - .dio_o (gpio_i[11:0]), - .dio_p (gpio_bd)); - system_wrapper i_system_wrapper ( .ddr_addr (ddr_addr), .ddr_ba (ddr_ba), @@ -239,18 +176,33 @@ module system_top ( .fixed_io_ps_clk (fixed_io_ps_clk), .fixed_io_ps_porb (fixed_io_ps_porb), .fixed_io_ps_srstb (fixed_io_ps_srstb), - .gpio_i (gpio_i), - .gpio_o (gpio_o), - .gpio_t (gpio_t), + .gpio_i ({63'd0, pcie_reset_done_int}), + .gpio_o (), + .gpio_t (), .iic_main_scl_io (iic_scl), .iic_main_sda_io (iic_sda), .otg_vbusoc (1'b0), + .pcie_clk (pcie_clk), .pcie_data_rxn (pcie_data_rx_n), .pcie_data_rxp (pcie_data_rx_p), .pcie_data_txn (pcie_data_tx_n), .pcie_data_txp (pcie_data_tx_p), .pcie_ref_clk (pcie_ref_clk), + .pcie_rst (pcie_rst), .pcie_rstn (pcie_rstn), + .pl_gpio0_i (gpio_i[31:0]), + .pl_gpio0_o (gpio_o[31:0]), + .pl_gpio0_t (gpio_t[31:0]), + .pl_gpio1_i (gpio_i[63:32]), + .pl_gpio1_o (gpio_o[63:32]), + .pl_gpio1_t (gpio_t[63:32]), + .pl_spi_clk_i (spi_clk), + .pl_spi_clk_o (spi_clk), + .pl_spi_csn_i (spi_csn), + .pl_spi_csn_o (spi_csn), + .pl_spi_sdi_i (spi_miso), + .pl_spi_sdo_i (spi_mosi), + .pl_spi_sdo_o (spi_mosi), .ps_intr_00 (1'b0), .ps_intr_01 (1'b0), .ps_intr_02 (1'b0), @@ -271,14 +223,14 @@ module system_top ( .rx_frame_in_n (rx_frame_in_n), .rx_frame_in_p (rx_frame_in_p), .spi0_clk_i (1'b0), - .spi0_clk_o (spi_clk), - .spi0_csn_0_o (spi_csn), + .spi0_clk_o (), + .spi0_csn_0_o (), .spi0_csn_1_o (), .spi0_csn_2_o (), .spi0_csn_i (1'b1), - .spi0_sdi_i (spi_miso), + .spi0_sdi_i (1'b0), .spi0_sdo_i (1'b0), - .spi0_sdo_o (spi_mosi), + .spi0_sdo_o (), .spi1_clk_i (1'b0), .spi1_clk_o (), .spi1_csn_0_o (), diff --git a/projects/pzsdr2/ccusb_lvds/Makefile b/projects/pzsdr2/ccusb_lvds/Makefile new file mode 100644 index 000000000..e5cf5afbf --- /dev/null +++ b/projects/pzsdr2/ccusb_lvds/Makefile @@ -0,0 +1,85 @@ +#################################################################################### +#################################################################################### +## Copyright 2011(c) Analog Devices, Inc. +## Auto-generated, do not modify! +#################################################################################### +#################################################################################### + +M_DEPS += system_top.v +M_DEPS += system_project.tcl +M_DEPS += system_bd.tcl +M_DEPS += ../common/pzsdr2_constr_lvds.xdc +M_DEPS += ../common/pzsdr2_constr.xdc +M_DEPS += ../common/pzsdr2_bd.tcl +M_DEPS += ../common/ccusb_constr.xdc +M_DEPS += ../common/ccusb_bd.tcl +M_DEPS += ../../scripts/adi_project.tcl +M_DEPS += ../../scripts/adi_env.tcl +M_DEPS += ../../scripts/adi_board.tcl +M_DEPS += ../../../library/xilinx/common/ad_iobuf.v +M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr +M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr +M_DEPS += ../../../library/axi_usb_fx3/axi_usb_fx3.xpr +M_DEPS += ../../../library/util_clkdiv/util_clkdiv.xpr +M_DEPS += ../../../library/util_cpack/util_cpack.xpr +M_DEPS += ../../../library/util_rfifo/util_rfifo.xpr +M_DEPS += ../../../library/util_tdd_sync/util_tdd_sync.xpr +M_DEPS += ../../../library/util_upack/util_upack.xpr +M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr + +M_VIVADO := vivado -mode batch -source + +M_FLIST := *.cache +M_FLIST += *.data +M_FLIST += *.xpr +M_FLIST += *.log +M_FLIST += *.jou +M_FLIST += xgui +M_FLIST += *.runs +M_FLIST += *.srcs +M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim +M_FLIST += .Xil +M_FLIST += *.ip_user_files + + + +.PHONY: all lib clean clean-all +all: lib pzsdr2_ccusb_lvds.sdk/system_top.hdf + + +clean: + rm -rf $(M_FLIST) + + +clean-all:clean + make -C ../../../library/axi_ad9361 clean + make -C ../../../library/axi_dmac clean + make -C ../../../library/axi_usb_fx3 clean + make -C ../../../library/util_clkdiv clean + make -C ../../../library/util_cpack clean + make -C ../../../library/util_rfifo clean + make -C ../../../library/util_tdd_sync clean + make -C ../../../library/util_upack clean + make -C ../../../library/util_wfifo clean + + +pzsdr2_ccusb_lvds.sdk/system_top.hdf: $(M_DEPS) + -rm -rf $(M_FLIST) + $(M_VIVADO) system_project.tcl >> pzsdr2_ccusb_lvds_vivado.log 2>&1 + + +lib: + make -C ../../../library/axi_ad9361 + make -C ../../../library/axi_dmac + make -C ../../../library/axi_usb_fx3 + make -C ../../../library/util_clkdiv + make -C ../../../library/util_cpack + make -C ../../../library/util_rfifo + make -C ../../../library/util_tdd_sync + make -C ../../../library/util_upack + make -C ../../../library/util_wfifo + +#################################################################################### +#################################################################################### diff --git a/projects/pzsdr2/ccusb_lvds/system_bd.tcl b/projects/pzsdr2/ccusb_lvds/system_bd.tcl new file mode 100644 index 000000000..40e1e08b3 --- /dev/null +++ b/projects/pzsdr2/ccusb_lvds/system_bd.tcl @@ -0,0 +1,6 @@ + +source ../common/pzsdr2_bd.tcl +source ../common/ccusb_bd.tcl + +cfg_ad9361_interface LVDS + diff --git a/projects/pzsdr2/ccusb_lvds/system_project.tcl b/projects/pzsdr2/ccusb_lvds/system_project.tcl new file mode 100644 index 000000000..e74d1e0cc --- /dev/null +++ b/projects/pzsdr2/ccusb_lvds/system_project.tcl @@ -0,0 +1,20 @@ + +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/projects/scripts/adi_project.tcl +source $ad_hdl_dir/projects/scripts/adi_board.tcl + +set p_device "xc7z035ifbg676-2L" +adi_project_create pzsdr2_ccusb_lvds +adi_project_files pzsdr2_ccusb_lvds [list \ + "system_top.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \ + "../common/pzsdr2_constr.xdc" \ + "../common/pzsdr2_constr_lvds.xdc" \ + "../common/ccusb_constr.xdc" ] + +set_property PROCESSING_ORDER EARLY [get_files ../common/pzsdr2_constr.xdc] +set_property PROCESSING_ORDER LATE [get_files ../common/ccusb_constr.xdc] + +adi_project_run pzsdr2_ccusb_lvds + + diff --git a/projects/pzsdr2/ccusb_lvds/system_top.v b/projects/pzsdr2/ccusb_lvds/system_top.v new file mode 100644 index 000000000..77536b9da --- /dev/null +++ b/projects/pzsdr2/ccusb_lvds/system_top.v @@ -0,0 +1,241 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top ( + + inout [14:0] ddr_addr, + inout [ 2:0] ddr_ba, + inout ddr_cas_n, + inout ddr_ck_n, + inout ddr_ck_p, + inout ddr_cke, + inout ddr_cs_n, + inout [ 3:0] ddr_dm, + inout [31:0] ddr_dq, + inout [ 3:0] ddr_dqs_n, + inout [ 3:0] ddr_dqs_p, + inout ddr_odt, + inout ddr_ras_n, + inout ddr_reset_n, + inout ddr_we_n, + + inout fixed_io_ddr_vrn, + inout fixed_io_ddr_vrp, + inout [53:0] fixed_io_mio, + inout fixed_io_ps_clk, + inout fixed_io_ps_porb, + inout fixed_io_ps_srstb, + + inout iic_scl, + inout iic_sda, + + input rx_clk_in_p, + input rx_clk_in_n, + input rx_frame_in_p, + input rx_frame_in_n, + input [ 5:0] rx_data_in_p, + input [ 5:0] rx_data_in_n, + output tx_clk_out_p, + output tx_clk_out_n, + output tx_frame_out_p, + output tx_frame_out_n, + output [ 5:0] tx_data_out_p, + output [ 5:0] tx_data_out_n, + + output enable, + output txnrx, + input clkout_in, + + inout gpio_clksel, + inout gpio_resetb, + inout gpio_sync, + inout gpio_en_agc, + inout [ 3:0] gpio_ctl, + inout [ 7:0] gpio_status, + + input usb_fx3_uart_tx, + output usb_fx3_uart_rx, + + input [ 7:0] fifo_rdy, + + inout [31:0] data, + output [ 4:0] addr, + output pclk, + output slcs_n, + output slrd_n, + output sloe_n, + output slwr_n, + output pktend_n, + output epswitch_n, + + input flag_a, + input flag_b, + + output reset_n, + + output [ 2:0] pmode, + + output spi_csn, + output spi_clk, + output spi_mosi, + input spi_miso); + + // internal signals + + wire [63:0] gpio_i; + wire [63:0] gpio_o; + wire [63:0] gpio_t; + + // assignments + + assign pmode = 3'b111; + assign addr[4:2] = 3'b000; + + assign epswitch_n = 1'b1; + assign reset_n = 1'b1; + + // instantiations + + ad_iobuf #(.DATA_WIDTH(16)) i_iobuf ( + .dio_t ({gpio_t[51], gpio_t[46:32]}), + .dio_i ({gpio_o[51], gpio_o[46:32]}), + .dio_o ({gpio_i[51], gpio_i[46:32]}), + .dio_p ({ gpio_clksel, // 51:51 + gpio_resetb, // 46:46 + gpio_sync, // 45:45 + gpio_en_agc, // 44:44 + gpio_ctl, // 43:40 + gpio_status})); // 39:32 + + system_wrapper i_system_wrapper ( + .ddr_addr (ddr_addr), + .ddr_ba (ddr_ba), + .ddr_cas_n (ddr_cas_n), + .ddr_ck_n (ddr_ck_n), + .ddr_ck_p (ddr_ck_p), + .ddr_cke (ddr_cke), + .ddr_cs_n (ddr_cs_n), + .ddr_dm (ddr_dm), + .ddr_dq (ddr_dq), + .ddr_dqs_n (ddr_dqs_n), + .ddr_dqs_p (ddr_dqs_p), + .ddr_odt (ddr_odt), + .ddr_ras_n (ddr_ras_n), + .ddr_reset_n (ddr_reset_n), + .ddr_we_n (ddr_we_n), + .enable (enable), + .fixed_io_ddr_vrn (fixed_io_ddr_vrn), + .fixed_io_ddr_vrp (fixed_io_ddr_vrp), + .fixed_io_mio (fixed_io_mio), + .fixed_io_ps_clk (fixed_io_ps_clk), + .fixed_io_ps_porb (fixed_io_ps_porb), + .fixed_io_ps_srstb (fixed_io_ps_srstb), + .gpio_i (gpio_i), + .gpio_o (gpio_o), + .gpio_t (gpio_t), + .iic_main_scl_io (iic_scl), + .iic_main_sda_io (iic_sda), + .otg_vbusoc (1'b0), + .ps_intr_00 (1'b0), + .ps_intr_01 (1'b0), + .ps_intr_02 (1'b0), + .ps_intr_03 (1'b0), + .ps_intr_04 (1'b0), + .ps_intr_05 (1'b0), + .ps_intr_06 (1'b0), + .ps_intr_07 (1'b0), + .ps_intr_08 (1'b0), + .ps_intr_09 (1'b0), + .ps_intr_15 (1'b0), + .rx_clk_in_n (rx_clk_in_n), + .rx_clk_in_p (rx_clk_in_p), + .rx_data_in_n (rx_data_in_n), + .rx_data_in_p (rx_data_in_p), + .rx_frame_in_n (rx_frame_in_n), + .rx_frame_in_p (rx_frame_in_p), + .spi0_clk_i (1'b0), + .spi0_clk_o (spi_clk), + .spi0_csn_0_o (spi_csn), + .spi0_csn_1_o (), + .spi0_csn_2_o (), + .spi0_csn_i (1'b1), + .spi0_sdi_i (spi_miso), + .spi0_sdo_i (1'b0), + .spi0_sdo_o (spi_mosi), + .spi1_clk_i (1'b0), + .spi1_clk_o (), + .spi1_csn_0_o (), + .spi1_csn_1_o (), + .spi1_csn_2_o (), + .spi1_csn_i (1'b1), + .spi1_sdi_i (1'b0), + .spi1_sdo_i (1'b0), + .spi1_sdo_o (), + .tdd_sync_i (1'b0), + .tdd_sync_o (), + .tdd_sync_t (), + .tx_clk_out_n (tx_clk_out_n), + .tx_clk_out_p (tx_clk_out_p), + .tx_data_out_n (tx_data_out_n), + .tx_data_out_p (tx_data_out_p), + .tx_frame_out_n (tx_frame_out_n), + .tx_frame_out_p (tx_frame_out_p), + .txnrx (txnrx), + .up_enable (gpio_o[47]), + .up_txnrx (gpio_o[48]), + .usb_fx3_uart_tx(usb_fx3_uart_tx), + .usb_fx3_uart_rx(usb_fx3_uart_rx), + .dma_rdy(), + .dma_wmk(), + .fifo_rdy(fifo_rdy[3:0]), + .pclk(pclk), + .data(data), + .addr(addr[1:0]), + .slcs_n(slcs_n), + .slrd_n(slrd_n), + .sloe_n(sloe_n), + .slwr_n(slwr_n), + // .epswitch_n(epswitch_n), + .pktend_n(pktend_n) + ); + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/projects/pzsdr2/common/ccbox_bd.tcl b/projects/pzsdr2/common/ccbox_bd.tcl new file mode 100644 index 000000000..0b2c89ea0 --- /dev/null +++ b/projects/pzsdr2/common/ccbox_bd.tcl @@ -0,0 +1,46 @@ + +# unused + +ad_connect sys_ps7/ENET1_GMII_RX_CLK GND +ad_connect sys_ps7/ENET1_GMII_TX_CLK GND + +# GPS-UART + +set_property CONFIG.PCW_UART0_PERIPHERAL_ENABLE {1} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_UART0_UART0_IO {MIO 14 .. 15} [get_bd_cells sys_ps7] +set_property CONFIG.PCW_USE_DMA0 1 [get_bd_cells sys_ps7] +set_property CONFIG.PCW_USE_DMA1 1 [get_bd_cells sys_ps7] + +# i2s + +create_bd_port -dir O -type clk i2s_mclk +create_bd_intf_port -mode Master -vlnv analog.com:interface:i2s_rtl:1.0 i2s + +set sys_audio_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.3 sys_audio_clkgen] +set_property -dict [list CONFIG.PRIM_IN_FREQ {200.000}] $sys_audio_clkgen +set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {12.288}] $sys_audio_clkgen +set_property -dict [list CONFIG.USE_LOCKED {false}] $sys_audio_clkgen +set_property -dict [list CONFIG.USE_RESET {true} CONFIG.RESET_TYPE {ACTIVE_LOW}] $sys_audio_clkgen + +set axi_i2s_adi [create_bd_cell -type ip -vlnv analog.com:user:axi_i2s_adi:1.0 axi_i2s_adi] +set_property -dict [list CONFIG.DMA_TYPE {1}] $axi_i2s_adi +set_property -dict [list CONFIG.S_AXI_ADDRESS_WIDTH {16}] $axi_i2s_adi + +ad_connect sys_200m_clk sys_audio_clkgen/clk_in1 +ad_connect sys_cpu_resetn sys_audio_clkgen/resetn +ad_connect sys_cpu_clk axi_i2s_adi/DMA_REQ_RX_ACLK +ad_connect sys_cpu_clk axi_i2s_adi/DMA_REQ_TX_ACLK +ad_connect sys_cpu_clk sys_ps7/DMA0_ACLK +ad_connect sys_cpu_clk sys_ps7/DMA1_ACLK +ad_connect sys_cpu_resetn axi_i2s_adi/DMA_REQ_RX_RSTN +ad_connect sys_cpu_resetn axi_i2s_adi/DMA_REQ_TX_RSTN +ad_connect sys_ps7/DMA0_REQ axi_i2s_adi/DMA_REQ_TX +ad_connect sys_ps7/DMA0_ACK axi_i2s_adi/DMA_ACK_TX +ad_connect sys_ps7/DMA1_REQ axi_i2s_adi/DMA_REQ_RX +ad_connect sys_ps7/DMA1_ACK axi_i2s_adi/DMA_ACK_RX +ad_connect sys_audio_clkgen/clk_out1 i2s_mclk +ad_connect sys_audio_clkgen/clk_out1 axi_i2s_adi/DATA_CLK_I +ad_connect i2s axi_i2s_adi/I2S + +ad_cpu_interconnect 0x77600000 axi_i2s_adi + diff --git a/projects/pzsdr2/common/ccbox_constr.xdc b/projects/pzsdr2/common/ccbox_constr.xdc new file mode 100644 index 000000000..94ffc8f27 --- /dev/null +++ b/projects/pzsdr2/common/ccbox_constr.xdc @@ -0,0 +1,76 @@ + +## constraints (ccbox.a) +## rf-gpio + +set_property -dict {PACKAGE_PIN F5 IOSTANDARD LVCMOS18} [get_ports gpio_rfpwr_enable] ; ## U1,F5,IO_L07_34_JX4_P,JX4,35,RF_GPIO4_BANK34 +set_property -dict {PACKAGE_PIN G5 IOSTANDARD LVCMOS18} [get_ports gpio_rf0] ; ## U1,G5,IO_L02_34_JX4_N,JX4,22,RF_GPIO0_BANK34 +set_property -dict {PACKAGE_PIN H9 IOSTANDARD LVCMOS18} [get_ports gpio_rf1] ; ## U1,H9,IO_L03_34_JX4_P,JX4,25,RF_GPIO1_BANK34 +set_property -dict {PACKAGE_PIN J9 IOSTANDARD LVCMOS18} [get_ports gpio_rf2] ; ## U1,J9,IO_L05_34_JX4_N,JX4,33,RF_GPIO2_BANK34 +set_property -dict {PACKAGE_PIN H8 IOSTANDARD LVCMOS18} [get_ports gpio_rf3] ; ## U1,H8,IO_L06_34_JX4_N,JX4,34,RF_GPIO3_BANK34 +set_property -dict {PACKAGE_PIN D9 IOSTANDARD LVCMOS18} [get_ports gpio_rf4] ; ## U1,D9,IO_L08_34_JX4_P,JX4,36,RF_GPIO5_BANK34 + +## push-button + +set_property -dict {PACKAGE_PIN J8 IOSTANDARD LVCMOS18} [get_ports ltc2955_kill_n] ; ## U1,J8,IO_L06_34_JX4_P,JX4,32,LTC2955_KILL_N +set_property -dict {PACKAGE_PIN J10 IOSTANDARD LVCMOS18} [get_ports ltc2955_int_n] ; ## U1,J10,IO_L05_34_JX4_P,JX4,31,LTC2955_INT_N + +## oled + +set_property -dict {PACKAGE_PIN AA24 IOSTANDARD LVCMOS25} [get_ports oled_csn] ; ## U1,AA24,IO_L06_13_JX2_P,JX2,18,OLED_CS# +set_property -dict {PACKAGE_PIN AD24 IOSTANDARD LVCMOS25} [get_ports oled_clk] ; ## U1,AD24,IO_L11_SRCC_13_JX2_N,JX2,37,OLED_SCL +set_property -dict {PACKAGE_PIN AC23 IOSTANDARD LVCMOS25} [get_ports oled_mosi] ; ## U1,AC23,IO_L12_MRCC_13_JX2_P,JX2,36,OLED_SDI +set_property -dict {PACKAGE_PIN AD23 IOSTANDARD LVCMOS25} [get_ports oled_rst] ; ## U1,AD23,IO_L11_SRCC_13_JX2_P,JX2,35,OLED_/RES +set_property -dict {PACKAGE_PIN AC24 IOSTANDARD LVCMOS25} [get_ports oled_dc] ; ## U1,AC24,IO_L12_MRCC_13_JX2_N,JX2,38,OLED_D/C + +## adp5061 + +set_property -dict {PACKAGE_PIN J11 IOSTANDARD LVCMOS18} [get_ports adp5061_io[0]] ; ## U1,J11,IO_L01_34_JX4_P,JX4,19,ADP5061_IO1 +set_property -dict {PACKAGE_PIN H11 IOSTANDARD LVCMOS18} [get_ports adp5061_io[1]] ; ## U1,H11,IO_L01_34_JX4_N,JX4,21,ADP5061_IO2 +set_property -dict {PACKAGE_PIN G6 IOSTANDARD LVCMOS18} [get_ports adp5061_io[2]] ; ## U1,G6,IO_L02_34_JX4_P,JX4,20,ADP5061_IO3 + +## GPS (DATA-UART) +## U1,D23,PS_MIO14_500_JX4,JX4,93,GPS_TXD1_1V8 +## U1,C24,PS_MIO15_500_JX4,JX4,85,GPS_RXD1_1V8 + +set_property -dict {PACKAGE_PIN Y20 IOSTANDARD LVCMOS25} [get_ports gps_reset] ; ## U1,Y20,IO_L19_13_JX2_N,JX2,63,GPS_RESET +set_property -dict {PACKAGE_PIN AA20 IOSTANDARD LVCMOS25} [get_ports gps_force_on] ; ## U1,AA20,IO_L20_13_JX2_P,JX2,62,GPS_FORCE_ON +set_property -dict {PACKAGE_PIN AB20 IOSTANDARD LVCMOS25} [get_ports gps_standby] ; ## U1,AB20,IO_L20_13_JX2_N,JX2,64,GPS_STANDBY +set_property -dict {PACKAGE_PIN W20 IOSTANDARD LVCMOS25} [get_ports gps_pps] ; ## U1,W20,IO_L19_13_JX2_P,JX2,61,GPS_PPS + +## imu + +set_property -dict {PACKAGE_PIN AE20 IOSTANDARD LVCMOS25} [get_ports imu_csn] ; ## U1,AE20,IO_L16_13_JX2_P,JX2,48,IMU_CS_N +set_property -dict {PACKAGE_PIN AE21 IOSTANDARD LVCMOS25} [get_ports imu_clk] ; ## U1,AE21,IO_L16_13_JX2_N,JX2,50,IMU_SCLK +set_property -dict {PACKAGE_PIN AD18 IOSTANDARD LVCMOS25} [get_ports imu_mosi] ; ## U1,AD18,IO_L17_13_JX2_P,JX2,53,IMU_DIN +set_property -dict {PACKAGE_PIN AF18 IOSTANDARD LVCMOS25} [get_ports imu_miso] ; ## U1,AF18,IO_L18_13_JX2_N,JX2,56,IMU_DOUT +set_property -dict {PACKAGE_PIN AF20 IOSTANDARD LVCMOS25} [get_ports imu_rstn] ; ## U1,AF20,IO_L15_13_JX2_N,JX2,49,IMU_RST_N +set_property -dict {PACKAGE_PIN AE18 IOSTANDARD LVCMOS25} [get_ports imu_sync] ; ## U1,AE18,IO_L18_13_JX2_P,JX2,54,IMU_SYNC +set_property -dict {PACKAGE_PIN AD19 IOSTANDARD LVCMOS25} [get_ports imu_ready] ; ## U1,AD19,IO_L17_13_JX2_N,JX2,55,IMU_DR + +## audio + +set_property -dict {PACKAGE_PIN AD21 IOSTANDARD LVCMOS25} [get_ports i2s_bclk] ; ## U1,AD21,IO_L13_MRCC_13_JX2_N,JX2,43,AUD_BCLK +set_property -dict {PACKAGE_PIN AC21 IOSTANDARD LVCMOS25} [get_ports i2s_lrclk] ; ## U1,AC21,IO_L14_SRCC_13_JX2_P,JX2,42,AUD_LRCLK +set_property -dict {PACKAGE_PIN AD20 IOSTANDARD LVCMOS25} [get_ports i2s_mclk] ; ## U1,AD20,IO_L13_MRCC_13_JX2_P,JX2,41,AUD_MCLK +set_property -dict {PACKAGE_PIN AC22 IOSTANDARD LVCMOS25} [get_ports i2s_sdata_in] ; ## U1,AC22,IO_L14_SRCC_13_JX2_N,JX2,44,AUD_SDATA_IN +set_property -dict {PACKAGE_PIN AF19 IOSTANDARD LVCMOS25} [get_ports i2s_sdata_out] ; ## U1,AF19,IO_L15_13_JX2_P,JX2,47,AUD_SDATA_OUT + +set_property -dict {PACKAGE_PIN E8 IOSTANDARD LVCMOS18} [get_ports mic_present_n] ; ## U1,E8,IO_L09_34_JX4_N,JX4,43,MIC_PRESENT_N_1V8 +set_property -dict {PACKAGE_PIN E5 IOSTANDARD LVCMOS18} [get_ports ts3a227_int_n] ; ## U1,E5,IO_L07_34_JX4_N,JX4,37,TS3A227_INT_N + +## switch-led + +set_property -dict {PACKAGE_PIN D8 IOSTANDARD LVCMOS18} [get_ports switch_led_r] ; ## U1,D8,IO_L08_34_JX4_N,JX4,38,SWITCH_LED_R +set_property -dict {PACKAGE_PIN F9 IOSTANDARD LVCMOS18} [get_ports switch_led_g] ; ## U1,F9,IO_L09_34_JX4_P,JX4,41,SWITCH_LED_G +set_property -dict {PACKAGE_PIN E6 IOSTANDARD LVCMOS18} [get_ports switch_led_b] ; ## U1,E6,IO_L10_34_JX4_P,JX4,42,SWITCH_LED_B + +## power source + +set_property -dict {PACKAGE_PIN G9 IOSTANDARD LVCMOS18} [get_ports pss_valid_n[0]] ; ## U1,G9,IO_L03_34_JX4_N,JX4,27,PSS_VALID1_N +set_property -dict {PACKAGE_PIN H7 IOSTANDARD LVCMOS18} [get_ports pss_valid_n[1]] ; ## U1,H7,IO_L04_34_JX4_P,JX4,26,PSS_VALID2_N +set_property -dict {PACKAGE_PIN H6 IOSTANDARD LVCMOS18} [get_ports pss_valid_n[2]] ; ## U1,H6,IO_L04_34_JX4_N,JX4,28,PSS_VALID3_N + +## misc + +set_property -dict {PACKAGE_PIN AC16 IOSTANDARD LVCMOS25} [get_ports otg_ctrl] ; ## U1,AC16,IO_L21_12_JX2_N,JX2,95,OTG_CTRL +set_property -dict {PACKAGE_PIN AC17 IOSTANDARD LVCMOS25} [get_ports adp1614_en] ; ## U1,AC17,IO_L21_12_JX2_P,JX2,93,ADP1614_EN diff --git a/projects/pzsdr2/common/ccbrk_bd.tcl b/projects/pzsdr2/common/ccbrk_bd.tcl new file mode 100644 index 000000000..a09cda635 --- /dev/null +++ b/projects/pzsdr2/common/ccbrk_bd.tcl @@ -0,0 +1,49 @@ + +# lbfmc + +ad_connect sys_ps7/ENET1_GMII_RX_CLK GND +ad_connect sys_ps7/ENET1_GMII_TX_CLK GND + +# un-used io (gt) + +set axi_pz_xcvrlb [create_bd_cell -type ip -vlnv analog.com:user:axi_xcvrlb:1.0 axi_pz_xcvrlb] +set_property -dict [list CONFIG.NUM_OF_LANES {4}] $axi_pz_xcvrlb + +create_bd_port -dir I gt_ref_clk +create_bd_port -dir I -from 3 -to 0 gt_rx_p +create_bd_port -dir I -from 3 -to 0 gt_rx_n +create_bd_port -dir O -from 3 -to 0 gt_tx_p +create_bd_port -dir O -from 3 -to 0 gt_tx_n + +ad_cpu_interconnect 0x44A60000 axi_pz_xcvrlb +ad_connect axi_pz_xcvrlb/ref_clk gt_ref_clk +ad_connect axi_pz_xcvrlb/rx_p gt_rx_p +ad_connect axi_pz_xcvrlb/rx_n gt_rx_n +ad_connect axi_pz_xcvrlb/tx_p gt_tx_p +ad_connect axi_pz_xcvrlb/tx_n gt_tx_n + +# un-used io (regular) + +set axi_gpreg [create_bd_cell -type ip -vlnv analog.com:user:axi_gpreg:1.0 axi_gpreg] +set_property -dict [list CONFIG.NUM_OF_CLK_MONS {0}] $axi_gpreg +set_property -dict [list CONFIG.NUM_OF_IO {4}] $axi_gpreg + +create_bd_port -dir I -from 31 -to 0 gp_in_0 +create_bd_port -dir I -from 31 -to 0 gp_in_1 +create_bd_port -dir I -from 31 -to 0 gp_in_2 +create_bd_port -dir I -from 31 -to 0 gp_in_3 +create_bd_port -dir O -from 31 -to 0 gp_out_0 +create_bd_port -dir O -from 31 -to 0 gp_out_1 +create_bd_port -dir O -from 31 -to 0 gp_out_2 +create_bd_port -dir O -from 31 -to 0 gp_out_3 + +ad_connect gp_in_0 axi_gpreg/up_gp_in_0 +ad_connect gp_in_1 axi_gpreg/up_gp_in_1 +ad_connect gp_in_2 axi_gpreg/up_gp_in_2 +ad_connect gp_in_3 axi_gpreg/up_gp_in_3 +ad_connect gp_out_0 axi_gpreg/up_gp_out_0 +ad_connect gp_out_1 axi_gpreg/up_gp_out_1 +ad_connect gp_out_2 axi_gpreg/up_gp_out_2 +ad_connect gp_out_3 axi_gpreg/up_gp_out_3 +ad_cpu_interconnect 0x41200000 axi_gpreg + diff --git a/projects/pzsdr2/common/ccbrk_constr.xdc b/projects/pzsdr2/common/ccbrk_constr.xdc new file mode 100644 index 000000000..5af874e7c --- /dev/null +++ b/projects/pzsdr2/common/ccbrk_constr.xdc @@ -0,0 +1,248 @@ + +## constraints (ccbrk.c + ccbrk_lb.a) +## ad9361 clkout forward + +set_property -dict {PACKAGE_PIN A7 IOSTANDARD LVCMOS18} [get_ports clkout_out] ; ## (lb: gpio_bd[15]) U1,A7,IO_L18_34_JX4_N,JX4,70,IO_L18_34_JX4_N,P7,32 + +## push-buttons- led- dip-switches- loopbacks- (ps7 gpio) + +set_property -dict {PACKAGE_PIN J3 IOSTANDARD LVCMOS18} [get_ports gpio_bd[0]] ; ## (lb: gpio_bd[4]) U1,J3,IO_L12_MRCC_33_JX1_N,JX1,83,PB_GPIO_0,P4,31 +set_property -dict {PACKAGE_PIN D8 IOSTANDARD LVCMOS18} [get_ports gpio_bd[1]] ; ## (lb: gpio_bd[5]) U1,D8,IO_L08_34_JX4_N,JX4,38,PB_GPIO_1,P6,19 +set_property -dict {PACKAGE_PIN F9 IOSTANDARD LVCMOS18} [get_ports gpio_bd[2]] ; ## (lb: gpio_bd[6]) U1,F9,IO_L09_34_JX4_P,JX4,41,PB_GPIO_2,P6,26 +set_property -dict {PACKAGE_PIN E8 IOSTANDARD LVCMOS18} [get_ports gpio_bd[3]] ; ## (lb: gpio_bd[12]) U1,E8,IO_L09_34_JX4_N,JX4,43,PB_GPIO_3,P6,28 +set_property -dict {PACKAGE_PIN A8 IOSTANDARD LVCMOS18} [get_ports gpio_bd[4]] ; ## (lb: gpio_bd[0]) U1,A8,IO_L17_34_JX4_N,JX4,69,LED_GPIO_0,P7,16 +set_property -dict {PACKAGE_PIN W14 IOSTANDARD LVCMOS25} [get_ports gpio_bd[5]] ; ## (lb: gpio_bd[1]) U1,W17,IO_25_12_JX4,JX4,16,LED_GPIO_2,P13,3 +set_property -dict {PACKAGE_PIN W17 IOSTANDARD LVCMOS25} [get_ports gpio_bd[6]] ; ## (lb: gpio_bd[2]) U1,W14,IO_00_12_JX4,JX4,14,LED_GPIO_1,P13,4 +set_property -dict {PACKAGE_PIN Y16 IOSTANDARD LVCMOS25} [get_ports gpio_bd[7]] ; ## (lb: i2c_scl) U1,Y16,IO_L23_12_JX2_P,JX2,97,LED_GPIO_3,P2,4 (U1,AF24,SCL,JX2,17,I2C_SCL,P2,14) +set_property -dict {PACKAGE_PIN Y15 IOSTANDARD LVCMOS25} [get_ports gpio_bd[8]] ; ## (lb: none) U1,Y15,IO_L23_12_JX2_N,JX2,99,DIP_GPIO_0 +set_property -dict {PACKAGE_PIN W16 IOSTANDARD LVCMOS25} [get_ports gpio_bd[9]] ; ## (lb: none) U1,W16,IO_L24_12_JX4_P,JX4,13,DIP_GPIO_1 +set_property -dict {PACKAGE_PIN W15 IOSTANDARD LVCMOS25} [get_ports gpio_bd[10]] ; ## (lb: none) U1,W15,IO_L24_12_JX4_N,JX4,15,DIP_GPIO_2 +set_property -dict {PACKAGE_PIN V19 IOSTANDARD LVCMOS25} [get_ports gpio_bd[11]] ; ## (lb: none) U1,V19,IO_00_13_JX2,JX2,13,DIP_GPIO_3 + +## orphans- io- (ps7 gpio) + +set_property -dict {PACKAGE_PIN V18 IOSTANDARD LVCMOS25} [get_ports gpio_bd[12]] ; ## (lb: gpio_bd[3]) U1,V18,IO_25_13_JX2,JX2,14,IO_25_13_JX2,P2,3 +set_property -dict {PACKAGE_PIN AB24 IOSTANDARD LVCMOS25} [get_ports gpio_bd[13]] ; ## (lb: i2c_sda) U1,AB24,IO_L06_13_JX2_N,JX2,20,IO_L06_13_JX2_N,P2,15 (U1,AF25,SDA,JX2,19,I2C_SDA,P2,16) +set_property -dict {PACKAGE_PIN AA24 IOSTANDARD LVCMOS25} [get_ports gpio_bd[14]] ; ## (lb: none) U1,AA24,IO_L06_13_JX2_P,JX2,18,IO_L06_13_JX2_P +set_property -dict {PACKAGE_PIN N8 IOSTANDARD LVCMOS18} [get_ports gpio_bd[15]] ; ## (lb: clkout_out) U1,N8,IO_25_33_JX1,JX1,10,IO_25_33_JX1,P7,31 + +## ps7- fixed io- to- fpga regular io (ps7 gpio) + +set_property -dict {PACKAGE_PIN K3 IOSTANDARD LVCMOS18} [get_ports gpio_bd[16]] ; ## U1,K3,IO_L11_SRCC_33_JX1_N,JX1,76,IO_L11_SRCC_33_JX1_N,P4,32 (U1,E26,PS_MIO00_500_JX4,JX4,97,PS_MIO00_500_JX4,P5,21) +set_property -dict {PACKAGE_PIN A9 IOSTANDARD LVCMOS18} [get_ports gpio_bd[17]] ; ## U1,A9,IO_L17_34_JX4_P,JX4,67,IO_L17_34_JX4_P,P6,9 (U1,B20,PS_MIO51_501_JX4,JX4,100,PS_MIO51_501_JX4,P6,11) +set_property -dict {PACKAGE_PIN E5 IOSTANDARD LVCMOS18} [get_ports gpio_bd[18]] ; ## U1,E5,IO_L07_34_JX4_N,JX4,37,IO_L07_34_JX4_N,P6,20 (U1,C24,PS_MIO15_500_JX4,JX4,85,PS_MIO15_500_JX4,P6,21) +set_property -dict {PACKAGE_PIN E6 IOSTANDARD LVCMOS18} [get_ports gpio_bd[19]] ; ## U1,E6,IO_L10_34_JX4_P,JX4,42,IO_L10_34_JX4_P,P6,25 (U1,A25,PS_MIO10_500_JX4,JX4,87,PS_MIO10_500_JX4,P6,23) + +## ps7- fixed io- to- ps7- fixed io (reference only) +## U1,B19,PS_MIO47_501_JX4,JX4,94,PS_MIO47_501_JX4,P7,24 == U1,E17,PS_MIO46_501_JX4,JX4,92,PS_MIO46_501_JX4,P7,22 + +## ps7- fixed io- orphans (reference only) +## U1,B25,PS_MIO13_500_JX4,JX4,91,PS_MIO13_500_JX4,P5,9 +## U1,D23,PS_MIO14_500_JX4,JX4,93,PS_MIO14_500_JX4,P5,11 +## U1,B26,PS_MIO11_500_JX4,JX4,88,PS_MIO11_500_JX4,P7,12 + +## fpga- regular io + +set_property -dict {PACKAGE_PIN AA25 IOSTANDARD LVCMOS25} [get_ports gp_out[0]] ; ## U1,AA25,IO_L01_13_JX2_P,JX2,1,IO_L01_13_JX2_P,P2,6 +set_property -dict {PACKAGE_PIN AB26 IOSTANDARD LVCMOS25} [get_ports gp_in[0]] ; ## U1,AB26,IO_L02_13_JX2_P,JX2,2,IO_L02_13_JX2_P,P2,5 +set_property -dict {PACKAGE_PIN AB25 IOSTANDARD LVCMOS25} [get_ports gp_out[1]] ; ## U1,AB25,IO_L01_13_JX2_N,JX2,3,IO_L01_13_JX2_N,P2,8 +set_property -dict {PACKAGE_PIN AC26 IOSTANDARD LVCMOS25} [get_ports gp_in[1]] ; ## U1,AC26,IO_L02_13_JX2_N,JX2,4,IO_L02_13_JX2_N,P2,7 +set_property -dict {PACKAGE_PIN AE25 IOSTANDARD LVCMOS25} [get_ports gp_out[2]] ; ## U1,AE25,IO_L03_13_JX2_P,JX2,5,IO_L03_13_JX2_P,P2,10 +set_property -dict {PACKAGE_PIN AD25 IOSTANDARD LVCMOS25} [get_ports gp_in[2]] ; ## U1,AD25,IO_L04_13_JX2_P,JX2,6,IO_L04_13_JX2_P,P2,9 +set_property -dict {PACKAGE_PIN AE26 IOSTANDARD LVCMOS25} [get_ports gp_out[3]] ; ## U1,AE26,IO_L03_13_JX2_N,JX2,7,IO_L03_13_JX2_N,P2,12 +set_property -dict {PACKAGE_PIN AD26 IOSTANDARD LVCMOS25} [get_ports gp_in[3]] ; ## U1,AD26,IO_L04_13_JX2_N,JX2,8,IO_L04_13_JX2_N,P2,11 +set_property -dict {PACKAGE_PIN AE22 IOSTANDARD LVCMOS25} [get_ports gp_out[4]] ; ## U1,AE22,IO_L07_13_JX2_P,JX2,23,IO_L07_13_JX2_P,P2,20 +set_property -dict {PACKAGE_PIN AE23 IOSTANDARD LVCMOS25} [get_ports gp_in[4]] ; ## U1,AE23,IO_L08_13_JX2_P,JX2,24,IO_L08_13_JX2_P,P2,19 +set_property -dict {PACKAGE_PIN AF22 IOSTANDARD LVCMOS25} [get_ports gp_out[5]] ; ## U1,AF22,IO_L07_13_JX2_N,JX2,25,IO_L07_13_JX2_N,P2,22 +set_property -dict {PACKAGE_PIN AF23 IOSTANDARD LVCMOS25} [get_ports gp_in[5]] ; ## U1,AF23,IO_L08_13_JX2_N,JX2,26,IO_L08_13_JX2_N,P2,21 +set_property -dict {PACKAGE_PIN AB21 IOSTANDARD LVCMOS25} [get_ports gp_out[6]] ; ## U1,AB21,IO_L09_13_JX2_P,JX2,29,IO_L09_13_JX2_P,P2,24 +set_property -dict {PACKAGE_PIN AA22 IOSTANDARD LVCMOS25} [get_ports gp_in[6]] ; ## U1,AA22,IO_L10_13_JX2_P,JX2,30,IO_L10_13_JX2_P,P2,23 +set_property -dict {PACKAGE_PIN AB22 IOSTANDARD LVCMOS25} [get_ports gp_out[7]] ; ## U1,AB22,IO_L09_13_JX2_N,JX2,31,IO_L09_13_JX2_N,P2,26 +set_property -dict {PACKAGE_PIN AA23 IOSTANDARD LVCMOS25} [get_ports gp_in[7]] ; ## U1,AA23,IO_L10_13_JX2_N,JX2,32,IO_L10_13_JX2_N,P2,25 +set_property -dict {PACKAGE_PIN AD23 IOSTANDARD LVCMOS25} [get_ports gp_out[8]] ; ## U1,AD23,IO_L11_SRCC_13_JX2_P,JX2,35,IO_L11_SRCC_13_JX2_P,P2,28 +set_property -dict {PACKAGE_PIN AC23 IOSTANDARD LVCMOS25} [get_ports gp_in[8]] ; ## U1,AC23,IO_L12_MRCC_13_JX2_P,JX2,36,IO_L12_MRCC_13_JX2_P,P2,27 +set_property -dict {PACKAGE_PIN AD24 IOSTANDARD LVCMOS25} [get_ports gp_out[9]] ; ## U1,AD24,IO_L11_SRCC_13_JX2_N,JX2,37,IO_L11_SRCC_13_JX2_N,P2,30 +set_property -dict {PACKAGE_PIN AC24 IOSTANDARD LVCMOS25} [get_ports gp_in[9]] ; ## U1,AC24,IO_L12_MRCC_13_JX2_N,JX2,38,IO_L12_MRCC_13_JX2_N,P2,29 +set_property -dict {PACKAGE_PIN AD20 IOSTANDARD LVCMOS25} [get_ports gp_out[10]] ; ## U1,AD20,IO_L13_MRCC_13_JX2_P,JX2,41,IO_L13_MRCC_13_JX2_P,P2,32 +set_property -dict {PACKAGE_PIN AC21 IOSTANDARD LVCMOS25} [get_ports gp_in[10]] ; ## U1,AC21,IO_L14_SRCC_13_JX2_P,JX2,42,IO_L14_SRCC_13_JX2_P,P2,31 +set_property -dict {PACKAGE_PIN AD21 IOSTANDARD LVCMOS25} [get_ports gp_out[11]] ; ## U1,AD21,IO_L13_MRCC_13_JX2_N,JX2,43,IO_L13_MRCC_13_JX2_N,P2,34 +set_property -dict {PACKAGE_PIN AC22 IOSTANDARD LVCMOS25} [get_ports gp_in[11]] ; ## U1,AC22,IO_L14_SRCC_13_JX2_N,JX2,44,IO_L14_SRCC_13_JX2_N,P2,33 +set_property -dict {PACKAGE_PIN AF19 IOSTANDARD LVCMOS25} [get_ports gp_out[12]] ; ## U1,AF19,IO_L15_13_JX2_P,JX2,47,IO_L15_13_JX2_P,P2,38 +set_property -dict {PACKAGE_PIN AE20 IOSTANDARD LVCMOS25} [get_ports gp_in[12]] ; ## U1,AE20,IO_L16_13_JX2_P,JX2,48,IO_L16_13_JX2_P,P2,37 +set_property -dict {PACKAGE_PIN AF20 IOSTANDARD LVCMOS25} [get_ports gp_out[13]] ; ## U1,AF20,IO_L15_13_JX2_N,JX2,49,IO_L15_13_JX2_N,P2,40 +set_property -dict {PACKAGE_PIN AE21 IOSTANDARD LVCMOS25} [get_ports gp_in[13]] ; ## U1,AE21,IO_L16_13_JX2_N,JX2,50,IO_L16_13_JX2_N,P2,39 +set_property -dict {PACKAGE_PIN AD18 IOSTANDARD LVCMOS25} [get_ports gp_out[14]] ; ## U1,AD18,IO_L17_13_JX2_P,JX2,53,IO_L17_13_JX2_P,P2,42 +set_property -dict {PACKAGE_PIN AE18 IOSTANDARD LVCMOS25} [get_ports gp_in[14]] ; ## U1,AE18,IO_L18_13_JX2_P,JX2,54,IO_L18_13_JX2_P,P2,41 +set_property -dict {PACKAGE_PIN AD19 IOSTANDARD LVCMOS25} [get_ports gp_out[15]] ; ## U1,AD19,IO_L17_13_JX2_N,JX2,55,IO_L17_13_JX2_N,P2,44 +set_property -dict {PACKAGE_PIN AF18 IOSTANDARD LVCMOS25} [get_ports gp_in[15]] ; ## U1,AF18,IO_L18_13_JX2_N,JX2,56,IO_L18_13_JX2_N,P2,43 +set_property -dict {PACKAGE_PIN W20 IOSTANDARD LVCMOS25} [get_ports gp_out[16]] ; ## U1,W20,IO_L19_13_JX2_P,JX2,61,IO_L19_13_JX2_P,P2,46 +set_property -dict {PACKAGE_PIN AA20 IOSTANDARD LVCMOS25} [get_ports gp_in[16]] ; ## U1,AA20,IO_L20_13_JX2_P,JX2,62,IO_L20_13_JX2_P,P2,45 +set_property -dict {PACKAGE_PIN Y20 IOSTANDARD LVCMOS25} [get_ports gp_out[17]] ; ## U1,Y20,IO_L19_13_JX2_N,JX2,63,IO_L19_13_JX2_N,P2,48 +set_property -dict {PACKAGE_PIN AB20 IOSTANDARD LVCMOS25} [get_ports gp_in[17]] ; ## U1,AB20,IO_L20_13_JX2_N,JX2,64,IO_L20_13_JX2_N,P2,47 +set_property -dict {PACKAGE_PIN AC18 IOSTANDARD LVCMOS25} [get_ports gp_out[18]] ; ## U1,AC18,IO_L21_13_JX2_P,JX2,67,IO_L21_13_JX2_P,P2,52 +set_property -dict {PACKAGE_PIN AA19 IOSTANDARD LVCMOS25} [get_ports gp_in[18]] ; ## U1,AA19,IO_L22_13_JX2_P,JX2,68,IO_L22_13_JX2_P,P2,51 +set_property -dict {PACKAGE_PIN AC19 IOSTANDARD LVCMOS25} [get_ports gp_out[19]] ; ## U1,AC19,IO_L21_13_JX2_N,JX2,69,IO_L21_13_JX2_N,P2,54 +set_property -dict {PACKAGE_PIN AB19 IOSTANDARD LVCMOS25} [get_ports gp_in[19]] ; ## U1,AB19,IO_L22_13_JX2_N,JX2,70,IO_L22_13_JX2_N,P2,53 +set_property -dict {PACKAGE_PIN W18 IOSTANDARD LVCMOS25} [get_ports gp_out[20]] ; ## U1,W18,IO_L23_13_JX2_P,JX2,73,IO_L23_13_JX2_P,P2,56 +set_property -dict {PACKAGE_PIN Y18 IOSTANDARD LVCMOS25} [get_ports gp_in[20]] ; ## U1,Y18,IO_L24_13_JX2_P,JX2,74,IO_L24_13_JX2_P,P2,55 +set_property -dict {PACKAGE_PIN W19 IOSTANDARD LVCMOS25} [get_ports gp_out[21]] ; ## U1,W19,IO_L23_13_JX2_N,JX2,75,IO_L23_13_JX2_N,P2,58 +set_property -dict {PACKAGE_PIN AA18 IOSTANDARD LVCMOS25} [get_ports gp_in[21]] ; ## U1,AA18,IO_L24_13_JX2_N,JX2,76,IO_L24_13_JX2_N,P2,57 +set_property -dict {PACKAGE_PIN G4 IOSTANDARD LVCMOS18} [get_ports gp_out[22]] ; ## U1,G4,IO_L01_33_JX1_P,JX1,35,IO_L01_33_JX1_P,P4,2 +set_property -dict {PACKAGE_PIN D4 IOSTANDARD LVCMOS18} [get_ports gp_in[22]] ; ## U1,D4,IO_L02_33_JX1_P,JX1,41,IO_L02_33_JX1_P,P4,1 +set_property -dict {PACKAGE_PIN F4 IOSTANDARD LVCMOS18} [get_ports gp_out[23]] ; ## U1,F4,IO_L01_33_JX1_N,JX1,37,IO_L01_33_JX1_N,P4,4 +set_property -dict {PACKAGE_PIN D3 IOSTANDARD LVCMOS18} [get_ports gp_in[23]] ; ## U1,D3,IO_L02_33_JX1_N,JX1,43,IO_L02_33_JX1_N,P4,3 +set_property -dict {PACKAGE_PIN G2 IOSTANDARD LVCMOS18} [get_ports gp_out[24]] ; ## U1,G2,IO_L03_33_JX1_P,JX1,42,IO_L03_33_JX1_P,P4,6 +set_property -dict {PACKAGE_PIN D1 IOSTANDARD LVCMOS18} [get_ports gp_in[24]] ; ## U1,D1,IO_L04_33_JX1_P,JX1,47,IO_L04_33_JX1_P,P4,5 +set_property -dict {PACKAGE_PIN F2 IOSTANDARD LVCMOS18} [get_ports gp_out[25]] ; ## U1,F2,IO_L03_33_JX1_N,JX1,44,IO_L03_33_JX1_N,P4,8 +set_property -dict {PACKAGE_PIN C1 IOSTANDARD LVCMOS18} [get_ports gp_in[25]] ; ## U1,C1,IO_L04_33_JX1_N,JX1,49,IO_L04_33_JX1_N,P4,7 +set_property -dict {PACKAGE_PIN E2 IOSTANDARD LVCMOS18} [get_ports gp_out[26]] ; ## U1,E2,IO_L05_33_JX1_P,JX1,54,IO_L05_33_JX1_P,P4,14 +set_property -dict {PACKAGE_PIN F3 IOSTANDARD LVCMOS18} [get_ports gp_in[26]] ; ## U1,F3,IO_L06_33_JX1_P,JX1,61,IO_L06_33_JX1_P,P4,13 +set_property -dict {PACKAGE_PIN E1 IOSTANDARD LVCMOS18} [get_ports gp_out[27]] ; ## U1,E1,IO_L05_33_JX1_N,JX1,56,IO_L05_33_JX1_N,P4,16 +set_property -dict {PACKAGE_PIN E3 IOSTANDARD LVCMOS18} [get_ports gp_in[27]] ; ## U1,E3,IO_L06_33_JX1_N,JX1,63,IO_L06_33_JX1_N,P4,15 +set_property -dict {PACKAGE_PIN J1 IOSTANDARD LVCMOS18} [get_ports gp_out[28]] ; ## U1,J1,IO_L07_33_JX1_P,JX1,62,IO_L07_33_JX1_P,P4,18 +set_property -dict {PACKAGE_PIN H4 IOSTANDARD LVCMOS18} [get_ports gp_in[28]] ; ## U1,H4,IO_L08_33_JX1_P,JX1,67,IO_L08_33_JX1_P,P4,17 +set_property -dict {PACKAGE_PIN H1 IOSTANDARD LVCMOS18} [get_ports gp_out[29]] ; ## U1,H1,IO_L07_33_JX1_N,JX1,64,IO_L07_33_JX1_N,P4,20 +set_property -dict {PACKAGE_PIN H3 IOSTANDARD LVCMOS18} [get_ports gp_in[29]] ; ## U1,H3,IO_L08_33_JX1_N,JX1,69,IO_L08_33_JX1_N,P4,19 +set_property -dict {PACKAGE_PIN K2 IOSTANDARD LVCMOS18} [get_ports gp_out[30]] ; ## U1,K2,IO_L09_33_JX1_P,JX1,68,IO_L09_33_JX1_P,P4,26 +set_property -dict {PACKAGE_PIN H2 IOSTANDARD LVCMOS18} [get_ports gp_in[30]] ; ## U1,H2,IO_L10_33_JX1_P,JX1,73,IO_L10_33_JX1_P,P4,25 +set_property -dict {PACKAGE_PIN K1 IOSTANDARD LVCMOS18} [get_ports gp_out[31]] ; ## U1,K1,IO_L09_33_JX1_N,JX1,70,IO_L09_33_JX1_N,P4,28 +set_property -dict {PACKAGE_PIN G1 IOSTANDARD LVCMOS18} [get_ports gp_in[31]] ; ## U1,G1,IO_L10_33_JX1_N,JX1,75,IO_L10_33_JX1_N,P4,27 +set_property -dict {PACKAGE_PIN L3 IOSTANDARD LVCMOS18} [get_ports gp_out[32]] ; ## U1,L3,IO_L11_SRCC_33_JX1_P,JX1,74,IO_L11_SRCC_33_JX1_P,P4,30 +set_property -dict {PACKAGE_PIN J4 IOSTANDARD LVCMOS18} [get_ports gp_in[32]] ; ## U1,J4,IO_L12_MRCC_33_JX1_P,JX1,81,IO_L12_MRCC_33_JX1_P,P4,29 +set_property -dict {PACKAGE_PIN M2 IOSTANDARD LVCMOS18} [get_ports gp_out[33]] ; ## U1,M2,IO_L16_33_JX1_P,JX1,11,IO_L16_33_JX1_P,P5,2 +set_property -dict {PACKAGE_PIN N4 IOSTANDARD LVCMOS18} [get_ports gp_in[33]] ; ## U1,N4,IO_L17_33_JX1_P,JX1,12,IO_L17_33_JX1_P,P5,1 +set_property -dict {PACKAGE_PIN L2 IOSTANDARD LVCMOS18} [get_ports gp_out[34]] ; ## U1,L2,IO_L16_33_JX1_N,JX1,13,IO_L16_33_JX1_N,P5,4 +set_property -dict {PACKAGE_PIN M4 IOSTANDARD LVCMOS18} [get_ports gp_in[34]] ; ## U1,M4,IO_L17_33_JX1_N,JX1,14,IO_L17_33_JX1_N,P5,3 +set_property -dict {PACKAGE_PIN N1 IOSTANDARD LVCMOS18} [get_ports gp_out[35]] ; ## U1,N1,IO_L18_33_JX1_P,JX1,17,IO_L18_33_JX1_P,P5,6 +set_property -dict {PACKAGE_PIN M7 IOSTANDARD LVCMOS18} [get_ports gp_in[35]] ; ## U1,M7,IO_L19_33_JX1_P,JX1,18,IO_L19_33_JX1_P,P5,5 +set_property -dict {PACKAGE_PIN M1 IOSTANDARD LVCMOS18} [get_ports gp_out[36]] ; ## U1,M1,IO_L18_33_JX1_N,JX1,19,IO_L18_33_JX1_N,P5,8 +set_property -dict {PACKAGE_PIN L7 IOSTANDARD LVCMOS18} [get_ports gp_in[36]] ; ## U1,L7,IO_L19_33_JX1_N,JX1,20,IO_L19_33_JX1_N,P5,7 +set_property -dict {PACKAGE_PIN M8 IOSTANDARD LVCMOS18} [get_ports gp_out[37]] ; ## U1,M8,IO_L21_33_JX1_P,JX1,24,IO_L21_33_JX1_P,P5,14 +set_property -dict {PACKAGE_PIN K5 IOSTANDARD LVCMOS18} [get_ports gp_in[37]] ; ## U1,K5,IO_L20_33_JX1_P,JX1,23,IO_L20_33_JX1_P,P5,13 +set_property -dict {PACKAGE_PIN L8 IOSTANDARD LVCMOS18} [get_ports gp_out[38]] ; ## U1,L8,IO_L21_33_JX1_N,JX1,26,IO_L21_33_JX1_N,P5,16 +set_property -dict {PACKAGE_PIN J5 IOSTANDARD LVCMOS18} [get_ports gp_in[38]] ; ## U1,J5,IO_L20_33_JX1_N,JX1,25,IO_L20_33_JX1_N,P5,15 +set_property -dict {PACKAGE_PIN N7 IOSTANDARD LVCMOS18} [get_ports gp_out[39]] ; ## U1,N7,IO_L23_33_JX1_P,JX1,30,IO_L23_33_JX1_P,P5,18 +set_property -dict {PACKAGE_PIN K6 IOSTANDARD LVCMOS18} [get_ports gp_in[39]] ; ## U1,K6,IO_L22_33_JX1_P,JX1,29,IO_L22_33_JX1_P,P5,17 +set_property -dict {PACKAGE_PIN N6 IOSTANDARD LVCMOS18} [get_ports gp_out[40]] ; ## U1,N6,IO_L23_33_JX1_N,JX1,32,IO_L23_33_JX1_N,P5,20 +set_property -dict {PACKAGE_PIN J6 IOSTANDARD LVCMOS18} [get_ports gp_in[40]] ; ## U1,J6,IO_L22_33_JX1_N,JX1,31,IO_L22_33_JX1_N,P5,19 +set_property -dict {PACKAGE_PIN D5 IOSTANDARD LVCMOS18} [get_ports gp_out[41]] ; ## U1,D5,IO_L10_34_JX4_N,JX4,44,IO_L10_34_JX4_N,P6,27 +set_property -dict {PACKAGE_PIN K10 IOSTANDARD LVCMOS18} [get_ports gp_in[41]] ; ## U1,K10,IO_25_34_JX4,JX4,64,IO_25_34_JX4,P5,23 +set_property -dict {PACKAGE_PIN K8 IOSTANDARD LVCMOS18} [get_ports gp_out[42]] ; ## U1,K8,IO_L24_33_JX1_P,JX1,36,IO_L24_33_JX1_P,P5,26 +set_property -dict {PACKAGE_PIN L5 IOSTANDARD LVCMOS18} [get_ports gp_in[42]] ; ## U1,L5,IO_L14_SRCC_33_JX1_P,JX1,48,IO_L14_SRCC_33_JX1_P,P5,25 +set_property -dict {PACKAGE_PIN K7 IOSTANDARD LVCMOS18} [get_ports gp_out[43]] ; ## U1,K7,IO_L24_33_JX1_N,JX1,38,IO_L24_33_JX1_N,P5,28 +set_property -dict {PACKAGE_PIN L4 IOSTANDARD LVCMOS18} [get_ports gp_in[43]] ; ## U1,L4,IO_L14_SRCC_33_JX1_N,JX1,50,IO_L14_SRCC_33_JX1_N,P5,27 +set_property -dict {PACKAGE_PIN N3 IOSTANDARD LVCMOS18} [get_ports gp_out[44]] ; ## U1,N3,IO_L15_33_JX1_P,JX1,53,IO_L15_33_JX1_P,P5,30 +set_property -dict {PACKAGE_PIN M6 IOSTANDARD LVCMOS18} [get_ports gp_in[44]] ; ## U1,M6,IO_L13_MRCC_33_JX1_P,JX1,82,IO_L13_MRCC_33_JX1_P,P5,29 +set_property -dict {PACKAGE_PIN N2 IOSTANDARD LVCMOS18} [get_ports gp_out[45]] ; ## U1,N2,IO_L15_33_JX1_N,JX1,55,IO_L15_33_JX1_N,P5,32 +set_property -dict {PACKAGE_PIN M5 IOSTANDARD LVCMOS18} [get_ports gp_in[45]] ; ## U1,M5,IO_L13_MRCC_33_JX1_N,JX1,84,IO_L13_MRCC_33_JX1_N,P5,31 +set_property -dict {PACKAGE_PIN J11 IOSTANDARD LVCMOS18} [get_ports gp_out[46]] ; ## U1,J11,IO_L01_34_JX4_P,JX4,19,IO_L01_34_JX4_P,P6,2 +set_property -dict {PACKAGE_PIN G6 IOSTANDARD LVCMOS18} [get_ports gp_in[46]] ; ## U1,G6,IO_L02_34_JX4_P,JX4,20,IO_L02_34_JX4_P,P6,1 +set_property -dict {PACKAGE_PIN H11 IOSTANDARD LVCMOS18} [get_ports gp_out[47]] ; ## U1,H11,IO_L01_34_JX4_N,JX4,21,IO_L01_34_JX4_N,P6,4 +set_property -dict {PACKAGE_PIN G5 IOSTANDARD LVCMOS18} [get_ports gp_in[47]] ; ## U1,G5,IO_L02_34_JX4_N,JX4,22,IO_L02_34_JX4_N,P6,3 +set_property -dict {PACKAGE_PIN H9 IOSTANDARD LVCMOS18} [get_ports gp_out[48]] ; ## U1,H9,IO_L03_34_JX4_P,JX4,25,IO_L03_34_JX4_P,P6,6 +set_property -dict {PACKAGE_PIN H7 IOSTANDARD LVCMOS18} [get_ports gp_in[48]] ; ## U1,H7,IO_L04_34_JX4_P,JX4,26,IO_L04_34_JX4_P,P6,5 +set_property -dict {PACKAGE_PIN G9 IOSTANDARD LVCMOS18} [get_ports gp_out[49]] ; ## U1,G9,IO_L03_34_JX4_N,JX4,27,IO_L03_34_JX4_N,P6,8 +set_property -dict {PACKAGE_PIN H6 IOSTANDARD LVCMOS18} [get_ports gp_in[49]] ; ## U1,H6,IO_L04_34_JX4_N,JX4,28,IO_L04_34_JX4_N,P6,7 +set_property -dict {PACKAGE_PIN J10 IOSTANDARD LVCMOS18} [get_ports gp_out[50]] ; ## U1,J10,IO_L05_34_JX4_P,JX4,31,IO_L05_34_JX4_P,P6,14 +set_property -dict {PACKAGE_PIN J8 IOSTANDARD LVCMOS18} [get_ports gp_in[50]] ; ## U1,J8,IO_L06_34_JX4_P,JX4,32,IO_L06_34_JX4_P,P6,13 +set_property -dict {PACKAGE_PIN J9 IOSTANDARD LVCMOS18} [get_ports gp_out[51]] ; ## U1,J9,IO_L05_34_JX4_N,JX4,33,IO_L05_34_JX4_N,P6,16 +set_property -dict {PACKAGE_PIN H8 IOSTANDARD LVCMOS18} [get_ports gp_in[51]] ; ## U1,H8,IO_L06_34_JX4_N,JX4,34,IO_L06_34_JX4_N,P6,15 +set_property -dict {PACKAGE_PIN F5 IOSTANDARD LVCMOS18} [get_ports gp_out[52]] ; ## U1,F5,IO_L07_34_JX4_P,JX4,35,IO_L07_34_JX4_P,P6,18 +set_property -dict {PACKAGE_PIN D9 IOSTANDARD LVCMOS18} [get_ports gp_in[52]] ; ## U1,D9,IO_L08_34_JX4_P,JX4,36,IO_L08_34_JX4_P,P6,17 +set_property -dict {PACKAGE_PIN F8 IOSTANDARD LVCMOS18} [get_ports gp_out[53]] ; ## U1,F8,IO_L11_SRCC_34_JX4_P,JX4,45,IO_L11_SRCC_34_JX4_P,P6,30 +set_property -dict {PACKAGE_PIN G7 IOSTANDARD LVCMOS18} [get_ports gp_in[53]] ; ## U1,G7,IO_L12_MRCC_34_JX4_P,JX4,46,IO_L12_MRCC_34_JX4_P,P6,29 +set_property -dict {PACKAGE_PIN E7 IOSTANDARD LVCMOS18} [get_ports gp_out[54]] ; ## U1,E7,IO_L11_SRCC_34_JX4_N,JX4,47,IO_L11_SRCC_34_JX4_N,P6,32 +set_property -dict {PACKAGE_PIN F7 IOSTANDARD LVCMOS18} [get_ports gp_in[54]] ; ## U1,F7,IO_L12_MRCC_34_JX4_N,JX4,48,IO_L12_MRCC_34_JX4_N,P6,31 +set_property -dict {PACKAGE_PIN C8 IOSTANDARD LVCMOS18} [get_ports gp_out[55]] ; ## U1,C8,IO_L13_MRCC_34_JX4_P,JX4,51,IO_L13_MRCC_34_JX4_P,P7,2 +set_property -dict {PACKAGE_PIN D6 IOSTANDARD LVCMOS18} [get_ports gp_in[55]] ; ## U1,D6,IO_L14_SRCC_34_JX4_P,JX4,52,IO_L14_SRCC_34_JX4_P,P7,1 +set_property -dict {PACKAGE_PIN C7 IOSTANDARD LVCMOS18} [get_ports gp_out[56]] ; ## U1,C7,IO_L13_MRCC_34_JX4_N,JX4,53,IO_L13_MRCC_34_JX4_N,P7,4 +set_property -dict {PACKAGE_PIN C6 IOSTANDARD LVCMOS18} [get_ports gp_in[56]] ; ## U1,C6,IO_L14_SRCC_34_JX4_N,JX4,54,IO_L14_SRCC_34_JX4_N,P7,3 +set_property -dict {PACKAGE_PIN C9 IOSTANDARD LVCMOS18} [get_ports gp_out[57]] ; ## U1,C9,IO_L15_34_JX4_P,JX4,57,IO_L15_34_JX4_P,P7,6 +set_property -dict {PACKAGE_PIN B10 IOSTANDARD LVCMOS18} [get_ports gp_in[57]] ; ## U1,B10,IO_L16_34_JX4_P,JX4,58,IO_L16_34_JX4_P,P7,5 +set_property -dict {PACKAGE_PIN B9 IOSTANDARD LVCMOS18} [get_ports gp_out[58]] ; ## U1,B9,IO_L15_34_JX4_N,JX4,59,IO_L15_34_JX4_N,P7,8 +set_property -dict {PACKAGE_PIN A10 IOSTANDARD LVCMOS18} [get_ports gp_in[58]] ; ## U1,A10,IO_L16_34_JX4_N,JX4,60,IO_L16_34_JX4_N,P7,7 +set_property -dict {PACKAGE_PIN C4 IOSTANDARD LVCMOS18} [get_ports gp_out[59]] ; ## U1,C4,IO_L19_34_JX4_P,JX4,73,IO_L19_34_JX4_P,P7,18 +set_property -dict {PACKAGE_PIN B5 IOSTANDARD LVCMOS18} [get_ports gp_in[59]] ; ## U1,B5,IO_L20_34_JX4_P,JX4,74,IO_L20_34_JX4_P,P7,17 +set_property -dict {PACKAGE_PIN C3 IOSTANDARD LVCMOS18} [get_ports gp_out[60]] ; ## U1,C3,IO_L19_34_JX4_N,JX4,75,IO_L19_34_JX4_N,P7,20 +set_property -dict {PACKAGE_PIN B4 IOSTANDARD LVCMOS18} [get_ports gp_in[60]] ; ## U1,B4,IO_L20_34_JX4_N,JX4,76,IO_L20_34_JX4_N,P7,19 +set_property -dict {PACKAGE_PIN B6 IOSTANDARD LVCMOS18} [get_ports gp_out[61]] ; ## U1,B6,IO_L21_34_JX4_P,JX4,77,IO_L21_34_JX4_P,P7,26 +set_property -dict {PACKAGE_PIN A4 IOSTANDARD LVCMOS18} [get_ports gp_in[61]] ; ## U1,A4,IO_L22_34_JX4_P,JX4,78,IO_L22_34_JX4_P,P7,25 +set_property -dict {PACKAGE_PIN A5 IOSTANDARD LVCMOS18} [get_ports gp_out[62]] ; ## U1,A5,IO_L21_34_JX4_N,JX4,79,IO_L21_34_JX4_N,P7,28 +set_property -dict {PACKAGE_PIN A3 IOSTANDARD LVCMOS18} [get_ports gp_in[62]] ; ## U1,A3,IO_L22_34_JX4_N,JX4,80,IO_L22_34_JX4_N,P7,27 +set_property -dict {PACKAGE_PIN B7 IOSTANDARD LVCMOS18} [get_ports gp_out[63]] ; ## U1,B7,IO_L18_34_JX4_P,JX4,68,IO_L18_34_JX4_P,P7,30 +set_property -dict {PACKAGE_PIN L9 IOSTANDARD LVCMOS18} [get_ports gp_in[63]] ; ## U1,L9,IO_00_33_JX1,JX1,9,IO_00_33_JX1,P7,29 +set_property -dict {PACKAGE_PIN AD15 IOSTANDARD LVCMOS25} [get_ports gp_out[64]] ; ## U1,AD15,IO_L15_12_JX3_N,JX3,99,IO_L15_12_JX3_N,P13,6 +set_property -dict {PACKAGE_PIN AF14 IOSTANDARD LVCMOS25} [get_ports gp_in[64]] ; ## U1,AF14,IO_L16_12_JX3_N,JX3,100,IO_L16_12_JX3_N,P13,5 +set_property -dict {PACKAGE_PIN AD16 IOSTANDARD LVCMOS25} [get_ports gp_out[65]] ; ## U1,AD16,IO_L15_12_JX3_P,JX3,97,IO_L15_12_JX3_P,P13,8 +set_property -dict {PACKAGE_PIN AF15 IOSTANDARD LVCMOS25} [get_ports gp_in[65]] ; ## U1,AF15,IO_L16_12_JX3_P,JX3,98,IO_L16_12_JX3_P,P13,7 +set_property -dict {PACKAGE_PIN AD14 IOSTANDARD LVCMOS25} [get_ports gp_out[66]] ; ## U1,AD14,IO_L13_MRCC_12_JX3_N,JX3,93,IO_L13_MRCC_12_JX3_N,P13,10 +set_property -dict {PACKAGE_PIN AB14 IOSTANDARD LVCMOS25} [get_ports gp_in[66]] ; ## U1,AB14,IO_L14_SRCC_12_JX3_N,JX3,94,IO_L14_SRCC_12_JX3_N,P13,9 +set_property -dict {PACKAGE_PIN AC14 IOSTANDARD LVCMOS25} [get_ports gp_out[67]] ; ## U1,AC14,IO_L13_MRCC_12_JX3_P,JX3,91,IO_L13_MRCC_12_JX3_P,P13,12 +set_property -dict {PACKAGE_PIN AB15 IOSTANDARD LVCMOS25} [get_ports gp_in[67]] ; ## U1,AB15,IO_L14_SRCC_12_JX3_P,JX3,92,IO_L14_SRCC_12_JX3_P,P13,11 +set_property -dict {PACKAGE_PIN AD11 IOSTANDARD LVCMOS25} [get_ports gp_out[68]] ; ## U1,AD11,IO_L11_SRCC_12_JX3_N,JX3,87,IO_L11_SRCC_12_JX3_N,P13,14 +set_property -dict {PACKAGE_PIN AD13 IOSTANDARD LVCMOS25} [get_ports gp_in[68]] ; ## U1,AD13,IO_L12_MRCC_12_JX3_N,JX3,88,IO_L12_MRCC_12_JX3_N,P13,13 +set_property -dict {PACKAGE_PIN AC12 IOSTANDARD LVCMOS25} [get_ports gp_out[69]] ; ## U1,AC12,IO_L11_SRCC_12_JX3_P,JX3,85,IO_L11_SRCC_12_JX3_P,P13,16 +set_property -dict {PACKAGE_PIN AC13 IOSTANDARD LVCMOS25} [get_ports gp_in[69]] ; ## U1,AC13,IO_L12_MRCC_12_JX3_P,JX3,86,IO_L12_MRCC_12_JX3_P,P13,15 +set_property -dict {PACKAGE_PIN AF10 IOSTANDARD LVCMOS25} [get_ports gp_out[70]] ; ## U1,AF10,IO_L09_12_JX3_N,JX3,81,IO_L09_12_JX3_N,P13,20 +set_property -dict {PACKAGE_PIN AF13 IOSTANDARD LVCMOS25} [get_ports gp_in[70]] ; ## U1,AF13,IO_L10_12_JX3_N,JX3,82,IO_L10_12_JX3_N,P13,19 +set_property -dict {PACKAGE_PIN AE11 IOSTANDARD LVCMOS25} [get_ports gp_out[71]] ; ## U1,AE11,IO_L09_12_JX3_P,JX3,79,IO_L09_12_JX3_P,P13,22 +set_property -dict {PACKAGE_PIN AE13 IOSTANDARD LVCMOS25} [get_ports gp_in[71]] ; ## U1,AE13,IO_L10_12_JX3_P,JX3,80,IO_L10_12_JX3_P,P13,21 +set_property -dict {PACKAGE_PIN AD10 IOSTANDARD LVCMOS25} [get_ports gp_out[72]] ; ## U1,AD10,IO_L07_12_JX3_N,JX3,75,IO_L07_12_JX3_N,P13,24 +set_property -dict {PACKAGE_PIN AF12 IOSTANDARD LVCMOS25} [get_ports gp_in[72]] ; ## U1,AF12,IO_L08_12_JX3_N,JX3,76,IO_L08_12_JX3_N,P13,23 +set_property -dict {PACKAGE_PIN AE10 IOSTANDARD LVCMOS25} [get_ports gp_out[73]] ; ## U1,AE10,IO_L07_12_JX3_P,JX3,73,IO_L07_12_JX3_P,P13,26 +set_property -dict {PACKAGE_PIN AE12 IOSTANDARD LVCMOS25} [get_ports gp_in[73]] ; ## U1,AE12,IO_L08_12_JX3_P,JX3,74,IO_L08_12_JX3_P,P13,25 +set_property -dict {PACKAGE_PIN Y13 IOSTANDARD LVCMOS25} [get_ports gp_out[74]] ; ## U1,Y13,IO_L05_12_JX3_N,JX3,44,IO_L05_12_JX3_N,P13,28 +set_property -dict {PACKAGE_PIN AA12 IOSTANDARD LVCMOS25} [get_ports gp_in[74]] ; ## U1,AA12,IO_L06_12_JX3_N,JX3,66,IO_L06_12_JX3_N,P13,27 +set_property -dict {PACKAGE_PIN W13 IOSTANDARD LVCMOS25} [get_ports gp_out[75]] ; ## U1,W13,IO_L05_12_JX3_P,JX3,42,IO_L05_12_JX3_P,P13,30 +set_property -dict {PACKAGE_PIN AA13 IOSTANDARD LVCMOS25} [get_ports gp_in[75]] ; ## U1,AA13,IO_L06_12_JX3_P,JX3,64,IO_L06_12_JX3_P,P13,29 +set_property -dict {PACKAGE_PIN AA10 IOSTANDARD LVCMOS25} [get_ports gp_out[76]] ; ## U1,AA10,IO_L03_12_JX3_N,JX3,28,IO_L03_12_JX3_N,P13,32 +set_property -dict {PACKAGE_PIN AB10 IOSTANDARD LVCMOS25} [get_ports gp_in[76]] ; ## U1,AB10,IO_L04_12_JX3_N,JX3,33,IO_L04_12_JX3_N,P13,31 +set_property -dict {PACKAGE_PIN Y10 IOSTANDARD LVCMOS25} [get_ports gp_out[77]] ; ## U1,Y10,IO_L03_12_JX3_P,JX3,26,IO_L03_12_JX3_P,P13,34 +set_property -dict {PACKAGE_PIN AB11 IOSTANDARD LVCMOS25} [get_ports gp_in[77]] ; ## U1,AB11,IO_L04_12_JX3_P,JX3,31,IO_L04_12_JX3_P,P13,33 +set_property -dict {PACKAGE_PIN Y11 IOSTANDARD LVCMOS25} [get_ports gp_out[78]] ; ## U1,Y11,IO_L01_12_JX3_N,JX3,22,IO_L01_12_JX3_N,P13,36 +set_property -dict {PACKAGE_PIN AC11 IOSTANDARD LVCMOS25} [get_ports gp_in[78]] ; ## U1,AC11,IO_L02_12_JX3_N,JX3,27,IO_L02_12_JX3_N,P13,35 +set_property -dict {PACKAGE_PIN Y12 IOSTANDARD LVCMOS25} [get_ports gp_out[79]] ; ## U1,Y12,IO_L01_12_JX3_P,JX3,20,IO_L01_12_JX3_P,P13,38 +set_property -dict {PACKAGE_PIN AB12 IOSTANDARD LVCMOS25} [get_ports gp_in[79]] ; ## U1,AB12,IO_L02_12_JX3_P,JX3,25,IO_L02_12_JX3_P,P13,37 +set_property -dict {PACKAGE_PIN AE16 IOSTANDARD LVCMOS25} [get_ports gp_out[80]] ; ## U1,AE16,IO_L17_12_JX2_P,JX2,82,IO_L17_12_JX2_P,P13,42 +set_property -dict {PACKAGE_PIN AE17 IOSTANDARD LVCMOS25} [get_ports gp_in[80]] ; ## U1,AE17,IO_L18_12_JX2_P,JX2,81,IO_L18_12_JX2_P,P13,41 +set_property -dict {PACKAGE_PIN AE15 IOSTANDARD LVCMOS25} [get_ports gp_out[81]] ; ## U1,AE15,IO_L17_12_JX2_N,JX2,84,IO_L17_12_JX2_N,P13,44 +set_property -dict {PACKAGE_PIN AF17 IOSTANDARD LVCMOS25} [get_ports gp_in[81]] ; ## U1,AF17,IO_L18_12_JX2_N,JX2,83,IO_L18_12_JX2_N,P13,43 +set_property -dict {PACKAGE_PIN Y17 IOSTANDARD LVCMOS25} [get_ports gp_out[82]] ; ## U1,Y17,IO_L19_12_JX2_P,JX2,88,IO_L19_12_JX2_P,P13,46 +set_property -dict {PACKAGE_PIN AB17 IOSTANDARD LVCMOS25} [get_ports gp_in[82]] ; ## U1,AB17,IO_L20_12_JX2_P,JX2,87,IO_L20_12_JX2_P,P13,45 +set_property -dict {PACKAGE_PIN AA17 IOSTANDARD LVCMOS25} [get_ports gp_out[83]] ; ## U1,AA17,IO_L19_12_JX2_N,JX2,90,IO_L19_12_JX2_N,P13,48 +set_property -dict {PACKAGE_PIN AB16 IOSTANDARD LVCMOS25} [get_ports gp_in[83]] ; ## U1,AB16,IO_L20_12_JX2_N,JX2,89,IO_L20_12_JX2_N,P13,47 +set_property -dict {PACKAGE_PIN AC17 IOSTANDARD LVCMOS25} [get_ports gp_out[84]] ; ## U1,AC17,IO_L21_12_JX2_P,JX2,93,IO_L21_12_JX2_P,P13,50 +set_property -dict {PACKAGE_PIN AA15 IOSTANDARD LVCMOS25} [get_ports gp_in[84]] ; ## U1,AA15,IO_L22_12_JX2_P,JX2,94,IO_L22_12_JX2_P,P13,49 +set_property -dict {PACKAGE_PIN AC16 IOSTANDARD LVCMOS25} [get_ports gp_out[85]] ; ## U1,AC16,IO_L21_12_JX2_N,JX2,95,IO_L21_12_JX2_N,P13,52 +set_property -dict {PACKAGE_PIN AA14 IOSTANDARD LVCMOS25} [get_ports gp_in[85]] ; ## U1,AA14,IO_L22_12_JX2_N,JX2,96,IO_L22_12_JX2_N,P13,51 + +## transceiver loop-backs (on-ccbrk) + +set_property -dict {PACKAGE_PIN R6} [get_ports gt_ref_clk_p] ; ## U1,R6,MGTREFCLK0_112_JX1_P (JX1,87) +set_property -dict {PACKAGE_PIN R5} [get_ports gt_ref_clk_n] ; ## U1,R5,MGTREFCLK0_112_JX1_N (JX1,89) +set_property -dict {PACKAGE_PIN AB4} [get_ports gt_rx_p[0]] ; ## U1,AB4,MGTXRX0_112_JX1_P (JX1,88) +set_property -dict {PACKAGE_PIN AB3} [get_ports gt_rx_n[0]] ; ## U1,AB3,MGTXRX0_112_JX1_N (JX1,90) +set_property -dict {PACKAGE_PIN Y4} [get_ports gt_rx_p[1]] ; ## U1,Y4,MGTXRX1_112_JX1_P (JX1,91) +set_property -dict {PACKAGE_PIN Y3} [get_ports gt_rx_n[1]] ; ## U1,Y3,MGTXRX1_112_JX1_N (JX1,93) +set_property -dict {PACKAGE_PIN V4} [get_ports gt_rx_p[2]] ; ## U1,V4,MGTXRX2_112_JX1_P (JX1,92) +set_property -dict {PACKAGE_PIN V3} [get_ports gt_rx_n[2]] ; ## U1,V3,MGTXRX2_112_JX1_N (JX1,94) +set_property -dict {PACKAGE_PIN T4} [get_ports gt_rx_p[3]] ; ## U1,T4,MGTXRX3_112_JX1_P (JX1,97) +set_property -dict {PACKAGE_PIN T3} [get_ports gt_rx_n[3]] ; ## U1,T3,MGTXRX3_112_JX1_N (JX1,99) +set_property -dict {PACKAGE_PIN AA2} [get_ports gt_tx_p[0]] ; ## U1,AA2,MGTXTX0_112_JX3_P (JX3,8) +set_property -dict {PACKAGE_PIN AA1} [get_ports gt_tx_n[0]] ; ## U1,AA1,MGTXTX0_112_JX3_N (JX3,10) +set_property -dict {PACKAGE_PIN W2} [get_ports gt_tx_p[1]] ; ## U1,W2,MGTXTX1_112_JX3_P (JX3,13) +set_property -dict {PACKAGE_PIN W1} [get_ports gt_tx_n[1]] ; ## U1,W1,MGTXTX1_112_JX3_N (JX3,15) +set_property -dict {PACKAGE_PIN U2} [get_ports gt_tx_p[2]] ; ## U1,U2,MGTXTX2_112_JX3_P (JX3,14) +set_property -dict {PACKAGE_PIN U1} [get_ports gt_tx_n[2]] ; ## U1,U1,MGTXTX2_112_JX3_N (JX3,16) +set_property -dict {PACKAGE_PIN R2} [get_ports gt_tx_p[3]] ; ## U1,R2,MGTXTX3_112_JX3_P (JX3,19) +set_property -dict {PACKAGE_PIN R1} [get_ports gt_tx_n[3]] ; ## U1,R1,MGTXTX3_112_JX3_N (JX3,21) + +## clocks + +create_clock -name ref_clk -period 4.00 [get_ports gt_ref_clk_p] +create_clock -name xcvr_clk_0 -period 8.00 [get_pins i_system_wrapper/system_i/axi_pz_xcvrlb/inst/g_lanes[0].i_xcvrlb_1/i_xch/i_gtxe2_channel/RXOUTCLK] +create_clock -name xcvr_clk_1 -period 8.00 [get_pins i_system_wrapper/system_i/axi_pz_xcvrlb/inst/g_lanes[1].i_xcvrlb_1/i_xch/i_gtxe2_channel/RXOUTCLK] +create_clock -name xcvr_clk_2 -period 8.00 [get_pins i_system_wrapper/system_i/axi_pz_xcvrlb/inst/g_lanes[2].i_xcvrlb_1/i_xch/i_gtxe2_channel/RXOUTCLK] +create_clock -name xcvr_clk_3 -period 8.00 [get_pins i_system_wrapper/system_i/axi_pz_xcvrlb/inst/g_lanes[3].i_xcvrlb_1/i_xch/i_gtxe2_channel/RXOUTCLK] + + diff --git a/projects/pzsdr/common/ccfmc_bd.tcl b/projects/pzsdr2/common/ccfmc_bd.tcl similarity index 53% rename from projects/pzsdr/common/ccfmc_bd.tcl rename to projects/pzsdr2/common/ccfmc_bd.tcl index b4da554ca..09a99b468 100644 --- a/projects/pzsdr/common/ccfmc_bd.tcl +++ b/projects/pzsdr2/common/ccfmc_bd.tcl @@ -5,15 +5,7 @@ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:mdio_rtl:1.0 eth1_mdio create_bd_intf_port -mode Master -vlnv xilinx.com:interface:rgmii_rtl:1.0 eth1_rgmii -create_bd_port -dir O eth1_link_status -create_bd_port -dir O eth1_duplex_status -create_bd_port -dir O -type clk eth1_refclk -create_bd_port -dir O -type clk eth1_125mclk -create_bd_port -dir O -type clk eth1_25mclk -create_bd_port -dir O -type clk eth1_2m5clk create_bd_port -dir I -type intr eth1_intn -create_bd_port -dir O -from 1 -to 0 eth1_clock_speed -create_bd_port -dir O -from 1 -to 0 eth1_speed_mode # hdmi interface @@ -59,7 +51,7 @@ set_property -dict [list CONFIG.c_include_s2mm {0}] $axi_hdmi_dma # audio peripherals -set sys_audio_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.2 sys_audio_clkgen] +set sys_audio_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.3 sys_audio_clkgen] set_property -dict [list CONFIG.PRIM_IN_FREQ {200.000}] $sys_audio_clkgen set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {12.288}] $sys_audio_clkgen set_property -dict [list CONFIG.USE_LOCKED {false}] $sys_audio_clkgen @@ -80,14 +72,6 @@ ad_connect sys_ps7/MDIO_ETHERNET_1 sys_rgmii/MDIO_GEM ad_connect sys_ps7/GMII_ETHERNET_1 sys_rgmii/GMII ad_connect sys_rgmii/MDIO_PHY eth1_mdio ad_connect sys_rgmii/RGMII eth1_rgmii -ad_connect sys_rgmii/ref_clk_out eth1_refclk -ad_connect sys_rgmii/gmii_clk_125m_out eth1_125mclk -ad_connect sys_rgmii/gmii_clk_25m_out eth1_25mclk -ad_connect sys_rgmii/gmii_clk_2_5m_out eth1_2m5clk -ad_connect sys_rgmii/link_status eth1_link_status -ad_connect sys_rgmii/duplex_status eth1_duplex_status -ad_connect sys_rgmii/clock_speed eth1_clock_speed -ad_connect sys_rgmii/speed_mode eth1_speed_mode ad_connect sys_ps7/ENET1_EXT_INTIN eth1_intn ad_connect sys_200m_clk sys_rgmii_rstgen/slowest_sync_clk ad_connect sys_200m_clk sys_rgmii/clkin @@ -155,123 +139,49 @@ ad_mem_hp0_interconnect sys_cpu_clk axi_hdmi_dma/M_AXI_MM2S # un-used io (gt) -set axi_pzslb_gt [create_bd_cell -type ip -vlnv analog.com:user:axi_jesd_gt:1.0 axi_pzslb_gt] -set_property -dict [list CONFIG.NUM_OF_LANES {2}] $axi_pzslb_gt -set_property -dict [list CONFIG.QPLL1_ENABLE {0}] $axi_pzslb_gt -set_property -dict [list CONFIG.RX_NUM_OF_LANES {2}] $axi_pzslb_gt -set_property -dict [list CONFIG.TX_NUM_OF_LANES {2}] $axi_pzslb_gt -set_property -dict [list CONFIG.RX_CLKBUF_ENABLE_0 {1}] $axi_pzslb_gt -set_property -dict [list CONFIG.TX_CLKBUF_ENABLE_0 {1}] $axi_pzslb_gt -set_property -dict [list CONFIG.TX_DATA_SEL_0 {0}] $axi_pzslb_gt -set_property -dict [list CONFIG.CPLL_FBDIV_0 {2}] $axi_pzslb_gt -set_property -dict [list CONFIG.RX_OUT_DIV_0 {1}] $axi_pzslb_gt -set_property -dict [list CONFIG.TX_OUT_DIV_0 {1}] $axi_pzslb_gt -set_property -dict [list CONFIG.RX_CLK25_DIV_0 {10}] $axi_pzslb_gt -set_property -dict [list CONFIG.TX_CLK25_DIV_0 {10}] $axi_pzslb_gt -set_property -dict [list CONFIG.PMA_RSV_0 {0x00018480}] $axi_pzslb_gt -set_property -dict [list CONFIG.RX_CDR_CFG_0 {0x03000023ff20400020}] $axi_pzslb_gt -set_property -dict [list CONFIG.RX_CLKBUF_ENABLE_1 {1}] $axi_pzslb_gt -set_property -dict [list CONFIG.TX_CLKBUF_ENABLE_1 {1}] $axi_pzslb_gt -set_property -dict [list CONFIG.TX_DATA_SEL_1 {1}] $axi_pzslb_gt -set_property -dict [list CONFIG.CPLL_FBDIV_1 {2}] $axi_pzslb_gt -set_property -dict [list CONFIG.RX_OUT_DIV_1 {1}] $axi_pzslb_gt -set_property -dict [list CONFIG.TX_OUT_DIV_1 {1}] $axi_pzslb_gt -set_property -dict [list CONFIG.RX_CLK25_DIV_1 {10}] $axi_pzslb_gt -set_property -dict [list CONFIG.TX_CLK25_DIV_1 {10}] $axi_pzslb_gt -set_property -dict [list CONFIG.PMA_RSV_1 {0x00018480}] $axi_pzslb_gt -set_property -dict [list CONFIG.RX_CDR_CFG_1 {0x03000023ff20400020}] $axi_pzslb_gt - -set util_pzslb_gtlb_0 [create_bd_cell -type ip -vlnv analog.com:user:util_gtlb:1.0 util_pzslb_gtlb_0] -set util_pzslb_gtlb_1 [create_bd_cell -type ip -vlnv analog.com:user:util_gtlb:1.0 util_pzslb_gtlb_1] - -ad_cpu_interconnect 0x44A60000 axi_pzslb_gt -ad_mem_hp3_interconnect sys_cpu_clk sys_ps7/S_AXI_HP3 -ad_mem_hp3_interconnect sys_cpu_clk axi_pzslb_gt/m_axi +set axi_pz_xcvrlb [create_bd_cell -type ip -vlnv analog.com:user:axi_xcvrlb:1.0 axi_pz_xcvrlb] +set_property -dict [list CONFIG.NUM_OF_LANES {2}] $axi_pz_xcvrlb create_bd_port -dir I gt_ref_clk_0 -create_bd_port -dir I gt_ref_clk_1 -create_bd_port -dir I gt_rx_0_p -create_bd_port -dir I gt_rx_0_n -create_bd_port -dir O gt_tx_0_p -create_bd_port -dir O gt_tx_0_n -create_bd_port -dir I gt_rx_1_p -create_bd_port -dir I gt_rx_1_n -create_bd_port -dir O gt_tx_1_p -create_bd_port -dir O gt_tx_1_n +create_bd_port -dir I -from 1 -to 0 gt_rx_p +create_bd_port -dir I -from 1 -to 0 gt_rx_n +create_bd_port -dir O -from 1 -to 0 gt_tx_p +create_bd_port -dir O -from 1 -to 0 gt_tx_n -ad_connect sys_cpu_clk util_pzslb_gtlb_0/up_clk -ad_connect sys_cpu_resetn util_pzslb_gtlb_0/up_rstn -ad_connect util_pzslb_gtlb_0/qpll_ref_clk gt_ref_clk_0 -ad_connect util_pzslb_gtlb_0/cpll_ref_clk gt_ref_clk_0 -ad_connect util_pzslb_gtlb_0/rx_p gt_rx_0_p -ad_connect util_pzslb_gtlb_0/rx_n gt_rx_0_n -ad_connect util_pzslb_gtlb_0/tx_p gt_tx_0_p -ad_connect util_pzslb_gtlb_0/tx_n gt_tx_0_n -ad_connect sys_cpu_clk util_pzslb_gtlb_1/up_clk -ad_connect sys_cpu_resetn util_pzslb_gtlb_1/up_rstn -ad_connect util_pzslb_gtlb_1/qpll_ref_clk gt_ref_clk_0 -ad_connect util_pzslb_gtlb_1/cpll_ref_clk gt_ref_clk_0 -ad_connect util_pzslb_gtlb_1/rx_p gt_rx_1_p -ad_connect util_pzslb_gtlb_1/rx_n gt_rx_1_n -ad_connect util_pzslb_gtlb_1/tx_p gt_tx_1_p -ad_connect util_pzslb_gtlb_1/tx_n gt_tx_1_n -ad_connect axi_pzslb_gt/gt_qpll_0 util_pzslb_gtlb_0/gt_qpll_0 -ad_connect axi_pzslb_gt/gt_pll_0 util_pzslb_gtlb_0/gt_pll_0 -ad_connect axi_pzslb_gt/gt_rx_0 util_pzslb_gtlb_0/gt_rx_0 -ad_connect axi_pzslb_gt/gt_tx_0 util_pzslb_gtlb_0/gt_tx_0 -ad_connect axi_pzslb_gt/gt_rx_ip_0 util_pzslb_gtlb_0/gt_rx_ip_0 -ad_connect axi_pzslb_gt/gt_tx_ip_0 util_pzslb_gtlb_0/gt_tx_ip_0 -ad_connect axi_pzslb_gt/rx_gt_comma_align_enb_0 util_pzslb_gtlb_0/rx_gt_comma_align_enb_0 -ad_connect axi_pzslb_gt/gt_pll_1 util_pzslb_gtlb_1/gt_pll_0 -ad_connect axi_pzslb_gt/gt_rx_1 util_pzslb_gtlb_1/gt_rx_0 -ad_connect axi_pzslb_gt/gt_tx_1 util_pzslb_gtlb_1/gt_tx_0 -ad_connect axi_pzslb_gt/gt_rx_ip_1 util_pzslb_gtlb_1/gt_rx_ip_0 -ad_connect axi_pzslb_gt/gt_tx_ip_1 util_pzslb_gtlb_1/gt_tx_ip_0 -ad_connect axi_pzslb_gt/rx_gt_comma_align_enb_1 util_pzslb_gtlb_1/rx_gt_comma_align_enb_0 +ad_cpu_interconnect 0x44A60000 axi_pz_xcvrlb +ad_connect axi_pz_xcvrlb/ref_clk gt_ref_clk_0 +ad_connect axi_pz_xcvrlb/rx_p gt_rx_p +ad_connect axi_pz_xcvrlb/rx_n gt_rx_n +ad_connect axi_pz_xcvrlb/tx_p gt_tx_p +ad_connect axi_pz_xcvrlb/tx_n gt_tx_n # un-used io (regular) set axi_gpreg [create_bd_cell -type ip -vlnv analog.com:user:axi_gpreg:1.0 axi_gpreg] -set_property -dict [list CONFIG.NUM_OF_CLK_MONS {8}] $axi_gpreg +set_property -dict [list CONFIG.NUM_OF_CLK_MONS {3}] $axi_gpreg +set_property -dict [list CONFIG.NUM_OF_IO {2}] $axi_gpreg set_property -dict [list CONFIG.BUF_ENABLE_0 {1}] $axi_gpreg set_property -dict [list CONFIG.BUF_ENABLE_1 {1}] $axi_gpreg set_property -dict [list CONFIG.BUF_ENABLE_2 {1}] $axi_gpreg -set_property -dict [list CONFIG.BUF_ENABLE_3 {0}] $axi_gpreg -set_property -dict [list CONFIG.BUF_ENABLE_4 {0}] $axi_gpreg -set_property -dict [list CONFIG.BUF_ENABLE_5 {1}] $axi_gpreg -set_property -dict [list CONFIG.BUF_ENABLE_6 {0}] $axi_gpreg -set_property -dict [list CONFIG.BUF_ENABLE_7 {0}] $axi_gpreg -set_property -dict [list CONFIG.NUM_OF_IO {4}] $axi_gpreg - -ad_cpu_interconnect 0x41200000 axi_gpreg - -create_bd_port -dir I clk_0 -create_bd_port -dir I clk_1 -ad_connect clk_0 axi_gpreg/d_clk_0 -ad_connect clk_1 axi_gpreg/d_clk_1 -ad_connect gt_ref_clk_0 axi_gpreg/d_clk_2 -ad_connect util_pzslb_gtlb_0/rx_clk axi_gpreg/d_clk_3 -ad_connect util_pzslb_gtlb_0/tx_clk axi_gpreg/d_clk_4 -ad_connect gt_ref_clk_1 axi_gpreg/d_clk_5 -ad_connect util_pzslb_gtlb_1/rx_clk axi_gpreg/d_clk_6 -ad_connect util_pzslb_gtlb_1/tx_clk axi_gpreg/d_clk_7 create_bd_port -dir I -from 31 -to 0 gp_in_0 create_bd_port -dir I -from 31 -to 0 gp_in_1 create_bd_port -dir O -from 31 -to 0 gp_out_0 create_bd_port -dir O -from 31 -to 0 gp_out_1 +create_bd_port -dir I clk_0 +create_bd_port -dir I clk_1 +create_bd_port -dir I gt_ref_clk_1 +ad_connect clk_0 axi_gpreg/d_clk_0 +ad_connect clk_1 axi_gpreg/d_clk_1 +ad_connect gt_ref_clk_1 axi_gpreg/d_clk_2 ad_connect gp_in_0 axi_gpreg/up_gp_in_0 ad_connect gp_in_1 axi_gpreg/up_gp_in_1 ad_connect gp_out_0 axi_gpreg/up_gp_out_0 ad_connect gp_out_1 axi_gpreg/up_gp_out_1 -ad_connect axi_gpreg/up_gp_in_2 util_pzslb_gtlb_0/up_gp_out -ad_connect axi_gpreg/up_gp_out_2 util_pzslb_gtlb_0/up_gp_in -ad_connect axi_gpreg/up_gp_in_3 util_pzslb_gtlb_1/up_gp_out -ad_connect axi_gpreg/up_gp_out_3 util_pzslb_gtlb_1/up_gp_in +ad_cpu_interconnect 0x41200000 axi_gpreg ## temporary (remove ila indirectly) delete_bd_objs [get_bd_cells ila_adc] -delete_bd_objs [get_bd_nets axi_ad9361_tdd_dbg] [get_bd_cells ila_tdd] diff --git a/projects/pzsdr2/common/ccfmc_constr.xdc b/projects/pzsdr2/common/ccfmc_constr.xdc new file mode 100644 index 000000000..bec9d8b10 --- /dev/null +++ b/projects/pzsdr2/common/ccfmc_constr.xdc @@ -0,0 +1,274 @@ + +# rf-board + +set_property -dict {PACKAGE_PIN K10 IOSTANDARD LVCMOS18} [get_ports gpio_rfpwr_enable] ; ## U1,K10,IO_25_34_JX4,JX4,64,RF_GPIO4_BANK34 +set_property -dict {PACKAGE_PIN AA20 IOSTANDARD LVCMOS25} [get_ports gpio_rf0] ; ## U1,AA20,IO_L20_13_JX2_P,JX2,62,RF_GPIO0_BANK13 +set_property -dict {PACKAGE_PIN AB20 IOSTANDARD LVCMOS25} [get_ports gpio_rf1] ; ## U1,AB20,IO_L20_13_JX2_N,JX2,64,RF_GPIO1_BANK13 +set_property -dict {PACKAGE_PIN AA14 IOSTANDARD LVCMOS25} [get_ports gpio_rf2] ; ## U1,AA14,IO_L22_12_JX2_N,JX2,96,RF_GPIO2_BANK12 +set_property -dict {PACKAGE_PIN J9 IOSTANDARD LVCMOS18} [get_ports gpio_rf3] ; ## U1,J9,IO_L05_34_JX4_N,JX4,33,RF_GPIO3_BANK34 +set_property -dict {PACKAGE_PIN A9 IOSTANDARD LVCMOS18} [get_ports gpio_rf4] ; ## U1,A9,IO_L17_34_JX4_P,JX4,67,RF_GPIO5_BANK34 +set_property -dict {PACKAGE_PIN W19 IOSTANDARD LVCMOS25} [get_ports tdd_sync] ; ## U1,W19,IO_L23_13_JX2_N,JX2,75,PMOD0_D5,R105,1 + +# ethernet-1 (U1,B20,PS_MIO51_501_JX4,JX4,100,ETH1_RESETN) + +set_property -dict {PACKAGE_PIN B10 IOSTANDARD LVCMOS18} [get_ports eth1_mdc] ; ## U1,B10,IO_L16_34_JX4_P,JX4,58,ETH1_MDC +set_property -dict {PACKAGE_PIN A10 IOSTANDARD LVCMOS18} [get_ports eth1_mdio] ; ## U1,A10,IO_L16_34_JX4_N,JX4,60,ETH1_MDIO +set_property -dict {PACKAGE_PIN G7 IOSTANDARD LVCMOS18} [get_ports eth1_rgmii_rxclk] ; ## U1,G7,IO_L12_MRCC_34_JX4_P,JX4,46,ETH1_RX_CLK +set_property -dict {PACKAGE_PIN F7 IOSTANDARD LVCMOS18} [get_ports eth1_rgmii_rxctl] ; ## U1,F7,IO_L12_MRCC_34_JX4_N,JX4,48,ETH1_RX_CTRL +set_property -dict {PACKAGE_PIN E6 IOSTANDARD LVCMOS18} [get_ports eth1_rgmii_rxdata[0]] ; ## U1,E6,IO_L10_34_JX4_P,JX4,42,ETH1_RXD0 +set_property -dict {PACKAGE_PIN D5 IOSTANDARD LVCMOS18} [get_ports eth1_rgmii_rxdata[1]] ; ## U1,D5,IO_L10_34_JX4_N,JX4,44,ETH1_RXD1 +set_property -dict {PACKAGE_PIN F8 IOSTANDARD LVCMOS18} [get_ports eth1_rgmii_rxdata[2]] ; ## U1,F8,IO_L11_SRCC_34_JX4_P,JX4,45,ETH1_RXD2 +set_property -dict {PACKAGE_PIN E7 IOSTANDARD LVCMOS18} [get_ports eth1_rgmii_rxdata[3]] ; ## U1,E7,IO_L11_SRCC_34_JX4_N,JX4,47,ETH1_RXD3 +set_property -dict {PACKAGE_PIN C8 IOSTANDARD LVCMOS18} [get_ports eth1_rgmii_txclk] ; ## U1,C8,IO_L13_MRCC_34_JX4_P,JX4,51,ETH1_TX_CLK +set_property -dict {PACKAGE_PIN C7 IOSTANDARD LVCMOS18} [get_ports eth1_rgmii_txctl] ; ## U1,C7,IO_L13_MRCC_34_JX4_N,JX4,53,ETH1_TX_CTRL +set_property -dict {PACKAGE_PIN D6 IOSTANDARD LVCMOS18} [get_ports eth1_rgmii_txdata[0]] ; ## U1,D6,IO_L14_SRCC_34_JX4_P,JX4,52,ETH1_TXD0 +set_property -dict {PACKAGE_PIN C6 IOSTANDARD LVCMOS18} [get_ports eth1_rgmii_txdata[1]] ; ## U1,C6,IO_L14_SRCC_34_JX4_N,JX4,54,ETH1_TXD1 +set_property -dict {PACKAGE_PIN C9 IOSTANDARD LVCMOS18} [get_ports eth1_rgmii_txdata[2]] ; ## U1,C9,IO_L15_34_JX4_P,JX4,57,ETH1_TXD2 +set_property -dict {PACKAGE_PIN B9 IOSTANDARD LVCMOS18} [get_ports eth1_rgmii_txdata[3]] ; ## U1,B9,IO_L15_34_JX4_N,JX4,59,ETH1_TXD3 + +# hdmi + +set_property -dict {PACKAGE_PIN L3 IOSTANDARD LVCMOS18} [get_ports hdmi_out_clk] ; ## U1,L3,IO_L11_SRCC_33_JX1_P,JX1,74,HDMI_CLK +set_property -dict {PACKAGE_PIN D4 IOSTANDARD LVCMOS18 IOB TRUE} [get_ports hdmi_vsync] ; ## U1,D4,IO_L02_33_JX1_P,JX1,41,HDMI_VSYNC +set_property -dict {PACKAGE_PIN D3 IOSTANDARD LVCMOS18 IOB TRUE} [get_ports hdmi_hsync] ; ## U1,D3,IO_L02_33_JX1_N,JX1,43,HDMI_HSYNC +set_property -dict {PACKAGE_PIN K3 IOSTANDARD LVCMOS18 IOB TRUE} [get_ports hdmi_data_e] ; ## U1,K3,IO_L11_SRCC_33_JX1_N,JX1,76,HDMI_DE +set_property -dict {PACKAGE_PIN G2 IOSTANDARD LVCMOS18 IOB TRUE} [get_ports hdmi_data[0]] ; ## U1,G2,IO_L03_33_JX1_P,JX1,42,HDMI_D20 +set_property -dict {PACKAGE_PIN F2 IOSTANDARD LVCMOS18 IOB TRUE} [get_ports hdmi_data[1]] ; ## U1,F2,IO_L03_33_JX1_N,JX1,44,HDMI_D21 +set_property -dict {PACKAGE_PIN D1 IOSTANDARD LVCMOS18 IOB TRUE} [get_ports hdmi_data[2]] ; ## U1,D1,IO_L04_33_JX1_P,JX1,47,HDMI_D22 +set_property -dict {PACKAGE_PIN C1 IOSTANDARD LVCMOS18 IOB TRUE} [get_ports hdmi_data[3]] ; ## U1,C1,IO_L04_33_JX1_N,JX1,49,HDMI_D23 +set_property -dict {PACKAGE_PIN E2 IOSTANDARD LVCMOS18 IOB TRUE} [get_ports hdmi_data[4]] ; ## U1,E2,IO_L05_33_JX1_P,JX1,54,HDMI_D24 +set_property -dict {PACKAGE_PIN E1 IOSTANDARD LVCMOS18 IOB TRUE} [get_ports hdmi_data[5]] ; ## U1,E1,IO_L05_33_JX1_N,JX1,56,HDMI_D25 +set_property -dict {PACKAGE_PIN F3 IOSTANDARD LVCMOS18 IOB TRUE} [get_ports hdmi_data[6]] ; ## U1,F3,IO_L06_33_JX1_P,JX1,61,HDMI_D26 +set_property -dict {PACKAGE_PIN E3 IOSTANDARD LVCMOS18 IOB TRUE} [get_ports hdmi_data[7]] ; ## U1,E3,IO_L06_33_JX1_N,JX1,63,HDMI_D27 +set_property -dict {PACKAGE_PIN J1 IOSTANDARD LVCMOS18 IOB TRUE} [get_ports hdmi_data[8]] ; ## U1,J1,IO_L07_33_JX1_P,JX1,62,HDMI_D28 +set_property -dict {PACKAGE_PIN H1 IOSTANDARD LVCMOS18 IOB TRUE} [get_ports hdmi_data[9]] ; ## U1,H1,IO_L07_33_JX1_N,JX1,64,HDMI_D29 +set_property -dict {PACKAGE_PIN H4 IOSTANDARD LVCMOS18 IOB TRUE} [get_ports hdmi_data[10]] ; ## U1,H4,IO_L08_33_JX1_P,JX1,67,HDMI_D30 +set_property -dict {PACKAGE_PIN H3 IOSTANDARD LVCMOS18 IOB TRUE} [get_ports hdmi_data[11]] ; ## U1,H3,IO_L08_33_JX1_N,JX1,69,HDMI_D31 +set_property -dict {PACKAGE_PIN K2 IOSTANDARD LVCMOS18 IOB TRUE} [get_ports hdmi_data[12]] ; ## U1,K2,IO_L09_33_JX1_P,JX1,68,HDMI_D32 +set_property -dict {PACKAGE_PIN K1 IOSTANDARD LVCMOS18 IOB TRUE} [get_ports hdmi_data[13]] ; ## U1,K1,IO_L09_33_JX1_N,JX1,70,HDMI_D33 +set_property -dict {PACKAGE_PIN H2 IOSTANDARD LVCMOS18 IOB TRUE} [get_ports hdmi_data[14]] ; ## U1,H2,IO_L10_33_JX1_P,JX1,73,HDMI_D34 +set_property -dict {PACKAGE_PIN G1 IOSTANDARD LVCMOS18 IOB TRUE} [get_ports hdmi_data[15]] ; ## U1,G1,IO_L10_33_JX1_N,JX1,75,HDMI_D35 +set_property -dict {PACKAGE_PIN L9 IOSTANDARD LVCMOS18} [get_ports hdmi_pd] ; ## U1,L9,IO_00_33_JX1,JX1,9,HDMI_PD +set_property -dict {PACKAGE_PIN N8 IOSTANDARD LVCMOS18} [get_ports hdmi_intn] ; ## U1,N8,IO_25_33_JX1,JX1,10,HDMI_INTN + +# hdmi-spdif + +set_property -dict {PACKAGE_PIN G4 IOSTANDARD LVCMOS18} [get_ports spdif] ; ## U1,G4,IO_L01_33_JX1_P,JX1,35,HDMI_SPDIF +set_property -dict {PACKAGE_PIN F4 IOSTANDARD LVCMOS18} [get_ports spdif_in] ; ## U1,F4,IO_L01_33_JX1_N,JX1,37,HDMI_SPDIF_OUT + +# audio + +set_property -dict {PACKAGE_PIN J8 IOSTANDARD LVCMOS18} [get_ports i2s_mclk] ; ## U1,J8,IO_L06_34_JX4_P,JX4,32,I2S_MCLK +set_property -dict {PACKAGE_PIN H8 IOSTANDARD LVCMOS18} [get_ports i2s_bclk] ; ## U1,H8,IO_L06_34_JX4_N,JX4,34,I2S_BCLK +set_property -dict {PACKAGE_PIN F5 IOSTANDARD LVCMOS18} [get_ports i2s_lrclk] ; ## U1,F5,IO_L07_34_JX4_P,JX4,35,I2S_LRCLK +set_property -dict {PACKAGE_PIN E5 IOSTANDARD LVCMOS18} [get_ports i2s_sdata_out] ; ## U1,E5,IO_L07_34_JX4_N,JX4,37,I2S_SDATA_OUT +set_property -dict {PACKAGE_PIN D9 IOSTANDARD LVCMOS18} [get_ports i2s_sdata_in] ; ## U1,D9,IO_L08_34_JX4_P,JX4,36,I2S_SDATA_IN + +# ad9517 + +set_property -dict {PACKAGE_PIN B4 IOSTANDARD LVCMOS18} [get_ports ad9517_csn] ; ## U1,B4,IO_L20_34_JX4_N,JX4,76,PMOD1_D3 +set_property -dict {PACKAGE_PIN C4 IOSTANDARD LVCMOS18} [get_ports ad9517_clk] ; ## U1,C4,IO_L19_34_JX4_P,JX4,73,PMOD1_D0 +set_property -dict {PACKAGE_PIN C3 IOSTANDARD LVCMOS18} [get_ports ad9517_mosi] ; ## U1,C3,IO_L19_34_JX4_N,JX4,75,PMOD1_D1 +set_property -dict {PACKAGE_PIN B5 IOSTANDARD LVCMOS18} [get_ports ad9517_miso] ; ## U1,B5,IO_L20_34_JX4_P,JX4,74,PMOD1_D2 +set_property -dict {PACKAGE_PIN B6 IOSTANDARD LVCMOS18} [get_ports ad9517_pdn] ; ## U1,B6,IO_L21_34_JX4_P,JX4,77,PMOD1_D4 +set_property -dict {PACKAGE_PIN A5 IOSTANDARD LVCMOS18} [get_ports ad9517_ref_sel] ; ## U1,A5,IO_L21_34_JX4_N,JX4,79,PMOD1_D5 +set_property -dict {PACKAGE_PIN A4 IOSTANDARD LVCMOS18} [get_ports ad9517_ld] ; ## U1,A4,IO_L22_34_JX4_P,JX4,78,PMOD1_D6 +set_property -dict {PACKAGE_PIN A3 IOSTANDARD LVCMOS18} [get_ports ad9517_status] ; ## U1,A3,IO_L22_34_JX4_N,JX4,80,PMOD1_D7 + +# clocks + +create_clock -period 8.000 -name eth1_rgmii_rxclk [get_ports eth1_rgmii_rxclk] + +# bad ip- we have to do this + +set_property IDELAY_VALUE 16 \ + [get_cells -hier -filter {name =~ *delay_rgmii_rxd*}] \ + [get_cells -hier -filter {name =~ *delay_rgmii_rx_ctl}] + +set_property IODELAY_GROUP gmii2rgmii_iodelay_group\ + [get_cells -hier -filter {name =~ *idelayctrl}] \ + [get_cells -hier -filter {name =~ *delay_rgmii_rxd*}] \ + [get_cells -hier -filter {name =~ *delay_rgmii_rx_ctl}] + +# fan control/sense + +set_property -dict {PACKAGE_PIN B7 IOSTANDARD LVCMOS18} [get_ports fan_pwm] ; ## U1,B7,IO_L18_34_JX4_P,JX4,68,FAN_PWM +set_property -dict {PACKAGE_PIN A7 IOSTANDARD LVCMOS18} [get_ports fan_tach] ; ## U1,A7,IO_L18_34_JX4_N,JX4,70,FAN_TACH + +## led, push buttons, dip switches + +set_property -dict {PACKAGE_PIN J3 IOSTANDARD LVCMOS18} [get_ports gpio_bd[0]] ; ## U1,J3,IO_L12_MRCC_33_JX1_N,JX1,83,PB_GPIO_0 +set_property -dict {PACKAGE_PIN D8 IOSTANDARD LVCMOS18} [get_ports gpio_bd[1]] ; ## U1,D8,IO_L08_34_JX4_N,JX4,38,PB_GPIO_1 +set_property -dict {PACKAGE_PIN F9 IOSTANDARD LVCMOS18} [get_ports gpio_bd[2]] ; ## U1,F9,IO_L09_34_JX4_P,JX4,41,PB_GPIO_2 +set_property -dict {PACKAGE_PIN E8 IOSTANDARD LVCMOS18} [get_ports gpio_bd[3]] ; ## U1,E8,IO_L09_34_JX4_N,JX4,43,PB_GPIO_3 +set_property -dict {PACKAGE_PIN A8 IOSTANDARD LVCMOS18} [get_ports gpio_bd[4]] ; ## U1,A8,IO_L17_34_JX4_N,JX4,69,LED_GPIO_0 +set_property -dict {PACKAGE_PIN W14 IOSTANDARD LVCMOS25} [get_ports gpio_bd[5]] ; ## U1,W14,IO_00_12_JX4,JX4,14,LED_GPIO_1 +set_property -dict {PACKAGE_PIN W17 IOSTANDARD LVCMOS25} [get_ports gpio_bd[6]] ; ## U1,W17,IO_25_12_JX4,JX4,16,LED_GPIO_2 +set_property -dict {PACKAGE_PIN Y16 IOSTANDARD LVCMOS25} [get_ports gpio_bd[7]] ; ## U1,Y16,IO_L23_12_JX2_P,JX2,97,LED_GPIO_3 +set_property -dict {PACKAGE_PIN Y15 IOSTANDARD LVCMOS25} [get_ports gpio_bd[8]] ; ## U1,Y15,IO_L23_12_JX2_N,JX2,99,DIP_GPIO_0 +set_property -dict {PACKAGE_PIN W16 IOSTANDARD LVCMOS25} [get_ports gpio_bd[9]] ; ## U1,W16,IO_L24_12_JX4_P,JX4,13,DIP_GPIO_1 +set_property -dict {PACKAGE_PIN W15 IOSTANDARD LVCMOS25} [get_ports gpio_bd[10]] ; ## U1,W15,IO_L24_12_JX4_N,JX4,15,DIP_GPIO_2 +set_property -dict {PACKAGE_PIN V19 IOSTANDARD LVCMOS25} [get_ports gpio_bd[11]] ; ## U1,V19,IO_00_13_JX2,JX2,13,DIP_GPIO_3 + +## orphans (ps7- gpio) + +set_property -dict {PACKAGE_PIN V18 IOSTANDARD LVCMOS25} [get_ports gpio_bd[12]] ; ## U1,V18,IO_25_13_JX2,JX2,14,FMC_PRSNT +set_property -dict {PACKAGE_PIN AC19 IOSTANDARD LVCMOS25} [get_ports gpio_bd[13]] ; ## U1,AC19,IO_L21_13_JX2_N,JX2,69,PMOD0_D1,R103,1 +set_property -dict {PACKAGE_PIN Y17 IOSTANDARD LVCMOS25} [get_ports gpio_bd[14]] ; ## U1,Y17,IO_L19_12_JX2_P,JX2,88,SFP_GPIO_0 +set_property -dict {PACKAGE_PIN AA17 IOSTANDARD LVCMOS25} [get_ports gpio_bd[15]] ; ## U1,AA17,IO_L19_12_JX2_N,JX2,90,SFP_GPIO_1 +set_property -dict {PACKAGE_PIN AB17 IOSTANDARD LVCMOS25} [get_ports gpio_bd[16]] ; ## U1,AB17,IO_L20_12_JX2_P,JX2,87,SFP_GPIO_2 +set_property -dict {PACKAGE_PIN AB16 IOSTANDARD LVCMOS25} [get_ports gpio_bd[17]] ; ## U1,AB16,IO_L20_12_JX2_N,JX2,89,SFP_GPIO_3 +set_property -dict {PACKAGE_PIN AC17 IOSTANDARD LVCMOS25} [get_ports gpio_bd[18]] ; ## U1,AC17,IO_L21_12_JX2_P,JX2,93,SFP_GPIO_4 +set_property -dict {PACKAGE_PIN AC16 IOSTANDARD LVCMOS25} [get_ports gpio_bd[19]] ; ## U1,AC16,IO_L21_12_JX2_N,JX2,95,SFP_GPIO_5 +set_property -dict {PACKAGE_PIN AA15 IOSTANDARD LVCMOS25} [get_ports gpio_bd[20]] ; ## U1,AA15,IO_L22_12_JX2_P,JX2,94,SFP_GPIO_6 + +# unused io (clocks & gt) + +set_property -dict {PACKAGE_PIN AC14 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports clk_0_p] ; ## U1,AC14,IO_L13_MRCC_12_JX3_P,JX3,91,FMC_CLK0_M2C_P +set_property -dict {PACKAGE_PIN AD14 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports clk_0_n] ; ## U1,AD14,IO_L13_MRCC_12_JX3_N,JX3,93,FMC_CLK0_M2C_N +set_property -dict {PACKAGE_PIN AD20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports clk_1_p] ; ## U1,AD20,IO_L13_MRCC_13_JX2_P,JX2,41,FMC_CLK1_M2C_P +set_property -dict {PACKAGE_PIN AD21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports clk_1_n] ; ## U1,AD21,IO_L13_MRCC_13_JX2_N,JX2,43,FMC_CLK1_M2C_N + +set_property -dict {PACKAGE_PIN R6} [get_ports gt_ref_clk_0_p] ; ## U1,R6,UNNAMED_7_CAP_I123_N2,JX1,87,MGTREFCLK0_112_JX1_P +set_property -dict {PACKAGE_PIN R5} [get_ports gt_ref_clk_0_n] ; ## U1,R5,UNNAMED_7_CAP_I125_N2,JX1,89,MGTREFCLK0_112_JX1_N +set_property -dict {PACKAGE_PIN U6} [get_ports gt_ref_clk_1_p] ; ## U1,U6,UNNAMED_7_CAP_I126_N2,JX3,2,MGTREFCLK1_112_JX3_P +set_property -dict {PACKAGE_PIN U5} [get_ports gt_ref_clk_1_n] ; ## U1,U5,UNNAMED_7_CAP_I124_N2,JX3,4,MGTREFCLK1_112_JX3_N +set_property -dict {PACKAGE_PIN AA2} [get_ports gt_tx_p[0]] ; ## U1,AA2,MGTXTX0_112_JX3_P,JX3,8,FMC_GBT_TX_P,P2,C2 +set_property -dict {PACKAGE_PIN AA1} [get_ports gt_tx_n[0]] ; ## U1,AA1,MGTXTX0_112_JX3_N,JX3,10,FMC_GBT_TX_N,P2,C3 +set_property -dict {PACKAGE_PIN AB4} [get_ports gt_rx_p[0]] ; ## U1,AB4,MGTXRX0_112_JX1_P,JX1,88,FMC_GBT_RX_P,P2,C6 +set_property -dict {PACKAGE_PIN AB3} [get_ports gt_rx_n[0]] ; ## U1,AB3,MGTXRX0_112_JX1_N,JX1,90,FMC_GBT_RX_N,P2,C7 +set_property -dict {PACKAGE_PIN AF4} [get_ports gt_tx_p[1]] ; ## U1,Y4,MGTXRX1_112_JX1_P,JX1,91,SFP_GBT_RX_P,P1,13 +set_property -dict {PACKAGE_PIN AF3} [get_ports gt_tx_n[1]] ; ## U1,Y3,MGTXRX1_112_JX1_N,JX1,93,SFP_GBT_RX_N,P1,12 +set_property -dict {PACKAGE_PIN AE6} [get_ports gt_rx_p[1]] ; ## U1,W2,MGTXTX1_112_JX3_P,JX3,13,SFP_GBT_TX_P,P1,18 +set_property -dict {PACKAGE_PIN AE5} [get_ports gt_rx_n[1]] ; ## U1,W1,MGTXTX1_112_JX3_N,JX3,15,SFP_GBT_TX_N,P1,19 + +## clocks + +create_clock -name ref_clk -period 4.00 [get_ports gt_ref_clk_0_p] +create_clock -name xcvr_clk_0 -period 8.00 [get_pins i_system_wrapper/system_i/axi_pz_xcvrlb/inst/g_lanes[0].i_xcvrlb_1/i_xch/i_gtxe2_channel/RXOUTCLK] +create_clock -name xcvr_clk_1 -period 8.00 [get_pins i_system_wrapper/system_i/axi_pz_xcvrlb/inst/g_lanes[1].i_xcvrlb_1/i_xch/i_gtxe2_channel/RXOUTCLK] + +## loopback (regular io- fmc) + +set_property -dict {PACKAGE_PIN AC13 IOSTANDARD LVCMOS25} [get_ports gp_out[0]] ; ## U1,AC13,IO_L12_MRCC_12_JX3_P,JX3,86,FMC_LA00_CC_P,P2,G6 +set_property -dict {PACKAGE_PIN AD13 IOSTANDARD LVCMOS25} [get_ports gp_out[1]] ; ## U1,AD13,IO_L12_MRCC_12_JX3_N,JX3,88,FMC_LA00_CC_N,P2,G7 +set_property -dict {PACKAGE_PIN AC12 IOSTANDARD LVCMOS25} [get_ports gp_out[2]] ; ## U1,AC12,IO_L11_SRCC_12_JX3_P,JX3,85,FMC_LA01_CC_P,P2,D8 +set_property -dict {PACKAGE_PIN AD11 IOSTANDARD LVCMOS25} [get_ports gp_out[3]] ; ## U1,AD11,IO_L11_SRCC_12_JX3_N,JX3,87,FMC_LA01_CC_N,P2,D9 +set_property -dict {PACKAGE_PIN Y12 IOSTANDARD LVCMOS25} [get_ports gp_out[4]] ; ## U1,Y12,IO_L01_12_JX3_P,JX3,20,FMC_LA02_P,P2,H7 +set_property -dict {PACKAGE_PIN Y11 IOSTANDARD LVCMOS25} [get_ports gp_out[5]] ; ## U1,Y11,IO_L01_12_JX3_N,JX3,22,FMC_LA02_N,P2,H8 +set_property -dict {PACKAGE_PIN AB12 IOSTANDARD LVCMOS25} [get_ports gp_out[6]] ; ## U1,AB12,IO_L02_12_JX3_P,JX3,25,FMC_LA03_P,P2,G9 +set_property -dict {PACKAGE_PIN AC11 IOSTANDARD LVCMOS25} [get_ports gp_out[7]] ; ## U1,AC11,IO_L02_12_JX3_N,JX3,27,FMC_LA03_N,P2,G10 +set_property -dict {PACKAGE_PIN Y10 IOSTANDARD LVCMOS25} [get_ports gp_out[8]] ; ## U1,Y10,IO_L03_12_JX3_P,JX3,26,FMC_LA04_P,P2,H10 +set_property -dict {PACKAGE_PIN AA10 IOSTANDARD LVCMOS25} [get_ports gp_out[9]] ; ## U1,AA10,IO_L03_12_JX3_N,JX3,28,FMC_LA04_N,P2,H11 +set_property -dict {PACKAGE_PIN AB11 IOSTANDARD LVCMOS25} [get_ports gp_out[10]] ; ## U1,AB11,IO_L04_12_JX3_P,JX3,31,FMC_LA05_P,P2,D11 +set_property -dict {PACKAGE_PIN AB10 IOSTANDARD LVCMOS25} [get_ports gp_out[11]] ; ## U1,AB10,IO_L04_12_JX3_N,JX3,33,FMC_LA05_N,P2,D12 +set_property -dict {PACKAGE_PIN W13 IOSTANDARD LVCMOS25} [get_ports gp_out[12]] ; ## U1,W13,IO_L05_12_JX3_P,JX3,42,FMC_LA06_P,P2,C10 +set_property -dict {PACKAGE_PIN Y13 IOSTANDARD LVCMOS25} [get_ports gp_out[13]] ; ## U1,Y13,IO_L05_12_JX3_N,JX3,44,FMC_LA06_N,P2,C11 +set_property -dict {PACKAGE_PIN AA13 IOSTANDARD LVCMOS25} [get_ports gp_out[14]] ; ## U1,AA13,IO_L06_12_JX3_P,JX3,64,FMC_LA07_P,P2,H13 +set_property -dict {PACKAGE_PIN AA12 IOSTANDARD LVCMOS25} [get_ports gp_out[15]] ; ## U1,AA12,IO_L06_12_JX3_N,JX3,66,FMC_LA07_N,P2,H14 +set_property -dict {PACKAGE_PIN AE10 IOSTANDARD LVCMOS25} [get_ports gp_out[16]] ; ## U1,AE10,IO_L07_12_JX3_P,JX3,73,FMC_LA08_P,P2,G12 +set_property -dict {PACKAGE_PIN AD10 IOSTANDARD LVCMOS25} [get_ports gp_out[17]] ; ## U1,AD10,IO_L07_12_JX3_N,JX3,75,FMC_LA08_N,P2,G13 +set_property -dict {PACKAGE_PIN AE12 IOSTANDARD LVCMOS25} [get_ports gp_out[18]] ; ## U1,AE12,IO_L08_12_JX3_P,JX3,74,FMC_LA09_P,P2,D14 +set_property -dict {PACKAGE_PIN AF12 IOSTANDARD LVCMOS25} [get_ports gp_out[19]] ; ## U1,AF12,IO_L08_12_JX3_N,JX3,76,FMC_LA09_N,P2,D15 +set_property -dict {PACKAGE_PIN AE11 IOSTANDARD LVCMOS25} [get_ports gp_out[20]] ; ## U1,AE11,IO_L09_12_JX3_P,JX3,79,FMC_LA10_P,P2,C14 +set_property -dict {PACKAGE_PIN AF10 IOSTANDARD LVCMOS25} [get_ports gp_out[21]] ; ## U1,AF10,IO_L09_12_JX3_N,JX3,81,FMC_LA10_N,P2,C15 +set_property -dict {PACKAGE_PIN AE13 IOSTANDARD LVCMOS25} [get_ports gp_out[22]] ; ## U1,AE13,IO_L10_12_JX3_P,JX3,80,FMC_LA11_P,P2,H16 +set_property -dict {PACKAGE_PIN AF13 IOSTANDARD LVCMOS25} [get_ports gp_out[23]] ; ## U1,AF13,IO_L10_12_JX3_N,JX3,82,FMC_LA11_N,P2,H17 +set_property -dict {PACKAGE_PIN AB15 IOSTANDARD LVCMOS25} [get_ports gp_out[24]] ; ## U1,AB15,IO_L14_SRCC_12_JX3_P,JX3,92,FMC_LA12_P,P2,G15 +set_property -dict {PACKAGE_PIN AB14 IOSTANDARD LVCMOS25} [get_ports gp_out[25]] ; ## U1,AB14,IO_L14_SRCC_12_JX3_N,JX3,94,FMC_LA12_N,P2,G16 +set_property -dict {PACKAGE_PIN AD16 IOSTANDARD LVCMOS25} [get_ports gp_out[26]] ; ## U1,AD16,IO_L15_12_JX3_P,JX3,97,FMC_LA13_P,P2,D17 +set_property -dict {PACKAGE_PIN AD15 IOSTANDARD LVCMOS25} [get_ports gp_out[27]] ; ## U1,AD15,IO_L15_12_JX3_N,JX3,99,FMC_LA13_N,P2,D18 +set_property -dict {PACKAGE_PIN AF15 IOSTANDARD LVCMOS25} [get_ports gp_out[28]] ; ## U1,AF15,IO_L16_12_JX3_P,JX3,98,FMC_LA14_P,P2,C18 +set_property -dict {PACKAGE_PIN AF14 IOSTANDARD LVCMOS25} [get_ports gp_out[29]] ; ## U1,AF14,IO_L16_12_JX3_N,JX3,100,FMC_LA14_N,P2,C19 +set_property -dict {PACKAGE_PIN AE16 IOSTANDARD LVCMOS25} [get_ports gp_out[30]] ; ## U1,AE16,IO_L17_12_JX2_P,JX2,82,FMC_LA15_P,P2,H19 +set_property -dict {PACKAGE_PIN AE15 IOSTANDARD LVCMOS25} [get_ports gp_out[31]] ; ## U1,AE15,IO_L17_12_JX2_N,JX2,84,FMC_LA15_N,P2,H20 +set_property -dict {PACKAGE_PIN AE17 IOSTANDARD LVCMOS25} [get_ports gp_out[32]] ; ## U1,AE17,IO_L18_12_JX2_P,JX2,81,FMC_LA16_P,P2,G18 +set_property -dict {PACKAGE_PIN AF17 IOSTANDARD LVCMOS25} [get_ports gp_out[33]] ; ## U1,AF17,IO_L18_12_JX2_N,JX2,83,FMC_LA16_N,P2,G19 +set_property -dict {PACKAGE_PIN AC23 IOSTANDARD LVCMOS25} [get_ports gp_in[0]] ; ## U1,AC23,IO_L12_MRCC_13_JX2_P,JX2,36,FMC_LA17_CC_P,P2,D20 +set_property -dict {PACKAGE_PIN AC24 IOSTANDARD LVCMOS25} [get_ports gp_in[1]] ; ## U1,AC24,IO_L12_MRCC_13_JX2_N,JX2,38,FMC_LA17_CC_N,P2,D21 +set_property -dict {PACKAGE_PIN AD23 IOSTANDARD LVCMOS25} [get_ports gp_in[2]] ; ## U1,AD23,IO_L11_SRCC_13_JX2_P,JX2,35,FMC_LA18_CC_P,P2,C22 +set_property -dict {PACKAGE_PIN AD24 IOSTANDARD LVCMOS25} [get_ports gp_in[3]] ; ## U1,AD24,IO_L11_SRCC_13_JX2_N,JX2,37,FMC_LA18_CC_N,P2,C23 +set_property -dict {PACKAGE_PIN AA25 IOSTANDARD LVCMOS25} [get_ports gp_in[4]] ; ## U1,AA25,IO_L01_13_JX2_P,JX2,1,FMC_LA19_P,P2,H22 +set_property -dict {PACKAGE_PIN AB25 IOSTANDARD LVCMOS25} [get_ports gp_in[5]] ; ## U1,AB25,IO_L01_13_JX2_N,JX2,3,FMC_LA19_N,P2,H23 +set_property -dict {PACKAGE_PIN AB26 IOSTANDARD LVCMOS25} [get_ports gp_in[6]] ; ## U1,AB26,IO_L02_13_JX2_P,JX2,2,FMC_LA20_P,P2,G21 +set_property -dict {PACKAGE_PIN AC26 IOSTANDARD LVCMOS25} [get_ports gp_in[7]] ; ## U1,AC26,IO_L02_13_JX2_N,JX2,4,FMC_LA20_N,P2,G22 +set_property -dict {PACKAGE_PIN AE25 IOSTANDARD LVCMOS25} [get_ports gp_in[8]] ; ## U1,AE25,IO_L03_13_JX2_P,JX2,5,FMC_LA21_P,P2,H25 +set_property -dict {PACKAGE_PIN AE26 IOSTANDARD LVCMOS25} [get_ports gp_in[9]] ; ## U1,AE26,IO_L03_13_JX2_N,JX2,7,FMC_LA21_N,P2,H26 +set_property -dict {PACKAGE_PIN AD25 IOSTANDARD LVCMOS25} [get_ports gp_in[10]] ; ## U1,AD25,IO_L04_13_JX2_P,JX2,6,FMC_LA22_P,P2,G24 +set_property -dict {PACKAGE_PIN AD26 IOSTANDARD LVCMOS25} [get_ports gp_in[11]] ; ## U1,AD26,IO_L04_13_JX2_N,JX2,8,FMC_LA22_N,P2,G25 +set_property -dict {PACKAGE_PIN AA24 IOSTANDARD LVCMOS25} [get_ports gp_in[12]] ; ## U1,AA24,IO_L06_13_JX2_P,JX2,18,FMC_LA23_P,P2,D23 +set_property -dict {PACKAGE_PIN AB24 IOSTANDARD LVCMOS25} [get_ports gp_in[13]] ; ## U1,AB24,IO_L06_13_JX2_N,JX2,20,FMC_LA23_N,P2,D24 +set_property -dict {PACKAGE_PIN AE22 IOSTANDARD LVCMOS25} [get_ports gp_in[14]] ; ## U1,AE22,IO_L07_13_JX2_P,JX2,23,FMC_LA24_P,P2,H28 +set_property -dict {PACKAGE_PIN AF22 IOSTANDARD LVCMOS25} [get_ports gp_in[15]] ; ## U1,AF22,IO_L07_13_JX2_N,JX2,25,FMC_LA24_N,P2,H29 +set_property -dict {PACKAGE_PIN AE23 IOSTANDARD LVCMOS25} [get_ports gp_in[16]] ; ## U1,AE23,IO_L08_13_JX2_P,JX2,24,FMC_LA25_P,P2,G27 +set_property -dict {PACKAGE_PIN AF23 IOSTANDARD LVCMOS25} [get_ports gp_in[17]] ; ## U1,AF23,IO_L08_13_JX2_N,JX2,26,FMC_LA25_N,P2,G28 +set_property -dict {PACKAGE_PIN AB21 IOSTANDARD LVCMOS25} [get_ports gp_in[18]] ; ## U1,AB21,IO_L09_13_JX2_P,JX2,29,FMC_LA26_P,P2,D26 +set_property -dict {PACKAGE_PIN AB22 IOSTANDARD LVCMOS25} [get_ports gp_in[19]] ; ## U1,AB22,IO_L09_13_JX2_N,JX2,31,FMC_LA26_N,P2,D27 +set_property -dict {PACKAGE_PIN AA22 IOSTANDARD LVCMOS25} [get_ports gp_in[20]] ; ## U1,AA22,IO_L10_13_JX2_P,JX2,30,FMC_LA27_P,P2,C26 +set_property -dict {PACKAGE_PIN AA23 IOSTANDARD LVCMOS25} [get_ports gp_in[21]] ; ## U1,AA23,IO_L10_13_JX2_N,JX2,32,FMC_LA27_N,P2,C27 +set_property -dict {PACKAGE_PIN AC21 IOSTANDARD LVCMOS25} [get_ports gp_in[22]] ; ## U1,AC21,IO_L14_SRCC_13_JX2_P,JX2,42,FMC_LA28_P,P2,H31 +set_property -dict {PACKAGE_PIN AC22 IOSTANDARD LVCMOS25} [get_ports gp_in[23]] ; ## U1,AC22,IO_L14_SRCC_13_JX2_N,JX2,44,FMC_LA28_N,P2,H32 +set_property -dict {PACKAGE_PIN AF19 IOSTANDARD LVCMOS25} [get_ports gp_in[24]] ; ## U1,AF19,IO_L15_13_JX2_P,JX2,47,FMC_LA29_P,P2,G30 +set_property -dict {PACKAGE_PIN AF20 IOSTANDARD LVCMOS25} [get_ports gp_in[25]] ; ## U1,AF20,IO_L15_13_JX2_N,JX2,49,FMC_LA29_N,P2,G31 +set_property -dict {PACKAGE_PIN AE20 IOSTANDARD LVCMOS25} [get_ports gp_in[26]] ; ## U1,AE20,IO_L16_13_JX2_P,JX2,48,FMC_LA30_P,P2,H34 +set_property -dict {PACKAGE_PIN AE21 IOSTANDARD LVCMOS25} [get_ports gp_in[27]] ; ## U1,AE21,IO_L16_13_JX2_N,JX2,50,FMC_LA30_N,P2,H35 +set_property -dict {PACKAGE_PIN AD18 IOSTANDARD LVCMOS25} [get_ports gp_in[28]] ; ## U1,AD18,IO_L17_13_JX2_P,JX2,53,FMC_LA31_P,P2,G33 +set_property -dict {PACKAGE_PIN AD19 IOSTANDARD LVCMOS25} [get_ports gp_in[29]] ; ## U1,AD19,IO_L17_13_JX2_N,JX2,55,FMC_LA31_N,P2,G34 +set_property -dict {PACKAGE_PIN AE18 IOSTANDARD LVCMOS25} [get_ports gp_in[30]] ; ## U1,AE18,IO_L18_13_JX2_P,JX2,54,FMC_LA32_P,P2,H37 +set_property -dict {PACKAGE_PIN AF18 IOSTANDARD LVCMOS25} [get_ports gp_in[31]] ; ## U1,AF18,IO_L18_13_JX2_N,JX2,56,FMC_LA32_N,P2,H38 +set_property -dict {PACKAGE_PIN W20 IOSTANDARD LVCMOS25} [get_ports gp_in[32]] ; ## U1,W20,IO_L19_13_JX2_P,JX2,61,FMC_LA33_P,P2,G36 +set_property -dict {PACKAGE_PIN Y20 IOSTANDARD LVCMOS25} [get_ports gp_in[33]] ; ## U1,Y20,IO_L19_13_JX2_N,JX2,63,FMC_LA33_N,P2,G37 + +## loopback (regular io- pmod) +## U1,C24,PS_MIO15_500_JX4,JX4,85,PMOD_MIO_D0 +## U1,A25,PS_MIO10_500_JX4,JX4,87,PMOD_MIO_D1 +## U1,B26,PS_MIO11_500_JX4,JX4,88,PMOD_MIO_D3 +## U1,B25,PS_MIO13_500_JX4,JX4,91,PMOD_MIO_D4 +## U1,D23,PS_MIO14_500_JX4,JX4,93,PMOD_MIO_D5 +## U1,E17,PS_MIO46_501_JX4,JX4,92,PMOD_MIO_D6 +## U1,B19,PS_MIO47_501_JX4,JX4,94,PMOD_MIO_D7 + +set_property -dict {PACKAGE_PIN AC18 IOSTANDARD LVCMOS25} [get_ports gp_out[34]] ; ## U1,AC18,IO_L21_13_JX2_P,JX2,67,PMOD0_D0,R95,1 +set_property -dict {PACKAGE_PIN AA19 IOSTANDARD LVCMOS25} [get_ports gp_out[35]] ; ## U1,AA19,IO_L22_13_JX2_P,JX2,68,PMOD0_D2,R96,1 +set_property -dict {PACKAGE_PIN AB19 IOSTANDARD LVCMOS25} [get_ports gp_out[36]] ; ## U1,AB19,IO_L22_13_JX2_N,JX2,70,PMOD0_D3,R104,1 +set_property -dict {PACKAGE_PIN W18 IOSTANDARD LVCMOS25} [get_ports gp_in[34]] ; ## U1,W18,IO_L23_13_JX2_P,JX2,73,PMOD0_D4,R97,1 +set_property -dict {PACKAGE_PIN Y18 IOSTANDARD LVCMOS25} [get_ports gp_in[35]] ; ## U1,Y18,IO_L24_13_JX2_P,JX2,74,PMOD0_D6,R98,1 +set_property -dict {PACKAGE_PIN AA18 IOSTANDARD LVCMOS25} [get_ports gp_in[36]] ; ## U1,AA18,IO_L24_13_JX2_N,JX2,76,PMOD0_D7,R106,1 + +## loopback (regular io- camera) + +set_property -dict {PACKAGE_PIN G6 IOSTANDARD LVCMOS18} [get_ports gp_out[37]] ; ## U1,G6,IO_L02_34_JX4_P,JX4,20,CAM_GPIO_2,P9,B23 +set_property -dict {PACKAGE_PIN G5 IOSTANDARD LVCMOS18} [get_ports gp_out[38]] ; ## U1,G5,IO_L02_34_JX4_N,JX4,22,CAM_GPIO_3,P9,B24 +set_property -dict {PACKAGE_PIN H7 IOSTANDARD LVCMOS18} [get_ports gp_out[39]] ; ## U1,H7,IO_L04_34_JX4_P,JX4,26,CAM_GPIO_6,P9,B27 +set_property -dict {PACKAGE_PIN H6 IOSTANDARD LVCMOS18} [get_ports gp_out[40]] ; ## U1,H6,IO_L04_34_JX4_N,JX4,28,CAM_GPIO_7,P9,B29 +set_property -dict {PACKAGE_PIN N3 IOSTANDARD LVCMOS18} [get_ports gp_out[41]] ; ## U1,N3,IO_L15_33_JX1_P,JX1,53,CAM_DATA0_P,P9,A7 +set_property -dict {PACKAGE_PIN N2 IOSTANDARD LVCMOS18} [get_ports gp_out[42]] ; ## U1,N2,IO_L15_33_JX1_N,JX1,55,CAM_DATA0_N,P9,A8 +set_property -dict {PACKAGE_PIN N4 IOSTANDARD LVCMOS18} [get_ports gp_out[43]] ; ## U1,N4,IO_L17_33_JX1_P,JX1,12,CAM_DATA2_P,P9,A13 +set_property -dict {PACKAGE_PIN M4 IOSTANDARD LVCMOS18} [get_ports gp_out[44]] ; ## U1,M4,IO_L17_33_JX1_N,JX1,14,CAM_DATA2_N,P9,A14 +set_property -dict {PACKAGE_PIN M7 IOSTANDARD LVCMOS18} [get_ports gp_out[45]] ; ## U1,M7,IO_L19_33_JX1_P,JX1,18,CAM_DATA4_P,P9,A19 +set_property -dict {PACKAGE_PIN L7 IOSTANDARD LVCMOS18} [get_ports gp_out[46]] ; ## U1,L7,IO_L19_33_JX1_N,JX1,20,CAM_DATA4_N,P9,A20 +set_property -dict {PACKAGE_PIN M8 IOSTANDARD LVCMOS18} [get_ports gp_out[47]] ; ## U1,M8,IO_L21_33_JX1_P,JX1,24,CAM_DATA6_P,P9,A25 +set_property -dict {PACKAGE_PIN L8 IOSTANDARD LVCMOS18} [get_ports gp_out[48]] ; ## U1,L8,IO_L21_33_JX1_N,JX1,26,CAM_DATA6_N,P9,A26 +set_property -dict {PACKAGE_PIN L5 IOSTANDARD LVCMOS18} [get_ports gp_out[49]] ; ## U1,L5,IO_L14_SRCC_33_JX1_P,JX1,48,CAM_SYNC_P,P9,A31 +set_property -dict {PACKAGE_PIN L4 IOSTANDARD LVCMOS18} [get_ports gp_out[50]] ; ## U1,L4,IO_L14_SRCC_33_JX1_N,JX1,50,CAM_SYNC_N,P9,A32 +set_property -dict {PACKAGE_PIN K8 IOSTANDARD LVCMOS18} [get_ports gp_out[51]] ; ## U1,K8,IO_L24_33_JX1_P,JX1,36,CAM_SPI_MISO,P9,B15 +set_property -dict {PACKAGE_PIN K7 IOSTANDARD LVCMOS18} [get_ports gp_out[52]] ; ## U1,K7,IO_L24_33_JX1_N,JX1,38,CAM_SPI_MOSI,P9,B18 +set_property -dict {PACKAGE_PIN J10 IOSTANDARD LVCMOS18} [get_ports gp_out[53]] ; ## U1,J10,IO_L05_34_JX4_P,JX4,31,CAM_GPIO_8,P9,B30 +set_property -dict {PACKAGE_PIN J11 IOSTANDARD LVCMOS18} [get_ports gp_in[37]] ; ## U1,J11,IO_L01_34_JX4_P,JX4,19,CAM_GPIO_0,P9,B20 +set_property -dict {PACKAGE_PIN H11 IOSTANDARD LVCMOS18} [get_ports gp_in[38]] ; ## U1,H11,IO_L01_34_JX4_N,JX4,21,CAM_GPIO_1,P9,B21 +set_property -dict {PACKAGE_PIN H9 IOSTANDARD LVCMOS18} [get_ports gp_in[39]] ; ## U1,H9,IO_L03_34_JX4_P,JX4,25,CAM_GPIO_4,P9,B25 +set_property -dict {PACKAGE_PIN G9 IOSTANDARD LVCMOS18} [get_ports gp_in[40]] ; ## U1,G9,IO_L03_34_JX4_N,JX4,27,CAM_GPIO_5,P9,B26 +set_property -dict {PACKAGE_PIN M6 IOSTANDARD LVCMOS18} [get_ports gp_in[41]] ; ## U1,M6,IO_L13_MRCC_33_JX1_P,JX1,82,CAM_CLK_P,P9,A4 +set_property -dict {PACKAGE_PIN M5 IOSTANDARD LVCMOS18} [get_ports gp_in[42]] ; ## U1,M5,IO_L13_MRCC_33_JX1_N,JX1,84,CAM_CLK_N,P9,A5 +set_property -dict {PACKAGE_PIN M2 IOSTANDARD LVCMOS18} [get_ports gp_in[43]] ; ## U1,M2,IO_L16_33_JX1_P,JX1,11,CAM_DATA1_P,P9,A10 +set_property -dict {PACKAGE_PIN L2 IOSTANDARD LVCMOS18} [get_ports gp_in[44]] ; ## U1,L2,IO_L16_33_JX1_N,JX1,13,CAM_DATA1_N,P9,A11 +set_property -dict {PACKAGE_PIN N1 IOSTANDARD LVCMOS18} [get_ports gp_in[45]] ; ## U1,N1,IO_L18_33_JX1_P,JX1,17,CAM_DATA3_P,P9,A16 +set_property -dict {PACKAGE_PIN M1 IOSTANDARD LVCMOS18} [get_ports gp_in[46]] ; ## U1,M1,IO_L18_33_JX1_N,JX1,19,CAM_DATA3_N,P9,A17 +set_property -dict {PACKAGE_PIN K5 IOSTANDARD LVCMOS18} [get_ports gp_in[47]] ; ## U1,K5,IO_L20_33_JX1_P,JX1,23,CAM_DATA5_P,P9,A22 +set_property -dict {PACKAGE_PIN J5 IOSTANDARD LVCMOS18} [get_ports gp_in[48]] ; ## U1,J5,IO_L20_33_JX1_N,JX1,25,CAM_DATA5_N,P9,A23 +set_property -dict {PACKAGE_PIN K6 IOSTANDARD LVCMOS18} [get_ports gp_in[49]] ; ## U1,K6,IO_L22_33_JX1_P,JX1,29,CAM_DATA7_P,P9,A28 +set_property -dict {PACKAGE_PIN J6 IOSTANDARD LVCMOS18} [get_ports gp_in[50]] ; ## U1,J6,IO_L22_33_JX1_N,JX1,31,CAM_DATA7_N,P9,A29 +set_property -dict {PACKAGE_PIN N7 IOSTANDARD LVCMOS18} [get_ports gp_in[51]] ; ## U1,N7,IO_L23_33_JX1_P,JX1,30,CAM_SPI_EN,P9,B14 +set_property -dict {PACKAGE_PIN N6 IOSTANDARD LVCMOS18} [get_ports gp_in[52]] ; ## U1,N6,IO_L23_33_JX1_N,JX1,32,CAM_SPI_CLK,P9,B12 +set_property -dict {PACKAGE_PIN J4 IOSTANDARD LVCMOS18} [get_ports gp_in[53]] ; ## U1,J4,IO_L12_MRCC_33_JX1_P,JX1,81,CAM_REFCLK,P9,A2 + diff --git a/projects/pzsdr/common/ccpci_bd.tcl b/projects/pzsdr2/common/ccpci_bd.tcl similarity index 96% rename from projects/pzsdr/common/ccpci_bd.tcl rename to projects/pzsdr2/common/ccpci_bd.tcl index 6662565ec..d42c21121 100644 --- a/projects/pzsdr/common/ccpci_bd.tcl +++ b/projects/pzsdr2/common/ccpci_bd.tcl @@ -49,7 +49,7 @@ ad_connect pl_gpio1_t axi_gpio/gpio2_io_t # pci-express -set axi_pcie_x4 [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_pcie:2.7 axi_pcie_x4] +set axi_pcie_x4 [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_pcie:2.8 axi_pcie_x4] set_property -dict [list CONFIG.NO_OF_LANES {X4}] $axi_pcie_x4 set_property -dict [list CONFIG.MAX_LINK_SPEED {5.0_GT/s}] $axi_pcie_x4 set_property -dict [list CONFIG.VENDOR_ID {0x11D4}] $axi_pcie_x4 @@ -67,6 +67,7 @@ set_property -dict [list CONFIG.PCIEBAR2AXIBAR_0 {0x40000000}] $axi_pcie_x4 set_property -dict [list CONFIG.AXIBAR2PCIEBAR_0 {0x00000000}] $axi_pcie_x4 set axi_pcie_x4_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 axi_pcie_x4_rstgen] +set_property -dict [list CONFIG.C_EXT_RST_WIDTH {16}] $axi_pcie_x4_rstgen set axi_pcie_intc [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_intc:4.1 axi_pcie_intc] set_property -dict [list CONFIG.C_HAS_FAST {0}] $axi_pcie_intc @@ -88,6 +89,12 @@ ad_connect axi_pcie_x4/mmcm_lock axi_pcie_x4_rstgen/dcm_locked ad_connect axi_pcie_x4/axi_ctl_aclk_out axi_pcie_x4_rstgen/slowest_sync_clk ad_connect pcie_axi_resetn axi_pcie_x4/axi_aresetn +create_bd_port -dir O pcie_rst +create_bd_port -dir O pcie_clk + +ad_connect axi_pcie_x4_rstgen/bus_struct_reset pcie_rst +ad_connect axi_pcie_x4/axi_ctl_aclk_out pcie_clk + # interrupts ad_connect axi_pcie_intc/irq axi_pcie_x4/INTX_MSI_Request @@ -155,6 +162,7 @@ delete_bd_objs [get_bd_intf_nets -of_objects [find_bd_objs -relation connected_t set axi_pcie_s_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_pcie_s_interconnect] set_property -dict [list CONFIG.NUM_SI {2}] $axi_pcie_s_interconnect set_property -dict [list CONFIG.NUM_MI {1}] $axi_pcie_s_interconnect +set_property -dict [list CONFIG.STRATEGY {2} ] $axi_pcie_s_interconnect ad_connect pcie_axi_clk axi_pcie_s_interconnect/ACLK ad_connect pcie_axi_clk axi_pcie_s_interconnect/M00_ACLK diff --git a/projects/pzsdr2/common/ccpci_constr.xdc b/projects/pzsdr2/common/ccpci_constr.xdc new file mode 100644 index 000000000..edc2b851a --- /dev/null +++ b/projects/pzsdr2/common/ccpci_constr.xdc @@ -0,0 +1,30 @@ + +# constraints (ccpci.b) +# reference-only & not-effective +# using axi_pcie_x0y0.xdc + +set_property -dict {PACKAGE_PIN U6 } [get_ports pcie_ref_clk_p] ; ## U1,U6,UNNAMED_7_CAP_I126_N2,JX3,2,MGTREFCLK1_112_JX3_P,P2,A13 +set_property -dict {PACKAGE_PIN U5 } [get_ports pcie_ref_clk_n] ; ## U1,U5,UNNAMED_7_CAP_I124_N2,JX3,4,MGTREFCLK1_112_JX3_N,P2,A14 +set_property -dict {PACKAGE_PIN T4 } [get_ports pcie_data_rx_p[0]] ; ## U1,T4,MGTXRX3_112_JX1_P,JX1,97,MGTXRX3_112_JX1_P,P2,B14 +set_property -dict {PACKAGE_PIN T3 } [get_ports pcie_data_rx_n[0]] ; ## U1,T3,MGTXRX3_112_JX1_N,JX1,99,MGTXRX3_112_JX1_N,P2,B15 +set_property -dict {PACKAGE_PIN V4 } [get_ports pcie_data_rx_p[1]] ; ## U1,V4,MGTXRX2_112_JX1_P,JX1,92,MGTXRX2_112_JX1_P,P2,B19 +set_property -dict {PACKAGE_PIN V3 } [get_ports pcie_data_rx_n[1]] ; ## U1,V3,MGTXRX2_112_JX1_N,JX1,94,MGTXRX2_112_JX1_N,P2,B20 +set_property -dict {PACKAGE_PIN Y4 } [get_ports pcie_data_rx_p[2]] ; ## U1,Y4,MGTXRX1_112_JX1_P,JX1,91,MGTXRX1_112_JX1_P,P2,B23 +set_property -dict {PACKAGE_PIN Y3 } [get_ports pcie_data_rx_n[2]] ; ## U1,Y3,MGTXRX1_112_JX1_N,JX1,93,MGTXRX1_112_JX1_N,P2,B24 +set_property -dict {PACKAGE_PIN AB4} [get_ports pcie_data_rx_p[3]] ; ## U1,AB4,MGTXRX0_112_JX1_P,JX1,88,MGTXRX0_112_JX1_P,P2,B27 +set_property -dict {PACKAGE_PIN AB3} [get_ports pcie_data_rx_n[3]] ; ## U1,AB3,MGTXRX0_112_JX1_N,JX1,90,MGTXRX0_112_JX1_N,P2,B28 +set_property -dict {PACKAGE_PIN R2 } [get_ports pcie_data_tx_p[0]] ; ## U1,R2,MGTXTX3_112_JX3_P,JX3,19,MGTXTX3_112_JX3_P,P2,A16 +set_property -dict {PACKAGE_PIN R1 } [get_ports pcie_data_tx_n[0]] ; ## U1,R1,MGTXTX3_112_JX3_N,JX3,21,MGTXTX3_112_JX3_N,P2,A17 +set_property -dict {PACKAGE_PIN U2 } [get_ports pcie_data_tx_p[1]] ; ## U1,U2,MGTXTX2_112_JX3_P,JX3,14,MGTXTX2_112_JX3_P,P2,A21 +set_property -dict {PACKAGE_PIN U1 } [get_ports pcie_data_tx_n[1]] ; ## U1,U1,MGTXTX2_112_JX3_N,JX3,16,MGTXTX2_112_JX3_N,P2,A22 +set_property -dict {PACKAGE_PIN W2 } [get_ports pcie_data_tx_p[2]] ; ## U1,W2,MGTXTX1_112_JX3_P,JX3,13,MGTXTX1_112_JX3_P,P2,A25 +set_property -dict {PACKAGE_PIN W1 } [get_ports pcie_data_tx_n[2]] ; ## U1,W1,MGTXTX1_112_JX3_N,JX3,15,MGTXTX1_112_JX3_N,P2,A26 +set_property -dict {PACKAGE_PIN AA2} [get_ports pcie_data_tx_p[3]] ; ## U1,AA2,MGTXTX0_112_JX3_P,JX3,8,MGTXTX0_112_JX3_P,P2,A29 +set_property -dict {PACKAGE_PIN AA1} [get_ports pcie_data_tx_n[3]] ; ## U1,AA1,MGTXTX0_112_JX3_N,JX3,10,MGTXTX0_112_JX3_N,P2,A30 +set_property -dict {PACKAGE_PIN W20 IOSTANDARD LVCMOS25} [get_ports pcie_rstn] ; ## U1,W20,IO_L19_13_JX2_P,JX2,61,PCIE_PRSNT,P2,A11 +set_property -dict {PACKAGE_PIN AB20 IOSTANDARD LVCMOS25} [get_ports pcie_waken] ; ## U1,AB20,IO_L20_13_JX2_N,JX2,64,PCIE_WAKEB,P2,B11 +set_property -dict {PACKAGE_PIN AA14 IOSTANDARD LVCMOS25} [get_ports pcie_reset_done] ; ## IO_L22N_T3_12, NOT-CONNECTED ???? + +set_property PULLUP true [get_ports pcie_rstn] +create_clock -name pcie_ref_clock -period 10 [get_ports pcie_ref_clk_p] + diff --git a/projects/pzsdr2/common/ccusb_bd.tcl b/projects/pzsdr2/common/ccusb_bd.tcl new file mode 100644 index 000000000..c656a53dd --- /dev/null +++ b/projects/pzsdr2/common/ccusb_bd.tcl @@ -0,0 +1,74 @@ + +ad_connect sys_ps7/ENET1_GMII_RX_CLK GND +ad_connect sys_ps7/ENET1_GMII_TX_CLK GND + +create_bd_port -dir I usb_fx3_uart_tx +create_bd_port -dir O usb_fx3_uart_rx + +create_bd_port -dir I dma_rdy +create_bd_port -dir I dma_wmk +create_bd_port -dir I -from 3 -to 0 fifo_rdy +create_bd_port -dir O pclk +create_bd_port -dir IO -from 31 -to 0 data +create_bd_port -dir O -from 1 -to 0 addr +create_bd_port -dir O slcs_n +create_bd_port -dir O slrd_n +create_bd_port -dir O sloe_n +create_bd_port -dir O slwr_n +create_bd_port -dir O pktend_n +create_bd_port -dir O epswitch_n + +set axi_uart [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_uartlite:2.0 axi_uart] +set_property -dict [list CONFIG.C_BAUDRATE {115200}] $axi_uart + +set axi_usb_fx3 [create_bd_cell -type ip -vlnv analog.com:user:axi_usb_fx3:1.0 axi_usb_fx3] + +set axi_usb_fx3_dma [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_usb_fx3_dma] +set_property -dict [list CONFIG.c_sg_include_stscntrl_strm {0}] $axi_usb_fx3_dma +set_property -dict [list CONFIG.c_mm2s_burst_size {256}] $axi_usb_fx3_dma +set_property -dict [list CONFIG.c_s2mm_burst_size {256}] $axi_usb_fx3_dma +set_property -dict [list CONFIG.c_sg_length_width {16}] $axi_usb_fx3_dma + +set usb_fx3_rx_axis_fifo [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:1.1 usb_fx3_rx_axis_fifo ] + +ad_connect axi_usb_fx3/s_axis axi_usb_fx3_dma/M_AXIS_MM2S + +ad_connect sys_cpu_clk usb_fx3_rx_axis_fifo/s_axis_aclk +ad_connect sys_cpu_resetn usb_fx3_rx_axis_fifo/s_axis_aresetn + +ad_connect axi_usb_fx3/m_axis usb_fx3_rx_axis_fifo/S_AXIS +ad_connect axi_usb_fx3_dma/S_AXIS_S2MM usb_fx3_rx_axis_fifo/M_AXIS + +ad_connect axi_uart/rx usb_fx3_uart_tx +ad_connect axi_uart/tx usb_fx3_uart_rx + +ad_connect sys_cpu_clk axi_usb_fx3/s_axi_aclk +ad_connect sys_cpu_resetn axi_usb_fx3/s_axi_aresetn + +ad_connect axi_usb_fx3/dma_rdy dma_rdy +ad_connect axi_usb_fx3/dma_wmk dma_wmk +ad_connect axi_usb_fx3/fifo_rdy fifo_rdy +ad_connect axi_usb_fx3/pclk pclk +ad_connect axi_usb_fx3/data data +ad_connect axi_usb_fx3/addr addr +ad_connect axi_usb_fx3/slcs_n slcs_n +ad_connect axi_usb_fx3/slrd_n slrd_n +ad_connect axi_usb_fx3/sloe_n sloe_n +ad_connect axi_usb_fx3/slwr_n slwr_n +ad_connect axi_usb_fx3/pktend_n pktend_n +ad_connect axi_usb_fx3/epswitch_n epswitch_n + + +ad_cpu_interrupt ps-13 mb-12 axi_usb_fx3/irq +ad_cpu_interrupt ps-12 mb-13 axi_usb_fx3_dma/mm2s_introut +ad_cpu_interrupt ps-11 mb-14 axi_usb_fx3_dma/s2mm_introut +ad_cpu_interrupt ps-10 mb-15 axi_uart/interrupt + +ad_cpu_interconnect 0x50000000 axi_usb_fx3 +ad_cpu_interconnect 0x40400000 axi_usb_fx3_dma +ad_cpu_interconnect 0x40600000 axi_uart + +ad_mem_hp3_interconnect sys_cpu_clk sys_ps7/S_AXI_HP3 +ad_mem_hp3_interconnect sys_cpu_clk axi_usb_fx3_dma/M_AXI_SG +ad_mem_hp3_interconnect sys_cpu_clk axi_usb_fx3_dma/M_AXI_MM2S +ad_mem_hp3_interconnect sys_cpu_clk axi_usb_fx3_dma/M_AXI_S2MM diff --git a/projects/pzsdr2/common/ccusb_constr.xdc b/projects/pzsdr2/common/ccusb_constr.xdc new file mode 100644 index 000000000..3c7d6bdcd --- /dev/null +++ b/projects/pzsdr2/common/ccusb_constr.xdc @@ -0,0 +1,74 @@ +# Default constraints have LVCMOS25, overwite it +set_property -dict {IOSTANDARD LVCMOS18} [get_ports iic_scl] ; +set_property -dict {IOSTANDARD LVCMOS18} [get_ports iic_sda] ; + +# USB_FX3 + +set_property -dict {PACKAGE_PIN J11 IOSTANDARD LVCMOS18} [get_ports data[30]] ; +set_property -dict {PACKAGE_PIN H11 IOSTANDARD LVCMOS18} [get_ports data[31]] ; +set_property -dict {PACKAGE_PIN H9 IOSTANDARD LVCMOS18} [get_ports data[24]] ; +set_property -dict {PACKAGE_PIN G9 IOSTANDARD LVCMOS18} [get_ports data[27]] ; +set_property -dict {PACKAGE_PIN J10 IOSTANDARD LVCMOS18} [get_ports data[26]] ; +set_property -dict {PACKAGE_PIN J9 IOSTANDARD LVCMOS18} [get_ports data[21]] ; +set_property -dict {PACKAGE_PIN F5 IOSTANDARD LVCMOS18} [get_ports data[18]] ; +set_property -dict {PACKAGE_PIN E5 IOSTANDARD LVCMOS18} [get_ports data[19]] ; +set_property -dict {PACKAGE_PIN F9 IOSTANDARD LVCMOS18} [get_ports data[23]] ; +set_property -dict {PACKAGE_PIN E8 IOSTANDARD LVCMOS18} [get_ports data[20]] ; +set_property -dict {PACKAGE_PIN E7 IOSTANDARD LVCMOS18} [get_ports data[2]] ; +set_property -dict {PACKAGE_PIN C8 IOSTANDARD LVCMOS18} [get_ports data[14]] ; +set_property -dict {PACKAGE_PIN C7 IOSTANDARD LVCMOS18} [get_ports data[13]] ; +set_property -dict {PACKAGE_PIN C9 IOSTANDARD LVCMOS18} [get_ports data[9]] ; +set_property -dict {PACKAGE_PIN B9 IOSTANDARD LVCMOS18} [get_ports data[12]] ; +set_property -dict {PACKAGE_PIN A9 IOSTANDARD LVCMOS18} [get_ports data[8]] ; +set_property -dict {PACKAGE_PIN A8 IOSTANDARD LVCMOS18} [get_ports data[7]] ; +set_property -dict {PACKAGE_PIN C4 IOSTANDARD LVCMOS18} [get_ports data[3]] ; +set_property -dict {PACKAGE_PIN C3 IOSTANDARD LVCMOS18} [get_ports data[0]] ; +set_property -dict {PACKAGE_PIN B6 IOSTANDARD LVCMOS18} [get_ports data[4]] ; +set_property -dict {PACKAGE_PIN A5 IOSTANDARD LVCMOS18} [get_ports data[5]] ; +set_property -dict {PACKAGE_PIN G6 IOSTANDARD LVCMOS18} [get_ports data[28]] ; +set_property -dict {PACKAGE_PIN H7 IOSTANDARD LVCMOS18} [get_ports data[29]] ; +set_property -dict {PACKAGE_PIN J8 IOSTANDARD LVCMOS18} [get_ports data[25]] ; +set_property -dict {PACKAGE_PIN D9 IOSTANDARD LVCMOS18} [get_ports data[22]] ; +set_property -dict {PACKAGE_PIN E6 IOSTANDARD LVCMOS18} [get_ports data[16]] ; +set_property -dict {PACKAGE_PIN G7 IOSTANDARD LVCMOS18} [get_ports data[17]] ; +set_property -dict {PACKAGE_PIN D6 IOSTANDARD LVCMOS18} [get_ports data[15]] ; +set_property -dict {PACKAGE_PIN B10 IOSTANDARD LVCMOS18} [get_ports data[11]] ; +set_property -dict {PACKAGE_PIN B7 IOSTANDARD LVCMOS18} [get_ports data[10]] ; +set_property -dict {PACKAGE_PIN B5 IOSTANDARD LVCMOS18} [get_ports data[6]] ; +set_property -dict {PACKAGE_PIN A4 IOSTANDARD LVCMOS18} [get_ports data[1]] ; + +set_property -dict {PACKAGE_PIN F8 IOSTANDARD LVCMOS18} [get_ports pclk] ; + +set_property -dict {PACKAGE_PIN A7 IOSTANDARD LVCMOS18} [get_ports addr[0]] ; +set_property -dict {PACKAGE_PIN A3 IOSTANDARD LVCMOS18} [get_ports addr[1]] ; +set_property -dict {PACKAGE_PIN AD19 IOSTANDARD LVCMOS18} [get_ports addr[2]] ; +set_property -dict {PACKAGE_PIN AD20 IOSTANDARD LVCMOS18} [get_ports addr[3]] ; +set_property -dict {PACKAGE_PIN AC22 IOSTANDARD LVCMOS18} [get_ports addr[4]] ; + +set_property -dict {PACKAGE_PIN AD21 IOSTANDARD LVCMOS18} [get_ports slcs_n] ; +set_property -dict {PACKAGE_PIN AF20 IOSTANDARD LVCMOS18} [get_ports slwr_n] ; +set_property -dict {PACKAGE_PIN AD24 IOSTANDARD LVCMOS18} [get_ports sloe_n] ; +set_property -dict {PACKAGE_PIN AD23 IOSTANDARD LVCMOS18} [get_ports slrd_n] ; +set_property -dict {PACKAGE_PIN AE18 IOSTANDARD LVCMOS18} [get_ports pktend_n] ; + +set_property -dict {PACKAGE_PIN H8 IOSTANDARD LVCMOS18} [get_ports usb_fx3_uart_tx] ; +set_property -dict {PACKAGE_PIN AC24 IOSTANDARD LVCMOS18} [get_ports usb_fx3_uart_rx] ; + +set_property -dict {PACKAGE_PIN AF19 IOSTANDARD LVCMOS18} [get_ports fifo_rdy[0]] ; +set_property -dict {PACKAGE_PIN AC21 IOSTANDARD LVCMOS18} [get_ports fifo_rdy[1]] ; +set_property -dict {PACKAGE_PIN G5 IOSTANDARD LVCMOS18} [get_ports fifo_rdy[2]] ; +set_property -dict {PACKAGE_PIN H6 IOSTANDARD LVCMOS18} [get_ports fifo_rdy[3]] ; +set_property -dict {PACKAGE_PIN D8 IOSTANDARD LVCMOS18} [get_ports fifo_rdy[4]] ; +set_property -dict {PACKAGE_PIN D5 IOSTANDARD LVCMOS18} [get_ports fifo_rdy[5]] ; +set_property -dict {PACKAGE_PIN F7 IOSTANDARD LVCMOS18} [get_ports fifo_rdy[6]] ; +set_property -dict {PACKAGE_PIN C6 IOSTANDARD LVCMOS18} [get_ports fifo_rdy[7]] ; + +set_property -dict {PACKAGE_PIN AE20 IOSTANDARD LVCMOS18} [get_ports flag_a] ; +set_property -dict {PACKAGE_PIN AE21 IOSTANDARD LVCMOS18} [get_ports flag_b] ; + +set_property -dict {PACKAGE_PIN A10 IOSTANDARD LVCMOS18} [get_ports pmode[0]] ; +set_property -dict {PACKAGE_PIN K10 IOSTANDARD LVCMOS18} [get_ports pmode[1]] ; +set_property -dict {PACKAGE_PIN B4 IOSTANDARD LVCMOS18} [get_ports pmode[2]] ; + +set_property -dict {PACKAGE_PIN AC23 IOSTANDARD LVCMOS18} [get_ports reset_n] ; +set_property -dict {PACKAGE_PIN AD18 IOSTANDARD LVCMOS18} [get_ports epswitch_n] ; diff --git a/projects/pzsdr2/common/pzsdr2_bd.tcl b/projects/pzsdr2/common/pzsdr2_bd.tcl new file mode 100644 index 000000000..f265bcfb6 --- /dev/null +++ b/projects/pzsdr2/common/pzsdr2_bd.tcl @@ -0,0 +1,464 @@ + +# create board design +# default ports + +create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr +create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 iic_main +create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 fixed_io + +create_bd_port -dir O spi0_csn_2_o +create_bd_port -dir O spi0_csn_1_o +create_bd_port -dir O spi0_csn_0_o +create_bd_port -dir I spi0_csn_i +create_bd_port -dir I spi0_clk_i +create_bd_port -dir O spi0_clk_o +create_bd_port -dir I spi0_sdo_i +create_bd_port -dir O spi0_sdo_o +create_bd_port -dir I spi0_sdi_i + +create_bd_port -dir O spi1_csn_2_o +create_bd_port -dir O spi1_csn_1_o +create_bd_port -dir O spi1_csn_0_o +create_bd_port -dir I spi1_csn_i +create_bd_port -dir I spi1_clk_i +create_bd_port -dir O spi1_clk_o +create_bd_port -dir I spi1_sdo_i +create_bd_port -dir O spi1_sdo_o +create_bd_port -dir I spi1_sdi_i + +create_bd_port -dir I -from 63 -to 0 gpio_i +create_bd_port -dir O -from 63 -to 0 gpio_o +create_bd_port -dir O -from 63 -to 0 gpio_t + +# otg + +set otg_vbusoc [create_bd_port -dir I otg_vbusoc] + +# interrupts + +create_bd_port -dir I -type intr ps_intr_00 +create_bd_port -dir I -type intr ps_intr_01 +create_bd_port -dir I -type intr ps_intr_02 +create_bd_port -dir I -type intr ps_intr_03 +create_bd_port -dir I -type intr ps_intr_04 +create_bd_port -dir I -type intr ps_intr_05 +create_bd_port -dir I -type intr ps_intr_06 +create_bd_port -dir I -type intr ps_intr_07 +create_bd_port -dir I -type intr ps_intr_08 +create_bd_port -dir I -type intr ps_intr_09 +create_bd_port -dir I -type intr ps_intr_10 +create_bd_port -dir I -type intr ps_intr_11 +create_bd_port -dir I -type intr ps_intr_12 +create_bd_port -dir I -type intr ps_intr_13 +create_bd_port -dir I -type intr ps_intr_15 + +# instance: sys_ps7 + +set sys_ps7 [create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 sys_ps7] +set_property -dict [list CONFIG.PCW_PRESET_BANK0_VOLTAGE {LVCMOS 1.8V}] $sys_ps7 +set_property -dict [list CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 1.8V}] $sys_ps7 +set_property -dict [list CONFIG.PCW_PACKAGE_NAME {fbg676}] $sys_ps7 +set_property -dict [list CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_ENET0_PERIPHERAL_ENABLE {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_ENET0_ENET0_IO {MIO 16 .. 27}] $sys_ps7 +set_property -dict [list CONFIG.PCW_ENET0_GRP_MDIO_ENABLE {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_ENET1_PERIPHERAL_ENABLE {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_ENET_RESET_SELECT {Separate reset pins}] $sys_ps7 +set_property -dict [list CONFIG.PCW_ENET0_RESET_ENABLE {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_ENET0_RESET_IO {MIO 8}] $sys_ps7 +set_property -dict [list CONFIG.PCW_ENET1_RESET_ENABLE {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_ENET1_RESET_IO {MIO 51}] $sys_ps7 +set_property -dict [list CONFIG.PCW_SD0_PERIPHERAL_ENABLE {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_SD0_GRP_CD_ENABLE {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_SD0_GRP_CD_IO {MIO 50}] $sys_ps7 +set_property -dict [list CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ {50}] $sys_ps7 +set_property -dict [list CONFIG.PCW_UART1_PERIPHERAL_ENABLE {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_USB0_PERIPHERAL_ENABLE {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_USB0_RESET_ENABLE {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_USB0_RESET_IO {MIO 7}] $sys_ps7 +set_property -dict [list CONFIG.PCW_QSPI_PERIPHERAL_ENABLE {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_UIPARAM_DDR_PARTNO {MT41K256M16 RE-125}] $sys_ps7 +set_property -dict [list CONFIG.PCW_UIPARAM_DDR_BUS_WIDTH {32 Bit}] $sys_ps7 +set_property -dict [list CONFIG.PCW_UIPARAM_DDR_USE_INTERNAL_VREF {0}] $sys_ps7 +set_property -dict [list CONFIG.PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_UIPARAM_DDR_TRAIN_READ_GATE {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_UIPARAM_DDR_TRAIN_DATA_EYE {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 {-0.053}] $sys_ps7 +set_property -dict [list CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 {-0.059}] $sys_ps7 +set_property -dict [list CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 {0.065}] $sys_ps7 +set_property -dict [list CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 {0.066}] $sys_ps7 +set_property -dict [list CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0 {0.264}] $sys_ps7 +set_property -dict [list CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1 {0.265}] $sys_ps7 +set_property -dict [list CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2 {0.330}] $sys_ps7 +set_property -dict [list CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3 {0.330}] $sys_ps7 +set_property -dict [list CONFIG.PCW_TTC0_PERIPHERAL_ENABLE {0}] $sys_ps7 +set_property -dict [list CONFIG.PCW_EN_CLK1_PORT {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_EN_RST1_PORT {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_EN_CLK2_PORT {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_EN_RST2_PORT {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100.0}] $sys_ps7 +set_property -dict [list CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ {200.0}] $sys_ps7 +set_property -dict [list CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {200.0}] $sys_ps7 +set_property -dict [list CONFIG.PCW_USE_FABRIC_INTERRUPT {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_IRQ_F2P_INTR {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_IO {64}] $sys_ps7 +set_property -dict [list CONFIG.PCW_IRQ_F2P_MODE {REVERSE}] $sys_ps7 +set_property -dict [list CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_SPI0_SPI0_IO {EMIO}] $sys_ps7 +set_property -dict [list CONFIG.PCW_SPI1_PERIPHERAL_ENABLE {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_SPI1_SPI1_IO {EMIO}] $sys_ps7 + +set axi_iic_main [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_iic:2.0 axi_iic_main] +set_property -dict [list CONFIG.USE_BOARD_FLOW {true}] $axi_iic_main +set_property -dict [list CONFIG.IIC_BOARD_INTERFACE {Custom}] $axi_iic_main + +set sys_concat_intc [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 sys_concat_intc] +set_property -dict [list CONFIG.NUM_PORTS {16}] $sys_concat_intc + +set sys_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 sys_rstgen] +set_property -dict [list CONFIG.C_EXT_RST_WIDTH {1}] $sys_rstgen + +set sys_logic_inv [create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 sys_logic_inv] +set_property -dict [list CONFIG.C_SIZE {1}] $sys_logic_inv +set_property -dict [list CONFIG.C_OPERATION {not}] $sys_logic_inv + +# system reset/clock definitions + +ad_connect sys_cpu_clk sys_ps7/FCLK_CLK0 +ad_connect sys_200m_clk sys_ps7/FCLK_CLK1 +ad_connect sys_cpu_reset sys_rstgen/peripheral_reset +ad_connect sys_cpu_resetn sys_rstgen/peripheral_aresetn +ad_connect sys_cpu_clk sys_rstgen/slowest_sync_clk +ad_connect sys_rstgen/ext_reset_in sys_ps7/FCLK_RESET0_N + +# interface connections + +ad_connect ddr sys_ps7/DDR +ad_connect gpio_i sys_ps7/GPIO_I +ad_connect gpio_o sys_ps7/GPIO_O +ad_connect gpio_t sys_ps7/GPIO_T +ad_connect fixed_io sys_ps7/FIXED_IO +ad_connect iic_main axi_iic_main/iic +ad_connect sys_logic_inv/Res sys_ps7/USB0_VBUS_PWRFAULT +ad_connect sys_logic_inv/Op1 otg_vbusoc + +# spi connections + +ad_connect spi0_csn_2_o sys_ps7/SPI0_SS2_O +ad_connect spi0_csn_1_o sys_ps7/SPI0_SS1_O +ad_connect spi0_csn_0_o sys_ps7/SPI0_SS_O +ad_connect spi0_csn_i sys_ps7/SPI0_SS_I +ad_connect spi0_clk_i sys_ps7/SPI0_SCLK_I +ad_connect spi0_clk_o sys_ps7/SPI0_SCLK_O +ad_connect spi0_sdo_i sys_ps7/SPI0_MOSI_I +ad_connect spi0_sdo_o sys_ps7/SPI0_MOSI_O +ad_connect spi0_sdi_i sys_ps7/SPI0_MISO_I + +ad_connect spi1_csn_2_o sys_ps7/SPI1_SS2_O +ad_connect spi1_csn_1_o sys_ps7/SPI1_SS1_O +ad_connect spi1_csn_0_o sys_ps7/SPI1_SS_O +ad_connect spi1_csn_i sys_ps7/SPI1_SS_I +ad_connect spi1_clk_i sys_ps7/SPI1_SCLK_I +ad_connect spi1_clk_o sys_ps7/SPI1_SCLK_O +ad_connect spi1_sdo_i sys_ps7/SPI1_MOSI_I +ad_connect spi1_sdo_o sys_ps7/SPI1_MOSI_O +ad_connect spi1_sdi_i sys_ps7/SPI1_MISO_I + +# interrupts + +ad_connect sys_concat_intc/dout sys_ps7/IRQ_F2P +ad_connect sys_concat_intc/In15 ps_intr_15 +ad_connect sys_concat_intc/In14 axi_iic_main/iic2intc_irpt +ad_connect sys_concat_intc/In13 ps_intr_13 +ad_connect sys_concat_intc/In12 ps_intr_12 +ad_connect sys_concat_intc/In11 ps_intr_11 +ad_connect sys_concat_intc/In10 ps_intr_10 +ad_connect sys_concat_intc/In9 ps_intr_09 +ad_connect sys_concat_intc/In8 ps_intr_08 +ad_connect sys_concat_intc/In7 ps_intr_07 +ad_connect sys_concat_intc/In6 ps_intr_06 +ad_connect sys_concat_intc/In5 ps_intr_05 +ad_connect sys_concat_intc/In4 ps_intr_04 +ad_connect sys_concat_intc/In3 ps_intr_03 +ad_connect sys_concat_intc/In2 ps_intr_02 +ad_connect sys_concat_intc/In1 ps_intr_01 +ad_connect sys_concat_intc/In0 ps_intr_00 + +# interconnects + +ad_cpu_interconnect 0x41600000 axi_iic_main + +# ad9361 + +create_bd_port -dir O enable +create_bd_port -dir O txnrx +create_bd_port -dir I up_enable +create_bd_port -dir I up_txnrx +create_bd_port -dir O tdd_sync_o +create_bd_port -dir I tdd_sync_i +create_bd_port -dir O tdd_sync_t + +# ad9361 core + +set axi_ad9361 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9361:1.0 axi_ad9361] +set_property -dict [list CONFIG.ID {0}] $axi_ad9361 +set_property -dict [list CONFIG.DAC_IODELAY_ENABLE {1}] $axi_ad9361 + +set axi_ad9361_dac_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9361_dac_dma] +set_property -dict [list CONFIG.DMA_TYPE_SRC {0}] $axi_ad9361_dac_dma +set_property -dict [list CONFIG.DMA_TYPE_DEST {2}] $axi_ad9361_dac_dma +set_property -dict [list CONFIG.CYCLIC {1}] $axi_ad9361_dac_dma +set_property -dict [list CONFIG.AXI_SLICE_SRC {0}] $axi_ad9361_dac_dma +set_property -dict [list CONFIG.AXI_SLICE_DEST {1}] $axi_ad9361_dac_dma +set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9361_dac_dma +set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $axi_ad9361_dac_dma + +set util_ad9361_dac_upack [create_bd_cell -type ip -vlnv analog.com:user:util_upack:1.0 util_ad9361_dac_upack] +set_property -dict [list CONFIG.NUM_OF_CHANNELS {4}] $util_ad9361_dac_upack +set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {16}] $util_ad9361_dac_upack + +set axi_ad9361_adc_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9361_adc_dma] +set_property -dict [list CONFIG.DMA_TYPE_SRC {2}] $axi_ad9361_adc_dma +set_property -dict [list CONFIG.DMA_TYPE_DEST {0}] $axi_ad9361_adc_dma +set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad9361_adc_dma +set_property -dict [list CONFIG.SYNC_TRANSFER_START {1}] $axi_ad9361_adc_dma +set_property -dict [list CONFIG.AXI_SLICE_SRC {0}] $axi_ad9361_adc_dma +set_property -dict [list CONFIG.AXI_SLICE_DEST {0}] $axi_ad9361_adc_dma +set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9361_adc_dma +set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {64}] $axi_ad9361_adc_dma + +set util_ad9361_adc_pack [create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 util_ad9361_adc_pack] +set_property -dict [list CONFIG.NUM_OF_CHANNELS {4}] $util_ad9361_adc_pack +set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {16}] $util_ad9361_adc_pack + +set util_ad9361_adc_fifo [create_bd_cell -type ip -vlnv analog.com:user:util_wfifo:1.0 util_ad9361_adc_fifo] +set_property -dict [list CONFIG.NUM_OF_CHANNELS {4}] $util_ad9361_adc_fifo +set_property -dict [list CONFIG.DIN_ADDRESS_WIDTH {4}] $util_ad9361_adc_fifo +set_property -dict [list CONFIG.DIN_DATA_WIDTH {16}] $util_ad9361_adc_fifo +set_property -dict [list CONFIG.DOUT_DATA_WIDTH {16}] $util_ad9361_adc_fifo + +set util_ad9361_tdd_sync [create_bd_cell -type ip -vlnv analog.com:user:util_tdd_sync:1.0 util_ad9361_tdd_sync] +set_property -dict [list CONFIG.TDD_SYNC_PERIOD {10000000}] $util_ad9361_tdd_sync + +set clkdiv [ create_bd_cell -type ip -vlnv analog.com:user:util_clkdiv:1.0 clkdiv ] + +set clkdiv_reset [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 clkdiv_reset] + +set dac_fifo [create_bd_cell -type ip -vlnv analog.com:user:util_rfifo:1.0 dac_fifo] +set_property -dict [list CONFIG.DIN_DATA_WIDTH {16}] $dac_fifo +set_property -dict [list CONFIG.DOUT_DATA_WIDTH {16}] $dac_fifo +set_property -dict [list CONFIG.DIN_ADDRESS_WIDTH {4}] $dac_fifo + +set clkdiv_sel_logic [create_bd_cell -type ip -vlnv xilinx.com:ip:util_reduced_logic:2.0 clkdiv_sel_logic] +set_property -dict [list CONFIG.C_SIZE {2}] $clkdiv_sel_logic + +set concat_logic [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 concat_logic] +set_property -dict [list CONFIG.NUM_PORTS {2}] $concat_logic + +# connections + +ad_connect sys_200m_clk axi_ad9361/delay_clk +ad_connect axi_ad9361_clk axi_ad9361/l_clk +ad_connect axi_ad9361_clk axi_ad9361/clk +ad_connect enable axi_ad9361/enable +ad_connect txnrx axi_ad9361/txnrx +ad_connect up_enable axi_ad9361/up_enable +ad_connect up_txnrx axi_ad9361/up_txnrx +ad_connect axi_ad9361_clk util_ad9361_adc_fifo/din_clk +ad_connect axi_ad9361/rst util_ad9361_adc_fifo/din_rst +ad_connect axi_ad9361_clk clkdiv/clk +ad_connect clkdiv/clk_out axi_ad9361_adc_dma/fifo_wr_clk +ad_connect clkdiv/clk_out util_ad9361_adc_fifo/dout_clk +ad_connect clkdiv/clk_out util_ad9361_adc_pack/adc_clk +ad_connect clkdiv_reset/ext_reset_in sys_rstgen/peripheral_aresetn +ad_connect clkdiv_reset/slowest_sync_clk clkdiv/clk_out +ad_connect util_ad9361_adc_pack/adc_rst clkdiv_reset/peripheral_reset +ad_connect util_ad9361_adc_fifo/dout_rstn clkdiv_reset/peripheral_aresetn +ad_connect axi_ad9361/adc_enable_i0 util_ad9361_adc_fifo/din_enable_0 +ad_connect axi_ad9361/adc_valid_i0 util_ad9361_adc_fifo/din_valid_0 +ad_connect axi_ad9361/adc_data_i0 util_ad9361_adc_fifo/din_data_0 +ad_connect axi_ad9361/adc_enable_q0 util_ad9361_adc_fifo/din_enable_1 +ad_connect axi_ad9361/adc_valid_q0 util_ad9361_adc_fifo/din_valid_1 +ad_connect axi_ad9361/adc_data_q0 util_ad9361_adc_fifo/din_data_1 +ad_connect axi_ad9361/adc_enable_i1 util_ad9361_adc_fifo/din_enable_2 +ad_connect axi_ad9361/adc_valid_i1 util_ad9361_adc_fifo/din_valid_2 +ad_connect axi_ad9361/adc_data_i1 util_ad9361_adc_fifo/din_data_2 +ad_connect axi_ad9361/adc_enable_q1 util_ad9361_adc_fifo/din_enable_3 +ad_connect axi_ad9361/adc_valid_q1 util_ad9361_adc_fifo/din_valid_3 +ad_connect axi_ad9361/adc_data_q1 util_ad9361_adc_fifo/din_data_3 +ad_connect util_ad9361_adc_fifo/dout_enable_0 util_ad9361_adc_pack/adc_enable_0 +ad_connect util_ad9361_adc_fifo/dout_valid_0 util_ad9361_adc_pack/adc_valid_0 +ad_connect util_ad9361_adc_fifo/dout_data_0 util_ad9361_adc_pack/adc_data_0 +ad_connect util_ad9361_adc_fifo/dout_enable_1 util_ad9361_adc_pack/adc_enable_1 +ad_connect util_ad9361_adc_fifo/dout_valid_1 util_ad9361_adc_pack/adc_valid_1 +ad_connect util_ad9361_adc_fifo/dout_data_1 util_ad9361_adc_pack/adc_data_1 +ad_connect util_ad9361_adc_fifo/dout_enable_2 util_ad9361_adc_pack/adc_enable_2 +ad_connect util_ad9361_adc_fifo/dout_valid_2 util_ad9361_adc_pack/adc_valid_2 +ad_connect util_ad9361_adc_fifo/dout_data_2 util_ad9361_adc_pack/adc_data_2 +ad_connect util_ad9361_adc_fifo/dout_enable_3 util_ad9361_adc_pack/adc_enable_3 +ad_connect util_ad9361_adc_fifo/dout_valid_3 util_ad9361_adc_pack/adc_valid_3 +ad_connect util_ad9361_adc_fifo/dout_data_3 util_ad9361_adc_pack/adc_data_3 +ad_connect util_ad9361_adc_pack/adc_valid axi_ad9361_adc_dma/fifo_wr_en +ad_connect util_ad9361_adc_pack/adc_sync axi_ad9361_adc_dma/fifo_wr_sync +ad_connect util_ad9361_adc_pack/adc_data axi_ad9361_adc_dma/fifo_wr_din +ad_connect axi_ad9361_adc_dma/fifo_wr_overflow util_ad9361_adc_fifo/dout_ovf +ad_connect util_ad9361_adc_fifo/din_ovf axi_ad9361/adc_dovf +ad_connect axi_ad9361/adc_r1_mode concat_logic/In0 +ad_connect axi_ad9361/dac_r1_mode concat_logic/In1 +ad_connect concat_logic/dout clkdiv_sel_logic/Op1 +ad_connect clkdiv/clk_sel clkdiv_sel_logic/Res +ad_connect util_ad9361_dac_upack/dac_valid axi_ad9361_dac_dma/fifo_rd_en +ad_connect util_ad9361_dac_upack/dac_data axi_ad9361_dac_dma/fifo_rd_dout +ad_connect clkdiv/clk_out axi_ad9361_dac_dma/fifo_rd_clk +ad_connect axi_ad9361/dac_dunf dac_fifo/dout_unf +ad_connect dac_fifo/din_clk clkdiv/clk_out +ad_connect dac_fifo/din_rstn clkdiv_reset/peripheral_aresetn +ad_connect axi_ad9361_clk dac_fifo/dout_clk +ad_connect dac_fifo/dout_rst axi_ad9361/rst +ad_connect util_ad9361_dac_upack/dac_clk clkdiv/clk_out +ad_connect dac_fifo/din_enable_0 util_ad9361_dac_upack/dac_enable_0 +ad_connect dac_fifo/din_valid_0 util_ad9361_dac_upack/dac_valid_0 +ad_connect dac_fifo/din_data_0 util_ad9361_dac_upack/dac_data_0 +ad_connect dac_fifo/din_enable_1 util_ad9361_dac_upack/dac_enable_1 +ad_connect dac_fifo/din_valid_1 util_ad9361_dac_upack/dac_valid_1 +ad_connect dac_fifo/din_data_1 util_ad9361_dac_upack/dac_data_1 +ad_connect dac_fifo/din_enable_2 util_ad9361_dac_upack/dac_enable_2 +ad_connect dac_fifo/din_valid_2 util_ad9361_dac_upack/dac_valid_2 +ad_connect dac_fifo/din_data_2 util_ad9361_dac_upack/dac_data_2 +ad_connect dac_fifo/din_enable_3 util_ad9361_dac_upack/dac_enable_3 +ad_connect dac_fifo/din_valid_3 util_ad9361_dac_upack/dac_valid_3 +ad_connect dac_fifo/din_data_3 util_ad9361_dac_upack/dac_data_3 +ad_connect axi_ad9361/dac_enable_i0 dac_fifo/dout_enable_0 +ad_connect axi_ad9361/dac_valid_i0 dac_fifo/dout_valid_0 +ad_connect axi_ad9361/dac_data_i0 dac_fifo/dout_data_0 +ad_connect axi_ad9361/dac_enable_q0 dac_fifo/dout_enable_1 +ad_connect axi_ad9361/dac_valid_q0 dac_fifo/dout_valid_1 +ad_connect axi_ad9361/dac_data_q0 dac_fifo/dout_data_1 +ad_connect axi_ad9361/dac_enable_i1 dac_fifo/dout_enable_2 +ad_connect axi_ad9361/dac_valid_i1 dac_fifo/dout_valid_2 +ad_connect axi_ad9361/dac_data_i1 dac_fifo/dout_data_2 +ad_connect axi_ad9361/dac_enable_q1 dac_fifo/dout_enable_3 +ad_connect axi_ad9361/dac_valid_q1 dac_fifo/dout_valid_3 +ad_connect axi_ad9361/dac_data_q1 dac_fifo/dout_data_3 +ad_connect sys_cpu_clk util_ad9361_tdd_sync/clk +ad_connect sys_cpu_resetn util_ad9361_tdd_sync/rstn +ad_connect util_ad9361_tdd_sync/sync_out axi_ad9361/tdd_sync +ad_connect util_ad9361_tdd_sync/sync_mode axi_ad9361/tdd_sync_cntr +ad_connect tdd_sync_t axi_ad9361/tdd_sync_cntr +ad_connect tdd_sync_o util_ad9361_tdd_sync/sync_out +ad_connect tdd_sync_i util_ad9361_tdd_sync/sync_in + +# interconnects + +ad_cpu_interconnect 0x79020000 axi_ad9361 +ad_cpu_interconnect 0x7C400000 axi_ad9361_adc_dma +ad_cpu_interconnect 0x7C420000 axi_ad9361_dac_dma +ad_mem_hp1_interconnect sys_cpu_clk sys_ps7/S_AXI_HP1 +ad_mem_hp1_interconnect sys_cpu_clk axi_ad9361_adc_dma/m_dest_axi +ad_mem_hp2_interconnect sys_cpu_clk sys_ps7/S_AXI_HP2 +ad_mem_hp2_interconnect sys_cpu_clk axi_ad9361_dac_dma/m_src_axi +ad_connect sys_cpu_resetn axi_ad9361_adc_dma/m_dest_axi_aresetn +ad_connect sys_cpu_resetn axi_ad9361_dac_dma/m_src_axi_aresetn + +# interrupts + +ad_cpu_interrupt ps-13 mb-13 axi_ad9361_adc_dma/irq +ad_cpu_interrupt ps-12 mb-12 axi_ad9361_dac_dma/irq + +## customization of core to disable data path logic (less resources) +## interface type - 1R1T (1) or 2R2T (0) (default is 2R2T) +## 2R2T supports 1R1T as a run time option. +## 1R1T allows core to run at a lower rate (1/2 of 2R2T) + +set_property CONFIG.MODE_1R1T 0 [get_bd_cells axi_ad9361] + +## interface type - CMOS (1) or LVDS (0) (default is LVDS) +## CMOS allows core to run at a lower rate (1/2 of LVDS) + +set_property CONFIG.CMOS_OR_LVDS_N 0 [get_bd_cells axi_ad9361] + +## data-path disable (global control)- allows removal of DSP functions within the core. +## also removes the corresponding AXI control interface registers + +set_property CONFIG.ADC_DATAPATH_DISABLE 0 [get_bd_cells axi_ad9361] +set_property CONFIG.DAC_DATAPATH_DISABLE 0 [get_bd_cells axi_ad9361] + +## data-path disable (individual control)- effective ONLY if DATAPATH_DISABLE is 0x0. + +set_property CONFIG.ADC_DATAFORMAT_DISABLE 0 [get_bd_cells axi_ad9361] +set_property CONFIG.ADC_DCFILTER_DISABLE 0 [get_bd_cells axi_ad9361] +set_property CONFIG.ADC_IQCORRECTION_DISABLE 0 [get_bd_cells axi_ad9361] +set_property CONFIG.ADC_USERPORTS_DISABLE 0 [get_bd_cells axi_ad9361] + +set_property CONFIG.DAC_DDS_DISABLE 0 [get_bd_cells axi_ad9361] +set_property CONFIG.DAC_IQCORRECTION_DISABLE 0 [get_bd_cells axi_ad9361] +set_property CONFIG.DAC_USERPORTS_DISABLE 0 [get_bd_cells axi_ad9361] + +## tdd-disable (control is moved exclusively to GPIO) + +set_property CONFIG.TDD_DISABLE 0 [get_bd_cells axi_ad9361] + +## lvds/cmos configuration +## core digital interface -- cmos (1) or lvds (0) + +proc cfg_ad9361_interface {cmos_or_lvds} { + + if {$cmos_or_lvds eq "LVDS"} { + + set_property CONFIG.CMOS_OR_LVDS_N 0 [get_bd_cells axi_ad9361] + + create_bd_port -dir I rx_clk_in_p + create_bd_port -dir I rx_clk_in_n + create_bd_port -dir I rx_frame_in_p + create_bd_port -dir I rx_frame_in_n + create_bd_port -dir I -from 5 -to 0 rx_data_in_p + create_bd_port -dir I -from 5 -to 0 rx_data_in_n + + create_bd_port -dir O tx_clk_out_p + create_bd_port -dir O tx_clk_out_n + create_bd_port -dir O tx_frame_out_p + create_bd_port -dir O tx_frame_out_n + create_bd_port -dir O -from 5 -to 0 tx_data_out_p + create_bd_port -dir O -from 5 -to 0 tx_data_out_n + + ad_connect rx_clk_in_p axi_ad9361/rx_clk_in_p + ad_connect rx_clk_in_n axi_ad9361/rx_clk_in_n + ad_connect rx_frame_in_p axi_ad9361/rx_frame_in_p + ad_connect rx_frame_in_n axi_ad9361/rx_frame_in_n + ad_connect rx_data_in_p axi_ad9361/rx_data_in_p + ad_connect rx_data_in_n axi_ad9361/rx_data_in_n + ad_connect tx_clk_out_p axi_ad9361/tx_clk_out_p + ad_connect tx_clk_out_n axi_ad9361/tx_clk_out_n + ad_connect tx_frame_out_p axi_ad9361/tx_frame_out_p + ad_connect tx_frame_out_n axi_ad9361/tx_frame_out_n + ad_connect tx_data_out_p axi_ad9361/tx_data_out_p + ad_connect tx_data_out_n axi_ad9361/tx_data_out_n + + return + } + + if {$cmos_or_lvds eq "CMOS"} { + + set_property CONFIG.CMOS_OR_LVDS_N 1 [get_bd_cells axi_ad9361] + + create_bd_port -dir I rx_clk_in + create_bd_port -dir I rx_frame_in + create_bd_port -dir I -from 11 -to 0 rx_data_in + create_bd_port -dir O tx_clk_out + create_bd_port -dir O tx_frame_out + create_bd_port -dir O -from 11 -to 0 tx_data_out + + ad_connect rx_clk_in axi_ad9361/rx_clk_in + ad_connect rx_frame_in axi_ad9361/rx_frame_in + ad_connect rx_data_in axi_ad9361/rx_data_in + ad_connect tx_clk_out axi_ad9361/tx_clk_out + ad_connect tx_frame_out axi_ad9361/tx_frame_out + ad_connect tx_data_out axi_ad9361/tx_data_out + + return + } + +} + + diff --git a/projects/pzsdr2/common/pzsdr2_constr.xdc b/projects/pzsdr2/common/pzsdr2_constr.xdc new file mode 100644 index 000000000..f7c98d224 --- /dev/null +++ b/projects/pzsdr2/common/pzsdr2_constr.xdc @@ -0,0 +1,195 @@ + +# constraints (pzsdr2.e) +# ad9361 + +set_property -dict {PACKAGE_PIN G14 IOSTANDARD LVCMOS18} [get_ports enable] ; ## IO_L11P_T1_SRCC_35 U1,G14,IO_L11_35_ENABLE +set_property -dict {PACKAGE_PIN F14 IOSTANDARD LVCMOS18} [get_ports txnrx] ; ## IO_L11N_T1_SRCC_35 U1,F14,IO_L11_35_TXNRX + +set_property -dict {PACKAGE_PIN D13 IOSTANDARD LVCMOS18} [get_ports gpio_status[0]] ; ## IO_L19P_T3_35 U1,D13,IO_L19_35_CTRL_OUT0 +set_property -dict {PACKAGE_PIN C13 IOSTANDARD LVCMOS18} [get_ports gpio_status[1]] ; ## IO_L19N_T3_VREF_35 U1,C13,IO_L19_35_CTRL_OUT1 +set_property -dict {PACKAGE_PIN C14 IOSTANDARD LVCMOS18} [get_ports gpio_status[2]] ; ## IO_L20P_T3_AD6P_35 U1,C14,IO_L20_35_CTRL_OUT2 +set_property -dict {PACKAGE_PIN B14 IOSTANDARD LVCMOS18} [get_ports gpio_status[3]] ; ## IO_L20N_T3_AD6N_35 U1,B14,IO_L20_35_CTRL_OUT3 +set_property -dict {PACKAGE_PIN A15 IOSTANDARD LVCMOS18} [get_ports gpio_status[4]] ; ## IO_L21P_T3_DQS_AD14P_35 U1,A15,IO_L21_35_CTRL_OUT4 +set_property -dict {PACKAGE_PIN A14 IOSTANDARD LVCMOS18} [get_ports gpio_status[5]] ; ## IO_L21N_T3_DQS_AD14N_35 U1,A14,IO_L21_35_CTRL_OUT5 +set_property -dict {PACKAGE_PIN C12 IOSTANDARD LVCMOS18} [get_ports gpio_status[6]] ; ## IO_L22P_T3_AD7P_35 U1,C12,IO_L22_35_CTRL_OUT6 +set_property -dict {PACKAGE_PIN B12 IOSTANDARD LVCMOS18} [get_ports gpio_status[7]] ; ## IO_L22N_T3_AD7N_35 U1,B12,IO_L22_35_CTRL_OUT7 +set_property -dict {PACKAGE_PIN C2 IOSTANDARD LVCMOS18} [get_ports gpio_ctl[0]] ; ## IO_L23P_T3_34 U1,C2,IO_L23_34_CTRL_IN0 +set_property -dict {PACKAGE_PIN B1 IOSTANDARD LVCMOS18} [get_ports gpio_ctl[1]] ; ## IO_L23N_T3_34 U1,B1,IO_L23_34_CTRL_IN1 +set_property -dict {PACKAGE_PIN B2 IOSTANDARD LVCMOS18} [get_ports gpio_ctl[2]] ; ## IO_L24P_T3_34 U1,B2,IO_L24_34_CTRL_IN2 +set_property -dict {PACKAGE_PIN A2 IOSTANDARD LVCMOS18} [get_ports gpio_ctl[3]] ; ## IO_L24N_T3_34 U1,A2,IO_L24_34_CTRL_IN3 +set_property -dict {PACKAGE_PIN G16 IOSTANDARD LVCMOS18} [get_ports gpio_en_agc] ; ## IO_L10P_T1_AD11P_35 U1,G16,IO_L10_35_EN_AGC +set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVCMOS18} [get_ports gpio_sync] ; ## IO_L10N_T1_AD11N_35 U1,G15,IO_L10_35_SYNC_IN +set_property -dict {PACKAGE_PIN H16 IOSTANDARD LVCMOS18} [get_ports gpio_resetb] ; ## IO_0_VRN_35 U1,H16,IO_00_35_AD9361_RST +set_property -dict {PACKAGE_PIN K11 IOSTANDARD LVCMOS18} [get_ports gpio_clksel] ; ## IO_0_VRN_34 U1,K11,IO_00_34_AD9361_CLKSEL + +set_property -dict {PACKAGE_PIN C11 IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports spi_csn] ; ## IO_L23P_T3_35 U1,C11,IO_L23_35_SPI_ENB +set_property -dict {PACKAGE_PIN B11 IOSTANDARD LVCMOS18} [get_ports spi_clk] ; ## IO_L23N_T3_35 U1,B11,IO_L23_35_SPI_CLK +set_property -dict {PACKAGE_PIN A13 IOSTANDARD LVCMOS18} [get_ports spi_mosi] ; ## IO_L24P_T3_AD15P_35 U1,A13,IO_L24_35_SPI_DI +set_property -dict {PACKAGE_PIN A12 IOSTANDARD LVCMOS18} [get_ports spi_miso] ; ## IO_L24N_T3_AD15N_35 U1,A12,IO_L24_35_SPI_DO + +set_property -dict {PACKAGE_PIN K12 IOSTANDARD LVCMOS18} [get_ports clkout_in] ; ## IO_25_VRP_35 U1,K12,IO_25_35_AD9361_CLKOUT + +# iic (ccbrk with loopback drives i2c back to the FPGA) + +set_property -dict {PACKAGE_PIN AF24 IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports iic_scl] ; ## IO_L5P_T0_13 U1,AF24,SCL,JX2,17,I2C_SCL,P2,14,P2,4,U1,Y16,IO_L23_12_JX2_P,JX2,97,LED_GPIO_3,P2,4 +set_property -dict {PACKAGE_PIN AF25 IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports iic_sda] ; ## IO_L5N_T0_13 U1,AF25,SDA,JX2,19,I2C_SDA,P2,16,P2,15,U1,AB24,IO_L06_13_JX2_N,JX2,20,IO_L06_13_JX2_N,P2,15 + +## reference-only +## -------------- +## ad9361 (optional rf-card) +## -------------------------- +## JX4,1,GPO0 +## JX4,2,GPO1 +## JX4,3,GPO2 +## JX4,4,GPO3 +## JX4,7,AUXADC +## JX4,8,AUXDAC1 +## JX4,10,AUXDAC2 +## JX4,63,AD9361_CLK + +## fixed-io (ps7) (som only, others are carrier specific) +## ------------------------------------------------------ +## U1,D26,PS_MIO01_500_QSPI0_SS_B +## U1,F23,PS_MIO06_500_QSPI0_SCLK +## U1,E25,PS_MIO02_500_QSPI0_IO0 +## U1,D25,PS_MIO03_500_QSPI0_IO1 +## U1,F24,PS_MIO04_500_QSPI0_IO2 +## U1,C26,PS_MIO05_500_QSPI0_IO3 +## U1,A24,PS_MIO08_500_ETH0_RESETN (magnetics-RJ45- JX3,47,ETH_PHY_LED0) +## U1,A19,PS_MIO53_501_ETH0_MDIO (magnetics-RJ45- JX3,48,ETH_PHY_LED1) +## U1,A20,PS_MIO52_501_ETH0_MDC (magnetics-RJ45- JX3,51,ETH_MD1_P) +## U1,G22,PS_MIO22_501_ETH0_RX_CLK (magnetics-RJ45- JX3,53,ETH_MD1_N) +## U1,F18,PS_MIO27_501_ETH0_RX_CTL (magnetics-RJ45- JX3,52,ETH_MD2_P) +## U1,F20,PS_MIO23_501_ETH0_RX_D0 (magnetics-RJ45- JX3,54,ETH_MD2_N) +## U1,J19,PS_MIO24_501_ETH0_RX_D1 (magnetics-RJ45- JX3,57,ETH_MD3_P) +## U1,F19,PS_MIO25_501_ETH0_RX_D2 (magnetics-RJ45- JX3,59,ETH_MD3_N) +## U1,H17,PS_MIO26_501_ETH0_RX_D3 (magnetics-RJ45- JX3,58,ETH_MD4_P) +## U1,G21,PS_MIO16_501_ETH0_TX_CLK (magnetics-RJ45- JX3,60,ETH_MD4_N) +## U1,F22,PS_MIO21_501_ETH0_TX_CTL +## U1,G17,PS_MIO17_501_ETH0_TX_D0 +## U1,G20,PS_MIO18_501_ETH0_TX_D1 +## U1,G19,PS_MIO19_501_ETH0_TX_D2 +## U1,H19,PS_MIO20_501_ETH0_TX_D3 +## U1,B21,PS_MIO48_501_JX4,JX4,99,USB_UART_RXD +## U1,A18,PS_MIO49_501_JX4,JX4,98,USB_UART_TXD +## U1,C22,PS_MIO40_501_SD0_CLK (off-board- JX3,43,SDIO_CLKB1) +## U1,C19,PS_MIO41_501_SD0_CMD (off-board- JX3,34,SDIO_CMDB1) +## U1,F17,PS_MIO42_501_SD0_DATA0 (off-board- JX3,37,SDIO_DAT0B1) +## U1,D18,PS_MIO43_501_SD0_DATA1 (off-board- JX3,36,SDIO_DAT1B1) +## U1,E18,PS_MIO44_501_SD0_DATA2 (off-board- JX3,39,SDIO_DAT2B1) +## U1,C18,PS_MIO45_501_SD0_DATA3 (off-board- JX3,38,SDIO_DAT3B1) +## U1,B22,PS_MIO50_501_SD0_CD (off-board- JX3,41,JX3_SD1_CDN) +## U1,E23,PS_MIO07_500_USB_RESET_B (usb- JX3,63,USB_ID) +## U1,D24,PS_MIO09_500_USB_CLK_PD (usb- JX3,67,USB_OTG_P) +## U1,E20,PS_MIO29_501_USB0_DIR (usb- JX3,69,USB_OTG_N) +## U1,K19,PS_MIO30_501_USB0_STP (usb- JX3,68,USB_VBUS_OTG) +## U1,E21,PS_MIO31_501_USB0_NXT (usb- JX3,70,USB_OTG_CPEN) +## U1,K16,PS_MIO36_501_USB0_CLK +## U1,K17,PS_MIO32_501_USB0_D0 +## U1,E22,PS_MIO33_501_USB0_D1 +## U1,J16,PS_MIO34_501_USB0_D2 +## U1,D19,PS_MIO35_501_USB0_D3 +## U1,J18,PS_MIO28_501_USB0_D4 +## U1,D20,PS_MIO37_501_USB0_D5 +## U1,D21,PS_MIO38_501_USB0_D6 +## U1,C21,PS_MIO39_501_USB0_D7 +## U1,A23,UNNAMED_3_ICXC7Z035_I94_PSMIO12 (JX4,86,PS_MIO12_500_JX4) + +## ddr (fixed-io) +## -------------- +## U1,H24,DDR3_DQS0_P +## U1,G25,DDR3_DQS0_N +## U1,L24,DDR3_DQS1_P +## U1,L25,DDR3_DQS1_N +## U1,P25,DDR3_DQS2_P +## U1,R25,DDR3_DQS2_N +## U1,W24,DDR3_DQS3_P +## U1,W25,DDR3_DQS3_N +## U1,J26,DDR3_DQ0 +## U1,F25,DDR3_DQ1 +## U1,J25,DDR3_DQ2 +## U1,G26,DDR3_DQ3 +## U1,H26,DDR3_DQ4 +## U1,H23,DDR3_DQ5 +## U1,J24,DDR3_DQ6 +## U1,J23,DDR3_DQ7 +## U1,K26,DDR3_DQ8 +## U1,L23,DDR3_DQ9 +## U1,M26,DDR3_DQ10 +## U1,K23,DDR3_DQ11 +## U1,M25,DDR3_DQ12 +## U1,N24,DDR3_DQ13 +## U1,M24,DDR3_DQ14 +## U1,N23,DDR3_DQ15 +## U1,R26,DDR3_DQ16 +## U1,P24,DDR3_DQ17 +## U1,N26,DDR3_DQ18 +## U1,P23,DDR3_DQ19 +## U1,T24,DDR3_DQ20 +## U1,T25,DDR3_DQ21 +## U1,T23,DDR3_DQ22 +## U1,R23,DDR3_DQ23 +## U1,V24,DDR3_DQ24 +## U1,U26,DDR3_DQ25 +## U1,U24,DDR3_DQ26 +## U1,U25,DDR3_DQ27 +## U1,W26,DDR3_DQ28 +## U1,Y25,DDR3_DQ29 +## U1,Y26,DDR3_DQ30 +## U1,W23,DDR3_DQ31 +## U1,G24,DDR3_DM0 +## U1,K25,DDR3_DM1 +## U1,P26,DDR3_DM2 +## U1,V26,DDR3_DM3 +## U1,K22,DDR3_A0 +## U1,K20,DDR3_A1 +## U1,N21,DDR3_A2 +## U1,L22,DDR3_A3 +## U1,M20,DDR3_A4 +## U1,N22,DDR3_A5 +## U1,L20,DDR3_A6 +## U1,J21,DDR3_A7 +## U1,T20,DDR3_A8 +## U1,U20,DDR3_A9 +## U1,M22,DDR3_A10 +## U1,H21,DDR3_A11 +## U1,P20,DDR3_A12 +## U1,J20,DDR3_A13 +## U1,R20,DDR3_A14 +## U1,U22,DDR3_BA0 +## U1,T22,DDR3_BA1 +## U1,R22,DDR3_BA2 +## U1,R21,DDR3_CK_P +## U1,P21,DDR3_CK_N +## U1,U21,DDR3_CKE +## U1,H22,DDR3_RST# +## U1,Y21,DDR3_CS# +## U1,V22,DDR3_WE# +## U1,V23,DDR3_RAS# +## U1,Y23,DDR3_CAS# +## U1,Y22,DDR3_ODT + +## resets, clock and power controls +## -------------------------------- +## U1,B24,UNNAMED_3_ICXC7Z035_I94_PSCLK50,33.33MEGHZ +## U1,A22,PS-SRST# +## U1,C23,PWR_GD_1.35V +## JX2,10,PG_1P8V +## JX2,11,PG_MODULE +## JX1,5,PWR_ENABLE +## JX1,6,CARRIER_RESET + +## JTAG +## ---- +## U1,W11,JTAG_TMS,JX1,2,JTAG_TMS +## U1,W12,JTAG_TCK,JX1,1,JTAG_TCK +## U1,V11,JTAG_TDI,JX1,4,FPGA_TDI,JTAG_TDI +## U1,W9,FPGA_DONE,JX1,8,CFG_DONE + +## GBT I/O (clocks) +## ---------------- +## U1,R5,UNNAMED_7_CAP_I125_N2 (JX1,87,MGTREFCLK0_112_JX1_P) +## U1,R6,UNNAMED_7_CAP_I123_N2 (JX1,89,MGTREFCLK0_112_JX1_N) +## U1,U6,UNNAMED_7_CAP_I126_N2 (JX3,2,MGTREFCLK1_112_JX3_P) +## U1,U5,UNNAMED_7_CAP_I124_N2 (JX3,4,MGTREFCLK1_112_JX3_N) + diff --git a/projects/pzsdr2/common/pzsdr2_constr_cmos.xdc b/projects/pzsdr2/common/pzsdr2_constr_cmos.xdc new file mode 100644 index 000000000..530511b80 --- /dev/null +++ b/projects/pzsdr2/common/pzsdr2_constr_cmos.xdc @@ -0,0 +1,42 @@ + +# constraints (pzsdr2.e) +# ad9361 (SWAP == 0x1) + +set_property -dict {PACKAGE_PIN J14 IOSTANDARD LVCMOS18} [get_ports rx_clk_in] ; ## IO_L12P_T1_MRCC_35 U1,J14,IO_L12_MRCC_35_DATA_CLK_P +set_property -dict {PACKAGE_PIN H13 IOSTANDARD LVCMOS18} [get_ports rx_frame_in] ; ## IO_L7P_T1_AD2P_35 U1,H13,IO_L07_35_RX_FRAME_P +set_property -dict {PACKAGE_PIN E12 IOSTANDARD LVCMOS18} [get_ports rx_data_in[0]] ; ## IO_L1N_T0_AD0N_35 U1,E12,IO_L01_35_RX_D0_N +set_property -dict {PACKAGE_PIN F12 IOSTANDARD LVCMOS18} [get_ports rx_data_in[1]] ; ## IO_L1P_T0_AD0P_35 U1,F12,IO_L01_35_RX_D0_P +set_property -dict {PACKAGE_PIN D10 IOSTANDARD LVCMOS18} [get_ports rx_data_in[2]] ; ## IO_L2N_T0_AD8N_35 U1,D10,IO_L02_35_RX_D1_N +set_property -dict {PACKAGE_PIN E10 IOSTANDARD LVCMOS18} [get_ports rx_data_in[3]] ; ## IO_L2P_T0_AD8P_35 U1,E10,IO_L02_35_RX_D1_P +set_property -dict {PACKAGE_PIN F10 IOSTANDARD LVCMOS18} [get_ports rx_data_in[4]] ; ## IO_L3N_T0_DQS_AD1N_35 U1,F10,IO_L03_35_RX_D2_N +set_property -dict {PACKAGE_PIN G10 IOSTANDARD LVCMOS18} [get_ports rx_data_in[5]] ; ## IO_L3P_T0_DQS_AD1P_35 U1,G10,IO_L03_35_RX_D2_P +set_property -dict {PACKAGE_PIN D11 IOSTANDARD LVCMOS18} [get_ports rx_data_in[6]] ; ## IO_L4N_T0_35 U1,D11,IO_L04_35_RX_D3_N +set_property -dict {PACKAGE_PIN E11 IOSTANDARD LVCMOS18} [get_ports rx_data_in[7]] ; ## IO_L4P_T0_35 U1,E11,IO_L04_35_RX_D3_P +set_property -dict {PACKAGE_PIN G11 IOSTANDARD LVCMOS18} [get_ports rx_data_in[8]] ; ## IO_L5N_T0_AD9N_35 U1,G11,IO_L05_35_RX_D4_N +set_property -dict {PACKAGE_PIN G12 IOSTANDARD LVCMOS18} [get_ports rx_data_in[9]] ; ## IO_L5P_T0_AD9P_35 U1,G12,IO_L05_35_RX_D4_P +set_property -dict {PACKAGE_PIN E13 IOSTANDARD LVCMOS18} [get_ports rx_data_in[10]] ; ## IO_L6N_T0_VREF_35 U1,E13,IO_L06_35_RX_D5_N +set_property -dict {PACKAGE_PIN F13 IOSTANDARD LVCMOS18} [get_ports rx_data_in[11]] ; ## IO_L6P_T0_35 U1,F13,IO_L06_35_RX_D5_P + +set_property -dict {PACKAGE_PIN K13 IOSTANDARD LVCMOS18} [get_ports tx_clk_out] ; ## IO_L8P_T1_AD10P_35 U1,K13,IO_L08_35_FB_CLK_P +set_property -dict {PACKAGE_PIN K15 IOSTANDARD LVCMOS18} [get_ports tx_frame_out] ; ## IO_L9P_T1_DQS_AD3P_35 U1,K15,IO_L09_35_TX_FRAME_P +set_property -dict {PACKAGE_PIN D14 IOSTANDARD LVCMOS18} [get_ports tx_data_out[0]] ; ## IO_L13N_T2_MRCC_35 U1,D14,IO_L13_35_TX_D0_N +set_property -dict {PACKAGE_PIN D15 IOSTANDARD LVCMOS18} [get_ports tx_data_out[1]] ; ## IO_L13P_T2_MRCC_35 U1,D15,IO_L13_35_TX_D0_P +set_property -dict {PACKAGE_PIN E15 IOSTANDARD LVCMOS18} [get_ports tx_data_out[2]] ; ## IO_L14N_T2_AD4N_SRCC_35 U1,E15,IO_L14_35_TX_D1_N +set_property -dict {PACKAGE_PIN F15 IOSTANDARD LVCMOS18} [get_ports tx_data_out[3]] ; ## IO_L14P_T2_AD4P_SRCC_35 U1,F15,IO_L14_35_TX_D1_P +set_property -dict {PACKAGE_PIN C16 IOSTANDARD LVCMOS18} [get_ports tx_data_out[4]] ; ## IO_L15N_T2_DQS_AD12N_35 U1,C16,IO_L15_35_TX_D2_N +set_property -dict {PACKAGE_PIN C17 IOSTANDARD LVCMOS18} [get_ports tx_data_out[5]] ; ## IO_L15P_T2_DQS_AD12P_35 U1,C17,IO_L15_35_TX_D2_P +set_property -dict {PACKAGE_PIN D16 IOSTANDARD LVCMOS18} [get_ports tx_data_out[6]] ; ## IO_L16N_T2_35 U1,D16,IO_L16_35_TX_D3_N +set_property -dict {PACKAGE_PIN E16 IOSTANDARD LVCMOS18} [get_ports tx_data_out[7]] ; ## IO_L16P_T2_35 U1,E16,IO_L16_35_TX_D3_P +set_property -dict {PACKAGE_PIN B15 IOSTANDARD LVCMOS18} [get_ports tx_data_out[8]] ; ## IO_L17N_T2_AD5N_35 U1,B15,IO_L17_35_TX_D4_N +set_property -dict {PACKAGE_PIN B16 IOSTANDARD LVCMOS18} [get_ports tx_data_out[9]] ; ## IO_L17P_T2_AD5P_35 U1,B16,IO_L17_35_TX_D4_P +set_property -dict {PACKAGE_PIN A17 IOSTANDARD LVCMOS18} [get_ports tx_data_out[10]] ; ## IO_L18N_T2_AD13N_35 U1,A17,IO_L18_35_TX_D5_N +set_property -dict {PACKAGE_PIN B17 IOSTANDARD LVCMOS18} [get_ports tx_data_out[11]] ; ## IO_L18P_T2_AD13P_35 U1,B17,IO_L18_35_TX_D5_P + +set_property -dict {PACKAGE_PIN J13 IOSTANDARD LVCMOS18} [get_ports tx_gnd[0]] ; ## IO_L8N_T1_AD10N_35 U1,J13,IO_L08_35_FB_CLK_N +set_property -dict {PACKAGE_PIN J15 IOSTANDARD LVCMOS18} [get_ports tx_gnd[1]] ; ## IO_L9N_T1_DQS_AD3N_35 U1,J15,IO_L09_35_TX_FRAME_N + +# clocks + +create_clock -name rx_clk -period 8 [get_ports rx_clk_in] +create_clock -name ad9361_clk -period 8 [get_pins i_system_wrapper/system_i/axi_ad9361/clk] + diff --git a/projects/pzsdr2/common/pzsdr2_constr_lvds.xdc b/projects/pzsdr2/common/pzsdr2_constr_lvds.xdc new file mode 100644 index 000000000..febfb5977 --- /dev/null +++ b/projects/pzsdr2/common/pzsdr2_constr_lvds.xdc @@ -0,0 +1,42 @@ + +# constraints (pzsdr2.e) +# ad9361 + +set_property -dict {PACKAGE_PIN J14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_clk_in_p] ; ## IO_L12P_T1_MRCC_35 U1,J14,IO_L12_MRCC_35_DATA_CLK_P +set_property -dict {PACKAGE_PIN H14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_clk_in_n] ; ## IO_L12N_T1_MRCC_35 U1,H14,IO_L12_MRCC_35_DATA_CLK_N +set_property -dict {PACKAGE_PIN H13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_frame_in_p] ; ## IO_L7P_T1_AD2P_35 U1,H13,IO_L07_35_RX_FRAME_P +set_property -dict {PACKAGE_PIN H12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_frame_in_n] ; ## IO_L7N_T1_AD2N_35 U1,H12,IO_L07_35_RX_FRAME_N +set_property -dict {PACKAGE_PIN F12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_p[0]] ; ## IO_L1P_T0_AD0P_35 U1,F12,IO_L01_35_RX_D0_P +set_property -dict {PACKAGE_PIN E12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_n[0]] ; ## IO_L1N_T0_AD0N_35 U1,E12,IO_L01_35_RX_D0_N +set_property -dict {PACKAGE_PIN E10 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_p[1]] ; ## IO_L2P_T0_AD8P_35 U1,E10,IO_L02_35_RX_D1_P +set_property -dict {PACKAGE_PIN D10 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_n[1]] ; ## IO_L2N_T0_AD8N_35 U1,D10,IO_L02_35_RX_D1_N +set_property -dict {PACKAGE_PIN G10 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_p[2]] ; ## IO_L3P_T0_DQS_AD1P_35 U1,G10,IO_L03_35_RX_D2_P +set_property -dict {PACKAGE_PIN F10 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_n[2]] ; ## IO_L3N_T0_DQS_AD1N_35 U1,F10,IO_L03_35_RX_D2_N +set_property -dict {PACKAGE_PIN E11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_p[3]] ; ## IO_L4P_T0_35 U1,E11,IO_L04_35_RX_D3_P +set_property -dict {PACKAGE_PIN D11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_n[3]] ; ## IO_L4N_T0_35 U1,D11,IO_L04_35_RX_D3_N +set_property -dict {PACKAGE_PIN G12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_p[4]] ; ## IO_L5P_T0_AD9P_35 U1,G12,IO_L05_35_RX_D4_P +set_property -dict {PACKAGE_PIN G11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_n[4]] ; ## IO_L5N_T0_AD9N_35 U1,G11,IO_L05_35_RX_D4_N +set_property -dict {PACKAGE_PIN F13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_p[5]] ; ## IO_L6P_T0_35 U1,F13,IO_L06_35_RX_D5_P +set_property -dict {PACKAGE_PIN E13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_n[5]] ; ## IO_L6N_T0_VREF_35 U1,E13,IO_L06_35_RX_D5_N +set_property -dict {PACKAGE_PIN K13 IOSTANDARD LVDS} [get_ports tx_clk_out_p] ; ## IO_L8P_T1_AD10P_35 U1,K13,IO_L08_35_FB_CLK_P +set_property -dict {PACKAGE_PIN J13 IOSTANDARD LVDS} [get_ports tx_clk_out_n] ; ## IO_L8N_T1_AD10N_35 U1,J13,IO_L08_35_FB_CLK_N +set_property -dict {PACKAGE_PIN K15 IOSTANDARD LVDS} [get_ports tx_frame_out_p] ; ## IO_L9P_T1_DQS_AD3P_35 U1,K15,IO_L09_35_TX_FRAME_P +set_property -dict {PACKAGE_PIN J15 IOSTANDARD LVDS} [get_ports tx_frame_out_n] ; ## IO_L9N_T1_DQS_AD3N_35 U1,J15,IO_L09_35_TX_FRAME_N +set_property -dict {PACKAGE_PIN D15 IOSTANDARD LVDS} [get_ports tx_data_out_p[0]] ; ## IO_L13P_T2_MRCC_35 U1,D15,IO_L13_35_TX_D0_P +set_property -dict {PACKAGE_PIN D14 IOSTANDARD LVDS} [get_ports tx_data_out_n[0]] ; ## IO_L13N_T2_MRCC_35 U1,D14,IO_L13_35_TX_D0_N +set_property -dict {PACKAGE_PIN F15 IOSTANDARD LVDS} [get_ports tx_data_out_p[1]] ; ## IO_L14P_T2_AD4P_SRCC_35 U1,F15,IO_L14_35_TX_D1_P +set_property -dict {PACKAGE_PIN E15 IOSTANDARD LVDS} [get_ports tx_data_out_n[1]] ; ## IO_L14N_T2_AD4N_SRCC_35 U1,E15,IO_L14_35_TX_D1_N +set_property -dict {PACKAGE_PIN C17 IOSTANDARD LVDS} [get_ports tx_data_out_p[2]] ; ## IO_L15P_T2_DQS_AD12P_35 U1,C17,IO_L15_35_TX_D2_P +set_property -dict {PACKAGE_PIN C16 IOSTANDARD LVDS} [get_ports tx_data_out_n[2]] ; ## IO_L15N_T2_DQS_AD12N_35 U1,C16,IO_L15_35_TX_D2_N +set_property -dict {PACKAGE_PIN E16 IOSTANDARD LVDS} [get_ports tx_data_out_p[3]] ; ## IO_L16P_T2_35 U1,E16,IO_L16_35_TX_D3_P +set_property -dict {PACKAGE_PIN D16 IOSTANDARD LVDS} [get_ports tx_data_out_n[3]] ; ## IO_L16N_T2_35 U1,D16,IO_L16_35_TX_D3_N +set_property -dict {PACKAGE_PIN B16 IOSTANDARD LVDS} [get_ports tx_data_out_p[4]] ; ## IO_L17P_T2_AD5P_35 U1,B16,IO_L17_35_TX_D4_P +set_property -dict {PACKAGE_PIN B15 IOSTANDARD LVDS} [get_ports tx_data_out_n[4]] ; ## IO_L17N_T2_AD5N_35 U1,B15,IO_L17_35_TX_D4_N +set_property -dict {PACKAGE_PIN B17 IOSTANDARD LVDS} [get_ports tx_data_out_p[5]] ; ## IO_L18P_T2_AD13P_35 U1,B17,IO_L18_35_TX_D5_P +set_property -dict {PACKAGE_PIN A17 IOSTANDARD LVDS} [get_ports tx_data_out_n[5]] ; ## IO_L18N_T2_AD13N_35 U1,A17,IO_L18_35_TX_D5_N + +# clocks + +create_clock -name rx_clk -period 4 [get_ports rx_clk_in_p] +create_clock -name ad9361_clk -period 4 [get_pins i_system_wrapper/system_i/axi_ad9361/clk] + diff --git a/projects/scripts/adi_board.tcl b/projects/scripts/adi_board.tcl index ea905c85a..347c4c2bb 100644 --- a/projects/scripts/adi_board.tcl +++ b/projects/scripts/adi_board.tcl @@ -8,6 +8,11 @@ variable sys_hp2_interconnect_index variable sys_hp3_interconnect_index variable sys_mem_interconnect_index +variable xcvr_index +variable xcvr_tx_index +variable xcvr_rx_index +variable xcvr_instance + ################################################################################################### ################################################################################################### @@ -18,6 +23,11 @@ set sys_hp2_interconnect_index -1 set sys_hp3_interconnect_index -1 set sys_mem_interconnect_index -1 +set xcvr_index -1 +set xcvr_tx_index 0 +set xcvr_rx_index 0 +set xcvr_instance NONE + ################################################################################################### ################################################################################################### @@ -94,6 +104,136 @@ proc ad_connect {p_name_1 p_name_2} { } } +proc ad_disconnect {p_name_1 p_name_2} { + + set m_name_1 [ad_connect_type $p_name_1] + set m_name_2 [ad_connect_type $p_name_2] + + if {[get_property CLASS $m_name_1] eq "bd_net"} { + disconnect_bd_net $m_name_1 $m_name_2 + return + } + +} + +proc ad_reconct {p_name_1 p_name_2} { + + set m_name_1 [ad_connect_type $p_name_1] + set m_name_2 [ad_connect_type $p_name_2] + + if {[get_property CLASS $m_name_1] eq "bd_pin"} { + delete_bd_objs -quiet [get_bd_nets -quiet -of_objects \ + [find_bd_objs -relation connected_to $m_name_1]] + delete_bd_objs -quiet [get_bd_nets -quiet -of_objects \ + [find_bd_objs -relation connected_to $m_name_2]] + } + + if {[get_property CLASS $m_name_1] eq "bd_intf_pin"} { + delete_bd_objs -quiet [get_bd_intf_nets -quiet -of_objects \ + [find_bd_objs -relation connected_to $m_name_1]] + delete_bd_objs -quiet [get_bd_intf_nets -quiet -of_objects \ + [find_bd_objs -relation connected_to $m_name_2]] + } + + ad_connect $p_name_1 $p_name_2 +} + +################################################################################################### +################################################################################################### + +proc ad_xcvrcon {u_xcvr a_xcvr a_jesd} { + + global xcvr_index + global xcvr_tx_index + global xcvr_rx_index + global xcvr_instance + + set no_of_lanes [get_property CONFIG.NUM_OF_LANES [get_bd_cells $a_xcvr]] + set qpll_enable [get_property CONFIG.QPLL_ENABLE [get_bd_cells $a_xcvr]] + set tx_or_rx_n [get_property CONFIG.TX_OR_RX_N [get_bd_cells $a_xcvr]] + + if {$xcvr_instance ne $u_xcvr} { + set xcvr_index [expr ($xcvr_index + 1)] + set xcvr_tx_index 0 + set xcvr_rx_index 0 + set xcvr_instance $u_xcvr + } + + set txrx "rx" + set data_dir "I" + set ctrl_dir "O" + set index $xcvr_rx_index + + if {$tx_or_rx_n == 1} { + + set txrx "tx" + set data_dir "O" + set ctrl_dir "I" + set index $xcvr_tx_index + } + + set m_sysref ${txrx}_sysref_${index} + set m_sync ${txrx}_sync_${index} + set m_data ${txrx}_data + + if {$xcvr_index >= 1} { + + set m_sysref ${txrx}_sysref_${xcvr_index}_${index} + set m_sync ${txrx}_sync_${xcvr_index}_${index} + set m_data ${txrx}_data_${xcvr_index} + } + + create_bd_port -dir I $m_sysref + create_bd_port -dir ${ctrl_dir} $m_sync + create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 ${a_jesd}_rstgen + + for {set n 0} {$n < $no_of_lanes} {incr n} { + + set m [expr ($n + $index)] + + if {$tx_or_rx_n == 0} { + ad_connect ${a_xcvr}/up_es_${n} ${u_xcvr}/up_es_${m} + ad_connect ${a_jesd}/rxencommaalign_out ${u_xcvr}/${txrx}_calign_${m} + } + + if {(($m%4) == 0) && ($qpll_enable == 1)} { + ad_connect ${a_xcvr}/up_cm_${n} ${u_xcvr}/up_cm_${m} + } + + ad_connect ${a_xcvr}/up_ch_${n} ${u_xcvr}/up_${txrx}_${m} + ad_connect ${u_xcvr}/${txrx}_${m} ${a_jesd}/gt${n}_${txrx} + ad_connect ${u_xcvr}/${txrx}_out_clk_${index} ${u_xcvr}/${txrx}_clk_${m} + + create_bd_port -dir ${data_dir} ${m_data}_${m}_p + create_bd_port -dir ${data_dir} ${m_data}_${m}_n + ad_connect ${u_xcvr}/${txrx}_${m}_p ${m_data}_${m}_p + ad_connect ${u_xcvr}/${txrx}_${m}_n ${m_data}_${m}_n + } + + ad_connect ${a_jesd}/${txrx}_sysref $m_sysref + ad_connect ${a_jesd}/${txrx}_sync $m_sync + ad_connect ${u_xcvr}/${txrx}_out_clk_${index} ${a_jesd}/${txrx}_core_clk + ad_connect ${a_xcvr}/up_status ${a_jesd}/${txrx}_reset_done + ad_connect ${u_xcvr}/${txrx}_out_clk_${index} ${a_jesd}_rstgen/slowest_sync_clk + ad_connect sys_cpu_resetn ${a_jesd}_rstgen/ext_reset_in + ad_connect sys_cpu_reset ${a_jesd}/${txrx}_reset + + if {$tx_or_rx_n == 0} { + set xcvr_rx_index [expr ($xcvr_rx_index + $no_of_lanes)] + } + + if {$tx_or_rx_n == 1} { + set xcvr_tx_index [expr ($xcvr_tx_index + $no_of_lanes)] + } +} + +proc ad_xcvrpll {m_src m_dst} { + + foreach p_dst [get_bd_pins -quiet $m_dst] { + connect_bd_net [ad_connect_type $m_src] $p_dst + } +} + ################################################################################################### ################################################################################################### @@ -103,7 +243,7 @@ proc ad_mem_hp0_interconnect {p_clk p_name} { if {($sys_zynq == 0) && ($p_name eq "sys_ps7/S_AXI_HP0")} {return} if {$sys_zynq == 0} {ad_mem_hpx_interconnect "MEM" $p_clk $p_name} - if {$sys_zynq == 1} {ad_mem_hpx_interconnect "HP0" $p_clk $p_name} + if {$sys_zynq >= 1} {ad_mem_hpx_interconnect "HP0" $p_clk $p_name} } proc ad_mem_hp1_interconnect {p_clk p_name} { @@ -112,7 +252,7 @@ proc ad_mem_hp1_interconnect {p_clk p_name} { if {($sys_zynq == 0) && ($p_name eq "sys_ps7/S_AXI_HP1")} {return} if {$sys_zynq == 0} {ad_mem_hpx_interconnect "MEM" $p_clk $p_name} - if {$sys_zynq == 1} {ad_mem_hpx_interconnect "HP1" $p_clk $p_name} + if {$sys_zynq >= 1} {ad_mem_hpx_interconnect "HP1" $p_clk $p_name} } proc ad_mem_hp2_interconnect {p_clk p_name} { @@ -121,7 +261,7 @@ proc ad_mem_hp2_interconnect {p_clk p_name} { if {($sys_zynq == 0) && ($p_name eq "sys_ps7/S_AXI_HP2")} {return} if {$sys_zynq == 0} {ad_mem_hpx_interconnect "MEM" $p_clk $p_name} - if {$sys_zynq == 1} {ad_mem_hpx_interconnect "HP2" $p_clk $p_name} + if {$sys_zynq >= 1} {ad_mem_hpx_interconnect "HP2" $p_clk $p_name} } proc ad_mem_hp3_interconnect {p_clk p_name} { @@ -130,7 +270,7 @@ proc ad_mem_hp3_interconnect {p_clk p_name} { if {($sys_zynq == 0) && ($p_name eq "sys_ps7/S_AXI_HP3")} {return} if {$sys_zynq == 0} {ad_mem_hpx_interconnect "MEM" $p_clk $p_name} - if {$sys_zynq == 1} {ad_mem_hpx_interconnect "HP3" $p_clk $p_name} + if {$sys_zynq >= 1} {ad_mem_hpx_interconnect "HP3" $p_clk $p_name} } ################################################################################################### @@ -146,6 +286,7 @@ proc ad_mem_hpx_interconnect {p_sel p_clk p_name} { global sys_hp3_interconnect_index global sys_mem_interconnect_index + set p_name_int $p_name set p_clk_source [get_bd_pins -filter {DIR == O} -of_objects [get_bd_nets $p_clk]] if {$p_sel eq "MEM"} { @@ -157,8 +298,9 @@ proc ad_mem_hpx_interconnect {p_sel p_clk p_name} { set m_addr_seg [get_bd_addr_segs -of_objects [get_bd_cells axi_ddr_cntrl]] } - if {$p_sel eq "HP0"} { + if {($p_sel eq "HP0") && ($sys_zynq == 1)} { if {$sys_hp0_interconnect_index < 0} { + set p_name_int sys_ps7/S_AXI_HP0 set_property CONFIG.PCW_USE_S_AXI_HP0 {1} [get_bd_cells sys_ps7] create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_hp0_interconnect } @@ -167,8 +309,9 @@ proc ad_mem_hpx_interconnect {p_sel p_clk p_name} { set m_addr_seg [get_bd_addr_segs sys_ps7/S_AXI_HP0/HP0_DDR_LOWOCM] } - if {$p_sel eq "HP1"} { + if {($p_sel eq "HP1") && ($sys_zynq == 1)} { if {$sys_hp1_interconnect_index < 0} { + set p_name_int sys_ps7/S_AXI_HP1 set_property CONFIG.PCW_USE_S_AXI_HP1 {1} [get_bd_cells sys_ps7] create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_hp1_interconnect } @@ -177,8 +320,9 @@ proc ad_mem_hpx_interconnect {p_sel p_clk p_name} { set m_addr_seg [get_bd_addr_segs sys_ps7/S_AXI_HP1/HP1_DDR_LOWOCM] } - if {$p_sel eq "HP2"} { + if {($p_sel eq "HP2") && ($sys_zynq == 1)} { if {$sys_hp2_interconnect_index < 0} { + set p_name_int sys_ps7/S_AXI_HP2 set_property CONFIG.PCW_USE_S_AXI_HP2 {1} [get_bd_cells sys_ps7] create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_hp2_interconnect } @@ -187,8 +331,9 @@ proc ad_mem_hpx_interconnect {p_sel p_clk p_name} { set m_addr_seg [get_bd_addr_segs sys_ps7/S_AXI_HP2/HP2_DDR_LOWOCM] } - if {$p_sel eq "HP3"} { + if {($p_sel eq "HP3") && ($sys_zynq == 1)} { if {$sys_hp3_interconnect_index < 0} { + set p_name_int sys_ps7/S_AXI_HP3 set_property CONFIG.PCW_USE_S_AXI_HP3 {1} [get_bd_cells sys_ps7] create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_hp3_interconnect } @@ -197,6 +342,50 @@ proc ad_mem_hpx_interconnect {p_sel p_clk p_name} { set m_addr_seg [get_bd_addr_segs sys_ps7/S_AXI_HP3/HP3_DDR_LOWOCM] } + if {($p_sel eq "HP0") && ($sys_zynq == 2)} { + if {$sys_hp0_interconnect_index < 0} { + set p_name_int sys_ps8/S_AXI_HP0_FPD + set_property CONFIG.PSU__USE__S_AXI_GP2 {1} [get_bd_cells sys_ps8] + create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_hp0_interconnect + } + set m_interconnect_index $sys_hp0_interconnect_index + set m_interconnect_cell [get_bd_cells axi_hp0_interconnect] + set m_addr_seg [get_bd_addr_segs sys_ps8/S_AXI_HP0_FPD/PLLPD_DDR_LOW] + } + + if {($p_sel eq "HP1") && ($sys_zynq == 2)} { + if {$sys_hp1_interconnect_index < 0} { + set p_name_int sys_ps8/S_AXI_HP1_FPD + set_property CONFIG.PSU__USE__S_AXI_GP3 {1} [get_bd_cells sys_ps8] + create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_hp1_interconnect + } + set m_interconnect_index $sys_hp1_interconnect_index + set m_interconnect_cell [get_bd_cells axi_hp1_interconnect] + set m_addr_seg [get_bd_addr_segs sys_ps8/S_AXI_HP1_FPD/HP0_DDR_LOW] + } + + if {($p_sel eq "HP2") && ($sys_zynq == 2)} { + if {$sys_hp2_interconnect_index < 0} { + set p_name_int sys_ps8/S_AXI_HP2_FPD + set_property CONFIG.PSU__USE__S_AXI_GP4 {1} [get_bd_cells sys_ps8] + create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_hp2_interconnect + } + set m_interconnect_index $sys_hp2_interconnect_index + set m_interconnect_cell [get_bd_cells axi_hp2_interconnect] + set m_addr_seg [get_bd_addr_segs sys_ps8/S_AXI_HP2_FPD/HP1_DDR_LOW] + } + + if {($p_sel eq "HP3") && ($sys_zynq == 2)} { + if {$sys_hp3_interconnect_index < 0} { + set p_name_int sys_ps8/S_AXI_HP3_FPD + set_property CONFIG.PSU__USE__S_AXI_GP5 {1} [get_bd_cells sys_ps8] + create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_hp3_interconnect + } + set m_interconnect_index $sys_hp3_interconnect_index + set m_interconnect_cell [get_bd_cells axi_hp3_interconnect] + set m_addr_seg [get_bd_addr_segs sys_ps8/S_AXI_HP3_FPD/HP2_DDR_LOW] + } + set i_str "S$m_interconnect_index" if {$m_interconnect_index < 10} { set i_str "S0$m_interconnect_index" @@ -204,8 +393,8 @@ proc ad_mem_hpx_interconnect {p_sel p_clk p_name} { set m_interconnect_index [expr $m_interconnect_index + 1] - set p_intf_name [lrange [split $p_name "/"] end end] - set p_cell_name [lrange [split $p_name "/"] 0 0] + set p_intf_name [lrange [split $p_name_int "/"] end end] + set p_cell_name [lrange [split $p_name_int "/"] 0 0] set p_intf_clock [get_bd_pins -filter "TYPE == clk && (CONFIG.ASSOCIATED_BUSIF == ${p_intf_name} || \ CONFIG.ASSOCIATED_BUSIF =~ ${p_intf_name}:* || CONFIG.ASSOCIATED_BUSIF =~ *:${p_intf_name} || \ CONFIG.ASSOCIATED_BUSIF =~ *:${p_intf_name}:*)" -quiet -of_objects [get_bd_cells $p_cell_name]] @@ -214,29 +403,34 @@ proc ad_mem_hpx_interconnect {p_sel p_clk p_name} { set p_intf_clock "" } + regsub clk $p_clk resetn p_rst + if {[get_bd_nets -quiet $p_rst] eq ""} { + set p_rst sys_cpu_resetn + } + if {$m_interconnect_index == 0} { set_property CONFIG.NUM_MI 1 $m_interconnect_cell set_property CONFIG.NUM_SI 1 $m_interconnect_cell - ad_connect sys_cpu_resetn $m_interconnect_cell/ARESETN + ad_connect $p_rst $m_interconnect_cell/ARESETN ad_connect $p_clk $m_interconnect_cell/ACLK - ad_connect sys_cpu_resetn $m_interconnect_cell/M00_ARESETN + ad_connect $p_rst $m_interconnect_cell/M00_ARESETN ad_connect $p_clk $m_interconnect_cell/M00_ACLK - ad_connect $m_interconnect_cell/M00_AXI $p_name + ad_connect $m_interconnect_cell/M00_AXI $p_name_int if {$p_intf_clock ne ""} { ad_connect $p_clk $p_intf_clock } } else { set_property CONFIG.NUM_SI $m_interconnect_index $m_interconnect_cell - ad_connect sys_cpu_resetn $m_interconnect_cell/${i_str}_ARESETN + ad_connect $p_rst $m_interconnect_cell/${i_str}_ARESETN ad_connect $p_clk $m_interconnect_cell/${i_str}_ACLK - ad_connect $m_interconnect_cell/${i_str}_AXI $p_name + ad_connect $m_interconnect_cell/${i_str}_AXI $p_name_int if {$p_intf_clock ne ""} { ad_connect $p_clk $p_intf_clock } assign_bd_address $m_addr_seg } - if {$m_interconnect_index == 3} { + if {$m_interconnect_index > 1} { set_property CONFIG.STRATEGY {2} $m_interconnect_cell } @@ -245,6 +439,7 @@ proc ad_mem_hpx_interconnect {p_sel p_clk p_name} { if {$p_sel eq "HP1"} {set sys_hp1_interconnect_index $m_interconnect_index} if {$p_sel eq "HP2"} {set sys_hp2_interconnect_index $m_interconnect_index} if {$p_sel eq "HP3"} {set sys_hp3_interconnect_index $m_interconnect_index} + } ################################################################################################### @@ -262,6 +457,14 @@ proc ad_cpu_interconnect {p_address p_name} { if {$sys_cpu_interconnect_index == 0} { create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_cpu_interconnect + if {$sys_zynq == 2} { + ad_connect sys_cpu_clk sys_ps8/maxihpm0_lpd_aclk + ad_connect sys_cpu_clk axi_cpu_interconnect/ACLK + ad_connect sys_cpu_clk axi_cpu_interconnect/S00_ACLK + ad_connect sys_cpu_resetn axi_cpu_interconnect/ARESETN + ad_connect sys_cpu_resetn axi_cpu_interconnect/S00_ARESETN + ad_connect axi_cpu_interconnect/S00_AXI sys_ps8/M_AXI_HPM0_LPD + } if {$sys_zynq == 1} { ad_connect sys_cpu_clk sys_ps7/M_AXI_GP0_ACLK ad_connect sys_cpu_clk axi_cpu_interconnect/ACLK @@ -269,7 +472,8 @@ proc ad_cpu_interconnect {p_address p_name} { ad_connect sys_cpu_resetn axi_cpu_interconnect/ARESETN ad_connect sys_cpu_resetn axi_cpu_interconnect/S00_ARESETN ad_connect axi_cpu_interconnect/S00_AXI sys_ps7/M_AXI_GP0 - } else { + } + if {$sys_zynq == 0} { ad_connect sys_cpu_clk axi_cpu_interconnect/ACLK ad_connect sys_cpu_clk axi_cpu_interconnect/S00_ACLK ad_connect sys_cpu_resetn axi_cpu_interconnect/ARESETN @@ -278,9 +482,13 @@ proc ad_cpu_interconnect {p_address p_name} { } } + if {$sys_zynq == 2} { + set sys_addr_cntrl_space [get_bd_addr_spaces sys_ps8/Data] + } if {$sys_zynq == 1} { set sys_addr_cntrl_space [get_bd_addr_spaces sys_ps7/Data] - } else { + } + if {$sys_zynq == 0} { set sys_addr_cntrl_space [get_bd_addr_spaces sys_mb/Data] } @@ -326,6 +534,17 @@ proc ad_cpu_interconnect {p_address p_name} { foreach p_seg_name $p_seg { if {$p_index == 0} { set p_seg_range [get_property range $p_seg_name] + if {$p_seg_range < 0x1000} { + set p_seg_range 0x1000 + } + if {$sys_zynq == 2} { + if {($p_address >= 0x40000000) && ($p_address <= 0x4fffffff)} { + set p_address [expr ($p_address + 0x40000000)] + } + if {($p_address >= 0x70000000) && ($p_address <= 0x7fffffff)} { + set p_address [expr ($p_address + 0x20000000)] + } + } create_bd_addr_seg -range $p_seg_range \ -offset $p_address $sys_addr_cntrl_space \ $p_seg_name "SEG_data_${p_name}" @@ -343,18 +562,39 @@ proc ad_cpu_interrupt {p_ps_index p_mb_index p_name} { global sys_zynq - if {$sys_zynq == 1} { - set p_index [regsub -all {[^0-9]} $p_ps_index ""] - } else { - set p_index [regsub -all {[^0-9]} $p_mb_index ""] + if {$sys_zynq == 0} {set p_index_int $p_mb_index} + if {$sys_zynq >= 1} {set p_index_int $p_ps_index} + + set p_index [regsub -all {[^0-9]} $p_index_int ""] + set m_index [expr ($p_index - 8)] + + if {($sys_zynq == 2) && ($p_index <= 7)} { + set p_net [get_bd_nets -of_objects [get_bd_pins sys_concat_intc_0/In$p_index]] + set p_pin [find_bd_objs -relation connected_to [get_bd_pins sys_concat_intc_0/In$p_index]] + + puts "delete_bd_objs $p_net $p_pin" + delete_bd_objs $p_net $p_pin + ad_connect sys_concat_intc_0/In$p_index $p_name } - set p_net [get_bd_nets -of_objects [get_bd_pins sys_concat_intc/In$p_index]] - set p_pin [find_bd_objs -relation connected_to [get_bd_pins sys_concat_intc/In$p_index]] + if {($sys_zynq == 2) && ($p_index >= 8)} { + set p_net [get_bd_nets -of_objects [get_bd_pins sys_concat_intc_1/In$m_index]] + set p_pin [find_bd_objs -relation connected_to [get_bd_pins sys_concat_intc_1/In$m_index]] - puts "delete_bd_objs $p_net $p_pin" - delete_bd_objs $p_net $p_pin - ad_connect sys_concat_intc/In$p_index $p_name + puts "delete_bd_objs $p_net $p_pin" + delete_bd_objs $p_net $p_pin + ad_connect sys_concat_intc_1/In$m_index $p_name + } + + if {$sys_zynq <= 1} { + + set p_net [get_bd_nets -of_objects [get_bd_pins sys_concat_intc/In$p_index]] + set p_pin [find_bd_objs -relation connected_to [get_bd_pins sys_concat_intc/In$p_index]] + + puts "delete_bd_objs $p_net $p_pin" + delete_bd_objs $p_net $p_pin + ad_connect sys_concat_intc/In$p_index $p_name + } } ################################################################################################### diff --git a/projects/scripts/adi_env.tcl b/projects/scripts/adi_env.tcl index e5e15c4ee..1e6ef3183 100644 --- a/projects/scripts/adi_env.tcl +++ b/projects/scripts/adi_env.tcl @@ -1,8 +1,9 @@ # environment related stuff -set ad_hdl_dir "../../.." -set ad_phdl_dir "../../.." +set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] +set ad_phdl_dir $ad_hdl_dir + if [info exists ::env(ADI_HDL_DIR)] { set ad_hdl_dir $::env(ADI_HDL_DIR) diff --git a/projects/scripts/adi_project.tcl b/projects/scripts/adi_project.tcl index f404df885..3e61925e5 100644 --- a/projects/scripts/adi_project.tcl +++ b/projects/scripts/adi_project.tcl @@ -7,7 +7,7 @@ variable p_prcfg_list variable p_prcfg_status if {![info exists REQUIRED_VIVADO_VERSION]} { - set REQUIRED_VIVADO_VERSION "2015.4.2" + set REQUIRED_VIVADO_VERSION "2016.2" } if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { @@ -16,6 +16,10 @@ if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { set IGNORE_VERSION_CHECK 0 } +set p_board "not-applicable" +set p_device "none" +set sys_zynq 1 + proc adi_project_create {project_name {mode 0}} { global ad_hdl_dir @@ -26,10 +30,6 @@ proc adi_project_create {project_name {mode 0}} { global REQUIRED_VIVADO_VERSION global IGNORE_VERSION_CHECK - set p_device "none" - set p_board "none" - set sys_zynq 0 - if [regexp "_ac701$" $project_name] { set p_device "xc7a200tfbg676-2" set p_board "xilinx.com:ac701:part0:1.0" @@ -55,6 +55,11 @@ proc adi_project_create {project_name {mode 0}} { set p_board "em.avnet.com:zed:part0:1.3" set sys_zynq 1 } + if [regexp "_microzed$" $project_name] { + set p_device "xc7z010clg400-1" + set p_board "not-applicable" + set sys_zynq 1 + } if [regexp "_zc702$" $project_name] { set p_device "xc7z020clg484-1" set p_board "xilinx.com:zc702:part0:1.2" @@ -70,10 +75,10 @@ proc adi_project_create {project_name {mode 0}} { set p_board "not-applicable" set sys_zynq 1 } - if [regexp "_pzsdr$" $project_name] { - set p_device "xc7z035ifbg676-2L" - set p_board "not-applicable" - set sys_zynq 1 + if [regexp "_zcu102$" $project_name] { + set p_device "xczu9eg-ffvb1156-1-i-es1" + set p_board "xilinx.com:zcu102:part0:1.2" + set sys_zynq 2 } if {!$IGNORE_VERSION_CHECK && [string compare [version -short] $REQUIRED_VIVADO_VERSION] != 0} { diff --git a/projects/scripts/adi_tquest.tcl b/projects/scripts/adi_tquest.tcl index 59abc8c0a..a8f5d4a7f 100755 --- a/projects/scripts/adi_tquest.tcl +++ b/projects/scripts/adi_tquest.tcl @@ -14,5 +14,11 @@ if {$slack > 0} { } if {$slack < 0} { + set sof_files [glob *.sof] + foreach sof_file $sof_files { + set root_sof_file [file rootname $sof_file] + set new_sof_file [append root_sof_file "_timing.sof"] + file rename -force $sof_file $new_sof_file + } return -code error [format "ERROR: Timing Constraints NOT met!"] } diff --git a/projects/usb_fx3/common/usb_fx3_bd.tcl b/projects/usb_fx3/common/usb_fx3_bd.tcl index 8c1c8f0ad..3cf47338a 100644 --- a/projects/usb_fx3/common/usb_fx3_bd.tcl +++ b/projects/usb_fx3/common/usb_fx3_bd.tcl @@ -4,10 +4,10 @@ create_bd_port -dir O usb_fx3_uart_rx create_bd_port -dir I dma_rdy create_bd_port -dir I dma_wmk -create_bd_port -dir I -from 10 -to 0 fifo_rdy +create_bd_port -dir I -from 3 -to 0 fifo_rdy create_bd_port -dir O pclk -create_bd_port -dir O -from 31 -to 0 data -create_bd_port -dir O -from 4 -to 0 addr +create_bd_port -dir IO -from 31 -to 0 data +create_bd_port -dir O -from 1 -to 0 addr create_bd_port -dir O slcs_n create_bd_port -dir O slrd_n create_bd_port -dir O sloe_n @@ -15,18 +15,31 @@ create_bd_port -dir O slwr_n create_bd_port -dir O pktend_n create_bd_port -dir O epswitch_n -set_property -dict [list CONFIG.PCW_UART0_PERIPHERAL_ENABLE {1}] $sys_ps7 +set axi_uart [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_uartlite:2.0 axi_uart] +set_property -dict [list CONFIG.C_BAUDRATE {115200}] $axi_uart set axi_usb_fx3 [create_bd_cell -type ip -vlnv analog.com:user:axi_usb_fx3:1.0 axi_usb_fx3] set axi_usb_fx3_dma [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_usb_fx3_dma] set_property -dict [list CONFIG.c_sg_include_stscntrl_strm {0}] $axi_usb_fx3_dma +set_property -dict [list CONFIG.c_mm2s_burst_size {256}] $axi_usb_fx3_dma +set_property -dict [list CONFIG.c_s2mm_burst_size {256}] $axi_usb_fx3_dma +set_property -dict [list CONFIG.c_sg_length_width {16}] $axi_usb_fx3_dma + +set usb_fx3_rx_axis_fifo [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:1.1 usb_fx3_rx_axis_fifo ] + +set intr_monitor [ create_bd_cell -type ip -vlnv analog.com:user:axi_intr_monitor:1.0 intr_monitor ] -ad_connect axi_usb_fx3_dma/S_AXIS_S2MM axi_usb_fx3/m_axis ad_connect axi_usb_fx3/s_axis axi_usb_fx3_dma/M_AXIS_MM2S -ad_connect /sys_ps7/UART0_RX usb_fx3_uart_tx -ad_connect /sys_ps7/UART0_TX usb_fx3_uart_rx +ad_connect sys_cpu_clk usb_fx3_rx_axis_fifo/s_axis_aclk +ad_connect sys_cpu_resetn usb_fx3_rx_axis_fifo/s_axis_aresetn + +ad_connect axi_usb_fx3/m_axis usb_fx3_rx_axis_fifo/S_AXIS +ad_connect axi_usb_fx3_dma/S_AXIS_S2MM usb_fx3_rx_axis_fifo/M_AXIS + +ad_connect axi_uart/rx usb_fx3_uart_tx +ad_connect axi_uart/tx usb_fx3_uart_rx ad_connect sys_cpu_clk axi_usb_fx3/s_axi_aclk ad_connect sys_cpu_resetn axi_usb_fx3/s_axi_aresetn @@ -47,9 +60,14 @@ ad_connect axi_usb_fx3/epswitch_n epswitch_n ad_cpu_interrupt ps-13 mb-12 axi_usb_fx3/irq ad_cpu_interrupt ps-12 mb-13 axi_usb_fx3_dma/mm2s_introut ad_cpu_interrupt ps-11 mb-14 axi_usb_fx3_dma/s2mm_introut +ad_cpu_interrupt ps-10 mb-15 axi_uart/interrupt +ad_cpu_interrupt ps-9 mb-16 intr_monitor/irq ad_cpu_interconnect 0x50000000 axi_usb_fx3 ad_cpu_interconnect 0x40400000 axi_usb_fx3_dma +ad_cpu_interconnect 0x40600000 axi_uart +ad_cpu_interconnect 0x43c00000 intr_monitor + ad_mem_hp1_interconnect sys_cpu_clk sys_ps7/S_AXI_HP1 ad_mem_hp1_interconnect sys_cpu_clk axi_usb_fx3_dma/M_AXI_SG ad_mem_hp1_interconnect sys_cpu_clk axi_usb_fx3_dma/M_AXI_MM2S @@ -57,16 +75,16 @@ ad_mem_hp1_interconnect sys_cpu_clk axi_usb_fx3_dma/M_AXI_S2MM # test -set vcc [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 vcc] -#ad_connect vcc/dout axi_usb_fx3/m_axis_tready +set ila [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.1 ila] -set ila [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.0 ila] set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila -set_property -dict [list CONFIG.C_NUM_OF_PROBES {3}] $ila +set_property -dict [list CONFIG.C_NUM_OF_PROBES {11}] $ila +set_property -dict [list CONFIG.C_PROBE10_WIDTH {4}] $ila +set_property -dict [list CONFIG.C_PROBE3_WIDTH {2}] $ila set_property -dict [list CONFIG.C_PROBE2_WIDTH {15}] $ila set_property -dict [list CONFIG.C_PROBE1_WIDTH {74}] $ila set_property -dict [list CONFIG.C_PROBE0_WIDTH {75}] $ila -set_property -dict [list CONFIG.C_DATA_DEPTH {32768}] $ila +set_property -dict [list CONFIG.C_DATA_DEPTH {65536}] $ila set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila set_property -dict [list CONFIG.C_PROBE2_MU_CNT {2}] $ila set_property -dict [list CONFIG.C_PROBE1_MU_CNT {2}] $ila @@ -78,3 +96,11 @@ ad_connect ila/clk axi_usb_fx3/pclk ad_connect ila/probe0 axi_usb_fx3/debug_fx32dma ad_connect ila/probe1 axi_usb_fx3/debug_dma2fx3 ad_connect ila/probe2 axi_usb_fx3/debug_status +ad_connect ila/probe3 axi_usb_fx3/addr +ad_connect ila/probe4 axi_usb_fx3/epswitch_n +ad_connect ila/probe5 axi_usb_fx3/slcs_n +ad_connect ila/probe6 axi_usb_fx3/slrd_n +ad_connect ila/probe7 axi_usb_fx3/sloe_n +ad_connect ila/probe8 axi_usb_fx3/slwr_n +ad_connect ila/probe9 axi_usb_fx3/pktend_n +ad_connect ila/probe10 fifo_rdy diff --git a/projects/usb_fx3/zc706/Makefile b/projects/usb_fx3/zc706/Makefile index eb786cf55..545469501 100644 --- a/projects/usb_fx3/zc706/Makefile +++ b/projects/usb_fx3/zc706/Makefile @@ -15,9 +15,10 @@ M_DEPS += ../../scripts/adi_env.tcl M_DEPS += ../../scripts/adi_board.tcl M_DEPS += ../../common/zc706/zc706_system_constr.xdc M_DEPS += ../../common/zc706/zc706_system_bd.tcl -M_DEPS += ../../../library/common/ad_iobuf.v +M_DEPS += ../../../library/xilinx/common/ad_iobuf.v M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr +M_DEPS += ../../../library/axi_intr_monitor/axi_intr_monitor.xpr M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr M_DEPS += ../../../library/axi_usb_fx3/axi_usb_fx3.xpr @@ -35,6 +36,7 @@ M_FLIST += *.sdk M_FLIST += *.hw M_FLIST += *.sim M_FLIST += .Xil +M_FLIST += *.ip_user_files @@ -49,18 +51,20 @@ clean: clean-all:clean make -C ../../../library/axi_clkgen clean make -C ../../../library/axi_hdmi_tx clean + make -C ../../../library/axi_intr_monitor clean make -C ../../../library/axi_spdif_tx clean make -C ../../../library/axi_usb_fx3 clean usb_fx3_zc706.sdk/system_top.hdf: $(M_DEPS) - rm -rf $(M_FLIST) + -rm -rf $(M_FLIST) $(M_VIVADO) system_project.tcl >> usb_fx3_zc706_vivado.log 2>&1 lib: make -C ../../../library/axi_clkgen make -C ../../../library/axi_hdmi_tx + make -C ../../../library/axi_intr_monitor make -C ../../../library/axi_spdif_tx make -C ../../../library/axi_usb_fx3 diff --git a/projects/usb_fx3/zc706/system_constr.xdc b/projects/usb_fx3/zc706/system_constr.xdc index c425d3f2d..e09775cbb 100644 --- a/projects/usb_fx3/zc706/system_constr.xdc +++ b/projects/usb_fx3/zc706/system_constr.xdc @@ -2,64 +2,66 @@ # constraints # USB_FX3 -#set_property -dict {PACKAGE_PIN AG17 IOSTANDARD LVCMOS33} [get_ports data[0]] ; ## H04 FMC_LPC_CLK0_M2C_P -#set_property -dict {PACKAGE_PIN AE12 IOSTANDARD LVCMOS33} [get_ports data[1]] ; ## H07 FMC_LPC_LA02_P -#set_property -dict {PACKAGE_PIN AF12 IOSTANDARD LVCMOS33} [get_ports data[2]] ; ## H08 FMC_LPC_LA02_N -#set_property -dict {PACKAGE_PIN AJ15 IOSTANDARD LVCMOS33} [get_ports data[3]] ; ## H10 FMC_LPC_LA04_P -#set_property -dict {PACKAGE_PIN AK15 IOSTANDARD LVCMOS33} [get_ports data[4]] ; ## H11 FMC_LPC_LA04_N -#set_property -dict {PACKAGE_PIN AA15 IOSTANDARD LVCMOS33} [get_ports data[5]] ; ## H13 FMC_LPC_LA07_P -#set_property -dict {PACKAGE_PIN AA14 IOSTANDARD LVCMOS33} [get_ports data[6]] ; ## H14 FMC_LPC_LA07_N -#set_property -dict {PACKAGE_PIN AJ16 IOSTANDARD LVCMOS33} [get_ports data[7]] ; ## H16 FMC_LPC_LA11_P -#set_property -dict {PACKAGE_PIN AK16 IOSTANDARD LVCMOS33} [get_ports data[8]] ; ## H17 FMC_LPC_LA11_N -#set_property -dict {PACKAGE_PIN AB15 IOSTANDARD LVCMOS33} [get_ports data[9]] ; ## H19 FMC_LPC_LA15_P -#set_property -dict {PACKAGE_PIN AB14 IOSTANDARD LVCMOS33} [get_ports data[10]] ; ## H20 FMC_LPC_LA15_N -#set_property -dict {PACKAGE_PIN AH26 IOSTANDARD LVCMOS33} [get_ports data[11]] ; ## H22 FMC_LPC_LA19_P -#set_property -dict {PACKAGE_PIN AH27 IOSTANDARD LVCMOS33} [get_ports data[12]] ; ## H23 FMC_LPC_LA19_N -#set_property -dict {PACKAGE_PIN AH28 IOSTANDARD LVCMOS33} [get_ports data[13]] ; ## H25 FMC_LPC_LA21_P -#set_property -dict {PACKAGE_PIN AH29 IOSTANDARD LVCMOS33} [get_ports data[14]] ; ## H26 FMC_LPC_LA21_N -#set_property -dict {PACKAGE_PIN AF30 IOSTANDARD LVCMOS33} [get_ports data[15]] ; ## H28 FMC_LPC_LA24_P -#set_property -dict {PACKAGE_PIN AG30 IOSTANDARD LVCMOS33} [get_ports data[16]] ; ## H29 FMC_LPC_LA24_N -#set_property -dict {PACKAGE_PIN AD25 IOSTANDARD LVCMOS33} [get_ports data[17]] ; ## H31 FMC_LPC_LA28_P -#set_property -dict {PACKAGE_PIN AE26 IOSTANDARD LVCMOS33} [get_ports data[18]] ; ## H32 FMC_LPC_LA28_N -#set_property -dict {PACKAGE_PIN AB29 IOSTANDARD LVCMOS33} [get_ports data[19]] ; ## H34 FMC_LPC_LA30_P -#set_property -dict {PACKAGE_PIN AB30 IOSTANDARD LVCMOS33} [get_ports data[20]] ; ## H35 FMC_LPC_LA30_N -#set_property -dict {PACKAGE_PIN Y26 IOSTANDARD LVCMOS33} [get_ports data[21]] ; ## H37 FMC_LPC_LA32_P -#set_property -dict {PACKAGE_PIN Y27 IOSTANDARD LVCMOS33} [get_ports data[22]] ; ## H38 FMC_LPC_LA32_N -#set_property -dict {PACKAGE_PIN AC28 IOSTANDARD LVCMOS33} [get_ports data[23]] ; ## G02 FMC_LPC_CLK1_M2C_P -#set_property -dict {PACKAGE_PIN AD28 IOSTANDARD LVCMOS33} [get_ports data[24]] ; ## G03 FMC_LPC_CLK1_M2C_N -#set_property -dict {PACKAGE_PIN AG12 IOSTANDARD LVCMOS33} [get_ports data[25]] ; ## G09 FMC_LPC_LA03_P -#set_property -dict {PACKAGE_PIN AH12 IOSTANDARD LVCMOS33} [get_ports data[26]] ; ## G10 FMC_LPC_LA03_N -#set_property -dict {PACKAGE_PIN AD14 IOSTANDARD LVCMOS33} [get_ports data[27]] ; ## G12 FMC_LPC_LA08_P -#set_property -dict {PACKAGE_PIN AD13 IOSTANDARD LVCMOS33} [get_ports data[28]] ; ## G13 FMC_LPC_LA08_N -#set_property -dict {PACKAGE_PIN AD16 IOSTANDARD LVCMOS33} [get_ports data[29]] ; ## G15 FMC_LPC_LA12_P -#set_property -dict {PACKAGE_PIN AD15 IOSTANDARD LVCMOS33} [get_ports data[30]] ; ## G16 FMC_LPC_LA12_N -#set_property -dict {PACKAGE_PIN AE18 IOSTANDARD LVCMOS33} [get_ports data[31]] ; ## G18 FMC_LPC_LA16_P -# -#set_property -dict {PACKAGE_PIN AE13 IOSTANDARD LVCMOS33} [get_ports pclk] ; ## G06 FMC_LPC_LA00_CC_P -# -#set_property -dict {PACKAGE_PIN AA30 IOSTANDARD LVCMOS33} [get_ports addr[0]] ; ## G37 FMC_LPC_LA33_N -#set_property -dict {PACKAGE_PIN Y30 IOSTANDARD LVCMOS33} [get_ports addr[1]] ; ## G36 FMC_LPC_LA33_P -#set_property -dict {PACKAGE_PIN AD29 IOSTANDARD LVCMOS33} [get_ports addr[2]] ; ## G34 FMC_LPC_LA31_N -#set_property -dict {PACKAGE_PIN AC29 IOSTANDARD LVCMOS33} [get_ports addr[3]] ; ## G33 FMC_LPC_LA31_P +set_property -dict {PACKAGE_PIN AG17 IOSTANDARD LVCMOS25} [get_ports data[0]] ; ## H04 FMC_LPC_CLK0_M2C_P +set_property -dict {PACKAGE_PIN AE12 IOSTANDARD LVCMOS25} [get_ports data[1]] ; ## H07 FMC_LPC_LA02_P +set_property -dict {PACKAGE_PIN AF12 IOSTANDARD LVCMOS25} [get_ports data[2]] ; ## H08 FMC_LPC_LA02_N +set_property -dict {PACKAGE_PIN AJ15 IOSTANDARD LVCMOS25} [get_ports data[3]] ; ## H10 FMC_LPC_LA04_P +set_property -dict {PACKAGE_PIN AK15 IOSTANDARD LVCMOS25} [get_ports data[4]] ; ## H11 FMC_LPC_LA04_N +set_property -dict {PACKAGE_PIN AA15 IOSTANDARD LVCMOS25} [get_ports data[5]] ; ## H13 FMC_LPC_LA07_P +set_property -dict {PACKAGE_PIN AA14 IOSTANDARD LVCMOS25} [get_ports data[6]] ; ## H14 FMC_LPC_LA07_N +set_property -dict {PACKAGE_PIN AJ16 IOSTANDARD LVCMOS25} [get_ports data[7]] ; ## H16 FMC_LPC_LA11_P +set_property -dict {PACKAGE_PIN AK16 IOSTANDARD LVCMOS25} [get_ports data[8]] ; ## H17 FMC_LPC_LA11_N +set_property -dict {PACKAGE_PIN AB15 IOSTANDARD LVCMOS25} [get_ports data[9]] ; ## H19 FMC_LPC_LA15_P +set_property -dict {PACKAGE_PIN AB14 IOSTANDARD LVCMOS25} [get_ports data[10]] ; ## H20 FMC_LPC_LA15_N +set_property -dict {PACKAGE_PIN AH26 IOSTANDARD LVCMOS25} [get_ports data[11]] ; ## H22 FMC_LPC_LA19_P +set_property -dict {PACKAGE_PIN AH27 IOSTANDARD LVCMOS25} [get_ports data[12]] ; ## H23 FMC_LPC_LA19_N +set_property -dict {PACKAGE_PIN AH28 IOSTANDARD LVCMOS25} [get_ports data[13]] ; ## H25 FMC_LPC_LA21_P +set_property -dict {PACKAGE_PIN AH29 IOSTANDARD LVCMOS25} [get_ports data[14]] ; ## H26 FMC_LPC_LA21_N +set_property -dict {PACKAGE_PIN AF30 IOSTANDARD LVCMOS25} [get_ports data[15]] ; ## H28 FMC_LPC_LA24_P +set_property -dict {PACKAGE_PIN AG30 IOSTANDARD LVCMOS25} [get_ports data[16]] ; ## H29 FMC_LPC_LA24_N +set_property -dict {PACKAGE_PIN AD25 IOSTANDARD LVCMOS25} [get_ports data[17]] ; ## H31 FMC_LPC_LA28_P +set_property -dict {PACKAGE_PIN AE26 IOSTANDARD LVCMOS25} [get_ports data[18]] ; ## H32 FMC_LPC_LA28_N +set_property -dict {PACKAGE_PIN AB29 IOSTANDARD LVCMOS25} [get_ports data[19]] ; ## H34 FMC_LPC_LA30_P +set_property -dict {PACKAGE_PIN AB30 IOSTANDARD LVCMOS25} [get_ports data[20]] ; ## H35 FMC_LPC_LA30_N +set_property -dict {PACKAGE_PIN Y26 IOSTANDARD LVCMOS25} [get_ports data[21]] ; ## H37 FMC_LPC_LA32_P +set_property -dict {PACKAGE_PIN Y27 IOSTANDARD LVCMOS25} [get_ports data[22]] ; ## H38 FMC_LPC_LA32_N +set_property -dict {PACKAGE_PIN AC28 IOSTANDARD LVCMOS25} [get_ports data[23]] ; ## G02 FMC_LPC_CLK1_M2C_P +set_property -dict {PACKAGE_PIN AD28 IOSTANDARD LVCMOS25} [get_ports data[24]] ; ## G03 FMC_LPC_CLK1_M2C_N +set_property -dict {PACKAGE_PIN AG12 IOSTANDARD LVCMOS25} [get_ports data[25]] ; ## G09 FMC_LPC_LA03_P +set_property -dict {PACKAGE_PIN AH12 IOSTANDARD LVCMOS25} [get_ports data[26]] ; ## G10 FMC_LPC_LA03_N +set_property -dict {PACKAGE_PIN AD14 IOSTANDARD LVCMOS25} [get_ports data[27]] ; ## G12 FMC_LPC_LA08_P +set_property -dict {PACKAGE_PIN AD13 IOSTANDARD LVCMOS25} [get_ports data[28]] ; ## G13 FMC_LPC_LA08_N +set_property -dict {PACKAGE_PIN AD16 IOSTANDARD LVCMOS25} [get_ports data[29]] ; ## G15 FMC_LPC_LA12_P +set_property -dict {PACKAGE_PIN AD15 IOSTANDARD LVCMOS25} [get_ports data[30]] ; ## G16 FMC_LPC_LA12_N +set_property -dict {PACKAGE_PIN AE18 IOSTANDARD LVCMOS25} [get_ports data[31]] ; ## G18 FMC_LPC_LA16_P + +set_property -dict {PACKAGE_PIN AE13 IOSTANDARD LVCMOS25} [get_ports pclk] ; ## G06 FMC_LPC_LA00_CC_P + +set_property -dict {PACKAGE_PIN AA30 IOSTANDARD LVCMOS25} [get_ports addr[0]] ; ## G37 FMC_LPC_LA33_N +set_property -dict {PACKAGE_PIN Y30 IOSTANDARD LVCMOS25} [get_ports addr[1]] ; ## G36 FMC_LPC_LA33_P +#set_property -dict {PACKAGE_PIN AD29 IOSTANDARD LVCMOS25} [get_ports addr[2]] ; ## G34 FMC_LPC_LA31_N +#set_property -dict {PACKAGE_PIN AC29 IOSTANDARD LVCMOS25} [get_ports addr[3]] ; ## G33 FMC_LPC_LA31_P #set_property -dict {PACKAGE_PIN AF25 IOSTANDARD LVCMOS33} [get_ports addr[4]] ; ## G31 FMC_LPC_LA29_N -# -#set_property -dict {PACKAGE_PIN AE17 IOSTANDARD LVCMOS33} [get_ports slcs_n] ; ## G19 FMC_LPC_LA16_N -#set_property -dict {PACKAGE_PIN AG26 IOSTANDARD LVCMOS33} [get_ports slwr_n] ; ## G21 FMC_LPC_LA20_P -#set_property -dict {PACKAGE_PIN AG27 IOSTANDARD LVCMOS33} [get_ports sloe_n] ; ## G22 FMC_LPC_LA20_N -#set_property -dict {PACKAGE_PIN AK27 IOSTANDARD LVCMOS33} [get_ports slrd_n] ; ## G24 FMC_LPC_LA22_P -#set_property -dict {PACKAGE_PIN AE25 IOSTANDARD LVCMOS33} [get_ports pktend_n] ; ## G30 FMC_LPC_LA29_P + +set_property -dict {PACKAGE_PIN AE17 IOSTANDARD LVCMOS25} [get_ports slcs_n] ; ## G19 FMC_LPC_LA16_N +set_property -dict {PACKAGE_PIN AG26 IOSTANDARD LVCMOS25} [get_ports slwr_n] ; ## G21 FMC_LPC_LA20_P +set_property -dict {PACKAGE_PIN AG27 IOSTANDARD LVCMOS25} [get_ports sloe_n] ; ## G22 FMC_LPC_LA20_N +set_property -dict {PACKAGE_PIN AK27 IOSTANDARD LVCMOS25} [get_ports slrd_n] ; ## G24 FMC_LPC_LA22_P +set_property -dict {PACKAGE_PIN AE25 IOSTANDARD LVCMOS25} [get_ports pktend_n] ; ## G30 FMC_LPC_LA29_P set_property -dict {PACKAGE_PIN AJ21 IOSTANDARD LVCMOS25} [get_ports usb_fx3_uart_tx] ; ## PMOD1_0, Connector J58 pin 1, 3.3V through level shifter set_property -dict {PACKAGE_PIN Y20 IOSTANDARD LVCMOS25} [get_ports usb_fx3_uart_rx] ; ## PMOD1_4, Connector J58 pin 2, 3.3V through level shifter -#set_property -dict {PACKAGE_PIN AE18 IOSTANDARD LVCMOS33} [get_ports fifo_rdy[0]] ; ## G18 FMC_LPC_LA16_P -#set_property -dict {PACKAGE_PIN AE18 IOSTANDARD LVCMOS33} [get_ports fifo_rdy[1]] ; ## G18 FMC_LPC_LA16_P -#set_property -dict {PACKAGE_PIN AE18 IOSTANDARD LVCMOS33} [get_ports fifo_rdy[2]] ; ## G18 FMC_LPC_LA16_P -#set_property -dict {PACKAGE_PIN AE18 IOSTANDARD LVCMOS33} [get_ports fifo_rdy[3]] ; ## G18 FMC_LPC_LA16_P +set_property -dict {PACKAGE_PIN AK28 IOSTANDARD LVCMOS25} [get_ports fifo_rdy[0]] ; ## G25 FMC_LPC_LA22_N +set_property -dict {PACKAGE_PIN AF29 IOSTANDARD LVCMOS25} [get_ports fifo_rdy[1]] ; ## G27 FMC_LPC_LA25_P +set_property -dict {PACKAGE_PIN AG29 IOSTANDARD LVCMOS25} [get_ports fifo_rdy[2]] ; ## G28 FMC_LPC_LA25_N +set_property -dict {PACKAGE_PIN AF25 IOSTANDARD LVCMOS25} [get_ports fifo_rdy[3]] ; ## G31 FMC_LPC_LA29_N #set_property -dict {PACKAGE_PIN AE18 IOSTANDARD LVCMOS33} [get_ports fifo_rdy[4]] ; ## G18 FMC_LPC_LA16_P #set_property -dict {PACKAGE_PIN AE18 IOSTANDARD LVCMOS33} [get_ports fifo_rdy[5]] ; ## G18 FMC_LPC_LA16_P #set_property -dict {PACKAGE_PIN AE18 IOSTANDARD LVCMOS33} [get_ports fifo_rdy[6]] ; ## G18 FMC_LPC_LA16_P #set_property -dict {PACKAGE_PIN AE18 IOSTANDARD LVCMOS33} [get_ports fifo_rdy[7]] ; ## G18 FMC_LPC_LA16_P #set_property -dict {PACKAGE_PIN AE18 IOSTANDARD LVCMOS33} [get_ports fifo_rdy[8]] ; ## G18 FMC_LPC_LA16_P #set_property -dict {PACKAGE_PIN AE18 IOSTANDARD LVCMOS33} [get_ports fifo_rdy[9]] ; ## G18 FMC_LPC_LA16_P -#set_property -dict {PACKAGE_PIN AE18 IOSTANDARD LVCMOS33} [get_ports fifo_rdy[10]] ; ## G18 FMC_LPC_LA16_P +#set_property -dict {PACKAGE_PIN AE18 IOSTANDARD LVCMOS33} [get_ports fifo_rdy[10]] ; ## G18 FMC_LPC_LA16_P +set_property -dict {PACKAGE_PIN AE16 IOSTANDARD LVCMOS25} [get_ports pmode[0]] ; ## D11 FMC_LPC_LA05_P +set_property -dict {PACKAGE_PIN AE15 IOSTANDARD LVCMOS25} [get_ports pmode[1]] ; ## D12 FMC_LPC_LA05_N diff --git a/projects/usb_fx3/zc706/system_project.tcl b/projects/usb_fx3/zc706/system_project.tcl index 8bfc00965..01174c14f 100644 --- a/projects/usb_fx3/zc706/system_project.tcl +++ b/projects/usb_fx3/zc706/system_project.tcl @@ -8,7 +8,7 @@ adi_project_files usb_fx3_zc706 [list \ "system_top.v" \ "system_constr.xdc" \ "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" \ - "$ad_hdl_dir/library/common/ad_iobuf.v"] + "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v"] adi_project_run usb_fx3_zc706 diff --git a/projects/usb_fx3/zc706/system_top.v b/projects/usb_fx3/zc706/system_top.v index d21458d0f..030872a4d 100644 --- a/projects/usb_fx3/zc706/system_top.v +++ b/projects/usb_fx3/zc706/system_top.v @@ -34,90 +34,64 @@ // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // *************************************************************************** // *************************************************************************** -// *************************************************************************** -// *************************************************************************** `timescale 1ns/100ps module system_top ( - ddr_addr, - ddr_ba, - ddr_cas_n, - ddr_ck_n, - ddr_ck_p, - ddr_cke, - ddr_cs_n, - ddr_dm, - ddr_dq, - ddr_dqs_n, - ddr_dqs_p, - ddr_odt, - ddr_ras_n, - ddr_reset_n, - ddr_we_n, + inout [14:0] ddr_addr, + inout [ 2:0] ddr_ba, + inout ddr_cas_n, + inout ddr_ck_n, + inout ddr_ck_p, + inout ddr_cke, + inout ddr_cs_n, + inout [ 3:0] ddr_dm, + inout [31:0] ddr_dq, + inout [ 3:0] ddr_dqs_n, + inout [ 3:0] ddr_dqs_p, + inout ddr_odt, + inout ddr_ras_n, + inout ddr_reset_n, + inout ddr_we_n, - fixed_io_ddr_vrn, - fixed_io_ddr_vrp, - fixed_io_mio, - fixed_io_ps_clk, - fixed_io_ps_porb, - fixed_io_ps_srstb, + inout fixed_io_ddr_vrn, + inout fixed_io_ddr_vrp, + inout [53:0] fixed_io_mio, + inout fixed_io_ps_clk, + inout fixed_io_ps_porb, + inout fixed_io_ps_srstb, - gpio_bd, + inout [14:0] gpio_bd, - usb_fx3_uart_tx, - usb_fx3_uart_rx, + input usb_fx3_uart_tx, + output usb_fx3_uart_rx, - hdmi_out_clk, - hdmi_vsync, - hdmi_hsync, - hdmi_data_e, - hdmi_data, + input [ 3:0] fifo_rdy, - spdif, + inout [31:0] data, + output [1:0] addr, + output pclk, + output slcs_n, + output slrd_n, + output sloe_n, + output slwr_n, + output pktend_n, - iic_scl, - iic_sda); + output [ 1:0] pmode, - inout [14:0] ddr_addr; - inout [ 2:0] ddr_ba; - inout ddr_cas_n; - inout ddr_ck_n; - inout ddr_ck_p; - inout ddr_cke; - inout ddr_cs_n; - inout [ 3:0] ddr_dm; - inout [31:0] ddr_dq; - inout [ 3:0] ddr_dqs_n; - inout [ 3:0] ddr_dqs_p; - inout ddr_odt; - inout ddr_ras_n; - inout ddr_reset_n; - inout ddr_we_n; + output hdmi_out_clk, + output hdmi_vsync, + output hdmi_hsync, + output hdmi_data_e, + output [23:0] hdmi_data, - inout fixed_io_ddr_vrn; - inout fixed_io_ddr_vrp; - inout [53:0] fixed_io_mio; - inout fixed_io_ps_clk; - inout fixed_io_ps_porb; - inout fixed_io_ps_srstb; + output spdif, - inout [14:0] gpio_bd; + inout iic_scl, + inout iic_sda - input usb_fx3_uart_tx; - output usb_fx3_uart_rx; - - output hdmi_out_clk; - output hdmi_vsync; - output hdmi_hsync; - output hdmi_data_e; - output [23:0] hdmi_data; - - output spdif; - - inout iic_scl; - inout iic_sda; +); // internal signals @@ -125,20 +99,8 @@ module system_top ( wire [63:0] gpio_o; wire [63:0] gpio_t; - wire usb_fx3_uart_tx; - wire usb_fx3_uart_rx; - wire dma_rdy; - wire dma_wmk; - wire [10:0] fifo_rdy; - wire pclk; - wire [31:0] data; - wire [4:0] addr; - wire slcs_n; - wire slrd_n; - wire sloe_n; - wire slwr_n; - wire epswitch_n; - wire pktend_n; + + assign pmode = 2'b11; // instantiations @@ -194,7 +156,7 @@ module system_top ( .slrd_n(slrd_n), .sloe_n(sloe_n), .slwr_n(slwr_n), - .epswitch_n(epswitch_n), + // .epswitch_n(epswitch_n), .pktend_n(pktend_n), .ps_intr_00 (1'b0), .ps_intr_01 (1'b0), @@ -205,8 +167,6 @@ module system_top ( .ps_intr_06 (1'b0), .ps_intr_07 (1'b0), .ps_intr_08 (1'b0), - .ps_intr_09 (1'b0), - .ps_intr_10 (1'b0), .spdif (spdif)); endmodule diff --git a/projects/usdrx1/a5gt/Makefile b/projects/usdrx1/a5gt/Makefile index d461204bb..24970af39 100644 --- a/projects/usdrx1/a5gt/Makefile +++ b/projects/usdrx1/a5gt/Makefile @@ -5,13 +5,80 @@ #################################################################################### #################################################################################### +ifeq ($(MMU),) + MMU := 1 +endif + +export ALT_NIOS_MMU_ENABLED := $(MMU) + +M_DEPS += system_top.v +M_DEPS += system_qsys.tcl M_DEPS += system_project.tcl +M_DEPS += system_constr.sdc M_DEPS += ../common/usdrx1_spi.v +M_DEPS += ../common/usdrx1_qsys.tcl +M_DEPS += ../../scripts/adi_tquest.tcl M_DEPS += ../../scripts/adi_env.tcl -M_DEPS += ../../common/a5gt/a5gt_system_bd.qsys +M_DEPS += ../../common/altera/sys_gen.tcl +M_DEPS += ../../common/a5gt/a5gt_system_qsys.tcl M_DEPS += ../../common/a5gt/a5gt_system_assign.tcl -M_DEPS += ../../../library/common/altera/ad_xcvr_rx_rst.v -M_DEPS += ../../../library/common/altera/ad_jesd_align.v +M_DEPS += ../../../library/common/ad_sysref_gen.v +M_DEPS += ../../../library/altera/avl_adxcvr/avl_adxcvr_hw.tcl +M_DEPS += ../../../library/altera/axi_adxcvr/axi_adxcvr.v +M_DEPS += ../../../library/altera/axi_adxcvr/axi_adxcvr_hw.tcl +M_DEPS += ../../../library/altera/axi_adxcvr/axi_adxcvr_up.v +M_DEPS += ../../../library/axi_ad9671/axi_ad9671.v +M_DEPS += ../../../library/axi_ad9671/axi_ad9671_channel.v +M_DEPS += ../../../library/axi_ad9671/axi_ad9671_hw.tcl +M_DEPS += ../../../library/axi_ad9671/axi_ad9671_if.v +M_DEPS += ../../../library/axi_ad9671/axi_ad9671_pnmon.v +M_DEPS += ../../../library/axi_dmac/2d_transfer.v +M_DEPS += ../../../library/axi_dmac/address_generator.v +M_DEPS += ../../../library/axi_dmac/axi_dmac.v +M_DEPS += ../../../library/axi_dmac/axi_dmac_constr.sdc +M_DEPS += ../../../library/axi_dmac/axi_dmac_hw.tcl +M_DEPS += ../../../library/axi_dmac/axi_register_slice.v +M_DEPS += ../../../library/axi_dmac/data_mover.v +M_DEPS += ../../../library/axi_dmac/dest_axi_mm.v +M_DEPS += ../../../library/axi_dmac/dest_axi_stream.v +M_DEPS += ../../../library/axi_dmac/dest_fifo_inf.v +M_DEPS += ../../../library/axi_dmac/inc_id.h +M_DEPS += ../../../library/axi_dmac/request_arb.v +M_DEPS += ../../../library/axi_dmac/request_generator.v +M_DEPS += ../../../library/axi_dmac/resp.h +M_DEPS += ../../../library/axi_dmac/response_generator.v +M_DEPS += ../../../library/axi_dmac/response_handler.v +M_DEPS += ../../../library/axi_dmac/splitter.v +M_DEPS += ../../../library/axi_dmac/src_axi_mm.v +M_DEPS += ../../../library/axi_dmac/src_axi_stream.v +M_DEPS += ../../../library/axi_dmac/src_fifo_inf.v +M_DEPS += ../../../library/common/ad_axi_ip_constr.sdc +M_DEPS += ../../../library/common/ad_axis_inf_rx.v +M_DEPS += ../../../library/common/ad_datafmt.v +M_DEPS += ../../../library/common/ad_mem.v +M_DEPS += ../../../library/common/ad_mem_asym.v +M_DEPS += ../../../library/common/ad_pnmon.v +M_DEPS += ../../../library/common/ad_rst.v +M_DEPS += ../../../library/common/ad_xcvr_rx_if.v +M_DEPS += ../../../library/common/sync_bits.v +M_DEPS += ../../../library/common/sync_gray.v +M_DEPS += ../../../library/common/up_adc_channel.v +M_DEPS += ../../../library/common/up_adc_common.v +M_DEPS += ../../../library/common/up_axi.v +M_DEPS += ../../../library/common/up_clock_mon.v +M_DEPS += ../../../library/common/up_delay_cntrl.v +M_DEPS += ../../../library/common/up_xfer_cntrl.v +M_DEPS += ../../../library/common/up_xfer_status.v +M_DEPS += ../../../library/scripts/adi_env.tcl +M_DEPS += ../../../library/scripts/adi_ip_alt.tcl +M_DEPS += ../../../library/util_adcfifo/util_adcfifo.v +M_DEPS += ../../../library/util_adcfifo/util_adcfifo_constr.sdc +M_DEPS += ../../../library/util_adcfifo/util_adcfifo_hw.tcl +M_DEPS += ../../../library/util_axis_fifo/address_gray.v +M_DEPS += ../../../library/util_axis_fifo/address_gray_pipelined.v +M_DEPS += ../../../library/util_axis_fifo/address_sync.v +M_DEPS += ../../../library/util_axis_fifo/util_axis_fifo.v +M_DEPS += ../../../library/util_axis_resize/util_axis_resize.v M_ALTERA := quartus_sh --64bit -t @@ -44,6 +111,8 @@ M_FLIST += reconfig_mif M_FLIST += *.sopcinfo M_FLIST += *.jdi M_FLIST += *.pin +M_FLIST += *_summary.csv +M_FLIST += *.dpf @@ -60,7 +129,7 @@ clean-all: usdrx1_a5gt.sof: $(M_DEPS) - rm -rf $(M_FLIST) + -rm -rf $(M_FLIST) $(M_ALTERA) system_project.tcl >> usdrx1_a5gt_quartus.log 2>&1 #################################################################################### diff --git a/projects/usdrx1/a5gt/system_bd.qsys b/projects/usdrx1/a5gt/system_bd.qsys deleted file mode 100644 index bc08c08f3..000000000 --- a/projects/usdrx1/a5gt/system_bd.qsys +++ /dev/null @@ -1,2844 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - sys_cpu.jtag_debug_module - - - - - - - - - - - - - ]]> - - - - - - - - - - - - - - - - - - - - - - ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 1 HARDCOPY 0 HAS_18_BIT_MULTS 1 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 1 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 1 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 1 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 0 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 1 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 0 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 1 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 0 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LVDS_IO 1 M10K_MEMORY 1 M144K_MEMORY 1 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 1 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 1 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 1 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 1 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 1 TRANSCEIVER_6G_BLOCK 1 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 1 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1 - - - - - - - - - - - - - - - - - ]]> - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ]]> - - - - - - - - ]]> - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - $${FILENAME}_sys_ethernet_desc_mem - - - - - ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 1 HARDCOPY 0 HAS_18_BIT_MULTS 1 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 1 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 1 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 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Switchover - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Create an adjpllin signal to connect with an upstream PLL - - - - - - - - - - - - - - - - - - - - - - - - Automatic Switchover - - - - - - - - - - - - - - - - - - - - - $${FILENAME}_sys_tcm_mem - - - - - ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 1 HARDCOPY 0 HAS_18_BIT_MULTS 1 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 1 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 1 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 1 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 0 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 1 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 0 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 1 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 0 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LVDS_IO 1 M10K_MEMORY 1 M144K_MEMORY 1 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 1 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 1 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 1 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 1 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 1 TRANSCEIVER_6G_BLOCK 1 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 1 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - NO_INTERACTIVE_WINDOWS - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/projects/usdrx1/a5gt/system_constr.sdc b/projects/usdrx1/a5gt/system_constr.sdc index 578df95d7..d8320bcbf 100644 --- a/projects/usdrx1/a5gt/system_constr.sdc +++ b/projects/usdrx1/a5gt/system_constr.sdc @@ -1,29 +1,27 @@ -create_clock -period "8.000 ns" -name n_eth_rx_clk_125m [get_ports {eth_rx_clk}] -create_clock -period "8.000 ns" -name n_eth_tx_clk_125m [get_ports {eth_tx_clk_out}] -create_clock -period "10.000 ns" -name n_clk_100m [get_ports {sys_clk}] -create_clock -period "12.500 ns" -name n_clk_80m [get_ports {ref_clk}] +create_clock -period "10.000 ns" -name sys_clk [get_ports {sys_clk}] +create_clock -period "12.500 ns" -name ref_clk [get_ports {ref_clk}] +create_clock -period "8.000 ns" -name eth_rx_clk [get_ports {eth_rx_clk}] derive_pll_clocks derive_clock_uncertainty -set clk_100m {i_system_bd|sys_pll|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk} -set clk_166m {i_system_bd|sys_pll|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk} -set clk_125m {i_system_bd|sys_pll|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk} -set clk_25m {i_system_bd|sys_pll|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk} -set clk_2m5 {i_system_bd|sys_pll|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk} -set clk_rxlink {i_system_bd|sys_jesd204b_s1_pll|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk} +set_clock_groups -exclusive \ + -group [get_clocks {i_system_bd|sys_pll|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] \ + -group [get_clocks {i_system_bd|sys_pll|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] \ + -group [get_clocks {i_system_bd|sys_pll|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk}] -set_clock_groups -asynchronous -group [get_clocks {n_clk_80m} ] -set_clock_groups -asynchronous -group [get_clocks {n_clk_100m} ] -set_clock_groups -asynchronous -group [get_clocks {n_eth_rx_clk_125m} ] -set_clock_groups -asynchronous -group [get_clocks {n_eth_tx_clk_125m} ] -set_clock_groups -asynchronous -group [get_clocks $clk_100m ] -set_clock_groups -asynchronous -group [get_clocks $clk_166m ] -set_clock_groups -asynchronous -group [get_clocks $clk_125m ] -set_clock_groups -asynchronous -group [get_clocks $clk_25m ] -set_clock_groups -asynchronous -group [get_clocks $clk_2m5 ] -set_clock_groups -asynchronous -group [get_clocks $clk_rxlink ] +set_false_path -to [get_registers *sysref_en_m1*] + +set_false_path -from [get_clocks {i_system_bd|sys_ddr3_cntrl|pll0|pll6~PLL_OUTPUT_COUNTER|divclk}] -through [get_nets *altera_jesd204_rx_ctl_inst*] \ + -to [get_clocks {i_system_bd|avl_usdrx1_xcvr|alt_core_pll|altera_pll_i|arriav_pll|counter[0].output_counter|divclk}] + +set_false_path -from [get_clocks {i_system_bd|avl_usdrx1_xcvr|alt_core_pll|altera_pll_i|arriav_pll|counter[0].output_counter|divclk}] \ + -through [get_nets *altera_jesd204_rx_ctl_inst*] -to [get_clocks {i_system_bd|sys_ddr3_cntrl|pll0|pll6~PLL_OUTPUT_COUNTER|divclk}] + +set_false_path -from [get_clocks {i_system_bd|sys_ddr3_cntrl|pll0|pll6~PLL_OUTPUT_COUNTER|divclk}] -through [get_nets *altera_jesd204_rx_csr_inst*] \ + -to [get_clocks {i_system_bd|avl_usdrx1_xcvr|alt_core_pll|altera_pll_i|arriav_pll|counter[0].output_counter|divclk}] + +set_false_path -from [get_clocks {i_system_bd|avl_usdrx1_xcvr|alt_core_pll|altera_pll_i|arriav_pll|counter[0].output_counter|divclk}] \ + -through [get_nets *altera_jesd204_rx_csr_inst*] -to [get_clocks {i_system_bd|sys_ddr3_cntrl|pll0|pll6~PLL_OUTPUT_COUNTER|divclk}] -set_false_path -from {sys_resetn} -to * -set_false_path -from * -to {sys_resetn} diff --git a/projects/usdrx1/a5gt/system_project.tcl b/projects/usdrx1/a5gt/system_project.tcl index 8bf4232aa..369f2e733 100644 --- a/projects/usdrx1/a5gt/system_project.tcl +++ b/projects/usdrx1/a5gt/system_project.tcl @@ -4,11 +4,15 @@ load_package flow source ../../scripts/adi_env.tcl project_new usdrx1_a5gt -overwrite -source $ad_hdl_dir/projects/common/a5gt/a5gt_system_assign.tcl +source "../../common/a5gt/a5gt_system_assign.tcl" -set_global_assignment -name VERILOG_FILE $ad_hdl_dir/library/common/altera/ad_jesd_align.v -set_global_assignment -name VERILOG_FILE $ad_hdl_dir/library/common/altera/ad_xcvr_rx_rst.v set_global_assignment -name VERILOG_FILE ../common/usdrx1_spi.v +set_global_assignment -name VERILOG_FILE ../../../library/common/ad_sysref_gen.v +set_global_assignment -name VERILOG_FILE system_top.v +set_global_assignment -name QSYS_FILE system_bd.qsys + +set_global_assignment -name SDC_FILE system_constr.sdc +set_global_assignment -name TOP_LEVEL_ENTITY system_top # reference clock @@ -163,5 +167,11 @@ set_instance_assignment -name IO_STANDARD "2.5 V" -to dac_data[11] set_instance_assignment -name IO_STANDARD "2.5 V" -to dac_data[12] set_instance_assignment -name IO_STANDARD "2.5 V" -to dac_data[13] +# disable auto-pack + +set_global_assignment -name OPTIMIZATION_MODE "AGGRESSIVE PERFORMANCE" +set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF +set_global_assignment -name QII_AUTO_PACKED_REGISTERS OFF + execute_flow -compile diff --git a/projects/usdrx1/a5gt/system_qsys.tcl b/projects/usdrx1/a5gt/system_qsys.tcl new file mode 100644 index 000000000..cf7c6ae15 --- /dev/null +++ b/projects/usdrx1/a5gt/system_qsys.tcl @@ -0,0 +1,5 @@ + +source $ad_hdl_dir/projects/common/a5gt/a5gt_system_qsys.tcl +source ../common/usdrx1_qsys.tcl + + diff --git a/projects/usdrx1/a5gt/system_top.v b/projects/usdrx1/a5gt/system_top.v index 31298ec5c..99797bf10 100644 --- a/projects/usdrx1/a5gt/system_top.v +++ b/projects/usdrx1/a5gt/system_top.v @@ -41,265 +41,206 @@ module system_top ( // clock and resets - sys_clk, - sys_resetn, + input sys_clk, + input sys_resetn, // ddr3 - ddr3_a, - ddr3_ba, - ddr3_clk_p, - ddr3_clk_n, - ddr3_cke, - ddr3_cs_n, - ddr3_dm, - ddr3_ras_n, - ddr3_cas_n, - ddr3_we_n, - ddr3_reset_n, - ddr3_dq, - ddr3_dqs_p, - ddr3_dqs_n, - ddr3_odt, - ddr3_rzq, + output ddr3_clk_p, + output ddr3_clk_n, + output [ 13:0] ddr3_a, + output [ 2:0] ddr3_ba, + output ddr3_cke, + output ddr3_cs_n, + output ddr3_odt, + output ddr3_reset_n, + output ddr3_we_n, + output ddr3_ras_n, + output ddr3_cas_n, + inout [ 7:0] ddr3_dqs_p, + inout [ 7:0] ddr3_dqs_n, + inout [ 63:0] ddr3_dq, + output [ 7:0] ddr3_dm, + input ddr3_rzq, // ethernet - eth_rx_clk, - eth_rx_data, - eth_rx_cntrl, - eth_tx_clk_out, - eth_tx_data, - eth_tx_cntrl, - eth_mdc, - eth_mdio_i, - eth_mdio_o, - eth_mdio_t, - eth_phy_resetn, - // board gpio - - led_grn, - led_red, - push_buttons, - dip_switches, - - // lane interface - - ref_clk, - rx_data, - rx_sync, - rx_sysref, - - // spi - - spi_fout_enb_clk, - spi_fout_enb_mlo, - spi_fout_enb_rst, - spi_fout_enb_sync, - spi_fout_enb_sysref, - spi_fout_enb_trig, - spi_fout_clk, - spi_fout_sdio, - spi_afe_csn, - spi_afe_clk, - spi_afe_sdio, - spi_clk_csn, - spi_clk_clk, - spi_clk_sdio, - - afe_rst, - afe_trig, - - // gpio - - dac_sleep, - dac_data, - afe_pdn, - afe_stby, - clk_resetn, - clk_syncn, - clk_status, - amp_disbn, - prc_sck, - prc_cnv, - prc_sdo_i, - prc_sdo_q); - - // clock and resets - - input sys_clk; - input sys_resetn; - - // ddr3 - - output [ 13:0] ddr3_a; - output [ 2:0] ddr3_ba; - output ddr3_clk_p; - output ddr3_clk_n; - output ddr3_cke; - output ddr3_cs_n; - output [ 7:0] ddr3_dm; - output ddr3_ras_n; - output ddr3_cas_n; - output ddr3_we_n; - output ddr3_reset_n; - inout [ 63:0] ddr3_dq; - inout [ 7:0] ddr3_dqs_p; - inout [ 7:0] ddr3_dqs_n; - output ddr3_odt; - input ddr3_rzq; - - // ethernet - - input eth_rx_clk; - input [ 3:0] eth_rx_data; - input eth_rx_cntrl; - output eth_tx_clk_out; - output [ 3:0] eth_tx_data; - output eth_tx_cntrl; - output eth_mdc; - input eth_mdio_i; - output eth_mdio_o; - output eth_mdio_t; - output eth_phy_resetn; + input eth_rx_clk, + input [ 3:0] eth_rx_data, + input eth_rx_cntrl, + output eth_tx_clk_out, + output [ 3:0] eth_tx_data, + output eth_tx_cntrl, + output eth_mdc, + input eth_mdio_i, + output eth_mdio_o, + output eth_mdio_t, + output eth_phy_resetn, // board gpio - output [ 7:0] led_grn; - output [ 7:0] led_red; - input [ 2:0] push_buttons; - input [ 7:0] dip_switches; + output [ 15:0] gpio_bd_o, + input [ 10:0] gpio_bd_i, // lane interface - input ref_clk; - input [ 7:0] rx_data; - output rx_sysref; - output rx_sync; + input ref_clk, + input [ 7:0] rx_data, + output rx_sync, + output rx_sysref, // spi - output spi_fout_enb_clk; - output spi_fout_enb_mlo; - output spi_fout_enb_rst; - output spi_fout_enb_sync; - output spi_fout_enb_sysref; - output spi_fout_enb_trig; - output spi_fout_clk; - output spi_fout_sdio; - output [ 3:0] spi_afe_csn; - output spi_afe_clk; - inout spi_afe_sdio; - output spi_clk_csn; - output spi_clk_clk; - inout spi_clk_sdio; - - output afe_rst; - output afe_trig; + output spi_fout_enb_clk, + output spi_fout_enb_mlo, + output spi_fout_enb_rst, + output spi_fout_enb_sync, + output spi_fout_enb_sysref, + output spi_fout_enb_trig, + output spi_fout_clk, + output spi_fout_sdio, + output [ 3:0] spi_afe_csn, + output spi_afe_clk, + inout spi_afe_sdio, + output spi_clk_csn, + output spi_clk_clk, + inout spi_clk_sdio, // gpio - output dac_sleep; - output [ 13:0] dac_data; - output afe_pdn; - output afe_stby; - output clk_resetn; - output clk_syncn; - input clk_status; - output amp_disbn; - inout prc_sck; - inout prc_cnv; - inout prc_sdo_i; - inout prc_sdo_q; + output clk_resetn, + output clk_syncn, + input clk_status, + output afe_rst, + output afe_trig, + output afe_pdn, + output afe_stby, + output [ 13:0] dac_data, + output dac_sleep, + output amp_disbn, + output prc_sck, + output prc_cnv, + input prc_sdo_i, + input prc_sdo_q); // internal registers - reg rx_sysref_m1 = 'd0; - reg rx_sysref_m2 = 'd0; - reg rx_sysref_m3 = 'd0; - reg rx_sysref = 'd0; - reg dma_sync = 'd0; - reg dma_wr = 'd0; - reg adc_dovf; - reg [511:0] dma_data = 'd0; - reg rx_sof_0_s = 'd0; - reg rx_sof_1_s = 'd0; - reg rx_sof_2_s = 'd0; - reg rx_sof_3_s = 'd0; reg [ 3:0] phy_rst_cnt = 0; reg phy_rst_reg = 0; - // internal clocks and resets + // internal signals wire sys_125m_clk; wire sys_25m_clk; wire sys_2m5_clk; + wire sys_cpu_clk; + wire sys_cpu_mem_resetn; + wire sys_cpu_resetn; + wire sys_pll_locked; wire eth_tx_clk; + wire eth_tx_mode_1g; + wire eth_tx_mode_10m_100m_n; wire rx_clk; - wire adc_clk; - - // internal signals - - wire sys_pll_locked_s; - wire eth_tx_reset_s; - wire eth_tx_mode_1g_s; - wire eth_tx_mode_10m_100m_n_s; - wire [ 4:0] spi_csn; + wire [ 31:0] rx_ch_wr; + wire [511:0] rx_ch_wdata; + wire rx_ch_wovf; + wire rx_ch_sync; + wire [ 3:0] rx_ch_raddr; + wire [ 3:0] rx_ip_sof; + wire [255:0] rx_ip_data; + wire [ 7:0] spi_csn_s; wire spi_clk; wire spi_mosi; wire spi_miso; - wire rx_ref_clk; - wire rx_sync; - wire [127:0] adc_data_0; - wire [127:0] adc_data_1; - wire [127:0] adc_data_2; - wire [127:0] adc_data_3; - wire adc_valid; - wire [ 7:0] adc_valid_0; - wire [ 7:0] adc_valid_1; - wire [ 7:0] adc_valid_2; - wire [ 7:0] adc_valid_3; - wire [ 7:0] adc_enable_0; - wire [ 7:0] adc_enable_1; - wire [ 7:0] adc_enable_2; - wire [ 7:0] adc_enable_3; - wire adc_dovf_0; - wire adc_dovf_1; - wire adc_dovf_2; - wire adc_dovf_3; - wire [ 3:0] rx_ip_sof_s; - wire [255:0] rx_ip_data_s; - wire [255:0] rx_data_s; - wire rx_sw_rstn_s; - wire rx_sysref_s; - wire rx_err_s; - wire rx_ready_s; - wire [ 3:0] rx_rst_state_s; - wire rx_lane_aligned_s; - wire [ 7:0] rx_analog_reset_s; - wire [ 7:0] rx_digital_reset_s; - wire [ 7:0] rx_cdr_locked_s; - wire [ 7:0] rx_cal_busy_s; - wire rx_pll_locked_s; - wire [ 22:0] rx_xcvr_status_s; - wire [ 7:0] rx_sof; - wire [ 3:0] sync_raddr; - wire sync_signal; + wire [ 63:0] gpio_i; + wire [ 63:0] gpio_o; + + // sys reset + + assign sys_cpu_resetn = sys_resetn & sys_cpu_mem_resetn & sys_pll_locked; // ethernet transmit clock - assign eth_tx_clk = (eth_tx_mode_1g_s == 1'b1) ? sys_125m_clk : - (eth_tx_mode_10m_100m_n_s == 1'b0) ? sys_25m_clk : sys_2m5_clk; + assign eth_tx_clk = (eth_tx_mode_1g == 1'b1) ? sys_125m_clk : + (eth_tx_mode_10m_100m_n == 1'b0) ? sys_25m_clk : sys_2m5_clk; assign eth_phy_resetn = phy_rst_reg; always@ (posedge eth_mdc) begin phy_rst_cnt <= phy_rst_cnt + 4'd1; if (phy_rst_cnt == 4'h0) begin - phy_rst_reg <= sys_pll_locked_s; + phy_rst_reg <= sys_pll_locked; end end + // gpio + + assign gpio_i[63:57] = gpio_o[63:57]; + assign amp_disbn = gpio_o[56]; + + assign gpio_i[55:40] = gpio_o[55:40]; + assign dac_sleep = gpio_o[54]; + assign dac_data = gpio_o[53:40]; + + assign gpio_i[39:36] = gpio_o[39:36]; + assign afe_stby = gpio_o[39]; + assign afe_pdn = gpio_o[38]; + assign afe_trig = gpio_o[37]; + assign afe_rst = gpio_o[36]; + + assign gpio_i[35:35] = clk_status; + assign gpio_i[34:32] = gpio_o[34:32]; + assign clk_sync = gpio_o[34]; + assign clk_resetn = gpio_o[33]; + + // gpio (bd) + + assign gpio_i[31:11] = gpio_o[31:11]; + assign gpio_i[10: 0] = gpio_bd_i; + + assign gpio_bd_o = gpio_o[26:11]; + + // sysref + + ad_sysref_gen i_sysref ( + .core_clk (rx_clk), + .sysref_en (gpio_o[60]), + .sysref_out (rx_sysref)); + + // spi (fanout buffers) + + assign spi_fout_enb_clk = 1'b0; + assign spi_fout_enb_mlo = 1'b0; + assign spi_fout_enb_rst = 1'b0; + assign spi_fout_enb_sync = 1'b0; + assign spi_fout_enb_sysref = 1'b0; + assign spi_fout_enb_trig = 1'b0; + assign spi_fout_clk = 1'b0; + assign spi_fout_sdio = 1'b0; + + // spi (adc) + + assign prc_sck = 1'b0; + assign prc_cnv = 1'b0; + + // spi (main) + + assign spi_afe_csn = spi_csn_s[ 4: 1]; + assign spi_clk_csn = spi_csn_s[ 0: 0]; + assign spi_afe_clk = spi_clk; + assign spi_clk_clk = spi_clk; + + // instantiations + + usdrx1_spi i_spi ( + .spi_afe_csn (spi_csn_s[4:1]), + .spi_clk_csn (spi_csn_s[0]), + .spi_clk (spi_clk), + .spi_mosi (spi_mosi), + .spi_miso (spi_miso), + .spi_afe_sdio (spi_afe_sdio), + .spi_clk_sdio (spi_clk_sdio)); + altddio_out #(.width(1)) i_eth_tx_clk_out ( .aset (1'b0), .sset (1'b0), @@ -309,231 +250,130 @@ module system_top ( .datain_h (1'b1), .datain_l (1'b0), .outclocken (1'b1), - .aclr (eth_tx_reset_s), + .aclr (~sys_pll_locked), .outclock (eth_tx_clk), .dataout (eth_tx_clk_out)); - assign eth_tx_reset_s = ~sys_pll_locked_s; - - always @(posedge adc_clk) begin - dma_sync <= 1'b1; - dma_wr <= (|adc_enable_0)| (| adc_enable_1) | (|adc_enable_2) | (|adc_enable_3); - dma_data <= {adc_data_3, adc_data_2, adc_data_1, adc_data_0}; - adc_dovf <= adc_dovf_3 | adc_dovf_2 | adc_dovf_1 | adc_dovf_0; - end - - always @(posedge rx_clk) begin - rx_sysref_m1 <= rx_sysref_s; - rx_sysref_m2 <= rx_sysref_m1; - rx_sysref_m3 <= rx_sysref_m2; - rx_sysref <= rx_sysref_m2 & ~rx_sysref_m3; - end - - sld_signaltap #( - .sld_advanced_trigger_entity ("basic,1,"), - .sld_data_bits (514), - .sld_data_bit_cntr_bits (8), - .sld_enable_advanced_trigger (0), - .sld_mem_address_bits (10), - .sld_node_crc_bits (32), - .sld_node_crc_hiword (10311), - .sld_node_crc_loword (14297), - .sld_node_info (1076736), - .sld_ram_block_type ("AUTO"), - .sld_sample_depth (1024), - .sld_storage_qualifier_gap_record (0), - .sld_storage_qualifier_mode ("OFF"), - .sld_trigger_bits (2), - .sld_trigger_in_enabled (0), - .sld_trigger_level (1), - .sld_trigger_level_pipeline (1)) - i_signaltap ( - .acq_clk (adc_clk), - .acq_data_in ({rx_sysref, rx_sync, dma_data}), - .acq_trigger_in ({rx_sysref, rx_sync})); - - genvar n; - generate - for (n = 0; n < 8; n = n + 1) begin: g_align_1 - ad_jesd_align i_jesd_align ( - .rx_clk (rx_clk), - .rx_ip_sof (rx_ip_sof_s), - .rx_ip_data (rx_ip_data_s[n*32+31:n*32]), - .rx_sof (rx_sof[n]), - .rx_data (rx_data_s[n*32+31:n*32])); - end - endgenerate - - assign rx_xcvr_status_s[22:22] = rx_sync; - assign rx_xcvr_status_s[21:21] = rx_ready_s; - assign rx_xcvr_status_s[20:20] = rx_pll_locked_s; - assign rx_xcvr_status_s[19:16] = rx_rst_state_s; - assign rx_xcvr_status_s[15: 8] = rx_cdr_locked_s; - assign rx_xcvr_status_s[ 7: 0] = rx_cal_busy_s; - - ad_xcvr_rx_rst #(.NUM_OF_LANES (8)) i_xcvr_rx_rst ( - .rx_clk (rx_clk), - .rx_rstn (sys_resetn), - .rx_sw_rstn (rx_sw_rstn_s), - .rx_pll_locked (rx_pll_locked_s), - .rx_cal_busy (rx_cal_busy_s), - .rx_cdr_locked (rx_cdr_locked_s), - .rx_analog_reset (rx_analog_reset_s), - .rx_digital_reset (rx_digital_reset_s), - .rx_ready (rx_ready_s), - .rx_rst_state (rx_rst_state_s)); - - assign spi_fout_enb_clk = 1'b0; - assign spi_fout_enb_mlo = 1'b0; - assign spi_fout_enb_rst = 1'b0; - assign spi_fout_enb_sync = 1'b0; - assign spi_fout_enb_sysref = 1'b0; - assign spi_fout_enb_trig = 1'b0; - assign spi_fout_clk = 1'b0; - assign spi_fout_sdio = 1'b0; - assign spi_afe_csn = spi_csn[ 4: 1]; - assign spi_clk_csn = spi_csn[ 0: 0]; - assign spi_afe_clk = spi_clk; - assign spi_clk_clk = spi_clk; - - always @(posedge rx_clk) - begin - rx_sof_0_s <= rx_sof[0] | rx_sof[1]; - rx_sof_1_s <= rx_sof[2] | rx_sof[3]; - rx_sof_2_s <= rx_sof[4] | rx_sof[5]; - rx_sof_3_s <= rx_sof[6] | rx_sof[7]; - end - - usdrx1_spi i_spi ( - .spi_afe_csn (spi_csn[4:1]), - .spi_clk_csn (spi_csn[0]), - .spi_clk (spi_clk), - .spi_mosi (spi_mosi), - .spi_miso (spi_miso), - .spi_afe_sdio (spi_afe_sdio), - .spi_clk_sdio (spi_clk_sdio)); - system_bd i_system_bd ( - .sys_clk_clk (sys_clk), - .sys_reset_reset_n (sys_resetn), + .rx_ch_wdata_data (rx_ch_wdata), + .rx_ch_wovf_ovf (rx_ch_wovf), + .rx_ch_wr_valid (&rx_ch_wr), + .rx_core_ch_0_enable (), + .rx_core_ch_0_valid (rx_ch_wr[7:0]), + .rx_core_ch_0_data (rx_ch_wdata[127:0]), + .rx_core_ch_1_enable (), + .rx_core_ch_1_valid (rx_ch_wr[15:8]), + .rx_core_ch_1_data (rx_ch_wdata[255:128]), + .rx_core_ch_2_enable (), + .rx_core_ch_2_valid (rx_ch_wr[23:16]), + .rx_core_ch_2_data (rx_ch_wdata[383:256]), + .rx_core_ch_3_enable (), + .rx_core_ch_3_valid (rx_ch_wr[31:24]), + .rx_core_ch_3_data (rx_ch_wdata[511:384]), + .rx_core_clk_clk (rx_clk), + .rx_core_ovf_0_ovf (rx_ch_wovf), + .rx_core_ovf_1_ovf (rx_ch_wovf), + .rx_core_ovf_2_ovf (rx_ch_wovf), + .rx_core_ovf_3_ovf (rx_ch_wovf), + .rx_core_sync_0_sync_in (1'b0), + .rx_core_sync_0_sync_out (rx_ch_sync), + .rx_core_sync_0_raddr_in (4'd0), + .rx_core_sync_0_raddr_out (rx_ch_raddr), + .rx_core_sync_1_sync_in (rx_ch_sync), + .rx_core_sync_1_sync_out (), + .rx_core_sync_1_raddr_in (rx_ch_raddr), + .rx_core_sync_1_raddr_out (), + .rx_core_sync_2_sync_in (rx_ch_sync), + .rx_core_sync_2_sync_out (), + .rx_core_sync_2_raddr_in (rx_ch_raddr), + .rx_core_sync_2_raddr_out (), + .rx_core_sync_3_sync_in (rx_ch_sync), + .rx_core_sync_3_sync_out (), + .rx_core_sync_3_raddr_in (rx_ch_raddr), + .rx_core_sync_3_raddr_out (), + .rx_core_unf_0_unf (1'd0), + .rx_core_unf_1_unf (1'd0), + .rx_core_unf_2_unf (1'd0), + .rx_core_unf_3_unf (1'd0), + .rx_data_0_rx_serial_data (rx_data[0]), + .rx_data_1_rx_serial_data (rx_data[1]), + .rx_data_2_rx_serial_data (rx_data[2]), + .rx_data_3_rx_serial_data (rx_data[3]), + .rx_data_4_rx_serial_data (rx_data[4]), + .rx_data_5_rx_serial_data (rx_data[5]), + .rx_data_6_rx_serial_data (rx_data[6]), + .rx_data_7_rx_serial_data (rx_data[7]), + .rx_ip_data_data (rx_ip_data), + .rx_ip_data_valid (), + .rx_ip_data_ready (1'b1), + .rx_ip_data_0_data (rx_ip_data[63:0]), + .rx_ip_data_0_valid (1'b1), + .rx_ip_data_0_ready (), + .rx_ip_data_1_data (rx_ip_data[127:64]), + .rx_ip_data_1_valid (1'b1), + .rx_ip_data_1_ready (), + .rx_ip_data_2_data (rx_ip_data[191:128]), + .rx_ip_data_2_valid (1'b1), + .rx_ip_data_2_ready (), + .rx_ip_data_3_data (rx_ip_data[255:192]), + .rx_ip_data_3_valid (1'b1), + .rx_ip_data_3_ready (), + .rx_ip_sof_export (rx_ip_sof), + .rx_ip_sof_0_export (rx_ip_sof), + .rx_ip_sof_1_export (rx_ip_sof), + .rx_ip_sof_2_export (rx_ip_sof), + .rx_ip_sof_3_export (rx_ip_sof), + .rx_ref_clk_clk (ref_clk), + .rx_sync_export (rx_sync), + .rx_sysref_export (rx_sysref), .sys_125m_clk_clk (sys_125m_clk), .sys_25m_clk_clk (sys_25m_clk), .sys_2m5_clk_clk (sys_2m5_clk), - .sys_pll_locked_export (sys_pll_locked_s), - .sys_ddr3_phy_mem_a (ddr3_a), - .sys_ddr3_phy_mem_ba (ddr3_ba), - .sys_ddr3_phy_mem_ck (ddr3_clk_p), - .sys_ddr3_phy_mem_ck_n (ddr3_clk_n), - .sys_ddr3_phy_mem_cke (ddr3_cke), - .sys_ddr3_phy_mem_cs_n (ddr3_cs_n), - .sys_ddr3_phy_mem_dm (ddr3_dm), - .sys_ddr3_phy_mem_ras_n (ddr3_ras_n), - .sys_ddr3_phy_mem_cas_n (ddr3_cas_n), - .sys_ddr3_phy_mem_we_n (ddr3_we_n), - .sys_ddr3_phy_mem_reset_n (ddr3_reset_n), - .sys_ddr3_phy_mem_dq (ddr3_dq), - .sys_ddr3_phy_mem_dqs (ddr3_dqs_p), - .sys_ddr3_phy_mem_dqs_n (ddr3_dqs_n), - .sys_ddr3_phy_mem_odt (ddr3_odt), - .sys_ddr3_oct_rzqin (ddr3_rzq), - .sys_ethernet_tx_clk_clk (eth_tx_clk), - .sys_ethernet_rx_clk_clk (eth_rx_clk), - .sys_ethernet_status_set_10 (), - .sys_ethernet_status_set_1000 (), - .sys_ethernet_status_eth_mode (eth_tx_mode_1g_s), - .sys_ethernet_status_ena_10 (eth_tx_mode_10m_100m_n_s), - .sys_ethernet_rgmii_rgmii_in (eth_rx_data), - .sys_ethernet_rgmii_rgmii_out (eth_tx_data), - .sys_ethernet_rgmii_rx_control (eth_rx_cntrl), - .sys_ethernet_rgmii_tx_control (eth_tx_cntrl), + .sys_clk_clk (sys_cpu_clk), + .sys_cpu_clk_clk (sys_cpu_clk), + .sys_cpu_reset_reset_n (sys_cpu_mem_resetn), + .sys_ddr3_cntrl_mem_mem_a (ddr3_a), + .sys_ddr3_cntrl_mem_mem_ba (ddr3_ba), + .sys_ddr3_cntrl_mem_mem_ck (ddr3_clk_p), + .sys_ddr3_cntrl_mem_mem_ck_n (ddr3_clk_n), + .sys_ddr3_cntrl_mem_mem_cke (ddr3_cke), + .sys_ddr3_cntrl_mem_mem_cs_n (ddr3_cs_n), + .sys_ddr3_cntrl_mem_mem_dm (ddr3_dm), + .sys_ddr3_cntrl_mem_mem_ras_n (ddr3_ras_n), + .sys_ddr3_cntrl_mem_mem_cas_n (ddr3_cas_n), + .sys_ddr3_cntrl_mem_mem_we_n (ddr3_we_n), + .sys_ddr3_cntrl_mem_mem_reset_n (ddr3_reset_n), + .sys_ddr3_cntrl_mem_mem_dq (ddr3_dq), + .sys_ddr3_cntrl_mem_mem_dqs (ddr3_dqs_p), + .sys_ddr3_cntrl_mem_mem_dqs_n (ddr3_dqs_n), + .sys_ddr3_cntrl_mem_mem_odt (ddr3_odt), + .sys_ddr3_cntrl_oct_rzqin (ddr3_rzq), .sys_ethernet_mdio_mdc (eth_mdc), .sys_ethernet_mdio_mdio_in (eth_mdio_i), .sys_ethernet_mdio_mdio_out (eth_mdio_o), .sys_ethernet_mdio_mdio_oen (eth_mdio_t), - .sys_gpio_in_port ({25'h0, clk_status, 6'h0 }), - .sys_gpio_out_port ({3'h0, rx_sysref_s, - rx_sw_rstn_s, dac_data, dac_sleep, - 1'b0, 1'b0, 1'b0, 1'b0, - amp_disbn, 1'b0, clk_syncn, clk_resetn, - afe_stby, afe_pdn, afe_trig, afe_rst}), + .sys_ethernet_rgmii_rgmii_in (eth_rx_data), + .sys_ethernet_rgmii_rgmii_out (eth_tx_data), + .sys_ethernet_rgmii_rx_control (eth_rx_cntrl), + .sys_ethernet_rgmii_tx_control (eth_tx_cntrl), + .sys_ethernet_rx_clk_clk (eth_rx_clk), + .sys_ethernet_status_set_10 (), + .sys_ethernet_status_set_1000 (), + .sys_ethernet_status_eth_mode (eth_tx_mode_1g), + .sys_ethernet_status_ena_10 (eth_tx_mode_10m_100m_n), + .sys_ethernet_tx_clk_clk (eth_tx_clk), + .sys_gpio_bd_in_port (gpio_i[31:0]), + .sys_gpio_bd_out_port (gpio_o[31:0]), + .sys_gpio_in_export (gpio_i[63:32]), + .sys_gpio_out_export (gpio_o[63:32]), + .sys_pll_locked_export (sys_pll_locked), + .sys_ref_clk_clk (sys_clk), + .sys_ref_rst_reset_n (sys_resetn), + .sys_rst_reset_n (sys_cpu_resetn), .sys_spi_MISO (spi_miso), .sys_spi_MOSI (spi_mosi), .sys_spi_SCLK (spi_clk), - .sys_spi_SS_n (spi_csn), - .axi_dmac_if_fifo_wr_clk_clk (adc_clk), - .axi_dmac_if_fifo_wr_overflow_adc_dovf (adc_dovf), - .axi_dmac_if_fifo_wr_en_adc_valid (dma_wr), - .axi_dmac_if_fifo_wr_din_adc_data (dma_data), - .axi_dmac_if_fifo_wr_sync_adc_sync (dma_sync), - .sys_jesd204b_s1_rx_link_data (rx_ip_data_s), - .sys_jesd204b_s1_rx_link_valid (), - .sys_jesd204b_s1_rx_link_ready (1'b1), - .sys_jesd204b_s1_lane_aligned_all_export (rx_lane_aligned_s), - .sys_jesd204b_s1_sysref_export (rx_sysref), - .sys_jesd204b_s1_rx_ferr_export (rx_err_s), - .sys_jesd204b_s1_lane_aligned_export (rx_lane_aligned_s), - .sys_jesd204b_s1_sync_n_export (rx_sync), - .sys_jesd204b_s1_rx_sof_export (rx_ip_sof_s), - .sys_jesd204b_s1_rx_xcvr_data_rx_serial_data (rx_data), - .sys_jesd204b_s1_rx_analogreset_rx_analogreset (rx_analog_reset_s), - .sys_jesd204b_s1_rx_digitalreset_rx_digitalreset (rx_digital_reset_s), - .sys_jesd204b_s1_locked_rx_is_lockedtodata (rx_cdr_locked_s), - .sys_jesd204b_s1_rx_cal_busy_rx_cal_busy (rx_cal_busy_s), - .sys_jesd204b_s1_ref_clk_clk (ref_clk), - .sys_jesd204b_s1_rx_clk_clk (rx_clk), - .sys_jesd204b_s1_pll_locked_export (rx_pll_locked_s), - .axi_ad9671_0_xcvr_clk_clk (rx_clk), - .axi_ad9671_0_xcvr_data_data (rx_data_s[63:0]), - .axi_ad9671_0_xcvr_data_data_sof(rx_sof_0_s), - .axi_ad9671_0_adc_clock_clk (adc_clk), - .axi_ad9671_0_adc_dma_if_valid (adc_valid_0), - .axi_ad9671_0_adc_dma_if_enable (adc_enable_0), - .axi_ad9671_0_adc_dma_if_data (adc_data_0), - .axi_ad9671_0_adc_dma_if_dovf (adc_dovf_0), - .axi_ad9671_0_adc_dma_if_dunf (1'b0), - .axi_ad9671_1_xcvr_clk_clk (rx_clk), - .axi_ad9671_1_xcvr_data_data (rx_data_s[127:64]), - .axi_ad9671_1_xcvr_data_data_sof(rx_sof_1_s), - .axi_ad9671_1_adc_clock_clk (), - .axi_ad9671_1_adc_dma_if_valid (adc_valid_1), - .axi_ad9671_1_adc_dma_if_enable (adc_enable_1), - .axi_ad9671_1_adc_dma_if_data (adc_data_1), - .axi_ad9671_1_adc_dma_if_dovf (adc_dovf_1), - .axi_ad9671_1_adc_dma_if_dunf (1'b0), - .axi_ad9671_2_xcvr_clk_clk (rx_clk), - .axi_ad9671_2_xcvr_data_data (rx_data_s[191:128]), - .axi_ad9671_2_xcvr_data_data_sof(rx_sof_2_s), - .axi_ad9671_2_adc_clock_clk (), - .axi_ad9671_2_adc_dma_if_valid (adc_valid_2), - .axi_ad9671_2_adc_dma_if_enable (adc_enable_2), - .axi_ad9671_2_adc_dma_if_data (adc_data_2), - .axi_ad9671_2_adc_dma_if_dovf (adc_dovf_2), - .axi_ad9671_2_adc_dma_if_dunf (1'b0), - .axi_ad9671_3_xcvr_clk_clk (rx_clk), - .axi_ad9671_3_xcvr_data_data (rx_data_s[255:192]), - .axi_ad9671_3_xcvr_data_data_sof(rx_sof_3_s), - .axi_ad9671_3_adc_clock_clk (), - .axi_ad9671_3_adc_dma_if_valid (adc_valid_3), - .axi_ad9671_3_adc_dma_if_enable (adc_enable_3), - .axi_ad9671_3_adc_dma_if_data (adc_data_3), - .axi_ad9671_3_adc_dma_if_dovf (adc_dovf_3), - .axi_ad9671_3_adc_dma_if_dunf (1'b0), - .axi_ad9671_0_xcvr_sync_sync_in (), - .axi_ad9671_0_xcvr_sync_sync_out (sync_signal), - .axi_ad9671_0_xcvr_sync_raddr_in (), - .axi_ad9671_0_xcvr_sync_raddr_out (sync_raddr), - .axi_ad9671_1_xcvr_sync_sync_in (sync_signal), - .axi_ad9671_1_xcvr_sync_sync_out (), - .axi_ad9671_1_xcvr_sync_raddr_in (sync_raddr), - .axi_ad9671_1_xcvr_sync_raddr_out(), - .axi_ad9671_2_xcvr_sync_sync_in (sync_signal), - .axi_ad9671_2_xcvr_sync_sync_out (), - .axi_ad9671_2_xcvr_sync_raddr_in (sync_raddr), - .axi_ad9671_2_xcvr_sync_raddr_out (), - .axi_ad9671_3_xcvr_sync_sync_in (sync_signal), - .axi_ad9671_3_xcvr_sync_sync_out (), - .axi_ad9671_3_xcvr_sync_raddr_in (sync_raddr), - .axi_ad9671_3_xcvr_sync_raddr_out ()); + .sys_spi_SS_n (spi_csn_s)); endmodule diff --git a/projects/usdrx1/common/usdrx1_bd.tcl b/projects/usdrx1/common/usdrx1_bd.tcl index 4b9f89177..e742136c5 100644 --- a/projects/usdrx1/common/usdrx1_bd.tcl +++ b/projects/usdrx1/common/usdrx1_bd.tcl @@ -8,37 +8,7 @@ create_bd_port -dir O spi_clk_o create_bd_port -dir I spi_sdo_i create_bd_port -dir O spi_sdo_o create_bd_port -dir I spi_sdi_i - -create_bd_port -dir I rx_ref_clk -create_bd_port -dir O rx_sync -create_bd_port -dir O rx_sysref -create_bd_port -dir I -from 7 -to 0 rx_data_p -create_bd_port -dir I -from 7 -to 0 rx_data_n - -create_bd_port -dir O -from 255 -to 0 gt_rx_data -create_bd_port -dir I -from 63 -to 0 gt_rx_data_0 -create_bd_port -dir I -from 63 -to 0 gt_rx_data_1 -create_bd_port -dir I -from 63 -to 0 gt_rx_data_2 -create_bd_port -dir I -from 63 -to 0 gt_rx_data_3 -create_bd_port -dir O -from 127 -to 0 adc_data_0 -create_bd_port -dir O -from 127 -to 0 adc_data_1 -create_bd_port -dir O -from 127 -to 0 adc_data_2 -create_bd_port -dir O -from 127 -to 0 adc_data_3 -create_bd_port -dir O -from 7 -to 0 adc_valid_0 -create_bd_port -dir O -from 7 -to 0 adc_valid_1 -create_bd_port -dir O -from 7 -to 0 adc_valid_2 -create_bd_port -dir O -from 7 -to 0 adc_valid_3 -create_bd_port -dir O -from 7 -to 0 adc_enable_0 -create_bd_port -dir O -from 7 -to 0 adc_enable_1 -create_bd_port -dir O -from 7 -to 0 adc_enable_2 -create_bd_port -dir O -from 7 -to 0 adc_enable_3 -create_bd_port -dir I adc_dovf_0 -create_bd_port -dir I adc_dovf_1 -create_bd_port -dir I adc_dovf_2 -create_bd_port -dir I adc_dovf_3 -create_bd_port -dir I -from 511 -to 0 adc_data -create_bd_port -dir I adc_wr_en -create_bd_port -dir O adc_dovf +create_bd_port -dir O rx_core_clk # adc peripherals @@ -58,82 +28,26 @@ set axi_ad9671_core_3 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9671: set_property -dict [list CONFIG.QUAD_OR_DUAL_N {0}] $axi_ad9671_core_3 set_property -dict [list CONFIG.ID {3}] $axi_ad9671_core_3 -set axi_usdrx1_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.2 axi_usdrx1_jesd] +set axi_usdrx1_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:7.0 axi_usdrx1_jesd] set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_usdrx1_jesd set_property -dict [list CONFIG.C_LANES {8}] $axi_usdrx1_jesd set_property -dict [list CONFIG.GT_Line_Rate {3.2} ] $axi_usdrx1_jesd set_property -dict [list CONFIG.GT_REFCLK_FREQ {80.000} ] $axi_usdrx1_jesd -set axi_usdrx1_gt [create_bd_cell -type ip -vlnv analog.com:user:axi_jesd_gt:1.0 axi_usdrx1_gt] -set_property -dict [list CONFIG.NUM_OF_LANES {8}] $axi_usdrx1_gt -set_property -dict [list CONFIG.QPLL0_ENABLE {0}] $axi_usdrx1_gt -set_property -dict [list CONFIG.QPLL1_ENABLE {0}] $axi_usdrx1_gt -set_property -dict [list CONFIG.RX_NUM_OF_LANES {8}] $axi_usdrx1_gt -set_property -dict [list CONFIG.TX_NUM_OF_LANES {0}] $axi_usdrx1_gt -set_property -dict [list CONFIG.CPLL_FBDIV_0 {4}] $axi_usdrx1_gt -set_property -dict [list CONFIG.RX_OUT_DIV_0 {1}] $axi_usdrx1_gt -set_property -dict [list CONFIG.TX_OUT_DIV_0 {1}] $axi_usdrx1_gt -set_property -dict [list CONFIG.RX_CLK25_DIV_0 {4}] $axi_usdrx1_gt -set_property -dict [list CONFIG.TX_CLK25_DIV_0 {4}] $axi_usdrx1_gt -set_property -dict [list CONFIG.PMA_RSV_0 {0x00018480}] $axi_usdrx1_gt -set_property -dict [list CONFIG.RX_CDR_CFG_0 {0x03000023ff20400020}] $axi_usdrx1_gt -set_property -dict [list CONFIG.CPLL_FBDIV_1 {4}] $axi_usdrx1_gt -set_property -dict [list CONFIG.RX_OUT_DIV_1 {1}] $axi_usdrx1_gt -set_property -dict [list CONFIG.TX_OUT_DIV_1 {1}] $axi_usdrx1_gt -set_property -dict [list CONFIG.RX_CLK25_DIV_1 {4}] $axi_usdrx1_gt -set_property -dict [list CONFIG.TX_CLK25_DIV_1 {4}] $axi_usdrx1_gt -set_property -dict [list CONFIG.PMA_RSV_1 {0x00018480}] $axi_usdrx1_gt -set_property -dict [list CONFIG.RX_CDR_CFG_1 {0x03000023ff20400020}] $axi_usdrx1_gt -set_property -dict [list CONFIG.CPLL_FBDIV_2 {4}] $axi_usdrx1_gt -set_property -dict [list CONFIG.RX_OUT_DIV_2 {1}] $axi_usdrx1_gt -set_property -dict [list CONFIG.TX_OUT_DIV_2 {1}] $axi_usdrx1_gt -set_property -dict [list CONFIG.RX_CLK25_DIV_2 {4}] $axi_usdrx1_gt -set_property -dict [list CONFIG.TX_CLK25_DIV_2 {4}] $axi_usdrx1_gt -set_property -dict [list CONFIG.PMA_RSV_2 {0x00018480}] $axi_usdrx1_gt -set_property -dict [list CONFIG.RX_CDR_CFG_2 {0x03000023ff20400020}] $axi_usdrx1_gt -set_property -dict [list CONFIG.CPLL_FBDIV_3 {4}] $axi_usdrx1_gt -set_property -dict [list CONFIG.RX_OUT_DIV_3 {1}] $axi_usdrx1_gt -set_property -dict [list CONFIG.TX_OUT_DIV_3 {1}] $axi_usdrx1_gt -set_property -dict [list CONFIG.RX_CLK25_DIV_3 {4}] $axi_usdrx1_gt -set_property -dict [list CONFIG.TX_CLK25_DIV_3 {4}] $axi_usdrx1_gt -set_property -dict [list CONFIG.PMA_RSV_3 {0x00018480}] $axi_usdrx1_gt -set_property -dict [list CONFIG.RX_CDR_CFG_3 {0x03000023ff20400020}] $axi_usdrx1_gt -set_property -dict [list CONFIG.CPLL_FBDIV_4 {4}] $axi_usdrx1_gt -set_property -dict [list CONFIG.RX_OUT_DIV_4 {1}] $axi_usdrx1_gt -set_property -dict [list CONFIG.TX_OUT_DIV_4 {1}] $axi_usdrx1_gt -set_property -dict [list CONFIG.RX_CLK25_DIV_4 {4}] $axi_usdrx1_gt -set_property -dict [list CONFIG.TX_CLK25_DIV_4 {4}] $axi_usdrx1_gt -set_property -dict [list CONFIG.PMA_RSV_4 {0x00018480}] $axi_usdrx1_gt -set_property -dict [list CONFIG.RX_CDR_CFG_4 {0x03000023ff20400020}] $axi_usdrx1_gt -set_property -dict [list CONFIG.CPLL_FBDIV_5 {4}] $axi_usdrx1_gt -set_property -dict [list CONFIG.RX_OUT_DIV_5 {1}] $axi_usdrx1_gt -set_property -dict [list CONFIG.TX_OUT_DIV_5 {1}] $axi_usdrx1_gt -set_property -dict [list CONFIG.RX_CLK25_DIV_5 {4}] $axi_usdrx1_gt -set_property -dict [list CONFIG.TX_CLK25_DIV_5 {4}] $axi_usdrx1_gt -set_property -dict [list CONFIG.PMA_RSV_5 {0x00018480}] $axi_usdrx1_gt -set_property -dict [list CONFIG.RX_CDR_CFG_5 {0x03000023ff20400020}] $axi_usdrx1_gt -set_property -dict [list CONFIG.CPLL_FBDIV_6 {4}] $axi_usdrx1_gt -set_property -dict [list CONFIG.RX_OUT_DIV_6 {1}] $axi_usdrx1_gt -set_property -dict [list CONFIG.TX_OUT_DIV_6 {1}] $axi_usdrx1_gt -set_property -dict [list CONFIG.RX_CLK25_DIV_6 {4}] $axi_usdrx1_gt -set_property -dict [list CONFIG.TX_CLK25_DIV_6 {4}] $axi_usdrx1_gt -set_property -dict [list CONFIG.PMA_RSV_6 {0x00018480}] $axi_usdrx1_gt -set_property -dict [list CONFIG.RX_CDR_CFG_6 {0x03000023ff20400020}] $axi_usdrx1_gt -set_property -dict [list CONFIG.CPLL_FBDIV_7 {4}] $axi_usdrx1_gt -set_property -dict [list CONFIG.RX_OUT_DIV_7 {1}] $axi_usdrx1_gt -set_property -dict [list CONFIG.TX_OUT_DIV_7 {1}] $axi_usdrx1_gt -set_property -dict [list CONFIG.RX_CLK25_DIV_7 {4}] $axi_usdrx1_gt -set_property -dict [list CONFIG.TX_CLK25_DIV_7 {4}] $axi_usdrx1_gt -set_property -dict [list CONFIG.PMA_RSV_7 {0x00018480}] $axi_usdrx1_gt -set_property -dict [list CONFIG.RX_CDR_CFG_7 {0x03000023ff20400020}] $axi_usdrx1_gt +set axi_usdrx1_xcvr [create_bd_cell -type ip -vlnv analog.com:user:axi_adxcvr:1.0 axi_usdrx1_xcvr] +set_property -dict [list CONFIG.NUM_OF_LANES {8}] $axi_usdrx1_xcvr +set_property -dict [list CONFIG.QPLL_ENABLE {0}] $axi_usdrx1_xcvr +set_property -dict [list CONFIG.TX_OR_RX_N {0}] $axi_usdrx1_xcvr + +set util_usdrx1_xcvr [create_bd_cell -type ip -vlnv analog.com:user:util_adxcvr:1.0 util_usdrx1_xcvr] +set_property -dict [list CONFIG.RX_NUM_OF_LANES {8}] $util_usdrx1_xcvr +set_property -dict [list CONFIG.TX_NUM_OF_LANES {0}] $util_usdrx1_xcvr +set_property -dict [list CONFIG.CPLL_FBDIV {4}] $util_usdrx1_xcvr +set_property -dict [list CONFIG.RX_CLK25_DIV {3}] $util_usdrx1_xcvr +set_property -dict [list CONFIG.RX_DFE_LPM_CFG {0x0954}] $util_usdrx1_xcvr +set_property -dict [list CONFIG.RX_PMA_CFG {0x00018480}] $util_usdrx1_xcvr +set_property -dict [list CONFIG.RX_CDR_CFG {0x03000023FF20400020}] $util_usdrx1_xcvr -set util_usdrx1_gt [create_bd_cell -type ip -vlnv analog.com:user:util_jesd_gt:1.0 util_usdrx1_gt] -set_property -dict [list CONFIG.QPLL0_ENABLE {0}] $util_usdrx1_gt -set_property -dict [list CONFIG.QPLL1_ENABLE {0}] $util_usdrx1_gt -set_property -dict [list CONFIG.NUM_OF_LANES {8}] $util_usdrx1_gt -set_property -dict [list CONFIG.RX_ENABLE {1}] $util_usdrx1_gt -set_property -dict [list CONFIG.RX_NUM_OF_LANES {8}] $util_usdrx1_gt -set_property -dict [list CONFIG.TX_ENABLE {0}] $util_usdrx1_gt set axi_usdrx1_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_usdrx1_dma] set_property -dict [list CONFIG.DMA_TYPE_SRC {1}] $axi_usdrx1_dma @@ -154,6 +68,40 @@ set_property -dict [list CONFIG.C_USE_STARTUP {0}] $axi_usdrx1_spi set_property -dict [list CONFIG.C_NUM_SS_BITS {5}] $axi_usdrx1_spi set_property -dict [list CONFIG.C_SCK_RATIO {8}] $axi_usdrx1_spi +set data_slice_0 [create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 data_slice_0] +set_property -dict [list CONFIG.DIN_WIDTH {256}] $data_slice_0 +set_property -dict [list CONFIG.DIN_TO {0}] $data_slice_0 +set_property -dict [list CONFIG.DIN_FROM {63}] $data_slice_0 +set_property -dict [list CONFIG.DOUT_WIDTH {64}] $data_slice_0 + +set data_slice_1 [create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 data_slice_1] +set_property -dict [list CONFIG.DIN_WIDTH {256}] $data_slice_1 +set_property -dict [list CONFIG.DIN_TO {64}] $data_slice_1 +set_property -dict [list CONFIG.DIN_FROM {127}] $data_slice_1 +set_property -dict [list CONFIG.DOUT_WIDTH {64}] $data_slice_1 + +set data_slice_2 [create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 data_slice_2] +set_property -dict [list CONFIG.DIN_WIDTH {256}] $data_slice_2 +set_property -dict [list CONFIG.DIN_TO {128}] $data_slice_2 +set_property -dict [list CONFIG.DIN_FROM {191}] $data_slice_2 +set_property -dict [list CONFIG.DOUT_WIDTH {64}] $data_slice_2 + +set data_slice_3 [create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 data_slice_3] +set_property -dict [list CONFIG.DIN_WIDTH {256}] $data_slice_3 +set_property -dict [list CONFIG.DIN_TO {192}] $data_slice_3 +set_property -dict [list CONFIG.DIN_FROM {255}] $data_slice_3 +set_property -dict [list CONFIG.DOUT_WIDTH {64}] $data_slice_3 + +set adc_data_concat [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 adc_data_concat] +set_property -dict [list CONFIG.NUM_PORTS {4}] $adc_data_concat + +set adc_valid_concat [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 adc_valid_concat] +set_property -dict [list CONFIG.NUM_PORTS {4}] $adc_valid_concat + +set adc_valid_reduced_or [create_bd_cell -type ip -vlnv xilinx.com:ip:util_reduced_logic:2.0 adc_valid_reduced_or] +set_property -dict [list CONFIG.C_SIZE {32}] $adc_valid_reduced_or +set_property -dict [list CONFIG.C_OPERATION {or} ] $adc_valid_reduced_or + # connections (spi) ad_connect spi_csn_i axi_usdrx1_spi/ss_i @@ -165,96 +113,56 @@ ad_connect spi_sdo_o axi_usdrx1_spi/io0_o ad_connect spi_sdi_i axi_usdrx1_spi/io1_i ad_connect sys_cpu_clk axi_usdrx1_spi/ext_spi_clk -# connections (gt) - -ad_connect util_usdrx1_gt/qpll_ref_clk rx_ref_clk -ad_connect util_usdrx1_gt/cpll_ref_clk rx_ref_clk - -ad_connect axi_usdrx1_gt/gt_pll_0 util_usdrx1_gt/gt_pll_0 -ad_connect axi_usdrx1_gt/gt_pll_1 util_usdrx1_gt/gt_pll_1 -ad_connect axi_usdrx1_gt/gt_pll_2 util_usdrx1_gt/gt_pll_2 -ad_connect axi_usdrx1_gt/gt_pll_3 util_usdrx1_gt/gt_pll_3 -ad_connect axi_usdrx1_gt/gt_pll_4 util_usdrx1_gt/gt_pll_4 -ad_connect axi_usdrx1_gt/gt_pll_5 util_usdrx1_gt/gt_pll_5 -ad_connect axi_usdrx1_gt/gt_pll_6 util_usdrx1_gt/gt_pll_6 -ad_connect axi_usdrx1_gt/gt_pll_7 util_usdrx1_gt/gt_pll_7 - -ad_connect axi_usdrx1_gt/gt_rx_0 util_usdrx1_gt/gt_rx_0 -ad_connect axi_usdrx1_gt/gt_rx_1 util_usdrx1_gt/gt_rx_1 -ad_connect axi_usdrx1_gt/gt_rx_2 util_usdrx1_gt/gt_rx_2 -ad_connect axi_usdrx1_gt/gt_rx_3 util_usdrx1_gt/gt_rx_3 -ad_connect axi_usdrx1_gt/gt_rx_4 util_usdrx1_gt/gt_rx_4 -ad_connect axi_usdrx1_gt/gt_rx_5 util_usdrx1_gt/gt_rx_5 -ad_connect axi_usdrx1_gt/gt_rx_6 util_usdrx1_gt/gt_rx_6 -ad_connect axi_usdrx1_gt/gt_rx_7 util_usdrx1_gt/gt_rx_7 - -ad_connect axi_usdrx1_gt/gt_rx_ip_0 axi_usdrx1_jesd/gt0_rx -ad_connect axi_usdrx1_gt/gt_rx_ip_1 axi_usdrx1_jesd/gt1_rx -ad_connect axi_usdrx1_gt/gt_rx_ip_2 axi_usdrx1_jesd/gt2_rx -ad_connect axi_usdrx1_gt/gt_rx_ip_3 axi_usdrx1_jesd/gt3_rx -ad_connect axi_usdrx1_gt/gt_rx_ip_4 axi_usdrx1_jesd/gt4_rx -ad_connect axi_usdrx1_gt/gt_rx_ip_5 axi_usdrx1_jesd/gt5_rx -ad_connect axi_usdrx1_gt/gt_rx_ip_6 axi_usdrx1_jesd/gt6_rx -ad_connect axi_usdrx1_gt/gt_rx_ip_7 axi_usdrx1_jesd/gt7_rx - -ad_connect axi_usdrx1_gt/rx_gt_comma_align_enb_0 axi_usdrx1_jesd/rxencommaalign_out -ad_connect axi_usdrx1_gt/rx_gt_comma_align_enb_1 axi_usdrx1_jesd/rxencommaalign_out -ad_connect axi_usdrx1_gt/rx_gt_comma_align_enb_2 axi_usdrx1_jesd/rxencommaalign_out -ad_connect axi_usdrx1_gt/rx_gt_comma_align_enb_3 axi_usdrx1_jesd/rxencommaalign_out -ad_connect axi_usdrx1_gt/rx_gt_comma_align_enb_4 axi_usdrx1_jesd/rxencommaalign_out -ad_connect axi_usdrx1_gt/rx_gt_comma_align_enb_5 axi_usdrx1_jesd/rxencommaalign_out -ad_connect axi_usdrx1_gt/rx_gt_comma_align_enb_6 axi_usdrx1_jesd/rxencommaalign_out -ad_connect axi_usdrx1_gt/rx_gt_comma_align_enb_7 axi_usdrx1_jesd/rxencommaalign_out +ad_connect sys_cpu_resetn util_usdrx1_xcvr/up_rstn +ad_connect sys_cpu_clk util_usdrx1_xcvr/up_clk # connections (adc) -ad_connect rx_data_p util_usdrx1_gt/rx_p -ad_connect rx_data_n util_usdrx1_gt/rx_n -ad_connect rx_sync util_usdrx1_gt/rx_sync -ad_connect rx_sysref util_usdrx1_gt/rx_ip_sysref +create_bd_port -dir I rx_ref_clk_0 -ad_connect util_usdrx1_gt/rx_out_clk util_usdrx1_gt/rx_clk -ad_connect util_usdrx1_gt/rx_out_clk axi_usdrx1_jesd/rx_core_clk +ad_xcvrpll rx_ref_clk_0 util_usdrx1_xcvr/cpll_ref_clk_* +ad_xcvrpll rx_ref_clk_0 util_usdrx1_xcvr/qpll_ref_clk_* +ad_xcvrpll axi_usdrx1_xcvr/up_pll_rst util_usdrx1_xcvr/up_cpll_rst_* +ad_xcvrpll axi_usdrx1_xcvr/up_pll_rst util_usdrx1_xcvr/up_qpll_rst_* -ad_connect util_usdrx1_gt/rx_ip_rst axi_usdrx1_jesd/rx_reset -ad_connect util_usdrx1_gt/rx_ip_rst_done axi_usdrx1_jesd/rx_reset_done -ad_connect util_usdrx1_gt/rx_ip_sysref axi_usdrx1_jesd/rx_sysref -ad_connect util_usdrx1_gt/rx_ip_sync axi_usdrx1_jesd/rx_sync -ad_connect util_usdrx1_gt/rx_ip_sof axi_usdrx1_jesd/rx_start_of_frame -ad_connect util_usdrx1_gt/rx_ip_data axi_usdrx1_jesd/rx_tdata +ad_xcvrcon util_usdrx1_xcvr axi_usdrx1_xcvr axi_usdrx1_jesd +ad_connect util_usdrx1_xcvr/rx_out_clk_0 axi_ad9671_core_0/rx_clk +ad_connect util_usdrx1_xcvr/rx_out_clk_0 axi_ad9671_core_1/rx_clk +ad_connect util_usdrx1_xcvr/rx_out_clk_0 axi_ad9671_core_2/rx_clk +ad_connect util_usdrx1_xcvr/rx_out_clk_0 axi_ad9671_core_3/rx_clk +ad_connect util_usdrx1_xcvr/rx_out_clk_0 rx_core_clk +ad_connect axi_usdrx1_jesd/rx_start_of_frame axi_ad9671_core_0/rx_sof +ad_connect axi_usdrx1_jesd/rx_start_of_frame axi_ad9671_core_1/rx_sof +ad_connect axi_usdrx1_jesd/rx_start_of_frame axi_ad9671_core_2/rx_sof +ad_connect axi_usdrx1_jesd/rx_start_of_frame axi_ad9671_core_3/rx_sof -ad_connect gt_rx_data util_usdrx1_gt/rx_data -ad_connect util_usdrx1_gt/rx_out_clk axi_ad9671_core_0/rx_clk -ad_connect gt_rx_data_0 axi_ad9671_core_0/rx_data -ad_connect util_usdrx1_gt/rx_sof axi_ad9671_core_0/rx_sof -ad_connect util_usdrx1_gt/rx_out_clk axi_ad9671_core_1/rx_clk -ad_connect gt_rx_data_1 axi_ad9671_core_1/rx_data -ad_connect util_usdrx1_gt/rx_sof axi_ad9671_core_1/rx_sof -ad_connect util_usdrx1_gt/rx_out_clk axi_ad9671_core_2/rx_clk -ad_connect gt_rx_data_2 axi_ad9671_core_2/rx_data -ad_connect util_usdrx1_gt/rx_sof axi_ad9671_core_2/rx_sof -ad_connect util_usdrx1_gt/rx_out_clk axi_ad9671_core_3/rx_clk -ad_connect gt_rx_data_3 axi_ad9671_core_3/rx_data -ad_connect util_usdrx1_gt/rx_sof axi_ad9671_core_3/rx_sof -ad_connect axi_ad9671_core_0/adc_clk usdrx1_fifo/adc_clk -ad_connect adc_data_0 axi_ad9671_core_0/adc_data -ad_connect adc_data_1 axi_ad9671_core_1/adc_data -ad_connect adc_data_2 axi_ad9671_core_2/adc_data -ad_connect adc_data_3 axi_ad9671_core_3/adc_data -ad_connect adc_valid_0 axi_ad9671_core_0/adc_valid -ad_connect adc_valid_1 axi_ad9671_core_1/adc_valid -ad_connect adc_valid_2 axi_ad9671_core_2/adc_valid -ad_connect adc_valid_3 axi_ad9671_core_3/adc_valid -ad_connect adc_enable_0 axi_ad9671_core_0/adc_enable -ad_connect adc_enable_1 axi_ad9671_core_1/adc_enable -ad_connect adc_enable_2 axi_ad9671_core_2/adc_enable -ad_connect adc_enable_3 axi_ad9671_core_3/adc_enable -ad_connect adc_dovf_0 axi_ad9671_core_0/adc_dovf -ad_connect adc_dovf_1 axi_ad9671_core_1/adc_dovf -ad_connect adc_dovf_2 axi_ad9671_core_2/adc_dovf -ad_connect adc_dovf_3 axi_ad9671_core_3/adc_dovf -ad_connect adc_wr_en usdrx1_fifo/adc_wr -ad_connect adc_data usdrx1_fifo/adc_wdata +ad_connect axi_usdrx1_jesd/rx_tdata data_slice_0/Din +ad_connect axi_usdrx1_jesd/rx_tdata data_slice_1/Din +ad_connect axi_usdrx1_jesd/rx_tdata data_slice_2/Din +ad_connect axi_usdrx1_jesd/rx_tdata data_slice_3/Din + +ad_connect data_slice_0/Dout axi_ad9671_core_0/rx_data +ad_connect data_slice_1/Dout axi_ad9671_core_1/rx_data +ad_connect data_slice_2/Dout axi_ad9671_core_2/rx_data +ad_connect data_slice_3/Dout axi_ad9671_core_3/rx_data + +ad_connect util_usdrx1_xcvr/rx_out_clk_0 usdrx1_fifo/adc_clk +ad_connect adc_data_concat/In0 axi_ad9671_core_0/adc_data +ad_connect adc_data_concat/In1 axi_ad9671_core_1/adc_data +ad_connect adc_data_concat/In2 axi_ad9671_core_2/adc_data +ad_connect adc_data_concat/In3 axi_ad9671_core_3/adc_data +ad_connect adc_valid_concat/In0 axi_ad9671_core_0/adc_valid +ad_connect adc_valid_concat/In1 axi_ad9671_core_1/adc_valid +ad_connect adc_valid_concat/In2 axi_ad9671_core_2/adc_valid +ad_connect adc_valid_concat/In3 axi_ad9671_core_3/adc_valid +ad_connect adc_valid_concat/dout adc_valid_reduced_or/Op1 + +ad_connect usdrx1_fifo/adc_wovf axi_ad9671_core_0/adc_dovf +ad_connect usdrx1_fifo/adc_wovf axi_ad9671_core_1/adc_dovf +ad_connect usdrx1_fifo/adc_wovf axi_ad9671_core_2/adc_dovf +ad_connect usdrx1_fifo/adc_wovf axi_ad9671_core_3/adc_dovf +ad_connect adc_valid_reduced_or/Res usdrx1_fifo/adc_wr +ad_connect adc_data_concat/dout usdrx1_fifo/adc_wdata ad_connect axi_ad9671_adc_raddr axi_ad9671_core_0/adc_raddr_out ad_connect axi_ad9671_adc_raddr axi_ad9671_core_1/adc_raddr_in ad_connect axi_ad9671_adc_raddr axi_ad9671_core_2/adc_raddr_in @@ -264,8 +172,7 @@ ad_connect axi_ad9671_adc_sync axi_ad9671_core_1/adc_sync_in ad_connect axi_ad9671_adc_sync axi_ad9671_core_2/adc_sync_in ad_connect axi_ad9671_adc_sync axi_ad9671_core_3/adc_sync_in -ad_connect util_usdrx1_gt/rx_rst usdrx1_fifo/adc_rst -ad_connect adc_dovf usdrx1_fifo/adc_wovf +ad_connect axi_usdrx1_jesd_rstgen/peripheral_reset usdrx1_fifo/adc_rst ad_connect usdrx1_fifo/dma_wdata axi_usdrx1_dma/s_axis_data ad_connect usdrx1_fifo/dma_wr axi_usdrx1_dma/s_axis_valid @@ -281,7 +188,7 @@ ad_cpu_interconnect 0x44A10000 axi_ad9671_core_1 ad_cpu_interconnect 0x44A20000 axi_ad9671_core_2 ad_cpu_interconnect 0x44A30000 axi_ad9671_core_3 -ad_cpu_interconnect 0x44A60000 axi_usdrx1_gt +ad_cpu_interconnect 0x44A60000 axi_usdrx1_xcvr ad_cpu_interconnect 0x44A91000 axi_usdrx1_jesd ad_cpu_interconnect 0x7c400000 axi_usdrx1_dma ad_cpu_interconnect 0x7c420000 axi_usdrx1_spi @@ -291,7 +198,7 @@ ad_mem_hp2_interconnect sys_200m_clk axi_usdrx1_dma/m_dest_axi ad_connect sys_cpu_resetn axi_usdrx1_dma/m_dest_axi_aresetn ad_mem_hp3_interconnect sys_cpu_clk sys_ps7/S_AXI_HP3 -ad_mem_hp3_interconnect sys_cpu_clk axi_usdrx1_gt/m_axi +ad_mem_hp3_interconnect sys_cpu_clk axi_usdrx1_xcvr/m_axi #interrupts @@ -300,7 +207,7 @@ ad_cpu_interrupt ps-13 mb-13 axi_usdrx1_dma/irq # ila -set ila_ad9671 [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.0 ila_ad9671] +set ila_ad9671 [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.1 ila_ad9671] set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_ad9671 set_property -dict [list CONFIG.C_NUM_OF_PROBES {9}] $ila_ad9671 set_property -dict [list CONFIG.C_PROBE0_WIDTH {128}] $ila_ad9671 @@ -315,12 +222,12 @@ set_property -dict [list CONFIG.C_PROBE8_WIDTH {1}] $ila_ad9671 set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila_ad9671 ad_connect axi_ad9671_core_0/adc_clk ila_ad9671/CLK -ad_connect adc_data_0 ila_ad9671/PROBE0 -ad_connect adc_valid_0 ila_ad9671/PROBE1 -ad_connect adc_data_1 ila_ad9671/PROBE2 -ad_connect adc_valid_1 ila_ad9671/PROBE3 -ad_connect adc_data_2 ila_ad9671/PROBE4 -ad_connect adc_valid_2 ila_ad9671/PROBE5 -ad_connect adc_data_3 ila_ad9671/PROBE6 -ad_connect adc_valid_3 ila_ad9671/PROBE7 -ad_connect adc_dovf_0 ila_ad9671/PROBE8 +ad_connect axi_ad9671_core_0/adc_data ila_ad9671/PROBE0 +ad_connect axi_ad9671_core_0/adc_valid ila_ad9671/PROBE1 +ad_connect axi_ad9671_core_1/adc_data ila_ad9671/PROBE2 +ad_connect axi_ad9671_core_1/adc_valid ila_ad9671/PROBE3 +ad_connect axi_ad9671_core_2/adc_data ila_ad9671/PROBE4 +ad_connect axi_ad9671_core_2/adc_valid ila_ad9671/PROBE5 +ad_connect axi_ad9671_core_3/adc_data ila_ad9671/PROBE6 +ad_connect axi_ad9671_core_3/adc_valid ila_ad9671/PROBE7 +ad_connect usdrx1_fifo/adc_wovf ila_ad9671/PROBE8 diff --git a/projects/usdrx1/common/usdrx1_qsys.tcl b/projects/usdrx1/common/usdrx1_qsys.tcl new file mode 100644 index 000000000..d30af0ead --- /dev/null +++ b/projects/usdrx1/common/usdrx1_qsys.tcl @@ -0,0 +1,230 @@ + +# usdrx1-xcvr + +add_instance avl_usdrx1_xcvr avl_adxcvr 1.0 +set_instance_parameter_value avl_usdrx1_xcvr {ID} {1} +set_instance_parameter_value avl_usdrx1_xcvr {TX_OR_RX_N} {0} +set_instance_parameter_value avl_usdrx1_xcvr {PCS_CONFIG} {JESD_PCS_CFG1} +set_instance_parameter_value avl_usdrx1_xcvr {LANE_RATE} {3200.0} +set_instance_parameter_value avl_usdrx1_xcvr {SYSCLK_FREQUENCY} {50.0} +set_instance_parameter_value avl_usdrx1_xcvr {PLLCLK_FREQUENCY} {1600.0} +set_instance_parameter_value avl_usdrx1_xcvr {REFCLK_FREQUENCY} {80.0} +set_instance_parameter_value avl_usdrx1_xcvr {CORECLK_FREQUENCY} {80.0} +set_instance_parameter_value avl_usdrx1_xcvr {NUM_OF_LANES} {8} +set_instance_parameter_value avl_usdrx1_xcvr {NUM_OF_CONVS} {32} +set_instance_parameter_value avl_usdrx1_xcvr {FRM_BCNT} {4} +set_instance_parameter_value avl_usdrx1_xcvr {FRM_SCNT} {1} +set_instance_parameter_value avl_usdrx1_xcvr {MF_FCNT} {32} +set_instance_parameter_value avl_usdrx1_xcvr {HD} {0} + +add_connection sys_clk.clk avl_usdrx1_xcvr.sys_clk +add_connection sys_clk.clk_reset avl_usdrx1_xcvr.sys_resetn +add_interface rx_ref_clk clock sink +set_interface_property rx_ref_clk EXPORT_OF avl_usdrx1_xcvr.ref_clk +add_interface rx_data_0 conduit end +set_interface_property rx_data_0 EXPORT_OF avl_usdrx1_xcvr.rx_data_0 +add_interface rx_data_1 conduit end +set_interface_property rx_data_1 EXPORT_OF avl_usdrx1_xcvr.rx_data_1 +add_interface rx_data_2 conduit end +set_interface_property rx_data_2 EXPORT_OF avl_usdrx1_xcvr.rx_data_2 +add_interface rx_data_3 conduit end +set_interface_property rx_data_3 EXPORT_OF avl_usdrx1_xcvr.rx_data_3 +add_interface rx_data_4 conduit end +set_interface_property rx_data_4 EXPORT_OF avl_usdrx1_xcvr.rx_data_4 +add_interface rx_data_5 conduit end +set_interface_property rx_data_5 EXPORT_OF avl_usdrx1_xcvr.rx_data_5 +add_interface rx_data_6 conduit end +set_interface_property rx_data_6 EXPORT_OF avl_usdrx1_xcvr.rx_data_6 +add_interface rx_data_7 conduit end +set_interface_property rx_data_7 EXPORT_OF avl_usdrx1_xcvr.rx_data_7 +add_interface rx_sysref conduit end +set_interface_property rx_sysref EXPORT_OF avl_usdrx1_xcvr.sysref +add_interface rx_sync conduit end +set_interface_property rx_sync EXPORT_OF avl_usdrx1_xcvr.sync +add_interface rx_ip_sof conduit end +set_interface_property rx_ip_sof EXPORT_OF avl_usdrx1_xcvr.ip_sof +add_interface rx_ip_data avalon_streaming source +set_interface_property rx_ip_data EXPORT_OF avl_usdrx1_xcvr.ip_data + +# usdrx1-xcvr + +add_instance axi_usdrx1_xcvr axi_adxcvr 1.0 +set_instance_parameter_value axi_usdrx1_xcvr {ID} {1} +set_instance_parameter_value axi_usdrx1_xcvr {TX_OR_RX_N} {0} +set_instance_parameter_value axi_usdrx1_xcvr {NUM_OF_LANES} {8} + +add_connection sys_clk.clk axi_usdrx1_xcvr.s_axi_clock +add_connection sys_clk.clk_reset axi_usdrx1_xcvr.s_axi_reset +add_connection axi_usdrx1_xcvr.if_up_rst avl_usdrx1_xcvr.rst +add_connection avl_usdrx1_xcvr.ready axi_usdrx1_xcvr.ready +add_connection axi_usdrx1_xcvr.core_pll_locked avl_usdrx1_xcvr.core_pll_locked + +# ad9671 + +add_instance axi_ad9671_core_0 axi_ad9671 1.0 +set_instance_parameter_value axi_ad9671_core_0 {ID} {0} +set_instance_parameter_value axi_ad9671_core_0 {QUAD_OR_DUAL_N} {0} +add_connection avl_usdrx1_xcvr.core_clk axi_ad9671_core_0.if_rx_clk +add_interface rx_ip_sof_0 conduit end +set_interface_property rx_ip_sof_0 EXPORT_OF axi_ad9671_core_0.if_rx_sof +add_interface rx_ip_data_0 avalon_streaming sink +set_interface_property rx_ip_data_0 EXPORT_OF axi_ad9671_core_0.if_rx_data +add_connection sys_clk.clk_reset axi_ad9671_core_0.s_axi_reset +add_connection sys_clk.clk axi_ad9671_core_0.s_axi_clock +add_interface rx_core_ch_0 conduit end +set_interface_property rx_core_ch_0 EXPORT_OF axi_ad9671_core_0.adc_ch +add_interface rx_core_sync_0 conduit end +set_interface_property rx_core_sync_0 EXPORT_OF axi_ad9671_core_0.if_sync +add_interface rx_core_ovf_0 conduit end +set_interface_property rx_core_ovf_0 EXPORT_OF axi_ad9671_core_0.if_adc_dovf +add_interface rx_core_unf_0 conduit end +set_interface_property rx_core_unf_0 EXPORT_OF axi_ad9671_core_0.if_adc_dunf + +add_instance axi_ad9671_core_1 axi_ad9671 1.0 +set_instance_parameter_value axi_ad9671_core_1 {ID} {1} +set_instance_parameter_value axi_ad9671_core_1 {QUAD_OR_DUAL_N} {0} +add_connection avl_usdrx1_xcvr.core_clk axi_ad9671_core_1.if_rx_clk +add_interface rx_ip_sof_1 conduit end +set_interface_property rx_ip_sof_1 EXPORT_OF axi_ad9671_core_1.if_rx_sof +add_interface rx_ip_data_1 avalon_streaming sink +set_interface_property rx_ip_data_1 EXPORT_OF axi_ad9671_core_1.if_rx_data +add_connection sys_clk.clk_reset axi_ad9671_core_1.s_axi_reset +add_connection sys_clk.clk axi_ad9671_core_1.s_axi_clock +add_interface rx_core_ch_1 conduit end +set_interface_property rx_core_ch_1 EXPORT_OF axi_ad9671_core_1.adc_ch +add_interface rx_core_sync_1 conduit end +set_interface_property rx_core_sync_1 EXPORT_OF axi_ad9671_core_1.if_sync +add_interface rx_core_ovf_1 conduit end +set_interface_property rx_core_ovf_1 EXPORT_OF axi_ad9671_core_1.if_adc_dovf +add_interface rx_core_unf_1 conduit end +set_interface_property rx_core_unf_1 EXPORT_OF axi_ad9671_core_1.if_adc_dunf + +add_instance axi_ad9671_core_2 axi_ad9671 1.0 +set_instance_parameter_value axi_ad9671_core_2 {ID} {2} +set_instance_parameter_value axi_ad9671_core_2 {QUAD_OR_DUAL_N} {0} +add_connection avl_usdrx1_xcvr.core_clk axi_ad9671_core_2.if_rx_clk +add_interface rx_ip_sof_2 conduit end +set_interface_property rx_ip_sof_2 EXPORT_OF axi_ad9671_core_2.if_rx_sof +add_interface rx_ip_data_2 avalon_streaming sink +set_interface_property rx_ip_data_2 EXPORT_OF axi_ad9671_core_2.if_rx_data +add_connection sys_clk.clk_reset axi_ad9671_core_2.s_axi_reset +add_connection sys_clk.clk axi_ad9671_core_2.s_axi_clock +add_interface rx_core_ch_2 conduit end +set_interface_property rx_core_ch_2 EXPORT_OF axi_ad9671_core_2.adc_ch +add_interface rx_core_sync_2 conduit end +set_interface_property rx_core_sync_2 EXPORT_OF axi_ad9671_core_2.if_sync +add_interface rx_core_ovf_2 conduit end +set_interface_property rx_core_ovf_2 EXPORT_OF axi_ad9671_core_2.if_adc_dovf +add_interface rx_core_unf_2 conduit end +set_interface_property rx_core_unf_2 EXPORT_OF axi_ad9671_core_2.if_adc_dunf + +add_instance axi_ad9671_core_3 axi_ad9671 1.0 +set_instance_parameter_value axi_ad9671_core_3 {ID} {3} +set_instance_parameter_value axi_ad9671_core_3 {QUAD_OR_DUAL_N} {0} +add_connection avl_usdrx1_xcvr.core_clk axi_ad9671_core_3.if_rx_clk +add_interface rx_ip_sof_3 conduit end +set_interface_property rx_ip_sof_3 EXPORT_OF axi_ad9671_core_3.if_rx_sof +add_interface rx_ip_data_3 avalon_streaming sink +set_interface_property rx_ip_data_3 EXPORT_OF axi_ad9671_core_3.if_rx_data +add_connection sys_clk.clk_reset axi_ad9671_core_3.s_axi_reset +add_connection sys_clk.clk axi_ad9671_core_3.s_axi_clock +add_interface rx_core_ch_3 conduit end +set_interface_property rx_core_ch_3 EXPORT_OF axi_ad9671_core_3.adc_ch +add_interface rx_core_sync_3 conduit end +set_interface_property rx_core_sync_3 EXPORT_OF axi_ad9671_core_3.if_sync +add_interface rx_core_ovf_3 conduit end +set_interface_property rx_core_ovf_3 EXPORT_OF axi_ad9671_core_3.if_adc_dovf +add_interface rx_core_unf_3 conduit end +set_interface_property rx_core_unf_3 EXPORT_OF axi_ad9671_core_3.if_adc_dunf + +# usdrx1-fifo + +add_instance usdrx1_adcfifo util_adcfifo 1.0 +set_instance_parameter_value usdrx1_adcfifo {ADC_DATA_WIDTH} {512} +set_instance_parameter_value usdrx1_adcfifo {DMA_DATA_WIDTH} {512} +set_instance_parameter_value usdrx1_adcfifo {DMA_ADDRESS_WIDTH} {10} + +add_connection sys_clk.clk_reset usdrx1_adcfifo.if_adc_rst +add_connection sys_dma_clk.clk_reset usdrx1_adcfifo.if_adc_rst +add_connection avl_usdrx1_xcvr.core_clk usdrx1_adcfifo.if_adc_clk +add_interface rx_ch_wr conduit end +set_interface_property rx_ch_wr EXPORT_OF usdrx1_adcfifo.if_adc_wr +add_interface rx_ch_wdata conduit end +set_interface_property rx_ch_wdata EXPORT_OF usdrx1_adcfifo.if_adc_wdata +add_interface rx_ch_wovf conduit end +set_interface_property rx_ch_wovf EXPORT_OF usdrx1_adcfifo.if_adc_wovf +add_connection sys_dma_clk.clk usdrx1_adcfifo.if_dma_clk + +# usdrx1-dma + +add_instance axi_usdrx1_dma axi_dmac 1.0 +set_instance_parameter_value axi_usdrx1_dma {DMA_DATA_WIDTH_SRC} {512} +set_instance_parameter_value axi_usdrx1_dma {DMA_DATA_WIDTH_DEST} {512} +set_instance_parameter_value axi_usdrx1_dma {DMA_LENGTH_WIDTH} {24} +set_instance_parameter_value axi_usdrx1_dma {DMA_2D_TRANSFER} {0} +set_instance_parameter_value axi_usdrx1_dma {SYNC_TRANSFER_START} {1} +set_instance_parameter_value axi_usdrx1_dma {CYCLIC} {0} +set_instance_parameter_value axi_usdrx1_dma {DMA_TYPE_DEST} {0} +set_instance_parameter_value axi_usdrx1_dma {DMA_TYPE_SRC} {1} + +add_connection sys_dma_clk.clk axi_usdrx1_dma.if_s_axis_aclk +add_connection usdrx1_adcfifo.if_dma_wr axi_usdrx1_dma.if_s_axis_valid +add_connection usdrx1_adcfifo.if_dma_wdata axi_usdrx1_dma.if_s_axis_data +add_connection usdrx1_adcfifo.if_dma_wready axi_usdrx1_dma.if_s_axis_ready +add_connection usdrx1_adcfifo.if_dma_xfer_req axi_usdrx1_dma.if_s_axis_xfer_req +add_connection sys_clk.clk_reset axi_usdrx1_dma.s_axi_reset +add_connection sys_clk.clk axi_usdrx1_dma.s_axi_clock +add_connection sys_dma_clk.clk_reset axi_usdrx1_dma.m_dest_axi_reset +add_connection sys_dma_clk.clk axi_usdrx1_dma.m_dest_axi_clock + +# core-clock + +add_instance rx_core_clk altera_clock_bridge 16.0 +add_connection avl_usdrx1_xcvr.core_clk rx_core_clk.in_clk +add_interface rx_core_clk clock source +set_interface_property rx_core_clk EXPORT_OF rx_core_clk.out_clk + +# phy reconfiguration + +add_instance avl_phy_reconfig alt_xcvr_reconfig 16.0 +set_instance_parameter_value avl_phy_reconfig {number_of_reconfig_interfaces} {8} +set_instance_parameter_value avl_phy_reconfig {gui_split_sizes} {1,1,1,1,1,1,1,1} +add_connection avl_phy_reconfig.ch0_0_to_xcvr avl_usdrx1_xcvr.phy_reconfig_to_xcvr_0 +add_connection avl_usdrx1_xcvr.phy_reconfig_from_xcvr_0 avl_phy_reconfig.ch0_0_from_xcvr +add_connection avl_phy_reconfig.ch1_1_to_xcvr avl_usdrx1_xcvr.phy_reconfig_to_xcvr_1 +add_connection avl_usdrx1_xcvr.phy_reconfig_from_xcvr_1 avl_phy_reconfig.ch1_1_from_xcvr +add_connection avl_phy_reconfig.ch2_2_to_xcvr avl_usdrx1_xcvr.phy_reconfig_to_xcvr_2 +add_connection avl_usdrx1_xcvr.phy_reconfig_from_xcvr_2 avl_phy_reconfig.ch2_2_from_xcvr +add_connection avl_phy_reconfig.ch3_3_to_xcvr avl_usdrx1_xcvr.phy_reconfig_to_xcvr_3 +add_connection avl_usdrx1_xcvr.phy_reconfig_from_xcvr_3 avl_phy_reconfig.ch3_3_from_xcvr +add_connection avl_phy_reconfig.ch4_4_to_xcvr avl_usdrx1_xcvr.phy_reconfig_to_xcvr_4 +add_connection avl_usdrx1_xcvr.phy_reconfig_from_xcvr_4 avl_phy_reconfig.ch4_4_from_xcvr +add_connection avl_phy_reconfig.ch5_5_to_xcvr avl_usdrx1_xcvr.phy_reconfig_to_xcvr_5 +add_connection avl_usdrx1_xcvr.phy_reconfig_from_xcvr_5 avl_phy_reconfig.ch5_5_from_xcvr +add_connection avl_phy_reconfig.ch6_6_to_xcvr avl_usdrx1_xcvr.phy_reconfig_to_xcvr_6 +add_connection avl_usdrx1_xcvr.phy_reconfig_from_xcvr_6 avl_phy_reconfig.ch6_6_from_xcvr +add_connection avl_phy_reconfig.ch7_7_to_xcvr avl_usdrx1_xcvr.phy_reconfig_to_xcvr_7 +add_connection avl_usdrx1_xcvr.phy_reconfig_from_xcvr_7 avl_phy_reconfig.ch7_7_from_xcvr +add_connection sys_clk.clk_reset avl_phy_reconfig.mgmt_rst_reset +add_connection sys_clk.clk avl_phy_reconfig.mgmt_clk_clk + +# addresses + +ad_cpu_interconnect 0x00010000 avl_phy_reconfig.reconfig_mgmt +ad_cpu_interconnect 0x00018000 avl_usdrx1_xcvr.core_pll_reconfig +ad_cpu_interconnect 0x00019000 avl_usdrx1_xcvr.ip_reconfig +ad_cpu_interconnect 0x00020000 axi_usdrx1_xcvr.s_axi +ad_cpu_interconnect 0x00050000 axi_ad9671_core_0.s_axi +ad_cpu_interconnect 0x00060000 axi_ad9671_core_1.s_axi +ad_cpu_interconnect 0x00070000 axi_ad9671_core_2.s_axi +ad_cpu_interconnect 0x00080000 axi_ad9671_core_3.s_axi +ad_cpu_interconnect 0x00090000 axi_usdrx1_dma.s_axi + +# dma interconnects + +ad_dma_interconnect axi_usdrx1_dma.m_dest_axi + +# interrupts + +ad_cpu_interrupt 11 axi_usdrx1_dma.interrupt_sender + diff --git a/projects/usdrx1/zc706/Makefile b/projects/usdrx1/zc706/Makefile index 936fbbcfe..0d892b3f2 100644 --- a/projects/usdrx1/zc706/Makefile +++ b/projects/usdrx1/zc706/Makefile @@ -14,19 +14,21 @@ M_DEPS += ../common/usdrx1_bd.tcl M_DEPS += ../../scripts/adi_project.tcl M_DEPS += ../../scripts/adi_env.tcl M_DEPS += ../../scripts/adi_board.tcl -M_DEPS += ../../common/zc706/zc706_system_plddr3.tcl +M_DEPS += ../../common/zc706/zc706_system_plddr3_adcfifo.tcl M_DEPS += ../../common/zc706/zc706_system_mig_constr.xdc M_DEPS += ../../common/zc706/zc706_system_mig.prj M_DEPS += ../../common/zc706/zc706_system_constr.xdc M_DEPS += ../../common/zc706/zc706_system_bd.tcl +M_DEPS += ../../../library/xilinx/common/ad_iobuf.v +M_DEPS += ../../../library/common/ad_sysref_gen.v M_DEPS += ../../../library/axi_ad9671/axi_ad9671.xpr -M_DEPS += ../../../library/axi_adcfifo/axi_adcfifo.xpr +M_DEPS += ../../../library/xilinx/axi_adcfifo/axi_adcfifo.xpr +M_DEPS += ../../../library/xilinx/axi_adxcvr/axi_adxcvr.xpr M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr -M_DEPS += ../../../library/axi_jesd_gt/axi_jesd_gt.xpr M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr -M_DEPS += ../../../library/util_jesd_gt/util_jesd_gt.xpr +M_DEPS += ../../../library/xilinx/util_adxcvr/util_adxcvr.xpr M_VIVADO := vivado -mode batch -source @@ -42,6 +44,7 @@ M_FLIST += *.sdk M_FLIST += *.hw M_FLIST += *.sim M_FLIST += .Xil +M_FLIST += *.ip_user_files @@ -55,29 +58,29 @@ clean: clean-all:clean make -C ../../../library/axi_ad9671 clean - make -C ../../../library/axi_adcfifo clean + make -C ../../../library/xilinx/axi_adcfifo clean + make -C ../../../library/xilinx/axi_adxcvr clean make -C ../../../library/axi_clkgen clean make -C ../../../library/axi_dmac clean make -C ../../../library/axi_hdmi_tx clean - make -C ../../../library/axi_jesd_gt clean make -C ../../../library/axi_spdif_tx clean - make -C ../../../library/util_jesd_gt clean + make -C ../../../library/xilinx/util_adxcvr clean usdrx1_zc706.sdk/system_top.hdf: $(M_DEPS) - rm -rf $(M_FLIST) + -rm -rf $(M_FLIST) $(M_VIVADO) system_project.tcl >> usdrx1_zc706_vivado.log 2>&1 lib: make -C ../../../library/axi_ad9671 - make -C ../../../library/axi_adcfifo + make -C ../../../library/xilinx/axi_adcfifo + make -C ../../../library/xilinx/axi_adxcvr make -C ../../../library/axi_clkgen make -C ../../../library/axi_dmac make -C ../../../library/axi_hdmi_tx - make -C ../../../library/axi_jesd_gt make -C ../../../library/axi_spdif_tx - make -C ../../../library/util_jesd_gt + make -C ../../../library/xilinx/util_adxcvr #################################################################################### #################################################################################### diff --git a/projects/usdrx1/zc706/system_bd.tcl b/projects/usdrx1/zc706/system_bd.tcl index 0657c681c..239c0152f 100644 --- a/projects/usdrx1/zc706/system_bd.tcl +++ b/projects/usdrx1/zc706/system_bd.tcl @@ -1,8 +1,9 @@ + source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl -source $ad_hdl_dir/projects/common/zc706/zc706_system_plddr3.tcl +source $ad_hdl_dir/projects/common/zc706/zc706_system_plddr3_adcfifo.tcl -p_plddr3_fifo [current_bd_instance .] usdrx1_fifo 512 +p_plddr3_adcfifo [current_bd_instance .] usdrx1_fifo 512 create_bd_port -dir I -type rst sys_rst create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr3 diff --git a/projects/usdrx1/zc706/system_constr.xdc b/projects/usdrx1/zc706/system_constr.xdc index e86c8c2d2..a162916e4 100644 --- a/projects/usdrx1/zc706/system_constr.xdc +++ b/projects/usdrx1/zc706/system_constr.xdc @@ -82,4 +82,4 @@ set_property -dict {PACKAGE_PIN AK17 IOSTANDARD LVCMOS25} [get_ports dac_data # clocks create_clock -name rx_ref_clk -period 12.50 [get_ports rx_ref_clk_p] -create_clock -name rx_div_clk -period 12.50 [get_nets i_system_wrapper/system_i/axi_usdrx1_gt_rx_clk] +create_clock -name rx_div_clk -period 12.50 [get_pins i_system_wrapper/system_i/util_usdrx1_xcvr/inst/i_xch_0/i_gtxe2_channel/RXOUTCLK] diff --git a/projects/usdrx1/zc706/system_project.tcl b/projects/usdrx1/zc706/system_project.tcl index e022ae874..30bcb0e78 100644 --- a/projects/usdrx1/zc706/system_project.tcl +++ b/projects/usdrx1/zc706/system_project.tcl @@ -10,9 +10,13 @@ adi_project_files usdrx1_zc706 [list \ "system_top.v" \ "system_constr.xdc" \ "../common/usdrx1_spi.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \ + "$ad_hdl_dir/library/common/ad_sysref_gen.v" \ "$ad_hdl_dir/projects/common/zc706/zc706_system_mig_constr.xdc" \ "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ] +set_property is_enabled false [get_files *system_axi*_spi*.xdc] + adi_project_run usdrx1_zc706 diff --git a/projects/usdrx1/zc706/system_top.v b/projects/usdrx1/zc706/system_top.v index f782ab0ae..334e6b354 100644 --- a/projects/usdrx1/zc706/system_top.v +++ b/projects/usdrx1/zc706/system_top.v @@ -246,34 +246,11 @@ module system_top ( wire rx_ref_clk; wire rx_sysref; wire rx_sync; - wire [511:0] adc_data; - wire [127:0] adc_data_0; - wire [127:0] adc_data_1; - wire [127:0] adc_data_2; - wire [127:0] adc_data_3; - wire adc_valid; - wire [ 7:0] adc_valid_0; - wire [ 7:0] adc_valid_1; - wire [ 7:0] adc_valid_2; - wire [ 7:0] adc_valid_3; - wire [ 7:0] adc_enable_0; - wire [ 7:0] adc_enable_1; - wire [ 7:0] adc_enable_2; - wire [ 7:0] adc_enable_3; - wire adc_dovf; - wire adc_dovf_0; - wire adc_dovf_1; - wire adc_dovf_2; - wire adc_dovf_3; - wire [255:0] gt_rx_data; - wire [63:0] gt_rx_data_0; - wire [63:0] gt_rx_data_1; - wire [63:0] gt_rx_data_2; - wire [63:0] gt_rx_data_3; wire [63:0] gpio_i; wire [63:0] gpio_o; wire [63:0] gpio_t; wire [15:0] ps_intrs; + wire rx_clk; // spi assignments @@ -290,31 +267,6 @@ module system_top ( assign spi_afe_clk = spi_clk; assign spi_clk_clk = spi_clk; - usdrx1_spi i_spi ( - .spi_afe_csn (spi_csn[4:1]), - .spi_clk_csn (spi_csn[0]), - .spi_clk (spi_clk), - .spi_mosi (spi_mosi), - .spi_miso (spi_miso), - .spi_afe_sdio (spi_afe_sdio), - .spi_clk_sdio (spi_clk_sdio)); - - // single dma for all channels - - assign gt_rx_data_3 = gt_rx_data[255:192]; - assign gt_rx_data_2 = gt_rx_data[191:128]; - assign gt_rx_data_1 = gt_rx_data[127: 64]; - assign gt_rx_data_0 = gt_rx_data[ 63: 0]; - - assign adc_data = {adc_data_3, adc_data_2, adc_data_1, adc_data_0}; - assign adc_valid = (|adc_valid_0) | (|adc_valid_1) | (|adc_valid_2) | (|adc_valid_3) ; - assign adc_dovf_0 = adc_dovf; - assign adc_dovf_1 = adc_dovf; - assign adc_dovf_2 = adc_dovf; - assign adc_dovf_3 = adc_dovf; - - // data interface - IBUFDS_GTE2 i_ibufds_rx_ref_clk ( .CEB (1'd0), .I (rx_ref_clk_p), @@ -332,40 +284,6 @@ module system_top ( .O (rx_sync_p), .OB (rx_sync_n)); - // gpio/control interface - - IOBUF i_iobuf_gpio_prc_sdo_q ( - .I (gpio_o[43]), - .O (gpio_i[43]), - .T (gpio_t[43]), - .IO (prc_sdo_q)); - - IOBUF i_iobuf_gpio_prc_sdo_i ( - .I (gpio_o[42]), - .O (gpio_i[42]), - .T (gpio_t[42]), - .IO (prc_sdo_i)); - - IOBUF i_iobuf_gpio_prc_cnv ( - .I (gpio_o[41]), - .O (gpio_i[41]), - .T (gpio_t[41]), - .IO (prc_cnv)); - - IOBUF i_iobuf_gpio_prc_sck ( - .I (gpio_o[40]), - .O (gpio_i[40]), - .T (gpio_t[40]), - .IO (prc_sck)); - - assign dac_sleep = gpio_o[44]; - assign amp_disbn = gpio_o[39]; - assign gpio_i[38] = clk_status; - assign clk_syncn = gpio_o[37]; - assign clk_resetn = gpio_o[36]; - assign afe_stby = gpio_o[35]; - assign afe_pdn = gpio_o[34]; - OBUFDS i_obufds_gpio_afe_trig ( .I (gpio_o[33]), .O (afe_trig_p), @@ -376,19 +294,44 @@ module system_top ( .O (afe_rst_p), .OB (afe_rst_n)); - genvar n; - generate - for (n = 0; n <= 13; n = n + 1) begin: g_iobuf_gpio_dac_data - assign dac_data[n] = gpio_o[45+n]; - end - for (n = 0; n <= 14; n = n + 1) begin: g_iobuf_gpio_bd - IOBUF i_iobuf_gpio_bd ( - .I (gpio_o[n]), - .O (gpio_i[n]), - .T (gpio_t[n]), - .IO (gpio_bd[n])); - end - endgenerate + assign dac_sleep = gpio_o[44]; + assign amp_disbn = gpio_o[39]; + assign gpio_i[38] = clk_status; + assign clk_syncn = gpio_o[37]; + assign clk_resetn = gpio_o[36]; + assign afe_stby = gpio_o[35]; + assign afe_pdn = gpio_o[34]; + + assign dac_data = gpio_o[59:45]; + + ad_iobuf #(.DATA_WIDTH(4)) i_iobuf_prc ( + .dio_t (gpio_t[43:40]), + .dio_i (gpio_o[43:40]), + .dio_o (gpio_i[43:40]), + .dio_p ({prc_sdo_q, + prc_sdo_i, + prc_cnv, + prc_sck})); + + ad_iobuf #(.DATA_WIDTH(15)) i_iobuf_bd ( + .dio_t (gpio_t[14:0]), + .dio_i (gpio_o[14:0]), + .dio_o (gpio_i[14:0]), + .dio_p (gpio_bd)); + + usdrx1_spi i_spi ( + .spi_afe_csn (spi_csn[4:1]), + .spi_clk_csn (spi_csn[0]), + .spi_clk (spi_clk), + .spi_mosi (spi_mosi), + .spi_miso (spi_miso), + .spi_afe_sdio (spi_afe_sdio), + .spi_clk_sdio (spi_clk_sdio)); + + ad_sysref_gen i_sysref ( + .core_clk (rx_clk), + .sysref_en (gpio_o[60]), + .sysref_out (rx_sysref)); system_wrapper i_system_wrapper ( .sys_clk_clk_n (sys_clk_n), @@ -433,30 +376,6 @@ module system_top ( .gpio_i (gpio_i), .gpio_o (gpio_o), .gpio_t (gpio_t), - .adc_data (adc_data), - .adc_data_0 (adc_data_0), - .adc_data_1 (adc_data_1), - .adc_data_2 (adc_data_2), - .adc_data_3 (adc_data_3), - .adc_wr_en(adc_valid), - .adc_valid_0 (adc_valid_0), - .adc_valid_1 (adc_valid_1), - .adc_valid_2 (adc_valid_2), - .adc_valid_3 (adc_valid_3), - .adc_enable_0 (adc_enable_0), - .adc_enable_1 (adc_enable_1), - .adc_enable_2 (adc_enable_2), - .adc_enable_3 (adc_enable_3), - .adc_dovf (adc_dovf), - .adc_dovf_0 (adc_dovf_0), - .adc_dovf_1 (adc_dovf_1), - .adc_dovf_2 (adc_dovf_2), - .adc_dovf_3 (adc_dovf_3), - .gt_rx_data (gt_rx_data), - .gt_rx_data_0 (gt_rx_data_0), - .gt_rx_data_1 (gt_rx_data_1), - .gt_rx_data_2 (gt_rx_data_2), - .gt_rx_data_3 (gt_rx_data_3), .hdmi_data (hdmi_data), .hdmi_data_e (hdmi_data_e), .hdmi_hsync (hdmi_hsync), @@ -476,11 +395,26 @@ module system_top ( .ps_intr_09 (1'b0), .ps_intr_10 (1'b0), .ps_intr_11 (1'b0), - .rx_data_n (rx_data_n), - .rx_data_p (rx_data_p), - .rx_ref_clk (rx_ref_clk), - .rx_sync (rx_sync), - .rx_sysref (rx_sysref), + .rx_data_0_n (rx_data_n[0]), + .rx_data_0_p (rx_data_p[0]), + .rx_data_1_n (rx_data_n[1]), + .rx_data_1_p (rx_data_p[1]), + .rx_data_2_n (rx_data_n[2]), + .rx_data_2_p (rx_data_p[2]), + .rx_data_3_n (rx_data_n[3]), + .rx_data_3_p (rx_data_p[3]), + .rx_data_4_n (rx_data_n[4]), + .rx_data_4_p (rx_data_p[4]), + .rx_data_5_n (rx_data_n[5]), + .rx_data_5_p (rx_data_p[5]), + .rx_data_6_n (rx_data_n[6]), + .rx_data_6_p (rx_data_p[6]), + .rx_data_7_n (rx_data_n[7]), + .rx_data_7_p (rx_data_p[7]), + .rx_ref_clk_0 (rx_ref_clk), + .rx_sync_0 (rx_sync), + .rx_sysref_0 (rx_sysref), + .rx_core_clk (rx_clk), .spdif (spdif), .spi_clk_i (spi_clk), .spi_clk_o (spi_clk), diff --git a/projects/usrpe31x/Makefile b/projects/usrpe31x/Makefile new file mode 100644 index 000000000..7e38ae702 --- /dev/null +++ b/projects/usrpe31x/Makefile @@ -0,0 +1,69 @@ +#################################################################################### +#################################################################################### +## Copyright 2011(c) Analog Devices, Inc. +## Auto-generated, do not modify! +#################################################################################### +#################################################################################### + +M_DEPS += system_top.v +M_DEPS += system_project.tcl +M_DEPS += system_constr.xdc +M_DEPS += system_bd.tcl +M_DEPS += ../scripts/adi_project.tcl +M_DEPS += ../scripts/adi_env.tcl +M_DEPS += ../scripts/adi_board.tcl +M_DEPS += ../../library/xilinx/common/ad_iobuf.v +M_DEPS += ../../library/axi_ad9361/axi_ad9361.xpr +M_DEPS += ../../library/axi_dmac/axi_dmac.xpr +M_DEPS += ../../library/util_cpack/util_cpack.xpr +M_DEPS += ../../library/util_tdd_sync/util_tdd_sync.xpr +M_DEPS += ../../library/util_upack/util_upack.xpr + +M_VIVADO := vivado -mode batch -source + +M_FLIST := *.cache +M_FLIST += *.data +M_FLIST += *.xpr +M_FLIST += *.log +M_FLIST += *.jou +M_FLIST += xgui +M_FLIST += *.runs +M_FLIST += *.srcs +M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim +M_FLIST += .Xil +M_FLIST += *.ip_user_files + + + +.PHONY: all lib clean clean-all +all: lib usrpe31x.sdk/system_top.hdf + + +clean: + rm -rf $(M_FLIST) + + +clean-all:clean + make -C ../../library/axi_ad9361 clean + make -C ../../library/axi_dmac clean + make -C ../../library/util_cpack clean + make -C ../../library/util_tdd_sync clean + make -C ../../library/util_upack clean + + +usrpe31x.sdk/system_top.hdf: $(M_DEPS) + -rm -rf $(M_FLIST) + $(M_VIVADO) system_project.tcl >> usrpe31x_vivado.log 2>&1 + + +lib: + make -C ../../library/axi_ad9361 + make -C ../../library/axi_dmac + make -C ../../library/util_cpack + make -C ../../library/util_tdd_sync + make -C ../../library/util_upack + +#################################################################################### +#################################################################################### diff --git a/projects/usrpe31x/system_bd.tcl b/projects/usrpe31x/system_bd.tcl new file mode 100644 index 000000000..bf5dbf721 --- /dev/null +++ b/projects/usrpe31x/system_bd.tcl @@ -0,0 +1,302 @@ +# create board design +# default ports + +create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr +create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 fixed_io + +create_bd_port -dir O spi0_csn_0 +create_bd_port -dir O spi0_csn_1 +create_bd_port -dir O spi0_csn_2 +create_bd_port -dir O spi0_clk +create_bd_port -dir O spi0_mosi +create_bd_port -dir I spi0_miso + +create_bd_port -dir I spi1_csn +create_bd_port -dir I spi1_clk +create_bd_port -dir I spi1_mosi +create_bd_port -dir O spi1_miso + +create_bd_port -dir I -from 63 -to 0 ps_gpio_i +create_bd_port -dir O -from 63 -to 0 ps_gpio_o +create_bd_port -dir O -from 63 -to 0 ps_gpio_t + +# interrupts + +create_bd_port -dir I -type intr ps_intr_00 +create_bd_port -dir I -type intr ps_intr_01 +create_bd_port -dir I -type intr ps_intr_02 +create_bd_port -dir I -type intr ps_intr_03 +create_bd_port -dir I -type intr ps_intr_04 +create_bd_port -dir I -type intr ps_intr_05 +create_bd_port -dir I -type intr ps_intr_06 +create_bd_port -dir I -type intr ps_intr_07 +create_bd_port -dir I -type intr ps_intr_08 +create_bd_port -dir I -type intr ps_intr_09 +create_bd_port -dir I -type intr ps_intr_10 +create_bd_port -dir I -type intr ps_intr_11 +create_bd_port -dir I -type intr ps_intr_12 +create_bd_port -dir I -type intr ps_intr_13 +create_bd_port -dir I -type intr ps_intr_14 +create_bd_port -dir I -type intr ps_intr_15 + +# instance: sys_ps7 + +set sys_ps7 [create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 sys_ps7] + +# ps7 settings + +set_property -dict [list CONFIG.PCW_PRESET_BANK0_VOLTAGE {LVCMOS 1.8V}] $sys_ps7 +set_property -dict [list CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 1.8V}] $sys_ps7 +set_property -dict [list CONFIG.PCW_USE_S_AXI_HP1 {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_USE_S_AXI_HP2 {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_EN_CLK1_PORT {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_EN_RST1_PORT {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100.0}] $sys_ps7 +set_property -dict [list CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ {200.0}] $sys_ps7 +set_property -dict [list CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_GPIO_MIO_GPIO_IO {MIO}] $sys_ps7 +set_property -dict [list CONFIG.PCW_ENET0_PERIPHERAL_ENABLE {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_ENET0_ENET0_IO {MIO 16 .. 27}] $sys_ps7 +set_property -dict [list CONFIG.PCW_ENET0_RESET_ENABLE {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_ENET0_RESET_IO {MIO 11}] $sys_ps7 +set_property -dict [list CONFIG.PCW_ENET0_GRP_MDIO_ENABLE {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_ENET0_GRP_MDIO_IO {MIO 52 .. 53}] $sys_ps7 +set_property -dict [list CONFIG.PCW_USB0_PERIPHERAL_ENABLE {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_USB0_USB0_IO {MIO 28 .. 39}] $sys_ps7 +set_property -dict [list CONFIG.PCW_USB0_RESET_ENABLE {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_USB0_RESET_IO {MIO 9}] $sys_ps7 +set_property -dict [list CONFIG.PCW_SD0_PERIPHERAL_ENABLE {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_SD0_SD0_IO {MIO 40 .. 45}] $sys_ps7 +set_property -dict [list CONFIG.PCW_SD0_GRP_CD_ENABLE {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_SD0_GRP_CD_IO {MIO 0}] $sys_ps7 +set_property -dict [list CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ {50}] $sys_ps7 +set_property -dict [list CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_SPI0_SPI0_IO {EMIO}] $sys_ps7 +set_property -dict [list CONFIG.PCW_SPI1_PERIPHERAL_ENABLE {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_SPI1_SPI1_IO {EMIO}] $sys_ps7 +set_property -dict [list CONFIG.PCW_UART0_PERIPHERAL_ENABLE {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_UART0_UART0_IO {MIO 14 .. 15}] $sys_ps7 +set_property -dict [list CONFIG.PCW_UART1_PERIPHERAL_ENABLE {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_UART1_UART1_IO {MIO 48 .. 49}] $sys_ps7 +set_property -dict [list CONFIG.PCW_I2C0_PERIPHERAL_ENABLE {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_I2C0_I2C0_IO {MIO 46 .. 47}] $sys_ps7 +set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_USE_FABRIC_INTERRUPT {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_IRQ_F2P_INTR {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_IRQ_F2P_MODE {REVERSE}] $sys_ps7 + +# DDR MT41K256M16 HA-125 (32M, 16bit, 8banks) + +set_property -dict [list CONFIG.PCW_UIPARAM_DDR_PARTNO {Custom}] $sys_ps7 +set_property -dict [list CONFIG.PCW_UIPARAM_DDR_BUS_WIDTH {32 Bit}] $sys_ps7 +set_property -dict [list CONFIG.PCW_UIPARAM_DDR_USE_INTERNAL_VREF {0}] $sys_ps7 +set_property -dict [list CONFIG.PCW_UIPARAM_DDR_DRAM_WIDTH {16 Bits}] $sys_ps7 +set_property -dict [list CONFIG.PCW_UIPARAM_DDR_DEVICE_CAPACITY {4096 MBits}] $sys_ps7 +set_property -dict [list CONFIG.PCW_UIPARAM_DDR_CWL {6}] $sys_ps7 +set_property -dict [list CONFIG.PCW_UIPARAM_DDR_T_RC {48.75}] $sys_ps7 +set_property -dict [list CONFIG.PCW_UIPARAM_DDR_T_RAS_MIN {35.0}] $sys_ps7 +set_property -dict [list CONFIG.PCW_UIPARAM_DDR_T_FAW {40.0}] $sys_ps7 +set_property -dict [list CONFIG.PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_UIPARAM_DDR_TRAIN_READ_GATE {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_UIPARAM_DDR_TRAIN_DATA_EYE {1}] $sys_ps7 + +set sys_concat_intc [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 sys_concat_intc] +set_property -dict [list CONFIG.NUM_PORTS {16}] $sys_concat_intc + +set sys_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 sys_rstgen] +set_property -dict [list CONFIG.C_EXT_RST_WIDTH {1}] $sys_rstgen + +# system reset/clock definitions + +ad_connect sys_cpu_clk sys_ps7/FCLK_CLK0 +ad_connect sys_200m_clk sys_ps7/FCLK_CLK1 +ad_connect sys_cpu_reset sys_rstgen/peripheral_reset +ad_connect sys_cpu_resetn sys_rstgen/peripheral_aresetn +ad_connect sys_cpu_clk sys_rstgen/slowest_sync_clk +ad_connect sys_rstgen/ext_reset_in sys_ps7/FCLK_RESET0_N + +# interface connections + +ad_connect ddr sys_ps7/DDR +ad_connect ps_gpio_i sys_ps7/GPIO_I +ad_connect ps_gpio_o sys_ps7/GPIO_O +ad_connect ps_gpio_t sys_ps7/GPIO_T +ad_connect fixed_io sys_ps7/FIXED_IO + +# spi connections + +ad_connect sys_ps7/SPI0_SS_O spi0_csn_0 +ad_connect sys_ps7/SPI0_SS1_O spi0_csn_1 +ad_connect sys_ps7/SPI0_SS2_O spi0_csn_2 +ad_connect sys_ps7/SPI0_SCLK_O spi0_clk +ad_connect sys_ps7/SPI0_MOSI_O spi0_mosi +ad_connect sys_ps7/SPI0_MISO_I spi0_miso +ad_connect sys_ps7/SPI0_SS_I VCC +ad_connect sys_ps7/SPI0_SCLK_I GND +ad_connect sys_ps7/SPI0_MOSI_I GND + +ad_connect sys_ps7/SPI1_SS_I spi1_csn +ad_connect sys_ps7/SPI1_SCLK_I spi1_clk +ad_connect sys_ps7/SPI1_MOSI_I spi1_mosi +ad_connect sys_ps7/SPI1_MISO_O spi1_miso +ad_connect sys_ps7/SPI1_MISO_I GND + +# interrupts + +ad_connect sys_concat_intc/dout sys_ps7/IRQ_F2P +ad_connect sys_concat_intc/In15 ps_intr_15 +ad_connect sys_concat_intc/In14 ps_intr_14 +ad_connect sys_concat_intc/In13 ps_intr_13 +ad_connect sys_concat_intc/In12 ps_intr_12 +ad_connect sys_concat_intc/In11 ps_intr_11 +ad_connect sys_concat_intc/In10 ps_intr_10 +ad_connect sys_concat_intc/In9 ps_intr_09 +ad_connect sys_concat_intc/In8 ps_intr_08 +ad_connect sys_concat_intc/In7 ps_intr_07 +ad_connect sys_concat_intc/In6 ps_intr_06 +ad_connect sys_concat_intc/In5 ps_intr_05 +ad_connect sys_concat_intc/In4 ps_intr_04 +ad_connect sys_concat_intc/In3 ps_intr_03 +ad_connect sys_concat_intc/In2 ps_intr_02 +ad_connect sys_concat_intc/In1 ps_intr_01 +ad_connect sys_concat_intc/In0 ps_intr_00 + +# ad9361 + +create_bd_port -dir I rx_clk_in +create_bd_port -dir I rx_frame_in +create_bd_port -dir I -from 11 -to 0 rx_data_in + +create_bd_port -dir O tx_clk_out +create_bd_port -dir O tx_frame_out +create_bd_port -dir O -from 11 -to 0 tx_data_out + +create_bd_port -dir O enable +create_bd_port -dir O txnrx +create_bd_port -dir I up_enable +create_bd_port -dir I up_txnrx + +# ad9361 core(s) + +set axi_ad9361 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9361:1.0 axi_ad9361] +set_property -dict [list CONFIG.ID {0}] $axi_ad9361 +set_property -dict [list CONFIG.CMOS_OR_LVDS_N {1}] $axi_ad9361 + +set axi_ad9361_dac_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9361_dac_dma] +set_property -dict [list CONFIG.DMA_TYPE_SRC {0}] $axi_ad9361_dac_dma +set_property -dict [list CONFIG.DMA_TYPE_DEST {2}] $axi_ad9361_dac_dma +set_property -dict [list CONFIG.CYCLIC {1}] $axi_ad9361_dac_dma +set_property -dict [list CONFIG.SYNC_TRANSFER_START {0}] $axi_ad9361_dac_dma +set_property -dict [list CONFIG.AXI_SLICE_SRC {0}] $axi_ad9361_dac_dma +set_property -dict [list CONFIG.AXI_SLICE_DEST {1}] $axi_ad9361_dac_dma +set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9361_dac_dma +set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {32}] $axi_ad9361_dac_dma + +set util_ad9361_dac_upack [create_bd_cell -type ip -vlnv analog.com:user:util_upack:1.0 util_ad9361_dac_upack] +set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $util_ad9361_dac_upack +set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {16}] $util_ad9361_dac_upack + +set axi_ad9361_adc_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9361_adc_dma] +set_property -dict [list CONFIG.DMA_TYPE_SRC {2}] $axi_ad9361_adc_dma +set_property -dict [list CONFIG.DMA_TYPE_DEST {0}] $axi_ad9361_adc_dma +set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad9361_adc_dma +set_property -dict [list CONFIG.SYNC_TRANSFER_START {1}] $axi_ad9361_adc_dma +set_property -dict [list CONFIG.AXI_SLICE_SRC {0}] $axi_ad9361_adc_dma +set_property -dict [list CONFIG.AXI_SLICE_DEST {0}] $axi_ad9361_adc_dma +set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9361_adc_dma +set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {32}] $axi_ad9361_adc_dma + +set util_ad9361_adc_pack [create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 util_ad9361_adc_pack] +set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $util_ad9361_adc_pack +set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {16}] $util_ad9361_adc_pack + +# connections + +ad_connect rx_clk_in axi_ad9361/rx_clk_in +ad_connect rx_frame_in axi_ad9361/rx_frame_in +ad_connect rx_data_in axi_ad9361/rx_data_in +ad_connect tx_clk_out axi_ad9361/tx_clk_out +ad_connect tx_frame_out axi_ad9361/tx_frame_out +ad_connect tx_data_out axi_ad9361/tx_data_out +ad_connect enable axi_ad9361/enable +ad_connect txnrx axi_ad9361/txnrx +ad_connect up_enable axi_ad9361/up_enable +ad_connect up_txnrx axi_ad9361/up_txnrx + +ad_connect sys_200m_clk axi_ad9361/delay_clk +ad_connect axi_ad9361/l_clk axi_ad9361/clk + +ad_connect axi_ad9361/l_clk util_ad9361_adc_pack/adc_clk +ad_connect axi_ad9361/rst util_ad9361_adc_pack/adc_rst +ad_connect axi_ad9361/adc_enable_i0 util_ad9361_adc_pack/adc_enable_0 +ad_connect axi_ad9361/adc_valid_i0 util_ad9361_adc_pack/adc_valid_0 +ad_connect axi_ad9361/adc_data_i0 util_ad9361_adc_pack/adc_data_0 +ad_connect axi_ad9361/adc_enable_q0 util_ad9361_adc_pack/adc_enable_1 +ad_connect axi_ad9361/adc_valid_q0 util_ad9361_adc_pack/adc_valid_1 +ad_connect axi_ad9361/adc_data_q0 util_ad9361_adc_pack/adc_data_1 +ad_connect axi_ad9361/l_clk axi_ad9361_adc_dma/fifo_wr_clk +ad_connect util_ad9361_adc_pack/adc_valid axi_ad9361_adc_dma/fifo_wr_en +ad_connect util_ad9361_adc_pack/adc_sync axi_ad9361_adc_dma/fifo_wr_sync +ad_connect util_ad9361_adc_pack/adc_data axi_ad9361_adc_dma/fifo_wr_din +ad_connect axi_ad9361_adc_dma/fifo_wr_overflow axi_ad9361/adc_dovf +ad_connect axi_ad9361/l_clk util_ad9361_dac_upack/dac_clk +ad_connect axi_ad9361/dac_enable_i0 util_ad9361_dac_upack/dac_enable_0 +ad_connect axi_ad9361/dac_valid_i0 util_ad9361_dac_upack/dac_valid_0 +ad_connect util_ad9361_dac_upack/dac_data_0 axi_ad9361/dac_data_i0 +ad_connect axi_ad9361/dac_enable_q0 util_ad9361_dac_upack/dac_enable_1 +ad_connect axi_ad9361/dac_valid_q0 util_ad9361_dac_upack/dac_valid_1 +ad_connect util_ad9361_dac_upack/dac_data_1 axi_ad9361/dac_data_q0 +ad_connect axi_ad9361/l_clk axi_ad9361_dac_dma/fifo_rd_clk +ad_connect util_ad9361_dac_upack/dac_valid axi_ad9361_dac_dma/fifo_rd_en +ad_connect axi_ad9361_dac_dma/fifo_rd_dout util_ad9361_dac_upack/dac_data +ad_connect axi_ad9361_dac_dma/fifo_rd_underflow axi_ad9361/dac_dunf +ad_connect axi_ad9361/dac_data_i1 GND +ad_connect axi_ad9361/dac_data_q1 GND + +# interconnects + +ad_cpu_interconnect 0x79020000 axi_ad9361 +ad_cpu_interconnect 0x7C400000 axi_ad9361_adc_dma +ad_cpu_interconnect 0x7C420000 axi_ad9361_dac_dma +ad_mem_hp1_interconnect sys_cpu_clk sys_ps7/S_AXI_HP1 +ad_mem_hp1_interconnect sys_cpu_clk axi_ad9361_adc_dma/m_dest_axi +ad_mem_hp2_interconnect sys_cpu_clk sys_ps7/S_AXI_HP2 +ad_mem_hp2_interconnect sys_cpu_clk axi_ad9361_dac_dma/m_src_axi +ad_connect sys_cpu_resetn axi_ad9361_adc_dma/m_dest_axi_aresetn +ad_connect sys_cpu_resetn axi_ad9361_dac_dma/m_src_axi_aresetn + +# interrupts + +ad_cpu_interrupt ps-13 mb-13 axi_ad9361_adc_dma/irq +ad_cpu_interrupt ps-12 mb-12 axi_ad9361_dac_dma/irq + +# tdd-sync + +set util_ad9361_tdd_sync [create_bd_cell -type ip -vlnv analog.com:user:util_tdd_sync:1.0 util_ad9361_tdd_sync] +set_property -dict [list CONFIG.TDD_SYNC_PERIOD {10000000}] $util_ad9361_tdd_sync + +create_bd_port -dir I tdd_sync + +ad_connect tdd_sync util_ad9361_tdd_sync/sync_in +ad_connect sys_cpu_clk util_ad9361_tdd_sync/clk +ad_connect sys_cpu_resetn util_ad9361_tdd_sync/rstn +ad_connect util_ad9361_tdd_sync/sync_out axi_ad9361/tdd_sync +ad_connect util_ad9361_tdd_sync/sync_mode axi_ad9361/tdd_sync_cntr + +# gpio + +create_bd_port -dir I -from 31 -to 0 pl_gpio_i +create_bd_port -dir O -from 31 -to 0 pl_gpio_o +create_bd_port -dir O -from 31 -to 0 pl_gpio_t + +set axi_gpio [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio] +set_property -dict [list CONFIG.C_GPIO_WIDTH {32}] $axi_gpio +set_property -dict [list CONFIG.C_INTERRUPT_PRESENT {1}] $axi_gpio + +ad_connect pl_gpio_i axi_gpio/gpio_io_i +ad_connect pl_gpio_o axi_gpio/gpio_io_o +ad_connect pl_gpio_t axi_gpio/gpio_io_t + +ad_cpu_interconnect 0x41600000 axi_gpio +ad_cpu_interrupt ps-15 mb-15 axi_gpio/ip2intc_irpt + diff --git a/projects/usrpe31x/system_constr.xdc b/projects/usrpe31x/system_constr.xdc new file mode 100644 index 000000000..5c79afb70 --- /dev/null +++ b/projects/usrpe31x/system_constr.xdc @@ -0,0 +1,157 @@ + +# ad9361 (SWAP == 0x1) + +set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVCMOS18} [get_ports rx_clk_in] +set_property -dict {PACKAGE_PIN N18 IOSTANDARD LVCMOS18} [get_ports rx_frame_in] +set_property -dict {PACKAGE_PIN L16 IOSTANDARD LVCMOS18} [get_ports rx_data_in[0]] +set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVCMOS18} [get_ports rx_data_in[1]] +set_property -dict {PACKAGE_PIN L17 IOSTANDARD LVCMOS18} [get_ports rx_data_in[2]] +set_property -dict {PACKAGE_PIN J17 IOSTANDARD LVCMOS18} [get_ports rx_data_in[3]] +set_property -dict {PACKAGE_PIN M16 IOSTANDARD LVCMOS18} [get_ports rx_data_in[4]] +set_property -dict {PACKAGE_PIN J15 IOSTANDARD LVCMOS18} [get_ports rx_data_in[5]] +set_property -dict {PACKAGE_PIN K16 IOSTANDARD LVCMOS18} [get_ports rx_data_in[6]] +set_property -dict {PACKAGE_PIN J16 IOSTANDARD LVCMOS18} [get_ports rx_data_in[7]] +set_property -dict {PACKAGE_PIN N20 IOSTANDARD LVCMOS18} [get_ports rx_data_in[8]] +set_property -dict {PACKAGE_PIN K15 IOSTANDARD LVCMOS18} [get_ports rx_data_in[9]] +set_property -dict {PACKAGE_PIN N17 IOSTANDARD LVCMOS18} [get_ports rx_data_in[10]] +set_property -dict {PACKAGE_PIN M17 IOSTANDARD LVCMOS18} [get_ports rx_data_in[11]] + +set_property -dict {PACKAGE_PIN R21 IOSTANDARD LVCMOS18} [get_ports tx_clk_out] +set_property -dict {PACKAGE_PIN P22 IOSTANDARD LVCMOS18} [get_ports tx_frame_out] +set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVCMOS18} [get_ports tx_data_out[0]] +set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVCMOS18} [get_ports tx_data_out[1]] +set_property -dict {PACKAGE_PIN P20 IOSTANDARD LVCMOS18} [get_ports tx_data_out[2]] +set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS18} [get_ports tx_data_out[3]] +set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS18} [get_ports tx_data_out[4]] +set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS18} [get_ports tx_data_out[5]] +set_property -dict {PACKAGE_PIN R20 IOSTANDARD LVCMOS18} [get_ports tx_data_out[6]] +set_property -dict {PACKAGE_PIN P21 IOSTANDARD LVCMOS18} [get_ports tx_data_out[7]] +set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVCMOS18} [get_ports tx_data_out[8]] +set_property -dict {PACKAGE_PIN T17 IOSTANDARD LVCMOS18} [get_ports tx_data_out[9]] +set_property -dict {PACKAGE_PIN N22 IOSTANDARD LVCMOS18} [get_ports tx_data_out[10]] +set_property -dict {PACKAGE_PIN N15 IOSTANDARD LVCMOS18} [get_ports tx_data_out[11]] + +set_property -dict {PACKAGE_PIN AB4 IOSTANDARD LVCMOS18} [get_ports enable] +set_property -dict {PACKAGE_PIN AB1 IOSTANDARD LVCMOS18} [get_ports txnrx] +set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVCMOS18} [get_ports out_clk] + +set_property -dict {PACKAGE_PIN U11 IOSTANDARD LVCMOS18} [get_ports gpio_resetb] +set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVCMOS18} [get_ports gpio_sync] +set_property -dict {PACKAGE_PIN AB2 IOSTANDARD LVCMOS18} [get_ports gpio_en_agc] +set_property -dict {PACKAGE_PIN V4 IOSTANDARD LVCMOS18} [get_ports gpio_ctl[0]] +set_property -dict {PACKAGE_PIN V5 IOSTANDARD LVCMOS18} [get_ports gpio_ctl[1]] +set_property -dict {PACKAGE_PIN U5 IOSTANDARD LVCMOS18} [get_ports gpio_ctl[2]] +set_property -dict {PACKAGE_PIN U6 IOSTANDARD LVCMOS18} [get_ports gpio_ctl[3]] +set_property -dict {PACKAGE_PIN AB5 IOSTANDARD LVCMOS18} [get_ports gpio_status[0]] +set_property -dict {PACKAGE_PIN AB6 IOSTANDARD LVCMOS18} [get_ports gpio_status[1]] +set_property -dict {PACKAGE_PIN AB7 IOSTANDARD LVCMOS18} [get_ports gpio_status[2]] +set_property -dict {PACKAGE_PIN AA4 IOSTANDARD LVCMOS18} [get_ports gpio_status[3]] +set_property -dict {PACKAGE_PIN K20 IOSTANDARD LVCMOS18} [get_ports gpio_status[4]] +set_property -dict {PACKAGE_PIN L19 IOSTANDARD LVCMOS18} [get_ports gpio_status[5]] +set_property -dict {PACKAGE_PIN V12 IOSTANDARD LVCMOS18} [get_ports gpio_status[6]] +set_property -dict {PACKAGE_PIN W12 IOSTANDARD LVCMOS18} [get_ports gpio_status[7]] + +# not-connected? + +set_property -dict {PACKAGE_PIN R18 IOSTANDARD LVCMOS18} [get_ports gpio_rf[0]] +set_property -dict {PACKAGE_PIN T18 IOSTANDARD LVCMOS18} [get_ports gpio_rf[1]] +set_property -dict {PACKAGE_PIN M15 IOSTANDARD LVCMOS18} [get_ports gpio_rf[2]] +set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS18} [get_ports gpio_rf[3]] +set_property -dict {PACKAGE_PIN J20 IOSTANDARD LVCMOS18} [get_ports gpio_rf[4]] +set_property -dict {PACKAGE_PIN K19 IOSTANDARD LVCMOS18} [get_ports gpio_rf[5]] +set_property -dict {PACKAGE_PIN AB12 IOSTANDARD LVCMOS18} [get_ports gpio_rf[6]] +set_property -dict {PACKAGE_PIN T6 IOSTANDARD LVCMOS18} [get_ports gpio_rf[7]] +set_property -dict {PACKAGE_PIN R6 IOSTANDARD LVCMOS18} [get_ports gpio_rf[8]] + +# forwarded clocks (not-connected?) + +set_property -dict {PACKAGE_PIN U4 IOSTANDARD LVCMOS18} [get_ports gpio_tcxo_clk] +set_property -dict {PACKAGE_PIN T4 IOSTANDARD LVCMOS18} [get_ports gpio_out_clk] + +# spi + +set_property -dict {PACKAGE_PIN W6 IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports spi_csn] +set_property -dict {PACKAGE_PIN W5 IOSTANDARD LVCMOS18} [get_ports spi_clk] +set_property -dict {PACKAGE_PIN V7 IOSTANDARD LVCMOS18} [get_ports spi_mosi] +set_property -dict {PACKAGE_PIN W7 IOSTANDARD LVCMOS18} [get_ports spi_miso] + +create_clock -name rx_clk -period 16 [get_ports rx_clk_in] + +# rf filter selects + +set_property -dict {PACKAGE_PIN F22 IOSTANDARD LVCMOS33} [get_ports tx_bandsel[0]] +set_property -dict {PACKAGE_PIN F21 IOSTANDARD LVCMOS33} [get_ports tx_bandsel[1]] +set_property -dict {PACKAGE_PIN H19 IOSTANDARD LVCMOS33} [get_ports tx_bandsel[2]] +set_property -dict {PACKAGE_PIN E19 IOSTANDARD LVCMOS33} [get_ports rx_bandsel_1[0]] +set_property -dict {PACKAGE_PIN G21 IOSTANDARD LVCMOS33} [get_ports rx_bandsel_1[1]] +set_property -dict {PACKAGE_PIN G20 IOSTANDARD LVCMOS33} [get_ports rx_bandsel_1[2]] +set_property -dict {PACKAGE_PIN F19 IOSTANDARD LVCMOS33} [get_ports rx_bandsel_1b[0]] +set_property -dict {PACKAGE_PIN G19 IOSTANDARD LVCMOS33} [get_ports rx_bandsel_1b[1]] +set_property -dict {PACKAGE_PIN A19 IOSTANDARD LVCMOS33} [get_ports rx_bandsel_1c[0]] +set_property -dict {PACKAGE_PIN B15 IOSTANDARD LVCMOS33} [get_ports rx_bandsel_1c[1]] +set_property -dict {PACKAGE_PIN AB9 IOSTANDARD LVCMOS18} [get_ports rx_bandsel_2[0]] +set_property -dict {PACKAGE_PIN AA9 IOSTANDARD LVCMOS18} [get_ports rx_bandsel_2[1]] +set_property -dict {PACKAGE_PIN AA8 IOSTANDARD LVCMOS18} [get_ports rx_bandsel_2[2]] +set_property -dict {PACKAGE_PIN Y4 IOSTANDARD LVCMOS18} [get_ports rx_bandsel_2b[0]] +set_property -dict {PACKAGE_PIN U9 IOSTANDARD LVCMOS18} [get_ports rx_bandsel_2b[1]] +set_property -dict {PACKAGE_PIN Y10 IOSTANDARD LVCMOS18} [get_ports rx_bandsel_2c[0]] +set_property -dict {PACKAGE_PIN U10 IOSTANDARD LVCMOS18} [get_ports rx_bandsel_2c[1]] + +# rf enables + +set_property -dict {PACKAGE_PIN G22 IOSTANDARD LVCMOS33} [get_ports tx_enable_1a] +set_property -dict {PACKAGE_PIN H22 IOSTANDARD LVCMOS33} [get_ports tx_enable_2a] +set_property -dict {PACKAGE_PIN A17 IOSTANDARD LVCMOS33} [get_ports tx_enable_1b] +set_property -dict {PACKAGE_PIN B16 IOSTANDARD LVCMOS33} [get_ports tx_enable_2b] + +# antennae selects + +set_property -dict {PACKAGE_PIN C15 IOSTANDARD LVCMOS33} [get_ports txrx1_antsel_v1] +set_property -dict {PACKAGE_PIN B17 IOSTANDARD LVCMOS33} [get_ports txrx1_antsel_v2] +set_property -dict {PACKAGE_PIN A16 IOSTANDARD LVCMOS33} [get_ports txrx2_antsel_v1] +set_property -dict {PACKAGE_PIN E20 IOSTANDARD LVCMOS33} [get_ports txrx2_antsel_v2] +set_property -dict {PACKAGE_PIN E18 IOSTANDARD LVCMOS33} [get_ports rx1_antsel_v1] +set_property -dict {PACKAGE_PIN F18 IOSTANDARD LVCMOS33} [get_ports rx1_antsel_v2] +set_property -dict {PACKAGE_PIN F17 IOSTANDARD LVCMOS33} [get_ports rx2_antsel_v1] +set_property -dict {PACKAGE_PIN G17 IOSTANDARD LVCMOS33} [get_ports rx2_antsel_v2] + +# fancy stuff + +set_property -dict {PACKAGE_PIN Y11 IOSTANDARD LVCMOS18} [get_ports txrx1_tx_led] +set_property -dict {PACKAGE_PIN AB10 IOSTANDARD LVCMOS18} [get_ports txrx1_rx_led] +set_property -dict {PACKAGE_PIN U12 IOSTANDARD LVCMOS18} [get_ports txrx2_tx_led] +set_property -dict {PACKAGE_PIN AB11 IOSTANDARD LVCMOS18} [get_ports txrx2_rx_led] +set_property -dict {PACKAGE_PIN AA12 IOSTANDARD LVCMOS18} [get_ports rx1_rx_led] +set_property -dict {PACKAGE_PIN AA11 IOSTANDARD LVCMOS18} [get_ports rx2_rx_led] + +# xtal tuning (ad5662) + +set_property -dict {PACKAGE_PIN K21 IOSTANDARD LVCMOS18} [get_ports tcxo_dac_csn] +set_property -dict {PACKAGE_PIN L22 IOSTANDARD LVCMOS18} [get_ports tcxo_dac_clk] +set_property -dict {PACKAGE_PIN L21 IOSTANDARD LVCMOS18} [get_ports tcxo_dac_mosi] +set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVCMOS18} [get_ports tcxo_clk] + +# board power + +set_property -dict {PACKAGE_PIN A22 IOSTANDARD LVCMOS33} [get_ports avr_csn] +set_property -dict {PACKAGE_PIN D22 IOSTANDARD LVCMOS33} [get_ports avr_clk] +set_property -dict {PACKAGE_PIN A21 IOSTANDARD LVCMOS33} [get_ports avr_mosi] +set_property -dict {PACKAGE_PIN C22 IOSTANDARD LVCMOS33} [get_ports avr_miso] +set_property -dict {PACKAGE_PIN B22 IOSTANDARD LVCMOS33} [get_ports avr_irq] + +set_property -dict {PACKAGE_PIN E21 IOSTANDARD LVCMOS33} [get_ports pwr_switch] + +# gps-sync + +set_property -dict {PACKAGE_PIN Y9 IOSTANDARD LVCMOS18} [get_ports pps_gps] +set_property -dict {PACKAGE_PIN D18 IOSTANDARD LVCMOS33} [get_ports pps_ext] + +# board-gpio + +set_property -dict {PACKAGE_PIN E16 IOSTANDARD LVCMOS33} [get_ports gpio_bd[0]] +set_property -dict {PACKAGE_PIN C18 IOSTANDARD LVCMOS33} [get_ports gpio_bd[1]] +set_property -dict {PACKAGE_PIN D17 IOSTANDARD LVCMOS33} [get_ports gpio_bd[2]] +set_property -dict {PACKAGE_PIN D16 IOSTANDARD LVCMOS33} [get_ports gpio_bd[3]] +set_property -dict {PACKAGE_PIN D15 IOSTANDARD LVCMOS33} [get_ports gpio_bd[4]] +set_property -dict {PACKAGE_PIN E15 IOSTANDARD LVCMOS33} [get_ports gpio_bd[5]] + diff --git a/projects/usrpe31x/system_project.tcl b/projects/usrpe31x/system_project.tcl new file mode 100644 index 000000000..4586ed0c6 --- /dev/null +++ b/projects/usrpe31x/system_project.tcl @@ -0,0 +1,16 @@ + +source ../scripts/adi_env.tcl +source $ad_hdl_dir/projects/scripts/adi_project.tcl +source $ad_hdl_dir/projects/scripts/adi_board.tcl + +set p_device "xc7z020clg484-1" +adi_project_create usrpe31x + +adi_project_files usrpe31x [list \ + "system_top.v" \ + "system_constr.xdc" \ + "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v"] + +adi_project_run usrpe31x + + diff --git a/projects/usrpe31x/system_top.v b/projects/usrpe31x/system_top.v new file mode 100644 index 000000000..dc7238fe5 --- /dev/null +++ b/projects/usrpe31x/system_top.v @@ -0,0 +1,311 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top ( + + inout [14:0] ddr_addr, + inout [ 2:0] ddr_ba, + inout ddr_cas_n, + inout ddr_ck_n, + inout ddr_ck_p, + inout ddr_cke, + inout ddr_cs_n, + inout [ 3:0] ddr_dm, + inout [31:0] ddr_dq, + inout [ 3:0] ddr_dqs_n, + inout [ 3:0] ddr_dqs_p, + inout ddr_odt, + inout ddr_ras_n, + inout ddr_reset_n, + inout ddr_we_n, + + inout fixed_io_ddr_vrn, + inout fixed_io_ddr_vrp, + inout [53:0] fixed_io_mio, + inout fixed_io_ps_clk, + inout fixed_io_ps_porb, + inout fixed_io_ps_srstb, + + input rx_clk_in, + input rx_frame_in, + input [11:0] rx_data_in, + output tx_clk_out, + output tx_frame_out, + output [11:0] tx_data_out, + + output enable, + output txnrx, + input out_clk, + + output gpio_resetb, + output gpio_sync, + output gpio_en_agc, + output [ 3:0] gpio_ctl, + input [ 7:0] gpio_status, + inout [ 8:0] gpio_rf, + output gpio_tcxo_clk, + output gpio_out_clk, + + output spi_csn, + output spi_clk, + output spi_mosi, + input spi_miso, + + output [ 2:0] tx_bandsel, + output [ 2:0] rx_bandsel_1, + output [ 1:0] rx_bandsel_1b, + output [ 1:0] rx_bandsel_1c, + output [ 2:0] rx_bandsel_2, + output [ 1:0] rx_bandsel_2b, + output [ 1:0] rx_bandsel_2c, + + output tx_enable_1a, + output tx_enable_2a, + output tx_enable_1b, + output tx_enable_2b, + + output txrx1_antsel_v1, + output txrx1_antsel_v2, + output txrx2_antsel_v1, + output txrx2_antsel_v2, + output rx1_antsel_v1, + output rx1_antsel_v2, + output rx2_antsel_v1, + output rx2_antsel_v2, + + output txrx1_tx_led, + output txrx1_rx_led, + output txrx2_tx_led, + output txrx2_rx_led, + output rx1_rx_led, + output rx2_rx_led, + + output tcxo_dac_csn, + output tcxo_dac_clk, + output tcxo_dac_mosi, + input tcxo_clk, + + input avr_csn, + input avr_clk, + input avr_mosi, + output avr_miso, + output avr_irq, + + input pwr_switch, + + input pps_gps, + input pps_ext, + + inout [ 5:0] gpio_bd); + + // internal signals + + wire pps_s; + wire [31:0] pl_gpio_i; + wire [31:0] pl_gpio_o; + wire [31:0] pl_gpio_t; + wire [63:0] ps_gpio_i; + wire [63:0] ps_gpio_o; + wire [63:0] ps_gpio_t; + + // assignments + + assign pps_s = pps_gps | pps_ext; + assign tcxo_dac_clk = spi_clk; + assign tcxo_dac_mosi = spi_mosi; + + // gpio-rf (pl) + + assign gpio_tcxo_clk = tcxo_clk; + assign gpio_out_clk = out_clk; + assign pl_gpio_i[31:9] = pl_gpio_o[31:9]; + + ad_iobuf #(.DATA_WIDTH(9)) i_iobuf_rf ( + .dio_t (pl_gpio_t[8:0]), + .dio_i (pl_gpio_o[8:0]), + .dio_o (pl_gpio_i[8:0]), + .dio_p (gpio_rf)); + + // gpio[63:56] - antennae selects + + assign ps_gpio_i[63:56] = ps_gpio_o[63:56]; + assign txrx1_antsel_v1 = ps_gpio_o[63]; + assign txrx1_antsel_v2 = ps_gpio_o[62]; + assign txrx2_antsel_v1 = ps_gpio_o[61]; + assign txrx2_antsel_v2 = ps_gpio_o[60]; + assign rx1_antsel_v1 = ps_gpio_o[59]; + assign rx1_antsel_v2 = ps_gpio_o[58]; + assign rx2_antsel_v1 = ps_gpio_o[57]; + assign rx2_antsel_v2 = ps_gpio_o[56]; + + // gpio[55:48] - antennae leds + + assign ps_gpio_i[55:49] = ps_gpio_o[55:49]; + assign txrx1_tx_led = ps_gpio_o[55]; + assign txrx1_rx_led = ps_gpio_o[54]; + assign txrx2_tx_led = ps_gpio_o[53]; + assign txrx2_rx_led = ps_gpio_o[52]; + assign rx1_rx_led = ps_gpio_o[51]; + assign rx2_rx_led = ps_gpio_o[50]; + + // gpio[48:32] - ad9361 + + assign ps_gpio_i[48:44] = ps_gpio_o[48:44]; + assign gpio_resetb = ps_gpio_o[46]; + assign gpio_sync = ps_gpio_o[45]; + assign gpio_en_agc = ps_gpio_o[44]; + + assign ps_gpio_i[43:40] = ps_gpio_o[43:40]; + assign gpio_ctl = ps_gpio_o[43:40]; + + assign ps_gpio_i[39:32] = gpio_status; + + // gpio[31:28] - tx_enable + + assign ps_gpio_i[31:28] = ps_gpio_o[31:28]; + + assign tx_enable_1a = ps_gpio_o[31]; + assign tx_enable_2a = ps_gpio_o[30]; + assign tx_enable_1b = ps_gpio_o[29]; + assign tx_enable_2b = ps_gpio_o[28]; + + // gpio[27:24] - tx_bandsel + + assign ps_gpio_i[27:24] = ps_gpio_o[27:24]; + + assign tx_bandsel = ps_gpio_o[26:24]; + + // gpio[23:16] - rx_bandsel(1) + + assign ps_gpio_i[23:16] = ps_gpio_o[23:16]; + + assign rx_bandsel_1 = ps_gpio_o[22:20]; + assign rx_bandsel_1b = ps_gpio_o[19:18]; + assign rx_bandsel_1c = ps_gpio_o[17:16]; + + // gpio[15:8] - rx_bandsel(2) + + assign ps_gpio_i[15:8] = ps_gpio_o[15:8]; + + assign rx_bandsel_2 = ps_gpio_o[14:12]; + assign rx_bandsel_2b = ps_gpio_o[11:10]; + assign rx_bandsel_2c = ps_gpio_o[9:8]; + + // gpio[7:0] - board stuff (+ pwr_switch, avr_irq) + + assign ps_gpio_i[7] = ps_gpio_o[7]; + assign avr_irq = ps_gpio_o[7]; + + assign ps_gpio_i[6] = pwr_switch; + + ad_iobuf #(.DATA_WIDTH(6)) i_iobuf_bd ( + .dio_t (ps_gpio_t[5:0]), + .dio_i (ps_gpio_o[5:0]), + .dio_o (ps_gpio_i[5:0]), + .dio_p (gpio_bd)); + + // instantiations + + system_wrapper i_system_wrapper ( + .ddr_addr (ddr_addr), + .ddr_ba (ddr_ba), + .ddr_cas_n (ddr_cas_n), + .ddr_ck_n (ddr_ck_n), + .ddr_ck_p (ddr_ck_p), + .ddr_cke (ddr_cke), + .ddr_cs_n (ddr_cs_n), + .ddr_dm (ddr_dm), + .ddr_dq (ddr_dq), + .ddr_dqs_n (ddr_dqs_n), + .ddr_dqs_p (ddr_dqs_p), + .ddr_odt (ddr_odt), + .ddr_ras_n (ddr_ras_n), + .ddr_reset_n (ddr_reset_n), + .ddr_we_n (ddr_we_n), + .enable (enable), + .fixed_io_ddr_vrn (fixed_io_ddr_vrn), + .fixed_io_ddr_vrp (fixed_io_ddr_vrp), + .fixed_io_mio (fixed_io_mio), + .fixed_io_ps_clk (fixed_io_ps_clk), + .fixed_io_ps_porb (fixed_io_ps_porb), + .fixed_io_ps_srstb (fixed_io_ps_srstb), + .pl_gpio_i (pl_gpio_i), + .pl_gpio_o (pl_gpio_o), + .pl_gpio_t (pl_gpio_t), + .ps_gpio_i (ps_gpio_i), + .ps_gpio_o (ps_gpio_o), + .ps_gpio_t (ps_gpio_t), + .ps_intr_00 (1'b0), + .ps_intr_01 (1'b0), + .ps_intr_02 (1'b0), + .ps_intr_03 (1'b0), + .ps_intr_04 (1'b0), + .ps_intr_05 (1'b0), + .ps_intr_06 (1'b0), + .ps_intr_07 (1'b0), + .ps_intr_08 (1'b0), + .ps_intr_09 (1'b0), + .ps_intr_10 (1'b0), + .ps_intr_11 (1'b0), + .ps_intr_14 (1'b0), + .rx_clk_in (rx_clk_in), + .rx_data_in (rx_data_in), + .rx_frame_in (rx_frame_in), + .spi0_clk (spi_clk), + .spi0_csn_0 (spi_csn), + .spi0_csn_1 (tcxo_dac_csn), + .spi0_csn_2 (), + .spi0_miso (spi_miso), + .spi0_mosi (spi_mosi), + .spi1_clk (avr_clk), + .spi1_csn (avr_csn), + .spi1_miso (avr_miso), + .spi1_mosi (avr_mosi), + .tdd_sync (pps_s), + .tx_clk_out (tx_clk_out), + .tx_data_out (tx_data_out), + .tx_frame_out (tx_frame_out), + .txnrx (txnrx), + .up_enable (ps_gpio_o[47]), + .up_txnrx (ps_gpio_o[48])); + +endmodule + +// *************************************************************************** +// ***************************************************************************