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Merge branch 'hdl_2016_r2'

main
Istvan Csomortani 2017-07-20 11:42:47 +01:00
parent ace09eb26e ed12efc620
commit 04843795d8
917 changed files with 71316 additions and 39861 deletions
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1
.gitattributes vendored
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@ -11,4 +11,5 @@
*.xdc text
*.xml text
*.qsys text
*.xise text
Makefile text

38
.gitignore vendored
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@ -2,6 +2,43 @@
*.data
*.xpr
*.log
*.bld
*.chk
*.cmd_log
*.cxt
*.gise
*.gyd
*.jed
*.lso
*.mfd
*.nga
*.ngc
*.ngd
*.ngr
*.pad
*.pnx
*.prj
*.rpt
*.stx
*.syr
*.tim
*.tspec
*.vm6
*.xst
*.html
*.xrpt
*.err
*_html
*.sld
*.txt
*.qsys
*.csv
xst
netgen
iseconfig
xlnx_auto*
_ngo
_xmsgs
component.xml
*.jou
xgui
@ -22,6 +59,7 @@ db
*.qpf
*.qws
*.sof
system_qsys_script.tcl
hc_output
hps_isw_handoff
hps_sdram_*.csv

56
library/Makefile
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@ -11,13 +11,16 @@ all: lib
clean:
make -C axi_ad6676 clean
make -C axi_ad7616 clean
make -C axi_ad9122 clean
make -C axi_ad9144 clean
make -C axi_ad9152 clean
make -C axi_ad9162 clean
make -C axi_ad9234 clean
make -C axi_ad9250 clean
make -C axi_ad9265 clean
make -C axi_ad9361 clean
make -C axi_ad9371 clean
make -C axi_ad9434 clean
make -C axi_ad9467 clean
make -C axi_ad9625 clean
@ -25,16 +28,21 @@ clean:
make -C axi_ad9652 clean
make -C axi_ad9671 clean
make -C axi_ad9680 clean
make -C axi_ad9684 clean
make -C axi_ad9739a clean
make -C axi_adcfifo clean
make -C axi_ad9963 clean
make -C axi_adc_decimate clean
make -C axi_adc_trigger clean
make -C axi_clkgen clean
make -C axi_dac_interpolate clean
make -C axi_dmac clean
make -C axi_generic_adc clean
make -C axi_gpreg clean
make -C axi_hdmi_rx clean
make -C axi_hdmi_tx clean
make -C axi_i2s_adi clean
make -C axi_jesd_gt clean
make -C axi_intr_monitor clean
make -C axi_logic_analyzer clean
make -C axi_mc_controller clean
make -C axi_mc_current_monitor clean
make -C axi_mc_speed clean
@ -44,12 +52,10 @@ clean:
make -C cn0363/cn0363_dma_sequencer clean
make -C cn0363/cn0363_phase_data_sync clean
make -C cordic_demod clean
make -C interfaces clean
make -C spi_engine/axi_spi_engine clean
make -C spi_engine/spi_engine_execution clean
make -C spi_engine/spi_engine_interconnect clean
make -C spi_engine/spi_engine_offload clean
make -C util_adc_pack clean
make -C util_adcfifo clean
make -C util_axis_fifo clean
make -C util_axis_resize clean
@ -57,12 +63,12 @@ clean:
make -C util_ccat clean
make -C util_clkdiv clean
make -C util_cpack clean
make -C util_dac_unpack clean
make -C util_dacfifo clean
make -C util_extract clean
make -C util_fir_dec clean
make -C util_fir_int clean
make -C util_gmii_to_rgmii clean
make -C util_gtlb clean
make -C util_i2c_mixer clean
make -C util_jesd_gt clean
make -C util_mfifo clean
make -C util_pmod_adc clean
make -C util_pmod_fmeter clean
@ -70,7 +76,15 @@ clean:
make -C util_sigma_delta_spi clean
make -C util_tdd_sync clean
make -C util_upack clean
make -C util_var_fifo clean
make -C util_wfifo clean
make -C xilinx/axi_adcfifo clean
make -C xilinx/axi_adxcvr clean
make -C xilinx/axi_dacfifo clean
make -C xilinx/axi_xcvrlb clean
make -C xilinx/util_adxcvr clean
make -C interfaces clean
clean-all:clean
@ -78,13 +92,16 @@ clean-all:clean
lib:
-make -C axi_ad6676
-make -C axi_ad7616
-make -C axi_ad9122
-make -C axi_ad9144
-make -C axi_ad9152
-make -C axi_ad9162
-make -C axi_ad9234
-make -C axi_ad9250
-make -C axi_ad9265
-make -C axi_ad9361
-make -C axi_ad9371
-make -C axi_ad9434
-make -C axi_ad9467
-make -C axi_ad9625
@ -92,16 +109,21 @@ lib:
-make -C axi_ad9652
-make -C axi_ad9671
-make -C axi_ad9680
-make -C axi_ad9684
-make -C axi_ad9739a
-make -C axi_adcfifo
-make -C axi_ad9963
-make -C axi_adc_decimate
-make -C axi_adc_trigger
-make -C axi_clkgen
-make -C axi_dac_interpolate
-make -C axi_dmac
-make -C axi_generic_adc
-make -C axi_gpreg
-make -C axi_hdmi_rx
-make -C axi_hdmi_tx
-make -C axi_i2s_adi
-make -C axi_jesd_gt
-make -C axi_intr_monitor
-make -C axi_logic_analyzer
-make -C axi_mc_controller
-make -C axi_mc_current_monitor
-make -C axi_mc_speed
@ -111,12 +133,10 @@ lib:
-make -C cn0363/cn0363_dma_sequencer
-make -C cn0363/cn0363_phase_data_sync
-make -C cordic_demod
-make -C interfaces
-make -C spi_engine/axi_spi_engine
-make -C spi_engine/spi_engine_execution
-make -C spi_engine/spi_engine_interconnect
-make -C spi_engine/spi_engine_offload
-make -C util_adc_pack
-make -C util_adcfifo
-make -C util_axis_fifo
-make -C util_axis_resize
@ -124,12 +144,12 @@ lib:
-make -C util_ccat
-make -C util_clkdiv
-make -C util_cpack
-make -C util_dac_unpack
-make -C util_dacfifo
-make -C util_extract
-make -C util_fir_dec
-make -C util_fir_int
-make -C util_gmii_to_rgmii
-make -C util_gtlb
-make -C util_i2c_mixer
-make -C util_jesd_gt
-make -C util_mfifo
-make -C util_pmod_adc
-make -C util_pmod_fmeter
@ -137,7 +157,15 @@ lib:
-make -C util_sigma_delta_spi
-make -C util_tdd_sync
-make -C util_upack
-make -C util_var_fifo
-make -C util_wfifo
-make -C xilinx/axi_adcfifo
-make -C xilinx/axi_adxcvr
-make -C xilinx/axi_dacfifo
-make -C xilinx/axi_xcvrlb
-make -C xilinx/util_adxcvr
-make -C interfaces
####################################################################################
####################################################################################

245
library/altera/alt_serdes/alt_serdes_hw.tcl Normal file
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@ -0,0 +1,245 @@
package require -exact qsys 14.0
set_module_property NAME alt_serdes
set_module_property DESCRIPTION "Altera SERDES"
set_module_property VERSION 1.0
set_module_property GROUP "Analog Devices"
set_module_property DISPLAY_NAME alt_serdes
set_module_property COMPOSITION_CALLBACK p_alt_serdes
# parameters
add_parameter MODE STRING "CLK"
set_parameter_property MODE DISPLAY_NAME MODE
set_parameter_property MODE TYPE STRING
set_parameter_property MODE UNITS None
set_parameter_property MODE HDL_PARAMETER false
set_parameter_property MODE ALLOWED_RANGES {"CLK" "IN" "OUT"}
add_parameter DDR_OR_SDR_N INTEGER 1
set_parameter_property DDR_OR_SDR_N DISPLAY_NAME DDR_OR_SDR_N
set_parameter_property DDR_OR_SDR_N TYPE INTEGER
set_parameter_property DDR_OR_SDR_N UNITS None
set_parameter_property DDR_OR_SDR_N HDL_PARAMETER false
set_parameter_property DDR_OR_SDR_N ALLOWED_RANGES {0 1}
add_parameter SERDES_FACTOR INTEGER 8
set_parameter_property SERDES_FACTOR DISPLAY_NAME SERDES_FACTOR
set_parameter_property SERDES_FACTOR TYPE INTEGER
set_parameter_property SERDES_FACTOR UNITS None
set_parameter_property SERDES_FACTOR HDL_PARAMETER false
set_parameter_property SERDES_FACTOR ALLOWED_RANGES {2 4 8}
add_parameter CLKIN_FREQUENCY FLOAT 500.0
set_parameter_property CLKIN_FREQUENCY DISPLAY_NAME CLKIN_FREQUENCY
set_parameter_property CLKIN_FREQUENCY TYPE FLOAT
set_parameter_property CLKIN_FREQUENCY UNITS None
set_parameter_property CLKIN_FREQUENCY DISPLAY_UNITS "MHz"
set_parameter_property CLKIN_FREQUENCY HDL_PARAMETER false
add_parameter DEVICE_FAMILY STRING "Arria 10"
set_parameter_property DEVICE_FAMILY SYSTEM_INFO {DEVICE_FAMILY}
set_parameter_property DEVICE_FAMILY AFFECTS_GENERATION true
set_parameter_property DEVICE_FAMILY HDL_PARAMETER false
set_parameter_property DEVICE_FAMILY ENABLED false
set_parameter_property DEVICE_FAMILY ALLOWED_RANGES {"Arria 10" "Cyclone V"}
proc p_alt_serdes {} {
set m_mode [get_parameter_value "MODE"]
set m_ddr_or_sdr_n [get_parameter_value "DDR_OR_SDR_N"]
set m_serdes_factor [get_parameter_value "SERDES_FACTOR"]
set m_clkin_frequency [get_parameter_value "CLKIN_FREQUENCY"]
set m_device_family [get_parameter_value DEVICE_FAMILY]
set m_hs_data_rate [expr ($m_clkin_frequency * ($m_ddr_or_sdr_n + 1))]
set m_ls_data_rate [expr ($m_hs_data_rate/$m_serdes_factor)]
set m_ls_phase 22.5
set m_ld_phase 315.0
set m_ld_duty_cycle 12.5
if {$m_serdes_factor == 4} {
set m_ls_phase 45
set m_ld_phase 270.0
set m_ld_duty_cycle 25.0
}
## arria 10, cmos data-in and data-out
if {($m_serdes_factor == 2) && ($m_device_family == "Arria 10")} {
add_instance alt_serdes_out altera_gpio
set_instance_parameter_value alt_serdes_out {PIN_TYPE_GUI} {Output}
set_instance_parameter_value alt_serdes_out {SIZE} {1}
set_instance_parameter_value alt_serdes_out {gui_diff_buff} {0}
set_instance_parameter_value alt_serdes_out {gui_io_reg_mode} {DDIO}
add_interface clk conduit end
set_interface_property clk EXPORT_OF alt_serdes_out.ck
add_interface din conduit end
set_interface_property din EXPORT_OF alt_serdes_out.din
add_interface pad_out conduit end
set_interface_property pad_out EXPORT_OF alt_serdes_out.pad_out
return
}
## cyclone v, cmos data-in and data-out
if {($m_serdes_factor == 2) && ($m_device_family == "Cyclone V")} {
return
}
## arria 10, serdes clock, data-in and data-out
if {($m_mode == "CLK") && ($m_device_family == "Arria 10")} {
add_instance alt_serdes_pll altera_iopll
set_instance_parameter_value alt_serdes_pll {gui_reference_clock_frequency} $m_clkin_frequency
set_instance_parameter_value alt_serdes_pll {gui_use_locked} {1}
set_instance_parameter_value alt_serdes_pll {gui_operation_mode} {lvds}
set_instance_parameter_value alt_serdes_pll {gui_en_lvds_ports} {Enable LVDS_CLK/LOADEN 0}
set_instance_parameter_value alt_serdes_pll {gui_en_phout_ports} {true}
set_instance_parameter_value alt_serdes_pll {gui_en_reconf} {true}
set_instance_parameter_value alt_serdes_pll {gui_output_clock_frequency0} $m_hs_data_rate
set_instance_parameter_value alt_serdes_pll {gui_ps_units0} {degrees}
set_instance_parameter_value alt_serdes_pll {gui_phase_shift_deg0} {180.0}
set_instance_parameter_value alt_serdes_pll {gui_output_clock_frequency1} $m_ls_data_rate
set_instance_parameter_value alt_serdes_pll {gui_ps_units1} {degrees}
set_instance_parameter_value alt_serdes_pll {gui_phase_shift_deg1} $m_ld_phase
set_instance_parameter_value alt_serdes_pll {gui_duty_cycle1} $m_ld_duty_cycle
set_instance_parameter_value alt_serdes_pll {gui_output_clock_frequency2} $m_ls_data_rate
set_instance_parameter_value alt_serdes_pll {gui_phase_shift_deg2} $m_ls_phase
set_instance_parameter_value alt_serdes_pll {gui_ps_units2} {degrees}
add_interface rst reset sink
set_interface_property rst EXPORT_OF alt_serdes_pll.reset
add_interface ref_clk clock sink
set_interface_property ref_clk EXPORT_OF alt_serdes_pll.refclk
add_interface locked conduit end
set_interface_property locked EXPORT_OF alt_serdes_pll.locked
add_interface hs_phase conduit end
set_interface_property hs_phase EXPORT_OF alt_serdes_pll.phout
add_interface hs_clk conduit end
set_interface_property hs_clk EXPORT_OF alt_serdes_pll.lvds_clk
add_interface loaden conduit end
set_interface_property loaden EXPORT_OF alt_serdes_pll.loaden
add_interface ls_clk clock source
set_interface_property ls_clk EXPORT_OF alt_serdes_pll.outclk2
add_instance alt_serdes_pll_reconfig altera_pll_reconfig
add_connection alt_serdes_pll.reconfig_from_pll alt_serdes_pll_reconfig.reconfig_from_pll
add_connection alt_serdes_pll_reconfig.reconfig_to_pll alt_serdes_pll.reconfig_to_pll
add_interface drp_clk clock sink
set_interface_property drp_clk EXPORT_OF alt_serdes_pll_reconfig.mgmt_clk
add_interface drp_rst reset sink
set_interface_property drp_rst EXPORT_OF alt_serdes_pll_reconfig.mgmt_reset
add_interface pll_reconfig avalon slave
set_interface_property pll_reconfig EXPORT_OF alt_serdes_pll_reconfig.mgmt_avalon_slave
return
}
if {($m_mode == "IN") && ($m_device_family == "Arria 10")} {
add_instance alt_serdes_in altera_lvds
set_instance_parameter_value alt_serdes_in {MODE} {RX_DPA-FIFO}
set_instance_parameter_value alt_serdes_in {NUM_CHANNELS} {1}
set_instance_parameter_value alt_serdes_in {DATA_RATE} $m_hs_data_rate
set_instance_parameter_value alt_serdes_in {J_FACTOR} $m_serdes_factor
set_instance_parameter_value alt_serdes_in {USE_EXTERNAL_PLL} {true}
set_instance_parameter_value alt_serdes_in {INCLOCK_FREQUENCY} $m_clkin_frequency
set_instance_parameter_value alt_serdes_in {PLL_USE_RESET} {false}
add_interface data_in conduit end
set_interface_property data_in EXPORT_OF alt_serdes_in.rx_in
add_interface clk conduit end
set_interface_property clk EXPORT_OF alt_serdes_in.ext_fclk
add_interface loaden conduit end
set_interface_property loaden EXPORT_OF alt_serdes_in.ext_loaden
add_interface div_clk conduit end
set_interface_property div_clk EXPORT_OF alt_serdes_in.ext_coreclock
add_interface hs_phase conduit end
set_interface_property hs_phase EXPORT_OF alt_serdes_in.ext_vcoph
add_interface locked conduit end
set_interface_property locked EXPORT_OF alt_serdes_in.ext_pll_locked
add_interface data_s conduit end
set_interface_property data_s EXPORT_OF alt_serdes_in.rx_out
add_interface delay_locked conduit end
set_interface_property delay_locked EXPORT_OF alt_serdes_in.rx_dpa_locked
return
}
if {($m_mode == "OUT") && ($m_device_family == "Arria 10")} {
add_instance alt_serdes_out altera_lvds
set_instance_parameter_value alt_serdes_out {MODE} {TX}
set_instance_parameter_value alt_serdes_out {NUM_CHANNELS} {1}
set_instance_parameter_value alt_serdes_out {DATA_RATE} $m_hs_data_rate
set_instance_parameter_value alt_serdes_out {J_FACTOR} $m_serdes_factor
set_instance_parameter_value alt_serdes_out {TX_EXPORT_CORECLOCK} {false}
set_instance_parameter_value alt_serdes_out {TX_USE_OUTCLOCK} {false}
set_instance_parameter_value alt_serdes_out {USE_EXTERNAL_PLL} {true}
set_instance_parameter_value alt_serdes_out {INCLOCK_FREQUENCY} $m_clkin_frequency
set_instance_parameter_value alt_serdes_out {PLL_USE_RESET} {false}
add_interface data_out conduit end
set_interface_property data_out EXPORT_OF alt_serdes_out.tx_out
add_interface clk conduit end
set_interface_property clk EXPORT_OF alt_serdes_out.ext_fclk
add_interface loaden conduit end
set_interface_property loaden EXPORT_OF alt_serdes_out.ext_loaden
add_interface div_clk conduit end
set_interface_property div_clk EXPORT_OF alt_serdes_out.ext_coreclock
add_interface data_s conduit end
set_interface_property data_s EXPORT_OF alt_serdes_out.tx_in
return
}
## cyclone v, serdes clock, data-in and data-out
if {($m_mode == "CLK") && ($m_device_family == "Cyclone V")} {
add_instance alt_serdes_pll altera_pll
set_instance_parameter_value alt_serdes_pll {gui_reference_clock_frequency} $m_clkin_frequency
set_instance_parameter_value alt_serdes_pll {gui_operation_mode} {lvds}
set_instance_parameter_value alt_serdes_pll {gui_use_locked} {1}
set_instance_parameter_value alt_serdes_pll {gui_number_of_clocks} {3}
set_instance_parameter_value alt_serdes_pll {gui_output_clock_frequency0} $m_hs_data_rate
set_instance_parameter_value alt_serdes_pll {gui_ps_units0} {degrees}
set_instance_parameter_value alt_serdes_pll {gui_phase_shift_deg0} {180.0}
set_instance_parameter_value alt_serdes_pll {gui_output_clock_frequency1} $m_ls_data_rate
set_instance_parameter_value alt_serdes_pll {gui_ps_units1} {degrees}
set_instance_parameter_value alt_serdes_pll {gui_phase_shift_deg1} $m_ld_phase
set_instance_parameter_value alt_serdes_pll {gui_duty_cycle1} $m_ld_duty_cycle
set_instance_parameter_value alt_serdes_pll {gui_output_clock_frequency2} $m_ls_data_rate
set_instance_parameter_value alt_serdes_pll {gui_ps_units2} {degrees}
set_instance_parameter_value alt_serdes_pll {gui_phase_shift_deg2} $m_ls_phase
set_instance_parameter_value alt_serdes_pll {gui_en_reconf} {true}
add_interface rst reset sink
set_interface_property rst EXPORT_OF alt_serdes_pll.reset
add_interface ref_clk clock sink
set_interface_property ref_clk EXPORT_OF alt_serdes_pll.refclk
add_interface locked conduit end
set_interface_property locked EXPORT_OF alt_serdes_pll.locked
add_interface hs_clk clock source
set_interface_property hs_clk EXPORT_OF alt_serdes_pll.outclk0
add_interface loaden clock source
set_interface_property loaden EXPORT_OF alt_serdes_pll.outclk1
add_interface ls_clk clock source
set_interface_property ls_clk EXPORT_OF alt_serdes_pll.outclk2
add_instance alt_serdes_pll_reconfig altera_pll_reconfig
add_connection alt_serdes_pll.reconfig_from_pll alt_serdes_pll_reconfig.reconfig_from_pll
add_connection alt_serdes_pll_reconfig.reconfig_to_pll alt_serdes_pll.reconfig_to_pll
add_interface drp_clk clock sink
set_interface_property drp_clk EXPORT_OF alt_serdes_pll_reconfig.mgmt_clk
add_interface drp_rst reset sink
set_interface_property drp_rst EXPORT_OF alt_serdes_pll_reconfig.mgmt_reset
add_interface pll_reconfig avalon slave
set_interface_property pll_reconfig EXPORT_OF alt_serdes_pll_reconfig.mgmt_avalon_slave
return
}
}

166
library/altera/avl_adxcfg/avl_adxcfg.v Normal file
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@ -0,0 +1,166 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/1ps
module avl_adxcfg (
// reconfig sharing
input rcfg_clk,
input rcfg_reset_n,
input rcfg_in_read_0,
input rcfg_in_write_0,
input [ 9:0] rcfg_in_address_0,
input [31:0] rcfg_in_writedata_0,
output [31:0] rcfg_in_readdata_0,
output rcfg_in_waitrequest_0,
input rcfg_in_read_1,
input rcfg_in_write_1,
input [ 9:0] rcfg_in_address_1,
input [31:0] rcfg_in_writedata_1,
output [31:0] rcfg_in_readdata_1,
output rcfg_in_waitrequest_1,
output rcfg_out_read_0,
output rcfg_out_write_0,
output [ 9:0] rcfg_out_address_0,
output [31:0] rcfg_out_writedata_0,
input [31:0] rcfg_out_readdata_0,
input rcfg_out_waitrequest_0,
output rcfg_out_read_1,
output rcfg_out_write_1,
output [ 9:0] rcfg_out_address_1,
output [31:0] rcfg_out_writedata_1,
input [31:0] rcfg_out_readdata_1,
input rcfg_out_waitrequest_1);
// internal registers
reg [ 1:0] rcfg_select = 'd0;
reg rcfg_read_int = 'd0;
reg rcfg_write_int = 'd0;
reg [ 9:0] rcfg_address_int = 'd0;
reg [31:0] rcfg_writedata_int = 'd0;
reg [31:0] rcfg_readdata_int = 'd0;
reg rcfg_waitrequest_int_0 = 'd1;
reg rcfg_waitrequest_int_1 = 'd1;
// internal signals
wire [31:0] rcfg_readdata_s;
wire rcfg_waitrequest_s;
// xcvr sharing requires same bus (sw must make sure they are mutually exclusive access).
assign rcfg_out_read_0 = rcfg_read_int;
assign rcfg_out_write_0 = rcfg_write_int;
assign rcfg_out_address_0 = rcfg_address_int;
assign rcfg_out_writedata_0 = rcfg_writedata_int;
assign rcfg_out_read_1 = rcfg_read_int;
assign rcfg_out_write_1 = rcfg_write_int;
assign rcfg_out_address_1 = rcfg_address_int;
assign rcfg_out_writedata_1 = rcfg_writedata_int;
assign rcfg_in_readdata_0 = rcfg_readdata_int;
assign rcfg_in_readdata_1 = rcfg_readdata_int;
assign rcfg_in_waitrequest_0 = rcfg_waitrequest_int_0;
assign rcfg_in_waitrequest_1 = rcfg_waitrequest_int_1;
assign rcfg_readdata_s = rcfg_out_readdata_1 & rcfg_out_readdata_0;
assign rcfg_waitrequest_s = rcfg_out_waitrequest_1 & rcfg_out_waitrequest_0;
always @(negedge rcfg_reset_n or posedge rcfg_clk) begin
if (rcfg_reset_n == 0) begin
rcfg_select <= 2'd0;
rcfg_read_int <= 1'd0;
rcfg_write_int <= 1'd0;
rcfg_address_int <= 10'd0;
rcfg_writedata_int <= 32'd0;
rcfg_readdata_int = 32'd0;
rcfg_waitrequest_int_0 <= 1'b1;
rcfg_waitrequest_int_1 <= 1'b1;
end else begin
if (rcfg_select[1] == 1'b1) begin
if (rcfg_waitrequest_s == 1'b0) begin
rcfg_select <= 2'd0;
rcfg_read_int <= 1'b0;
rcfg_write_int <= 1'b0;
rcfg_address_int <= 10'd0;
rcfg_writedata_int <= 32'd0;
end
rcfg_readdata_int = rcfg_readdata_s;
rcfg_waitrequest_int_0 <= rcfg_waitrequest_s | rcfg_select[0];
rcfg_waitrequest_int_1 <= rcfg_waitrequest_s | ~rcfg_select[0];
end else if ((rcfg_in_read_0 == 1'b1) || (rcfg_in_write_0 == 1'b1)) begin
rcfg_select <= 2'b10;
rcfg_read_int <= rcfg_in_read_0;
rcfg_write_int <= rcfg_in_write_0;
rcfg_address_int <= rcfg_in_address_0;
rcfg_writedata_int <= rcfg_in_writedata_0;
rcfg_readdata_int = 32'd0;
rcfg_waitrequest_int_0 <= 1'b1;
rcfg_waitrequest_int_1 <= 1'b1;
end else if ((rcfg_in_read_1 == 1'b1) || (rcfg_in_write_1 == 1'b1)) begin
rcfg_select <= 2'b11;
rcfg_read_int <= rcfg_in_read_1;
rcfg_write_int <= rcfg_in_write_1;
rcfg_address_int <= rcfg_in_address_1;
rcfg_writedata_int <= rcfg_in_writedata_1;
rcfg_readdata_int = 32'd0;
rcfg_waitrequest_int_0 <= 1'b1;
rcfg_waitrequest_int_1 <= 1'b1;
end else begin
rcfg_select <= 2'd0;
rcfg_read_int <= 1'd0;
rcfg_write_int <= 1'd0;
rcfg_address_int <= 10'd0;
rcfg_writedata_int <= 32'd0;
rcfg_readdata_int = 32'd0;
rcfg_waitrequest_int_0 <= 1'b1;
rcfg_waitrequest_int_1 <= 1'b1;
end
end
end
endmodule
// ***************************************************************************
// ***************************************************************************

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library/altera/avl_adxcfg/avl_adxcfg_hw.tcl Normal file
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package require -exact qsys 14.0
set_module_property NAME avl_adxcfg
set_module_property DESCRIPTION "Avalon ADXCFG Core"
set_module_property VERSION 1.0
set_module_property GROUP "Analog Devices"
set_module_property DISPLAY_NAME avl_adxcfg
# files
add_fileset quartus_synth QUARTUS_SYNTH "" ""
set_fileset_property quartus_synth TOP_LEVEL avl_adxcfg
add_fileset_file avl_adxcfg.v VERILOG PATH avl_adxcfg.v TOP_LEVEL_FILE
# reconfiguration interfaces
add_interface rcfg_clk clock sink
add_interface_port rcfg_clk rcfg_clk clk Input 1
add_interface rcfg_reset_n reset end
set_interface_property rcfg_reset_n associatedClock rcfg_clk
add_interface_port rcfg_reset_n rcfg_reset_n reset_n Input 1
for {set n 0} {$n < 2} {incr n} {
add_interface rcfg_s${n} avalon slave
add_interface rcfg_m${n} avalon master
add_interface_port rcfg_s${n} rcfg_in_read_${n} read Input 1
add_interface_port rcfg_s${n} rcfg_in_write_${n} write Input 1
add_interface_port rcfg_s${n} rcfg_in_address_${n} address Input 10
add_interface_port rcfg_s${n} rcfg_in_writedata_${n} writedata Input 32
add_interface_port rcfg_s${n} rcfg_in_readdata_${n} readdata Output 32
add_interface_port rcfg_s${n} rcfg_in_waitrequest_${n} waitrequest Output 1
add_interface_port rcfg_m${n} rcfg_out_read_${n} read Output 1
add_interface_port rcfg_m${n} rcfg_out_write_${n} write Output 1
add_interface_port rcfg_m${n} rcfg_out_address_${n} address Output 10
add_interface_port rcfg_m${n} rcfg_out_writedata_${n} writedata Output 32
add_interface_port rcfg_m${n} rcfg_out_readdata_${n} readdata Input 32
add_interface_port rcfg_m${n} rcfg_out_waitrequest_${n} waitrequest Input 1
set_interface_property rcfg_s${n} associatedClock rcfg_clk
set_interface_property rcfg_s${n} associatedReset rcfg_reset_n
set_interface_property rcfg_s${n} addressUnits WORDS
set_interface_property rcfg_s${n} burstCountUnits WORDS
set_interface_property rcfg_s${n} explicitAddressSpan 0
set_interface_property rcfg_m${n} associatedClock rcfg_clk
set_interface_property rcfg_m${n} associatedReset rcfg_reset_n
set_interface_property rcfg_m${n} addressUnits WORDS
set_interface_property rcfg_m${n} burstCountUnits WORDS
}

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library/altera/avl_adxcvr/avl_adxcvr_hw.tcl Executable file
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package require -exact qsys 14.0
set_module_property NAME avl_adxcvr
set_module_property DESCRIPTION "Avalon ADXCVR Core"
set_module_property VERSION 1.0
set_module_property GROUP "Analog Devices"
set_module_property DISPLAY_NAME avl_adxcvr
set_module_property COMPOSITION_CALLBACK p_avl_adxcvr
# parameters
add_parameter DEVICE_FAMILY STRING
set_parameter_property DEVICE_FAMILY SYSTEM_INFO {DEVICE_FAMILY}
set_parameter_property DEVICE_FAMILY AFFECTS_GENERATION true
set_parameter_property DEVICE_FAMILY HDL_PARAMETER false
set_parameter_property DEVICE_FAMILY ENABLED false
add_parameter TX_OR_RX_N INTEGER 0
set_parameter_property TX_OR_RX_N DISPLAY_NAME TX_OR_RX_N
set_parameter_property TX_OR_RX_N TYPE INTEGER
set_parameter_property TX_OR_RX_N UNITS None
set_parameter_property TX_OR_RX_N HDL_PARAMETER false
add_parameter ID INTEGER 0
set_parameter_property ID DISPLAY_NAME ID
set_parameter_property ID TYPE INTEGER
set_parameter_property ID UNITS None
set_parameter_property ID HDL_PARAMETER false
add_parameter PCS_CONFIG STRING "JESD_PCS_CFG2"
set_parameter_property PCS_CONFIG DISPLAY_NAME PCS_CONFIG
set_parameter_property PCS_CONFIG TYPE STRING
set_parameter_property PCS_CONFIG UNITS None
set_parameter_property PCS_CONFIG HDL_PARAMETER false
add_parameter LANE_RATE FLOAT 10000
set_parameter_property LANE_RATE DISPLAY_NAME LANE_RATE
set_parameter_property LANE_RATE TYPE FLOAT
set_parameter_property LANE_RATE UNITS None
set_parameter_property LANE_RATE DISPLAY_UNITS "Mbps"
set_parameter_property LANE_RATE HDL_PARAMETER false
add_parameter SYSCLK_FREQUENCY FLOAT 100.0
set_parameter_property SYSCLK_FREQUENCY DISPLAY_NAME SYSCLK_FREQUENCY
set_parameter_property SYSCLK_FREQUENCY TYPE FLOAT
set_parameter_property SYSCLK_FREQUENCY UNITS Megahertz
set_parameter_property SYSCLK_FREQUENCY HDL_PARAMETER false
add_parameter PLLCLK_FREQUENCY FLOAT 5000.0
set_parameter_property PLLCLK_FREQUENCY DISPLAY_NAME PLLCLK_FREQUENCY
set_parameter_property PLLCLK_FREQUENCY TYPE FLOAT
set_parameter_property PLLCLK_FREQUENCY UNITS Megahertz
set_parameter_property PLLCLK_FREQUENCY HDL_PARAMETER false
add_parameter REFCLK_FREQUENCY FLOAT 500.0
set_parameter_property REFCLK_FREQUENCY DISPLAY_NAME REFCLK_FREQUENCY
set_parameter_property REFCLK_FREQUENCY TYPE FLOAT
set_parameter_property REFCLK_FREQUENCY UNITS Megahertz
set_parameter_property REFCLK_FREQUENCY HDL_PARAMETER false
add_parameter CORECLK_FREQUENCY FLOAT 250.0
set_parameter_property CORECLK_FREQUENCY DISPLAY_NAME CORECLK_FREQUENCY
set_parameter_property CORECLK_FREQUENCY TYPE FLOAT
set_parameter_property CORECLK_FREQUENCY UNITS Megahertz
set_parameter_property CORECLK_FREQUENCY HDL_PARAMETER false
add_parameter NUM_OF_LANES INTEGER 4
set_parameter_property NUM_OF_LANES DISPLAY_NAME NUM_OF_LANES
set_parameter_property NUM_OF_LANES TYPE INTEGER
set_parameter_property NUM_OF_LANES UNITS None
set_parameter_property NUM_OF_LANES HDL_PARAMETER false
add_parameter NUM_OF_CONVS INTEGER 2
set_parameter_property NUM_OF_CONVS DISPLAY_NAME NUM_OF_CONVS
set_parameter_property NUM_OF_CONVS TYPE INTEGER
set_parameter_property NUM_OF_CONVS UNITS None
set_parameter_property NUM_OF_CONVS HDL_PARAMETER false
add_parameter FRM_BCNT INTEGER 1
set_parameter_property FRM_BCNT DISPLAY_NAME FRM_BCNT
set_parameter_property FRM_BCNT TYPE INTEGER
set_parameter_property FRM_BCNT UNITS None
set_parameter_property FRM_BCNT HDL_PARAMETER false
add_parameter FRM_SCNT INTEGER 1
set_parameter_property FRM_SCNT DISPLAY_NAME FRM_SCNT
set_parameter_property FRM_SCNT TYPE INTEGER
set_parameter_property FRM_SCNT UNITS None
set_parameter_property FRM_SCNT HDL_PARAMETER false
add_parameter MF_FCNT INTEGER 32
set_parameter_property MF_FCNT DISPLAY_NAME MF_FCNT
set_parameter_property MF_FCNT TYPE INTEGER
set_parameter_property MF_FCNT UNITS None
set_parameter_property MF_FCNT HDL_PARAMETER false
add_parameter HD INTEGER 1
set_parameter_property HD DISPLAY_NAME HD
set_parameter_property HD TYPE INTEGER
set_parameter_property HD UNITS None
set_parameter_property HD HDL_PARAMETER false
proc p_avl_adxcvr {} {
set m_id [get_parameter_value "ID"]
set m_lane_rate [get_parameter_value "LANE_RATE"]
set m_pcs_config [get_parameter_value "PCS_CONFIG"]
set m_tx_or_rx_n [get_parameter_value "TX_OR_RX_N"]
set m_num_of_lanes [get_parameter_value "NUM_OF_LANES"]
set m_device_family [get_parameter_value "DEVICE_FAMILY"]
set m_sysclk_frequency [get_parameter_value "SYSCLK_FREQUENCY"]
set m_pllclk_frequency [get_parameter_value "PLLCLK_FREQUENCY"]
set m_refclk_frequency [get_parameter_value "REFCLK_FREQUENCY"]
set m_coreclk_frequency [get_parameter_value "CORECLK_FREQUENCY"]
set m_num_of_convs [get_parameter_value "NUM_OF_CONVS"]
set m_frm_bcnt [get_parameter_value "FRM_BCNT"]
set m_frm_scnt [get_parameter_value "FRM_SCNT"]
set m_mf_fcnt [get_parameter_value "MF_FCNT"]
set m_hd [get_parameter_value "HD"]
add_instance alt_sys_clk clock_source 16.0
set_instance_parameter_value alt_sys_clk {clockFrequency} [expr $m_sysclk_frequency*1000000]
add_interface sys_clk clock sink
set_interface_property sys_clk EXPORT_OF alt_sys_clk.clk_in
add_interface sys_resetn reset sink
set_interface_property sys_resetn EXPORT_OF alt_sys_clk.clk_in_reset
add_instance alt_ref_clk altera_clock_bridge 16.0
set_instance_parameter_value alt_ref_clk {EXPLICIT_CLOCK_RATE} [expr $m_refclk_frequency*1000000]
add_interface ref_clk clock sink
set_interface_property ref_clk EXPORT_OF alt_ref_clk.in_clk
if {$m_device_family eq "Arria V"} {
add_instance alt_core_pll altera_pll 16.0
set_instance_parameter_value alt_core_pll {gui_en_reconf} {1}
set_instance_parameter_value alt_core_pll {gui_reference_clock_frequency} $m_refclk_frequency
set_instance_parameter_value alt_core_pll {gui_use_locked} {1}
set_instance_parameter_value alt_core_pll {gui_output_clock_frequency0} $m_coreclk_frequency
add_connection alt_ref_clk.out_clk alt_core_pll.refclk
add_connection alt_sys_clk.clk_reset alt_core_pll.reset
add_interface core_pll_locked conduit end
set_interface_property core_pll_locked EXPORT_OF alt_core_pll.locked
} else {
add_instance alt_core_pll altera_iopll 16.0
set_instance_parameter_value alt_core_pll {gui_en_reconf} {1}
set_instance_parameter_value alt_core_pll {gui_reference_clock_frequency} $m_refclk_frequency
set_instance_parameter_value alt_core_pll {gui_use_locked} {1}
set_instance_parameter_value alt_core_pll {gui_output_clock_frequency0} $m_coreclk_frequency
add_connection alt_ref_clk.out_clk alt_core_pll.refclk
add_connection alt_sys_clk.clk_reset alt_core_pll.reset
add_interface core_pll_locked conduit end
set_interface_property core_pll_locked EXPORT_OF alt_core_pll.locked
}
add_instance alt_core_pll_reconfig altera_pll_reconfig 16.0
add_connection alt_sys_clk.clk_reset alt_core_pll_reconfig.mgmt_reset
add_connection alt_sys_clk.clk alt_core_pll_reconfig.mgmt_clk
add_connection alt_core_pll_reconfig.reconfig_to_pll alt_core_pll.reconfig_to_pll
add_connection alt_core_pll.reconfig_from_pll alt_core_pll_reconfig.reconfig_from_pll
add_interface core_pll_reconfig avalon slave
set_interface_property core_pll_reconfig EXPORT_OF alt_core_pll_reconfig.mgmt_avalon_slave
add_instance alt_core_clk altera_clock_bridge 16.0
set_instance_parameter_value alt_core_clk {EXPLICIT_CLOCK_RATE} $m_coreclk_frequency
add_connection alt_core_pll.outclk0 alt_core_clk.in_clk
add_interface core_clk clock source
set_interface_property core_clk EXPORT_OF alt_core_clk.out_clk
if {$m_tx_or_rx_n == 1} {
add_instance alt_rst_cntrol altera_xcvr_reset_control 16.0
set_instance_parameter_value alt_rst_cntrol {CHANNELS} $m_num_of_lanes
set_instance_parameter_value alt_rst_cntrol {SYS_CLK_IN_MHZ} $m_sysclk_frequency
set_instance_parameter_value alt_rst_cntrol {TX_PLL_ENABLE} {1}
set_instance_parameter_value alt_rst_cntrol {T_PLL_POWERDOWN} {1000}
set_instance_parameter_value alt_rst_cntrol {TX_ENABLE} {1}
set_instance_parameter_value alt_rst_cntrol {T_TX_ANALOGRESET} {70000}
set_instance_parameter_value alt_rst_cntrol {T_TX_DIGITALRESET} {70000}
set_instance_parameter_value alt_rst_cntrol {gui_pll_cal_busy} {1}
set_instance_parameter_value alt_rst_cntrol {RX_ENABLE} {0}
add_connection alt_sys_clk.clk alt_rst_cntrol.clock
add_interface rst reset sink
set_interface_property rst EXPORT_OF alt_rst_cntrol.reset
add_interface ready conduit end
set_interface_property ready EXPORT_OF alt_rst_cntrol.tx_ready
add_instance alt_lane_pll altera_xcvr_atx_pll_a10 16.0
set_instance_parameter_value alt_lane_pll {enable_pll_reconfig} {1}
set_instance_parameter_value alt_lane_pll {rcfg_separate_avmm_busy} {1}
set_instance_parameter_value alt_lane_pll {set_capability_reg_enable} {1}
set_instance_parameter_value alt_lane_pll {set_user_identifier} $m_id
set_instance_parameter_value alt_lane_pll {set_csr_soft_logic_enable} {1}
set_instance_parameter_value alt_lane_pll {set_output_clock_frequency} $m_pllclk_frequency
set_instance_parameter_value alt_lane_pll {set_auto_reference_clock_frequency} $m_refclk_frequency
add_connection alt_rst_cntrol.pll_powerdown alt_lane_pll.pll_powerdown
add_connection alt_lane_pll.pll_locked alt_rst_cntrol.pll_locked
add_connection alt_lane_pll.pll_cal_busy alt_rst_cntrol.pll_cal_busy
add_connection alt_ref_clk.out_clk alt_lane_pll.pll_refclk0
add_connection alt_sys_clk.clk alt_lane_pll.reconfig_clk0
add_connection alt_sys_clk.clk_reset alt_lane_pll.reconfig_reset0
add_interface lane_pll_reconfig avalon slave
set_interface_property lane_pll_reconfig EXPORT_OF alt_lane_pll.reconfig_avmm0
add_instance alt_ip altera_jesd204 16.0
set_instance_parameter_value alt_ip {wrapper_opt} {base}
set_instance_parameter_value alt_ip {DATA_PATH} {TX}
set_instance_parameter_value alt_ip {lane_rate} $m_lane_rate
set_instance_parameter_value alt_ip {L} $m_num_of_lanes
set_instance_parameter_value alt_ip {M} $m_num_of_convs
set_instance_parameter_value alt_ip {GUI_EN_CFG_F} {1}
set_instance_parameter_value alt_ip {GUI_CFG_F} $m_frm_bcnt
set_instance_parameter_value alt_ip {N} {16}
set_instance_parameter_value alt_ip {N_PRIME} {16}
set_instance_parameter_value alt_ip {S} $m_frm_scnt
set_instance_parameter_value alt_ip {K} $m_mf_fcnt
set_instance_parameter_value alt_ip {SCR} {1}
set_instance_parameter_value alt_ip {HD} $m_hd
add_connection alt_core_pll.outclk0 alt_ip.txlink_clk
add_connection alt_sys_clk.clk_reset alt_ip.txlink_rst_n
add_interface ip_data avalon_streaming sink
set_interface_property ip_data EXPORT_OF alt_ip.jesd204_tx_link
add_connection alt_sys_clk.clk alt_ip.jesd204_tx_avs_clk
add_connection alt_sys_clk.clk_reset alt_ip.jesd204_tx_avs_rst_n
add_interface ip_reconfig avalon slave
set_interface_property ip_reconfig EXPORT_OF alt_ip.jesd204_tx_avs
add_interface sysref conduit end
set_interface_property sysref EXPORT_OF alt_ip.sysref
add_interface sync conduit end
set_interface_property sync EXPORT_OF alt_ip.sync_n
add_connection alt_ip.dev_sync_n alt_ip.mdev_sync_n
add_instance alt_xphy avl_adxphy 1.0
set_instance_parameter_value alt_xphy {TX_OR_RX_N} {1}
set_instance_parameter_value alt_xphy {NUM_OF_LANES} $m_num_of_lanes
add_connection alt_rst_cntrol.tx_analogreset alt_xphy.tx_core_analogreset
add_connection alt_rst_cntrol.tx_digitalreset alt_xphy.tx_core_digitalreset
add_connection alt_xphy.tx_core_cal_busy alt_rst_cntrol.tx_cal_busy
add_connection alt_xphy.tx_ip_cal_busy alt_ip.tx_cal_busy
add_connection alt_xphy.tx_ip_pcfifo_full alt_ip.phy_csr_tx_pcfifo_full
add_connection alt_xphy.tx_ip_pcfifo_empty alt_ip.phy_csr_tx_pcfifo_empty
add_connection alt_ip.jesd204_tx_pcs_data alt_xphy.tx_ip_pcs_data
add_connection alt_ip.jesd204_tx_pcs_kchar_data alt_xphy.tx_ip_pcs_kchar_data
add_connection alt_ip.phy_tx_elecidle alt_xphy.tx_ip_elecidle
add_connection alt_ip.csr_lane_polarity alt_xphy.tx_ip_csr_lane_polarity
add_connection alt_ip.csr_lane_powerdown alt_xphy.tx_ip_csr_lane_powerdown
add_connection alt_ip.csr_bit_reversal alt_xphy.tx_ip_csr_bit_reversal
add_connection alt_ip.csr_byte_reversal alt_xphy.tx_ip_csr_byte_reversal
for {set n 0} {$n < $m_num_of_lanes} {incr n} {
add_interface tx_ip_s_${n} conduit end
set_interface_property tx_ip_s_${n} EXPORT_OF alt_xphy.tx_ip_s_${n}
add_interface tx_ip_d_${n} conduit end
set_interface_property tx_ip_d_${n} EXPORT_OF alt_xphy.tx_ip_d_${n}
add_interface tx_phy_s_${n} conduit end
set_interface_property tx_phy_s_${n} EXPORT_OF alt_xphy.tx_phy_s_${n}
add_interface tx_phy_d_${n} conduit end
set_interface_property tx_phy_d_${n} EXPORT_OF alt_xphy.tx_phy_d_${n}
add_instance alt_phy_${n} altera_jesd204 16.0
set_instance_parameter_value alt_phy_${n} {wrapper_opt} {phy}
set_instance_parameter_value alt_phy_${n} {DATA_PATH} {TX}
set_instance_parameter_value alt_phy_${n} {lane_rate} $m_lane_rate
set_instance_parameter_value alt_phy_${n} {PCS_CONFIG} $m_pcs_config
set_instance_parameter_value alt_phy_${n} {bonded_mode} {non_bonded}
set_instance_parameter_value alt_phy_${n} {pll_reconfig_enable} {1}
set_instance_parameter_value alt_phy_${n} {set_capability_reg_enable} {1}
set_instance_parameter_value alt_phy_${n} {set_user_identifier} $m_id
set_instance_parameter_value alt_phy_${n} {set_csr_soft_logic_enable} {1}
set_instance_parameter_value alt_phy_${n} {L} 1
add_connection alt_core_pll.outclk0 alt_phy_${n}.txlink_clk
add_connection alt_sys_clk.clk_reset alt_phy_${n}.txlink_rst_n
add_interface tx_data_${n} conduit end
set_interface_property tx_data_${n} EXPORT_OF alt_phy_${n}.tx_serial_data
add_connection alt_xphy.tx_phy${n}_analogreset alt_phy_${n}.tx_analogreset
add_connection alt_xphy.tx_phy${n}_digitalreset alt_phy_${n}.tx_digitalreset
add_connection alt_lane_pll.tx_serial_clk alt_phy_${n}.tx_serial_clk0
if {$m_device_family eq "Arria V"} {
add_instance alt_phy_reconfig_${n} alt_xcvr_reconfig 16.0
set_instance_parameter_value alt_phy_reconfig_${n} {number_of_reconfig_interfaces} {1}
add_connection alt_sys_clk.clk alt_phy_reconfig_${n}.mgmt_clk_clk
add_connection alt_sys_clk.clk_reset alt_phy_reconfig_${n}.mgmt_rst_reset
add_interface phy_reconfig_${n} avalon slave
set_interface_property phy_reconfig_${n} EXPORT_OF alt_phy_reconfig_${n}.reconfig_mgmt
add_connection alt_phy_reconfig_${n}.reconfig_to_xcvr alt_phy_${n}.reconfig_to_xcvr
add_connection alt_phy_${n}.reconfig_from_xcvr alt_phy_reconfig_${n}.reconfig_from_xcvr
} else {
add_connection alt_sys_clk.clk alt_phy_${n}.reconfig_clk
add_connection alt_sys_clk.clk_reset alt_phy_${n}.reconfig_reset
add_interface phy_reconfig_${n} avalon slave
set_interface_property phy_reconfig_${n} EXPORT_OF alt_phy_${n}.reconfig_avmm
}
add_connection alt_phy_${n}.tx_cal_busy alt_xphy.tx_phy${n}_cal_busy
add_connection alt_phy_${n}.phy_csr_tx_pcfifo_full alt_xphy.tx_phy${n}_pcfifo_full
add_connection alt_phy_${n}.phy_csr_tx_pcfifo_empty alt_xphy.tx_phy${n}_pcfifo_empty
add_connection alt_xphy.tx_phy${n}_pcs_data alt_phy_${n}.jesd204_tx_pcs_data
add_connection alt_xphy.tx_phy${n}_pcs_kchar_data alt_phy_${n}.jesd204_tx_pcs_kchar_data
add_connection alt_xphy.tx_phy${n}_elecidle alt_phy_${n}.phy_tx_elecidle
add_connection alt_xphy.tx_phy${n}_csr_lane_polarity alt_phy_${n}.csr_lane_polarity
add_connection alt_xphy.tx_phy${n}_csr_lane_powerdown alt_phy_${n}.csr_lane_powerdown
add_connection alt_xphy.tx_phy${n}_csr_bit_reversal alt_phy_${n}.csr_bit_reversal
add_connection alt_xphy.tx_phy${n}_csr_byte_reversal alt_phy_${n}.csr_byte_reversal
}
}
if {$m_tx_or_rx_n == 0} {
add_instance alt_rst_cntrol altera_xcvr_reset_control 16.0
set_instance_parameter_value alt_rst_cntrol {CHANNELS} $m_num_of_lanes
set_instance_parameter_value alt_rst_cntrol {SYS_CLK_IN_MHZ} $m_sysclk_frequency
set_instance_parameter_value alt_rst_cntrol {TX_PLL_ENABLE} {0}
set_instance_parameter_value alt_rst_cntrol {TX_ENABLE} {0}
set_instance_parameter_value alt_rst_cntrol {RX_ENABLE} {1}
set_instance_parameter_value alt_rst_cntrol {T_RX_ANALOGRESET} {70000}
set_instance_parameter_value alt_rst_cntrol {T_RX_DIGITALRESET} {4000}
add_connection alt_sys_clk.clk alt_rst_cntrol.clock
add_interface rst reset sink
set_interface_property rst EXPORT_OF alt_rst_cntrol.reset
add_interface ready conduit end
set_interface_property ready EXPORT_OF alt_rst_cntrol.rx_ready
add_instance alt_ip altera_jesd204 16.0
set_instance_parameter_value alt_ip {wrapper_opt} {base}
set_instance_parameter_value alt_ip {DATA_PATH} {RX}
set_instance_parameter_value alt_ip {lane_rate} $m_lane_rate
set_instance_parameter_value alt_ip {L} $m_num_of_lanes
set_instance_parameter_value alt_ip {M} $m_num_of_convs
set_instance_parameter_value alt_ip {GUI_EN_CFG_F} {1}
set_instance_parameter_value alt_ip {GUI_CFG_F} $m_frm_bcnt
set_instance_parameter_value alt_ip {N} {16}
set_instance_parameter_value alt_ip {N_PRIME} {16}
set_instance_parameter_value alt_ip {S} $m_frm_scnt
set_instance_parameter_value alt_ip {K} $m_mf_fcnt
set_instance_parameter_value alt_ip {SCR} {1}
set_instance_parameter_value alt_ip {HD} $m_hd
add_connection alt_core_pll.outclk0 alt_ip.rxlink_clk
add_connection alt_sys_clk.clk_reset alt_ip.rxlink_rst_n
add_interface ip_sof conduit end
set_interface_property ip_sof EXPORT_OF alt_ip.sof
add_interface ip_data avalon_streaming source
set_interface_property ip_data EXPORT_OF alt_ip.jesd204_rx_link
add_connection alt_sys_clk.clk alt_ip.jesd204_rx_avs_clk
add_connection alt_sys_clk.clk_reset alt_ip.jesd204_rx_avs_rst_n
add_interface ip_reconfig avalon slave
set_interface_property ip_reconfig EXPORT_OF alt_ip.jesd204_rx_avs
add_interface sysref conduit end
set_interface_property sysref EXPORT_OF alt_ip.sysref
add_interface sync conduit end
set_interface_property sync EXPORT_OF alt_ip.dev_sync_n
add_connection alt_ip.dev_lane_aligned alt_ip.alldev_lane_aligned
add_instance alt_xphy avl_adxphy 1.0
set_instance_parameter_value alt_xphy {TX_OR_RX_N} {0}
set_instance_parameter_value alt_xphy {NUM_OF_LANES} $m_num_of_lanes
add_connection alt_rst_cntrol.rx_analogreset alt_xphy.rx_core_analogreset
add_connection alt_rst_cntrol.rx_digitalreset alt_xphy.rx_core_digitalreset
add_connection alt_xphy.rx_core_is_lockedtodata alt_rst_cntrol.rx_is_lockedtodata
add_connection alt_xphy.rx_core_cal_busy alt_rst_cntrol.rx_cal_busy
add_connection alt_xphy.rx_ip_is_lockedtodata alt_ip.rx_islockedtodata
add_connection alt_xphy.rx_ip_cal_busy alt_ip.rx_cal_busy
add_connection alt_xphy.rx_ip_pcs_data_valid alt_ip.jesd204_rx_pcs_data_valid
add_connection alt_xphy.rx_ip_pcs_data alt_ip.jesd204_rx_pcs_data
add_connection alt_xphy.rx_ip_pcs_disperr alt_ip.jesd204_rx_pcs_disperr
add_connection alt_xphy.rx_ip_pcs_errdetect alt_ip.jesd204_rx_pcs_errdetect
add_connection alt_xphy.rx_ip_pcs_kchar_data alt_ip.jesd204_rx_pcs_kchar_data
add_connection alt_xphy.rx_ip_pcfifo_full alt_ip.phy_csr_rx_pcfifo_full
add_connection alt_xphy.rx_ip_pcfifo_empty alt_ip.phy_csr_rx_pcfifo_empty
add_connection alt_xphy.rx_ip_patternalign_en alt_ip.patternalign_en
add_connection alt_xphy.rx_ip_csr_lane_polarity alt_ip.csr_lane_polarity
add_connection alt_xphy.rx_ip_csr_lane_powerdown alt_ip.csr_lane_powerdown
add_connection alt_xphy.rx_ip_csr_bit_reversal alt_ip.csr_bit_reversal
add_connection alt_xphy.rx_ip_csr_byte_reversal alt_ip.csr_byte_reversal
for {set n 0} {$n < $m_num_of_lanes} {incr n} {
add_instance alt_phy_${n} altera_jesd204 16.0
set_instance_parameter_value alt_phy_${n} {wrapper_opt} {phy}
set_instance_parameter_value alt_phy_${n} {DATA_PATH} {RX}
set_instance_parameter_value alt_phy_${n} {lane_rate} $m_lane_rate
set_instance_parameter_value alt_phy_${n} {PCS_CONFIG} $m_pcs_config
set_instance_parameter_value alt_phy_${n} {REFCLK_FREQ} $m_refclk_frequency
set_instance_parameter_value alt_phy_${n} {pll_reconfig_enable} {1}
set_instance_parameter_value alt_phy_${n} {set_capability_reg_enable} {1}
set_instance_parameter_value alt_phy_${n} {set_user_identifier} $m_id
set_instance_parameter_value alt_phy_${n} {set_csr_soft_logic_enable} {1}
set_instance_parameter_value alt_phy_${n} {L} 1
if {$m_device_family eq "Arria V"} {
add_interface phy_reconfig_to_xcvr_${n} conduit end
set_interface_property phy_reconfig_to_xcvr_${n} EXPORT_OF alt_phy_${n}.reconfig_to_xcvr
add_interface phy_reconfig_from_xcvr_${n} conduit end
set_interface_property phy_reconfig_from_xcvr_${n} EXPORT_OF alt_phy_${n}.reconfig_from_xcvr
} else {
add_connection alt_sys_clk.clk alt_phy_${n}.reconfig_clk
add_connection alt_sys_clk.clk_reset alt_phy_${n}.reconfig_reset
add_interface phy_reconfig_${n} avalon slave
set_interface_property phy_reconfig_${n} EXPORT_OF alt_phy_${n}.reconfig_avmm
}
add_connection alt_ref_clk.out_clk alt_phy_${n}.pll_ref_clk
add_connection alt_core_pll.outclk0 alt_phy_${n}.rxlink_clk
add_connection alt_sys_clk.clk_reset alt_phy_${n}.rxlink_rst_n
add_interface rx_data_${n} conduit end
set_interface_property rx_data_${n} EXPORT_OF alt_phy_${n}.rx_serial_data
add_connection alt_xphy.rx_phy${n}_analogreset alt_phy_${n}.rx_analogreset
add_connection alt_xphy.rx_phy${n}_digitalreset alt_phy_${n}.rx_digitalreset
add_connection alt_phy_${n}.rx_islockedtodata alt_xphy.rx_phy${n}_is_lockedtodata
add_connection alt_phy_${n}.rx_cal_busy alt_xphy.rx_phy${n}_cal_busy
add_connection alt_phy_${n}.jesd204_rx_pcs_data_valid alt_xphy.rx_phy${n}_pcs_data_valid
add_connection alt_phy_${n}.jesd204_rx_pcs_data alt_xphy.rx_phy${n}_pcs_data
add_connection alt_phy_${n}.jesd204_rx_pcs_disperr alt_xphy.rx_phy${n}_pcs_disperr
add_connection alt_phy_${n}.jesd204_rx_pcs_errdetect alt_xphy.rx_phy${n}_pcs_errdetect
add_connection alt_phy_${n}.jesd204_rx_pcs_kchar_data alt_xphy.rx_phy${n}_pcs_kchar_data
add_connection alt_phy_${n}.phy_csr_rx_pcfifo_full alt_xphy.rx_phy${n}_pcfifo_full
add_connection alt_phy_${n}.phy_csr_rx_pcfifo_empty alt_xphy.rx_phy${n}_pcfifo_empty
add_connection alt_xphy.rx_phy${n}_patternalign_en alt_phy_${n}.patternalign_en
add_connection alt_xphy.rx_phy${n}_csr_lane_polarity alt_phy_${n}.csr_lane_polarity
add_connection alt_xphy.rx_phy${n}_csr_lane_powerdown alt_phy_${n}.csr_lane_powerdown
add_connection alt_xphy.rx_phy${n}_csr_bit_reversal alt_phy_${n}.csr_bit_reversal
add_connection alt_xphy.rx_phy${n}_csr_byte_reversal alt_phy_${n}.csr_byte_reversal
}
}
}

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package require -exact qsys 14.0
source ../../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip_alt.tcl
set_module_property NAME avl_adxphy
set_module_property DESCRIPTION "Avalon ADXPHY Core"
set_module_property VERSION 1.0
set_module_property GROUP "Analog Devices"
set_module_property DISPLAY_NAME avl_adxphy
set_module_property ELABORATION_CALLBACK p_avl_adxphy
# files
add_fileset quartus_synth QUARTUS_SYNTH "" ""
set_fileset_property quartus_synth TOP_LEVEL avl_adxphy
add_fileset_file avl_adxphy.v VERILOG PATH avl_adxphy.v TOP_LEVEL_FILE
# parameters
add_parameter TX_OR_RX_N INTEGER 0
set_parameter_property TX_OR_RX_N DISPLAY_NAME TX_OR_RX_N
set_parameter_property TX_OR_RX_N TYPE INTEGER
set_parameter_property TX_OR_RX_N UNITS None
set_parameter_property TX_OR_RX_N HDL_PARAMETER false
add_parameter NUM_OF_LANES INTEGER 4
set_parameter_property NUM_OF_LANES DISPLAY_NAME NUM_OF_LANES
set_parameter_property NUM_OF_LANES TYPE INTEGER
set_parameter_property NUM_OF_LANES UNITS None
set_parameter_property NUM_OF_LANES HDL_PARAMETER true
proc p_avl_adxphy {} {
set m_tx_or_rx_n [get_parameter_value TX_OR_RX_N]
set m_num_of_lanes [get_parameter_value NUM_OF_LANES]
if {$m_tx_or_rx_n == 1} {
ad_conduit tx_core_analogreset tx_analogreset tx_core_analogreset input $m_num_of_lanes
ad_conduit tx_core_digitalreset tx_digitalreset tx_core_digitalreset input $m_num_of_lanes
ad_conduit tx_core_cal_busy tx_cal_busy tx_core_cal_busy output $m_num_of_lanes
ad_conduit tx_ip_cal_busy tx_cal_busy tx_ip_cal_busy output $m_num_of_lanes
ad_conduit tx_ip_pcfifo_full export tx_ip_full output $m_num_of_lanes
ad_conduit tx_ip_pcfifo_empty export tx_ip_empty output $m_num_of_lanes
ad_conduit tx_ip_pcs_data export tx_ip_data input 32*$m_num_of_lanes
ad_conduit tx_ip_pcs_kchar_data export tx_ip_kchar input 4*$m_num_of_lanes
ad_conduit tx_ip_elecidle export tx_ip_elecidle input $m_num_of_lanes
ad_conduit tx_ip_csr_lane_polarity export tx_ip_lane_polarity input $m_num_of_lanes
ad_conduit tx_ip_csr_lane_powerdown export tx_ip_lane_powerdown input $m_num_of_lanes
ad_conduit tx_ip_csr_bit_reversal export rx_ip_bit_reversal input 1
ad_conduit tx_ip_csr_byte_reversal export rx_ip_byte_reversal input 1
for {set n 0} {$n < $m_num_of_lanes} {incr n} {
ad_conduit tx_ip_s_${n} export tx_ip_s_${n} input 3
ad_conduit tx_ip_d_${n} export tx_ip_d_${n} output 39
ad_conduit tx_phy_s_${n} export tx_phy_s_${n} output 3
ad_conduit tx_phy_d_${n} export tx_phy_d_${n} input 39
ad_conduit tx_phy${n}_cal_busy tx_cal_busy tx_phy_cal_busy_${n} input 1
ad_conduit tx_phy${n}_pcfifo_full export tx_phy_full_${n} input 1
ad_conduit tx_phy${n}_pcfifo_empty export tx_phy_empty_${n} input 1
ad_conduit tx_phy${n}_pcs_data export tx_phy_data_${n} output 32
ad_conduit tx_phy${n}_pcs_kchar_data export tx_phy_kchar_${n} output 4
ad_conduit tx_phy${n}_elecidle export tx_phy_elecidle_${n} output 1
ad_conduit tx_phy${n}_csr_lane_polarity export tx_phy_lane_polarity_${n} output 1
ad_conduit tx_phy${n}_csr_lane_powerdown export tx_phy_lane_powerdown_${n} output 1
ad_conduit tx_phy${n}_csr_bit_reversal export tx_phy_bit_reversal_${n} output 1
ad_conduit tx_phy${n}_csr_byte_reversal export tx_phy_byte_reversal_${n} output 1
ad_conduit tx_phy${n}_analogreset tx_analogreset tx_phy_analogreset_${n} output 1
ad_conduit tx_phy${n}_digitalreset tx_digitalreset tx_phy_digitalreset_${n} output 1
}
}
if {$m_tx_or_rx_n == 0} {
ad_conduit rx_core_analogreset rx_analogreset rx_core_analogreset input $m_num_of_lanes
ad_conduit rx_core_digitalreset rx_digitalreset rx_core_digitalreset input $m_num_of_lanes
ad_conduit rx_core_is_lockedtodata rx_is_lockedtodata rx_core_locked output $m_num_of_lanes
ad_conduit rx_core_cal_busy rx_cal_busy rx_core_cal_busy output $m_num_of_lanes
ad_conduit rx_ip_is_lockedtodata rx_is_lockedtodata rx_ip_locked output $m_num_of_lanes
ad_conduit rx_ip_cal_busy rx_cal_busy rx_ip_cal_busy output $m_num_of_lanes
ad_conduit rx_ip_pcs_data_valid export rx_ip_valid output $m_num_of_lanes
ad_conduit rx_ip_pcs_data export rx_ip_data output 32*$m_num_of_lanes
ad_conduit rx_ip_pcs_disperr export rx_ip_disperr output 4*$m_num_of_lanes
ad_conduit rx_ip_pcs_errdetect export rx_ip_deterr output 4*$m_num_of_lanes
ad_conduit rx_ip_pcs_kchar_data export rx_ip_kchar output 4*$m_num_of_lanes
ad_conduit rx_ip_pcfifo_full export rx_ip_full output $m_num_of_lanes
ad_conduit rx_ip_pcfifo_empty export rx_ip_empty output $m_num_of_lanes
ad_conduit rx_ip_patternalign_en export rx_ip_align_en input $m_num_of_lanes
ad_conduit rx_ip_csr_lane_polarity export rx_ip_lane_polarity input $m_num_of_lanes
ad_conduit rx_ip_csr_lane_powerdown export rx_ip_lane_powerdown input $m_num_of_lanes
ad_conduit rx_ip_csr_bit_reversal export rx_ip_bit_reversal input 1
ad_conduit rx_ip_csr_byte_reversal export rx_ip_byte_reversal input 1
for {set n 0} {$n < $m_num_of_lanes} {incr n} {
ad_conduit rx_phy${n}_is_lockedtodata rx_is_lockedtodata rx_phy_locked_${n} input 1
ad_conduit rx_phy${n}_cal_busy rx_cal_busy rx_phy_cal_busy_${n} input 1
ad_conduit rx_phy${n}_pcs_data_valid export rx_phy_valid_${n} input 1
ad_conduit rx_phy${n}_pcs_data export rx_phy_data_${n} input 32
ad_conduit rx_phy${n}_pcs_disperr export rx_phy_disperr_${n} input 4
ad_conduit rx_phy${n}_pcs_errdetect export rx_phy_deterr_${n} input 4
ad_conduit rx_phy${n}_pcs_kchar_data export rx_phy_kchar_${n} input 4
ad_conduit rx_phy${n}_pcfifo_full export rx_phy_full_${n} input 1
ad_conduit rx_phy${n}_pcfifo_empty export rx_phy_empty_${n} input 1
ad_conduit rx_phy${n}_patternalign_en export rx_phy_align_en_${n} output 1
ad_conduit rx_phy${n}_csr_lane_polarity export rx_phy_lane_polarity_${n} output 1
ad_conduit rx_phy${n}_csr_lane_powerdown export rx_phy_lane_powerdown_${n} output 1
ad_conduit rx_phy${n}_csr_bit_reversal export rx_phy_bit_reversal_${n} output 1
ad_conduit rx_phy${n}_csr_byte_reversal export rx_phy_byte_reversal_${n} output 1
ad_conduit rx_phy${n}_analogreset rx_analogreset rx_phy_analogreset_${n} output 1
ad_conduit rx_phy${n}_digitalreset rx_digitalreset rx_phy_digitalreset_${n} output 1
}
}
}

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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/1ps
module axi_adxcvr #(
// parameters
parameter integer ID = 0,
parameter integer TX_OR_RX_N = 0,
parameter integer NUM_OF_LANES = 4) (
// xcvr, lane-pll and ref-pll are shared
output up_rst,
input up_pll_locked,
input [(NUM_OF_LANES-1):0] up_ready,
input s_axi_aclk,
input s_axi_aresetn,
input s_axi_awvalid,
input [31:0] s_axi_awaddr,
input [ 2:0] s_axi_awprot,
output s_axi_awready,
input s_axi_wvalid,
input [31:0] s_axi_wdata,
input [ 3:0] s_axi_wstrb,
output s_axi_wready,
output s_axi_bvalid,
output [ 1:0] s_axi_bresp,
input s_axi_bready,
input s_axi_arvalid,
input [31:0] s_axi_araddr,
input [ 2:0] s_axi_arprot,
output s_axi_arready,
output s_axi_rvalid,
output [ 1:0] s_axi_rresp,
output [31:0] s_axi_rdata,
input s_axi_rready);
// internal signals
wire up_rstn;
wire up_clk;
wire up_wreq;
wire [ 9:0] up_waddr;
wire [31:0] up_wdata;
wire up_wack;
wire up_rreq;
wire [ 9:0] up_raddr;
wire [31:0] up_rdata;
wire up_rack;
// clk & rst
assign up_rstn = s_axi_aresetn;
assign up_clk = s_axi_aclk;
// instantiations
axi_adxcvr_up #(
.ID (ID),
.TX_OR_RX_N (TX_OR_RX_N),
.NUM_OF_LANES (NUM_OF_LANES))
i_up (
.up_rst (up_rst),
.up_pll_locked (up_pll_locked),
.up_ready (up_ready),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata),
.up_rack (up_rack));
up_axi #(.ADDRESS_WIDTH (10)) i_axi (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_axi_awvalid (s_axi_awvalid),
.up_axi_awaddr (s_axi_awaddr),
.up_axi_awready (s_axi_awready),
.up_axi_wvalid (s_axi_wvalid),
.up_axi_wdata (s_axi_wdata),
.up_axi_wstrb (s_axi_wstrb),
.up_axi_wready (s_axi_wready),
.up_axi_bvalid (s_axi_bvalid),
.up_axi_bresp (s_axi_bresp),
.up_axi_bready (s_axi_bready),
.up_axi_arvalid (s_axi_arvalid),
.up_axi_araddr (s_axi_araddr),
.up_axi_arready (s_axi_arready),
.up_axi_rvalid (s_axi_rvalid),
.up_axi_rresp (s_axi_rresp),
.up_axi_rdata (s_axi_rdata),
.up_axi_rready (s_axi_rready),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata),
.up_rack (up_rack));
endmodule
// ***************************************************************************
// ***************************************************************************

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package require -exact qsys 14.0
source ../../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip_alt.tcl
set_module_property NAME axi_adxcvr
set_module_property DESCRIPTION "AXI ADXCVR Core"
set_module_property VERSION 1.0
set_module_property GROUP "Analog Devices"
set_module_property DISPLAY_NAME axi_adxcvr
set_module_property ELABORATION_CALLBACK p_axi_adxcvr
# files
add_fileset quartus_synth QUARTUS_SYNTH "" ""
set_fileset_property quartus_synth TOP_LEVEL axi_adxcvr
add_fileset_file up_axi.v VERILOG PATH $ad_hdl_dir/library/common/up_axi.v
add_fileset_file axi_adxcvr_up.v VERILOG PATH axi_adxcvr_up.v
add_fileset_file axi_adxcvr.v VERILOG PATH axi_adxcvr.v TOP_LEVEL_FILE
# parameters
add_parameter ID INTEGER 0
set_parameter_property ID DISPLAY_NAME ID
set_parameter_property ID TYPE INTEGER
set_parameter_property ID UNITS None
set_parameter_property ID HDL_PARAMETER true
add_parameter TX_OR_RX_N INTEGER 0
set_parameter_property TX_OR_RX_N DISPLAY_NAME TX_OR_RX_N
set_parameter_property TX_OR_RX_N TYPE INTEGER
set_parameter_property TX_OR_RX_N UNITS None
set_parameter_property TX_OR_RX_N HDL_PARAMETER true
add_parameter NUM_OF_LANES INTEGER 4
set_parameter_property NUM_OF_LANES DISPLAY_NAME NUM_OF_LANES
set_parameter_property NUM_OF_LANES TYPE INTEGER
set_parameter_property NUM_OF_LANES UNITS None
set_parameter_property NUM_OF_LANES HDL_PARAMETER true
# axi4 slave interface
add_interface s_axi_clock clock end
add_interface_port s_axi_clock s_axi_aclk clk Input 1
add_interface s_axi_reset reset end
set_interface_property s_axi_reset associatedClock s_axi_clock
add_interface_port s_axi_reset s_axi_aresetn reset_n Input 1
add_interface s_axi axi4lite end
set_interface_property s_axi associatedClock s_axi_clock
set_interface_property s_axi associatedReset s_axi_reset
add_interface_port s_axi s_axi_awvalid awvalid Input 1
add_interface_port s_axi s_axi_awaddr awaddr Input 16
add_interface_port s_axi s_axi_awprot awprot Input 3
add_interface_port s_axi s_axi_awready awready Output 1
add_interface_port s_axi s_axi_wvalid wvalid Input 1
add_interface_port s_axi s_axi_wdata wdata Input 32
add_interface_port s_axi s_axi_wstrb wstrb Input 4
add_interface_port s_axi s_axi_wready wready Output 1
add_interface_port s_axi s_axi_bvalid bvalid Output 1
add_interface_port s_axi s_axi_bresp bresp Output 2
add_interface_port s_axi s_axi_bready bready Input 1
add_interface_port s_axi s_axi_arvalid arvalid Input 1
add_interface_port s_axi s_axi_araddr araddr Input 16
add_interface_port s_axi s_axi_arprot arprot Input 3
add_interface_port s_axi s_axi_arready arready Output 1
add_interface_port s_axi s_axi_rvalid rvalid Output 1
add_interface_port s_axi s_axi_rresp rresp Output 2
add_interface_port s_axi s_axi_rdata rdata Output 32
add_interface_port s_axi s_axi_rready rready Input 1
# xcvr interface
ad_alt_intf reset up_rst output 1 s_axi_clock
set_interface_property if_up_rst associatedResetSinks s_axi_reset
add_interface core_pll_locked conduit end
add_interface_port core_pll_locked up_pll_locked export Input 1
# name changes
proc p_axi_adxcvr {} {
set m_tx_or_rx_n [get_parameter_value TX_OR_RX_N]
set m_num_of_lanes [get_parameter_value NUM_OF_LANES]
if {$m_tx_or_rx_n == 1} {
add_interface ready conduit end
add_interface_port ready up_ready tx_ready input $m_num_of_lanes
}
if {$m_tx_or_rx_n == 0} {
add_interface ready conduit end
add_interface_port ready up_ready rx_ready input $m_num_of_lanes
}
}

184
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@ -0,0 +1,184 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_adxcvr_up #(
// parameters
parameter integer ID = 0,
parameter integer TX_OR_RX_N = 0,
parameter integer NUM_OF_LANES = 4) (
// xcvr, lane-pll and ref-pll are shared
output up_rst,
input up_pll_locked,
input [(NUM_OF_LANES-1):0] up_ready,
// bus interface
input up_rstn,
input up_clk,
input up_wreq,
input [ 9:0] up_waddr,
input [31:0] up_wdata,
output up_wack,
input up_rreq,
input [ 9:0] up_raddr,
output [31:0] up_rdata,
output up_rack);
// parameters
localparam [31:0] VERSION = 32'h00100161;
// internal registers
reg up_wreq_d = 'd0;
reg [31:0] up_scratch = 'd0;
reg up_resetn = 'd0;
reg [ 3:0] up_rst_cnt = 'd8;
reg up_status_int = 'd0;
reg up_rreq_d = 'd0;
reg [31:0] up_rdata_d = 'd0;
// internal signals
wire up_ready_s;
wire [31:0] up_status_32_s;
wire [31:0] up_rparam_s;
// defaults
assign up_wack = up_wreq_d;
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_wreq_d <= 'd0;
up_scratch <= 'd0;
end else begin
up_wreq_d <= up_wreq;
if ((up_wreq == 1'b1) && (up_waddr == 10'h002)) begin
up_scratch <= up_wdata;
end
end
end
// reset-controller
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_resetn <= 'd0;
end else begin
if ((up_wreq == 1'b1) && (up_waddr == 10'h004)) begin
up_resetn <= up_wdata[0];
end
end
end
assign up_rst = up_rst_cnt[3];
assign up_ready_s = & up_status_32_s[NUM_OF_LANES:1];
assign up_status_32_s[31:(NUM_OF_LANES+1)] = 'd0;
assign up_status_32_s[NUM_OF_LANES] = up_pll_locked;
assign up_status_32_s[(NUM_OF_LANES-1):0] = up_ready;
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_rst_cnt <= 4'h8;
up_status_int <= 1'b0;
end else begin
if (up_resetn == 1'b0) begin
up_rst_cnt <= 4'h8;
end else if (up_rst_cnt[3] == 1'b1) begin
up_rst_cnt <= up_rst_cnt + 1'b1;
end
if (up_resetn == 1'b0) begin
up_status_int <= 1'b0;
end else if (up_ready_s == 1'b1) begin
up_status_int <= 1'b1;
end
end
end
// altera specific
assign up_rparam_s[31:24] = 8'd0;
// xilinx specific
assign up_rparam_s[23:16] = 8'd0;
// generic
assign up_rparam_s[15: 9] = 7'd0;
assign up_rparam_s[ 8: 8] = (TX_OR_RX_N == 0) ? 1'b0 : 1'b1;
assign up_rparam_s[ 7: 0] = NUM_OF_LANES;
// read interface
assign up_rack = up_rreq_d;
assign up_rdata = up_rdata_d;
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_rreq_d <= 'd0;
up_rdata_d <= 'd0;
end else begin
up_rreq_d <= up_rreq;
if (up_rreq == 1'b1) begin
case (up_raddr)
10'h000: up_rdata_d <= VERSION;
10'h001: up_rdata_d <= ID;
10'h002: up_rdata_d <= up_scratch;
10'h004: up_rdata_d <= {31'd0, up_resetn};
10'h005: up_rdata_d <= {31'd0, up_status_int};
10'h006: up_rdata_d <= up_status_32_s;
10'h009: up_rdata_d <= up_rparam_s;
default: up_rdata_d <= 32'd0;
endcase
end else begin
up_rdata_d <= 32'd0;
end
end
end
endmodule
// ***************************************************************************
// ***************************************************************************

89
library/altera/common/ad_cmos_clk.v Normal file
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@ -0,0 +1,89 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module ad_cmos_clk (
rst,
locked,
clk_in,
clk);
parameter DEVICE_TYPE = 0;
input rst;
output locked;
input clk_in;
output clk;
// instantiations
generate
if (DEVICE_TYPE == 0) begin
alt_clk i_clk (
.rst (rst),
.refclk (clk_in),
.outclk_0 (clk),
.locked (locked));
end
endgenerate
generate
if (DEVICE_TYPE == 1) begin
altera_pll #(
.reference_clock_frequency("250.0 MHz"),
.operation_mode("source synchronous"),
.number_of_clocks(1),
.output_clock_frequency0("0 MHz"),
.phase_shift0("0"))
i_clk (
.rst (rst),
.refclk (clk_in),
.outclk (clk),
.fboutclk (),
.fbclk (1'b0),
.locked (locked));
end
endgenerate
endmodule
// ***************************************************************************
// ***************************************************************************

138
library/altera/common/ad_cmos_in.v Normal file
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@ -0,0 +1,138 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module ad_cmos_in (
// data interface
rx_clk,
rx_data_in,
rx_data_p,
rx_data_n,
// delay-data interface
up_clk,
up_dld,
up_dwdata,
up_drdata,
// delay-cntrl interface
delay_clk,
delay_rst,
delay_locked);
// parameters
parameter SINGLE_ENDED = 0;
parameter DEVICE_TYPE = 0;
parameter IODELAY_CTRL = 0;
parameter IODELAY_GROUP = "dev_if_delay_group";
// data interface
input rx_clk;
input rx_data_in;
output rx_data_p;
output rx_data_n;
// delay-data interface
input up_clk;
input up_dld;
input [ 4:0] up_dwdata;
output [ 4:0] up_drdata;
// delay-cntrl interface
input delay_clk;
input delay_rst;
output delay_locked;
// internal registers
reg rx_data_p = 'd0;
reg rx_data_n = 'd0;
// internal signals
wire rx_data_p_s;
wire rx_data_n_s;
// defaults
assign up_drdata = 5'd0;
assign delay_locked = 1'b1;
// instantiations
generate
if (DEVICE_TYPE == 0) begin
alt_ddio_in i_rx_data_iddr (
.ck (rx_clk),
.pad_in (rx_data_in),
.dout ({rx_data_p_s, rx_data_n_s}));
end
endgenerate
generate
if (DEVICE_TYPE == 1) begin
altddio_in #(.width (1), .lpm_hint("UNUSED")) i_rx_data_iddr (
.inclock (rx_clk),
.datain (rx_data_in),
.dataout_h (rx_data_p_s),
.dataout_l (rx_data_n_s),
.inclocken (1'b1),
.aclr (1'b0),
.aset (1'b0),
.sclr (1'b0),
.sset (1'b0));
end
endgenerate
always @(posedge rx_clk) begin
rx_data_p <= rx_data_p_s;
rx_data_n <= rx_data_n_s;
end
endmodule
// ***************************************************************************
// ***************************************************************************

101
library/altera/common/ad_cmos_out.v Normal file
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@ -0,0 +1,101 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module __ad_cmos_out__ #(
parameter DEVICE_TYPE = 0,
parameter SINGLE_ENDED = 0,
parameter IODELAY_ENABLE = 0,
parameter IODELAY_CTRL = 0,
parameter IODELAY_GROUP = "dev_if_delay_group") (
// data interface
input tx_clk,
input tx_data_p,
input tx_data_n,
output tx_data_out,
// delay-data interface
input up_clk,
input up_dld,
input [ 4:0] up_dwdata,
output [ 4:0] up_drdata,
// delay-cntrl interface
input delay_clk,
input delay_rst,
output delay_locked);
// local parameter
localparam ARRIA10 = 0;
localparam CYCLONE5 = 1;
// defaults
assign up_drdata = 5'd0;
assign delay_locked = 1'b1;
// instantiations
generate
if (DEVICE_TYPE == ARRIA10) begin
__ad_cmos_out_1__ i_tx_data_oddr (
.clk_export (tx_clk),
.din_export ({tx_data_p, tx_data_n}),
.pad_out_export (tx_data_out));
end
endgenerate
generate
if (DEVICE_TYPE == CYCLONE5) begin
ad_cmos_out_core_c5 i_tx_data_oddr (
.clk (tx_clk),
.din ({tx_data_p, tx_data_n}),
.pad_out (tx_data_out));
end
endgenerate
endmodule
// ***************************************************************************
// ***************************************************************************

36
library/common/altera/ad_lvds_clk.v → library/altera/common/ad_cmos_out_core_c5.v
View File

@ -34,26 +34,34 @@
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
`timescale 1ns/1ps
module ad_lvds_clk (
module ad_cmos_out_core_c5 (
clk_in_p,
clk_in_n,
clk);
// data interface
parameter DEVICE_TYPE = 0;
localparam SERIES7 = 0;
localparam VIRTEX6 = 1;
input clk,
input [ 1:0] din,
output pad_out);
input clk_in_p;
input clk_in_n;
output clk;
// instantiations
assign clk = clk_in_p;
altddio_out #(
.width (1),
.lpm_hint ("UNUSED"))
i_altddio_out (
.outclock (clk),
.datain_h (din[1]),
.datain_l (din[0]),
.dataout (pad_out),
.outclocken (1'b1),
.oe_out (),
.oe (1'b1),
.aclr (1'b0),
.aset (1'b0),
.sclr (1'b0),
.sset (1'b0));
endmodule

57
library/common/altera/ad_dcfilter_alt.v → library/altera/common/ad_dcfilter.v Normal file → Executable file
View File

@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014(c) Analog Devices, Inc.
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
@ -34,41 +34,30 @@
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// dc filter- y(n) = c*x(n) + (1-c)*y(n-1)
// NOT IMPLEMENTED
`timescale 1ps/1ps
module ad_dcfilter (
module ad_dcfilter #(
// data path disable
parameter DISABLE = 0) (
// data interface
clk,
valid,
data,
valid_out,
data_out,
input clk,
input valid,
input [15:0] data,
output reg valid_out,
output reg [15:0] data_out,
// control interface
dcfilt_enb,
dcfilt_coeff,
dcfilt_offset);
// data interface
input clk;
input valid;
input [15:0] data;
output valid_out;
output [15:0] data_out;
// control interface
input dcfilt_enb;
input [15:0] dcfilt_coeff;
input [15:0] dcfilt_offset;
input dcfilt_enb,
input [15:0] dcfilt_coeff,
input [15:0] dcfilt_offset);
// internal registers
@ -76,28 +65,20 @@ module ad_dcfilter (
reg [15:0] data_d = 'd0;
reg valid_2d = 'd0;
reg [15:0] data_2d = 'd0;
reg valid_out = 'd0;
reg [15:0] data_out = 'd0;
// internal signals
// cancelling the dc offset
wire [47:0] dc_offset_s;
always @(posedge clk) begin
dc_offset <= 16'h0;
valid_d <= valid;
if (valid == 1'b1) begin
data_d <= data + dcfilt_offset;
end
valid_2d <= valid_d;
data_2d <= data_d - dc_offset;
if (dcfilt_enb == 1'b1) begin
data_2d <= data_d;
valid_out <= valid_2d;
data_out <= data_d; // DC filter not implemented in this version
end else begin
valid_out <= valid_d;
data_out <= data_d;
end
data_out <= data_2d;
end
endmodule

89
library/altera/common/ad_lvds_clk.v Normal file
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@ -0,0 +1,89 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module ad_lvds_clk (
rst,
locked,
clk_in_p,
clk_in_n,
clk);
parameter DEVICE_TYPE = 0;
input rst;
output locked;
input clk_in_p;
input clk_in_n;
output clk;
// instantiations
generate
if (DEVICE_TYPE == 0) begin
alt_clk i_clk (
.rst (rst),
.refclk (clk_in_p),
.outclk_0 (clk),
.locked (locked));
end
endgenerate
generate
if (DEVICE_TYPE == 1) begin
altera_pll #(
.reference_clock_frequency("250.0 MHz"),
.operation_mode("lvds"),
.number_of_clocks(1),
.output_clock_frequency0("250.0 MHz"),
.phase_shift0("0"))
i_clk (
.rst (rst),
.refclk (clk_in_p),
.outclk (clk),
.locked (locked));
end
endgenerate
endmodule
// ***************************************************************************
// ***************************************************************************

79
library/common/altera/ad_lvds_in.v → library/altera/common/ad_lvds_in.v
View File

@ -34,8 +34,6 @@
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
@ -49,22 +47,25 @@ module ad_lvds_in (
rx_data_p,
rx_data_n,
// delay interface
// delay-data interface
up_clk,
up_dld,
up_dwdata,
up_drdata,
// delay-cntrl interface
delay_clk,
delay_rst,
delay_ld,
delay_wdata,
delay_rdata,
delay_locked);
// parameters
parameter SINGLE_ENDED = 0;
parameter DEVICE_TYPE = 0;
parameter IODELAY_CTRL = 0;
parameter IODELAY_GROUP = "dev_if_delay_group";
localparam SERIES7 = 0;
localparam VIRTEX6 = 1;
// data interface
@ -74,38 +75,64 @@ module ad_lvds_in (
output rx_data_p;
output rx_data_n;
// delay interface
// delay-data interface
input up_clk;
input up_dld;
input [ 4:0] up_dwdata;
output [ 4:0] up_drdata;
// delay-cntrl interface
input delay_clk;
input delay_rst;
input delay_ld;
input [ 4:0] delay_wdata;
output [ 4:0] delay_rdata;
output delay_locked;
// internal registers
reg rx_data_p = 'd0;
reg rx_data_n = 'd0;
// internal signals
wire rx_data_p_s;
wire rx_data_n_s;
// defaults
assign delay_rdata = 5'd0;
assign up_drdata = 5'd0;
assign delay_locked = 1'b1;
// instantiations
altddio_in #(
.invert_input_clocks("OFF"),
.lpm_hint("UNUSED"),
.lpm_type("altddio_in"),
.power_up_high("OFF"),
.width(1))
i_rx_data_iddr (
generate
if (DEVICE_TYPE == 0) begin
alt_ddio_in i_rx_data_iddr (
.ck (rx_clk),
.pad_in (rx_data_in_p),
.dout ({rx_data_p_s, rx_data_n_s}));
end
endgenerate
generate
if (DEVICE_TYPE == 1) begin
altddio_in #(.width (1), .lpm_hint("UNUSED")) i_rx_data_iddr (
.inclock (rx_clk),
.datain (rx_data_in_p),
.dataout_h (rx_data_p_s),
.dataout_l (rx_data_n_s),
.inclocken (1'b1),
.aclr (1'b0),
.aset (1'b0),
.sclr (1'b0),
.sset (1'b0),
.inclocken (1'b1),
.inclock (rx_clk),
.datain (rx_data_in_p),
.dataout_h (rx_data_p),
.dataout_l (rx_data_n));
.sset (1'b0));
end
endgenerate
always @(posedge rx_clk) begin
rx_data_p <= rx_data_p_s;
rx_data_n <= rx_data_n_s;
end
endmodule

79
library/common/altera/ad_lvds_out.v → library/altera/common/ad_lvds_out.v
View File

@ -34,8 +34,6 @@
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
@ -47,13 +45,28 @@ module ad_lvds_out (
tx_data_p,
tx_data_n,
tx_data_out_p,
tx_data_out_n);
tx_data_out_n,
// delay-data interface
up_clk,
up_dld,
up_dwdata,
up_drdata,
// delay-cntrl interface
delay_clk,
delay_rst,
delay_locked);
// parameters
parameter DEVICE_TYPE = 0;
localparam SERIES7 = 0;
localparam VIRTEX6 = 1;
parameter SINGLE_ENDED = 0;
parameter IODELAY_ENABLE = 0;
parameter IODELAY_CTRL = 0;
parameter IODELAY_GROUP = "dev_if_delay_group";
// data interface
@ -63,33 +76,51 @@ module ad_lvds_out (
output tx_data_out_p;
output tx_data_out_n;
// delay-data interface
input up_clk;
input up_dld;
input [ 4:0] up_dwdata;
output [ 4:0] up_drdata;
// delay-cntrl interface
input delay_clk;
input delay_rst;
output delay_locked;
// defaults
assign tx_data_out_n = 1'd0;
assign up_drdata = 5'd0;
assign delay_locked = 1'b1;
// instantiations
altddio_out #(
.extend_oe_disable("OFF"),
.intended_device_family("Cyclone V"),
.invert_output("OFF"),
.lpm_hint("UNUSED"),
.lpm_type("altddio_out"),
.oe_reg("UNREGISTERED"),
.power_up_high("OFF"),
.width(1))
i_tx_data_oddr (
.aclr (1'b0),
.aset (1'b0),
.sclr (1'b0),
.sset (1'b0),
.oe (1'b1),
.oe_out (),
.outclocken (1'b1),
generate
if (DEVICE_TYPE == 0) begin
alt_ddio_out i_tx_data_oddr (
.ck (tx_clk),
.din ({tx_data_p, tx_data_n}),
.pad_out (tx_data_out_p));
end
endgenerate
generate
if (DEVICE_TYPE == 1) begin
altddio_out #(.width (1), .lpm_hint ("UNUSED")) i_tx_data_oddr (
.outclock (tx_clk),
.datain_h (tx_data_p),
.datain_l (tx_data_n),
.dataout (tx_data_out_p));
.dataout (tx_data_out_p),
.outclocken (1'b1),
.oe_out (),
.oe (1'b1),
.aclr (1'b0),
.aset (1'b0),
.sclr (1'b0),
.sset (1'b0));
end
endgenerate
endmodule

53
library/common/ad_mul_u16.v → library/altera/common/ad_mul.v
View File

@ -36,12 +36,10 @@
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// both inputs are considered unsigned 16 bits-
// ddata is delay matched generic data
`timescale 1ps/1ps
module ad_mul_u16 (
module ad_mul (
// data_p = data_a * data_b;
@ -58,29 +56,24 @@ module ad_mul_u16 (
// delayed data bus width
parameter DELAY_DATA_WIDTH = 16;
localparam DW = DELAY_DATA_WIDTH - 1;
// data_p = data_a * data_b;
input clk;
input [15:0] data_a;
input [15:0] data_b;
output [31:0] data_p;
input [16:0] data_a;
input [16:0] data_b;
output [33:0] data_p;
// delay interface
input [DW:0] ddata_in;
output [DW:0] ddata_out;
input [(DELAY_DATA_WIDTH-1):0] ddata_in;
output [(DELAY_DATA_WIDTH-1):0] ddata_out;
// internal registers
reg [DW:0] p1_ddata = 'd0;
reg [DW:0] p2_ddata = 'd0;
reg [DW:0] ddata_out = 'd0;
// internal signals
wire [33:0] data_p_s;
reg [(DELAY_DATA_WIDTH-1):0] p1_ddata = 'd0;
reg [(DELAY_DATA_WIDTH-1):0] p2_ddata = 'd0;
reg [(DELAY_DATA_WIDTH-1):0] ddata_out = 'd0;
// a/b reg, m-reg, p-reg delay match
@ -90,19 +83,21 @@ module ad_mul_u16 (
ddata_out <= p2_ddata;
end
assign data_p = data_p_s[31:0];
MULT_MACRO #(
.LATENCY (3),
.A_DATA_WIDTH (17),
.B_DATA_WIDTH (17))
i_mult_macro (
.CE (1'b1),
.RST (1'b0),
.CLK (clk),
.A ({1'b0, data_a}),
.B ({1'b0, data_b}),
.P (data_p_s));
lpm_mult #(
.lpm_type ("lpm_mult"),
.lpm_widtha (17),
.lpm_widthb (17),
.lpm_widthp (34),
.lpm_representation ("SIGNED"),
.lpm_pipeline (3))
i_lpm_mult (
.clken (1'b1),
.aclr (1'b0),
.sum (1'b0),
.clock (clk),
.dataa (data_a),
.datab (data_b),
.result (data_p));
endmodule

211
library/altera/common/ad_serdes_clk.v Normal file
View File

@ -0,0 +1,211 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
`timescale 1ps/1ps
module __ad_serdes_clk__ #(
// parameters
parameter DEVICE_TYPE = 0,
parameter DDR_OR_SDR_N = 1,
parameter SERDES_FACTOR = 8,
parameter MMCM_OR_BUFR_N = 1,
parameter MMCM_CLKIN_PERIOD = 1.667,
parameter MMCM_VCO_DIV = 6,
parameter MMCM_VCO_MUL = 12.000,
parameter MMCM_CLK0_DIV = 2.000,
parameter MMCM_CLK1_DIV = 6) (
// clock and divided clock
input rst,
input clk_in_p,
input clk_in_n,
output clk,
output div_clk,
output out_clk,
output loaden,
output [ 7:0] phase,
// drp interface
input up_clk,
input up_rstn,
input up_drp_sel,
input up_drp_wr,
input [11:0] up_drp_addr,
input [31:0] up_drp_wdata,
output [31:0] up_drp_rdata,
output up_drp_ready,
output up_drp_locked);
// local parameter
localparam ARRIA10 = 0;
localparam CYCLONE5 = 1;
// internal registers
reg up_drp_sel_int = 'd0;
reg up_drp_rd_int = 'd0;
reg up_drp_wr_int = 'd0;
reg [ 8:0] up_drp_addr_int = 'd0;
reg [31:0] up_drp_wdata_int = 'd0;
reg [31:0] up_drp_rdata_int = 'd0;
reg up_drp_ready_int = 'd0;
reg up_drp_locked_int_m = 'd0;
reg up_drp_locked_int = 'd0;
// internal signals
wire up_drp_reset;
wire [31:0] up_drp_rdata_int_s;
wire up_drp_busy_int_s;
wire up_drp_locked_int_s;
wire loaden_s;
wire clk_s;
// defaults
assign up_drp_reset = ~up_rstn;
assign out_clk = div_clk;
assign up_drp_rdata = up_drp_rdata_int;
assign up_drp_ready = up_drp_ready_int;
assign up_drp_locked = up_drp_locked_int;
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 1'b0) begin
up_drp_sel_int <= 1'b0;
up_drp_rd_int <= 1'b0;
up_drp_wr_int <= 1'b0;
up_drp_addr_int <= 9'd0;
up_drp_wdata_int <= 32'd0;
up_drp_rdata_int <= 32'd0;
up_drp_ready_int <= 1'b0;
up_drp_locked_int_m <= 1'd0;
up_drp_locked_int <= 1'd0;
end else begin
if (up_drp_sel_int == 1'b1) begin
if (up_drp_busy_int_s == 1'b0) begin
up_drp_sel_int <= 1'b0;
up_drp_rd_int <= 1'b0;
up_drp_wr_int <= 1'b0;
up_drp_addr_int <= 9'd0;
up_drp_wdata_int <= 32'd0;
up_drp_rdata_int <= up_drp_rdata_int_s;
up_drp_ready_int <= 1'b1;
end
end else if (up_drp_sel == 1'b1) begin
up_drp_sel_int <= 1'b1;
up_drp_rd_int <= ~up_drp_wr;
up_drp_wr_int <= up_drp_wr;
up_drp_addr_int <= up_drp_addr[8:0];
up_drp_wdata_int <= up_drp_wdata;
up_drp_rdata_int <= 32'd0;
up_drp_ready_int <= 1'b0;
end else begin
up_drp_sel_int <= 1'b0;
up_drp_rd_int <= 1'b0;
up_drp_wr_int <= 1'b0;
up_drp_addr_int <= 9'd0;
up_drp_wdata_int <= 32'd0;
up_drp_rdata_int <= 32'd0;
up_drp_ready_int <= 1'b0;
end
up_drp_locked_int_m <= up_drp_locked_int_s;
up_drp_locked_int <= up_drp_locked_int_m;
end
end
generate
if (DEVICE_TYPE == ARRIA10) begin
__ad_serdes_clk_1__ i_core (
.rst_reset (rst),
.ref_clk_clk (clk_in_p),
.locked_export (up_drp_locked_int_s),
.hs_phase_phout (phase),
.hs_clk_lvds_clk (clk),
.loaden_loaden (loaden),
.ls_clk_clk (div_clk),
.drp_clk_clk (up_clk),
.drp_rst_reset (up_drp_reset),
.pll_reconfig_waitrequest (up_drp_busy_int_s),
.pll_reconfig_read (up_drp_rd_int),
.pll_reconfig_write (up_drp_wr_int),
.pll_reconfig_readdata (up_drp_rdata_int_s),
.pll_reconfig_address (up_drp_addr_int),
.pll_reconfig_writedata (up_drp_wdata_int));
end
endgenerate
generate
if (DEVICE_TYPE == CYCLONE5) begin
assign phase = 8'd0;
__ad_serdes_clk_1__ i_core (
.rst_reset (rst),
.ref_clk_clk (clk_in_p),
.locked_export (up_drp_locked_int_s),
.hs_clk_clk (clk_s),
.loaden_clk (loaden_s),
.ls_clk_clk (div_clk),
.drp_clk_clk (up_clk),
.drp_rst_reset (up_drp_reset),
.pll_reconfig_waitrequest (up_drp_busy_int_s),
.pll_reconfig_read (up_drp_rd_int),
.pll_reconfig_write (up_drp_wr_int),
.pll_reconfig_readdata (up_drp_rdata_int_s),
.pll_reconfig_address (up_drp_addr_int[5:0]),
.pll_reconfig_writedata (up_drp_wdata_int));
cyclonev_pll_lvds_output #(
.pll_loaden_enable_disable ("true"),
.pll_lvdsclk_enable_disable ("true"))
i_clk_buf (
.ccout ({loaden_s, clk_s}),
.loaden (loaden),
.lvdsclk (clk));
end
endgenerate
endmodule
// ***************************************************************************
// ***************************************************************************

170
library/altera/common/ad_serdes_in.v Normal file
View File

@ -0,0 +1,170 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
`timescale 1ps/1ps
module __ad_serdes_in__ #(
// parameters
parameter DEVICE_TYPE = 0,
parameter DDR_OR_SDR_N = 0,
parameter SERDES_FACTOR = 8,
parameter DATA_WIDTH = 16,
parameter IODELAY_CTRL = 0,
parameter IODELAY_GROUP = "dev_if_delay_group") (
// reset and clocks
input rst,
input clk,
input div_clk,
input loaden,
input [ 7:0] phase,
input locked,
// data interface
output [(DATA_WIDTH-1):0] data_s0,
output [(DATA_WIDTH-1):0] data_s1,
output [(DATA_WIDTH-1):0] data_s2,
output [(DATA_WIDTH-1):0] data_s3,
output [(DATA_WIDTH-1):0] data_s4,
output [(DATA_WIDTH-1):0] data_s5,
output [(DATA_WIDTH-1):0] data_s6,
output [(DATA_WIDTH-1):0] data_s7,
input [(DATA_WIDTH-1):0] data_in_p,
input [(DATA_WIDTH-1):0] data_in_n,
// delay-data interface
input up_clk,
input [(DATA_WIDTH-1):0] up_dld,
input [((DATA_WIDTH*5)-1):0] up_dwdata,
output [((DATA_WIDTH*5)-1):0] up_drdata,
// delay-control interface
input delay_clk,
input delay_rst,
output delay_locked);
// local parameter
localparam ARRIA10 = 0;
localparam CYCLONE5 = 1;
// internal signals
wire [(DATA_WIDTH-1):0] delay_locked_s;
wire [(DATA_WIDTH-1):0] data_samples_s[0:(SERDES_FACTOR-1)];
wire [(SERDES_FACTOR-1):0] data_out_s[0:(DATA_WIDTH-1)];
// assignments
assign up_drdata = 5'd0;
assign delay_locked = & delay_locked_s;
// instantiations
genvar n;
genvar i;
generate
if (SERDES_FACTOR == 8) begin
assign data_s7 = data_samples_s[7];
assign data_s6 = data_samples_s[6];
assign data_s5 = data_samples_s[5];
assign data_s4 = data_samples_s[4];
end else begin
assign data_s7 = 'd0;
assign data_s6 = 'd0;
assign data_s5 = 'd0;
assign data_s4 = 'd0;
end
endgenerate
assign data_s3 = data_samples_s[3];
assign data_s2 = data_samples_s[2];
assign data_s1 = data_samples_s[1];
assign data_s0 = data_samples_s[0];
generate
for (i = 0; i < SERDES_FACTOR; i = i + 1) begin: g_samples
for (n = 0; n < DATA_WIDTH; n = n + 1) begin: g_swap
assign data_samples_s[i][n] = data_out_s[n][((SERDES_FACTOR-1)-i)];
end
end
endgenerate
generate
for (n = 0; n < DATA_WIDTH; n = n + 1) begin: g_data
if (DEVICE_TYPE == CYCLONE5) begin
assign delay_locked_s[n] = 1'b1;
ad_serdes_in_core_c5 #(
.SERDES_FACTOR (SERDES_FACTOR))
i_core (
.clk (clk),
.div_clk (div_clk),
.enable (loaden),
.data_in (data_in_p[n]),
.data (data_out_s[n]));
end
if (DEVICE_TYPE == ARRIA10) begin
__ad_serdes_in_1__ i_core (
.clk_export (clk),
.div_clk_export (div_clk),
.hs_phase_export (phase),
.loaden_export (loaden),
.locked_export (locked),
.data_in_export (data_in_p[n]),
.data_s_export (data_out_s[n]),
.delay_locked_export (delay_locked_s[n]));
end
end
endgenerate
endmodule
// ***************************************************************************
// ***************************************************************************

146
library/altera/common/ad_serdes_in_core_c5.v Normal file
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@ -0,0 +1,146 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
`timescale 1ps/1ps
module ad_serdes_in_core_c5 #(
parameter SERDES_FACTOR = 8) (
input clk,
input div_clk,
input enable,
input data_in,
output [(SERDES_FACTOR-1):0] data);
reg [(SERDES_FACTOR-1):0] data_int = 'd0;
wire [(SERDES_FACTOR-1):0] data_s;
assign data = data_int;
always @(posedge div_clk) begin
data_int <= data_s;
end
altlvds_rx i_altlvds_rx (
.rx_enable (enable),
.rx_in (data_in),
.rx_inclock (clk),
.rx_out (data_s),
.dpa_pll_cal_busy (),
.dpa_pll_recal (1'b0),
.pll_areset (1'b0),
.pll_phasecounterselect (),
.pll_phasedone (1'b1),
.pll_phasestep (),
.pll_phaseupdown (),
.pll_scanclk (),
.rx_cda_max (),
.rx_cda_reset (1'b0),
.rx_channel_data_align (1'b0),
.rx_coreclk (1'b1),
.rx_data_align (1'b0),
.rx_data_align_reset (1'b0),
.rx_data_reset (1'b0),
.rx_deskew (1'b0),
.rx_divfwdclk (),
.rx_dpa_lock_reset (1'b0),
.rx_dpa_locked (),
.rx_dpaclock (1'b0),
.rx_dpll_enable (1'b1),
.rx_dpll_hold (1'b0),
.rx_dpll_reset (1'b0),
.rx_fifo_reset (1'b0),
.rx_locked (),
.rx_outclock (),
.rx_pll_enable (1'b1),
.rx_readclock (1'b0),
.rx_reset (1'b0),
.rx_syncclock (1'b0));
defparam
i_altlvds_rx.buffer_implementation = "RAM",
i_altlvds_rx.cds_mode = "UNUSED",
i_altlvds_rx.common_rx_tx_pll = "OFF",
i_altlvds_rx.data_align_rollover = 4,
i_altlvds_rx.data_rate = "800.0 Mbps",
i_altlvds_rx.deserialization_factor = SERDES_FACTOR,
i_altlvds_rx.dpa_initial_phase_value = 0,
i_altlvds_rx.dpll_lock_count = 0,
i_altlvds_rx.dpll_lock_window = 0,
i_altlvds_rx.enable_clock_pin_mode = "UNUSED",
i_altlvds_rx.enable_dpa_align_to_rising_edge_only = "OFF",
i_altlvds_rx.enable_dpa_calibration = "ON",
i_altlvds_rx.enable_dpa_fifo = "UNUSED",
i_altlvds_rx.enable_dpa_initial_phase_selection = "OFF",
i_altlvds_rx.enable_dpa_mode = "OFF",
i_altlvds_rx.enable_dpa_pll_calibration = "OFF",
i_altlvds_rx.enable_soft_cdr_mode = "OFF",
i_altlvds_rx.implement_in_les = "OFF",
i_altlvds_rx.inclock_boost = 0,
i_altlvds_rx.inclock_data_alignment = "EDGE_ALIGNED",
i_altlvds_rx.inclock_period = 50000,
i_altlvds_rx.inclock_phase_shift = 0,
i_altlvds_rx.input_data_rate = 800,
i_altlvds_rx.intended_device_family = "Cyclone V",
i_altlvds_rx.lose_lock_on_one_change = "UNUSED",
i_altlvds_rx.lpm_hint = "CBX_MODULE_PREFIX=ad_serdes_in_core_c5",
i_altlvds_rx.lpm_type = "altlvds_rx",
i_altlvds_rx.number_of_channels = 1,
i_altlvds_rx.outclock_resource = "Dual-Regional clock",
i_altlvds_rx.pll_operation_mode = "NORMAL",
i_altlvds_rx.pll_self_reset_on_loss_lock = "UNUSED",
i_altlvds_rx.port_rx_channel_data_align = "PORT_UNUSED",
i_altlvds_rx.port_rx_data_align = "PORT_UNUSED",
i_altlvds_rx.refclk_frequency = "20.000000 MHz",
i_altlvds_rx.registered_data_align_input = "UNUSED",
i_altlvds_rx.registered_output = "OFF",
i_altlvds_rx.reset_fifo_at_first_lock = "UNUSED",
i_altlvds_rx.rx_align_data_reg = "RISING_EDGE",
i_altlvds_rx.sim_dpa_is_negative_ppm_drift = "OFF",
i_altlvds_rx.sim_dpa_net_ppm_variation = 0,
i_altlvds_rx.sim_dpa_output_clock_phase_shift = 0,
i_altlvds_rx.use_coreclock_input = "OFF",
i_altlvds_rx.use_dpll_rawperror = "OFF",
i_altlvds_rx.use_external_pll = "ON",
i_altlvds_rx.use_no_phase_shift = "ON",
i_altlvds_rx.x_on_bitslip = "ON",
i_altlvds_rx.clk_src_is_pll = "off";
endmodule
// ***************************************************************************
// ***************************************************************************

138
library/altera/common/ad_serdes_out.v Normal file
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@ -0,0 +1,138 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
`timescale 1ps/1ps
module __ad_serdes_out__ #(
parameter DEVICE_TYPE = 0,
parameter DDR_OR_SDR_N = 1,
parameter SERDES_FACTOR = 8,
parameter DATA_WIDTH = 16) (
// reset and clocks
input rst,
input clk,
input div_clk,
input loaden,
// data interface
input [(DATA_WIDTH-1):0] data_s0,
input [(DATA_WIDTH-1):0] data_s1,
input [(DATA_WIDTH-1):0] data_s2,
input [(DATA_WIDTH-1):0] data_s3,
input [(DATA_WIDTH-1):0] data_s4,
input [(DATA_WIDTH-1):0] data_s5,
input [(DATA_WIDTH-1):0] data_s6,
input [(DATA_WIDTH-1):0] data_s7,
output [(DATA_WIDTH-1):0] data_out_p,
output [(DATA_WIDTH-1):0] data_out_n);
// local parameter
localparam ARRIA10 = 0;
localparam CYCLONE5 = 1;
// internal signals
wire [(DATA_WIDTH-1):0] data_samples_s[0:(SERDES_FACTOR-1)];
wire [(SERDES_FACTOR-1):0] data_in_s[0:(DATA_WIDTH-1)];
// defaults
assign data_out_n = 'd0;
// instantiations
genvar n;
genvar i;
generate
if (SERDES_FACTOR == 8) begin
assign data_samples_s[7] = data_s7;
assign data_samples_s[6] = data_s6;
assign data_samples_s[5] = data_s5;
assign data_samples_s[4] = data_s4;
end
endgenerate
assign data_samples_s[3] = data_s3;
assign data_samples_s[2] = data_s2;
assign data_samples_s[1] = data_s1;
assign data_samples_s[0] = data_s0;
generate
for (n = 0; n < DATA_WIDTH; n = n + 1) begin: g_swap
for (i = 0; i < SERDES_FACTOR; i = i + 1) begin: g_samples
assign data_in_s[n][((SERDES_FACTOR-1)-i)] = data_samples_s[i][n];
end
end
endgenerate
generate
for (n = 0; n < DATA_WIDTH; n = n + 1) begin: g_data
if (DEVICE_TYPE == CYCLONE5) begin
ad_serdes_out_core_c5 #(
.SERDES_FACTOR (SERDES_FACTOR))
i_core (
.clk (clk),
.div_clk (div_clk),
.enable (loaden),
.data_out (data_out_p[n]),
.data (data_in_s[n]));
end
if (DEVICE_TYPE == ARRIA10) begin
__ad_serdes_out_1__ i_core (
.clk_export (clk),
.div_clk_export (div_clk),
.loaden_export (loaden),
.data_out_export (data_out_p[n]),
.data_s_export (data_in_s[n]));
end
end
endgenerate
endmodule
// ***************************************************************************
// ***************************************************************************

107
library/altera/common/ad_serdes_out_core_c5.v Normal file
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@ -0,0 +1,107 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
`timescale 1ps/1ps
module ad_serdes_out_core_c5 #(
parameter SERDES_FACTOR = 8) (
input clk,
input div_clk,
input enable,
output data_out,
input [(SERDES_FACTOR-1):0] data);
reg [(SERDES_FACTOR-1):0] data_int = 'd0;
always @(posedge div_clk) begin
data_int <= data;
end
altlvds_tx i_altlvds_tx (
.tx_enable (enable),
.tx_in (data),
.tx_inclock (clk),
.tx_out (data_out),
.pll_areset (1'b0),
.sync_inclock (1'b0),
.tx_coreclock (),
.tx_data_reset (1'b0),
.tx_locked (),
.tx_outclock (),
.tx_pll_enable (1'b1),
.tx_syncclock (1'b0));
defparam
i_altlvds_tx.center_align_msb = "UNUSED",
i_altlvds_tx.common_rx_tx_pll = "OFF",
i_altlvds_tx.coreclock_divide_by = 1,
i_altlvds_tx.data_rate = "800.0 Mbps",
i_altlvds_tx.deserialization_factor = SERDES_FACTOR,
i_altlvds_tx.differential_drive = 0,
i_altlvds_tx.enable_clock_pin_mode = "UNUSED",
i_altlvds_tx.implement_in_les = "OFF",
i_altlvds_tx.inclock_boost = 0,
i_altlvds_tx.inclock_data_alignment = "EDGE_ALIGNED",
i_altlvds_tx.inclock_period = 50000,
i_altlvds_tx.inclock_phase_shift = 0,
i_altlvds_tx.intended_device_family = "Cyclone V",
i_altlvds_tx.lpm_hint = "CBX_MODULE_PREFIX=ad_serdes_out_core_c5",
i_altlvds_tx.lpm_type = "altlvds_tx",
i_altlvds_tx.multi_clock = "OFF",
i_altlvds_tx.number_of_channels = 1,
i_altlvds_tx.outclock_alignment = "EDGE_ALIGNED",
i_altlvds_tx.outclock_divide_by = 1,
i_altlvds_tx.outclock_duty_cycle = 50,
i_altlvds_tx.outclock_multiply_by = 1,
i_altlvds_tx.outclock_phase_shift = 0,
i_altlvds_tx.outclock_resource = "Dual-Regional clock",
i_altlvds_tx.output_data_rate = 800,
i_altlvds_tx.pll_compensation_mode = "AUTO",
i_altlvds_tx.pll_self_reset_on_loss_lock = "OFF",
i_altlvds_tx.preemphasis_setting = 0,
i_altlvds_tx.refclk_frequency = "20.000000 MHz",
i_altlvds_tx.registered_input = "OFF",
i_altlvds_tx.use_external_pll = "ON",
i_altlvds_tx.use_no_phase_shift = "ON",
i_altlvds_tx.vod_setting = 0,
i_altlvds_tx.clk_src_is_pll = "off";
endmodule
// ***************************************************************************
// ***************************************************************************

31
library/axi_ad6676/Makefile
View File

@ -5,23 +5,24 @@
####################################################################################
####################################################################################
M_DEPS := axi_ad6676_ip.tcl
M_DEPS += ../scripts/adi_env.tcl
M_DEPS += ../scripts/adi_ip.tcl
M_DEPS += ../common/ad_rst.v
M_DEPS += ../common/ad_axi_ip_constr.xdc
M_DEPS += ../common/ad_pnmon.v
M_DEPS += ../common/ad_rst.v
M_DEPS += ../common/ad_xcvr_rx_if.v
M_DEPS += ../common/up_adc_channel.v
M_DEPS += ../common/up_adc_common.v
M_DEPS += ../common/up_axi.v
M_DEPS += ../common/up_clock_mon.v
M_DEPS += ../common/up_xfer_cntrl.v
M_DEPS += ../common/up_xfer_status.v
M_DEPS += ../common/up_clock_mon.v
M_DEPS += ../common/up_adc_common.v
M_DEPS += ../common/up_adc_channel.v
M_DEPS += ../common/ad_axi_ip_constr.xdc
M_DEPS += axi_ad6676_pnmon.v
M_DEPS += axi_ad6676_channel.v
M_DEPS += axi_ad6676_if.v
M_DEPS += axi_ad6676_constr.xdc
M_DEPS += ../scripts/adi_env.tcl
M_DEPS += ../scripts/adi_ip.tcl
M_DEPS += axi_ad6676.v
M_DEPS += axi_ad6676_channel.v
M_DEPS += axi_ad6676_constr.xdc
M_DEPS += axi_ad6676_if.v
M_DEPS += axi_ad6676_ip.tcl
M_DEPS += axi_ad6676_pnmon.v
M_VIVADO := vivado -mode batch -source
@ -32,6 +33,10 @@ M_FLIST += *.log
M_FLIST += component.xml
M_FLIST += *.jou
M_FLIST += xgui
M_FLIST += *.ip_user_files
M_FLIST += *.srcs
M_FLIST += *.hw
M_FLIST += *.sim
M_FLIST += .Xil
@ -48,7 +53,7 @@ clean-all:
axi_ad6676.xpr: $(M_DEPS)
rm -rf $(M_FLIST)
-rm -rf $(M_FLIST)
$(M_VIVADO) axi_ad6676_ip.tcl >> axi_ad6676_ip.log 2>&1
####################################################################################

68
library/axi_ad6676/axi_ad6676.v
View File

@ -45,18 +45,21 @@ module axi_ad6676 (
// rx_clk is (line-rate/40)
rx_clk,
rx_sof,
rx_valid,
rx_ready,
rx_data,
// dma interface
adc_clk,
adc_rst,
adc_valid_a,
adc_enable_a,
adc_data_a,
adc_valid_b,
adc_enable_b,
adc_data_b,
adc_valid_0,
adc_enable_0,
adc_data_0,
adc_valid_1,
adc_enable_1,
adc_data_1,
adc_dovf,
adc_dunf,
@ -80,7 +83,9 @@ module axi_ad6676 (
s_axi_rvalid,
s_axi_rresp,
s_axi_rdata,
s_axi_rready);
s_axi_rready,
s_axi_awprot,
s_axi_arprot);
parameter ID = 0;
parameter DEVICE_TYPE = 0;
@ -90,18 +95,21 @@ module axi_ad6676 (
// rx_clk is (line-rate/40)
input rx_clk;
input [ 3:0] rx_sof;
input rx_valid;
output rx_ready;
input [63:0] rx_data;
// dma interface
output adc_clk;
output adc_rst;
output adc_valid_a;
output adc_enable_a;
output [31:0] adc_data_a;
output adc_valid_b;
output adc_enable_b;
output [31:0] adc_data_b;
output adc_valid_0;
output adc_enable_0;
output [31:0] adc_data_0;
output adc_valid_1;
output adc_enable_1;
output [31:0] adc_data_1;
input adc_dovf;
input adc_dunf;
@ -126,6 +134,9 @@ module axi_ad6676 (
output [ 1:0] s_axi_rresp;
output [31:0] s_axi_rdata;
input s_axi_rready;
input [ 2:0] s_axi_awprot;
input [ 2:0] s_axi_arprot;
// internal registers
@ -144,8 +155,8 @@ module axi_ad6676 (
// internal signals
wire [31:0] adc_data_a_s;
wire [31:0] adc_data_b_s;
wire [31:0] adc_data_0_s;
wire [31:0] adc_data_1_s;
wire adc_or_a_s;
wire adc_or_b_s;
wire adc_status_s;
@ -166,6 +177,8 @@ module axi_ad6676 (
assign up_clk = s_axi_aclk;
assign up_rstn = s_axi_aresetn;
assign rx_ready = 1'b1;
// processor read interface
always @(negedge up_rstn or posedge up_clk) begin
@ -188,18 +201,19 @@ module axi_ad6676 (
// adc valid
assign adc_valid_a = 1'b1;
assign adc_valid_b = 1'b1;
assign adc_valid_0 = 1'b1;
assign adc_valid_1 = 1'b1;
// main (device interface)
axi_ad6676_if i_if (
axi_ad6676_if #(.DEVICE_TYPE (DEVICE_TYPE)) i_if (
.rx_clk (rx_clk),
.rx_sof (rx_sof),
.rx_data (rx_data),
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_data_a (adc_data_a_s),
.adc_data_b (adc_data_b_s),
.adc_data_a (adc_data_0_s),
.adc_data_b (adc_data_1_s),
.adc_or_a (adc_or_a_s),
.adc_or_b (adc_or_b_s),
.adc_status (adc_status_s));
@ -209,10 +223,10 @@ module axi_ad6676 (
axi_ad6676_channel #(.Q_OR_I_N(0), .CHANNEL_ID(0)) i_channel_0 (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_data (adc_data_a_s),
.adc_data (adc_data_0_s),
.adc_or (adc_or_a_s),
.adc_dfmt_data (adc_data_a),
.adc_enable (adc_enable_a),
.adc_dfmt_data (adc_data_0),
.adc_enable (adc_enable_0),
.up_adc_pn_err (up_status_pn_err_s[0]),
.up_adc_pn_oos (up_status_pn_oos_s[0]),
.up_adc_or (up_status_or_s[0]),
@ -232,10 +246,10 @@ module axi_ad6676 (
axi_ad6676_channel #(.Q_OR_I_N(1), .CHANNEL_ID(1)) i_channel_1 (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_data (adc_data_b_s),
.adc_data (adc_data_1_s),
.adc_or (adc_or_b_s),
.adc_dfmt_data (adc_data_b),
.adc_enable (adc_enable_b),
.adc_dfmt_data (adc_data_1),
.adc_enable (adc_enable_1),
.up_adc_pn_err (up_status_pn_err_s[1]),
.up_adc_pn_oos (up_status_pn_oos_s[1]),
.up_adc_or (up_status_or_s[1]),
@ -273,7 +287,7 @@ module axi_ad6676 (
.up_drp_wr (),
.up_drp_addr (),
.up_drp_wdata (),
.up_drp_rdata (16'd0),
.up_drp_rdata (32'd0),
.up_drp_ready (1'd0),
.up_drp_locked (1'd1),
.up_usr_chanmax (),

2
library/axi_ad6676/axi_ad6676_channel.v
View File

@ -120,7 +120,7 @@ module axi_ad6676_channel (
assign adc_dfmt_data = adc_data;
up_adc_channel #(.ADC_CHANNEL_ID(CHANNEL_ID)) i_up_adc_channel (
up_adc_channel #(.CHANNEL_ID(CHANNEL_ID)) i_up_adc_channel (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_enable (adc_enable),

24
library/axi_ad6676/axi_ad6676_if.v
View File

@ -36,7 +36,6 @@
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// This is the LVDS/DDR interface
`timescale 1ns/100ps
@ -46,6 +45,7 @@ module axi_ad6676_if (
// rx_clk is (line-rate/40)
rx_clk,
rx_sof,
rx_data,
// adc data output
@ -58,10 +58,14 @@ module axi_ad6676_if (
adc_or_b,
adc_status);
// parameters
parameter DEVICE_TYPE = 0;
// jesd interface
// rx_clk is (line-rate/40)
input rx_clk;
input [ 3:0] rx_sof;
input [63:0] rx_data;
// adc data output
@ -84,6 +88,7 @@ module axi_ad6676_if (
wire [15:0] adc_data_a_s0_s;
wire [15:0] adc_data_b_s1_s;
wire [15:0] adc_data_b_s0_s;
wire [63:0] rx_data_s;
// adc clock is the reference clock
@ -113,6 +118,21 @@ module axi_ad6676_if (
end
end
// frame-alignment
genvar n;
generate
for (n = 0; n < 2; n = n + 1) begin: g_xcvr_if
ad_xcvr_rx_if #(.DEVICE_TYPE (DEVICE_TYPE)) i_xcvr_if (
.rx_clk (rx_clk),
.rx_ip_sof (rx_sof),
.rx_ip_data (rx_data[((n*32)+31):(n*32)]),
.rx_sof (),
.rx_data (rx_data_s[((n*32)+31):(n*32)]));
end
endgenerate
endmodule
// ***************************************************************************

2
library/axi_ad6676/axi_ad6676_ip.tcl
View File

@ -13,6 +13,7 @@ adi_ip_files axi_ad6676 [list \
"$ad_hdl_dir/library/common/up_clock_mon.v" \
"$ad_hdl_dir/library/common/up_adc_common.v" \
"$ad_hdl_dir/library/common/up_adc_channel.v" \
"$ad_hdl_dir/library/common/ad_xcvr_rx_if.v" \
"$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc" \
"axi_ad6676_pnmon.v" \
"axi_ad6676_channel.v" \
@ -25,6 +26,7 @@ adi_ip_constraints axi_ad6676 [list \
"$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc" \
"axi_ad6676_constr.xdc" ]
set_property driver_value 0 [ipx::get_ports *rx_valid* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]]

61
library/axi_ad7616/Makefile Normal file
View File

@ -0,0 +1,61 @@
####################################################################################
####################################################################################
## Copyright 2011(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################
####################################################################################
M_DEPS += ../common/ad_edge_detect.v
M_DEPS += ../common/up_axi.v
M_DEPS += ../scripts/adi_env.tcl
M_DEPS += ../scripts/adi_ip.tcl
M_DEPS += axi_ad7616.v
M_DEPS += axi_ad7616_control.v
M_DEPS += axi_ad7616_ip.tcl
M_DEPS += axi_ad7616_maxis2wrfifo.v
M_DEPS += axi_ad7616_pif.v
M_DEPS += ../spi_engine/axi_spi_engine/axi_spi_engine.xpr
M_DEPS += ../spi_engine/spi_engine_execution/spi_engine_execution.xpr
M_DEPS += ../spi_engine/spi_engine_interconnect/spi_engine_interconnect.xpr
M_DEPS += ../spi_engine/spi_engine_offload/spi_engine_offload.xpr
M_VIVADO := vivado -mode batch -source
M_FLIST := *.cache
M_FLIST += *.data
M_FLIST += *.xpr
M_FLIST += *.log
M_FLIST += component.xml
M_FLIST += *.jou
M_FLIST += xgui
M_FLIST += *.ip_user_files
M_FLIST += *.srcs
M_FLIST += *.hw
M_FLIST += *.sim
M_FLIST += .Xil
.PHONY: all dep clean clean-all
all: dep axi_ad7616.xpr
clean:clean-all
clean-all:
rm -rf $(M_FLIST)
axi_ad7616.xpr: $(M_DEPS)
-rm -rf $(M_FLIST)
$(M_VIVADO) axi_ad7616_ip.tcl >> axi_ad7616_ip.log 2>&1
dep:
make -C ../spi_engine/axi_spi_engine/
make -C ../spi_engine/spi_engine_execution/
make -C ../spi_engine/spi_engine_interconnect/
make -C ../spi_engine/spi_engine_offload/
####################################################################################
####################################################################################

521
library/axi_ad7616/axi_ad7616.v Normal file
View File

@ -0,0 +1,521 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2013(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_ad7616 (
// physical data interface
rx_sclk,
rx_cs_n,
rx_sdo,
rx_sdi_0,
rx_sdi_1,
rx_db_o,
rx_db_i,
rx_db_t,
rx_rd_n,
rx_wr_n,
// physical control interface
rx_cnvst,
rx_busy,
// AXI Slave Memory Map
s_axi_aclk,
s_axi_aresetn,
s_axi_awvalid,
s_axi_awaddr,
s_axi_awprot,
s_axi_awready,
s_axi_wvalid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wready,
s_axi_bvalid,
s_axi_bresp,
s_axi_bready,
s_axi_arvalid,
s_axi_araddr,
s_axi_arprot,
s_axi_arready,
s_axi_rvalid,
s_axi_rresp,
s_axi_rdata,
s_axi_rready,
// Write FIFO interface
adc_valid,
adc_data,
adc_sync,
irq
);
// parameters
parameter ID = 0;
parameter IF_TYPE = 1;
// local parameters
localparam NUM_OF_SDI = 2;
localparam SERIAL = 0;
localparam PARALLEL = 1;
localparam NEG_EDGE = 1;
localparam UP_ADDRESS_WIDTH = 14;
// IO definitions
output rx_sclk;
output rx_cs_n;
output rx_sdo;
input rx_sdi_0;
input rx_sdi_1;
output [15:0] rx_db_o;
input [15:0] rx_db_i;
output rx_db_t;
output rx_rd_n;
output rx_wr_n;
output rx_cnvst;
input rx_busy;
input s_axi_aclk;
input s_axi_aresetn;
input s_axi_awvalid;
input [31:0] s_axi_awaddr;
output s_axi_awready;
input s_axi_wvalid;
input [31:0] s_axi_wdata;
input [ 3:0] s_axi_wstrb;
output s_axi_wready;
output s_axi_bvalid;
output [ 1:0] s_axi_bresp;
input s_axi_bready;
input s_axi_arvalid;
input [31:0] s_axi_araddr;
output s_axi_arready;
output s_axi_rvalid;
output [ 1:0] s_axi_rresp;
output [31:0] s_axi_rdata;
input s_axi_rready;
input [ 2:0] s_axi_awprot;
input [ 2:0] s_axi_arprot;
output adc_valid;
output [15:0] adc_data;
output adc_sync;
output irq;
// internal registers
reg up_wack = 1'b0;
reg up_rack = 1'b0;
reg [31:0] up_rdata = 32'b0;
// internal signals
wire up_clk;
wire up_rstn;
wire up_rst;
wire up_rreq_s;
wire [(UP_ADDRESS_WIDTH-1):0] up_raddr_s;
wire up_wreq_s;
wire [(UP_ADDRESS_WIDTH-1):0] up_waddr_s;
wire [31:0] up_wdata_s;
wire up_wack_if_s;
wire up_rack_if_s;
wire [31:0] up_rdata_if_s;
wire up_wack_cntrl_s;
wire up_rack_cntrl_s;
wire [31:0] up_rdata_cntrl_s;
wire trigger_s;
wire rd_req_s;
wire wr_req_s;
wire [15:0] wr_data_s;
wire [15:0] rd_data_s;
wire rd_valid_s;
wire [ 4:0] burst_length_s;
wire m_axis_ready_s;
wire m_axis_valid_s;
wire [15:0] m_axis_data_s;
wire m_axis_xfer_req_s;
// defaults
assign up_clk = s_axi_aclk;
assign up_rstn = s_axi_aresetn;
assign up_rst = ~s_axi_aresetn;
// processor read interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_wack <= 'd0;
up_rack <= 'd0;
up_rdata <= 'd0;
end else begin
up_wack <= up_wack_if_s | up_wack_cntrl_s;
up_rack <= up_rack_if_s | up_rack_cntrl_s;
up_rdata <= up_rdata_if_s | up_rdata_cntrl_s;
end
end
generate if (IF_TYPE == SERIAL) begin
// ground all parallel interface signals
assign rx_db_o = 16'b0;
assign rx_rd_n = 1'b0;
assign rx_wr_n = 1'b0;
// SPI Framework instances and logic
wire spi_resetn_s;
wire s0_cmd_ready_s;
wire s0_cmd_valid_s;
wire [15:0] s0_cmd_data_s;
wire s0_sdo_data_ready_s;
wire s0_sdo_data_valid_s;
wire [ 7:0] s0_sdo_data_s;
wire s0_sdi_data_ready_s;
wire s0_sdi_data_valid_s;
wire [15:0] s0_sdi_data_s;
wire s0_sync_ready_s;
wire s0_sync_valid_s;
wire [ 7:0] s0_sync_s;
wire s1_cmd_ready_s;
wire s1_cmd_valid_s;
wire [15:0] s1_cmd_data_s;
wire s1_sdo_data_ready_s;
wire s1_sdo_data_valid_s;
wire [ 7:0] s1_sdo_data_s;
wire s1_sdi_data_ready_s;
wire s1_sdi_data_valid_s;
wire [15:0] s1_sdi_data_s;
wire s1_sync_ready_s;
wire s1_sync_valid_s;
wire [ 7:0] s1_sync_s;
wire m_cmd_ready_s;
wire m_cmd_valid_s;
wire [15:0] m_cmd_data_s;
wire m_sdo_data_ready_s;
wire m_sdo_data_valid_s;
wire [7:0] m_sdo_data_s;
wire m_sdi_data_ready_s;
wire m_sdi_data_valid_s;
wire [15:0] m_sdi_data_s;
wire m_sync_ready_s;
wire m_sync_valid_s;
wire [ 7:0] m_sync_s;
wire offload0_cmd_wr_en_s;
wire [15:0] offload0_cmd_wr_data_s;
wire offload0_sdo_wr_en_s;
wire [ 7:0] offload0_sdo_wr_data_s;
wire offload0_mem_reset_s;
wire offload0_enable_s;
wire offload0_enabled_s;
axi_spi_engine #(
.DATA_WIDTH (8),
.NUM_OF_SDI (NUM_OF_SDI),
.NUM_OFFLOAD(1),
.MM_IF_TYPE(1),
.UP_ADDRESS_WIDTH (UP_ADDRESS_WIDTH)
) i_axi_spi_engine (
.up_clk (up_clk),
.up_rstn (up_rstn),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_if_s),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_if_s),
.up_rack (up_rack_if_s),
.irq (irq),
.spi_clk (up_clk),
.spi_resetn (spi_resetn_s),
.cmd_ready (s0_cmd_ready_s),
.cmd_valid (s0_cmd_valid_s),
.cmd_data (s0_cmd_data_s),
.sdo_data_ready (s0_sdo_data_ready_s),
.sdo_data_valid (s0_sdo_data_valid_s),
.sdo_data (s0_sdo_data_s),
.sdi_data_ready (s0_sdi_data_ready_s),
.sdi_data_valid (s0_sdi_data_valid_s),
.sdi_data (s0_sdi_data_s),
.sync_ready (s0_sync_ready_s),
.sync_valid (s0_sync_valid_s),
.sync_data (s0_sync_s),
.offload0_cmd_wr_en (offload0_cmd_wr_en_s),
.offload0_cmd_wr_data (offload0_cmd_wr_data_s),
.offload0_sdo_wr_en (offload0_sdo_wr_en_s),
.offload0_sdo_wr_data (offload0_sdo_wr_data_s),
.offload0_mem_reset (offload0_mem_reset_s),
.offload0_enable (offload0_enable_s),
.offload0_enabled(offload0_enabled_s));
spi_engine_offload #(
.DATA_WIDTH (8),
.NUM_OF_SDI (NUM_OF_SDI)
) i_spi_engine_offload (
.ctrl_clk (up_clk),
.ctrl_cmd_wr_en (offload0_cmd_wr_en_s),
.ctrl_cmd_wr_data (offload0_cmd_wr_data_s),
.ctrl_sdo_wr_en (offload0_sdo_wr_en_s),
.ctrl_sdo_wr_data (offload0_sdo_wr_data_s),
.ctrl_enable (offload0_enable_s),
.ctrl_enabled (offload0_enabled_s),
.ctrl_mem_reset (offload0_mem_reset_s),
.spi_clk (up_clk),
.spi_resetn (spi_resetn_s),
.trigger (trigger_s),
.cmd_valid (s1_cmd_valid_s),
.cmd_ready (s1_cmd_ready_s),
.cmd (s1_cmd_data_s),
.sdo_data_valid (s1_sdo_data_valid_s),
.sdo_data_ready (s1_sdo_data_ready_s),
.sdo_data (s1_sdo_data_s),
.sdi_data_valid (s1_sdi_data_valid_s),
.sdi_data_ready (s1_sdi_data_ready_s),
.sdi_data (s1_sdi_data_s),
.sync_valid (s1_sync_valid_s),
.sync_ready (s1_sync_ready_s),
.sync_data (s1_sync_s),
.offload_sdi_valid (m_axis_valid_s),
.offload_sdi_ready (m_axis_ready_s),
.offload_sdi_data (m_axis_data_s));
spi_engine_interconnect #(
.DATA_WIDTH (8),
.NUM_OF_SDI (NUM_OF_SDI)
) i_spi_engine_interconnect (
.clk (up_clk),
.resetn (spi_resetn_s),
.m_cmd_valid (m_cmd_valid_s),
.m_cmd_ready (m_cmd_ready_s),
.m_cmd_data (m_cmd_data_s),
.m_sdo_valid (m_sdo_data_valid_s),
.m_sdo_ready (m_sdo_data_ready_s),
.m_sdo_data (m_sdo_data_s),
.m_sdi_valid (m_sdi_data_valid_s),
.m_sdi_ready (m_sdi_data_ready_s),
.m_sdi_data (m_sdi_data_s),
.m_sync_valid (m_sync_valid_s),
.m_sync_ready (m_sync_ready_s),
.m_sync (m_sync_s),
.s0_cmd_valid (s0_cmd_valid_s),
.s0_cmd_ready (s0_cmd_ready_s),
.s0_cmd_data (s0_cmd_data_s),
.s0_sdo_valid (s0_sdo_data_valid_s),
.s0_sdo_ready (s0_sdo_data_ready_s),
.s0_sdo_data (s0_sdo_data_s),
.s0_sdi_valid (s0_sdi_data_valid_s),
.s0_sdi_ready (s0_sdi_data_ready_s),
.s0_sdi_data (s0_sdi_data_s),
.s0_sync_valid (s0_sync_valid_s),
.s0_sync_ready (s0_sync_ready_s),
.s0_sync (s0_sync_s),
.s1_cmd_valid (s1_cmd_valid_s),
.s1_cmd_ready (s1_cmd_ready_s),
.s1_cmd_data (s1_cmd_data_s),
.s1_sdo_valid (s1_sdo_data_valid_s),
.s1_sdo_ready (s1_sdo_data_ready_s),
.s1_sdo_data (s1_sdo_data_s),
.s1_sdi_valid (s1_sdi_data_valid_s),
.s1_sdi_ready (s1_sdi_data_ready_s),
.s1_sdi_data (s1_sdi_data_s),
.s1_sync_valid (s1_sync_valid_s),
.s1_sync_ready (s1_sync_ready_s),
.s1_sync (s1_sync_s));
spi_engine_execution #(
.DATA_WIDTH (8),
.NUM_OF_SDI (NUM_OF_SDI)
) i_spi_engine_execution (
.clk (up_clk),
.resetn (spi_resetn_s),
.active (),
.cmd_ready (m_cmd_ready_s),
.cmd_valid (m_cmd_valid_s),
.cmd (m_cmd_data_s),
.sdo_data_valid (m_sdo_data_valid_s),
.sdo_data_ready (m_sdo_data_ready_s),
.sdo_data (m_sdo_data_s),
.sdi_data_ready (m_sdi_data_ready_s),
.sdi_data_valid (m_sdi_data_valid_s),
.sdi_data (m_sdi_data_s),
.sync_ready (m_sync_ready_s),
.sync_valid (m_sync_valid_s),
.sync (m_sync_s),
.sclk (rx_sclk),
.sdo (rx_sdo),
.sdo_t (),
.sdi (rx_sdi_0),
.sdi_1 (rx_sdi_1),
.sdi_2 (1'b0),
.sdi_3 (1'b0),
.cs (rx_cs_n),
.three_wire ());
axi_ad7616_maxis2wrfifo #(
.DATA_WIDTH(16)
) i_maxis2wrfifo (
.clk(up_clk),
.rstn(up_rstn),
.sync_in(trigger_s),
.m_axis_data(m_axis_data_s),
.m_axis_ready(m_axis_ready_s),
.m_axis_valid(m_axis_valid_s),
.fifo_wr_en(adc_valid),
.fifo_wr_data(adc_data),
.fifo_wr_sync(adc_sync)
);
end
endgenerate
generate if (IF_TYPE == PARALLEL) begin
assign rx_sclk = 1'h0;
assign rx_sdo = 1'h0;
assign irq = 1'h0;
assign up_wack_if_s = 1'h0;
assign up_rack_if_s = 1'h0;
assign up_rdata_if_s = 1'h0;
axi_ad7616_pif i_ad7616_parallel_interface (
.cs_n (rx_cs_n),
.db_o (rx_db_o),
.db_i (rx_db_i),
.db_t (rx_db_t),
.rd_n (rx_rd_n),
.wr_n (rx_wr_n),
.adc_data (adc_data),
.adc_valid (adc_valid),
.adc_sync (adc_sync),
.end_of_conv (trigger_s),
.burst_length(burst_length_s),
.clk (up_clk),
.rstn (up_rstn),
.rd_req (rd_req_s),
.wr_req (wr_req_s),
.wr_data (wr_data_s),
.rd_data (rd_data_s),
.rd_valid (rd_valid_s)
);
end
endgenerate
axi_ad7616_control #(
.ID(ID),
.IF_TYPE(IF_TYPE)
) i_ad7616_control (
.cnvst (rx_cnvst),
.busy (rx_busy),
.up_burst_length (burst_length_s),
.up_read_data (rd_data_s),
.up_read_valid (rd_valid_s),
.up_write_data (wr_data_s),
.up_read_req (rd_req_s),
.up_write_req (wr_req_s),
.end_of_conv (trigger_s),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_cntrl_s),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_cntrl_s),
.up_rack (up_rack_cntrl_s));
// up bus interface
up_axi #(
.ADDRESS_WIDTH (UP_ADDRESS_WIDTH)
) i_up_axi (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_axi_awvalid (s_axi_awvalid),
.up_axi_awaddr (s_axi_awaddr),
.up_axi_awready (s_axi_awready),
.up_axi_wvalid (s_axi_wvalid),
.up_axi_wdata (s_axi_wdata),
.up_axi_wstrb (s_axi_wstrb),
.up_axi_wready (s_axi_wready),
.up_axi_bvalid (s_axi_bvalid),
.up_axi_bresp (s_axi_bresp),
.up_axi_bready (s_axi_bready),
.up_axi_arvalid (s_axi_arvalid),
.up_axi_araddr (s_axi_araddr),
.up_axi_arready (s_axi_arready),
.up_axi_rvalid (s_axi_rvalid),
.up_axi_rresp (s_axi_rresp),
.up_axi_rdata (s_axi_rdata),
.up_axi_rready (s_axi_rready),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata),
.up_rack (up_rack));
endmodule
// ***************************************************************************
// ***************************************************************************

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// ***************************************************************************
// ***************************************************************************
// Copyright 2015(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_ad7616_control (
// control signals
cnvst,
busy,
up_read_data,
up_read_valid,
up_write_data,
up_read_req,
up_write_req,
up_burst_length,
end_of_conv,
// bus interface
up_rstn,
up_clk,
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_rack
);
parameter ID = 0;
parameter IF_TYPE = 0;
localparam PCORE_VERSION = 'h0001001;
localparam POS_EDGE = 0;
localparam NEG_EDGE = 1;
localparam SERIAL = 0;
localparam PARALLEL = 1;
output cnvst;
input busy;
output end_of_conv;
output [ 4:0] up_burst_length;
input [15:0] up_read_data;
input up_read_valid;
output [15:0] up_write_data;
output up_read_req;
output up_write_req;
// bus interface
input up_rstn;
input up_clk;
input up_wreq;
input [13:0] up_waddr;
input [31:0] up_wdata;
output up_wack;
input up_rreq;
input [13:0] up_raddr;
output [31:0] up_rdata;
output up_rack;
// internal signals
reg [31:0] up_scratch = 32'b0;
reg up_resetn = 1'b0;
reg up_cnvst_en = 1'b0;
reg up_wack = 1'b0;
reg up_rack = 1'b0;
reg [31:0] up_rdata = 32'b0;
reg [31:0] up_conv_rate = 32'b0;
reg [ 4:0] up_burst_length = 5'h0;
reg [15:0] up_write_data = 16'h0;
reg [31:0] cnvst_counter = 32'b0;
reg [ 3:0] pulse_counter = 8'b0;
reg cnvst_buf = 1'b0;
reg cnvst_pulse = 1'b0;
reg [ 2:0] chsel_ff = 3'b0;
wire up_rst;
wire up_rreq_s;
wire up_rack_s;
wire up_wreq_s;
wire [31:0] up_read_data_s;
wire up_read_valid_s;
// decode block select
assign up_wreq_s = (up_waddr[13:8] == 6'h01) ? up_wreq : 1'b0;
assign up_rreq_s = (up_raddr[13:8] == 6'h01) ? up_rreq : 1'b0;
// the up_[read/write]_data interfaces are valid just in parallel mode
assign up_read_valid_s = (IF_TYPE == PARALLEL) ? up_read_valid : 1'b1;
assign up_read_data_s = (IF_TYPE == PARALLEL) ? {16'h0, up_read_data} : {2{16'hDEAD}};
// processor write interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_wack <= 1'h0;
up_scratch <= 32'b0;
up_resetn <= 1'b0;
up_cnvst_en <= 1'b0;
up_conv_rate <= 32'b0;
up_burst_length <= 5'h0;
up_write_data <= 16'h0;
end else begin
up_wack <= up_wreq_s;
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h02)) begin
up_scratch <= up_wdata;
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h10)) begin
up_resetn <= up_wdata[0];
up_cnvst_en <= up_wdata[1];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h11)) begin
up_conv_rate <= up_wdata;
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h12)) begin
up_burst_length <= up_wdata;
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h14)) begin
up_write_data <= up_wdata;
end
end
end
assign up_write_req = (up_waddr[7:0] == 8'h14) ? up_wreq_s : 1'h0;
// processor read interface
assign up_rack_s = (up_raddr[7:0] == 8'h13) ? up_read_valid_s : up_rreq_s;
assign up_read_req = (up_raddr[7:0] == 8'h13) ? up_rreq_s : 1'b0;
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_rack <= 1'b0;
up_rdata <= 32'b0;
end else begin
up_rack <= up_rack_s;
if (up_rack_s == 1'b1) begin
case (up_raddr[7:0])
8'h00 : up_rdata = PCORE_VERSION;
8'h01 : up_rdata = ID;
8'h02 : up_rdata = up_scratch;
8'h03 : up_rdata = IF_TYPE;
8'h10 : up_rdata = {29'b0, up_cnvst_en, up_resetn};
8'h11 : up_rdata = up_conv_rate;
8'h12 : up_rdata = {27'b0, up_burst_length};
8'h13 : up_rdata = up_read_data_s;
endcase
end
end
end
// instantiations
assign up_rst = ~up_rstn;
ad_edge_detect #(
.EDGE(NEG_EDGE)
) i_ad_edge_detect (
.clk (up_clk),
.rst (up_rst),
.in (busy),
.out (end_of_conv)
);
// convertion start generator
// NOTE: + The minimum convertion cycle is 1 us
// + The rate of the cnvst must be defined in a way,
// to not lose any data. cnvst_rate >= t_conversion + t_aquisition
// See the AD7616 datasheet for more information.
always @(posedge up_clk) begin
if(up_resetn == 1'b0) begin
cnvst_counter <= 32'b0;
end else begin
cnvst_counter <= (cnvst_counter < up_conv_rate) ? cnvst_counter + 1 : 32'b0;
end
end
always @(cnvst_counter, up_conv_rate) begin
cnvst_pulse <= (cnvst_counter == up_conv_rate) ? 1'b1 : 1'b0;
end
always @(posedge up_clk) begin
if(up_resetn == 1'b0) begin
pulse_counter <= 3'b0;
cnvst_buf <= 1'b0;
end else begin
pulse_counter <= (cnvst == 1'b1) ? pulse_counter + 1 : 3'b0;
if(cnvst_pulse == 1'b1) begin
cnvst_buf <= 1'b1;
end else if (pulse_counter[2] == 1'b1) begin
cnvst_buf <= 1'b0;
end
end
end
assign cnvst = (up_cnvst_en == 1'b1) ? cnvst_buf : 1'b0;
endmodule

27
library/axi_ad7616/axi_ad7616_ip.tcl Normal file
View File

@ -0,0 +1,27 @@
# ip
source ../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip.tcl
adi_ip_create axi_ad7616
adi_ip_files axi_ad7616 [list \
"$ad_hdl_dir/library/common/ad_edge_detect.v" \
"$ad_hdl_dir/library/common/up_axi.v" \
"axi_ad7616_control.v" \
"axi_ad7616_pif.v" \
"axi_ad7616_maxis2wrfifo.v" \
"axi_ad7616.v" ]
adi_ip_properties axi_ad7616
adi_ip_add_core_dependencies { \
analog.com:user:spi_engine_execution:1.0 \
analog.com:user:axi_spi_engine:1.0 \
analog.com:user:spi_engine_offload:1.0 \
analog.com:user:spi_engine_interconnect:1.0 \
}
set_property DRIVER_VALUE "0" [ipx::get_ports rx_db_i]
ipx::save_core [ipx::current_core]

107
library/common/altera/ad_mul_u16_alt.v → library/axi_ad7616/axi_ad7616_maxis2wrfifo.v
View File

@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014(c) Analog Devices, Inc.
// Copyright 2013(c) Analog Devices, Inc.
//
// All rights reserved.
//
@ -36,77 +36,72 @@
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// both inputs are considered unsigned 16 bits-
// ddata is delay matched generic data
`timescale 1ps/1ps
`timescale 1ns/100ps
module ad_mul_u16 (
// data_p = data_a * data_b;
module axi_ad7616_maxis2wrfifo (
clk,
data_a,
data_b,
data_p,
rstn,
sync_in,
// delay interface
// m_axis interface
ddata_in,
ddata_out);
m_axis_data,
m_axis_ready,
m_axis_valid,
m_axis_xfer_req,
// delayed data bus width
// write fifo interface
parameter DELAY_DATA_WIDTH = 16;
localparam DW = DELAY_DATA_WIDTH - 1;
fifo_wr_en,
fifo_wr_data,
fifo_wr_sync,
fifo_wr_xfer_req
// data_p = data_a * data_b;
);
parameter DATA_WIDTH = 16;
input clk;
input [15:0] data_a;
input [15:0] data_b;
output [31:0] data_p;
input rstn;
input sync_in;
// delay interface
input [DATA_WIDTH-1:0] m_axis_data;
output m_axis_ready;
input m_axis_valid;
output m_axis_xfer_req;
input [DW:0] ddata_in;
output [DW:0] ddata_out;
output fifo_wr_en;
output [DATA_WIDTH-1:0] fifo_wr_data;
output fifo_wr_sync;
input fifo_wr_xfer_req;
// internal registers
reg [DW:0] p1_ddata = 'd0;
reg [DW:0] p2_ddata = 'd0;
reg [DW:0] ddata_out = 'd0;
// internal signals
// a/b reg, m-reg, p-reg delay match
reg m_axis_ready = 1'b0;
reg m_axis_xfer_req = 1'b0;
reg fifo_wr_en = 1'b0;
reg [DATA_WIDTH-1:0] fifo_wr_data = 'b0;
reg fifo_wr_sync = 1'b0;
always @(posedge clk) begin
p1_ddata <= ddata_in;
p2_ddata <= p1_ddata;
ddata_out <= p2_ddata;
if (rstn == 1'b0) begin
m_axis_ready <= 1'b0;
m_axis_xfer_req <= 1'b0;
fifo_wr_data <= 'b0;
fifo_wr_en <= 1'b0;
fifo_wr_sync <= 1'b0;
end else begin
m_axis_ready <= 1'b1;
m_axis_xfer_req <= fifo_wr_xfer_req;
fifo_wr_data <= m_axis_data;
fifo_wr_en <= m_axis_valid;
if (sync_in == 1'b1) begin
fifo_wr_sync <= 1'b1;
end else if ((m_axis_valid == 1'b1) &&
(fifo_wr_sync == 1'b1)) begin
fifo_wr_sync <= 1'b0;
end
end
end
lpm_mult i_mult_macro (
.clock (clk),
.dataa (data_a),
.datab (data_b),
.result (data_p),
.aclr (1'b0),
.clken (1'b1),
.sum (1'b0));
defparam
lpm_mult_component.lpm_hint = "MAXIMIZE_SPEED=5",
lpm_mult_component.lpm_pipeline = 3,
lpm_mult_component.lpm_representation = "UNSIGNED",
lpm_mult_component.lpm_type = "LPM_MULT",
lpm_mult_component.lpm_widtha = 16,
lpm_mult_component.lpm_widthb = 16,
lpm_mult_component.lpm_widthp = 32;
endmodule
// ***************************************************************************
// ***************************************************************************

246
library/axi_ad7616/axi_ad7616_pif.v Normal file
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@ -0,0 +1,246 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2015(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_ad7616_pif (
// physical interface
cs_n,
db_o,
db_i,
db_t,
rd_n,
wr_n,
// FIFO interface
adc_data,
adc_valid,
adc_sync,
// end of convertion
end_of_conv,
burst_length,
// register access
clk,
rstn,
rd_req,
wr_req,
wr_data,
rd_data,
rd_valid
);
parameter UP_ADDRESS_WIDTH = 14;
// IO definitions
output cs_n;
output [15:0] db_o;
input [15:0] db_i;
output db_t;
output rd_n;
output wr_n;
input end_of_conv;
input [ 4:0] burst_length;
input clk;
input rstn;
input rd_req;
input wr_req;
input [15:0] wr_data;
output [15:0] rd_data;
output rd_valid;
output [15:0] adc_data;
output adc_valid;
output adc_sync;
// state registers
localparam [ 2:0] IDLE = 3'h0,
CS_LOW = 3'h1,
CNTRL0_LOW = 3'h2,
CNTRL0_HIGH = 3'h3,
CNTRL1_LOW = 3'h4,
CNTRL1_HIGH = 3'h5,
CS_HIGH = 3'h6;
// internal registers
reg [ 2:0] transfer_state = 3'h0;
reg [ 2:0] transfer_state_next = 3'h0;
reg [ 1:0] width_counter = 2'h0;
reg [ 4:0] burst_counter = 5'h0;
reg wr_req_d = 1'h0;
reg rd_req_d = 1'h0;
reg rd_conv_d = 1'h0;
reg xfer_req_d = 1'h0;
reg adc_sync = 1'h0;
reg rd_valid = 1'h0;
reg rd_valid_d = 1'h0;
reg [15:0] rd_data = 16'h0;
// internal wires
wire start_transfer_s;
wire rd_valid_s;
// FSM state register
always @(posedge clk) begin
if (rstn == 1'b0) begin
transfer_state <= 3'h0;
end else begin
transfer_state <= transfer_state_next;
end
end
// counters to control the RD_N and WR_N lines
assign start_transfer_s = end_of_conv | rd_req | wr_req;
always @(posedge clk) begin
if (rstn == 1'b0) begin
width_counter <= 2'h0;
end else begin
if((transfer_state == CNTRL0_LOW) || (transfer_state == CNTRL0_HIGH) ||
(transfer_state == CNTRL1_LOW) || (transfer_state == CNTRL1_HIGH))
width_counter <= width_counter + 1;
else
width_counter <= 2'h0;
end
end
always @(posedge clk) begin
if (rstn == 1'b0) begin
burst_counter <= 2'h0;
end else begin
if (transfer_state == CS_HIGH)
burst_counter <= burst_counter + 1;
else if (transfer_state == IDLE)
burst_counter <= 5'h0;
end
end
always @(negedge clk) begin
if (transfer_state == IDLE) begin
wr_req_d <= wr_req;
rd_req_d <= rd_req;
rd_conv_d <= end_of_conv;
end
end
// FSM next state logic
always @(*) begin
case (transfer_state)
IDLE : begin
transfer_state_next <= (start_transfer_s == 1'b1) ? CS_LOW : IDLE;
end
CS_LOW : begin
transfer_state_next <= CNTRL0_LOW;
end
CNTRL0_LOW : begin
transfer_state_next <= (width_counter != 2'b11) ? CNTRL0_LOW : CNTRL0_HIGH;
end
CNTRL0_HIGH : begin
transfer_state_next <= (width_counter != 2'b11) ? CNTRL0_HIGH :
((wr_req_d == 1'b1) || (rd_req_d == 1'b1)) ? CS_HIGH : CNTRL1_LOW;
end
CNTRL1_LOW : begin
transfer_state_next <= (width_counter != 2'b11) ? CNTRL1_LOW : CNTRL1_HIGH;
end
CNTRL1_HIGH : begin
transfer_state_next <= (width_counter != 2'b11) ? CNTRL1_HIGH : CS_HIGH;
end
CS_HIGH : begin
transfer_state_next <= (burst_length == burst_counter) ? IDLE : CNTRL0_LOW;
end
default : begin
transfer_state_next <= IDLE;
end
endcase
end
// data valid for the register access and m_axis interface
assign rd_valid_s = (((transfer_state == CNTRL0_HIGH) || (transfer_state == CNTRL1_HIGH)) &&
((rd_req_d == 1'b1) || (rd_conv_d == 1'b1))) ? 1'b1 : 1'b0;
// FSM output logic
assign db_o = wr_data;
always @(posedge clk) begin
rd_data <= (rd_valid_s & ~rd_valid_d) ? db_i : rd_data;
rd_valid_d <= rd_valid_s;
rd_valid <= rd_valid_s & ~rd_valid_d;
end
assign adc_valid = rd_valid;
assign adc_data = rd_data;
assign cs_n = (transfer_state == IDLE) ? 1'b1 : 1'b0;
assign db_t = ~wr_req_d;
assign rd_n = (((transfer_state == CNTRL0_LOW) && ((rd_conv_d == 1'b1) || rd_req_d == 1'b1)) ||
(transfer_state == CNTRL1_LOW)) ? 1'b0 : 1'b1;
assign wr_n = ((transfer_state == CNTRL0_LOW) && (wr_req_d == 1'b1)) ? 1'b0 : 1'b1;
// sync will be asserted at the first valid data right after the convertion start
always @(posedge clk) begin
if (end_of_conv == 1'b1) begin
adc_sync <= 1'b1;
end else if (rd_valid == 1'b1) begin
adc_sync <= 1'b0;
end
end
endmodule

36
library/axi_ad9122/Makefile
View File

@ -5,29 +5,29 @@
####################################################################################
####################################################################################
M_DEPS := axi_ad9122_ip.tcl
M_DEPS += ../scripts/adi_env.tcl
M_DEPS += ../scripts/adi_ip.tcl
M_DEPS += ../common/ad_mul.v
M_DEPS += ../common/ad_dds_sine.v
M_DEPS += ../common/ad_dds_1.v
M_DEPS += ../common/ad_axi_ip_constr.xdc
M_DEPS += ../common/ad_dds.v
M_DEPS += ../common/ad_dds_1.v
M_DEPS += ../common/ad_dds_sine.v
M_DEPS += ../common/ad_rst.v
M_DEPS += ../common/ad_mmcm_drp.v
M_DEPS += ../common/ad_serdes_out.v
M_DEPS += ../common/ad_serdes_clk.v
M_DEPS += ../common/up_axi.v
M_DEPS += ../common/up_clock_mon.v
M_DEPS += ../common/up_dac_channel.v
M_DEPS += ../common/up_dac_common.v
M_DEPS += ../common/up_xfer_cntrl.v
M_DEPS += ../common/up_xfer_status.v
M_DEPS += ../common/up_clock_mon.v
M_DEPS += ../common/up_dac_common.v
M_DEPS += ../common/up_dac_channel.v
M_DEPS += ../common/ad_axi_ip_constr.xdc
M_DEPS += ../scripts/adi_env.tcl
M_DEPS += ../scripts/adi_ip.tcl
M_DEPS += ../xilinx/common/ad_mmcm_drp.v
M_DEPS += ../xilinx/common/ad_mul.v
M_DEPS += ../xilinx/common/ad_serdes_clk.v
M_DEPS += ../xilinx/common/ad_serdes_out.v
M_DEPS += axi_ad9122.v
M_DEPS += axi_ad9122_channel.v
M_DEPS += axi_ad9122_constr.xdc
M_DEPS += axi_ad9122_core.v
M_DEPS += axi_ad9122_if.v
M_DEPS += axi_ad9122_constr.xdc
M_DEPS += axi_ad9122.v
M_DEPS += axi_ad9122_ip.tcl
M_VIVADO := vivado -mode batch -source
@ -38,6 +38,10 @@ M_FLIST += *.log
M_FLIST += component.xml
M_FLIST += *.jou
M_FLIST += xgui
M_FLIST += *.ip_user_files
M_FLIST += *.srcs
M_FLIST += *.hw
M_FLIST += *.sim
M_FLIST += .Xil
@ -54,7 +58,7 @@ clean-all:
axi_ad9122.xpr: $(M_DEPS)
rm -rf $(M_FLIST)
-rm -rf $(M_FLIST)
$(M_VIVADO) axi_ad9122_ip.tcl >> axi_ad9122_ip.log 2>&1
####################################################################################

23
library/axi_ad9122/axi_ad9122.v
View File

@ -87,7 +87,9 @@ module axi_ad9122 (
s_axi_rvalid,
s_axi_rdata,
s_axi_rresp,
s_axi_rready);
s_axi_rready,
s_axi_awprot,
s_axi_arprot);
// parameters
@ -95,6 +97,11 @@ module axi_ad9122 (
parameter DEVICE_TYPE = 0;
parameter SERDES_OR_DDR_N = 1;
parameter MMCM_OR_BUFIO_N = 1;
parameter MMCM_CLKIN_PERIOD = 1.667;
parameter MMCM_VCO_DIV = 2;
parameter MMCM_VCO_MUL = 4;
parameter MMCM_CLK0_DIV = 2;
parameter MMCM_CLK1_DIV = 8;
parameter DAC_DATAPATH_DISABLE = 0;
parameter IO_DELAY_GROUP = "dev_if_delay_group";
@ -147,6 +154,9 @@ module axi_ad9122 (
output [31:0] s_axi_rdata;
output [ 1:0] s_axi_rresp;
input s_axi_rready;
input [ 2:0] s_axi_awprot;
input [ 2:0] s_axi_arprot;
// internal clocks and resets
@ -177,8 +187,8 @@ module axi_ad9122 (
wire up_drp_sel_s;
wire up_drp_wr_s;
wire [11:0] up_drp_addr_s;
wire [15:0] up_drp_wdata_s;
wire [15:0] up_drp_rdata_s;
wire [31:0] up_drp_wdata_s;
wire [31:0] up_drp_rdata_s;
wire up_drp_ready_s;
wire up_drp_locked_s;
wire up_wreq_s;
@ -200,7 +210,12 @@ module axi_ad9122 (
axi_ad9122_if #(
.DEVICE_TYPE (DEVICE_TYPE),
.SERDES_OR_DDR_N (SERDES_OR_DDR_N),
.MMCM_OR_BUFIO_N (MMCM_OR_BUFIO_N))
.MMCM_OR_BUFIO_N (MMCM_OR_BUFIO_N),
.MMCM_CLKIN_PERIOD (MMCM_CLKIN_PERIOD),
.MMCM_VCO_DIV (MMCM_VCO_DIV),
.MMCM_VCO_MUL (MMCM_VCO_MUL),
.MMCM_CLK0_DIV (MMCM_CLK0_DIV),
.MMCM_CLK1_DIV (MMCM_CLK1_DIV))
i_if (
.dac_clk_in_p (dac_clk_in_p),
.dac_clk_in_n (dac_clk_in_n),

5
library/axi_ad9122/axi_ad9122_channel.v
View File

@ -141,7 +141,7 @@ module axi_ad9122_channel (
dac_enable <= (dac_data_sel_s == 4'h2) ? 1'b1 : 1'b0;
case (dac_data_sel_s)
4'h2: dac_data <= dma_data;
4'h1: dac_data <= { dac_pat_data_2_s, dac_pat_data_1_s,
4'ha, 4'h1: dac_data <= {dac_pat_data_2_s, dac_pat_data_1_s,
dac_pat_data_2_s, dac_pat_data_1_s};
default: dac_data <= dac_dds_data;
endcase
@ -245,7 +245,7 @@ module axi_ad9122_channel (
// single channel processor
up_dac_channel #(.DAC_CHANNEL_ID(CHANNEL_ID)) i_up_dac_channel (
up_dac_channel #(.CHANNEL_ID(CHANNEL_ID)) i_up_dac_channel (
.dac_clk (dac_div_clk),
.dac_rst (dac_rst),
.dac_dds_scale_1 (dac_dds_scale_1_s),
@ -257,6 +257,7 @@ module axi_ad9122_channel (
.dac_pat_data_1 (dac_pat_data_1_s),
.dac_pat_data_2 (dac_pat_data_2_s),
.dac_data_sel (dac_data_sel_s),
.dac_iq_mode (),
.dac_iqcor_enb (),
.dac_iqcor_coeff_1 (),
.dac_iqcor_coeff_2 (),

3
library/axi_ad9122/axi_ad9122_constr.sdc Normal file
View File

@ -0,0 +1,3 @@
set_false_path -from [get_registers *up_drp_locked*] -to [get_registers *dac_status_m1*]

4
library/axi_ad9122/axi_ad9122_constr.xdc
View File

@ -1 +1,3 @@
set_false_path -from [get_cells -hier -filter {name =~ *up_drp_locked_reg && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *dac_status_m1_reg && IS_SEQUENTIAL}]
set_false_path -from [get_cells -hier -filter {name =~ *up_drp_locked_reg && IS_SEQUENTIAL}] \
-to [get_cells -hier -filter {name =~ *dac_status_m1_reg && IS_SEQUENTIAL}]

5
library/axi_ad9122/axi_ad9122_core.v
View File

@ -156,8 +156,8 @@ module axi_ad9122_core (
output up_drp_sel;
output up_drp_wr;
output [11:0] up_drp_addr;
output [15:0] up_drp_wdata;
input [15:0] up_drp_rdata;
output [31:0] up_drp_wdata;
input [31:0] up_drp_rdata;
input up_drp_ready;
input up_drp_locked;
@ -278,6 +278,7 @@ module axi_ad9122_core (
.dac_rst (dac_rst),
.dac_sync (dac_sync_out),
.dac_frame (dac_frame_s),
.dac_clksel (),
.dac_par_type (),
.dac_par_enb (),
.dac_r1_mode (),

107
library/axi_ad9122/axi_ad9122_hw.tcl Normal file
View File

@ -0,0 +1,107 @@
package require -exact qsys 13.0
source ../scripts/adi_env.tcl
source ../scripts/adi_ip_alt.tcl
ad_ip_create axi_ad9122 {AXI AD9122 Interface}
ad_ip_files axi_ad9122 [list \
$ad_hdl_dir/library/common/ad_dds_sine.v \
$ad_hdl_dir/library/common/ad_dds_1.v \
$ad_hdl_dir/library/common/ad_dds.v \
$ad_hdl_dir/library/altera/common/ad_mul.v \
$ad_hdl_dir/library/common/ad_rst.v \
$ad_hdl_dir/library/common/up_axi.v \
$ad_hdl_dir/library/common/up_xfer_cntrl.v \
$ad_hdl_dir/library/common/up_xfer_status.v \
$ad_hdl_dir/library/common/up_clock_mon.v \
$ad_hdl_dir/library/common/up_dac_common.v \
$ad_hdl_dir/library/common/up_dac_channel.v \
axi_ad9122_channel.v \
axi_ad9122_core.v \
axi_ad9122_if.v \
axi_ad9122.v \
$ad_hdl_dir/library/common/ad_axi_ip_constr.sdc \
axi_ad9122_constr.sdc] \
axi_ad9122_fileset
# parameters
add_parameter ID INTEGER 0
set_parameter_property ID DEFAULT_VALUE 0
set_parameter_property ID DISPLAY_NAME ID
set_parameter_property ID TYPE INTEGER
set_parameter_property ID UNITS None
set_parameter_property ID HDL_PARAMETER true
add_parameter DEVICE_TYPE INTEGER 0
set_parameter_property DEVICE_TYPE DEFAULT_VALUE 0
set_parameter_property DEVICE_TYPE DISPLAY_NAME DEVICE_TYPE
set_parameter_property DEVICE_TYPE TYPE INTEGER
set_parameter_property DEVICE_TYPE UNITS None
set_parameter_property DEVICE_TYPE HDL_PARAMETER true
# axi4 slave
ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn
# dac device interface
add_interface device_if conduit end
set_interface_property device_if associatedClock none
set_interface_property device_if associatedReset none
add_interface_port device_if dac_clk_in_p dac_clk_in_p Input 1
add_interface_port device_if dac_clk_in_n dac_clk_in_n Input 1
add_interface_port device_if dac_clk_out_p dac_clk_out_p Output 1
add_interface_port device_if dac_clk_out_n dac_clk_out_n Output 1
add_interface_port device_if dac_frame_out_p dac_frame_out_p Output 1
add_interface_port device_if dac_frame_out_n dac_frame_out_n Output 1
add_interface_port device_if dac_data_out_p dac_data_out_p Output 16
add_interface_port device_if dac_data_out_n dac_data_out_n Output 16
add_interface_port device_if dac_sync_out dac_sync_out Output 1
add_interface_port device_if dac_sync_in dac_sync_in Input 1
# dma interface
ad_alt_intf clock dac_div_clk Output 1
add_interface dac_ch_0 conduit end
add_interface_port dac_ch_0 dac_valid_0 valid Output 1
add_interface_port dac_ch_0 dac_enable_0 enable Output 1
add_interface_port dac_ch_0 dac_ddata_0 data Input 64
set_interface_property dac_ch_0 associatedClock if_dac_div_clk
set_interface_property dac_ch_0 associatedReset none
add_interface dac_ch_1 conduit end
add_interface_port dac_ch_1 dac_valid_1 valid Output 1
add_interface_port dac_ch_1 dac_enable_1 enable Output 1
add_interface_port dac_ch_1 dac_ddata_1 data Input 64
set_interface_property dac_ch_1 associatedClock if_dac_div_clk
set_interface_property dac_ch_1 associatedReset none
ad_alt_intf signal dac_dovf input 1 ovf
ad_alt_intf signal dac_dunf input 1 unf
# SERDES instances and configurations
add_hdl_instance ad_serdes_clk_core_tx alt_serdes
set_instance_parameter_value ad_serdes_clk_core_tx {MODE} {CLK}
set_instance_parameter_value ad_serdes_clk_core_tx {DDR_OR_SDR_N} {1}
set_instance_parameter_value ad_serdes_clk_core_tx {SERDES_FACTOR} {8}
set_instance_parameter_value ad_serdes_clk_core_tx {CLKIN_FREQUENCY} {500.0}
add_hdl_instance ad_serdes_out_core alt_serdes
set_instance_parameter_value ad_serdes_out_core {MODE} {OUT}
set_instance_parameter_value ad_serdes_out_core {DDR_OR_SDR_N} {1}
set_instance_parameter_value ad_serdes_out_core {SERDES_FACTOR} {8}
set_instance_parameter_value ad_serdes_out_core {CLKIN_FREQUENCY} {500.0}
proc axi_ad9122_fileset { entityName } {
ad_ip_modfile ad_serdes_out.v ad_serdes_out.v ad_serdes_out_core
ad_ip_modfile ad_serdes_clk.v ad_serdes_clk.v ad_serdes_clk_core_tx
}

48
library/axi_ad9122/axi_ad9122_if.v
View File

@ -100,6 +100,11 @@ module axi_ad9122_if (
parameter DEVICE_TYPE = 0;
parameter SERDES_OR_DDR_N = 1;
parameter MMCM_OR_BUFIO_N = 1;
parameter MMCM_CLKIN_PERIOD = 1.667;
parameter MMCM_VCO_DIV = 6;
parameter MMCM_VCO_MUL = 12;
parameter MMCM_CLK0_DIV = 2;
parameter MMCM_CLK1_DIV = 8;
parameter IO_DELAY_GROUP = "dac_if_delay_group";
// dac interface
@ -151,8 +156,8 @@ module axi_ad9122_if (
input up_drp_sel;
input up_drp_wr;
input [11:0] up_drp_addr;
input [15:0] up_drp_wdata;
output [15:0] up_drp_rdata;
input [31:0] up_drp_wdata;
output [31:0] up_drp_rdata;
output up_drp_ready;
output up_drp_locked;
@ -161,6 +166,11 @@ module axi_ad9122_if (
reg dac_status_m1 = 'd0;
reg dac_status = 'd0;
// internal signals
wire dac_out_clk;
wire loaden_s;
// dac status
always @(posedge dac_div_clk) begin
@ -177,12 +187,13 @@ module axi_ad9122_if (
ad_serdes_out #(
.DEVICE_TYPE (DEVICE_TYPE),
.SERDES_OR_DDR_N(SERDES_OR_DDR_N),
.DATA_WIDTH(16))
.DDR_OR_SDR_N (SERDES_OR_DDR_N),
.DATA_WIDTH (16))
i_serdes_out_data (
.rst (dac_rst),
.clk (dac_clk),
.div_clk (dac_div_clk),
.loaden (loaden_s),
.data_s0 (dac_data_i0),
.data_s1 (dac_data_q0),
.data_s2 (dac_data_i1),
@ -198,12 +209,13 @@ module axi_ad9122_if (
ad_serdes_out #(
.DEVICE_TYPE (DEVICE_TYPE),
.SERDES_OR_DDR_N(SERDES_OR_DDR_N),
.DATA_WIDTH(1))
.DDR_OR_SDR_N (SERDES_OR_DDR_N),
.DATA_WIDTH (1))
i_serdes_out_frame (
.rst (dac_rst),
.clk (dac_clk),
.div_clk (dac_div_clk),
.loaden (loaden_s),
.data_s0 (dac_frame_i0),
.data_s1 (dac_frame_q0),
.data_s2 (dac_frame_i1),
@ -219,12 +231,13 @@ module axi_ad9122_if (
ad_serdes_out #(
.DEVICE_TYPE (DEVICE_TYPE),
.SERDES_OR_DDR_N(SERDES_OR_DDR_N),
.DATA_WIDTH(1))
.DDR_OR_SDR_N (SERDES_OR_DDR_N),
.DATA_WIDTH (1))
i_serdes_out_clk (
.rst (dac_rst),
.clk (dac_clk),
.div_clk (dac_div_clk),
.loaden (loaden_s),
.data_s0 (1'b1),
.data_s1 (1'b0),
.data_s2 (1'b1),
@ -239,20 +252,23 @@ module axi_ad9122_if (
// dac clock input buffers
ad_serdes_clk #(
.SERDES_OR_DDR_N (SERDES_OR_DDR_N),
.DDR_OR_SDR_N (SERDES_OR_DDR_N),
.MMCM_OR_BUFR_N (MMCM_OR_BUFIO_N),
.MMCM_DEVICE_TYPE (DEVICE_TYPE),
.MMCM_CLKIN_PERIOD (1.667),
.MMCM_VCO_DIV (6),
.MMCM_VCO_MUL (12),
.MMCM_CLK0_DIV (2),
.MMCM_CLK1_DIV (8))
.DEVICE_TYPE (DEVICE_TYPE),
.MMCM_CLKIN_PERIOD (MMCM_CLKIN_PERIOD),
.MMCM_VCO_DIV (MMCM_VCO_DIV),
.MMCM_VCO_MUL (MMCM_VCO_MUL),
.MMCM_CLK0_DIV (MMCM_CLK0_DIV),
.MMCM_CLK1_DIV (MMCM_CLK1_DIV))
i_serdes_clk (
.mmcm_rst (mmcm_rst),
.rst (mmcm_rst),
.clk_in_p (dac_clk_in_p),
.clk_in_n (dac_clk_in_n),
.clk (dac_clk),
.div_clk (dac_div_clk),
.out_clk (dac_out_clk),
.loaden (loaden_s),
.phase (),
.up_clk (up_clk),
.up_rstn (up_rstn),
.up_drp_sel (up_drp_sel),

8
library/axi_ad9122/axi_ad9122_ip.tcl
View File

@ -5,14 +5,14 @@ source $ad_hdl_dir/library/scripts/adi_ip.tcl
adi_ip_create axi_ad9122
adi_ip_files axi_ad9122 [list \
"$ad_hdl_dir/library/common/ad_mul.v" \
"$ad_hdl_dir/library/xilinx/common/ad_mul.v" \
"$ad_hdl_dir/library/common/ad_dds_sine.v" \
"$ad_hdl_dir/library/common/ad_dds_1.v" \
"$ad_hdl_dir/library/common/ad_dds.v" \
"$ad_hdl_dir/library/common/ad_rst.v" \
"$ad_hdl_dir/library/common/ad_mmcm_drp.v" \
"$ad_hdl_dir/library/common/ad_serdes_out.v" \
"$ad_hdl_dir/library/common/ad_serdes_clk.v" \
"$ad_hdl_dir/library/xilinx/common/ad_mmcm_drp.v" \
"$ad_hdl_dir/library/xilinx/common/ad_serdes_out.v" \
"$ad_hdl_dir/library/xilinx/common/ad_serdes_clk.v" \
"$ad_hdl_dir/library/common/up_axi.v" \
"$ad_hdl_dir/library/common/up_xfer_cntrl.v" \
"$ad_hdl_dir/library/common/up_xfer_status.v" \

26
library/axi_ad9144/Makefile
View File

@ -5,25 +5,25 @@
####################################################################################
####################################################################################
M_DEPS := axi_ad9144_ip.tcl
M_DEPS += ../scripts/adi_env.tcl
M_DEPS += ../scripts/adi_ip.tcl
M_DEPS += ../common/ad_axi_ip_constr.xdc
M_DEPS += ../common/ad_mul.v
M_DEPS += ../common/ad_dds_sine.v
M_DEPS += ../common/ad_dds_1.v
M_DEPS += ../common/ad_dds.v
M_DEPS += ../common/ad_dds_1.v
M_DEPS += ../common/ad_dds_sine.v
M_DEPS += ../common/ad_rst.v
M_DEPS += ../common/up_axi.v
M_DEPS += ../common/up_clock_mon.v
M_DEPS += ../common/up_dac_channel.v
M_DEPS += ../common/up_dac_common.v
M_DEPS += ../common/up_xfer_cntrl.v
M_DEPS += ../common/up_xfer_status.v
M_DEPS += ../common/up_clock_mon.v
M_DEPS += ../common/up_dac_common.v
M_DEPS += ../common/up_dac_channel.v
M_DEPS += ../scripts/adi_env.tcl
M_DEPS += ../scripts/adi_ip.tcl
M_DEPS += ../xilinx/common/ad_mul.v
M_DEPS += axi_ad9144.v
M_DEPS += axi_ad9144_channel.v
M_DEPS += axi_ad9144_core.v
M_DEPS += axi_ad9144_if.v
M_DEPS += axi_ad9144.v
M_DEPS += axi_ad9144_ip.tcl
M_VIVADO := vivado -mode batch -source
@ -34,6 +34,10 @@ M_FLIST += *.log
M_FLIST += component.xml
M_FLIST += *.jou
M_FLIST += xgui
M_FLIST += *.ip_user_files
M_FLIST += *.srcs
M_FLIST += *.hw
M_FLIST += *.sim
M_FLIST += .Xil
@ -50,7 +54,7 @@ clean-all:
axi_ad9144.xpr: $(M_DEPS)
rm -rf $(M_FLIST)
-rm -rf $(M_FLIST)
$(M_VIVADO) axi_ad9144_ip.tcl >> axi_ad9144_ip.log 2>&1
####################################################################################

10
library/axi_ad9144/axi_ad9144.v
View File

@ -34,8 +34,6 @@
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
@ -45,7 +43,9 @@ module axi_ad9144 (
// tx_clk is (line-rate/40)
tx_clk,
tx_valid,
tx_data,
tx_ready,
// dma interface
@ -92,6 +92,7 @@ module axi_ad9144 (
// parameters
parameter ID = 0;
parameter DEVICE_TYPE = 0;
parameter QUAD_OR_DUAL_N = 1;
parameter DAC_DATAPATH_DISABLE = 0;
@ -99,7 +100,9 @@ module axi_ad9144 (
// tx_clk is (line-rate/40)
input tx_clk;
output tx_valid;
output [(128*QUAD_OR_DUAL_N)+127:0] tx_data;
input tx_ready;
// dma interface
@ -184,11 +187,12 @@ module axi_ad9144 (
// dual/quad cores
assign tx_valid = 1'b1;
assign tx_data = (QUAD_OR_DUAL_N == 1) ? tx_data_s : tx_data_s[127:0];
// device interface
axi_ad9144_if i_if (
axi_ad9144_if #(.DEVICE_TYPE (DEVICE_TYPE)) i_if (
.tx_clk (tx_clk),
.tx_data (tx_data_s),
.dac_clk (dac_clk),

445
library/axi_ad9144/axi_ad9144_channel.v
View File

@ -34,8 +34,6 @@
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
@ -104,8 +102,6 @@ module axi_ad9144_channel (
reg [63:0] dac_data = 'd0;
reg [63:0] dac_pn7_data = 'd0;
reg [63:0] dac_pn15_data = 'd0;
reg [63:0] dac_pn23_data = 'd0;
reg [63:0] dac_pn31_data = 'd0;
reg [15:0] dac_dds_phase_0_0 = 'd0;
reg [15:0] dac_dds_phase_0_1 = 'd0;
reg [15:0] dac_dds_phase_1_0 = 'd0;
@ -133,312 +129,174 @@ module axi_ad9144_channel (
wire [15:0] dac_pat_data_1_s;
wire [15:0] dac_pat_data_2_s;
wire [ 3:0] dac_data_sel_s;
wire [63:0] dac_pn7_data_i_s;
wire [63:0] dac_pn15_data_i_s;
wire [63:0] dac_pn7_data_s;
wire [63:0] dac_pn15_data_s;
// pn7 function
// PN7 function
function [63:0] pn7;
input [63:0] din;
input [7:0] din;
reg [63:0] dout;
begin
dout[63] = din[ 7] ^ din[ 6];
dout[62] = din[ 6] ^ din[ 5];
dout[61] = din[ 5] ^ din[ 4];
dout[60] = din[ 4] ^ din[ 3];
dout[59] = din[ 3] ^ din[ 2];
dout[58] = din[ 2] ^ din[ 1];
dout[57] = din[ 1] ^ din[ 0];
dout[56] = din[ 0] ^ din[ 7] ^ din[ 6];
dout[55] = din[ 7] ^ din[ 5];
dout[54] = din[ 6] ^ din[ 4];
dout[53] = din[ 5] ^ din[ 3];
dout[52] = din[ 4] ^ din[ 2];
dout[51] = din[ 3] ^ din[ 1];
dout[50] = din[ 2] ^ din[ 0];
dout[49] = din[ 1] ^ din[ 7] ^ din[ 6];
dout[48] = din[ 0] ^ din[ 6] ^ din[ 5];
dout[47] = din[ 7] ^ din[ 5] ^ din[ 6] ^ din[ 4];
dout[46] = din[ 6] ^ din[ 4] ^ din[ 5] ^ din[ 3];
dout[45] = din[ 5] ^ din[ 3] ^ din[ 4] ^ din[ 2];
dout[44] = din[ 4] ^ din[ 2] ^ din[ 3] ^ din[ 1];
dout[43] = din[ 3] ^ din[ 1] ^ din[ 2] ^ din[ 0];
dout[42] = din[ 2] ^ din[ 0] ^ din[ 1] ^ din[ 7] ^ din[ 6];
dout[41] = din[ 1] ^ din[ 7] ^ din[ 0] ^ din[ 5];
dout[40] = din[ 0] ^ din[ 7] ^ din[ 4];
dout[39] = din[ 7] ^ din[ 3];
dout[38] = din[ 6] ^ din[ 2];
dout[37] = din[ 5] ^ din[ 1];
dout[36] = din[ 4] ^ din[ 0];
dout[35] = din[ 3] ^ din[ 7] ^ din[ 6];
dout[34] = din[ 2] ^ din[ 6] ^ din[ 5];
dout[33] = din[ 1] ^ din[ 5] ^ din[ 4];
dout[32] = din[ 0] ^ din[ 4] ^ din[ 3];
dout[31] = din[ 7] ^ din[ 3] ^ din[ 6] ^ din[ 2];
dout[30] = din[ 6] ^ din[ 2] ^ din[ 5] ^ din[ 1];
dout[29] = din[ 5] ^ din[ 1] ^ din[ 4] ^ din[ 0];
dout[28] = din[ 4] ^ din[ 0] ^ din[ 3] ^ din[ 7] ^ din[ 6];
dout[27] = din[ 3] ^ din[ 7] ^ din[ 2] ^ din[ 5];
dout[26] = din[ 2] ^ din[ 6] ^ din[ 1] ^ din[ 4];
dout[25] = din[ 1] ^ din[ 5] ^ din[ 0] ^ din[ 3];
dout[24] = din[ 0] ^ din[ 4] ^ din[ 7] ^ din[ 6] ^ din[ 2];
dout[23] = din[ 7] ^ din[ 3] ^ din[ 5] ^ din[ 1];
dout[22] = din[ 6] ^ din[ 2] ^ din[ 4] ^ din[ 0];
dout[21] = din[ 5] ^ din[ 1] ^ din[ 3] ^ din[ 7] ^ din[ 6];
dout[20] = din[ 4] ^ din[ 0] ^ din[ 6] ^ din[ 2] ^ din[ 5];
dout[19] = din[ 3] ^ din[ 7] ^ din[ 5] ^ din[ 6] ^ din[ 1] ^ din[ 4];
dout[18] = din[ 2] ^ din[ 6] ^ din[ 4] ^ din[ 5] ^ din[ 0] ^ din[ 3];
dout[17] = din[ 1] ^ din[ 5] ^ din[ 3] ^ din[ 4] ^ din[ 7] ^ din[ 6] ^ din[ 2];
dout[16] = din[ 0] ^ din[ 4] ^ din[ 6] ^ din[ 2] ^ din[ 3] ^ din[ 5] ^ din[ 1];
dout[15] = din[ 7] ^ din[ 3] ^ din[ 5] ^ din[ 1] ^ din[ 6] ^ din[ 2] ^ din[ 4] ^ din[ 0];
dout[14] = din[ 2] ^ din[ 4] ^ din[ 0] ^ din[ 5] ^ din[ 1] ^ din[ 3] ^ din[ 7];
dout[13] = din[ 1] ^ din[ 3] ^ din[ 7] ^ din[ 4] ^ din[ 0] ^ din[ 2];
dout[12] = din[ 0] ^ din[ 2] ^ din[ 3] ^ din[ 7] ^ din[ 1];
dout[11] = din[ 7] ^ din[ 1] ^ din[ 2] ^ din[ 0];
dout[10] = din[ 0] ^ din[ 1] ^ din[ 7];
dout[ 9] = din[ 7] ^ din[ 0];
dout[ 8] = din[ 7];
dout[ 7] = din[ 6];
dout[ 6] = din[ 5];
dout[ 5] = din[ 4];
dout[ 4] = din[ 3];
dout[ 3] = din[ 2];
dout[ 2] = din[ 1];
dout[ 1] = din[ 0];
dout[ 0] = din[ 7] ^ din[ 6];
dout[15] = din[ 6] ^ din[ 5];
dout[14] = din[ 5] ^ din[ 4];
dout[13] = din[ 4] ^ din[ 3];
dout[12] = din[ 3] ^ din[ 2];
dout[11] = din[ 2] ^ din[ 1];
dout[10] = din[ 1] ^ din[ 0];
dout[ 9] = din[ 0] ^ din[ 6] ^ din[ 5];
dout[ 8] = din[ 6] ^ din[ 4];
dout[ 7] = din[ 5] ^ din[ 3];
dout[ 6] = din[ 4] ^ din[ 2];
dout[ 5] = din[ 3] ^ din[ 1];
dout[ 4] = din[ 2] ^ din[ 0];
dout[ 3] = din[ 1] ^ din[ 6] ^ din[ 5];
dout[ 2] = din[ 0] ^ din[ 5] ^ din[ 4];
dout[ 1] = din[ 6] ^ din[ 4] ^ din[ 5] ^ din[ 3];
dout[ 0] = din[ 5] ^ din[ 3] ^ din[ 4] ^ din[ 2];
dout[31] = din[ 4] ^ din[ 2] ^ din[ 3] ^ din[ 1];
dout[30] = din[ 3] ^ din[ 1] ^ din[ 2] ^ din[ 0];
dout[29] = din[ 2] ^ din[ 0] ^ din[ 1] ^ din[ 6] ^ din[ 5];
dout[28] = din[ 1] ^ din[ 6] ^ din[ 0] ^ din[ 4];
dout[27] = din[ 0] ^ din[ 6] ^ din[ 3];
dout[26] = din[ 6] ^ din[ 2];
dout[25] = din[ 5] ^ din[ 1];
dout[24] = din[ 4] ^ din[ 0];
dout[23] = din[ 3] ^ din[ 6] ^ din[ 5];
dout[22] = din[ 2] ^ din[ 5] ^ din[ 4];
dout[21] = din[ 1] ^ din[ 4] ^ din[ 3];
dout[20] = din[ 0] ^ din[ 3] ^ din[ 2];
dout[19] = din[ 6] ^ din[ 2] ^ din[ 5] ^ din[ 1];
dout[18] = din[ 5] ^ din[ 1] ^ din[ 4] ^ din[ 0];
dout[17] = din[ 4] ^ din[ 0] ^ din[ 3] ^ din[ 6] ^ din[ 5];
dout[16] = din[ 3] ^ din[ 6] ^ din[ 2] ^ din[ 4];
dout[47] = din[ 2] ^ din[ 5] ^ din[ 1] ^ din[ 3];
dout[46] = din[ 1] ^ din[ 4] ^ din[ 0] ^ din[ 2];
dout[45] = din[ 0] ^ din[ 3] ^ din[ 6] ^ din[ 5] ^ din[ 1];
dout[44] = din[ 6] ^ din[ 2] ^ din[ 4] ^ din[ 0];
dout[43] = din[ 1] ^ din[ 3] ^ din[ 6];
dout[42] = din[ 0] ^ din[ 5] ^ din[ 2];
dout[41] = din[ 6] ^ din[ 4] ^ din[ 5] ^ din[ 1];
dout[40] = din[ 5] ^ din[ 3] ^ din[ 4] ^ din[ 0];
dout[39] = din[ 4] ^ din[ 2] ^ din[ 3] ^ din[ 6] ^ din[ 5];
dout[38] = din[ 3] ^ din[ 5] ^ din[ 1] ^ din[ 2] ^ din[ 4];
dout[37] = din[ 2] ^ din[ 4] ^ din[ 0] ^ din[ 1] ^ din[ 3];
dout[36] = din[ 1] ^ din[ 3] ^ din[ 6] ^ din[ 0] ^ din[ 5] ^ din[ 2];
dout[35] = din[ 0] ^ din[ 2] ^ din[ 6] ^ din[ 4] ^ din[ 1];
dout[34] = din[ 6] ^ din[ 1] ^ din[ 3] ^ din[ 0];
dout[33] = din[ 0] ^ din[ 2] ^ din[ 6];
dout[32] = din[ 6] ^ din[ 1];
dout[63] = din[ 5] ^ din[ 0];
dout[62] = din[ 4] ^ din[ 6] ^ din[ 5];
dout[61] = din[ 3] ^ din[ 5] ^ din[ 4];
dout[60] = din[ 2] ^ din[ 4] ^ din[ 3];
dout[59] = din[ 1] ^ din[ 3] ^ din[ 2];
dout[58] = din[ 0] ^ din[ 2] ^ din[ 1];
dout[57] = din[ 6] ^ din[ 1] ^ din[ 5] ^ din[ 0];
dout[56] = din[ 0] ^ din[ 4] ^ din[ 6];
dout[55] = din[ 6] ^ din[ 3];
dout[54] = din[ 5] ^ din[ 2];
dout[53] = din[ 4] ^ din[ 1];
dout[52] = din[ 3] ^ din[ 0];
dout[51] = din[ 2] ^ din[ 6] ^ din[ 5];
dout[50] = din[ 1] ^ din[ 5] ^ din[ 4];
dout[49] = din[ 0] ^ din[ 4] ^ din[ 3];
dout[48] = din[ 6] ^ din[ 3] ^ din[ 5] ^ din[ 2];
pn7 = dout;
end
endfunction
// pn15 function
// PN15 function
function [63:0] pn15;
input [63:0] din;
input [15:0] din;
reg [63:0] dout;
begin
dout[63] = din[15] ^ din[14];
dout[62] = din[14] ^ din[13];
dout[61] = din[13] ^ din[12];
dout[60] = din[12] ^ din[11];
dout[59] = din[11] ^ din[10];
dout[58] = din[10] ^ din[ 9];
dout[57] = din[ 9] ^ din[ 8];
dout[56] = din[ 8] ^ din[ 7];
dout[55] = din[ 7] ^ din[ 6];
dout[54] = din[ 6] ^ din[ 5];
dout[53] = din[ 5] ^ din[ 4];
dout[52] = din[ 4] ^ din[ 3];
dout[51] = din[ 3] ^ din[ 2];
dout[50] = din[ 2] ^ din[ 1];
dout[49] = din[ 1] ^ din[ 0];
dout[48] = din[ 0] ^ din[15] ^ din[14];
dout[47] = din[15] ^ din[13];
dout[46] = din[14] ^ din[12];
dout[45] = din[13] ^ din[11];
dout[44] = din[12] ^ din[10];
dout[43] = din[11] ^ din[ 9];
dout[42] = din[10] ^ din[ 8];
dout[41] = din[ 9] ^ din[ 7];
dout[40] = din[ 8] ^ din[ 6];
dout[39] = din[ 7] ^ din[ 5];
dout[38] = din[ 6] ^ din[ 4];
dout[37] = din[ 5] ^ din[ 3];
dout[36] = din[ 4] ^ din[ 2];
dout[35] = din[ 3] ^ din[ 1];
dout[34] = din[ 2] ^ din[ 0];
dout[33] = din[ 1] ^ din[15] ^ din[14];
dout[32] = din[ 0] ^ din[14] ^ din[13];
dout[31] = din[15] ^ din[13] ^ din[14] ^ din[12];
dout[30] = din[14] ^ din[12] ^ din[13] ^ din[11];
dout[29] = din[13] ^ din[11] ^ din[12] ^ din[10];
dout[28] = din[12] ^ din[10] ^ din[11] ^ din[ 9];
dout[27] = din[11] ^ din[ 9] ^ din[10] ^ din[ 8];
dout[26] = din[10] ^ din[ 8] ^ din[ 9] ^ din[ 7];
dout[25] = din[ 9] ^ din[ 7] ^ din[ 8] ^ din[ 6];
dout[24] = din[ 8] ^ din[ 6] ^ din[ 7] ^ din[ 5];
dout[23] = din[ 7] ^ din[ 5] ^ din[ 6] ^ din[ 4];
dout[22] = din[ 6] ^ din[ 4] ^ din[ 5] ^ din[ 3];
dout[21] = din[ 5] ^ din[ 3] ^ din[ 4] ^ din[ 2];
dout[20] = din[ 4] ^ din[ 2] ^ din[ 3] ^ din[ 1];
dout[19] = din[ 3] ^ din[ 1] ^ din[ 2] ^ din[ 0];
dout[18] = din[ 2] ^ din[ 0] ^ din[ 1] ^ din[15] ^ din[14];
dout[17] = din[ 1] ^ din[15] ^ din[ 0] ^ din[13];
dout[16] = din[ 0] ^ din[15] ^ din[12];
dout[15] = din[15] ^ din[11];
dout[14] = din[14] ^ din[10];
dout[13] = din[13] ^ din[ 9];
dout[12] = din[12] ^ din[ 8];
dout[11] = din[11] ^ din[ 7];
dout[10] = din[10] ^ din[ 6];
dout[ 9] = din[ 9] ^ din[ 5];
dout[ 8] = din[ 8] ^ din[ 4];
dout[ 7] = din[ 7] ^ din[ 3];
dout[ 6] = din[ 6] ^ din[ 2];
dout[ 5] = din[ 5] ^ din[ 1];
dout[ 4] = din[ 4] ^ din[ 0];
dout[ 3] = din[ 3] ^ din[15] ^ din[14];
dout[ 2] = din[ 2] ^ din[14] ^ din[13];
dout[ 1] = din[ 1] ^ din[13] ^ din[12];
dout[ 0] = din[ 0] ^ din[12] ^ din[11];
dout[15] = din[14] ^ din[13];
dout[14] = din[13] ^ din[12];
dout[13] = din[12] ^ din[11];
dout[12] = din[11] ^ din[10];
dout[11] = din[10] ^ din[ 9];
dout[10] = din[ 9] ^ din[ 8];
dout[ 9] = din[ 8] ^ din[ 7];
dout[ 8] = din[ 7] ^ din[ 6];
dout[ 7] = din[ 6] ^ din[ 5];
dout[ 6] = din[ 5] ^ din[ 4];
dout[ 5] = din[ 4] ^ din[ 3];
dout[ 4] = din[ 3] ^ din[ 2];
dout[ 3] = din[ 2] ^ din[ 1];
dout[ 2] = din[ 1] ^ din[ 0];
dout[ 1] = din[ 0] ^ din[14] ^ din[13];
dout[ 0] = din[14] ^ din[12];
dout[31] = din[13] ^ din[11];
dout[30] = din[12] ^ din[10];
dout[29] = din[11] ^ din[ 9];
dout[28] = din[10] ^ din[ 8];
dout[27] = din[ 9] ^ din[ 7];
dout[26] = din[ 8] ^ din[ 6];
dout[25] = din[ 7] ^ din[ 5];
dout[24] = din[ 6] ^ din[ 4];
dout[23] = din[ 5] ^ din[ 3];
dout[22] = din[ 4] ^ din[ 2];
dout[21] = din[ 3] ^ din[ 1];
dout[20] = din[ 2] ^ din[ 0];
dout[19] = din[ 1] ^ din[14] ^ din[13];
dout[18] = din[ 0] ^ din[13] ^ din[12];
dout[17] = din[14] ^ din[12] ^ din[13] ^ din[11];
dout[16] = din[13] ^ din[11] ^ din[12] ^ din[10];
dout[47] = din[12] ^ din[10] ^ din[11] ^ din[ 9];
dout[46] = din[11] ^ din[ 9] ^ din[10] ^ din[ 8];
dout[45] = din[10] ^ din[ 8] ^ din[ 9] ^ din[ 7];
dout[44] = din[ 9] ^ din[ 7] ^ din[ 8] ^ din[ 6];
dout[43] = din[ 8] ^ din[ 6] ^ din[ 7] ^ din[ 5];
dout[42] = din[ 7] ^ din[ 5] ^ din[ 6] ^ din[ 4];
dout[41] = din[ 6] ^ din[ 4] ^ din[ 5] ^ din[ 3];
dout[40] = din[ 5] ^ din[ 3] ^ din[ 4] ^ din[ 2];
dout[39] = din[ 4] ^ din[ 2] ^ din[ 3] ^ din[ 1];
dout[38] = din[ 3] ^ din[ 1] ^ din[ 2] ^ din[ 0];
dout[37] = din[ 2] ^ din[ 0] ^ din[ 1] ^ din[14] ^ din[13];
dout[36] = din[ 1] ^ din[14] ^ din[ 0] ^ din[12];
dout[35] = din[ 0] ^ din[14] ^ din[11];
dout[34] = din[14] ^ din[10];
dout[33] = din[13] ^ din[ 9];
dout[32] = din[12] ^ din[ 8];
dout[63] = din[11] ^ din[ 7];
dout[62] = din[10] ^ din[ 6];
dout[61] = din[ 9] ^ din[ 5];
dout[60] = din[ 8] ^ din[ 4];
dout[59] = din[ 7] ^ din[ 3];
dout[58] = din[ 6] ^ din[ 2];
dout[57] = din[ 5] ^ din[ 1];
dout[56] = din[ 4] ^ din[ 0];
dout[55] = din[ 3] ^ din[14] ^ din[13];
dout[54] = din[ 2] ^ din[13] ^ din[12];
dout[53] = din[ 1] ^ din[12] ^ din[11];
dout[52] = din[ 0] ^ din[11] ^ din[10];
dout[51] = din[14] ^ din[10] ^ din[13] ^ din[ 9];
dout[50] = din[13] ^ din[ 9] ^ din[12] ^ din[ 8];
dout[49] = din[12] ^ din[ 8] ^ din[11] ^ din[ 7];
dout[48] = din[11] ^ din[ 7] ^ din[10] ^ din[ 6];
pn15 = dout;
end
endfunction
// pn23 function
assign dac_pn7_data_i_s = ~dac_pn7_data;
assign dac_pn15_data_i_s = ~dac_pn15_data;
function [63:0] pn23;
input [63:0] din;
reg [63:0] dout;
begin
dout[63] = din[23] ^ din[18];
dout[62] = din[22] ^ din[17];
dout[61] = din[21] ^ din[16];
dout[60] = din[20] ^ din[15];
dout[59] = din[19] ^ din[14];
dout[58] = din[18] ^ din[13];
dout[57] = din[17] ^ din[12];
dout[56] = din[16] ^ din[11];
dout[55] = din[15] ^ din[10];
dout[54] = din[14] ^ din[ 9];
dout[53] = din[13] ^ din[ 8];
dout[52] = din[12] ^ din[ 7];
dout[51] = din[11] ^ din[ 6];
dout[50] = din[10] ^ din[ 5];
dout[49] = din[ 9] ^ din[ 4];
dout[48] = din[ 8] ^ din[ 3];
dout[47] = din[ 7] ^ din[ 2];
dout[46] = din[ 6] ^ din[ 1];
dout[45] = din[ 5] ^ din[ 0];
dout[44] = din[ 4] ^ din[23] ^ din[18];
dout[43] = din[ 3] ^ din[22] ^ din[17];
dout[42] = din[ 2] ^ din[21] ^ din[16];
dout[41] = din[ 1] ^ din[20] ^ din[15];
dout[40] = din[ 0] ^ din[19] ^ din[14];
dout[39] = din[23] ^ din[13];
dout[38] = din[22] ^ din[12];
dout[37] = din[21] ^ din[11];
dout[36] = din[20] ^ din[10];
dout[35] = din[19] ^ din[ 9];
dout[34] = din[18] ^ din[ 8];
dout[33] = din[17] ^ din[ 7];
dout[32] = din[16] ^ din[ 6];
dout[31] = din[15] ^ din[ 5];
dout[30] = din[14] ^ din[ 4];
dout[29] = din[13] ^ din[ 3];
dout[28] = din[12] ^ din[ 2];
dout[27] = din[11] ^ din[ 1];
dout[26] = din[10] ^ din[ 0];
dout[25] = din[ 9] ^ din[23] ^ din[18];
dout[24] = din[ 8] ^ din[22] ^ din[17];
dout[23] = din[ 7] ^ din[21] ^ din[16];
dout[22] = din[ 6] ^ din[20] ^ din[15];
dout[21] = din[ 5] ^ din[19] ^ din[14];
dout[20] = din[ 4] ^ din[18] ^ din[13];
dout[19] = din[ 3] ^ din[17] ^ din[12];
dout[18] = din[ 2] ^ din[16] ^ din[11];
dout[17] = din[ 1] ^ din[15] ^ din[10];
dout[16] = din[ 0] ^ din[14] ^ din[ 9];
dout[15] = din[23] ^ din[13] ^ din[18] ^ din[ 8];
dout[14] = din[22] ^ din[12] ^ din[17] ^ din[ 7];
dout[13] = din[21] ^ din[11] ^ din[16] ^ din[ 6];
dout[12] = din[20] ^ din[10] ^ din[15] ^ din[ 5];
dout[11] = din[19] ^ din[ 9] ^ din[14] ^ din[ 4];
dout[10] = din[18] ^ din[ 8] ^ din[13] ^ din[ 3];
dout[ 9] = din[17] ^ din[ 7] ^ din[12] ^ din[ 2];
dout[ 8] = din[16] ^ din[ 6] ^ din[11] ^ din[ 1];
dout[ 7] = din[15] ^ din[ 5] ^ din[10] ^ din[ 0];
dout[ 6] = din[14] ^ din[ 4] ^ din[ 9] ^ din[23] ^ din[18];
dout[ 5] = din[13] ^ din[ 3] ^ din[ 8] ^ din[22] ^ din[17];
dout[ 4] = din[12] ^ din[ 2] ^ din[ 7] ^ din[21] ^ din[16];
dout[ 3] = din[11] ^ din[ 1] ^ din[ 6] ^ din[20] ^ din[15];
dout[ 2] = din[10] ^ din[ 0] ^ din[ 5] ^ din[19] ^ din[14];
dout[ 1] = din[ 9] ^ din[23] ^ din[ 4] ^ din[13];
dout[ 0] = din[ 8] ^ din[22] ^ din[ 3] ^ din[12];
pn23 = dout;
end
endfunction
// pn31 function
function [63:0] pn31;
input [63:0] din;
reg [63:0] dout;
begin
dout[63] = din[31] ^ din[28];
dout[62] = din[30] ^ din[27];
dout[61] = din[29] ^ din[26];
dout[60] = din[28] ^ din[25];
dout[59] = din[27] ^ din[24];
dout[58] = din[26] ^ din[23];
dout[57] = din[25] ^ din[22];
dout[56] = din[24] ^ din[21];
dout[55] = din[23] ^ din[20];
dout[54] = din[22] ^ din[19];
dout[53] = din[21] ^ din[18];
dout[52] = din[20] ^ din[17];
dout[51] = din[19] ^ din[16];
dout[50] = din[18] ^ din[15];
dout[49] = din[17] ^ din[14];
dout[48] = din[16] ^ din[13];
dout[47] = din[15] ^ din[12];
dout[46] = din[14] ^ din[11];
dout[45] = din[13] ^ din[10];
dout[44] = din[12] ^ din[ 9];
dout[43] = din[11] ^ din[ 8];
dout[42] = din[10] ^ din[ 7];
dout[41] = din[ 9] ^ din[ 6];
dout[40] = din[ 8] ^ din[ 5];
dout[39] = din[ 7] ^ din[ 4];
dout[38] = din[ 6] ^ din[ 3];
dout[37] = din[ 5] ^ din[ 2];
dout[36] = din[ 4] ^ din[ 1];
dout[35] = din[ 3] ^ din[ 0];
dout[34] = din[ 2] ^ din[31] ^ din[28];
dout[33] = din[ 1] ^ din[30] ^ din[27];
dout[32] = din[ 0] ^ din[29] ^ din[26];
dout[31] = din[31] ^ din[25];
dout[30] = din[30] ^ din[24];
dout[29] = din[29] ^ din[23];
dout[28] = din[28] ^ din[22];
dout[27] = din[27] ^ din[21];
dout[26] = din[26] ^ din[20];
dout[25] = din[25] ^ din[19];
dout[24] = din[24] ^ din[18];
dout[23] = din[23] ^ din[17];
dout[22] = din[22] ^ din[16];
dout[21] = din[21] ^ din[15];
dout[20] = din[20] ^ din[14];
dout[19] = din[19] ^ din[13];
dout[18] = din[18] ^ din[12];
dout[17] = din[17] ^ din[11];
dout[16] = din[16] ^ din[10];
dout[15] = din[15] ^ din[ 9];
dout[14] = din[14] ^ din[ 8];
dout[13] = din[13] ^ din[ 7];
dout[12] = din[12] ^ din[ 6];
dout[11] = din[11] ^ din[ 5];
dout[10] = din[10] ^ din[ 4];
dout[ 9] = din[ 9] ^ din[ 3];
dout[ 8] = din[ 8] ^ din[ 2];
dout[ 7] = din[ 7] ^ din[ 1];
dout[ 6] = din[ 6] ^ din[ 0];
dout[ 5] = din[ 5] ^ din[31] ^ din[28];
dout[ 4] = din[ 4] ^ din[30] ^ din[27];
dout[ 3] = din[ 3] ^ din[29] ^ din[26];
dout[ 2] = din[ 2] ^ din[28] ^ din[25];
dout[ 1] = din[ 1] ^ din[27] ^ din[24];
dout[ 0] = din[ 0] ^ din[26] ^ din[23];
pn31 = dout;
end
endfunction
assign dac_pn7_data_s = dac_pn7_data;
assign dac_pn15_data_s = dac_pn15_data;
// dac data select
always @(posedge dac_clk) begin
dac_enable <= (dac_data_sel_s == 4'h2) ? 1'b1 : 1'b0;
case (dac_data_sel_s)
4'h7: dac_data <= dac_pn31_data;
4'h6: dac_data <= dac_pn23_data;
4'h5: dac_data <= dac_pn15_data;
4'h4: dac_data <= dac_pn7_data;
4'h7: dac_data <= dac_pn15_data_s;
4'h6: dac_data <= dac_pn7_data_s;
4'h5: dac_data <= dac_pn15_data_i_s;
4'h4: dac_data <= dac_pn7_data_i_s;
4'h3: dac_data <= 64'd0;
4'h2: dac_data <= dma_data;
4'h1: dac_data <= { dac_pat_data_2_s, dac_pat_data_1_s,
@ -453,13 +311,9 @@ module axi_ad9144_channel (
if (dac_data_sync == 1'b1) begin
dac_pn7_data <= {64{1'd1}};
dac_pn15_data <= {64{1'd1}};
dac_pn23_data <= {64{1'd1}};
dac_pn31_data <= {64{1'd1}};
end else begin
dac_pn7_data <= pn7(dac_pn7_data);
dac_pn15_data <= pn15(dac_pn15_data);
dac_pn23_data <= pn23(dac_pn23_data);
dac_pn31_data <= pn31(dac_pn31_data);
dac_pn7_data <= pn7(dac_pn7_data[55:48]);
dac_pn15_data <= pn15(dac_pn15_data[63:48]);
end
end
@ -556,7 +410,7 @@ module axi_ad9144_channel (
// single channel processor
up_dac_channel #(.DAC_CHANNEL_ID(CHANNEL_ID)) i_up_dac_channel (
up_dac_channel #(.CHANNEL_ID(CHANNEL_ID)) i_up_dac_channel (
.dac_clk (dac_clk),
.dac_rst (dac_rst),
.dac_dds_scale_1 (dac_dds_scale_1_s),
@ -568,6 +422,7 @@ module axi_ad9144_channel (
.dac_pat_data_1 (dac_pat_data_1_s),
.dac_pat_data_2 (dac_pat_data_2_s),
.dac_data_sel (dac_data_sel_s),
.dac_iq_mode (),
.dac_iqcor_enb (),
.dac_iqcor_coeff_1 (),
.dac_iqcor_coeff_2 (),
@ -600,3 +455,7 @@ endmodule
// ***************************************************************************
// ***************************************************************************

3
library/axi_ad9144/axi_ad9144_core.v
View File

@ -287,6 +287,7 @@ module axi_ad9144_core (
.dac_rst (dac_rst),
.dac_sync (dac_sync_s),
.dac_frame (),
.dac_clksel (),
.dac_par_type (),
.dac_par_enb (),
.dac_r1_mode (),
@ -300,7 +301,7 @@ module axi_ad9144_core (
.up_drp_wr (),
.up_drp_addr (),
.up_drp_wdata (),
.up_drp_rdata (16'd0),
.up_drp_rdata (32'd0),
.up_drp_ready (1'd0),
.up_drp_locked (1'd1),
.up_usr_chanmax (),

66
library/axi_ad9144/axi_ad9144_hw.tcl
View File

@ -15,9 +15,7 @@ set_module_property ELABORATION_CALLBACK p_axi_ad9144
add_fileset quartus_synth QUARTUS_SYNTH "" "Quartus Synthesis"
set_fileset_property quartus_synth TOP_LEVEL axi_ad9144
add_fileset_file ad_rst.v VERILOG PATH $ad_hdl_dir/library/common/ad_rst.v
add_fileset_file MULT_MACRO.v VERILOG PATH $ad_hdl_dir/library/common/altera/MULT_MACRO.v
add_fileset_file ad_mul.v VERILOG PATH $ad_hdl_dir/library/common/ad_mul.v
add_fileset_file ad_mul.v VERILOG PATH $ad_hdl_dir/library/altera/common/ad_mul.v
add_fileset_file ad_dds_sine.v VERILOG PATH $ad_hdl_dir/library/common/ad_dds_sine.v
add_fileset_file ad_dds_1.v VERILOG PATH $ad_hdl_dir/library/common/ad_dds_1.v
add_fileset_file ad_dds.v VERILOG PATH $ad_hdl_dir/library/common/ad_dds.v
@ -50,6 +48,13 @@ set_parameter_property QUAD_OR_DUAL_N TYPE INTEGER
set_parameter_property QUAD_OR_DUAL_N UNITS None
set_parameter_property QUAD_OR_DUAL_N HDL_PARAMETER true
add_parameter DEVICE_TYPE INTEGER 0
set_parameter_property DEVICE_TYPE DEFAULT_VALUE 1
set_parameter_property DEVICE_TYPE DISPLAY_NAME DEVICE_TYPE
set_parameter_property DEVICE_TYPE TYPE INTEGER
set_parameter_property DEVICE_TYPE UNITS None
set_parameter_property DEVICE_TYPE HDL_PARAMETER true
# axi4 slave
add_interface s_axi_clock clock end
@ -85,24 +90,36 @@ add_interface_port s_axi s_axi_rready rready Input 1
# transceiver interface
ad_alt_intf clock tx_clk input 1
ad_alt_intf signal tx_data output 128*(QUAD_OR_DUAL_N+1) data
add_interface if_tx_data avalon_streaming source
add_interface_port if_tx_data tx_data data output 128*(QUAD_OR_DUAL_N+1)
add_interface_port if_tx_data tx_valid valid output 1
add_interface_port if_tx_data tx_ready ready input 1
set_interface_property if_tx_data associatedClock if_tx_clk
set_interface_property if_tx_data dataBitsPerSymbol 128
# dma interface
ad_alt_intf clock dac_clk output 1
add_interface fifo_ch_0_out conduit end
add_interface_port fifo_ch_0_out dac_enable_0 enable Output 1
add_interface_port fifo_ch_0_out dac_valid_0 valid Output 1
add_interface_port fifo_ch_0_out dac_data_0 data Input 64
add_interface dac_ch_0 conduit end
add_interface_port dac_ch_0 dac_enable_0 enable Output 1
add_interface_port dac_ch_0 dac_valid_0 valid Output 1
add_interface_port dac_ch_0 dac_ddata_0 data Input 64
add_interface fifo_ch_1_out conduit end
add_interface_port fifo_ch_1_out dac_enable_1 enable Output 1
add_interface_port fifo_ch_1_out dac_valid_1 valid Output 1
add_interface_port fifo_ch_1_out dac_data_1 data Input 64
set_interface_property dac_ch_0 associatedClock if_tx_clk
set_interface_property dac_ch_0 associatedReset none
ad_alt_intf signal dac_dovf input 1
ad_alt_intf signal dac_dunf input 1
add_interface dac_ch_1 conduit end
add_interface_port dac_ch_1 dac_enable_1 enable Output 1
add_interface_port dac_ch_1 dac_valid_1 valid Output 1
add_interface_port dac_ch_1 dac_ddata_1 data Input 64
set_interface_property dac_ch_1 associatedClock if_tx_clk
set_interface_property dac_ch_1 associatedReset none
ad_alt_intf signal dac_dovf input 1 ovf
ad_alt_intf signal dac_dunf input 1 unf
proc p_axi_ad9144 {} {
@ -110,15 +127,20 @@ proc p_axi_ad9144 {} {
if {[get_parameter_value QUAD_OR_DUAL_N] == 1} {
add_interface fifo_ch_2_out conduit end
add_interface_port fifo_ch_2_out dac_enable_2 enable Output 1
add_interface_port fifo_ch_2_out dac_valid_2 valid Output 1
add_interface_port fifo_ch_2_out dac_data_2 data Input 64
add_interface dac_ch_2 conduit end
add_interface_port dac_ch_2 dac_enable_2 enable Output 1
add_interface_port dac_ch_2 dac_valid_2 valid Output 1
add_interface_port dac_ch_2 dac_ddata_2 data Input 64
add_interface fifo_ch_3_out conduit end
add_interface_port fifo_ch_3_out dac_enable_3 enable Output 1
add_interface_port fifo_ch_3_out dac_valid_3 valid Output 1
add_interface_port fifo_ch_3_out dac_data_3 data Input 64
set_interface_property dac_ch_2 associatedClock if_tx_clk
set_interface_property dac_ch_2 associatedReset none
add_interface dac_ch_3 conduit end
add_interface_port dac_ch_3 dac_enable_3 enable Output 1
add_interface_port dac_ch_3 dac_valid_3 valid Output 1
add_interface_port dac_ch_3 dac_ddata_3 data Input 64
set_interface_property dac_ch_3 associatedClock if_tx_clk
set_interface_property dac_ch_3 associatedReset none
}
}

72
library/axi_ad9144/axi_ad9144_if.v
View File

@ -34,10 +34,6 @@
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// This is the dac physical interface (drives samples from the low speed clock to the
// dac clock domain.
`timescale 1ns/100ps
@ -70,6 +66,10 @@ module axi_ad9144_if (
dac_data_3_2,
dac_data_3_3);
// altera (0x1) or xilinx (0x0)
parameter DEVICE_TYPE = 0;
// jesd interface
// tx_clk is (line-rate/40)
@ -109,38 +109,38 @@ module axi_ad9144_if (
if (dac_rst == 1'b1) begin
tx_data <= 256'd0;
end else begin
tx_data[255:248] <= dac_data_3_3[ 7: 0];
tx_data[247:240] <= dac_data_3_2[ 7: 0];
tx_data[239:232] <= dac_data_3_1[ 7: 0];
tx_data[231:224] <= dac_data_3_0[ 7: 0];
tx_data[223:216] <= dac_data_3_3[15: 8];
tx_data[215:208] <= dac_data_3_2[15: 8];
tx_data[207:200] <= dac_data_3_1[15: 8];
tx_data[199:192] <= dac_data_3_0[15: 8];
tx_data[191:184] <= dac_data_2_3[ 7: 0];
tx_data[183:176] <= dac_data_2_2[ 7: 0];
tx_data[175:168] <= dac_data_2_1[ 7: 0];
tx_data[167:160] <= dac_data_2_0[ 7: 0];
tx_data[159:152] <= dac_data_2_3[15: 8];
tx_data[151:144] <= dac_data_2_2[15: 8];
tx_data[143:136] <= dac_data_2_1[15: 8];
tx_data[135:128] <= dac_data_2_0[15: 8];
tx_data[127:120] <= dac_data_1_3[ 7: 0];
tx_data[119:112] <= dac_data_1_2[ 7: 0];
tx_data[111:104] <= dac_data_1_1[ 7: 0];
tx_data[103: 96] <= dac_data_1_0[ 7: 0];
tx_data[ 95: 88] <= dac_data_1_3[15: 8];
tx_data[ 87: 80] <= dac_data_1_2[15: 8];
tx_data[ 79: 72] <= dac_data_1_1[15: 8];
tx_data[ 71: 64] <= dac_data_1_0[15: 8];
tx_data[ 63: 56] <= dac_data_0_3[ 7: 0];
tx_data[ 55: 48] <= dac_data_0_2[ 7: 0];
tx_data[ 47: 40] <= dac_data_0_1[ 7: 0];
tx_data[ 39: 32] <= dac_data_0_0[ 7: 0];
tx_data[ 31: 24] <= dac_data_0_3[15: 8];
tx_data[ 23: 16] <= dac_data_0_2[15: 8];
tx_data[ 15: 8] <= dac_data_0_1[15: 8];
tx_data[ 7: 0] <= dac_data_0_0[15: 8];
tx_data[255:248] <= (DEVICE_TYPE == 1) ? dac_data_3_0[ 7: 0] : dac_data_3_3[ 7: 0];
tx_data[247:240] <= (DEVICE_TYPE == 1) ? dac_data_3_1[ 7: 0] : dac_data_3_2[ 7: 0];
tx_data[239:232] <= (DEVICE_TYPE == 1) ? dac_data_3_2[ 7: 0] : dac_data_3_1[ 7: 0];
tx_data[231:224] <= (DEVICE_TYPE == 1) ? dac_data_3_3[ 7: 0] : dac_data_3_0[ 7: 0];
tx_data[223:216] <= (DEVICE_TYPE == 1) ? dac_data_3_0[15: 8] : dac_data_3_3[15: 8];
tx_data[215:208] <= (DEVICE_TYPE == 1) ? dac_data_3_1[15: 8] : dac_data_3_2[15: 8];
tx_data[207:200] <= (DEVICE_TYPE == 1) ? dac_data_3_2[15: 8] : dac_data_3_1[15: 8];
tx_data[199:192] <= (DEVICE_TYPE == 1) ? dac_data_3_3[15: 8] : dac_data_3_0[15: 8];
tx_data[191:184] <= (DEVICE_TYPE == 1) ? dac_data_2_0[ 7: 0] : dac_data_2_3[ 7: 0];
tx_data[183:176] <= (DEVICE_TYPE == 1) ? dac_data_2_1[ 7: 0] : dac_data_2_2[ 7: 0];
tx_data[175:168] <= (DEVICE_TYPE == 1) ? dac_data_2_2[ 7: 0] : dac_data_2_1[ 7: 0];
tx_data[167:160] <= (DEVICE_TYPE == 1) ? dac_data_2_3[ 7: 0] : dac_data_2_0[ 7: 0];
tx_data[159:152] <= (DEVICE_TYPE == 1) ? dac_data_2_0[15: 8] : dac_data_2_3[15: 8];
tx_data[151:144] <= (DEVICE_TYPE == 1) ? dac_data_2_1[15: 8] : dac_data_2_2[15: 8];
tx_data[143:136] <= (DEVICE_TYPE == 1) ? dac_data_2_2[15: 8] : dac_data_2_1[15: 8];
tx_data[135:128] <= (DEVICE_TYPE == 1) ? dac_data_2_3[15: 8] : dac_data_2_0[15: 8];
tx_data[127:120] <= (DEVICE_TYPE == 1) ? dac_data_1_0[ 7: 0] : dac_data_1_3[ 7: 0];
tx_data[119:112] <= (DEVICE_TYPE == 1) ? dac_data_1_1[ 7: 0] : dac_data_1_2[ 7: 0];
tx_data[111:104] <= (DEVICE_TYPE == 1) ? dac_data_1_2[ 7: 0] : dac_data_1_1[ 7: 0];
tx_data[103: 96] <= (DEVICE_TYPE == 1) ? dac_data_1_3[ 7: 0] : dac_data_1_0[ 7: 0];
tx_data[ 95: 88] <= (DEVICE_TYPE == 1) ? dac_data_1_0[15: 8] : dac_data_1_3[15: 8];
tx_data[ 87: 80] <= (DEVICE_TYPE == 1) ? dac_data_1_1[15: 8] : dac_data_1_2[15: 8];
tx_data[ 79: 72] <= (DEVICE_TYPE == 1) ? dac_data_1_2[15: 8] : dac_data_1_1[15: 8];
tx_data[ 71: 64] <= (DEVICE_TYPE == 1) ? dac_data_1_3[15: 8] : dac_data_1_0[15: 8];
tx_data[ 63: 56] <= (DEVICE_TYPE == 1) ? dac_data_0_0[ 7: 0] : dac_data_0_3[ 7: 0];
tx_data[ 55: 48] <= (DEVICE_TYPE == 1) ? dac_data_0_1[ 7: 0] : dac_data_0_2[ 7: 0];
tx_data[ 47: 40] <= (DEVICE_TYPE == 1) ? dac_data_0_2[ 7: 0] : dac_data_0_1[ 7: 0];
tx_data[ 39: 32] <= (DEVICE_TYPE == 1) ? dac_data_0_3[ 7: 0] : dac_data_0_0[ 7: 0];
tx_data[ 31: 24] <= (DEVICE_TYPE == 1) ? dac_data_0_0[15: 8] : dac_data_0_3[15: 8];
tx_data[ 23: 16] <= (DEVICE_TYPE == 1) ? dac_data_0_1[15: 8] : dac_data_0_2[15: 8];
tx_data[ 15: 8] <= (DEVICE_TYPE == 1) ? dac_data_0_2[15: 8] : dac_data_0_1[15: 8];
tx_data[ 7: 0] <= (DEVICE_TYPE == 1) ? dac_data_0_3[15: 8] : dac_data_0_0[15: 8];
end
end

3
library/axi_ad9144/axi_ad9144_ip.tcl
View File

@ -6,7 +6,7 @@ source $ad_hdl_dir/library/scripts/adi_ip.tcl
adi_ip_create axi_ad9144
adi_ip_files axi_ad9144 [list \
"$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc" \
"$ad_hdl_dir/library/common/ad_mul.v" \
"$ad_hdl_dir/library/xilinx/common/ad_mul.v" \
"$ad_hdl_dir/library/common/ad_dds_sine.v" \
"$ad_hdl_dir/library/common/ad_dds_1.v" \
"$ad_hdl_dir/library/common/ad_dds.v" \
@ -29,6 +29,7 @@ adi_ip_constraints axi_ad9144 [list \
set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *tx_ready* -of_objects [ipx::current_core]]
ipx::save_core [ipx::current_core]

26
library/axi_ad9152/Makefile
View File

@ -5,25 +5,25 @@
####################################################################################
####################################################################################
M_DEPS := axi_ad9152_ip.tcl
M_DEPS += ../scripts/adi_env.tcl
M_DEPS += ../scripts/adi_ip.tcl
M_DEPS += ../common/ad_axi_ip_constr.xdc
M_DEPS += ../common/ad_mul.v
M_DEPS += ../common/ad_dds_sine.v
M_DEPS += ../common/ad_dds_1.v
M_DEPS += ../common/ad_dds.v
M_DEPS += ../common/ad_dds_1.v
M_DEPS += ../common/ad_dds_sine.v
M_DEPS += ../common/ad_rst.v
M_DEPS += ../common/up_axi.v
M_DEPS += ../common/up_clock_mon.v
M_DEPS += ../common/up_dac_channel.v
M_DEPS += ../common/up_dac_common.v
M_DEPS += ../common/up_xfer_cntrl.v
M_DEPS += ../common/up_xfer_status.v
M_DEPS += ../common/up_clock_mon.v
M_DEPS += ../common/up_dac_common.v
M_DEPS += ../common/up_dac_channel.v
M_DEPS += ../scripts/adi_env.tcl
M_DEPS += ../scripts/adi_ip.tcl
M_DEPS += ../xilinx/common/ad_mul.v
M_DEPS += axi_ad9152.v
M_DEPS += axi_ad9152_channel.v
M_DEPS += axi_ad9152_core.v
M_DEPS += axi_ad9152_if.v
M_DEPS += axi_ad9152.v
M_DEPS += axi_ad9152_ip.tcl
M_VIVADO := vivado -mode batch -source
@ -34,6 +34,10 @@ M_FLIST += *.log
M_FLIST += component.xml
M_FLIST += *.jou
M_FLIST += xgui
M_FLIST += *.ip_user_files
M_FLIST += *.srcs
M_FLIST += *.hw
M_FLIST += *.sim
M_FLIST += .Xil
@ -50,7 +54,7 @@ clean-all:
axi_ad9152.xpr: $(M_DEPS)
rm -rf $(M_FLIST)
-rm -rf $(M_FLIST)
$(M_VIVADO) axi_ad9152_ip.tcl >> axi_ad9152_ip.log 2>&1
####################################################################################

8
library/axi_ad9152/axi_ad9152.v
View File

@ -46,6 +46,8 @@ module axi_ad9152 (
tx_clk,
tx_data,
tx_valid,
tx_ready,
// dma interface
@ -87,12 +89,15 @@ module axi_ad9152 (
parameter ID = 0;
parameter DAC_DATAPATH_DISABLE = 0;
parameter DEVICE_TYPE = 0;
// jesd interface
// tx_clk is (line-rate/40)
input tx_clk;
output [127:0] tx_data;
output tx_valid;
input tx_ready;
// dma interface
@ -159,10 +164,11 @@ module axi_ad9152 (
assign up_clk = s_axi_aclk;
assign up_rstn = s_axi_aresetn;
assign tx_valid = 1'b1;
// device interface
axi_ad9152_if i_if (
axi_ad9152_if #(.DEVICE_TYPE (DEVICE_TYPE)) i_if (
.tx_clk (tx_clk),
.tx_data (tx_data),
.dac_clk (dac_clk),

441
library/axi_ad9152/axi_ad9152_channel.v
View File

@ -34,8 +34,6 @@
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
@ -104,8 +102,6 @@ module axi_ad9152_channel (
reg [63:0] dac_data = 'd0;
reg [63:0] dac_pn7_data = 'd0;
reg [63:0] dac_pn15_data = 'd0;
reg [63:0] dac_pn23_data = 'd0;
reg [63:0] dac_pn31_data = 'd0;
reg [15:0] dac_dds_phase_0_0 = 'd0;
reg [15:0] dac_dds_phase_0_1 = 'd0;
reg [15:0] dac_dds_phase_1_0 = 'd0;
@ -133,312 +129,174 @@ module axi_ad9152_channel (
wire [15:0] dac_pat_data_1_s;
wire [15:0] dac_pat_data_2_s;
wire [ 3:0] dac_data_sel_s;
wire [63:0] dac_pn7_data_i_s;
wire [63:0] dac_pn15_data_i_s;
wire [63:0] dac_pn7_data_s;
wire [63:0] dac_pn15_data_s;
// pn7 function
// PN7 function
function [63:0] pn7;
input [63:0] din;
input [7:0] din;
reg [63:0] dout;
begin
dout[63] = din[ 7] ^ din[ 6];
dout[62] = din[ 6] ^ din[ 5];
dout[61] = din[ 5] ^ din[ 4];
dout[60] = din[ 4] ^ din[ 3];
dout[59] = din[ 3] ^ din[ 2];
dout[58] = din[ 2] ^ din[ 1];
dout[57] = din[ 1] ^ din[ 0];
dout[56] = din[ 0] ^ din[ 7] ^ din[ 6];
dout[55] = din[ 7] ^ din[ 5];
dout[54] = din[ 6] ^ din[ 4];
dout[53] = din[ 5] ^ din[ 3];
dout[52] = din[ 4] ^ din[ 2];
dout[51] = din[ 3] ^ din[ 1];
dout[50] = din[ 2] ^ din[ 0];
dout[49] = din[ 1] ^ din[ 7] ^ din[ 6];
dout[48] = din[ 0] ^ din[ 6] ^ din[ 5];
dout[47] = din[ 7] ^ din[ 5] ^ din[ 6] ^ din[ 4];
dout[46] = din[ 6] ^ din[ 4] ^ din[ 5] ^ din[ 3];
dout[45] = din[ 5] ^ din[ 3] ^ din[ 4] ^ din[ 2];
dout[44] = din[ 4] ^ din[ 2] ^ din[ 3] ^ din[ 1];
dout[43] = din[ 3] ^ din[ 1] ^ din[ 2] ^ din[ 0];
dout[42] = din[ 2] ^ din[ 0] ^ din[ 1] ^ din[ 7] ^ din[ 6];
dout[41] = din[ 1] ^ din[ 7] ^ din[ 0] ^ din[ 5];
dout[40] = din[ 0] ^ din[ 7] ^ din[ 4];
dout[39] = din[ 7] ^ din[ 3];
dout[38] = din[ 6] ^ din[ 2];
dout[37] = din[ 5] ^ din[ 1];
dout[36] = din[ 4] ^ din[ 0];
dout[35] = din[ 3] ^ din[ 7] ^ din[ 6];
dout[34] = din[ 2] ^ din[ 6] ^ din[ 5];
dout[33] = din[ 1] ^ din[ 5] ^ din[ 4];
dout[32] = din[ 0] ^ din[ 4] ^ din[ 3];
dout[31] = din[ 7] ^ din[ 3] ^ din[ 6] ^ din[ 2];
dout[30] = din[ 6] ^ din[ 2] ^ din[ 5] ^ din[ 1];
dout[29] = din[ 5] ^ din[ 1] ^ din[ 4] ^ din[ 0];
dout[28] = din[ 4] ^ din[ 0] ^ din[ 3] ^ din[ 7] ^ din[ 6];
dout[27] = din[ 3] ^ din[ 7] ^ din[ 2] ^ din[ 5];
dout[26] = din[ 2] ^ din[ 6] ^ din[ 1] ^ din[ 4];
dout[25] = din[ 1] ^ din[ 5] ^ din[ 0] ^ din[ 3];
dout[24] = din[ 0] ^ din[ 4] ^ din[ 7] ^ din[ 6] ^ din[ 2];
dout[23] = din[ 7] ^ din[ 3] ^ din[ 5] ^ din[ 1];
dout[22] = din[ 6] ^ din[ 2] ^ din[ 4] ^ din[ 0];
dout[21] = din[ 5] ^ din[ 1] ^ din[ 3] ^ din[ 7] ^ din[ 6];
dout[20] = din[ 4] ^ din[ 0] ^ din[ 6] ^ din[ 2] ^ din[ 5];
dout[19] = din[ 3] ^ din[ 7] ^ din[ 5] ^ din[ 6] ^ din[ 1] ^ din[ 4];
dout[18] = din[ 2] ^ din[ 6] ^ din[ 4] ^ din[ 5] ^ din[ 0] ^ din[ 3];
dout[17] = din[ 1] ^ din[ 5] ^ din[ 3] ^ din[ 4] ^ din[ 7] ^ din[ 6] ^ din[ 2];
dout[16] = din[ 0] ^ din[ 4] ^ din[ 6] ^ din[ 2] ^ din[ 3] ^ din[ 5] ^ din[ 1];
dout[15] = din[ 7] ^ din[ 3] ^ din[ 5] ^ din[ 1] ^ din[ 6] ^ din[ 2] ^ din[ 4] ^ din[ 0];
dout[14] = din[ 2] ^ din[ 4] ^ din[ 0] ^ din[ 5] ^ din[ 1] ^ din[ 3] ^ din[ 7];
dout[13] = din[ 1] ^ din[ 3] ^ din[ 7] ^ din[ 4] ^ din[ 0] ^ din[ 2];
dout[12] = din[ 0] ^ din[ 2] ^ din[ 3] ^ din[ 7] ^ din[ 1];
dout[11] = din[ 7] ^ din[ 1] ^ din[ 2] ^ din[ 0];
dout[10] = din[ 0] ^ din[ 1] ^ din[ 7];
dout[ 9] = din[ 7] ^ din[ 0];
dout[ 8] = din[ 7];
dout[ 7] = din[ 6];
dout[ 6] = din[ 5];
dout[ 5] = din[ 4];
dout[ 4] = din[ 3];
dout[ 3] = din[ 2];
dout[ 2] = din[ 1];
dout[ 1] = din[ 0];
dout[ 0] = din[ 7] ^ din[ 6];
dout[15] = din[ 6] ^ din[ 5];
dout[14] = din[ 5] ^ din[ 4];
dout[13] = din[ 4] ^ din[ 3];
dout[12] = din[ 3] ^ din[ 2];
dout[11] = din[ 2] ^ din[ 1];
dout[10] = din[ 1] ^ din[ 0];
dout[ 9] = din[ 0] ^ din[ 6] ^ din[ 5];
dout[ 8] = din[ 6] ^ din[ 4];
dout[ 7] = din[ 5] ^ din[ 3];
dout[ 6] = din[ 4] ^ din[ 2];
dout[ 5] = din[ 3] ^ din[ 1];
dout[ 4] = din[ 2] ^ din[ 0];
dout[ 3] = din[ 1] ^ din[ 6] ^ din[ 5];
dout[ 2] = din[ 0] ^ din[ 5] ^ din[ 4];
dout[ 1] = din[ 6] ^ din[ 4] ^ din[ 5] ^ din[ 3];
dout[ 0] = din[ 5] ^ din[ 3] ^ din[ 4] ^ din[ 2];
dout[31] = din[ 4] ^ din[ 2] ^ din[ 3] ^ din[ 1];
dout[30] = din[ 3] ^ din[ 1] ^ din[ 2] ^ din[ 0];
dout[29] = din[ 2] ^ din[ 0] ^ din[ 1] ^ din[ 6] ^ din[ 5];
dout[28] = din[ 1] ^ din[ 6] ^ din[ 0] ^ din[ 4];
dout[27] = din[ 0] ^ din[ 6] ^ din[ 3];
dout[26] = din[ 6] ^ din[ 2];
dout[25] = din[ 5] ^ din[ 1];
dout[24] = din[ 4] ^ din[ 0];
dout[23] = din[ 3] ^ din[ 6] ^ din[ 5];
dout[22] = din[ 2] ^ din[ 5] ^ din[ 4];
dout[21] = din[ 1] ^ din[ 4] ^ din[ 3];
dout[20] = din[ 0] ^ din[ 3] ^ din[ 2];
dout[19] = din[ 6] ^ din[ 2] ^ din[ 5] ^ din[ 1];
dout[18] = din[ 5] ^ din[ 1] ^ din[ 4] ^ din[ 0];
dout[17] = din[ 4] ^ din[ 0] ^ din[ 3] ^ din[ 6] ^ din[ 5];
dout[16] = din[ 3] ^ din[ 6] ^ din[ 2] ^ din[ 4];
dout[47] = din[ 2] ^ din[ 5] ^ din[ 1] ^ din[ 3];
dout[46] = din[ 1] ^ din[ 4] ^ din[ 0] ^ din[ 2];
dout[45] = din[ 0] ^ din[ 3] ^ din[ 6] ^ din[ 5] ^ din[ 1];
dout[44] = din[ 6] ^ din[ 2] ^ din[ 4] ^ din[ 0];
dout[43] = din[ 1] ^ din[ 3] ^ din[ 6];
dout[42] = din[ 0] ^ din[ 5] ^ din[ 2];
dout[41] = din[ 6] ^ din[ 4] ^ din[ 5] ^ din[ 1];
dout[40] = din[ 5] ^ din[ 3] ^ din[ 4] ^ din[ 0];
dout[39] = din[ 4] ^ din[ 2] ^ din[ 3] ^ din[ 6] ^ din[ 5];
dout[38] = din[ 3] ^ din[ 5] ^ din[ 1] ^ din[ 2] ^ din[ 4];
dout[37] = din[ 2] ^ din[ 4] ^ din[ 0] ^ din[ 1] ^ din[ 3];
dout[36] = din[ 1] ^ din[ 3] ^ din[ 6] ^ din[ 0] ^ din[ 5] ^ din[ 2];
dout[35] = din[ 0] ^ din[ 2] ^ din[ 6] ^ din[ 4] ^ din[ 1];
dout[34] = din[ 6] ^ din[ 1] ^ din[ 3] ^ din[ 0];
dout[33] = din[ 0] ^ din[ 2] ^ din[ 6];
dout[32] = din[ 6] ^ din[ 1];
dout[63] = din[ 5] ^ din[ 0];
dout[62] = din[ 4] ^ din[ 6] ^ din[ 5];
dout[61] = din[ 3] ^ din[ 5] ^ din[ 4];
dout[60] = din[ 2] ^ din[ 4] ^ din[ 3];
dout[59] = din[ 1] ^ din[ 3] ^ din[ 2];
dout[58] = din[ 0] ^ din[ 2] ^ din[ 1];
dout[57] = din[ 6] ^ din[ 1] ^ din[ 5] ^ din[ 0];
dout[56] = din[ 0] ^ din[ 4] ^ din[ 6];
dout[55] = din[ 6] ^ din[ 3];
dout[54] = din[ 5] ^ din[ 2];
dout[53] = din[ 4] ^ din[ 1];
dout[52] = din[ 3] ^ din[ 0];
dout[51] = din[ 2] ^ din[ 6] ^ din[ 5];
dout[50] = din[ 1] ^ din[ 5] ^ din[ 4];
dout[49] = din[ 0] ^ din[ 4] ^ din[ 3];
dout[48] = din[ 6] ^ din[ 3] ^ din[ 5] ^ din[ 2];
pn7 = dout;
end
endfunction
// pn15 function
// PN15 function
function [63:0] pn15;
input [63:0] din;
input [15:0] din;
reg [63:0] dout;
begin
dout[63] = din[15] ^ din[14];
dout[62] = din[14] ^ din[13];
dout[61] = din[13] ^ din[12];
dout[60] = din[12] ^ din[11];
dout[59] = din[11] ^ din[10];
dout[58] = din[10] ^ din[ 9];
dout[57] = din[ 9] ^ din[ 8];
dout[56] = din[ 8] ^ din[ 7];
dout[55] = din[ 7] ^ din[ 6];
dout[54] = din[ 6] ^ din[ 5];
dout[53] = din[ 5] ^ din[ 4];
dout[52] = din[ 4] ^ din[ 3];
dout[51] = din[ 3] ^ din[ 2];
dout[50] = din[ 2] ^ din[ 1];
dout[49] = din[ 1] ^ din[ 0];
dout[48] = din[ 0] ^ din[15] ^ din[14];
dout[47] = din[15] ^ din[13];
dout[46] = din[14] ^ din[12];
dout[45] = din[13] ^ din[11];
dout[44] = din[12] ^ din[10];
dout[43] = din[11] ^ din[ 9];
dout[42] = din[10] ^ din[ 8];
dout[41] = din[ 9] ^ din[ 7];
dout[40] = din[ 8] ^ din[ 6];
dout[39] = din[ 7] ^ din[ 5];
dout[38] = din[ 6] ^ din[ 4];
dout[37] = din[ 5] ^ din[ 3];
dout[36] = din[ 4] ^ din[ 2];
dout[35] = din[ 3] ^ din[ 1];
dout[34] = din[ 2] ^ din[ 0];
dout[33] = din[ 1] ^ din[15] ^ din[14];
dout[32] = din[ 0] ^ din[14] ^ din[13];
dout[31] = din[15] ^ din[13] ^ din[14] ^ din[12];
dout[30] = din[14] ^ din[12] ^ din[13] ^ din[11];
dout[29] = din[13] ^ din[11] ^ din[12] ^ din[10];
dout[28] = din[12] ^ din[10] ^ din[11] ^ din[ 9];
dout[27] = din[11] ^ din[ 9] ^ din[10] ^ din[ 8];
dout[26] = din[10] ^ din[ 8] ^ din[ 9] ^ din[ 7];
dout[25] = din[ 9] ^ din[ 7] ^ din[ 8] ^ din[ 6];
dout[24] = din[ 8] ^ din[ 6] ^ din[ 7] ^ din[ 5];
dout[23] = din[ 7] ^ din[ 5] ^ din[ 6] ^ din[ 4];
dout[22] = din[ 6] ^ din[ 4] ^ din[ 5] ^ din[ 3];
dout[21] = din[ 5] ^ din[ 3] ^ din[ 4] ^ din[ 2];
dout[20] = din[ 4] ^ din[ 2] ^ din[ 3] ^ din[ 1];
dout[19] = din[ 3] ^ din[ 1] ^ din[ 2] ^ din[ 0];
dout[18] = din[ 2] ^ din[ 0] ^ din[ 1] ^ din[15] ^ din[14];
dout[17] = din[ 1] ^ din[15] ^ din[ 0] ^ din[13];
dout[16] = din[ 0] ^ din[15] ^ din[12];
dout[15] = din[15] ^ din[11];
dout[14] = din[14] ^ din[10];
dout[13] = din[13] ^ din[ 9];
dout[12] = din[12] ^ din[ 8];
dout[11] = din[11] ^ din[ 7];
dout[10] = din[10] ^ din[ 6];
dout[ 9] = din[ 9] ^ din[ 5];
dout[ 8] = din[ 8] ^ din[ 4];
dout[ 7] = din[ 7] ^ din[ 3];
dout[ 6] = din[ 6] ^ din[ 2];
dout[ 5] = din[ 5] ^ din[ 1];
dout[ 4] = din[ 4] ^ din[ 0];
dout[ 3] = din[ 3] ^ din[15] ^ din[14];
dout[ 2] = din[ 2] ^ din[14] ^ din[13];
dout[ 1] = din[ 1] ^ din[13] ^ din[12];
dout[ 0] = din[ 0] ^ din[12] ^ din[11];
dout[15] = din[14] ^ din[13];
dout[14] = din[13] ^ din[12];
dout[13] = din[12] ^ din[11];
dout[12] = din[11] ^ din[10];
dout[11] = din[10] ^ din[ 9];
dout[10] = din[ 9] ^ din[ 8];
dout[ 9] = din[ 8] ^ din[ 7];
dout[ 8] = din[ 7] ^ din[ 6];
dout[ 7] = din[ 6] ^ din[ 5];
dout[ 6] = din[ 5] ^ din[ 4];
dout[ 5] = din[ 4] ^ din[ 3];
dout[ 4] = din[ 3] ^ din[ 2];
dout[ 3] = din[ 2] ^ din[ 1];
dout[ 2] = din[ 1] ^ din[ 0];
dout[ 1] = din[ 0] ^ din[14] ^ din[13];
dout[ 0] = din[14] ^ din[12];
dout[31] = din[13] ^ din[11];
dout[30] = din[12] ^ din[10];
dout[29] = din[11] ^ din[ 9];
dout[28] = din[10] ^ din[ 8];
dout[27] = din[ 9] ^ din[ 7];
dout[26] = din[ 8] ^ din[ 6];
dout[25] = din[ 7] ^ din[ 5];
dout[24] = din[ 6] ^ din[ 4];
dout[23] = din[ 5] ^ din[ 3];
dout[22] = din[ 4] ^ din[ 2];
dout[21] = din[ 3] ^ din[ 1];
dout[20] = din[ 2] ^ din[ 0];
dout[19] = din[ 1] ^ din[14] ^ din[13];
dout[18] = din[ 0] ^ din[13] ^ din[12];
dout[17] = din[14] ^ din[12] ^ din[13] ^ din[11];
dout[16] = din[13] ^ din[11] ^ din[12] ^ din[10];
dout[47] = din[12] ^ din[10] ^ din[11] ^ din[ 9];
dout[46] = din[11] ^ din[ 9] ^ din[10] ^ din[ 8];
dout[45] = din[10] ^ din[ 8] ^ din[ 9] ^ din[ 7];
dout[44] = din[ 9] ^ din[ 7] ^ din[ 8] ^ din[ 6];
dout[43] = din[ 8] ^ din[ 6] ^ din[ 7] ^ din[ 5];
dout[42] = din[ 7] ^ din[ 5] ^ din[ 6] ^ din[ 4];
dout[41] = din[ 6] ^ din[ 4] ^ din[ 5] ^ din[ 3];
dout[40] = din[ 5] ^ din[ 3] ^ din[ 4] ^ din[ 2];
dout[39] = din[ 4] ^ din[ 2] ^ din[ 3] ^ din[ 1];
dout[38] = din[ 3] ^ din[ 1] ^ din[ 2] ^ din[ 0];
dout[37] = din[ 2] ^ din[ 0] ^ din[ 1] ^ din[14] ^ din[13];
dout[36] = din[ 1] ^ din[14] ^ din[ 0] ^ din[12];
dout[35] = din[ 0] ^ din[14] ^ din[11];
dout[34] = din[14] ^ din[10];
dout[33] = din[13] ^ din[ 9];
dout[32] = din[12] ^ din[ 8];
dout[63] = din[11] ^ din[ 7];
dout[62] = din[10] ^ din[ 6];
dout[61] = din[ 9] ^ din[ 5];
dout[60] = din[ 8] ^ din[ 4];
dout[59] = din[ 7] ^ din[ 3];
dout[58] = din[ 6] ^ din[ 2];
dout[57] = din[ 5] ^ din[ 1];
dout[56] = din[ 4] ^ din[ 0];
dout[55] = din[ 3] ^ din[14] ^ din[13];
dout[54] = din[ 2] ^ din[13] ^ din[12];
dout[53] = din[ 1] ^ din[12] ^ din[11];
dout[52] = din[ 0] ^ din[11] ^ din[10];
dout[51] = din[14] ^ din[10] ^ din[13] ^ din[ 9];
dout[50] = din[13] ^ din[ 9] ^ din[12] ^ din[ 8];
dout[49] = din[12] ^ din[ 8] ^ din[11] ^ din[ 7];
dout[48] = din[11] ^ din[ 7] ^ din[10] ^ din[ 6];
pn15 = dout;
end
endfunction
// pn23 function
assign dac_pn7_data_i_s = ~dac_pn7_data;
assign dac_pn15_data_i_s = ~dac_pn15_data;
function [63:0] pn23;
input [63:0] din;
reg [63:0] dout;
begin
dout[63] = din[23] ^ din[18];
dout[62] = din[22] ^ din[17];
dout[61] = din[21] ^ din[16];
dout[60] = din[20] ^ din[15];
dout[59] = din[19] ^ din[14];
dout[58] = din[18] ^ din[13];
dout[57] = din[17] ^ din[12];
dout[56] = din[16] ^ din[11];
dout[55] = din[15] ^ din[10];
dout[54] = din[14] ^ din[ 9];
dout[53] = din[13] ^ din[ 8];
dout[52] = din[12] ^ din[ 7];
dout[51] = din[11] ^ din[ 6];
dout[50] = din[10] ^ din[ 5];
dout[49] = din[ 9] ^ din[ 4];
dout[48] = din[ 8] ^ din[ 3];
dout[47] = din[ 7] ^ din[ 2];
dout[46] = din[ 6] ^ din[ 1];
dout[45] = din[ 5] ^ din[ 0];
dout[44] = din[ 4] ^ din[23] ^ din[18];
dout[43] = din[ 3] ^ din[22] ^ din[17];
dout[42] = din[ 2] ^ din[21] ^ din[16];
dout[41] = din[ 1] ^ din[20] ^ din[15];
dout[40] = din[ 0] ^ din[19] ^ din[14];
dout[39] = din[23] ^ din[13];
dout[38] = din[22] ^ din[12];
dout[37] = din[21] ^ din[11];
dout[36] = din[20] ^ din[10];
dout[35] = din[19] ^ din[ 9];
dout[34] = din[18] ^ din[ 8];
dout[33] = din[17] ^ din[ 7];
dout[32] = din[16] ^ din[ 6];
dout[31] = din[15] ^ din[ 5];
dout[30] = din[14] ^ din[ 4];
dout[29] = din[13] ^ din[ 3];
dout[28] = din[12] ^ din[ 2];
dout[27] = din[11] ^ din[ 1];
dout[26] = din[10] ^ din[ 0];
dout[25] = din[ 9] ^ din[23] ^ din[18];
dout[24] = din[ 8] ^ din[22] ^ din[17];
dout[23] = din[ 7] ^ din[21] ^ din[16];
dout[22] = din[ 6] ^ din[20] ^ din[15];
dout[21] = din[ 5] ^ din[19] ^ din[14];
dout[20] = din[ 4] ^ din[18] ^ din[13];
dout[19] = din[ 3] ^ din[17] ^ din[12];
dout[18] = din[ 2] ^ din[16] ^ din[11];
dout[17] = din[ 1] ^ din[15] ^ din[10];
dout[16] = din[ 0] ^ din[14] ^ din[ 9];
dout[15] = din[23] ^ din[13] ^ din[18] ^ din[ 8];
dout[14] = din[22] ^ din[12] ^ din[17] ^ din[ 7];
dout[13] = din[21] ^ din[11] ^ din[16] ^ din[ 6];
dout[12] = din[20] ^ din[10] ^ din[15] ^ din[ 5];
dout[11] = din[19] ^ din[ 9] ^ din[14] ^ din[ 4];
dout[10] = din[18] ^ din[ 8] ^ din[13] ^ din[ 3];
dout[ 9] = din[17] ^ din[ 7] ^ din[12] ^ din[ 2];
dout[ 8] = din[16] ^ din[ 6] ^ din[11] ^ din[ 1];
dout[ 7] = din[15] ^ din[ 5] ^ din[10] ^ din[ 0];
dout[ 6] = din[14] ^ din[ 4] ^ din[ 9] ^ din[23] ^ din[18];
dout[ 5] = din[13] ^ din[ 3] ^ din[ 8] ^ din[22] ^ din[17];
dout[ 4] = din[12] ^ din[ 2] ^ din[ 7] ^ din[21] ^ din[16];
dout[ 3] = din[11] ^ din[ 1] ^ din[ 6] ^ din[20] ^ din[15];
dout[ 2] = din[10] ^ din[ 0] ^ din[ 5] ^ din[19] ^ din[14];
dout[ 1] = din[ 9] ^ din[23] ^ din[ 4] ^ din[13];
dout[ 0] = din[ 8] ^ din[22] ^ din[ 3] ^ din[12];
pn23 = dout;
end
endfunction
// pn31 function
function [63:0] pn31;
input [63:0] din;
reg [63:0] dout;
begin
dout[63] = din[31] ^ din[28];
dout[62] = din[30] ^ din[27];
dout[61] = din[29] ^ din[26];
dout[60] = din[28] ^ din[25];
dout[59] = din[27] ^ din[24];
dout[58] = din[26] ^ din[23];
dout[57] = din[25] ^ din[22];
dout[56] = din[24] ^ din[21];
dout[55] = din[23] ^ din[20];
dout[54] = din[22] ^ din[19];
dout[53] = din[21] ^ din[18];
dout[52] = din[20] ^ din[17];
dout[51] = din[19] ^ din[16];
dout[50] = din[18] ^ din[15];
dout[49] = din[17] ^ din[14];
dout[48] = din[16] ^ din[13];
dout[47] = din[15] ^ din[12];
dout[46] = din[14] ^ din[11];
dout[45] = din[13] ^ din[10];
dout[44] = din[12] ^ din[ 9];
dout[43] = din[11] ^ din[ 8];
dout[42] = din[10] ^ din[ 7];
dout[41] = din[ 9] ^ din[ 6];
dout[40] = din[ 8] ^ din[ 5];
dout[39] = din[ 7] ^ din[ 4];
dout[38] = din[ 6] ^ din[ 3];
dout[37] = din[ 5] ^ din[ 2];
dout[36] = din[ 4] ^ din[ 1];
dout[35] = din[ 3] ^ din[ 0];
dout[34] = din[ 2] ^ din[31] ^ din[28];
dout[33] = din[ 1] ^ din[30] ^ din[27];
dout[32] = din[ 0] ^ din[29] ^ din[26];
dout[31] = din[31] ^ din[25];
dout[30] = din[30] ^ din[24];
dout[29] = din[29] ^ din[23];
dout[28] = din[28] ^ din[22];
dout[27] = din[27] ^ din[21];
dout[26] = din[26] ^ din[20];
dout[25] = din[25] ^ din[19];
dout[24] = din[24] ^ din[18];
dout[23] = din[23] ^ din[17];
dout[22] = din[22] ^ din[16];
dout[21] = din[21] ^ din[15];
dout[20] = din[20] ^ din[14];
dout[19] = din[19] ^ din[13];
dout[18] = din[18] ^ din[12];
dout[17] = din[17] ^ din[11];
dout[16] = din[16] ^ din[10];
dout[15] = din[15] ^ din[ 9];
dout[14] = din[14] ^ din[ 8];
dout[13] = din[13] ^ din[ 7];
dout[12] = din[12] ^ din[ 6];
dout[11] = din[11] ^ din[ 5];
dout[10] = din[10] ^ din[ 4];
dout[ 9] = din[ 9] ^ din[ 3];
dout[ 8] = din[ 8] ^ din[ 2];
dout[ 7] = din[ 7] ^ din[ 1];
dout[ 6] = din[ 6] ^ din[ 0];
dout[ 5] = din[ 5] ^ din[31] ^ din[28];
dout[ 4] = din[ 4] ^ din[30] ^ din[27];
dout[ 3] = din[ 3] ^ din[29] ^ din[26];
dout[ 2] = din[ 2] ^ din[28] ^ din[25];
dout[ 1] = din[ 1] ^ din[27] ^ din[24];
dout[ 0] = din[ 0] ^ din[26] ^ din[23];
pn31 = dout;
end
endfunction
assign dac_pn7_data_s = dac_pn7_data;
assign dac_pn15_data_s = dac_pn15_data;
// dac data select
always @(posedge dac_clk) begin
dac_enable <= (dac_data_sel_s == 4'h2) ? 1'b1 : 1'b0;
case (dac_data_sel_s)
4'h7: dac_data <= dac_pn31_data;
4'h6: dac_data <= dac_pn23_data;
4'h5: dac_data <= dac_pn15_data;
4'h4: dac_data <= dac_pn7_data;
4'h7: dac_data <= dac_pn15_data_s;
4'h6: dac_data <= dac_pn7_data_s;
4'h5: dac_data <= dac_pn15_data_i_s;
4'h4: dac_data <= dac_pn7_data_i_s;
4'h3: dac_data <= 64'd0;
4'h2: dac_data <= dma_data;
4'h1: dac_data <= { dac_pat_data_2_s, dac_pat_data_1_s,
@ -453,13 +311,9 @@ module axi_ad9152_channel (
if (dac_data_sync == 1'b1) begin
dac_pn7_data <= {64{1'd1}};
dac_pn15_data <= {64{1'd1}};
dac_pn23_data <= {64{1'd1}};
dac_pn31_data <= {64{1'd1}};
end else begin
dac_pn7_data <= pn7(dac_pn7_data);
dac_pn15_data <= pn15(dac_pn15_data);
dac_pn23_data <= pn23(dac_pn23_data);
dac_pn31_data <= pn31(dac_pn31_data);
dac_pn7_data <= pn7(dac_pn7_data[55:48]);
dac_pn15_data <= pn15(dac_pn15_data[63:48]);
end
end
@ -556,7 +410,7 @@ module axi_ad9152_channel (
// single channel processor
up_dac_channel #(.DAC_CHANNEL_ID(CHANNEL_ID)) i_up_dac_channel (
up_dac_channel #(.CHANNEL_ID(CHANNEL_ID)) i_up_dac_channel (
.dac_clk (dac_clk),
.dac_rst (dac_rst),
.dac_dds_scale_1 (dac_dds_scale_1_s),
@ -568,6 +422,7 @@ module axi_ad9152_channel (
.dac_pat_data_1 (dac_pat_data_1_s),
.dac_pat_data_2 (dac_pat_data_2_s),
.dac_data_sel (dac_data_sel_s),
.dac_iq_mode (),
.dac_iqcor_enb (),
.dac_iqcor_coeff_1 (),
.dac_iqcor_coeff_2 (),

3
library/axi_ad9152/axi_ad9152_core.v
View File

@ -211,6 +211,7 @@ module axi_ad9152_core (
.dac_rst (dac_rst),
.dac_sync (dac_sync_s),
.dac_frame (),
.dac_clksel (),
.dac_par_type (),
.dac_par_enb (),
.dac_r1_mode (),
@ -224,7 +225,7 @@ module axi_ad9152_core (
.up_drp_wr (),
.up_drp_addr (),
.up_drp_wdata (),
.up_drp_rdata (16'd0),
.up_drp_rdata (32'd0),
.up_drp_ready (1'd0),
.up_drp_locked (1'd1),
.up_usr_chanmax (),

40
library/axi_ad9152/axi_ad9152_hw.tcl
View File

@ -14,8 +14,7 @@ set_module_property DISPLAY_NAME axi_ad9152
add_fileset quartus_synth QUARTUS_SYNTH "" "Quartus Synthesis"
set_fileset_property quartus_synth TOP_LEVEL axi_ad9152
add_fileset_file MULT_MACRO.v VERILOG PATH $ad_hdl_dir/library/common/altera/MULT_MACRO.v
add_fileset_file ad_mul.v VERILOG PATH $ad_hdl_dir/library/common/ad_mul.v
add_fileset_file ad_mul.v VERILOG PATH $ad_hdl_dir/library/altera/common/ad_mul.v
add_fileset_file ad_dds_sine.v VERILOG PATH $ad_hdl_dir/library/common/ad_dds_sine.v
add_fileset_file ad_dds_1.v VERILOG PATH $ad_hdl_dir/library/common/ad_dds_1.v
add_fileset_file ad_dds.v VERILOG PATH $ad_hdl_dir/library/common/ad_dds.v
@ -41,6 +40,13 @@ set_parameter_property ID TYPE INTEGER
set_parameter_property ID UNITS None
set_parameter_property ID HDL_PARAMETER true
add_parameter DEVICE_TYPE INTEGER 0
set_parameter_property DEVICE_TYPE DEFAULT_VALUE 1
set_parameter_property DEVICE_TYPE DISPLAY_NAME DEVICE_TYPE
set_parameter_property DEVICE_TYPE TYPE INTEGER
set_parameter_property DEVICE_TYPE UNITS None
set_parameter_property DEVICE_TYPE HDL_PARAMETER true
# axi4 slave
add_interface s_axi_clock clock end
@ -76,21 +82,33 @@ add_interface_port s_axi s_axi_rready rready Input 1
# transceiver interface
ad_alt_intf clock tx_clk input 1
ad_alt_intf signal tx_data output 128 data
add_interface if_tx_data avalon_streaming source
add_interface_port if_tx_data tx_data data output 128
add_interface_port if_tx_data tx_valid valid output 1
add_interface_port if_tx_data tx_ready ready input 1
set_interface_property if_tx_data associatedClock if_tx_clk
set_interface_property if_tx_data dataBitsPerSymbol 128
# dma interface
ad_alt_intf clock dac_clk output 1
add_interface fifo_ch_0_out conduit end
add_interface_port fifo_ch_0_out dac_enable_0 enable Output 1
add_interface_port fifo_ch_0_out dac_valid_0 valid Output 1
add_interface_port fifo_ch_0_out dac_ddata_0 data Input 64
add_interface dac_ch_0 conduit end
add_interface_port dac_ch_0 dac_enable_0 enable Output 1
add_interface_port dac_ch_0 dac_valid_0 valid Output 1
add_interface_port dac_ch_0 dac_ddata_0 data Input 64
add_interface fifo_ch_1_out conduit end
add_interface_port fifo_ch_1_out dac_enable_1 enable Output 1
add_interface_port fifo_ch_1_out dac_valid_1 valid Output 1
add_interface_port fifo_ch_1_out dac_ddata_1 data Input 64
set_interface_property dac_ch_0 associatedClock if_tx_clk
set_interface_property dac_ch_0 associatedReset none
add_interface dac_ch_1 conduit end
add_interface_port dac_ch_1 dac_enable_1 enable Output 1
add_interface_port dac_ch_1 dac_valid_1 valid Output 1
add_interface_port dac_ch_1 dac_ddata_1 data Input 64
set_interface_property dac_ch_1 associatedClock if_tx_clk
set_interface_property dac_ch_1 associatedReset none
ad_alt_intf signal dac_dovf input 1 ovf
ad_alt_intf signal dac_dunf input 1 unf

85
library/axi_ad9152/axi_ad9152_if.v
View File

@ -41,49 +41,30 @@
`timescale 1ns/100ps
module axi_ad9152_if (
module axi_ad9152_if #(
// altera (0x1) or xilinx (0x0)
parameter DEVICE_TYPE = 0)(
// jesd interface
// tx_clk is (line-rate/40)
tx_clk,
tx_data,
input tx_clk,
output reg [127:0] tx_data,
// dac interface
dac_clk,
dac_rst,
dac_data_0_0,
dac_data_0_1,
dac_data_0_2,
dac_data_0_3,
dac_data_1_0,
dac_data_1_1,
dac_data_1_2,
dac_data_1_3);
// jesd interface
// tx_clk is (line-rate/40)
input tx_clk;
output [127:0] tx_data;
// dac interface
output dac_clk;
input dac_rst;
input [15:0] dac_data_0_0;
input [15:0] dac_data_0_1;
input [15:0] dac_data_0_2;
input [15:0] dac_data_0_3;
input [15:0] dac_data_1_0;
input [15:0] dac_data_1_1;
input [15:0] dac_data_1_2;
input [15:0] dac_data_1_3;
// internal registers
reg [127:0] tx_data = 'd0;
output dac_clk,
input dac_rst,
input [15:0] dac_data_0_0,
input [15:0] dac_data_0_1,
input [15:0] dac_data_0_2,
input [15:0] dac_data_0_3,
input [15:0] dac_data_1_0,
input [15:0] dac_data_1_1,
input [15:0] dac_data_1_2,
input [15:0] dac_data_1_3);
// reorder data for the jesd links
@ -93,22 +74,22 @@ module axi_ad9152_if (
if (dac_rst == 1'b1) begin
tx_data <= 128'd0;
end else begin
tx_data[127:120] <= dac_data_1_3[ 7: 0];
tx_data[119:112] <= dac_data_1_2[ 7: 0];
tx_data[111:104] <= dac_data_1_1[ 7: 0];
tx_data[103: 96] <= dac_data_1_0[ 7: 0];
tx_data[ 95: 88] <= dac_data_1_3[15: 8];
tx_data[ 87: 80] <= dac_data_1_2[15: 8];
tx_data[ 79: 72] <= dac_data_1_1[15: 8];
tx_data[ 71: 64] <= dac_data_1_0[15: 8];
tx_data[ 63: 56] <= dac_data_0_3[ 7: 0];
tx_data[ 55: 48] <= dac_data_0_2[ 7: 0];
tx_data[ 47: 40] <= dac_data_0_1[ 7: 0];
tx_data[ 39: 32] <= dac_data_0_0[ 7: 0];
tx_data[ 31: 24] <= dac_data_0_3[15: 8];
tx_data[ 23: 16] <= dac_data_0_2[15: 8];
tx_data[ 15: 8] <= dac_data_0_1[15: 8];
tx_data[ 7: 0] <= dac_data_0_0[15: 8];
tx_data[127:120] <= (DEVICE_TYPE == 1) ? dac_data_1_0[ 7: 0] : dac_data_1_3[ 7: 0];
tx_data[119:112] <= (DEVICE_TYPE == 1) ? dac_data_1_1[ 7: 0] : dac_data_1_2[ 7: 0];
tx_data[111:104] <= (DEVICE_TYPE == 1) ? dac_data_1_2[ 7: 0] : dac_data_1_1[ 7: 0];
tx_data[103: 96] <= (DEVICE_TYPE == 1) ? dac_data_1_3[ 7: 0] : dac_data_1_0[ 7: 0];
tx_data[ 95: 88] <= (DEVICE_TYPE == 1) ? dac_data_1_0[15: 8] : dac_data_1_3[15: 8];
tx_data[ 87: 80] <= (DEVICE_TYPE == 1) ? dac_data_1_1[15: 8] : dac_data_1_2[15: 8];
tx_data[ 79: 72] <= (DEVICE_TYPE == 1) ? dac_data_1_2[15: 8] : dac_data_1_1[15: 8];
tx_data[ 71: 64] <= (DEVICE_TYPE == 1) ? dac_data_1_3[15: 8] : dac_data_1_0[15: 8];
tx_data[ 63: 56] <= (DEVICE_TYPE == 1) ? dac_data_0_0[ 7: 0] : dac_data_0_3[ 7: 0];
tx_data[ 55: 48] <= (DEVICE_TYPE == 1) ? dac_data_0_1[ 7: 0] : dac_data_0_2[ 7: 0];
tx_data[ 47: 40] <= (DEVICE_TYPE == 1) ? dac_data_0_2[ 7: 0] : dac_data_0_1[ 7: 0];
tx_data[ 39: 32] <= (DEVICE_TYPE == 1) ? dac_data_0_3[ 7: 0] : dac_data_0_0[ 7: 0];
tx_data[ 31: 24] <= (DEVICE_TYPE == 1) ? dac_data_0_0[15: 8] : dac_data_0_3[15: 8];
tx_data[ 23: 16] <= (DEVICE_TYPE == 1) ? dac_data_0_1[15: 8] : dac_data_0_2[15: 8];
tx_data[ 15: 8] <= (DEVICE_TYPE == 1) ? dac_data_0_2[15: 8] : dac_data_0_1[15: 8];
tx_data[ 7: 0] <= (DEVICE_TYPE == 1) ? dac_data_0_3[15: 8] : dac_data_0_0[15: 8];
end
end

3
library/axi_ad9152/axi_ad9152_ip.tcl
View File

@ -6,7 +6,7 @@ source $ad_hdl_dir/library/scripts/adi_ip.tcl
adi_ip_create axi_ad9152
adi_ip_files axi_ad9152 [list \
"$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc" \
"$ad_hdl_dir/library/common/ad_mul.v" \
"$ad_hdl_dir/library/xilinx/common/ad_mul.v" \
"$ad_hdl_dir/library/common/ad_dds_sine.v" \
"$ad_hdl_dir/library/common/ad_dds_1.v" \
"$ad_hdl_dir/library/common/ad_dds.v" \
@ -29,6 +29,7 @@ adi_ip_constraints axi_ad9152 [list \
set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *tx_ready* -of_objects [ipx::current_core]]
ipx::save_core [ipx::current_core]

61
library/axi_ad9162/Makefile Normal file
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@ -0,0 +1,61 @@
####################################################################################
####################################################################################
## Copyright 2011(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################
####################################################################################
M_DEPS += ../common/ad_axi_ip_constr.xdc
M_DEPS += ../common/ad_dds.v
M_DEPS += ../common/ad_dds_1.v
M_DEPS += ../common/ad_dds_sine.v
M_DEPS += ../common/ad_rst.v
M_DEPS += ../common/up_axi.v
M_DEPS += ../common/up_clock_mon.v
M_DEPS += ../common/up_dac_channel.v
M_DEPS += ../common/up_dac_common.v
M_DEPS += ../common/up_xfer_cntrl.v
M_DEPS += ../common/up_xfer_status.v
M_DEPS += ../scripts/adi_env.tcl
M_DEPS += ../scripts/adi_ip.tcl
M_DEPS += ../xilinx/common/ad_mul.v
M_DEPS += axi_ad9162.v
M_DEPS += axi_ad9162_channel.v
M_DEPS += axi_ad9162_core.v
M_DEPS += axi_ad9162_if.v
M_DEPS += axi_ad9162_ip.tcl
M_VIVADO := vivado -mode batch -source
M_FLIST := *.cache
M_FLIST += *.data
M_FLIST += *.xpr
M_FLIST += *.log
M_FLIST += component.xml
M_FLIST += *.jou
M_FLIST += xgui
M_FLIST += *.ip_user_files
M_FLIST += *.srcs
M_FLIST += *.hw
M_FLIST += *.sim
M_FLIST += .Xil
.PHONY: all clean clean-all
all: axi_ad9162.xpr
clean:clean-all
clean-all:
rm -rf $(M_FLIST)
axi_ad9162.xpr: $(M_DEPS)
-rm -rf $(M_FLIST)
$(M_VIVADO) axi_ad9162_ip.tcl >> axi_ad9162_ip.log 2>&1
####################################################################################
####################################################################################

225
library/axi_ad9162/axi_ad9162.v Normal file
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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
`timescale 1ns / 1ps
module axi_ad9162 (
// jesd interface
// tx_clk is (line-rate/40)
tx_clk,
tx_valid,
tx_data,
tx_ready,
// dma interface
dac_clk,
dac_valid,
dac_enable,
dac_ddata,
dac_dovf,
dac_dunf,
// axi interface
s_axi_aclk,
s_axi_aresetn,
s_axi_awvalid,
s_axi_awaddr,
s_axi_awprot,
s_axi_awready,
s_axi_wvalid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wready,
s_axi_bvalid,
s_axi_bresp,
s_axi_bready,
s_axi_arvalid,
s_axi_araddr,
s_axi_arprot,
s_axi_arready,
s_axi_rvalid,
s_axi_rdata,
s_axi_rresp,
s_axi_rready);
// parameters
parameter ID = 0;
parameter DEVICE_TYPE = 0;
parameter DAC_DATAPATH_DISABLE = 0;
// jesd interface
// tx_clk is (line-rate/40)
input tx_clk;
output tx_valid;
output [255:0] tx_data;
input tx_ready;
// dma interface
output dac_clk;
output dac_valid;
output dac_enable;
input [255:0] dac_ddata;
input dac_dovf;
input dac_dunf;
// axi interface
input s_axi_aclk;
input s_axi_aresetn;
input s_axi_awvalid;
input [ 31:0] s_axi_awaddr;
input [ 2:0] s_axi_awprot;
output s_axi_awready;
input s_axi_wvalid;
input [ 31:0] s_axi_wdata;
input [ 3:0] s_axi_wstrb;
output s_axi_wready;
output s_axi_bvalid;
output [ 1:0] s_axi_bresp;
input s_axi_bready;
input s_axi_arvalid;
input [ 31:0] s_axi_araddr;
input [ 2:0] s_axi_arprot;
output s_axi_arready;
output s_axi_rvalid;
output [ 31:0] s_axi_rdata;
output [ 1:0] s_axi_rresp;
input s_axi_rready;
// internal clocks and resets
wire dac_rst;
wire up_clk;
wire up_rstn;
// internal signals
wire [255:0] dac_data_s;
wire up_wreq_s;
wire [ 13:0] up_waddr_s;
wire [ 31:0] up_wdata_s;
wire up_wack_s;
wire up_rreq_s;
wire [ 13:0] up_raddr_s;
wire [ 31:0] up_rdata_s;
wire up_rack_s;
// signal name changes
assign up_clk = s_axi_aclk;
assign up_rstn = s_axi_aresetn;
// defaults
assign tx_valid = 1'b1;
// device interface
axi_ad9162_if #(.DEVICE_TYPE (DEVICE_TYPE)) i_if (
.tx_clk (tx_clk),
.tx_data (tx_data),
.dac_clk (dac_clk),
.dac_rst (dac_rst),
.dac_data (dac_data_s));
// core
axi_ad9162_core #(
.ID (ID),
.DATAPATH_DISABLE (DAC_DATAPATH_DISABLE))
i_core (
.dac_clk (dac_clk),
.dac_rst (dac_rst),
.dac_data (dac_data_s),
.dac_valid (dac_valid),
.dac_enable (dac_enable),
.dac_ddata (dac_ddata),
.dac_dovf (dac_dovf),
.dac_dunf (dac_dunf),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s),
.up_rack (up_rack_s));
// up bus interface
up_axi i_up_axi (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_axi_awvalid (s_axi_awvalid),
.up_axi_awaddr (s_axi_awaddr),
.up_axi_awready (s_axi_awready),
.up_axi_wvalid (s_axi_wvalid),
.up_axi_wdata (s_axi_wdata),
.up_axi_wstrb (s_axi_wstrb),
.up_axi_wready (s_axi_wready),
.up_axi_bvalid (s_axi_bvalid),
.up_axi_bresp (s_axi_bresp),
.up_axi_bready (s_axi_bready),
.up_axi_arvalid (s_axi_arvalid),
.up_axi_araddr (s_axi_araddr),
.up_axi_arready (s_axi_arready),
.up_axi_rvalid (s_axi_rvalid),
.up_axi_rresp (s_axi_rresp),
.up_axi_rdata (s_axi_rdata),
.up_axi_rready (s_axi_rready),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s),
.up_rack (up_rack_s));
endmodule
// ***************************************************************************
// ***************************************************************************

502
library/axi_ad9162/axi_ad9162_channel.v Normal file
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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
`timescale 1ns / 1ps
module axi_ad9162_channel (
// dac interface
dac_clk,
dac_rst,
dac_enable,
dac_data,
dma_data,
// processor interface
dac_data_sync,
dac_dds_format,
// bus interface
up_rstn,
up_clk,
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_rack);
// parameters
parameter CHANNEL_ID = 32'h0;
parameter DATAPATH_DISABLE = 0;
// dac interface
input dac_clk;
input dac_rst;
output dac_enable;
output [255:0] dac_data;
input [255:0] dma_data;
// processor interface
input dac_data_sync;
input dac_dds_format;
// bus interface
input up_rstn;
input up_clk;
input up_wreq;
input [ 13:0] up_waddr;
input [ 31:0] up_wdata;
output up_wack;
input up_rreq;
input [ 13:0] up_raddr;
output [ 31:0] up_rdata;
output up_rack;
// internal registers
reg dac_enable = 'd0;
reg [255:0] dac_data = 'd0;
reg [255:0] dac_data_int = 'd0;
reg [ 15:0] dac_dds_phase_00_0 = 'd0;
reg [ 15:0] dac_dds_phase_00_1 = 'd0;
reg [ 15:0] dac_dds_phase_01_0 = 'd0;
reg [ 15:0] dac_dds_phase_01_1 = 'd0;
reg [ 15:0] dac_dds_phase_02_0 = 'd0;
reg [ 15:0] dac_dds_phase_02_1 = 'd0;
reg [ 15:0] dac_dds_phase_03_0 = 'd0;
reg [ 15:0] dac_dds_phase_03_1 = 'd0;
reg [ 15:0] dac_dds_phase_04_0 = 'd0;
reg [ 15:0] dac_dds_phase_04_1 = 'd0;
reg [ 15:0] dac_dds_phase_05_0 = 'd0;
reg [ 15:0] dac_dds_phase_05_1 = 'd0;
reg [ 15:0] dac_dds_phase_06_0 = 'd0;
reg [ 15:0] dac_dds_phase_06_1 = 'd0;
reg [ 15:0] dac_dds_phase_07_0 = 'd0;
reg [ 15:0] dac_dds_phase_07_1 = 'd0;
reg [ 15:0] dac_dds_phase_08_0 = 'd0;
reg [ 15:0] dac_dds_phase_08_1 = 'd0;
reg [ 15:0] dac_dds_phase_09_0 = 'd0;
reg [ 15:0] dac_dds_phase_09_1 = 'd0;
reg [ 15:0] dac_dds_phase_10_0 = 'd0;
reg [ 15:0] dac_dds_phase_10_1 = 'd0;
reg [ 15:0] dac_dds_phase_11_0 = 'd0;
reg [ 15:0] dac_dds_phase_11_1 = 'd0;
reg [ 15:0] dac_dds_phase_12_0 = 'd0;
reg [ 15:0] dac_dds_phase_12_1 = 'd0;
reg [ 15:0] dac_dds_phase_13_0 = 'd0;
reg [ 15:0] dac_dds_phase_13_1 = 'd0;
reg [ 15:0] dac_dds_phase_14_0 = 'd0;
reg [ 15:0] dac_dds_phase_14_1 = 'd0;
reg [ 15:0] dac_dds_phase_15_0 = 'd0;
reg [ 15:0] dac_dds_phase_15_1 = 'd0;
reg [ 15:0] dac_dds_incr_0 = 'd0;
reg [ 15:0] dac_dds_incr_1 = 'd0;
reg [255:0] dac_dds_data = 'd0;
// internal signals
wire [ 15:0] dac_dds_scale_1_s;
wire [ 15:0] dac_dds_init_1_s;
wire [ 15:0] dac_dds_incr_1_s;
wire [ 15:0] dac_dds_scale_2_s;
wire [ 15:0] dac_dds_init_2_s;
wire [ 15:0] dac_dds_incr_2_s;
wire [ 15:0] dac_pat_data_1_s;
wire [ 15:0] dac_pat_data_2_s;
wire [ 3:0] dac_data_sel_s;
wire dac_iq_mode_s;
wire [255:0] dac_pat_data_s;
wire [255:0] dac_dds_data_s;
// dac sample mux
always @(posedge dac_clk) begin
dac_data[255:240] <= (dac_iq_mode_s == 1'b1) ? dac_data_int[255:240] : dac_data_int[255:240];
dac_data[239:224] <= (dac_iq_mode_s == 1'b1) ? dac_data_int[223:208] : dac_data_int[239:224];
dac_data[223:208] <= (dac_iq_mode_s == 1'b1) ? dac_data_int[239:224] : dac_data_int[223:208];
dac_data[207:192] <= (dac_iq_mode_s == 1'b1) ? dac_data_int[207:192] : dac_data_int[207:192];
dac_data[191:176] <= (dac_iq_mode_s == 1'b1) ? dac_data_int[191:176] : dac_data_int[191:176];
dac_data[175:160] <= (dac_iq_mode_s == 1'b1) ? dac_data_int[159:144] : dac_data_int[175:160];
dac_data[159:144] <= (dac_iq_mode_s == 1'b1) ? dac_data_int[175:160] : dac_data_int[159:144];
dac_data[143:128] <= (dac_iq_mode_s == 1'b1) ? dac_data_int[143:128] : dac_data_int[143:128];
dac_data[127:112] <= (dac_iq_mode_s == 1'b1) ? dac_data_int[127:112] : dac_data_int[127:112];
dac_data[111: 96] <= (dac_iq_mode_s == 1'b1) ? dac_data_int[ 95: 80] : dac_data_int[111: 96];
dac_data[ 95: 80] <= (dac_iq_mode_s == 1'b1) ? dac_data_int[111: 96] : dac_data_int[ 95: 80];
dac_data[ 79: 64] <= (dac_iq_mode_s == 1'b1) ? dac_data_int[ 79: 64] : dac_data_int[ 79: 64];
dac_data[ 63: 48] <= (dac_iq_mode_s == 1'b1) ? dac_data_int[ 63: 48] : dac_data_int[ 63: 48];
dac_data[ 47: 32] <= (dac_iq_mode_s == 1'b1) ? dac_data_int[ 31: 16] : dac_data_int[ 47: 32];
dac_data[ 31: 16] <= (dac_iq_mode_s == 1'b1) ? dac_data_int[ 47: 32] : dac_data_int[ 31: 16];
dac_data[ 15: 0] <= (dac_iq_mode_s == 1'b1) ? dac_data_int[ 15: 0] : dac_data_int[ 15: 0];
end
// dac pattern data
genvar n;
generate
for (n = 0; n < 8; n = n + 1) begin: g_dac_pat_data
assign dac_pat_data_s[((32*n)+31):((32*n)+16)] = dac_pat_data_2_s;
assign dac_pat_data_s[((32*n)+15):((32*n)+ 0)] = dac_pat_data_1_s;
end
endgenerate
// dac data select
always @(posedge dac_clk) begin
dac_enable <= (dac_data_sel_s == 4'h2) ? 1'b1 : 1'b0;
case (dac_data_sel_s)
4'h3: dac_data_int <= 256'd0;
4'h2: dac_data_int <= dma_data;
4'h1: dac_data_int <= dac_pat_data_s;
default: dac_data_int <= dac_dds_data;
endcase
end
// dds
always @(posedge dac_clk) begin
if (dac_data_sync == 1'b0) begin
dac_dds_phase_00_0 <= dac_dds_phase_00_0 + dac_dds_incr_0;
dac_dds_phase_00_1 <= dac_dds_phase_00_1 + dac_dds_incr_1;
dac_dds_phase_01_0 <= dac_dds_phase_01_0 + dac_dds_incr_0;
dac_dds_phase_01_1 <= dac_dds_phase_01_1 + dac_dds_incr_1;
dac_dds_phase_02_0 <= dac_dds_phase_02_0 + dac_dds_incr_0;
dac_dds_phase_02_1 <= dac_dds_phase_02_1 + dac_dds_incr_1;
dac_dds_phase_03_0 <= dac_dds_phase_03_0 + dac_dds_incr_0;
dac_dds_phase_03_1 <= dac_dds_phase_03_1 + dac_dds_incr_1;
dac_dds_phase_04_0 <= dac_dds_phase_04_0 + dac_dds_incr_0;
dac_dds_phase_04_1 <= dac_dds_phase_04_1 + dac_dds_incr_1;
dac_dds_phase_05_0 <= dac_dds_phase_05_0 + dac_dds_incr_0;
dac_dds_phase_05_1 <= dac_dds_phase_05_1 + dac_dds_incr_1;
dac_dds_phase_06_0 <= dac_dds_phase_06_0 + dac_dds_incr_0;
dac_dds_phase_06_1 <= dac_dds_phase_06_1 + dac_dds_incr_1;
dac_dds_phase_07_0 <= dac_dds_phase_07_0 + dac_dds_incr_0;
dac_dds_phase_07_1 <= dac_dds_phase_07_1 + dac_dds_incr_1;
dac_dds_phase_08_0 <= dac_dds_phase_08_0 + dac_dds_incr_0;
dac_dds_phase_08_1 <= dac_dds_phase_08_1 + dac_dds_incr_1;
dac_dds_phase_09_0 <= dac_dds_phase_09_0 + dac_dds_incr_0;
dac_dds_phase_09_1 <= dac_dds_phase_09_1 + dac_dds_incr_1;
dac_dds_phase_10_0 <= dac_dds_phase_10_0 + dac_dds_incr_0;
dac_dds_phase_10_1 <= dac_dds_phase_10_1 + dac_dds_incr_1;
dac_dds_phase_11_0 <= dac_dds_phase_11_0 + dac_dds_incr_0;
dac_dds_phase_11_1 <= dac_dds_phase_11_1 + dac_dds_incr_1;
dac_dds_phase_12_0 <= dac_dds_phase_12_0 + dac_dds_incr_0;
dac_dds_phase_12_1 <= dac_dds_phase_12_1 + dac_dds_incr_1;
dac_dds_phase_13_0 <= dac_dds_phase_13_0 + dac_dds_incr_0;
dac_dds_phase_13_1 <= dac_dds_phase_13_1 + dac_dds_incr_1;
dac_dds_phase_14_0 <= dac_dds_phase_14_0 + dac_dds_incr_0;
dac_dds_phase_14_1 <= dac_dds_phase_14_1 + dac_dds_incr_1;
dac_dds_phase_15_0 <= dac_dds_phase_15_0 + dac_dds_incr_0;
dac_dds_phase_15_1 <= dac_dds_phase_15_1 + dac_dds_incr_1;
dac_dds_incr_0 <= dac_dds_incr_0;
dac_dds_incr_1 <= dac_dds_incr_1;
dac_dds_data <= dac_dds_data_s;
end else if (dac_iq_mode_s == 1'b1) begin
dac_dds_phase_00_0 <= dac_dds_init_1_s;
dac_dds_phase_00_1 <= dac_dds_init_2_s;
dac_dds_phase_01_0 <= dac_dds_phase_00_0 + 16'h4000;
dac_dds_phase_01_1 <= dac_dds_phase_00_1 + 16'h4000;
dac_dds_phase_02_0 <= dac_dds_phase_00_0 + dac_dds_incr_1_s;
dac_dds_phase_02_1 <= dac_dds_phase_00_1 + dac_dds_incr_2_s;
dac_dds_phase_03_0 <= dac_dds_phase_02_0 + 16'h4000;
dac_dds_phase_03_1 <= dac_dds_phase_02_1 + 16'h4000;
dac_dds_phase_04_0 <= dac_dds_phase_02_0 + dac_dds_incr_1_s;
dac_dds_phase_04_1 <= dac_dds_phase_02_1 + dac_dds_incr_2_s;
dac_dds_phase_05_0 <= dac_dds_phase_04_0 + 16'h4000;
dac_dds_phase_05_1 <= dac_dds_phase_04_1 + 16'h4000;
dac_dds_phase_06_0 <= dac_dds_phase_04_0 + dac_dds_incr_1_s;
dac_dds_phase_06_1 <= dac_dds_phase_04_1 + dac_dds_incr_2_s;
dac_dds_phase_07_0 <= dac_dds_phase_06_0 + 16'h4000;
dac_dds_phase_07_1 <= dac_dds_phase_06_1 + 16'h4000;
dac_dds_phase_08_0 <= dac_dds_phase_06_0 + dac_dds_incr_1_s;
dac_dds_phase_08_1 <= dac_dds_phase_06_1 + dac_dds_incr_2_s;
dac_dds_phase_09_0 <= dac_dds_phase_08_0 + 16'h4000;
dac_dds_phase_09_1 <= dac_dds_phase_08_1 + 16'h4000;
dac_dds_phase_10_0 <= dac_dds_phase_08_0 + dac_dds_incr_1_s;
dac_dds_phase_10_1 <= dac_dds_phase_08_1 + dac_dds_incr_2_s;
dac_dds_phase_11_0 <= dac_dds_phase_10_0 + 16'h4000;
dac_dds_phase_11_1 <= dac_dds_phase_10_1 + 16'h4000;
dac_dds_phase_12_0 <= dac_dds_phase_10_0 + dac_dds_incr_1_s;
dac_dds_phase_12_1 <= dac_dds_phase_10_1 + dac_dds_incr_2_s;
dac_dds_phase_13_0 <= dac_dds_phase_12_0 + 16'h4000;
dac_dds_phase_13_1 <= dac_dds_phase_12_1 + 16'h4000;
dac_dds_phase_14_0 <= dac_dds_phase_12_0 + dac_dds_incr_1_s;
dac_dds_phase_14_1 <= dac_dds_phase_12_1 + dac_dds_incr_2_s;
dac_dds_phase_15_0 <= dac_dds_phase_14_0 + 16'h4000;
dac_dds_phase_15_1 <= dac_dds_phase_14_1 + 16'h4000;
dac_dds_incr_0 <= {dac_dds_incr_1_s[12:0], 3'd0};
dac_dds_incr_1 <= {dac_dds_incr_2_s[12:0], 3'd0};
dac_dds_data <= 256'd0;
end else begin
dac_dds_phase_00_0 <= dac_dds_init_1_s;
dac_dds_phase_00_1 <= dac_dds_init_2_s;
dac_dds_phase_01_0 <= dac_dds_phase_00_0 + dac_dds_incr_1_s;
dac_dds_phase_01_1 <= dac_dds_phase_00_1 + dac_dds_incr_2_s;
dac_dds_phase_02_0 <= dac_dds_phase_01_0 + dac_dds_incr_1_s;
dac_dds_phase_02_1 <= dac_dds_phase_01_1 + dac_dds_incr_2_s;
dac_dds_phase_03_0 <= dac_dds_phase_02_0 + dac_dds_incr_1_s;
dac_dds_phase_03_1 <= dac_dds_phase_02_1 + dac_dds_incr_2_s;
dac_dds_phase_04_0 <= dac_dds_phase_03_0 + dac_dds_incr_1_s;
dac_dds_phase_04_1 <= dac_dds_phase_03_1 + dac_dds_incr_2_s;
dac_dds_phase_05_0 <= dac_dds_phase_04_0 + dac_dds_incr_1_s;
dac_dds_phase_05_1 <= dac_dds_phase_04_1 + dac_dds_incr_2_s;
dac_dds_phase_06_0 <= dac_dds_phase_05_0 + dac_dds_incr_1_s;
dac_dds_phase_06_1 <= dac_dds_phase_05_1 + dac_dds_incr_2_s;
dac_dds_phase_07_0 <= dac_dds_phase_06_0 + dac_dds_incr_1_s;
dac_dds_phase_07_1 <= dac_dds_phase_06_1 + dac_dds_incr_2_s;
dac_dds_phase_08_0 <= dac_dds_phase_07_0 + dac_dds_incr_1_s;
dac_dds_phase_08_1 <= dac_dds_phase_07_1 + dac_dds_incr_2_s;
dac_dds_phase_09_0 <= dac_dds_phase_08_0 + dac_dds_incr_1_s;
dac_dds_phase_09_1 <= dac_dds_phase_08_1 + dac_dds_incr_2_s;
dac_dds_phase_10_0 <= dac_dds_phase_09_0 + dac_dds_incr_1_s;
dac_dds_phase_10_1 <= dac_dds_phase_09_1 + dac_dds_incr_2_s;
dac_dds_phase_11_0 <= dac_dds_phase_10_0 + dac_dds_incr_1_s;
dac_dds_phase_11_1 <= dac_dds_phase_10_1 + dac_dds_incr_2_s;
dac_dds_phase_12_0 <= dac_dds_phase_11_0 + dac_dds_incr_1_s;
dac_dds_phase_12_1 <= dac_dds_phase_11_1 + dac_dds_incr_2_s;
dac_dds_phase_13_0 <= dac_dds_phase_12_0 + dac_dds_incr_1_s;
dac_dds_phase_13_1 <= dac_dds_phase_12_1 + dac_dds_incr_2_s;
dac_dds_phase_14_0 <= dac_dds_phase_13_0 + dac_dds_incr_1_s;
dac_dds_phase_14_1 <= dac_dds_phase_13_1 + dac_dds_incr_2_s;
dac_dds_phase_15_0 <= dac_dds_phase_14_0 + dac_dds_incr_1_s;
dac_dds_phase_15_1 <= dac_dds_phase_14_1 + dac_dds_incr_2_s;
dac_dds_incr_0 <= {dac_dds_incr_1_s[11:0], 4'd0};
dac_dds_incr_1 <= {dac_dds_incr_2_s[11:0], 4'd0};
dac_dds_data <= 256'd0;
end
end
ad_dds #(.DISABLE (DATAPATH_DISABLE)) i_dds_00 (
.clk (dac_clk),
.dds_format (dac_dds_format),
.dds_phase_0 (dac_dds_phase_00_0),
.dds_scale_0 (dac_dds_scale_1_s),
.dds_phase_1 (dac_dds_phase_00_1),
.dds_scale_1 (dac_dds_scale_2_s),
.dds_data (dac_dds_data_s[15:0]));
ad_dds #(.DISABLE (DATAPATH_DISABLE)) i_dds_01 (
.clk (dac_clk),
.dds_format (dac_dds_format),
.dds_phase_0 (dac_dds_phase_01_0),
.dds_scale_0 (dac_dds_scale_1_s),
.dds_phase_1 (dac_dds_phase_01_1),
.dds_scale_1 (dac_dds_scale_2_s),
.dds_data (dac_dds_data_s[31:16]));
ad_dds #(.DISABLE (DATAPATH_DISABLE)) i_dds_02 (
.clk (dac_clk),
.dds_format (dac_dds_format),
.dds_phase_0 (dac_dds_phase_02_0),
.dds_scale_0 (dac_dds_scale_1_s),
.dds_phase_1 (dac_dds_phase_02_1),
.dds_scale_1 (dac_dds_scale_2_s),
.dds_data (dac_dds_data_s[47:32]));
ad_dds #(.DISABLE (DATAPATH_DISABLE)) i_dds_03 (
.clk (dac_clk),
.dds_format (dac_dds_format),
.dds_phase_0 (dac_dds_phase_03_0),
.dds_scale_0 (dac_dds_scale_1_s),
.dds_phase_1 (dac_dds_phase_03_1),
.dds_scale_1 (dac_dds_scale_2_s),
.dds_data (dac_dds_data_s[63:48]));
ad_dds #(.DISABLE (DATAPATH_DISABLE)) i_dds_04 (
.clk (dac_clk),
.dds_format (dac_dds_format),
.dds_phase_0 (dac_dds_phase_04_0),
.dds_scale_0 (dac_dds_scale_1_s),
.dds_phase_1 (dac_dds_phase_04_1),
.dds_scale_1 (dac_dds_scale_2_s),
.dds_data (dac_dds_data_s[79:64]));
ad_dds #(.DISABLE (DATAPATH_DISABLE)) i_dds_05 (
.clk (dac_clk),
.dds_format (dac_dds_format),
.dds_phase_0 (dac_dds_phase_05_0),
.dds_scale_0 (dac_dds_scale_1_s),
.dds_phase_1 (dac_dds_phase_05_1),
.dds_scale_1 (dac_dds_scale_2_s),
.dds_data (dac_dds_data_s[95:80]));
ad_dds #(.DISABLE (DATAPATH_DISABLE)) i_dds_06 (
.clk (dac_clk),
.dds_format (dac_dds_format),
.dds_phase_0 (dac_dds_phase_06_0),
.dds_scale_0 (dac_dds_scale_1_s),
.dds_phase_1 (dac_dds_phase_06_1),
.dds_scale_1 (dac_dds_scale_2_s),
.dds_data (dac_dds_data_s[111:96]));
ad_dds #(.DISABLE (DATAPATH_DISABLE)) i_dds_07 (
.clk (dac_clk),
.dds_format (dac_dds_format),
.dds_phase_0 (dac_dds_phase_07_0),
.dds_scale_0 (dac_dds_scale_1_s),
.dds_phase_1 (dac_dds_phase_07_1),
.dds_scale_1 (dac_dds_scale_2_s),
.dds_data (dac_dds_data_s[127:112]));
ad_dds #(.DISABLE (DATAPATH_DISABLE)) i_dds_08 (
.clk (dac_clk),
.dds_format (dac_dds_format),
.dds_phase_0 (dac_dds_phase_08_0),
.dds_scale_0 (dac_dds_scale_1_s),
.dds_phase_1 (dac_dds_phase_08_1),
.dds_scale_1 (dac_dds_scale_2_s),
.dds_data (dac_dds_data_s[143:128]));
ad_dds #(.DISABLE (DATAPATH_DISABLE)) i_dds_09 (
.clk (dac_clk),
.dds_format (dac_dds_format),
.dds_phase_0 (dac_dds_phase_09_0),
.dds_scale_0 (dac_dds_scale_1_s),
.dds_phase_1 (dac_dds_phase_09_1),
.dds_scale_1 (dac_dds_scale_2_s),
.dds_data (dac_dds_data_s[159:144]));
ad_dds #(.DISABLE (DATAPATH_DISABLE)) i_dds_10 (
.clk (dac_clk),
.dds_format (dac_dds_format),
.dds_phase_0 (dac_dds_phase_10_0),
.dds_scale_0 (dac_dds_scale_1_s),
.dds_phase_1 (dac_dds_phase_10_1),
.dds_scale_1 (dac_dds_scale_2_s),
.dds_data (dac_dds_data_s[175:160]));
ad_dds #(.DISABLE (DATAPATH_DISABLE)) i_dds_11 (
.clk (dac_clk),
.dds_format (dac_dds_format),
.dds_phase_0 (dac_dds_phase_11_0),
.dds_scale_0 (dac_dds_scale_1_s),
.dds_phase_1 (dac_dds_phase_11_1),
.dds_scale_1 (dac_dds_scale_2_s),
.dds_data (dac_dds_data_s[191:176]));
ad_dds #(.DISABLE (DATAPATH_DISABLE)) i_dds_12 (
.clk (dac_clk),
.dds_format (dac_dds_format),
.dds_phase_0 (dac_dds_phase_12_0),
.dds_scale_0 (dac_dds_scale_1_s),
.dds_phase_1 (dac_dds_phase_12_1),
.dds_scale_1 (dac_dds_scale_2_s),
.dds_data (dac_dds_data_s[207:192]));
ad_dds #(.DISABLE (DATAPATH_DISABLE)) i_dds_13 (
.clk (dac_clk),
.dds_format (dac_dds_format),
.dds_phase_0 (dac_dds_phase_13_0),
.dds_scale_0 (dac_dds_scale_1_s),
.dds_phase_1 (dac_dds_phase_13_1),
.dds_scale_1 (dac_dds_scale_2_s),
.dds_data (dac_dds_data_s[223:208]));
ad_dds #(.DISABLE (DATAPATH_DISABLE)) i_dds_14 (
.clk (dac_clk),
.dds_format (dac_dds_format),
.dds_phase_0 (dac_dds_phase_14_0),
.dds_scale_0 (dac_dds_scale_1_s),
.dds_phase_1 (dac_dds_phase_14_1),
.dds_scale_1 (dac_dds_scale_2_s),
.dds_data (dac_dds_data_s[239:224]));
ad_dds #(.DISABLE (DATAPATH_DISABLE)) i_dds_15 (
.clk (dac_clk),
.dds_format (dac_dds_format),
.dds_phase_0 (dac_dds_phase_15_0),
.dds_scale_0 (dac_dds_scale_1_s),
.dds_phase_1 (dac_dds_phase_15_1),
.dds_scale_1 (dac_dds_scale_2_s),
.dds_data (dac_dds_data_s[255:240]));
// single channel processor
up_dac_channel #(.CHANNEL_ID(CHANNEL_ID)) i_up_dac_channel (
.dac_clk (dac_clk),
.dac_rst (dac_rst),
.dac_dds_scale_1 (dac_dds_scale_1_s),
.dac_dds_init_1 (dac_dds_init_1_s),
.dac_dds_incr_1 (dac_dds_incr_1_s),
.dac_dds_scale_2 (dac_dds_scale_2_s),
.dac_dds_init_2 (dac_dds_init_2_s),
.dac_dds_incr_2 (dac_dds_incr_2_s),
.dac_pat_data_1 (dac_pat_data_1_s),
.dac_pat_data_2 (dac_pat_data_2_s),
.dac_data_sel (dac_data_sel_s),
.dac_iq_mode (dac_iq_mode_s),
.dac_iqcor_enb (),
.dac_iqcor_coeff_1 (),
.dac_iqcor_coeff_2 (),
.up_usr_datatype_be (),
.up_usr_datatype_signed (),
.up_usr_datatype_shift (),
.up_usr_datatype_total_bits (),
.up_usr_datatype_bits (),
.up_usr_interpolation_m (),
.up_usr_interpolation_n (),
.dac_usr_datatype_be (1'b0),
.dac_usr_datatype_signed (1'b1),
.dac_usr_datatype_shift (8'd0),
.dac_usr_datatype_total_bits (8'd16),
.dac_usr_datatype_bits (8'd16),
.dac_usr_interpolation_m (16'd1),
.dac_usr_interpolation_n (16'd1),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata),
.up_rack (up_rack));
endmodule
// ***************************************************************************
// ***************************************************************************

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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
`timescale 1ns / 1ps
module axi_ad9162_core (
// dac interface
dac_clk,
dac_rst,
dac_data,
// dma interface
dac_valid,
dac_enable,
dac_ddata,
dac_dovf,
dac_dunf,
// processor interface
up_rstn,
up_clk,
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_rack);
// parameters
parameter ID = 0;
parameter DATAPATH_DISABLE = 0;
// dac interface
input dac_clk;
output dac_rst;
output [255:0] dac_data;
// dma interface
output dac_valid;
output dac_enable;
input [255:0] dac_ddata;
input dac_dovf;
input dac_dunf;
// processor interface
input up_rstn;
input up_clk;
input up_wreq;
input [ 13:0] up_waddr;
input [ 31:0] up_wdata;
output up_wack;
input up_rreq;
input [ 13:0] up_raddr;
output [ 31:0] up_rdata;
output up_rack;
// internal registers
reg [ 31:0] up_rdata = 'd0;
reg up_rack = 'd0;
reg up_wack = 'd0;
// internal signals
wire dac_sync_s;
wire dac_datafmt_s;
wire [ 31:0] up_rdata_0_s;
wire up_rack_0_s;
wire up_wack_0_s;
wire [ 31:0] up_rdata_s;
wire up_rack_s;
wire up_wack_s;
// dac valid
assign dac_valid = 1'b1;
// processor read interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_rdata <= 'd0;
up_rack <= 'd0;
up_wack <= 'd0;
end else begin
up_rdata <= up_rdata_s | up_rdata_0_s;
up_rack <= up_rack_s | up_rack_0_s;
up_wack <= up_wack_s | up_wack_0_s;
end
end
// dac channel
axi_ad9162_channel #(
.CHANNEL_ID (0),
.DATAPATH_DISABLE (DATAPATH_DISABLE))
i_channel_0 (
.dac_clk (dac_clk),
.dac_rst (dac_rst),
.dac_enable (dac_enable),
.dac_data (dac_data),
.dma_data (dac_ddata),
.dac_data_sync (dac_sync_s),
.dac_dds_format (dac_datafmt_s),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack_0_s),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata_0_s),
.up_rack (up_rack_0_s));
// dac common processor interface
up_dac_common #(.ID(ID)) i_up_dac_common (
.mmcm_rst (),
.dac_clk (dac_clk),
.dac_rst (dac_rst),
.dac_sync (dac_sync_s),
.dac_frame (),
.dac_clksel (),
.dac_par_type (),
.dac_par_enb (),
.dac_r1_mode (),
.dac_datafmt (dac_datafmt_s),
.dac_datarate (),
.dac_status (1'b1),
.dac_status_ovf (dac_dovf),
.dac_status_unf (dac_dunf),
.dac_clk_ratio (32'd16),
.up_drp_sel (),
.up_drp_wr (),
.up_drp_addr (),
.up_drp_wdata (),
.up_drp_rdata (32'd0),
.up_drp_ready (1'd0),
.up_drp_locked (1'd1),
.up_usr_chanmax (),
.dac_usr_chanmax (8'd0),
.up_dac_gpio_in (32'd0),
.up_dac_gpio_out (),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack_s),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata_s),
.up_rack (up_rack_s));
endmodule
// ***************************************************************************
// ***************************************************************************

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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
`timescale 1ns / 1ps
module axi_ad9162_if (
// jesd interface
// tx_clk is (line-rate/40)
tx_clk,
tx_data,
// dac interface
dac_clk,
dac_rst,
dac_data);
// altera (0x1) or xilinx (0x0)
parameter DEVICE_TYPE = 0;
// jesd interface
// tx_clk is (line-rate/40)
input tx_clk;
output [255:0] tx_data;
// dac interface
output dac_clk;
input dac_rst;
input [255:0] dac_data;
// internal registers
reg [255:0] tx_data = 'd0;
// reorder data for the jesd links
assign dac_clk = tx_clk;
always @(posedge tx_clk) begin
tx_data[255:248] <= (DEVICE_TYPE == 1) ? dac_data[ 55: 48] : dac_data[247:240];
tx_data[247:240] <= (DEVICE_TYPE == 1) ? dac_data[119:112] : dac_data[183:176];
tx_data[239:232] <= (DEVICE_TYPE == 1) ? dac_data[183:176] : dac_data[119:112];
tx_data[231:224] <= (DEVICE_TYPE == 1) ? dac_data[247:240] : dac_data[ 55: 48];
tx_data[223:216] <= (DEVICE_TYPE == 1) ? dac_data[ 63: 56] : dac_data[255:248];
tx_data[215:208] <= (DEVICE_TYPE == 1) ? dac_data[127:120] : dac_data[191:184];
tx_data[207:200] <= (DEVICE_TYPE == 1) ? dac_data[191:184] : dac_data[127:120];
tx_data[199:192] <= (DEVICE_TYPE == 1) ? dac_data[255:248] : dac_data[ 63: 56];
tx_data[191:184] <= (DEVICE_TYPE == 1) ? dac_data[ 39: 32] : dac_data[231:224];
tx_data[183:176] <= (DEVICE_TYPE == 1) ? dac_data[103: 96] : dac_data[167:160];
tx_data[175:168] <= (DEVICE_TYPE == 1) ? dac_data[167:160] : dac_data[103: 96];
tx_data[167:160] <= (DEVICE_TYPE == 1) ? dac_data[231:224] : dac_data[ 39: 32];
tx_data[159:152] <= (DEVICE_TYPE == 1) ? dac_data[ 47: 40] : dac_data[239:232];
tx_data[151:144] <= (DEVICE_TYPE == 1) ? dac_data[111:104] : dac_data[175:168];
tx_data[143:136] <= (DEVICE_TYPE == 1) ? dac_data[175:168] : dac_data[111:104];
tx_data[135:128] <= (DEVICE_TYPE == 1) ? dac_data[239:232] : dac_data[ 47: 40];
tx_data[127:120] <= (DEVICE_TYPE == 1) ? dac_data[ 23: 16] : dac_data[215:208];
tx_data[119:112] <= (DEVICE_TYPE == 1) ? dac_data[ 87: 80] : dac_data[151:144];
tx_data[111:104] <= (DEVICE_TYPE == 1) ? dac_data[151:144] : dac_data[ 87: 80];
tx_data[103: 96] <= (DEVICE_TYPE == 1) ? dac_data[215:208] : dac_data[ 23: 16];
tx_data[ 95: 88] <= (DEVICE_TYPE == 1) ? dac_data[ 31: 24] : dac_data[223:216];
tx_data[ 87: 80] <= (DEVICE_TYPE == 1) ? dac_data[ 95: 88] : dac_data[159:152];
tx_data[ 79: 72] <= (DEVICE_TYPE == 1) ? dac_data[159:152] : dac_data[ 95: 88];
tx_data[ 71: 64] <= (DEVICE_TYPE == 1) ? dac_data[223:216] : dac_data[ 31: 24];
tx_data[ 63: 56] <= (DEVICE_TYPE == 1) ? dac_data[ 7: 0] : dac_data[199:192];
tx_data[ 55: 48] <= (DEVICE_TYPE == 1) ? dac_data[ 71: 64] : dac_data[135:128];
tx_data[ 47: 40] <= (DEVICE_TYPE == 1) ? dac_data[135:128] : dac_data[ 71: 64];
tx_data[ 39: 32] <= (DEVICE_TYPE == 1) ? dac_data[199:192] : dac_data[ 7: 0];
tx_data[ 31: 24] <= (DEVICE_TYPE == 1) ? dac_data[ 15: 8] : dac_data[207:200];
tx_data[ 23: 16] <= (DEVICE_TYPE == 1) ? dac_data[ 79: 72] : dac_data[143:136];
tx_data[ 15: 8] <= (DEVICE_TYPE == 1) ? dac_data[143:136] : dac_data[ 79: 72];
tx_data[ 7: 0] <= (DEVICE_TYPE == 1) ? dac_data[207:200] : dac_data[ 15: 8];
end
endmodule
// ***************************************************************************
// ***************************************************************************

36
library/axi_ad9162/axi_ad9162_ip.tcl Normal file
View File

@ -0,0 +1,36 @@
# ip
source ../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip.tcl
adi_ip_create axi_ad9162
adi_ip_files axi_ad9162 [list \
"$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc" \
"$ad_hdl_dir/library/xilinx/common/ad_mul.v" \
"$ad_hdl_dir/library/common/ad_dds_sine.v" \
"$ad_hdl_dir/library/common/ad_dds_1.v" \
"$ad_hdl_dir/library/common/ad_dds.v" \
"$ad_hdl_dir/library/common/ad_rst.v" \
"$ad_hdl_dir/library/common/up_axi.v" \
"$ad_hdl_dir/library/common/up_xfer_cntrl.v" \
"$ad_hdl_dir/library/common/up_xfer_status.v" \
"$ad_hdl_dir/library/common/up_clock_mon.v" \
"$ad_hdl_dir/library/common/up_dac_common.v" \
"$ad_hdl_dir/library/common/up_dac_channel.v" \
"axi_ad9162_channel.v" \
"axi_ad9162_core.v" \
"axi_ad9162_if.v" \
"axi_ad9162.v" ]
adi_ip_properties axi_ad9162
adi_ip_constraints axi_ad9162 [list \
"$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc" ]
set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *tx_ready* -of_objects [ipx::current_core]]
ipx::save_core [ipx::current_core]

26
library/axi_ad9234/Makefile
View File

@ -5,22 +5,22 @@
####################################################################################
####################################################################################
M_DEPS := axi_ad9234_ip.tcl
M_DEPS += ../scripts/adi_env.tcl
M_DEPS += ../scripts/adi_ip.tcl
M_DEPS += ../common/ad_rst.v
M_DEPS += ../common/ad_pnmon.v
M_DEPS += ../common/ad_rst.v
M_DEPS += ../common/up_adc_channel.v
M_DEPS += ../common/up_adc_common.v
M_DEPS += ../common/up_axi.v
M_DEPS += ../common/up_clock_mon.v
M_DEPS += ../common/up_xfer_cntrl.v
M_DEPS += ../common/up_xfer_status.v
M_DEPS += ../common/up_clock_mon.v
M_DEPS += ../common/up_adc_common.v
M_DEPS += ../common/up_adc_channel.v
M_DEPS += axi_ad9234_pnmon.v
M_DEPS += axi_ad9234_channel.v
M_DEPS += axi_ad9234_if.v
M_DEPS += ../scripts/adi_env.tcl
M_DEPS += ../scripts/adi_ip.tcl
M_DEPS += axi_ad9234.v
M_DEPS += axi_ad9234_channel.v
M_DEPS += axi_ad9234_constr.xdc
M_DEPS += axi_ad9234_if.v
M_DEPS += axi_ad9234_ip.tcl
M_DEPS += axi_ad9234_pnmon.v
M_VIVADO := vivado -mode batch -source
@ -31,6 +31,10 @@ M_FLIST += *.log
M_FLIST += component.xml
M_FLIST += *.jou
M_FLIST += xgui
M_FLIST += *.ip_user_files
M_FLIST += *.srcs
M_FLIST += *.hw
M_FLIST += *.sim
M_FLIST += .Xil
@ -47,7 +51,7 @@ clean-all:
axi_ad9234.xpr: $(M_DEPS)
rm -rf $(M_FLIST)
-rm -rf $(M_FLIST)
$(M_VIVADO) axi_ad9234_ip.tcl >> axi_ad9234_ip.log 2>&1
####################################################################################

9
library/axi_ad9234/axi_ad9234.v
View File

@ -79,7 +79,9 @@ module axi_ad9234 (
s_axi_rvalid,
s_axi_rresp,
s_axi_rdata,
s_axi_rready);
s_axi_rready,
s_axi_awprot,
s_axi_arprot);
parameter ID = 0;
parameter DEVICE_TYPE = 0;
@ -124,6 +126,9 @@ module axi_ad9234 (
output [ 1:0] s_axi_rresp;
output [31:0] s_axi_rdata;
input s_axi_rready;
input [ 2:0] s_axi_awprot;
input [ 2:0] s_axi_arprot;
// internal registers
@ -271,7 +276,7 @@ module axi_ad9234 (
.up_drp_wr (),
.up_drp_addr (),
.up_drp_wdata (),
.up_drp_rdata (16'd0),
.up_drp_rdata (32'd0),
.up_drp_ready (1'd0),
.up_drp_locked (1'd1),
.up_usr_chanmax (),

2
library/axi_ad9234/axi_ad9234_channel.v
View File

@ -120,7 +120,7 @@ module axi_ad9234_channel (
assign adc_dfmt_data = adc_data;
up_adc_channel #(.ADC_CHANNEL_ID(CHANNEL_ID)) i_up_adc_channel (
up_adc_channel #(.CHANNEL_ID(CHANNEL_ID)) i_up_adc_channel (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_enable (adc_enable),

33
library/axi_ad9250/Makefile
View File

@ -5,24 +5,25 @@
####################################################################################
####################################################################################
M_DEPS := axi_ad9250_ip.tcl
M_DEPS += ../scripts/adi_env.tcl
M_DEPS += ../scripts/adi_ip.tcl
M_DEPS += ../common/ad_rst.v
M_DEPS += ../common/ad_pnmon.v
M_DEPS += ../common/ad_axi_ip_constr.xdc
M_DEPS += ../common/ad_datafmt.v
M_DEPS += ../common/ad_pnmon.v
M_DEPS += ../common/ad_rst.v
M_DEPS += ../common/ad_xcvr_rx_if.v
M_DEPS += ../common/up_adc_channel.v
M_DEPS += ../common/up_adc_common.v
M_DEPS += ../common/up_axi.v
M_DEPS += ../common/up_clock_mon.v
M_DEPS += ../common/up_xfer_cntrl.v
M_DEPS += ../common/up_xfer_status.v
M_DEPS += ../common/up_clock_mon.v
M_DEPS += ../common/up_adc_common.v
M_DEPS += ../common/up_adc_channel.v
M_DEPS += ../common/ad_axi_ip_constr.xdc
M_DEPS += axi_ad9250_pnmon.v
M_DEPS += axi_ad9250_channel.v
M_DEPS += axi_ad9250_if.v
M_DEPS += axi_ad9250_constr.xdc
M_DEPS += ../scripts/adi_env.tcl
M_DEPS += ../scripts/adi_ip.tcl
M_DEPS += axi_ad9250.v
M_DEPS += axi_ad9250_channel.v
M_DEPS += axi_ad9250_constr.xdc
M_DEPS += axi_ad9250_if.v
M_DEPS += axi_ad9250_ip.tcl
M_DEPS += axi_ad9250_pnmon.v
M_VIVADO := vivado -mode batch -source
@ -33,6 +34,10 @@ M_FLIST += *.log
M_FLIST += component.xml
M_FLIST += *.jou
M_FLIST += xgui
M_FLIST += *.ip_user_files
M_FLIST += *.srcs
M_FLIST += *.hw
M_FLIST += *.sim
M_FLIST += .Xil
@ -49,7 +54,7 @@ clean-all:
axi_ad9250.xpr: $(M_DEPS)
rm -rf $(M_FLIST)
-rm -rf $(M_FLIST)
$(M_VIVADO) axi_ad9250_ip.tcl >> axi_ad9250_ip.log 2>&1
####################################################################################

18
library/axi_ad9250/axi_ad9250.v
View File

@ -34,8 +34,6 @@
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
@ -45,7 +43,10 @@ module axi_ad9250 (
// rx_clk is (line-rate/40)
rx_clk,
rx_sof,
rx_valid,
rx_data,
rx_ready,
// dma interface
@ -86,13 +87,15 @@ module axi_ad9250 (
parameter ID = 0;
parameter DEVICE_TYPE = 0;
parameter IO_DELAY_GROUP = "adc_if_delay_group";
// jesd interface
// rx_clk is (line-rate/40)
input rx_clk;
input [ 3:0] rx_sof;
input rx_valid;
input [63:0] rx_data;
output rx_ready;
// dma interface
@ -170,6 +173,10 @@ module axi_ad9250 (
assign up_clk = s_axi_aclk;
assign up_rstn = s_axi_aresetn;
// defaults
assign rx_ready = 1'b1;
// processor read interface
always @(negedge up_rstn or posedge up_clk) begin
@ -197,8 +204,9 @@ module axi_ad9250 (
// main (device interface)
axi_ad9250_if i_if (
axi_ad9250_if #(.DEVICE_TYPE (DEVICE_TYPE)) i_if (
.rx_clk (rx_clk),
.rx_sof (rx_sof),
.rx_data (rx_data),
.adc_clk (adc_clk),
.adc_rst (adc_rst),
@ -277,7 +285,7 @@ module axi_ad9250 (
.up_drp_wr (),
.up_drp_addr (),
.up_drp_wdata (),
.up_drp_rdata (16'd0),
.up_drp_rdata (32'd0),
.up_drp_ready (1'd0),
.up_drp_locked (1'd1),
.up_usr_chanmax (),

2
library/axi_ad9250/axi_ad9250_channel.v
View File

@ -136,7 +136,7 @@ module axi_ad9250_channel (
end
endgenerate
up_adc_channel #(.ADC_CHANNEL_ID(CHANNEL_ID)) i_up_adc_channel (
up_adc_channel #(.CHANNEL_ID(CHANNEL_ID)) i_up_adc_channel (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_enable (adc_enable),

36
library/axi_ad9250/axi_ad9250_hw.tcl
View File

@ -24,6 +24,7 @@ add_fileset_file up_clock_mon.v VERILOG PATH $ad_hdl_dir/library/common/up
add_fileset_file up_delay_cntrl.v VERILOG PATH $ad_hdl_dir/library/common/up_delay_cntrl.v
add_fileset_file up_adc_common.v VERILOG PATH $ad_hdl_dir/library/common/up_adc_common.v
add_fileset_file up_adc_channel.v VERILOG PATH $ad_hdl_dir/library/common/up_adc_channel.v
add_fileset_file ad_xcvr_rx_if.v VERILOG PATH $ad_hdl_dir/library/common/ad_xcvr_rx_if.v
add_fileset_file axi_ad9250_pnmon.v VERILOG PATH axi_ad9250_pnmon.v
add_fileset_file axi_ad9250_if.v VERILOG PATH axi_ad9250_if.v
add_fileset_file axi_ad9250_channel.v VERILOG PATH axi_ad9250_channel.v
@ -40,7 +41,7 @@ set_parameter_property ID UNITS None
set_parameter_property ID HDL_PARAMETER true
add_parameter DEVICE_TYPE INTEGER 0
set_parameter_property DEVICE_TYPE DEFAULT_VALUE 0
set_parameter_property DEVICE_TYPE DEFAULT_VALUE 1
set_parameter_property DEVICE_TYPE DISPLAY_NAME DEVICE_TYPE
set_parameter_property DEVICE_TYPE TYPE INTEGER
set_parameter_property DEVICE_TYPE UNITS None
@ -81,24 +82,35 @@ add_interface_port s_axi s_axi_rready rready Input 1
# transceiver interface
ad_alt_intf clock rx_clk input 1
ad_alt_intf signal rx_data input 64 data
ad_alt_intf signal rx_sof input 4 export
add_interface if_rx_data avalon_streaming sink
add_interface_port if_rx_data rx_data data input 64
add_interface_port if_rx_data rx_valid valid input 1
add_interface_port if_rx_data rx_ready ready output 1
set_interface_property if_rx_data associatedClock if_rx_clk
set_interface_property if_rx_data dataBitsPerSymbol 64
# dma interface
ad_alt_intf clock adc_clk output 1
ad_alt_intf reset adc_rst output 1 if_adc_clk
add_interface fifo_ch_0_in conduit end
#set_interface_property fifo_ch_0_in associatedClock if_adc_clk
add_interface_port fifo_ch_0_in adc_enable_a enable Output 1
add_interface_port fifo_ch_0_in adc_valid_a valid Output 1
add_interface_port fifo_ch_0_in adc_data_a data Output 32
add_interface adc_ch_0 conduit end
add_interface_port adc_ch_0 adc_enable_a enable Output 1
add_interface_port adc_ch_0 adc_valid_a valid Output 1
add_interface_port adc_ch_0 adc_data_a data Output 32
add_interface fifo_ch_1_in conduit end
#set_interface_property fifo_ch_1_in associatedClock if_adc_clk
add_interface_port fifo_ch_1_in adc_enable_b enable Output 1
add_interface_port fifo_ch_1_in adc_valid_b valid Output 1
add_interface_port fifo_ch_1_in adc_data_b data Output 32
set_interface_property adc_ch_0 associatedClock if_rx_clk
set_interface_property adc_ch_0 associatedReset none
add_interface adc_ch_1 conduit end
add_interface_port adc_ch_1 adc_enable_b enable Output 1
add_interface_port adc_ch_1 adc_valid_b valid Output 1
add_interface_port adc_ch_1 adc_data_b data Output 32
set_interface_property adc_ch_1 associatedClock if_rx_clk
set_interface_property adc_ch_1 associatedReset none
ad_alt_intf signal adc_dovf input 1 ovf
ad_alt_intf signal adc_dunf input 1 unf

33
library/axi_ad9250/axi_ad9250_if.v
View File

@ -34,9 +34,6 @@
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// This is the LVDS/DDR interface
`timescale 1ns/100ps
@ -46,6 +43,7 @@ module axi_ad9250_if (
// rx_clk is (line-rate/40)
rx_clk,
rx_sof,
rx_data,
// adc data output
@ -58,10 +56,15 @@ module axi_ad9250_if (
adc_or_b,
adc_status);
// parameters
parameter DEVICE_TYPE = 0;
// jesd interface
// rx_clk is (line-rate/40)
input rx_clk;
input [ 3:0] rx_sof;
input [63:0] rx_data;
// adc data output
@ -84,6 +87,7 @@ module axi_ad9250_if (
wire [15:0] adc_data_a_s0_s;
wire [15:0] adc_data_b_s1_s;
wire [15:0] adc_data_b_s0_s;
wire [63:0] rx_data_s;
// adc clock is the reference clock
@ -98,10 +102,10 @@ module axi_ad9250_if (
// data multiplex
assign adc_data_a_s1_s = {rx_data[25:24], rx_data[23:16], rx_data[31:26]};
assign adc_data_a_s0_s = {rx_data[ 9: 8], rx_data[ 7: 0], rx_data[15:10]};
assign adc_data_b_s1_s = {rx_data[57:56], rx_data[55:48], rx_data[63:58]};
assign adc_data_b_s0_s = {rx_data[41:40], rx_data[39:32], rx_data[47:42]};
assign adc_data_a_s1_s = {rx_data_s[25:24], rx_data_s[23:16], rx_data_s[31:26]};
assign adc_data_a_s0_s = {rx_data_s[ 9: 8], rx_data_s[ 7: 0], rx_data_s[15:10]};
assign adc_data_b_s1_s = {rx_data_s[57:56], rx_data_s[55:48], rx_data_s[63:58]};
assign adc_data_b_s0_s = {rx_data_s[41:40], rx_data_s[39:32], rx_data_s[47:42]};
// status
@ -113,6 +117,21 @@ module axi_ad9250_if (
end
end
// frame-alignment
genvar n;
generate
for (n = 0; n < 2; n = n + 1) begin: g_xcvr_if
ad_xcvr_rx_if #(.DEVICE_TYPE (DEVICE_TYPE)) i_xcvr_if (
.rx_clk (rx_clk),
.rx_ip_sof (rx_sof),
.rx_ip_data (rx_data[((n*32)+31):(n*32)]),
.rx_sof (),
.rx_data (rx_data_s[((n*32)+31):(n*32)]));
end
endgenerate
endmodule
// ***************************************************************************

2
library/axi_ad9250/axi_ad9250_ip.tcl
View File

@ -14,6 +14,7 @@ adi_ip_files axi_ad9250 [list \
"$ad_hdl_dir/library/common/up_clock_mon.v" \
"$ad_hdl_dir/library/common/up_adc_common.v" \
"$ad_hdl_dir/library/common/up_adc_channel.v" \
"$ad_hdl_dir/library/common/ad_xcvr_rx_if.v" \
"$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc" \
"axi_ad9250_pnmon.v" \
"axi_ad9250_channel.v" \
@ -27,6 +28,7 @@ adi_ip_constraints axi_ad9250 [list \
"$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc" \
"axi_ad9250_constr.xdc" ]
set_property driver_value 0 [ipx::get_ports *rx_valid* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]]

36
library/axi_ad9265/Makefile
View File

@ -5,28 +5,28 @@
####################################################################################
####################################################################################
M_DEPS := axi_ad9265_ip.tcl
M_DEPS += ../scripts/adi_env.tcl
M_DEPS += ../scripts/adi_ip.tcl
M_DEPS += ../common/ad_rst.v
M_DEPS += ../common/ad_lvds_clk.v
M_DEPS += ../common/ad_lvds_in.v
M_DEPS += ../common/ad_axi_ip_constr.xdc
M_DEPS += ../common/ad_datafmt.v
M_DEPS += ../common/ad_dcfilter.v
M_DEPS += ../common/ad_pnmon.v
M_DEPS += ../common/up_xfer_status.v
M_DEPS += ../common/up_xfer_cntrl.v
M_DEPS += ../common/ad_rst.v
M_DEPS += ../common/up_adc_channel.v
M_DEPS += ../common/up_adc_common.v
M_DEPS += ../common/up_axi.v
M_DEPS += ../common/up_clock_mon.v
M_DEPS += ../common/up_delay_cntrl.v
M_DEPS += ../common/up_adc_common.v
M_DEPS += ../common/up_adc_channel.v
M_DEPS += ../common/up_axi.v
M_DEPS += ../common/ad_axi_ip_constr.xdc
M_DEPS += axi_ad9265_pnmon.v
M_DEPS += axi_ad9265_if.v
M_DEPS += ../common/up_xfer_cntrl.v
M_DEPS += ../common/up_xfer_status.v
M_DEPS += ../scripts/adi_env.tcl
M_DEPS += ../scripts/adi_ip.tcl
M_DEPS += ../xilinx/common/ad_lvds_clk.v
M_DEPS += ../xilinx/common/ad_lvds_in.v
M_DEPS += axi_ad9265.v
M_DEPS += axi_ad9265_channel.v
M_DEPS += axi_ad9265_constr.xdc
M_DEPS += axi_ad9265.v
M_DEPS += axi_ad9265_if.v
M_DEPS += axi_ad9265_ip.tcl
M_DEPS += axi_ad9265_pnmon.v
M_VIVADO := vivado -mode batch -source
@ -37,6 +37,10 @@ M_FLIST += *.log
M_FLIST += component.xml
M_FLIST += *.jou
M_FLIST += xgui
M_FLIST += *.ip_user_files
M_FLIST += *.srcs
M_FLIST += *.hw
M_FLIST += *.sim
M_FLIST += .Xil
@ -53,7 +57,7 @@ clean-all:
axi_ad9265.xpr: $(M_DEPS)
rm -rf $(M_FLIST)
-rm -rf $(M_FLIST)
$(M_VIVADO) axi_ad9265_ip.tcl >> axi_ad9265_ip.log 2>&1
####################################################################################

9
library/axi_ad9265/axi_ad9265.v
View File

@ -84,7 +84,9 @@ module axi_ad9265 (
s_axi_rvalid,
s_axi_rresp,
s_axi_rdata,
s_axi_rready);
s_axi_rready,
s_axi_awprot,
s_axi_arprot);
// parameters
@ -137,6 +139,9 @@ module axi_ad9265 (
output [ 1:0] s_axi_rresp;
output [31:0] s_axi_rdata;
input s_axi_rready;
input [ 2:0] s_axi_awprot;
input [ 2:0] s_axi_arprot;
// internal registers
@ -294,7 +299,7 @@ module axi_ad9265 (
.up_drp_wr (),
.up_drp_addr (),
.up_drp_wdata (),
.up_drp_rdata (16'd0),
.up_drp_rdata (32'd0),
.up_drp_ready (1'd0),
.up_drp_locked (1'd1),
.up_usr_chanmax (),

2
library/axi_ad9265/axi_ad9265_channel.v
View File

@ -159,7 +159,7 @@ module axi_ad9265_channel (
end
endgenerate
up_adc_channel #(.ADC_CHANNEL_ID(CHANNEL_ID)) i_up_adc_channel (
up_adc_channel #(.CHANNEL_ID(CHANNEL_ID)) i_up_adc_channel (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_enable (adc_enable),

2
library/axi_ad9265/axi_ad9265_if.v
View File

@ -175,6 +175,8 @@ module axi_ad9265_if (
ad_lvds_clk #(
.DEVICE_TYPE (DEVICE_TYPE))
i_adc_clk (
.rst (1'b0),
.locked (),
.clk_in_p (adc_clk_in_p),
.clk_in_n (adc_clk_in_n),
.clk (adc_clk));

4
library/axi_ad9265/axi_ad9265_ip.tcl
View File

@ -6,8 +6,8 @@ source $ad_hdl_dir/library/scripts/adi_ip.tcl
adi_ip_create axi_ad9265
adi_ip_files axi_ad9265 [list \
"$ad_hdl_dir/library/common/ad_rst.v" \
"$ad_hdl_dir/library/common/ad_lvds_clk.v" \
"$ad_hdl_dir/library/common/ad_lvds_in.v" \
"$ad_hdl_dir/library/xilinx/common/ad_lvds_clk.v" \
"$ad_hdl_dir/library/xilinx/common/ad_lvds_in.v" \
"$ad_hdl_dir/library/common/ad_datafmt.v" \
"$ad_hdl_dir/library/common/ad_dcfilter.v" \
"$ad_hdl_dir/library/common/ad_pnmon.v" \

62
library/axi_ad9361/Makefile
View File

@ -5,44 +5,48 @@
####################################################################################
####################################################################################
M_DEPS := axi_ad9361_ip.tcl
M_DEPS += ../scripts/adi_env.tcl
M_DEPS += ../scripts/adi_ip.tcl
M_DEPS += ../common/ad_addsub.v
M_DEPS += ../common/ad_axi_ip_constr.xdc
M_DEPS += ../common/ad_rst.v
M_DEPS += ../common/ad_lvds_clk.v
M_DEPS += ../common/ad_lvds_in.v
M_DEPS += ../common/ad_lvds_out.v
M_DEPS += ../common/ad_mul.v
M_DEPS += ../common/ad_pnmon.v
M_DEPS += ../common/ad_dds_sine.v
M_DEPS += ../common/ad_dds_1.v
M_DEPS += ../common/ad_dds.v
M_DEPS += ../common/ad_datafmt.v
M_DEPS += ../common/ad_dcfilter.v
M_DEPS += ../common/ad_dds.v
M_DEPS += ../common/ad_dds_1.v
M_DEPS += ../common/ad_dds_sine.v
M_DEPS += ../common/ad_iqcor.v
M_DEPS += ../common/ad_addsub.v
M_DEPS += ../common/ad_pnmon.v
M_DEPS += ../common/ad_rst.v
M_DEPS += ../common/ad_tdd_control.v
M_DEPS += ../common/up_adc_channel.v
M_DEPS += ../common/up_adc_common.v
M_DEPS += ../common/up_axi.v
M_DEPS += ../common/up_clock_mon.v
M_DEPS += ../common/up_dac_channel.v
M_DEPS += ../common/up_dac_common.v
M_DEPS += ../common/up_delay_cntrl.v
M_DEPS += ../common/up_tdd_cntrl.v
M_DEPS += ../common/up_xfer_cntrl.v
M_DEPS += ../common/up_xfer_status.v
M_DEPS += ../common/up_clock_mon.v
M_DEPS += ../common/up_delay_cntrl.v
M_DEPS += ../common/up_adc_common.v
M_DEPS += ../common/up_adc_channel.v
M_DEPS += ../common/up_dac_common.v
M_DEPS += ../common/up_dac_channel.v
M_DEPS += ../common/up_tdd_cntrl.v
M_DEPS += ../scripts/adi_env.tcl
M_DEPS += ../scripts/adi_ip.tcl
M_DEPS += ../xilinx/common/ad_cmos_clk.v
M_DEPS += ../xilinx/common/ad_cmos_in.v
M_DEPS += ../xilinx/common/ad_cmos_out.v
M_DEPS += ../xilinx/common/ad_lvds_clk.v
M_DEPS += ../xilinx/common/ad_lvds_in.v
M_DEPS += ../xilinx/common/ad_lvds_out.v
M_DEPS += ../xilinx/common/ad_mul.v
M_DEPS += axi_ad9361.v
M_DEPS += axi_ad9361_constr.xdc
M_DEPS += axi_ad9361_dev_if.v
M_DEPS += axi_ad9361_rx_pnmon.v
M_DEPS += axi_ad9361_rx_channel.v
M_DEPS += axi_ad9361_ip.tcl
M_DEPS += axi_ad9361_rx.v
M_DEPS += axi_ad9361_tx_channel.v
M_DEPS += axi_ad9361_tx.v
M_DEPS += axi_ad9361_rx_channel.v
M_DEPS += axi_ad9361_rx_pnmon.v
M_DEPS += axi_ad9361_tdd.v
M_DEPS += axi_ad9361_tdd_if.v
M_DEPS += axi_ad9361.v
M_DEPS += axi_ad9361_tx.v
M_DEPS += axi_ad9361_tx_channel.v
M_DEPS += xilinx/axi_ad9361_cmos_if.v
M_DEPS += xilinx/axi_ad9361_lvds_if.v
M_VIVADO := vivado -mode batch -source
@ -53,6 +57,10 @@ M_FLIST += *.log
M_FLIST += component.xml
M_FLIST += *.jou
M_FLIST += xgui
M_FLIST += *.ip_user_files
M_FLIST += *.srcs
M_FLIST += *.hw
M_FLIST += *.sim
M_FLIST += .Xil
@ -69,7 +77,7 @@ clean-all:
axi_ad9361.xpr: $(M_DEPS)
rm -rf $(M_FLIST)
-rm -rf $(M_FLIST)
$(M_VIVADO) axi_ad9361_ip.tcl >> axi_ad9361_ip.log 2>&1
####################################################################################

0
library/axi_ad9361/axi_ad9361_alt_lvds_rx.v → library/axi_ad9361/altera/axi_ad9361_alt_lvds_rx.v
View File

0
library/axi_ad9361/axi_ad9361_alt_lvds_tx.v → library/axi_ad9361/altera/axi_ad9361_alt_lvds_tx.v
View File

583
library/axi_ad9361/altera/axi_ad9361_cmos_if.v Normal file
View File

@ -0,0 +1,583 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_ad9361_cmos_if (
// physical interface (receive)
rx_clk_in,
rx_frame_in,
rx_data_in,
// physical interface (transmit)
tx_clk_out,
tx_frame_out,
tx_data_out,
// ensm control
enable,
txnrx,
// clock (common to both receive and transmit)
rst,
clk,
l_clk,
// receive data path interface
adc_valid,
adc_data,
adc_status,
adc_r1_mode,
adc_ddr_edgesel,
// transmit data path interface
dac_valid,
dac_data,
dac_clksel,
dac_r1_mode,
// tdd interface
tdd_enable,
tdd_txnrx,
tdd_mode,
// delay interface
mmcm_rst,
up_clk,
up_enable,
up_txnrx,
up_adc_dld,
up_adc_dwdata,
up_adc_drdata,
up_dac_dld,
up_dac_dwdata,
up_dac_drdata,
delay_clk,
delay_rst,
delay_locked);
// this parameter controls the buffer type based on the target device.
parameter DEVICE_TYPE = 0;
parameter DAC_IODELAY_ENABLE = 0;
parameter IO_DELAY_GROUP = "dev_if_delay_group";
// physical interface (receive)
input rx_clk_in;
input rx_frame_in;
input [11:0] rx_data_in;
// physical interface (transmit)
output tx_clk_out;
output tx_frame_out;
output [11:0] tx_data_out;
// ensm control
output enable;
output txnrx;
// clock (common to both receive and transmit)
input rst;
input clk;
output l_clk;
// receive data path interface
output adc_valid;
output [47:0] adc_data;
output adc_status;
input adc_r1_mode;
input adc_ddr_edgesel;
// transmit data path interface
input dac_valid;
input [47:0] dac_data;
input dac_clksel;
input dac_r1_mode;
// tdd interface
input tdd_enable;
input tdd_txnrx;
input tdd_mode;
// delay interface
input mmcm_rst;
input up_clk;
input up_enable;
input up_txnrx;
input [12:0] up_adc_dld;
input [64:0] up_adc_dwdata;
output [64:0] up_adc_drdata;
input [15:0] up_dac_dld;
input [79:0] up_dac_dwdata;
output [79:0] up_dac_drdata;
input delay_clk;
input delay_rst;
output delay_locked;
// internal registers
reg [ 1:0] rx_frame = 0;
reg [11:0] rx_data_p = 0;
reg rx_error_r1 = 'd0;
reg rx_valid_r1 = 'd0;
reg [23:0] rx_data_r1 = 'd0;
reg rx_error_r2 = 'd0;
reg rx_valid_r2 = 'd0;
reg [47:0] rx_data_r2 = 'd0;
reg adc_p_valid = 'd0;
reg [47:0] adc_p_data = 'd0;
reg adc_p_status = 'd0;
reg adc_n_valid = 'd0;
reg [47:0] adc_n_data = 'd0;
reg adc_n_status = 'd0;
reg adc_valid_int = 'd0;
reg [47:0] adc_data_int = 'd0;
reg adc_status_int = 'd0;
reg adc_valid = 'd0;
reg [47:0] adc_data = 'd0;
reg adc_status = 'd0;
reg [ 1:0] tx_data_cnt = 'd0;
reg [47:0] tx_data = 'd0;
reg tx_frame_p = 'd0;
reg tx_frame_n = 'd0;
reg [11:0] tx_data_p = 'd0;
reg [11:0] tx_data_n = 'd0;
reg tx_n_frame_p = 'd0;
reg tx_n_frame_n = 'd0;
reg [11:0] tx_n_data_p = 'd0;
reg [11:0] tx_n_data_n = 'd0;
reg tx_p_frame_p = 'd0;
reg tx_p_frame_n = 'd0;
reg [11:0] tx_p_data_p = 'd0;
reg [11:0] tx_p_data_n = 'd0;
reg up_enable_int = 'd0;
reg up_txnrx_int = 'd0;
reg enable_up_m1 = 'd0;
reg txnrx_up_m1 = 'd0;
reg enable_up = 'd0;
reg txnrx_up = 'd0;
reg enable_int = 'd0;
reg txnrx_int = 'd0;
reg enable_n_int = 'd0;
reg txnrx_n_int = 'd0;
reg enable_p_int = 'd0;
reg txnrx_p_int = 'd0;
reg dac_clkdata_p = 'd0;
reg dac_clkdata_n = 'd0;
reg locked_m1 = 'd0;
reg locked = 'd0;
// internal signals
wire [ 1:0] rx_frame_s;
wire [ 3:0] rx_frame_4_s;
wire [ 2:0] tx_data_sel_s;
wire [11:0] rx_data_p_s;
wire [11:0] rx_data_n_s;
wire rx_frame_p_s;
wire rx_frame_n_s;
wire locked_s;
genvar l_inst;
// receive data path interface
assign rx_frame_s = {rx_frame_p_s, rx_frame_n_s};
assign rx_frame_4_s = {rx_frame_s, rx_frame};
always @(posedge l_clk) begin
rx_frame <= rx_frame_s;
rx_data_p <= rx_data_p_s;
end
// receive data path for single rf, frame is expected to qualify i only
always @(posedge l_clk) begin
rx_error_r1 <= ~^ rx_frame_s;
rx_valid_r1 <= ^ rx_frame_s;
case (rx_frame_s)
2'b01: rx_data_r1 <= {rx_data_p_s, rx_data_n_s};
2'b10: rx_data_r1 <= {rx_data_n_s, rx_data_p};
default: rx_data_r1 <= 24'd0;
endcase
end
// receive data path for dual rf, frame is expected to qualify iq for rf-1 only
always @(posedge l_clk) begin
rx_error_r2 <= ((rx_frame_4_s == 4'b0011) || (rx_frame_4_s == 4'b1100) ||
(rx_frame_4_s == 4'b1001) || (rx_frame_4_s == 4'b0110)) ? 1'b0 : 1'b1;
rx_valid_r2 <= ((rx_frame_4_s == 4'b0011) ||
(rx_frame_4_s == 4'b1001)) ? 1'b1 : 1'b0;
case (rx_frame_s)
2'b11: rx_data_r2[23: 0] <= {rx_data_p_s, rx_data_n_s};
2'b01: rx_data_r2[23: 0] <= {rx_data_n_s, rx_data_p};
default: rx_data_r2[23: 0] <= rx_data_r2[23: 0];
endcase
case (rx_frame_s)
2'b00: rx_data_r2[47:24] <= {rx_data_p_s, rx_data_n_s};
2'b10: rx_data_r2[47:24] <= {rx_data_n_s, rx_data_p};
default: rx_data_r2[47:24] <= rx_data_r2[47:24];
endcase
end
// receive data path mux
always @(posedge l_clk) begin
if (adc_r1_mode == 1'b1) begin
adc_p_valid <= rx_valid_r1;
adc_p_data <= {24'd0, rx_data_r1};
adc_p_status <= ~rx_error_r1;
end else begin
adc_p_valid <= rx_valid_r2;
adc_p_data <= rx_data_r2;
adc_p_status <= ~rx_error_r2;
end
end
// transfer to a synchronous common clock
always @(negedge l_clk) begin
adc_n_valid <= adc_p_valid;
adc_n_data <= adc_p_data;
adc_n_status <= adc_p_status;
end
always @(posedge clk) begin
adc_valid_int <= adc_n_valid;
adc_data_int <= adc_n_data;
adc_status_int <= adc_n_status;
adc_valid <= adc_valid_int;
if (adc_valid_int == 1'b1) begin
adc_data <= adc_data_int;
end
adc_status <= adc_status_int & locked;
end
// transmit data path mux (reverse of what receive does above)
// the count simply selets the data muxing on the ddr outputs
assign tx_data_sel_s = {tx_data_cnt[1], dac_r1_mode, tx_data_cnt[0]};
always @(posedge clk) begin
if (dac_valid == 1'b1) begin
tx_data_cnt <= 2'b10;
end else if (tx_data_cnt[1] == 1'b1) begin
tx_data_cnt <= tx_data_cnt + 1'b1;
end
if (dac_valid == 1'b1) begin
tx_data <= dac_data;
end
case (tx_data_sel_s)
3'b101: begin
tx_frame_p <= 1'b0;
tx_frame_n <= 1'b0;
tx_data_p <= tx_data[35:24];
tx_data_n <= tx_data[47:36];
end
3'b100: begin
tx_frame_p <= 1'b1;
tx_frame_n <= 1'b1;
tx_data_p <= tx_data[11: 0];
tx_data_n <= tx_data[23:12];
end
3'b110: begin
tx_frame_p <= 1'b1;
tx_frame_n <= 1'b0;
tx_data_p <= tx_data[11: 0];
tx_data_n <= tx_data[23:12];
end
default: begin
tx_frame_p <= 1'd0;
tx_frame_n <= 1'd0;
tx_data_p <= 12'd0;
tx_data_n <= 12'd0;
end
endcase
end
// transfer data from a synchronous clock (skew less than 2ns)
always @(negedge clk) begin
tx_n_frame_p <= tx_frame_p;
tx_n_frame_n <= tx_frame_n;
tx_n_data_p <= tx_data_p;
tx_n_data_n <= tx_data_n;
end
always @(posedge l_clk) begin
tx_p_frame_p <= tx_n_frame_p;
tx_p_frame_n <= tx_n_frame_n;
tx_p_data_p <= tx_n_data_p;
tx_p_data_n <= tx_n_data_n;
end
// tdd/ensm control
always @(posedge up_clk) begin
up_enable_int <= up_enable;
up_txnrx_int <= up_txnrx;
end
always @(posedge clk or posedge rst) begin
if (rst == 1'b1) begin
enable_up_m1 <= 1'b0;
txnrx_up_m1 <= 1'b0;
enable_up <= 1'b0;
txnrx_up <= 1'b0;
end else begin
enable_up_m1 <= up_enable_int;
txnrx_up_m1 <= up_txnrx_int;
enable_up <= enable_up_m1;
txnrx_up <= txnrx_up_m1;
end
end
always @(posedge clk) begin
if (tdd_mode == 1'b1) begin
enable_int <= tdd_enable;
txnrx_int <= tdd_txnrx;
end else begin
enable_int <= enable_up;
txnrx_int <= txnrx_up;
end
end
always @(negedge clk) begin
enable_n_int <= enable_int;
txnrx_n_int <= txnrx_int;
end
always @(posedge l_clk) begin
enable_p_int <= enable_n_int;
txnrx_p_int <= txnrx_n_int;
end
always @(posedge l_clk) begin
dac_clkdata_p <= dac_clksel;
dac_clkdata_n <= ~dac_clksel;
end
// receive data interface, ibuf -> idelay -> iddr
generate
for (l_inst = 0; l_inst <= 11; l_inst = l_inst + 1) begin: g_rx_data
ad_cmos_in #(
.SINGLE_ENDED (1),
.DEVICE_TYPE (DEVICE_TYPE),
.IODELAY_CTRL (0),
.IODELAY_GROUP (IO_DELAY_GROUP))
i_rx_data (
.rx_clk (l_clk),
.rx_data_in (rx_data_in[l_inst]),
.rx_data_p (rx_data_p_s[l_inst]),
.rx_data_n (rx_data_n_s[l_inst]),
.up_clk (up_clk),
.up_dld (up_adc_dld[l_inst]),
.up_dwdata (up_adc_dwdata[((l_inst*5)+4):(l_inst*5)]),
.up_drdata (up_adc_drdata[((l_inst*5)+4):(l_inst*5)]),
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_locked ());
end
endgenerate
// receive frame interface, ibuf -> idelay -> iddr
ad_cmos_in #(
.SINGLE_ENDED (1),
.DEVICE_TYPE (DEVICE_TYPE),
.IODELAY_CTRL (1),
.IODELAY_GROUP (IO_DELAY_GROUP))
i_rx_frame (
.rx_clk (l_clk),
.rx_data_in (rx_frame_in),
.rx_data_p (rx_frame_p_s),
.rx_data_n (rx_frame_n_s),
.up_clk (up_clk),
.up_dld (up_adc_dld[12]),
.up_dwdata (up_adc_dwdata[64:60]),
.up_drdata (up_adc_drdata[64:60]),
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_locked (delay_locked));
// transmit data interface, oddr -> obuf
generate
for (l_inst = 0; l_inst <= 11; l_inst = l_inst + 1) begin: g_tx_data
ad_cmos_out #(
.DEVICE_TYPE (DEVICE_TYPE),
.SINGLE_ENDED (1),
.IODELAY_ENABLE (DAC_IODELAY_ENABLE),
.IODELAY_CTRL (0),
.IODELAY_GROUP (IO_DELAY_GROUP))
i_tx_data (
.tx_clk (l_clk),
.tx_data_p (tx_p_data_p[l_inst]),
.tx_data_n (tx_p_data_n[l_inst]),
.tx_data_out (tx_data_out[l_inst]),
.up_clk (up_clk),
.up_dld (up_dac_dld[l_inst]),
.up_dwdata (up_dac_dwdata[((l_inst*5)+4):(l_inst*5)]),
.up_drdata (up_dac_drdata[((l_inst*5)+4):(l_inst*5)]),
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_locked ());
end
endgenerate
// transmit frame interface, oddr -> obuf
ad_cmos_out #(
.DEVICE_TYPE (DEVICE_TYPE),
.SINGLE_ENDED (1),
.IODELAY_ENABLE (DAC_IODELAY_ENABLE),
.IODELAY_CTRL (0),
.IODELAY_GROUP (IO_DELAY_GROUP))
i_tx_frame (
.tx_clk (l_clk),
.tx_data_p (tx_p_frame_p),
.tx_data_n (tx_p_frame_n),
.tx_data_out (tx_frame_out),
.up_clk (up_clk),
.up_dld (up_dac_dld[12]),
.up_dwdata (up_dac_dwdata[64:60]),
.up_drdata (up_dac_drdata[64:60]),
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_locked ());
// transmit clock interface, oddr -> obuf
ad_cmos_out #(
.DEVICE_TYPE (DEVICE_TYPE),
.SINGLE_ENDED (1),
.IODELAY_ENABLE (DAC_IODELAY_ENABLE),
.IODELAY_CTRL (0),
.IODELAY_GROUP (IO_DELAY_GROUP))
i_tx_clk (
.tx_clk (l_clk),
.tx_data_p (dac_clkdata_p),
.tx_data_n (dac_clkdata_n),
.tx_data_out (tx_clk_out),
.up_clk (up_clk),
.up_dld (up_dac_dld[13]),
.up_dwdata (up_dac_dwdata[69:65]),
.up_drdata (up_dac_drdata[69:65]),
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_locked ());
// enable, oddr -> obuf
ad_cmos_out #(
.DEVICE_TYPE (DEVICE_TYPE),
.SINGLE_ENDED (1),
.IODELAY_ENABLE (DAC_IODELAY_ENABLE),
.IODELAY_CTRL (0),
.IODELAY_GROUP (IO_DELAY_GROUP))
i_enable (
.tx_clk (l_clk),
.tx_data_p (enable_p_int),
.tx_data_n (enable_p_int),
.tx_data_out (enable),
.up_clk (up_clk),
.up_dld (up_dac_dld[14]),
.up_dwdata (up_dac_dwdata[74:70]),
.up_drdata (up_dac_drdata[74:70]),
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_locked ());
// txnrx, oddr -> obuf
ad_cmos_out #(
.DEVICE_TYPE (DEVICE_TYPE),
.SINGLE_ENDED (1),
.IODELAY_ENABLE (DAC_IODELAY_ENABLE),
.IODELAY_CTRL (0),
.IODELAY_GROUP (IO_DELAY_GROUP))
i_txnrx (
.tx_clk (l_clk),
.tx_data_p (txnrx_p_int),
.tx_data_n (txnrx_p_int),
.tx_data_out (txnrx),
.up_clk (up_clk),
.up_dld (up_dac_dld[15]),
.up_dwdata (up_dac_dwdata[79:75]),
.up_drdata (up_dac_drdata[79:75]),
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_locked ());
// device clock interface (receive clock)
always @(posedge clk) begin
locked_m1 <= locked_s;
locked <= locked_m1;
end
ad_cmos_clk #(
.DEVICE_TYPE (DEVICE_TYPE))
i_clk (
.rst (mmcm_rst),
.locked (locked_s),
.clk_in (rx_clk_in),
.clk (l_clk));
endmodule
// ***************************************************************************
// ***************************************************************************

224
library/axi_ad9361/axi_ad9361_dev_if_alt.v → library/axi_ad9361/altera/axi_ad9361_lvds_if.v
View File

@ -1,179 +1,122 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// All rights reserved.
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
// The user should read each of these license terms, and understand the
// freedoms and responsabilities that he or she has by using this source/core.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// This interface includes both the transmit and receive components -
// They both uses the same clock (sourced from the receiving side).
`timescale 1ns/100ps
module axi_ad9361_dev_if (
module axi_ad9361_lvds_if #(
parameter DEVICE_TYPE = 0,
parameter DAC_IODELAY_ENABLE = 0,
parameter IO_DELAY_GROUP = "dev_if_delay_group") (
// physical interface (receive)
rx_clk_in_p,
rx_clk_in_n,
rx_frame_in_p,
rx_frame_in_n,
rx_data_in_p,
rx_data_in_n,
input rx_clk_in_p,
input rx_clk_in_n,
input rx_frame_in_p,
input rx_frame_in_n,
input [ 5:0] rx_data_in_p,
input [ 5:0] rx_data_in_n,
// physical interface (transmit)
tx_clk_out_p,
tx_clk_out_n,
tx_frame_out_p,
tx_frame_out_n,
tx_data_out_p,
tx_data_out_n,
output tx_clk_out_p,
output tx_clk_out_n,
output tx_frame_out_p,
output tx_frame_out_n,
output [ 5:0] tx_data_out_p,
output [ 5:0] tx_data_out_n,
// ensm control
enable,
txnrx,
output enable,
output txnrx,
// clock (common to both receive and transmit)
rst,
clk,
l_clk,
input rst,
input clk,
output l_clk,
// receive data path interface
adc_valid,
adc_data,
adc_status,
adc_r1_mode,
adc_ddr_edgesel,
output reg adc_valid,
output reg [47:0] adc_data,
output reg adc_status,
input adc_r1_mode,
input adc_ddr_edgesel,
// transmit data path interface
dac_valid,
dac_data,
dac_r1_mode,
input dac_valid,
input [47:0] dac_data,
input dac_clksel,
input dac_r1_mode,
// tdd interface
tdd_enable,
tdd_txnrx,
tdd_mode,
input tdd_enable,
input tdd_txnrx,
input tdd_mode,
// delay interface
up_clk,
up_enable,
up_txnrx,
up_adc_dld,
up_adc_dwdata,
up_adc_drdata,
up_dac_dld,
up_dac_dwdata,
up_dac_drdata,
delay_clk,
delay_rst,
delay_locked);
input mmcm_rst,
input up_clk,
input up_rstn,
input up_enable,
input up_txnrx,
input [ 6:0] up_adc_dld,
input [34:0] up_adc_dwdata,
output [34:0] up_adc_drdata,
input [ 9:0] up_dac_dld,
input [49:0] up_dac_dwdata,
output [49:0] up_dac_drdata,
input delay_clk,
input delay_rst,
output delay_locked,
// this parameter controls the buffer type based on the target device.
// drp interface
parameter DEVICE_TYPE = 0;
parameter DAC_IODELAY_ENABLE = 0;
parameter IO_DELAY_GROUP = "dev_if_delay_group";
// physical interface (receive)
input rx_clk_in_p;
input rx_clk_in_n;
input rx_frame_in_p;
input rx_frame_in_n;
input [ 5:0] rx_data_in_p;
input [ 5:0] rx_data_in_n;
// physical interface (transmit)
output tx_clk_out_p;
output tx_clk_out_n;
output tx_frame_out_p;
output tx_frame_out_n;
output [ 5:0] tx_data_out_p;
output [ 5:0] tx_data_out_n;
// ensm control
output enable;
output txnrx;
// clock (common to both receive and transmit)
input rst;
input clk;
output l_clk;
// receive data path interface
output adc_valid;
output [47:0] adc_data;
output adc_status;
input adc_r1_mode;
input adc_ddr_edgesel;
// transmit data path interface
input dac_valid;
input [47:0] dac_data;
input dac_r1_mode;
// tdd interface
input tdd_enable;
input tdd_txnrx;
input tdd_mode;
// delay interface
input up_clk;
input up_enable;
input up_txnrx;
input [ 6:0] up_adc_dld;
input [34:0] up_adc_dwdata;
output [34:0] up_adc_drdata;
input [ 9:0] up_dac_dld;
input [49:0] up_dac_dwdata;
output [49:0] up_dac_drdata;
input delay_clk;
input delay_rst;
output delay_locked;
input up_drp_sel,
input up_drp_wr,
input [11:0] up_drp_addr,
input [31:0] up_drp_wdata,
output [31:0] up_drp_rdata,
output up_drp_ready,
output up_drp_locked);
// internal registers
@ -185,9 +128,6 @@ module axi_ad9361_dev_if (
reg rx_error_r2 = 'd0;
reg rx_valid_r2 = 'd0;
reg [23:0] rx_data_r2 = 'd0;
reg adc_valid = 'd0;
reg [47:0] adc_data = 'd0;
reg adc_status = 'd0;
reg tx_data_sel = 'd0;
reg [47:0] tx_data = 'd0;
reg [ 3:0] tx_frame = 'd0;

599
library/axi_ad9361/axi_ad9361.v
View File

@ -37,249 +37,174 @@
`timescale 1ns/100ps
module axi_ad9361 (
// physical interface (receive)
rx_clk_in_p,
rx_clk_in_n,
rx_frame_in_p,
rx_frame_in_n,
rx_data_in_p,
rx_data_in_n,
// physical interface (transmit)
tx_clk_out_p,
tx_clk_out_n,
tx_frame_out_p,
tx_frame_out_n,
tx_data_out_p,
tx_data_out_n,
// ensm control
enable,
txnrx,
// transmit master/slave
dac_sync_in,
dac_sync_out,
// tdd sync (1s pulse)
tdd_sync,
tdd_sync_en,
tdd_terminal_type,
// delay clock
delay_clk,
// master interface
l_clk,
clk,
rst,
// dma interface
adc_enable_i0,
adc_valid_i0,
adc_data_i0,
adc_enable_q0,
adc_valid_q0,
adc_data_q0,
adc_enable_i1,
adc_valid_i1,
adc_data_i1,
adc_enable_q1,
adc_valid_q1,
adc_data_q1,
adc_dovf,
adc_dunf,
adc_r1_mode,
dac_enable_i0,
dac_valid_i0,
dac_data_i0,
dac_enable_q0,
dac_valid_q0,
dac_data_q0,
dac_enable_i1,
dac_valid_i1,
dac_data_i1,
dac_enable_q1,
dac_valid_q1,
dac_data_q1,
dac_dovf,
dac_dunf,
dac_r1_mode,
// axi interface
s_axi_aclk,
s_axi_aresetn,
s_axi_awvalid,
s_axi_awaddr,
s_axi_awprot,
s_axi_awready,
s_axi_wvalid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wready,
s_axi_bvalid,
s_axi_bresp,
s_axi_bready,
s_axi_arvalid,
s_axi_araddr,
s_axi_arprot,
s_axi_arready,
s_axi_rvalid,
s_axi_rdata,
s_axi_rresp,
s_axi_rready,
// gpio
up_enable,
up_txnrx,
up_dac_gpio_in,
up_dac_gpio_out,
up_adc_gpio_in,
up_adc_gpio_out,
// chipscope signals
tdd_dbg);
module axi_ad9361 #(
// parameters
parameter ID = 0;
parameter DEVICE_TYPE = 0;
parameter DAC_IODELAY_ENABLE = 0;
parameter IO_DELAY_GROUP = "dev_if_delay_group";
parameter DAC_DATAPATH_DISABLE = 0;
parameter ADC_DATAPATH_DISABLE = 0;
parameter ID = 0,
parameter MODE_1R1T = 0,
parameter DEVICE_TYPE = 0,
parameter TDD_DISABLE = 0,
parameter CMOS_OR_LVDS_N = 0,
parameter ADC_DATAPATH_DISABLE = 0,
parameter ADC_USERPORTS_DISABLE = 0,
parameter ADC_DATAFORMAT_DISABLE = 0,
parameter ADC_DCFILTER_DISABLE = 0,
parameter ADC_IQCORRECTION_DISABLE = 0,
parameter DAC_IODELAY_ENABLE = 0,
parameter DAC_DATAPATH_DISABLE = 0,
parameter DAC_DDS_DISABLE = 0,
parameter DAC_USERPORTS_DISABLE = 0,
parameter DAC_IQCORRECTION_DISABLE = 0,
parameter IO_DELAY_GROUP = "dev_if_delay_group") (
// physical interface (receive)
// physical interface (receive-lvds)
input rx_clk_in_p;
input rx_clk_in_n;
input rx_frame_in_p;
input rx_frame_in_n;
input [ 5:0] rx_data_in_p;
input [ 5:0] rx_data_in_n;
input rx_clk_in_p,
input rx_clk_in_n,
input rx_frame_in_p,
input rx_frame_in_n,
input [ 5:0] rx_data_in_p,
input [ 5:0] rx_data_in_n,
// physical interface (transmit)
// physical interface (receive-cmos)
output tx_clk_out_p;
output tx_clk_out_n;
output tx_frame_out_p;
output tx_frame_out_n;
output [ 5:0] tx_data_out_p;
output [ 5:0] tx_data_out_n;
input rx_clk_in,
input rx_frame_in,
input [11:0] rx_data_in,
// physical interface (transmit-lvds)
output tx_clk_out_p,
output tx_clk_out_n,
output tx_frame_out_p,
output tx_frame_out_n,
output [ 5:0] tx_data_out_p,
output [ 5:0] tx_data_out_n,
// physical interface (transmit-cmos)
output tx_clk_out,
output tx_frame_out,
output [11:0] tx_data_out,
// ensm control
output enable;
output txnrx;
output enable,
output txnrx,
// transmit master/slave
input dac_sync_in;
output dac_sync_out;
input dac_sync_in,
output dac_sync_out,
// tdd sync
input tdd_sync;
output tdd_sync_en;
output tdd_terminal_type;
input tdd_sync,
output tdd_sync_cntr,
// delay clock
input delay_clk;
input delay_clk,
// master interface
output l_clk;
input clk;
output rst;
output l_clk,
input clk,
output rst,
// dma interface
output adc_enable_i0;
output adc_valid_i0;
output [15:0] adc_data_i0;
output adc_enable_q0;
output adc_valid_q0;
output [15:0] adc_data_q0;
output adc_enable_i1;
output adc_valid_i1;
output [15:0] adc_data_i1;
output adc_enable_q1;
output adc_valid_q1;
output [15:0] adc_data_q1;
input adc_dovf;
input adc_dunf;
output adc_r1_mode;
output adc_enable_i0,
output adc_valid_i0,
output [15:0] adc_data_i0,
output adc_enable_q0,
output adc_valid_q0,
output [15:0] adc_data_q0,
output adc_enable_i1,
output adc_valid_i1,
output [15:0] adc_data_i1,
output adc_enable_q1,
output adc_valid_q1,
output [15:0] adc_data_q1,
input adc_dovf,
input adc_dunf,
output adc_r1_mode,
output dac_enable_i0;
output dac_valid_i0;
input [15:0] dac_data_i0;
output dac_enable_q0;
output dac_valid_q0;
input [15:0] dac_data_q0;
output dac_enable_i1;
output dac_valid_i1;
input [15:0] dac_data_i1;
output dac_enable_q1;
output dac_valid_q1;
input [15:0] dac_data_q1;
input dac_dovf;
input dac_dunf;
output dac_r1_mode;
output dac_enable_i0,
output dac_valid_i0,
input [15:0] dac_data_i0,
output dac_enable_q0,
output dac_valid_q0,
input [15:0] dac_data_q0,
output dac_enable_i1,
output dac_valid_i1,
input [15:0] dac_data_i1,
output dac_enable_q1,
output dac_valid_q1,
input [15:0] dac_data_q1,
input dac_dovf,
input dac_dunf,
output dac_r1_mode,
// axi interface
input s_axi_aclk;
input s_axi_aresetn;
input s_axi_awvalid;
input [31:0] s_axi_awaddr;
input [ 2:0] s_axi_awprot;
output s_axi_awready;
input s_axi_wvalid;
input [31:0] s_axi_wdata;
input [ 3:0] s_axi_wstrb;
output s_axi_wready;
output s_axi_bvalid;
output [ 1:0] s_axi_bresp;
input s_axi_bready;
input s_axi_arvalid;
input [31:0] s_axi_araddr;
input [ 2:0] s_axi_arprot;
output s_axi_arready;
output s_axi_rvalid;
output [31:0] s_axi_rdata;
output [ 1:0] s_axi_rresp;
input s_axi_rready;
input s_axi_aclk,
input s_axi_aresetn,
input s_axi_awvalid,
input [31:0] s_axi_awaddr,
input [ 2:0] s_axi_awprot,
output s_axi_awready,
input s_axi_wvalid,
input [31:0] s_axi_wdata,
input [ 3:0] s_axi_wstrb,
output s_axi_wready,
output s_axi_bvalid,
output [ 1:0] s_axi_bresp,
input s_axi_bready,
input s_axi_arvalid,
input [31:0] s_axi_araddr,
input [ 2:0] s_axi_arprot,
output s_axi_arready,
output s_axi_rvalid,
output [31:0] s_axi_rdata,
output [ 1:0] s_axi_rresp,
input s_axi_rready,
// gpio
input up_enable;
input up_txnrx;
input [31:0] up_dac_gpio_in;
output [31:0] up_dac_gpio_out;
input [31:0] up_adc_gpio_in;
output [31:0] up_adc_gpio_out;
input up_enable,
input up_txnrx,
input [31:0] up_dac_gpio_in,
output [31:0] up_dac_gpio_out,
input [31:0] up_adc_gpio_in,
output [31:0] up_adc_gpio_out);
// chipscope signals
// derived parameters
output [41:0] tdd_dbg;
localparam ADC_USERPORTS_DISABLE_INT = (ADC_DATAPATH_DISABLE == 1) ? 1 : ADC_USERPORTS_DISABLE;
localparam ADC_DATAFORMAT_DISABLE_INT = (ADC_DATAPATH_DISABLE == 1) ? 1 : ADC_DATAFORMAT_DISABLE;
localparam ADC_DCFILTER_DISABLE_INT = (ADC_DATAPATH_DISABLE == 1) ? 1 : ADC_DCFILTER_DISABLE;
localparam ADC_IQCORRECTION_DISABLE_INT = (ADC_DATAPATH_DISABLE == 1) ? 1 : ADC_IQCORRECTION_DISABLE;
localparam DAC_DDS_DISABLE_INT = (DAC_DATAPATH_DISABLE == 1) ? 1 : DAC_DDS_DISABLE;
localparam DAC_USERPORTS_DISABLE_INT = (DAC_DATAPATH_DISABLE == 1) ? 1 : DAC_USERPORTS_DISABLE;
localparam DAC_DELAYCNTRL_DISABLE_INT = (DAC_IODELAY_ENABLE == 1) ? 0 : 1;
localparam DAC_IQCORRECTION_DISABLE_INT = (DAC_DATAPATH_DISABLE == 1) ? 1 : DAC_IQCORRECTION_DISABLE;
// internal registers
reg adc_valid_i0_int = 'd0;
reg adc_valid_q0_int = 'd0;
reg adc_valid_i1_int = 'd0;
reg adc_valid_q1_int = 'd0;
reg [15:0] adc_data_i0_int = 'd0;
reg [15:0] adc_data_q0_int = 'd0;
reg [15:0] adc_data_i1_int = 'd0;
reg [15:0] adc_data_q1_int = 'd0;
reg dac_valid_i0_int = 'd0;
reg dac_valid_q0_int = 'd0;
reg dac_valid_i1_int = 'd0;
reg dac_valid_q1_int = 'd0;
reg up_wack = 'd0;
reg up_rack = 'd0;
reg [31:0] up_rdata = 'd0;
@ -288,26 +213,40 @@ module axi_ad9361 (
wire up_clk;
wire up_rstn;
wire mmcm_rst;
wire delay_rst;
// internal signals
wire adc_ddr_edgesel;
wire adc_ddr_edgesel_s;
wire adc_valid_s;
wire adc_valid_i0_s;
wire adc_valid_q0_s;
wire adc_valid_i1_s;
wire adc_valid_q1_s;
wire [15:0] adc_data_i0_s;
wire [15:0] adc_data_q0_s;
wire [15:0] adc_data_i1_s;
wire [15:0] adc_data_q1_s;
wire [47:0] adc_data_s;
wire adc_status_s;
wire dac_clksel_s;
wire dac_valid_s;
wire [47:0] dac_data_s;
wire dac_valid_i0_s;
wire dac_valid_q0_s;
wire dac_valid_i1_s;
wire dac_valid_q1_s;
wire [ 6:0] up_adc_dld_s;
wire [34:0] up_adc_dwdata_s;
wire [34:0] up_adc_drdata_s;
wire [ 9:0] up_dac_dld_s;
wire [49:0] up_dac_dwdata_s;
wire [49:0] up_dac_drdata_s;
wire dac_data_i0_s;
wire dac_data_q0_s;
wire dac_data_i1_s;
wire dac_data_q1_s;
wire [12:0] up_adc_dld_s;
wire [64:0] up_adc_dwdata_s;
wire [64:0] up_adc_drdata_s;
wire [15:0] up_dac_dld_s;
wire [79:0] up_dac_dwdata_s;
wire [79:0] up_dac_drdata_s;
wire delay_locked_s;
wire up_wreq_s;
wire [13:0] up_waddr_s;
@ -323,16 +262,23 @@ module axi_ad9361 (
wire up_wack_tdd_s;
wire up_rack_tdd_s;
wire [31:0] up_rdata_tdd_s;
wire tdd_tx_dp_en_s;
wire tdd_enable_s;
wire tdd_txnrx_s;
wire tdd_mode_s;
wire tdd_tx_valid_s;
wire tdd_rx_valid_s;
wire tdd_rx_vco_en_s;
wire tdd_tx_vco_en_s;
wire tdd_rx_rf_en_s;
wire tdd_tx_rf_en_s;
wire [ 7:0] tdd_status_s;
wire tdd_enable_s;
wire tdd_txnrx_s;
wire tdd_mode_s;
wire up_drp_sel;
wire up_drp_wr;
wire [11:0] up_drp_addr;
wire [31:0] up_drp_wdata;
wire [31:0] up_drp_rdata;
wire up_drp_ready;
wire up_drp_locked;
// signal name changes
@ -355,7 +301,74 @@ module axi_ad9361 (
// device interface
axi_ad9361_dev_if #(
generate
if (CMOS_OR_LVDS_N == 1) begin
assign tx_clk_out_p = 1'd0;
assign tx_clk_out_n = 1'd1;
assign tx_frame_out_p = 1'd0;
assign tx_frame_out_n = 1'd0;
assign tx_data_out_p = 6'h00;
assign tx_data_out_n = 6'h3f;
assign up_drp_rdata = 32'd0;
assign up_drp_ready = 1'd0;
assign up_drp_locked = 1'd1;
axi_ad9361_cmos_if #(
.DEVICE_TYPE (DEVICE_TYPE),
.DAC_IODELAY_ENABLE (DAC_IODELAY_ENABLE),
.IO_DELAY_GROUP (IO_DELAY_GROUP))
i_dev_if (
.rx_clk_in (rx_clk_in),
.rx_frame_in (rx_frame_in),
.rx_data_in (rx_data_in),
.tx_clk_out (tx_clk_out),
.tx_frame_out (tx_frame_out),
.tx_data_out (tx_data_out),
.enable (enable),
.txnrx (txnrx),
.rst (rst),
.clk (clk),
.l_clk (l_clk),
.adc_valid (adc_valid_s),
.adc_data (adc_data_s),
.adc_status (adc_status_s),
.adc_r1_mode (adc_r1_mode),
.adc_ddr_edgesel (adc_ddr_edgesel_s),
.dac_valid (dac_valid_s),
.dac_data (dac_data_s),
.dac_clksel (dac_clksel_s),
.dac_r1_mode (dac_r1_mode),
.tdd_enable (tdd_enable_s),
.tdd_txnrx (tdd_txnrx_s),
.tdd_mode (tdd_mode_s),
.mmcm_rst (mmcm_rst),
.up_clk (up_clk),
.up_enable (up_enable),
.up_txnrx (up_txnrx),
.up_adc_dld (up_adc_dld_s),
.up_adc_dwdata (up_adc_dwdata_s),
.up_adc_drdata (up_adc_drdata_s),
.up_dac_dld (up_dac_dld_s),
.up_dac_dwdata (up_dac_dwdata_s),
.up_dac_drdata (up_dac_drdata_s),
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_locked (delay_locked_s));
end
endgenerate
generate
if (CMOS_OR_LVDS_N == 0) begin
assign tx_clk_out = 1'd0;
assign tx_frame_out = 1'd0;
assign tx_data_out = 12'd0;
assign up_adc_drdata_s[64:35] = 30'd0;
assign up_dac_drdata_s[79:50] = 30'd0;
axi_ad9361_lvds_if #(
.DEVICE_TYPE (DEVICE_TYPE),
.DAC_IODELAY_ENABLE (DAC_IODELAY_ENABLE),
.IO_DELAY_GROUP (IO_DELAY_GROUP))
@ -381,28 +394,97 @@ module axi_ad9361 (
.adc_data (adc_data_s),
.adc_status (adc_status_s),
.adc_r1_mode (adc_r1_mode),
.adc_ddr_edgesel (adc_ddr_edgesel),
.adc_ddr_edgesel (adc_ddr_edgesel_s),
.dac_valid (dac_valid_s),
.dac_data (dac_data_s),
.dac_clksel (dac_clksel_s),
.dac_r1_mode (dac_r1_mode),
.tdd_enable (tdd_enable_s),
.tdd_txnrx (tdd_txnrx_s),
.tdd_mode (tdd_mode_s),
.mmcm_rst (mmcm_rst),
.up_clk (up_clk),
.up_enable (up_enable),
.up_txnrx (up_txnrx),
.up_adc_dld (up_adc_dld_s),
.up_adc_dwdata (up_adc_dwdata_s),
.up_adc_drdata (up_adc_drdata_s),
.up_dac_dld (up_dac_dld_s),
.up_dac_dwdata (up_dac_dwdata_s),
.up_dac_drdata (up_dac_drdata_s),
.up_adc_dld (up_adc_dld_s[6:0]),
.up_adc_dwdata (up_adc_dwdata_s[34:0]),
.up_adc_drdata (up_adc_drdata_s[34:0]),
.up_dac_dld (up_dac_dld_s[9:0]),
.up_dac_dwdata (up_dac_dwdata_s[49:0]),
.up_dac_drdata (up_dac_drdata_s[49:0]),
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_locked (delay_locked_s));
.delay_locked (delay_locked_s),
.up_drp_sel (up_drp_sel),
.up_drp_wr (up_drp_wr),
.up_drp_addr (up_drp_addr),
.up_drp_wdata (up_drp_wdata),
.up_drp_rdata (up_drp_rdata),
.up_drp_ready (up_drp_ready),
.up_drp_locked(up_drp_locked));
end
endgenerate
// TDD interface
assign adc_valid_i0 = adc_valid_i0_int;
assign adc_valid_q0 = adc_valid_q0_int;
assign adc_valid_i1 = adc_valid_i1_int;
assign adc_valid_q1 = adc_valid_q1_int;
always @(posedge clk) begin
adc_valid_i0_int <= tdd_rx_valid_s & adc_valid_i0_s;
adc_valid_q0_int <= tdd_rx_valid_s & adc_valid_q0_s;
adc_valid_i1_int <= tdd_rx_valid_s & adc_valid_i1_s;
adc_valid_q1_int <= tdd_rx_valid_s & adc_valid_q1_s;
end
assign adc_data_i0 = adc_data_i0_int;
assign adc_data_q0 = adc_data_q0_int;
assign adc_data_i1 = adc_data_i1_int;
assign adc_data_q1 = adc_data_q1_int;
always @(posedge clk) begin
adc_data_i0_int <= adc_data_i0_s;
adc_data_q0_int <= adc_data_q0_s;
adc_data_i1_int <= adc_data_i1_s;
adc_data_q1_int <= adc_data_q1_s;
end
assign dac_valid_i0 = dac_valid_i0_int;
assign dac_valid_q0 = dac_valid_q0_int;
assign dac_valid_i1 = dac_valid_i1_int;
assign dac_valid_q1 = dac_valid_q1_int;
always @(posedge clk) begin
dac_valid_i0_int <= tdd_tx_valid_s & dac_valid_i0_s;
dac_valid_q0_int <= tdd_tx_valid_s & dac_valid_q0_s;
dac_valid_i1_int <= tdd_tx_valid_s & dac_valid_i1_s;
dac_valid_q1_int <= tdd_tx_valid_s & dac_valid_q1_s;
end
// tdd
generate
if (TDD_DISABLE == 1) begin
assign tdd_enable_s = 1'b0;
assign tdd_txnrx_s = 1'b0;
assign tdd_txnrx_s = 1'b0;
assign tdd_mode_s = 1'b0;
assign tdd_rx_vco_en_s = 1'b0;
assign tdd_tx_vco_en_s = 1'b0;
assign tdd_rx_rf_en_s = 1'b0;
assign tdd_tx_rf_en_s = 1'b0;
assign tdd_status_s = 8'd0;
assign tdd_sync_cntr = 1'b0;
assign tdd_tx_valid_s = 1'b1;
assign tdd_rx_valid_s = 1'b1;
assign up_wack_tdd_s = 1'b0;
assign up_rack_tdd_s = 1'b0;
assign up_rdata_tdd_s = 32'b0;
end
endgenerate
generate
if (TDD_DISABLE == 0) begin
axi_ad9361_tdd_if #(.LEVEL_OR_PULSE_N(1)) i_tdd_if (
.clk (clk),
.rst (rst),
@ -414,8 +496,6 @@ module axi_ad9361 (
.ad9361_enable (tdd_enable_s),
.ad9361_tdd_status (tdd_status_s));
// TDD control
axi_ad9361_tdd i_tdd (
.clk (clk),
.rst (rst),
@ -426,24 +506,9 @@ module axi_ad9361 (
.tdd_enabled (tdd_mode_s),
.tdd_status (tdd_status_s),
.tdd_sync (tdd_sync),
.tdd_sync_en (tdd_sync_en),
.tdd_terminal_type (tdd_terminal_type),
.tx_valid_i0 (dac_valid_i0_s),
.tx_valid_q0 (dac_valid_q0_s),
.tx_valid_i1 (dac_valid_i1_s),
.tx_valid_q1 (dac_valid_q1_s),
.tdd_tx_valid_i0 (dac_valid_i0),
.tdd_tx_valid_q0 (dac_valid_q0),
.tdd_tx_valid_i1 (dac_valid_i1),
.tdd_tx_valid_q1 (dac_valid_q1),
.rx_valid_i0 (adc_valid_i0_s),
.rx_valid_q0 (adc_valid_q0_s),
.rx_valid_i1 (adc_valid_i1_s),
.rx_valid_q1 (adc_valid_q1_s),
.tdd_rx_valid_i0 (adc_valid_i0),
.tdd_rx_valid_q0 (adc_valid_q0),
.tdd_rx_valid_i1 (adc_valid_i1),
.tdd_rx_valid_q1 (adc_valid_q1),
.tdd_sync_cntr (tdd_sync_cntr),
.tdd_tx_valid (tdd_tx_valid_s),
.tdd_rx_valid (tdd_rx_valid_s),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq_s),
@ -453,22 +518,28 @@ module axi_ad9361 (
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_tdd_s),
.up_rack (up_rack_tdd_s),
.tdd_dbg (tdd_dbg));
.up_rack (up_rack_tdd_s));
end
endgenerate
// receive
axi_ad9361_rx #(
.ID (ID),
.DATAPATH_DISABLE (ADC_DATAPATH_DISABLE))
.MODE_1R1T (MODE_1R1T),
.USERPORTS_DISABLE (ADC_USERPORTS_DISABLE_INT),
.DATAFORMAT_DISABLE (ADC_DATAFORMAT_DISABLE_INT),
.DCFILTER_DISABLE (ADC_DCFILTER_DISABLE_INT),
.IQCORRECTION_DISABLE (ADC_IQCORRECTION_DISABLE_INT))
i_rx (
.mmcm_rst (mmcm_rst),
.adc_rst (rst),
.adc_clk (clk),
.adc_valid (adc_valid_s),
.adc_data (adc_data_s),
.adc_status (adc_status_s),
.adc_r1_mode (adc_r1_mode),
.adc_ddr_edgesel (adc_ddr_edgesel),
.adc_ddr_edgesel (adc_ddr_edgesel_s),
.dac_data (dac_data_s),
.up_dld (up_adc_dld_s),
.up_dwdata (up_adc_dwdata_s),
@ -478,16 +549,16 @@ module axi_ad9361 (
.delay_locked (delay_locked_s),
.adc_enable_i0 (adc_enable_i0),
.adc_valid_i0 (adc_valid_i0_s),
.adc_data_i0 (adc_data_i0),
.adc_data_i0 (adc_data_i0_s),
.adc_enable_q0 (adc_enable_q0),
.adc_valid_q0 (adc_valid_q0_s),
.adc_data_q0 (adc_data_q0),
.adc_data_q0 (adc_data_q0_s),
.adc_enable_i1 (adc_enable_i1),
.adc_valid_i1 (adc_valid_i1_s),
.adc_data_i1 (adc_data_i1),
.adc_data_i1 (adc_data_i1_s),
.adc_enable_q1 (adc_enable_q1),
.adc_valid_q1 (adc_valid_q1_s),
.adc_data_q1 (adc_data_q1),
.adc_data_q1 (adc_data_q1_s),
.adc_dovf (adc_dovf),
.adc_dunf (adc_dunf),
.up_adc_gpio_in (up_adc_gpio_in),
@ -501,17 +572,29 @@ module axi_ad9361 (
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_rx_s),
.up_rack (up_rack_rx_s));
.up_rack (up_rack_rx_s),
.up_drp_sel (up_drp_sel),
.up_drp_wr (up_drp_wr),
.up_drp_addr (up_drp_addr),
.up_drp_wdata (up_drp_wdata),
.up_drp_rdata (up_drp_rdata),
.up_drp_ready (up_drp_ready),
.up_drp_locked(up_drp_locked));
// transmit
axi_ad9361_tx #(
.ID (ID),
.DATAPATH_DISABLE (DAC_DATAPATH_DISABLE))
.MODE_1R1T (MODE_1R1T),
.DDS_DISABLE (DAC_DDS_DISABLE_INT),
.USERPORTS_DISABLE (DAC_USERPORTS_DISABLE_INT),
.DELAYCNTRL_DISABLE (DAC_DELAYCNTRL_DISABLE_INT),
.IQCORRECTION_DISABLE (DAC_IQCORRECTION_DISABLE_INT))
i_tx (
.dac_clk (clk),
.dac_valid (dac_valid_s),
.dac_data (dac_data_s),
.dac_clksel (dac_clksel_s),
.dac_r1_mode (dac_r1_mode),
.adc_data (adc_data_s),
.up_dld (up_dac_dld_s),

7
library/axi_ad9361/axi_ad9361_constr.sdc Normal file
View File

@ -0,0 +1,7 @@
set_false_path -from [get_registers *i_dev_if|up_enable_int*] -to [get_registers *i_dev_if|enable_up_m1*]
set_false_path -from [get_registers *i_dev_if|up_txnrx_int*] -to [get_registers *i_dev_if|txnrx_up_m1*]
set_false_path -from [get_registers *up_xfer_cntrl:i_xfer_tdd_control|d_xfer_toggle*] -to [get_registers *up_xfer_cntrl:i_xfer_tdd_control|up_xfer_state_m1*]
set_false_path -from [get_registers *up_xfer_cntrl:i_xfer_tdd_control|up_xfer_toggle*] -to [get_registers *up_xfer_cntrl:i_xfer_tdd_control|d_xfer_toggle_m1*]
set_false_path -from [get_registers *up_xfer_cntrl:i_xfer_tdd_control|up_xfer_data*] -to [get_registers *up_xfer_cntrl:i_xfer_tdd_control|d_data_cntrl*]

361
library/axi_ad9361/axi_ad9361_hw.tcl
View File

@ -1,185 +1,234 @@
package require -exact qsys 13.0
source ../scripts/adi_env.tcl
source ../scripts/adi_ip_alt.tcl
set_module_property NAME axi_ad9361
set_module_property DESCRIPTION "AXI AD9361 Interface"
set_module_property VERSION 1.0
set_module_property GROUP "Analog Devices"
set_module_property DISPLAY_NAME axi_ad9361
# files
add_fileset quartus_synth QUARTUS_SYNTH "" "Quartus Synthesis"
set_fileset_property quartus_synth TOP_LEVEL axi_ad9361
add_fileset_file ad_rst.v VERILOG PATH $ad_hdl_dir/library/common/ad_rst.v
add_fileset_file ad_lvds_clk.v VERILOG PATH $ad_hdl_dir/library/common/altera/ad_lvds_clk.v
add_fileset_file ad_lvds_in.v VERILOG PATH $ad_hdl_dir/library/common/altera/ad_lvds_in.v
add_fileset_file ad_lvds_out.v VERILOG PATH $ad_hdl_dir/library/common/altera/ad_lvds_out.v
add_fileset_file MULT_MACRO.v VERILOG PATH $ad_hdl_dir/library/common/altera/MULT_MACRO.v
add_fileset_file DSP48E1.v VERILOG PATH $ad_hdl_dir/library/common/altera/DSP48E1.v
add_fileset_file ad_mul.v VERILOG PATH $ad_hdl_dir/library/common/ad_mul.v
add_fileset_file ad_pnmon.v VERILOG PATH $ad_hdl_dir/library/common/ad_pnmon.v
add_fileset_file ad_dds_sine.v VERILOG PATH $ad_hdl_dir/library/common/ad_dds_sine.v
add_fileset_file ad_dds_1.v VERILOG PATH $ad_hdl_dir/library/common/ad_dds_1.v
add_fileset_file ad_dds.v VERILOG PATH $ad_hdl_dir/library/common/ad_dds.v
add_fileset_file ad_datafmt.v VERILOG PATH $ad_hdl_dir/library/common/ad_datafmt.v
add_fileset_file ad_dcfilter.v VERILOG PATH $ad_hdl_dir/library/common/ad_dcfilter.v
add_fileset_file ad_iqcor.v VERILOG PATH $ad_hdl_dir/library/common/ad_iqcor.v
add_fileset_file up_axi.v VERILOG PATH $ad_hdl_dir/library/common/up_axi.v
add_fileset_file up_xfer_cntrl.v VERILOG PATH $ad_hdl_dir/library/common/up_xfer_cntrl.v
add_fileset_file up_xfer_status.v VERILOG PATH $ad_hdl_dir/library/common/up_xfer_status.v
add_fileset_file up_clock_mon.v VERILOG PATH $ad_hdl_dir/library/common/up_clock_mon.v
add_fileset_file up_delay_cntrl.v VERILOG PATH $ad_hdl_dir/library/common/up_delay_cntrl.v
add_fileset_file up_adc_common.v VERILOG PATH $ad_hdl_dir/library/common/up_adc_common.v
add_fileset_file up_adc_channel.v VERILOG PATH $ad_hdl_dir/library/common/up_adc_channel.v
add_fileset_file up_dac_common.v VERILOG PATH $ad_hdl_dir/library/common/up_dac_common.v
add_fileset_file up_dac_channel.v VERILOG PATH $ad_hdl_dir/library/common/up_dac_channel.v
add_fileset_file up_tdd_cntrl.v VERILOG PATH $ad_hdl_dir/library/common/up_tdd_cntrl.v
add_fileset_file ad_tdd_control.v VERILOG PATH $ad_hdl_dir/library/common/ad_tdd_control.v
add_fileset_file ad_addsub.v VERILOG PATH $ad_hdl_dir/library/common/ad_addsub.v
add_fileset_file axi_ad9361_alt_lvds_tx.v VERILOG PATH axi_ad9361_alt_lvds_tx.v
add_fileset_file axi_ad9361_alt_lvds_rx.v VERILOG PATH axi_ad9361_alt_lvds_rx.v
add_fileset_file axi_ad9361_dev_if_alt.v VERILOG PATH axi_ad9361_dev_if_alt.v
add_fileset_file axi_ad9361_rx_pnmon.v VERILOG PATH axi_ad9361_rx_pnmon.v
add_fileset_file axi_ad9361_rx_channel.v VERILOG PATH axi_ad9361_rx_channel.v
add_fileset_file axi_ad9361_rx.v VERILOG PATH axi_ad9361_rx.v
add_fileset_file axi_ad9361_tx_channel.v VERILOG PATH axi_ad9361_tx_channel.v
add_fileset_file axi_ad9361_tx.v VERILOG PATH axi_ad9361_tx.v
add_fileset_file axi_ad9361_tdd.v VERILOG PATH axi_ad9361_tdd.v
add_fileset_file axi_ad9361_tdd_if.v VERILOG PATH axi_ad9361_tdd_if.v
add_fileset_file axi_ad9361.v VERILOG PATH axi_ad9361.v TOP_LEVEL_FILE
ad_ip_create axi_ad9361 {AXI AD9361 Interface} axi_ad9361_elab
ad_ip_files axi_ad9361 [list\
$ad_hdl_dir/library/altera/common/ad_lvds_clk.v \
$ad_hdl_dir/library/altera/common/ad_lvds_in.v \
$ad_hdl_dir/library/altera/common/ad_lvds_out.v \
$ad_hdl_dir/library/altera/common/ad_mul.v \
$ad_hdl_dir/library/altera/common/ad_dcfilter.v \
$ad_hdl_dir/library/common/ad_rst.v \
$ad_hdl_dir/library/common/ad_pnmon.v \
$ad_hdl_dir/library/common/ad_dds_sine.v \
$ad_hdl_dir/library/common/ad_dds_1.v \
$ad_hdl_dir/library/common/ad_dds.v \
$ad_hdl_dir/library/common/ad_datafmt.v \
$ad_hdl_dir/library/common/ad_iqcor.v \
$ad_hdl_dir/library/common/ad_addsub.v \
$ad_hdl_dir/library/common/ad_tdd_control.v \
$ad_hdl_dir/library/common/up_axi.v \
$ad_hdl_dir/library/common/up_xfer_cntrl.v \
$ad_hdl_dir/library/common/up_xfer_status.v \
$ad_hdl_dir/library/common/up_clock_mon.v \
$ad_hdl_dir/library/common/up_delay_cntrl.v \
$ad_hdl_dir/library/common/up_adc_common.v \
$ad_hdl_dir/library/common/up_adc_channel.v \
$ad_hdl_dir/library/common/up_dac_common.v \
$ad_hdl_dir/library/common/up_dac_channel.v \
$ad_hdl_dir/library/common/up_tdd_cntrl.v \
altera/axi_ad9361_alt_lvds_tx.v \
altera/axi_ad9361_alt_lvds_rx.v \
altera/axi_ad9361_lvds_if.v \
axi_ad9361_rx_pnmon.v \
axi_ad9361_rx_channel.v \
axi_ad9361_rx.v \
axi_ad9361_tx_channel.v \
axi_ad9361_tx.v \
axi_ad9361_tdd.v \
axi_ad9361_tdd_if.v \
axi_ad9361.v \
$ad_hdl_dir/library/common/ad_axi_ip_constr.sdc \
axi_ad9361_constr.sdc]
# parameters
add_parameter ID INTEGER 0
set_parameter_property ID DEFAULT_VALUE 0
set_parameter_property ID DISPLAY_NAME ID
set_parameter_property ID TYPE INTEGER
set_parameter_property ID UNITS None
set_parameter_property ID HDL_PARAMETER true
ad_ip_parameter DEVICE_FAMILY STRING {Arria 10}
ad_ip_parameter ID INTEGER 0
ad_ip_parameter MODE_1R1T INTEGER 0
ad_ip_parameter DEVICE_TYPE INTEGER 0
ad_ip_parameter TDD_DISABLE INTEGER 0
ad_ip_parameter CMOS_OR_LVDS_N INTEGER 0
ad_ip_parameter ADC_DATAPATH_DISABLE INTEGER 0
ad_ip_parameter ADC_USERPORTS_DISABLE INTEGER 0
ad_ip_parameter ADC_DATAFORMAT_DISABLE INTEGER 0
ad_ip_parameter ADC_DCFILTER_DISABLE INTEGER 0
ad_ip_parameter ADC_IQCORRECTION_DISABLE INTEGER 0
ad_ip_parameter DAC_IODELAY_ENABLE INTEGER 0
ad_ip_parameter DAC_DATAPATH_DISABLE INTEGER 0
ad_ip_parameter DAC_DDS_DISABLE INTEGER 0
ad_ip_parameter DAC_USERPORTS_DISABLE INTEGER 0
ad_ip_parameter DAC_IQCORRECTION_DISABLE INTEGER 0
ad_ip_parameter IO_DELAY_GROUP STRING {dev_if_delay_group}
add_parameter DEVICE_TYPE INTEGER 0
set_parameter_property DEVICE_TYPE DEFAULT_VALUE 0
set_parameter_property DEVICE_TYPE DISPLAY_NAME DEVICE_TYPE
set_parameter_property DEVICE_TYPE TYPE INTEGER
set_parameter_property DEVICE_TYPE UNITS None
set_parameter_property DEVICE_TYPE HDL_PARAMETER true
# interfaces
# axi4 slave
ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn
add_interface s_axi_clock clock end
add_interface_port s_axi_clock s_axi_aclk clk Input 1
add_interface s_axi_reset reset end
set_interface_property s_axi_reset associatedClock s_axi_clock
add_interface_port s_axi_reset s_axi_aresetn reset_n Input 1
add_interface s_axi axi4lite end
set_interface_property s_axi associatedClock s_axi_clock
set_interface_property s_axi associatedReset s_axi_reset
add_interface_port s_axi s_axi_awvalid awvalid Input 1
add_interface_port s_axi s_axi_awaddr awaddr Input 16
add_interface_port s_axi s_axi_awprot awprot Input 3
add_interface_port s_axi s_axi_awready awready Output 1
add_interface_port s_axi s_axi_wvalid wvalid Input 1
add_interface_port s_axi s_axi_wdata wdata Input 32
add_interface_port s_axi s_axi_wstrb wstrb Input 4
add_interface_port s_axi s_axi_wready wready Output 1
add_interface_port s_axi s_axi_bvalid bvalid Output 1
add_interface_port s_axi s_axi_bresp bresp Output 2
add_interface_port s_axi s_axi_bready bready Input 1
add_interface_port s_axi s_axi_arvalid arvalid Input 1
add_interface_port s_axi s_axi_araddr araddr Input 16
add_interface_port s_axi s_axi_arprot arprot Input 3
add_interface_port s_axi s_axi_arready arready Output 1
add_interface_port s_axi s_axi_rvalid rvalid Output 1
add_interface_port s_axi s_axi_rresp rresp Output 2
add_interface_port s_axi s_axi_rdata rdata Output 32
add_interface_port s_axi s_axi_rready rready Input 1
# device interface
add_interface device_clock clock end
add_interface_port device_clock clk clk Input 1
add_interface device_if conduit end
set_interface_property device_if associatedClock device_clock
add_interface_port device_if rx_clk_in_p rx_clk_in_p Input 1
add_interface_port device_if rx_clk_in_n rx_clk_in_n Input 1
add_interface_port device_if rx_frame_in_p rx_frame_in_p Input 1
add_interface_port device_if rx_frame_in_n rx_frame_in_n Input 1
add_interface_port device_if rx_data_in_p rx_data_in_p Input 6
add_interface_port device_if rx_data_in_n rx_data_in_n Input 6
add_interface_port device_if tx_clk_out_p tx_clk_out_p Output 1
add_interface_port device_if tx_clk_out_n tx_clk_out_n Output 1
add_interface_port device_if tx_frame_out_p tx_frame_out_p Output 1
add_interface_port device_if tx_frame_out_n tx_frame_out_n Output 1
add_interface_port device_if tx_data_out_p tx_data_out_p Output 6
add_interface_port device_if tx_data_out_n tx_data_out_n Output 6
ad_alt_intf signal dac_sync_in input 1 sync
ad_alt_intf signal dac_sync_out output 1 sync
ad_alt_intf signal dac_sync_in input 1
ad_alt_intf signal dac_sync_out output 1
ad_alt_intf signal tdd_sync input 1
ad_alt_intf signal tdd_sync_cntr output 1
ad_alt_intf clock delay_clk input 1
ad_alt_intf clock l_clk output 1
ad_alt_intf reset rst output 1 if_l_clk
ad_alt_intf clock clk input 1
add_interface fifo_ch_0_in conduit end
#set_interface_property fifo_ch_0_in associatedClock if_l_clk
add_interface_port fifo_ch_0_in adc_enable_i0 enable Output 1
add_interface_port fifo_ch_0_in adc_valid_i0 valid Output 1
add_interface_port fifo_ch_0_in adc_data_i0 data Output 16
ad_alt_intf reset rst output 1 if_clk
set_interface_property if_rst associatedResetSinks s_axi_reset
add_interface fifo_ch_1_in conduit end
#set_interface_property fifo_ch_1_in associatedClock if_l_clk
add_interface_port fifo_ch_1_in adc_enable_q0 enable Output 1
add_interface_port fifo_ch_1_in adc_valid_q0 valid Output 1
add_interface_port fifo_ch_1_in adc_data_q0 data Output 16
add_interface adc_ch_0 conduit end
add_interface_port adc_ch_0 adc_enable_i0 enable Output 1
add_interface_port adc_ch_0 adc_valid_i0 valid Output 1
add_interface_port adc_ch_0 adc_data_i0 data Output 16
add_interface fifo_ch_2_in conduit end
#set_interface_property fifo_ch_2_in associatedClock if_l_clk
add_interface_port fifo_ch_2_in adc_enable_i1 enable Output 1
add_interface_port fifo_ch_2_in adc_valid_i1 valid Output 1
add_interface_port fifo_ch_2_in adc_data_i1 data Output 16
set_interface_property adc_ch_0 associatedClock if_clk
set_interface_property adc_ch_0 associatedReset none
add_interface fifo_ch_3_in conduit end
#set_interface_property fifo_ch_3_in associatedClock if_l_clk
add_interface_port fifo_ch_3_in adc_enable_q1 enable Output 1
add_interface_port fifo_ch_3_in adc_valid_q1 valid Output 1
add_interface_port fifo_ch_3_in adc_data_q1 data Output 16
add_interface adc_ch_1 conduit end
add_interface_port adc_ch_1 adc_enable_q0 enable Output 1
add_interface_port adc_ch_1 adc_valid_q0 valid Output 1
add_interface_port adc_ch_1 adc_data_q0 data Output 16
set_interface_property adc_ch_1 associatedClock if_clk
set_interface_property adc_ch_1 associatedReset none
add_interface adc_ch_2 conduit end
add_interface_port adc_ch_2 adc_enable_i1 enable Output 1
add_interface_port adc_ch_2 adc_valid_i1 valid Output 1
add_interface_port adc_ch_2 adc_data_i1 data Output 16
set_interface_property adc_ch_2 associatedClock if_clk
set_interface_property adc_ch_2 associatedReset none
add_interface adc_ch_3 conduit end
add_interface_port adc_ch_3 adc_enable_q1 enable Output 1
add_interface_port adc_ch_3 adc_valid_q1 valid Output 1
add_interface_port adc_ch_3 adc_data_q1 data Output 16
set_interface_property adc_ch_3 associatedClock if_clk
set_interface_property adc_ch_3 associatedReset none
ad_alt_intf signal adc_dovf input 1 ovf
ad_alt_intf signal adc_dunf input 1 unf
ad_alt_intf signal adc_r1_mode output 1 r1_mode
add_interface fifo_ch_0_out conduit end
#set_interface_property fifo_ch_0_out associatedClock if_l_clk
add_interface_port fifo_ch_0_out dac_enable_i0 enable Output 1
add_interface_port fifo_ch_0_out dac_valid_i0 valid Output 1
add_interface_port fifo_ch_0_out dac_data_i0 data Input 16
add_interface dac_ch_0 conduit end
add_interface_port dac_ch_0 dac_enable_i0 enable Output 1
add_interface_port dac_ch_0 dac_valid_i0 valid Output 1
add_interface_port dac_ch_0 dac_data_i0 data Input 16
add_interface fifo_ch_1_out conduit end
#set_interface_property fifo_ch_1_out associatedClock if_l_clk
add_interface_port fifo_ch_1_out dac_enable_q0 enable Output 1
add_interface_port fifo_ch_1_out dac_valid_q0 valid Output 1
add_interface_port fifo_ch_1_out dac_data_q0 data Input 16
set_interface_property dac_ch_0 associatedClock if_clk
set_interface_property dac_ch_0 associatedReset none
add_interface fifo_ch_2_out conduit end
#set_interface_property fifo_ch_2_out associatedClock if_l_clk
add_interface_port fifo_ch_2_out dac_enable_i1 enable Output 1
add_interface_port fifo_ch_2_out dac_valid_i1 valid Output 1
add_interface_port fifo_ch_2_out dac_data_i1 data Input 16
add_interface dac_ch_1 conduit end
add_interface_port dac_ch_1 dac_enable_q0 enable Output 1
add_interface_port dac_ch_1 dac_valid_q0 valid Output 1
add_interface_port dac_ch_1 dac_data_q0 data Input 16
add_interface fifo_ch_3_out conduit end
#set_interface_property fifo_ch_3_out associatedClock if_l_clk
add_interface_port fifo_ch_3_out dac_enable_q1 enable Output 1
add_interface_port fifo_ch_3_out dac_valid_q1 valid Output 1
add_interface_port fifo_ch_3_out dac_data_q1 data Input 16
set_interface_property dac_ch_1 associatedClock if_clk
set_interface_property dac_ch_1 associatedReset none
add_interface dac_ch_2 conduit end
add_interface_port dac_ch_2 dac_enable_i1 enable Output 1
add_interface_port dac_ch_2 dac_valid_i1 valid Output 1
add_interface_port dac_ch_2 dac_data_i1 data Input 16
set_interface_property dac_ch_2 associatedClock if_clk
set_interface_property dac_ch_2 associatedReset none
add_interface dac_ch_3 conduit end
add_interface_port dac_ch_3 dac_enable_q1 enable Output 1
add_interface_port dac_ch_3 dac_valid_q1 valid Output 1
add_interface_port dac_ch_3 dac_data_q1 data Input 16
set_interface_property dac_ch_3 associatedClock if_clk
set_interface_property dac_ch_3 associatedReset none
ad_alt_intf signal dac_dovf input 1 ovf
ad_alt_intf signal dac_dunf input 1 unf
ad_alt_intf signal dac_r1_mode output 1 r1_mode
add_interface delay_clock clock end
add_interface_port delay_clock delay_clk clk Input 1
ad_alt_intf signal up_enable input 1
ad_alt_intf signal up_txnrx input 1
ad_alt_intf signal up_dac_gpio_in input 32
ad_alt_intf signal up_dac_gpio_out output 32
ad_alt_intf signal up_adc_gpio_in input 32
ad_alt_intf signal up_adc_gpio_out output 32
# generated cores
add_hdl_instance ad_serdes_clk_core alt_serdes
set_instance_parameter_value ad_serdes_clk_core {MODE} {CLK}
set_instance_parameter_value ad_serdes_clk_core {DDR_OR_SDR_N} {1}
set_instance_parameter_value ad_serdes_clk_core {SERDES_FACTOR} {4}
set_instance_parameter_value ad_serdes_clk_core {CLKIN_FREQUENCY} {250.0}
add_hdl_instance ad_serdes_in_core_a10 alt_serdes
set_instance_parameter_value ad_serdes_in_core_a10 {MODE} {IN}
set_instance_parameter_value ad_serdes_in_core_a10 {DDR_OR_SDR_N} {1}
set_instance_parameter_value ad_serdes_in_core_a10 {SERDES_FACTOR} {4}
set_instance_parameter_value ad_serdes_in_core_a10 {CLKIN_FREQUENCY} {250.0}
add_hdl_instance ad_serdes_out_core_a10 alt_serdes
set_instance_parameter_value ad_serdes_out_core_a10 {MODE} {OUT}
set_instance_parameter_value ad_serdes_out_core_a10 {DDR_OR_SDR_N} {1}
set_instance_parameter_value ad_serdes_out_core_a10 {SERDES_FACTOR} {4}
set_instance_parameter_value ad_serdes_out_core_a10 {CLKIN_FREQUENCY} {250.0}
add_hdl_instance ad_cmos_out_core_a10 alt_serdes
set_instance_parameter_value ad_cmos_out_core_a10 {MODE} {OUT}
set_instance_parameter_value ad_cmos_out_core_a10 {DDR_OR_SDR_N} {1}
set_instance_parameter_value ad_cmos_out_core_a10 {SERDES_FACTOR} {2}
set_instance_parameter_value ad_cmos_out_core_a10 {CLKIN_FREQUENCY} {250.0}
# updates
proc axi_ad9361_elab {} {
set m_cmos_or_lvds_n [get_parameter_value CMOS_OR_LVDS_N]
add_interface device_if conduit end
set_interface_property device_if associatedClock none
set_interface_property device_if associatedReset none
if {$m_cmos_or_lvds_n == 1} {
add_interface_port device_if rx_clk_in rx_clk_in Input 1
add_interface_port device_if rx_frame_in rx_frame_in Input 1
add_interface_port device_if rx_data_in rx_data_in Input 12
add_interface_port device_if tx_clk_out tx_clk_out Output 1
add_interface_port device_if tx_frame_out tx_frame_out Output 1
add_interface_port device_if tx_data_out tx_data_out Output 12
}
if {$m_cmos_or_lvds_n == 0} {
add_interface_port device_if rx_clk_in_p rx_clk_in_p Input 1
add_interface_port device_if rx_clk_in_n rx_clk_in_n Input 1
add_interface_port device_if rx_frame_in_p rx_frame_in_p Input 1
add_interface_port device_if rx_frame_in_n rx_frame_in_n Input 1
add_interface_port device_if rx_data_in_p rx_data_in_p Input 6
add_interface_port device_if rx_data_in_n rx_data_in_n Input 6
add_interface_port device_if tx_clk_out_p tx_clk_out_p Output 1
add_interface_port device_if tx_clk_out_n tx_clk_out_n Output 1
add_interface_port device_if tx_frame_out_p tx_frame_out_p Output 1
add_interface_port device_if tx_frame_out_n tx_frame_out_n Output 1
add_interface_port device_if tx_data_out_p tx_data_out_p Output 6
add_interface_port device_if tx_data_out_n tx_data_out_n Output 6
}
add_interface_port device_if enable enable Output 1
add_interface_port device_if txnrx txnrx Output 1
}
proc axi_ad9361_fileset {entityName} {
ad_ip_modfile ad_cmos_out.v ad_cmos_out.v ad_cmos_out_core_a10
ad_ip_modfile ad_serdes_in.v ad_serdes_in.v ad_serdes_in_core_a10
ad_ip_modfile ad_serdes_out.v ad_serdes_out.v ad_serdes_out_core_a10
ad_ip_modfile ad_serdes_clk.v ad_serdes_clk.v ad_serdes_clk_core
}

39
library/axi_ad9361/axi_ad9361_ip.tcl
View File

@ -7,10 +7,13 @@ adi_ip_create axi_ad9361
adi_ip_files axi_ad9361 [list \
"$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc" \
"$ad_hdl_dir/library/common/ad_rst.v" \
"$ad_hdl_dir/library/common/ad_lvds_clk.v" \
"$ad_hdl_dir/library/common/ad_lvds_in.v" \
"$ad_hdl_dir/library/common/ad_lvds_out.v" \
"$ad_hdl_dir/library/common/ad_mul.v" \
"$ad_hdl_dir/library/xilinx/common/ad_lvds_clk.v" \
"$ad_hdl_dir/library/xilinx/common/ad_lvds_in.v" \
"$ad_hdl_dir/library/xilinx/common/ad_lvds_out.v" \
"$ad_hdl_dir/library/xilinx/common/ad_cmos_clk.v" \
"$ad_hdl_dir/library/xilinx/common/ad_cmos_in.v" \
"$ad_hdl_dir/library/xilinx/common/ad_cmos_out.v" \
"$ad_hdl_dir/library/xilinx/common/ad_mul.v" \
"$ad_hdl_dir/library/common/ad_pnmon.v" \
"$ad_hdl_dir/library/common/ad_dds_sine.v" \
"$ad_hdl_dir/library/common/ad_dds_1.v" \
@ -31,7 +34,8 @@ adi_ip_files axi_ad9361 [list \
"$ad_hdl_dir/library/common/up_dac_channel.v" \
"$ad_hdl_dir/library/common/up_tdd_cntrl.v" \
"axi_ad9361_constr.xdc" \
"axi_ad9361_dev_if.v" \
"xilinx/axi_ad9361_lvds_if.v" \
"xilinx/axi_ad9361_cmos_if.v" \
"axi_ad9361_rx_pnmon.v" \
"axi_ad9361_rx_channel.v" \
"axi_ad9361_rx.v" \
@ -46,11 +50,36 @@ adi_ip_constraints axi_ad9361 [list \
"axi_ad9361_constr.xdc" \
"$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc" ]
set_property driver_value 0 [ipx::get_ports *rx_clk_in* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *rx_frame_in* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *rx_data_in* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *dac_sync_in* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *gpio_in* -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.CMOS_OR_LVDS_N')) == 0} \
[ipx::get_ports rx_clk_in_p -of_objects [ipx::current_core]] \
[ipx::get_ports rx_clk_in_n -of_objects [ipx::current_core]] \
[ipx::get_ports rx_frame_in_p -of_objects [ipx::current_core]] \
[ipx::get_ports rx_frame_in_n -of_objects [ipx::current_core]] \
[ipx::get_ports rx_data_in_p -of_objects [ipx::current_core]] \
[ipx::get_ports rx_data_in_n -of_objects [ipx::current_core]] \
[ipx::get_ports tx_clk_out_p -of_objects [ipx::current_core]] \
[ipx::get_ports tx_clk_out_n -of_objects [ipx::current_core]] \
[ipx::get_ports tx_frame_out_p -of_objects [ipx::current_core]] \
[ipx::get_ports tx_frame_out_n -of_objects [ipx::current_core]] \
[ipx::get_ports tx_data_out_p -of_objects [ipx::current_core]] \
[ipx::get_ports tx_data_out_n -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.CMOS_OR_LVDS_N')) == 1} \
[ipx::get_ports rx_clk_in -of_objects [ipx::current_core]] \
[ipx::get_ports rx_frame_in -of_objects [ipx::current_core]] \
[ipx::get_ports rx_data_in -of_objects [ipx::current_core]] \
[ipx::get_ports tx_clk_out -of_objects [ipx::current_core]] \
[ipx::get_ports tx_frame_out -of_objects [ipx::current_core]] \
[ipx::get_ports tx_data_out -of_objects [ipx::current_core]]
ipx::remove_bus_interface rst [ipx::current_core]
ipx::remove_bus_interface clk [ipx::current_core]
ipx::remove_bus_interface l_clk [ipx::current_core]

265
library/axi_ad9361/axi_ad9361_rx.v
View File

@ -34,137 +34,106 @@
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ADC channel-need to work on dual mode for pn sequence
`timescale 1ns/100ps
module axi_ad9361_rx (
// adc interface
adc_rst,
adc_clk,
adc_valid,
adc_data,
adc_status,
adc_r1_mode,
adc_ddr_edgesel,
dac_data,
// delay interface
up_dld,
up_dwdata,
up_drdata,
delay_clk,
delay_rst,
delay_locked,
// dma interface
adc_enable_i0,
adc_valid_i0,
adc_data_i0,
adc_enable_q0,
adc_valid_q0,
adc_data_q0,
adc_enable_i1,
adc_valid_i1,
adc_data_i1,
adc_enable_q1,
adc_valid_q1,
adc_data_q1,
adc_dovf,
adc_dunf,
// gpio
up_adc_gpio_in,
up_adc_gpio_out,
// processor interface
up_rstn,
up_clk,
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_rack);
module axi_ad9361_rx #(
// parameters
parameter DATAPATH_DISABLE = 0;
parameter ID = 0;
parameter ID = 0,
parameter MODE_1R1T = 0,
parameter USERPORTS_DISABLE = 0,
parameter DATAFORMAT_DISABLE = 0,
parameter DCFILTER_DISABLE = 0,
parameter IQCORRECTION_DISABLE = 0) (
// common
output mmcm_rst,
// adc interface
output adc_rst;
input adc_clk;
input adc_valid;
input [47:0] adc_data;
input adc_status;
output adc_r1_mode;
output adc_ddr_edgesel;
input [47:0] dac_data;
output adc_rst,
input adc_clk,
input adc_valid,
input [47:0] adc_data,
input adc_status,
output adc_r1_mode,
output adc_ddr_edgesel,
input [47:0] dac_data,
// delay interface
output [ 6:0] up_dld;
output [34:0] up_dwdata;
input [34:0] up_drdata;
input delay_clk;
output delay_rst;
input delay_locked;
output [12:0] up_dld,
output [64:0] up_dwdata,
input [64:0] up_drdata,
input delay_clk,
output delay_rst,
input delay_locked,
// dma interface
output adc_enable_i0;
output adc_valid_i0;
output [15:0] adc_data_i0;
output adc_enable_q0;
output adc_valid_q0;
output [15:0] adc_data_q0;
output adc_enable_i1;
output adc_valid_i1;
output [15:0] adc_data_i1;
output adc_enable_q1;
output adc_valid_q1;
output [15:0] adc_data_q1;
input adc_dovf;
input adc_dunf;
output adc_enable_i0,
output adc_valid_i0,
output [15:0] adc_data_i0,
output adc_enable_q0,
output adc_valid_q0,
output [15:0] adc_data_q0,
output adc_enable_i1,
output adc_valid_i1,
output [15:0] adc_data_i1,
output adc_enable_q1,
output adc_valid_q1,
output [15:0] adc_data_q1,
input adc_dovf,
input adc_dunf,
// gpio
input [31:0] up_adc_gpio_in;
output [31:0] up_adc_gpio_out;
input [31:0] up_adc_gpio_in,
output [31:0] up_adc_gpio_out,
// processor interface
input up_rstn;
input up_clk;
input up_wreq;
input [13:0] up_waddr;
input [31:0] up_wdata;
output up_wack;
input up_rreq;
input [13:0] up_raddr;
output [31:0] up_rdata;
output up_rack;
input up_rstn,
input up_clk,
input up_wreq,
input [13:0] up_waddr,
input [31:0] up_wdata,
output up_wack,
input up_rreq,
input [13:0] up_raddr,
output [31:0] up_rdata,
output up_rack,
// drp interface
output up_drp_sel,
output up_drp_wr,
output [11:0] up_drp_addr,
output [31:0] up_drp_wdata,
input [31:0] up_drp_rdata,
input up_drp_ready,
input up_drp_locked);
// configuration settings
localparam CONFIG = (MODE_1R1T * 16) +
(USERPORTS_DISABLE * 8) +
(DATAFORMAT_DISABLE * 4) +
(DCFILTER_DISABLE * 2) +
(IQCORRECTION_DISABLE * 1);
// internal registers
reg up_status_pn_err = 'd0;
reg up_status_pn_oos = 'd0;
reg up_status_or = 'd0;
reg [31:0] up_rdata = 'd0;
reg up_rack = 'd0;
reg up_wack = 'd0;
reg [31:0] up_rdata_int = 'd0;
reg up_rack_int = 'd0;
reg up_wack_int = 'd0;
// internal signals
@ -176,38 +145,44 @@ module axi_ad9361_rx (
wire [ 3:0] up_adc_pn_oos_s;
wire [ 3:0] up_adc_or_s;
wire [31:0] up_rdata_s[0:5];
wire up_rack_s[0:5];
wire up_wack_s[0:5];
wire [ 5:0] up_rack_s;
wire [ 5:0] up_wack_s;
// processor read interface
assign up_wack = up_wack_int;
assign up_rack = up_rack_int;
assign up_rdata = up_rdata_int;
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_status_pn_err <= 'd0;
up_status_pn_oos <= 'd0;
up_status_or <= 'd0;
up_rdata <= 'd0;
up_rack <= 'd0;
up_wack <= 'd0;
up_rdata_int <= 'd0;
up_rack_int <= 'd0;
up_wack_int <= 'd0;
end else begin
up_status_pn_err <= | up_adc_pn_err_s;
up_status_pn_oos <= | up_adc_pn_oos_s;
up_status_or <= | up_adc_or_s;
up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2] |
up_rdata_int <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2] |
up_rdata_s[3] | up_rdata_s[4] | up_rdata_s[5];
up_rack <= up_rack_s[0] | up_rack_s[1] | up_rack_s[2] |
up_rack_s[3] | up_rack_s[4] | up_rack_s[5];
up_wack <= up_wack_s[0] | up_wack_s[1] | up_wack_s[2] |
up_wack_s[3] | up_wack_s[4] | up_wack_s[5];
up_rack_int <= | up_rack_s;
up_wack_int <= | up_wack_s;
end
end
// channel 0 (i)
axi_ad9361_rx_channel #(
.Q_OR_I_N(0),
.CHANNEL_ID(0),
.DATAPATH_DISABLE (DATAPATH_DISABLE))
.Q_OR_I_N (0),
.CHANNEL_ID (0),
.DISABLE (0),
.USERPORTS_DISABLE (USERPORTS_DISABLE),
.DATAFORMAT_DISABLE (DATAFORMAT_DISABLE),
.DCFILTER_DISABLE (DCFILTER_DISABLE),
.IQCORRECTION_DISABLE (IQCORRECTION_DISABLE))
i_rx_channel_0 (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
@ -238,9 +213,13 @@ module axi_ad9361_rx (
// channel 1 (q)
axi_ad9361_rx_channel #(
.Q_OR_I_N(1),
.CHANNEL_ID(1),
.DATAPATH_DISABLE (DATAPATH_DISABLE))
.Q_OR_I_N (1),
.CHANNEL_ID (1),
.DISABLE (0),
.USERPORTS_DISABLE (USERPORTS_DISABLE),
.DATAFORMAT_DISABLE (DATAFORMAT_DISABLE),
.DCFILTER_DISABLE (DCFILTER_DISABLE),
.IQCORRECTION_DISABLE (IQCORRECTION_DISABLE))
i_rx_channel_1 (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
@ -271,9 +250,13 @@ module axi_ad9361_rx (
// channel 2 (i)
axi_ad9361_rx_channel #(
.Q_OR_I_N(0),
.CHANNEL_ID(2),
.DATAPATH_DISABLE (DATAPATH_DISABLE))
.Q_OR_I_N (0),
.CHANNEL_ID (2),
.DISABLE (MODE_1R1T),
.USERPORTS_DISABLE (USERPORTS_DISABLE),
.DATAFORMAT_DISABLE (DATAFORMAT_DISABLE),
.DCFILTER_DISABLE (DCFILTER_DISABLE),
.IQCORRECTION_DISABLE (IQCORRECTION_DISABLE))
i_rx_channel_2 (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
@ -304,9 +287,13 @@ module axi_ad9361_rx (
// channel 3 (q)
axi_ad9361_rx_channel #(
.Q_OR_I_N(1),
.CHANNEL_ID(3),
.DATAPATH_DISABLE (DATAPATH_DISABLE))
.Q_OR_I_N (1),
.CHANNEL_ID (3),
.DISABLE (MODE_1R1T),
.USERPORTS_DISABLE (USERPORTS_DISABLE),
.DATAFORMAT_DISABLE (DATAFORMAT_DISABLE),
.DCFILTER_DISABLE (DCFILTER_DISABLE),
.IQCORRECTION_DISABLE (IQCORRECTION_DISABLE))
i_rx_channel_3 (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
@ -336,8 +323,13 @@ module axi_ad9361_rx (
// common processor control
up_adc_common #(.ID (ID)) i_up_adc_common (
.mmcm_rst (),
up_adc_common #(
.ID (ID),
.CONFIG (CONFIG),
.DRP_DISABLE (1),
.USERPORTS_DISABLE (USERPORTS_DISABLE))
i_up_adc_common (
.mmcm_rst (mmcm_rst),
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_r1_mode (adc_r1_mode),
@ -353,13 +345,13 @@ module axi_ad9361_rx (
.up_status_pn_err (up_status_pn_err),
.up_status_pn_oos (up_status_pn_oos),
.up_status_or (up_status_or),
.up_drp_sel (),
.up_drp_wr (),
.up_drp_addr (),
.up_drp_wdata (),
.up_drp_rdata (16'd0),
.up_drp_ready (1'd0),
.up_drp_locked (1'd1),
.up_drp_sel (up_drp_sel),
.up_drp_wr (up_drp_wr),
.up_drp_addr (up_drp_addr),
.up_drp_wdata (up_drp_wdata),
.up_drp_rdata (up_drp_rdata),
.up_drp_ready (up_drp_ready),
.up_drp_locked (up_drp_locked),
.up_usr_chanmax (),
.adc_usr_chanmax (8'd3),
.up_adc_gpio_in (up_adc_gpio_in),
@ -377,7 +369,10 @@ module axi_ad9361_rx (
// adc delay control
up_delay_cntrl #(.DATA_WIDTH(7), .BASE_ADDRESS(6'h02)) i_delay_cntrl (
up_delay_cntrl #(
.DATA_WIDTH (13),
.BASE_ADDRESS (6'h02))
i_delay_cntrl (
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_locked (delay_locked),

170
library/axi_ad9361/axi_ad9361_rx_channel.v
View File

@ -34,87 +34,54 @@
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ADC channel-need to work on dual mode for pn sequence
`timescale 1ns/100ps
module axi_ad9361_rx_channel (
// adc interface
adc_clk,
adc_rst,
adc_valid,
adc_data,
adc_data_q,
adc_or,
dac_data,
// channel interface
adc_dcfilter_data_out,
adc_dcfilter_data_in,
adc_iqcor_valid,
adc_iqcor_data,
adc_enable,
up_adc_pn_err,
up_adc_pn_oos,
up_adc_or,
// processor interface
up_rstn,
up_clk,
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_rack);
module axi_ad9361_rx_channel #(
// parameters
parameter Q_OR_I_N = 0;
parameter CHANNEL_ID = 0;
parameter DATAPATH_DISABLE = 0;
parameter Q_OR_I_N = 0,
parameter CHANNEL_ID = 0,
parameter DISABLE = 0,
parameter USERPORTS_DISABLE = 0,
parameter DATAFORMAT_DISABLE = 0,
parameter DCFILTER_DISABLE = 0,
parameter IQCORRECTION_DISABLE = 0) (
// adc interface
input adc_clk;
input adc_rst;
input adc_valid;
input [11:0] adc_data;
input [11:0] adc_data_q;
input adc_or;
input [11:0] dac_data;
input adc_clk,
input adc_rst,
input adc_valid,
input [11:0] adc_data,
input [11:0] adc_data_q,
input adc_or,
input [11:0] dac_data,
// channel interface
output [15:0] adc_dcfilter_data_out;
input [15:0] adc_dcfilter_data_in;
output adc_iqcor_valid;
output [15:0] adc_iqcor_data;
output adc_enable;
output up_adc_pn_err;
output up_adc_pn_oos;
output up_adc_or;
output [15:0] adc_dcfilter_data_out,
input [15:0] adc_dcfilter_data_in,
output adc_iqcor_valid,
output [15:0] adc_iqcor_data,
output adc_enable,
output up_adc_pn_err,
output up_adc_pn_oos,
output up_adc_or,
// processor interface
input up_rstn;
input up_clk;
input up_wreq;
input [13:0] up_waddr;
input [31:0] up_wdata;
output up_wack;
input up_rreq;
input [13:0] up_raddr;
output [31:0] up_rdata;
output up_rack;
input up_rstn,
input up_clk,
input up_wreq,
input [13:0] up_waddr,
input [31:0] up_wdata,
output up_wack,
input up_rreq,
input [13:0] up_raddr,
output [31:0] up_rdata,
output up_rack);
// internal signals
@ -137,12 +104,35 @@ module axi_ad9361_rx_channel (
wire adc_pn_err_s;
wire adc_pn_oos_s;
// data-path disable
generate
if (DISABLE == 1) begin
assign adc_dcfilter_data_out = 16'd0;
assign adc_iqcor_valid = 1'd0;
assign adc_iqcor_data = 16'd0;
assign adc_enable = 1'd0;
assign up_adc_pn_err = 1'd0;
assign up_adc_pn_oos = 1'd0;
assign up_adc_or = 1'd0;
assign up_wack = 1'd0;
assign up_rdata = 32'd0;
assign up_rack = 1'd0;
end
endgenerate
generate
if (DISABLE == 0) begin
// iq correction inputs
assign adc_data_s = (adc_data_sel_s == 4'h0) ? adc_data : dac_data;
assign adc_dcfilter_data_out = adc_dcfilter_data_s;
axi_ad9361_rx_pnmon #(.Q_OR_I_N (Q_OR_I_N), .PRBS_SEL (CHANNEL_ID)) i_rx_pnmon (
axi_ad9361_rx_pnmon #(
.Q_OR_I_N (Q_OR_I_N),
.PRBS_SEL (CHANNEL_ID))
i_rx_pnmon (
.adc_clk (adc_clk),
.adc_valid (adc_valid),
.adc_data_i (adc_data),
@ -151,12 +141,10 @@ module axi_ad9361_rx_channel (
.adc_pn_oos (adc_pn_oos_s),
.adc_pn_err (adc_pn_err_s));
generate
if (DATAPATH_DISABLE == 1) begin
assign adc_dfmt_valid_s = adc_valid;
assign adc_dfmt_data_s = {4'd0, adc_data_s};
end else begin
ad_datafmt #(.DATA_WIDTH (12)) i_ad_datafmt (
ad_datafmt #(
.DATA_WIDTH (12),
.DISABLE (DATAFORMAT_DISABLE))
i_ad_datafmt (
.clk (adc_clk),
.valid (adc_valid),
.data (adc_data_s),
@ -165,15 +153,10 @@ module axi_ad9361_rx_channel (
.dfmt_enable (adc_dfmt_enable_s),
.dfmt_type (adc_dfmt_type_s),
.dfmt_se (adc_dfmt_se_s));
end
endgenerate
generate
if (DATAPATH_DISABLE == 1) begin
assign adc_dcfilter_valid_s = adc_dfmt_valid_s;
assign adc_dcfilter_data_s = adc_dfmt_data_s;
end else begin
ad_dcfilter i_ad_dcfilter (
ad_dcfilter #(
.DISABLE (DCFILTER_DISABLE))
i_ad_dcfilter (
.clk (adc_clk),
.valid (adc_dfmt_valid_s),
.data (adc_dfmt_data_s),
@ -182,15 +165,11 @@ module axi_ad9361_rx_channel (
.dcfilt_enb (adc_dcfilt_enb_s),
.dcfilt_coeff (adc_dcfilt_coeff_s),
.dcfilt_offset (adc_dcfilt_offset_s));
end
endgenerate
generate
if (DATAPATH_DISABLE == 1) begin
assign adc_iqcor_valid = adc_dcfilter_valid_s;
assign adc_iqcor_data = adc_dcfilter_data_s;
end else begin
ad_iqcor #(.Q_OR_I_N (Q_OR_I_N)) i_ad_iqcor (
ad_iqcor #(
.Q_OR_I_N (Q_OR_I_N),
.DISABLE (IQCORRECTION_DISABLE))
i_ad_iqcor (
.clk (adc_clk),
.valid (adc_dcfilter_valid_s),
.data_in (adc_dcfilter_data_s),
@ -200,10 +179,14 @@ module axi_ad9361_rx_channel (
.iqcor_enable (adc_iqcor_enb_s),
.iqcor_coeff_1 (adc_iqcor_coeff_1_s),
.iqcor_coeff_2 (adc_iqcor_coeff_2_s));
end
endgenerate
up_adc_channel #(.ADC_CHANNEL_ID (CHANNEL_ID)) i_up_adc_channel (
up_adc_channel #(
.CHANNEL_ID (CHANNEL_ID),
.USERPORTS_DISABLE (USERPORTS_DISABLE),
.DATAFORMAT_DISABLE (DATAFORMAT_DISABLE),
.DCFILTER_DISABLE (DCFILTER_DISABLE),
.IQCORRECTION_DISABLE (IQCORRECTION_DISABLE))
i_up_adc_channel (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_enable (adc_enable),
@ -249,6 +232,9 @@ module axi_ad9361_rx_channel (
.up_rdata (up_rdata),
.up_rack (up_rack));
end
endgenerate
endmodule
// ***************************************************************************

121
library/axi_ad9361/axi_ad9361_tdd.v
View File

@ -61,30 +61,12 @@ module axi_ad9361_tdd (
// sync signal
tdd_sync,
tdd_sync_en,
tdd_terminal_type,
tdd_sync_cntr,
// tx/rx data flow control
tx_valid_i0,
tx_valid_q0,
tx_valid_i1,
tx_valid_q1,
tdd_tx_valid_i0,
tdd_tx_valid_q0,
tdd_tx_valid_i1,
tdd_tx_valid_q1,
rx_valid_i0,
rx_valid_q0,
rx_valid_i1,
rx_valid_q1,
tdd_rx_valid_i0,
tdd_rx_valid_q0,
tdd_rx_valid_i1,
tdd_rx_valid_q1,
tdd_tx_valid,
tdd_rx_valid,
// bus interface
@ -97,10 +79,7 @@ module axi_ad9361_tdd (
up_rreq,
up_raddr,
up_rdata,
up_rack,
tdd_dbg
);
up_rack);
input clk;
input rst;
@ -116,32 +95,12 @@ module axi_ad9361_tdd (
input [ 7:0] tdd_status;
input tdd_sync;
output tdd_sync_en;
output tdd_terminal_type;
output tdd_sync_cntr;
// tx data flow control
// data flow control
input tx_valid_i0;
input tx_valid_q0;
input tx_valid_i1;
input tx_valid_q1;
output tdd_tx_valid_i0;
output tdd_tx_valid_q0;
output tdd_tx_valid_i1;
output tdd_tx_valid_q1;
// rx data flow control
input rx_valid_i0;
input rx_valid_q0;
input rx_valid_i1;
input rx_valid_q1;
output tdd_rx_valid_i0;
output tdd_rx_valid_q0;
output tdd_rx_valid_i1;
output tdd_rx_valid_q1;
output tdd_tx_valid;
output tdd_rx_valid;
// bus interface
@ -156,15 +115,13 @@ module axi_ad9361_tdd (
output [31:0] up_rdata;
output up_rack;
output [41:0] tdd_dbg;
reg tdd_slave_synced = 1'b0;
reg tdd_tx_valid = 1'b0;
reg tdd_rx_valid = 1'b0;
// internal signals
wire rst;
wire tdd_enable_s;
wire tdd_enable_synced_s;
wire tdd_secondary_s;
wire [ 7:0] tdd_burst_count_s;
wire tdd_rx_only_s;
@ -181,6 +138,8 @@ module axi_ad9361_tdd (
wire [23:0] tdd_vco_tx_off_1_s;
wire [23:0] tdd_rx_on_1_s;
wire [23:0] tdd_rx_off_1_s;
wire [23:0] tdd_rx_dp_on_1_s;
wire [23:0] tdd_rx_dp_off_1_s;
wire [23:0] tdd_tx_on_1_s;
wire [23:0] tdd_tx_off_1_s;
wire [23:0] tdd_tx_dp_on_1_s;
@ -191,6 +150,8 @@ module axi_ad9361_tdd (
wire [23:0] tdd_vco_tx_off_2_s;
wire [23:0] tdd_rx_on_2_s;
wire [23:0] tdd_rx_off_2_s;
wire [23:0] tdd_rx_dp_on_2_s;
wire [23:0] tdd_rx_dp_off_2_s;
wire [23:0] tdd_tx_on_2_s;
wire [23:0] tdd_tx_off_2_s;
wire [23:0] tdd_tx_dp_on_2_s;
@ -198,33 +159,29 @@ module axi_ad9361_tdd (
wire [23:0] tdd_counter_status;
wire tdd_rx_dp_en_s;
wire tdd_tx_dp_en_s;
assign tdd_dbg = {tdd_counter_status, tdd_enable_s, tdd_sync, tdd_tx_dp_en_s,
tdd_rx_vco_en, tdd_tx_vco_en, tdd_rx_rf_en, tdd_tx_rf_en};
assign tdd_enabled = tdd_enable_s;
assign tdd_sync_cntr = ~(tdd_enable_s & tdd_terminal_type_s);
// tx/rx data flow control
assign tdd_tx_valid_i0 = ((tdd_enable_synced_s & tdd_gated_tx_dmapath_s) == 1'b1) ?
(tx_valid_i0 & tdd_tx_dp_en_s) : tx_valid_i0;
assign tdd_tx_valid_q0 = ((tdd_enable_synced_s & tdd_gated_tx_dmapath_s) == 1'b1) ?
(tx_valid_q0 & tdd_tx_dp_en_s) : tx_valid_q0;
assign tdd_tx_valid_i1 = ((tdd_enable_synced_s & tdd_gated_tx_dmapath_s) == 1'b1) ?
(tx_valid_i1 & tdd_tx_dp_en_s) : tx_valid_i1;
assign tdd_tx_valid_q1 = ((tdd_enable_synced_s & tdd_gated_tx_dmapath_s) == 1'b1) ?
(tx_valid_q1 & tdd_tx_dp_en_s) : tx_valid_q1;
always @(posedge clk) begin
if((tdd_enable_s == 1) && (tdd_gated_tx_dmapath_s == 1)) begin
tdd_tx_valid <= tdd_tx_dp_en_s;
end else begin
tdd_tx_valid <= 1'b1;
end
end
assign tdd_rx_valid_i0 = ((tdd_enable_synced_s & tdd_gated_rx_dmapath_s) == 1'b1) ?
(rx_valid_i0 & tdd_rx_rf_en) : rx_valid_i0;
assign tdd_rx_valid_q0 = ((tdd_enable_synced_s & tdd_gated_rx_dmapath_s) == 1'b1) ?
(rx_valid_q0 & tdd_rx_rf_en) : rx_valid_q0;
assign tdd_rx_valid_i1 = ((tdd_enable_synced_s & tdd_gated_rx_dmapath_s) == 1'b1) ?
(rx_valid_i1 & tdd_rx_rf_en) : rx_valid_i1;
assign tdd_rx_valid_q1 = ((tdd_enable_synced_s & tdd_gated_rx_dmapath_s) == 1'b1) ?
(rx_valid_q1 & tdd_rx_rf_en) : rx_valid_q1;
assign tdd_enabled = tdd_enable_synced_s;
assign tdd_terminal_type = ~tdd_terminal_type_s;
always @(posedge clk) begin
if((tdd_enable_s == 1) && (tdd_gated_tx_dmapath_s == 1)) begin
tdd_rx_valid <= tdd_rx_dp_en_s;
end else begin
tdd_rx_valid <= 1'b1;
end
end
// instantiations
@ -241,13 +198,14 @@ module axi_ad9361_tdd (
.tdd_counter_init(tdd_counter_init_s),
.tdd_frame_length(tdd_frame_length_s),
.tdd_terminal_type(tdd_terminal_type_s),
.tdd_sync_enable(tdd_sync_enable_s),
.tdd_vco_rx_on_1(tdd_vco_rx_on_1_s),
.tdd_vco_rx_off_1(tdd_vco_rx_off_1_s),
.tdd_vco_tx_on_1(tdd_vco_tx_on_1_s),
.tdd_vco_tx_off_1(tdd_vco_tx_off_1_s),
.tdd_rx_on_1(tdd_rx_on_1_s),
.tdd_rx_off_1(tdd_rx_off_1_s),
.tdd_rx_dp_on_1(tdd_rx_dp_on_1_s),
.tdd_rx_dp_off_1(tdd_rx_dp_off_1_s),
.tdd_tx_on_1(tdd_tx_on_1_s),
.tdd_tx_off_1(tdd_tx_off_1_s),
.tdd_tx_dp_on_1(tdd_tx_dp_on_1_s),
@ -258,6 +216,8 @@ module axi_ad9361_tdd (
.tdd_vco_tx_off_2(tdd_vco_tx_off_2_s),
.tdd_rx_on_2(tdd_rx_on_2_s),
.tdd_rx_off_2(tdd_rx_off_2_s),
.tdd_rx_dp_on_2(tdd_rx_dp_on_2_s),
.tdd_rx_dp_off_2(tdd_rx_dp_off_2_s),
.tdd_tx_on_2(tdd_tx_on_2_s),
.tdd_tx_off_2(tdd_tx_off_2_s),
.tdd_tx_dp_on_2(tdd_tx_dp_on_2_s),
@ -278,13 +238,12 @@ module axi_ad9361_tdd (
// for the axi_ad9361 core
ad_tdd_control #(
.TX_DATA_PATH_DELAY(14),
.CONTROL_PATH_DELAY(3))
.TX_DATA_PATH_DELAY(),
.CONTROL_PATH_DELAY())
i_tdd_control(
.clk(clk),
.rst(rst),
.tdd_enable(tdd_enable_s),
.tdd_enable_synced (tdd_enable_synced_s),
.tdd_secondary(tdd_secondary_s),
.tdd_counter_init(tdd_counter_init_s),
.tdd_frame_length(tdd_frame_length_s),
@ -292,13 +251,14 @@ module axi_ad9361_tdd (
.tdd_rx_only(tdd_rx_only_s),
.tdd_tx_only(tdd_tx_only_s),
.tdd_sync (tdd_sync),
.tdd_sync_en (tdd_sync_en),
.tdd_vco_rx_on_1(tdd_vco_rx_on_1_s),
.tdd_vco_rx_off_1(tdd_vco_rx_off_1_s),
.tdd_vco_tx_on_1(tdd_vco_tx_on_1_s),
.tdd_vco_tx_off_1(tdd_vco_tx_off_1_s),
.tdd_rx_on_1(tdd_rx_on_1_s),
.tdd_rx_off_1(tdd_rx_off_1_s),
.tdd_rx_dp_on_1(tdd_rx_dp_on_1_s),
.tdd_rx_dp_off_1(tdd_rx_dp_off_1_s),
.tdd_tx_on_1(tdd_tx_on_1_s),
.tdd_tx_off_1(tdd_tx_off_1_s),
.tdd_tx_dp_on_1(tdd_tx_dp_on_1_s),
@ -309,10 +269,13 @@ module axi_ad9361_tdd (
.tdd_vco_tx_off_2(tdd_vco_tx_off_2_s),
.tdd_rx_on_2(tdd_rx_on_2_s),
.tdd_rx_off_2(tdd_rx_off_2_s),
.tdd_rx_dp_on_2(tdd_rx_dp_on_2_s),
.tdd_rx_dp_off_2(tdd_rx_dp_off_2_s),
.tdd_tx_on_2(tdd_tx_on_2_s),
.tdd_tx_off_2(tdd_tx_off_2_s),
.tdd_tx_dp_on_2(tdd_tx_dp_on_2_s),
.tdd_tx_dp_off_2(tdd_tx_dp_off_2_s),
.tdd_rx_dp_en(tdd_rx_dp_en_s),
.tdd_tx_dp_en(tdd_tx_dp_en_s),
.tdd_rx_vco_en(tdd_rx_vco_en),
.tdd_tx_vco_en(tdd_tx_vco_en),

252
library/axi_ad9361/axi_ad9361_tx.v
View File

@ -37,139 +37,95 @@
`timescale 1ns/100ps
module axi_ad9361_tx (
// dac interface
dac_clk,
dac_valid,
dac_data,
dac_r1_mode,
adc_data,
// delay interface
up_dld,
up_dwdata,
up_drdata,
delay_clk,
delay_rst,
delay_locked,
// master/slave
dac_sync_in,
dac_sync_out,
// dma interface
dac_enable_i0,
dac_valid_i0,
dac_data_i0,
dac_enable_q0,
dac_valid_q0,
dac_data_q0,
dac_enable_i1,
dac_valid_i1,
dac_data_i1,
dac_enable_q1,
dac_valid_q1,
dac_data_q1,
dac_dovf,
dac_dunf,
// gpio
up_dac_gpio_in,
up_dac_gpio_out,
// processor interface
up_rstn,
up_clk,
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_rack);
module axi_ad9361_tx #(
// parameters
parameter DATAPATH_DISABLE = 0;
parameter ID = 0;
parameter ID = 0,
parameter MODE_1R1T = 0,
parameter DDS_DISABLE = 0,
parameter USERPORTS_DISABLE = 0,
parameter DELAYCNTRL_DISABLE = 0,
parameter IQCORRECTION_DISABLE = 0) (
// dac interface
input dac_clk;
output dac_valid;
output [47:0] dac_data;
output dac_r1_mode;
input [47:0] adc_data;
input dac_clk,
output dac_valid,
output [47:0] dac_data,
output dac_clksel,
output dac_r1_mode,
input [47:0] adc_data,
// delay interface
output [ 9:0] up_dld;
output [49:0] up_dwdata;
input [49:0] up_drdata;
input delay_clk;
output delay_rst;
input delay_locked;
output [15:0] up_dld,
output [79:0] up_dwdata,
input [79:0] up_drdata,
input delay_clk,
output delay_rst,
input delay_locked,
// master/slave
input dac_sync_in;
output dac_sync_out;
input dac_sync_in,
output dac_sync_out,
// dma interface
output dac_enable_i0;
output dac_valid_i0;
input [15:0] dac_data_i0;
output dac_enable_q0;
output dac_valid_q0;
input [15:0] dac_data_q0;
output dac_enable_i1;
output dac_valid_i1;
input [15:0] dac_data_i1;
output dac_enable_q1;
output dac_valid_q1;
input [15:0] dac_data_q1;
input dac_dovf;
input dac_dunf;
output dac_enable_i0,
output dac_valid_i0,
input [15:0] dac_data_i0,
output dac_enable_q0,
output dac_valid_q0,
input [15:0] dac_data_q0,
output dac_enable_i1,
output dac_valid_i1,
input [15:0] dac_data_i1,
output dac_enable_q1,
output dac_valid_q1,
input [15:0] dac_data_q1,
input dac_dovf,
input dac_dunf,
// gpio
input [31:0] up_dac_gpio_in;
output [31:0] up_dac_gpio_out;
input [31:0] up_dac_gpio_in,
output [31:0] up_dac_gpio_out,
// processor interface
input up_rstn;
input up_clk;
input up_wreq;
input [13:0] up_waddr;
input [31:0] up_wdata;
output up_wack;
input up_rreq;
input [13:0] up_raddr;
output [31:0] up_rdata;
output up_rack;
input up_rstn,
input up_clk,
input up_wreq,
input [13:0] up_waddr,
input [31:0] up_wdata,
output up_wack,
input up_rreq,
input [13:0] up_raddr,
output [31:0] up_rdata,
output up_rack);
// configuration settings
localparam CONFIG = (DDS_DISABLE * 64) +
(DELAYCNTRL_DISABLE * 32) +
(MODE_1R1T * 16) +
(USERPORTS_DISABLE * 8) +
(IQCORRECTION_DISABLE * 1);
// internal registers
reg dac_data_sync = 'd0;
reg [ 7:0] dac_rate_cnt = 'd0;
reg dac_valid = 'd0;
reg dac_valid_i0 = 'd0;
reg dac_valid_q0 = 'd0;
reg dac_valid_i1 = 'd0;
reg dac_valid_q1 = 'd0;
reg [31:0] up_rdata = 'd0;
reg up_rack = 'd0;
reg up_wack = 'd0;
reg dac_valid_int = 'd0;
reg dac_valid_i0_int = 'd0;
reg dac_valid_q0_int = 'd0;
reg dac_valid_i1_int = 'd0;
reg dac_valid_q1_int = 'd0;
reg up_wack_int = 'd0;
reg up_rack_int = 'd0;
reg [31:0] up_rdata_int = 'd0;
// internal clock and resets
@ -181,9 +137,9 @@ module axi_ad9361_tx (
wire dac_dds_format_s;
wire [ 7:0] dac_datarate_s;
wire [47:0] dac_data_int_s;
wire [ 5:0] up_wack_s;
wire [ 5:0] up_rack_s;
wire [31:0] up_rdata_s[0:5];
wire up_rack_s[0:5];
wire up_wack_s[0:5];
// master/slave
@ -205,28 +161,36 @@ module axi_ad9361_tx (
// dma interface
assign dac_valid = dac_valid_int;
assign dac_valid_i0 = dac_valid_i0_int;
assign dac_valid_q0 = dac_valid_q0_int;
assign dac_valid_i1 = dac_valid_i1_int;
assign dac_valid_q1 = dac_valid_q1_int;
always @(posedge dac_clk) begin
dac_valid <= (dac_rate_cnt == 8'd0) ? 1'b1 : 1'b0;
dac_valid_i0 <= dac_valid;
dac_valid_q0 <= dac_valid;
dac_valid_i1 <= dac_valid & ~dac_r1_mode;
dac_valid_q1 <= dac_valid & ~dac_r1_mode;
dac_valid_int <= (dac_rate_cnt == 8'd0) ? 1'b1 : 1'b0;
dac_valid_i0_int <= dac_valid_int;
dac_valid_q0_int <= dac_valid_int;
dac_valid_i1_int <= dac_valid_int & ~dac_r1_mode;
dac_valid_q1_int <= dac_valid_int & ~dac_r1_mode;
end
// processor read interface
assign up_wack = up_wack_int;
assign up_rack = up_rack_int;
assign up_rdata = up_rdata_int;
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_rdata <= 'd0;
up_rack <= 'd0;
up_wack <= 'd0;
up_wack_int <= 'd0;
up_rack_int <= 'd0;
up_rdata_int <= 'd0;
end else begin
up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2] |
up_wack_int <= | up_wack_s;
up_rack_int <= | up_rack_s;
up_rdata_int <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2] |
up_rdata_s[3] | up_rdata_s[4] | up_rdata_s[5];
up_rack <= up_rack_s[0] | up_rack_s[1] | up_rack_s[2] |
up_rack_s[3] | up_rack_s[4] | up_rack_s[5];
up_wack <= up_wack_s[0] | up_wack_s[1] | up_wack_s[2] |
up_wack_s[3] | up_wack_s[4] | up_wack_s[5];
end
end
@ -235,11 +199,14 @@ module axi_ad9361_tx (
axi_ad9361_tx_channel #(
.CHANNEL_ID (0),
.Q_OR_I_N (0),
.DATAPATH_DISABLE (DATAPATH_DISABLE))
.DISABLE (0),
.DDS_DISABLE (DDS_DISABLE),
.USERPORTS_DISABLE (USERPORTS_DISABLE),
.IQCORRECTION_DISABLE (IQCORRECTION_DISABLE))
i_tx_channel_0 (
.dac_clk (dac_clk),
.dac_rst (dac_rst),
.dac_valid (dac_valid),
.dac_valid (dac_valid_int),
.dma_data (dac_data_i0),
.adc_data (adc_data[11:0]),
.dac_data (dac_data[11:0]),
@ -264,11 +231,14 @@ module axi_ad9361_tx (
axi_ad9361_tx_channel #(
.CHANNEL_ID (1),
.Q_OR_I_N (1),
.DATAPATH_DISABLE (DATAPATH_DISABLE))
.DISABLE (0),
.DDS_DISABLE (DDS_DISABLE),
.USERPORTS_DISABLE (USERPORTS_DISABLE),
.IQCORRECTION_DISABLE (IQCORRECTION_DISABLE))
i_tx_channel_1 (
.dac_clk (dac_clk),
.dac_rst (dac_rst),
.dac_valid (dac_valid),
.dac_valid (dac_valid_int),
.dma_data (dac_data_q0),
.adc_data (adc_data[23:12]),
.dac_data (dac_data[23:12]),
@ -293,11 +263,14 @@ module axi_ad9361_tx (
axi_ad9361_tx_channel #(
.CHANNEL_ID (2),
.Q_OR_I_N (0),
.DATAPATH_DISABLE (DATAPATH_DISABLE))
.DISABLE (MODE_1R1T),
.DDS_DISABLE (DDS_DISABLE),
.USERPORTS_DISABLE (USERPORTS_DISABLE),
.IQCORRECTION_DISABLE (IQCORRECTION_DISABLE))
i_tx_channel_2 (
.dac_clk (dac_clk),
.dac_rst (dac_rst),
.dac_valid (dac_valid),
.dac_valid (dac_valid_int),
.dma_data (dac_data_i1),
.adc_data (adc_data[35:24]),
.dac_data (dac_data[35:24]),
@ -322,11 +295,14 @@ module axi_ad9361_tx (
axi_ad9361_tx_channel #(
.CHANNEL_ID (3),
.Q_OR_I_N (1),
.DATAPATH_DISABLE (DATAPATH_DISABLE))
.DISABLE (MODE_1R1T),
.DDS_DISABLE (DDS_DISABLE),
.USERPORTS_DISABLE (USERPORTS_DISABLE),
.IQCORRECTION_DISABLE (IQCORRECTION_DISABLE))
i_tx_channel_3 (
.dac_clk (dac_clk),
.dac_rst (dac_rst),
.dac_valid (dac_valid),
.dac_valid (dac_valid_int),
.dma_data (dac_data_q1),
.adc_data (adc_data[47:36]),
.dac_data (dac_data[47:36]),
@ -348,12 +324,18 @@ module axi_ad9361_tx (
// dac common processor interface
up_dac_common #(.ID (ID)) i_up_dac_common (
up_dac_common #(
.ID (ID),
.CONFIG (CONFIG),
.DRP_DISABLE (1),
.USERPORTS_DISABLE (USERPORTS_DISABLE))
i_up_dac_common (
.mmcm_rst (),
.dac_clk (dac_clk),
.dac_rst (dac_rst),
.dac_sync (dac_sync_out),
.dac_frame (),
.dac_clksel (dac_clksel),
.dac_par_type (),
.dac_par_enb (),
.dac_r1_mode (dac_r1_mode),
@ -367,7 +349,7 @@ module axi_ad9361_tx (
.up_drp_wr (),
.up_drp_addr (),
.up_drp_wdata (),
.up_drp_rdata (16'd0),
.up_drp_rdata (32'd0),
.up_drp_ready (1'd0),
.up_drp_locked (1'd1),
.up_usr_chanmax (),
@ -387,7 +369,11 @@ module axi_ad9361_tx (
// dac delay control
up_delay_cntrl #(.DATA_WIDTH(10), .BASE_ADDRESS(6'h12)) i_delay_cntrl (
up_delay_cntrl #(
.DISABLE (DELAYCNTRL_DISABLE),
.DATA_WIDTH(16),
.BASE_ADDRESS(6'h12))
i_delay_cntrl (
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_locked (delay_locked),

178
library/axi_ad9361/axi_ad9361_tx_channel.v
View File

@ -34,90 +34,64 @@
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_ad9361_tx_channel (
// dac interface
dac_clk,
dac_rst,
dac_valid,
dma_data,
adc_data,
dac_data,
dac_data_out,
dac_data_in,
// processor interface
dac_enable,
dac_data_sync,
dac_dds_format,
// bus interface
up_rstn,
up_clk,
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_rack);
module axi_ad9361_tx_channel #(
// parameters
parameter Q_OR_I_N = 0,
parameter CHANNEL_ID = 32'h0,
parameter DISABLE = 0,
parameter DDS_DISABLE = 0,
parameter USERPORTS_DISABLE = 0,
parameter IQCORRECTION_DISABLE = 0) (
// dac interface
input dac_clk,
input dac_rst,
input dac_valid,
input [15:0] dma_data,
input [11:0] adc_data,
output [11:0] dac_data,
output [11:0] dac_data_out,
input [11:0] dac_data_in,
// processor interface
output dac_enable,
input dac_data_sync,
input dac_dds_format,
// bus interface
input up_rstn,
input up_clk,
input up_wreq,
input [13:0] up_waddr,
input [31:0] up_wdata,
output up_wack,
input up_rreq,
input [13:0] up_raddr,
output [31:0] up_rdata,
output up_rack);
// parameters
parameter CHANNEL_ID = 32'h0;
parameter Q_OR_I_N = 0;
parameter DATAPATH_DISABLE = 0;
localparam PRBS_SEL = CHANNEL_ID;
localparam PRBS_P09 = 0;
localparam PRBS_P11 = 1;
localparam PRBS_P15 = 2;
localparam PRBS_P20 = 3;
// dac interface
input dac_clk;
input dac_rst;
input dac_valid;
input [15:0] dma_data;
input [11:0] adc_data;
output [11:0] dac_data;
output [11:0] dac_data_out;
input [11:0] dac_data_in;
// processor interface
output dac_enable;
input dac_data_sync;
input dac_dds_format;
// bus interface
input up_rstn;
input up_clk;
input up_wreq;
input [13:0] up_waddr;
input [31:0] up_wdata;
output up_wack;
input up_rreq;
input [13:0] up_raddr;
output [31:0] up_rdata;
output up_rack;
// internal registers
reg dac_valid_sel = 'd0;
reg dac_enable = 'd0;
reg [11:0] dac_data = 'd0;
reg [11:0] dac_data_out = 'd0;
reg dac_enable_int = 'd0;
reg [11:0] dac_data_int = 'd0;
reg [11:0] dac_data_out_int = 'd0;
reg [23:0] dac_pn_seq = 'd0;
reg [11:0] dac_pn_data = 'd0;
reg [15:0] dac_pat_data = 'd0;
@ -144,6 +118,9 @@ module axi_ad9361_tx_channel (
wire dac_iqcor_enb_s;
wire [15:0] dac_iqcor_coeff_1_s;
wire [15:0] dac_iqcor_coeff_2_s;
wire up_wack_s;
wire up_rack_s;
wire [31:0] up_rdata_s;
// standard prbs functions
@ -273,41 +250,42 @@ module axi_ad9361_tx_channel (
// dac iq correction
assign dac_enable = (DISABLE == 1) ? 'd0 : dac_enable_int;
assign dac_data = (DISABLE == 1) ? 'd0 : dac_data_int;
always @(posedge dac_clk) begin
dac_enable <= (dac_data_sel_s == 4'h2) ? 1'b1 : 1'b0;
dac_enable_int <= (dac_data_sel_s == 4'h2) ? 1'b1 : 1'b0;
if (dac_iqcor_valid_s == 1'b1) begin
dac_data <= dac_iqcor_data_s[15:4];
dac_data_int <= dac_iqcor_data_s[15:4];
end
end
generate
if (DATAPATH_DISABLE == 1) begin
assign dac_iqcor_valid_s = dac_valid;
assign dac_iqcor_data_s = {dac_data_out, 4'd0};
end else begin
ad_iqcor #(.Q_OR_I_N (Q_OR_I_N)) i_ad_iqcor (
ad_iqcor #(
.Q_OR_I_N (Q_OR_I_N),
.DISABLE (IQCORRECTION_DISABLE))
i_ad_iqcor (
.clk (dac_clk),
.valid (dac_valid),
.data_in ({dac_data_out, 4'd0}),
.data_in ({dac_data_out_int, 4'd0}),
.data_iq ({dac_data_in, 4'd0}),
.valid_out (dac_iqcor_valid_s),
.data_out (dac_iqcor_data_s),
.iqcor_enable (dac_iqcor_enb_s),
.iqcor_coeff_1 (dac_iqcor_coeff_1_s),
.iqcor_coeff_2 (dac_iqcor_coeff_2_s));
end
endgenerate
// dac mux
assign dac_data_out = (DISABLE == 1) ? 'd0 : dac_data_out_int;
always @(posedge dac_clk) begin
case (dac_data_sel_s)
4'h9: dac_data_out <= dac_pn_data;
4'h8: dac_data_out <= adc_data;
4'h3: dac_data_out <= 12'd0;
4'h2: dac_data_out <= dma_data[15:4];
4'h1: dac_data_out <= dac_pat_data[15:4];
default: dac_data_out <= dac_dds_data[15:4];
4'h9: dac_data_out_int <= dac_pn_data;
4'h8: dac_data_out_int <= adc_data;
4'h3: dac_data_out_int <= 12'd0;
4'h2: dac_data_out_int <= dma_data[15:4];
4'h1: dac_data_out_int <= dac_pat_data[15:4];
default: dac_data_out_int <= dac_dds_data[15:4];
endcase
end
@ -360,11 +338,9 @@ module axi_ad9361_tx_channel (
// dds
generate
if (DATAPATH_DISABLE == 1) begin
assign dac_dds_data_s = 16'd0;
end else begin
ad_dds i_dds (
ad_dds #(
.DISABLE (DDS_DISABLE))
i_dds (
.clk (dac_clk),
.dds_format (dac_dds_format),
.dds_phase_0 (dac_dds_phase_0),
@ -372,12 +348,19 @@ module axi_ad9361_tx_channel (
.dds_phase_1 (dac_dds_phase_1),
.dds_scale_1 (dac_dds_scale_2_s),
.dds_data (dac_dds_data_s));
end
endgenerate
// single channel processor
up_dac_channel #(.DAC_CHANNEL_ID(CHANNEL_ID)) i_up_dac_channel (
assign up_wack = (DISABLE == 1) ? 'd0 : up_wack_s;
assign up_rack = (DISABLE == 1) ? 'd0 : up_rack_s;
assign up_rdata = (DISABLE == 1) ? 'd0 : up_rdata_s;
up_dac_channel #(
.CHANNEL_ID (CHANNEL_ID),
.DDS_DISABLE (DDS_DISABLE),
.USERPORTS_DISABLE (USERPORTS_DISABLE),
.IQCORRECTION_DISABLE (IQCORRECTION_DISABLE))
i_up_dac_channel (
.dac_clk (dac_clk),
.dac_rst (dac_rst),
.dac_dds_scale_1 (dac_dds_scale_1_s),
@ -389,6 +372,7 @@ module axi_ad9361_tx_channel (
.dac_pat_data_1 (dac_pat_data_1_s),
.dac_pat_data_2 (dac_pat_data_2_s),
.dac_data_sel (dac_data_sel_s),
.dac_iq_mode (),
.dac_iqcor_enb (dac_iqcor_enb_s),
.dac_iqcor_coeff_1 (dac_iqcor_coeff_1_s),
.dac_iqcor_coeff_2 (dac_iqcor_coeff_2_s),
@ -411,11 +395,11 @@ module axi_ad9361_tx_channel (
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack),
.up_wack (up_wack_s),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata),
.up_rack (up_rack));
.up_rdata (up_rdata_s),
.up_rack (up_rack_s));
endmodule

583
library/axi_ad9361/xilinx/axi_ad9361_cmos_if.v Normal file
View File

@ -0,0 +1,583 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_ad9361_cmos_if (
// physical interface (receive)
rx_clk_in,
rx_frame_in,
rx_data_in,
// physical interface (transmit)
tx_clk_out,
tx_frame_out,
tx_data_out,
// ensm control
enable,
txnrx,
// clock (common to both receive and transmit)
rst,
clk,
l_clk,
// receive data path interface
adc_valid,
adc_data,
adc_status,
adc_r1_mode,
adc_ddr_edgesel,
// transmit data path interface
dac_valid,
dac_data,
dac_clksel,
dac_r1_mode,
// tdd interface
tdd_enable,
tdd_txnrx,
tdd_mode,
// delay interface
mmcm_rst,
up_clk,
up_enable,
up_txnrx,
up_adc_dld,
up_adc_dwdata,
up_adc_drdata,
up_dac_dld,
up_dac_dwdata,
up_dac_drdata,
delay_clk,
delay_rst,
delay_locked);
// this parameter controls the buffer type based on the target device.
parameter DEVICE_TYPE = 0;
parameter DAC_IODELAY_ENABLE = 0;
parameter IO_DELAY_GROUP = "dev_if_delay_group";
// physical interface (receive)
input rx_clk_in;
input rx_frame_in;
input [11:0] rx_data_in;
// physical interface (transmit)
output tx_clk_out;
output tx_frame_out;
output [11:0] tx_data_out;
// ensm control
output enable;
output txnrx;
// clock (common to both receive and transmit)
input rst;
input clk;
output l_clk;
// receive data path interface
output adc_valid;
output [47:0] adc_data;
output adc_status;
input adc_r1_mode;
input adc_ddr_edgesel;
// transmit data path interface
input dac_valid;
input [47:0] dac_data;
input dac_clksel;
input dac_r1_mode;
// tdd interface
input tdd_enable;
input tdd_txnrx;
input tdd_mode;
// delay interface
input mmcm_rst;
input up_clk;
input up_enable;
input up_txnrx;
input [12:0] up_adc_dld;
input [64:0] up_adc_dwdata;
output [64:0] up_adc_drdata;
input [15:0] up_dac_dld;
input [79:0] up_dac_dwdata;
output [79:0] up_dac_drdata;
input delay_clk;
input delay_rst;
output delay_locked;
// internal registers
reg [ 1:0] rx_frame = 0;
reg [11:0] rx_data_p = 0;
reg rx_error_r1 = 'd0;
reg rx_valid_r1 = 'd0;
reg [23:0] rx_data_r1 = 'd0;
reg rx_error_r2 = 'd0;
reg rx_valid_r2 = 'd0;
reg [47:0] rx_data_r2 = 'd0;
reg adc_p_valid = 'd0;
reg [47:0] adc_p_data = 'd0;
reg adc_p_status = 'd0;
reg adc_n_valid = 'd0;
reg [47:0] adc_n_data = 'd0;
reg adc_n_status = 'd0;
reg adc_valid_int = 'd0;
reg [47:0] adc_data_int = 'd0;
reg adc_status_int = 'd0;
reg adc_valid = 'd0;
reg [47:0] adc_data = 'd0;
reg adc_status = 'd0;
reg [ 1:0] tx_data_cnt = 'd0;
reg [47:0] tx_data = 'd0;
reg tx_frame_p = 'd0;
reg tx_frame_n = 'd0;
reg [11:0] tx_data_p = 'd0;
reg [11:0] tx_data_n = 'd0;
reg tx_n_frame_p = 'd0;
reg tx_n_frame_n = 'd0;
reg [11:0] tx_n_data_p = 'd0;
reg [11:0] tx_n_data_n = 'd0;
reg tx_p_frame_p = 'd0;
reg tx_p_frame_n = 'd0;
reg [11:0] tx_p_data_p = 'd0;
reg [11:0] tx_p_data_n = 'd0;
reg up_enable_int = 'd0;
reg up_txnrx_int = 'd0;
reg enable_up_m1 = 'd0;
reg txnrx_up_m1 = 'd0;
reg enable_up = 'd0;
reg txnrx_up = 'd0;
reg enable_int = 'd0;
reg txnrx_int = 'd0;
reg enable_n_int = 'd0;
reg txnrx_n_int = 'd0;
reg enable_p_int = 'd0;
reg txnrx_p_int = 'd0;
reg dac_clkdata_p = 'd0;
reg dac_clkdata_n = 'd0;
reg locked_m1 = 'd0;
reg locked = 'd0;
// internal signals
wire [ 1:0] rx_frame_s;
wire [ 3:0] rx_frame_4_s;
wire [ 2:0] tx_data_sel_s;
wire [11:0] rx_data_p_s;
wire [11:0] rx_data_n_s;
wire rx_frame_p_s;
wire rx_frame_n_s;
wire locked_s;
genvar l_inst;
// receive data path interface
assign rx_frame_s = {rx_frame_p_s, rx_frame_n_s};
assign rx_frame_4_s = {rx_frame_s, rx_frame};
always @(posedge l_clk) begin
rx_frame <= rx_frame_s;
rx_data_p <= rx_data_p_s;
end
// receive data path for single rf, frame is expected to qualify i only
always @(posedge l_clk) begin
rx_error_r1 <= ~^ rx_frame_s;
rx_valid_r1 <= ^ rx_frame_s;
case (rx_frame_s)
2'b01: rx_data_r1 <= {rx_data_p_s, rx_data_n_s};
2'b10: rx_data_r1 <= {rx_data_n_s, rx_data_p};
default: rx_data_r1 <= 24'd0;
endcase
end
// receive data path for dual rf, frame is expected to qualify iq for rf-1 only
always @(posedge l_clk) begin
rx_error_r2 <= ((rx_frame_4_s == 4'b0011) || (rx_frame_4_s == 4'b1100) ||
(rx_frame_4_s == 4'b1001) || (rx_frame_4_s == 4'b0110)) ? 1'b0 : 1'b1;
rx_valid_r2 <= ((rx_frame_4_s == 4'b0011) ||
(rx_frame_4_s == 4'b1001)) ? 1'b1 : 1'b0;
case (rx_frame_s)
2'b11: rx_data_r2[23: 0] <= {rx_data_p_s, rx_data_n_s};
2'b01: rx_data_r2[23: 0] <= {rx_data_n_s, rx_data_p};
default: rx_data_r2[23: 0] <= rx_data_r2[23: 0];
endcase
case (rx_frame_s)
2'b00: rx_data_r2[47:24] <= {rx_data_p_s, rx_data_n_s};
2'b10: rx_data_r2[47:24] <= {rx_data_n_s, rx_data_p};
default: rx_data_r2[47:24] <= rx_data_r2[47:24];
endcase
end
// receive data path mux
always @(posedge l_clk) begin
if (adc_r1_mode == 1'b1) begin
adc_p_valid <= rx_valid_r1;
adc_p_data <= {24'd0, rx_data_r1};
adc_p_status <= ~rx_error_r1;
end else begin
adc_p_valid <= rx_valid_r2;
adc_p_data <= rx_data_r2;
adc_p_status <= ~rx_error_r2;
end
end
// transfer to a synchronous common clock
always @(negedge l_clk) begin
adc_n_valid <= adc_p_valid;
adc_n_data <= adc_p_data;
adc_n_status <= adc_p_status;
end
always @(posedge clk) begin
adc_valid_int <= adc_n_valid;
adc_data_int <= adc_n_data;
adc_status_int <= adc_n_status;
adc_valid <= adc_valid_int;
if (adc_valid_int == 1'b1) begin
adc_data <= adc_data_int;
end
adc_status <= adc_status_int & locked;
end
// transmit data path mux (reverse of what receive does above)
// the count simply selets the data muxing on the ddr outputs
assign tx_data_sel_s = {tx_data_cnt[1], dac_r1_mode, tx_data_cnt[0]};
always @(posedge clk) begin
if (dac_valid == 1'b1) begin
tx_data_cnt <= 2'b10;
end else if (tx_data_cnt[1] == 1'b1) begin
tx_data_cnt <= tx_data_cnt + 1'b1;
end
if (dac_valid == 1'b1) begin
tx_data <= dac_data;
end
case (tx_data_sel_s)
3'b101: begin
tx_frame_p <= 1'b0;
tx_frame_n <= 1'b0;
tx_data_p <= tx_data[35:24];
tx_data_n <= tx_data[47:36];
end
3'b100: begin
tx_frame_p <= 1'b1;
tx_frame_n <= 1'b1;
tx_data_p <= tx_data[11: 0];
tx_data_n <= tx_data[23:12];
end
3'b110: begin
tx_frame_p <= 1'b1;
tx_frame_n <= 1'b0;
tx_data_p <= tx_data[11: 0];
tx_data_n <= tx_data[23:12];
end
default: begin
tx_frame_p <= 1'd0;
tx_frame_n <= 1'd0;
tx_data_p <= 12'd0;
tx_data_n <= 12'd0;
end
endcase
end
// transfer data from a synchronous clock (skew less than 2ns)
always @(negedge clk) begin
tx_n_frame_p <= tx_frame_p;
tx_n_frame_n <= tx_frame_n;
tx_n_data_p <= tx_data_p;
tx_n_data_n <= tx_data_n;
end
always @(posedge l_clk) begin
tx_p_frame_p <= tx_n_frame_p;
tx_p_frame_n <= tx_n_frame_n;
tx_p_data_p <= tx_n_data_p;
tx_p_data_n <= tx_n_data_n;
end
// tdd/ensm control
always @(posedge up_clk) begin
up_enable_int <= up_enable;
up_txnrx_int <= up_txnrx;
end
always @(posedge clk or posedge rst) begin
if (rst == 1'b1) begin
enable_up_m1 <= 1'b0;
txnrx_up_m1 <= 1'b0;
enable_up <= 1'b0;
txnrx_up <= 1'b0;
end else begin
enable_up_m1 <= up_enable_int;
txnrx_up_m1 <= up_txnrx_int;
enable_up <= enable_up_m1;
txnrx_up <= txnrx_up_m1;
end
end
always @(posedge clk) begin
if (tdd_mode == 1'b1) begin
enable_int <= tdd_enable;
txnrx_int <= tdd_txnrx;
end else begin
enable_int <= enable_up;
txnrx_int <= txnrx_up;
end
end
always @(negedge clk) begin
enable_n_int <= enable_int;
txnrx_n_int <= txnrx_int;
end
always @(posedge l_clk) begin
enable_p_int <= enable_n_int;
txnrx_p_int <= txnrx_n_int;
end
always @(posedge l_clk) begin
dac_clkdata_p <= dac_clksel;
dac_clkdata_n <= ~dac_clksel;
end
// receive data interface, ibuf -> idelay -> iddr
generate
for (l_inst = 0; l_inst <= 11; l_inst = l_inst + 1) begin: g_rx_data
ad_cmos_in #(
.SINGLE_ENDED (1),
.DEVICE_TYPE (DEVICE_TYPE),
.IODELAY_CTRL (0),
.IODELAY_GROUP (IO_DELAY_GROUP))
i_rx_data (
.rx_clk (l_clk),
.rx_data_in (rx_data_in[l_inst]),
.rx_data_p (rx_data_p_s[l_inst]),
.rx_data_n (rx_data_n_s[l_inst]),
.up_clk (up_clk),
.up_dld (up_adc_dld[l_inst]),
.up_dwdata (up_adc_dwdata[((l_inst*5)+4):(l_inst*5)]),
.up_drdata (up_adc_drdata[((l_inst*5)+4):(l_inst*5)]),
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_locked ());
end
endgenerate
// receive frame interface, ibuf -> idelay -> iddr
ad_cmos_in #(
.SINGLE_ENDED (1),
.DEVICE_TYPE (DEVICE_TYPE),
.IODELAY_CTRL (1),
.IODELAY_GROUP (IO_DELAY_GROUP))
i_rx_frame (
.rx_clk (l_clk),
.rx_data_in (rx_frame_in),
.rx_data_p (rx_frame_p_s),
.rx_data_n (rx_frame_n_s),
.up_clk (up_clk),
.up_dld (up_adc_dld[12]),
.up_dwdata (up_adc_dwdata[64:60]),
.up_drdata (up_adc_drdata[64:60]),
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_locked (delay_locked));
// transmit data interface, oddr -> obuf
generate
for (l_inst = 0; l_inst <= 11; l_inst = l_inst + 1) begin: g_tx_data
ad_cmos_out #(
.DEVICE_TYPE (DEVICE_TYPE),
.SINGLE_ENDED (1),
.IODELAY_ENABLE (DAC_IODELAY_ENABLE),
.IODELAY_CTRL (0),
.IODELAY_GROUP (IO_DELAY_GROUP))
i_tx_data (
.tx_clk (l_clk),
.tx_data_p (tx_p_data_p[l_inst]),
.tx_data_n (tx_p_data_n[l_inst]),
.tx_data_out (tx_data_out[l_inst]),
.up_clk (up_clk),
.up_dld (up_dac_dld[l_inst]),
.up_dwdata (up_dac_dwdata[((l_inst*5)+4):(l_inst*5)]),
.up_drdata (up_dac_drdata[((l_inst*5)+4):(l_inst*5)]),
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_locked ());
end
endgenerate
// transmit frame interface, oddr -> obuf
ad_cmos_out #(
.DEVICE_TYPE (DEVICE_TYPE),
.SINGLE_ENDED (1),
.IODELAY_ENABLE (DAC_IODELAY_ENABLE),
.IODELAY_CTRL (0),
.IODELAY_GROUP (IO_DELAY_GROUP))
i_tx_frame (
.tx_clk (l_clk),
.tx_data_p (tx_p_frame_p),
.tx_data_n (tx_p_frame_n),
.tx_data_out (tx_frame_out),
.up_clk (up_clk),
.up_dld (up_dac_dld[12]),
.up_dwdata (up_dac_dwdata[64:60]),
.up_drdata (up_dac_drdata[64:60]),
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_locked ());
// transmit clock interface, oddr -> obuf
ad_cmos_out #(
.DEVICE_TYPE (DEVICE_TYPE),
.SINGLE_ENDED (1),
.IODELAY_ENABLE (DAC_IODELAY_ENABLE),
.IODELAY_CTRL (0),
.IODELAY_GROUP (IO_DELAY_GROUP))
i_tx_clk (
.tx_clk (l_clk),
.tx_data_p (dac_clkdata_p),
.tx_data_n (dac_clkdata_n),
.tx_data_out (tx_clk_out),
.up_clk (up_clk),
.up_dld (up_dac_dld[13]),
.up_dwdata (up_dac_dwdata[69:65]),
.up_drdata (up_dac_drdata[69:65]),
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_locked ());
// enable, oddr -> obuf
ad_cmos_out #(
.DEVICE_TYPE (DEVICE_TYPE),
.SINGLE_ENDED (1),
.IODELAY_ENABLE (DAC_IODELAY_ENABLE),
.IODELAY_CTRL (0),
.IODELAY_GROUP (IO_DELAY_GROUP))
i_enable (
.tx_clk (l_clk),
.tx_data_p (enable_p_int),
.tx_data_n (enable_p_int),
.tx_data_out (enable),
.up_clk (up_clk),
.up_dld (up_dac_dld[14]),
.up_dwdata (up_dac_dwdata[74:70]),
.up_drdata (up_dac_drdata[74:70]),
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_locked ());
// txnrx, oddr -> obuf
ad_cmos_out #(
.DEVICE_TYPE (DEVICE_TYPE),
.SINGLE_ENDED (1),
.IODELAY_ENABLE (DAC_IODELAY_ENABLE),
.IODELAY_CTRL (0),
.IODELAY_GROUP (IO_DELAY_GROUP))
i_txnrx (
.tx_clk (l_clk),
.tx_data_p (txnrx_p_int),
.tx_data_n (txnrx_p_int),
.tx_data_out (txnrx),
.up_clk (up_clk),
.up_dld (up_dac_dld[15]),
.up_dwdata (up_dac_dwdata[79:75]),
.up_drdata (up_dac_drdata[79:75]),
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_locked ());
// device clock interface (receive clock)
always @(posedge clk) begin
locked_m1 <= locked_s;
locked <= locked_m1;
end
ad_cmos_clk #(
.DEVICE_TYPE (DEVICE_TYPE))
i_clk (
.rst (mmcm_rst),
.locked (locked_s),
.clk_in (rx_clk_in),
.clk (l_clk));
endmodule
// ***************************************************************************
// ***************************************************************************

69
library/axi_ad9361/axi_ad9361_dev_if.v → library/axi_ad9361/xilinx/axi_ad9361_lvds_if.v
View File

@ -34,12 +34,10 @@
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// This interface includes both the transmit and receive components -
// They both uses the same clock (sourced from the receiving side).
`timescale 1ns/100ps
module axi_ad9361_dev_if (
module axi_ad9361_lvds_if (
// physical interface (receive)
@ -82,6 +80,7 @@ module axi_ad9361_dev_if (
dac_valid,
dac_data,
dac_clksel,
dac_r1_mode,
// tdd interface
@ -92,6 +91,7 @@ module axi_ad9361_dev_if (
// delay interface
mmcm_rst,
up_clk,
up_enable,
up_txnrx,
@ -103,7 +103,17 @@ module axi_ad9361_dev_if (
up_dac_drdata,
delay_clk,
delay_rst,
delay_locked);
delay_locked,
//drp interface
up_drp_sel,
up_drp_wr,
up_drp_addr,
up_drp_wdata,
up_drp_rdata,
up_drp_ready,
up_drp_locked);
// this parameter controls the buffer type based on the target device.
@ -152,6 +162,7 @@ module axi_ad9361_dev_if (
input dac_valid;
input [47:0] dac_data;
input dac_clksel;
input dac_r1_mode;
// tdd interface
@ -162,6 +173,7 @@ module axi_ad9361_dev_if (
// delay interface
input mmcm_rst;
input up_clk;
input up_enable;
input up_txnrx;
@ -175,6 +187,16 @@ module axi_ad9361_dev_if (
input delay_rst;
output delay_locked;
//drp interface
input up_drp_sel;
input up_drp_wr;
input [11:0] up_drp_addr;
input [31:0] up_drp_wdata;
output [31:0] up_drp_rdata;
output up_drp_ready;
output up_drp_locked;
// internal registers
reg [ 5:0] rx_data_p = 0;
@ -227,6 +249,10 @@ module axi_ad9361_dev_if (
reg txnrx_n_int = 'd0;
reg enable_p_int = 'd0;
reg txnrx_p_int = 'd0;
reg dac_clkdata_p = 'd0;
reg dac_clkdata_n = 'd0;
reg locked_m1 = 'd0;
reg locked = 'd0;
// internal signals
@ -237,6 +263,13 @@ module axi_ad9361_dev_if (
wire [ 5:0] rx_data_n_s;
wire rx_frame_p_s;
wire rx_frame_n_s;
wire locked_s;
// drp interface signals
assign up_drp_rdata = 32'd0;
assign up_drp_ready = 1'd0;
assign up_drp_locked = 1'd1;
genvar l_inst;
@ -328,7 +361,7 @@ module axi_ad9361_dev_if (
if (adc_valid_int == 1'b1) begin
adc_data <= adc_data_int;
end
adc_status <= adc_status_int;
adc_status <= adc_status_int & locked;
end
// transmit data path mux (reverse of what receive does above)
@ -449,6 +482,11 @@ module axi_ad9361_dev_if (
txnrx_p_int <= txnrx_n_int;
end
always @(posedge l_clk) begin
dac_clkdata_p <= dac_clksel;
dac_clkdata_n <= ~dac_clksel;
end
// receive data interface, ibuf -> idelay -> iddr
generate
@ -551,8 +589,8 @@ module axi_ad9361_dev_if (
.IODELAY_GROUP (IO_DELAY_GROUP))
i_tx_clk (
.tx_clk (l_clk),
.tx_data_p (1'b0),
.tx_data_n (1'b1),
.tx_data_p (dac_clkdata_p),
.tx_data_n (dac_clkdata_n),
.tx_data_out_p (tx_clk_out_p),
.tx_data_out_n (tx_clk_out_n),
.up_clk (up_clk),
@ -565,7 +603,7 @@ module axi_ad9361_dev_if (
// enable, oddr -> obuf
ad_lvds_out #(
ad_cmos_out #(
.DEVICE_TYPE (DEVICE_TYPE),
.SINGLE_ENDED (1),
.IODELAY_ENABLE (DAC_IODELAY_ENABLE),
@ -575,8 +613,7 @@ module axi_ad9361_dev_if (
.tx_clk (l_clk),
.tx_data_p (enable_p_int),
.tx_data_n (enable_p_int),
.tx_data_out_p (enable),
.tx_data_out_n (),
.tx_data_out (enable),
.up_clk (up_clk),
.up_dld (up_dac_dld[8]),
.up_dwdata (up_dac_dwdata[44:40]),
@ -587,7 +624,7 @@ module axi_ad9361_dev_if (
// txnrx, oddr -> obuf
ad_lvds_out #(
ad_cmos_out #(
.DEVICE_TYPE (DEVICE_TYPE),
.SINGLE_ENDED (1),
.IODELAY_ENABLE (DAC_IODELAY_ENABLE),
@ -597,8 +634,7 @@ module axi_ad9361_dev_if (
.tx_clk (l_clk),
.tx_data_p (txnrx_p_int),
.tx_data_n (txnrx_p_int),
.tx_data_out_p (txnrx),
.tx_data_out_n (),
.tx_data_out (txnrx),
.up_clk (up_clk),
.up_dld (up_dac_dld[9]),
.up_dwdata (up_dac_dwdata[49:45]),
@ -609,9 +645,16 @@ module axi_ad9361_dev_if (
// device clock interface (receive clock)
always @(posedge clk) begin
locked_m1 <= locked_s;
locked <= locked_m1;
end
ad_lvds_clk #(
.DEVICE_TYPE (DEVICE_TYPE))
i_clk (
.rst (mmcm_rst),
.locked (locked_s),
.clk_in_p (rx_clk_in_p),
.clk_in_n (rx_clk_in_n),
.clk (l_clk));

70
library/axi_ad9371/Makefile Normal file
View File

@ -0,0 +1,70 @@
####################################################################################
####################################################################################
## Copyright 2011(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################
####################################################################################
M_DEPS += ../common/ad_axi_ip_constr.xdc
M_DEPS += ../common/ad_datafmt.v
M_DEPS += ../common/ad_dcfilter.v
M_DEPS += ../common/ad_dds.v
M_DEPS += ../common/ad_dds_1.v
M_DEPS += ../common/ad_dds_sine.v
M_DEPS += ../common/ad_iqcor.v
M_DEPS += ../common/ad_rst.v
M_DEPS += ../common/ad_xcvr_rx_if.v
M_DEPS += ../common/up_adc_channel.v
M_DEPS += ../common/up_adc_common.v
M_DEPS += ../common/up_axi.v
M_DEPS += ../common/up_clock_mon.v
M_DEPS += ../common/up_dac_channel.v
M_DEPS += ../common/up_dac_common.v
M_DEPS += ../common/up_xfer_cntrl.v
M_DEPS += ../common/up_xfer_status.v
M_DEPS += ../scripts/adi_env.tcl
M_DEPS += ../scripts/adi_ip.tcl
M_DEPS += ../xilinx/common/ad_mul.v
M_DEPS += axi_ad9371.v
M_DEPS += axi_ad9371_if.v
M_DEPS += axi_ad9371_ip.tcl
M_DEPS += axi_ad9371_rx.v
M_DEPS += axi_ad9371_rx_channel.v
M_DEPS += axi_ad9371_rx_os.v
M_DEPS += axi_ad9371_tx.v
M_DEPS += axi_ad9371_tx_channel.v
M_VIVADO := vivado -mode batch -source
M_FLIST := *.cache
M_FLIST += *.data
M_FLIST += *.xpr
M_FLIST += *.log
M_FLIST += component.xml
M_FLIST += *.jou
M_FLIST += xgui
M_FLIST += *.ip_user_files
M_FLIST += *.srcs
M_FLIST += *.hw
M_FLIST += *.sim
M_FLIST += .Xil
.PHONY: all clean clean-all
all: axi_ad9371.xpr
clean:clean-all
clean-all:
rm -rf $(M_FLIST)
axi_ad9371.xpr: $(M_DEPS)
-rm -rf $(M_FLIST)
$(M_VIVADO) axi_ad9371_ip.tcl >> axi_ad9371_ip.log 2>&1
####################################################################################
####################################################################################

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library/axi_ad9371/axi_ad9371.v Normal file
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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_ad9371 (
// receive
adc_clk,
adc_rx_valid,
adc_rx_sof,
adc_rx_data,
adc_rx_ready,
adc_os_clk,
adc_rx_os_valid,
adc_rx_os_sof,
adc_rx_os_data,
adc_rx_os_ready,
// transmit
dac_clk,
dac_tx_valid,
dac_tx_data,
dac_tx_ready,
// master/slave
dac_sync_in,
dac_sync_out,
// dma interface
adc_enable_i0,
adc_valid_i0,
adc_data_i0,
adc_enable_q0,
adc_valid_q0,
adc_data_q0,
adc_enable_i1,
adc_valid_i1,
adc_data_i1,
adc_enable_q1,
adc_valid_q1,
adc_data_q1,
adc_dovf,
adc_dunf,
adc_os_enable_i0,
adc_os_valid_i0,
adc_os_data_i0,
adc_os_enable_q0,
adc_os_valid_q0,
adc_os_data_q0,
adc_os_dovf,
adc_os_dunf,
dac_enable_i0,
dac_valid_i0,
dac_data_i0,
dac_enable_q0,
dac_valid_q0,
dac_data_q0,
dac_enable_i1,
dac_valid_i1,
dac_data_i1,
dac_enable_q1,
dac_valid_q1,
dac_data_q1,
dac_dovf,
dac_dunf,
// axi interface
s_axi_aclk,
s_axi_aresetn,
s_axi_awvalid,
s_axi_awaddr,
s_axi_awprot,
s_axi_awready,
s_axi_wvalid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wready,
s_axi_bvalid,
s_axi_bresp,
s_axi_bready,
s_axi_arvalid,
s_axi_araddr,
s_axi_arprot,
s_axi_arready,
s_axi_rvalid,
s_axi_rdata,
s_axi_rresp,
s_axi_rready);
// parameters
parameter ID = 0;
parameter DEVICE_TYPE = 0;
parameter DAC_DATAPATH_DISABLE = 0;
parameter ADC_DATAPATH_DISABLE = 0;
// receive
input adc_clk;
input adc_rx_valid;
input [ 3:0] adc_rx_sof;
input [ 63:0] adc_rx_data;
output adc_rx_ready;
input adc_os_clk;
input adc_rx_os_valid;
input [ 3:0] adc_rx_os_sof;
input [ 63:0] adc_rx_os_data;
output adc_rx_os_ready;
// transmit
input dac_clk;
output dac_tx_valid;
output [127:0] dac_tx_data;
input dac_tx_ready;
// master/slave
input dac_sync_in;
output dac_sync_out;
// dma interface
output adc_enable_i0;
output adc_valid_i0;
output [ 15:0] adc_data_i0;
output adc_enable_q0;
output adc_valid_q0;
output [ 15:0] adc_data_q0;
output adc_enable_i1;
output adc_valid_i1;
output [ 15:0] adc_data_i1;
output adc_enable_q1;
output adc_valid_q1;
output [ 15:0] adc_data_q1;
input adc_dovf;
input adc_dunf;
output adc_os_enable_i0;
output adc_os_valid_i0;
output [ 31:0] adc_os_data_i0;
output adc_os_enable_q0;
output adc_os_valid_q0;
output [ 31:0] adc_os_data_q0;
input adc_os_dovf;
input adc_os_dunf;
output dac_enable_i0;
output dac_valid_i0;
input [ 31:0] dac_data_i0;
output dac_enable_q0;
output dac_valid_q0;
input [ 31:0] dac_data_q0;
output dac_enable_i1;
output dac_valid_i1;
input [ 31:0] dac_data_i1;
output dac_enable_q1;
output dac_valid_q1;
input [ 31:0] dac_data_q1;
input dac_dovf;
input dac_dunf;
// axi interface
input s_axi_aclk;
input s_axi_aresetn;
input s_axi_awvalid;
input [ 31:0] s_axi_awaddr;
input [ 2:0] s_axi_awprot;
output s_axi_awready;
input s_axi_wvalid;
input [ 31:0] s_axi_wdata;
input [ 3:0] s_axi_wstrb;
output s_axi_wready;
output s_axi_bvalid;
output [ 1:0] s_axi_bresp;
input s_axi_bready;
input s_axi_arvalid;
input [ 31:0] s_axi_araddr;
input [ 2:0] s_axi_arprot;
output s_axi_arready;
output s_axi_rvalid;
output [ 31:0] s_axi_rdata;
output [ 1:0] s_axi_rresp;
input s_axi_rready;
// internal registers
reg up_wack = 'd0;
reg up_rack = 'd0;
reg [ 31:0] up_rdata = 'd0;
// internal signals
wire up_clk;
wire up_rstn;
wire [ 63:0] adc_data_s;
wire adc_os_valid_s;
wire [ 63:0] adc_os_data_s;
wire [127:0] dac_data_s;
wire up_wreq_s;
wire [ 13:0] up_waddr_s;
wire [ 31:0] up_wdata_s;
wire [ 2:0] up_wack_s;
wire up_rreq_s;
wire [ 13:0] up_raddr_s;
wire [ 31:0] up_rdata_s[0:2];
wire [ 2:0] up_rack_s;
// signal name changes
assign up_clk = s_axi_aclk;
assign up_rstn = s_axi_aresetn;
// defaults
assign dac_tx_valid = 1'b1;
assign adc_rx_ready = 1'b1;
assign adc_rx_os_ready = 1'b1;
// processor read interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_wack <= 'd0;
up_rack <= 'd0;
up_rdata <= 'd0;
end else begin
up_wack <= | up_wack_s;
up_rack <= | up_rack_s;
up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2];
end
end
// device interface
axi_ad9371_if #(
.DEVICE_TYPE (DEVICE_TYPE))
i_if (
.adc_clk (adc_clk),
.adc_rx_sof (adc_rx_sof),
.adc_rx_data (adc_rx_data),
.adc_os_clk (adc_os_clk),
.adc_rx_os_sof (adc_rx_os_sof),
.adc_rx_os_data (adc_rx_os_data),
.adc_data (adc_data_s),
.adc_os_valid (adc_os_valid_s),
.adc_os_data (adc_os_data_s),
.dac_clk (dac_clk),
.dac_tx_data (dac_tx_data),
.dac_data (dac_data_s));
// receive
axi_ad9371_rx #(
.ID (ID),
.DATAPATH_DISABLE (ADC_DATAPATH_DISABLE))
i_rx (
.adc_rst (adc_rst),
.adc_clk (adc_clk),
.adc_data (adc_data_s),
.adc_enable_i0 (adc_enable_i0),
.adc_valid_i0 (adc_valid_i0),
.adc_data_i0 (adc_data_i0),
.adc_enable_q0 (adc_enable_q0),
.adc_valid_q0 (adc_valid_q0),
.adc_data_q0 (adc_data_q0),
.adc_enable_i1 (adc_enable_i1),
.adc_valid_i1 (adc_valid_i1),
.adc_data_i1 (adc_data_i1),
.adc_enable_q1 (adc_enable_q1),
.adc_valid_q1 (adc_valid_q1),
.adc_data_q1 (adc_data_q1),
.adc_dovf (adc_dovf),
.adc_dunf (adc_dunf),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s[0]),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s[0]),
.up_rack (up_rack_s[0]));
// receive (o/s)
axi_ad9371_rx_os #(
.ID (ID),
.DATAPATH_DISABLE (ADC_DATAPATH_DISABLE))
i_rx_os (
.adc_os_rst (adc_os_rst),
.adc_os_clk (adc_os_clk),
.adc_os_valid (adc_os_valid_s),
.adc_os_data (adc_os_data_s),
.adc_os_enable_i0 (adc_os_enable_i0),
.adc_os_valid_i0 (adc_os_valid_i0),
.adc_os_data_i0 (adc_os_data_i0),
.adc_os_enable_q0 (adc_os_enable_q0),
.adc_os_valid_q0 (adc_os_valid_q0),
.adc_os_data_q0 (adc_os_data_q0),
.adc_os_dovf (adc_os_dovf),
.adc_os_dunf (adc_os_dunf),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s[1]),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s[1]),
.up_rack (up_rack_s[1]));
// transmit
axi_ad9371_tx #(
.ID (ID),
.DATAPATH_DISABLE (DAC_DATAPATH_DISABLE))
i_tx (
.dac_rst (dac_rst),
.dac_clk (dac_clk),
.dac_data (dac_data_s),
.dac_sync_in (dac_sync_in),
.dac_sync_out (dac_sync_out),
.dac_enable_i0 (dac_enable_i0),
.dac_valid_i0 (dac_valid_i0),
.dac_data_i0 (dac_data_i0),
.dac_enable_q0 (dac_enable_q0),
.dac_valid_q0 (dac_valid_q0),
.dac_data_q0 (dac_data_q0),
.dac_enable_i1 (dac_enable_i1),
.dac_valid_i1 (dac_valid_i1),
.dac_data_i1 (dac_data_i1),
.dac_enable_q1 (dac_enable_q1),
.dac_valid_q1 (dac_valid_q1),
.dac_data_q1 (dac_data_q1),
.dac_dovf(dac_dovf),
.dac_dunf(dac_dunf),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s[2]),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s[2]),
.up_rack (up_rack_s[2]));
// axi interface
up_axi i_up_axi (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_axi_awvalid (s_axi_awvalid),
.up_axi_awaddr (s_axi_awaddr),
.up_axi_awready (s_axi_awready),
.up_axi_wvalid (s_axi_wvalid),
.up_axi_wdata (s_axi_wdata),
.up_axi_wstrb (s_axi_wstrb),
.up_axi_wready (s_axi_wready),
.up_axi_bvalid (s_axi_bvalid),
.up_axi_bresp (s_axi_bresp),
.up_axi_bready (s_axi_bready),
.up_axi_arvalid (s_axi_arvalid),
.up_axi_araddr (s_axi_araddr),
.up_axi_arready (s_axi_arready),
.up_axi_rvalid (s_axi_rvalid),
.up_axi_rresp (s_axi_rresp),
.up_axi_rdata (s_axi_rdata),
.up_axi_rready (s_axi_rready),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata),
.up_rack (up_rack));
endmodule
// ***************************************************************************
// ***************************************************************************

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library/axi_ad9371/axi_ad9371_hw.tcl Executable file
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package require -exact qsys 13.0
source ../scripts/adi_env.tcl
source ../scripts/adi_ip_alt.tcl
set_module_property NAME axi_ad9371
set_module_property DESCRIPTION "AXI AD9371 Interface"
set_module_property VERSION 1.0
set_module_property GROUP "Analog Devices"
set_module_property DISPLAY_NAME axi_ad9371
# files
add_fileset quartus_synth QUARTUS_SYNTH "" "Quartus Synthesis"
set_fileset_property quartus_synth TOP_LEVEL axi_ad9371
add_fileset_file ad_rst.v VERILOG PATH $ad_hdl_dir/library/common/ad_rst.v
add_fileset_file ad_mul.v VERILOG PATH $ad_hdl_dir/library/altera/common/ad_mul.v
add_fileset_file ad_dds_sine.v VERILOG PATH $ad_hdl_dir/library/common/ad_dds_sine.v
add_fileset_file ad_dds_1.v VERILOG PATH $ad_hdl_dir/library/common/ad_dds_1.v
add_fileset_file ad_dds.v VERILOG PATH $ad_hdl_dir/library/common/ad_dds.v
add_fileset_file ad_datafmt.v VERILOG PATH $ad_hdl_dir/library/common/ad_datafmt.v
add_fileset_file ad_dcfilter.v VERILOG PATH $ad_hdl_dir/library/altera/common/ad_dcfilter.v
add_fileset_file ad_iqcor.v VERILOG PATH $ad_hdl_dir/library/common/ad_iqcor.v
add_fileset_file up_axi.v VERILOG PATH $ad_hdl_dir/library/common/up_axi.v
add_fileset_file up_xfer_cntrl.v VERILOG PATH $ad_hdl_dir/library/common/up_xfer_cntrl.v
add_fileset_file up_xfer_status.v VERILOG PATH $ad_hdl_dir/library/common/up_xfer_status.v
add_fileset_file up_clock_mon.v VERILOG PATH $ad_hdl_dir/library/common/up_clock_mon.v
add_fileset_file up_adc_common.v VERILOG PATH $ad_hdl_dir/library/common/up_adc_common.v
add_fileset_file up_adc_channel.v VERILOG PATH $ad_hdl_dir/library/common/up_adc_channel.v
add_fileset_file up_dac_common.v VERILOG PATH $ad_hdl_dir/library/common/up_dac_common.v
add_fileset_file up_dac_channel.v VERILOG PATH $ad_hdl_dir/library/common/up_dac_channel.v
add_fileset_file ad_xcvr_rx_if.v VERILOG PATH $ad_hdl_dir/library/common/ad_xcvr_rx_if.v
add_fileset_file axi_ad9371_if.v VERILOG PATH axi_ad9371_if.v
add_fileset_file axi_ad9371_rx_channel.v VERILOG PATH axi_ad9371_rx_channel.v
add_fileset_file axi_ad9371_rx.v VERILOG PATH axi_ad9371_rx.v
add_fileset_file axi_ad9371_rx_os.v VERILOG PATH axi_ad9371_rx_os.v
add_fileset_file axi_ad9371_tx_channel.v VERILOG PATH axi_ad9371_tx_channel.v
add_fileset_file axi_ad9371_tx.v VERILOG PATH axi_ad9371_tx.v
add_fileset_file axi_ad9371.v VERILOG PATH axi_ad9371.v TOP_LEVEL_FILE
add_fileset_file ad_axi_ip_constr.sdc SDC PATH $ad_hdl_dir/library/common/ad_axi_ip_constr.sdc
# parameters
add_parameter ID INTEGER 0
set_parameter_property ID DEFAULT_VALUE 0
set_parameter_property ID DISPLAY_NAME ID
set_parameter_property ID TYPE INTEGER
set_parameter_property ID UNITS None
set_parameter_property ID HDL_PARAMETER true
add_parameter DEVICE_TYPE INTEGER 0
set_parameter_property DEVICE_TYPE DEFAULT_VALUE 1
set_parameter_property DEVICE_TYPE DISPLAY_NAME DEVICE_TYPE
set_parameter_property DEVICE_TYPE TYPE INTEGER
set_parameter_property DEVICE_TYPE UNITS None
set_parameter_property DEVICE_TYPE HDL_PARAMETER true
add_parameter DAC_DATAPATH_DISABLE INTEGER 0
set_parameter_property DAC_DATAPATH_DISABLE DEFAULT_VALUE 0
set_parameter_property DAC_DATAPATH_DISABLE DISPLAY_NAME DAC_DATAPATH_DISABLE
set_parameter_property DAC_DATAPATH_DISABLE TYPE INTEGER
set_parameter_property DAC_DATAPATH_DISABLE UNITS None
set_parameter_property DAC_DATAPATH_DISABLE HDL_PARAMETER true
add_parameter ADC_DATAPATH_DISABLE INTEGER 0
set_parameter_property ADC_DATAPATH_DISABLE DEFAULT_VALUE 0
set_parameter_property ADC_DATAPATH_DISABLE DISPLAY_NAME ADC_DATAPATH_DISABLE
set_parameter_property ADC_DATAPATH_DISABLE TYPE INTEGER
set_parameter_property ADC_DATAPATH_DISABLE UNITS None
set_parameter_property ADC_DATAPATH_DISABLE HDL_PARAMETER true
# axi4 slave
add_interface s_axi_clock clock end
add_interface_port s_axi_clock s_axi_aclk clk Input 1
add_interface s_axi_reset reset end
set_interface_property s_axi_reset associatedClock s_axi_clock
add_interface_port s_axi_reset s_axi_aresetn reset_n Input 1
add_interface s_axi axi4lite end
set_interface_property s_axi associatedClock s_axi_clock
set_interface_property s_axi associatedReset s_axi_reset
add_interface_port s_axi s_axi_awvalid awvalid Input 1
add_interface_port s_axi s_axi_awaddr awaddr Input 16
add_interface_port s_axi s_axi_awprot awprot Input 3
add_interface_port s_axi s_axi_awready awready Output 1
add_interface_port s_axi s_axi_wvalid wvalid Input 1
add_interface_port s_axi s_axi_wdata wdata Input 32
add_interface_port s_axi s_axi_wstrb wstrb Input 4
add_interface_port s_axi s_axi_wready wready Output 1
add_interface_port s_axi s_axi_bvalid bvalid Output 1
add_interface_port s_axi s_axi_bresp bresp Output 2
add_interface_port s_axi s_axi_bready bready Input 1
add_interface_port s_axi s_axi_arvalid arvalid Input 1
add_interface_port s_axi s_axi_araddr araddr Input 16
add_interface_port s_axi s_axi_arprot arprot Input 3
add_interface_port s_axi s_axi_arready arready Output 1
add_interface_port s_axi s_axi_rvalid rvalid Output 1
add_interface_port s_axi s_axi_rresp rresp Output 2
add_interface_port s_axi s_axi_rdata rdata Output 32
add_interface_port s_axi s_axi_rready rready Input 1
# transceiver interface
ad_alt_intf clock adc_clk input 1
ad_alt_intf signal adc_rx_sof input 4 export
add_interface if_adc_rx_data avalon_streaming sink
add_interface_port if_adc_rx_data adc_rx_data data input 64
add_interface_port if_adc_rx_data adc_rx_valid valid input 1
add_interface_port if_adc_rx_data adc_rx_ready ready output 1
set_interface_property if_adc_rx_data associatedClock if_adc_clk
set_interface_property if_adc_rx_data dataBitsPerSymbol 64
ad_alt_intf clock adc_os_clk input 1
ad_alt_intf signal adc_rx_os_sof input 4 export
add_interface if_adc_rx_os_data avalon_streaming sink
add_interface_port if_adc_rx_os_data adc_rx_os_data data input 64
add_interface_port if_adc_rx_os_data adc_rx_os_valid valid input 1
add_interface_port if_adc_rx_os_data adc_rx_os_ready ready output 1
set_interface_property if_adc_rx_os_data associatedClock if_adc_os_clk
set_interface_property if_adc_rx_os_data dataBitsPerSymbol 64
ad_alt_intf clock dac_clk input 1
add_interface if_dac_tx_data avalon_streaming source
add_interface_port if_dac_tx_data dac_tx_data data output 128
add_interface_port if_dac_tx_data dac_tx_valid valid output 1
add_interface_port if_dac_tx_data dac_tx_ready ready input 1
set_interface_property if_dac_tx_data associatedClock if_dac_clk
set_interface_property if_dac_tx_data dataBitsPerSymbol 128
# master/slave
ad_alt_intf signal dac_sync_in input 1
ad_alt_intf signal dac_sync_out output 1
# adc-channel interface
add_interface adc_ch_0 conduit end
add_interface_port adc_ch_0 adc_enable_i0 enable Output 1
add_interface_port adc_ch_0 adc_valid_i0 valid Output 1
add_interface_port adc_ch_0 adc_data_i0 data Output 16
set_interface_property adc_ch_0 associatedClock if_adc_clk
set_interface_property adc_ch_0 associatedReset none
add_interface adc_ch_1 conduit end
add_interface_port adc_ch_1 adc_enable_q0 enable Output 1
add_interface_port adc_ch_1 adc_valid_q0 valid Output 1
add_interface_port adc_ch_1 adc_data_q0 data Output 16
set_interface_property adc_ch_1 associatedClock if_adc_clk
set_interface_property adc_ch_1 associatedReset none
add_interface adc_ch_2 conduit end
add_interface_port adc_ch_2 adc_enable_i1 enable Output 1
add_interface_port adc_ch_2 adc_valid_i1 valid Output 1
add_interface_port adc_ch_2 adc_data_i1 data Output 16
set_interface_property adc_ch_2 associatedClock if_adc_clk
set_interface_property adc_ch_2 associatedReset none
add_interface adc_ch_3 conduit end
add_interface_port adc_ch_3 adc_enable_q1 enable Output 1
add_interface_port adc_ch_3 adc_valid_q1 valid Output 1
add_interface_port adc_ch_3 adc_data_q1 data Output 16
set_interface_property adc_ch_3 associatedClock if_adc_clk
set_interface_property adc_ch_3 associatedReset none
ad_alt_intf signal adc_dovf input 1 ovf
ad_alt_intf signal adc_dunf input 1 unf
# adc-os-channel interface
add_interface adc_os_ch_0 conduit end
add_interface_port adc_os_ch_0 adc_os_enable_i0 enable Output 1
add_interface_port adc_os_ch_0 adc_os_valid_i0 valid Output 1
add_interface_port adc_os_ch_0 adc_os_data_i0 data Output 32
set_interface_property adc_os_ch_0 associatedClock if_adc_os_clk
set_interface_property adc_os_ch_0 associatedReset none
add_interface adc_os_ch_1 conduit end
add_interface_port adc_os_ch_1 adc_os_enable_q0 enable Output 1
add_interface_port adc_os_ch_1 adc_os_valid_q0 valid Output 1
add_interface_port adc_os_ch_1 adc_os_data_q0 data Output 32
set_interface_property adc_os_ch_1 associatedClock if_adc_os_clk
set_interface_property adc_os_ch_1 associatedReset none
ad_alt_intf signal adc_os_dovf input 1 ovf
ad_alt_intf signal adc_os_dunf input 1 unf
# dac-channel interface
add_interface dac_ch_0 conduit end
add_interface_port dac_ch_0 dac_enable_i0 enable Output 1
add_interface_port dac_ch_0 dac_valid_i0 valid Output 1
add_interface_port dac_ch_0 dac_data_i0 data Input 32
set_interface_property dac_ch_0 associatedClock if_dac_clk
set_interface_property dac_ch_0 associatedReset none
add_interface dac_ch_1 conduit end
add_interface_port dac_ch_1 dac_enable_q0 enable Output 1
add_interface_port dac_ch_1 dac_valid_q0 valid Output 1
add_interface_port dac_ch_1 dac_data_q0 data Input 32
set_interface_property dac_ch_1 associatedClock if_dac_clk
set_interface_property dac_ch_1 associatedReset none
add_interface dac_ch_2 conduit end
add_interface_port dac_ch_2 dac_enable_i1 enable Output 1
add_interface_port dac_ch_2 dac_valid_i1 valid Output 1
add_interface_port dac_ch_2 dac_data_i1 data Input 32
set_interface_property dac_ch_2 associatedClock if_dac_clk
set_interface_property dac_ch_2 associatedReset none
add_interface dac_ch_3 conduit end
add_interface_port dac_ch_3 dac_enable_q1 enable Output 1
add_interface_port dac_ch_3 dac_valid_q1 valid Output 1
add_interface_port dac_ch_3 dac_data_q1 data Input 32
set_interface_property dac_ch_3 associatedClock if_dac_clk
set_interface_property dac_ch_3 associatedReset none
ad_alt_intf signal dac_dovf input 1 ovf
ad_alt_intf signal dac_dunf input 1 unf

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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_ad9371_if (
// receive
adc_clk,
adc_rx_sof,
adc_rx_data,
adc_os_clk,
adc_rx_os_sof,
adc_rx_os_data,
adc_data,
adc_os_valid,
adc_os_data,
// transmit
dac_clk,
dac_tx_data,
dac_data);
// parameters
parameter DEVICE_TYPE = 0;
// receive
input adc_clk;
input [ 3:0] adc_rx_sof;
input [ 63:0] adc_rx_data;
input adc_os_clk;
input [ 3:0] adc_rx_os_sof;
input [ 63:0] adc_rx_os_data;
output [ 63:0] adc_data;
output adc_os_valid;
output [ 63:0] adc_os_data;
// transmit
input dac_clk;
output [127:0] dac_tx_data;
input [127:0] dac_data;
// internal signals
wire [ 63:0] adc_rx_data_s;
wire [ 63:0] adc_rx_os_data_s;
// delineating
assign adc_data[((8* 7)+7):(8* 7)] = adc_rx_data_s[((8* 6)+7):(8* 6)];
assign adc_data[((8* 6)+7):(8* 6)] = adc_rx_data_s[((8* 7)+7):(8* 7)];
assign adc_data[((8* 5)+7):(8* 5)] = adc_rx_data_s[((8* 4)+7):(8* 4)];
assign adc_data[((8* 4)+7):(8* 4)] = adc_rx_data_s[((8* 5)+7):(8* 5)];
assign adc_data[((8* 3)+7):(8* 3)] = adc_rx_data_s[((8* 2)+7):(8* 2)];
assign adc_data[((8* 2)+7):(8* 2)] = adc_rx_data_s[((8* 3)+7):(8* 3)];
assign adc_data[((8* 1)+7):(8* 1)] = adc_rx_data_s[((8* 0)+7):(8* 0)];
assign adc_data[((8* 0)+7):(8* 0)] = adc_rx_data_s[((8* 1)+7):(8* 1)];
assign adc_os_valid = 'd1;
assign adc_os_data[((8* 7)+7):(8* 7)] = adc_rx_os_data_s[((8* 6)+7):(8* 6)];
assign adc_os_data[((8* 6)+7):(8* 6)] = adc_rx_os_data_s[((8* 7)+7):(8* 7)];
assign adc_os_data[((8* 5)+7):(8* 5)] = adc_rx_os_data_s[((8* 4)+7):(8* 4)];
assign adc_os_data[((8* 4)+7):(8* 4)] = adc_rx_os_data_s[((8* 5)+7):(8* 5)];
assign adc_os_data[((8* 3)+7):(8* 3)] = adc_rx_os_data_s[((8* 2)+7):(8* 2)];
assign adc_os_data[((8* 2)+7):(8* 2)] = adc_rx_os_data_s[((8* 3)+7):(8* 3)];
assign adc_os_data[((8* 1)+7):(8* 1)] = adc_rx_os_data_s[((8* 0)+7):(8* 0)];
assign adc_os_data[((8* 0)+7):(8* 0)] = adc_rx_os_data_s[((8* 1)+7):(8* 1)];
assign dac_tx_data[((8*15)+7):(8*15)] = (DEVICE_TYPE == 1) ? dac_data[((8*13)+7):(8*13)] : dac_data[((8*14)+7):(8*14)];
assign dac_tx_data[((8*14)+7):(8*14)] = (DEVICE_TYPE == 1) ? dac_data[((8*12)+7):(8*12)] : dac_data[((8*15)+7):(8*15)];
assign dac_tx_data[((8*13)+7):(8*13)] = (DEVICE_TYPE == 1) ? dac_data[((8*15)+7):(8*15)] : dac_data[((8*12)+7):(8*12)];
assign dac_tx_data[((8*12)+7):(8*12)] = (DEVICE_TYPE == 1) ? dac_data[((8*14)+7):(8*14)] : dac_data[((8*13)+7):(8*13)];
assign dac_tx_data[((8*11)+7):(8*11)] = (DEVICE_TYPE == 1) ? dac_data[((8* 9)+7):(8* 9)] : dac_data[((8*10)+7):(8*10)];
assign dac_tx_data[((8*10)+7):(8*10)] = (DEVICE_TYPE == 1) ? dac_data[((8* 8)+7):(8* 8)] : dac_data[((8*11)+7):(8*11)];
assign dac_tx_data[((8* 9)+7):(8* 9)] = (DEVICE_TYPE == 1) ? dac_data[((8*11)+7):(8*11)] : dac_data[((8* 8)+7):(8* 8)];
assign dac_tx_data[((8* 8)+7):(8* 8)] = (DEVICE_TYPE == 1) ? dac_data[((8*10)+7):(8*10)] : dac_data[((8* 9)+7):(8* 9)];
assign dac_tx_data[((8* 7)+7):(8* 7)] = (DEVICE_TYPE == 1) ? dac_data[((8* 5)+7):(8* 5)] : dac_data[((8* 6)+7):(8* 6)];
assign dac_tx_data[((8* 6)+7):(8* 6)] = (DEVICE_TYPE == 1) ? dac_data[((8* 4)+7):(8* 4)] : dac_data[((8* 7)+7):(8* 7)];
assign dac_tx_data[((8* 5)+7):(8* 5)] = (DEVICE_TYPE == 1) ? dac_data[((8* 7)+7):(8* 7)] : dac_data[((8* 4)+7):(8* 4)];
assign dac_tx_data[((8* 4)+7):(8* 4)] = (DEVICE_TYPE == 1) ? dac_data[((8* 6)+7):(8* 6)] : dac_data[((8* 5)+7):(8* 5)];
assign dac_tx_data[((8* 3)+7):(8* 3)] = (DEVICE_TYPE == 1) ? dac_data[((8* 1)+7):(8* 1)] : dac_data[((8* 2)+7):(8* 2)];
assign dac_tx_data[((8* 2)+7):(8* 2)] = (DEVICE_TYPE == 1) ? dac_data[((8* 0)+7):(8* 0)] : dac_data[((8* 3)+7):(8* 3)];
assign dac_tx_data[((8* 1)+7):(8* 1)] = (DEVICE_TYPE == 1) ? dac_data[((8* 3)+7):(8* 3)] : dac_data[((8* 0)+7):(8* 0)];
assign dac_tx_data[((8* 0)+7):(8* 0)] = (DEVICE_TYPE == 1) ? dac_data[((8* 2)+7):(8* 2)] : dac_data[((8* 1)+7):(8* 1)];
// instantiations
genvar n;
generate
for (n = 0; n < 2; n = n + 1) begin: g_xcvr_if
ad_xcvr_rx_if #(.DEVICE_TYPE (DEVICE_TYPE)) i_xcvr_rx_if (
.rx_clk (adc_clk),
.rx_ip_sof (adc_rx_sof),
.rx_ip_data (adc_rx_data[((n*32)+31):(n*32)]),
.rx_sof (),
.rx_data (adc_rx_data_s[((n*32)+31):(n*32)]));
ad_xcvr_rx_if #(.DEVICE_TYPE (DEVICE_TYPE)) i_xcvr_rx_os_if (
.rx_clk (adc_os_clk),
.rx_ip_sof (adc_rx_os_sof),
.rx_ip_data (adc_rx_os_data[((n*32)+31):(n*32)]),
.rx_sof (),
.rx_data (adc_rx_os_data_s[((n*32)+31):(n*32)]));
end
endgenerate
endmodule
// ***************************************************************************
// ***************************************************************************

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