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avl_dacfifo: Fix a few control signals 

+ avl_last_transfer depends on the avl_xfer_req state
  + avl_xfer_req will be asserted after the last avalon write
transfer
main
Istvan Csomortani 2017-05-15 12:24:27 +03:00
parent 8f9cadb017
commit 04f397f688
1 changed files with 2 additions and 3 deletions
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5
library/altera/avl_dacfifo/avl_dacfifo_wr.v
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@ -292,7 +292,7 @@ module avl_dacfifo_wr #(
// avalon write signaling // avalon write signaling
assign avl_last_transfer_req_s = avl_last_beat_req & ~avl_mem_readen; assign avl_last_transfer_req_s = avl_last_beat_req & ~avl_mem_readen & ~avl_xfer_req;
assign avl_pending_write_cycle_s = ~avl_write & ~avl_write_d[0] & ~avl_write_d[1]; assign avl_pending_write_cycle_s = ~avl_write & ~avl_write_d[0] & ~avl_write_d[1];
// min distance between two consecutive writes is three avalon clock cycles, // min distance between two consecutive writes is three avalon clock cycles,
@ -494,8 +494,7 @@ module avl_dacfifo_wr #(
if (avl_reset == 1'b1) begin if (avl_reset == 1'b1) begin
avl_xfer_req <= 1'b0; avl_xfer_req <= 1'b0;
end else begin end else begin
if ((avl_last_transfer_req_s == 1'b1) && if ((avl_write_xfer_req == 0) && (avl_write_xfer_req_d == 1)) begin
(avl_write_transfer == 1'b1)) begin
avl_xfer_req <= 1'b1; avl_xfer_req <= 1'b1;
end else if ((avl_xfer_req == 1'b1) && (avl_dma_xfer_req == 1'b1)) begin end else if ((avl_xfer_req == 1'b1) && (avl_dma_xfer_req == 1'b1)) begin
avl_xfer_req <= 1'b0; avl_xfer_req <= 1'b0;