util_cpack2: support for 64 channels
Laszlo Nagy
Laszlo Nagy
parent
b49928fca6
commit
04fed45e54
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@ -75,6 +75,38 @@ module util_cpack2 #(
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input enable_29,
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input enable_30,
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input enable_31,
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input enable_32,
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input enable_33,
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input enable_34,
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input enable_35,
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input enable_36,
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input enable_37,
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input enable_38,
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input enable_39,
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input enable_40,
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input enable_41,
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input enable_42,
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input enable_43,
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input enable_44,
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input enable_45,
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input enable_46,
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input enable_47,
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input enable_48,
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input enable_49,
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input enable_50,
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input enable_51,
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input enable_52,
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input enable_53,
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input enable_54,
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input enable_55,
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input enable_56,
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input enable_57,
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input enable_58,
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input enable_59,
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input enable_60,
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input enable_61,
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input enable_62,
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input enable_63,
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input fifo_wr_en,
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output fifo_wr_overflow,
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@ -111,7 +143,38 @@ module util_cpack2 #(
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input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_29,
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input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_30,
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input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_31,
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input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_32,
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input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_33,
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input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_34,
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input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_35,
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input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_36,
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input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_37,
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input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_38,
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input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_39,
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input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_40,
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input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_41,
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input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_42,
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input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_43,
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input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_44,
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input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_45,
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input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_46,
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input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_47,
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input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_48,
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input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_49,
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input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_50,
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input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_51,
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input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_52,
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input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_53,
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input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_54,
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input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_55,
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input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_56,
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input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_57,
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input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_58,
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input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_59,
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input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_60,
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input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_61,
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input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_62,
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input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_63,
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output packed_fifo_wr_en,
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input packed_fifo_wr_overflow,
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@ -124,7 +187,8 @@ localparam CHANNEL_DATA_WIDTH = SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL;
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* Round up to the next power of two and zero out the additional channels
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* internally.
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*/
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localparam REAL_NUM_OF_CHANNELS = NUM_OF_CHANNELS > 16 ? 32 :
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localparam REAL_NUM_OF_CHANNELS = NUM_OF_CHANNELS > 32 ? 64 :
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NUM_OF_CHANNELS > 16 ? 32 :
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NUM_OF_CHANNELS > 8 ? 16 :
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NUM_OF_CHANNELS > 4 ? 8 :
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NUM_OF_CHANNELS > 2 ? 4 :
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@ -133,11 +197,15 @@ localparam REAL_NUM_OF_CHANNELS = NUM_OF_CHANNELS > 16 ? 32 :
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/* FIXME: Find out how to do this in the IP-XACT */
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wire [REAL_NUM_OF_CHANNELS-1:0] enable;
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wire [31:0] enable_s;
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wire [63:0] enable_s;
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wire [CHANNEL_DATA_WIDTH*REAL_NUM_OF_CHANNELS-1:0] fifo_wr_data;
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wire [CHANNEL_DATA_WIDTH*32-1:0] fifo_wr_data_s;
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wire [CHANNEL_DATA_WIDTH*64-1:0] fifo_wr_data_s;
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assign enable_s = {
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enable_63,enable_62,enable_61,enable_60,enable_59,enable_58,enable_57,enable_56,
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enable_55,enable_54,enable_53,enable_52,enable_51,enable_50,enable_49,enable_48,
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enable_47,enable_46,enable_45,enable_44,enable_43,enable_42,enable_41,enable_40,
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enable_39,enable_38,enable_37,enable_36,enable_35,enable_34,enable_33,enable_32,
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enable_31,enable_30,enable_29,enable_28,enable_27,enable_26,enable_25,enable_24,
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enable_23,enable_22,enable_21,enable_20,enable_19,enable_18,enable_17,enable_16,
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enable_15,enable_14,enable_13,enable_12,enable_11,enable_10,enable_9,enable_8,
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@ -177,6 +245,38 @@ assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*28+:CHANNEL_DATA_WIDTH] = fifo_wr_data_
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assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*29+:CHANNEL_DATA_WIDTH] = fifo_wr_data_29;
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assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*30+:CHANNEL_DATA_WIDTH] = fifo_wr_data_30;
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assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*31+:CHANNEL_DATA_WIDTH] = fifo_wr_data_31;
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assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*32+:CHANNEL_DATA_WIDTH] = fifo_wr_data_32;
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assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*33+:CHANNEL_DATA_WIDTH] = fifo_wr_data_33;
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assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*34+:CHANNEL_DATA_WIDTH] = fifo_wr_data_34;
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assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*35+:CHANNEL_DATA_WIDTH] = fifo_wr_data_35;
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assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*36+:CHANNEL_DATA_WIDTH] = fifo_wr_data_36;
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assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*37+:CHANNEL_DATA_WIDTH] = fifo_wr_data_37;
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assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*38+:CHANNEL_DATA_WIDTH] = fifo_wr_data_38;
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assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*39+:CHANNEL_DATA_WIDTH] = fifo_wr_data_39;
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assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*40+:CHANNEL_DATA_WIDTH] = fifo_wr_data_40;
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assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*41+:CHANNEL_DATA_WIDTH] = fifo_wr_data_41;
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assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*42+:CHANNEL_DATA_WIDTH] = fifo_wr_data_42;
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assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*43+:CHANNEL_DATA_WIDTH] = fifo_wr_data_43;
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assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*44+:CHANNEL_DATA_WIDTH] = fifo_wr_data_44;
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assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*45+:CHANNEL_DATA_WIDTH] = fifo_wr_data_45;
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assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*46+:CHANNEL_DATA_WIDTH] = fifo_wr_data_46;
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assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*47+:CHANNEL_DATA_WIDTH] = fifo_wr_data_47;
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assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*48+:CHANNEL_DATA_WIDTH] = fifo_wr_data_48;
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assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*49+:CHANNEL_DATA_WIDTH] = fifo_wr_data_49;
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assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*50+:CHANNEL_DATA_WIDTH] = fifo_wr_data_50;
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assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*51+:CHANNEL_DATA_WIDTH] = fifo_wr_data_51;
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assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*52+:CHANNEL_DATA_WIDTH] = fifo_wr_data_52;
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assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*53+:CHANNEL_DATA_WIDTH] = fifo_wr_data_53;
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assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*54+:CHANNEL_DATA_WIDTH] = fifo_wr_data_54;
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assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*55+:CHANNEL_DATA_WIDTH] = fifo_wr_data_55;
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assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*56+:CHANNEL_DATA_WIDTH] = fifo_wr_data_56;
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assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*57+:CHANNEL_DATA_WIDTH] = fifo_wr_data_57;
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assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*58+:CHANNEL_DATA_WIDTH] = fifo_wr_data_58;
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assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*59+:CHANNEL_DATA_WIDTH] = fifo_wr_data_59;
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assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*60+:CHANNEL_DATA_WIDTH] = fifo_wr_data_60;
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assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*61+:CHANNEL_DATA_WIDTH] = fifo_wr_data_61;
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assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*62+:CHANNEL_DATA_WIDTH] = fifo_wr_data_62;
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assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*63+:CHANNEL_DATA_WIDTH] = fifo_wr_data_63;
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assign fifo_wr_data = fifo_wr_data_s[0+:REAL_NUM_OF_CHANNELS*CHANNEL_DATA_WIDTH];
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util_cpack2_impl #(
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@ -49,7 +49,7 @@ adi_add_bus_clock "clk" "packed_fifo_wr" "reset"
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set cc [ipx::current_core]
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for {set i 1} {$i < 32} {incr i} {
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for {set i 1} {$i < 64} {incr i} {
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set_property enablement_dependency "spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > $i" \
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[ipx::get_ports *_$i -of_objects $cc]
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}
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