diff --git a/projects/scripts/adi_project_intel.tcl b/projects/scripts/adi_project_intel.tcl
index 1034fc016..caf837534 100644
--- a/projects/scripts/adi_project_intel.tcl
+++ b/projects/scripts/adi_project_intel.tcl
@@ -115,22 +115,6 @@ proc adi_project {project_name {parameter_list {}}} {
     system_bd.qsys --synthesis=VERILOG --output-directory=system_bd \
     --family=$family --part=$device
 
-  # ignored warnings and such
-
-  set_global_assignment -name MESSAGE_DISABLE 17951 ; ## unused RX channels
-  set_global_assignment -name MESSAGE_DISABLE 18655 ; ## unused TX channels
-  set_global_assignment -name MESSAGE_DISABLE 114001 ; ## Time value $x truncated to $y
-
-  # The Merlin cores are especially spammy, lets hope non of these warnings is
-  # an actual issue...
-  foreach entity {altera_merlin_axi_master_ni altera_merlin_axi_slave_ni \
-                  altera_merlin_traffic_limiter altera_merlin_burst_adapter_new} {
-    ## truncated value
-    set_instance_assignment -name MESSAGE_DISABLE 10230 -entity $entity
-  }
-  ## assigned a value but never read
-  set_instance_assignment -name MESSAGE_DISABLE 10036 -entity altera_merlin_burst_adapter_new
-
   # default assignments
 
   set_global_assignment -name QIP_FILE $system_qip_file