docs: review fixes

Signed-off-by: Jorge Marques <jorge.marques@analog.com>

docs/conf.py

@@ -31,7 +31,7 @@ exclude_patterns = ['_build', 'Thumbs.db', '.DS_Store']
 
 # -- Custom extensions configuration -------------------------------------------
 
-hide_collapsible_content = False
+hide_collapsible_content = True
 
 # -- todo configuration -------------------------------------------------------
 

docs/library/spi_engine/axi_spi_engine.rst

@@ -93,7 +93,7 @@ In order to reduce the necessary context switches the AXI SPI Engine peripheral
 incorporates FIFOs to buffer the command as well as the data streams.
 
 FIFOs
---------------------------------------------------------------------------------
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
 The AXI SPI Engine peripheral has three FIFOs, one for each of the command, SDO
 and SDI streams.
@@ -124,7 +124,7 @@ If the peripheral is disabled by setting the ENABLE register to 0 any data
 stored in the FIFOs is discarded and the state of the FIFO is reset.
 
 Synchronization Events
---------------------------------------------------------------------------------
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
 Synchronization events can be used to notify the software application about the
 progress of the command stream.
@@ -175,7 +175,7 @@ IRQ_PENDING register.
    IRQ = |IRQ_PENDING;
 
 FIFO Threshold Interrupts
---------------------------------------------------------------------------------
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
 The FIFO threshold interrupts can be used by software for flow control of the
 command, SDI and SDO streams.
@@ -191,7 +191,7 @@ watermark and is automatically de-asserted when the level drops below the
 watermark.
 
 SYNC_EVENT Interrupt
---------------------------------------------------------------------------------
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
 The SYNC_EVENT interrupt is asserted when a new sync event is received from the
 sync stream.

docs/library/spi_engine/spi-bus-interface.rst

@@ -71,3 +71,20 @@ In some configurations three-wire support may not be required and ``sdi`` can
 directly be connected to the input buffer for the ``miso`` signal. Similarly
 when ``mosi`` tri-stating is not required the ``sdo`` signal can be directly
 connected to the ``mosi`` signal leaving the ``sdo_t`` signal unconnected.
+
+Example Verilog IO configuration
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+ The following example Verilog code shows the most generic IO configuration,
+ which represents the diagram above. Depending on system requirements some
+ simplification might be possible.
+
+Signals with phy prefix are assumed to be connected to the physical input/output
+pins and signals with the spi prefix are assumed to be connected SPI-Engine bus
+interface.
+
+.. code-block:: verilog
+
+   assign phy_sclk = spi_sclk;
+   assign phy_cs = spi_cs;
+   assign phy_mosi = spi_sdo_t ? 1'bz : spi_sdo;
+   assign spi_sdi = spi_three_wire ? phy_mosi : phy_miso;

docs/library/spi_engine/spi_engine_offload.rst

@@ -1,6 +1,6 @@
 .. _spi_engine offload:
 
-SPI Engine Offload
+SPI Engine Offload Module
 ================================================================================
 
 .. symbolator:: ../../../library/spi_engine/spi_engine_offload/spi_engine_offload.v