diff --git a/library/axi_ad9250/axi_ad9250.v b/library/axi_ad9250/axi_ad9250.v
index a88f95ad6..679c22af1 100644
--- a/library/axi_ad9250/axi_ad9250.v
+++ b/library/axi_ad9250/axi_ad9250.v
@@ -50,6 +50,7 @@ module axi_ad9250 (
   // dma interface
 
   adc_clk,
+  adc_rst,
   adc_valid_a,
   adc_enable_a,
   adc_data_a,
@@ -96,6 +97,7 @@ module axi_ad9250 (
   // dma interface
 
   output          adc_clk;
+  output          adc_rst;
   output          adc_valid_a;
   output          adc_enable_a;
   output  [31:0]  adc_data_a;
diff --git a/library/axi_ad9250/axi_ad9250_constr.xdc b/library/axi_ad9250/axi_ad9250_constr.xdc
index 04729f7fc..8b1378917 100644
--- a/library/axi_ad9250/axi_ad9250_constr.xdc
+++ b/library/axi_ad9250/axi_ad9250_constr.xdc
@@ -1,44 +1 @@
-set up_clk [get_clocks -of_objects [get_ports s_axi_aclk]]
-set ad9250_clk [get_clocks -of_objects [get_ports rx_clk]]
 
-set_property ASYNC_REG TRUE \
-  [get_cells -hier *toggle_m1_reg*] \
-  [get_cells -hier *toggle_m2_reg*] \
-  [get_cells -hier *state_m1_reg*] \
-  [get_cells -hier *state_m2_reg*]
-
-set_false_path \
-  -from [get_cells -hier up_xfer_toggle_reg* -filter {primitive_subgroup == flop}] \
-  -to [get_cells -hier d_xfer_toggle_m1_reg* -filter {primitive_subgroup == flop}]
-set_false_path \
-  -from [get_cells -hier d_xfer_toggle_reg* -filter {primitive_subgroup == flop}] \
-  -to [get_cells -hier up_xfer_state_m1_reg* -filter {primitive_subgroup == flop}]
-set_max_delay -datapath_only \
-  -from [get_cells -hier up_xfer_data_reg* -filter {primitive_subgroup == flop}] \
-  -to [get_cells -hier d_data_cntrl_reg* -filter {primitive_subgroup == flop}] \
-  [get_property PERIOD $ad9250_clk]
-
-set_false_path \
-  -from [get_cells -hier d_xfer_toggle_reg* -filter {primitive_subgroup == flop}] \
-  -to [get_cells -hier up_xfer_toggle_m1_reg* -filter {primitive_subgroup == flop}]
-set_false_path \
-  -from [get_cells -hier up_xfer_toggle_reg* -filter {primitive_subgroup == flop}] \
-  -to [get_cells -hier d_xfer_state_m1_reg* -filter {primitive_subgroup == flop}]
-set_max_delay -datapath_only \
-  -from [get_cells -hier d_xfer_data_reg* -filter {primitive_subgroup == flop}] \
-  -to [get_cells -hier up_data_status_reg* -filter {primitive_subgroup == flop}] \
-  [get_property PERIOD $up_clk]
-
-set_false_path \
-  -from [get_cells -hier up_count_toggle_reg* -filter {primitive_subgroup == flop}] \
-  -to [get_cells -hier d_count_toggle_m1_reg* -filter {primitive_subgroup == flop}]
-set_false_path \
-  -from [get_cells -hier d_count_toggle_reg* -filter {primitive_subgroup == flop}] \
-  -to [get_cells -hier up_count_toggle_m1_reg* -filter {primitive_subgroup == flop}]
-set_max_delay -datapath_only \
-  -from [get_cells -hier d_count_hold_reg* -filter {primitive_subgroup == flop}] \
-  -to [get_cells -hier up_d_count_reg* -filter {primitive_subgroup == flop}] \
-  [get_property PERIOD $up_clk]
-
-set_false_path \
-  -to [get_pins -hier */PRE -filter {NAME =~ *i_*rst_reg*}]
diff --git a/library/axi_ad9250/axi_ad9250_ip.tcl b/library/axi_ad9250/axi_ad9250_ip.tcl
index b6b95dba0..390d75954 100644
--- a/library/axi_ad9250/axi_ad9250_ip.tcl
+++ b/library/axi_ad9250/axi_ad9250_ip.tcl
@@ -14,6 +14,7 @@ adi_ip_files axi_ad9250 [list \
   "$ad_hdl_dir/library/common/up_clock_mon.v" \
   "$ad_hdl_dir/library/common/up_adc_common.v" \
   "$ad_hdl_dir/library/common/up_adc_channel.v" \
+  "$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc" \
   "axi_ad9250_pnmon.v" \
   "axi_ad9250_channel.v" \
   "axi_ad9250_if.v" \
@@ -23,6 +24,7 @@ adi_ip_files axi_ad9250 [list \
 adi_ip_properties axi_ad9250
 
 adi_ip_constraints axi_ad9250 [list \
+  "$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc" \
   "axi_ad9250_constr.xdc" ]
 
 set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]]