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axi_ad9250: Update library 

- added adc reset port
- addded common constraints
main
Adrian Costina 2015-09-24 19:10:19 +03:00
parent 58ab70bc0e
commit 061f468fb1
3 changed files with 4 additions and 43 deletions
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2
library/axi_ad9250/axi_ad9250.v
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@ -50,6 +50,7 @@ module axi_ad9250 (
// dma interface // dma interface
adc_clk, adc_clk,
adc_rst,
adc_valid_a, adc_valid_a,
adc_enable_a, adc_enable_a,
adc_data_a, adc_data_a,
@ -96,6 +97,7 @@ module axi_ad9250 (
// dma interface // dma interface
output adc_clk; output adc_clk;
output adc_rst;
output adc_valid_a; output adc_valid_a;
output adc_enable_a; output adc_enable_a;
output [31:0] adc_data_a; output [31:0] adc_data_a;

43
library/axi_ad9250/axi_ad9250_constr.xdc
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@ -1,44 +1 @@
set up_clk [get_clocks -of_objects [get_ports s_axi_aclk]]
set ad9250_clk [get_clocks -of_objects [get_ports rx_clk]]
set_property ASYNC_REG TRUE \
[get_cells -hier *toggle_m1_reg*] \
[get_cells -hier *toggle_m2_reg*] \
[get_cells -hier *state_m1_reg*] \
[get_cells -hier *state_m2_reg*]
set_false_path \
-from [get_cells -hier up_xfer_toggle_reg* -filter {primitive_subgroup == flop}] \
-to [get_cells -hier d_xfer_toggle_m1_reg* -filter {primitive_subgroup == flop}]
set_false_path \
-from [get_cells -hier d_xfer_toggle_reg* -filter {primitive_subgroup == flop}] \
-to [get_cells -hier up_xfer_state_m1_reg* -filter {primitive_subgroup == flop}]
set_max_delay -datapath_only \
-from [get_cells -hier up_xfer_data_reg* -filter {primitive_subgroup == flop}] \
-to [get_cells -hier d_data_cntrl_reg* -filter {primitive_subgroup == flop}] \
[get_property PERIOD $ad9250_clk]
set_false_path \
-from [get_cells -hier d_xfer_toggle_reg* -filter {primitive_subgroup == flop}] \
-to [get_cells -hier up_xfer_toggle_m1_reg* -filter {primitive_subgroup == flop}]
set_false_path \
-from [get_cells -hier up_xfer_toggle_reg* -filter {primitive_subgroup == flop}] \
-to [get_cells -hier d_xfer_state_m1_reg* -filter {primitive_subgroup == flop}]
set_max_delay -datapath_only \
-from [get_cells -hier d_xfer_data_reg* -filter {primitive_subgroup == flop}] \
-to [get_cells -hier up_data_status_reg* -filter {primitive_subgroup == flop}] \
[get_property PERIOD $up_clk]
set_false_path \
-from [get_cells -hier up_count_toggle_reg* -filter {primitive_subgroup == flop}] \
-to [get_cells -hier d_count_toggle_m1_reg* -filter {primitive_subgroup == flop}]
set_false_path \
-from [get_cells -hier d_count_toggle_reg* -filter {primitive_subgroup == flop}] \
-to [get_cells -hier up_count_toggle_m1_reg* -filter {primitive_subgroup == flop}]
set_max_delay -datapath_only \
-from [get_cells -hier d_count_hold_reg* -filter {primitive_subgroup == flop}] \
-to [get_cells -hier up_d_count_reg* -filter {primitive_subgroup == flop}] \
[get_property PERIOD $up_clk]
set_false_path \
-to [get_pins -hier */PRE -filter {NAME =~ *i_*rst_reg*}]

2
library/axi_ad9250/axi_ad9250_ip.tcl
View File

@ -14,6 +14,7 @@ adi_ip_files axi_ad9250 [list \
"$ad_hdl_dir/library/common/up_clock_mon.v" \ "$ad_hdl_dir/library/common/up_clock_mon.v" \
"$ad_hdl_dir/library/common/up_adc_common.v" \ "$ad_hdl_dir/library/common/up_adc_common.v" \
"$ad_hdl_dir/library/common/up_adc_channel.v" \ "$ad_hdl_dir/library/common/up_adc_channel.v" \
"$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc" \
"axi_ad9250_pnmon.v" \ "axi_ad9250_pnmon.v" \
"axi_ad9250_channel.v" \ "axi_ad9250_channel.v" \
"axi_ad9250_if.v" \ "axi_ad9250_if.v" \
@ -23,6 +24,7 @@ adi_ip_files axi_ad9250 [list \
adi_ip_properties axi_ad9250 adi_ip_properties axi_ad9250
adi_ip_constraints axi_ad9250 [list \ adi_ip_constraints axi_ad9250 [list \
"$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc" \
"axi_ad9250_constr.xdc" ] "axi_ad9250_constr.xdc" ]
set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]] set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]]