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axi_dmac: Reset fifo_rd_data when DMA is off - v2 

The first attempt (f3daf0) faild miserably. When the data_req signal
from the device had more than 1 cycle of deassert state, because of the
added latency of the data stream, the device got 'zeros' too.
In this fix, the DMA will hold the valid data on the bus, between two
consecutive data request. The bus is reseted just after all the data
were sent out.
main
Istvan Csomortani 2017-10-10 08:10:24 +01:00
parent d9acdb8092
commit 06bab87733
1 changed files with 10 additions and 23 deletions
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33
library/axi_dmac/dest_fifo_inf.v
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@ -55,10 +55,10 @@ module dmac_dest_fifo_inf #(
input en,
output reg [DATA_WIDTH-1:0] dout,
output reg valid,
output reg underflow,
output valid,
output underflow,
output reg xfer_req,
output xfer_req,
output fifo_ready,
input fifo_valid,
@ -81,9 +81,6 @@ wire _fifo_ready;
assign fifo_ready = _fifo_ready | ~enabled;
wire [DATA_WIDTH-1:0] dout_s;
wire valid_s;
wire underflow_s;
wire xfer_req_s;
reg en_d1;
wire data_ready;
wire data_valid;
@ -97,9 +94,9 @@ begin
end
end
assign underflow_s = en_d1 & (~data_valid | ~enable);
assign underflow = en_d1 & (~data_valid | ~enable);
assign data_ready = en_d1 & (data_valid | ~enable);
assign valid_s = en_d1 & data_valid & enable;
assign valid = en_d1 & data_valid & enable;
dmac_data_mover # (
.ID_WIDTH(ID_WIDTH),
@ -113,7 +110,7 @@ dmac_data_mover # (
.enable(enable),
.enabled(data_enabled),
.sync_id(sync_id),
.xfer_req(xfer_req_s),
.xfer_req(xfer_req),
.request_id(request_id),
.response_id(data_id),
@ -133,22 +130,12 @@ dmac_data_mover # (
);
always @(posedge clk) begin
if (resetn == 1'b0) begin
valid <= 1'b0;
underflow <= 1'b0;
xfer_req <= 1'b0;
end else begin
valid <= valid_s;
underflow <= underflow_s;
xfer_req <= xfer_req_s;
end
end
always @(posedge clk) begin
if ((resetn == 1'b0) || (valid_s == 1'b0)) begin
if ((resetn == 1'b0) || (data_enabled == 1'b0)) begin
dout <= {DATA_WIDTH{1'b0}};
end else begin
dout <= dout_s;
if (data_valid) begin
dout <= dout_s;
end
end
end