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ccpci- added

main
Rejeesh Kutty 2015-09-21 09:31:18 -04:00
parent 3a72d26f5b
commit 0702f2c231
3 changed files with 16 additions and 4 deletions
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2
projects/pzsdr/ccpci/system_bd.tcl
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@ -1,4 +1,4 @@
source $ad_hdl_dir/projects/common/pzsdr/pzsdr_system_bd.tcl
source ../common/ccbrk_bd.tcl
source ../common/ccpci_bd.tcl

6
projects/pzsdr/ccpci/system_project.tcl
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@ -5,8 +5,8 @@ source ../../scripts/adi_env.tcl -notrace
source $ad_hdl_dir/projects/scripts/adi_project.tcl -notrace
source $ad_hdl_dir/projects/scripts/adi_board.tcl -notrace
adi_project_create ccbrk_pzsdr
adi_project_files ccbrk_pzsdr [list \
adi_project_create ccpci_pzsdr
adi_project_files ccpci_pzsdr [list \
"system_top.v" \
"system_constr.xdc"\
"$ad_hdl_dir/library/common/ad_iobuf.v" \
@ -15,6 +15,6 @@ adi_project_files ccbrk_pzsdr [list \
set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/pzsdr/pzsdr_system_constr.xdc]
set_property PROCESSING_ORDER EARLY [get_files system_constr.xdc]
adi_project_run ccbrk_pzsdr
adi_project_run ccpci_pzsdr

12
projects/pzsdr/common/ccpci_bd.tcl Normal file
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@ -0,0 +1,12 @@
# pci-express
set axi_pcie_x4 [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_pcie:2.6 axi_pcie_x4]
set_property -dict [list CONFIG.NO_OF_LANES {X4}] $axi_pcie_x4
set_property -dict [list CONFIG.MAX_LINK_SPEED {5.0_GT/s}] $axi_pcie_x4
set_property -dict [list CONFIG.DEVICE_ID {0x7022}] $axi_pcie_x4
ad_cpu_interconnect 0x44A60000 axi_pcie_x4
ad_mem_hp0_interconnect sys_cpu_clk sys_ps7/S_AXI_HP0
ad_mem_hp0_interconnect sys_cpu_clk axi_pcie_x4/M_AXI