From 07184b31d291b3388c36f7a9d7a275cf94c83a20 Mon Sep 17 00:00:00 2001 From: Istvan Csomortani Date: Thu, 16 Feb 2017 12:35:24 +0200 Subject: [PATCH] fmcadc2: Define default clock selection for Xilinx GTs --- projects/fmcadc2/vc707/system_bd.tcl | 3 +++ projects/fmcadc2/zc706/system_bd.tcl | 4 ++++ 2 files changed, 7 insertions(+) diff --git a/projects/fmcadc2/vc707/system_bd.tcl b/projects/fmcadc2/vc707/system_bd.tcl index b9644f373..e01b765fd 100644 --- a/projects/fmcadc2/vc707/system_bd.tcl +++ b/projects/fmcadc2/vc707/system_bd.tcl @@ -6,4 +6,7 @@ p_sys_adcfifo [current_bd_instance .] axi_ad9625_fifo 256 18 source ../common/fmcadc2_bd.tcl +set_property -dict [list CONFIG.LPM_OR_DFE_N {1}] [get_bd_cells axi_ad9625_xcvr] +set_property -dict [list CONFIG.SYS_CLK_SEL {0}] [get_bd_cells axi_ad9625_xcvr] +set_property -dict [list CONFIG.OUT_CLK_SEL {2}] [get_bd_cells axi_ad9625_xcvr] diff --git a/projects/fmcadc2/zc706/system_bd.tcl b/projects/fmcadc2/zc706/system_bd.tcl index f7567d53a..b122c4b2e 100644 --- a/projects/fmcadc2/zc706/system_bd.tcl +++ b/projects/fmcadc2/zc706/system_bd.tcl @@ -21,3 +21,7 @@ create_bd_addr_seg -range 0x40000000 -offset 0x80000000 \ source ../common/fmcadc2_bd.tcl +set_property -dict [list CONFIG.LPM_OR_DFE_N {1}] [get_bd_cells axi_ad9625_xcvr] +set_property -dict [list CONFIG.SYS_CLK_SEL {0}] [get_bd_cells axi_ad9625_xcvr] +set_property -dict [list CONFIG.OUT_CLK_SEL {2}] [get_bd_cells axi_ad9625_xcvr] +