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fmcadc2: Define default clock selection for Xilinx GTs

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Istvan Csomortani 2017-02-16 12:35:24 +02:00
parent 358aa48c76
commit 07184b31d2
2 changed files with 7 additions and 0 deletions
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3
projects/fmcadc2/vc707/system_bd.tcl
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@ -6,4 +6,7 @@ p_sys_adcfifo [current_bd_instance .] axi_ad9625_fifo 256 18
source ../common/fmcadc2_bd.tcl
set_property -dict [list CONFIG.LPM_OR_DFE_N {1}] [get_bd_cells axi_ad9625_xcvr]
set_property -dict [list CONFIG.SYS_CLK_SEL {0}] [get_bd_cells axi_ad9625_xcvr]
set_property -dict [list CONFIG.OUT_CLK_SEL {2}] [get_bd_cells axi_ad9625_xcvr]

4
projects/fmcadc2/zc706/system_bd.tcl
View File

@ -21,3 +21,7 @@ create_bd_addr_seg -range 0x40000000 -offset 0x80000000 \
source ../common/fmcadc2_bd.tcl
set_property -dict [list CONFIG.LPM_OR_DFE_N {1}] [get_bd_cells axi_ad9625_xcvr]
set_property -dict [list CONFIG.SYS_CLK_SEL {0}] [get_bd_cells axi_ad9625_xcvr]
set_property -dict [list CONFIG.OUT_CLK_SEL {2}] [get_bd_cells axi_ad9625_xcvr]