docs: Add JESD204 documentation (#1280)

docs: Add JESD204 documentation in sphinx

Fixes several semantic issues from the original doc in wiki
Implicit path to library when the doc is hierarchically coherent with the
library.

Signed-off-by: Carlos Souza <carlos.souza@analog.com>
Co-authored-by: Jorge Marques <jorge.marques@analog.com>
main
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.. _axi_adxcvr:
AXI_ADXCVR
================================================================================
.. hdl-component-diagram::
:path: library/xilinx/axi_adxcvr
The AXI_ADXCVR is a utility core used to control and configure the highspeed
transceivers.
There are separate AXI_ADXCVR cores for Intel and AMD Xilinx designs, due to the
small differences between the AMD Xilinx's and Intel's transceivers architecture.
For the AMD Xilinx architecture, the transceivers are instantiated in
:ref:`UTIL_ADXCVR <util_adxcvr>`.
Features
--------------------------------------------------------------------------------
- Supports :git-hdl:`Intel <library/intel/axi_adxcvr>`
and :git-hdl:`AMD Xilinx <library/xilinx/axi_adxcvr>` devices.
- Software can access the core's registers through an AXI4 Lite Memory Mapped
interface.
- Link reset and monitor for Intel and AMD Xilinx.
- Reconfiguration interface control with broadcast capability for AMD Xilinx.
- Access to the Statistical eye scan interface of the PHY (AMD Xilinx).
- Supports up to 16 transceiver lanes per link (AMD Xilinx).
Intel Devices
--------------------------------------------------------------------------------
For Intel devices, the adi_jesd204 IP is using the axi_adxcvr core, which can be
accessed by the **link_management** interface. It provides a global reset signal
for the JESD204B framework. Resets the XCVR reset controller IP, the link PLL
reset controller, the PHY itself, and also the link layer of the stack. Besides
the reset generation, monitors the PLLs and the PHY state.
Parameters
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
.. hdl-parameters::
:path: library/xilinx/axi_adxcvr
* - ID
- Instance identification number, if more than one instance is used.
* - NUM_OF_LANES
- The number of lanes (primitives) used in this link.
* - XCVR_TYPE
- Refers to the transceiver speed grade 0-9.
* - FPGA_TECHNOLOGY
- Encoded value describing the technology/generation of the FPGA device
(e.g. Cyclone V, Arria 10, Stratix 10).
* - FPGA_FAMILY
- Encoded value describing the family variant of the FPGA device
(e.g. SX, GX, GT).
* - SPEED_GRADE
- Encoded value describing the FPGAs speed-grade.
* - DEV_PACKAGE
- Encoded value describing the device package. The package might affect
high-speed interfaces.
* - FPGA_VOLTAGE
- Contains the value(0-5000 mV) at wich the FPGA device supplied.
* - TX_OR_RX_N
- If set (0x1), configures the link in transmit mode, otherwise receive.
Interfaces
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
.. hdl-interfaces::
:path: library/xilinx/axi_adxcvr
* - s_axi_aclk
- System clock. (in general 100 MHz)
* - s_axi_aresetn
- System reset.
* - s_axi
- Slave AXI4 Lite Memory Mapped interface
* - up_ch_*
- | Connect logical port ``pll_locked`` to the fPLLs **pll_locked** pin;
| Connect logical port ``ready`` to PHY reset controller.
Register Map
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
.. hdl-regmap::
:name: INTEL_XCVR
:no-type-info:
Software Guidelines
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
When the board powers up, both ATX and fPLL's must have a stable reference clock
in order to lock automatically. If this requirement can not be respected by the
system (e.g. the reference clocks are generated by a device that requires
software configuration, through an interface implemented in FPGA), the software
needs to reconfigure both PLLs, and just after that resets the transceivers.
AMD Xilinx Devices
--------------------------------------------------------------------------------
In AMD Xilinx Devices, the core configures itself to be interfaced with the GT
variant supported by the UTIL_ADXCVR core. All the transceiver primitives are
configured and programmed identically.
.. _parameters-1:
Parameters
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
.. hdl-parameters::
:path: library/xilinx/axi_adxcvr
* - ID
- Instance identification number, if more than one instance is used
* - NUM_OF_LANES
- The number of lanes (primitives) used in this link
* - XCVR_TYPE
- Define the current GT type, GTXE2(2), GTHE3(5), GTHE4(7)
* - FPGA_TECHNOLOGY
- Encoded value describing the technology/generation of the FPGA device
(7series/ultrascale)
* - FPGA_FAMILY
- Encoded value describing the family variant of the FPGA device(e.g.,
zynq, kintex, virtex)
* - SPEED_GRADE
- Encoded value describing the FPGA's speed-grade
* - DEV_PACKAGE
- Encoded value describing the device package. The package might affect
high-speed interfaces
* - FPGA_VOLTAGE
- Contains the value(0-5000 mV) at wich the FPGA device supplied
* - TX_OR_RX_N
- If set (0x1), configures the link in transmit mode, otherwise receive
* - QPLL_ENABLE
- If set (0x1), configures the link to use QPLL on QUAD basis. If multiple
links are sharing the same transceiver, only one of them may enable the
QPLL.
* - LPM_OR_DFE_N
- Chosing between LPM or DFE of modes for the RX Equalizer
* - RATE
- Defines the initial values for Transceiver Control Register (REG_CONTROL
0x0008)
* - TX_DIFFCTRL
- Driver Swing Control(TX Configurable Driver)
* - TX_POSTCURSOR
- Transmitter post-cursor TX pre-emphasis control
* - TX_PRECURSOR
- Transmitter pre-cursor TX pre-emphasis control
* - SYS_CLK_SEL
- Selects the PLL reference clock source to drive the RXOUTCLK
:ref:`Table 1 <axi_adxcvr table_one_label>`
* - OUT_CLK_SEL
- select the transceiver reference clock as the source of TXOUTCLK
:ref:`Table 2 <axi_adxcvr table_two_label>`
Interfaces
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
.. hdl-interfaces::
:path: library/xilinx/axi_adxcvr
.. _register-map-1:
Register Map
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
.. hdl-regmap::
:name: XCVR
:no-type-info:
.. _software-guidelines-1:
Software Guidelines
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
The system must have active DRP and reference clocks before any software access.
The software is expected to write necessary control parameters to LPM_DFE_N,
RATE, SYSCLK_SEL, OUTCLK_SEL register bits and then set RESETN bit to 0x1.
After that, monitor the STATUS bit to be set. There are no other requirements
for initialization.
The DRP access is identical for common and channel interfaces. The SEL bits may
be set to a specific transceiver lane or 0xff to broadcast. A write to the
CONTROL register (bits WR, ADDR, WDATA) initiates DRP access in hardware. A read
to this register has no effect. In order to write to the transceiver, set WR to
0x1 with the address. In order to read from the transceiver, set WR to 0x0 with
the address. As soon as this register is written, the BUSY signal is set and is
cleared only after the access is complete. The broadcast read is a logical OR of
all the channels. After an access is started, do NOT interrupt the core for any
reason (including setting RESETN to 0x0), allow the access to finish itself.
Though the core itself is immune to a software abort, the transceiver may fail
on further accesses and may require a system-wide reset.
The eye-scan feature also allows a SEL option and a broadcast has the effect of
a combined mask. That is, the error counter will be zero ONLY if all the
transceiver error counters are zero. To start eye-scan, set ES_REQ to 0x1 and
wait for the same bit to self-clear. If eye-scan needs to be stopped, set the
ES_REQ bit to 0x0.
.. _axi_adxcvr table_one_label:
Table 1
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
.. list-table::
:header-rows: 1
* - SYSCLK_SEL
- 00
- 01
- 10
- 11
* - GTXE2
- CPLL
- RESERVED
- RESERVED
- QPLL
* - GTHE3
- CPLL
- RESERVED
- QPLL1
- QPLL0
* - GTHE4
- CPLL
- RESERVED
- QPLL1
- QPLL0
* - GTYE4
- CPLL
- RESERVED
- QPLL1
- QPLL0
.. _axi_adxcvr table_two_label:
Table 2
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
.. list-table::
:header-rows: 1
* - OUTCLK_SEL
- 001
- 010
- 011
- 100
- 101
- All other combinations
* - GTXE2
- OUTCLKPCS
- OUTCLKPMA
- REFCLK
- REFCLK/2
- RESERVED
- RESERVED
* - GTHE3
- OUTCLKPCS
- OUTCLKPMA
- REFCLK
- REFCLK/2
- PROGDIVCLK
- RESERVED
* - GTHE4
- OUTCLKPCS
- OUTCLKPMA
- REFCLK
- REFCLK/2
- PROGDIVCLK
- RESERVED
* - GTYE4
- OUTCLKPCS
- OUTCLKPMA
- REFCLK
- REFCLK/2
- PROGDIVCLK
- RESERVED
The REFCLK selected by OUTCLK_SEL depends on the SYSCLK_SEL, it may be CPLL,
QPLL0 or QPLL1 refclk.
Physical layer PRBS testing
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
The REG_PRBS_CNTRL and REG_PRBS_STATUS registers expose controls of internal
PRBS generators and checkers allowing the testing the multi-gigabit serial link
at the physical layer without the need of the link layer bringup.
TX link procedure
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
#. Configure the reference clock and device clocks for under test lane rate.
Bring XCVR out from reset.
#. In the REG_PRBS_CNTRL registers set PRBSSEL to a non-zero value. See the
transceiver guides for exact values, different transceiver families may have
different encoding for the same pattern.
#. On the receiving side of the link, set the checker for the same pattern and
reset the error counters.
#. No error should be recorded on the receiver side.
#. Set the PRBSFORCEERR bit in the REG_PRBS_CNTRL register to force the error
injection into the stream of bits.
#. The error should be detected and recorded on the receiver side.
RX link procedure
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
#. Configure the reference clock and device clocks for under test lane rate.
Bring XCVR out from reset.
#. On the transmit side of the link, set a test pattern that is available in the
receiving transceiver. Consult the transceiver documentation for details.
#. In the REG_PRBS_CNTRL registers set PRBSSEL to the corresponding pattern.
Reset the error counters with PRBSCNTRESET.
#. Check REG_PRBS_STATUS fields for results. If the check is successful for
non-GTX transceivers the PRBSLOCKED bit must appear as set and PRBSERR must
stay low. For GTX transceivers the PRBSLOCKED bit can be ignored and checking
the PRBSERR alone is sufficient. If PRBSERR is set, check with DRP accesses
the internal error counter to get the number of errors received. See the
transceiver guide for details.
More Information
--------------------------------------------------------------------------------
- :ref:`jesd204`
- :dokuwiki:`JESD204B/C AXI_ADXCVR Highspeed Transceivers Linux Driver <resources/tools-software/linux-drivers/jesd204/axi_adxcvr>`
Reference
--------------------------------------------------------------------------------
- :intel:`Intel® Arria® 10 Transceiver PHY User Guide <content/dam/www/programmable/us/en/pdfs/literature/hb/arria-10/ug_arria10_xcvr_phy.pdf>`
- `7 Series FPGAs GTX/GTH Transceivers User Guide - AMD Xilinx <https://docs.amd.com/v/u/en-US/ug476_7Series_Transceivers>`_
- `Ultrascale Architecture GTH Transceivers User Guide - AMD Xilinx <https://docs.amd.com/v/u/en-US/ug576-ultrascale-gth-transceivers>`_

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axi_dmac/index
spi_engine/index
jesd204/index
axi_adxcvr/index
xilinx/index

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.. _ad_ip_jesd204_tpl_adc:
ADC JESD204B/C Transport Peripheral
================================================================================
.. hdl-component-diagram::
The ADC JESD204B/C Transport Peripheral implements the transport level handling
of a JESD204B/C transmitter device. It is compatible with a
:ref:`wide range of Analog Devices high-speed analog-to-digital converters <ad_ip_jesd204_tpl_adc_supported_devices>`.
The core handles the JESD204B/C deframing of the payload data.
The peripheral can be configured at runtime through a AXI4-Lite memory mapped
register map.
Features
--------------------------------------------------------------------------------
- ADI high-speed ADC compatible JESD204B/C data deframing;
- Test-pattern checker;
- Per-channel data formatting (sign extension, two's complement to offset
binary);
- Runtime reconfigurability through memory-mapped register interface
(AXI4-Lite).
Files
--------------------------------------------------------------------------------
:git-hdl:`ad_ip_jesd204_tpl_adc.v <library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc.v>`
Block Diagram
-------------
.. image:: ad_ip_jesd204_transport_adc.svg
:align: center
Synthesis Configuration Parameters
--------------------------------------------------------------------------------
.. hdl-parameters::
* - ID
- Instance identification number.
* - NUM_LANES
- Number of lanes supported by the peripheral.
Equivalent to JESD204 ``L`` parameter.
* - NUM_CHANNELS
- Number of converters supported by the peripheral.
Equivalent to JESD204 ``M`` parameter.
* - SAMPLES_PER_FRAME
- Number of samples per frame.
Equivalent to JESD204 ``S`` parameter.
* - CONVERTER_RESOLUTION
- Resolution of the converter.
Equivalent to JESD204 ``N`` parameter.
* - BITS_PER_SAMPLE
- Number of bits per sample.
Equivalent to JESD204 ``NP`` parameter.
* - OCTETS_PER_BEAT
- Number of bytes per beat for each link.
* - TWOS_COMPLEMENT
- PRBS data format.
* - PN7_ENABLE
- Enable PN7 check.
* - PN15_ENABLE
- Enable PN15 check.
.. *- PN31_ENABLE
.. - Enable PN31 check.
Signal and Interface Pins
--------------------------------------------------------------------------------
.. hdl-interfaces::
* - s_axi_aclk
- All ``S_AXI`` signals are synchronous to this clock.
* - s_axi_aresetn
- Resets the internal state of the peripheral.
* - s_axi
- Memory mapped AXI-lite bus that provides access to modules register map.
* - link
- link_data: JESD204 link data interface (link layer interface).
* - link_clk
- :dokuwiki:`Device clock <resources/fpga/peripherals/jesd204/jesd204_glossary#clocks>`
for the JESD204B interface of the Link Layer Interface. Must
be line clock/40 for correct 204B operation. Must be line
clock/66 for correct 64b66b 204C operation.
* - enable
- Channel enable indicator of the Application layer Interface
* - adc_valid
- Qualifier signal for each channel of the Application layer
interface. Always '1'.
* - adc_data
- Raw application layer data, every channel concatenated
(Application layer interface).
* - adc_dovf
- Application layer overflow of the Application layer interface.
The S_AXI interface is synchronous to the s_axi_aclk clock. All other signals
and interfaces are synchronous to the device_clk clock.
Register Map
--------------------------------------------------------------------------------
.. hdl-regmap::
:name: COMMON
:no-type-info:
.. hdl-regmap::
:name: ADC_COMMON
:no-type-info:
.. hdl-regmap::
:name: JESD_TPL
:no-type-info:
.. hdl-regmap::
:name: ADC_CHANNEL
:no-type-info:
Theory of Operation
--------------------------------------------------------------------------------
Interfaces and Signals
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Configuration Interface
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
The Peripheral features a register map configuration interface that can be
accessed through the AXI4-Lite ``S_AXI`` port. The register map can be used to
configure the Peripheral's operational parameters, query the current status of
the device and query the features supported by the device.
Link layer interface
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
The link layer interface description can be found in the
:ref:`User Data Interface <axi_jesd204_rx_user_data>` section of the
:ref:`JESD204B/C Link Receive Peripheral <axi_jesd204_rx>` IP.
Application layer interface
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
The application layer is connected to the deframer block output. The deframer
module creates sample data from the lane mapped and formatted JESD204 link data
based on the specified deframer configuration.
The data in the application layer interface ``adc_data`` has the following
layout:
::
MSB LSB
[ MmSn, ..., MmS1, MnS0, ..., M1Sn, ... M1S1, M1S0, M0Sn, ... M0S1, M0S0 ]
Where MjSi refers to the i-th sample of the j-th converter. With m being the
number of converters and n the number of samples per converter per beat.
The core asserts the ``enable`` signal for each channel that is enabled by the
software.
Clock Monitor
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
The ``REG_STATUS`` (``0x054``) register ``CLK_FREQ`` field allows to determine
the clock rate of the device clock (``link_clk``) relative to the AXI interface
clock (``s_axi_aclk``). This can be used to verify that the device clock is
running at the expected rate.
The number is represented as unsigned 16.16 format. Assuming a 100MHz processor
clock, this corresponds to a resolution of 1.523kHz per LSB. A raw value of 0
indicates that the link clock is currently not active.
Data Formatter
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
The component is configured by the ``REG_CHAN_CNTRL`` register
``FORMAT_SIGNEXT,FORMAT_TYPE,FORMAT_ENABLE`` fields. The block introduces one
clock cycle latency.
PRBS Check
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
The block can monitor and compare the incoming deframed raw data against
PN9, PN23 and PN7, PN15 (if enabled) patterns selected by the ``ADC_PN_SEL``
field of ``REG_CHAN_CNTRL_3`` register.
..
it is missing PN31, because it does not exist on the source code
.. list-table::
:header-rows: 1
* - ADC_PN_SEL
- PN
- ENABLE
* - 0
- PN9
- 1
* - 1
- PN23
- 1
* - 4
- PN7
- PN7_ENABLE
* - 5
- PN15
- PN15_ENABLE
.. *-7
.. -PN31
.. -PN31_ENABLE
Before performing these tests you need to make sure that the ADC OUTPUT FORMAT
is set according to the ``TWOS_COMPLEMENT`` synthesis parameter.
For each channel, mismatches are reported in ``PN_ERR`` and ``PN_OOS`` fields of
the ``REG_CHAN_STATUS`` register.
External synchronization
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
An external synchronization signal ``adc_sync_in`` can be used to trigger data
movement from the link layer to user application layer.
The external synchronization signal should be synchronous with the ADC clock.
Synchronization will be done on the rising edge of the signal.
The self clearing ``SYNC`` control bit from the ``REG_CNTRL (0x44)`` register,
will arm the trigger logic to wait for the external sync signal. The
``ADC_SYNC`` status bit from ``REG_SYNC_STATUS (0x68)`` register, will show that
the synchronization is armed, but the synchronization signal has not yet been
received.
Once the sync signal is received, the data will start to flow and the
``ADC_SYNC`` status bit will reflect that with a deassertion.
While the synchronization mechanism is armed, the ``adc_rst`` output signal is
set such that downstream logic can be cleared, to have a fresh start once the
trigger is received.
Software Support
--------------------------------------------------------------------------------
.. warning::
To ensure correct operation, it is highly recommended to use the
Analog Devices provided JESD204B/C software packages for interfacing the
peripheral. Analog Devices is not able to provide support in case issues arise
from using custom low-level software for interfacing the peripheral.
Restrictions
--------------------------------------------------------------------------------
Reduced number of octets-per-frame (``F``) settings. The following values are
supported by the peripheral: 1, 2, 4
- Starting from
`this <https://github.com/analogdevicesinc/hdl/commit/454b900f90081fb95be857114e768f662178c8bd>`__
commit this restriction no longer applies.
.. _ad_ip_jesd204_tpl_adc_supported_devices:
Supported Devices
--------------------------------------------------------------------------------
JESD204B Analog-to-Digital Converters
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
- :adi:`AD6673 <en/products/AD6673>`: 80 MHz Bandwidth, Dual IF Receiver
- :adi:`AD6674 <en/products/AD6674>`: 385 MHz BW IF Diversity Receiver
- :adi:`AD6676 <en/products/AD6676>`: Wideband IF Receiver Subsystem
- :adi:`AD6677 <en/products/AD6677>`: 80 MHz Bandwidth, IF Receiver
- :adi:`AD6684 <en/products/AD6684>`: 135 MHz Quad IF Receiver
- :adi:`AD6688 <en/products/AD6688>`: RF Diversity and 1.2GHz BW Observation
Receiver
- :adi:`AD9207 <en/products/AD9207>`: 12-Bit, 6 GSPS, JESD204B/JESD204C
Dual Analog-to-Digital Converter
- :adi:`AD9208 <en/products/AD9208>`: 14-Bit, 3GSPS, JESD204B,
Dual Analog-to-Digital Converter
- :adi:`AD9209 <en/products/AD9209>`: 12-Bit, 4GSPS, JESD204B/C, Quad
Analog-to-Digital Converter
- :adi:`AD9213 <en/products/AD9213>`: 12-Bit, 10.25 GSPS, JESD204B, RF
Analog-to-Digital Converter
- :adi:`AD9234 <en/products/AD9234>`: 12-Bit, 1 GSPS/500 MSPS JESD204B, Dual
Analog-to-Digital Converter
- :adi:`AD9250 <en/products/AD9250>`: 14-Bit, 170 MSPS/250 MSPS, JESD204B, Dual
Analog-to-Digital Converter
- :adi:`AD9625 <en/products/AD9625>`: 12-Bit, 2.6 GSPS/2.5 GSPS/2.0 GSPS,
1.3 V/2.5 V Analog-to-Digital Converter
- :adi:`AD9656 <en/products/AD9656>`: Quad, 16-Bit, 125 MSPS JESD204B 1.8 V
Analog-to-Digital Converter
- :adi:`AD9680 <en/products/AD9680>`: 14-Bit, 1.25 GSPS/1 GSPS/820 MSPS/500
MSPS JESD204B, Dual Analog-to-Digital Converter
- :adi:`AD9683 <en/products/AD9683>`: 14-Bit, 170 MSPS/250 MSPS, JESD204B,
Analog-to-Digital Converter
- :adi:`AD9690 <en/products/AD9690>`: 14-Bit, 500 MSPS / 1 GSPS JESD204B,
Analog-to-Digital Converter
- :adi:`AD9691 <en/products/AD9691>`: 14-Bit, 1.25 GSPS JESD204B,
Dual Analog-to-Digital Converter
- :adi:`AD9694 <en/products/AD9694>`: 14-Bit, 500 MSPS JESD204B, Quad
Analog-to-Digital Converter
- :adi:`AD9695 <en/products/AD9695>`: 14-Bit, 1300 MSPS/625 MSPS,
JESD204B, Dual Analog-to-Digital Converter Analog-to-Digital Converter
- :adi:`AD9083 <en/products/AD9083>`: 16-Channel, 125 MHz Bandwidth, JESD204B
Analog-to-Digital Converter
- :adi:`AD9094 <en/products/AD9094>`: 8-Bit, 1 GSPS, JESD204B, Quad
Analog-to-Digital Converter
JESD204B RF Transceivers
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
- :adi:`AD9371 <en/products/AD9371>`: SDR Integrated, Dual RF Transceiver with
Observation Path
- :adi:`AD9375 <en/products/AD9375>`: SDR Integrated, Dual RF Transceiver with
Observation Path and DPD
- :adi:`ADRV9009 <en/products/ADRV9009>`: SDR Integrated, Dual RF Transceiver
with Observation Path
- :adi:`ADRV9008-1 <en/products/ADRV9008-1>`: SDR Integrated, Dual RF Receiver
- :adi:`ADRV9008-2 <en/products/ADRV9008-2>`: SDR Integrated, Dual RF
Transmitter with Observation Path
JESD204B/C Mixed-Signal Front Ends
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
- :adi:`AD9081 <en/products/AD9081>`: MxFE™ Quad, 16-Bit, 12GSPS RFDAC and
Quad, 12-Bit, 4GSPS RFADC
- :adi:`AD9082 <en/products/AD9082>`: MxFE™ QUAD, 16-Bit, 12GSPS RFDAC and
DUAL, 12-Bit, 6GSPS RFADC
- :adi:`AD9986 <en/products/AD9986>`: 4T2R Direct RF Transmitter and
Observation Receiver
- :adi:`AD9988 <en/products/AD9988>`: 4T4R Direct RF Receiver and Transmitter
More Information
--------------------------------------------------------------------------------
- :ref:`JESD204 Interface Framework <jesd204>`
- :dokuwiki:`Glossary of terms <resources/fpga/peripherals/jesd204/jesd204_glossary>`
- :ref:`HDL User Guide <user_guide>`
Technical Support
--------------------------------------------------------------------------------
Analog Devices will provide limited online support for anyone using the core
with Analog Devices components (ADC, DAC, Video, Audio, etc) via the
:ez:`EngineerZone <fpga>`.

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.. _ad_ip_jesd204_tpl_dac:
DAC JESD204B/C Transport Peripheral
================================================================================
.. hdl-component-diagram::
The DAC JESD204B/C Transport Peripheral (AD-IP-JESD204-TRANSPORT-DAC) implements
the transport level handling of a JESD204B/C transmitter device. It is
compatible with a
:ref:`wide range of Analog Devices high-speed digital-to-analog converters <ad_ip_jesd204_tpl_dac_supported_devices>`.
The core handles the JESD204B/C framing of the user-provided payload data. In
addition, it is capable of generating standard and user-defined test-pattern
data for interface verification. It also features a per-channel dual-tone DDS
that can be used to dynamically generate test-tones.
The peripheral can be configured at runtime through a AXI4-Lite memory mapped
register map.
Features
--------------------------------------------------------------------------------
- ADI high-speed DAC compatible JESD204B/C data framing;
- Test-pattern generator for interface verification;
- Per-channel dual-tone DDS (optional);
- Runtime reconfigurability through memory-mapped register interface
(AXI4-Lite).
Files
--------------------------------------------------------------------------------
:git-hdl:`ad_ip_jesd204_tpl_dac.v <library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac.v>`
Block Diagram
--------------------------------------------------------------------------------
.. image:: ad_ip_jesd204_transport_dac.svg
:align: center
Synthesis Configuration Parameters
--------------------------------------------------------------------------------
.. hdl-parameters::
* - ID
- Instance identification number.
* - NUM_LANES
- Number of lanes supported by the peripheral.
Equivalent to JESD204 ``L`` parameter.
* - NUM_CHANNELS
- Number of converters supported by the peripheral.
- Equivalent to JESD204 ``M`` parameter.
* - SAMPLES_PER_FRAME
- Number of samples per frame.
Equivalent to JESD204 ``S`` parameter.
* - CONVERTER_RESOLUTION
- Resolution of the converter.
Equivalent to JESD204 ``N`` parameter.
* - BITS_PER_SAMPLE
- Number of bits per sample.
Equivalent to JESD204 ``NP`` parameter.
* - OCTETS_PER_BEAT
- Number of bytes per beat for each link.
* - DDS_TYPE
- DDS Type. Set 1 for CORDIC or 2 for Polynomial
* - DDS_CORDIC_DW
- CORDIC DDS Data Width.
* - DDS_CORDIC_PHASE_DW
- CORDIC DDS Phase Width.
* - DATAPATH_DISABLE
- Disable instantiation of DDS core.
Signal and Interface Pins
--------------------------------------------------------------------------------
.. hdl-interfaces::
* - s_axi_aclk
- All ``S_AXI`` signals and ``irq`` are synchronous to this clock.
* - s_axi_aresetn
- Resets the internal state of the peripheral.
* - s_axi
- Memory mapped AXI-lite bus that provides access to modules register map.
* - link
- link_data: Framed transmit data towards link layer.
* - link_clk
- :dokuwiki:`Device clock <resources/fpga/peripherals/jesd204/jesd204_glossary#clocks>`
for the JESD204B/C interface. Must be line clock/40 for 204B correct operation.
Must be line clock/66 for correct 204C operation.
* - enable
- Request signal for each channel.
* - dac_valid
- Qualifier signal for each channel. Always '1'.
* - dac_ddata
- Raw application layer data, every channel concatenated.
* - dac_dunf
- Application layer underflow.
Register Map
--------------------------------------------------------------------------------
.. hdl-regmap::
:name: COMMON
:no-type-info:
.. hdl-regmap::
:name: DAC_COMMON
:no-type-info:
.. hdl-regmap::
:name: JESD_TPL
:no-type-info:
.. hdl-regmap::
:name: DAC_CHANNEL
:no-type-info:
Theory of Operation
--------------------------------------------------------------------------------
Data paths
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
The data intended for the DAC can have multiple sources:
- **DMA source** Raw data can be accepted from a external block representing
the Application layer;
- **DDS source** For each DAC channel, a dual-tone can be generated by a DDS
core;
- **PRBS source** For each DAC channel, one of the following PN sequence can
be selected: PN7, PN15, inverted PN7, inverted PN15.
Interfaces and Signals
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Application layer interface
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
The application layer connects to the framer block when the DMA source is
selected. The framer module takes sample data and maps it onto the format that
the JESD204 link expects for the specified framer configuration.
The data in the application layer interface ``dac_ddata`` is expected to have
the following layout:
::
MSB LSB
[ MmSn, ..., MmS1, MnS0, ..., M1Sn, ... M1S1, M1S0, M0Sn, ... M0S1, M0S0 ]
Where MjSi refers to the i-th sample of the j-th converter. With m being the
number of converters and n the number of samples per converter per beat.
The core asserts the ``enable`` signal for each channel that is enabled by the
software. The ``dac_ddata`` data bus must contain data for each channel
regardless if the channels are enabled or not.
Link layer interface
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
The link layer interface description can be found in the
:ref:`User Data Interface <axi_jesd204_tx_user_data>` section of the
:ref:`JESD204B/C Link Transmit Peripheral <axi_jesd204_tx>` IP.
Clock Monitor
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
The ``REG_STATUS`` (``0x054``) register ``CLK_FREQ`` field allows to determine
the clock rate of the device clock (``link_clk``) relative to the AXI interface
clock (``s_axi_aclk``). This can be used to verify that the device clock is
running at the expected rate.
The number is represented as unsigned 16.16 format. Assuming a 100MHz processor
clock, this corresponds to a resolution of 1.523kHz per LSB. A raw value of 0
indicates that the link clock is currently not active.
External synchronization
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
By setting the ``EXT_SYNC`` parameter of the IP to 1, an external
synchronization signal ``dac_sync_in`` can be used to trigger data movement
from user application layer to the link layer, reset internal DDS cores or PRBS
generators. If the ``EXT_SYNC`` parameter is set to zero, the external signal
is ignored and only a software controlled reset happens inside the DDS,
PRBS logic.
The external synchronization signal should be synchronous with the DAC clock.
Synchronization will be done on the rising edge of the signal.
The self clearing ``SYNC`` control bit from the ``REG_CNTRL_1`` (``0x44``)
register will arm the trigger logic to wait for the external sync signal. The
``DAC_SYNC_STATUS`` status bit from the ``REG_SYNC_STATUS`` (``0x68``) register
will show that the synchronization is armed but the synchronization signal has
not yet been received.
Once the sync signal is received, the data will start to flow and the
``DAC_SYNC_STATUS`` status bit will reflect that with a deassertion.
While the synchronization mechanism is armed, the ``dac_valid`` output signal
is gated until the trigger signal is received. The gating happens only during
this period, meaning that ``dac_valid`` will stay high in all other
cases (normal operation).
Restrictions
--------------------------------------------------------------------------------
Reduced number of octets-per-frame (``F``) settings. The following values are
supported by the peripheral: 1, 2, 4
- Starting from
`this <https://github.com/analogdevicesinc/hdl/commit/454b900f90081fb95be857114e768f662178c8bd>`__
commit this restriction no longer applies
Software Support
--------------------------------------------------------------------------------
.. warning::
To ensure correct operation it is highly recommended to use the Analog
Devices provided JESD204B/C software packages for interfacing the peripheral.
Analog Devices is not able to provide support in case issues arise from using
custom low-level software for interfacing the peripheral.
.. _ad_ip_jesd204_tpl_dac_supported_devices:
Supported Devices
--------------------------------------------------------------------------------
JESD204B Digital-to-Analog Converters
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
- :adi:`AD9135 <en/products/AD9135>`: Dual, 11-Bit, high dynamic, 2.8 GSPS,
TxDAC+® Digital-to-Analog Converter
- :adi:`AD9136 <en/products/AD9136>`: Dual, 16-Bit, 2.8 GSPS, TxDAC+®
Digital-to-Analog Converter
- :adi:`AD9144 <en/products/AD9144>`: Quad, 16-Bit, 2.8 GSPS, TxDAC+®
Digital-to-Analog Converter
- :adi:`AD9152 <en/products/AD9152>`: Dual, 16-Bit, 2.25 GSPS, TxDAC+
Digital-to-Analog Converter
- :adi:`AD9154 <en/products/AD9154>`: Quad, 16-Bit, 2.4 GSPS, TxDAC+®
Digital-to-Analog Converter
- :adi:`AD9161 <en/products/AD9161>`: 11-Bit, 12 GSPS, RF Digital-to-Analog
Converter
- :adi:`AD9162 <en/products/AD9162>`: 16-Bit, 12 GSPS, RF Digital-to-Analog
Converter
- :adi:`AD9163 <en/products/AD9163>`: 16-Bit, 12 GSPS, RF DAC and Digital
Upconverter
- :adi:`AD9164 <AD9164>`: 16-Bit, 12 GSPS, RF DAC and Direct Digital
Synthesizer
- :adi:`AD9172 <en/products/AD9172>`: Dual, 16-Bit, 12.6 GSPS RF DAC with
Channelizers
- :adi:`AD9173 <en/products/AD9173>`: Dual, 16-Bit, 12.6 GSPS RF DAC with
Channelizers
- :adi:`AD9174 <en/products/AD9174>`: Dual, 16-Bit, 12.6 GSPS RF DAC and Direct
Digital Synthesizer
- :adi:`AD9175 <en/products/AD9175>`: Dual, 11-Bit/16-Bit, 12.6 GSPS RF DAC with
Wideband Channelizers
- :adi:`AD9176 <en/products/AD9176>`: Dual, 16-Bit, 12.6 GSPS RF DAC with
Wideband Channelizers
- :adi:`AD9177 <en/products/AD9177>`: Quad, 16-Bit, 12 GSPS RF DAC with
Wideband Channelizers
JESD204B RF Transceivers
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
- :adi:`AD9371 <en/products/AD9371>`: SDR Integrated, Dual RF Transceiver with
Observation Path
- :adi:`AD9375 <en/products/AD9375>`: SDR Integrated, Dual RF Transceiver with
Observation Path and DPD
- :adi:`ADRV9009 <en/products/ADRV9009>`: SDR Integrated, Dual RF Transceiver
with Observation Path
- :adi:`ADRV9008-1 <en/products/ADRV9008-1>`: SDR Integrated, Dual RF Receiver
- :adi:`ADRV9008-2 <en/products/ADRV9008-2>`: SDR Integrated, Dual RF
Transmitter with Observation Path
JESD204B/C Mixed-Signal Front Ends
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
- :adi:`AD9081 <en/products/AD9081>`: MxFE™ Quad, 16-Bit, 12GSPS RFDAC and
Quad, 12-Bit, 4GSPS RFADC
- :adi:`AD9082 <en/products/AD9082>`: MxFE™ QUAD, 16-Bit, 12GSPS RFDAC and
DUAL, 12-Bit, 6GSPS RFADC
- :adi:`AD9986 <en/products/AD9986>`: 4T2R Direct RF Transmitter and
Observation Receiver
- :adi:`AD9988 <en/products/AD9988>`: 4T4R Direct RF Receiver and Transmitter
More Information
--------------------------------------------------------------------------------
- :ref:`JESD204 Interface Framework <jesd204>`
- :dokuwiki:`Glossary of terms <resources/fpga/peripherals/jesd204/jesd204_glossary>`
- :ref:`HDL User Guide <user_guide>`
Technical Support
--------------------------------------------------------------------------------
Analog Devices will provide limited online support for anyone using the core
with Analog Devices components (ADC, DAC, Video, Audio, etc) via the
:ez:`EngineerZone <fpga>`.

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x="126.29234"
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id="text16-4-1-0-4"><tspan
x="126.29234"
y="123.62984"
style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:12px;font-family:sans-serif;-inkscape-font-specification:'sans-serif, ';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-variant-east-asian:normal;text-align:start;letter-spacing:0px;text-anchor:start;fill:#000000;fill-opacity:1;stroke:none;stroke-width:0.415661"
id="tspan27-2-3">!disabled</tspan></text>
<text
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style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:12px;font-family:sans-serif;-inkscape-font-specification:'sans-serif, ';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-variant-east-asian:normal;text-align:start;letter-spacing:0px;word-spacing:0px;text-anchor:start;fill:none;stroke:none;stroke-width:0.415661;stroke-linejoin:round;stroke-dasharray:none"
x="126.89961"
y="222.66722"
id="text16-4-1-0-4-6"><tspan
x="126.89961"
y="222.66722"
style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:12px;font-family:sans-serif;-inkscape-font-specification:'sans-serif, ';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-variant-east-asian:normal;text-align:start;letter-spacing:0px;text-anchor:start;fill:#000000;fill-opacity:1;stroke:none;stroke-width:0.415661"
id="tspan27-2-3-7">PHY controller for when</tspan><tspan
x="126.89961"
y="235.16722"
style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:12px;font-family:sans-serif;-inkscape-font-specification:'sans-serif, ';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-variant-east-asian:normal;text-align:start;letter-spacing:0px;text-anchor:start;fill:#000000;fill-opacity:1;stroke:none;stroke-width:0.415661"
id="tspan5">all lanes are ready</tspan></text>
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id="path16-1"
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<text
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style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:14px;font-family:sans-serif;-inkscape-font-specification:'sans-serif, Normal';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-variant-east-asian:normal;text-align:center;letter-spacing:0px;word-spacing:0px;text-anchor:middle;fill:none;stroke:none;stroke-width:0.415661;stroke-linejoin:round;stroke-dasharray:none"
x="118.91644"
y="76.009346"
id="text16-06"><tspan
id="tspan16-7"
x="118.91644"
y="76.009346"
style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:14px;font-family:sans-serif;-inkscape-font-specification:'sans-serif, Normal';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-variant-east-asian:normal;letter-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;stroke-width:0.415661">RESET</tspan></text>
<text
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style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:14px;font-family:sans-serif;-inkscape-font-specification:'sans-serif, Normal';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-variant-east-asian:normal;text-align:center;letter-spacing:0px;word-spacing:0px;text-anchor:middle;fill:none;stroke:none;stroke-width:0.415661;stroke-linejoin:round;stroke-dasharray:none"
x="94.147125"
y="10.636719"
id="text16-06-1"><tspan
id="tspan16-7-9"
x="94.147125"
y="10.636719"
style="font-style:normal;font-variant:normal;font-weight:bold;font-stretch:normal;font-size:14px;font-family:Sans;-inkscape-font-specification:'Sans, Bold';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-variant-east-asian:normal;letter-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;stroke-width:0.415661">Link State Machine</tspan></text>
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<text
xml:space="preserve"
style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:12px;font-family:sans-serif;-inkscape-font-specification:'sans-serif, ';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-variant-east-asian:normal;text-align:start;letter-spacing:0px;word-spacing:0px;text-anchor:start;fill:none;stroke:none;stroke-width:0.415661;stroke-linejoin:round;stroke-dasharray:none"
x="127.15289"
y="331.22256"
id="text16-4-1-0-4-8"><tspan
x="127.15289"
y="331.22256"
style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:12px;font-family:sans-serif;-inkscape-font-specification:'sans-serif, ';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-variant-east-asian:normal;text-align:start;letter-spacing:0px;text-anchor:start;fill:#000000;fill-opacity:1;stroke:none;stroke-width:0.415661"
id="tspan27-2-3-1">All lanes are in</tspan><tspan
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y="343.72256"
style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:12px;font-family:sans-serif;-inkscape-font-specification:'sans-serif, ';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-variant-east-asian:normal;text-align:start;letter-spacing:0px;text-anchor:start;fill:#000000;fill-opacity:1;stroke:none;stroke-width:0.415661"
id="tspan6">the DATA phase</tspan></text>
<text
xml:space="preserve"
style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:12px;font-family:sans-serif;-inkscape-font-specification:'sans-serif, ';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-variant-east-asian:normal;text-align:start;letter-spacing:0px;word-spacing:0px;text-anchor:start;fill:none;stroke:none;stroke-width:0.415661;stroke-linejoin:round;stroke-dasharray:none"
x="10.411446"
y="546.25116"
id="text16-4-1-0-4-8-4"><tspan
x="10.411446"
y="546.25116"
style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:12px;font-family:sans-serif;-inkscape-font-specification:'sans-serif, ';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-variant-east-asian:normal;text-align:start;letter-spacing:0px;text-anchor:start;fill:#000000;fill-opacity:1;stroke:none;stroke-width:0.415661"
id="tspan6-1">At least four</tspan><tspan
x="10.411446"
y="558.75116"
style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:12px;font-family:sans-serif;-inkscape-font-specification:'sans-serif, ';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-variant-east-asian:normal;text-align:start;letter-spacing:0px;text-anchor:start;fill:#000000;fill-opacity:1;stroke:none;stroke-width:0.415661"
id="tspan10">consecutive</tspan><tspan
x="10.411446"
y="571.25116"
style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:12px;font-family:sans-serif;-inkscape-font-specification:'sans-serif, ';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-variant-east-asian:normal;text-align:start;letter-spacing:0px;text-anchor:start;fill:#000000;fill-opacity:1;stroke:none;stroke-width:0.415661"
id="tspan11">/K/ characters</tspan><tspan
x="10.411446"
y="583.75116"
style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:12px;font-family:sans-serif;-inkscape-font-specification:'sans-serif, ';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-variant-east-asian:normal;text-align:start;letter-spacing:0px;text-anchor:start;fill:#000000;fill-opacity:1;stroke:none;stroke-width:0.415661"
id="tspan12">are received</tspan></text>
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style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:12px;font-family:sans-serif;-inkscape-font-specification:'sans-serif, ';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-variant-east-asian:normal;text-align:start;letter-spacing:0px;word-spacing:0px;text-anchor:start;fill:none;stroke:none;stroke-width:0.415661;stroke-linejoin:round;stroke-dasharray:none"
x="151.89297"
y="550.39148"
id="text16-4-1-0-4-8-4-7"><tspan
x="151.89297"
y="550.39148"
style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:12px;font-family:sans-serif;-inkscape-font-specification:'sans-serif, ';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-variant-east-asian:normal;text-align:start;letter-spacing:0px;text-anchor:start;fill:#000000;fill-opacity:1;stroke:none;stroke-width:0.415661"
id="tspan12-9">More than three</tspan><tspan
x="151.89297"
y="562.89148"
style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:12px;font-family:sans-serif;-inkscape-font-specification:'sans-serif, ';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-variant-east-asian:normal;text-align:start;letter-spacing:0px;text-anchor:start;fill:#000000;fill-opacity:1;stroke:none;stroke-width:0.415661"
id="tspan15">invalid characters</tspan><tspan
x="151.89297"
y="575.39148"
style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:12px;font-family:sans-serif;-inkscape-font-specification:'sans-serif, ';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-variant-east-asian:normal;text-align:start;letter-spacing:0px;text-anchor:start;fill:#000000;fill-opacity:1;stroke:none;stroke-width:0.415661"
id="tspan16">are received</tspan></text>
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style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:12px;font-family:sans-serif;-inkscape-font-specification:'sans-serif, ';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-variant-east-asian:normal;text-align:start;letter-spacing:0px;word-spacing:0px;text-anchor:start;fill:none;stroke:none;stroke-width:0.415661;stroke-linejoin:round;stroke-dasharray:none"
x="84.842606"
y="457.83777"
id="text16-4-1-0-6"><tspan
x="84.842606"
y="457.83777"
style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:12px;font-family:sans-serif;-inkscape-font-specification:'sans-serif, ';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-variant-east-asian:normal;text-align:start;letter-spacing:0px;text-anchor:start;fill:#000000;fill-opacity:1;stroke:none;stroke-width:0.415661"
id="tspan27-2-4">reset</tspan></text>
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cx="119.55518"
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id="path16-2-1-6"
cx="119.55518"
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<text
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style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:14px;font-family:sans-serif;-inkscape-font-specification:'sans-serif, Normal';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-variant-east-asian:normal;text-align:center;letter-spacing:0px;word-spacing:0px;text-anchor:middle;fill:none;stroke:none;stroke-width:0.415661;stroke-linejoin:round;stroke-dasharray:none"
x="119.01395"
y="504.92889"
id="text16-06-7"><tspan
id="tspan16-7-4"
x="119.01395"
y="504.92889"
style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:14px;font-family:sans-serif;-inkscape-font-specification:'sans-serif, Normal';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-variant-east-asian:normal;letter-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;stroke-width:0.415661">INIT</tspan></text>
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id="path16-9-6-7"
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id="tspan4-2">CHECK</tspan></text>
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<text
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style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:14px;font-family:sans-serif;-inkscape-font-specification:'sans-serif, Normal';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-variant-east-asian:normal;text-align:center;letter-spacing:0px;word-spacing:0px;text-anchor:middle;fill:none;stroke:none;stroke-width:0.415661;stroke-linejoin:round;stroke-dasharray:none"
x="118.94638"
y="714.83191"
id="text16-0-9-3"><tspan
id="tspan16-8-8-3"
x="118.94638"
y="714.83191"
style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:14px;font-family:sans-serif;-inkscape-font-specification:'sans-serif, Normal';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-variant-east-asian:normal;letter-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;stroke-width:0.415661">DATA</tspan></text>
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id="path10" />
<path
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<path
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<text
xml:space="preserve"
style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:12px;font-family:sans-serif;-inkscape-font-specification:'sans-serif, ';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-variant-east-asian:normal;text-align:start;letter-spacing:0px;word-spacing:0px;text-anchor:start;fill:none;stroke:none;stroke-width:0.415661;stroke-linejoin:round;stroke-dasharray:none"
x="153.60271"
y="649.02429"
id="text16-4-1-0-4-8-4-6"><tspan
x="153.60271"
y="649.02429"
style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:12px;font-family:sans-serif;-inkscape-font-specification:'sans-serif, ';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-variant-east-asian:normal;text-align:start;letter-spacing:0px;text-anchor:start;fill:#000000;fill-opacity:1;stroke:none;stroke-width:0.415661"
id="tspan12-2">At least one</tspan><tspan
x="153.60271"
y="661.52429"
style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:12px;font-family:sans-serif;-inkscape-font-specification:'sans-serif, ';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-variant-east-asian:normal;text-align:start;letter-spacing:0px;text-anchor:start;fill:#000000;fill-opacity:1;stroke:none;stroke-width:0.415661"
id="tspan19">invalid character</tspan><tspan
x="153.60271"
y="674.02429"
style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:12px;font-family:sans-serif;-inkscape-font-specification:'sans-serif, ';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-variant-east-asian:normal;text-align:start;letter-spacing:0px;text-anchor:start;fill:#000000;fill-opacity:1;stroke:none;stroke-width:0.415661"
id="tspan20">is received</tspan></text>
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style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:12px;font-family:sans-serif;-inkscape-font-specification:'sans-serif, ';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-variant-east-asian:normal;text-align:start;letter-spacing:0px;word-spacing:0px;text-anchor:start;fill:none;stroke:none;stroke-width:0.415661;stroke-linejoin:round;stroke-dasharray:none"
x="-0.15234375"
y="644.88391"
id="text16-4-1-0-4-8-4-67"><tspan
x="-0.15234375"
y="644.88391"
style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:12px;font-family:sans-serif;-inkscape-font-specification:'sans-serif, ';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-variant-east-asian:normal;text-align:start;letter-spacing:0px;text-anchor:start;fill:#000000;fill-opacity:1;stroke:none;stroke-width:0.415661"
id="tspan6-1-9">At least four</tspan><tspan
x="-0.15234375"
y="657.38391"
style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:12px;font-family:sans-serif;-inkscape-font-specification:'sans-serif, ';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-variant-east-asian:normal;text-align:start;letter-spacing:0px;text-anchor:start;fill:#000000;fill-opacity:1;stroke:none;stroke-width:0.415661"
id="tspan10-7">consecutive</tspan><tspan
x="-0.15234375"
y="669.88391"
style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:12px;font-family:sans-serif;-inkscape-font-specification:'sans-serif, ';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-variant-east-asian:normal;text-align:start;letter-spacing:0px;text-anchor:start;fill:#000000;fill-opacity:1;stroke:none;stroke-width:0.415661"
id="tspan11-6">valid characters</tspan><tspan
x="-0.15234375"
y="682.38391"
style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:12px;font-family:sans-serif;-inkscape-font-specification:'sans-serif, ';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-variant-east-asian:normal;text-align:start;letter-spacing:0px;text-anchor:start;fill:#000000;fill-opacity:1;stroke:none;stroke-width:0.415661"
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.. _jesd204:
JESD204 Interface Framework
================================================================================
.. toctree::
:hidden:
JESD204B/C Link Transmit Peripheral <axi_jesd204_tx/index>
JESD204B/C Link Receive Peripheral <axi_jesd204_rx/index>
ADC JESD204B/C Transport Peripheral <ad_ip_jesd204_tpl_adc/index>
DAC JESD204B/C Transport Peripheral <ad_ip_jesd204_tpl_dac/index>
The JESD204, JESD204A, JESD204B and the JESD204C data converter serial interface
standard was created through the JEDEC committee to standardize and reduce the
number of data inputs/outputs between high-speed data converters and other
devices, such as FPGAs (field-programmable gate arrays). Fewer interconnects
simplifies layout and allows smaller form factor realization without impacting
overall system performance. These attributes are important to address the system
size and cost constraints of a range of high-speed ADC applications, including
wireless infrastructure (GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA)
transceiver architectures, software-defined radios, portable instrumentation,
medical ultrasound equipment, and Mil/Aero applications such as radar and secure
communications. Analog Devices is an original participating member of the JEDEC
JESD204 standards committee and we have concurrently developed compliant data
converter technology and tools, and a comprehensive product roadmap to fully
enable our customers to take advantage of this significant interfacing
breakthrough.
Analog Devices supplies a full-stack supporting JESD204B/C which provides a
fully integrated system level experience. This solution includes:
.. hint::
* :ref:`Reference hardware platforms <rapid_prototyping_label>` for
rapid-prototyping
* :ref:`FPGA HDL support <fpga_hdl_support_label>` for interfacing JESD204B/C ADCs,
DACs, and RF Transceivers
* :ref:`Software support <software_support_label>` to configure the converter
devices and FPGA HDL peripherals
How to Obtain a License
--------------------------------------------------------------------------------
When customers and partners download/use software from GitHub, e-mail or
similar ways, they are obligated to comply to the terms and conditions of
the :git-hdl:`Software License Agreement <LICENSE_ADIJESD204>`.
This core is released under two different licenses. You may choose either:
- Commercial licenses may be purchased from :adi:`Analog Devices, Inc. <>`. or any
authorized distributor by ordering
:adi:`IP-JESD204 <en/design-center/evaluation-hardware-and-software/jesd204-interface-framework.html>`.
This will allow you to use the core in a closed system.
- GPL 2, this allows you to use the core for any purpose, but you must release
anything else that links to the JESD204 core (this would normally be your
algorithmic IP). **You do not need to sign or purchase** anything to use
the JESD204 core under the GPL license.
There is only one core -- the only difference is the license and support.
If you have a question about the license, you can email
`jesd204-licensing@analog.com <jesd204-licensing@analog.com>`__.
.. _fpga_hdl_support_label:
FPGA HDL Support
--------------------------------------------------------------------------------
.. image:: jesd204_layers2.svg
:align: right
The JESD204B/C standard defines multiple layers, each layer being responsible
for a particular function. The Analog Devices JESD204B/C HDL solution follows
the current standard and defines 4 layers. Physical layer, link layer, transport
layer and application layer. For the first three layers, :adi:`ADI <>` provides
standard components that can be linked to provide a full JESD204B/C protocol
processing chain.
Depending on the FPGA and converter combinations that are being interfaced,
different components can be chosen for the physical and transport layer. The
FPGA defines which **physical** layer component should be used, meanwhile the
interfaced converter defines which **transport** layer component should be used.
The **link** layer component is selected based on the direction of the
JESD204B/C link.
The **application** layer is user-defined and can be used to implement
application-specific signal processing.
.. image:: jesd204_chain.svg
:align: center
.. _jesd204_physical_layer:
Physical Layer
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Physical layer peripherals are responsible for interfacing and configuring the
high-speed serial transceivers. Currently, we have support for GTXE2, GTHE3,
GTHE4, GTYE4 for AMD Xilinx and Arria 10 transceivers for Intel.
* :ref:`axi_adxcvr`: JESD204B Gigabit
Transceiver Register Configuration Peripheral
* :ref:`UTIL_ADXCVR <util_adxcvr>`: JESD204B Gigabit
Transceiver Interface Peripheral for AMD Xilinx FPGAs
Link Layer
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Link layer peripherals are responsible for JESD204B/C protocol handling,
including scrambling/descrambling, lane alignment, character replacement and
alignment monitoring.
* :ref:`JESD204B/C Transmit Peripheral <axi_jesd204_tx>`:
JESD204B/C Link Layer Transmit Peripheral
* :ref:`JESD204B/C Receive Peripheral <axi_jesd204_rx>`:
JESD204B/C Link Layer Receive Peripheral
.. _jesd204_transport_layer:
Transport Layer
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Transport layer peripherals are responsible for converter specific data framing
and de-framing.
* :ref:`ADC JESD204B/C Transport Peripheral <ad_ip_jesd204_tpl_adc>`:
JESD204B/C Transport Layer Receive Peripheral
* :ref:`DAC JESD204B/C Transport Peripheral <ad_ip_jesd204_tpl_dac>`:
JESD204B/C Transport Layer Transmit Peripheral
Interfaces
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Interfaces are a well-defined collection of wires that are used to communicate
between components. The following interfaces are used to connect components of
the HDL JESD204B/C processing stack.
.. _software_support_label:
Software Support
--------------------------------------------------------------------------------
Linux
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
- :dokuwiki:`JESD204 (FSM) Interface Linux Kernel Framework <resources/tools-software/linux-drivers/jesd204/jesd204-fsm-framework>`
- :dokuwiki:`JESD204B/C Transmit Linux Driver <resources/tools-software/linux-drivers/jesd204/axi_jesd204_tx>`:
Linux driver for the JESD204B transmit core.
- :dokuwiki:`JESD204B/C Receive Linux Driver <resources/tools-software/linux-drivers/jesd204/axi_jesd204_rx>`:
Linux driver for the JESD204B receive core.
- :dokuwiki:`JESD204B/C AXI_ADXCVR Highspeed Transceivers Linux Driver <resources/tools-software/linux-drivers/jesd204/axi_adxcvr>`
- :dokuwiki:`JESD204B Statistical Eyescan Application <resources/tools-software/linux-software/jesd_eye_scan>`
- :dokuwiki:`JESD204B Status Utility <resources/tools-software/linux-software/jesd_status>`
- :dokuwiki:`AXI DAC HDL Linux Driver <resources/tools-software/linux-drivers/iio-dds/axi-dac-dds-hdl>`
- :dokuwiki:`AD9172 DAC Linux Driver <resources/tools-software/linux-drivers/iio-dds/ad9172>`
- :dokuwiki:`AD9081 MxFE Linux Driver <resources/tools-software/linux-drivers/iio-mxfe/ad9081>`
- :dokuwiki:`ADRV9009, ADRV9008 highly integrated, wideband RF transceiver Linux device driver <resources/tools-software/linux-drivers/iio-transceiver/adrv9009>`
- :dokuwiki:`AD9371, AD9375 highly integrated, wideband RF transceiver Linux device driver <resources/tools-software/linux-drivers/iio-transceiver/ad9371>`
- :dokuwiki:`AXI ADC HDL Linux Driver <resources/tools-software/linux-drivers/iio-adc/axi-adc-hdl>`
- :dokuwiki:`AD9208 ADC Linux Driver <resources/tools-software/linux-drivers/iio-adc/ad9208>`
- :dokuwiki:`AD9081 MxFE Linux Driver <resources/tools-software/linux-drivers/iio-mxfe/ad9081>`
- :dokuwiki:`ADRV9009, ADRV9008 highly integrated, wideband RF transceiver Linux device driver <resources/tools-software/linux-drivers/iio-transceiver/adrv9009>`
- :dokuwiki:`AD9371, AD9375 highly integrated, wideband RF transceiver Linux device driver <resources/tools-software/linux-drivers/iio-transceiver/ad9371>`
No-OS
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
- :dokuwiki:`ADI JESD204B/C AXI_ADXCVR Highspeed Transceivers No-OS Driver <resources/tools-software/uc-drivers/jesd204/axi_adxcvr>`
- :dokuwiki:`ADI JESD204B/C Receive Peripheral No-OS Driver <resources/tools-software/uc-drivers/jesd204/axi_jesd204_rx>`
- :dokuwiki:`ADI JESD204B/C Transmit Peripheral No-OS Driver <resources/tools-software/uc-drivers/jesd204/axi_jesd204_tx>`
- :dokuwiki:`AXI ADC No-OS Driver <resources/tools-software/uc-drivers/jesd204/axi_adc_core>`
- :dokuwiki:`AXI DAC No-OS Driver <resources/tools-software/uc-drivers/jesd204/axi_dac_core>`
Tutorial
--------------------------------------------------------------------------------
#. :dokuwiki:`Introduction <resources/fpga/peripherals/jesd204/tutorial/introduction>`
#. :dokuwiki:`System Architecture <resources/fpga/peripherals/jesd204/tutorial/system_architecture>`
#. :dokuwiki:`Generic JESD204B block designs <resources/fpga/docs/hdl/generic_jesd_bds>`.
This will help you understand the generic blocks for the next steps.
#. Checkout the :ref:`HDL Source <build_hdl>`, and then build either one of:
#. :dokuwiki:`HDL AMD Xilinx <resources/fpga/peripherals/jesd204/tutorial/hdl_xilinx>`
#. :dokuwiki:`HDL Altera <resources/fpga/peripherals/jesd204/tutorial/hdl_altera>`
#. :dokuwiki:`Linux <resources/fpga/peripherals/jesd204/tutorial/linux>`
Example Projects
--------------------------------------------------------------------------------
- :dokuwiki:`AD-FMCADC2-EBZ Reference Design <resources/fpga/xilinx/fmc/ad-fmcadc2-ebz>`
- :git-hdl:`AMD Xilinx VC707 <projects/fmcadc2/vc707>`
- :git-hdl:`AMD Xilinx ZC706 <projects/fmcadc2/zc706>`
- :dokuwiki:`AD-FMCADC3-EBZ Reference Design <resources/fpga/xilinx/fmc/ad-fmcadc3-ebz>`
- :git-hdl:`AMD Xilinx VC707 <projects/fmcadc2/vc707>`
- :git-hdl:`AMD Xilinx ZC706 <projects/fmcadc2/zc706>`
- :dokuwiki:`AD-FMCADC4-EBZ Reference Design (RETIRED) <resources/fpga/xilinx/fmc/ad-fmcadc4-ebz>`
- :git-hdl:`AMD Xilinx ZC706 <hdl_2018_r2:projects/fmcadc4/zc706>`
- :dokuwiki:`AD-FMCJESDADC1-EBZ Reference Design <resources/fpga/xilinx/fmc/ad-fmcjesdadc1-ebz>`
- :git-hdl:`AMD Xilinx KC705 <projects/fmcjesdadc1/kc705>`
- :git-hdl:`AMD Xilinx VC707 <projects/fmcjesdadc1/vc707>`
- :git-hdl:`AMD Xilinx ZC706 <projects/fmcjesdadc1/zc706>`
- :dokuwiki:`AD-FMCOMMS8-EBZ Reference Design <resources/eval/user-guides/ad-fmcomms8-ebz/quick-start-guide>`
- :git-hdl:`Intel A10SOC <projects/fmcomms8/a10soc>`
- :git-hdl:`AMD Xilinx ZCU102 <projects/fmcomms8/zcu102>`
- :dokuwiki:`AD-FMCOMMS11-EBZ Reference Design <resources/eval/user-guides/ad-fmcomms11-ebz>`
- :git-hdl:`AMD Xilinx ZC706 <projects/fmcomms11/zc706>`
- :dokuwiki:`AD-FMCDAQ2-EBZ Reference Design <resources/eval/user-guides/ad-fmcdaq2-ebz>`
- :git-hdl:`Intel A10SOC <projects/daq2/a10soc>`
- :git-hdl:`Intel A10Gx (RETIRED) <hdl_2021_r1:projects/daq2/a10gx>`
- :git-hdl:`AMD Xilinx KC705 <projects/daq2/kc705>`
- :git-hdl:`AMD Xilinx KCU105 <projects/daq2/kcu105>`
- :git-hdl:`AMD Xilinx VC707 (RETIRED) <hdl_2018_r2:projects/daq2/vc707>`
- :git-hdl:`AMD Xilinx ZC706 <projects/daq2/zc706>`
- :git-hdl:`AMD Xilinx ZCU102 <projects/daq2/zcu102>`
- :dokuwiki:`AD-FMCDAQ3-EBZ Reference Design <resources/eval/user-guides/ad-fmcdaq3-ebz>`
- :git-hdl:`Intel A10Gx (RETIRED) <hdl_2021_r1:projects/daq3/a10gx>`
- :git-hdl:`AMD Xilinx KCU105 <projects/daq3/kcu105>`
- :git-hdl:`AMD Xilinx VCU118 <projects/daq3/vcu118>`
- :git-hdl:`AMD Xilinx ZC706 <projects/daq3/zc706>`
- :git-hdl:`AMD Xilinx ZCU102 <projects/daq3/zcu102>`
- :dokuwiki:`ADRV9371 Reference Design <resources/eval/user-guides/mykonos>`
- :git-hdl:`Intel A10SOC <projects/adrv9371x/a10soc>`
- :git-hdl:`Intel A10Gx (RETIRED) <hdl_2021_r1:projects/adrv9371x/a10gx>`
- :git-hdl:`AMD Xilinx KCU105 <projects/adrv9371x/kcu105>`
- :git-hdl:`AMD Xilinx ZC706 <projects/adrv9371x/zc706>`
- :git-hdl:`AMD Xilinx ZCU102 <projects/adrv9371x/zcu102>`
- :dokuwiki:`ADRV9009 Reference Design <resources/eval/user-guides/adrv9009>`
- :git-hdl:`AMD Xilinx ZCU102 <projects/adrv9009/zcu102>`
- :dokuwiki:`ADRV9009-ZU11EG-SOM Reference Design <resources/eval/user-guides/adrv9009-zu11eg>`
- :git-hdl:`Intel A10SOC <projects/adrv9009/a10soc>`
- :git-hdl:`Intel A10Gx (RETIRED) <hdl_2021_r1:projects/adrv9009/a10gx>`
- :git-hdl:`AMD Xilinx ZC706 <projects/adrv9009/zc706>`
- :git-hdl:`ADRV9009-ZU11EG-SOM <projects/adrv9009zu11eg>`
- :dokuwiki:`AD913x/AD917x/AD9144/AD915x/AD916X Reference Design <resources/eval/user-guides/ad-dac-fmc-ebz>`
- See the :git-hdl:`list of supported parts <projects/dac_fmc_ebz#readme>`
- :git-hdl:`Intel A10SOC <projects/dac_fmc_ebz/a10soc>`
- :git-hdl:`AMD Xilinx VCU118 <projects/dac_fmc_ebz/vcu118>`
- :git-hdl:`AMD Xilinx ZC706 <projects/dac_fmc_ebz/zc706>`
- :git-hdl:`AMD Xilinx ZCU102 <projects/dac_fmc_ebz/zcu102>`
- :ref:`AD9081-FMCA-EBZ Reference Design <ad9081_fmca_ebz>`
- :git-hdl:`Intel A10SOC <projects/ad9081_fmca_ebz/a10soc>`
- :git-hdl:`AMD Xilinx ZC706 <projects/ad9081_fmca_ebz/zc706>`
- :git-hdl:`AMD Xilinx ZCU102 <projects/ad9081_fmca_ebz/zcu102>`
- :git-hdl:`AMD Xilinx VCU118 <projects/ad9081_fmca_ebz/vcu118>`
- :git-hdl:`AMD Xilinx VCU128 <projects/ad9081_fmca_ebz/vcu128>`
- :git-hdl:`AMD Xilinx VCK190 <projects/ad9081_fmca_ebz/vck190>`
- :ref:`AD9082-FMCA-EBZ Reference Design <ad9081_fmca_ebz>`
- :git-hdl:`AMD Xilinx VCK190 <projects/ad9081_fmca_ebz/vck190>`
- :git-hdl:`AMD Xilinx VCU118 <projects/ad9081_fmca_ebz/vcu118>`
- :git-hdl:`AMD Xilinx ZC706 <projects/ad9081_fmca_ebz/zc706>`
- :git-hdl:`AMD Xilinx ZCU102 <projects/ad9081_fmca_ebz/zcu102>`
- :dokuwiki:`AD9081-FMCA-EBZ X-Band Phased Array Reference Design <resources/eval/user-guides/x-band-platform>`
- :git-hdl:`AMD Xilinx ZCU102 <projects/ad9081_fmca_ebz_x_band/zcu102>`
- :dokuwiki:`AD9213-DUAL-EBZ Reference Design <resources/eval/user-guides/ad9213_dual_ebz/ad9213_dual_ebz_hdl>`
- :git-hdl:`Intel S10SOC <projects/ad9213_dual_ebz/s10soc>`
- :dokuwiki:`AD9213-EBZ Reference Design <resources/eval/user-guides/ad9213_evb/ad9213_evb_hdl>`
- :git-hdl:`AMD Xilinx VCU118 <projects/ad9213_evb/vcu118>`
- :dokuwiki:`AD6676-EBZ Reference Design <resources/eval/user-guides/ad6676-ebz/software/baremetal>`
- :git-hdl:`AMD Xilinx VC707 <projects/ad6676evb/vc707>`
- :git-hdl:`AMD Xilinx ZC706 <projects/ad6676evb/zc706>`
- :dokuwiki:`AD9083-FMC <resources/eval/user-guides/ad9083/ad9083_evb_reference_hdl>`
- :git-hdl:`Intel A10SOC <projects/ad9083_evb/a10soc>`
- :git-hdl:`AMD Xilinx ZCU102 <projects/ad9083_evb/zcu102>`
- :dokuwiki:`AD9208-DUAL-EBZ reference design <resources/eval/user-guides/ad9208_dual_ebz/ad9208_dual_ebz_hdl>`
- :git-hdl:`AMD Xilinx VCU118 <projects/ad9208_dual_ebz/vcu118>`
- :dokuwiki:`AD9209-FMCA-EBZ reference design <resources/eval/user-guides/ad9209_fmca_ebz/ad9209_fmca_ebz>`
- :git-hdl:`AMD Xilinx VCK190 <projects/ad9209_fmca_ebz/vck190>`
- :dokuwiki:`AD9656 HDL Reference Design <resources/eval/user-guides/ad9656/reference_hdl>`
- :git-hdl:`AMD Xilinx ZCU102 <projects/ad9656_fmc/zcu102>`
- :dokuwiki:`AD9695-FMC reference design <resources/eval/user-guides/ad9695_fmc>`
- :git-hdl:`AMD Xilinx ZCU102 <projects/ad9695_fmc/zcu102>`
- :dokuwiki:`AD-QUADMXFE1-EBZ reference design <resources/eval/user-guides/ad_quadmxfe1_ebz/ad_quadmxfe1_ebz_hdl>`
- :git-hdl:`AMD Xilinx VCU118 <projects/ad_quadmxfe1_ebz/vcu118>`
- :dokuwiki:`AD-FMCLIDAR1-EBZ reference design <resources/eval/user-guides/ad-fmclidar1-ebz>`
- :git-hdl:`Intel A10SOC (RETIRED) <projects/ad_fmclidar1_ebz/a10soc>`
- :git-hdl:`AMD Xilinx ZC706 (RETIRED)<projects/ad_fmclidar1_ebz/zc706>`
- :git-hdl:`AMD Xilinx ZCU102 (RETIRED)<projects/ad_fmclidar1_ebz/zcu102>`
- :dokuwiki:`ADRV9026 reference design <resources/eval/user-guides/adrv9026/ad9026_hdl>`
- :git-hdl:`AMD Xilinx ZCU102 <projects/adrv9026/zcu102>`
Additional Information
--------------------------------------------------------------------------------
- :dokuwiki:`JESD204B Glossary <resources/fpga/peripherals/jesd204/jesd204_glossary>`
Technical Articles
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
- :adi:`JESD204B Survival Guide <media/en/technical-documentation/technical-articles/JESD204B-Survival-Guide.pdf>`
- :adi:`Synchronizing Sample Clocks of a Data Converter Array <en/resources/technical-articles/synchronizing-sample-clocks-of-a-data-converter-array>`
.. _rapid_prototyping_label:
JESD204B Rapid Prototyping Platforms
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
- :adi:`EVAL-ADRV9371 <en/resources/evaluation-hardware-and-software/evaluation-boards-kits/EVAL-ADRV9371>`
:dokuwiki:`(User Guide) <resources/eval/user-guides/mykonos>`
- :adi:`EVAL-ADRV9008-9009 <en/resources/evaluation-hardware-and-software/evaluation-boards-kits/EVAL-ADRV9008-9009>`
:dokuwiki:`(User Guide) <resources/eval/user-guides/adrv9009>`
- :dokuwiki:`ADRV9009-ZU11EG (User Guide) <resources/eval/user-guides/adrv9009-zu11eg>`
- :adi:`AD-FMCJESDADC1-EBZ <en/resources/evaluation-hardware-and-software/evaluation-boards-kits/eval-ad-fmcjesdadc1-ebz>`
- :adi:`AD-FMCOMMS11-EBZ <resources/evaluation-hardware-and-software/evaluation-boards-kits/AD-FMCOMMS11-EBZ>`
:dokuwiki:`(User Guide) <resources/eval/user-guides/ad-fmcomms11-ebz>`
- :adi:`AD-FMCADC2-EBZ <en/resources/evaluation-hardware-and-software/evaluation-boards-kits/AD-FMCADC2-EBZ>`
- :adi:`AD-FMCADC3-EBZ <en/resources/evaluation-hardware-and-software/evaluation-boards-kits/EVAL-AD-FMCADC3-EBZ>`
- :adi:`AD-FMCADC4-EBZ <en/resources/evaluation-hardware-and-software/evaluation-boards-kits/EVAL-AD-FMCADC4-EBZ>`\ (RETIRED)
- :adi:`AD-FMCDAQ2-EBZ <en/resources/evaluation-hardware-and-software/evaluation-boards-kits/AD-FMCDAQ2-EBZ>`
:dokuwiki:`(User Guide) <resources/eval/user-guides/ad-fmcdaq2-ebz>`
- :adi:`EVAL-FMCDAQ3-EBZ <en/resources/evaluation-hardware-and-software/evaluation-boards-kits/EVAL-FMCDAQ3-EBZ>`
:dokuwiki:`(User Guide) <resources/eval/user-guides/ad-fmcdaq3-ebz>`
- :adi:`EVAL-AD917X <en/resources/evaluation-hardware-and-software/evaluation-boards-kits/eval-ad9172>`
JESD204B Analog-to-Digital Converters
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
- :adi:`AD6673 <en/products/AD6673>`: 80 MHz Bandwidth, Dual IF Receiver
- :adi:`AD6674 <en/products/AD6674>`: 385 MHz BW IF Diversity Receiver
- :adi:`AD6676 <en/products/AD6676>`: Wideband IF Receiver Subsystem
- :adi:`AD6677 <en/products/AD6677>`: 80 MHz Bandwidth, IF Receiver
- :adi:`AD6684 <en/products/AD6684>`: 135 MHz Quad IF Receiver
- :adi:`AD6688 <en/products/AD6688>`: RF Diversity and 1.2GHz BW Observation
Receiver
- :adi:`AD9207 <en/products/AD9207>`: 12-Bit, 6 GSPS, JESD204B/JESD204C
Dual Analog-to-Digital Converter
- :adi:`AD9208 <en/products/AD9208>`: 14-Bit, 3GSPS, JESD204B,
Dual Analog-to-Digital Converter
- :adi:`AD9209 <en/products/AD9209>`: 12-Bit, 4GSPS, JESD204B/C, Quad
Analog-to-Digital Converter
- :adi:`AD9213 <en/products/AD9213>`: 12-Bit, 10.25 GSPS, JESD204B, RF
Analog-to-Digital Converter
- :adi:`AD9234 <en/products/AD9234>`: 12-Bit, 1 GSPS/500 MSPS JESD204B, Dual
Analog-to-Digital Converter
- :adi:`AD9250 <en/products/AD9250>`: 14-Bit, 170 MSPS/250 MSPS, JESD204B, Dual
Analog-to-Digital Converter
- :adi:`AD9625 <en/products/AD9625>`: 12-Bit, 2.6 GSPS/2.5 GSPS/2.0 GSPS,
1.3 V/2.5 V Analog-to-Digital Converter
- :adi:`AD9656 <en/products/AD9656>`: Quad, 16-Bit, 125 MSPS JESD204B 1.8 V
Analog-to-Digital Converter
- :adi:`AD9680 <en/products/AD9680>`: 14-Bit, 1.25 GSPS/1 GSPS/820 MSPS/500
MSPS JESD204B, Dual Analog-to-Digital Converter
- :adi:`AD9683 <en/products/AD9683>`: 14-Bit, 170 MSPS/250 MSPS, JESD204B,
Analog-to-Digital Converter
- :adi:`AD9690 <en/products/AD9690>`: 14-Bit, 500 MSPS / 1 GSPS JESD204B,
Analog-to-Digital Converter
- :adi:`AD9691 <en/products/AD9691>`: 14-Bit, 1.25 GSPS JESD204B,
Dual Analog-to-Digital Converter
- :adi:`AD9694 <en/products/AD9694>`: 14-Bit, 500 MSPS JESD204B, Quad
Analog-to-Digital Converter
- :adi:`AD9695 <en/products/AD9695>`: 14-Bit, 1300 MSPS/625 MSPS,
JESD204B, Dual Analog-to-Digital Converter Analog-to-Digital Converter
- :adi:`AD9083 <en/products/AD9083>`: 16-Channel, 125 MHz Bandwidth, JESD204B
Analog-to-Digital Converter
- :adi:`AD9094 <en/products/AD9094>`: 8-Bit, 1 GSPS, JESD204B, Quad
Analog-to-Digital Converter
JESD204B Digital-to-Analog Converters
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
- :adi:`AD9135 <en/products/AD9135>`: Dual, 11-Bit, high dynamic, 2.8 GSPS,
TxDAC+® Digital-to-Analog Converter
- :adi:`AD9136 <en/products/AD9136>`: Dual, 16-Bit, 2.8 GSPS, TxDAC+®
Digital-to-Analog Converter
- :adi:`AD9144 <en/products/AD9144>`: Quad, 16-Bit, 2.8 GSPS, TxDAC+®
Digital-to-Analog Converter
- :adi:`AD9152 <en/products/AD9152>`: Dual, 16-Bit, 2.25 GSPS, TxDAC+
Digital-to-Analog Converter
- :adi:`AD9154 <en/products/AD9154>`: Quad, 16-Bit, 2.4 GSPS, TxDAC+®
Digital-to-Analog Converter
- :adi:`AD9161 <en/products/AD9161>`: 11-Bit, 12 GSPS, RF Digital-to-Analog
Converter
- :adi:`AD9162 <en/products/AD9162>`: 16-Bit, 12 GSPS, RF Digital-to-Analog
Converter
- :adi:`AD9163 <en/products/AD9163>`: 16-Bit, 12 GSPS, RF DAC and Digital
Upconverter
- :adi:`AD9164 <AD9164>`: 16-Bit, 12 GSPS, RF DAC and Direct Digital
Synthesizer
- :adi:`AD9172 <en/products/AD9172>`: Dual, 16-Bit, 12.6 GSPS RF DAC with
Channelizers
- :adi:`AD9173 <en/products/AD9173>`: Dual, 16-Bit, 12.6 GSPS RF DAC with
Channelizers
- :adi:`AD9174 <en/products/AD9174>`: Dual, 16-Bit, 12.6 GSPS RF DAC and Direct
Digital Synthesizer
- :adi:`AD9175 <en/products/AD9175>`: Dual, 11-Bit/16-Bit, 12.6 GSPS RF DAC with
Wideband Channelizers
- :adi:`AD9176 <en/products/AD9176>`: Dual, 16-Bit, 12.6 GSPS RF DAC with
Wideband Channelizers
- :adi:`AD9177 <en/products/AD9177>`: Quad, 16-Bit, 12 GSPS RF DAC with
Wideband Channelizers
JESD204B RF Transceivers
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
- :adi:`AD9371 <en/products/AD9371>`: SDR Integrated, Dual RF Transceiver with
Observation Path
- :adi:`AD9375 <en/products/AD9375>`: SDR Integrated, Dual RF Transceiver with
Observation Path and DPD
- :adi:`ADRV9009 <en/products/ADRV9009>`: SDR Integrated, Dual RF Transceiver
with Observation Path
- :adi:`ADRV9008-1 <en/products/ADRV9008-1>`: SDR Integrated, Dual RF Receiver
- :adi:`ADRV9008-2 <en/products/ADRV9008-2>`: SDR Integrated, Dual RF
Transmitter with Observation Path
JESD204B/C Mixed-Signal Front Ends
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
- :adi:`AD9081 <en/products/AD9081>`: MxFE™ Quad, 16-Bit, 12GSPS RFDAC and
Quad, 12-Bit, 4GSPS RFADC
- :adi:`AD9082 <en/products/AD9082>`: MxFE™ QUAD, 16-Bit, 12GSPS RFDAC and
DUAL, 12-Bit, 6GSPS RFADC
- :adi:`AD9986 <en/products/AD9986>`: 4T2R Direct RF Transmitter and
Observation Receiver
- :adi:`AD9988 <en/products/AD9988>`: 4T4R Direct RF Receiver and Transmitter
JESD204B Clocking Solutions
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
- :adi:`AD9528 <en/products/AD9528>`: JESD204B Clock Generator with 14
LVDS/HSTL Outputs
- :adi:`HMC7043 <en/products/HMC7043>`: High Performance, 3.2 GHz, 14-Output
Fanout Buffer
- :adi:`HMC7044 <en/products/HMC7044>`: High Performance, 3.2 GHz, 14-Output
Jitter Attenuator with JESD204B
- :adi:`LTC6952 <en/products/LTC6952>`: Ultralow Jitter, 4.5GHz PLL,
JESD204B/JESD204C
- :adi:`ADF 4371 <en/products/ADF4371>`: Microwave Wideband Synthesizer
with Integrated VCO

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@ -54,15 +54,13 @@ Signal and Interface Pins
* - resetn
- Synchronous active-low reset.
Resets the internal state of the module.
* - s0_ctrl
* - s*_ctrl
- :ref:`spi_engine control-interface` slave.
Connects to the first control interface master.
* - s1_ctrl
- :ref:`spi_engine control-interface` slave.
Connects to the second control interface master.
| ``s0_ctrl`` connects to the first control interface master.
| ``s1_ctrl`` connects to the second control interface master.
* - m_ctrl
- :ref:`spi_engine control-interface` master.
Connects to the control interface slave.
- | :ref:`spi_engine control-interface` master.
| Connects to the control interface slave.
Theory of Operation
--------------------------------------------------------------------------------

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@ -0,0 +1,12 @@
.. _xilinx:
AMD Xilinx Specific IPs
================================================================================
Contents
--------
.. toctree::
:maxdepth: 2
UTIL_ADXCVR <util_adxcvr/index>

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.. _util_adxcvr:
UTIL_ADXCVR core for AMD Xilinx devices
================================================================================
.. hdl-component-diagram::
:path: library/xilinx/util_adxcvr
The
:git-hdl:`util_adxcvr <library/xilinx/util_adxcvr>`
IP core instantiates a Gigabit Transceiver (GT) and sets up the required
configuration. Basically, it is a simple wrapper file for a GT\* Column,
exposing just the necessary ports and attributes.
.. note::
To understand the below wiki page is important to have a basic
understanding about High Speed Serial I/O interfaces and Gigabit Serial
Transceivers. To find more information about these technologies, please visit
the :xilinx:`AMD Xilinx's solution center <support/answers/37181.html>`.
Currently this IP supports three different GT types:
- GTXE2
(:xilinx:`7 Series devices <support/documentation/user_guides/ug476_7Series_Transceivers.pdf>`)
- GTHE3
(:xilinx:`Ultrascale and Ultrascale+ <support/documentation/user_guides/ug576-ultrascale-gth-transceivers.pdf>`)
- GTHE4
(:xilinx:`Ultrascale and Ultrascale+ <support/documentation/user_guides/ug576-ultrascale-gth-transceivers.pdf>`)
- GTYE4
(:xilinx:`Ultrascale and Ultrascale+ <support/documentation/user_guides/ug578-ultrascale-gty-transceivers.pdf>`)
Features
--------------------------------------------------------------------------------
* Supports GTX2, GTH3 and GTH4
* Exposes all the necessary attributes for QPLL/CPLL configuration
* Supports shared transceiver mode
* Supports dynamic reconfiguration
* RX Eye Scan
Block Diagram
--------------------------------------------------------------------------------
The following diagram shows a GTXE2 Column, which contains four GT Quads. Each
quad contains a GTEX2_COMMON and four GTXE2_CHANNEL primitives.
.. image:: gtx_column.svg
:align: center
Configuration Parameters
--------------------------------------------------------------------------------
.. hdl-parameters::
* - XCVR_TYPE
- | Define the current GT type:
| GTXE2(0), GTHE3(1), GTHE4(2)
* - QPLL_REFCLK_DIV
- QPLL reference clock divider M, see User Guide for more info
* - QPLL_FBDIV_RATIO
- QPLL reference clock divider N ratio, see User Guide for more info
* - QPLL_CFG
- Configuration settings for QPLL, see User Guide for more info
* - QPLL_FBDIV
- QPLL reference clock divider N, see User Guide for more info
* - CPLL_FBDIV
- CPLL feedback divider N2 settings, see User Guide for more info
* - CPLL_FBDIV_4_5
- CPLL reference clock divider N1 settings, see User Guide for more info
* - TX_NUM_OF_LANES
- Number of transmit lanes.
* - TX_OUT_DIV
- CPLL/QPLL output clock divider D for the TX datapath, see User Guide for
more info
* - TX_CLK25_DIV
- Divider for internal 25 MHz clock for the TX datapath, see User Guide
for more info
* - TX_LANE_INVERT
- Per lane polarity inversion. Set the n-th bit to invert the polarity of
the n-th transmit lane.
* - RX_NUM_OF_LANES
- Number of transmit lanes
* - RX_OUT_DIV
- CPLL/QPLL output clock divider D for the RX datapath, see User Guide for
more info
* - RX_CLK25_DIV
- Divider for internal 25 MHz clock for the RX datapath, see User Guide
for more info
* - RX_DFE_LPM_CFG
- Configure the GT use modes, LPM or DFE, see User Guide for more info
* - RX_PMA_CFG
- Search for PMA_RSV in User Guide for more info
* - RX_CDR_CFG
- Configure the RX clock data recovery circuit for GTXE2, see User Guide
for more info
* - RX_LANE_INVERT
- Per lane polarity inversion. Set the n-th bit to invert the polarity of
the n-th receive lane.
Interface
--------------------------------------------------------------------------------
Microprocessor clock and reset
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
.. list-table::
:header-rows: 1
* - Pin
- Type
- Description
* - ``up_clk``
- ``input``
- System clock, running on 100 MHz
* - ``up_rstn``
- ``input``
- System reset, the same as AXI memory map slave interface reset
PLL reference clock
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
.. list-table::
:header-rows: 1
* - Pin
- Type
- Description
* - ``qpll_ref_clk_0``
- ``input``
- Reference clock for the QPLL
* - ``cpll_ref_clk_0``
- ``input``
- Reference clock for the CPLL
RX interface
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
.. list-table::
:header-rows: 1
* - Pin
- Type
- Description
* - ``rx_*_p``
- ``input``
- Positive differential serial data input
* - ``rx_*_n``
- ``input``
- Negative differential serial data input
* - ``rx_out_clk_*``
- ``output``
- Core logic clock output. Frequency = serial line rate/40
* - ``rx_clk_*``
- ``input``
- Core logic clock loop-back input
* - ``rx_charisk_*``
- ``output[3:0]``
- RX Char is K to the JESD204B IP
* - ``rx_disperr_*``
- ``output[3:0]``
- RX disparity error to the JESD204B IP
* - ``rx_notintable_*``
- ``output[3:0]``
- RX Not In Table to the JESD204B IP
* - ``rx_data_*``
- ``output[3:0]``
- RX data to the JESD204B IP
* - ``rx_calign_*``
- ``input``
- RX enable comma alignment from the JESD204B IP
TX interface
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
.. list-table::
:header-rows: 1
* - Pin
- Type
- Description
* - ``tx_*_p``
- ``output``
- Positive differential serial output
* - ``tx_*_n``
- ``output``
- Negative differential serial output
* - ``tx_out_clk_*``
- ``output``
- Core logic clock output. Frequency = serial line rate/40
* - ``tx_clk_*``
- ``input``
- Core logic clock loop-back input
* - ``tx_charisk_*``
- ``input[3:0]``
- TX Char is K from the JESD204B IP
* - ``tx_data_*``
- ``input[31:0]``
- TX data from the JESD204B IP
Common DRP Interface
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
.. list-table::
:header-rows: 1
* - Pin
- Type
- Description
* - ``up_cm_*``
- ``IO``
- The common DRP interface, must be connected to the equivalent DRP ports
of AXI_ADXCVR. This is a QUAD interface, shared by four transceiver
lanes. This interface is available only if parameter QPLL_ENABLE is set
to 0x1.
Channel DRP Interface
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
.. list-table::
:header-rows: 1
* - Pin
- Type
- Description
* - ``up_rx_*``
- ``IO``
- The RX channel DRP interface, must be connected to the equivalent DRP ports
of AXI_ADXCVR. This is a channel interface, one per each RX transceiver
lane.
* - ``up_tx_*``
- ``IO``
- The TX channel DRP interface, must be connected to the equivalent DRP ports
of AXI_ADXCVR. This is a channel interface, one per each TX transceiver
lane.
Eye Scan DRP Interface
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
.. list-table::
:header-rows: 1
* - Pin
- Type
- Description
* - ``up_es_*``
- ``IO``
- The Eye-Scan DRP interface, must be connected to the equivalent DRP
ports of UTIL_ADXCVR. This is a channel interface, one per each
transceiver lane. This interface is available only if parameter
TX_OR_RX_N is set to 0x0.
Design Guidelines
--------------------------------------------------------------------------------
.. note::
Please refer to :dokuwiki:`AMD Xilinx FPGAs Transceivers Wizard <resources/fpga/docs/xgt_wizard>`
to generate the optimal parameters needed to configure the transceivers for
your project.
Physical constraints considerations
--------------------------------------------------------------------------------
The util_adxcvr allocates resources/quads (channels and common) sequentially.
Meaning, if you have 8 lanes it will insert two quads, 4 channels and a common
block for each quad.
Channels within a quad are tightly coupled to the common block, the placement of
the channel resources can be permuted within a quad and is affected by the
constraint file with the restriction that rx\_<N>_p/n connect to tx\_<N>_p/n
must connect to the same channel.
Supposing we have the following pin constraints and connections to the
util_adxcvr:
.. image:: xcvr_mapping_example.svg
:align: center
So in this case we end up with a conflict during implementation:
.. image:: xcvr_conflict.svg
:align: center
We have to ensure that in implementation the mapping is correct either by
rearranging the Rx connections
.. image:: xcvr_rx_rearrangement.svg
:align: center
or by rearranging the Tx connections of the util_adxcvr:
.. image:: xcvr_tx_rearrangement.svg
:align: center
In such cases, when rearrangement is required due placement constraints,
complementary reordering is required either in the converter device (lane
crossbars) or inside the FPGA between the physical and link layer, to connect
the logical lanes with the same index on both end of the link.
Software Guidelines
--------------------------------------------------------------------------------
The software can configure this core through the :ref:`AXI_ADXCVR <axi_adxcvr>` IP
core.
References
--------------------------------------------------------------------------------
- :xilinx:`High Speed Serial <products/technology/high-speed-serial.html>`
- :xilinx:`7 Series FPGAs GTX/GTH Transceivers <support/documentation/user_guides/ug476_7Series_Transceivers.pdf>`
- :xilinx:`UltraScale Architecture GTH Transceivers <support/documentation/user_guides/ug576-ultrascale-gth-transceivers.pdf>`
- :xilinx:`UltraScale Architecture GTY Transceivers <support/documentation/user_guides/ug578-ultrascale-gty-transceivers.pdf>`
More Information
--------------------------------------------------------------------------------
- :ref:`JESD204B High-Speed Serial Interface Support <jesd204>`

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@ -1,5 +1,5 @@
TITLE
Xilinx XCVR (axi_xcvr) Regmap
Xilinx XCVR (axi_xcvr)
XCVR
ENDTITLE
@ -110,7 +110,7 @@ ENDFIELD
REG
0x0007
FPGA_INFO
FPGA device information [[https://github.com/analogdevicesinc/hdl/blob/main/library/scripts/adi_xilinx_device_info_enc.tcl |Xilinx encoded values]]
FPGA device information :git-hdl:`Xilinx encoded values <library/scripts/adi_xilinx_device_info_enc.tcl>`
ENDREG
FIELD
@ -168,14 +168,19 @@ FIELD
[5:4]
SYSCLK_SEL[1:0]
RW
For GTX drives directly the (RX/TX)SYSCLKSEL pin of the transceiver. Refer to Xilinx documentation. For GTH/GTY drives directly the (RX/TX)PLLCLKSEL pin of the transceiver and indirectly the (RX/TX)SYSCLKSEL pin of the transceiver see [[:resources:fpga:docs:axi_adxcvr#Table 1]].
For GTX drives directly the (RX/TX)SYSCLKSEL pin of the transceiver refer to
Xilinx documentation.
For GTH/GTY drives directly the (RX/TX)PLLCLKSEL pin of the transceiver and
indirectly the (RX/TX)SYSCLKSEL pin of the transceiver see
:ref:`Table 1 <axi_adxcvr table_one_label>`.
ENDFIELD
FIELD
[2:0]
OUTCLK_SEL[2:0]
RW
Transceiver primitive control [[:resources:fpga:docs:axi_adxcvr#Table 2]], refer Xilinx documentation.
Transceiver primitive control :ref:`Table 2 <axi_adxcvr table_two_label>`,
refer Xilinx documentation.
ENDFIELD
############################################################################################
@ -198,7 +203,7 @@ FIELD
[19:16]
XCVR_TYPE[3:0]
RO
[[https://github.com/analogdevicesinc/hdl/blob/main/library/scripts/adi_xilinx_device_info_enc.tcl | Xilinx encoded values.]]
:git-hdl:`Xilinx encoded values <library/scripts/adi_xilinx_device_info_enc.tcl>`.
ENDFIELD
FIELD
@ -649,5 +654,224 @@ RO
Ignore this bit for GTX transceivers. For others: Indicates that the RX PRBS checker has been error free for 15 XCLK cycles after reset. Once asserted High, it does not deassert until reset of the RX pattern checker via PRBSCNTRESET
ENDFIELD
############################################################################################
############################################################################################
TITLE
Intel XCVR (axi_xcvr)
INTEL_XCVR
ENDTITLE
############################################################################################
############################################################################################
REG
0x0000
REG_VERSION
Version Register
ENDREG
FIELD
[31:0]
VERSION[31:0]
RO
Version number.
ENDFIELD
############################################################################################
############################################################################################
REG
0x0001
REG_ID
Instance Identification Register
ENDREG
FIELD
[31:0]
ID[31:0]
RO
Instance identifier number.
ENDFIELD
############################################################################################
############################################################################################
REG
0x0002
REG_SCRATCH
Scratch (GP R/W) Register
ENDREG
FIELD
[31:0]
SCRATCH[31:0]
RW
Scratch register.
ENDFIELD
############################################################################################
############################################################################################
REG
0x0004
RESETN
Reset Control Register
ENDREG
FIELD
[0]
RESETN
RW
If clear, link is held in reset, set this bit to 0x1 to activate link. Note that the reference clock must be active before setting this bit.
ENDFIELD
############################################################################################
############################################################################################
REG
0x0005
REG_STATUS
Status Reporting Register
ENDREG
FIELD
[0]
STATUS
RO
After setting the RESETN bit above, wait for this bit to set. If set, indicates successful link activation.
ENDFIELD
############################################################################################
############################################################################################
REG
0x0006
REG_STATUS_32
Status Reporting Register
ENDREG
FIELD
[31:NUM_OF_LANES]
RESERVED
RO
0
ENDFIELD
FIELD
[NUM_OF_LANES]
UP_PLL_LOCKED
RO
After setting the RESETN bit above, wait for this bit be to set.
ENDFIELD
FIELD
[NUM_OF_LANES-1:0]
CHANNEL_N_READY
RO
After setting the RESETN bit above, wait for this registers to be set.
ENDFIELD
############################################################################################
############################################################################################
REG
0x0007
REG_FPGA_INFO
FPGA device information :git-hdl:`Intel Encoded Values <library/scripts/adi_intel_device_info_enc.tcl>`
ENDREG
FIELD
[31:24]
FPGA_TECHNOLOGY
RO
Encoded value describing the technology/generation of the FPGA device (e.g., cyclone V, arria 10, stratix 10)
ENDFIELD
FIELD
[23:16]
FPGA_FAMILY
RO
Encoded value describing the family variant of the FPGA device(e.g., SX, GX, GT or zynq, kintex, virtex)
ENDFIELD
FIELD
[15:8]
SPEED_GRADE
RO
Encoded value describing the FPGA's speed-grade
ENDFIELD
FIELD
[7:0]
DEV_PACKAGE
RO
Encoded value describing the device package. The package might affect high-speed interfaces
ENDFIELD
############################################################################################
############################################################################################
REG
0x0009
REG_GENERIC_INFO
Physical layer info
ENDREG
FIELD
[31:28]
RESERVED
RO
0
ENDFIELD
FIELD
[27:24]
XCVR_TYPE[3:0]
RO
Refers to the transceiver speed grade 0-9.
ENDFIELD
FIELD
[23:12]
RESERVED
RO
0
ENDFIELD
FIELD
[11:9]
RESERVED
RO
0
ENDFIELD
FIELD
[8]
TX_OR_RX_N
RO
Transceiver type (transmit or receive)
ENDFIELD
FIELD
[7:0]
NUM_OF_LANES
RO
Physical layer number of lanes.
ENDFIELD
############################################################################################
############################################################################################
REG
0x0050
REG_FPGA_VOLTAGE
FPGA device voltage information
ENDREG
FIELD
[15:0]
FPGA_VOLTAGE
RO
The voltage of the FPGA device in mv
ENDFIELD