From 075378fb924f1db6986a6ef938313abbe74eb6b4 Mon Sep 17 00:00:00 2001 From: caosjr Date: Wed, 27 Mar 2024 09:33:20 -0300 Subject: [PATCH] docs: Add JESD204 documentation (#1280) docs: Add JESD204 documentation in sphinx Fixes several semantic issues from the original doc in wiki Implicit path to library when the doc is hierarchically coherent with the library. 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+:ref:`UTIL_ADXCVR `. + +Features +-------------------------------------------------------------------------------- + +- Supports :git-hdl:`Intel ` + and :git-hdl:`AMD Xilinx ` devices. +- Software can access the core's registers through an AXI4 Lite Memory Mapped + interface. +- Link reset and monitor for Intel and AMD Xilinx. +- Reconfiguration interface control with broadcast capability for AMD Xilinx. +- Access to the Statistical eye scan interface of the PHY (AMD Xilinx). +- Supports up to 16 transceiver lanes per link (AMD Xilinx). + +Intel Devices +-------------------------------------------------------------------------------- + +For Intel devices, the adi_jesd204 IP is using the axi_adxcvr core, which can be +accessed by the **link_management** interface. It provides a global reset signal +for the JESD204B framework. Resets the XCVR reset controller IP, the link PLL +reset controller, the PHY itself, and also the link layer of the stack. Besides +the reset generation, monitors the PLLs and the PHY state. + +Parameters +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. hdl-parameters:: + :path: library/xilinx/axi_adxcvr + + * - ID + - Instance identification number, if more than one instance is used. + * - NUM_OF_LANES + - The number of lanes (primitives) used in this link. + * - XCVR_TYPE + - Refers to the transceiver speed grade 0-9. + * - FPGA_TECHNOLOGY + - Encoded value describing the technology/generation of the FPGA device + (e.g. Cyclone V, Arria 10, Stratix 10). + * - FPGA_FAMILY + - Encoded value describing the family variant of the FPGA device + (e.g. SX, GX, GT). + * - SPEED_GRADE + - Encoded value describing the FPGA’s speed-grade. + * - DEV_PACKAGE + - Encoded value describing the device package. The package might affect + high-speed interfaces. + * - FPGA_VOLTAGE + - Contains the value(0-5000 mV) at wich the FPGA device supplied. + * - TX_OR_RX_N + - If set (0x1), configures the link in transmit mode, otherwise receive. + +Interfaces +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. hdl-interfaces:: + :path: library/xilinx/axi_adxcvr + + * - s_axi_aclk + - System clock. (in general 100 MHz) + * - s_axi_aresetn + - System reset. + * - s_axi + - Slave AXI4 Lite Memory Mapped interface + * - up_ch_* + - | Connect logical port ``pll_locked`` to the fPLL’s **pll_locked** pin; + | Connect logical port ``ready`` to PHY reset controller. + +Register Map +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. hdl-regmap:: + :name: INTEL_XCVR + :no-type-info: + +Software Guidelines +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +When the board powers up, both ATX and fPLL's must have a stable reference clock +in order to lock automatically. If this requirement can not be respected by the +system (e.g. the reference clocks are generated by a device that requires +software configuration, through an interface implemented in FPGA), the software +needs to reconfigure both PLLs, and just after that resets the transceivers. + +AMD Xilinx Devices +-------------------------------------------------------------------------------- + +In AMD Xilinx Devices, the core configures itself to be interfaced with the GT +variant supported by the UTIL_ADXCVR core. All the transceiver primitives are +configured and programmed identically. + +.. _parameters-1: + +Parameters +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. hdl-parameters:: + :path: library/xilinx/axi_adxcvr + + * - ID + - Instance identification number, if more than one instance is used + * - NUM_OF_LANES + - The number of lanes (primitives) used in this link + * - XCVR_TYPE + - Define the current GT type, GTXE2(2), GTHE3(5), GTHE4(7) + * - FPGA_TECHNOLOGY + - Encoded value describing the technology/generation of the FPGA device + (7series/ultrascale) + * - FPGA_FAMILY + - Encoded value describing the family variant of the FPGA device(e.g., + zynq, kintex, virtex) + * - SPEED_GRADE + - Encoded value describing the FPGA's speed-grade + * - DEV_PACKAGE + - Encoded value describing the device package. The package might affect + high-speed interfaces + * - FPGA_VOLTAGE + - Contains the value(0-5000 mV) at wich the FPGA device supplied + * - TX_OR_RX_N + - If set (0x1), configures the link in transmit mode, otherwise receive + * - QPLL_ENABLE + - If set (0x1), configures the link to use QPLL on QUAD basis. If multiple + links are sharing the same transceiver, only one of them may enable the + QPLL. + * - LPM_OR_DFE_N + - Chosing between LPM or DFE of modes for the RX Equalizer + * - RATE + - Defines the initial values for Transceiver Control Register (REG_CONTROL + 0x0008) + * - TX_DIFFCTRL + - Driver Swing Control(TX Configurable Driver) + * - TX_POSTCURSOR + - Transmitter post-cursor TX pre-emphasis control + * - TX_PRECURSOR + - Transmitter pre-cursor TX pre-emphasis control + * - SYS_CLK_SEL + - Selects the PLL reference clock source to drive the RXOUTCLK + :ref:`Table 1 ` + * - OUT_CLK_SEL + - select the transceiver reference clock as the source of TXOUTCLK + :ref:`Table 2 ` + +Interfaces +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. hdl-interfaces:: + :path: library/xilinx/axi_adxcvr + +.. _register-map-1: + +Register Map +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. hdl-regmap:: + :name: XCVR + :no-type-info: + +.. _software-guidelines-1: + +Software Guidelines +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +The system must have active DRP and reference clocks before any software access. +The software is expected to write necessary control parameters to LPM_DFE_N, +RATE, SYSCLK_SEL, OUTCLK_SEL register bits and then set RESETN bit to 0x1. +After that, monitor the STATUS bit to be set. There are no other requirements +for initialization. + +The DRP access is identical for common and channel interfaces. The SEL bits may +be set to a specific transceiver lane or 0xff to broadcast. A write to the +CONTROL register (bits WR, ADDR, WDATA) initiates DRP access in hardware. A read +to this register has no effect. In order to write to the transceiver, set WR to +0x1 with the address. In order to read from the transceiver, set WR to 0x0 with +the address. As soon as this register is written, the BUSY signal is set and is +cleared only after the access is complete. The broadcast read is a logical OR of +all the channels. After an access is started, do NOT interrupt the core for any +reason (including setting RESETN to 0x0), allow the access to finish itself. +Though the core itself is immune to a software abort, the transceiver may fail +on further accesses and may require a system-wide reset. + +The eye-scan feature also allows a SEL option and a broadcast has the effect of +a combined mask. That is, the error counter will be zero ONLY if all the +transceiver error counters are zero. To start eye-scan, set ES_REQ to 0x1 and +wait for the same bit to self-clear. If eye-scan needs to be stopped, set the +ES_REQ bit to 0x0. + +.. _axi_adxcvr table_one_label: + +Table 1 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +.. list-table:: + :header-rows: 1 + + * - SYSCLK_SEL + - 00 + - 01 + - 10 + - 11 + * - GTXE2 + - CPLL + - RESERVED + - RESERVED + - QPLL + * - GTHE3 + - CPLL + - RESERVED + - QPLL1 + - QPLL0 + * - GTHE4 + - CPLL + - RESERVED + - QPLL1 + - QPLL0 + * - GTYE4 + - CPLL + - RESERVED + - QPLL1 + - QPLL0 + +.. _axi_adxcvr table_two_label: + +Table 2 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +.. list-table:: + :header-rows: 1 + + * - OUTCLK_SEL + - 001 + - 010 + - 011 + - 100 + - 101 + - All other combinations + * - GTXE2 + - OUTCLKPCS + - OUTCLKPMA + - REFCLK + - REFCLK/2 + - RESERVED + - RESERVED + * - GTHE3 + - OUTCLKPCS + - OUTCLKPMA + - REFCLK + - REFCLK/2 + - PROGDIVCLK + - RESERVED + * - GTHE4 + - OUTCLKPCS + - OUTCLKPMA + - REFCLK + - REFCLK/2 + - PROGDIVCLK + - RESERVED + * - GTYE4 + - OUTCLKPCS + - OUTCLKPMA + - REFCLK + - REFCLK/2 + - PROGDIVCLK + - RESERVED + +The REFCLK selected by OUTCLK_SEL depends on the SYSCLK_SEL, it may be CPLL, +QPLL0 or QPLL1 refclk. + +Physical layer PRBS testing +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +The REG_PRBS_CNTRL and REG_PRBS_STATUS registers expose controls of internal +PRBS generators and checkers allowing the testing the multi-gigabit serial link +at the physical layer without the need of the link layer bringup. + +TX link procedure +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +#. Configure the reference clock and device clocks for under test lane rate. + Bring XCVR out from reset. +#. In the REG_PRBS_CNTRL registers set PRBSSEL to a non-zero value. See the + transceiver guides for exact values, different transceiver families may have + different encoding for the same pattern. +#. On the receiving side of the link, set the checker for the same pattern and + reset the error counters. +#. No error should be recorded on the receiver side. +#. Set the PRBSFORCEERR bit in the REG_PRBS_CNTRL register to force the error + injection into the stream of bits. +#. The error should be detected and recorded on the receiver side. + +RX link procedure +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +#. Configure the reference clock and device clocks for under test lane rate. + Bring XCVR out from reset. +#. On the transmit side of the link, set a test pattern that is available in the + receiving transceiver. Consult the transceiver documentation for details. +#. In the REG_PRBS_CNTRL registers set PRBSSEL to the corresponding pattern. + Reset the error counters with PRBSCNTRESET. +#. Check REG_PRBS_STATUS fields for results. If the check is successful for + non-GTX transceivers the PRBSLOCKED bit must appear as set and PRBSERR must + stay low. For GTX transceivers the PRBSLOCKED bit can be ignored and checking + the PRBSERR alone is sufficient. If PRBSERR is set, check with DRP accesses + the internal error counter to get the number of errors received. See the + transceiver guide for details. + +More Information +-------------------------------------------------------------------------------- + +- :ref:`jesd204` +- :dokuwiki:`JESD204B/C AXI_ADXCVR Highspeed Transceivers Linux Driver ` + +Reference +-------------------------------------------------------------------------------- + +- :intel:`Intel® Arria® 10 Transceiver PHY User Guide ` +- `7 Series FPGAs GTX/GTH Transceivers User Guide - AMD Xilinx `_ +- `Ultrascale Architecture GTH Transceivers User Guide - AMD Xilinx `_ diff --git a/docs/library/index.rst b/docs/library/index.rst index f33b30d0a..bb7060ef8 100644 --- a/docs/library/index.rst +++ b/docs/library/index.rst @@ -16,3 +16,6 @@ Contents axi_dmac/index spi_engine/index + jesd204/index + axi_adxcvr/index + xilinx/index diff --git a/docs/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_transport_adc.svg b/docs/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_transport_adc.svg new file mode 100644 index 000000000..31f0568ee --- /dev/null +++ b/docs/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_transport_adc.svg @@ -0,0 +1,1159 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Channel N + + + + + Channel 2 + + + + + REGISTERMAP + + + S_AXI + + + JESD204DEFRAMER + + + + + + Channel 1 + + + + PRBSCHECKER + + + + + + + + + + s_axi_aclk + + + + + FORMATCONVERSION + + + + Status + Conf. + + + DMAInterface + JESD204Link LayerInterface + + + + + + + + + + + device_clk + + + CONTROL + + + + + ... + enable_0 + enable_1 + enable_N + + + + + + + Conf. + + + + + + Conf. + Conf. + + + CLOCKMONITOR + + + + diff --git a/docs/library/jesd204/ad_ip_jesd204_tpl_adc/index.rst b/docs/library/jesd204/ad_ip_jesd204_tpl_adc/index.rst new file mode 100644 index 000000000..c4390ae2b --- /dev/null +++ b/docs/library/jesd204/ad_ip_jesd204_tpl_adc/index.rst @@ -0,0 +1,348 @@ +.. _ad_ip_jesd204_tpl_adc: + +ADC JESD204B/C Transport Peripheral +================================================================================ + +.. hdl-component-diagram:: + +The ADC JESD204B/C Transport Peripheral implements the transport level handling +of a JESD204B/C transmitter device. It is compatible with a +:ref:`wide range of Analog Devices high-speed analog-to-digital converters `. + +The core handles the JESD204B/C deframing of the payload data. + +The peripheral can be configured at runtime through a AXI4-Lite memory mapped +register map. + +Features +-------------------------------------------------------------------------------- + +- ADI high-speed ADC compatible JESD204B/C data deframing; +- Test-pattern checker; +- Per-channel data formatting (sign extension, two's complement to offset + binary); +- Runtime reconfigurability through memory-mapped register interface + (AXI4-Lite). + +Files +-------------------------------------------------------------------------------- + +:git-hdl:`ad_ip_jesd204_tpl_adc.v ` + +Block Diagram +------------- + +.. image:: ad_ip_jesd204_transport_adc.svg + :align: center + +Synthesis Configuration Parameters +-------------------------------------------------------------------------------- + +.. hdl-parameters:: + + * - ID + - Instance identification number. + * - NUM_LANES + - Number of lanes supported by the peripheral. + Equivalent to JESD204 ``L`` parameter. + * - NUM_CHANNELS + - Number of converters supported by the peripheral. + Equivalent to JESD204 ``M`` parameter. + * - SAMPLES_PER_FRAME + - Number of samples per frame. + Equivalent to JESD204 ``S`` parameter. + * - CONVERTER_RESOLUTION + - Resolution of the converter. + Equivalent to JESD204 ``N`` parameter. + * - BITS_PER_SAMPLE + - Number of bits per sample. + Equivalent to JESD204 ``NP`` parameter. + * - OCTETS_PER_BEAT + - Number of bytes per beat for each link. + * - TWOS_COMPLEMENT + - PRBS data format. + * - PN7_ENABLE + - Enable PN7 check. + * - PN15_ENABLE + - Enable PN15 check. + +.. *- PN31_ENABLE +.. - Enable PN31 check. + +Signal and Interface Pins +-------------------------------------------------------------------------------- + +.. hdl-interfaces:: + + * - s_axi_aclk + - All ``S_AXI`` signals are synchronous to this clock. + * - s_axi_aresetn + - Resets the internal state of the peripheral. + * - s_axi + - Memory mapped AXI-lite bus that provides access to modules register map. + * - link + - link_data: JESD204 link data interface (link layer interface). + * - link_clk + - :dokuwiki:`Device clock ` + for the JESD204B interface of the Link Layer Interface. Must + be line clock/40 for correct 204B operation. Must be line + clock/66 for correct 64b66b 204C operation. + * - enable + - Channel enable indicator of the Application layer Interface + * - adc_valid + - Qualifier signal for each channel of the Application layer + interface. Always '1'. + * - adc_data + - Raw application layer data, every channel concatenated + (Application layer interface). + * - adc_dovf + - Application layer overflow of the Application layer interface. + +The S_AXI interface is synchronous to the s_axi_aclk clock. All other signals +and interfaces are synchronous to the device_clk clock. + +Register Map +-------------------------------------------------------------------------------- + +.. hdl-regmap:: + :name: COMMON + :no-type-info: + +.. hdl-regmap:: + :name: ADC_COMMON + :no-type-info: + +.. hdl-regmap:: + :name: JESD_TPL + :no-type-info: + +.. hdl-regmap:: + :name: ADC_CHANNEL + :no-type-info: + +Theory of Operation +-------------------------------------------------------------------------------- + +Interfaces and Signals +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Configuration Interface +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +The Peripheral features a register map configuration interface that can be +accessed through the AXI4-Lite ``S_AXI`` port. The register map can be used to +configure the Peripheral's operational parameters, query the current status of +the device and query the features supported by the device. + +Link layer interface +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +The link layer interface description can be found in the +:ref:`User Data Interface ` section of the +:ref:`JESD204B/C Link Receive Peripheral ` IP. + +Application layer interface +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +The application layer is connected to the deframer block output. The deframer +module creates sample data from the lane mapped and formatted JESD204 link data +based on the specified deframer configuration. + +The data in the application layer interface ``adc_data`` has the following +layout: + +:: + + MSB LSB + [ MmSn, ..., MmS1, MnS0, ..., M1Sn, ... M1S1, M1S0, M0Sn, ... M0S1, M0S0 ] + +Where MjSi refers to the i-th sample of the j-th converter. With m being the +number of converters and n the number of samples per converter per beat. + +The core asserts the ``enable`` signal for each channel that is enabled by the +software. + +Clock Monitor +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +The ``REG_STATUS`` (``0x054``) register ``CLK_FREQ`` field allows to determine +the clock rate of the device clock (``link_clk``) relative to the AXI interface +clock (``s_axi_aclk``). This can be used to verify that the device clock is +running at the expected rate. + +The number is represented as unsigned 16.16 format. Assuming a 100MHz processor +clock, this corresponds to a resolution of 1.523kHz per LSB. A raw value of 0 +indicates that the link clock is currently not active. + +Data Formatter +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +The component is configured by the ``REG_CHAN_CNTRL`` register +``FORMAT_SIGNEXT,FORMAT_TYPE,FORMAT_ENABLE`` fields. The block introduces one +clock cycle latency. + +PRBS Check +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +The block can monitor and compare the incoming deframed raw data against +PN9, PN23 and PN7, PN15 (if enabled) patterns selected by the ``ADC_PN_SEL`` +field of ``REG_CHAN_CNTRL_3`` register. + +.. + it is missing PN31, because it does not exist on the source code + +.. list-table:: + :header-rows: 1 + + * - ADC_PN_SEL + - PN + - ENABLE + * - 0 + - PN9 + - 1 + * - 1 + - PN23 + - 1 + * - 4 + - PN7 + - PN7_ENABLE + * - 5 + - PN15 + - PN15_ENABLE + +.. *-7 +.. -PN31 +.. -PN31_ENABLE + +Before performing these tests you need to make sure that the ADC OUTPUT FORMAT +is set according to the ``TWOS_COMPLEMENT`` synthesis parameter. + +For each channel, mismatches are reported in ``PN_ERR`` and ``PN_OOS`` fields of +the ``REG_CHAN_STATUS`` register. + +External synchronization +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +An external synchronization signal ``adc_sync_in`` can be used to trigger data +movement from the link layer to user application layer. + +The external synchronization signal should be synchronous with the ADC clock. +Synchronization will be done on the rising edge of the signal. + +The self clearing ``SYNC`` control bit from the ``REG_CNTRL (0x44)`` register, +will arm the trigger logic to wait for the external sync signal. The +``ADC_SYNC`` status bit from ``REG_SYNC_STATUS (0x68)`` register, will show that +the synchronization is armed, but the synchronization signal has not yet been +received. + +Once the sync signal is received, the data will start to flow and the +``ADC_SYNC`` status bit will reflect that with a deassertion. + +While the synchronization mechanism is armed, the ``adc_rst`` output signal is +set such that downstream logic can be cleared, to have a fresh start once the +trigger is received. + +Software Support +-------------------------------------------------------------------------------- + +.. warning:: + To ensure correct operation, it is highly recommended to use the + Analog Devices provided JESD204B/C software packages for interfacing the + peripheral. Analog Devices is not able to provide support in case issues arise + from using custom low-level software for interfacing the peripheral. + +Restrictions +-------------------------------------------------------------------------------- + +Reduced number of octets-per-frame (``F``) settings. The following values are +supported by the peripheral: 1, 2, 4 + +- Starting from + `this `__ + commit this restriction no longer applies. + +.. _ad_ip_jesd204_tpl_adc_supported_devices: + +Supported Devices +-------------------------------------------------------------------------------- + +JESD204B Analog-to-Digital Converters +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- :adi:`AD6673 `: 80 MHz Bandwidth, Dual IF Receiver +- :adi:`AD6674 `: 385 MHz BW IF Diversity Receiver +- :adi:`AD6676 `: Wideband IF Receiver Subsystem +- :adi:`AD6677 `: 80 MHz Bandwidth, IF Receiver +- :adi:`AD6684 `: 135 MHz Quad IF Receiver +- :adi:`AD6688 `: RF Diversity and 1.2GHz BW Observation + Receiver +- :adi:`AD9207 `: 12-Bit, 6 GSPS, JESD204B/JESD204C + Dual Analog-to-Digital Converter +- :adi:`AD9208 `: 14-Bit, 3GSPS, JESD204B, + Dual Analog-to-Digital Converter +- :adi:`AD9209 `: 12-Bit, 4GSPS, JESD204B/C, Quad + Analog-to-Digital Converter +- :adi:`AD9213 `: 12-Bit, 10.25 GSPS, JESD204B, RF + Analog-to-Digital Converter +- :adi:`AD9234 `: 12-Bit, 1 GSPS/500 MSPS JESD204B, Dual + Analog-to-Digital Converter +- :adi:`AD9250 `: 14-Bit, 170 MSPS/250 MSPS, JESD204B, Dual + Analog-to-Digital Converter +- :adi:`AD9625 `: 12-Bit, 2.6 GSPS/2.5 GSPS/2.0 GSPS, + 1.3 V/2.5 V Analog-to-Digital Converter +- :adi:`AD9656 `: Quad, 16-Bit, 125 MSPS JESD204B 1.8 V + Analog-to-Digital Converter +- :adi:`AD9680 `: 14-Bit, 1.25 GSPS/1 GSPS/820 MSPS/500 + MSPS JESD204B, Dual Analog-to-Digital Converter +- :adi:`AD9683 `: 14-Bit, 170 MSPS/250 MSPS, JESD204B, + Analog-to-Digital Converter +- :adi:`AD9690 `: 14-Bit, 500 MSPS / 1 GSPS JESD204B, + Analog-to-Digital Converter +- :adi:`AD9691 `: 14-Bit, 1.25 GSPS JESD204B, + Dual Analog-to-Digital Converter +- :adi:`AD9694 `: 14-Bit, 500 MSPS JESD204B, Quad + Analog-to-Digital Converter +- :adi:`AD9695 `: 14-Bit, 1300 MSPS/625 MSPS, + JESD204B, Dual Analog-to-Digital Converter Analog-to-Digital Converter +- :adi:`AD9083 `: 16-Channel, 125 MHz Bandwidth, JESD204B + Analog-to-Digital Converter +- :adi:`AD9094 `: 8-Bit, 1 GSPS, JESD204B, Quad + Analog-to-Digital Converter + +JESD204B RF Transceivers +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- :adi:`AD9371 `: SDR Integrated, Dual RF Transceiver with + Observation Path +- :adi:`AD9375 `: SDR Integrated, Dual RF Transceiver with + Observation Path and DPD +- :adi:`ADRV9009 `: SDR Integrated, Dual RF Transceiver + with Observation Path +- :adi:`ADRV9008-1 `: SDR Integrated, Dual RF Receiver +- :adi:`ADRV9008-2 `: SDR Integrated, Dual RF + Transmitter with Observation Path + +JESD204B/C Mixed-Signal Front Ends +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- :adi:`AD9081 `: MxFE™ Quad, 16-Bit, 12GSPS RFDAC and + Quad, 12-Bit, 4GSPS RFADC +- :adi:`AD9082 `: MxFE™ QUAD, 16-Bit, 12GSPS RFDAC and + DUAL, 12-Bit, 6GSPS RFADC +- :adi:`AD9986 `: 4T2R Direct RF Transmitter and + Observation Receiver +- :adi:`AD9988 `: 4T4R Direct RF Receiver and Transmitter + +More Information +-------------------------------------------------------------------------------- + +- :ref:`JESD204 Interface Framework ` +- :dokuwiki:`Glossary of terms ` +- :ref:`HDL User Guide ` + +Technical Support +-------------------------------------------------------------------------------- + +Analog Devices will provide limited online support for anyone using the core +with Analog Devices components (ADC, DAC, Video, Audio, etc) via the +:ez:`EngineerZone `. diff --git a/docs/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_transport_dac.svg b/docs/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_transport_dac.svg new file mode 100644 index 000000000..f8fc20f2c --- /dev/null +++ b/docs/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_transport_dac.svg @@ -0,0 +1,1571 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + image/svg+xml + + + + + + + + + + Channel N + + + + + Channel 2 + + + + + REGISTERMAP + + + S_AXI + + + JESD204FRAMER + + + + + + Channel 1 + + + + PATTERNGENERATOR + + + + + + + + + + s_axi_aclk + + + + + + DUAL TONEDDS + + + Status + Conf. + + + DMAInterface + JESD204Link LayerInterface + + + + + + + device_clk + + + CONTROL + + + + + ... + enable_0 + enable_1 + enable_N + + + + + + + Conf. + + + + + + Conf. + Conf. + + + CLOCKMONITOR + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/docs/library/jesd204/ad_ip_jesd204_tpl_dac/index.rst b/docs/library/jesd204/ad_ip_jesd204_tpl_dac/index.rst new file mode 100644 index 000000000..f522fd610 --- /dev/null +++ b/docs/library/jesd204/ad_ip_jesd204_tpl_dac/index.rst @@ -0,0 +1,300 @@ +.. _ad_ip_jesd204_tpl_dac: + +DAC JESD204B/C Transport Peripheral +================================================================================ + +.. hdl-component-diagram:: + +The DAC JESD204B/C Transport Peripheral (AD-IP-JESD204-TRANSPORT-DAC) implements +the transport level handling of a JESD204B/C transmitter device. It is +compatible with a +:ref:`wide range of Analog Devices high-speed digital-to-analog converters `. + +The core handles the JESD204B/C framing of the user-provided payload data. In +addition, it is capable of generating standard and user-defined test-pattern +data for interface verification. It also features a per-channel dual-tone DDS +that can be used to dynamically generate test-tones. + +The peripheral can be configured at runtime through a AXI4-Lite memory mapped +register map. + +Features +-------------------------------------------------------------------------------- + +- ADI high-speed DAC compatible JESD204B/C data framing; +- Test-pattern generator for interface verification; +- Per-channel dual-tone DDS (optional); +- Runtime reconfigurability through memory-mapped register interface + (AXI4-Lite). + +Files +-------------------------------------------------------------------------------- + +:git-hdl:`ad_ip_jesd204_tpl_dac.v ` + +Block Diagram +-------------------------------------------------------------------------------- + +.. image:: ad_ip_jesd204_transport_dac.svg + :align: center + +Synthesis Configuration Parameters +-------------------------------------------------------------------------------- + +.. hdl-parameters:: + + * - ID + - Instance identification number. + * - NUM_LANES + - Number of lanes supported by the peripheral. + Equivalent to JESD204 ``L`` parameter. + * - NUM_CHANNELS + - Number of converters supported by the peripheral. + - Equivalent to JESD204 ``M`` parameter. + * - SAMPLES_PER_FRAME + - Number of samples per frame. + Equivalent to JESD204 ``S`` parameter. + * - CONVERTER_RESOLUTION + - Resolution of the converter. + Equivalent to JESD204 ``N`` parameter. + * - BITS_PER_SAMPLE + - Number of bits per sample. + Equivalent to JESD204 ``NP`` parameter. + * - OCTETS_PER_BEAT + - Number of bytes per beat for each link. + * - DDS_TYPE + - DDS Type. Set 1 for CORDIC or 2 for Polynomial + * - DDS_CORDIC_DW + - CORDIC DDS Data Width. + * - DDS_CORDIC_PHASE_DW + - CORDIC DDS Phase Width. + * - DATAPATH_DISABLE + - Disable instantiation of DDS core. + +Signal and Interface Pins +-------------------------------------------------------------------------------- + +.. hdl-interfaces:: + + * - s_axi_aclk + - All ``S_AXI`` signals and ``irq`` are synchronous to this clock. + * - s_axi_aresetn + - Resets the internal state of the peripheral. + * - s_axi + - Memory mapped AXI-lite bus that provides access to modules register map. + * - link + - link_data: Framed transmit data towards link layer. + * - link_clk + - :dokuwiki:`Device clock ` + for the JESD204B/C interface. Must be line clock/40 for 204B correct operation. + Must be line clock/66 for correct 204C operation. + * - enable + - Request signal for each channel. + * - dac_valid + - Qualifier signal for each channel. Always '1'. + * - dac_ddata + - Raw application layer data, every channel concatenated. + * - dac_dunf + - Application layer underflow. + +Register Map +-------------------------------------------------------------------------------- + +.. hdl-regmap:: + :name: COMMON + :no-type-info: + +.. hdl-regmap:: + :name: DAC_COMMON + :no-type-info: + +.. hdl-regmap:: + :name: JESD_TPL + :no-type-info: + +.. hdl-regmap:: + :name: DAC_CHANNEL + :no-type-info: + +Theory of Operation +-------------------------------------------------------------------------------- + +Data paths +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +The data intended for the DAC can have multiple sources: + +- **DMA source** Raw data can be accepted from a external block representing + the Application layer; +- **DDS source** For each DAC channel, a dual-tone can be generated by a DDS + core; +- **PRBS source** For each DAC channel, one of the following PN sequence can + be selected: PN7, PN15, inverted PN7, inverted PN15. + +Interfaces and Signals +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Application layer interface +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +The application layer connects to the framer block when the DMA source is +selected. The framer module takes sample data and maps it onto the format that +the JESD204 link expects for the specified framer configuration. + +The data in the application layer interface ``dac_ddata`` is expected to have +the following layout: + +:: + + MSB LSB + [ MmSn, ..., MmS1, MnS0, ..., M1Sn, ... M1S1, M1S0, M0Sn, ... M0S1, M0S0 ] + + +Where MjSi refers to the i-th sample of the j-th converter. With m being the +number of converters and n the number of samples per converter per beat. + +The core asserts the ``enable`` signal for each channel that is enabled by the +software. The ``dac_ddata`` data bus must contain data for each channel +regardless if the channels are enabled or not. + +Link layer interface +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +The link layer interface description can be found in the +:ref:`User Data Interface ` section of the +:ref:`JESD204B/C Link Transmit Peripheral ` IP. + +Clock Monitor +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +The ``REG_STATUS`` (``0x054``) register ``CLK_FREQ`` field allows to determine +the clock rate of the device clock (``link_clk``) relative to the AXI interface +clock (``s_axi_aclk``). This can be used to verify that the device clock is +running at the expected rate. + +The number is represented as unsigned 16.16 format. Assuming a 100MHz processor +clock, this corresponds to a resolution of 1.523kHz per LSB. A raw value of 0 +indicates that the link clock is currently not active. + +External synchronization +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +By setting the ``EXT_SYNC`` parameter of the IP to 1, an external +synchronization signal ``dac_sync_in`` can be used to trigger data movement +from user application layer to the link layer, reset internal DDS cores or PRBS +generators. If the ``EXT_SYNC`` parameter is set to zero, the external signal +is ignored and only a software controlled reset happens inside the DDS, +PRBS logic. + +The external synchronization signal should be synchronous with the DAC clock. +Synchronization will be done on the rising edge of the signal. + +The self clearing ``SYNC`` control bit from the ``REG_CNTRL_1`` (``0x44``) +register will arm the trigger logic to wait for the external sync signal. The +``DAC_SYNC_STATUS`` status bit from the ``REG_SYNC_STATUS`` (``0x68``) register +will show that the synchronization is armed but the synchronization signal has +not yet been received. + +Once the sync signal is received, the data will start to flow and the +``DAC_SYNC_STATUS`` status bit will reflect that with a deassertion. + +While the synchronization mechanism is armed, the ``dac_valid`` output signal +is gated until the trigger signal is received. The gating happens only during +this period, meaning that ``dac_valid`` will stay high in all other +cases (normal operation). + +Restrictions +-------------------------------------------------------------------------------- + +Reduced number of octets-per-frame (``F``) settings. The following values are +supported by the peripheral: 1, 2, 4 + +- Starting from + `this `__ + commit this restriction no longer applies + +Software Support +-------------------------------------------------------------------------------- + +.. warning:: + To ensure correct operation it is highly recommended to use the Analog + Devices provided JESD204B/C software packages for interfacing the peripheral. + Analog Devices is not able to provide support in case issues arise from using + custom low-level software for interfacing the peripheral. + +.. _ad_ip_jesd204_tpl_dac_supported_devices: + +Supported Devices +-------------------------------------------------------------------------------- + +JESD204B Digital-to-Analog Converters +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- :adi:`AD9135 `: Dual, 11-Bit, high dynamic, 2.8 GSPS, + TxDAC+® Digital-to-Analog Converter +- :adi:`AD9136 `: Dual, 16-Bit, 2.8 GSPS, TxDAC+® + Digital-to-Analog Converter +- :adi:`AD9144 `: Quad, 16-Bit, 2.8 GSPS, TxDAC+® + Digital-to-Analog Converter +- :adi:`AD9152 `: Dual, 16-Bit, 2.25 GSPS, TxDAC+ + Digital-to-Analog Converter +- :adi:`AD9154 `: Quad, 16-Bit, 2.4 GSPS, TxDAC+® + Digital-to-Analog Converter +- :adi:`AD9161 `: 11-Bit, 12 GSPS, RF Digital-to-Analog + Converter +- :adi:`AD9162 `: 16-Bit, 12 GSPS, RF Digital-to-Analog + Converter +- :adi:`AD9163 `: 16-Bit, 12 GSPS, RF DAC and Digital + Upconverter +- :adi:`AD9164 `: 16-Bit, 12 GSPS, RF DAC and Direct Digital + Synthesizer +- :adi:`AD9172 `: Dual, 16-Bit, 12.6 GSPS RF DAC with + Channelizers +- :adi:`AD9173 `: Dual, 16-Bit, 12.6 GSPS RF DAC with + Channelizers +- :adi:`AD9174 `: Dual, 16-Bit, 12.6 GSPS RF DAC and Direct + Digital Synthesizer +- :adi:`AD9175 `: Dual, 11-Bit/16-Bit, 12.6 GSPS RF DAC with + Wideband Channelizers +- :adi:`AD9176 `: Dual, 16-Bit, 12.6 GSPS RF DAC with + Wideband Channelizers +- :adi:`AD9177 `: Quad, 16-Bit, 12 GSPS RF DAC with + Wideband Channelizers + +JESD204B RF Transceivers +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- :adi:`AD9371 `: SDR Integrated, Dual RF Transceiver with + Observation Path +- :adi:`AD9375 `: SDR Integrated, Dual RF Transceiver with + Observation Path and DPD +- :adi:`ADRV9009 `: SDR Integrated, Dual RF Transceiver + with Observation Path +- :adi:`ADRV9008-1 `: SDR Integrated, Dual RF Receiver +- :adi:`ADRV9008-2 `: SDR Integrated, Dual RF + Transmitter with Observation Path + +JESD204B/C Mixed-Signal Front Ends +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- :adi:`AD9081 `: MxFE™ Quad, 16-Bit, 12GSPS RFDAC and + Quad, 12-Bit, 4GSPS RFADC +- :adi:`AD9082 `: MxFE™ QUAD, 16-Bit, 12GSPS RFDAC and + DUAL, 12-Bit, 6GSPS RFADC +- :adi:`AD9986 `: 4T2R Direct RF Transmitter and + Observation Receiver +- :adi:`AD9988 `: 4T4R Direct RF Receiver and Transmitter + +More Information +-------------------------------------------------------------------------------- + +- :ref:`JESD204 Interface Framework ` +- :dokuwiki:`Glossary of terms ` +- :ref:`HDL User Guide ` + +Technical Support +-------------------------------------------------------------------------------- + +Analog Devices will provide limited online support for anyone using the core +with Analog Devices components (ADC, DAC, Video, Audio, etc) via the +:ez:`EngineerZone `. diff --git a/docs/library/jesd204/axi_jesd204_rx/axi_jesd204_rx_204c.svg b/docs/library/jesd204/axi_jesd204_rx/axi_jesd204_rx_204c.svg new file mode 100644 index 000000000..bab343c7f --- /dev/null +++ b/docs/library/jesd204/axi_jesd204_rx/axi_jesd204_rx_204c.svg @@ -0,0 +1,1113 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Lane 1 + Lane 2 + Lane n + + CONTROL + SYNC~ + SYSREF + + + + RX_DATA + RX_PHY0 + RX_PHY1 + RX_PHYn + + + + REGISTERMAP + + S_AXI + + + Status + Configuration + + Enable + + + + + + + s_axi_aclk + device_clk + + + irq + + + + + + + + 8B/10B or 64B/66B decoder + + Release + + + diff --git a/docs/library/jesd204/axi_jesd204_rx/axi_jesd204_rx_204c_64b66b.svg b/docs/library/jesd204/axi_jesd204_rx/axi_jesd204_rx_204c_64b66b.svg new file mode 100644 index 000000000..05f04f62b --- /dev/null +++ b/docs/library/jesd204/axi_jesd204_rx/axi_jesd204_rx_204c_64b66b.svg @@ -0,0 +1,1213 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + CRC + + + + + + + + 64 + 2 + Lane x + 64b66b mode decoder + + DESCRAMBLER + + HEADERDECODER + + ERRORMONITOR + + + EoMB + + EoEMB + CRC + + + emb_state + + invalid Sync Header + + unexpected EoMB + + unexpected EoEMB + configuration + phy_header + + phy_block_sync + + + + + + + CRC error + phy_data + + + ELASTICBUFFER + + + + 64 + rx_data + + Release + Ready + + + + + + + + EoEMB + sh_count + + + diff --git a/docs/library/jesd204/axi_jesd204_rx/axi_jesd204_rx_204c_8b10b.svg b/docs/library/jesd204/axi_jesd204_rx/axi_jesd204_rx_204c_8b10b.svg new file mode 100644 index 000000000..786c2c18d --- /dev/null +++ b/docs/library/jesd204/axi_jesd204_rx/axi_jesd204_rx_204c_8b10b.svg @@ -0,0 +1,687 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + DESCRAMBLER + + ILAS MONITOR + + Lane x + + + CGS MONITOR + ILAS data + + + + 8b10b mode decoder + + + + ELASTICBUFFER + + + + 32 + rx_data + + + 32 + phy_data + Release + + + + + Ready + + + cgs_state + ALIGNER + + diff --git a/docs/library/jesd204/axi_jesd204_rx/dual_clock_operation.svg b/docs/library/jesd204/axi_jesd204_rx/dual_clock_operation.svg new file mode 100644 index 000000000..d5eedcec7 --- /dev/null +++ b/docs/library/jesd204/axi_jesd204_rx/dual_clock_operation.svg @@ -0,0 +1,252 @@ + + + + + + + + + + + + + + + + + + + PHY + Transport Layer + Application Layer + Link Layer + + + + 4:Nor8:N + + + + + + + + SYSREF + Gearbox + device clock + ref clock + link clock + + diff --git a/docs/library/jesd204/axi_jesd204_rx/index.rst b/docs/library/jesd204/axi_jesd204_rx/index.rst new file mode 100644 index 000000000..399764355 --- /dev/null +++ b/docs/library/jesd204/axi_jesd204_rx/index.rst @@ -0,0 +1,1154 @@ +.. _axi_jesd204_rx: + +JESD204B/C Link Receive Peripheral +================================================================================ + +.. hdl-component-diagram:: + +The Analog Devices JESD204B/C Link Receive Peripheral implements the link layer +handling of a JESD204 receive logic device. Implements the 8B/10B based link +layer defined in JESD204C standard that is similar to the link layer defined in +JESD204B. This includes handling of the SYSREF and SYNC~ and controlling the +:ref:`link state machine ` accordingly +as well as performing per lane descrambling and character replacement. +Implements the 64B/66B based link layer defined in the JESD204C standard. This +includes handling of the SYSREF, per lane decoding of sync header, +descrambling, CRC checking of data blocks and error monitoring. + +The type of link layer is selectable during implementation phase through the +``LINK_MODE`` synthesis parameter. + +It has been designed for interoperability with +:ref:`Analog Devices JESD204 ADC converter products `. +To form a complete JESD204 receive logic device, it has to be combined with a +:ref:`PHY layer ` and +:ref:`transport layer ` peripheral. + +Features +-------------------------------------------------------------------------------- + +- Backwards compatibility with JESD204B; +- 64B/66B link layer defined in JESD204C; +- Subclass 0 and Subclass 1 support; +- Deterministic Latency (for Subclass 1 operation); +- Runtime reconfigurability through memory-mapped register interface + (AXI4-Lite); +- Interrupts for event notification; +- Diagnostics; +- Max Lanerate with 8B/10B mode: 15 Gbps; +- Max Lanerate with 64B/66B mode: 32 Gbps; +- Low Latency; +- Independent per lane enable/disable. + +.. + Utilization + -------------------------------------------------------------------------------- + + .. collapsible:: Detailed Utilization + + +---------------+---------+----+---+ + |Device Family |NUM_LANES|LUTs|FFs| + +===============+=========+====+===+ + |Intel Arria 10 |1 |TBD |TDB| + + +---------+----+---+ + | |2 |TBD |TBD| + + +---------+----+---+ + | |4 |TBD |TBD| + + +---------+----+---+ + | |8 |TBD |TBD| + +---------------+---------+----+---+ + |AMD Xilinx |1 |TBD |TBD| + |Artix 7 +---------+----+---+ + | |2 |TBD |TBD| + + +---------+----+---+ + | |4 |TBD |TBD| + + +---------+----+---+ + | |8 |TBD |TBD| + +---------------+---------+----+---+ + |AMD Xilinx |1 |TBD |TBD| + |Kintex 7 +---------+----+---+ + | |2 |TBD |TBD| + + +---------+----+---+ + | |4 |824 |897| + + +---------+----+---+ + | |8 |TBD |TBD| + +---------------+---------+----+---+ + |AMD Xilinx |1 |TBD |TBD| + |Virtex 7 +---------+----+---+ + | |2 |TBD |TBD| + + +---------+----+---+ + | |4 |TBD |TBD| + + +---------+----+---+ + | |8 |TBD |TBD| + +---------------+---------+----+---+ + +Files +-------------------------------------------------------------------------------- + +.. list-table:: + :header-rows: 1 + + * - Name + - Description + * - :git-hdl:`axi_jesd204_rx.v ` + - Verilog source for the peripheral. + * - :git-hdl:`axi_jesd204_rx_ip.tcl ` + - TCL script to generate the Vivado IP-integrator project for the + peripheral. + +Block Diagram +-------------------------------------------------------------------------------- + +.. image:: axi_jesd204_rx_204c.svg + :align: center + +AXI JESD204 RX Synthesis Configuration Parameters +-------------------------------------------------------------------------------- + +.. hdl-parameters:: + + * - ID + - Instance identification number. + * - NUM_LANES + - Maximum number of lanes supported by the peripheral. + * - NUM_LINKS + - Maximum number of links supported by the peripheral. + * - LINK_MODE + - | Decoder selection of the link layer: + | 1 - 8B/10B mode; + | 2 - 64B/66B mode. + * - DATA_PATH_WIDTH + - Data path width in bytes. Set it to 4 in case of 8B/10B, 8 in case of + 64B/66B + +JESD204 RX Synthesis Configuration Parameters +-------------------------------------------------------------------------------- + +.. hdl-parameters:: + :path: library/jesd204/jesd204_rx + + * - NUM_LANES + - Maximum number of lanes supported by the peripheral. + * - NUM_LINKS + - Maximum number of links supported by the peripheral. + * - LINK_MODE + - | Decoder selection of the link layer: + | 1 - 8B/10B mode; + | 2 - 64B/66B mode. + * - DATA_PATH_WIDTH + - Data path width in bytes. Set it to 4 in case of 8B/10B, 8 in case of + 64B/66B. + * - TPL_DATA_PATH_WIDTH + - Data path width in bytes towards transport layer. Must be greater or + equal to ``DATA_PATH_WIDTH``. Must be a power of 2 integer multiple of + the F parameter. + * - ASYNC_CLK + - Set this parameter to 1 if the link clock and the device clocks have + different frequencies, or if they have the same frequency but a + different source. If set, synchronizing logic and a gearbox of ratio + ``DATA_PATH_WIDTH``:``TPL_DATA_PATH_WIDTH`` is inserted to do the rate + conversion. If not set, ``TPL_DATA_PATH_WIDTH`` must match + ``DATA_PATH_WIDTH``, the same clock must be connected to ``clk`` and + ``device_clk`` inputs. + +AXI JESD204 RX Signal and Interface Pins +-------------------------------------------------------------------------------- + +.. hdl-interfaces:: + + * - s_axi_aclk + - All ``S_AXI`` signals and ``irq`` are synchronous to this clock. + * - s_axi_aresetn + - Resets the internal state of the peripheral. + * - s_axi + - Memory mapped AXI-lite bus that provides access to modules register map. + * - irq + - Interrupt output of the module. Is asserted when at least one of the + modules interrupt is pending and enabled. + * - device_clk + - :dokuwiki:`Device clock ` + for the JESD204 interface. Its frequency must be link clock + \* ``DATA_PATH_WIDTH`` / ``TPL_DATA_PATH_WIDTH`` + * - device_reset + - Reset active high synchronous with the + :dokuwiki:`Device clock `. + +JESD204 RX Signal and Interface Pins +-------------------------------------------------------------------------------- + +.. hdl-interfaces:: + :path: library/jesd204/jesd204_rx + + * - clk + - :dokuwiki:`Link clock ` + for the JESD204 interface. Must be line clock/40 for correct operation + in 8B/10B mode, line clock/66 in 64B/66B mode. + * - reset + - Reset active high synchronous with the + :dokuwiki:`Link clock ` + * - rx_data + - Received data. + * - sync + - sync[m-1:0] is JESD204 SYNC~ (or SYNC_N) signals, available in 8B/10B mode. + (``0 <= m < NUM_LINKS``) + * - sysref + - JESD204 SYSREF signal. + * - rx_phy* + - n-th lane of the JESD204 interface (``0 <= n < NUM_LANES``). + * - phy_en_char_align + - Enable transceiver character alignment. + +.. it was optimized out because it is always 1 in the source code +.. * - phy_ready + - phy_ready Transceiver status. + +Register Map +-------------------------------------------------------------------------------- + +.. hdl-regmap:: + :name: JESD_RX + :no-type-info: + +Theory of Operation +-------------------------------------------------------------------------------- + +The JESD204B/C receive peripheral consists of two main components. The register +map and the link processor. Both components are fully asynchronous and are +clocked by independent clocks. The register map is in the ``s_axi_aclk`` clock +domain, while the link processor is in the ``clk`` and ``device_clk`` clock +domain. + +The register map is used to configure the operational parameters of the link +processor as well as to query the current state of the link processor. The link +processor itself is responsible for handling the JESD204 link layer protocol. + +Interfaces and Signals +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Register Map Configuration Interface +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +The register map configuration interface can be accessed through the AXI4-Lite +``S_AXI`` interface. The interface is synchronous to the ``s_axi_aclk``. The +``s_axi_aresetn`` signal is used to reset the peripheral and should be asserted +during system startup until the ``s_axi_aclk`` is active and stable. +De-assertion of the reset signal should be synchronous to ``s_axi_aclk``. + +JESD204 Control Signals +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +The ``sync`` and ``sysref`` signals correspond to the SYNC~ and SYSREF signals +of the JESD204 specification. + +The ``sync`` signal is asserted by the peripheral during link initialization and +must be connected to the corresponding JESD204 ADC converter devices on the same +link. + +The ``sysref`` signal is generated externally and is optional. It is only +required to achieve deterministic latency in subclass 1 mode operation. If the +``sysref`` signal is not connected software needs to configure the peripheral +accordingly to indicate this. + +When the ``sysref`` signal is used, in order to ensure correct operation, it is +important that setup and hold of the external signal relative to the +``device_clk`` signal are met. Otherwise, deterministic latency cannot be +guaranteed. + +Transceiver Interface (RX_PHYn) +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +For each lane, the peripheral has one corresponding RX_PHY interface. These +interfaces accept the physical layer data from the downstream physical layer +transceiver peripheral. + +The physical layer is responsible for clock recovery, character alignment, +de-serialization as well an 8b10b decoding. + +.. _axi_jesd204_rx_user_data: + +User Data Interface (RX_DATA) +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +User data is provided on the AXI4-Stream ``RX_DATA`` interface. The interface is +a reduced AXI4-Stream interface and only features the TVALID flow control +signal, but not the TREADY flow control signal. The behavior of the interface is +as if the TREADY signal was always asserted. This means as soon as ``rx_valid`` +is asserted, a continuous stream of user data must be accepted from ``rx_data``. + +.. wavedrom:: + :align: center + + { + signal: [ + ['RX_DATA', + { name: "device_clk", wave: 'P.........' }, + { name: "rx_data", wave: "x...======", data: ["D0", "D1", "D2", + "D3", "D4", "..."] }, + { name: 'rx_valid', wave: '0...1.....' }, + ] + ], + foot: { + text: + ['tspan',{dx:'-45'}, 'Link Inicialization', ['tspan', {dx:'60'}, + 'User Data Phase'],], + } + } + +After reset and during link initialization, the ``rx_valid`` signal is +deasserted. As soon as the User Data Phase is entered, the ``rx_valid`` will be +asserted to indicate that the peripheral is now providing the processed data +at the ``rx_data`` signal. The ``rx_valid`` signal stays asserted until the link +is either deactivated or reinitialized. + +.. image:: octets_mapping.svg + :align: right + +Typically, the ``RX_DATA`` interface is connected to a JESD204 transport layer +peripheral that deframes the data and passes it to the application layer. The +internal data path width of the peripheral is 4, this means that 4 octets +per lane are processed in parallel. When in the user data phase, the peripheral +provides 4 octets for each lane in each beat. + +This means that ``RX_DATA`` interface is ``DATA_PATH_WIDTH`` \* 8 \* +``NUM_LANES`` bits wide. With each block of consecutive ``DATA_PATH_WIDTH`` \* 8 +bits corresponding to one lane. The lowest ``DATA_PATH_WIDTH`` \* 8 bits +correspond to the first lane, while the highest ``DATA_PATH_WIDTH`` \* 8 bits +correspond to the last lane. + +E.g. for 8B/10B mode where ``DATA_PATH_WIDTH``\ =4. Each lane specific 32-bit +block corresponds to 4 octets each 8 bits wide. The temporal ordering of the +octets is from LSB to MSB, this means the octet placed in the lowest 8 bits was +received first, the octet placed in the highest 8 bits was received last. + +Data corresponding to lanes that have been disabled should be ignored and their +value is undefined. + +Configuration Interface +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +The peripheral features a register map configuration interface that can be +accessed through the AXI4-Lite ``S_AXI`` port. The register map can be used to +configure the peripherals operational parameters, query the current status of +the device and query the features supported by the device. + +Peripheral Identification and HDL Synthesis Settings +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +The peripheral contains multiple registers that allow the identification of the +peripheral as well as the discovery of features that were configured at HDL +synthesis time. Apart from the ``SCRATCH`` register, all registers in this +section are read-only and write access to them will be ignored. + +The ``VERSION`` (``0x000``) register contains the version of the peripheral. The +version determines the register map layout and general features supported by the +peripheral. The version number follows `semantic versioning `__. +Increments in the major number indicate backward incompatible changes, +increments in the minor number indicate backward compatible changes, patch +letter increments indicate bug fix. + +The ``PERIPHERAL_ID`` (``0x004``) register contains the value of the ``ID`` HDL +configuration parameter that was set during synthesis. Its primary function is +to allow to distinguish between multiple instances of the peripheral in the same +design. + +The ``SCRATCH`` (``0x008``) register is a general purpose 32-bit register that +can be set to an arbitrary values. Reading the register will yield the value +previously written (the value will be cleared when the peripheral is reset). Its +content does not affect the operation of the peripheral. It can be used by +software to test whether the register map is accessible or store custom +peripheral associated data. + +The ``IDENTIFICATION`` (``0x00c``) register contains the value of ``"204R"``. +This value is unique to this type of peripheral and can be used to ensure that +the peripheral exists at the expected location in the memory mapped IO register +space. + +The ``SYNTH_NUM_LANES`` (``0x010``) register contains the value of the +``NUM_LANES`` HDL configuration parameter that was set during synthesis. It +corresponds to the maximum of lanes supported by the peripheral. Possible values +are between ``1`` and ``32``. + +The ``SYNTH_DATA_PATH_WIDTH`` (``0x014``) register contains the value of the +internal data path width per lane in octets. This is how many octets are +processed in parallel on each lane and affects the restrictions of possible +values for certain runtime configuration registers. The value is encoded as the +log2() of the data path width. Possible values are: + +#. Internal data path width is 2; +#. Internal data path width is 4; +#. Internal data path width is 8. + +The ``SYNTH_ELASTIC_BUFFER_SIZE`` (``0x040``) register describes the maximum +amount of octets that the elastic buffer can hold. This puts a limit on the +maximum local-multi-frame-clock (LMFC) / local-multiblock-clock (LEMC) period +(subclass 1) as well as the maximum skew between individual lanes (subclass 0). +Both must be less than the elastic buffer size. + +Interrupt Handling +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +Interrupt processing is handled by 3 closely related registers. All 3 +registers follow the same layout, each bit in the register corresponds to one +particular interrupt. + +When an interrupt event occurs it is recorded in the ``IRQ_SOURCE`` (``0x088``) +register. For a recorded interrupt event, the corresponding bit is set to 1. If +an interrupt event occurs while the bit is already set to 1, it will stay set +to 1. + +The ``IRQ_ENABLE`` (``0x080``) register controls how recorded interrupt events +propagate. An interrupt is considered to be enabled if the corresponding bit in +the ``IRQ_ENABLE`` register is set to 1, it is considered to be disabled if the +bit is set to 0. + +Disabling an interrupt will not prevent it from being recorded, but only its +propagation. This means if an interrupt event was previously recorded while the +interrupt was disabled and the interrupt is being enabled the interrupt event +will then propagate. + +An interrupt event that has been recorded and is enabled propagates to the +``IRQ_PENDING`` (``0x084``) register. The corresponding bit for such an +interrupt will read as 1. Disabled or interrupts for which no events have been +recorded will read as 0. Also if at least one interrupt has been recorded and is +enabled the external ``irq`` signal will be asserted to signal the IRQ event to +the upstream IRQ controller. + +A recorded interrupt event can be cleared (or acknowledged) by writing a 1 to +the corresponding bit to either the ``IRQ_SOURCE`` or ``IRQ_PENDING`` register. +It is possible to clear multiple interrupt events at the same time by setting +multiple bits in a single write operation. + +For more details regarding interrupt operation see the +:ref:`interrupts section ` of this document. + +Link Control +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +The ``LINK_DISABLE`` (``0x0c0``) register is used to control the link state and +switch between enabled and disabled. While the link is disabled its state +machine will remain in reset and it will not react to any external event like +the ``SYSREF``\ signal. + +Writing a 0 to the ``LINK_DISABLE`` register will enable the link. While the +link state is changing from disabled to enabled it will go through a short +initialization procedure, which will take a few clock cycles. To check whether +the initialization procedure has completed and the link is fully operational the +``LINK_STATE`` (``0x0c4``) register can be checked. The LINK_STATE (``[0]``) bit +will contain a 0 when the link is fully enabled and will contain a 1 while it is +disabled or going through the initialization procedure. + +Writing a 1 to the ``LINK_DISABLE`` register will immediately disable the link. + +The ``EXTERNAL_RESET`` (``[1]``) bit in the ``LINK_STATE`` register indicates +whether the external link reset signal is asserted (``1``) or de-asserted +(``0``). When the external link reset is asserted the link is disabled +regardless of the setting of ``LINK_DISABLE``. The external link reset is +controlled by the fabric and might be asserted if the link clock is not stable +yet. + +Multi-link Control +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +A multi-link is a link where multiple converter devices are connected to a +single logic device (FPGA). All links involved in a multi-link are synchronous +and established at the same time. For an 8B/10B RX link, this means that the +``SYNC~`` signal needs to be propagated from the FPGA to each converter. + +For an 8B/10B link the ``MULTI_LINK_DISABLE`` register allows activating or +deactivating each ``SYNC~`` lines independently. This is useful when depending +on the use case profile some converter devices are supposed to be disabled. + +Link Configuration +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +The link configuration registers control certain aspects of the runtime behavior +of the peripheral. Since the JESD204 standard does now allow changes to link +configuration while the link is active the link configuration registers can only +be modified while the link is disabled. As soon as it is enabled the +configuration registers turn read-only and any writes to them will be ignored. + +The ``LANES_DISABLE`` (``0x200``) register allows to disable individual lanes. +Each bit in the register corresponds to a particular lane and indicates whether +that lane is enabled or disabled. Bit 0 corresponds to the first lane, bit 1 to +the second lane and so on. A value of 0 for a specific bit means the +corresponding lane is enabled, a value of 1 means the lane is disabled. A +disabled lane will not receive any data when the link is otherwise active. By +default, all lanes are enabled. + +The ``LINK_CONF0`` register configures the octets-per-frame and +frames-per-multi-frame settings of the link. The ``OCTETS_PER_FRAME`` +(``[18:16]``) field should be set to the number of octets-per-frame minus 1 (F - +1). The ``OCTETS_PER_MULTIFRAME`` (``[7:0]``) field should be set to the number +of octets-per-frame multiplied by the number of frames-per-multi-frame minus 1 +(FxK - 1). For correct operation FxK must be a multiple of 4. In 64B/66B mode +this field matches and also represents the number of octets per extended +multiblock (Ex32x8 - 1). + +The ``LINK_CONF1`` register allows disabling optional link level processing +stages. The ``DESCRAMBLER_DISABLE`` (``[0]``) bit controls whether descrambling +of the received user data is enabled or disabled. A value of 0 enables +descrambling and a value of 1 disables it. In 64B/66B mode descrambling must be +always enabled. The ``CHAR_REPLACEMENT_DISABLE`` (``[1]``) bit controls whether +alignment character replacement is performed or not. A value of 0 enables +character replacement and a value of 1 disables it. If character replacement is +disabled and an alignment character is received +(:dokuwiki:`/F/ ` +or +:dokuwiki:`/A/ `) +a unexpected K-character error is raised. + +For correct operation, character replacement must be disabled when descrambling +is disabled otherwise undefined behavior might occur. + +Both the transmitter as well as receiver device on the JESD204 link need to be +configured with the same settings for scrambling/descrambling and character +replacement for correct operation. + +Character replacement is used only in 8B/10B links and completely disregarded in +64B/66B mode. + +The ``LINK_CONF2`` register controls the behavior of elastic buffer. The +``BUFFER_EARLY_RELEASE`` (``[16]``) bit configures when the data is released +from the elastic buffer to the RX_DATA port. If the bit is set to 0 the data +will be released at the earliest configured release point after all lanes are +ready. When the bit is set to 1 the data will be released as soon as all lanes +are ready. The former gives deterministic latency and is required for subclass 1 +operation, the later gives minimum latency. + +The ``BUFFER_DELAY`` (``[11:0]``) field allows to configure the buffer release +opportunity point relative to the local-multi frame-clock (LMFC)/ +local-multiblock-clock (LEMC). A setting of 0 indicates that the release +opportunity is aligned to the LMFC/LEMC edge. A setting of X indicates that it +trails the LMFC/LEMC edge by X octets. + +.. wavedrom:: + :scale: 100% + :align: center + + { + signal: [ + { name: "device_clk", wave: 'P.........' }, + { name: "LMFC edge", wave: "l..10.....", node:"...a"}, + { name: 'Release Opportunity', wave: '0.....10..', node:"......b"}, + ], + edge: ['a~>b BUFFER DELAY/4'] + } + +The ``BUFFER_DELAY`` field must be set to a multiple of 4. Writing a value that +is not a multiple of 4 will be rounded down to the next multiple of 4. For +correct operation, the ``BUFFER_DELAY`` field must also be set to a value +smaller than the number of octets per multi-frame (``F``\ x\ ``K``). + +This mechanism can be used to reduce overall latency while still maintaining +deterministic latency if the maximum link latency (overall valid PVT settings) +is known. + +SYSREF Handling +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +The external SYSREF signal is used to align the internal local multiframe clocks +(LMFC)/ local-multiblock-clock (LEMC) between multiple devices on the same link. + +The ``SYSREF_CONF`` (``0x100``) register allows to configure the behavior of the +SYSREF capture circuitry. Setting the ``SYSREF_DISABLE`` (``[0]``) bit to 1 +disables the SYSREF handling. All external SYSREF events are ignored and the +LMFC/LEMC is generated internally. For Subclass 1 operation, SYSREF handling +should be enabled and for Subclass 0 operation it should be disabled. + +The ``SYSREF_LMFC_OFFSET`` (``0x104``) register allows to modify the offset +between the SYSREF rising edge and the rising edge of the LMFC/LEMC. + +For optimal operation it is recommended that all device on a JESD204 link should +be configured in a way so that the total offset between the value of the +``SYSREF_LMFC_OFFSET`` register must be set to a value smaller than the +configured number of octets-per-multiframe (``OCTETS_PER_MULTIFRAME``), +otherwise undefined behavior might occur. + +The ``SYSREF_STATUS`` (``0x108``) register allows to monitor the status of the +SYSREF signals. ``SYSREF_DETECTED`` (``[0]``) bit indicates that the +peripheral as observed a SYSREF event. The ``SYSREF_ALIGNMENT_ERROR`` (``[1]``) +bit indicates that a SYSREF event has been observed which was unaligned, in +regards to the LMFC/LEMC period, to a previously recorded SYSREF event. + +All bits in the ``SYSREF_STATUS`` register are write-to-clear. All bits will +also be cleared when the link is disabled. + +Note that the ``SYSREF_STATUS`` register will not record any events if SYSREF +operation is disabled or the JESD204 link is disabled. + +Link Status +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +All link status registers are read-only. While the link is disabled, some of the +link status registers might contain bogus values. Their content should be +ignored until the link is fully enabled. + +The ``STATUS_STATE`` (``[1:0]``) field of the ``LINK_STATUS`` (``0x280``) +register indicates the state of the +:ref:`8B/10B link state machine ` or +:ref:`64B/66B link state machine ` +depending on the selected decoder. + +Possible values for a 8B/10B link are: + +- RESET (0x0): The link is currently disabled; +- WAIT FOR PHY (0x1): The controller waits for the PHY level component to be + ready; +- CGS (0x2): The controller is waiting for one or more lanes to complete the + CGS phase; +- DATA (0x3): All lanes are in the data phase and the link is properly + established. + +Possible values for a 64B/66B link are: + +- RESET (0x0): The link is currently disabled; +- WAIT BLOCK SYNC (0x1): The controller waits for all enabled lanes to reach + sync header alignment; +- BLOCK SYNC (0x2): All enabled lanes from the PHY reached sync header + alignment phase; +- DATA (0x3): All enabled lanes reached the multi-block synchronization phase, + elastic buffer released the data and the link is properly established. + +The state of each individual lane can be queried from the +:ref:`lane status ` registers. + +.. _axi_jesd204_rx_lane_status: + +Lane Status +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +Each lane has a independent status register (``LANEn_STATUS`` (``0x300``)) that +indicates the current state of the lane. + +8B/10B Link Lane Status Fields +'''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''' + +The ``CGS_STATE`` (``[1:0]``) indicates the current state of the lane code group +synchronization: + +- INIT (0x0): Lane is not synchronized; +- CHECK (0x1): Lane is in the process of synchronizing, at least some /K/ + synchronization characters have been observed; +- DATA (0x2): Lane is synchronized and ready to receive data. + +The ``IFS_READY`` (``[4]``) bit indicates that initial frame synchronization has +completed for the lane and the lane is receiving either ILAS data or user data. + +The ``LANEn_LATENCY`` (``0x304``) register holds the duration in octets between +when the SYNC~ signal was de-asserted and when the frame synchronization for +this particular lane has completed. The ``LANEn_LATENCY`` register only holds +valid data if the ``IFS_READY`` bit of the ``LANEn_STATUS`` register is set. + +64B/66B Link Lane Status Fields +'''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''' + +The ``EMB_STATE`` (``[10:8]``) indicates the current state of the Extended +Multi-Block alignment state machine: + +- EMB_INIT (3'b001): Wait for sync header alignment and for an end of extended + multiblock (EoEMB) indicator; +- EMB_HUNT (3'b010): Keep track and monitor consecutive EoEMBs until a + threshold is reached; +- EMB_LOCK (3'b100): Asserted by receiver to indicate that extended multiblock + alignment has been achieved. + +8B/10B Link ILAS Configuration Data +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +If the JESD204 transmitter emits an initial lane alignment sequence (ILAS) the +configuration data embedded in the second multi-frame of the ILA sequence is +captured by the peripheral and stored in a set of four per-lane registers +(``LANEn_ILAS0``, ``LANEn_ILAS1``, ``LANEn_ILAS2`` and ``LANEn_ILAS3``). +``ILAS_READY`` (``[5]``) bit in the corresponding ``LANEn_STATUS`` register +indicates whether the ILAS configuration data has been captured for a specific +lane. The data in the ``LANEn_ILASx`` registers is only valid when that bit is +asserted. + +The received ILAS configuration data can be used to verify that the transmitter +device is using the expected configuration and that the lane and device mapping +is correct. + +Clock Monitor +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +The ``LINK_CLK_FREQ`` (``0x0c8``) register allows to determine the clock rate of +the link clock (``clk``) relative to the AXI interface clock (``s_axi_aclk``). +This can be used to verify that the link clock is running at the expected rate. + +The ``DEVICE_CLK_FREQ`` (``0x0cc``) register allows to determine the clock rate +of the device clock (``device_clk``) relative to the AXI interface clock +(``s_axi_aclk``). This can be used to verify that the device clock is running at +the expected rate. + +The number is represented as unsigned 16.16 format. Assuming a 100MHz processor +clock, this corresponds to a resolution of 1.523kHz per LSB. A raw value of 0 +indicates that the link clock is currently not active. + +.. _axi_jesd204_rx_interrupts: + +Interrupts +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +The core does not generate interrupts. + +8B/10B Link +-------------------------------------------------------------------------------- + +.. image:: axi_jesd204_rx_204c_8b10b.svg + :align: center + +.. _axi_jesd204_rx_8b10b_link_state_machine: + +8B/10B Link State Machine +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. image:: jesd204_rx_state_machine.svg + :align: right + +The peripheral can be in one of four main operating phases: RESET, WAIT FOR PHY, +CGS, or DATA. Upon reset the peripheral starts in the RESET phase. The WAIT FOR +PHY and CGS phases are used during the initialization of the JESD204 link. The +DATA phase is used during normal operation when user data is received across the +JESD204 link. + +RESET phase +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +The RESET phase is the default state entered during reset. While disabled the +peripheral will stay in the RESET phase. When enabled, the peripheral will +transition from the RESET phase to the WAIT FOR PHY phase. + +If at any point the peripheral is disabled, it will automatically transition +back to the RESET state. + +Lanes that have been disabled in the register map configuration interface, will +behave as if the link was in the RESET state regardless of the actual state. + +WAIT FOR PHY phase +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +During the WAIT FOR PHY phase the peripheral will wait for all PHY controllers +for all enabled lanes to be ready for operation. Once this condition is +satisfied the controlled will transition to the CGS phase. + +CGS phase +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +During the CGS phase the peripheral will assert the external ~SYNC signal and +expects the connected JESD204 transmitter to send /K/ characters. + +Each lane will independently the incoming data stream for /K/ characters and +adjust its state machine according to the received characters. + +Once all enabled lanes have entered the DATA state the link state will +transition from the CGS phase to the DATA phase. + +DATA phase +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +The DATA phase is the main operating mode of the peripheral. In this phase it +will transmit transport layer data at the RX_DATA port. When the peripheral +enters the DATA phase the ``valid`` signal of the ``RX_DATA`` interface will be +asserted to indicate that transport layer data is now available. + +By default the data received on each lane is descrambled. Descrambling can +optionally be disabled via the register map configuration interface. +Descrambling is enabled or disabled for all lanes equally. + +Scrambling reduces data-dependent effects, which can affect both the analog +performance of the data converter as well as the bit-error rate of JESD204 +serial link, therefore it is highly recommended to enable scrambling for the +link. + +The peripheral also performs per-lane alignment character monitoring. When +alignment character replacement is enabled the JESD204 transmitter replaces +under certain predictable conditions (i.e. the receiver can recover the replaced +character) the last octet in a frame or multi-frame. Replaced characters at the +end of a frame, that is also the end of a multi-frame, are replaced by the /A/ +character. Replaced characters at the end of a frame, that is not the end of a +multi-frame, are replaced by the /F/ character. If a alignment character is +received the peripheral checks that the it is in the expected position, either +the end of a frame or the end of a multi-frame, and reports an error if a lane +has become misaligned. This allows to detect alignment errors and allows the +application to re-initialize the link. + +Alignment character monitoring can optionally be disabled via the register map +configuration interface. Alignment character monitoring is enabled or disabled +for all lanes equally. If alignment character monitoring is disabled, no errors +are reported when a misaligned alignment character is received. + +Data on the ``RX_DATA`` port corresponding to a disabled lanes are undefined and +should be ignored. + +8B/10B Multi-endpoint RX link establishment +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +In a multi-endpoint configuration one link receive peripheral connects to +several endpoints/converter devices. In such cases the link is established +only when all enabled endpoints reach the DATA phase. For that all endpoints +must pass through CGS and ILAS stages. Depending on the software +implementation that controls the converter devices the endpoints can be +enabled at different moments. The link receive peripheral will receive the CGS +characters and do character alignment until for all enabled endpoints lanes +succeeds that and signalize that through the de-assertion of ``SYNC~`` signal. +In the below example we have a multi-point link of four endpoints +(``NUM_LINKS`` = 4): + +.. image:: quadmxfe_linkbringup_204b_adc.svg + :align: center + +.. note:: + + The physical layer is not depicted on purpose. JTXn represents the link + layer counterpart in the converter device/endpoint *n* + +The steps of the link bring-up are presented below: + +* **1** - Link receive peripheral is enabled, will assert its ``SYNC~`` signal + to indicate to the endpoints it is ready to receive and align to the ``CGS`` + characters. All ``SYNC~`` signal to all enabled endpoints assert in the same + time; +* **2,3,4,5** - JESD transmit block of DAC enabled, will start sending ``CGS`` + characters until its ``SYNC~`` pin is not pulled low. The timing depends on + the software implementation that controls the DAC; +* **6** - In Subclass 1 (SC1) ``SYSREF`` is captured and ``LMFC`` in the + FPGA and converter device is adjusted; +* **7** - Once the ``CGS`` characters are received correctly on all enabled + lanes, on the next Frame clock boundary in SC0 or ``LMFC`` boundary in SC1 + the ``SYNC~`` is de-asserted. All ``SYNC~`` signal to all enabled endpoints + de-assert in the same time. **In SC1 if** ``SYSREF`` **is not captured the + link receive peripheral will stay in CGS state and will keep** ``SYNC~`` + **asserted.**; +* **8** - Once all enabled endpoints (not masked by ``MULTI_LINK_DISABLE``) + observe the de-assert of the ``SYNC~`` signal, on the next Frame clock + boundary for SC0 or the next ``LMFC`` boundary for SC1, will start sending + the ``ILAS`` sequence, then after typically 4 ``LMFC`` periods later the + actual ``DATA``. + +64B/66B Link +-------------------------------------------------------------------------------- + +The 64-bit wide datapath of the link layer is fairly simple, the data received +from the PHY is sent through a mandatory descrambler block to an elastic buffer +that serves as an aligner cross lanes. Each beat of the datapath contains a +block of data of 8 octets. + +For each lane the control path starts from the 2-bit sync header connected to +the header decoder that tracks and monitors multiblock and extended multiblock +markers from the stream, reconstructs the 32-bit sync word corresponding to +every multiblock and extracts the received CRC from it. The CRC is calculated +for every multiblock and is compared against the received CRC. The mismatches +are recorded by the error monitor block. + +Beside the CRC errors the error monitor records invalid end of multiblock, end +of extended multiblock and invalid sync header errors. The source of every error +can be masked from the corresponding bit of the ``LINK_CONF3`` register. + +.. image:: axi_jesd204_rx_204c_64b66b.svg + :align: center + +.. _axi_jesd204_rx_64b66b_link_state_machine: + +64B/66B Link State Machine +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +The peripheral can be in one of four main operating phases: RESET, WAIT BS, +BLOCK SYNC, or DATA. Upon reset the peripheral starts in the RESET phase. The +WAIT BS and BLOCK SYNC phases are used during the initialization of the JESD204 +link. The DATA phase is used during normal operation when user data is received +across the JESD204 link. + +.. image:: jesd204c_rx_state_machine.svg + :align: right + +.. _axi_jesd204_rx_reset-phase-1: + +RESET phase +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +The RESET phase is the default state entered during reset. While disabled the +peripheral will stay in the RESET phase. When enabled the peripheral will +transition from the RESET phase to the WAIT FOR PHY phase. + +If at any point the peripheral is disabled it will automatically transition back +to the RESET state. + +WAIT BS phase +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +During the WAIT BS phase the peripheral will wait for all PHY controllers for +all enabled lanes to reach sync header alignment state ensuring the sync header +stream separation from the data blocks. Once this condition is satisfied the +controlled will transition to the BLOCK SYNC phase. + +If one of the enabled lanes loses the the sync header alignment the link will +fall back to WAIT BS state. + +BLOCK SYNC phase +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +The BLOCK SYNC state ensures all enabled lanes achieved sync header alignment or +block synchronization phase in other terms. During this state the peripheral +will wait for all enabled lanes to reach extended multiblock alignment and the +elastic buffer get released. Once each enabled lane is extended multiblock +aligned for each lane the data blocks are stored in the elastic buffer then are +released at a well defined moment relative to the ``SYSREF`` signal. + +.. _axi_jesd204_rx_data-phase-1: + +DATA phase +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +The DATA phase is the main operating mode of the peripheral. In this phase it +will transmit transport layer data at the ``RX_DATA`` port. When the peripheral +enters the DATA phase the ``valid`` signal of the ``RX_DATA`` interface will be +asserted to indicate that transport layer data is now available. + +64B/66B Link Extended MultiBlock Alignment State Machine +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +For each lane a state machine is used to detect the boundary of the extended +multiblocks by tracking well defined markers in the sync header stream. Once the +boundary is detected for each lane the corresponding data stream can be aligned +across all enabled lanes. This is done through the elastic buffer. + +.. image:: jesd204c_rx_emb_state_machine.svg + :align: right + +EMB INIT State +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +The EMB INIT is the default state of the state machine, all disabled lanes stay +in this state. The state is left only when the lane is enabled, the PHY +controller of the corresponding lane is sync header aligned and a valid end of +extended multiblock marker is detected in the sync header stream. + +At any moment the PHY loses sync header alignment the state machine will fall +back to the EMB INIT state. + +EMB HUNT State +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +In the EMB HUNT state the state machine will look after four consecutive correct +extended multiblock indicators, once this is achieved the state machine enters +the EMB LOCK state. In case invalid end of multiblock or end of extended +multiblock markers are detected the state machine falls back to the EMB INIT +state. + +EMB LOCK State +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +In the EMB LOCK state the monitoring of multiblock and extended multiblock +indicators is continued. In case of eight consecutive indicators are incorrect +the state machine will return in the EMB INIT state. This state ensures the +validity of the 32-bit sync words constructed from the sync header stream. For +each multiblock the calculated CRC of the previous multiblock is extracted from +the current sync word. + +Dual clock operation +-------------------------------------------------------------------------------- + +In case ``ASYNC_CLK`` parameter is set, a gearbox with 4:N (204B) or 8:N (204C) +ratio is enabled in the link layer peripherals, where N depends on the F +parameter of the link. The goal of the gearbox is to have at the transport layer +interface a data width that contains an integer number of frames per every +device clock cycle (each beat) so an integer number of samples can be +delivered/consumed to/from the application layer aligned to SYSREF ensuring +deterministic latency in modes where N'=12 or F!=1,2,4. + +.. image:: dual_clock_operation.svg + :align: center + +The gearbox ratio corresponds with the ratio of the link layer interface data +width towards physical layer and transport layer in octets. The interface width +towards the physical layer in 8B/10B (204B) mode depends on the DATA_PATH_WIDTH +synthesis parameter, and can be either 4 octets (default) or 8 octets. In 204B +mode the util_adxcvr supports only data width of 4 octets. In 64b66b (aka 204C) +mode the data width towards the physical interface is always 8 octets. + +The data path width towards the transport layer is defined by the +TPL_DATA_PATH_WIDTH synthesis parameter. + +The following rules apply: + +- TPL_DATA_PATH_WIDTH >= DATA_PATH_WIDTH; +- TPL_DATA_PATH_WIDTH = m x F; where m is a positive integer, power of 2. + +The link clock and device clock ratio should be the inverse of the +DATA_PATH_WIDTH : TPL_DATA_PATH_WIDTH ratio. + +In this context the link clock will be lane rate/40 or lane rate/80 for 204B +depending on DATA_PATH_WIDTH and lane rate/66 for 204C 64B/66B, however the +device clock could vary based in the F parameter. + +64b/66b Link latency reduction +-------------------------------------------------------------------------------- + +Deterministic latency can be reduced by adjusting the release point of the +elastic buffer in RX link layer. By default the release point of the elastic +buffer is at the edge of LEMC. In case of 64b66b link the ``LATENCY`` register +will indicate how many octets will the elastic buffer store before the default +release point for that specific lane. The release point can be adjusted to bring +it closer to the last arrival lane (that will have the least octets in the +buffer) so minimizing the buffer usage and the latency in turn. The ``LATENCY`` +must be measured over multiple power-ups and bring-up sequence. Identify the +slowest arrival lane (min value of the register). If multiple parallel links +must be synchronized all lanes from all links must be included in the process. + +Once the slowest lane delay is identified, before enabling the links, SW needs +to set the register ``BUFFER_DEALY`` (0x240) from all parallel Rx links if +exists based on the following formula: + +.. math:: + Buffer Delay = \frac{(F*K - min(latency regs) + 32)}{TPLDW} + 4 + +Where: + +- Buffer Delay - register 0x240 of the core; +- F*K - is the size of a multiframe in octets; +- ‘latency regs’ - is the measured latency of each lane observed during + consecutive link bring-ups measured for all Rx links, see regs (0x304 + + n*0x20) where n = 0..L-1 ; L is number of lanes; +- TPLDW - TPL datapath width in octets. Can be read from the + ``SYNTH_DATA_PATH_WIDTH`` (0x14) reg ``TPL_DATA_PATH_WIDTH`` field. + +**This value it the absolute minimum. It is recommended to increase it +slightly to have a better margin against power-up to power-up latency +variations.** + +Software Support +-------------------------------------------------------------------------------- + +.. warning:: + To ensure correct operation it is highly recommended to use the + Analog Devices provided JESD204 software packages for interfacing the + peripheral. Analog Devices is not able to provide support in case issues arise + from using custom low-level software for interfacing the peripheral. + +- :dokuwiki:`JESD204 Receive Linux Driver Support ` + +Restrictions +-------------------------------------------------------------------------------- + +During the design of the peripheral the deliberate decision was made to support +only a subset of the features mandated by the JESD204 standard for receiver +logic devices. The reasoning here is that the peripheral has been designed to +interface to Analog Devices JESD204 ADC converter devices and features that are +either not required or not supported by those converter devices would otherwise +lie dormant in peripheral and never be used. Instead the decision was made to +not implement those unneeded features even when the JESD204 standard requires +them for general purpose JESD204 receiver logic devices. As Analog Devices ADC +converter devices with new requirements are released the peripheral will be +adjusted accordingly. + +This approach allows for a leaner design using less resources, allowing for +lower pipeline latency and a higher maximum device clock frequency. + +The following lists where the peripheral deviates from the standard: + +- No subclass 2 support. JESD204 subclass 2 has due to its implementation + details restricted applicability and is seldom a viable option for a modern + high-speed data converter system. To achieve deterministic latency it is + recommend to use subclass 1 mode; +- Reduced number of octets-per-frame settings. The JESD204 standard allows for + any value between 1 and 256 to be used for the number of octets-per-frame; +- The following octets-per-frame are supported by the peripheral: 1, 2, 4 and + 1. (No longer applies starting from 1.07.a); +- Reduced number of frames-per-multi-frame settings. The following values are + supported by the peripheral: 1-32, with the additional requirement that F*K + is a multiple of 4. In addition F*K needs to be in the range of 4-256; +- No support for alignment character replacement when scrambling is disabled. + (No longer applies starting from 1.07.a). + +Additional Information +-------------------------------------------------------------------------------- + +- :dokuwiki:`JESD204 Glossary ` + +.. _axi_jesd204_rx_supported_devices: + +Supported Devices +-------------------------------------------------------------------------------- + +JESD204B Analog-to-Digital Converters +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- :adi:`AD6673 `: 80 MHz Bandwidth, Dual IF Receiver +- :adi:`AD6674 `: 385 MHz BW IF Diversity Receiver +- :adi:`AD6676 `: Wideband IF Receiver Subsystem +- :adi:`AD6677 `: 80 MHz Bandwidth, IF Receiver +- :adi:`AD6684 `: 135 MHz Quad IF Receiver +- :adi:`AD6688 `: RF Diversity and 1.2GHz BW Observation + Receiver +- :adi:`AD9207 `: 12-Bit, 6 GSPS, JESD204B/JESD204C + Dual Analog-to-Digital Converter +- :adi:`AD9208 `: 14-Bit, 3GSPS, JESD204B, + Dual Analog-to-Digital Converter +- :adi:`AD9209 `: 12-Bit, 4GSPS, JESD204B/C, Quad + Analog-to-Digital Converter +- :adi:`AD9213 `: 12-Bit, 10.25 GSPS, JESD204B, RF + Analog-to-Digital Converter +- :adi:`AD9234 `: 12-Bit, 1 GSPS/500 MSPS JESD204B, Dual + Analog-to-Digital Converter +- :adi:`AD9250 `: 14-Bit, 170 MSPS/250 MSPS, JESD204B, Dual + Analog-to-Digital Converter +- :adi:`AD9625 `: 12-Bit, 2.6 GSPS/2.5 GSPS/2.0 GSPS, + 1.3 V/2.5 V Analog-to-Digital Converter +- :adi:`AD9656 `: Quad, 16-Bit, 125 MSPS JESD204B 1.8 V + Analog-to-Digital Converter +- :adi:`AD9680 `: 14-Bit, 1.25 GSPS/1 GSPS/820 MSPS/500 + MSPS JESD204B, Dual Analog-to-Digital Converter +- :adi:`AD9683 `: 14-Bit, 170 MSPS/250 MSPS, JESD204B, + Analog-to-Digital Converter +- :adi:`AD9690 `: 14-Bit, 500 MSPS / 1 GSPS JESD204B, + Analog-to-Digital Converter +- :adi:`AD9691 `: 14-Bit, 1.25 GSPS JESD204B, + Dual Analog-to-Digital Converter +- :adi:`AD9694 `: 14-Bit, 500 MSPS JESD204B, Quad + Analog-to-Digital Converter +- :adi:`AD9695 `: 14-Bit, 1300 MSPS/625 MSPS, + JESD204B, Dual Analog-to-Digital Converter Analog-to-Digital Converter +- :adi:`AD9083 `: 16-Channel, 125 MHz Bandwidth, JESD204B + Analog-to-Digital Converter +- :adi:`AD9094 `: 8-Bit, 1 GSPS, JESD204B, Quad + Analog-to-Digital Converter + +JESD204B RF Transceivers +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- :adi:`AD9371 `: SDR Integrated, Dual RF Transceiver with + Observation Path +- :adi:`AD9375 `: SDR Integrated, Dual RF Transceiver with + Observation Path and DPD +- :adi:`ADRV9009 `: SDR Integrated, Dual RF Transceiver + with Observation Path +- :adi:`ADRV9008-1 `: SDR Integrated, Dual RF Receiver +- :adi:`ADRV9008-2 `: SDR Integrated, Dual RF + Transmitter with Observation Path + +JESD204B/C Mixed-Signal Front Ends +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- :adi:`AD9081 `: MxFE™ Quad, 16-Bit, 12GSPS RFDAC and + Quad, 12-Bit, 4GSPS RFADC +- :adi:`AD9082 `: MxFE™ QUAD, 16-Bit, 12GSPS RFDAC and + DUAL, 12-Bit, 6GSPS RFADC +- :adi:`AD9986 `: 4T2R Direct RF Transmitter and + Observation Receiver +- :adi:`AD9988 `: 4T4R Direct RF Receiver and Transmitter + +Technical Support +-------------------------------------------------------------------------------- + +Analog Devices will provide limited online support for anyone using the core +with Analog Devices components (ADC, DAC, Clock, etc) via the +:ez:`EngineerZone ` under the GPL license. If you would like +deterministic support when using this core with an ADI component, please +investigate a commercial license. Using a non-ADI JESD204 device with this core +is possible under the GPL, but Analog Devices will not help with issues you may +encounter. + +More Information +-------------------------------------------------------------------------------- + +- :ref:`JESD204 High-Speed Serial Interface Support ` diff --git a/docs/library/jesd204/axi_jesd204_rx/jesd204_rx_buffer_delay_timing.svg b/docs/library/jesd204/axi_jesd204_rx/jesd204_rx_buffer_delay_timing.svg new file mode 100644 index 000000000..2b18a760f --- /dev/null +++ b/docs/library/jesd204/axi_jesd204_rx/jesd204_rx_buffer_delay_timing.svg @@ -0,0 +1,4 @@ + + + +device_clkLMFC edgeRelease OpportunityBUFFER DELAY/4ab \ No newline at end of file diff --git a/docs/library/jesd204/axi_jesd204_rx/jesd204_rx_rx_data_timing.svg b/docs/library/jesd204/axi_jesd204_rx/jesd204_rx_rx_data_timing.svg new file mode 100644 index 000000000..fe68c008e --- /dev/null +++ b/docs/library/jesd204/axi_jesd204_rx/jesd204_rx_rx_data_timing.svg @@ -0,0 +1,4347 @@ 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--- /dev/null +++ b/docs/library/jesd204/axi_jesd204_rx/jesd204_rx_state_machine.svg @@ -0,0 +1,419 @@ + + + + + + + + + + + + + + + + reset + !disabled + PHY controller for whenall lanes are ready + + + RESET + Link State Machine + + All lanes are inthe DATA phase + At least fourconsecutive/K/ charactersare received + More than threeinvalid charactersare received + reset + + + INIT + + + CHECK + + DATA + + + + + At least oneinvalid characteris received + At least fourconsecutivevalid charactersare received + + + + + WAITFORPHY + + CGS + + DATA + Lane State Machine + diff --git a/docs/library/jesd204/axi_jesd204_rx/jesd204c_rx_emb_state_machine.svg b/docs/library/jesd204/axi_jesd204_rx/jesd204c_rx_emb_state_machine.svg new file mode 100644 index 000000000..220f67ea2 --- /dev/null +++ b/docs/library/jesd204/axi_jesd204_rx/jesd204c_rx_emb_state_machine.svg @@ -0,0 +1,395 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + Reset || Sync header alignment lost + + EMBINIT + + + EMBHUNT + + + An EoEMB received + + + EMBLOCK + + + Four consecutive correct EoMB received. + + + Unexpected EoMB or EoEMB received + Extendend Multi-BlockAlignment State Machine + Eight incorrect EoMBor EoEMB received. + diff --git a/docs/library/jesd204/axi_jesd204_rx/jesd204c_rx_state_machine.svg b/docs/library/jesd204/axi_jesd204_rx/jesd204c_rx_state_machine.svg new file mode 100644 index 000000000..62208d081 --- /dev/null +++ b/docs/library/jesd204/axi_jesd204_rx/jesd204c_rx_state_machine.svg @@ -0,0 +1,482 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + WAITBS + + DATA + + BLOCK SYNC + + reset + All lanes reached sync header allignment + + RESET + +   + + + + + + 64B66B Link State Machine + One of the lanes lostsync header allignment + All lanes reached multi-block allignmentand buffer was released + One of the lanes lostmulti-block allignment + One of the lanes lostsync header allignment + diff --git a/docs/library/jesd204/axi_jesd204_rx/octets_mapping.svg b/docs/library/jesd204/axi_jesd204_rx/octets_mapping.svg new file mode 100644 index 000000000..2fe83e2b4 --- /dev/null +++ b/docs/library/jesd204/axi_jesd204_rx/octets_mapping.svg @@ -0,0 +1,562 @@ + +OCTET_0_0OCTET_0_1OCTET_0_2OCTET_0_3OCTET_N_0OCTET_N_1OCTET_N_2OCTET_N_308N*32-321624N*32-24N*32N*32-16N*32-832RX_DATALane 0Lane N}}DATA_PATH_WIDTH = 4 diff --git a/docs/library/jesd204/axi_jesd204_rx/quadmxfe_linkbringup_204b_adc.svg b/docs/library/jesd204/axi_jesd204_rx/quadmxfe_linkbringup_204b_adc.svg new file mode 100644 index 000000000..879439d0a --- /dev/null +++ b/docs/library/jesd204/axi_jesd204_rx/quadmxfe_linkbringup_204b_adc.svg @@ -0,0 +1,5505 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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+ + + LMFC + + + + + + + + + + + + + + + + + + + + + + + + + + + + + SYSREF + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 6 + + 7 + + 8 + + + + + + + + + MxFE2Txbringup + MxFE3Txbringup + + + + + + + + diff --git a/docs/library/jesd204/axi_jesd204_tx/axi_jesd204_tx_204c.svg b/docs/library/jesd204/axi_jesd204_tx/axi_jesd204_tx_204c.svg new file mode 100644 index 000000000..a01213974 --- /dev/null +++ b/docs/library/jesd204/axi_jesd204_tx/axi_jesd204_tx_204c.svg @@ -0,0 +1,1074 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Lane 1 + Lane 2 + Lane n + + CONTROL + SYNC~ + SYSREF + + + + TX_DATA + TX_PHY0 + TX_PHY1 + TX_PHYn + + + + REGISTERMAP + + S_AXI + + + Status + Configuration + + Enable + + + + + + + s_axi_aclk + device_clk + + + irq + + + + + + + + 8B/10B or 64B/66B encoder + diff --git a/docs/library/jesd204/axi_jesd204_tx/axi_jesd204_tx_204c_64b66b.svg b/docs/library/jesd204/axi_jesd204_tx/axi_jesd204_tx_204c_64b66b.svg new file mode 100644 index 000000000..08f9b25c7 --- /dev/null +++ b/docs/library/jesd204/axi_jesd204_tx/axi_jesd204_tx_204c_64b66b.svg @@ -0,0 +1,598 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ... + + + + CRC + + + + + + + SCRAMBLER + + + + + + + + HEADERENCODER + + + + + + + + + + + + + + + 64 + 2 + EoEMB,LEMC + phy_header + + phy_data + + + + + + + + 64 + 64B/66B mode encoder + TX_DATA + Lane x + + + diff --git a/docs/library/jesd204/axi_jesd204_tx/axi_jesd204_tx_204c_8b10b.svg b/docs/library/jesd204/axi_jesd204_tx/axi_jesd204_tx_204c_8b10b.svg new file mode 100644 index 000000000..6796d4eb2 --- /dev/null +++ b/docs/library/jesd204/axi_jesd204_tx/axi_jesd204_tx_204c_8b10b.svg @@ -0,0 +1,576 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + CHARACTERREPLACEMENT + + + + + SCRAMBLER + + + + + ILAS GENERATION + + + Lane x + + + + + CGS GENERATION + + + + + + + + TX_DATA + ILAS data + + + + + + + TX_PHYx + 8B/10B mode encoder + + diff --git a/docs/library/jesd204/axi_jesd204_tx/dual_clock_operation.svg b/docs/library/jesd204/axi_jesd204_tx/dual_clock_operation.svg new file mode 100644 index 000000000..d5eedcec7 --- /dev/null +++ b/docs/library/jesd204/axi_jesd204_tx/dual_clock_operation.svg @@ -0,0 +1,252 @@ + + + + + + + + + + + + + + + + + + + PHY + Transport Layer + Application Layer + Link Layer + + + + 4:Nor8:N + + + + + + + + SYSREF + Gearbox + device clock + ref clock + link clock + + diff --git a/docs/library/jesd204/axi_jesd204_tx/index.rst b/docs/library/jesd204/axi_jesd204_tx/index.rst new file mode 100644 index 000000000..ee15f21aa --- /dev/null +++ b/docs/library/jesd204/axi_jesd204_tx/index.rst @@ -0,0 +1,1021 @@ +.. _axi_jesd204_tx: + +JESD204B/C Link Transmit Peripheral +================================================================================ + +.. hdl-component-diagram:: + +The Analog Devices JESD204B/C Link Transmit Peripheral implements the link layer +handling of a JESD204 transmit logic device. Implements the 8B/10B based link +layer defined in JESD204C standard that is similar to the link layer defined in +JESD204B. This includes handling of the SYSREF and SYNC~ and controlling the +:ref:`link state machine ` accordingly +as well as performing per lane scrambling and character replacement. It has +been designed for interoperability with +:ref:`Analog Devices JESD204B DAC converter products `. +Implements the 64B/66B based link layer defined in the JESD204C standard. +This includes handling of the SYSREF, per lane encoding of sync header, +scrambling as per data multi-block CRC generation. + +The type of link layer is selectable during implementation phase through the +``LINK_MODE`` synthesis parameter. + +To form a complete JESD204 transmit logic device it has to be combined with a +:ref:`PHY layer ` and +:ref:`transport layer ` peripheral. + +Features +-------------------------------------------------------------------------------- + +* Backwards compatibility with JESD204B; +* 64B/66B link layer defined in JESD204C; +* Subclass 0 and Subclass 1 support; +* Deterministic Latency (for Subclass 1 operation); +* Runtime re-configurability through memory-mapped register interface (AXI4); +* Interrupts for event notification; +* Diagnostics; +* Max Lanerate with 8B/10B mode: 15 Gbps; +* Max Lanerate with 64B/66B mode: 32 Gbps; +* Low Latency; +* Independent per lane enable/disable. + +.. + Utilization + -------------------------------------------------------------------------------- + + .. collapsible:: Detailed Utilization + + +---------------+---------+----+---+ + |Device Family |NUM_LANES|LUTs|FFs| + +===============+=========+====+===+ + |Intel Arria 10 |1 |TBD |TDB| + + +---------+----+---+ + | |2 |TBD |TBD| + + +---------+----+---+ + | |4 |TBD |TBD| + + +---------+----+---+ + | |8 |TBD |TBD| + +---------------+---------+----+---+ + |AMD Xilinx |1 |TBD |TBD| + |Artix 7 +---------+----+---+ + | |2 |TBD |TBD| + + +---------+----+---+ + | |4 |TBD |TBD| + + +---------+----+---+ + | |8 |TBD |TBD| + +---------------+---------+----+---+ + |AMD Xilinx |1 |TBD |TBD| + |Kintex 7 +---------+----+---+ + | |2 |TBD |TBD| + + +---------+----+---+ + | |4 |824 |897| + + +---------+----+---+ + | |8 |TBD |TBD| + +---------------+---------+----+---+ + |AMD Xilinx |1 |TBD |TBD| + |Virtex 7 +---------+----+---+ + | |2 |TBD |TBD| + + +---------+----+---+ + | |4 |TBD |TBD| + + +---------+----+---+ + | |8 |TBD |TBD| + +---------------+---------+----+---+ + +Files +-------------------------------------------------------------------------------- + +.. list-table:: + :header-rows: 1 + + * - Name + - Description + * - :git-hdl:`axi_jesd204_tx.v ` + - Verilog source for the peripheral. + * - :git-hdl:`axi_jesd204_tx_ip.tcl ` + - TCL script to generate the Vivado IP-integrator project for the + peripheral. + +Block Diagram +-------------------------------------------------------------------------------- + +.. image:: axi_jesd204_tx_204c.svg + :align: center + +AXI JESD204 TX Synthesis Configuration Parameters +-------------------------------------------------------------------------------- + +.. hdl-parameters:: + + * - ID + - Instance identification number. + * - NUM_LANES + - Maximum number of lanes supported by the peripheral. + * - NUM_LINKS + - Maximum number of links supported by the peripheral. + * - LINK_MODE + - | Decoder selection of the link layer. + | 1 - 8B/10B mode; + | 2 - 64B/66B mode. + * - DATA_PATH_WIDTH + - Data path width in bytes. Set it 4 in case of 8B/10B, 8 in case of + 64B/66B. + +JESD204 TX Synthesis Configuration Parameters +-------------------------------------------------------------------------------- + +.. hdl-parameters:: + :path: library/jesd204/jesd204_tx + + * - NUM_LANES + - Maximum number of lanes supported by the peripheral. + * - NUM_LINKS + - Maximum number of links supported by the peripheral. + * - LINK_MODE + - | Decoder selection of the link layer. + | 1 - 8B/10B mode; + | 2 - 64B/66B mode. + * - DATA_PATH_WIDTH + - Data path width in bytes. Set it to 4 in case of 8B/10B, 8 in case of + 64B/66B. + * - TPL_DATA_PATH_WIDTH + - Data path width in bytes towards transport layer. Must be greater or + equal to ``DATA_PATH_WIDTH``. Must be a power of 2 integer multiple of + the F parameter. + * - ASYNC_CLK + - Set this parameter to 1 if the link clock and the device clocks have + different frequencies, or if they have the same frequency but a + different source. If set, synchronizing logic and a gearbox of ratio + ``DATA_PATH_WIDTH``:``TPL_DATA_PATH_WIDTH`` is inserted to do the rate + conversion. If not set, ``TPL_DATA_PATH_WIDTH`` must match + ``DATA_PATH_WIDTH``, the same clock must be connected to ``clk`` and + ``device_clk`` inputs. + +AXI JESD204 TX Signal and Interface Pins +-------------------------------------------------------------------------------- + +.. hdl-interfaces:: + + * - s_axi_aclk + - All ``S_AXI`` signals and ``irq`` are synchronous to this clock. + * - s_axi_aresetn + - Resets the internal state of the peripheral. + * - s_axi + - Memory mapped AXI-lite bus that provides access to modules register map. + * - irq + - Interrupt output of the module. Is asserted when at least one of the + modules interrupt is pending and enabled. + * - device_clk + - :dokuwiki:`Device clock ` + for the JESD204 interface. Its frequency must be link clock \* ``DATA_PATH_WIDTH`` / + ``TPL_DATA_PATH_WIDTH`` + * - device_reset + - Reset active high synchronous with the + :dokuwiki:`Device clock `. + +JESD204 TX Signal and Interface Pins +-------------------------------------------------------------------------------- + +.. hdl-interfaces:: + :path: library/jesd204/jesd204_tx + + * - clk + - :dokuwiki:`Link clock ` + for the JESD204 interface. Must be line clock/40 for correct + operation in 8B/10B mode, line clock/66 in 64B/66B mode. + * - reset + - Reset active high synchronous with the + :dokuwiki:`Link clock `. + * - tx_data + - Transmit data. + * - sync + - sync[m-1:0] is JESD204B SYNC~ (or SYNC_N) signal, available in 8B/10B mode. + (``0 <= n < NUM_LINKS``) + * - sysref + - JESD204 SYSREF signal. + * - tx_phy* + - n-th lane of the JESD204 interface (``0 <= n < NUM_LANES``). + +Register Map +-------------------------------------------------------------------------------- + +.. hdl-regmap:: + :name: JESD_TX + :no-type-info: + +Theory of Operation +-------------------------------------------------------------------------------- + +The JESD204B/C transmit peripheral consists of two main components. The register +map and the link processor. Both components are fully asynchronous and are +clocked by independent clocks. The register map is in the ``s_axi_aclk`` clock +domain, while the link processor is in the ``clk`` and ``device_clk`` clock +domain. + +The register map is used to configure the operational parameters of the link +processor as well as to query the current state of the link processor. The link +processor itself is responsible for handling the JESD204 link layer protocol. + +Interfaces and Signals +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Register Map Configuration Interface +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +The register map configuration interface can be accessed through the AXI4-Lite +``S_AXI`` interface. The interface is synchronous to the ``s_axi_aclk``. The +``s_axi_aresetn`` signal is used to reset the peripheral and should be asserted +during system startup until the ``s_axi_aclk`` is active and stable. +De-assertion of the reset signal should by synchronous to ``s_axi_aclk``. + +JESD204B Control Signals +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +The ``sync`` and ``sysref`` signals corresponds to the SYNC~ and SYSREF signals +of the JESD204 specification. These are signals generated externally and need to +be connected to the peripheral for correct operation. + +In 8B/10B link layer the ``sysref`` signal is optional and only required to +achieve deterministic latency in subclass 1 mode operation. If the ``sysref`` +signal is not connected software needs to configure the peripheral accordingly +to indicate this. In 64B/66B link layer the ``sysref`` signal is mandatory. + +When the ``sysref`` signal is used, in order to ensure correct operation, it is +important that setup and hold of the external signal relative to the +``device_clk`` signal are met. Otherwise deterministic latency can not be +guaranteed. + +Transceiver Interface (TX_PHYn) +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +For each lane the peripheral has one corresponding ``TX_PHY`` interface. These +interfaces provide the pre-processed physical layer data. The TX_PHY interfaces +should be connected to the down-stream physical layer transceiver peripheral. + +The physical layer peripheral receiving data from these interfaces are +responsible for performing the final 8b10b mapping as well as serializing the +data and transmitting it on the physical CML differential high-speed serial +lane. + +.. _axi_jesd204_tx_user_data: + +User Data Interface (TX_DATA) +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +User data is accepted on the the AXI4-Stream ``TX_DATA`` interface. The +interface is a reduced AXI4-Stream interface and only features the TREADY flow +control signal, but not the TVALID flow control signal. The behavior of the +interface is as if the TVALID signal was always asserted. This means as soon as +tx_ready is asserted a continuous stream of user data must be provided on +tx_data. + +.. wavedrom:: + :align: center + + {signal: + [ + ['TX_DATA', + { name: "device_clk", wave: 'P.........' }, + { name: "tx_data", wave: "x...======", + data: ["D0", "D1", "D2", "D3", "D4", "..."] }, + { name: 'tx_ready', wave: '0...1.....' }, + ] + ], + foot: + {text: + ['tspan',{dx:'-45'}, 'Link Inicialization', ['tspan', {dx:'60'}, + 'User Data Phase'],], + } + } + +After reset and during link initialization the ``tx_ready`` signal is +de-asserted. As soon as the :ref:`User Data Phase ` is +entered the ``tx_ready`` will be asserted to indicate that the peripheral is now +accepting and processing the data from the ``tx_data`` signal. The ``tx_ready`` +signal stays asserted until the link is either deactivated or re-initialized. + +.. image:: octets_mapping.svg + :align: right + +Typically the ``TX_DATA`` interface is connected to a JESD204B transport layer +peripheral that provides framed and lane mapped data. The internal data path +width of the peripheral is four, this means that four octets per lane are +processed in parallel. When in the user data phase the peripheral expects to +receive data for four octets for each lane in each beat. + +This means that ``TX_DATA`` interface is ``DATA_PATH_WIDTH`` \* 8 \* +``NUM_LANES`` bits wide. With each block of consecutive ``DATA_PATH_WIDTH`` \* +8 bits corresponding to one lane. The lowest ``DATA_PATH_WIDTH`` \* 8 bits +correspond to the first lane, while the highest ``DATA_PATH_WIDTH`` \* 8 bits +correspond to the last lane. +E.g. for 8B/10B mode where DATA_PATH_WIDTH=4. Each lane specific 32-bit block +corresponds to four octets each 8 bits wide. The temporal ordering of the +octets is from LSB to MSB, this means the octet placed in the lowest 8 bits is +transmitted first, the octet placed in the highest 8 bits is transmitted last. + +Data corresponding to lanes that have been disabled are ignored and their value +is don't care. + +Configuration Interface +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +The peripheral features a register map configuration interface that can be +accessed through the AXI4-Lite ``S_AXI`` port. The register map can be used to +configure the peripherals operational parameters, query the current status of +the device and query the features supported by the device. + +Peripheral Identification and HDL Synthesis Settings +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +The peripheral contains multiple registers that allow the identification of the +peripheral as well as the discovery of features that were configured at HDL +synthesis time. Apart from the ``SCRATCH`` register all registers in this +section are read-only and write to them will be ignored. + +The ``VERSION`` (``0x000``) register contains the version of the peripheral. The +version determines the register map layout and general features supported by the +peripheral. The version number follows `semantic versioning `__. +Increments in the major number indicate backward incompatible changes, +increments in the minor number indicate backward compatible changes, patch +letter increments indicate a bug fix. + +The ``PERIPHERAL_ID`` (``0x004``) register contains the value of the ``ID`` HDL +configuration parameter that was set during synthesis. Its primary function is +to allow to distinguish between multiple instances of the peripheral in the same +design. + +The ``SCRATCH`` (``0x008``) register is a general purpose 32-bit register that +can be set to an arbitrary values. Reading the register will yield the value +previously written (The value will be cleared when the peripheral is reset). Its +content does not affect the operation of the peripheral. It can be used by +software to test whether the register map is accessible or store custom +peripheral associated data. + +The ``IDENTIFICATION`` (``0x00c``) register contains the value of ``"204T"``. +This value is unique to this type of peripheral and can be used to ensure that +the peripheral exists at the expected location in the memory mapped IO register +space. + +The ``SYNTH_NUM_LANES`` (``0x010``) register contains the value of the +``NUM_LANES`` HDL configuration parameter that was set during synthesis. It +corresponds to the maximum of lanes supported by the peripheral. Possible values +are between ``1`` and ``32``. + +The ``SYNTH_DATA_PATH_WIDTH`` (``0x014``) register contains the value of the +internal data path width per lane in octets. This is how many octets are +processed in parallel on each lane and affects the restrictions of possible +values for certain runtime configuration registers. The value is encoded as the +log2() of the data path width. Possible values are: + +#. Internal data path width is 2; +#. Internal data path width is 4; +#. Internal data path width is 8. + +Interrupt Handling +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +Interrupt processing is handled by three closely related registers. All three +registers follow the same layout, each bit in the register corresponds to one +particular interrupt. + +When an interrupt event occurs it is recorded in the ``IRQ_SOURCE`` (``0x088``) +register. For a recorded interrupt event the corresponding bit is set to 1. If +an interrupt event occurs while the bit is already set to 1 it will stay set to +1. + +The ``IRQ_ENABLE`` (``0x080``) register controls how recorded interrupt events +propagate. An interrupt is considered to be enabled if the corresponding bit in +the ``IRQ_ENABLE`` register is set to 1, it is considered to be disabled if the +bit is set to 0. + +Disabling an interrupt will not prevent it from being recorded, but only its +propagation. This means if an interrupt event was previously recorded while the +interrupt was disabled and the interrupt is being enabled the interrupt event +will then propagate. + +An interrupt event that has been recorded and is enabled propagates to the +``IRQ_PENDING`` (``0x084``) register. The corresponding bit for such an +interrupt will read as 1. Disabled or interrupts for which no events have been +recorded will read as 0. Also if at least one interrupt has been recorded and is +enabled the external ``irq`` signal will be asserted to signal the IRQ event to +the upstream IRQ controller. + +A recorded interrupt event can be cleared (or acknowledged) by writing a 1 to +the corresponding bit to either the ``IRQ_SOURCE`` or ``IRQ_PENDING`` register. +It is possible to clear multiple interrupt events at the same time by setting +multiple bits in a single write operation. + +For more details regarding interrupt operation see the +:ref:`interrupts section ` of this document. + +Link Control +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +The ``LINK_DISABLE`` (``0x0c0``) register is used to control the link state and +switch between enabled and disabled. While the link is disabled its state +machine will remain in reset and it will not react to any external event like +the ``SYSREF`` or ``SYNC~`` signals. + +Writing a 0 to the ``LINK_DISABLE`` register will enable the link. While the +link state is changing from disabled to enabled it will go through a short +initialization procedure, which will take a few clock cycles. To check whether +the initialization procedure has completed and the link is fully operational the +``LINK_STATE`` (``0x0c4``) register can be checked. This register will contain a +0 when the link is fully enabled and will contain a 1 while it is disabled or +going through the initialization procedure. + +Writing a 1 to the ``LINK_DISABLE`` register will immediately disable the link. + +The ``EXTERNAL_RESET`` (``[1]``) bit in the ``LINK_STATE`` register indicates +whether the external link reset signal is asserted (``1``) or de-asserted +(``0``). When the external link reset is asserted the link is disabled +regardless of the setting of ``LINK_DISABLE``. The external link reset is +controlled by the fabric and might be asserted if the link clock is not stable +yet. + +Multi-link Control +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +A multi-link is a link where multiple converter devices are connected to a +single logic device (FPGA). All links involved in a multi-link are synchronous +and established at the same time. For an 8B/10B TX link, this means that the +FPGA receives multiple SYNC signals, one for each link. + +For a 8B/10B link the ``MULTI_LINK_DISABLE`` register allows activating or +deactivating each ``SYNC~`` lines independently. This is useful when depending +on the use case profile some converter devices are supposed to be disabled. + +Link Configuration +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +The link configuration registers control certain aspects of the runtime behavior +of the peripheral. Since the JESD204 standard does now allow changes to link +configuration while the link is active the link configuration registers can only +be modified while the link is disabled. As soon as it is enabled the +configuration registers turn read-only and any writes to them will be ignored. + +The ``LANES_DISABLE`` (``0x200``) register allows to disable individual lanes. +Each bit in the register corresponds to a particular lane and indicates whether +that lane is enabled or disabled. Bit 0 corresponds to the first lane, bit 1 to +the second lane and so on. A value of 0 for a specific bit means the +corresponding lane is enabled, a value of 1 means the lane is disabled. A +disabled lane will not transmit any data when the link is otherwise active. By +default, all lanes are enabled. + +The ``LINK_CONF0`` register configures the octets-per-frame and +frames-per-multi-frame settings of the link. The ``OCTETS_PER_FRAME`` +(``[18:16]``) field should be set to the number of octets-per-frame minus 1 (F - +1). The ``OCTETS_PER_MULTIFRAME`` (``[9:0]``) field should be set to the number +of octets-per-frame multiplied by the number of frames-per-multi-frame minus 1 +(FxK - 1). For correct operation FxK must be a multiple of ``DATA_PATH_WIDTH``. +In 64B/66B mode this field matches and also represents the number of octets per +extended multiblock (Ex32x8 - 1). + +The ``LINK_CONF1`` register controls the optional link level processing stages. +The ``SCRAMBLER_DISABLE`` (``[0]``) bit controls whether scrambling of the +transmitted user data is enabled or disabled. A value of 0 enables scrambling +and a value of 1 disables it. In 64B/66B mode scrambling must be always enabled. +The ``CHAR_REPLACEMENT_DISABLE`` (``[1]``) bit controls whether alignment +character replacement is performed or not. A value of 0 enables character +replacement and a value of 1 disables it. For correct operation, character +replacement must be disabled when scrambling is disabled otherwise undefined +behavior might occur. + +Both the transmitter as well as receiver device on the JESD204 link need to be +configured with the same settings for scrambling/descrambling and character +replacement for correct operation. + +It is recommended to leave both scrambling as well as alignment character +replacement enabled during normal operation and only disable it for debugging or +testing purposes. + +Character replacement is used only in 8B/10B links and completely disregarded in +64B/66B mode. + +The ``LINK_CONF2`` (``0x240``) register contains configuration data that affects +the transitions of the :ref:`link state machine `. If the +``CONTINUOUS_CGS`` (``[0]``) bit is set the state machine will remain in the CGS +phase indefinitely and send repeated :dokuwiki:`/K/ control character +`. +If the ``CONTINUOUS_ILAS`` (``[1]``) bit is set the state machine will remain +in the ILAS phase indefinitely and send repeated ILAS sequences. If the +``SKIP_ILAS`` (``[2]``) bit is set the state machine will directly transition +to the DATA phase from the CGS phase without going through the ILAS phase. +The ``LINK_CONFIG2`` register is used only in 8B/10B links and completely +disregarded in 64B/66B mode. + +The ``LINK_CONF3`` (``0x244``) register configures the duration of the ILAS +sequence in number of multi-frames. Its value is equal to the number of +multi-frames minus one. In the current iteration of the peripheral, this +register is read-only and the ILAS will always last for four multi-frames. The +``LINK_CONFIG3`` register is used only in 8B/10B links and completely +disregarded in 64B/66B mode. + +ILAS Configuration Data +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +For 8B/10B link layer the ILAS configuration data registers contain the +configuration data that is sent during the ILAS phase. Similar to the link +configuration registers, the ILAS configuration data registers can only be +modified while the link is disabled and turn read-only as soon as it is enabled. + +For each lane there is a set of four registers (``LANEn_ILAS0``, +``LANEn_ILAS1``, ``LANEn_ILAS2``, ``LANEn_ILAS3``) that allow access to the 14 +configuration data octets. Aside from the ``LID`` and ``FCHK`` fields all fields +for each of the lanes map to the same internal storage. This means only the +``LID`` and ``FCHK`` fields can be configured with per-lane configuration data, +all other fields must be set to the same value for all lanes. + +SYSREF Handling +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +The external SYSREF signal is used to align the internal local multiframe clocks +(LMFC)/ local-multiblock-clock (LEMC) between multiple devices on the same link. + +The ``SYSREF_CONF`` (``0x100``) register controls the behavior of the SYSREF +capture circuitry. Setting the ``SYSREF_DISABLE`` (``[0]``) bit to 1 disables +the SYSREF handling. All external SYSREF events are ignored and the LMFC/LEMC is +generated internally. For Subclass 1 operation SYSREF handling should be enabled +and for Subclass 0 operation it should be disabled. + +The ``SYSREF_LMFC_OFFSET`` (``0x104``) register allows modifying the offset +between the SYSREF rising edge and the rising edge of the LMFC/LEMC. Must be a +multiple of ``DATA_PATH_WIDTH``. + +For optimal operation, it is recommended that all device on a JESD204 link +should be configured in a way so that the total offset between + +The value of the ``SYSREF_LMFC_OFFSET`` register must be set to a value smaller +than the configured number of octets-per-multiframe (``OCTETS_PER_MULTIFRAME``), +otherwise undefined behavior might occur. + +The ``SYSREF_STATUS`` (``0x108``) register allows monitoring the status of the +SYSREF signals. ``SYSREF_DETECTED`` (``[0]``) bit indicates that the peripheral +as observed a SYSREF event. The ``SYSREF_ALIGNMENT_ERROR`` (``[1]``) bit +indicates that a SYSREF event has been observed which was unaligned, in regards +to the LMFC period, to a previously recorded SYSREF event. + +All bits in the ``SYSREF_STATUS`` register are write-to-clear. All bits will +also be cleared when the link is disabled. + +Note that the ``SYSREF_STATUS`` register will not record any events if SYSREF +operation is disabled or the JESD204 link is disabled. + +Link Status +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +All link status registers are read-only. While the link is disabled some of the +link status registers might contain bogus values. Their content should be +ignored until the link is fully enabled. + +The ``STATUS_STATE`` (``[1:0]``) field of the ``LINK_STATUS`` (``0x280``) +register indicates the state of the +:ref:`8B/10B link state machine ` +or 64B/66B link state machine depending on the selected encoder. Possible +values are: + +Possible values for a 8B/10B link are: + +- 0: WAIT phase; +- 1: CGS phase; +- 2: ILAS phase; +- 3: DATA phase. + +Possible values for a 64B/66B link are: + +- 0: WAIT phase; +- 3: DATA phase. + +The ``STATUS_SYNC`` (``[4]``) field represents the raw state of the external +SYNC~ and can be used to monitor whether the JESD204B converter device has +requested link synchronization. This is available only for 8B/10B links. + +Manual Synchronization Request +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +For 8B/10B links the ``MANUAL_SYNC_REQUEST`` (``0x248``) register can be used to +transition the link state from the WAIT phase to the CGS phase in the absence of +an external synchronization request. This is useful for test cases where the +peripheral is connected to signal analyzer instead of a JESD204B receiver +device. + +Writing a 1 to this register will trigger a manual synchronization request. +Writing the register while the link is disabled or writing a 0 to the register +has no effect. The register is self-clearing and reading it will always return +0. + +This feature is useful if the ``SYNC~`` is stuck high from some reason. Setting +the ``MANUAL_SYNC_REQUEST`` bit will bring out the Tx link peripheral from +``CGS`` and will continue with sending ``ILAS`` and ``DATA`` information. After +this, the ``SYNC_STATUS`` bit would read high, and ``LINK_STATE`` would be +``DATA``. + +If the ``SYNC~`` is stuck low, writing the ``MANUAL_SYNC_REQUEST`` would not do +too much, the link would stay in ``CGS`` and wait the de-assertion of ``SYNC~`` +which won't happen. In this case the ``SYNC_STATUS`` would stay low and +``LINK_STATE``\ would be ``CGS``. + +Clock Monitor +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +The ``LINK_CLK_FREQ`` (``0x0c8``) register allows to determine the clock rate of +the link clock (``clk``) relative to the AXI interface clock (``s_axi_aclk``). +This can be used to verify that the link clock is running at the expected rate. + +The ``DEVICE_CLK_FREQ`` (``0x0cc``) register allows to determine the clock rate +of the device clock (``device_clk``) relative to the AXI interface clock +(``s_axi_aclk``). This can be used to verify that the device clock is running at +the expected rate. + +The number is represented as unsigned 16.16 format. Assuming a 100MHz processor +clock this corresponds to a resolution of 1.523kHz per LSB. A raw value of 0 +indicates that the link clock is currently not active. + +.. _axi_jesd204_tx_interrupts: + +Interrupts +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +The core does not generate interrupts. + +8B/10B Link +-------------------------------------------------------------------------------- + +.. image:: axi_jesd204_tx_204c_8b10b.svg + :align: center + +.. _axi_jesd204_tx_8b_10b_link_state_machine: + +8B/10B Link State Machine +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. image:: jesd204_tx_state_machine.svg + :align: right + +The peripheral can be in one of four main operating phases: WAIT, CGS, ILAS or +DATA. Upon reset the peripheral starts in the WAIT phase. The CGS and ILAS +phases are used during the initialization of the JESD204B link. The DATA phase +is used during normal operation when user data is transmitted across the +JESD204B link. + +Wait Phase (WAIT) +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +The WAIT phase is the default state entered during reset. While disabled the +peripheral will stay in the WAIT phase. When enabled, the peripheral will stay +in the WAIT phase until a synchronization request is received. + +A synchronization request can either be generated manually through the register +map configuration interface or by one of the JESD204B receivers by asserting the +``SYNC~`` signal. Once a synchronization request is received the peripheral +transitions to the CGS phase. + +During the WAIT phase the peripheral will continuously transmit +:dokuwiki:`/K/ control character ` +on each of the ``TX_PHYn`` interfaces. + +If at any point the peripheral is disabled, it will automatically transition +back to the WAIT state. + +Lanes that have been disabled in the register map configuration interface, will +behave as if the link was in the WAIT state regardless of the actual state. + +Code Group Synchronization Phase (CGS) +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +During the CGS phase the peripheral will continuously transmit +:dokuwiki:`/K/ control character ` +on each of the ``TX_PHYn`` interfaces. + +The peripheral will stay in the CGS phase until all of following conditions are +satisfied: + +- The synchronization request is de-asserted; +- The CGS phase has lasted for at least the configured minimum CGS duration (1 + frame + 9 octets by default); +- The end of a multi-frame is reached (This means the next phase will start at + the beginning of a multi-frame); +- The SYSREF signal has been captured and the LMFC is properly aligned. + +If the peripheral is configured for continuous CGS operation it will stay in the +CGS phase indefinitely regardless of whether the above conditions are met or +not. + +By default the peripheral will transition to the ILAS phase at the end of the +CGS phase. If the core is configured to skip the ILAS phase it will instead +directly transition to the DATA phase. + +Initial Lane Alignment Sequence Phase (ILAS) +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +During the ILAS phase the peripheral transmits the initial lane alignment +sequence. The transmitted ILAS consists of four multi-frames. The first octet of +each multi-frame is the +:dokuwiki:`/R/ control character ` +and the last octet of each multi-frame is the +:dokuwiki:`/A/ control character `. + +During the second multi-frame the link configuration data is transmitted from +the 3rd to 16th octet. The second octet of the second multi-frame is the +:dokuwiki:`/Q/ control character ` +to indicate that this multi-frame carries configuration data. The ILAS +configuration data sequence can be programmed through the register map +configuration interface. + +All other octets of the ILAS sequence will contain the numerical value +corresponding to the position of the octet in the ILAS sequence (E.g. the fifth +octet of the first multi-frame contains the value 4). + +.. wavedrom:: + + { + signal: + [ + { name: "ILAS", wave: "x35x|.54378x|x5435x|.5435x|x54", data: ["/R/", + "D", "D", "/A/", "/R/", "/Q/", "C", "D", "/A/", "/R/", "D", "D", + "/A/", "/R/", "D", "D", "A"] }, + { name: "LMFC", wave: 'pH..|l..H...|l..H..|l..H..|l..' }, + ], + config: { skin: 'narrow' } + } + +By default the ILAS is transmitted for a duration of 4 multi-frames. After the +last ILAS multi-frame the peripheral switches to the DATA phase. + +If the peripheral is configured for continuous ILAS operation it will instead +remain in the ILAS phase indefinitely. In continuous ILAS mode the peripheral +will transition back to the first multi-frame of the ILAS sequence after the +last multi-frame has been transmitted. + +In accordance with the JESD204B standard the data transmitted during the ILAS +phase is not scrambled regardless of whether scrambling is enabled or not. + +.. _axi_jesd204_tx_user_data_phase: + +User Data Phase (DATA) +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +The DATA phase is the main operating mode of the peripheral. In this phase it +will receive transport layer data at the ``TX_DATA`` port, split it onto the +corresponding lanes and perform per-lane processing of the data according to the +peripherals configuration. When the peripheral enters the DATA phase the +``ready`` signal of the ``TX_DATA`` will be asserted to indicate that transport +layer data is now accepted. + +By default the data transmitted on each lane will be scrambled. Scrambling can +optionally be disabled via the register map configuration interface. Scrambling +is enabled or disabled for all lanes equally. + +Scrambling reduces data-dependent effects, which can affect both the analog +performance of the data converter as well as the bit-error rate of JESD204B +serial link, therefore it is highly recommended to enable scrambling. + +The peripheral also performs per-lane alignment character replacement. Alignment +character replacement will replace under certain predictable conditions (i.e. +the receiver can recover the replaced character) the last octet in a frame or +multi-frame. Replaced characters at the end of a frame, that is also the end of +a multi-frame, are replaced by the +:dokuwiki:`/A/ character `. +Replaced characters at the end of a frame, that is not the end of a +multi-frame, are replaced by the +:dokuwiki:`/F/ character `. +Alignment characters can be used by the receiver to ensure proper frame +and lane alignment. + +Alignment character replacement can optionally be disabled via the register map +configuration interface. Alignment character replacement is enabled or disabled +for all lanes equally. Alignment character replacement is only available when +scrambling is enabled and must be disabled when scrambling is disabled, +otherwise undefined behavior might occur. + +Data on the ``TX_DATA`` port corresponding to a disabled lane is ignored. + +8B/10B Multi-endpoint TX link establishment +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +In a multi-endpoint configuration one link transmit peripheral connects to +several endpoints/converter devices. In such cases the link is established +only when all enabled endpoints reach the DATA phase. For that all endpoints +must pass through CGS and ILAS stages. Depending on the software +implementation that controls the converter devices the endpoints can be +enabled at different moments. The link transmit peripheral will send CGS +characters until all enabled endpoints succeeded character alignment and +signalize that through the de-assertion of ``SYNC~`` signal. +In the below example we have a multi-point link of four endpoints +(``NUM_LINKS`` = 4): + +.. image:: quadmxfe_linkbringup_204b_dac.svg + :align: center + +.. note:: + + The physical layer is not depicted on purpose. JRXn represents the link + layer counterpart in the converter device/endpoint *n*. + +The steps of the link bring-up are presented below: + +- **1** - Link transmit peripheral is enabled, will start to send ``CGS`` + characters on all lanes regardless of the state of the ``SYNC~`` signal; +- **2,3,4,5** - JESD Receive block of ADC enabled, its corresponding ``SYNC~`` + pin is pulled low. The timing depends on the software implementation that + controls the ADC; +- **6** - In Subclass 1 (SC1) ``SYSREF`` is captured and ``LMFC`` in the + FPGA and converter device is adjusted; +- **7** - Once the ``CGS`` characters are received correctly, on the next + Frame clock boundary in SC0 or ``LMFC`` boundary in SC1 the ``SYNC~`` is + de-asserted; +- **8** - Once all enabled endpoints (not masked by ``MULTI_LINK_DISABLE``) + de-assert the ``SYNC~`` signal, on the next Frame clock boundary for SC0 or + the next ``LMFC`` boundary for SC1, the transmit peripheral will start + sending the ``ILAS`` sequence, then ``MFRAMES_PER_ILAS`` (typically 4) + ``LMFC`` periods later the actual ``DATA``. **In SC1 if** ``SYSREF`` **is not + captured the link transmit peripheral will stay in CGS state.** + +Diagnostics +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +:dokuwiki:`Troubleshooting JESD204B Tx links ` + +64B/66B Link +-------------------------------------------------------------------------------- + +.. image:: axi_jesd204_tx_204c_64b66b.svg + :align: center + +The 64-bit wide datapath of the link layer is fairly simple, the only mandatory +part of the 64B66B link layer datapath is the scrambler. This must be active +during the operation of the link, however for debug purposes can be bypasses +with a control register ``SCRAMBLER_DISABLE``. + +The data is accepted from the upstream transport layer core once the local +extended multiblock clock (LEMC) is adjusted to the captured SYSREF signal. Once +this happened the data will be accepted without interruption until the link is +disabled since there is no back-pressure from the physical layer. + +If the core does not receives at least one SYSREF pulse it will not pass any +data from transport layer to physical layer. + +For each multiblock sent on the data interface a CRC is calculated which is sent +on the 2-bit sync header stream during the next multiblock period. Beside the +CRC the sync header stream contains synchronization information to mark the +boundary of the multiblock and extended multiblocks. + +Dual clock operation +-------------------------------------------------------------------------------- + +In case ``ASYNC_CLK`` parameter is set, a gearbox with 4:N (204B) or 8:N (204C) +ratio is enabled in the link layer peripherals, where N depends on the F +parameter of the link. The goal of the gearbox is to have at the transport +layer interface a data width that contains an integer number of frames per +every device clock cycle (each beat) so an integer number of samples can be +delivered/consumed to/from the application layer aligned to SYSREF ensuring +deterministic latency in modes where N'=12 or F!=1,2,4. + +.. image:: dual_clock_operation.svg + :align: center + +The gearbox ratio corresponds with the ratio of the link layer interface data +width towards physical layer and transport layer in octets. The interface width +towards the physical layer in 8B/10B (204B) mode depends on the DATA_PATH_WIDTH +synthesis parameter, and can be either 4 octets (default) or 8 octets. In 204B +mode the util_adxcvr supports only data width of 4 octets. In 64b66b (aka 204C) +mode the data width towards the physical interface is always 8 octets. + +The data path width towards the transport layer is defined by the +TPL_DATA_PATH_WIDTH synthesis parameter. + +The following rules apply: + +- TPL_DATA_PATH_WIDTH >= DATA_PATH_WIDTH; +- TPL_DATA_PATH_WIDTH = m x F; where m is a positive integer, power of 2. + +The link clock and device clock ratio should be the inverse of the +DATA_PATH_WIDTH : TPL_DATA_PATH_WIDTH ratio. + +In this context the link clock will be lane rate/40 or lane rate/80 for 204B +depending on DATA_PATH_WIDTH and lane rate / 66 for 204C 64B/66B, however the +device clock could vary based in the F parameter. + +Software Support +-------------------------------------------------------------------------------- + +.. warning:: + + To ensure correct operation it is highly recommended to use the + Analog Devices provided JESD204B software packages for interfacing the + peripheral. Analog Devices is not able to provide support in case issues arise + from using custom low-level software for interfacing the peripheral. + +- :dokuwiki:`JESD204B Transmit Linux Driver Support ` + +Restrictions +-------------------------------------------------------------------------------- + +During the design of the peripheral the deliberate decision was made to support +only a subset of the features mandated by the JESD204B standard for transmitter +logic devices. The reasoning here is that the peripheral has been designed to +interface to Analog Devices JESD204B DAC converter devices and features that are +either not required or not supported by those converter devices would otherwise +lie dormant in peripheral and never be used. Instead the decision was made to +not implement those unneeded features even when the JESD204B standard requires +them for general purpose JESD204B transmitter logic devices. As Analog Devices +DAC converter devices with new requirements are released the peripheral will be +adjusted accordingly. + +This approach allows for a leaner design using less resources, allowing for +lower pipeline latency and a higher maximum device clock frequency. + +The following lists where the peripheral deviates from the standard: + +- No subclass 2 support. JESD204B subclass 2 has due to its implementation + details restricted applicability and is seldom a viable option for a modern + high-speed data converter system. To achieve deterministic latency it is + recommend to use subclass 1 mode; +- Reduced number of octets-per-frame settings. The JESD204B standard allows for + any value between 1 and 256 to be used for the number of octets-per-frame; +- The following octets-per-frame values are supported by the peripheral: 1, 2, + 4 and 8.(No longer applies starting from 1.06.a); +- Reduced number of frames-per-multi-frame settings. The following values are + supported by the peripheral: 1-32, with the additional requirement that F*K + is a multiple of 4. In addition F*K needs to be in the range of 4-256; +- No support for alignment character replacement when scrambling is + disabled.(No longer applies starting from 1.06.a). + +.. _axi_jesd204_tx_supported_devices: + +Supported Devices +-------------------------------------------------------------------------------- + +JESD204B Digital-to-Analog Converters +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- :adi:`AD9135 `: Dual, 11-Bit, high dynamic, 2.8 GSPS, + TxDAC+® Digital-to-Analog Converter +- :adi:`AD9136 `: Dual, 16-Bit, 2.8 GSPS, TxDAC+® + Digital-to-Analog Converter +- :adi:`AD9144 `: Quad, 16-Bit, 2.8 GSPS, TxDAC+® + Digital-to-Analog Converter +- :adi:`AD9152 `: Dual, 16-Bit, 2.25 GSPS, TxDAC+ + Digital-to-Analog Converter +- :adi:`AD9154 `: Quad, 16-Bit, 2.4 GSPS, TxDAC+® + Digital-to-Analog Converter +- :adi:`AD9161 `: 11-Bit, 12 GSPS, RF Digital-to-Analog + Converter +- :adi:`AD9162 `: 16-Bit, 12 GSPS, RF Digital-to-Analog + Converter +- :adi:`AD9163 `: 16-Bit, 12 GSPS, RF DAC and Digital + Upconverter +- :adi:`AD9164 `: 16-Bit, 12 GSPS, RF DAC and Direct Digital + Synthesizer +- :adi:`AD9172 `: Dual, 16-Bit, 12.6 GSPS RF DAC with + Channelizers +- :adi:`AD9173 `: Dual, 16-Bit, 12.6 GSPS RF DAC with + Channelizers +- :adi:`AD9174 `: Dual, 16-Bit, 12.6 GSPS RF DAC and Direct + Digital Synthesizer +- :adi:`AD9175 `: Dual, 11-Bit/16-Bit, 12.6 GSPS RF DAC with + Wideband Channelizers +- :adi:`AD9176 `: Dual, 16-Bit, 12.6 GSPS RF DAC with + Wideband Channelizers +- :adi:`AD9177 `: Quad, 16-Bit, 12 GSPS RF DAC with + Wideband Channelizers + +JESD204B RF Transceivers +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- :adi:`AD9371 `: SDR Integrated, Dual RF Transceiver with + Observation Path +- :adi:`AD9375 `: SDR Integrated, Dual RF Transceiver with + Observation Path and DPD +- :adi:`ADRV9009 `: SDR Integrated, Dual RF Transceiver + with Observation Path +- :adi:`ADRV9008-1 `: SDR Integrated, Dual RF Receiver +- :adi:`ADRV9008-2 `: SDR Integrated, Dual RF + Transmitter with Observation Path + +JESD204B/C Mixed-Signal Front Ends +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- :adi:`AD9081 `: MxFE™ Quad, 16-Bit, 12GSPS RFDAC and + Quad, 12-Bit, 4GSPS RFADC +- :adi:`AD9082 `: MxFE™ QUAD, 16-Bit, 12GSPS RFDAC and + DUAL, 12-Bit, 6GSPS RFADC +- :adi:`AD9986 `: 4T2R Direct RF Transmitter and + Observation Receiver +- :adi:`AD9988 `: 4T4R Direct RF Receiver and Transmitter + +Technical Support +-------------------------------------------------------------------------------- + +Analog Devices will provide limited online support for anyone using the core +with Analog Devices components (ADC, DAC, Clock, etc) via the +:ez:`EngineerZone ` under the GPL license. If you would like +deterministic support when using this core with an ADI component, please +investigate a commercial license. Using a non-ADI JESD204 device with this core +is possible under the GPL, but Analog Devices will not help with issues you may +encounter. + +More Information +-------------------------------------------------------------------------------- + +- :ref:`JESD204B High-Speed Serial Interface Support ` +- :ref:`HDL User Guide ` diff --git a/docs/library/jesd204/axi_jesd204_tx/jesd204_ilas_sequence.svg b/docs/library/jesd204/axi_jesd204_tx/jesd204_ilas_sequence.svg new file mode 100644 index 000000000..95c1ece01 --- /dev/null +++ b/docs/library/jesd204/axi_jesd204_tx/jesd204_ilas_sequence.svg @@ -0,0 +1,4 @@ + + + +ILAS/R/DD/A//R//Q/CD/A//R/DD/A//R/DDALMFC \ No newline at end of file diff --git a/docs/library/jesd204/axi_jesd204_tx/jesd204_tx_state_machine.svg b/docs/library/jesd204/axi_jesd204_tx/jesd204_tx_state_machine.svg new file mode 100644 index 000000000..2be219486 --- /dev/null +++ b/docs/library/jesd204/axi_jesd204_tx/jesd204_tx_state_machine.svg @@ -0,0 +1,467 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + CGS + + + + ILAS + + + + DATA + + + + + + reset + !continuous_cgs &&!sync_request &&!skip_ilas + !continuous_cgs &&!sync_request &&skip_ilas  + + WAIT + + sync_request &&!disabled + ilas_mframes == 4 &&!continuous_ilas +   + diff --git a/docs/library/jesd204/axi_jesd204_tx/jesd204_tx_tx_data_timing.svg b/docs/library/jesd204/axi_jesd204_tx/jesd204_tx_tx_data_timing.svg new file mode 100644 index 000000000..4d01ab743 --- /dev/null +++ b/docs/library/jesd204/axi_jesd204_tx/jesd204_tx_tx_data_timing.svg @@ -0,0 +1,4347 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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Transport Peripheral + +The JESD204, JESD204A, JESD204B and the JESD204C data converter serial interface +standard was created through the JEDEC committee to standardize and reduce the +number of data inputs/outputs between high-speed data converters and other +devices, such as FPGAs (field-programmable gate arrays). Fewer interconnects +simplifies layout and allows smaller form factor realization without impacting +overall system performance. These attributes are important to address the system +size and cost constraints of a range of high-speed ADC applications, including +wireless infrastructure (GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA) +transceiver architectures, software-defined radios, portable instrumentation, +medical ultrasound equipment, and Mil/Aero applications such as radar and secure +communications. Analog Devices is an original participating member of the JEDEC +JESD204 standards committee and we have concurrently developed compliant data +converter technology and tools, and a comprehensive product roadmap to fully +enable our customers to take advantage of this significant interfacing +breakthrough. + +Analog Devices supplies a full-stack supporting JESD204B/C which provides a +fully integrated system level experience. This solution includes: + +.. hint:: + + * :ref:`Reference hardware platforms ` for + rapid-prototyping + * :ref:`FPGA HDL support ` for interfacing JESD204B/C ADCs, + DACs, and RF Transceivers + * :ref:`Software support ` to configure the converter + devices and FPGA HDL peripherals + +How to Obtain a License +-------------------------------------------------------------------------------- + +When customers and partners download/use software from GitHub, e-mail or +similar ways, they are obligated to comply to the terms and conditions of +the :git-hdl:`Software License Agreement `. +This core is released under two different licenses. You may choose either: + +- Commercial licenses may be purchased from :adi:`Analog Devices, Inc. <>`. or any + authorized distributor by ordering + :adi:`IP-JESD204 `. + This will allow you to use the core in a closed system. +- GPL 2, this allows you to use the core for any purpose, but you must release + anything else that links to the JESD204 core (this would normally be your + algorithmic IP). **You do not need to sign or purchase** anything to use + the JESD204 core under the GPL license. + +There is only one core -- the only difference is the license and support. +If you have a question about the license, you can email +`jesd204-licensing@analog.com `__. + +.. _fpga_hdl_support_label: + +FPGA HDL Support +-------------------------------------------------------------------------------- + +.. image:: jesd204_layers2.svg + :align: right + +The JESD204B/C standard defines multiple layers, each layer being responsible +for a particular function. The Analog Devices JESD204B/C HDL solution follows +the current standard and defines 4 layers. Physical layer, link layer, transport +layer and application layer. For the first three layers, :adi:`ADI <>` provides +standard components that can be linked to provide a full JESD204B/C protocol +processing chain. + +Depending on the FPGA and converter combinations that are being interfaced, +different components can be chosen for the physical and transport layer. The +FPGA defines which **physical** layer component should be used, meanwhile the +interfaced converter defines which **transport** layer component should be used. + +The **link** layer component is selected based on the direction of the +JESD204B/C link. + +The **application** layer is user-defined and can be used to implement +application-specific signal processing. + +.. image:: jesd204_chain.svg + :align: center + +.. _jesd204_physical_layer: + +Physical Layer +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Physical layer peripherals are responsible for interfacing and configuring the +high-speed serial transceivers. Currently, we have support for GTXE2, GTHE3, +GTHE4, GTYE4 for AMD Xilinx and Arria 10 transceivers for Intel. + +* :ref:`axi_adxcvr`: JESD204B Gigabit + Transceiver Register Configuration Peripheral +* :ref:`UTIL_ADXCVR `: JESD204B Gigabit + Transceiver Interface Peripheral for AMD Xilinx FPGAs + +Link Layer +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Link layer peripherals are responsible for JESD204B/C protocol handling, +including scrambling/descrambling, lane alignment, character replacement and +alignment monitoring. + +* :ref:`JESD204B/C Transmit Peripheral `: + JESD204B/C Link Layer Transmit Peripheral +* :ref:`JESD204B/C Receive Peripheral `: + JESD204B/C Link Layer Receive Peripheral + +.. _jesd204_transport_layer: + +Transport Layer +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Transport layer peripherals are responsible for converter specific data framing +and de-framing. + +* :ref:`ADC JESD204B/C Transport Peripheral `: + JESD204B/C Transport Layer Receive Peripheral +* :ref:`DAC JESD204B/C Transport Peripheral `: + JESD204B/C Transport Layer Transmit Peripheral + +Interfaces +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Interfaces are a well-defined collection of wires that are used to communicate +between components. The following interfaces are used to connect components of +the HDL JESD204B/C processing stack. + +.. _software_support_label: + +Software Support +-------------------------------------------------------------------------------- + +Linux +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- :dokuwiki:`JESD204 (FSM) Interface Linux Kernel Framework ` +- :dokuwiki:`JESD204B/C Transmit Linux Driver `: + Linux driver for the JESD204B transmit core. +- :dokuwiki:`JESD204B/C Receive Linux Driver `: + Linux driver for the JESD204B receive core. +- :dokuwiki:`JESD204B/C AXI_ADXCVR Highspeed Transceivers Linux Driver ` +- :dokuwiki:`JESD204B Statistical Eyescan Application ` +- :dokuwiki:`JESD204B Status Utility ` +- :dokuwiki:`AXI DAC HDL Linux Driver ` + + - :dokuwiki:`AD9172 DAC Linux Driver ` + - :dokuwiki:`AD9081 MxFE Linux Driver ` + - :dokuwiki:`ADRV9009, ADRV9008 highly integrated, wideband RF transceiver Linux device driver ` + - :dokuwiki:`AD9371, AD9375 highly integrated, wideband RF transceiver Linux device driver ` + +- :dokuwiki:`AXI ADC HDL Linux Driver ` + + - :dokuwiki:`AD9208 ADC Linux Driver ` + - :dokuwiki:`AD9081 MxFE Linux Driver ` + - :dokuwiki:`ADRV9009, ADRV9008 highly integrated, wideband RF transceiver Linux device driver ` + - :dokuwiki:`AD9371, AD9375 highly integrated, wideband RF transceiver Linux device driver ` + +No-OS +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- :dokuwiki:`ADI JESD204B/C AXI_ADXCVR Highspeed Transceivers No-OS Driver ` +- :dokuwiki:`ADI JESD204B/C Receive Peripheral No-OS Driver ` +- :dokuwiki:`ADI JESD204B/C Transmit Peripheral No-OS Driver ` +- :dokuwiki:`AXI ADC No-OS Driver ` +- :dokuwiki:`AXI DAC No-OS Driver ` + +Tutorial +-------------------------------------------------------------------------------- + +#. :dokuwiki:`Introduction ` +#. :dokuwiki:`System Architecture ` +#. :dokuwiki:`Generic JESD204B block designs `. + This will help you understand the generic blocks for the next steps. +#. Checkout the :ref:`HDL Source `, and then build either one of: + + #. :dokuwiki:`HDL AMD Xilinx ` + #. :dokuwiki:`HDL Altera ` + +#. :dokuwiki:`Linux ` + +Example Projects +-------------------------------------------------------------------------------- + +- :dokuwiki:`AD-FMCADC2-EBZ Reference Design ` + + - :git-hdl:`AMD Xilinx VC707 ` + - :git-hdl:`AMD Xilinx ZC706 ` + +- :dokuwiki:`AD-FMCADC3-EBZ Reference Design ` + + - :git-hdl:`AMD Xilinx VC707 ` + - :git-hdl:`AMD Xilinx ZC706 ` + +- :dokuwiki:`AD-FMCADC4-EBZ Reference Design (RETIRED) ` + + - :git-hdl:`AMD Xilinx ZC706 ` + +- :dokuwiki:`AD-FMCJESDADC1-EBZ Reference Design ` + + - :git-hdl:`AMD Xilinx KC705 ` + - :git-hdl:`AMD Xilinx VC707 ` + - :git-hdl:`AMD Xilinx ZC706 ` + +- :dokuwiki:`AD-FMCOMMS8-EBZ Reference Design ` + + - :git-hdl:`Intel A10SOC ` + - :git-hdl:`AMD Xilinx ZCU102 ` + +- :dokuwiki:`AD-FMCOMMS11-EBZ Reference Design ` + + - :git-hdl:`AMD Xilinx ZC706 ` + +- :dokuwiki:`AD-FMCDAQ2-EBZ Reference Design ` + + - :git-hdl:`Intel A10SOC ` + - :git-hdl:`Intel A10Gx (RETIRED) ` + - :git-hdl:`AMD Xilinx KC705 ` + - :git-hdl:`AMD Xilinx KCU105 ` + - :git-hdl:`AMD Xilinx VC707 (RETIRED) ` + - :git-hdl:`AMD Xilinx ZC706 ` + - :git-hdl:`AMD Xilinx ZCU102 ` + +- :dokuwiki:`AD-FMCDAQ3-EBZ Reference Design ` + + - :git-hdl:`Intel A10Gx (RETIRED) ` + - :git-hdl:`AMD Xilinx KCU105 ` + - :git-hdl:`AMD Xilinx VCU118 ` + - :git-hdl:`AMD Xilinx ZC706 ` + - :git-hdl:`AMD Xilinx ZCU102 ` + +- :dokuwiki:`ADRV9371 Reference Design ` + + - :git-hdl:`Intel A10SOC ` + - :git-hdl:`Intel A10Gx (RETIRED) ` + - :git-hdl:`AMD Xilinx KCU105 ` + - :git-hdl:`AMD Xilinx ZC706 ` + - :git-hdl:`AMD Xilinx ZCU102 ` + +- :dokuwiki:`ADRV9009 Reference Design ` + + - :git-hdl:`AMD Xilinx ZCU102 ` + +- :dokuwiki:`ADRV9009-ZU11EG-SOM Reference Design ` + + - :git-hdl:`Intel A10SOC ` + - :git-hdl:`Intel A10Gx (RETIRED) ` + - :git-hdl:`AMD Xilinx ZC706 ` + - :git-hdl:`ADRV9009-ZU11EG-SOM ` + +- :dokuwiki:`AD913x/AD917x/AD9144/AD915x/AD916X Reference Design ` + + - See the :git-hdl:`list of supported parts ` + - :git-hdl:`Intel A10SOC ` + - :git-hdl:`AMD Xilinx VCU118 ` + - :git-hdl:`AMD Xilinx ZC706 ` + - :git-hdl:`AMD Xilinx ZCU102 ` + +- :ref:`AD9081-FMCA-EBZ Reference Design ` + + - :git-hdl:`Intel A10SOC ` + - :git-hdl:`AMD Xilinx ZC706 ` + - :git-hdl:`AMD Xilinx ZCU102 ` + - :git-hdl:`AMD Xilinx VCU118 ` + - :git-hdl:`AMD Xilinx VCU128 ` + - :git-hdl:`AMD Xilinx VCK190 ` + +- :ref:`AD9082-FMCA-EBZ Reference Design ` + + - :git-hdl:`AMD Xilinx VCK190 ` + - :git-hdl:`AMD Xilinx VCU118 ` + - :git-hdl:`AMD Xilinx ZC706 ` + - :git-hdl:`AMD Xilinx ZCU102 ` + +- :dokuwiki:`AD9081-FMCA-EBZ X-Band Phased Array Reference Design ` + + - :git-hdl:`AMD Xilinx ZCU102 ` + +- :dokuwiki:`AD9213-DUAL-EBZ Reference Design ` + + - :git-hdl:`Intel S10SOC ` + +- :dokuwiki:`AD9213-EBZ Reference Design ` + + - :git-hdl:`AMD Xilinx VCU118 ` + +- :dokuwiki:`AD6676-EBZ Reference Design ` + + - :git-hdl:`AMD Xilinx VC707 ` + - :git-hdl:`AMD Xilinx ZC706 ` + +- :dokuwiki:`AD9083-FMC ` + + - :git-hdl:`Intel A10SOC ` + - :git-hdl:`AMD Xilinx ZCU102 ` + +- :dokuwiki:`AD9208-DUAL-EBZ reference design ` + + - :git-hdl:`AMD Xilinx VCU118 ` + +- :dokuwiki:`AD9209-FMCA-EBZ reference design ` + + - :git-hdl:`AMD Xilinx VCK190 ` + +- :dokuwiki:`AD9656 HDL Reference Design ` + + - :git-hdl:`AMD Xilinx ZCU102 ` + +- :dokuwiki:`AD9695-FMC reference design ` + + - :git-hdl:`AMD Xilinx ZCU102 ` + +- :dokuwiki:`AD-QUADMXFE1-EBZ reference design ` + + - :git-hdl:`AMD Xilinx VCU118 ` + +- :dokuwiki:`AD-FMCLIDAR1-EBZ reference design ` + + - :git-hdl:`Intel A10SOC (RETIRED) ` + - :git-hdl:`AMD Xilinx ZC706 (RETIRED)` + - :git-hdl:`AMD Xilinx ZCU102 (RETIRED)` + +- :dokuwiki:`ADRV9026 reference design ` + + - :git-hdl:`AMD Xilinx ZCU102 ` + +Additional Information +-------------------------------------------------------------------------------- + +- :dokuwiki:`JESD204B Glossary ` + +Technical Articles +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- :adi:`JESD204B Survival Guide ` +- :adi:`Synchronizing Sample Clocks of a Data Converter Array ` + +.. _rapid_prototyping_label: + +JESD204B Rapid Prototyping Platforms +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- :adi:`EVAL-ADRV9371 ` + :dokuwiki:`(User Guide) ` +- :adi:`EVAL-ADRV9008-9009 ` + :dokuwiki:`(User Guide) ` +- :dokuwiki:`ADRV9009-ZU11EG (User Guide) ` +- :adi:`AD-FMCJESDADC1-EBZ ` +- :adi:`AD-FMCOMMS11-EBZ ` + :dokuwiki:`(User Guide) ` +- :adi:`AD-FMCADC2-EBZ ` +- :adi:`AD-FMCADC3-EBZ ` +- :adi:`AD-FMCADC4-EBZ `\ (RETIRED) +- :adi:`AD-FMCDAQ2-EBZ ` + :dokuwiki:`(User Guide) ` +- :adi:`EVAL-FMCDAQ3-EBZ ` + :dokuwiki:`(User Guide) ` +- :adi:`EVAL-AD917X ` + +JESD204B Analog-to-Digital Converters +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- :adi:`AD6673 `: 80 MHz Bandwidth, Dual IF Receiver +- :adi:`AD6674 `: 385 MHz BW IF Diversity Receiver +- :adi:`AD6676 `: Wideband IF Receiver Subsystem +- :adi:`AD6677 `: 80 MHz Bandwidth, IF Receiver +- :adi:`AD6684 `: 135 MHz Quad IF Receiver +- :adi:`AD6688 `: RF Diversity and 1.2GHz BW Observation + Receiver +- :adi:`AD9207 `: 12-Bit, 6 GSPS, JESD204B/JESD204C + Dual Analog-to-Digital Converter +- :adi:`AD9208 `: 14-Bit, 3GSPS, JESD204B, + Dual Analog-to-Digital Converter +- :adi:`AD9209 `: 12-Bit, 4GSPS, JESD204B/C, Quad + Analog-to-Digital Converter +- :adi:`AD9213 `: 12-Bit, 10.25 GSPS, JESD204B, RF + Analog-to-Digital Converter +- :adi:`AD9234 `: 12-Bit, 1 GSPS/500 MSPS JESD204B, Dual + Analog-to-Digital Converter +- :adi:`AD9250 `: 14-Bit, 170 MSPS/250 MSPS, JESD204B, Dual + Analog-to-Digital Converter +- :adi:`AD9625 `: 12-Bit, 2.6 GSPS/2.5 GSPS/2.0 GSPS, + 1.3 V/2.5 V Analog-to-Digital Converter +- :adi:`AD9656 `: Quad, 16-Bit, 125 MSPS JESD204B 1.8 V + Analog-to-Digital Converter +- :adi:`AD9680 `: 14-Bit, 1.25 GSPS/1 GSPS/820 MSPS/500 + MSPS JESD204B, Dual Analog-to-Digital Converter +- :adi:`AD9683 `: 14-Bit, 170 MSPS/250 MSPS, JESD204B, + Analog-to-Digital Converter +- :adi:`AD9690 `: 14-Bit, 500 MSPS / 1 GSPS JESD204B, + Analog-to-Digital Converter +- :adi:`AD9691 `: 14-Bit, 1.25 GSPS JESD204B, + Dual Analog-to-Digital Converter +- :adi:`AD9694 `: 14-Bit, 500 MSPS JESD204B, Quad + Analog-to-Digital Converter +- :adi:`AD9695 `: 14-Bit, 1300 MSPS/625 MSPS, + JESD204B, Dual Analog-to-Digital Converter Analog-to-Digital Converter +- :adi:`AD9083 `: 16-Channel, 125 MHz Bandwidth, JESD204B + Analog-to-Digital Converter +- :adi:`AD9094 `: 8-Bit, 1 GSPS, JESD204B, Quad + Analog-to-Digital Converter + +JESD204B Digital-to-Analog Converters +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- :adi:`AD9135 `: Dual, 11-Bit, high dynamic, 2.8 GSPS, + TxDAC+® Digital-to-Analog Converter +- :adi:`AD9136 `: Dual, 16-Bit, 2.8 GSPS, TxDAC+® + Digital-to-Analog Converter +- :adi:`AD9144 `: Quad, 16-Bit, 2.8 GSPS, TxDAC+® + Digital-to-Analog Converter +- :adi:`AD9152 `: Dual, 16-Bit, 2.25 GSPS, TxDAC+ + Digital-to-Analog Converter +- :adi:`AD9154 `: Quad, 16-Bit, 2.4 GSPS, TxDAC+® + Digital-to-Analog Converter +- :adi:`AD9161 `: 11-Bit, 12 GSPS, RF Digital-to-Analog + Converter +- :adi:`AD9162 `: 16-Bit, 12 GSPS, RF Digital-to-Analog + Converter +- :adi:`AD9163 `: 16-Bit, 12 GSPS, RF DAC and Digital + Upconverter +- :adi:`AD9164 `: 16-Bit, 12 GSPS, RF DAC and Direct Digital + Synthesizer +- :adi:`AD9172 `: Dual, 16-Bit, 12.6 GSPS RF DAC with + Channelizers +- :adi:`AD9173 `: Dual, 16-Bit, 12.6 GSPS RF DAC with + Channelizers +- :adi:`AD9174 `: Dual, 16-Bit, 12.6 GSPS RF DAC and Direct + Digital Synthesizer +- :adi:`AD9175 `: Dual, 11-Bit/16-Bit, 12.6 GSPS RF DAC with + Wideband Channelizers +- :adi:`AD9176 `: Dual, 16-Bit, 12.6 GSPS RF DAC with + Wideband Channelizers +- :adi:`AD9177 `: Quad, 16-Bit, 12 GSPS RF DAC with + Wideband Channelizers + +JESD204B RF Transceivers +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- :adi:`AD9371 `: SDR Integrated, Dual RF Transceiver with + Observation Path +- :adi:`AD9375 `: SDR Integrated, Dual RF Transceiver with + Observation Path and DPD +- :adi:`ADRV9009 `: SDR Integrated, Dual RF Transceiver + with Observation Path +- :adi:`ADRV9008-1 `: SDR Integrated, Dual RF Receiver +- :adi:`ADRV9008-2 `: SDR Integrated, Dual RF + Transmitter with Observation Path + +JESD204B/C Mixed-Signal Front Ends +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- :adi:`AD9081 `: MxFE™ Quad, 16-Bit, 12GSPS RFDAC and + Quad, 12-Bit, 4GSPS RFADC +- :adi:`AD9082 `: MxFE™ QUAD, 16-Bit, 12GSPS RFDAC and + DUAL, 12-Bit, 6GSPS RFADC +- :adi:`AD9986 `: 4T2R Direct RF Transmitter and + Observation Receiver +- :adi:`AD9988 `: 4T4R Direct RF Receiver and Transmitter + +JESD204B Clocking Solutions +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- :adi:`AD9528 `: JESD204B Clock Generator with 14 + LVDS/HSTL Outputs +- :adi:`HMC7043 `: High Performance, 3.2 GHz, 14-Output + Fanout Buffer +- :adi:`HMC7044 `: High Performance, 3.2 GHz, 14-Output + Jitter Attenuator with JESD204B +- :adi:`LTC6952 `: Ultralow Jitter, 4.5GHz PLL, + JESD204B/JESD204C +- :adi:`ADF 4371 `: Microwave Wideband Synthesizer + with Integrated VCO \ No newline at end of file diff --git a/docs/library/jesd204/jesd204_chain.svg b/docs/library/jesd204/jesd204_chain.svg new file mode 100644 index 000000000..9ba152108 --- /dev/null +++ b/docs/library/jesd204/jesd204_chain.svg @@ -0,0 +1,1515 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + DAC ConverterDevice + + + + + + + + FPGA + + + PhyLayer + + + + LinkLayer + + + + TransportLayer + + + ApplicationLayer + + + + + + + + + + + + + + SYNC~* + + ADC ConverterDevice + + + + FPGA + + PhyLayer + + LinkLayer + + TransportLayer + + ApplicationLayer + + + + + + + + + + SYNC~* + + External hardwarecomponents + + Standard HDLcomponents + + Application specificuser-defined HDL components + * SYNC~ present in JESD204B only + + + ADC ConverterDevice + + FPGA + + + PhyLayer + + + + LinkLayer + + + + TransportLayer + + + + + + + ApplicationLayer + + + + SYNC~* + + + Standard HDLcomponents + + + + External hardwarecomponents + + + DAC ConverterDevice + + FPGA + + + PhyLayer + + + + LinkLayer + + + + TransportLayer + + + + + + + ApplicationLayer + + + + SYNC~* + JESD204B/C TX Chain + JESD204B/C RX Chain + + + + + + + + + + + + + + + + + + + + + + + + + * SYNC~ present in JESD204B only + + Application specific user-definedHDL component + diff --git a/docs/library/jesd204/jesd204_layers2.svg b/docs/library/jesd204/jesd204_layers2.svg new file mode 100644 index 000000000..80f5af0bf --- /dev/null +++ b/docs/library/jesd204/jesd204_layers2.svg @@ -0,0 +1,134 @@ + + + + + + + + + + + Application + + Transport + + Link + + Physical + diff --git a/docs/library/spi_engine/spi_engine_interconnect.rst b/docs/library/spi_engine/spi_engine_interconnect.rst index ff6d52f89..092d5c097 100644 --- a/docs/library/spi_engine/spi_engine_interconnect.rst +++ b/docs/library/spi_engine/spi_engine_interconnect.rst @@ -54,15 +54,13 @@ Signal and Interface Pins * - resetn - Synchronous active-low reset. Resets the internal state of the module. - * - s0_ctrl + * - s*_ctrl - :ref:`spi_engine control-interface` slave. - Connects to the first control interface master. - * - s1_ctrl - - :ref:`spi_engine control-interface` slave. - Connects to the second control interface master. + | ``s0_ctrl`` connects to the first control interface master. + | ``s1_ctrl`` connects to the second control interface master. * - m_ctrl - - :ref:`spi_engine control-interface` master. - Connects to the control interface slave. + - | :ref:`spi_engine control-interface` master. + | Connects to the control interface slave. Theory of Operation -------------------------------------------------------------------------------- diff --git a/docs/library/xilinx/index.rst b/docs/library/xilinx/index.rst new file mode 100644 index 000000000..8a1b41825 --- /dev/null +++ b/docs/library/xilinx/index.rst @@ -0,0 +1,12 @@ +.. _xilinx: + +AMD Xilinx Specific IPs +================================================================================ + +Contents +-------- + +.. toctree:: + :maxdepth: 2 + + UTIL_ADXCVR diff --git a/docs/library/xilinx/util_adxcvr/gtx_column.svg b/docs/library/xilinx/util_adxcvr/gtx_column.svg new file mode 100644 index 000000000..bcfb1c894 --- /dev/null +++ b/docs/library/xilinx/util_adxcvr/gtx_column.svg @@ -0,0 +1,3384 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/docs/library/xilinx/util_adxcvr/index.rst b/docs/library/xilinx/util_adxcvr/index.rst new file mode 100644 index 000000000..e8589b570 --- /dev/null +++ b/docs/library/xilinx/util_adxcvr/index.rst @@ -0,0 +1,316 @@ +.. _util_adxcvr: + +UTIL_ADXCVR core for AMD Xilinx devices +================================================================================ + +.. hdl-component-diagram:: + :path: library/xilinx/util_adxcvr + +The +:git-hdl:`util_adxcvr ` +IP core instantiates a Gigabit Transceiver (GT) and sets up the required +configuration. Basically, it is a simple wrapper file for a GT\* Column, +exposing just the necessary ports and attributes. + +.. note:: + To understand the below wiki page is important to have a basic + understanding about High Speed Serial I/O interfaces and Gigabit Serial + Transceivers. To find more information about these technologies, please visit + the :xilinx:`AMD Xilinx's solution center `. + +Currently this IP supports three different GT types: + +- GTXE2 + (:xilinx:`7 Series devices `) +- GTHE3 + (:xilinx:`Ultrascale and Ultrascale+ `) +- GTHE4 + (:xilinx:`Ultrascale and Ultrascale+ `) +- GTYE4 + (:xilinx:`Ultrascale and Ultrascale+ `) + +Features +-------------------------------------------------------------------------------- + +* Supports GTX2, GTH3 and GTH4 +* Exposes all the necessary attributes for QPLL/CPLL configuration +* Supports shared transceiver mode +* Supports dynamic reconfiguration +* RX Eye Scan + +Block Diagram +-------------------------------------------------------------------------------- + +The following diagram shows a GTXE2 Column, which contains four GT Quads. Each +quad contains a GTEX2_COMMON and four GTXE2_CHANNEL primitives. + +.. image:: gtx_column.svg + :align: center + +Configuration Parameters +-------------------------------------------------------------------------------- + +.. hdl-parameters:: + + * - XCVR_TYPE + - | Define the current GT type: + | GTXE2(0), GTHE3(1), GTHE4(2) + * - QPLL_REFCLK_DIV + - QPLL reference clock divider M, see User Guide for more info + * - QPLL_FBDIV_RATIO + - QPLL reference clock divider N ratio, see User Guide for more info + * - QPLL_CFG + - Configuration settings for QPLL, see User Guide for more info + * - QPLL_FBDIV + - QPLL reference clock divider N, see User Guide for more info + * - CPLL_FBDIV + - CPLL feedback divider N2 settings, see User Guide for more info + * - CPLL_FBDIV_4_5 + - CPLL reference clock divider N1 settings, see User Guide for more info + * - TX_NUM_OF_LANES + - Number of transmit lanes. + * - TX_OUT_DIV + - CPLL/QPLL output clock divider D for the TX datapath, see User Guide for + more info + * - TX_CLK25_DIV + - Divider for internal 25 MHz clock for the TX datapath, see User Guide + for more info + * - TX_LANE_INVERT + - Per lane polarity inversion. Set the n-th bit to invert the polarity of + the n-th transmit lane. + * - RX_NUM_OF_LANES + - Number of transmit lanes + * - RX_OUT_DIV + - CPLL/QPLL output clock divider D for the RX datapath, see User Guide for + more info + * - RX_CLK25_DIV + - Divider for internal 25 MHz clock for the RX datapath, see User Guide + for more info + * - RX_DFE_LPM_CFG + - Configure the GT use modes, LPM or DFE, see User Guide for more info + * - RX_PMA_CFG + - Search for PMA_RSV in User Guide for more info + * - RX_CDR_CFG + - Configure the RX clock data recovery circuit for GTXE2, see User Guide + for more info + * - RX_LANE_INVERT + - Per lane polarity inversion. Set the n-th bit to invert the polarity of + the n-th receive lane. + +Interface +-------------------------------------------------------------------------------- + +Microprocessor clock and reset +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +.. list-table:: + :header-rows: 1 + + * - Pin + - Type + - Description + * - ``up_clk`` + - ``input`` + - System clock, running on 100 MHz + * - ``up_rstn`` + - ``input`` + - System reset, the same as AXI memory map slave interface reset + +PLL reference clock +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +.. list-table:: + :header-rows: 1 + + * - Pin + - Type + - Description + * - ``qpll_ref_clk_0`` + - ``input`` + - Reference clock for the QPLL + * - ``cpll_ref_clk_0`` + - ``input`` + - Reference clock for the CPLL + +RX interface +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +.. list-table:: + :header-rows: 1 + + * - Pin + - Type + - Description + * - ``rx_*_p`` + - ``input`` + - Positive differential serial data input + * - ``rx_*_n`` + - ``input`` + - Negative differential serial data input + * - ``rx_out_clk_*`` + - ``output`` + - Core logic clock output. Frequency = serial line rate/40 + * - ``rx_clk_*`` + - ``input`` + - Core logic clock loop-back input + * - ``rx_charisk_*`` + - ``output[3:0]`` + - RX Char is K to the JESD204B IP + * - ``rx_disperr_*`` + - ``output[3:0]`` + - RX disparity error to the JESD204B IP + * - ``rx_notintable_*`` + - ``output[3:0]`` + - RX Not In Table to the JESD204B IP + * - ``rx_data_*`` + - ``output[3:0]`` + - RX data to the JESD204B IP + * - ``rx_calign_*`` + - ``input`` + - RX enable comma alignment from the JESD204B IP + +TX interface +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +.. list-table:: + :header-rows: 1 + + * - Pin + - Type + - Description + * - ``tx_*_p`` + - ``output`` + - Positive differential serial output + * - ``tx_*_n`` + - ``output`` + - Negative differential serial output + * - ``tx_out_clk_*`` + - ``output`` + - Core logic clock output. Frequency = serial line rate/40 + * - ``tx_clk_*`` + - ``input`` + - Core logic clock loop-back input + * - ``tx_charisk_*`` + - ``input[3:0]`` + - TX Char is K from the JESD204B IP + * - ``tx_data_*`` + - ``input[31:0]`` + - TX data from the JESD204B IP + +Common DRP Interface +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +.. list-table:: + :header-rows: 1 + + * - Pin + - Type + - Description + * - ``up_cm_*`` + - ``IO`` + - The common DRP interface, must be connected to the equivalent DRP ports + of AXI_ADXCVR. This is a QUAD interface, shared by four transceiver + lanes. This interface is available only if parameter QPLL_ENABLE is set + to 0x1. + +Channel DRP Interface +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +.. list-table:: + :header-rows: 1 + + * - Pin + - Type + - Description + * - ``up_rx_*`` + - ``IO`` + - The RX channel DRP interface, must be connected to the equivalent DRP ports + of AXI_ADXCVR. This is a channel interface, one per each RX transceiver + lane. + * - ``up_tx_*`` + - ``IO`` + - The TX channel DRP interface, must be connected to the equivalent DRP ports + of AXI_ADXCVR. This is a channel interface, one per each TX transceiver + lane. + +Eye Scan DRP Interface +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +.. list-table:: + :header-rows: 1 + + * - Pin + - Type + - Description + * - ``up_es_*`` + - ``IO`` + - The Eye-Scan DRP interface, must be connected to the equivalent DRP + ports of UTIL_ADXCVR. This is a channel interface, one per each + transceiver lane. This interface is available only if parameter + TX_OR_RX_N is set to 0x0. + +Design Guidelines +-------------------------------------------------------------------------------- + +.. note:: + Please refer to :dokuwiki:`AMD Xilinx FPGAs Transceivers Wizard ` + to generate the optimal parameters needed to configure the transceivers for + your project. + +Physical constraints considerations +-------------------------------------------------------------------------------- + +The util_adxcvr allocates resources/quads (channels and common) sequentially. +Meaning, if you have 8 lanes it will insert two quads, 4 channels and a common +block for each quad. + +Channels within a quad are tightly coupled to the common block, the placement of +the channel resources can be permuted within a quad and is affected by the +constraint file with the restriction that rx\__p/n connect to tx\__p/n +must connect to the same channel. + +Supposing we have the following pin constraints and connections to the +util_adxcvr: + +.. image:: xcvr_mapping_example.svg + :align: center + +So in this case we end up with a conflict during implementation: + +.. image:: xcvr_conflict.svg + :align: center + +We have to ensure that in implementation the mapping is correct either by +rearranging the Rx connections + +.. image:: xcvr_rx_rearrangement.svg + :align: center + +or by rearranging the Tx connections of the util_adxcvr: + +.. image:: xcvr_tx_rearrangement.svg + :align: center + +In such cases, when rearrangement is required due placement constraints, +complementary reordering is required either in the converter device (lane +crossbars) or inside the FPGA between the physical and link layer, to connect +the logical lanes with the same index on both end of the link. + +Software Guidelines +-------------------------------------------------------------------------------- + +The software can configure this core through the :ref:`AXI_ADXCVR ` IP +core. + +References +-------------------------------------------------------------------------------- + +- :xilinx:`High Speed Serial ` +- :xilinx:`7 Series FPGAs GTX/GTH Transceivers ` +- :xilinx:`UltraScale Architecture GTH Transceivers ` +- :xilinx:`UltraScale Architecture GTY Transceivers ` + +More Information +-------------------------------------------------------------------------------- + +- :ref:`JESD204B High-Speed Serial Interface Support ` diff --git a/docs/library/xilinx/util_adxcvr/xcvr_conflict.svg b/docs/library/xilinx/util_adxcvr/xcvr_conflict.svg new file mode 100644 index 000000000..2f4a5dc10 --- /dev/null +++ b/docs/library/xilinx/util_adxcvr/xcvr_conflict.svg @@ -0,0 +1,1528 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Tx ch constraint + + + tx top port + + + tx ch pin + + + Internal ch index + + + rx ch pin + + + rx top port + + + rx ch constraint + + + MGTHTXP3_224 + + + tx_data_p[0] + + + tx_0_p + + + ch0 + + + rx_0_p + + + rx_data_p[0] + + + MGTHRXP0_225 + + + MGTHTXP2_224 + + + tx_data_p[1] + + + tx_1_p + + + ch1 + + + rx_1_p + + + rx_data_p[1] + + + MGTHRXP1_225 + + + MGTHTXP1_224 + + + tx_data_p[2] + + + tx_2_p + + + ch2 + + + MGTHTXP0_224 + + + tx_data_p[3] + + + tx_3_p + + + ch3 + + + MGTHTXP3_225 + + + tx_data_p[4] + + + tx_4_p + + + ch4 + + + MGTHTXP2_225 + + + tx_data_p[5] + + + tx_5_p + + + ch5 + + + MGTHTXP1_225 + + + tx_data_p[6] + + + tx_6_p + + + ch6 + + + MGTHTXP0_225 + + + tx_data_p[7] + + + tx_7_p + + + ch7 + + + util_adxcvr + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/docs/library/xilinx/util_adxcvr/xcvr_mapping_example.svg b/docs/library/xilinx/util_adxcvr/xcvr_mapping_example.svg new file mode 100644 index 000000000..4d078a78a --- /dev/null +++ b/docs/library/xilinx/util_adxcvr/xcvr_mapping_example.svg @@ -0,0 +1,1163 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + MGTH Channel + + + util_adxcvr pin + + + FPGA_PIN + + + Top level port + + + MGTHTXP3_224 + + + tx_0_p + + + K6 + + + tx_data_p[0] + + + MGTHTXP2_224 + + + tx_1_p + + + L4 + + + tx_data_p[1] + + + MGTHTXP1_224 + + + tx_2_p + + + M6 + + + tx_data_p[2] + + + MGTHTXP0_224 + + + tx_3_p + + + P6 + + + tx_data_p[3] + + + MGTHTXP3_225 + + + tx_4_p + + + E8 + + + tx_data_p[4] + + + MGTHTXP2_225 + + + tx_5_p + + + F6 + + + tx_data_p[5] + + + MGTHTXP1_225 + + + tx_6_p + + + G8 + + + tx_data_p[6] + + + MGTHTXP0_225 + + + tx_7_p + + + H6 + + + tx_data_p[7] + + + MGTHRXP0_225 + + + rx_0_p + + + H2 + + + rx_data_p[0] + + + MGTHRXP1_225 + + + rx_1_p + + + G4 + + + rx_data_p[1] + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/docs/library/xilinx/util_adxcvr/xcvr_mapping_example.xlsx b/docs/library/xilinx/util_adxcvr/xcvr_mapping_example.xlsx new file mode 100644 index 0000000000000000000000000000000000000000..8313fc76e5e044a89cc845955def38640b0bc79f GIT binary patch literal 18669 zcmeIabyQr-wmpnH1b2eFySoGr?(Xic!QEYhyStMB!3pl}?(RR5bI!}Xx#zuczdzsi zZZpQ--Sn>6yH~B6wQAN{Eh7O8f(!r#00961fDd2+vS8%}2mp`{1^|Er00E>fXl>!VXE7YOX!&h2T0)gFv ztxmKDp6r5$8e-`R2IajPqN<=sC4iS8QPz{$7=D~2Z7rKHfDMFc%s4KdMgW+`X?aA1 zq}_en8z&kaKV9O0%1{l0+e6VTsoJH4w>ePhzHtM@e@qvDon6|Q+X@wM-l_V179)azp170Fn z*7s@HbwkD|f`xm)WD%eMiiQV%y1jG&1T299CtENw8>V^Y%H+x-x+>^V&K92U1i5Qh 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z`1e8O*#8~SpR3J(A5@j|-vRx(cKIFjpJU%&76ky%;RXQsmq_^c=Kma|{A2T*win|4+6N&>;M1& literal 0 HcmV?d00001 diff --git a/docs/library/xilinx/util_adxcvr/xcvr_rx_rearrangement.svg b/docs/library/xilinx/util_adxcvr/xcvr_rx_rearrangement.svg new file mode 100644 index 000000000..a37d86085 --- /dev/null +++ b/docs/library/xilinx/util_adxcvr/xcvr_rx_rearrangement.svg @@ -0,0 +1,1640 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Tx ch constraint + + + tx top port + + + tx ch pin + + + Internal ch index + + + rx ch pin + + + rx top port + + + rx ch constraint + + + MGTHTXP3_224 + + + tx_data_p[0] + + + tx_0_p + + + ch0 + + + rx_0_p + + + MGTHTXP2_224 + + + tx_data_p[1] + + + tx_1_p + + + ch1 + + + rx_1_p + + + MGTHTXP1_224 + + + tx_data_p[2] + + + tx_2_p + + + ch2 + + + rx_2_p + + + MGTHTXP0_224 + + + tx_data_p[3] + + + tx_3_p + + + ch3 + + + rx_3_p + + + MGTHTXP3_225 + + + tx_data_p[4] + + + tx_4_p + + + ch4 + + + rx_4_p + + + MGTHTXP2_225 + + + tx_data_p[5] + + + tx_5_p + + + ch5 + + + rx_5_p + + + MGTHTXP1_225 + + + tx_data_p[6] + + + tx_6_p + + + ch6 + + + rx_6_p + + + rx_data_p[1] + + + MGTHRXP1_225 + + + MGTHTXP0_225 + + + tx_data_p[7] + + + tx_7_p + + + ch7 + + + rx_7_p + + + rx_data_p[0] + + + MGTHRXP0_225 + + + util_adxcvr + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/docs/library/xilinx/util_adxcvr/xcvr_tx_rearrangement.svg b/docs/library/xilinx/util_adxcvr/xcvr_tx_rearrangement.svg new file mode 100644 index 000000000..e0e09b776 --- /dev/null +++ b/docs/library/xilinx/util_adxcvr/xcvr_tx_rearrangement.svg @@ -0,0 +1,1482 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Tx ch constraint + + + tx top port + + + tx ch pin + + + Internal ch index + + + rx ch pin + + + rx top port + + + rx ch constraint + + + MGTHTXP0_225 + + + tx_data_p[7] + + + tx_0_p + + + ch0 + + + rx_0_p + + + rx_data_p[0] + + + MGTHRXP0_225 + + + MGTHTXP1_225 + + + tx_data_p[6] + + + tx_1_p + + + ch1 + + + rx_1_p + + + rx_data_p[1] + + + MGTHRXP1_225 + + + MGTHTXP2_225 + + + tx_data_p[5] + + + tx_2_p + + + ch2 + + + MGTHTXP3_225 + + + tx_data_p[4] + + + tx_3_p + + + ch3 + + + MGTHTXP0_224 + + + tx_data_p[3] + + + tx_4_p + + + ch4 + + + MGTHTXP1_224 + + + tx_data_p[2] + + + tx_5_p + + + ch5 + + + MGTHTXP2_224 + + + tx_data_p[1] + + + tx_6_p + + + ch6 + + + MGTHTXP3_224 + + + tx_data_p[0] + + + tx_7_p + + + ch7 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/docs/regmap/adi_regmap_xcvr.txt b/docs/regmap/adi_regmap_xcvr.txt index 174dd7a05..b5642ce67 100644 --- a/docs/regmap/adi_regmap_xcvr.txt +++ b/docs/regmap/adi_regmap_xcvr.txt @@ -1,5 +1,5 @@ TITLE -Xilinx XCVR (axi_xcvr) Regmap +Xilinx XCVR (axi_xcvr) XCVR ENDTITLE @@ -110,7 +110,7 @@ ENDFIELD REG 0x0007 FPGA_INFO -FPGA device information [[https://github.com/analogdevicesinc/hdl/blob/main/library/scripts/adi_xilinx_device_info_enc.tcl |Xilinx encoded values]] +FPGA device information :git-hdl:`Xilinx encoded values ` ENDREG FIELD @@ -168,14 +168,19 @@ FIELD [5:4] SYSCLK_SEL[1:0] RW -For GTX drives directly the (RX/TX)SYSCLKSEL pin of the transceiver. Refer to Xilinx documentation. For GTH/GTY drives directly the (RX/TX)PLLCLKSEL pin of the transceiver and indirectly the (RX/TX)SYSCLKSEL pin of the transceiver see [[:resources:fpga:docs:axi_adxcvr#Table 1]]. +For GTX drives directly the (RX/TX)SYSCLKSEL pin of the transceiver refer to +Xilinx documentation. +For GTH/GTY drives directly the (RX/TX)PLLCLKSEL pin of the transceiver and +indirectly the (RX/TX)SYSCLKSEL pin of the transceiver see +:ref:`Table 1 `. ENDFIELD FIELD [2:0] OUTCLK_SEL[2:0] RW -Transceiver primitive control [[:resources:fpga:docs:axi_adxcvr#Table 2]], refer Xilinx documentation. +Transceiver primitive control :ref:`Table 2 `, +refer Xilinx documentation. ENDFIELD ############################################################################################ @@ -198,7 +203,7 @@ FIELD [19:16] XCVR_TYPE[3:0] RO -[[https://github.com/analogdevicesinc/hdl/blob/main/library/scripts/adi_xilinx_device_info_enc.tcl | Xilinx encoded values.]] +:git-hdl:`Xilinx encoded values `. ENDFIELD FIELD @@ -649,5 +654,224 @@ RO Ignore this bit for GTX transceivers. For others: Indicates that the RX PRBS checker has been error free for 15 XCLK cycles after reset. Once asserted High, it does not deassert until reset of the RX pattern checker via PRBSCNTRESET ENDFIELD +############################################################################################ +############################################################################################ +TITLE +Intel XCVR (axi_xcvr) +INTEL_XCVR +ENDTITLE +############################################################################################ +############################################################################################ + +REG +0x0000 +REG_VERSION +Version Register +ENDREG + +FIELD +[31:0] +VERSION[31:0] +RO +Version number. +ENDFIELD + +############################################################################################ +############################################################################################ + +REG +0x0001 +REG_ID +Instance Identification Register +ENDREG + +FIELD +[31:0] +ID[31:0] +RO +Instance identifier number. +ENDFIELD + +############################################################################################ +############################################################################################ + +REG +0x0002 +REG_SCRATCH +Scratch (GP R/W) Register +ENDREG + +FIELD +[31:0] +SCRATCH[31:0] +RW +Scratch register. +ENDFIELD + +############################################################################################ +############################################################################################ + +REG +0x0004 +RESETN +Reset Control Register +ENDREG + +FIELD +[0] +RESETN +RW +If clear, link is held in reset, set this bit to 0x1 to activate link. Note that the reference clock must be active before setting this bit. +ENDFIELD + +############################################################################################ +############################################################################################ + +REG +0x0005 +REG_STATUS +Status Reporting Register +ENDREG + +FIELD +[0] +STATUS +RO +After setting the RESETN bit above, wait for this bit to set. If set, indicates successful link activation. +ENDFIELD + +############################################################################################ +############################################################################################ + +REG +0x0006 +REG_STATUS_32 +Status Reporting Register +ENDREG + +FIELD +[31:NUM_OF_LANES] +RESERVED +RO +0 +ENDFIELD + +FIELD +[NUM_OF_LANES] +UP_PLL_LOCKED +RO +After setting the RESETN bit above, wait for this bit be to set. +ENDFIELD + +FIELD +[NUM_OF_LANES-1:0] +CHANNEL_N_READY +RO +After setting the RESETN bit above, wait for this registers to be set. +ENDFIELD + +############################################################################################ +############################################################################################ + +REG +0x0007 +REG_FPGA_INFO +FPGA device information :git-hdl:`Intel Encoded Values ` +ENDREG + +FIELD +[31:24] +FPGA_TECHNOLOGY +RO +Encoded value describing the technology/generation of the FPGA device (e.g., cyclone V, arria 10, stratix 10) +ENDFIELD + +FIELD +[23:16] +FPGA_FAMILY +RO +Encoded value describing the family variant of the FPGA device(e.g., SX, GX, GT or zynq, kintex, virtex) +ENDFIELD + +FIELD +[15:8] +SPEED_GRADE +RO +Encoded value describing the FPGA's speed-grade +ENDFIELD + +FIELD +[7:0] +DEV_PACKAGE +RO +Encoded value describing the device package. The package might affect high-speed interfaces +ENDFIELD + +############################################################################################ +############################################################################################ + +REG +0x0009 +REG_GENERIC_INFO +Physical layer info +ENDREG + +FIELD +[31:28] +RESERVED +RO +0 +ENDFIELD + +FIELD +[27:24] +XCVR_TYPE[3:0] +RO +Refers to the transceiver speed grade 0-9. +ENDFIELD + +FIELD +[23:12] +RESERVED +RO +0 +ENDFIELD + +FIELD +[11:9] +RESERVED +RO +0 +ENDFIELD + +FIELD +[8] +TX_OR_RX_N +RO +Transceiver type (transmit or receive) +ENDFIELD + +FIELD +[7:0] +NUM_OF_LANES +RO +Physical layer number of lanes. +ENDFIELD + +############################################################################################ +############################################################################################ + +REG +0x0050 +REG_FPGA_VOLTAGE +FPGA device voltage information +ENDREG + +FIELD +[15:0] +FPGA_VOLTAGE +RO +The voltage of the FPGA device in mv +ENDFIELD