docs: Add JESD204 documentation (#1280)
docs: Add JESD204 documentation in sphinx Fixes several semantic issues from the original doc in wiki Implicit path to library when the doc is hierarchically coherent with the library. Signed-off-by: Carlos Souza <carlos.souza@analog.com> Co-authored-by: Jorge Marques <jorge.marques@analog.com>main
caosjr
GitHub
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.. _axi_adxcvr:
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AXI_ADXCVR
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================================================================================
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.. hdl-component-diagram::
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:path: library/xilinx/axi_adxcvr
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The AXI_ADXCVR is a utility core used to control and configure the highspeed
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transceivers.
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There are separate AXI_ADXCVR cores for Intel and AMD Xilinx designs, due to the
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small differences between the AMD Xilinx's and Intel's transceivers architecture.
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For the AMD Xilinx architecture, the transceivers are instantiated in
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:ref:`UTIL_ADXCVR <util_adxcvr>`.
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Features
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--------------------------------------------------------------------------------
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- Supports :git-hdl:`Intel <library/intel/axi_adxcvr>`
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and :git-hdl:`AMD Xilinx <library/xilinx/axi_adxcvr>` devices.
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- Software can access the core's registers through an AXI4 Lite Memory Mapped
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interface.
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- Link reset and monitor for Intel and AMD Xilinx.
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- Reconfiguration interface control with broadcast capability for AMD Xilinx.
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- Access to the Statistical eye scan interface of the PHY (AMD Xilinx).
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- Supports up to 16 transceiver lanes per link (AMD Xilinx).
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Intel Devices
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--------------------------------------------------------------------------------
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For Intel devices, the adi_jesd204 IP is using the axi_adxcvr core, which can be
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accessed by the **link_management** interface. It provides a global reset signal
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for the JESD204B framework. Resets the XCVR reset controller IP, the link PLL
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reset controller, the PHY itself, and also the link layer of the stack. Besides
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the reset generation, monitors the PLLs and the PHY state.
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Parameters
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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.. hdl-parameters::
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:path: library/xilinx/axi_adxcvr
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* - ID
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- Instance identification number, if more than one instance is used.
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* - NUM_OF_LANES
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- The number of lanes (primitives) used in this link.
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* - XCVR_TYPE
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- Refers to the transceiver speed grade 0-9.
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* - FPGA_TECHNOLOGY
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- Encoded value describing the technology/generation of the FPGA device
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(e.g. Cyclone V, Arria 10, Stratix 10).
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* - FPGA_FAMILY
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- Encoded value describing the family variant of the FPGA device
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(e.g. SX, GX, GT).
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* - SPEED_GRADE
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- Encoded value describing the FPGA’s speed-grade.
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* - DEV_PACKAGE
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- Encoded value describing the device package. The package might affect
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high-speed interfaces.
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* - FPGA_VOLTAGE
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- Contains the value(0-5000 mV) at wich the FPGA device supplied.
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* - TX_OR_RX_N
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- If set (0x1), configures the link in transmit mode, otherwise receive.
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Interfaces
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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.. hdl-interfaces::
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:path: library/xilinx/axi_adxcvr
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* - s_axi_aclk
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- System clock. (in general 100 MHz)
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* - s_axi_aresetn
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- System reset.
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* - s_axi
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- Slave AXI4 Lite Memory Mapped interface
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* - up_ch_*
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- | Connect logical port ``pll_locked`` to the fPLL’s **pll_locked** pin;
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| Connect logical port ``ready`` to PHY reset controller.
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Register Map
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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.. hdl-regmap::
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:name: INTEL_XCVR
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:no-type-info:
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Software Guidelines
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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When the board powers up, both ATX and fPLL's must have a stable reference clock
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in order to lock automatically. If this requirement can not be respected by the
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system (e.g. the reference clocks are generated by a device that requires
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software configuration, through an interface implemented in FPGA), the software
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needs to reconfigure both PLLs, and just after that resets the transceivers.
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AMD Xilinx Devices
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--------------------------------------------------------------------------------
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In AMD Xilinx Devices, the core configures itself to be interfaced with the GT
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variant supported by the UTIL_ADXCVR core. All the transceiver primitives are
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configured and programmed identically.
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.. _parameters-1:
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Parameters
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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.. hdl-parameters::
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:path: library/xilinx/axi_adxcvr
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* - ID
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- Instance identification number, if more than one instance is used
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* - NUM_OF_LANES
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- The number of lanes (primitives) used in this link
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* - XCVR_TYPE
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- Define the current GT type, GTXE2(2), GTHE3(5), GTHE4(7)
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* - FPGA_TECHNOLOGY
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- Encoded value describing the technology/generation of the FPGA device
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(7series/ultrascale)
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* - FPGA_FAMILY
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- Encoded value describing the family variant of the FPGA device(e.g.,
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zynq, kintex, virtex)
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* - SPEED_GRADE
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- Encoded value describing the FPGA's speed-grade
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* - DEV_PACKAGE
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- Encoded value describing the device package. The package might affect
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high-speed interfaces
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* - FPGA_VOLTAGE
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- Contains the value(0-5000 mV) at wich the FPGA device supplied
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* - TX_OR_RX_N
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- If set (0x1), configures the link in transmit mode, otherwise receive
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* - QPLL_ENABLE
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- If set (0x1), configures the link to use QPLL on QUAD basis. If multiple
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links are sharing the same transceiver, only one of them may enable the
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QPLL.
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* - LPM_OR_DFE_N
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- Chosing between LPM or DFE of modes for the RX Equalizer
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* - RATE
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- Defines the initial values for Transceiver Control Register (REG_CONTROL
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0x0008)
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* - TX_DIFFCTRL
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- Driver Swing Control(TX Configurable Driver)
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* - TX_POSTCURSOR
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- Transmitter post-cursor TX pre-emphasis control
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* - TX_PRECURSOR
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- Transmitter pre-cursor TX pre-emphasis control
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* - SYS_CLK_SEL
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- Selects the PLL reference clock source to drive the RXOUTCLK
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:ref:`Table 1 <axi_adxcvr table_one_label>`
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* - OUT_CLK_SEL
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- select the transceiver reference clock as the source of TXOUTCLK
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:ref:`Table 2 <axi_adxcvr table_two_label>`
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Interfaces
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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.. hdl-interfaces::
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:path: library/xilinx/axi_adxcvr
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.. _register-map-1:
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Register Map
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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.. hdl-regmap::
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:name: XCVR
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:no-type-info:
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.. _software-guidelines-1:
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Software Guidelines
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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The system must have active DRP and reference clocks before any software access.
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The software is expected to write necessary control parameters to LPM_DFE_N,
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RATE, SYSCLK_SEL, OUTCLK_SEL register bits and then set RESETN bit to 0x1.
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After that, monitor the STATUS bit to be set. There are no other requirements
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for initialization.
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The DRP access is identical for common and channel interfaces. The SEL bits may
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be set to a specific transceiver lane or 0xff to broadcast. A write to the
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CONTROL register (bits WR, ADDR, WDATA) initiates DRP access in hardware. A read
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to this register has no effect. In order to write to the transceiver, set WR to
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0x1 with the address. In order to read from the transceiver, set WR to 0x0 with
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the address. As soon as this register is written, the BUSY signal is set and is
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cleared only after the access is complete. The broadcast read is a logical OR of
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all the channels. After an access is started, do NOT interrupt the core for any
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reason (including setting RESETN to 0x0), allow the access to finish itself.
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Though the core itself is immune to a software abort, the transceiver may fail
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on further accesses and may require a system-wide reset.
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The eye-scan feature also allows a SEL option and a broadcast has the effect of
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a combined mask. That is, the error counter will be zero ONLY if all the
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transceiver error counters are zero. To start eye-scan, set ES_REQ to 0x1 and
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wait for the same bit to self-clear. If eye-scan needs to be stopped, set the
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ES_REQ bit to 0x0.
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.. _axi_adxcvr table_one_label:
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Table 1
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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.. list-table::
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:header-rows: 1
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* - SYSCLK_SEL
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- 00
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- 01
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- 10
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- 11
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* - GTXE2
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- CPLL
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- RESERVED
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- RESERVED
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- QPLL
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* - GTHE3
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- CPLL
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- RESERVED
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- QPLL1
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- QPLL0
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* - GTHE4
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- CPLL
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- RESERVED
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- QPLL1
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- QPLL0
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* - GTYE4
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- CPLL
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- RESERVED
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- QPLL1
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- QPLL0
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.. _axi_adxcvr table_two_label:
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Table 2
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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.. list-table::
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:header-rows: 1
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* - OUTCLK_SEL
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- 001
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- 010
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- 011
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- 100
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- 101
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- All other combinations
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* - GTXE2
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- OUTCLKPCS
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- OUTCLKPMA
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- REFCLK
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- REFCLK/2
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- RESERVED
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- RESERVED
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* - GTHE3
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- OUTCLKPCS
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- OUTCLKPMA
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- REFCLK
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- REFCLK/2
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- PROGDIVCLK
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- RESERVED
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* - GTHE4
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- OUTCLKPCS
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- OUTCLKPMA
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- REFCLK
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- REFCLK/2
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- PROGDIVCLK
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- RESERVED
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* - GTYE4
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- OUTCLKPCS
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- OUTCLKPMA
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- REFCLK
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- REFCLK/2
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- PROGDIVCLK
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- RESERVED
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The REFCLK selected by OUTCLK_SEL depends on the SYSCLK_SEL, it may be CPLL,
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QPLL0 or QPLL1 refclk.
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Physical layer PRBS testing
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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The REG_PRBS_CNTRL and REG_PRBS_STATUS registers expose controls of internal
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PRBS generators and checkers allowing the testing the multi-gigabit serial link
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at the physical layer without the need of the link layer bringup.
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TX link procedure
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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#. Configure the reference clock and device clocks for under test lane rate.
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Bring XCVR out from reset.
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#. In the REG_PRBS_CNTRL registers set PRBSSEL to a non-zero value. See the
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transceiver guides for exact values, different transceiver families may have
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different encoding for the same pattern.
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#. On the receiving side of the link, set the checker for the same pattern and
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reset the error counters.
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#. No error should be recorded on the receiver side.
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#. Set the PRBSFORCEERR bit in the REG_PRBS_CNTRL register to force the error
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injection into the stream of bits.
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#. The error should be detected and recorded on the receiver side.
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RX link procedure
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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#. Configure the reference clock and device clocks for under test lane rate.
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Bring XCVR out from reset.
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#. On the transmit side of the link, set a test pattern that is available in the
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receiving transceiver. Consult the transceiver documentation for details.
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#. In the REG_PRBS_CNTRL registers set PRBSSEL to the corresponding pattern.
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Reset the error counters with PRBSCNTRESET.
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#. Check REG_PRBS_STATUS fields for results. If the check is successful for
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non-GTX transceivers the PRBSLOCKED bit must appear as set and PRBSERR must
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stay low. For GTX transceivers the PRBSLOCKED bit can be ignored and checking
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the PRBSERR alone is sufficient. If PRBSERR is set, check with DRP accesses
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the internal error counter to get the number of errors received. See the
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transceiver guide for details.
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More Information
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--------------------------------------------------------------------------------
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- :ref:`jesd204`
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- :dokuwiki:`JESD204B/C AXI_ADXCVR Highspeed Transceivers Linux Driver <resources/tools-software/linux-drivers/jesd204/axi_adxcvr>`
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Reference
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--------------------------------------------------------------------------------
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- :intel:`Intel® Arria® 10 Transceiver PHY User Guide <content/dam/www/programmable/us/en/pdfs/literature/hb/arria-10/ug_arria10_xcvr_phy.pdf>`
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- `7 Series FPGAs GTX/GTH Transceivers User Guide - AMD Xilinx <https://docs.amd.com/v/u/en-US/ug476_7Series_Transceivers>`_
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- `Ultrascale Architecture GTH Transceivers User Guide - AMD Xilinx <https://docs.amd.com/v/u/en-US/ug576-ultrascale-gth-transceivers>`_
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@ -16,3 +16,6 @@ Contents
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axi_dmac/index
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axi_dmac/index
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spi_engine/index
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spi_engine/index
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jesd204/index
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axi_adxcvr/index
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xilinx/index
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File diff suppressed because it is too large
Load Diff
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After Width: | Height: | Size: 59 KiB |
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@ -0,0 +1,348 @@
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.. _ad_ip_jesd204_tpl_adc:
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ADC JESD204B/C Transport Peripheral
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================================================================================
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.. hdl-component-diagram::
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The ADC JESD204B/C Transport Peripheral implements the transport level handling
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of a JESD204B/C transmitter device. It is compatible with a
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:ref:`wide range of Analog Devices high-speed analog-to-digital converters <ad_ip_jesd204_tpl_adc_supported_devices>`.
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The core handles the JESD204B/C deframing of the payload data.
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The peripheral can be configured at runtime through a AXI4-Lite memory mapped
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register map.
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Features
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--------------------------------------------------------------------------------
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- ADI high-speed ADC compatible JESD204B/C data deframing;
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- Test-pattern checker;
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- Per-channel data formatting (sign extension, two's complement to offset
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binary);
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- Runtime reconfigurability through memory-mapped register interface
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(AXI4-Lite).
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Files
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--------------------------------------------------------------------------------
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:git-hdl:`ad_ip_jesd204_tpl_adc.v <library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc.v>`
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Block Diagram
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-------------
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.. image:: ad_ip_jesd204_transport_adc.svg
|
||||||
|
:align: center
|
||||||
|
|
||||||
|
Synthesis Configuration Parameters
|
||||||
|
--------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
.. hdl-parameters::
|
||||||
|
|
||||||
|
* - ID
|
||||||
|
- Instance identification number.
|
||||||
|
* - NUM_LANES
|
||||||
|
- Number of lanes supported by the peripheral.
|
||||||
|
Equivalent to JESD204 ``L`` parameter.
|
||||||
|
* - NUM_CHANNELS
|
||||||
|
- Number of converters supported by the peripheral.
|
||||||
|
Equivalent to JESD204 ``M`` parameter.
|
||||||
|
* - SAMPLES_PER_FRAME
|
||||||
|
- Number of samples per frame.
|
||||||
|
Equivalent to JESD204 ``S`` parameter.
|
||||||
|
* - CONVERTER_RESOLUTION
|
||||||
|
- Resolution of the converter.
|
||||||
|
Equivalent to JESD204 ``N`` parameter.
|
||||||
|
* - BITS_PER_SAMPLE
|
||||||
|
- Number of bits per sample.
|
||||||
|
Equivalent to JESD204 ``NP`` parameter.
|
||||||
|
* - OCTETS_PER_BEAT
|
||||||
|
- Number of bytes per beat for each link.
|
||||||
|
* - TWOS_COMPLEMENT
|
||||||
|
- PRBS data format.
|
||||||
|
* - PN7_ENABLE
|
||||||
|
- Enable PN7 check.
|
||||||
|
* - PN15_ENABLE
|
||||||
|
- Enable PN15 check.
|
||||||
|
|
||||||
|
.. *- PN31_ENABLE
|
||||||
|
.. - Enable PN31 check.
|
||||||
|
|
||||||
|
Signal and Interface Pins
|
||||||
|
--------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
.. hdl-interfaces::
|
||||||
|
|
||||||
|
* - s_axi_aclk
|
||||||
|
- All ``S_AXI`` signals are synchronous to this clock.
|
||||||
|
* - s_axi_aresetn
|
||||||
|
- Resets the internal state of the peripheral.
|
||||||
|
* - s_axi
|
||||||
|
- Memory mapped AXI-lite bus that provides access to modules register map.
|
||||||
|
* - link
|
||||||
|
- link_data: JESD204 link data interface (link layer interface).
|
||||||
|
* - link_clk
|
||||||
|
- :dokuwiki:`Device clock <resources/fpga/peripherals/jesd204/jesd204_glossary#clocks>`
|
||||||
|
for the JESD204B interface of the Link Layer Interface. Must
|
||||||
|
be line clock/40 for correct 204B operation. Must be line
|
||||||
|
clock/66 for correct 64b66b 204C operation.
|
||||||
|
* - enable
|
||||||
|
- Channel enable indicator of the Application layer Interface
|
||||||
|
* - adc_valid
|
||||||
|
- Qualifier signal for each channel of the Application layer
|
||||||
|
interface. Always '1'.
|
||||||
|
* - adc_data
|
||||||
|
- Raw application layer data, every channel concatenated
|
||||||
|
(Application layer interface).
|
||||||
|
* - adc_dovf
|
||||||
|
- Application layer overflow of the Application layer interface.
|
||||||
|
|
||||||
|
The S_AXI interface is synchronous to the s_axi_aclk clock. All other signals
|
||||||
|
and interfaces are synchronous to the device_clk clock.
|
||||||
|
|
||||||
|
Register Map
|
||||||
|
--------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
.. hdl-regmap::
|
||||||
|
:name: COMMON
|
||||||
|
:no-type-info:
|
||||||
|
|
||||||
|
.. hdl-regmap::
|
||||||
|
:name: ADC_COMMON
|
||||||
|
:no-type-info:
|
||||||
|
|
||||||
|
.. hdl-regmap::
|
||||||
|
:name: JESD_TPL
|
||||||
|
:no-type-info:
|
||||||
|
|
||||||
|
.. hdl-regmap::
|
||||||
|
:name: ADC_CHANNEL
|
||||||
|
:no-type-info:
|
||||||
|
|
||||||
|
Theory of Operation
|
||||||
|
--------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
Interfaces and Signals
|
||||||
|
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
|
||||||
|
Configuration Interface
|
||||||
|
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||||
|
|
||||||
|
The Peripheral features a register map configuration interface that can be
|
||||||
|
accessed through the AXI4-Lite ``S_AXI`` port. The register map can be used to
|
||||||
|
configure the Peripheral's operational parameters, query the current status of
|
||||||
|
the device and query the features supported by the device.
|
||||||
|
|
||||||
|
Link layer interface
|
||||||
|
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||||
|
|
||||||
|
The link layer interface description can be found in the
|
||||||
|
:ref:`User Data Interface <axi_jesd204_rx_user_data>` section of the
|
||||||
|
:ref:`JESD204B/C Link Receive Peripheral <axi_jesd204_rx>` IP.
|
||||||
|
|
||||||
|
Application layer interface
|
||||||
|
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||||
|
|
||||||
|
The application layer is connected to the deframer block output. The deframer
|
||||||
|
module creates sample data from the lane mapped and formatted JESD204 link data
|
||||||
|
based on the specified deframer configuration.
|
||||||
|
|
||||||
|
The data in the application layer interface ``adc_data`` has the following
|
||||||
|
layout:
|
||||||
|
|
||||||
|
::
|
||||||
|
|
||||||
|
MSB LSB
|
||||||
|
[ MmSn, ..., MmS1, MnS0, ..., M1Sn, ... M1S1, M1S0, M0Sn, ... M0S1, M0S0 ]
|
||||||
|
|
||||||
|
Where MjSi refers to the i-th sample of the j-th converter. With m being the
|
||||||
|
number of converters and n the number of samples per converter per beat.
|
||||||
|
|
||||||
|
The core asserts the ``enable`` signal for each channel that is enabled by the
|
||||||
|
software.
|
||||||
|
|
||||||
|
Clock Monitor
|
||||||
|
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||||
|
|
||||||
|
The ``REG_STATUS`` (``0x054``) register ``CLK_FREQ`` field allows to determine
|
||||||
|
the clock rate of the device clock (``link_clk``) relative to the AXI interface
|
||||||
|
clock (``s_axi_aclk``). This can be used to verify that the device clock is
|
||||||
|
running at the expected rate.
|
||||||
|
|
||||||
|
The number is represented as unsigned 16.16 format. Assuming a 100MHz processor
|
||||||
|
clock, this corresponds to a resolution of 1.523kHz per LSB. A raw value of 0
|
||||||
|
indicates that the link clock is currently not active.
|
||||||
|
|
||||||
|
Data Formatter
|
||||||
|
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||||
|
|
||||||
|
The component is configured by the ``REG_CHAN_CNTRL`` register
|
||||||
|
``FORMAT_SIGNEXT,FORMAT_TYPE,FORMAT_ENABLE`` fields. The block introduces one
|
||||||
|
clock cycle latency.
|
||||||
|
|
||||||
|
PRBS Check
|
||||||
|
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||||
|
|
||||||
|
The block can monitor and compare the incoming deframed raw data against
|
||||||
|
PN9, PN23 and PN7, PN15 (if enabled) patterns selected by the ``ADC_PN_SEL``
|
||||||
|
field of ``REG_CHAN_CNTRL_3`` register.
|
||||||
|
|
||||||
|
..
|
||||||
|
it is missing PN31, because it does not exist on the source code
|
||||||
|
|
||||||
|
.. list-table::
|
||||||
|
:header-rows: 1
|
||||||
|
|
||||||
|
* - ADC_PN_SEL
|
||||||
|
- PN
|
||||||
|
- ENABLE
|
||||||
|
* - 0
|
||||||
|
- PN9
|
||||||
|
- 1
|
||||||
|
* - 1
|
||||||
|
- PN23
|
||||||
|
- 1
|
||||||
|
* - 4
|
||||||
|
- PN7
|
||||||
|
- PN7_ENABLE
|
||||||
|
* - 5
|
||||||
|
- PN15
|
||||||
|
- PN15_ENABLE
|
||||||
|
|
||||||
|
.. *-7
|
||||||
|
.. -PN31
|
||||||
|
.. -PN31_ENABLE
|
||||||
|
|
||||||
|
Before performing these tests you need to make sure that the ADC OUTPUT FORMAT
|
||||||
|
is set according to the ``TWOS_COMPLEMENT`` synthesis parameter.
|
||||||
|
|
||||||
|
For each channel, mismatches are reported in ``PN_ERR`` and ``PN_OOS`` fields of
|
||||||
|
the ``REG_CHAN_STATUS`` register.
|
||||||
|
|
||||||
|
External synchronization
|
||||||
|
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||||
|
|
||||||
|
An external synchronization signal ``adc_sync_in`` can be used to trigger data
|
||||||
|
movement from the link layer to user application layer.
|
||||||
|
|
||||||
|
The external synchronization signal should be synchronous with the ADC clock.
|
||||||
|
Synchronization will be done on the rising edge of the signal.
|
||||||
|
|
||||||
|
The self clearing ``SYNC`` control bit from the ``REG_CNTRL (0x44)`` register,
|
||||||
|
will arm the trigger logic to wait for the external sync signal. The
|
||||||
|
``ADC_SYNC`` status bit from ``REG_SYNC_STATUS (0x68)`` register, will show that
|
||||||
|
the synchronization is armed, but the synchronization signal has not yet been
|
||||||
|
received.
|
||||||
|
|
||||||
|
Once the sync signal is received, the data will start to flow and the
|
||||||
|
``ADC_SYNC`` status bit will reflect that with a deassertion.
|
||||||
|
|
||||||
|
While the synchronization mechanism is armed, the ``adc_rst`` output signal is
|
||||||
|
set such that downstream logic can be cleared, to have a fresh start once the
|
||||||
|
trigger is received.
|
||||||
|
|
||||||
|
Software Support
|
||||||
|
--------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
.. warning::
|
||||||
|
To ensure correct operation, it is highly recommended to use the
|
||||||
|
Analog Devices provided JESD204B/C software packages for interfacing the
|
||||||
|
peripheral. Analog Devices is not able to provide support in case issues arise
|
||||||
|
from using custom low-level software for interfacing the peripheral.
|
||||||
|
|
||||||
|
Restrictions
|
||||||
|
--------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
Reduced number of octets-per-frame (``F``) settings. The following values are
|
||||||
|
supported by the peripheral: 1, 2, 4
|
||||||
|
|
||||||
|
- Starting from
|
||||||
|
`this <https://github.com/analogdevicesinc/hdl/commit/454b900f90081fb95be857114e768f662178c8bd>`__
|
||||||
|
commit this restriction no longer applies.
|
||||||
|
|
||||||
|
.. _ad_ip_jesd204_tpl_adc_supported_devices:
|
||||||
|
|
||||||
|
Supported Devices
|
||||||
|
--------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
JESD204B Analog-to-Digital Converters
|
||||||
|
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
|
||||||
|
- :adi:`AD6673 <en/products/AD6673>`: 80 MHz Bandwidth, Dual IF Receiver
|
||||||
|
- :adi:`AD6674 <en/products/AD6674>`: 385 MHz BW IF Diversity Receiver
|
||||||
|
- :adi:`AD6676 <en/products/AD6676>`: Wideband IF Receiver Subsystem
|
||||||
|
- :adi:`AD6677 <en/products/AD6677>`: 80 MHz Bandwidth, IF Receiver
|
||||||
|
- :adi:`AD6684 <en/products/AD6684>`: 135 MHz Quad IF Receiver
|
||||||
|
- :adi:`AD6688 <en/products/AD6688>`: RF Diversity and 1.2GHz BW Observation
|
||||||
|
Receiver
|
||||||
|
- :adi:`AD9207 <en/products/AD9207>`: 12-Bit, 6 GSPS, JESD204B/JESD204C
|
||||||
|
Dual Analog-to-Digital Converter
|
||||||
|
- :adi:`AD9208 <en/products/AD9208>`: 14-Bit, 3GSPS, JESD204B,
|
||||||
|
Dual Analog-to-Digital Converter
|
||||||
|
- :adi:`AD9209 <en/products/AD9209>`: 12-Bit, 4GSPS, JESD204B/C, Quad
|
||||||
|
Analog-to-Digital Converter
|
||||||
|
- :adi:`AD9213 <en/products/AD9213>`: 12-Bit, 10.25 GSPS, JESD204B, RF
|
||||||
|
Analog-to-Digital Converter
|
||||||
|
- :adi:`AD9234 <en/products/AD9234>`: 12-Bit, 1 GSPS/500 MSPS JESD204B, Dual
|
||||||
|
Analog-to-Digital Converter
|
||||||
|
- :adi:`AD9250 <en/products/AD9250>`: 14-Bit, 170 MSPS/250 MSPS, JESD204B, Dual
|
||||||
|
Analog-to-Digital Converter
|
||||||
|
- :adi:`AD9625 <en/products/AD9625>`: 12-Bit, 2.6 GSPS/2.5 GSPS/2.0 GSPS,
|
||||||
|
1.3 V/2.5 V Analog-to-Digital Converter
|
||||||
|
- :adi:`AD9656 <en/products/AD9656>`: Quad, 16-Bit, 125 MSPS JESD204B 1.8 V
|
||||||
|
Analog-to-Digital Converter
|
||||||
|
- :adi:`AD9680 <en/products/AD9680>`: 14-Bit, 1.25 GSPS/1 GSPS/820 MSPS/500
|
||||||
|
MSPS JESD204B, Dual Analog-to-Digital Converter
|
||||||
|
- :adi:`AD9683 <en/products/AD9683>`: 14-Bit, 170 MSPS/250 MSPS, JESD204B,
|
||||||
|
Analog-to-Digital Converter
|
||||||
|
- :adi:`AD9690 <en/products/AD9690>`: 14-Bit, 500 MSPS / 1 GSPS JESD204B,
|
||||||
|
Analog-to-Digital Converter
|
||||||
|
- :adi:`AD9691 <en/products/AD9691>`: 14-Bit, 1.25 GSPS JESD204B,
|
||||||
|
Dual Analog-to-Digital Converter
|
||||||
|
- :adi:`AD9694 <en/products/AD9694>`: 14-Bit, 500 MSPS JESD204B, Quad
|
||||||
|
Analog-to-Digital Converter
|
||||||
|
- :adi:`AD9695 <en/products/AD9695>`: 14-Bit, 1300 MSPS/625 MSPS,
|
||||||
|
JESD204B, Dual Analog-to-Digital Converter Analog-to-Digital Converter
|
||||||
|
- :adi:`AD9083 <en/products/AD9083>`: 16-Channel, 125 MHz Bandwidth, JESD204B
|
||||||
|
Analog-to-Digital Converter
|
||||||
|
- :adi:`AD9094 <en/products/AD9094>`: 8-Bit, 1 GSPS, JESD204B, Quad
|
||||||
|
Analog-to-Digital Converter
|
||||||
|
|
||||||
|
JESD204B RF Transceivers
|
||||||
|
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
|
||||||
|
- :adi:`AD9371 <en/products/AD9371>`: SDR Integrated, Dual RF Transceiver with
|
||||||
|
Observation Path
|
||||||
|
- :adi:`AD9375 <en/products/AD9375>`: SDR Integrated, Dual RF Transceiver with
|
||||||
|
Observation Path and DPD
|
||||||
|
- :adi:`ADRV9009 <en/products/ADRV9009>`: SDR Integrated, Dual RF Transceiver
|
||||||
|
with Observation Path
|
||||||
|
- :adi:`ADRV9008-1 <en/products/ADRV9008-1>`: SDR Integrated, Dual RF Receiver
|
||||||
|
- :adi:`ADRV9008-2 <en/products/ADRV9008-2>`: SDR Integrated, Dual RF
|
||||||
|
Transmitter with Observation Path
|
||||||
|
|
||||||
|
JESD204B/C Mixed-Signal Front Ends
|
||||||
|
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
|
||||||
|
- :adi:`AD9081 <en/products/AD9081>`: MxFE™ Quad, 16-Bit, 12GSPS RFDAC and
|
||||||
|
Quad, 12-Bit, 4GSPS RFADC
|
||||||
|
- :adi:`AD9082 <en/products/AD9082>`: MxFE™ QUAD, 16-Bit, 12GSPS RFDAC and
|
||||||
|
DUAL, 12-Bit, 6GSPS RFADC
|
||||||
|
- :adi:`AD9986 <en/products/AD9986>`: 4T2R Direct RF Transmitter and
|
||||||
|
Observation Receiver
|
||||||
|
- :adi:`AD9988 <en/products/AD9988>`: 4T4R Direct RF Receiver and Transmitter
|
||||||
|
|
||||||
|
More Information
|
||||||
|
--------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
- :ref:`JESD204 Interface Framework <jesd204>`
|
||||||
|
- :dokuwiki:`Glossary of terms <resources/fpga/peripherals/jesd204/jesd204_glossary>`
|
||||||
|
- :ref:`HDL User Guide <user_guide>`
|
||||||
|
|
||||||
|
Technical Support
|
||||||
|
--------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
Analog Devices will provide limited online support for anyone using the core
|
||||||
|
with Analog Devices components (ADC, DAC, Video, Audio, etc) via the
|
||||||
|
:ez:`EngineerZone <fpga>`.
|
||||||
File diff suppressed because it is too large
Load Diff
|
After Width: | Height: | Size: 66 KiB |
|
|
@ -0,0 +1,300 @@
|
||||||
|
.. _ad_ip_jesd204_tpl_dac:
|
||||||
|
|
||||||
|
DAC JESD204B/C Transport Peripheral
|
||||||
|
================================================================================
|
||||||
|
|
||||||
|
.. hdl-component-diagram::
|
||||||
|
|
||||||
|
The DAC JESD204B/C Transport Peripheral (AD-IP-JESD204-TRANSPORT-DAC) implements
|
||||||
|
the transport level handling of a JESD204B/C transmitter device. It is
|
||||||
|
compatible with a
|
||||||
|
:ref:`wide range of Analog Devices high-speed digital-to-analog converters <ad_ip_jesd204_tpl_dac_supported_devices>`.
|
||||||
|
|
||||||
|
The core handles the JESD204B/C framing of the user-provided payload data. In
|
||||||
|
addition, it is capable of generating standard and user-defined test-pattern
|
||||||
|
data for interface verification. It also features a per-channel dual-tone DDS
|
||||||
|
that can be used to dynamically generate test-tones.
|
||||||
|
|
||||||
|
The peripheral can be configured at runtime through a AXI4-Lite memory mapped
|
||||||
|
register map.
|
||||||
|
|
||||||
|
Features
|
||||||
|
--------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
- ADI high-speed DAC compatible JESD204B/C data framing;
|
||||||
|
- Test-pattern generator for interface verification;
|
||||||
|
- Per-channel dual-tone DDS (optional);
|
||||||
|
- Runtime reconfigurability through memory-mapped register interface
|
||||||
|
(AXI4-Lite).
|
||||||
|
|
||||||
|
Files
|
||||||
|
--------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
:git-hdl:`ad_ip_jesd204_tpl_dac.v <library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac.v>`
|
||||||
|
|
||||||
|
Block Diagram
|
||||||
|
--------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
.. image:: ad_ip_jesd204_transport_dac.svg
|
||||||
|
:align: center
|
||||||
|
|
||||||
|
Synthesis Configuration Parameters
|
||||||
|
--------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
.. hdl-parameters::
|
||||||
|
|
||||||
|
* - ID
|
||||||
|
- Instance identification number.
|
||||||
|
* - NUM_LANES
|
||||||
|
- Number of lanes supported by the peripheral.
|
||||||
|
Equivalent to JESD204 ``L`` parameter.
|
||||||
|
* - NUM_CHANNELS
|
||||||
|
- Number of converters supported by the peripheral.
|
||||||
|
- Equivalent to JESD204 ``M`` parameter.
|
||||||
|
* - SAMPLES_PER_FRAME
|
||||||
|
- Number of samples per frame.
|
||||||
|
Equivalent to JESD204 ``S`` parameter.
|
||||||
|
* - CONVERTER_RESOLUTION
|
||||||
|
- Resolution of the converter.
|
||||||
|
Equivalent to JESD204 ``N`` parameter.
|
||||||
|
* - BITS_PER_SAMPLE
|
||||||
|
- Number of bits per sample.
|
||||||
|
Equivalent to JESD204 ``NP`` parameter.
|
||||||
|
* - OCTETS_PER_BEAT
|
||||||
|
- Number of bytes per beat for each link.
|
||||||
|
* - DDS_TYPE
|
||||||
|
- DDS Type. Set 1 for CORDIC or 2 for Polynomial
|
||||||
|
* - DDS_CORDIC_DW
|
||||||
|
- CORDIC DDS Data Width.
|
||||||
|
* - DDS_CORDIC_PHASE_DW
|
||||||
|
- CORDIC DDS Phase Width.
|
||||||
|
* - DATAPATH_DISABLE
|
||||||
|
- Disable instantiation of DDS core.
|
||||||
|
|
||||||
|
Signal and Interface Pins
|
||||||
|
--------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
.. hdl-interfaces::
|
||||||
|
|
||||||
|
* - s_axi_aclk
|
||||||
|
- All ``S_AXI`` signals and ``irq`` are synchronous to this clock.
|
||||||
|
* - s_axi_aresetn
|
||||||
|
- Resets the internal state of the peripheral.
|
||||||
|
* - s_axi
|
||||||
|
- Memory mapped AXI-lite bus that provides access to modules register map.
|
||||||
|
* - link
|
||||||
|
- link_data: Framed transmit data towards link layer.
|
||||||
|
* - link_clk
|
||||||
|
- :dokuwiki:`Device clock <resources/fpga/peripherals/jesd204/jesd204_glossary#clocks>`
|
||||||
|
for the JESD204B/C interface. Must be line clock/40 for 204B correct operation.
|
||||||
|
Must be line clock/66 for correct 204C operation.
|
||||||
|
* - enable
|
||||||
|
- Request signal for each channel.
|
||||||
|
* - dac_valid
|
||||||
|
- Qualifier signal for each channel. Always '1'.
|
||||||
|
* - dac_ddata
|
||||||
|
- Raw application layer data, every channel concatenated.
|
||||||
|
* - dac_dunf
|
||||||
|
- Application layer underflow.
|
||||||
|
|
||||||
|
Register Map
|
||||||
|
--------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
.. hdl-regmap::
|
||||||
|
:name: COMMON
|
||||||
|
:no-type-info:
|
||||||
|
|
||||||
|
.. hdl-regmap::
|
||||||
|
:name: DAC_COMMON
|
||||||
|
:no-type-info:
|
||||||
|
|
||||||
|
.. hdl-regmap::
|
||||||
|
:name: JESD_TPL
|
||||||
|
:no-type-info:
|
||||||
|
|
||||||
|
.. hdl-regmap::
|
||||||
|
:name: DAC_CHANNEL
|
||||||
|
:no-type-info:
|
||||||
|
|
||||||
|
Theory of Operation
|
||||||
|
--------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
Data paths
|
||||||
|
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
|
||||||
|
The data intended for the DAC can have multiple sources:
|
||||||
|
|
||||||
|
- **DMA source** Raw data can be accepted from a external block representing
|
||||||
|
the Application layer;
|
||||||
|
- **DDS source** For each DAC channel, a dual-tone can be generated by a DDS
|
||||||
|
core;
|
||||||
|
- **PRBS source** For each DAC channel, one of the following PN sequence can
|
||||||
|
be selected: PN7, PN15, inverted PN7, inverted PN15.
|
||||||
|
|
||||||
|
Interfaces and Signals
|
||||||
|
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
|
||||||
|
Application layer interface
|
||||||
|
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||||
|
|
||||||
|
The application layer connects to the framer block when the DMA source is
|
||||||
|
selected. The framer module takes sample data and maps it onto the format that
|
||||||
|
the JESD204 link expects for the specified framer configuration.
|
||||||
|
|
||||||
|
The data in the application layer interface ``dac_ddata`` is expected to have
|
||||||
|
the following layout:
|
||||||
|
|
||||||
|
::
|
||||||
|
|
||||||
|
MSB LSB
|
||||||
|
[ MmSn, ..., MmS1, MnS0, ..., M1Sn, ... M1S1, M1S0, M0Sn, ... M0S1, M0S0 ]
|
||||||
|
|
||||||
|
|
||||||
|
Where MjSi refers to the i-th sample of the j-th converter. With m being the
|
||||||
|
number of converters and n the number of samples per converter per beat.
|
||||||
|
|
||||||
|
The core asserts the ``enable`` signal for each channel that is enabled by the
|
||||||
|
software. The ``dac_ddata`` data bus must contain data for each channel
|
||||||
|
regardless if the channels are enabled or not.
|
||||||
|
|
||||||
|
Link layer interface
|
||||||
|
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||||
|
|
||||||
|
The link layer interface description can be found in the
|
||||||
|
:ref:`User Data Interface <axi_jesd204_tx_user_data>` section of the
|
||||||
|
:ref:`JESD204B/C Link Transmit Peripheral <axi_jesd204_tx>` IP.
|
||||||
|
|
||||||
|
Clock Monitor
|
||||||
|
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||||
|
|
||||||
|
The ``REG_STATUS`` (``0x054``) register ``CLK_FREQ`` field allows to determine
|
||||||
|
the clock rate of the device clock (``link_clk``) relative to the AXI interface
|
||||||
|
clock (``s_axi_aclk``). This can be used to verify that the device clock is
|
||||||
|
running at the expected rate.
|
||||||
|
|
||||||
|
The number is represented as unsigned 16.16 format. Assuming a 100MHz processor
|
||||||
|
clock, this corresponds to a resolution of 1.523kHz per LSB. A raw value of 0
|
||||||
|
indicates that the link clock is currently not active.
|
||||||
|
|
||||||
|
External synchronization
|
||||||
|
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||||
|
|
||||||
|
By setting the ``EXT_SYNC`` parameter of the IP to 1, an external
|
||||||
|
synchronization signal ``dac_sync_in`` can be used to trigger data movement
|
||||||
|
from user application layer to the link layer, reset internal DDS cores or PRBS
|
||||||
|
generators. If the ``EXT_SYNC`` parameter is set to zero, the external signal
|
||||||
|
is ignored and only a software controlled reset happens inside the DDS,
|
||||||
|
PRBS logic.
|
||||||
|
|
||||||
|
The external synchronization signal should be synchronous with the DAC clock.
|
||||||
|
Synchronization will be done on the rising edge of the signal.
|
||||||
|
|
||||||
|
The self clearing ``SYNC`` control bit from the ``REG_CNTRL_1`` (``0x44``)
|
||||||
|
register will arm the trigger logic to wait for the external sync signal. The
|
||||||
|
``DAC_SYNC_STATUS`` status bit from the ``REG_SYNC_STATUS`` (``0x68``) register
|
||||||
|
will show that the synchronization is armed but the synchronization signal has
|
||||||
|
not yet been received.
|
||||||
|
|
||||||
|
Once the sync signal is received, the data will start to flow and the
|
||||||
|
``DAC_SYNC_STATUS`` status bit will reflect that with a deassertion.
|
||||||
|
|
||||||
|
While the synchronization mechanism is armed, the ``dac_valid`` output signal
|
||||||
|
is gated until the trigger signal is received. The gating happens only during
|
||||||
|
this period, meaning that ``dac_valid`` will stay high in all other
|
||||||
|
cases (normal operation).
|
||||||
|
|
||||||
|
Restrictions
|
||||||
|
--------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
Reduced number of octets-per-frame (``F``) settings. The following values are
|
||||||
|
supported by the peripheral: 1, 2, 4
|
||||||
|
|
||||||
|
- Starting from
|
||||||
|
`this <https://github.com/analogdevicesinc/hdl/commit/454b900f90081fb95be857114e768f662178c8bd>`__
|
||||||
|
commit this restriction no longer applies
|
||||||
|
|
||||||
|
Software Support
|
||||||
|
--------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
.. warning::
|
||||||
|
To ensure correct operation it is highly recommended to use the Analog
|
||||||
|
Devices provided JESD204B/C software packages for interfacing the peripheral.
|
||||||
|
Analog Devices is not able to provide support in case issues arise from using
|
||||||
|
custom low-level software for interfacing the peripheral.
|
||||||
|
|
||||||
|
.. _ad_ip_jesd204_tpl_dac_supported_devices:
|
||||||
|
|
||||||
|
Supported Devices
|
||||||
|
--------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
JESD204B Digital-to-Analog Converters
|
||||||
|
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
|
||||||
|
- :adi:`AD9135 <en/products/AD9135>`: Dual, 11-Bit, high dynamic, 2.8 GSPS,
|
||||||
|
TxDAC+® Digital-to-Analog Converter
|
||||||
|
- :adi:`AD9136 <en/products/AD9136>`: Dual, 16-Bit, 2.8 GSPS, TxDAC+®
|
||||||
|
Digital-to-Analog Converter
|
||||||
|
- :adi:`AD9144 <en/products/AD9144>`: Quad, 16-Bit, 2.8 GSPS, TxDAC+®
|
||||||
|
Digital-to-Analog Converter
|
||||||
|
- :adi:`AD9152 <en/products/AD9152>`: Dual, 16-Bit, 2.25 GSPS, TxDAC+
|
||||||
|
Digital-to-Analog Converter
|
||||||
|
- :adi:`AD9154 <en/products/AD9154>`: Quad, 16-Bit, 2.4 GSPS, TxDAC+®
|
||||||
|
Digital-to-Analog Converter
|
||||||
|
- :adi:`AD9161 <en/products/AD9161>`: 11-Bit, 12 GSPS, RF Digital-to-Analog
|
||||||
|
Converter
|
||||||
|
- :adi:`AD9162 <en/products/AD9162>`: 16-Bit, 12 GSPS, RF Digital-to-Analog
|
||||||
|
Converter
|
||||||
|
- :adi:`AD9163 <en/products/AD9163>`: 16-Bit, 12 GSPS, RF DAC and Digital
|
||||||
|
Upconverter
|
||||||
|
- :adi:`AD9164 <AD9164>`: 16-Bit, 12 GSPS, RF DAC and Direct Digital
|
||||||
|
Synthesizer
|
||||||
|
- :adi:`AD9172 <en/products/AD9172>`: Dual, 16-Bit, 12.6 GSPS RF DAC with
|
||||||
|
Channelizers
|
||||||
|
- :adi:`AD9173 <en/products/AD9173>`: Dual, 16-Bit, 12.6 GSPS RF DAC with
|
||||||
|
Channelizers
|
||||||
|
- :adi:`AD9174 <en/products/AD9174>`: Dual, 16-Bit, 12.6 GSPS RF DAC and Direct
|
||||||
|
Digital Synthesizer
|
||||||
|
- :adi:`AD9175 <en/products/AD9175>`: Dual, 11-Bit/16-Bit, 12.6 GSPS RF DAC with
|
||||||
|
Wideband Channelizers
|
||||||
|
- :adi:`AD9176 <en/products/AD9176>`: Dual, 16-Bit, 12.6 GSPS RF DAC with
|
||||||
|
Wideband Channelizers
|
||||||
|
- :adi:`AD9177 <en/products/AD9177>`: Quad, 16-Bit, 12 GSPS RF DAC with
|
||||||
|
Wideband Channelizers
|
||||||
|
|
||||||
|
JESD204B RF Transceivers
|
||||||
|
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
|
||||||
|
- :adi:`AD9371 <en/products/AD9371>`: SDR Integrated, Dual RF Transceiver with
|
||||||
|
Observation Path
|
||||||
|
- :adi:`AD9375 <en/products/AD9375>`: SDR Integrated, Dual RF Transceiver with
|
||||||
|
Observation Path and DPD
|
||||||
|
- :adi:`ADRV9009 <en/products/ADRV9009>`: SDR Integrated, Dual RF Transceiver
|
||||||
|
with Observation Path
|
||||||
|
- :adi:`ADRV9008-1 <en/products/ADRV9008-1>`: SDR Integrated, Dual RF Receiver
|
||||||
|
- :adi:`ADRV9008-2 <en/products/ADRV9008-2>`: SDR Integrated, Dual RF
|
||||||
|
Transmitter with Observation Path
|
||||||
|
|
||||||
|
JESD204B/C Mixed-Signal Front Ends
|
||||||
|
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
|
||||||
|
- :adi:`AD9081 <en/products/AD9081>`: MxFE™ Quad, 16-Bit, 12GSPS RFDAC and
|
||||||
|
Quad, 12-Bit, 4GSPS RFADC
|
||||||
|
- :adi:`AD9082 <en/products/AD9082>`: MxFE™ QUAD, 16-Bit, 12GSPS RFDAC and
|
||||||
|
DUAL, 12-Bit, 6GSPS RFADC
|
||||||
|
- :adi:`AD9986 <en/products/AD9986>`: 4T2R Direct RF Transmitter and
|
||||||
|
Observation Receiver
|
||||||
|
- :adi:`AD9988 <en/products/AD9988>`: 4T4R Direct RF Receiver and Transmitter
|
||||||
|
|
||||||
|
More Information
|
||||||
|
--------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
- :ref:`JESD204 Interface Framework <jesd204>`
|
||||||
|
- :dokuwiki:`Glossary of terms <resources/fpga/peripherals/jesd204/jesd204_glossary>`
|
||||||
|
- :ref:`HDL User Guide <user_guide>`
|
||||||
|
|
||||||
|
Technical Support
|
||||||
|
--------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
Analog Devices will provide limited online support for anyone using the core
|
||||||
|
with Analog Devices components (ADC, DAC, Video, Audio, etc) via the
|
||||||
|
:ez:`EngineerZone <fpga>`.
|
||||||
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|
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|
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|
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d="m 73.180397,26.919243 19.254899,15.41408"
|
||||||
|
id="path26-5" />
|
||||||
|
<text
|
||||||
|
xml:space="preserve"
|
||||||
|
style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:12px;font-family:sans-serif;-inkscape-font-specification:'sans-serif, ';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-variant-east-asian:normal;text-align:start;letter-spacing:0px;word-spacing:0px;text-anchor:start;fill:none;stroke:none;stroke-width:0.415661;stroke-linejoin:round;stroke-dasharray:none"
|
||||||
|
x="127.15289"
|
||||||
|
y="331.22256"
|
||||||
|
id="text16-4-1-0-4-8"><tspan
|
||||||
|
x="127.15289"
|
||||||
|
y="331.22256"
|
||||||
|
style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:12px;font-family:sans-serif;-inkscape-font-specification:'sans-serif, ';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-variant-east-asian:normal;text-align:start;letter-spacing:0px;text-anchor:start;fill:#000000;fill-opacity:1;stroke:none;stroke-width:0.415661"
|
||||||
|
id="tspan27-2-3-1">All lanes are in</tspan><tspan
|
||||||
|
x="127.15289"
|
||||||
|
y="343.72256"
|
||||||
|
style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:12px;font-family:sans-serif;-inkscape-font-specification:'sans-serif, ';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-variant-east-asian:normal;text-align:start;letter-spacing:0px;text-anchor:start;fill:#000000;fill-opacity:1;stroke:none;stroke-width:0.415661"
|
||||||
|
id="tspan6">the DATA phase</tspan></text>
|
||||||
|
<text
|
||||||
|
xml:space="preserve"
|
||||||
|
style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:12px;font-family:sans-serif;-inkscape-font-specification:'sans-serif, ';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-variant-east-asian:normal;text-align:start;letter-spacing:0px;word-spacing:0px;text-anchor:start;fill:none;stroke:none;stroke-width:0.415661;stroke-linejoin:round;stroke-dasharray:none"
|
||||||
|
x="10.411446"
|
||||||
|
y="546.25116"
|
||||||
|
id="text16-4-1-0-4-8-4"><tspan
|
||||||
|
x="10.411446"
|
||||||
|
y="546.25116"
|
||||||
|
style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:12px;font-family:sans-serif;-inkscape-font-specification:'sans-serif, ';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-variant-east-asian:normal;text-align:start;letter-spacing:0px;text-anchor:start;fill:#000000;fill-opacity:1;stroke:none;stroke-width:0.415661"
|
||||||
|
id="tspan6-1">At least four</tspan><tspan
|
||||||
|
x="10.411446"
|
||||||
|
y="558.75116"
|
||||||
|
style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:12px;font-family:sans-serif;-inkscape-font-specification:'sans-serif, ';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-variant-east-asian:normal;text-align:start;letter-spacing:0px;text-anchor:start;fill:#000000;fill-opacity:1;stroke:none;stroke-width:0.415661"
|
||||||
|
id="tspan10">consecutive</tspan><tspan
|
||||||
|
x="10.411446"
|
||||||
|
y="571.25116"
|
||||||
|
style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:12px;font-family:sans-serif;-inkscape-font-specification:'sans-serif, ';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-variant-east-asian:normal;text-align:start;letter-spacing:0px;text-anchor:start;fill:#000000;fill-opacity:1;stroke:none;stroke-width:0.415661"
|
||||||
|
id="tspan11">/K/ characters</tspan><tspan
|
||||||
|
x="10.411446"
|
||||||
|
y="583.75116"
|
||||||
|
style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:12px;font-family:sans-serif;-inkscape-font-specification:'sans-serif, ';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-variant-east-asian:normal;text-align:start;letter-spacing:0px;text-anchor:start;fill:#000000;fill-opacity:1;stroke:none;stroke-width:0.415661"
|
||||||
|
id="tspan12">are received</tspan></text>
|
||||||
|
<text
|
||||||
|
xml:space="preserve"
|
||||||
|
style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:12px;font-family:sans-serif;-inkscape-font-specification:'sans-serif, ';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-variant-east-asian:normal;text-align:start;letter-spacing:0px;word-spacing:0px;text-anchor:start;fill:none;stroke:none;stroke-width:0.415661;stroke-linejoin:round;stroke-dasharray:none"
|
||||||
|
x="151.89297"
|
||||||
|
y="550.39148"
|
||||||
|
id="text16-4-1-0-4-8-4-7"><tspan
|
||||||
|
x="151.89297"
|
||||||
|
y="550.39148"
|
||||||
|
style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:12px;font-family:sans-serif;-inkscape-font-specification:'sans-serif, ';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-variant-east-asian:normal;text-align:start;letter-spacing:0px;text-anchor:start;fill:#000000;fill-opacity:1;stroke:none;stroke-width:0.415661"
|
||||||
|
id="tspan12-9">More than three</tspan><tspan
|
||||||
|
x="151.89297"
|
||||||
|
y="562.89148"
|
||||||
|
style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:12px;font-family:sans-serif;-inkscape-font-specification:'sans-serif, ';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-variant-east-asian:normal;text-align:start;letter-spacing:0px;text-anchor:start;fill:#000000;fill-opacity:1;stroke:none;stroke-width:0.415661"
|
||||||
|
id="tspan15">invalid characters</tspan><tspan
|
||||||
|
x="151.89297"
|
||||||
|
y="575.39148"
|
||||||
|
style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:12px;font-family:sans-serif;-inkscape-font-specification:'sans-serif, ';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-variant-east-asian:normal;text-align:start;letter-spacing:0px;text-anchor:start;fill:#000000;fill-opacity:1;stroke:none;stroke-width:0.415661"
|
||||||
|
id="tspan16">are received</tspan></text>
|
||||||
|
<text
|
||||||
|
xml:space="preserve"
|
||||||
|
style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:12px;font-family:sans-serif;-inkscape-font-specification:'sans-serif, ';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-variant-east-asian:normal;text-align:start;letter-spacing:0px;word-spacing:0px;text-anchor:start;fill:none;stroke:none;stroke-width:0.415661;stroke-linejoin:round;stroke-dasharray:none"
|
||||||
|
x="84.842606"
|
||||||
|
y="457.83777"
|
||||||
|
id="text16-4-1-0-6"><tspan
|
||||||
|
x="84.842606"
|
||||||
|
y="457.83777"
|
||||||
|
style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:12px;font-family:sans-serif;-inkscape-font-specification:'sans-serif, ';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-variant-east-asian:normal;text-align:start;letter-spacing:0px;text-anchor:start;fill:#000000;fill-opacity:1;stroke:none;stroke-width:0.415661"
|
||||||
|
id="tspan27-2-4">reset</tspan></text>
|
||||||
|
<circle
|
||||||
|
style="fill:none;stroke:#000000;stroke-width:0.416403;stroke-linejoin:round;stroke-dasharray:none"
|
||||||
|
id="path16-1-6"
|
||||||
|
cx="119.55518"
|
||||||
|
cy="500.89951"
|
||||||
|
r="33.044682" />
|
||||||
|
<circle
|
||||||
|
style="fill:none;stroke:#000000;stroke-width:0.468453;stroke-linejoin:round;stroke-dasharray:none"
|
||||||
|
id="path16-2-1-6"
|
||||||
|
cx="119.55518"
|
||||||
|
cy="500.89948"
|
||||||
|
r="37.175262" />
|
||||||
|
<text
|
||||||
|
xml:space="preserve"
|
||||||
|
style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:14px;font-family:sans-serif;-inkscape-font-specification:'sans-serif, Normal';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-variant-east-asian:normal;text-align:center;letter-spacing:0px;word-spacing:0px;text-anchor:middle;fill:none;stroke:none;stroke-width:0.415661;stroke-linejoin:round;stroke-dasharray:none"
|
||||||
|
x="119.01395"
|
||||||
|
y="504.92889"
|
||||||
|
id="text16-06-7"><tspan
|
||||||
|
id="tspan16-7-4"
|
||||||
|
x="119.01395"
|
||||||
|
y="504.92889"
|
||||||
|
style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:14px;font-family:sans-serif;-inkscape-font-specification:'sans-serif, Normal';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-variant-east-asian:normal;letter-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;stroke-width:0.415661">INIT</tspan></text>
|
||||||
|
<path
|
||||||
|
style="fill:#000000;fill-opacity:1;stroke:#000000;stroke-width:0.74819;stroke-linejoin:round;stroke-dasharray:none;marker-end:url(#marker27-3-4)"
|
||||||
|
d="M 73.277895,455.83878 92.53279,471.25286"
|
||||||
|
id="path26-5-8" />
|
||||||
|
<circle
|
||||||
|
style="fill:none;stroke:#000000;stroke-width:0.416403;stroke-linejoin:round;stroke-dasharray:none"
|
||||||
|
id="path16-9-6-7"
|
||||||
|
cx="119.65266"
|
||||||
|
cy="606.92194"
|
||||||
|
r="33.044682" />
|
||||||
|
<text
|
||||||
|
xml:space="preserve"
|
||||||
|
style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:14px;font-family:sans-serif;-inkscape-font-specification:'sans-serif, Normal';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-variant-east-asian:normal;text-align:center;letter-spacing:0px;word-spacing:0px;text-anchor:middle;fill:none;stroke:none;stroke-width:0.415661;stroke-linejoin:round;stroke-dasharray:none"
|
||||||
|
x="119.40099"
|
||||||
|
y="610.95135"
|
||||||
|
id="text16-0-2-6"><tspan
|
||||||
|
x="119.40099"
|
||||||
|
y="610.95135"
|
||||||
|
style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:14px;font-family:sans-serif;-inkscape-font-specification:'sans-serif, Normal';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-variant-east-asian:normal;letter-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;stroke-width:0.415661"
|
||||||
|
id="tspan4-2">CHECK</tspan></text>
|
||||||
|
<circle
|
||||||
|
style="fill:none;stroke:#000000;stroke-width:0.416403;stroke-linejoin:round;stroke-dasharray:none"
|
||||||
|
id="path16-9-5-8"
|
||||||
|
cx="119.65266"
|
||||||
|
cy="708.78778"
|
||||||
|
r="33.044682" />
|
||||||
|
<text
|
||||||
|
xml:space="preserve"
|
||||||
|
style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:14px;font-family:sans-serif;-inkscape-font-specification:'sans-serif, Normal';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-variant-east-asian:normal;text-align:center;letter-spacing:0px;word-spacing:0px;text-anchor:middle;fill:none;stroke:none;stroke-width:0.415661;stroke-linejoin:round;stroke-dasharray:none"
|
||||||
|
x="118.94638"
|
||||||
|
y="714.83191"
|
||||||
|
id="text16-0-9-3"><tspan
|
||||||
|
id="tspan16-8-8-3"
|
||||||
|
x="118.94638"
|
||||||
|
y="714.83191"
|
||||||
|
style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:14px;font-family:sans-serif;-inkscape-font-specification:'sans-serif, Normal';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-variant-east-asian:normal;letter-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;stroke-width:0.415661">DATA</tspan></text>
|
||||||
|
<path
|
||||||
|
style="fill:none;stroke:#000000;stroke-width:0.415661;stroke-linecap:round;stroke-linejoin:round;stroke-dasharray:none;marker-start:url(#marker27-3)"
|
||||||
|
d="m 104.32902,576.06014 c 0,0 -5.306007,-12.95931 -5.195768,-20.7311 0.09811,-6.91633 5.195768,-20.09006 5.195768,-20.09006"
|
||||||
|
id="path9" />
|
||||||
|
<path
|
||||||
|
style="fill:none;stroke:#000000;stroke-width:0.415661;stroke-linecap:round;stroke-linejoin:round;stroke-dasharray:none;marker-end:url(#marker27-3)"
|
||||||
|
d="m 134.8801,577.10935 c 0,0 5.54768,-14.53586 5.54768,-21.663 0,-7.12715 -5.54768,-18.96962 -5.54768,-18.96962"
|
||||||
|
id="path10" />
|
||||||
|
<path
|
||||||
|
style="fill:none;stroke:#000000;stroke-width:0.415661;stroke-linecap:round;stroke-linejoin:round;stroke-dasharray:none;marker-start:url(#marker27-3-8)"
|
||||||
|
d="m 104.56636,677.46494 c 0,0 -5.305999,-12.95931 -5.195759,-20.7311 0.0981,-6.91632 5.195759,-20.09006 5.195759,-20.09006"
|
||||||
|
id="path9-4" />
|
||||||
|
<path
|
||||||
|
style="fill:none;stroke:#000000;stroke-width:0.415661;stroke-linecap:round;stroke-linejoin:round;stroke-dasharray:none;marker-end:url(#marker27-3-8)"
|
||||||
|
d="m 135.11745,679.29645 c 0,0 5.54767,-14.53586 5.54767,-21.66301 0,-7.12715 -5.54767,-18.96961 -5.54767,-18.96961"
|
||||||
|
id="path10-3" />
|
||||||
|
<text
|
||||||
|
xml:space="preserve"
|
||||||
|
style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:12px;font-family:sans-serif;-inkscape-font-specification:'sans-serif, ';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-variant-east-asian:normal;text-align:start;letter-spacing:0px;word-spacing:0px;text-anchor:start;fill:none;stroke:none;stroke-width:0.415661;stroke-linejoin:round;stroke-dasharray:none"
|
||||||
|
x="153.60271"
|
||||||
|
y="649.02429"
|
||||||
|
id="text16-4-1-0-4-8-4-6"><tspan
|
||||||
|
x="153.60271"
|
||||||
|
y="649.02429"
|
||||||
|
style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:12px;font-family:sans-serif;-inkscape-font-specification:'sans-serif, ';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-variant-east-asian:normal;text-align:start;letter-spacing:0px;text-anchor:start;fill:#000000;fill-opacity:1;stroke:none;stroke-width:0.415661"
|
||||||
|
id="tspan12-2">At least one</tspan><tspan
|
||||||
|
x="153.60271"
|
||||||
|
y="661.52429"
|
||||||
|
style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:12px;font-family:sans-serif;-inkscape-font-specification:'sans-serif, ';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-variant-east-asian:normal;text-align:start;letter-spacing:0px;text-anchor:start;fill:#000000;fill-opacity:1;stroke:none;stroke-width:0.415661"
|
||||||
|
id="tspan19">invalid character</tspan><tspan
|
||||||
|
x="153.60271"
|
||||||
|
y="674.02429"
|
||||||
|
style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:12px;font-family:sans-serif;-inkscape-font-specification:'sans-serif, ';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-variant-east-asian:normal;text-align:start;letter-spacing:0px;text-anchor:start;fill:#000000;fill-opacity:1;stroke:none;stroke-width:0.415661"
|
||||||
|
id="tspan20">is received</tspan></text>
|
||||||
|
<text
|
||||||
|
xml:space="preserve"
|
||||||
|
style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:12px;font-family:sans-serif;-inkscape-font-specification:'sans-serif, ';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-variant-east-asian:normal;text-align:start;letter-spacing:0px;word-spacing:0px;text-anchor:start;fill:none;stroke:none;stroke-width:0.415661;stroke-linejoin:round;stroke-dasharray:none"
|
||||||
|
x="-0.15234375"
|
||||||
|
y="644.88391"
|
||||||
|
id="text16-4-1-0-4-8-4-67"><tspan
|
||||||
|
x="-0.15234375"
|
||||||
|
y="644.88391"
|
||||||
|
style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:12px;font-family:sans-serif;-inkscape-font-specification:'sans-serif, ';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-variant-east-asian:normal;text-align:start;letter-spacing:0px;text-anchor:start;fill:#000000;fill-opacity:1;stroke:none;stroke-width:0.415661"
|
||||||
|
id="tspan6-1-9">At least four</tspan><tspan
|
||||||
|
x="-0.15234375"
|
||||||
|
y="657.38391"
|
||||||
|
style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:12px;font-family:sans-serif;-inkscape-font-specification:'sans-serif, ';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-variant-east-asian:normal;text-align:start;letter-spacing:0px;text-anchor:start;fill:#000000;fill-opacity:1;stroke:none;stroke-width:0.415661"
|
||||||
|
id="tspan10-7">consecutive</tspan><tspan
|
||||||
|
x="-0.15234375"
|
||||||
|
y="669.88391"
|
||||||
|
style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:12px;font-family:sans-serif;-inkscape-font-specification:'sans-serif, ';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-variant-east-asian:normal;text-align:start;letter-spacing:0px;text-anchor:start;fill:#000000;fill-opacity:1;stroke:none;stroke-width:0.415661"
|
||||||
|
id="tspan11-6">valid characters</tspan><tspan
|
||||||
|
x="-0.15234375"
|
||||||
|
y="682.38391"
|
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inkscape:export-filename="/home/lars/text14934.png"
|
||||||
|
id="circle1087"
|
||||||
|
style="fill:#ffffff;fill-opacity:1;fill-rule:evenodd;stroke:#000000;stroke-width:3.51027;stroke-linecap:square;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1"
|
||||||
|
cx="189.02844"
|
||||||
|
cy="160.87465"
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|
r="46.229843" />
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||||||
|
<text
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|
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|
inkscape:export-xdpi="90.034584"
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|
inkscape:export-filename="/home/lars/text14934.png"
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|
id="text1093"
|
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|
y="157.89743"
|
||||||
|
x="163.96887"
|
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|
style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:22px;line-height:0%;font-family:sans-serif;-inkscape-font-specification:'sans-serif, ';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-variant-east-asian:normal;text-align:start;letter-spacing:0px;word-spacing:0px;writing-mode:lr-tb;text-anchor:start;fill:#000000;fill-opacity:1;stroke:none;stroke-width:0.877569"
|
||||||
|
xml:space="preserve"><tspan
|
||||||
|
style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:22px;line-height:1.25;font-family:sans-serif;-inkscape-font-specification:'sans-serif, ';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-variant-east-asian:normal;text-align:start;writing-mode:lr-tb;text-anchor:start;stroke-width:0.877569"
|
||||||
|
y="157.89743"
|
||||||
|
x="163.96887"
|
||||||
|
id="tspan1089"
|
||||||
|
sodipodi:role="line">EMB</tspan><tspan
|
||||||
|
id="tspan1091"
|
||||||
|
style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:22px;line-height:1.25;font-family:sans-serif;-inkscape-font-specification:'sans-serif, ';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-variant-east-asian:normal;text-align:start;writing-mode:lr-tb;text-anchor:start;stroke-width:0.877569"
|
||||||
|
y="185.39743"
|
||||||
|
x="163.96887"
|
||||||
|
sodipodi:role="line">INIT</tspan></text>
|
||||||
|
<g
|
||||||
|
id="g1103"
|
||||||
|
transform="matrix(0.87756872,0,0,0.87756872,150.84093,293.63815)"
|
||||||
|
inkscape:export-filename="/home/lars/text14934.png"
|
||||||
|
inkscape:export-xdpi="90.034584"
|
||||||
|
inkscape:export-ydpi="90.034584">
|
||||||
|
<circle
|
||||||
|
style="fill:#ffffff;fill-opacity:1;fill-rule:evenodd;stroke:#000000;stroke-width:5;stroke-linecap:square;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1"
|
||||||
|
id="circle1095"
|
||||||
|
transform="translate(0.54321289)"
|
||||||
|
cx="212.48558"
|
||||||
|
cy="78.67614"
|
||||||
|
r="52.679455" />
|
||||||
|
<text
|
||||||
|
xml:space="preserve"
|
||||||
|
style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:25.0693px;line-height:0%;font-family:sans-serif;-inkscape-font-specification:'sans-serif, ';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-variant-east-asian:normal;text-align:start;letter-spacing:0px;word-spacing:0px;writing-mode:lr-tb;text-anchor:start;fill:#000000;fill-opacity:1;stroke:none"
|
||||||
|
x="183.17365"
|
||||||
|
y="72.29348"
|
||||||
|
id="text1101"><tspan
|
||||||
|
sodipodi:role="line"
|
||||||
|
id="tspan1097"
|
||||||
|
x="183.17365"
|
||||||
|
y="72.29348"
|
||||||
|
style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:25.0693px;line-height:1.25;font-family:sans-serif;-inkscape-font-specification:'sans-serif, ';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-variant-east-asian:normal;text-align:start;writing-mode:lr-tb;text-anchor:start">EMB</tspan><tspan
|
||||||
|
id="tspan1099"
|
||||||
|
sodipodi:role="line"
|
||||||
|
x="183.17365"
|
||||||
|
y="103.6301"
|
||||||
|
style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:25.0693px;line-height:1.25;font-family:sans-serif;-inkscape-font-specification:'sans-serif, ';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-variant-east-asian:normal;text-align:start;writing-mode:lr-tb;text-anchor:start">HUNT</tspan></text>
|
||||||
|
</g>
|
||||||
|
<path
|
||||||
|
inkscape:export-ydpi="90.034584"
|
||||||
|
inkscape:export-xdpi="90.034584"
|
||||||
|
sodipodi:nodetypes="cc"
|
||||||
|
inkscape:connector-curvature="0"
|
||||||
|
id="path1105"
|
||||||
|
d="m 245.66439,175.68967 c 46.12647,7.35727 81.63461,42.31154 96.77374,130.20477"
|
||||||
|
style="vector-effect:none;fill:none;fill-opacity:1;stroke:#000000;stroke-width:3.51027;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1;marker-end:url(#TriangleOutS)" />
|
||||||
|
<text
|
||||||
|
xml:space="preserve"
|
||||||
|
style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:12px;line-height:0%;font-family:sans-serif;-inkscape-font-specification:'sans-serif, Normal';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-variant-east-asian:normal;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;stroke-width:0.877569"
|
||||||
|
x="315.49448"
|
||||||
|
y="214.25241"
|
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|
id="text1109"
|
||||||
|
inkscape:export-filename="/home/lars/text14934.png"
|
||||||
|
inkscape:export-xdpi="90.034584"
|
||||||
|
inkscape:export-ydpi="90.034584"><tspan
|
||||||
|
sodipodi:role="line"
|
||||||
|
x="315.49448"
|
||||||
|
y="214.25241"
|
||||||
|
style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:12px;line-height:1.25;font-family:sans-serif;-inkscape-font-specification:'sans-serif, Normal';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-variant-east-asian:normal;stroke-width:0.877569"
|
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|
id="tspan1107">An EoEMB received</tspan></text>
|
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|
<g
|
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|
inkscape:export-ydpi="90.034584"
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|
inkscape:export-xdpi="90.034584"
|
||||||
|
inkscape:export-filename="/home/lars/text14934.png"
|
||||||
|
transform="matrix(0.87756872,0,0,0.87756872,-135.18355,293.63815)"
|
||||||
|
id="g1119">
|
||||||
|
<circle
|
||||||
|
r="52.679455"
|
||||||
|
cy="78.67614"
|
||||||
|
cx="212.48558"
|
||||||
|
transform="translate(0.54321289)"
|
||||||
|
id="circle1111"
|
||||||
|
style="fill:#ffffff;fill-opacity:1;fill-rule:evenodd;stroke:#000000;stroke-width:5;stroke-linecap:square;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1" />
|
||||||
|
<text
|
||||||
|
id="text1117"
|
||||||
|
y="73.126175"
|
||||||
|
x="180.17743"
|
||||||
|
style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:25.0693px;line-height:0%;font-family:sans-serif;-inkscape-font-specification:'sans-serif, ';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-variant-east-asian:normal;text-align:start;letter-spacing:0px;word-spacing:0px;writing-mode:lr-tb;text-anchor:start;fill:#000000;fill-opacity:1;stroke:none"
|
||||||
|
xml:space="preserve"><tspan
|
||||||
|
style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:25.0693px;line-height:1.25;font-family:sans-serif;-inkscape-font-specification:'sans-serif, ';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-variant-east-asian:normal;text-align:start;writing-mode:lr-tb;text-anchor:start"
|
||||||
|
y="73.126175"
|
||||||
|
x="180.17743"
|
||||||
|
id="tspan1113"
|
||||||
|
sodipodi:role="line">EMB</tspan><tspan
|
||||||
|
id="tspan1115"
|
||||||
|
style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:25.0693px;line-height:1.25;font-family:sans-serif;-inkscape-font-specification:'sans-serif, ';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-variant-east-asian:normal;text-align:start;writing-mode:lr-tb;text-anchor:start"
|
||||||
|
y="104.46275"
|
||||||
|
x="180.17743"
|
||||||
|
sodipodi:role="line">LOCK</tspan></text>
|
||||||
|
</g>
|
||||||
|
<path
|
||||||
|
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|
||||||
|
inkscape:export-xdpi="90.034584"
|
||||||
|
style="vector-effect:none;fill:none;fill-opacity:1;stroke:#000000;stroke-width:3.51027;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1;marker-end:url(#TriangleOutS)"
|
||||||
|
d="m 285.25186,372.35296 c -54.28411,26.06423 -113.05239,33.04416 -180.42261,3.41498"
|
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|
id="path1121"
|
||||||
|
inkscape:connector-curvature="0"
|
||||||
|
sodipodi:nodetypes="cc" />
|
||||||
|
<text
|
||||||
|
inkscape:export-ydpi="90.034584"
|
||||||
|
inkscape:export-xdpi="90.034584"
|
||||||
|
inkscape:export-filename="/home/lars/text14934.png"
|
||||||
|
id="text1127"
|
||||||
|
y="415.92331"
|
||||||
|
x="152.49796"
|
||||||
|
style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:12px;line-height:0%;font-family:sans-serif;-inkscape-font-specification:'sans-serif, Normal';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-variant-east-asian:normal;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;stroke-width:0.877569"
|
||||||
|
xml:space="preserve"><tspan
|
||||||
|
id="tspan1123"
|
||||||
|
style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:12px;line-height:1.25;font-family:sans-serif;-inkscape-font-specification:'sans-serif, Normal';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-variant-east-asian:normal;stroke-width:0.877569"
|
||||||
|
y="415.92331"
|
||||||
|
x="152.49796"
|
||||||
|
sodipodi:role="line">Four consecutive correct</tspan><tspan
|
||||||
|
id="tspan1125"
|
||||||
|
style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:12px;line-height:1.25;font-family:sans-serif;-inkscape-font-specification:'sans-serif, Normal';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-variant-east-asian:normal;stroke-width:0.877569"
|
||||||
|
y="430.92331"
|
||||||
|
x="152.49796"
|
||||||
|
sodipodi:role="line"> EoMB received.</tspan></text>
|
||||||
|
<path
|
||||||
|
inkscape:export-ydpi="90.034584"
|
||||||
|
inkscape:export-xdpi="90.034584"
|
||||||
|
style="vector-effect:none;fill:none;fill-opacity:1;stroke:#000000;stroke-width:3.51027;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1;marker-end:url(#TriangleOutS)"
|
||||||
|
d="m 41.248628,310.8793 c 5.36076,-65.28361 29.20009,-115.41538 88.486622,-136.48155"
|
||||||
|
id="path1129"
|
||||||
|
inkscape:connector-curvature="0"
|
||||||
|
sodipodi:nodetypes="cc" />
|
||||||
|
<path
|
||||||
|
inkscape:export-ydpi="90.034584"
|
||||||
|
inkscape:export-xdpi="90.034584"
|
||||||
|
style="vector-effect:none;fill:none;fill-opacity:1;stroke:#000000;stroke-width:3.51027;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1;marker-end:url(#TriangleOutS)"
|
||||||
|
d="M 318.64736,312.2264 C 278.68738,306.01282 247.9262,276.49224 234.81096,202.26217"
|
||||||
|
id="path1135"
|
||||||
|
inkscape:connector-curvature="0"
|
||||||
|
sodipodi:nodetypes="cc" />
|
||||||
|
<text
|
||||||
|
inkscape:export-ydpi="90.034584"
|
||||||
|
inkscape:export-xdpi="90.034584"
|
||||||
|
inkscape:export-filename="/home/lars/text14934.png"
|
||||||
|
id="text1139"
|
||||||
|
y="303.03339"
|
||||||
|
x="157.80576"
|
||||||
|
style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:12px;line-height:0%;font-family:sans-serif;-inkscape-font-specification:'sans-serif, Normal';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-variant-east-asian:normal;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;stroke-width:0.877569"
|
||||||
|
xml:space="preserve"><tspan
|
||||||
|
id="tspan1137"
|
||||||
|
style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:12px;line-height:1.25;font-family:sans-serif;-inkscape-font-specification:'sans-serif, Normal';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-variant-east-asian:normal;stroke-width:0.877569"
|
||||||
|
y="303.03339"
|
||||||
|
x="157.80576"
|
||||||
|
sodipodi:role="line">Unexpected EoMB</tspan><tspan
|
||||||
|
style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:12px;line-height:1.25;font-family:sans-serif;-inkscape-font-specification:'sans-serif, Normal';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-variant-east-asian:normal;stroke-width:0.877569"
|
||||||
|
y="318.03339"
|
||||||
|
x="157.80576"
|
||||||
|
sodipodi:role="line"
|
||||||
|
id="tspan1151"> or EoEMB received</tspan></text>
|
||||||
|
<text
|
||||||
|
xml:space="preserve"
|
||||||
|
style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:22px;line-height:0%;font-family:sans-serif;-inkscape-font-specification:'sans-serif, ';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-variant-east-asian:normal;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;stroke-width:0.877569"
|
||||||
|
x="50.12146"
|
||||||
|
y="20.480965"
|
||||||
|
id="text1145"
|
||||||
|
inkscape:export-filename="/home/lars/text14934.png"
|
||||||
|
inkscape:export-xdpi="90.034584"
|
||||||
|
inkscape:export-ydpi="90.034584"><tspan
|
||||||
|
sodipodi:role="line"
|
||||||
|
id="tspan1141"
|
||||||
|
x="50.12146"
|
||||||
|
y="20.480965"
|
||||||
|
style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:22px;line-height:1.25;font-family:sans-serif;-inkscape-font-specification:'sans-serif, ';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-variant-east-asian:normal;text-align:start;writing-mode:lr-tb;text-anchor:start;stroke-width:0.877569">Extendend Multi-Block</tspan><tspan
|
||||||
|
id="tspan1143"
|
||||||
|
sodipodi:role="line"
|
||||||
|
x="50.12146"
|
||||||
|
y="47.980965"
|
||||||
|
style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:22px;line-height:1.25;font-family:sans-serif;-inkscape-font-specification:'sans-serif, ';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-variant-east-asian:normal;text-align:start;writing-mode:lr-tb;text-anchor:start;stroke-width:0.877569">Alignment State Machine</tspan></text>
|
||||||
|
<text
|
||||||
|
inkscape:export-ydpi="90.034584"
|
||||||
|
inkscape:export-xdpi="90.034584"
|
||||||
|
inkscape:export-filename="/home/lars/text14934.png"
|
||||||
|
id="text1127-4"
|
||||||
|
y="239.94699"
|
||||||
|
x="67.197937"
|
||||||
|
style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:12px;line-height:0%;font-family:sans-serif;-inkscape-font-specification:'sans-serif, Normal';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-variant-east-asian:normal;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;stroke-width:0.877569"
|
||||||
|
xml:space="preserve"><tspan
|
||||||
|
id="tspan1125-6"
|
||||||
|
style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:12px;line-height:1.25;font-family:sans-serif;-inkscape-font-specification:'sans-serif, Normal';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-variant-east-asian:normal;stroke-width:0.877569"
|
||||||
|
y="239.94699"
|
||||||
|
x="67.197937"
|
||||||
|
sodipodi:role="line">Eight incorrect EoMB</tspan><tspan
|
||||||
|
style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:12px;line-height:1.25;font-family:sans-serif;-inkscape-font-specification:'sans-serif, Normal';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-variant-east-asian:normal;stroke-width:0.877569"
|
||||||
|
y="254.94699"
|
||||||
|
x="67.197937"
|
||||||
|
sodipodi:role="line"
|
||||||
|
id="tspan1180">or EoEMB received.</tspan></text>
|
||||||
|
</svg>
|
||||||
|
After Width: | Height: | Size: 22 KiB |
|
|
@ -0,0 +1,482 @@
|
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@ -0,0 +1,482 @@
|
||||||
|
.. _jesd204:
|
||||||
|
|
||||||
|
JESD204 Interface Framework
|
||||||
|
================================================================================
|
||||||
|
|
||||||
|
.. toctree::
|
||||||
|
:hidden:
|
||||||
|
|
||||||
|
JESD204B/C Link Transmit Peripheral <axi_jesd204_tx/index>
|
||||||
|
JESD204B/C Link Receive Peripheral <axi_jesd204_rx/index>
|
||||||
|
ADC JESD204B/C Transport Peripheral <ad_ip_jesd204_tpl_adc/index>
|
||||||
|
DAC JESD204B/C Transport Peripheral <ad_ip_jesd204_tpl_dac/index>
|
||||||
|
|
||||||
|
The JESD204, JESD204A, JESD204B and the JESD204C data converter serial interface
|
||||||
|
standard was created through the JEDEC committee to standardize and reduce the
|
||||||
|
number of data inputs/outputs between high-speed data converters and other
|
||||||
|
devices, such as FPGAs (field-programmable gate arrays). Fewer interconnects
|
||||||
|
simplifies layout and allows smaller form factor realization without impacting
|
||||||
|
overall system performance. These attributes are important to address the system
|
||||||
|
size and cost constraints of a range of high-speed ADC applications, including
|
||||||
|
wireless infrastructure (GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA)
|
||||||
|
transceiver architectures, software-defined radios, portable instrumentation,
|
||||||
|
medical ultrasound equipment, and Mil/Aero applications such as radar and secure
|
||||||
|
communications. Analog Devices is an original participating member of the JEDEC
|
||||||
|
JESD204 standards committee and we have concurrently developed compliant data
|
||||||
|
converter technology and tools, and a comprehensive product roadmap to fully
|
||||||
|
enable our customers to take advantage of this significant interfacing
|
||||||
|
breakthrough.
|
||||||
|
|
||||||
|
Analog Devices supplies a full-stack supporting JESD204B/C which provides a
|
||||||
|
fully integrated system level experience. This solution includes:
|
||||||
|
|
||||||
|
.. hint::
|
||||||
|
|
||||||
|
* :ref:`Reference hardware platforms <rapid_prototyping_label>` for
|
||||||
|
rapid-prototyping
|
||||||
|
* :ref:`FPGA HDL support <fpga_hdl_support_label>` for interfacing JESD204B/C ADCs,
|
||||||
|
DACs, and RF Transceivers
|
||||||
|
* :ref:`Software support <software_support_label>` to configure the converter
|
||||||
|
devices and FPGA HDL peripherals
|
||||||
|
|
||||||
|
How to Obtain a License
|
||||||
|
--------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
When customers and partners download/use software from GitHub, e-mail or
|
||||||
|
similar ways, they are obligated to comply to the terms and conditions of
|
||||||
|
the :git-hdl:`Software License Agreement <LICENSE_ADIJESD204>`.
|
||||||
|
This core is released under two different licenses. You may choose either:
|
||||||
|
|
||||||
|
- Commercial licenses may be purchased from :adi:`Analog Devices, Inc. <>`. or any
|
||||||
|
authorized distributor by ordering
|
||||||
|
:adi:`IP-JESD204 <en/design-center/evaluation-hardware-and-software/jesd204-interface-framework.html>`.
|
||||||
|
This will allow you to use the core in a closed system.
|
||||||
|
- GPL 2, this allows you to use the core for any purpose, but you must release
|
||||||
|
anything else that links to the JESD204 core (this would normally be your
|
||||||
|
algorithmic IP). **You do not need to sign or purchase** anything to use
|
||||||
|
the JESD204 core under the GPL license.
|
||||||
|
|
||||||
|
There is only one core -- the only difference is the license and support.
|
||||||
|
If you have a question about the license, you can email
|
||||||
|
`jesd204-licensing@analog.com <jesd204-licensing@analog.com>`__.
|
||||||
|
|
||||||
|
.. _fpga_hdl_support_label:
|
||||||
|
|
||||||
|
FPGA HDL Support
|
||||||
|
--------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
.. image:: jesd204_layers2.svg
|
||||||
|
:align: right
|
||||||
|
|
||||||
|
The JESD204B/C standard defines multiple layers, each layer being responsible
|
||||||
|
for a particular function. The Analog Devices JESD204B/C HDL solution follows
|
||||||
|
the current standard and defines 4 layers. Physical layer, link layer, transport
|
||||||
|
layer and application layer. For the first three layers, :adi:`ADI <>` provides
|
||||||
|
standard components that can be linked to provide a full JESD204B/C protocol
|
||||||
|
processing chain.
|
||||||
|
|
||||||
|
Depending on the FPGA and converter combinations that are being interfaced,
|
||||||
|
different components can be chosen for the physical and transport layer. The
|
||||||
|
FPGA defines which **physical** layer component should be used, meanwhile the
|
||||||
|
interfaced converter defines which **transport** layer component should be used.
|
||||||
|
|
||||||
|
The **link** layer component is selected based on the direction of the
|
||||||
|
JESD204B/C link.
|
||||||
|
|
||||||
|
The **application** layer is user-defined and can be used to implement
|
||||||
|
application-specific signal processing.
|
||||||
|
|
||||||
|
.. image:: jesd204_chain.svg
|
||||||
|
:align: center
|
||||||
|
|
||||||
|
.. _jesd204_physical_layer:
|
||||||
|
|
||||||
|
Physical Layer
|
||||||
|
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
|
||||||
|
Physical layer peripherals are responsible for interfacing and configuring the
|
||||||
|
high-speed serial transceivers. Currently, we have support for GTXE2, GTHE3,
|
||||||
|
GTHE4, GTYE4 for AMD Xilinx and Arria 10 transceivers for Intel.
|
||||||
|
|
||||||
|
* :ref:`axi_adxcvr`: JESD204B Gigabit
|
||||||
|
Transceiver Register Configuration Peripheral
|
||||||
|
* :ref:`UTIL_ADXCVR <util_adxcvr>`: JESD204B Gigabit
|
||||||
|
Transceiver Interface Peripheral for AMD Xilinx FPGAs
|
||||||
|
|
||||||
|
Link Layer
|
||||||
|
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
|
||||||
|
Link layer peripherals are responsible for JESD204B/C protocol handling,
|
||||||
|
including scrambling/descrambling, lane alignment, character replacement and
|
||||||
|
alignment monitoring.
|
||||||
|
|
||||||
|
* :ref:`JESD204B/C Transmit Peripheral <axi_jesd204_tx>`:
|
||||||
|
JESD204B/C Link Layer Transmit Peripheral
|
||||||
|
* :ref:`JESD204B/C Receive Peripheral <axi_jesd204_rx>`:
|
||||||
|
JESD204B/C Link Layer Receive Peripheral
|
||||||
|
|
||||||
|
.. _jesd204_transport_layer:
|
||||||
|
|
||||||
|
Transport Layer
|
||||||
|
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
|
||||||
|
Transport layer peripherals are responsible for converter specific data framing
|
||||||
|
and de-framing.
|
||||||
|
|
||||||
|
* :ref:`ADC JESD204B/C Transport Peripheral <ad_ip_jesd204_tpl_adc>`:
|
||||||
|
JESD204B/C Transport Layer Receive Peripheral
|
||||||
|
* :ref:`DAC JESD204B/C Transport Peripheral <ad_ip_jesd204_tpl_dac>`:
|
||||||
|
JESD204B/C Transport Layer Transmit Peripheral
|
||||||
|
|
||||||
|
Interfaces
|
||||||
|
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
|
||||||
|
Interfaces are a well-defined collection of wires that are used to communicate
|
||||||
|
between components. The following interfaces are used to connect components of
|
||||||
|
the HDL JESD204B/C processing stack.
|
||||||
|
|
||||||
|
.. _software_support_label:
|
||||||
|
|
||||||
|
Software Support
|
||||||
|
--------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
Linux
|
||||||
|
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
|
||||||
|
- :dokuwiki:`JESD204 (FSM) Interface Linux Kernel Framework <resources/tools-software/linux-drivers/jesd204/jesd204-fsm-framework>`
|
||||||
|
- :dokuwiki:`JESD204B/C Transmit Linux Driver <resources/tools-software/linux-drivers/jesd204/axi_jesd204_tx>`:
|
||||||
|
Linux driver for the JESD204B transmit core.
|
||||||
|
- :dokuwiki:`JESD204B/C Receive Linux Driver <resources/tools-software/linux-drivers/jesd204/axi_jesd204_rx>`:
|
||||||
|
Linux driver for the JESD204B receive core.
|
||||||
|
- :dokuwiki:`JESD204B/C AXI_ADXCVR Highspeed Transceivers Linux Driver <resources/tools-software/linux-drivers/jesd204/axi_adxcvr>`
|
||||||
|
- :dokuwiki:`JESD204B Statistical Eyescan Application <resources/tools-software/linux-software/jesd_eye_scan>`
|
||||||
|
- :dokuwiki:`JESD204B Status Utility <resources/tools-software/linux-software/jesd_status>`
|
||||||
|
- :dokuwiki:`AXI DAC HDL Linux Driver <resources/tools-software/linux-drivers/iio-dds/axi-dac-dds-hdl>`
|
||||||
|
|
||||||
|
- :dokuwiki:`AD9172 DAC Linux Driver <resources/tools-software/linux-drivers/iio-dds/ad9172>`
|
||||||
|
- :dokuwiki:`AD9081 MxFE Linux Driver <resources/tools-software/linux-drivers/iio-mxfe/ad9081>`
|
||||||
|
- :dokuwiki:`ADRV9009, ADRV9008 highly integrated, wideband RF transceiver Linux device driver <resources/tools-software/linux-drivers/iio-transceiver/adrv9009>`
|
||||||
|
- :dokuwiki:`AD9371, AD9375 highly integrated, wideband RF transceiver Linux device driver <resources/tools-software/linux-drivers/iio-transceiver/ad9371>`
|
||||||
|
|
||||||
|
- :dokuwiki:`AXI ADC HDL Linux Driver <resources/tools-software/linux-drivers/iio-adc/axi-adc-hdl>`
|
||||||
|
|
||||||
|
- :dokuwiki:`AD9208 ADC Linux Driver <resources/tools-software/linux-drivers/iio-adc/ad9208>`
|
||||||
|
- :dokuwiki:`AD9081 MxFE Linux Driver <resources/tools-software/linux-drivers/iio-mxfe/ad9081>`
|
||||||
|
- :dokuwiki:`ADRV9009, ADRV9008 highly integrated, wideband RF transceiver Linux device driver <resources/tools-software/linux-drivers/iio-transceiver/adrv9009>`
|
||||||
|
- :dokuwiki:`AD9371, AD9375 highly integrated, wideband RF transceiver Linux device driver <resources/tools-software/linux-drivers/iio-transceiver/ad9371>`
|
||||||
|
|
||||||
|
No-OS
|
||||||
|
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
|
||||||
|
- :dokuwiki:`ADI JESD204B/C AXI_ADXCVR Highspeed Transceivers No-OS Driver <resources/tools-software/uc-drivers/jesd204/axi_adxcvr>`
|
||||||
|
- :dokuwiki:`ADI JESD204B/C Receive Peripheral No-OS Driver <resources/tools-software/uc-drivers/jesd204/axi_jesd204_rx>`
|
||||||
|
- :dokuwiki:`ADI JESD204B/C Transmit Peripheral No-OS Driver <resources/tools-software/uc-drivers/jesd204/axi_jesd204_tx>`
|
||||||
|
- :dokuwiki:`AXI ADC No-OS Driver <resources/tools-software/uc-drivers/jesd204/axi_adc_core>`
|
||||||
|
- :dokuwiki:`AXI DAC No-OS Driver <resources/tools-software/uc-drivers/jesd204/axi_dac_core>`
|
||||||
|
|
||||||
|
Tutorial
|
||||||
|
--------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
#. :dokuwiki:`Introduction <resources/fpga/peripherals/jesd204/tutorial/introduction>`
|
||||||
|
#. :dokuwiki:`System Architecture <resources/fpga/peripherals/jesd204/tutorial/system_architecture>`
|
||||||
|
#. :dokuwiki:`Generic JESD204B block designs <resources/fpga/docs/hdl/generic_jesd_bds>`.
|
||||||
|
This will help you understand the generic blocks for the next steps.
|
||||||
|
#. Checkout the :ref:`HDL Source <build_hdl>`, and then build either one of:
|
||||||
|
|
||||||
|
#. :dokuwiki:`HDL AMD Xilinx <resources/fpga/peripherals/jesd204/tutorial/hdl_xilinx>`
|
||||||
|
#. :dokuwiki:`HDL Altera <resources/fpga/peripherals/jesd204/tutorial/hdl_altera>`
|
||||||
|
|
||||||
|
#. :dokuwiki:`Linux <resources/fpga/peripherals/jesd204/tutorial/linux>`
|
||||||
|
|
||||||
|
Example Projects
|
||||||
|
--------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
- :dokuwiki:`AD-FMCADC2-EBZ Reference Design <resources/fpga/xilinx/fmc/ad-fmcadc2-ebz>`
|
||||||
|
|
||||||
|
- :git-hdl:`AMD Xilinx VC707 <projects/fmcadc2/vc707>`
|
||||||
|
- :git-hdl:`AMD Xilinx ZC706 <projects/fmcadc2/zc706>`
|
||||||
|
|
||||||
|
- :dokuwiki:`AD-FMCADC3-EBZ Reference Design <resources/fpga/xilinx/fmc/ad-fmcadc3-ebz>`
|
||||||
|
|
||||||
|
- :git-hdl:`AMD Xilinx VC707 <projects/fmcadc2/vc707>`
|
||||||
|
- :git-hdl:`AMD Xilinx ZC706 <projects/fmcadc2/zc706>`
|
||||||
|
|
||||||
|
- :dokuwiki:`AD-FMCADC4-EBZ Reference Design (RETIRED) <resources/fpga/xilinx/fmc/ad-fmcadc4-ebz>`
|
||||||
|
|
||||||
|
- :git-hdl:`AMD Xilinx ZC706 <hdl_2018_r2:projects/fmcadc4/zc706>`
|
||||||
|
|
||||||
|
- :dokuwiki:`AD-FMCJESDADC1-EBZ Reference Design <resources/fpga/xilinx/fmc/ad-fmcjesdadc1-ebz>`
|
||||||
|
|
||||||
|
- :git-hdl:`AMD Xilinx KC705 <projects/fmcjesdadc1/kc705>`
|
||||||
|
- :git-hdl:`AMD Xilinx VC707 <projects/fmcjesdadc1/vc707>`
|
||||||
|
- :git-hdl:`AMD Xilinx ZC706 <projects/fmcjesdadc1/zc706>`
|
||||||
|
|
||||||
|
- :dokuwiki:`AD-FMCOMMS8-EBZ Reference Design <resources/eval/user-guides/ad-fmcomms8-ebz/quick-start-guide>`
|
||||||
|
|
||||||
|
- :git-hdl:`Intel A10SOC <projects/fmcomms8/a10soc>`
|
||||||
|
- :git-hdl:`AMD Xilinx ZCU102 <projects/fmcomms8/zcu102>`
|
||||||
|
|
||||||
|
- :dokuwiki:`AD-FMCOMMS11-EBZ Reference Design <resources/eval/user-guides/ad-fmcomms11-ebz>`
|
||||||
|
|
||||||
|
- :git-hdl:`AMD Xilinx ZC706 <projects/fmcomms11/zc706>`
|
||||||
|
|
||||||
|
- :dokuwiki:`AD-FMCDAQ2-EBZ Reference Design <resources/eval/user-guides/ad-fmcdaq2-ebz>`
|
||||||
|
|
||||||
|
- :git-hdl:`Intel A10SOC <projects/daq2/a10soc>`
|
||||||
|
- :git-hdl:`Intel A10Gx (RETIRED) <hdl_2021_r1:projects/daq2/a10gx>`
|
||||||
|
- :git-hdl:`AMD Xilinx KC705 <projects/daq2/kc705>`
|
||||||
|
- :git-hdl:`AMD Xilinx KCU105 <projects/daq2/kcu105>`
|
||||||
|
- :git-hdl:`AMD Xilinx VC707 (RETIRED) <hdl_2018_r2:projects/daq2/vc707>`
|
||||||
|
- :git-hdl:`AMD Xilinx ZC706 <projects/daq2/zc706>`
|
||||||
|
- :git-hdl:`AMD Xilinx ZCU102 <projects/daq2/zcu102>`
|
||||||
|
|
||||||
|
- :dokuwiki:`AD-FMCDAQ3-EBZ Reference Design <resources/eval/user-guides/ad-fmcdaq3-ebz>`
|
||||||
|
|
||||||
|
- :git-hdl:`Intel A10Gx (RETIRED) <hdl_2021_r1:projects/daq3/a10gx>`
|
||||||
|
- :git-hdl:`AMD Xilinx KCU105 <projects/daq3/kcu105>`
|
||||||
|
- :git-hdl:`AMD Xilinx VCU118 <projects/daq3/vcu118>`
|
||||||
|
- :git-hdl:`AMD Xilinx ZC706 <projects/daq3/zc706>`
|
||||||
|
- :git-hdl:`AMD Xilinx ZCU102 <projects/daq3/zcu102>`
|
||||||
|
|
||||||
|
- :dokuwiki:`ADRV9371 Reference Design <resources/eval/user-guides/mykonos>`
|
||||||
|
|
||||||
|
- :git-hdl:`Intel A10SOC <projects/adrv9371x/a10soc>`
|
||||||
|
- :git-hdl:`Intel A10Gx (RETIRED) <hdl_2021_r1:projects/adrv9371x/a10gx>`
|
||||||
|
- :git-hdl:`AMD Xilinx KCU105 <projects/adrv9371x/kcu105>`
|
||||||
|
- :git-hdl:`AMD Xilinx ZC706 <projects/adrv9371x/zc706>`
|
||||||
|
- :git-hdl:`AMD Xilinx ZCU102 <projects/adrv9371x/zcu102>`
|
||||||
|
|
||||||
|
- :dokuwiki:`ADRV9009 Reference Design <resources/eval/user-guides/adrv9009>`
|
||||||
|
|
||||||
|
- :git-hdl:`AMD Xilinx ZCU102 <projects/adrv9009/zcu102>`
|
||||||
|
|
||||||
|
- :dokuwiki:`ADRV9009-ZU11EG-SOM Reference Design <resources/eval/user-guides/adrv9009-zu11eg>`
|
||||||
|
|
||||||
|
- :git-hdl:`Intel A10SOC <projects/adrv9009/a10soc>`
|
||||||
|
- :git-hdl:`Intel A10Gx (RETIRED) <hdl_2021_r1:projects/adrv9009/a10gx>`
|
||||||
|
- :git-hdl:`AMD Xilinx ZC706 <projects/adrv9009/zc706>`
|
||||||
|
- :git-hdl:`ADRV9009-ZU11EG-SOM <projects/adrv9009zu11eg>`
|
||||||
|
|
||||||
|
- :dokuwiki:`AD913x/AD917x/AD9144/AD915x/AD916X Reference Design <resources/eval/user-guides/ad-dac-fmc-ebz>`
|
||||||
|
|
||||||
|
- See the :git-hdl:`list of supported parts <projects/dac_fmc_ebz#readme>`
|
||||||
|
- :git-hdl:`Intel A10SOC <projects/dac_fmc_ebz/a10soc>`
|
||||||
|
- :git-hdl:`AMD Xilinx VCU118 <projects/dac_fmc_ebz/vcu118>`
|
||||||
|
- :git-hdl:`AMD Xilinx ZC706 <projects/dac_fmc_ebz/zc706>`
|
||||||
|
- :git-hdl:`AMD Xilinx ZCU102 <projects/dac_fmc_ebz/zcu102>`
|
||||||
|
|
||||||
|
- :ref:`AD9081-FMCA-EBZ Reference Design <ad9081_fmca_ebz>`
|
||||||
|
|
||||||
|
- :git-hdl:`Intel A10SOC <projects/ad9081_fmca_ebz/a10soc>`
|
||||||
|
- :git-hdl:`AMD Xilinx ZC706 <projects/ad9081_fmca_ebz/zc706>`
|
||||||
|
- :git-hdl:`AMD Xilinx ZCU102 <projects/ad9081_fmca_ebz/zcu102>`
|
||||||
|
- :git-hdl:`AMD Xilinx VCU118 <projects/ad9081_fmca_ebz/vcu118>`
|
||||||
|
- :git-hdl:`AMD Xilinx VCU128 <projects/ad9081_fmca_ebz/vcu128>`
|
||||||
|
- :git-hdl:`AMD Xilinx VCK190 <projects/ad9081_fmca_ebz/vck190>`
|
||||||
|
|
||||||
|
- :ref:`AD9082-FMCA-EBZ Reference Design <ad9081_fmca_ebz>`
|
||||||
|
|
||||||
|
- :git-hdl:`AMD Xilinx VCK190 <projects/ad9081_fmca_ebz/vck190>`
|
||||||
|
- :git-hdl:`AMD Xilinx VCU118 <projects/ad9081_fmca_ebz/vcu118>`
|
||||||
|
- :git-hdl:`AMD Xilinx ZC706 <projects/ad9081_fmca_ebz/zc706>`
|
||||||
|
- :git-hdl:`AMD Xilinx ZCU102 <projects/ad9081_fmca_ebz/zcu102>`
|
||||||
|
|
||||||
|
- :dokuwiki:`AD9081-FMCA-EBZ X-Band Phased Array Reference Design <resources/eval/user-guides/x-band-platform>`
|
||||||
|
|
||||||
|
- :git-hdl:`AMD Xilinx ZCU102 <projects/ad9081_fmca_ebz_x_band/zcu102>`
|
||||||
|
|
||||||
|
- :dokuwiki:`AD9213-DUAL-EBZ Reference Design <resources/eval/user-guides/ad9213_dual_ebz/ad9213_dual_ebz_hdl>`
|
||||||
|
|
||||||
|
- :git-hdl:`Intel S10SOC <projects/ad9213_dual_ebz/s10soc>`
|
||||||
|
|
||||||
|
- :dokuwiki:`AD9213-EBZ Reference Design <resources/eval/user-guides/ad9213_evb/ad9213_evb_hdl>`
|
||||||
|
|
||||||
|
- :git-hdl:`AMD Xilinx VCU118 <projects/ad9213_evb/vcu118>`
|
||||||
|
|
||||||
|
- :dokuwiki:`AD6676-EBZ Reference Design <resources/eval/user-guides/ad6676-ebz/software/baremetal>`
|
||||||
|
|
||||||
|
- :git-hdl:`AMD Xilinx VC707 <projects/ad6676evb/vc707>`
|
||||||
|
- :git-hdl:`AMD Xilinx ZC706 <projects/ad6676evb/zc706>`
|
||||||
|
|
||||||
|
- :dokuwiki:`AD9083-FMC <resources/eval/user-guides/ad9083/ad9083_evb_reference_hdl>`
|
||||||
|
|
||||||
|
- :git-hdl:`Intel A10SOC <projects/ad9083_evb/a10soc>`
|
||||||
|
- :git-hdl:`AMD Xilinx ZCU102 <projects/ad9083_evb/zcu102>`
|
||||||
|
|
||||||
|
- :dokuwiki:`AD9208-DUAL-EBZ reference design <resources/eval/user-guides/ad9208_dual_ebz/ad9208_dual_ebz_hdl>`
|
||||||
|
|
||||||
|
- :git-hdl:`AMD Xilinx VCU118 <projects/ad9208_dual_ebz/vcu118>`
|
||||||
|
|
||||||
|
- :dokuwiki:`AD9209-FMCA-EBZ reference design <resources/eval/user-guides/ad9209_fmca_ebz/ad9209_fmca_ebz>`
|
||||||
|
|
||||||
|
- :git-hdl:`AMD Xilinx VCK190 <projects/ad9209_fmca_ebz/vck190>`
|
||||||
|
|
||||||
|
- :dokuwiki:`AD9656 HDL Reference Design <resources/eval/user-guides/ad9656/reference_hdl>`
|
||||||
|
|
||||||
|
- :git-hdl:`AMD Xilinx ZCU102 <projects/ad9656_fmc/zcu102>`
|
||||||
|
|
||||||
|
- :dokuwiki:`AD9695-FMC reference design <resources/eval/user-guides/ad9695_fmc>`
|
||||||
|
|
||||||
|
- :git-hdl:`AMD Xilinx ZCU102 <projects/ad9695_fmc/zcu102>`
|
||||||
|
|
||||||
|
- :dokuwiki:`AD-QUADMXFE1-EBZ reference design <resources/eval/user-guides/ad_quadmxfe1_ebz/ad_quadmxfe1_ebz_hdl>`
|
||||||
|
|
||||||
|
- :git-hdl:`AMD Xilinx VCU118 <projects/ad_quadmxfe1_ebz/vcu118>`
|
||||||
|
|
||||||
|
- :dokuwiki:`AD-FMCLIDAR1-EBZ reference design <resources/eval/user-guides/ad-fmclidar1-ebz>`
|
||||||
|
|
||||||
|
- :git-hdl:`Intel A10SOC (RETIRED) <projects/ad_fmclidar1_ebz/a10soc>`
|
||||||
|
- :git-hdl:`AMD Xilinx ZC706 (RETIRED)<projects/ad_fmclidar1_ebz/zc706>`
|
||||||
|
- :git-hdl:`AMD Xilinx ZCU102 (RETIRED)<projects/ad_fmclidar1_ebz/zcu102>`
|
||||||
|
|
||||||
|
- :dokuwiki:`ADRV9026 reference design <resources/eval/user-guides/adrv9026/ad9026_hdl>`
|
||||||
|
|
||||||
|
- :git-hdl:`AMD Xilinx ZCU102 <projects/adrv9026/zcu102>`
|
||||||
|
|
||||||
|
Additional Information
|
||||||
|
--------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
- :dokuwiki:`JESD204B Glossary <resources/fpga/peripherals/jesd204/jesd204_glossary>`
|
||||||
|
|
||||||
|
Technical Articles
|
||||||
|
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
|
||||||
|
- :adi:`JESD204B Survival Guide <media/en/technical-documentation/technical-articles/JESD204B-Survival-Guide.pdf>`
|
||||||
|
- :adi:`Synchronizing Sample Clocks of a Data Converter Array <en/resources/technical-articles/synchronizing-sample-clocks-of-a-data-converter-array>`
|
||||||
|
|
||||||
|
.. _rapid_prototyping_label:
|
||||||
|
|
||||||
|
JESD204B Rapid Prototyping Platforms
|
||||||
|
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
|
||||||
|
- :adi:`EVAL-ADRV9371 <en/resources/evaluation-hardware-and-software/evaluation-boards-kits/EVAL-ADRV9371>`
|
||||||
|
:dokuwiki:`(User Guide) <resources/eval/user-guides/mykonos>`
|
||||||
|
- :adi:`EVAL-ADRV9008-9009 <en/resources/evaluation-hardware-and-software/evaluation-boards-kits/EVAL-ADRV9008-9009>`
|
||||||
|
:dokuwiki:`(User Guide) <resources/eval/user-guides/adrv9009>`
|
||||||
|
- :dokuwiki:`ADRV9009-ZU11EG (User Guide) <resources/eval/user-guides/adrv9009-zu11eg>`
|
||||||
|
- :adi:`AD-FMCJESDADC1-EBZ <en/resources/evaluation-hardware-and-software/evaluation-boards-kits/eval-ad-fmcjesdadc1-ebz>`
|
||||||
|
- :adi:`AD-FMCOMMS11-EBZ <resources/evaluation-hardware-and-software/evaluation-boards-kits/AD-FMCOMMS11-EBZ>`
|
||||||
|
:dokuwiki:`(User Guide) <resources/eval/user-guides/ad-fmcomms11-ebz>`
|
||||||
|
- :adi:`AD-FMCADC2-EBZ <en/resources/evaluation-hardware-and-software/evaluation-boards-kits/AD-FMCADC2-EBZ>`
|
||||||
|
- :adi:`AD-FMCADC3-EBZ <en/resources/evaluation-hardware-and-software/evaluation-boards-kits/EVAL-AD-FMCADC3-EBZ>`
|
||||||
|
- :adi:`AD-FMCADC4-EBZ <en/resources/evaluation-hardware-and-software/evaluation-boards-kits/EVAL-AD-FMCADC4-EBZ>`\ (RETIRED)
|
||||||
|
- :adi:`AD-FMCDAQ2-EBZ <en/resources/evaluation-hardware-and-software/evaluation-boards-kits/AD-FMCDAQ2-EBZ>`
|
||||||
|
:dokuwiki:`(User Guide) <resources/eval/user-guides/ad-fmcdaq2-ebz>`
|
||||||
|
- :adi:`EVAL-FMCDAQ3-EBZ <en/resources/evaluation-hardware-and-software/evaluation-boards-kits/EVAL-FMCDAQ3-EBZ>`
|
||||||
|
:dokuwiki:`(User Guide) <resources/eval/user-guides/ad-fmcdaq3-ebz>`
|
||||||
|
- :adi:`EVAL-AD917X <en/resources/evaluation-hardware-and-software/evaluation-boards-kits/eval-ad9172>`
|
||||||
|
|
||||||
|
JESD204B Analog-to-Digital Converters
|
||||||
|
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
|
||||||
|
- :adi:`AD6673 <en/products/AD6673>`: 80 MHz Bandwidth, Dual IF Receiver
|
||||||
|
- :adi:`AD6674 <en/products/AD6674>`: 385 MHz BW IF Diversity Receiver
|
||||||
|
- :adi:`AD6676 <en/products/AD6676>`: Wideband IF Receiver Subsystem
|
||||||
|
- :adi:`AD6677 <en/products/AD6677>`: 80 MHz Bandwidth, IF Receiver
|
||||||
|
- :adi:`AD6684 <en/products/AD6684>`: 135 MHz Quad IF Receiver
|
||||||
|
- :adi:`AD6688 <en/products/AD6688>`: RF Diversity and 1.2GHz BW Observation
|
||||||
|
Receiver
|
||||||
|
- :adi:`AD9207 <en/products/AD9207>`: 12-Bit, 6 GSPS, JESD204B/JESD204C
|
||||||
|
Dual Analog-to-Digital Converter
|
||||||
|
- :adi:`AD9208 <en/products/AD9208>`: 14-Bit, 3GSPS, JESD204B,
|
||||||
|
Dual Analog-to-Digital Converter
|
||||||
|
- :adi:`AD9209 <en/products/AD9209>`: 12-Bit, 4GSPS, JESD204B/C, Quad
|
||||||
|
Analog-to-Digital Converter
|
||||||
|
- :adi:`AD9213 <en/products/AD9213>`: 12-Bit, 10.25 GSPS, JESD204B, RF
|
||||||
|
Analog-to-Digital Converter
|
||||||
|
- :adi:`AD9234 <en/products/AD9234>`: 12-Bit, 1 GSPS/500 MSPS JESD204B, Dual
|
||||||
|
Analog-to-Digital Converter
|
||||||
|
- :adi:`AD9250 <en/products/AD9250>`: 14-Bit, 170 MSPS/250 MSPS, JESD204B, Dual
|
||||||
|
Analog-to-Digital Converter
|
||||||
|
- :adi:`AD9625 <en/products/AD9625>`: 12-Bit, 2.6 GSPS/2.5 GSPS/2.0 GSPS,
|
||||||
|
1.3 V/2.5 V Analog-to-Digital Converter
|
||||||
|
- :adi:`AD9656 <en/products/AD9656>`: Quad, 16-Bit, 125 MSPS JESD204B 1.8 V
|
||||||
|
Analog-to-Digital Converter
|
||||||
|
- :adi:`AD9680 <en/products/AD9680>`: 14-Bit, 1.25 GSPS/1 GSPS/820 MSPS/500
|
||||||
|
MSPS JESD204B, Dual Analog-to-Digital Converter
|
||||||
|
- :adi:`AD9683 <en/products/AD9683>`: 14-Bit, 170 MSPS/250 MSPS, JESD204B,
|
||||||
|
Analog-to-Digital Converter
|
||||||
|
- :adi:`AD9690 <en/products/AD9690>`: 14-Bit, 500 MSPS / 1 GSPS JESD204B,
|
||||||
|
Analog-to-Digital Converter
|
||||||
|
- :adi:`AD9691 <en/products/AD9691>`: 14-Bit, 1.25 GSPS JESD204B,
|
||||||
|
Dual Analog-to-Digital Converter
|
||||||
|
- :adi:`AD9694 <en/products/AD9694>`: 14-Bit, 500 MSPS JESD204B, Quad
|
||||||
|
Analog-to-Digital Converter
|
||||||
|
- :adi:`AD9695 <en/products/AD9695>`: 14-Bit, 1300 MSPS/625 MSPS,
|
||||||
|
JESD204B, Dual Analog-to-Digital Converter Analog-to-Digital Converter
|
||||||
|
- :adi:`AD9083 <en/products/AD9083>`: 16-Channel, 125 MHz Bandwidth, JESD204B
|
||||||
|
Analog-to-Digital Converter
|
||||||
|
- :adi:`AD9094 <en/products/AD9094>`: 8-Bit, 1 GSPS, JESD204B, Quad
|
||||||
|
Analog-to-Digital Converter
|
||||||
|
|
||||||
|
JESD204B Digital-to-Analog Converters
|
||||||
|
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
|
||||||
|
- :adi:`AD9135 <en/products/AD9135>`: Dual, 11-Bit, high dynamic, 2.8 GSPS,
|
||||||
|
TxDAC+® Digital-to-Analog Converter
|
||||||
|
- :adi:`AD9136 <en/products/AD9136>`: Dual, 16-Bit, 2.8 GSPS, TxDAC+®
|
||||||
|
Digital-to-Analog Converter
|
||||||
|
- :adi:`AD9144 <en/products/AD9144>`: Quad, 16-Bit, 2.8 GSPS, TxDAC+®
|
||||||
|
Digital-to-Analog Converter
|
||||||
|
- :adi:`AD9152 <en/products/AD9152>`: Dual, 16-Bit, 2.25 GSPS, TxDAC+
|
||||||
|
Digital-to-Analog Converter
|
||||||
|
- :adi:`AD9154 <en/products/AD9154>`: Quad, 16-Bit, 2.4 GSPS, TxDAC+®
|
||||||
|
Digital-to-Analog Converter
|
||||||
|
- :adi:`AD9161 <en/products/AD9161>`: 11-Bit, 12 GSPS, RF Digital-to-Analog
|
||||||
|
Converter
|
||||||
|
- :adi:`AD9162 <en/products/AD9162>`: 16-Bit, 12 GSPS, RF Digital-to-Analog
|
||||||
|
Converter
|
||||||
|
- :adi:`AD9163 <en/products/AD9163>`: 16-Bit, 12 GSPS, RF DAC and Digital
|
||||||
|
Upconverter
|
||||||
|
- :adi:`AD9164 <AD9164>`: 16-Bit, 12 GSPS, RF DAC and Direct Digital
|
||||||
|
Synthesizer
|
||||||
|
- :adi:`AD9172 <en/products/AD9172>`: Dual, 16-Bit, 12.6 GSPS RF DAC with
|
||||||
|
Channelizers
|
||||||
|
- :adi:`AD9173 <en/products/AD9173>`: Dual, 16-Bit, 12.6 GSPS RF DAC with
|
||||||
|
Channelizers
|
||||||
|
- :adi:`AD9174 <en/products/AD9174>`: Dual, 16-Bit, 12.6 GSPS RF DAC and Direct
|
||||||
|
Digital Synthesizer
|
||||||
|
- :adi:`AD9175 <en/products/AD9175>`: Dual, 11-Bit/16-Bit, 12.6 GSPS RF DAC with
|
||||||
|
Wideband Channelizers
|
||||||
|
- :adi:`AD9176 <en/products/AD9176>`: Dual, 16-Bit, 12.6 GSPS RF DAC with
|
||||||
|
Wideband Channelizers
|
||||||
|
- :adi:`AD9177 <en/products/AD9177>`: Quad, 16-Bit, 12 GSPS RF DAC with
|
||||||
|
Wideband Channelizers
|
||||||
|
|
||||||
|
JESD204B RF Transceivers
|
||||||
|
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
|
||||||
|
- :adi:`AD9371 <en/products/AD9371>`: SDR Integrated, Dual RF Transceiver with
|
||||||
|
Observation Path
|
||||||
|
- :adi:`AD9375 <en/products/AD9375>`: SDR Integrated, Dual RF Transceiver with
|
||||||
|
Observation Path and DPD
|
||||||
|
- :adi:`ADRV9009 <en/products/ADRV9009>`: SDR Integrated, Dual RF Transceiver
|
||||||
|
with Observation Path
|
||||||
|
- :adi:`ADRV9008-1 <en/products/ADRV9008-1>`: SDR Integrated, Dual RF Receiver
|
||||||
|
- :adi:`ADRV9008-2 <en/products/ADRV9008-2>`: SDR Integrated, Dual RF
|
||||||
|
Transmitter with Observation Path
|
||||||
|
|
||||||
|
JESD204B/C Mixed-Signal Front Ends
|
||||||
|
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
|
||||||
|
- :adi:`AD9081 <en/products/AD9081>`: MxFE™ Quad, 16-Bit, 12GSPS RFDAC and
|
||||||
|
Quad, 12-Bit, 4GSPS RFADC
|
||||||
|
- :adi:`AD9082 <en/products/AD9082>`: MxFE™ QUAD, 16-Bit, 12GSPS RFDAC and
|
||||||
|
DUAL, 12-Bit, 6GSPS RFADC
|
||||||
|
- :adi:`AD9986 <en/products/AD9986>`: 4T2R Direct RF Transmitter and
|
||||||
|
Observation Receiver
|
||||||
|
- :adi:`AD9988 <en/products/AD9988>`: 4T4R Direct RF Receiver and Transmitter
|
||||||
|
|
||||||
|
JESD204B Clocking Solutions
|
||||||
|
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
|
||||||
|
- :adi:`AD9528 <en/products/AD9528>`: JESD204B Clock Generator with 14
|
||||||
|
LVDS/HSTL Outputs
|
||||||
|
- :adi:`HMC7043 <en/products/HMC7043>`: High Performance, 3.2 GHz, 14-Output
|
||||||
|
Fanout Buffer
|
||||||
|
- :adi:`HMC7044 <en/products/HMC7044>`: High Performance, 3.2 GHz, 14-Output
|
||||||
|
Jitter Attenuator with JESD204B
|
||||||
|
- :adi:`LTC6952 <en/products/LTC6952>`: Ultralow Jitter, 4.5GHz PLL,
|
||||||
|
JESD204B/JESD204C
|
||||||
|
- :adi:`ADF 4371 <en/products/ADF4371>`: Microwave Wideband Synthesizer
|
||||||
|
with Integrated VCO
|
||||||
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|
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||||||
|
y="105.19193"
|
||||||
|
ry="10.995686" />
|
||||||
|
<text
|
||||||
|
xml:space="preserve"
|
||||||
|
style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:23.7301px;font-family:sans-serif;-inkscape-font-specification:'sans-serif, ';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-variant-east-asian:normal;fill:#000000;fill-opacity:1;stroke:none;stroke-width:1.41852;stroke-linejoin:round"
|
||||||
|
x="75.94458"
|
||||||
|
y="135.13809"
|
||||||
|
id="text3-5"><tspan
|
||||||
|
id="tspan3-7"
|
||||||
|
x="75.94458"
|
||||||
|
y="135.13809"
|
||||||
|
style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:23.7301px;font-family:sans-serif;-inkscape-font-specification:'sans-serif, ';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-variant-east-asian:normal;fill:#000000;fill-opacity:1;stroke:none;stroke-width:1.41852">Link</tspan></text>
|
||||||
|
<rect
|
||||||
|
style="fill:#809eaf;fill-opacity:1;stroke:#000000;stroke-width:1.39635;stroke-linejoin:round;stroke-dasharray:none;stroke-opacity:1"
|
||||||
|
id="rect1-6"
|
||||||
|
width="201.44069"
|
||||||
|
height="41.863022"
|
||||||
|
x="0.69817543"
|
||||||
|
y="157.4388"
|
||||||
|
ry="10.995686" />
|
||||||
|
<text
|
||||||
|
xml:space="preserve"
|
||||||
|
style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:23.7301px;font-family:sans-serif;-inkscape-font-specification:'sans-serif, ';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-variant-east-asian:normal;fill:#000000;fill-opacity:1;stroke:none;stroke-width:1.41852;stroke-linejoin:round"
|
||||||
|
x="53.772926"
|
||||||
|
y="184.99805"
|
||||||
|
id="text3-1"><tspan
|
||||||
|
id="tspan3-1"
|
||||||
|
x="53.772926"
|
||||||
|
y="184.99805"
|
||||||
|
style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:23.7301px;font-family:sans-serif;-inkscape-font-specification:'sans-serif, ';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-variant-east-asian:normal;fill:#000000;fill-opacity:1;stroke:none;stroke-width:1.41852">Physical</tspan></text>
|
||||||
|
</svg>
|
||||||
|
After Width: | Height: | Size: 7.2 KiB |
|
|
@ -54,15 +54,13 @@ Signal and Interface Pins
|
||||||
* - resetn
|
* - resetn
|
||||||
- Synchronous active-low reset.
|
- Synchronous active-low reset.
|
||||||
Resets the internal state of the module.
|
Resets the internal state of the module.
|
||||||
* - s0_ctrl
|
* - s*_ctrl
|
||||||
- :ref:`spi_engine control-interface` slave.
|
- :ref:`spi_engine control-interface` slave.
|
||||||
Connects to the first control interface master.
|
| ``s0_ctrl`` connects to the first control interface master.
|
||||||
* - s1_ctrl
|
| ``s1_ctrl`` connects to the second control interface master.
|
||||||
- :ref:`spi_engine control-interface` slave.
|
|
||||||
Connects to the second control interface master.
|
|
||||||
* - m_ctrl
|
* - m_ctrl
|
||||||
- :ref:`spi_engine control-interface` master.
|
- | :ref:`spi_engine control-interface` master.
|
||||||
Connects to the control interface slave.
|
| Connects to the control interface slave.
|
||||||
|
|
||||||
Theory of Operation
|
Theory of Operation
|
||||||
--------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------
|
||||||
|
|
|
||||||
|
|
@ -0,0 +1,12 @@
|
||||||
|
.. _xilinx:
|
||||||
|
|
||||||
|
AMD Xilinx Specific IPs
|
||||||
|
================================================================================
|
||||||
|
|
||||||
|
Contents
|
||||||
|
--------
|
||||||
|
|
||||||
|
.. toctree::
|
||||||
|
:maxdepth: 2
|
||||||
|
|
||||||
|
UTIL_ADXCVR <util_adxcvr/index>
|
||||||
File diff suppressed because it is too large
Load Diff
|
After Width: | Height: | Size: 178 KiB |
|
|
@ -0,0 +1,316 @@
|
||||||
|
.. _util_adxcvr:
|
||||||
|
|
||||||
|
UTIL_ADXCVR core for AMD Xilinx devices
|
||||||
|
================================================================================
|
||||||
|
|
||||||
|
.. hdl-component-diagram::
|
||||||
|
:path: library/xilinx/util_adxcvr
|
||||||
|
|
||||||
|
The
|
||||||
|
:git-hdl:`util_adxcvr <library/xilinx/util_adxcvr>`
|
||||||
|
IP core instantiates a Gigabit Transceiver (GT) and sets up the required
|
||||||
|
configuration. Basically, it is a simple wrapper file for a GT\* Column,
|
||||||
|
exposing just the necessary ports and attributes.
|
||||||
|
|
||||||
|
.. note::
|
||||||
|
To understand the below wiki page is important to have a basic
|
||||||
|
understanding about High Speed Serial I/O interfaces and Gigabit Serial
|
||||||
|
Transceivers. To find more information about these technologies, please visit
|
||||||
|
the :xilinx:`AMD Xilinx's solution center <support/answers/37181.html>`.
|
||||||
|
|
||||||
|
Currently this IP supports three different GT types:
|
||||||
|
|
||||||
|
- GTXE2
|
||||||
|
(:xilinx:`7 Series devices <support/documentation/user_guides/ug476_7Series_Transceivers.pdf>`)
|
||||||
|
- GTHE3
|
||||||
|
(:xilinx:`Ultrascale and Ultrascale+ <support/documentation/user_guides/ug576-ultrascale-gth-transceivers.pdf>`)
|
||||||
|
- GTHE4
|
||||||
|
(:xilinx:`Ultrascale and Ultrascale+ <support/documentation/user_guides/ug576-ultrascale-gth-transceivers.pdf>`)
|
||||||
|
- GTYE4
|
||||||
|
(:xilinx:`Ultrascale and Ultrascale+ <support/documentation/user_guides/ug578-ultrascale-gty-transceivers.pdf>`)
|
||||||
|
|
||||||
|
Features
|
||||||
|
--------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
* Supports GTX2, GTH3 and GTH4
|
||||||
|
* Exposes all the necessary attributes for QPLL/CPLL configuration
|
||||||
|
* Supports shared transceiver mode
|
||||||
|
* Supports dynamic reconfiguration
|
||||||
|
* RX Eye Scan
|
||||||
|
|
||||||
|
Block Diagram
|
||||||
|
--------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
The following diagram shows a GTXE2 Column, which contains four GT Quads. Each
|
||||||
|
quad contains a GTEX2_COMMON and four GTXE2_CHANNEL primitives.
|
||||||
|
|
||||||
|
.. image:: gtx_column.svg
|
||||||
|
:align: center
|
||||||
|
|
||||||
|
Configuration Parameters
|
||||||
|
--------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
.. hdl-parameters::
|
||||||
|
|
||||||
|
* - XCVR_TYPE
|
||||||
|
- | Define the current GT type:
|
||||||
|
| GTXE2(0), GTHE3(1), GTHE4(2)
|
||||||
|
* - QPLL_REFCLK_DIV
|
||||||
|
- QPLL reference clock divider M, see User Guide for more info
|
||||||
|
* - QPLL_FBDIV_RATIO
|
||||||
|
- QPLL reference clock divider N ratio, see User Guide for more info
|
||||||
|
* - QPLL_CFG
|
||||||
|
- Configuration settings for QPLL, see User Guide for more info
|
||||||
|
* - QPLL_FBDIV
|
||||||
|
- QPLL reference clock divider N, see User Guide for more info
|
||||||
|
* - CPLL_FBDIV
|
||||||
|
- CPLL feedback divider N2 settings, see User Guide for more info
|
||||||
|
* - CPLL_FBDIV_4_5
|
||||||
|
- CPLL reference clock divider N1 settings, see User Guide for more info
|
||||||
|
* - TX_NUM_OF_LANES
|
||||||
|
- Number of transmit lanes.
|
||||||
|
* - TX_OUT_DIV
|
||||||
|
- CPLL/QPLL output clock divider D for the TX datapath, see User Guide for
|
||||||
|
more info
|
||||||
|
* - TX_CLK25_DIV
|
||||||
|
- Divider for internal 25 MHz clock for the TX datapath, see User Guide
|
||||||
|
for more info
|
||||||
|
* - TX_LANE_INVERT
|
||||||
|
- Per lane polarity inversion. Set the n-th bit to invert the polarity of
|
||||||
|
the n-th transmit lane.
|
||||||
|
* - RX_NUM_OF_LANES
|
||||||
|
- Number of transmit lanes
|
||||||
|
* - RX_OUT_DIV
|
||||||
|
- CPLL/QPLL output clock divider D for the RX datapath, see User Guide for
|
||||||
|
more info
|
||||||
|
* - RX_CLK25_DIV
|
||||||
|
- Divider for internal 25 MHz clock for the RX datapath, see User Guide
|
||||||
|
for more info
|
||||||
|
* - RX_DFE_LPM_CFG
|
||||||
|
- Configure the GT use modes, LPM or DFE, see User Guide for more info
|
||||||
|
* - RX_PMA_CFG
|
||||||
|
- Search for PMA_RSV in User Guide for more info
|
||||||
|
* - RX_CDR_CFG
|
||||||
|
- Configure the RX clock data recovery circuit for GTXE2, see User Guide
|
||||||
|
for more info
|
||||||
|
* - RX_LANE_INVERT
|
||||||
|
- Per lane polarity inversion. Set the n-th bit to invert the polarity of
|
||||||
|
the n-th receive lane.
|
||||||
|
|
||||||
|
Interface
|
||||||
|
--------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
Microprocessor clock and reset
|
||||||
|
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||||
|
|
||||||
|
.. list-table::
|
||||||
|
:header-rows: 1
|
||||||
|
|
||||||
|
* - Pin
|
||||||
|
- Type
|
||||||
|
- Description
|
||||||
|
* - ``up_clk``
|
||||||
|
- ``input``
|
||||||
|
- System clock, running on 100 MHz
|
||||||
|
* - ``up_rstn``
|
||||||
|
- ``input``
|
||||||
|
- System reset, the same as AXI memory map slave interface reset
|
||||||
|
|
||||||
|
PLL reference clock
|
||||||
|
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||||
|
|
||||||
|
.. list-table::
|
||||||
|
:header-rows: 1
|
||||||
|
|
||||||
|
* - Pin
|
||||||
|
- Type
|
||||||
|
- Description
|
||||||
|
* - ``qpll_ref_clk_0``
|
||||||
|
- ``input``
|
||||||
|
- Reference clock for the QPLL
|
||||||
|
* - ``cpll_ref_clk_0``
|
||||||
|
- ``input``
|
||||||
|
- Reference clock for the CPLL
|
||||||
|
|
||||||
|
RX interface
|
||||||
|
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||||
|
|
||||||
|
.. list-table::
|
||||||
|
:header-rows: 1
|
||||||
|
|
||||||
|
* - Pin
|
||||||
|
- Type
|
||||||
|
- Description
|
||||||
|
* - ``rx_*_p``
|
||||||
|
- ``input``
|
||||||
|
- Positive differential serial data input
|
||||||
|
* - ``rx_*_n``
|
||||||
|
- ``input``
|
||||||
|
- Negative differential serial data input
|
||||||
|
* - ``rx_out_clk_*``
|
||||||
|
- ``output``
|
||||||
|
- Core logic clock output. Frequency = serial line rate/40
|
||||||
|
* - ``rx_clk_*``
|
||||||
|
- ``input``
|
||||||
|
- Core logic clock loop-back input
|
||||||
|
* - ``rx_charisk_*``
|
||||||
|
- ``output[3:0]``
|
||||||
|
- RX Char is K to the JESD204B IP
|
||||||
|
* - ``rx_disperr_*``
|
||||||
|
- ``output[3:0]``
|
||||||
|
- RX disparity error to the JESD204B IP
|
||||||
|
* - ``rx_notintable_*``
|
||||||
|
- ``output[3:0]``
|
||||||
|
- RX Not In Table to the JESD204B IP
|
||||||
|
* - ``rx_data_*``
|
||||||
|
- ``output[3:0]``
|
||||||
|
- RX data to the JESD204B IP
|
||||||
|
* - ``rx_calign_*``
|
||||||
|
- ``input``
|
||||||
|
- RX enable comma alignment from the JESD204B IP
|
||||||
|
|
||||||
|
TX interface
|
||||||
|
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||||
|
|
||||||
|
.. list-table::
|
||||||
|
:header-rows: 1
|
||||||
|
|
||||||
|
* - Pin
|
||||||
|
- Type
|
||||||
|
- Description
|
||||||
|
* - ``tx_*_p``
|
||||||
|
- ``output``
|
||||||
|
- Positive differential serial output
|
||||||
|
* - ``tx_*_n``
|
||||||
|
- ``output``
|
||||||
|
- Negative differential serial output
|
||||||
|
* - ``tx_out_clk_*``
|
||||||
|
- ``output``
|
||||||
|
- Core logic clock output. Frequency = serial line rate/40
|
||||||
|
* - ``tx_clk_*``
|
||||||
|
- ``input``
|
||||||
|
- Core logic clock loop-back input
|
||||||
|
* - ``tx_charisk_*``
|
||||||
|
- ``input[3:0]``
|
||||||
|
- TX Char is K from the JESD204B IP
|
||||||
|
* - ``tx_data_*``
|
||||||
|
- ``input[31:0]``
|
||||||
|
- TX data from the JESD204B IP
|
||||||
|
|
||||||
|
Common DRP Interface
|
||||||
|
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||||
|
|
||||||
|
.. list-table::
|
||||||
|
:header-rows: 1
|
||||||
|
|
||||||
|
* - Pin
|
||||||
|
- Type
|
||||||
|
- Description
|
||||||
|
* - ``up_cm_*``
|
||||||
|
- ``IO``
|
||||||
|
- The common DRP interface, must be connected to the equivalent DRP ports
|
||||||
|
of AXI_ADXCVR. This is a QUAD interface, shared by four transceiver
|
||||||
|
lanes. This interface is available only if parameter QPLL_ENABLE is set
|
||||||
|
to 0x1.
|
||||||
|
|
||||||
|
Channel DRP Interface
|
||||||
|
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||||
|
|
||||||
|
.. list-table::
|
||||||
|
:header-rows: 1
|
||||||
|
|
||||||
|
* - Pin
|
||||||
|
- Type
|
||||||
|
- Description
|
||||||
|
* - ``up_rx_*``
|
||||||
|
- ``IO``
|
||||||
|
- The RX channel DRP interface, must be connected to the equivalent DRP ports
|
||||||
|
of AXI_ADXCVR. This is a channel interface, one per each RX transceiver
|
||||||
|
lane.
|
||||||
|
* - ``up_tx_*``
|
||||||
|
- ``IO``
|
||||||
|
- The TX channel DRP interface, must be connected to the equivalent DRP ports
|
||||||
|
of AXI_ADXCVR. This is a channel interface, one per each TX transceiver
|
||||||
|
lane.
|
||||||
|
|
||||||
|
Eye Scan DRP Interface
|
||||||
|
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||||
|
|
||||||
|
.. list-table::
|
||||||
|
:header-rows: 1
|
||||||
|
|
||||||
|
* - Pin
|
||||||
|
- Type
|
||||||
|
- Description
|
||||||
|
* - ``up_es_*``
|
||||||
|
- ``IO``
|
||||||
|
- The Eye-Scan DRP interface, must be connected to the equivalent DRP
|
||||||
|
ports of UTIL_ADXCVR. This is a channel interface, one per each
|
||||||
|
transceiver lane. This interface is available only if parameter
|
||||||
|
TX_OR_RX_N is set to 0x0.
|
||||||
|
|
||||||
|
Design Guidelines
|
||||||
|
--------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
.. note::
|
||||||
|
Please refer to :dokuwiki:`AMD Xilinx FPGAs Transceivers Wizard <resources/fpga/docs/xgt_wizard>`
|
||||||
|
to generate the optimal parameters needed to configure the transceivers for
|
||||||
|
your project.
|
||||||
|
|
||||||
|
Physical constraints considerations
|
||||||
|
--------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
The util_adxcvr allocates resources/quads (channels and common) sequentially.
|
||||||
|
Meaning, if you have 8 lanes it will insert two quads, 4 channels and a common
|
||||||
|
block for each quad.
|
||||||
|
|
||||||
|
Channels within a quad are tightly coupled to the common block, the placement of
|
||||||
|
the channel resources can be permuted within a quad and is affected by the
|
||||||
|
constraint file with the restriction that rx\_<N>_p/n connect to tx\_<N>_p/n
|
||||||
|
must connect to the same channel.
|
||||||
|
|
||||||
|
Supposing we have the following pin constraints and connections to the
|
||||||
|
util_adxcvr:
|
||||||
|
|
||||||
|
.. image:: xcvr_mapping_example.svg
|
||||||
|
:align: center
|
||||||
|
|
||||||
|
So in this case we end up with a conflict during implementation:
|
||||||
|
|
||||||
|
.. image:: xcvr_conflict.svg
|
||||||
|
:align: center
|
||||||
|
|
||||||
|
We have to ensure that in implementation the mapping is correct either by
|
||||||
|
rearranging the Rx connections
|
||||||
|
|
||||||
|
.. image:: xcvr_rx_rearrangement.svg
|
||||||
|
:align: center
|
||||||
|
|
||||||
|
or by rearranging the Tx connections of the util_adxcvr:
|
||||||
|
|
||||||
|
.. image:: xcvr_tx_rearrangement.svg
|
||||||
|
:align: center
|
||||||
|
|
||||||
|
In such cases, when rearrangement is required due placement constraints,
|
||||||
|
complementary reordering is required either in the converter device (lane
|
||||||
|
crossbars) or inside the FPGA between the physical and link layer, to connect
|
||||||
|
the logical lanes with the same index on both end of the link.
|
||||||
|
|
||||||
|
Software Guidelines
|
||||||
|
--------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
The software can configure this core through the :ref:`AXI_ADXCVR <axi_adxcvr>` IP
|
||||||
|
core.
|
||||||
|
|
||||||
|
References
|
||||||
|
--------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
- :xilinx:`High Speed Serial <products/technology/high-speed-serial.html>`
|
||||||
|
- :xilinx:`7 Series FPGAs GTX/GTH Transceivers <support/documentation/user_guides/ug476_7Series_Transceivers.pdf>`
|
||||||
|
- :xilinx:`UltraScale Architecture GTH Transceivers <support/documentation/user_guides/ug576-ultrascale-gth-transceivers.pdf>`
|
||||||
|
- :xilinx:`UltraScale Architecture GTY Transceivers <support/documentation/user_guides/ug578-ultrascale-gty-transceivers.pdf>`
|
||||||
|
|
||||||
|
More Information
|
||||||
|
--------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
- :ref:`JESD204B High-Speed Serial Interface Support <jesd204>`
|
||||||
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|
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|
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|
|
@ -1,5 +1,5 @@
|
||||||
TITLE
|
TITLE
|
||||||
Xilinx XCVR (axi_xcvr) Regmap
|
Xilinx XCVR (axi_xcvr)
|
||||||
XCVR
|
XCVR
|
||||||
ENDTITLE
|
ENDTITLE
|
||||||
|
|
||||||
|
|
@ -110,7 +110,7 @@ ENDFIELD
|
||||||
REG
|
REG
|
||||||
0x0007
|
0x0007
|
||||||
FPGA_INFO
|
FPGA_INFO
|
||||||
FPGA device information [[https://github.com/analogdevicesinc/hdl/blob/main/library/scripts/adi_xilinx_device_info_enc.tcl |Xilinx encoded values]]
|
FPGA device information :git-hdl:`Xilinx encoded values <library/scripts/adi_xilinx_device_info_enc.tcl>`
|
||||||
ENDREG
|
ENDREG
|
||||||
|
|
||||||
FIELD
|
FIELD
|
||||||
|
|
@ -168,14 +168,19 @@ FIELD
|
||||||
[5:4]
|
[5:4]
|
||||||
SYSCLK_SEL[1:0]
|
SYSCLK_SEL[1:0]
|
||||||
RW
|
RW
|
||||||
For GTX drives directly the (RX/TX)SYSCLKSEL pin of the transceiver. Refer to Xilinx documentation. For GTH/GTY drives directly the (RX/TX)PLLCLKSEL pin of the transceiver and indirectly the (RX/TX)SYSCLKSEL pin of the transceiver see [[:resources:fpga:docs:axi_adxcvr#Table 1]].
|
For GTX drives directly the (RX/TX)SYSCLKSEL pin of the transceiver refer to
|
||||||
|
Xilinx documentation.
|
||||||
|
For GTH/GTY drives directly the (RX/TX)PLLCLKSEL pin of the transceiver and
|
||||||
|
indirectly the (RX/TX)SYSCLKSEL pin of the transceiver see
|
||||||
|
:ref:`Table 1 <axi_adxcvr table_one_label>`.
|
||||||
ENDFIELD
|
ENDFIELD
|
||||||
|
|
||||||
FIELD
|
FIELD
|
||||||
[2:0]
|
[2:0]
|
||||||
OUTCLK_SEL[2:0]
|
OUTCLK_SEL[2:0]
|
||||||
RW
|
RW
|
||||||
Transceiver primitive control [[:resources:fpga:docs:axi_adxcvr#Table 2]], refer Xilinx documentation.
|
Transceiver primitive control :ref:`Table 2 <axi_adxcvr table_two_label>`,
|
||||||
|
refer Xilinx documentation.
|
||||||
ENDFIELD
|
ENDFIELD
|
||||||
|
|
||||||
############################################################################################
|
############################################################################################
|
||||||
|
|
@ -198,7 +203,7 @@ FIELD
|
||||||
[19:16]
|
[19:16]
|
||||||
XCVR_TYPE[3:0]
|
XCVR_TYPE[3:0]
|
||||||
RO
|
RO
|
||||||
[[https://github.com/analogdevicesinc/hdl/blob/main/library/scripts/adi_xilinx_device_info_enc.tcl | Xilinx encoded values.]]
|
:git-hdl:`Xilinx encoded values <library/scripts/adi_xilinx_device_info_enc.tcl>`.
|
||||||
ENDFIELD
|
ENDFIELD
|
||||||
|
|
||||||
FIELD
|
FIELD
|
||||||
|
|
@ -649,5 +654,224 @@ RO
|
||||||
Ignore this bit for GTX transceivers. For others: Indicates that the RX PRBS checker has been error free for 15 XCLK cycles after reset. Once asserted High, it does not deassert until reset of the RX pattern checker via PRBSCNTRESET
|
Ignore this bit for GTX transceivers. For others: Indicates that the RX PRBS checker has been error free for 15 XCLK cycles after reset. Once asserted High, it does not deassert until reset of the RX pattern checker via PRBSCNTRESET
|
||||||
ENDFIELD
|
ENDFIELD
|
||||||
|
|
||||||
|
############################################################################################
|
||||||
|
############################################################################################
|
||||||
|
|
||||||
|
TITLE
|
||||||
|
Intel XCVR (axi_xcvr)
|
||||||
|
INTEL_XCVR
|
||||||
|
ENDTITLE
|
||||||
|
|
||||||
|
############################################################################################
|
||||||
|
############################################################################################
|
||||||
|
|
||||||
|
REG
|
||||||
|
0x0000
|
||||||
|
REG_VERSION
|
||||||
|
Version Register
|
||||||
|
ENDREG
|
||||||
|
|
||||||
|
FIELD
|
||||||
|
[31:0]
|
||||||
|
VERSION[31:0]
|
||||||
|
RO
|
||||||
|
Version number.
|
||||||
|
ENDFIELD
|
||||||
|
|
||||||
|
############################################################################################
|
||||||
|
############################################################################################
|
||||||
|
|
||||||
|
REG
|
||||||
|
0x0001
|
||||||
|
REG_ID
|
||||||
|
Instance Identification Register
|
||||||
|
ENDREG
|
||||||
|
|
||||||
|
FIELD
|
||||||
|
[31:0]
|
||||||
|
ID[31:0]
|
||||||
|
RO
|
||||||
|
Instance identifier number.
|
||||||
|
ENDFIELD
|
||||||
|
|
||||||
|
############################################################################################
|
||||||
|
############################################################################################
|
||||||
|
|
||||||
|
REG
|
||||||
|
0x0002
|
||||||
|
REG_SCRATCH
|
||||||
|
Scratch (GP R/W) Register
|
||||||
|
ENDREG
|
||||||
|
|
||||||
|
FIELD
|
||||||
|
[31:0]
|
||||||
|
SCRATCH[31:0]
|
||||||
|
RW
|
||||||
|
Scratch register.
|
||||||
|
ENDFIELD
|
||||||
|
|
||||||
|
############################################################################################
|
||||||
|
############################################################################################
|
||||||
|
|
||||||
|
REG
|
||||||
|
0x0004
|
||||||
|
RESETN
|
||||||
|
Reset Control Register
|
||||||
|
ENDREG
|
||||||
|
|
||||||
|
FIELD
|
||||||
|
[0]
|
||||||
|
RESETN
|
||||||
|
RW
|
||||||
|
If clear, link is held in reset, set this bit to 0x1 to activate link. Note that the reference clock must be active before setting this bit.
|
||||||
|
ENDFIELD
|
||||||
|
|
||||||
|
############################################################################################
|
||||||
|
############################################################################################
|
||||||
|
|
||||||
|
REG
|
||||||
|
0x0005
|
||||||
|
REG_STATUS
|
||||||
|
Status Reporting Register
|
||||||
|
ENDREG
|
||||||
|
|
||||||
|
FIELD
|
||||||
|
[0]
|
||||||
|
STATUS
|
||||||
|
RO
|
||||||
|
After setting the RESETN bit above, wait for this bit to set. If set, indicates successful link activation.
|
||||||
|
ENDFIELD
|
||||||
|
|
||||||
|
############################################################################################
|
||||||
|
############################################################################################
|
||||||
|
|
||||||
|
REG
|
||||||
|
0x0006
|
||||||
|
REG_STATUS_32
|
||||||
|
Status Reporting Register
|
||||||
|
ENDREG
|
||||||
|
|
||||||
|
FIELD
|
||||||
|
[31:NUM_OF_LANES]
|
||||||
|
RESERVED
|
||||||
|
RO
|
||||||
|
0
|
||||||
|
ENDFIELD
|
||||||
|
|
||||||
|
FIELD
|
||||||
|
[NUM_OF_LANES]
|
||||||
|
UP_PLL_LOCKED
|
||||||
|
RO
|
||||||
|
After setting the RESETN bit above, wait for this bit be to set.
|
||||||
|
ENDFIELD
|
||||||
|
|
||||||
|
FIELD
|
||||||
|
[NUM_OF_LANES-1:0]
|
||||||
|
CHANNEL_N_READY
|
||||||
|
RO
|
||||||
|
After setting the RESETN bit above, wait for this registers to be set.
|
||||||
|
ENDFIELD
|
||||||
|
|
||||||
|
############################################################################################
|
||||||
|
############################################################################################
|
||||||
|
|
||||||
|
REG
|
||||||
|
0x0007
|
||||||
|
REG_FPGA_INFO
|
||||||
|
FPGA device information :git-hdl:`Intel Encoded Values <library/scripts/adi_intel_device_info_enc.tcl>`
|
||||||
|
ENDREG
|
||||||
|
|
||||||
|
FIELD
|
||||||
|
[31:24]
|
||||||
|
FPGA_TECHNOLOGY
|
||||||
|
RO
|
||||||
|
Encoded value describing the technology/generation of the FPGA device (e.g., cyclone V, arria 10, stratix 10)
|
||||||
|
ENDFIELD
|
||||||
|
|
||||||
|
FIELD
|
||||||
|
[23:16]
|
||||||
|
FPGA_FAMILY
|
||||||
|
RO
|
||||||
|
Encoded value describing the family variant of the FPGA device(e.g., SX, GX, GT or zynq, kintex, virtex)
|
||||||
|
ENDFIELD
|
||||||
|
|
||||||
|
FIELD
|
||||||
|
[15:8]
|
||||||
|
SPEED_GRADE
|
||||||
|
RO
|
||||||
|
Encoded value describing the FPGA's speed-grade
|
||||||
|
ENDFIELD
|
||||||
|
|
||||||
|
FIELD
|
||||||
|
[7:0]
|
||||||
|
DEV_PACKAGE
|
||||||
|
RO
|
||||||
|
Encoded value describing the device package. The package might affect high-speed interfaces
|
||||||
|
ENDFIELD
|
||||||
|
|
||||||
|
############################################################################################
|
||||||
|
############################################################################################
|
||||||
|
|
||||||
|
REG
|
||||||
|
0x0009
|
||||||
|
REG_GENERIC_INFO
|
||||||
|
Physical layer info
|
||||||
|
ENDREG
|
||||||
|
|
||||||
|
FIELD
|
||||||
|
[31:28]
|
||||||
|
RESERVED
|
||||||
|
RO
|
||||||
|
0
|
||||||
|
ENDFIELD
|
||||||
|
|
||||||
|
FIELD
|
||||||
|
[27:24]
|
||||||
|
XCVR_TYPE[3:0]
|
||||||
|
RO
|
||||||
|
Refers to the transceiver speed grade 0-9.
|
||||||
|
ENDFIELD
|
||||||
|
|
||||||
|
FIELD
|
||||||
|
[23:12]
|
||||||
|
RESERVED
|
||||||
|
RO
|
||||||
|
0
|
||||||
|
ENDFIELD
|
||||||
|
|
||||||
|
FIELD
|
||||||
|
[11:9]
|
||||||
|
RESERVED
|
||||||
|
RO
|
||||||
|
0
|
||||||
|
ENDFIELD
|
||||||
|
|
||||||
|
FIELD
|
||||||
|
[8]
|
||||||
|
TX_OR_RX_N
|
||||||
|
RO
|
||||||
|
Transceiver type (transmit or receive)
|
||||||
|
ENDFIELD
|
||||||
|
|
||||||
|
FIELD
|
||||||
|
[7:0]
|
||||||
|
NUM_OF_LANES
|
||||||
|
RO
|
||||||
|
Physical layer number of lanes.
|
||||||
|
ENDFIELD
|
||||||
|
|
||||||
|
############################################################################################
|
||||||
|
############################################################################################
|
||||||
|
|
||||||
|
REG
|
||||||
|
0x0050
|
||||||
|
REG_FPGA_VOLTAGE
|
||||||
|
FPGA device voltage information
|
||||||
|
ENDREG
|
||||||
|
|
||||||
|
FIELD
|
||||||
|
[15:0]
|
||||||
|
FPGA_VOLTAGE
|
||||||
|
RO
|
||||||
|
The voltage of the FPGA device in mv
|
||||||
|
ENDFIELD
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue