daq2/a10gx: added axi_jesd_xcvr control
Rejeesh Kutty
parent
c1fcbeec8e
commit
075b1e5424
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@ -29,7 +29,7 @@
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{
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datum baseAddress
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{
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value = "262144";
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value = "327680";
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type = "String";
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}
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}
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@ -50,7 +50,7 @@
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{
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datum baseAddress
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{
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value = "393216";
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value = "458752";
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type = "String";
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}
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}
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@ -66,7 +66,7 @@
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{
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datum baseAddress
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{
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value = "327680";
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value = "393216";
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type = "String";
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}
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}
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@ -95,7 +95,23 @@
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{
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datum baseAddress
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{
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value = "409600";
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value = "475136";
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type = "String";
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}
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}
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element axi_jesd_xcvr
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{
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datum _sortIndex
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{
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value = "22";
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type = "int";
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}
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}
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element axi_jesd_xcvr.s_axi
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{
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datum baseAddress
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{
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value = "262144";
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type = "String";
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}
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}
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@ -124,7 +140,7 @@
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{
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datum baseAddress
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{
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value = "436224";
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value = "501760";
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type = "String";
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}
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}
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@ -166,7 +182,7 @@
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{
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datum baseAddress
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{
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value = "438272";
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value = "503808";
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type = "String";
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}
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}
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@ -182,7 +198,7 @@
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{
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datum baseAddress
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{
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value = "439424";
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value = "504960";
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type = "String";
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}
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}
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@ -190,7 +206,7 @@
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{
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datum baseAddress
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{
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value = "439392";
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value = "504928";
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type = "String";
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}
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}
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@ -198,7 +214,7 @@
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{
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datum baseAddress
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{
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value = "439520";
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value = "505056";
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type = "String";
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}
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}
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@ -214,7 +230,7 @@
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{
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datum baseAddress
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{
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value = "439456";
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value = "504992";
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type = "String";
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}
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}
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@ -222,7 +238,7 @@
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{
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datum baseAddress
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{
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value = "439360";
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value = "504896";
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type = "String";
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}
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}
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@ -238,7 +254,7 @@
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{
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datum baseAddress
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{
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value = "439488";
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value = "505024";
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type = "String";
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}
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}
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@ -259,7 +275,7 @@
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{
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datum baseAddress
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{
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value = "439504";
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value = "505040";
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type = "String";
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}
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}
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@ -280,7 +296,7 @@
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{
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datum baseAddress
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{
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value = "439528";
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value = "505064";
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type = "String";
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}
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}
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@ -327,7 +343,7 @@
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{
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datum baseAddress
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{
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value = "439296";
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value = "504832";
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type = "String";
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}
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}
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@ -343,7 +359,7 @@
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{
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datum baseAddress
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{
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value = "430080";
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value = "495616";
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type = "String";
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}
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}
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@ -364,7 +380,7 @@
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{
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datum baseAddress
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{
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value = "439328";
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value = "504864";
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type = "String";
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}
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}
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@ -385,7 +401,7 @@
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{
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datum baseAddress
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{
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value = "439536";
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value = "505072";
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type = "String";
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}
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}
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@ -405,14 +421,6 @@
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type = "String";
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}
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}
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element sys_xcvr_rst
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{
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datum _sortIndex
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{
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value = "22";
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type = "int";
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}
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}
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element sys_xcvr_rstcntrl
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{
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datum _sortIndex
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@ -573,6 +581,30 @@
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type = "String";
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}
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}
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element system_bd
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{
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datum _originalDeviceFamily
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{
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value = "Arria 10";
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type = "String";
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}
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}
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element system_bd
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{
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datum _originalDeviceFamily
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{
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value = "Arria 10";
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type = "String";
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}
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}
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element system_bd
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{
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datum _originalDeviceFamily
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{
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value = "Arria 10";
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type = "String";
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}
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}
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element util_cpack_0
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{
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datum _sortIndex
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@ -646,6 +678,26 @@
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name="axi_dmac_1_fifo_wr_clock"
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internal="axi_ad9144_dma.fifo_wr_clock" />
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<interface name="axi_dmac_1_fifo_wr_if" internal="axi_ad9144_dma.fifo_wr_if" />
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<interface
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name="rx_data"
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internal="sys_xcvr.rx_serial_data"
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type="conduit"
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dir="end" />
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<interface
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name="rx_ref_clk"
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internal="sys_xcvr_rx_ref_clk.clk_in"
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type="clock"
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dir="end" />
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<interface
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name="rx_sync"
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internal="axi_jesd_xcvr.if_rx_sync"
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type="conduit"
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dir="end" />
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<interface
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name="rx_sysref"
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internal="axi_jesd_xcvr.if_rx_ext_sysref"
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type="conduit"
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dir="end" />
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<interface name="sys_clk" internal="sys_clk.clk_in" type="clock" dir="end" />
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<interface
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name="sys_ddr3_cntrl_mem"
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@ -718,58 +770,23 @@
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dir="end" />
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<interface name="sys_spi" internal="sys_spi.external" type="conduit" dir="end" />
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<interface
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name="sys_xcvr_reset"
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internal="sys_xcvr_rst.in_reset"
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type="reset"
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dir="end" />
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<interface
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name="sys_xcvr_rstcntrl_rx_ready"
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internal="sys_xcvr_rstcntrl.rx_ready"
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name="tx_data"
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internal="sys_xcvr.tx_serial_data"
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type="conduit"
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dir="end" />
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<interface
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name="sys_xcvr_rstcntrl_tx_ready"
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internal="sys_xcvr_rstcntrl.tx_ready"
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type="conduit"
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dir="end" />
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<interface
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name="sys_xcvr_rx_ref_clk"
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internal="sys_xcvr_rx_ref_clk.clk_in"
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type="clock"
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dir="end" />
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<interface
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name="sys_xcvr_rx_sync_n"
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internal="sys_xcvr.rx_dev_sync_n"
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type="conduit"
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dir="end" />
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<interface
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name="sys_xcvr_rx_sysref"
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internal="sys_xcvr.rx_sysref"
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type="conduit"
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dir="end" />
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<interface
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name="sys_xcvr_rxd"
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internal="sys_xcvr.rx_serial_data"
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type="conduit"
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dir="end" />
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<interface
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name="sys_xcvr_tx_ref_clk"
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name="tx_ref_clk"
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internal="sys_xcvr_tx_ref_clk.clk_in"
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type="clock"
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dir="end" />
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<interface
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name="sys_xcvr_tx_sync_n"
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internal="sys_xcvr.sync_n"
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name="tx_sync"
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internal="axi_jesd_xcvr.if_tx_sync"
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type="conduit"
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dir="end" />
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<interface
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name="sys_xcvr_tx_sysref"
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internal="sys_xcvr.tx_sysref"
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type="conduit"
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dir="end" />
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<interface
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name="sys_xcvr_txd"
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internal="sys_xcvr.tx_serial_data"
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name="tx_sysref"
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internal="axi_jesd_xcvr.if_tx_ext_sysref"
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type="conduit"
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dir="end" />
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<module name="axi_ad9144_core" kind="axi_ad9144" version="1.0" enabled="1">
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@ -811,6 +828,12 @@
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<parameter name="C_SYNC_TRANSFER_START" value="0" />
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<parameter name="PCORE_ID" value="0" />
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</module>
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<module name="axi_jesd_xcvr" kind="axi_jesd_xcvr" version="1.0" enabled="1">
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<parameter name="PCORE_DEVICE_TYPE" value="0" />
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<parameter name="PCORE_ID" value="0" />
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<parameter name="PCORE_NUM_OF_RX_LANES" value="4" />
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<parameter name="PCORE_NUM_OF_TX_LANES" value="4" />
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</module>
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<module name="sys_clk" kind="clock_source" version="15.0" enabled="1">
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<parameter name="clockFrequency" value="100000000" />
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<parameter name="clockFrequencyKnown" value="true" />
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@ -818,8 +841,8 @@
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<parameter name="resetSynchronousEdges" value="NONE" />
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</module>
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<module name="sys_cpu" kind="altera_nios2_gen2" version="15.0" enabled="1">
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<parameter name="AUTO_CLK_CLOCK_DOMAIN" value="1" />
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<parameter name="AUTO_CLK_RESET_DOMAIN" value="1" />
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<parameter name="AUTO_CLK_CLOCK_DOMAIN" value="2" />
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<parameter name="AUTO_CLK_RESET_DOMAIN" value="2" />
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<parameter name="AUTO_DEVICE" value="10AX115S3F45I2SGE2" />
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<parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
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<parameter name="bht_ramBlockType" value="Automatic" />
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@ -837,7 +860,7 @@
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<parameter name="dataAddrWidth" value="32" />
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<parameter name="dataMasterHighPerformanceAddrWidth" value="1" />
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<parameter name="dataMasterHighPerformanceMapParam" value="" />
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<parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='sys_int_mem.s1' start='0x0' end='0x28000' /><slave name='axi_ad9144_core.s_axi' start='0x40000' end='0x50000' /><slave name='axi_ad9680_core.s_axi' start='0x50000' end='0x60000' /><slave name='axi_ad9144_dma.s_axi' start='0x60000' end='0x64000' /><slave name='axi_ad9680_dma.s_axi' start='0x64000' end='0x68000' /><slave name='sys_cpu.debug_mem_slave' start='0x6A800' end='0x6B000' /><slave name='sys_ethernet.control_port' start='0x6B000' end='0x6B400' /><slave name='sys_spi.spi_control_port' start='0x6B400' end='0x6B420' /><slave name='sys_timer.s1' start='0x6B420' end='0x6B440' /><slave name='sys_ethernet_dma_tx.descriptor_slave' start='0x6B440' end='0x6B460' /><slave name='sys_ethernet_dma_rx.descriptor_slave' start='0x6B460' end='0x6B480' /><slave name='sys_ethernet_dma_rx.csr' start='0x6B480' end='0x6B4A0' /><slave name='sys_ethernet_dma_tx.csr' start='0x6B4A0' end='0x6B4C0' /><slave name='sys_gpio.s1' start='0x6B4C0' end='0x6B4D0' /><slave name='sys_gpio_bd.s1' start='0x6B4D0' end='0x6B4E0' /><slave name='sys_ethernet_dma_rx.response' start='0x6B4E0' end='0x6B4E8' /><slave name='sys_id.control_slave' start='0x6B4E8' end='0x6B4F0' /><slave name='sys_uart.avalon_jtag_slave' start='0x6B4F0' end='0x6B4F8' /><slave name='sys_ddr3_cntrl.ctrl_amm_0' start='0x80000000' end='0x100000000' /></address-map>]]></parameter>
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<parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='sys_int_mem.s1' start='0x0' end='0x28000' /><slave name='axi_jesd_xcvr.s_axi' start='0x40000' end='0x50000' /><slave name='axi_ad9144_core.s_axi' start='0x50000' end='0x60000' /><slave name='axi_ad9680_core.s_axi' start='0x60000' end='0x70000' /><slave name='axi_ad9144_dma.s_axi' start='0x70000' end='0x74000' /><slave name='axi_ad9680_dma.s_axi' start='0x74000' end='0x78000' /><slave name='sys_cpu.debug_mem_slave' start='0x7A800' end='0x7B000' /><slave name='sys_ethernet.control_port' start='0x7B000' end='0x7B400' /><slave name='sys_spi.spi_control_port' start='0x7B400' end='0x7B420' /><slave name='sys_timer.s1' start='0x7B420' end='0x7B440' /><slave name='sys_ethernet_dma_tx.descriptor_slave' start='0x7B440' end='0x7B460' /><slave name='sys_ethernet_dma_rx.descriptor_slave' start='0x7B460' end='0x7B480' /><slave name='sys_ethernet_dma_rx.csr' start='0x7B480' end='0x7B4A0' /><slave name='sys_ethernet_dma_tx.csr' start='0x7B4A0' end='0x7B4C0' /><slave name='sys_gpio.s1' start='0x7B4C0' end='0x7B4D0' /><slave name='sys_gpio_bd.s1' start='0x7B4D0' end='0x7B4E0' /><slave name='sys_ethernet_dma_rx.response' start='0x7B4E0' end='0x7B4E8' /><slave name='sys_id.control_slave' start='0x7B4E8' end='0x7B4F0' /><slave name='sys_uart.avalon_jtag_slave' start='0x7B4F0' end='0x7B4F8' /><slave name='sys_ddr3_cntrl.ctrl_amm_0' start='0x80000000' end='0x100000000' /></address-map>]]></parameter>
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<parameter name="data_master_high_performance_paddr_base" value="0" />
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<parameter name="data_master_high_performance_paddr_size" value="0" />
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<parameter name="data_master_paddr_base" value="0" />
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@ -876,7 +899,7 @@
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<parameter name="icache_tagramBlockType" value="Automatic" />
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<parameter name="impl" value="Fast" />
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<parameter name="instAddrWidth" value="32" />
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<parameter name="instSlaveMapParam"><![CDATA[<address-map><slave name='sys_int_mem.s1' start='0x0' end='0x28000' /><slave name='sys_cpu.debug_mem_slave' start='0x6A800' end='0x6B000' /><slave name='sys_ddr3_cntrl.ctrl_amm_0' start='0x80000000' end='0x100000000' /></address-map>]]></parameter>
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<parameter name="instSlaveMapParam"><![CDATA[<address-map><slave name='sys_int_mem.s1' start='0x0' end='0x28000' /><slave name='sys_cpu.debug_mem_slave' start='0x7A800' end='0x7B000' /><slave name='sys_ddr3_cntrl.ctrl_amm_0' start='0x80000000' end='0x100000000' /></address-map>]]></parameter>
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<parameter name="instructionMasterHighPerformanceAddrWidth" value="1" />
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<parameter name="instructionMasterHighPerformanceMapParam" value="" />
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<parameter name="instruction_master_high_performance_paddr_base" value="0" />
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@ -958,7 +981,7 @@
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<parameter name="setting_usedesignware" value="false" />
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<parameter name="shift_rot_impl" value="0" />
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<parameter name="tightlyCoupledDataMaster0AddrWidth" value="19" />
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<parameter name="tightlyCoupledDataMaster0MapParam"><![CDATA[<address-map><slave name='sys_tcm_mem.s1' start='0x69000' end='0x6A000' /></address-map>]]></parameter>
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<parameter name="tightlyCoupledDataMaster0MapParam"><![CDATA[<address-map><slave name='sys_tcm_mem.s1' start='0x79000' end='0x7A000' /></address-map>]]></parameter>
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<parameter name="tightlyCoupledDataMaster1AddrWidth" value="1" />
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<parameter name="tightlyCoupledDataMaster1MapParam" value="" />
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<parameter name="tightlyCoupledDataMaster2AddrWidth" value="1" />
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@ -966,7 +989,7 @@
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<parameter name="tightlyCoupledDataMaster3AddrWidth" value="1" />
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<parameter name="tightlyCoupledDataMaster3MapParam" value="" />
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<parameter name="tightlyCoupledInstructionMaster0AddrWidth" value="19" />
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<parameter name="tightlyCoupledInstructionMaster0MapParam"><![CDATA[<address-map><slave name='sys_tcm_mem.s1' start='0x69000' end='0x6A000' /></address-map>]]></parameter>
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<parameter name="tightlyCoupledInstructionMaster0MapParam"><![CDATA[<address-map><slave name='sys_tcm_mem.s1' start='0x79000' end='0x7A000' /></address-map>]]></parameter>
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<parameter name="tightlyCoupledInstructionMaster1AddrWidth" value="1" />
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<parameter name="tightlyCoupledInstructionMaster1MapParam" value="" />
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<parameter name="tightlyCoupledInstructionMaster2AddrWidth" value="1" />
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@ -1753,9 +1776,9 @@
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<parameter name="AUTO_DEVICE_FAMILY" value="Arria 10" />
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<parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
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<parameter name="AUTO_MM_READ_ADDRESS_MAP" value="" />
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<parameter name="AUTO_MM_READ_ADDRESS_WIDTH" value="" />
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<parameter name="AUTO_MM_READ_ADDRESS_WIDTH" value="AddressWidth = -1" />
|
||||
<parameter name="AUTO_MM_WRITE_ADDRESS_MAP"><![CDATA[<address-map><slave name='sys_ddr3_cntrl.ctrl_amm_0' start='0x80000000' end='0x100000000' /></address-map>]]></parameter>
|
||||
<parameter name="AUTO_MM_WRITE_ADDRESS_WIDTH">com.altera.entityinterfaces.moduleext.AddressWidthType@65c0d72e</parameter>
|
||||
<parameter name="AUTO_MM_WRITE_ADDRESS_WIDTH" value="AddressWidth = 32" />
|
||||
<parameter name="BURST_ENABLE" value="1" />
|
||||
<parameter name="BURST_WRAPPING_SUPPORT" value="0" />
|
||||
<parameter name="CHANNEL_ENABLE" value="0" />
|
||||
|
|
@ -1785,9 +1808,9 @@
|
|||
<parameter name="AUTO_DEVICE_FAMILY" value="Arria 10" />
|
||||
<parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
|
||||
<parameter name="AUTO_MM_READ_ADDRESS_MAP"><![CDATA[<address-map><slave name='sys_ddr3_cntrl.ctrl_amm_0' start='0x80000000' end='0x100000000' /></address-map>]]></parameter>
|
||||
<parameter name="AUTO_MM_READ_ADDRESS_WIDTH">com.altera.entityinterfaces.moduleext.AddressWidthType@346e210f</parameter>
|
||||
<parameter name="AUTO_MM_READ_ADDRESS_WIDTH" value="AddressWidth = 32" />
|
||||
<parameter name="AUTO_MM_WRITE_ADDRESS_MAP" value="" />
|
||||
<parameter name="AUTO_MM_WRITE_ADDRESS_WIDTH" value="" />
|
||||
<parameter name="AUTO_MM_WRITE_ADDRESS_WIDTH" value="AddressWidth = -1" />
|
||||
<parameter name="BURST_ENABLE" value="1" />
|
||||
<parameter name="BURST_WRAPPING_SUPPORT" value="0" />
|
||||
<parameter name="CHANNEL_ENABLE" value="0" />
|
||||
|
|
@ -2013,17 +2036,6 @@
|
|||
<parameter name="set_user_identifier" value="0" />
|
||||
<parameter name="wrapper_opt" value="base_phy" />
|
||||
</module>
|
||||
<module
|
||||
name="sys_xcvr_rst"
|
||||
kind="altera_reset_bridge"
|
||||
version="15.0"
|
||||
enabled="1">
|
||||
<parameter name="ACTIVE_LOW_RESET" value="0" />
|
||||
<parameter name="AUTO_CLK_CLOCK_RATE" value="100000000" />
|
||||
<parameter name="NUM_RESET_OUTPUTS" value="1" />
|
||||
<parameter name="SYNCHRONOUS_EDGES" value="deassert" />
|
||||
<parameter name="USE_RESET_REQUEST" value="0" />
|
||||
</module>
|
||||
<module
|
||||
name="sys_xcvr_rstcntrl"
|
||||
kind="altera_xcvr_reset_control"
|
||||
|
|
@ -2725,7 +2737,7 @@
|
|||
start="sys_cpu.data_master"
|
||||
end="sys_uart.avalon_jtag_slave">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
<parameter name="baseAddress" value="0x0006b4f0" />
|
||||
<parameter name="baseAddress" value="0x0007b4f0" />
|
||||
<parameter name="defaultConnection" value="false" />
|
||||
</connection>
|
||||
<connection
|
||||
|
|
@ -2734,7 +2746,7 @@
|
|||
start="sys_cpu.data_master"
|
||||
end="sys_ethernet.control_port">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
<parameter name="baseAddress" value="0x0006b000" />
|
||||
<parameter name="baseAddress" value="0x0007b000" />
|
||||
<parameter name="defaultConnection" value="false" />
|
||||
</connection>
|
||||
<connection
|
||||
|
|
@ -2743,7 +2755,7 @@
|
|||
start="sys_cpu.data_master"
|
||||
end="sys_id.control_slave">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
<parameter name="baseAddress" value="0x0006b4e8" />
|
||||
<parameter name="baseAddress" value="0x0007b4e8" />
|
||||
<parameter name="defaultConnection" value="false" />
|
||||
</connection>
|
||||
<connection
|
||||
|
|
@ -2752,7 +2764,7 @@
|
|||
start="sys_cpu.data_master"
|
||||
end="sys_ethernet_dma_tx.csr">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
<parameter name="baseAddress" value="0x0006b4a0" />
|
||||
<parameter name="baseAddress" value="0x0007b4a0" />
|
||||
<parameter name="defaultConnection" value="false" />
|
||||
</connection>
|
||||
<connection
|
||||
|
|
@ -2761,7 +2773,7 @@
|
|||
start="sys_cpu.data_master"
|
||||
end="sys_ethernet_dma_rx.csr">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
<parameter name="baseAddress" value="0x0006b480" />
|
||||
<parameter name="baseAddress" value="0x0007b480" />
|
||||
<parameter name="defaultConnection" value="false" />
|
||||
</connection>
|
||||
<connection
|
||||
|
|
@ -2779,7 +2791,7 @@
|
|||
start="sys_cpu.data_master"
|
||||
end="sys_cpu.debug_mem_slave">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
<parameter name="baseAddress" value="0x0006a800" />
|
||||
<parameter name="baseAddress" value="0x0007a800" />
|
||||
<parameter name="defaultConnection" value="false" />
|
||||
</connection>
|
||||
<connection
|
||||
|
|
@ -2788,7 +2800,7 @@
|
|||
start="sys_cpu.data_master"
|
||||
end="sys_ethernet_dma_rx.descriptor_slave">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
<parameter name="baseAddress" value="0x0006b460" />
|
||||
<parameter name="baseAddress" value="0x0007b460" />
|
||||
<parameter name="defaultConnection" value="false" />
|
||||
</connection>
|
||||
<connection
|
||||
|
|
@ -2797,7 +2809,7 @@
|
|||
start="sys_cpu.data_master"
|
||||
end="sys_ethernet_dma_tx.descriptor_slave">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
<parameter name="baseAddress" value="0x0006b440" />
|
||||
<parameter name="baseAddress" value="0x0007b440" />
|
||||
<parameter name="defaultConnection" value="false" />
|
||||
</connection>
|
||||
<connection
|
||||
|
|
@ -2806,7 +2818,7 @@
|
|||
start="sys_cpu.data_master"
|
||||
end="sys_ethernet_dma_rx.response">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
<parameter name="baseAddress" value="0x0006b4e0" />
|
||||
<parameter name="baseAddress" value="0x0007b4e0" />
|
||||
<parameter name="defaultConnection" value="false" />
|
||||
</connection>
|
||||
<connection
|
||||
|
|
@ -2824,7 +2836,7 @@
|
|||
start="sys_cpu.data_master"
|
||||
end="sys_gpio_bd.s1">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
<parameter name="baseAddress" value="0x0006b4d0" />
|
||||
<parameter name="baseAddress" value="0x0007b4d0" />
|
||||
<parameter name="defaultConnection" value="false" />
|
||||
</connection>
|
||||
<connection
|
||||
|
|
@ -2833,7 +2845,7 @@
|
|||
start="sys_cpu.data_master"
|
||||
end="sys_timer.s1">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
<parameter name="baseAddress" value="0x0006b420" />
|
||||
<parameter name="baseAddress" value="0x0007b420" />
|
||||
<parameter name="defaultConnection" value="false" />
|
||||
</connection>
|
||||
<connection
|
||||
|
|
@ -2842,7 +2854,7 @@
|
|||
start="sys_cpu.data_master"
|
||||
end="sys_gpio.s1">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
<parameter name="baseAddress" value="0x0006b4c0" />
|
||||
<parameter name="baseAddress" value="0x0007b4c0" />
|
||||
<parameter name="defaultConnection" value="false" />
|
||||
</connection>
|
||||
<connection
|
||||
|
|
@ -2851,7 +2863,7 @@
|
|||
start="sys_cpu.data_master"
|
||||
end="axi_ad9680_dma.s_axi">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
<parameter name="baseAddress" value="0x00064000" />
|
||||
<parameter name="baseAddress" value="0x00074000" />
|
||||
<parameter name="defaultConnection" value="false" />
|
||||
</connection>
|
||||
<connection
|
||||
|
|
@ -2860,7 +2872,7 @@
|
|||
start="sys_cpu.data_master"
|
||||
end="axi_ad9144_dma.s_axi">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
<parameter name="baseAddress" value="0x00060000" />
|
||||
<parameter name="baseAddress" value="0x00070000" />
|
||||
<parameter name="defaultConnection" value="false" />
|
||||
</connection>
|
||||
<connection
|
||||
|
|
@ -2869,7 +2881,7 @@
|
|||
start="sys_cpu.data_master"
|
||||
end="axi_ad9680_core.s_axi">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
<parameter name="baseAddress" value="0x00050000" />
|
||||
<parameter name="baseAddress" value="0x00060000" />
|
||||
<parameter name="defaultConnection" value="false" />
|
||||
</connection>
|
||||
<connection
|
||||
|
|
@ -2878,6 +2890,15 @@
|
|||
start="sys_cpu.data_master"
|
||||
end="axi_ad9144_core.s_axi">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
<parameter name="baseAddress" value="0x00050000" />
|
||||
<parameter name="defaultConnection" value="false" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="avalon"
|
||||
version="15.0"
|
||||
start="sys_cpu.data_master"
|
||||
end="axi_jesd_xcvr.s_axi">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
<parameter name="baseAddress" value="0x00040000" />
|
||||
<parameter name="defaultConnection" value="false" />
|
||||
</connection>
|
||||
|
|
@ -2887,7 +2908,7 @@
|
|||
start="sys_cpu.data_master"
|
||||
end="sys_spi.spi_control_port">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
<parameter name="baseAddress" value="0x0006b400" />
|
||||
<parameter name="baseAddress" value="0x0007b400" />
|
||||
<parameter name="defaultConnection" value="false" />
|
||||
</connection>
|
||||
<connection
|
||||
|
|
@ -2905,7 +2926,7 @@
|
|||
start="sys_cpu.instruction_master"
|
||||
end="sys_cpu.debug_mem_slave">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
<parameter name="baseAddress" value="0x0006a800" />
|
||||
<parameter name="baseAddress" value="0x0007a800" />
|
||||
<parameter name="defaultConnection" value="false" />
|
||||
</connection>
|
||||
<connection
|
||||
|
|
@ -2959,7 +2980,7 @@
|
|||
start="sys_cpu.tightly_coupled_data_master_0"
|
||||
end="sys_tcm_mem.s1">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
<parameter name="baseAddress" value="0x00069000" />
|
||||
<parameter name="baseAddress" value="0x00079000" />
|
||||
<parameter name="defaultConnection" value="false" />
|
||||
</connection>
|
||||
<connection
|
||||
|
|
@ -2968,7 +2989,7 @@
|
|||
start="sys_cpu.tightly_coupled_instruction_master_0"
|
||||
end="sys_tcm_mem.s1">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
<parameter name="baseAddress" value="0x00069000" />
|
||||
<parameter name="baseAddress" value="0x00079000" />
|
||||
<parameter name="defaultConnection" value="false" />
|
||||
</connection>
|
||||
<connection
|
||||
|
|
@ -3008,11 +3029,6 @@
|
|||
<connection kind="clock" version="15.0" start="sys_clk.clk" end="sys_gpio_bd.clk" />
|
||||
<connection kind="clock" version="15.0" start="sys_clk.clk" end="sys_gpio.clk" />
|
||||
<connection kind="clock" version="15.0" start="sys_clk.clk" end="sys_spi.clk" />
|
||||
<connection
|
||||
kind="clock"
|
||||
version="15.0"
|
||||
start="sys_clk.clk"
|
||||
end="sys_xcvr_rst.clk" />
|
||||
<connection
|
||||
kind="clock"
|
||||
version="15.0"
|
||||
|
|
@ -3098,6 +3114,11 @@
|
|||
version="15.0"
|
||||
start="sys_clk.clk"
|
||||
end="axi_ad9144_core.s_axi_clock" />
|
||||
<connection
|
||||
kind="clock"
|
||||
version="15.0"
|
||||
start="sys_clk.clk"
|
||||
end="axi_jesd_xcvr.s_axi_clock" />
|
||||
<connection
|
||||
kind="clock"
|
||||
version="15.0"
|
||||
|
|
@ -3143,6 +3164,11 @@
|
|||
version="15.0"
|
||||
start="sys_xcvr_rx_clk.outclk0"
|
||||
end="util_jesd_align.if_rx_clk" />
|
||||
<connection
|
||||
kind="clock"
|
||||
version="15.0"
|
||||
start="sys_xcvr_rx_clk.outclk0"
|
||||
end="axi_jesd_xcvr.if_rx_clk" />
|
||||
<connection
|
||||
kind="clock"
|
||||
version="15.0"
|
||||
|
|
@ -3153,6 +3179,11 @@
|
|||
version="15.0"
|
||||
start="sys_xcvr_tx_clk.outclk0"
|
||||
end="util_jesd_xmit.if_tx_clk" />
|
||||
<connection
|
||||
kind="clock"
|
||||
version="15.0"
|
||||
start="sys_xcvr_tx_clk.outclk0"
|
||||
end="axi_jesd_xcvr.if_tx_clk" />
|
||||
<connection
|
||||
kind="clock"
|
||||
version="15.0"
|
||||
|
|
@ -3361,6 +3392,39 @@
|
|||
<parameter name="startPortLSB" value="0" />
|
||||
<parameter name="width" value="0" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="conduit"
|
||||
version="15.0"
|
||||
start="axi_jesd_xcvr.if_rx_ip_sync"
|
||||
end="sys_xcvr.rx_dev_sync_n">
|
||||
<parameter name="endPort" value="" />
|
||||
<parameter name="endPortLSB" value="0" />
|
||||
<parameter name="startPort" value="" />
|
||||
<parameter name="startPortLSB" value="0" />
|
||||
<parameter name="width" value="0" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="conduit"
|
||||
version="15.0"
|
||||
start="axi_jesd_xcvr.if_rx_status"
|
||||
end="sys_xcvr_rstcntrl.rx_ready">
|
||||
<parameter name="endPort" value="" />
|
||||
<parameter name="endPortLSB" value="0" />
|
||||
<parameter name="startPort" value="" />
|
||||
<parameter name="startPortLSB" value="0" />
|
||||
<parameter name="width" value="0" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="conduit"
|
||||
version="15.0"
|
||||
start="axi_jesd_xcvr.if_tx_ip_sync"
|
||||
end="sys_xcvr.sync_n">
|
||||
<parameter name="endPort" value="" />
|
||||
<parameter name="endPortLSB" value="0" />
|
||||
<parameter name="startPort" value="" />
|
||||
<parameter name="startPortLSB" value="0" />
|
||||
<parameter name="width" value="0" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="conduit"
|
||||
version="15.0"
|
||||
|
|
@ -3438,6 +3502,17 @@
|
|||
<parameter name="startPortLSB" value="0" />
|
||||
<parameter name="width" value="0" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="conduit"
|
||||
version="15.0"
|
||||
start="sys_xcvr.rx_sysref"
|
||||
end="axi_jesd_xcvr.if_rx_sysref">
|
||||
<parameter name="endPort" value="" />
|
||||
<parameter name="endPortLSB" value="0" />
|
||||
<parameter name="startPort" value="" />
|
||||
<parameter name="startPortLSB" value="0" />
|
||||
<parameter name="width" value="0" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="conduit"
|
||||
version="15.0"
|
||||
|
|
@ -3482,6 +3557,28 @@
|
|||
<parameter name="startPortLSB" value="0" />
|
||||
<parameter name="width" value="0" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="conduit"
|
||||
version="15.0"
|
||||
start="sys_xcvr_rstcntrl.tx_ready"
|
||||
end="axi_jesd_xcvr.if_tx_status">
|
||||
<parameter name="endPort" value="" />
|
||||
<parameter name="endPortLSB" value="0" />
|
||||
<parameter name="startPort" value="" />
|
||||
<parameter name="startPortLSB" value="0" />
|
||||
<parameter name="width" value="0" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="conduit"
|
||||
version="15.0"
|
||||
start="sys_xcvr.tx_sysref"
|
||||
end="axi_jesd_xcvr.if_tx_sysref">
|
||||
<parameter name="endPort" value="" />
|
||||
<parameter name="endPortLSB" value="0" />
|
||||
<parameter name="startPort" value="" />
|
||||
<parameter name="startPortLSB" value="0" />
|
||||
<parameter name="width" value="0" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="hssi_serial_clock"
|
||||
version="15.0"
|
||||
|
|
@ -3666,6 +3763,11 @@
|
|||
version="15.0"
|
||||
start="sys_clk.clk_reset"
|
||||
end="axi_ad9144_core.s_axi_reset" />
|
||||
<connection
|
||||
kind="reset"
|
||||
version="15.0"
|
||||
start="sys_clk.clk_reset"
|
||||
end="axi_jesd_xcvr.s_axi_reset" />
|
||||
<connection
|
||||
kind="reset"
|
||||
version="15.0"
|
||||
|
|
@ -3684,37 +3786,37 @@
|
|||
<connection
|
||||
kind="reset"
|
||||
version="15.0"
|
||||
start="sys_xcvr_rst.out_reset"
|
||||
end="sys_xcvr_tx_ref_clk.clk_in_reset" />
|
||||
<connection
|
||||
kind="reset"
|
||||
version="15.0"
|
||||
start="sys_xcvr_rst.out_reset"
|
||||
start="axi_jesd_xcvr.if_rst"
|
||||
end="sys_xcvr_rx_ref_clk.clk_in_reset" />
|
||||
<connection
|
||||
kind="reset"
|
||||
version="15.0"
|
||||
start="sys_xcvr_rst.out_reset"
|
||||
end="sys_xcvr_tx_clk.reset" />
|
||||
start="axi_jesd_xcvr.if_rst"
|
||||
end="sys_xcvr_tx_ref_clk.clk_in_reset" />
|
||||
<connection
|
||||
kind="reset"
|
||||
version="15.0"
|
||||
start="sys_xcvr_rst.out_reset"
|
||||
end="sys_xcvr_rx_clk.reset" />
|
||||
<connection
|
||||
kind="reset"
|
||||
version="15.0"
|
||||
start="sys_xcvr_rst.out_reset"
|
||||
start="axi_jesd_xcvr.if_rst"
|
||||
end="sys_xcvr_rstcntrl.reset" />
|
||||
<connection
|
||||
kind="reset"
|
||||
version="15.0"
|
||||
start="sys_xcvr_rst.out_reset"
|
||||
start="axi_jesd_xcvr.if_rst"
|
||||
end="sys_xcvr_rx_clk.reset" />
|
||||
<connection
|
||||
kind="reset"
|
||||
version="15.0"
|
||||
start="axi_jesd_xcvr.if_rst"
|
||||
end="sys_xcvr_tx_clk.reset" />
|
||||
<connection
|
||||
kind="reset"
|
||||
version="15.0"
|
||||
start="axi_jesd_xcvr.if_rx_rst"
|
||||
end="sys_xcvr.rxlink_rst_n" />
|
||||
<connection
|
||||
kind="reset"
|
||||
version="15.0"
|
||||
start="sys_xcvr_rst.out_reset"
|
||||
start="axi_jesd_xcvr.if_tx_rst"
|
||||
end="sys_xcvr.txlink_rst_n" />
|
||||
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="FIFO" />
|
||||
<interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="false" />
|
||||
|
|
|
|||
|
|
@ -8,6 +8,5 @@ create_clock -period "2.000 ns" -name tx_ref_clk_500mhz [get_ports {tx_ref_c
|
|||
derive_pll_clocks
|
||||
derive_clock_uncertainty
|
||||
|
||||
set_false_path -from [get_registers *dev_sync_n*] -to [get_registers *up_*_sync_m1*]
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -181,15 +181,6 @@ module system_top (
|
|||
inout spi_sdio;
|
||||
output spi_dir;
|
||||
|
||||
// internal registers
|
||||
|
||||
reg up_tx_sync_m1 = 'd0;
|
||||
reg up_tx_sync_m2 = 'd0;
|
||||
reg up_tx_sync = 'd0;
|
||||
reg up_rx_sync_m1 = 'd0;
|
||||
reg up_rx_sync_m2 = 'd0;
|
||||
reg up_rx_sync = 'd0;
|
||||
|
||||
// internal signals
|
||||
|
||||
wire eth_mdio_i;
|
||||
|
|
@ -200,8 +191,6 @@ module system_top (
|
|||
wire spi_miso_s;
|
||||
wire spi_mosi_s;
|
||||
wire [ 7:0] spi_csn_s;
|
||||
wire [ 3:0] xcvr_rx_ready;
|
||||
wire [ 3:0] xcvr_tx_ready;
|
||||
|
||||
// daq2
|
||||
|
||||
|
|
@ -217,34 +206,10 @@ module system_top (
|
|||
.spi_sdio (spi_sdio),
|
||||
.spi_dir (spi_dir));
|
||||
|
||||
always @(posedge sys_clk or negedge sys_resetn) begin
|
||||
if (sys_resetn == 1'b0) begin
|
||||
up_tx_sync_m1 <= 1'd0;
|
||||
up_tx_sync_m2 <= 1'd0;
|
||||
up_tx_sync <= 1'd0;
|
||||
up_rx_sync_m1 <= 1'd0;
|
||||
up_rx_sync_m2 <= 1'd0;
|
||||
up_rx_sync <= 1'd0;
|
||||
end else begin
|
||||
up_tx_sync_m1 <= tx_sync;
|
||||
up_tx_sync_m2 <= up_tx_sync_m1;
|
||||
up_tx_sync <= up_tx_sync_m2;
|
||||
up_rx_sync_m1 <= rx_sync;
|
||||
up_rx_sync_m2 <= up_rx_sync_m1;
|
||||
up_rx_sync <= up_rx_sync_m2;
|
||||
end
|
||||
end
|
||||
|
||||
assign gpio_i[63:60] = xcvr_tx_ready;
|
||||
assign gpio_i[59:56] = xcvr_rx_ready;
|
||||
assign gpio_i[55:55] = up_tx_sync;
|
||||
assign gpio_i[54:54] = up_rx_sync;
|
||||
assign gpio_i[53:52] = 2'd0;
|
||||
assign gpio_i[51:51] = gpio_o[51];
|
||||
assign gpio_i[50:44] = 7'd0;
|
||||
assign gpio_i[63:44] = gpio_o[63:44];
|
||||
assign gpio_i[43:43] = trig;
|
||||
assign gpio_i[39:39] = 1'd0;
|
||||
assign gpio_i[37:37] = 1'd0;
|
||||
assign gpio_i[39:39] = gpio_o[39:39];
|
||||
assign gpio_i[37:37] = gpio_o[37:37];
|
||||
|
||||
ad_iobuf #(.DATA_WIDTH(9)) i_iobuf (
|
||||
.dio_t ({3'h0, 1'h0, 5'h1f}),
|
||||
|
|
@ -265,11 +230,7 @@ module system_top (
|
|||
assign eth_mdio_i = eth_mdio;
|
||||
assign eth_mdio = (eth_mdio_t == 1'b1) ? 1'bz : eth_mdio_o;
|
||||
|
||||
assign gpio_i[31] = 1'd0;
|
||||
assign gpio_i[30] = 1'd0;
|
||||
assign gpio_i[29] = 1'd0;
|
||||
assign gpio_i[28] = 1'd0;
|
||||
assign gpio_i[27] = 1'd0;
|
||||
assign gpio_i[31:27] = gpio_o[31:27];
|
||||
|
||||
ad_iobuf #(.DATA_WIDTH(27)) i_iobuf_bd (
|
||||
.dio_t ({11'h7ff, 16'h0}),
|
||||
|
|
@ -278,6 +239,10 @@ module system_top (
|
|||
.dio_p (gpio_bd));
|
||||
|
||||
system_bd i_system_bd (
|
||||
.rx_data_rx_serial_data (rx_data),
|
||||
.rx_ref_clk_clk (rx_ref_clk),
|
||||
.rx_sync_rx_sync (rx_sync),
|
||||
.rx_sysref_rx_ext_sysref (rx_sysref),
|
||||
.sys_clk_clk (sys_clk),
|
||||
.sys_ddr3_cntrl_mem_mem_ck (ddr3_clk_p),
|
||||
.sys_ddr3_cntrl_mem_mem_ck_n (ddr3_clk_n),
|
||||
|
|
@ -312,18 +277,10 @@ module system_top (
|
|||
.sys_spi_MOSI (spi_mosi_s),
|
||||
.sys_spi_SCLK (spi_clk),
|
||||
.sys_spi_SS_n (spi_csn_s),
|
||||
.sys_xcvr_reset_reset (gpio_o[51]),
|
||||
.sys_xcvr_rstcntrl_rx_ready_rx_ready (xcvr_rx_ready),
|
||||
.sys_xcvr_rstcntrl_tx_ready_tx_ready (xcvr_tx_ready),
|
||||
.sys_xcvr_rx_ref_clk_clk (rx_ref_clk),
|
||||
.sys_xcvr_rx_sync_n_export (rx_sync),
|
||||
.sys_xcvr_rx_sysref_export (rx_sysref),
|
||||
.sys_xcvr_rxd_rx_serial_data (rx_data),
|
||||
.sys_xcvr_tx_ref_clk_clk (tx_ref_clk),
|
||||
.sys_xcvr_tx_sync_n_export (tx_sync),
|
||||
.sys_xcvr_tx_sysref_export (tx_sysref),
|
||||
.sys_xcvr_txd_tx_serial_data (tx_data));
|
||||
|
||||
.tx_data_tx_serial_data (tx_data),
|
||||
.tx_ref_clk_clk (tx_ref_clk),
|
||||
.tx_sync_tx_sync (tx_sync),
|
||||
.tx_sysref_tx_ext_sysref (tx_sysref));
|
||||
|
||||
endmodule
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue