Update ad_data_in &_out (#1060)
* ad_data_in: Add new logic and explanations * Added parameters IDELAY_TYPE, DELAY_FORMAT, US_DELAY_TYPE to be used with the IDELAY instances * Added explanations * Added option to bypass IDELAY if it's not instantiated, regardless of the FPGA_TECHNOLOGY parameter * Determined a part of the logic for EN_VTC (by the UG) but not for all modes since we don't have use cases for them * Changed logic when adding ODELAY: now you must set IODELAY_ENABLE = 1 and FPGA_TECHNOLOGY != NONE if you want it * ad_data_out: * Updated ODDR parameter * Fixed issue with ODDR inputs D1, D2: D1 must be with _p and D2 with _n, according to the Xilinx template * Removed _ES1 from IODELAY_SIM_DEVICE * Added ODELAY for UltraScale * Before, there was no support for UltraScale/+, and the output data was completely disconnected from the ODDR * The support for this was requested in this issue, although as of now we don't have a design that uses it: https://github.com/analogdevicesinc/hdl/issues/917 * Added parameters ODELAY_TYPE, DELAY_FORMAT, US_DELAY_TYPE to be used with the ODELAY instances * Added explanations * Added option to bypass ODELAY if it's not instantiated, regardless of the FPGA_TECHNOLOGY parameter * Determined a part of the logic for the EN_VTC (by the UG) but not for all modes since we don't have use cases for them * Changed logic when adding ODELAY: now you must set IODELAY_ENABLE = 1 and FPGA_TECHNOLOGY != NONE if you want it --------- Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>main
imoldovan
GitHub
parent
cadb8e637d
commit
075ee05189
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@ -1,6 +1,6 @@
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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// Copyright 2014 - 2023 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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@ -39,6 +39,12 @@ module ad_data_in #(
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parameter SINGLE_ENDED = 0,
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parameter FPGA_TECHNOLOGY = 0,
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parameter IDDR_CLK_EDGE ="SAME_EDGE",
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// for 7 series devices
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parameter IDELAY_TYPE = "VAR_LOAD",
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// for ultrascale devices
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parameter DELAY_FORMAT = "COUNT",
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parameter US_DELAY_TYPE = "VAR_LOAD",
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// for all
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parameter IODELAY_ENABLE = 1,
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parameter IODELAY_CTRL = 0,
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parameter IODELAY_GROUP = "dev_if_delay_group",
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@ -74,20 +80,68 @@ module ad_data_in #(
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localparam ULTRASCALE = 2;
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localparam ULTRASCALE_PLUS = 3;
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localparam IODELAY_CTRL_ENABLED = (IODELAY_ENABLE == 1) ? IODELAY_CTRL : 0;
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// do not instantiate an IDELAYCTRL if no IDELAY is instantiated
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localparam IODELAY_CTRL_ENABLED = (IODELAY_ENABLE & IODELAY_CTRL);
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localparam IODELAY_CTRL_SIM_DEVICE = (FPGA_TECHNOLOGY == ULTRASCALE_PLUS) ? "ULTRASCALE" :
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(FPGA_TECHNOLOGY == ULTRASCALE) ? "ULTRASCALE" : "7SERIES";
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localparam IODELAY_FPGA_TECHNOLOGY = (IODELAY_ENABLE == 1) ? FPGA_TECHNOLOGY : NONE;
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localparam IODELAY_SIM_DEVICE = (FPGA_TECHNOLOGY == ULTRASCALE_PLUS) ? "ULTRASCALE_PLUS" :
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(FPGA_TECHNOLOGY == ULTRASCALE) ? "ULTRASCALE" : "7SERIES";
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/*
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* For 7 series, IDELAYCTRL is enabled ALWAYS, meaning in the following situations:
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* when IDELAY_TYPE = FIXED
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* when IDELAY_TYPE = VARIABLE
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* when IDELAY_TYPE = VAR_LOAD
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**/
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/*
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* For UltraScale/UltraScale+:
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* when DELAY_FORMAT = TIME:
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* IDELAYCTRL must be used
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* REFCLK_FREQUENCY must reflect the clock frequency of REF_CLK applied to
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the IDELAYCTRL component
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* DELAY_VALUE attribute represents an amount in ps
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* The total delay through the IDELAYE3 is the align delay + DELAY_VALUE
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* EN_VTC depends on DELAY_TYPE attribute:
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* when FIXED mode: EN_VTC = 1
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* It must be actively manipulated when the delay line is used in
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VARIABLE or VAR_LOAD mode
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(this section is NOT IMPLEMENTED! More details in UG571, DELAY_TYPE = VAR_LOAD mode and VARIABLE mode)
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* when DELAY_FORMAT = COUNT:
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* DO NOT use an IDELAYCTRL
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* REFCLK_FREQUENCY must be set to default frequency (300MHz)
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* Delay line represents an amount of taps (512 taps available)
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* CNTVALUEIN/OUT[8:0] values represent the amount of taps the delay line
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is set to
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* EN_VTC = 0
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**/
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// internal signals
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wire rx_data_ibuf_s;
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wire rx_data_idelay_s;
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wire [ 8:0] up_drdata_s;
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// internal registers
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reg en_vtc;
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// determine EN_VTC (VAR_LOAD and VARIABLE modes not implemented as in UG571)
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always @(posedge rx_clk) begin
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if (DELAY_FORMAT == "TIME") begin
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if (US_DELAY_TYPE == "FIXED") begin
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en_vtc <= 1'b1;
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end else begin // "VAR_LOAD", "VARIABLE"
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en_vtc <= ~up_dld;
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end
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end else begin // "COUNT"
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en_vtc <= 1'b0;
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end
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end
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// delay controller
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generate
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@ -106,6 +160,8 @@ module ad_data_in #(
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// receive data interface, ibuf -> idelay -> iddr
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// ibuf
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generate
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if (SINGLE_ENDED == 1) begin
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IBUF i_rx_data_ibuf (
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@ -119,16 +175,25 @@ module ad_data_in #(
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end
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endgenerate
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// bypass IDELAY
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generate
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if (IODELAY_ENABLE == 0) begin
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assign rx_data_idelay_s = rx_data_ibuf_s;
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assign up_drdata = 5'd0;
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end
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endgenerate
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// idelay
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generate
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if (IODELAY_FPGA_TECHNOLOGY == SEVEN_SERIES) begin
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if (FPGA_TECHNOLOGY == SEVEN_SERIES && IODELAY_ENABLE == 1) begin
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(* IODELAY_GROUP = IODELAY_GROUP *)
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IDELAYE2 #(
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.CINVCTRL_SEL ("FALSE"),
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.DELAY_SRC ("IDATAIN"),
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.HIGH_PERFORMANCE_MODE ("FALSE"),
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.IDELAY_TYPE ("VAR_LOAD"),
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.IDELAY_TYPE (IDELAY_TYPE),
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.IDELAY_VALUE (0),
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.REFCLK_FREQUENCY (REFCLK_FREQUENCY),
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.PIPE_SEL ("FALSE"),
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@ -150,15 +215,17 @@ module ad_data_in #(
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endgenerate
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generate
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if ((IODELAY_FPGA_TECHNOLOGY == ULTRASCALE) || (IODELAY_FPGA_TECHNOLOGY == ULTRASCALE_PLUS)) begin
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if ((FPGA_TECHNOLOGY == ULTRASCALE || FPGA_TECHNOLOGY == ULTRASCALE_PLUS)
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&& (IODELAY_ENABLE == 1)) begin
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assign up_drdata = up_drdata_s[8:4];
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(* IODELAY_GROUP = IODELAY_GROUP *)
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IDELAYE3 #(
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.SIM_DEVICE (IODELAY_SIM_DEVICE),
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.DELAY_SRC ("IDATAIN"),
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.DELAY_TYPE ("VAR_LOAD"),
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.DELAY_TYPE (US_DELAY_TYPE),
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.REFCLK_FREQUENCY (REFCLK_FREQUENCY),
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.DELAY_FORMAT ("COUNT")
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.DELAY_FORMAT (DELAY_FORMAT)
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) i_rx_data_idelay (
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.CASC_RETURN (1'b0),
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.CASC_IN (1'b0),
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@ -173,21 +240,14 @@ module ad_data_in #(
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.IDATAIN (rx_data_ibuf_s),
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.DATAOUT (rx_data_idelay_s),
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.RST (1'b0),
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.EN_VTC (~up_dld));
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end
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endgenerate
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generate
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if (IODELAY_FPGA_TECHNOLOGY == NONE) begin
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assign rx_data_idelay_s = rx_data_ibuf_s;
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assign up_drdata = 5'd0;
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.EN_VTC (en_vtc));
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end
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endgenerate
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// iddr
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generate
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if ((FPGA_TECHNOLOGY == ULTRASCALE) || (FPGA_TECHNOLOGY == ULTRASCALE_PLUS)) begin
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if (FPGA_TECHNOLOGY == ULTRASCALE || FPGA_TECHNOLOGY == ULTRASCALE_PLUS) begin
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IDDRE1 #(
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.DDR_CLK_EDGE (IDDR_CLK_EDGE)
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) i_rx_data_iddr (
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@ -1,6 +1,6 @@
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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// Copyright 2014 - 2023 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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@ -40,6 +40,12 @@ module ad_data_out #(
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parameter FPGA_TECHNOLOGY = 0,
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parameter SINGLE_ENDED = 0,
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parameter IDDR_CLK_EDGE ="SAME_EDGE",
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// for 7 series devices
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parameter ODELAY_TYPE = "VAR_LOAD",
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// for ultrascale devices
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parameter DELAY_FORMAT = "COUNT",
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parameter US_DELAY_TYPE = "VAR_LOAD",
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// for all
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parameter IODELAY_ENABLE = 0,
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parameter IODELAY_CTRL = 0,
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parameter IODELAY_GROUP = "dev_if_delay_group",
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@ -73,73 +79,134 @@ module ad_data_out #(
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localparam ULTRASCALE = 2;
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localparam ULTRASCALE_PLUS = 3;
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localparam IODELAY_CTRL_ENABLED = (IODELAY_ENABLE == 1) ? IODELAY_CTRL : 0;
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// do not instantiate an IDELAYCTRL if no ODELAY is instantiated
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localparam IODELAY_CTRL_ENABLED = (IODELAY_ENABLE & IODELAY_CTRL);
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localparam IODELAY_CTRL_SIM_DEVICE = (FPGA_TECHNOLOGY == ULTRASCALE_PLUS) ? "ULTRASCALE" :
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(FPGA_TECHNOLOGY == ULTRASCALE) ? "ULTRASCALE" : "7SERIES";
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localparam IODELAY_FPGA_TECHNOLOGY = (IODELAY_ENABLE == 1) ? FPGA_TECHNOLOGY : NONE;
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localparam IODELAY_SIM_DEVICE = (FPGA_TECHNOLOGY == ULTRASCALE_PLUS) ? "ULTRASCALE_PLUS_ES1" :
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localparam IODELAY_SIM_DEVICE = (FPGA_TECHNOLOGY == ULTRASCALE_PLUS) ? "ULTRASCALE_PLUS" :
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(FPGA_TECHNOLOGY == ULTRASCALE) ? "ULTRASCALE" : "7SERIES";
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/*
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* For 7 series, IDELAYCTRL is enabled ALWAYS, meaning in the following situations:
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* when ODELAY_TYPE = FIXED
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* when ODELAY_TYPE = VARIABLE
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* when ODELAY_TYPE = VAR_LOAD
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**/
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/*
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* For UltraScale/UltraScale+:
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* when DELAY_FORMAT = TIME:
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* IDELAYCTRL must be used
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* REFCLK_FREQUENCY must reflect the clock frequency of REF_CLK applied to
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the IDELAYCTRL component
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* DELAY_VALUE attribute represents an amount in ps
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* The total delay through the IDELAYE3 is the align delay + DELAY_VALUE
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* EN_VTC depends on DELAY_TYPE attribute:
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* when FIXED mode: EN_VTC = 1
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* It must be actively manipulated when the delay line is used in
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VARIABLE or VAR_LOAD mode
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(this section is NOT IMPLEMENTED! More details in UG571, DELAY_TYPE = VAR_LOAD mode and VARIABLE mode)
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* when DELAY_FORMAT = COUNT:
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* DO NOT use an IDELAYCTRL
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* REFCLK_FREQUENCY must be set to default frequency (300MHz)
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* Delay line represents an amount of taps (512 taps available)
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* CNTVALUEIN/OUT[8:0] values represent the amount of taps the delay line
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is set to
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* EN_VTC = 0
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**/
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// internal signals
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wire tx_data_oddr_s;
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wire tx_data_odelay_s;
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// internal registers
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reg en_vtc;
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// determine EN_VTC (VAR_LOAD and VARIABLE modes not implemented as in UG571)
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always @(posedge tx_clk) begin
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if (DELAY_FORMAT == "TIME") begin
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if (US_DELAY_TYPE == "FIXED") begin
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en_vtc <= 1'b1;
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end else begin // "VAR_LOAD", "VARIABLE"
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en_vtc <= ~up_dld;
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end
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end else begin // "COUNT"
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en_vtc <= 1'b0;
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end
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end
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// delay controller
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generate
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if (IODELAY_CTRL_ENABLED == 0) begin
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assign delay_locked = 1'b1;
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assign delay_locked = 1'b1;
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end else begin
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(* IODELAY_GROUP = IODELAY_GROUP *)
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IDELAYCTRL #(
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.SIM_DEVICE (IODELAY_CTRL_SIM_DEVICE)
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) i_delay_ctrl (
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.RST (delay_rst),
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.REFCLK (delay_clk),
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.RDY (delay_locked));
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(* IODELAY_GROUP = IODELAY_GROUP *)
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IDELAYCTRL #(
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.SIM_DEVICE (IODELAY_CTRL_SIM_DEVICE)
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) i_delay_ctrl (
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.RST (delay_rst),
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.REFCLK (delay_clk),
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.RDY (delay_locked));
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end
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endgenerate
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// bypass ODELAY
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generate
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if (IODELAY_ENABLE == 0) begin
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assign tx_data_odelay_s = tx_data_oddr_s;
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assign up_drdata = 5'd0;
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end
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endgenerate
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// transmit data interface, oddr -> odelay -> obuf
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// oddr
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generate
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if ((FPGA_TECHNOLOGY == ULTRASCALE) || (FPGA_TECHNOLOGY == ULTRASCALE_PLUS)) begin
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ODDRE1 i_tx_data_oddr (
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.SR (1'b0),
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.C (tx_clk),
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.D1 (tx_data_n),
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.D2 (tx_data_p),
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.Q (tx_data_oddr_s));
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ODDRE1 #(
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.SIM_DEVICE (IODELAY_SIM_DEVICE)
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) i_tx_data_oddr (
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.SR (1'b0),
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.C (tx_clk),
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.D1 (tx_data_p),
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.D2 (tx_data_n),
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.Q (tx_data_oddr_s));
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end
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endgenerate
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generate
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if (FPGA_TECHNOLOGY == SEVEN_SERIES) begin
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ODDR #(
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.DDR_CLK_EDGE (IDDR_CLK_EDGE)
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) i_tx_data_oddr (
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.CE (1'b1),
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.R (1'b0),
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.S (1'b0),
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.C (tx_clk),
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.D1 (tx_data_n),
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.D2 (tx_data_p),
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.Q (tx_data_oddr_s));
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ODDR #(
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.DDR_CLK_EDGE (IDDR_CLK_EDGE)
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) i_tx_data_oddr (
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.CE (1'b1),
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.R (1'b0),
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.S (1'b0),
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.C (tx_clk),
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.D1 (tx_data_p),
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.D2 (tx_data_n),
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.Q (tx_data_oddr_s));
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end
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endgenerate
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// odelay
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generate
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if (IODELAY_FPGA_TECHNOLOGY == SEVEN_SERIES) begin
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if (FPGA_TECHNOLOGY == SEVEN_SERIES && IODELAY_ENABLE == 1) begin
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(* IODELAY_GROUP = IODELAY_GROUP *)
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ODELAYE2 #(
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.CINVCTRL_SEL ("FALSE"),
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.DELAY_SRC ("ODATAIN"),
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.HIGH_PERFORMANCE_MODE ("FALSE"),
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.ODELAY_TYPE ("VAR_LOAD"),
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.ODELAY_TYPE (ODELAY_TYPE),
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.ODELAY_VALUE (0),
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.REFCLK_FREQUENCY (REFCLK_FREQUENCY),
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.PIPE_SEL ("FALSE"),
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@ -161,9 +228,34 @@ module ad_data_out #(
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endgenerate
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generate
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if (IODELAY_FPGA_TECHNOLOGY == NONE) begin
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assign up_drdata = 5'd0;
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assign tx_data_odelay_s = tx_data_oddr_s;
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if ((FPGA_TECHNOLOGY == ULTRASCALE_PLUS || FPGA_TECHNOLOGY == ULTRASCALE)
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&& (IODELAY_ENABLE == 1)) begin
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(* IODELAY_GROUP = IODELAY_GROUP *)
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ODELAYE3 #(
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.CASCADE ("NONE"),
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.DELAY_FORMAT (DELAY_FORMAT),
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.DELAY_TYPE (US_DELAY_TYPE),
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.DELAY_VALUE (0),
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.IS_CLK_INVERTED (1'b0),
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.IS_RST_INVERTED (1'b0),
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.REFCLK_FREQUENCY (REFCLK_FREQUENCY),
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.SIM_DEVICE (IODELAY_SIM_DEVICE),
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.UPDATE_MODE ("ASYNC")
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) i_tx_data_odelay (
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.CASC_RETURN (1'b0),
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.CASC_IN (1'b0),
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.CASC_OUT (),
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.CE (1'b0),
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.CLK (up_clk),
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.INC (1'b0),
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.LOAD (up_dld),
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.CNTVALUEIN (up_dwdata),
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.CNTVALUEOUT (up_drdata),
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.ODATAIN (tx_data_oddr_s),
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.DATAOUT (tx_data_odelay_s),
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.RST (1'b0),
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.EN_VTC (en_vtc));
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end
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endgenerate
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@ -171,15 +263,15 @@ module ad_data_out #(
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generate
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if (SINGLE_ENDED == 1) begin
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assign tx_data_out_n = 1'b0;
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OBUF i_tx_data_obuf (
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.I (tx_data_odelay_s),
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.O (tx_data_out_p));
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assign tx_data_out_n = 1'b0;
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OBUF i_tx_data_obuf (
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.I (tx_data_odelay_s),
|
||||
.O (tx_data_out_p));
|
||||
end else begin
|
||||
OBUFDS i_tx_data_obuf (
|
||||
.I (tx_data_odelay_s),
|
||||
.O (tx_data_out_p),
|
||||
.OB (tx_data_out_n));
|
||||
OBUFDS i_tx_data_obuf (
|
||||
.I (tx_data_odelay_s),
|
||||
.O (tx_data_out_p),
|
||||
.OB (tx_data_out_n));
|
||||
end
|
||||
endgenerate
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue