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ad_ip_jesd204_tpl_dac: Removed unused clk signal from framer module 

The framer module is purely combinational at this point and the clk signal
is unused.

This is a leftover of commit commit 5af80e79b3 ("ad_ip_jesd204_tpl_dac:
Drop extra pipeline stage from the framer").

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
main
Lars-Peter Clausen 2018-08-21 12:38:17 +02:00 committed by István Csomortáni
parent 870d09d44d
commit 07ca770607
2 changed files with 0 additions and 3 deletions
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1
library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_core.v
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@ -76,7 +76,6 @@ module ad_ip_jesd204_tpl_dac_core #(
.NUM_LANES (NUM_LANES),
.NUM_CHANNELS (NUM_CHANNELS)
) i_framer (
.clk (clk),
.link_data (link_data),
.dac_data (dac_data_s)
);

2
library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_framer.v
View File

@ -28,9 +28,7 @@ module ad_ip_jesd204_tpl_dac_framer #(
parameter NUM_CHANNELS = 4
) (
// jesd interface
// clk is (line-rate/40)
input clk,
output [NUM_LANES*32-1:0] link_data,
// dac interface