axi_adrv9001: Populate correct ratio of the SSI interface and user interface clocks

Depending on FPGA technology the physical layer uses different
deserialization factors and corresponding clock division factors to
divide the source synchronous interface clock. This must be
exposed to software so it can act on it while setting the DDS rate.

Xilinx CMOS clock ratio - 4
Xilinx LVDS clock ratio - 4
Intel  CMOS clock ratio - 1

library/axi_adrv9001/adrv9001_rx.v

@@ -64,6 +64,8 @@ module adrv9001_rx #(
   output      [7:0]       adc_data_strobe,
   output                  adc_valid,
 
+  output     [31:0]       adc_clk_ratio,
+
   // delay interface (for IDELAY macros)
   input                             up_clk,
   input   [NUM_LANES-1:0]           up_adc_dld,
@@ -270,5 +272,6 @@ module adrv9001_rx #(
 
   assign adc_clk = adc_clk_in_fast;
   assign adc_valid = 1'b1;
+  assign adc_clk_ratio = 4;
 
 endmodule

library/axi_adrv9001/adrv9001_tx.v

@@ -64,6 +64,7 @@ module adrv9001_tx #(
   input                   rx_ssi_rst,
 
   // internal resets and clocks
+  output     [31:0]       dac_clk_ratio,
 
   input                   dac_rst,
   output                  dac_clk_div,
@@ -240,4 +241,6 @@ module adrv9001_tx #(
 
   endgenerate
 
+  assign dac_clk_ratio = 4;
+
 endmodule

library/axi_adrv9001/axi_adrv9001.v

@@ -253,6 +253,8 @@ module axi_adrv9001 #(
   wire                              delay_rx2_rst;
   wire                              delay_rx1_locked;
   wire                              delay_rx2_locked;
+  wire                       [31:0] adc_clk_ratio;
+  wire                       [31:0] dac_clk_ratio;
 
   axi_adrv9001_if #(
     .CMOS_LVDS_N (CMOS_LVDS_N),
@@ -334,6 +336,7 @@ module axi_adrv9001 #(
     //
 
     // ADC interface
+    .adc_clk_ratio (adc_clk_ratio),
     .rx1_clk (adc_1_clk),
     .rx1_rst (adc_1_rst),
     .rx1_data_valid (rx1_data_valid),
@@ -353,6 +356,7 @@ module axi_adrv9001 #(
     .rx2_sdr_ddr_n (rx2_sdr_ddr_n),
 
     // DAC interface
+    .dac_clk_ratio (dac_clk_ratio),
     .tx1_clk (dac_1_clk),
     .tx1_rst (dac_1_rst),
     .tx1_data_valid (tx1_data_valid),
@@ -407,6 +411,8 @@ module axi_adrv9001 #(
     .rx2_single_lane (rx2_single_lane),
     .rx2_sdr_ddr_n (rx2_sdr_ddr_n),
 
+    .adc_clk_ratio (adc_clk_ratio),
+
     //DAC interface
     .tx1_clk (dac_1_clk),
     .tx1_rst (dac_1_rst),
@@ -426,6 +432,7 @@ module axi_adrv9001 #(
     .tx2_single_lane (tx2_single_lane),
     .tx2_sdr_ddr_n (tx2_sdr_ddr_n),
 
+    .dac_clk_ratio (dac_clk_ratio),
     //
     // User layer interface
     //

library/axi_adrv9001/axi_adrv9001_core.v

@@ -92,6 +92,9 @@ module axi_ad9001_core #(
   output                  tx2_single_lane,
   output                  tx2_sdr_ddr_n,
 
+  input       [ 31:0]     adc_clk_ratio,
+  input       [ 31:0]     dac_clk_ratio,
+
   // DMA interface
   output                  adc_1_valid,
   output                  adc_1_enable_i0,
@@ -311,6 +314,8 @@ module axi_ad9001_core #(
     .adc_sdr_ddr_n (rx1_sdr_ddr_n),
     .adc_r1_mode (rx1_r1_mode),
 
+    .adc_clk_ratio (adc_clk_ratio),
+
     .dac_data_valid_A (tx1_data_valid_A),
     .dac_data_i_A (tx1_data_i_A),
     .dac_data_q_A (tx1_data_q_A),
@@ -370,6 +375,8 @@ module axi_ad9001_core #(
     .adc_single_lane (rx2_single_lane_loc),
     .adc_sdr_ddr_n (rx2_sdr_ddr_n_loc),
 
+    .adc_clk_ratio (adc_clk_ratio),
+
     .dac_data_valid_A (tx2_data_valid_A),
     .dac_data_i_A (tx2_data_i_A),
     .dac_data_q_A (tx2_data_q_A),
@@ -426,6 +433,7 @@ module axi_ad9001_core #(
     .dac_sdr_ddr_n (tx1_sdr_ddr_n),
     .dac_r1_mode (tx1_r1_mode),
     .tdd_tx_valid (tdd_tx1_valid),
+    .dac_clk_ratio (dac_clk_ratio),
     .dac_sync_in (1'b0),
     .dac_sync_out (),
     .dac_enable_i0 (dac_1_enable_i0),
@@ -490,6 +498,7 @@ module axi_ad9001_core #(
     .dac_data_q1 (16'b0),
     .dac_dunf (dac_2_dunf),
     .tdd_tx_valid (tdd_tx2_valid),
+    .dac_clk_ratio (dac_clk_ratio),
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_wreq (up_wreq),

library/axi_adrv9001/axi_adrv9001_if.v

@@ -108,6 +108,9 @@ module axi_adrv9001_if #(
 
   // upper layer data interface
 
+  output [ 31:0]    adc_clk_ratio,
+  output [ 31:0]    dac_clk_ratio,
+
   output            rx1_clk,
   input             rx1_rst,
   output            rx1_data_valid,
@@ -215,6 +218,8 @@ module axi_adrv9001_if #(
     .adc_data_strobe (adc_1_data_strobe),
     .adc_valid (adc_1_valid),
 
+    .adc_clk_ratio (adc_clk_ratio),
+
     .up_clk (up_clk),
     .up_adc_dld (up_rx1_dld),
     .up_adc_dwdata (up_rx1_dwdata),
@@ -346,6 +351,8 @@ module axi_adrv9001_if #(
    .dac_data_clk (dac_1_data_clk),
    .dac_data_valid (dac_1_data_valid),
 
+   .dac_clk_ratio (dac_clk_ratio),
+
    .mssi_sync (mssi_sync)
   );
 

library/axi_adrv9001/axi_adrv9001_rx.v

@@ -65,6 +65,8 @@ module axi_adrv9001_rx #(
   output                  adc_sdr_ddr_n,
   output                  adc_r1_mode,
 
+  input       [ 31:0]     adc_clk_ratio,
+
   // dac loopback interface
   input                   dac_data_valid_A,
   input       [ 15:0]     dac_data_i_A,
@@ -354,7 +356,7 @@ end else begin : core_enabled
     .adc_status (1'b1),
     .adc_sync_status (1'd0),
     .adc_status_ovf (adc_dovf),
-    .adc_clk_ratio (32'd1),
+    .adc_clk_ratio (adc_clk_ratio),
     .adc_start_code (),
     .adc_sref_sync (),
     .adc_sync (),

library/axi_adrv9001/axi_adrv9001_tx.v

@@ -71,6 +71,8 @@ module axi_adrv9001_tx #(
 
   input                   tdd_tx_valid,
 
+  input       [ 31:0]     dac_clk_ratio,
+
   // master/slave
   input                   dac_sync_in,
   output                  dac_sync_out,
@@ -378,7 +380,7 @@ end else begin : core_enabled
     .dac_datarate (dac_datarate_s),
     .dac_status (1'b1),
     .dac_status_unf (dac_dunf),
-    .dac_clk_ratio (32'd2),
+    .dac_clk_ratio (dac_clk_ratio),
     .up_dac_ce (),
     .up_pps_rcounter(32'h0),
     .up_pps_status(1'b0),

library/axi_adrv9001/intel/adrv9001_rx.v

@@ -64,6 +64,8 @@ module adrv9001_rx #(
   output      [7:0]       adc_data_strobe,
   output                  adc_valid,
 
+  output     [31:0]       adc_clk_ratio,
+
   // delay interface (for IDELAY macros)
   input                             up_clk,
   input   [NUM_LANES-1:0]           up_adc_dld,
@@ -139,6 +141,7 @@ module adrv9001_rx #(
   // No clock divider, qualifier used instead
   assign adc_clk_div = rx_clk;
   assign adc_clk = rx_clk;
+  assign adc_clk_ratio = 1;
 
   // Drive unused signals
   assign delay_locked = 'b0;

library/axi_adrv9001/intel/adrv9001_tx.v

@@ -65,6 +65,8 @@ module adrv9001_tx #(
 
   // internal resets and clocks
 
+  output     [31:0]       dac_clk_ratio,
+
   input                   dac_rst,
   output                  dac_clk_div,
 
@@ -132,4 +134,6 @@ module adrv9001_tx #(
   assign dac_clk_div = tx_clk;
   assign dac_clk = tx_clk;
 
+  assign dac_clk_ratio = 1;
+
 endmodule