ad7768evb: added
Rejeesh Kutty
parent
12c95b059d
commit
0938041d97
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####################################################################################
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####################################################################################
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## Copyright 2011(c) Analog Devices, Inc.
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## Auto-generated, do not modify!
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####################################################################################
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####################################################################################
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.PHONY: all clean clean-all
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all:
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-make -C zed all
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clean:
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make -C zed clean
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clean-all:
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make -C zed clean-all
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####################################################################################
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####################################################################################
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module ad7768_if (
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// device-interface
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clk_in,
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ready_in,
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data_in,
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// data path interface
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adc_clk,
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adc_valid,
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adc_data,
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// control interface
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up_sshot,
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up_format,
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up_crc_enable,
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up_crc_4_or_16_n,
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up_status_clr,
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up_status);
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// device-interface
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input clk_in;
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input ready_in;
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input [ 7:0] data_in;
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// data path interface
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output adc_clk;
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output adc_valid;
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output [ 31:0] adc_data;
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// control interface
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input up_sshot;
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input [ 1:0] up_format;
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input up_crc_enable;
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input up_crc_4_or_16_n;
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input [ 35:0] up_status_clr;
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output [ 35:0] up_status;
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// internal registers
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reg [ 1:0] adc_status_8 = 'd0;
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reg [ 2:0] adc_status_7 = 'd0;
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reg [ 2:0] adc_status_6 = 'd0;
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reg [ 2:0] adc_status_5 = 'd0;
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reg [ 2:0] adc_status_4 = 'd0;
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reg [ 2:0] adc_status_3 = 'd0;
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reg [ 2:0] adc_status_2 = 'd0;
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reg [ 2:0] adc_status_1 = 'd0;
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reg [ 2:0] adc_status_0 = 'd0;
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reg adc_valid = 'd0;
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reg [ 31:0] adc_data = 'd0;
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reg [ 2:0] adc_seq = 'd0;
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reg [ 4:0] adc_status = 'd0;
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reg [ 63:0] adc_crc_8 = 'd0;
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reg [ 7:0] adc_crc_mismatch_int = 'd0;
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reg adc_crc_valid = 'd0;
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reg [ 7:0] adc_crc_data = 'd0;
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reg [ 7:0] adc_crc_mismatch_8 = 'd0;
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reg adc_valid_int = 'd0;
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reg [ 31:0] adc_data_int = 'd0;
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reg [ 2:0] adc_seq_int = 'd0;
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reg adc_enable_int = 'd0;
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reg [ 3:0] adc_crc_scnt_int = 'd0;
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reg [ 3:0] adc_crc_scnt_8 = 'd0;
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reg [ 23:0] adc_seq_data = 'd0;
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reg adc_seq_fmatch = 'd0;
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reg [ 23:0] adc_seq_fdata = 'd0;
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reg adc_seq_foos = 'd0;
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reg [ 7:0] adc_enable_8 = 'd0;
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reg [ 23:0] adc_seq_8 = 'd0;
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reg adc_valid_8 = 'd0;
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reg [ 31:0] adc_data_8 = 'd0;
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reg [ 7:0] adc_ch_valid_d = 'd0;
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reg [255:0] adc_ch_data_d0 = 'd0;
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reg [255:0] adc_ch_data_d1 = 'd0;
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reg [255:0] adc_ch_data_d2 = 'd0;
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reg [255:0] adc_ch_data_d3 = 'd0;
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reg [255:0] adc_ch_data_d4 = 'd0;
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reg [255:0] adc_ch_data_d5 = 'd0;
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reg [255:0] adc_ch_data_d6 = 'd0;
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reg [255:0] adc_ch_data_d7 = 'd0;
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reg adc_ch_valid_0 = 'd0;
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reg adc_ch_valid_1 = 'd0;
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reg adc_ch_valid_2 = 'd0;
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reg adc_ch_valid_3 = 'd0;
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reg adc_ch_valid_4 = 'd0;
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reg adc_ch_valid_5 = 'd0;
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reg adc_ch_valid_6 = 'd0;
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reg adc_ch_valid_7 = 'd0;
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reg [ 31:0] adc_ch_data_0 = 'd0;
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reg [ 31:0] adc_ch_data_1 = 'd0;
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reg [ 31:0] adc_ch_data_2 = 'd0;
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reg [ 31:0] adc_ch_data_3 = 'd0;
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reg [ 31:0] adc_ch_data_4 = 'd0;
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reg [ 31:0] adc_ch_data_5 = 'd0;
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reg [ 31:0] adc_ch_data_6 = 'd0;
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reg [ 31:0] adc_ch_data_7 = 'd0;
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reg adc_ch_valid = 'd0;
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reg [255:0] adc_ch_data = 'd0;
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reg [ 8:0] adc_cnt_p = 'd0;
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reg adc_valid_p = 'd0;
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reg [255:0] adc_data_p = 'd0;
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reg [ 7:0] adc_data_d1 = 'd0;
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reg [ 7:0] adc_data_d2 = 'd0;
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reg adc_ready_d1 = 'd0;
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reg adc_ready = 'd0;
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reg adc_ready_d = 'd0;
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reg adc_sshot_m1 = 'd0;
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reg adc_sshot = 'd0;
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reg [ 1:0] adc_format_m1 = 'd0;
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reg [ 1:0] adc_format = 'd0;
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reg adc_crc_enable_m1 = 'd0;
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reg adc_crc_enable = 'd0;
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reg adc_crc_4_or_16_n_m1 = 'd0;
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reg adc_crc_4_or_16_n = 'd0;
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reg [ 35:0] adc_status_clr_m1 = 'd0;
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reg [ 35:0] adc_status_clr = 'd0;
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reg [ 35:0] adc_status_clr_d = 'd0;
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// internal signals
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wire [ 7:0] adc_crc_in_s;
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wire [ 7:0] adc_crc_s;
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wire adc_crc_mismatch_s;
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wire adc_seq_fmatch_s;
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wire adc_seq_fupdate_s;
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wire [ 7:0] adc_enable_8_s;
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wire [ 23:0] adc_seq_8_s;
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wire adc_cnt_enable_1_s;
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wire adc_cnt_enable_4_s;
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wire adc_cnt_enable_8_s;
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wire adc_cnt_enable_s;
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wire [ 7:0] adc_data_in_s;
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wire adc_ready_in_s;
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wire adc_clk_in_s;
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wire [ 35:0] adc_status_clr_s;
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// function (crc)
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function [ 7:0] crc8;
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input [23:0] din;
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input [ 7:0] cin;
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reg [ 7:0] cout;
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begin
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cout[ 7] = cin[ 1] ^ cin[ 2] ^ cin[ 4] ^ cin[ 6] ^ din[ 5] ^ din[ 6] ^ din[ 7] ^ din[11] ^
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din[13] ^ din[15] ^ din[17] ^ din[18] ^ din[20] ^ din[22];
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cout[ 6] = cin[ 0] ^ cin[ 1] ^ cin[ 3] ^ cin[ 5] ^ din[ 4] ^ din[ 5] ^ din[ 6] ^ din[10] ^
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din[12] ^ din[14] ^ din[16] ^ din[17] ^ din[19] ^ din[21];
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cout[ 5] = cin[ 0] ^ cin[ 2] ^ cin[ 4] ^ din[ 3] ^ din[ 4] ^ din[ 5] ^ din[ 9] ^ din[11] ^
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din[13] ^ din[15] ^ din[16] ^ din[18] ^ din[20];
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cout[ 4] = cin[ 1] ^ cin[ 3] ^ din[ 2] ^ din[ 3] ^ din[ 4] ^ din[ 8] ^ din[10] ^ din[12] ^
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din[14] ^ din[15] ^ din[17] ^ din[19];
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cout[ 3] = cin[ 0] ^ cin[ 2] ^ cin[ 7] ^ din[ 1] ^ din[ 2] ^ din[ 3] ^ din[ 7] ^ din[ 9] ^
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din[11] ^ din[13] ^ din[14] ^ din[16] ^ din[18] ^ din[23];
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cout[ 2] = cin[ 1] ^ cin[ 6] ^ din[ 0] ^ din[ 1] ^ din[ 2] ^ din[ 6] ^ din[ 8] ^ din[10] ^
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din[12] ^ din[13] ^ din[15] ^ din[17] ^ din[22];
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cout[ 1] = cin[ 0] ^ cin[ 1] ^ cin[ 2] ^ cin[ 4] ^ cin[ 5] ^ cin[ 6] ^ cin[ 7] ^ din[ 0] ^
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din[ 1] ^ din[ 6] ^ din[ 9] ^ din[12] ^ din[13] ^ din[14] ^ din[15] ^ din[16] ^
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din[17] ^ din[18] ^ din[20] ^ din[21] ^ din[22] ^ din[23];
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cout[ 0] = cin[ 0] ^ cin[ 2] ^ cin[ 3] ^ cin[ 5] ^ cin[ 7] ^ din[ 0] ^ din[ 6] ^ din[ 7] ^
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din[ 8] ^ din[12] ^ din[14] ^ din[16] ^ din[18] ^ din[19] ^ din[21] ^ din[23];
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crc8 = cout;
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end
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endfunction
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// status
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assign up_status[35:32] = {2'd0, adc_status_8};
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assign up_status[31:28] = {1'd0, adc_status_7};
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assign up_status[27:24] = {1'd0, adc_status_6};
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assign up_status[23:20] = {1'd0, adc_status_5};
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assign up_status[19:16] = {1'd0, adc_status_4};
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assign up_status[15:12] = {1'd0, adc_status_3};
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assign up_status[11: 8] = {1'd0, adc_status_2};
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assign up_status[ 7: 4] = {1'd0, adc_status_1};
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assign up_status[ 3: 0] = {1'd0, adc_status_0};
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always @(posedge adc_clk) begin
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if (adc_valid == 1'b1) begin
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adc_status_8 <= adc_status_8 | adc_status[1:0];
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end else begin
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adc_status_8 <= adc_status_8 & ~adc_status_clr_s[33:32];
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end
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if ((adc_valid == 1'b1) && (adc_seq[2:0] == 3'd7)) begin
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adc_status_7 <= adc_status_7 | adc_status[4:2];
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end else begin
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adc_status_7 <= adc_status_7 & ~adc_status_clr_s[30:28];
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end
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if ((adc_valid == 1'b1) && (adc_seq[2:0] == 3'd6)) begin
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adc_status_6 <= adc_status_6 | adc_status[4:2];
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end else begin
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adc_status_6 <= adc_status_6 & ~adc_status_clr_s[26:24];
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end
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if ((adc_valid == 1'b1) && (adc_seq[2:0] == 3'd5)) begin
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adc_status_5 <= adc_status_5 | adc_status[4:2];
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end else begin
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adc_status_5 <= adc_status_5 & ~adc_status_clr_s[22:20];
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end
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if ((adc_valid == 1'b1) && (adc_seq[2:0] == 3'd4)) begin
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adc_status_4 <= adc_status_4 | adc_status[4:2];
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end else begin
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adc_status_4 <= adc_status_4 & ~adc_status_clr_s[18:16];
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end
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if ((adc_valid == 1'b1) && (adc_seq[2:0] == 3'd3)) begin
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adc_status_3 <= adc_status_3 | adc_status[4:2];
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end else begin
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adc_status_3 <= adc_status_3 & ~adc_status_clr_s[14:12];
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end
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if ((adc_valid == 1'b1) && (adc_seq[2:0] == 3'd2)) begin
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adc_status_2 <= adc_status_2 | adc_status[4:2];
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end else begin
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adc_status_2 <= adc_status_2 & ~adc_status_clr_s[10: 8];
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end
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if ((adc_valid == 1'b1) && (adc_seq[2:0] == 3'd1)) begin
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adc_status_1 <= adc_status_1 | adc_status[4:2];
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end else begin
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adc_status_1 <= adc_status_1 & ~adc_status_clr_s[ 6: 4];
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end
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if ((adc_valid == 1'b1) && (adc_seq[2:0] == 3'd0)) begin
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adc_status_0 <= adc_status_0 | adc_status[4:2];
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end else begin
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adc_status_0 <= adc_status_0 & ~adc_status_clr_s[ 2: 0];
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end
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end
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// data & status
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always @(posedge adc_clk) begin
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adc_valid <= adc_valid_int & adc_enable_int;
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adc_data <= {{8{adc_data_int[23]}}, adc_data_int[23:0]};
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adc_seq <= adc_seq_int;
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if ((adc_crc_enable == 1'b1) && (adc_crc_scnt_int == 4'd0)) begin
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adc_status[4] <= adc_crc_mismatch_8[7] & adc_enable_int;
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adc_status[3] <= 1'b0;
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adc_status[2] <= 1'b0;
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adc_status[1] <= 1'b0;
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adc_status[0] <= adc_seq_foos;
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end else begin
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adc_status[4] <= adc_crc_mismatch_8[7] & adc_enable_int;
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adc_status[3] <= adc_data_int[30] & adc_enable_int;
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adc_status[2] <= adc_data_int[27] & adc_enable_int;
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adc_status[1] <= adc_data_int[31] & adc_enable_int;
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adc_status[0] <= adc_seq_foos;
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end
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end
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// crc- not much useful at the interface, since it is post-framing
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assign adc_crc_in_s = (adc_crc_scnt_int == 4'd1) ? 8'hff : adc_crc_8[63:56];
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assign adc_crc_s = crc8(adc_data_int[23:0], adc_crc_in_s);
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assign adc_crc_mismatch_s = (adc_crc_data == adc_crc_8[7:0]) ? 1'b0 : adc_crc_enable;
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always @(posedge adc_clk) begin
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if (adc_valid_int == 1'b1) begin
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adc_crc_8 <= {adc_crc_8[55:0], adc_crc_s};
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end
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if (adc_valid_int == 1'b1) begin
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adc_crc_mismatch_int <= {adc_crc_mismatch_int[6:0], 1'd0};
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end else begin
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adc_crc_mismatch_int <= adc_crc_mismatch_8;
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end
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if (adc_crc_scnt_int == 4'd0) begin
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adc_crc_valid <= adc_valid_int;
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end else begin
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adc_crc_valid <= 1'd0;
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end
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adc_crc_data <= adc_data_int[31:24];
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if (adc_crc_valid == 1'b1) begin
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adc_crc_mismatch_8 <= {adc_crc_mismatch_8[6:0], adc_crc_mismatch_s};
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end
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end
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// data interleaved & all-aligned
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always @(posedge adc_clk) begin
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adc_valid_int <= adc_valid_8;
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adc_data_int <= adc_data_8;
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adc_seq_int <= adc_seq_8[23:21];
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adc_enable_int <= adc_enable_8[7] & adc_valid_8;
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adc_crc_scnt_int <= adc_crc_scnt_8;
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end
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// crc- count
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always @(posedge adc_clk) begin
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if ((adc_ready == 1'b0) && (adc_ready_d == 1'b1)) begin
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if (adc_seq_fmatch_s == 1'b0) begin
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adc_crc_scnt_8 <= 4'd1;
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end else if ((adc_crc_4_or_16_n == 1'b1) && (adc_crc_scnt_8 == 4'h3)) begin
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adc_crc_scnt_8 <= 4'd0;
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end else begin
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adc_crc_scnt_8 <= adc_crc_scnt_8 + 1'b1;
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end
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end
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end
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// three sample framing logic
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always @(posedge adc_clk) begin
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if (adc_ready == 1'b0) begin
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adc_seq_data <= 24'd0;
|
||||
end else if (adc_valid_8 == 1'b1) begin
|
||||
adc_seq_data <= {adc_seq_data[20:0], adc_data_8[26:24]};
|
||||
end
|
||||
end
|
||||
|
||||
assign adc_seq_fmatch_s = (adc_seq_data == adc_seq_fdata) ? 1'b1 : 1'b0;
|
||||
assign adc_seq_fupdate_s = adc_seq_fmatch_s ^ adc_seq_fmatch;
|
||||
|
||||
always @(posedge adc_clk) begin
|
||||
if ((adc_ready == 1'b0) && (adc_ready_d == 1'b1)) begin
|
||||
adc_seq_fmatch <= adc_seq_fmatch_s;
|
||||
if (adc_seq_foos == 1'b1) begin
|
||||
adc_seq_fdata <= adc_seq_data;
|
||||
end
|
||||
if (adc_seq_fupdate_s == 1'b0) begin
|
||||
adc_seq_foos <= ~adc_seq_fmatch_s;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// we are cluless on 0 -- safe to compare all 32bits against 0x0?
|
||||
|
||||
assign adc_enable_8_s[7] = (adc_seq_8[23:21] == adc_seq_fdata[23:21]) ? 1'b1 : 1'b0;
|
||||
assign adc_enable_8_s[6] = (adc_seq_8[20:18] == adc_seq_fdata[20:18]) ? 1'b1 : 1'b0;
|
||||
assign adc_enable_8_s[5] = (adc_seq_8[17:15] == adc_seq_fdata[17:15]) ? 1'b1 : 1'b0;
|
||||
assign adc_enable_8_s[4] = (adc_seq_8[14:12] == adc_seq_fdata[14:12]) ? 1'b1 : 1'b0;
|
||||
assign adc_enable_8_s[3] = (adc_seq_8[11: 9] == adc_seq_fdata[11: 9]) ? 1'b1 : 1'b0;
|
||||
assign adc_enable_8_s[2] = (adc_seq_8[ 8: 6] == adc_seq_fdata[ 8: 6]) ? 1'b1 : 1'b0;
|
||||
assign adc_enable_8_s[1] = (adc_seq_8[ 5: 3] == adc_seq_fdata[ 5: 3]) ? 1'b1 : 1'b0;
|
||||
assign adc_enable_8_s[0] = (adc_seq_8[ 2: 0] == adc_seq_fdata[ 2: 0]) ? 1'b1 : 1'b0;
|
||||
|
||||
always @(posedge adc_clk) begin
|
||||
if (adc_ready_d == 1'b0) begin
|
||||
adc_enable_8 <= adc_enable_8_s;
|
||||
end else if (adc_valid_8 == 1'b1) begin
|
||||
adc_enable_8 <= {adc_enable_8[6:0], 1'd0};
|
||||
end
|
||||
end
|
||||
|
||||
// channel-sequence
|
||||
|
||||
assign adc_seq_8_s[23:21] = (adc_format == 2'b01) ? 3'd0 : 3'd0;
|
||||
assign adc_seq_8_s[20:18] = (adc_format == 2'b01) ? 3'd4 : 3'd1;
|
||||
assign adc_seq_8_s[17:15] = (adc_format == 2'b01) ? 3'd1 : 3'd2;
|
||||
assign adc_seq_8_s[14:12] = (adc_format == 2'b01) ? 3'd5 : 3'd3;
|
||||
assign adc_seq_8_s[11: 9] = (adc_format == 2'b01) ? 3'd2 : 3'd4;
|
||||
assign adc_seq_8_s[ 8: 6] = (adc_format == 2'b01) ? 3'd6 : 3'd5;
|
||||
assign adc_seq_8_s[ 5: 3] = (adc_format == 2'b01) ? 3'd3 : 3'd6;
|
||||
assign adc_seq_8_s[ 2: 0] = (adc_format == 2'b01) ? 3'd7 : 3'd7;
|
||||
|
||||
always @(posedge adc_clk) begin
|
||||
if ((adc_ready == 1'b0) && (adc_ready_d == 1'b1)) begin
|
||||
adc_seq_8 <= adc_seq_8_s;
|
||||
end else if (adc_valid_8 == 1'b1) begin
|
||||
adc_seq_8 <= {adc_seq_8[20:0], 3'd0};
|
||||
end
|
||||
end
|
||||
|
||||
// data (interleaving)
|
||||
|
||||
always @(posedge adc_clk) begin
|
||||
adc_valid_8 <= adc_ch_valid_0 | adc_ch_valid_1 | adc_ch_valid_2 | adc_ch_valid_3 |
|
||||
adc_ch_valid_4 | adc_ch_valid_5 | adc_ch_valid_6 | adc_ch_valid_7;
|
||||
adc_data_8 <= adc_ch_data_0 | adc_ch_data_1 | adc_ch_data_2 | adc_ch_data_3 |
|
||||
adc_ch_data_4 | adc_ch_data_5 | adc_ch_data_6 | adc_ch_data_7;
|
||||
end
|
||||
|
||||
always @(posedge adc_clk) begin
|
||||
adc_ch_valid_d <= {adc_ch_valid_d[6:0], adc_ch_valid};
|
||||
adc_ch_data_d0[((32*0)+31):(32*0)] <= adc_ch_data[((32*0)+31):(32*0)];
|
||||
adc_ch_data_d0[((32*7)+31):(32*1)] <= adc_ch_data_d0[((32*6)+31):(32*0)];
|
||||
adc_ch_data_d1[((32*0)+31):(32*0)] <= adc_ch_data[((32*1)+31):(32*1)];
|
||||
adc_ch_data_d1[((32*7)+31):(32*1)] <= adc_ch_data_d1[((32*6)+31):(32*0)];
|
||||
adc_ch_data_d2[((32*0)+31):(32*0)] <= adc_ch_data[((32*2)+31):(32*2)];
|
||||
adc_ch_data_d2[((32*7)+31):(32*1)] <= adc_ch_data_d2[((32*6)+31):(32*0)];
|
||||
adc_ch_data_d3[((32*0)+31):(32*0)] <= adc_ch_data[((32*3)+31):(32*3)];
|
||||
adc_ch_data_d3[((32*7)+31):(32*1)] <= adc_ch_data_d3[((32*6)+31):(32*0)];
|
||||
adc_ch_data_d4[((32*0)+31):(32*0)] <= adc_ch_data[((32*4)+31):(32*4)];
|
||||
adc_ch_data_d4[((32*7)+31):(32*1)] <= adc_ch_data_d4[((32*6)+31):(32*0)];
|
||||
adc_ch_data_d5[((32*0)+31):(32*0)] <= adc_ch_data[((32*5)+31):(32*5)];
|
||||
adc_ch_data_d5[((32*7)+31):(32*1)] <= adc_ch_data_d5[((32*6)+31):(32*0)];
|
||||
adc_ch_data_d6[((32*0)+31):(32*0)] <= adc_ch_data[((32*6)+31):(32*6)];
|
||||
adc_ch_data_d6[((32*7)+31):(32*1)] <= adc_ch_data_d6[((32*6)+31):(32*0)];
|
||||
adc_ch_data_d7[((32*0)+31):(32*0)] <= adc_ch_data[((32*7)+31):(32*7)];
|
||||
adc_ch_data_d7[((32*7)+31):(32*1)] <= adc_ch_data_d7[((32*6)+31):(32*0)];
|
||||
end
|
||||
|
||||
always @(posedge adc_clk) begin
|
||||
adc_ch_valid_0 <= adc_ch_valid_d[0];
|
||||
adc_ch_valid_1 <= adc_ch_valid_d[1] & ~adc_format[1];
|
||||
adc_ch_valid_2 <= adc_ch_valid_d[2] & ~adc_format[1] & ~adc_format[0];
|
||||
adc_ch_valid_3 <= adc_ch_valid_d[3] & ~adc_format[1] & ~adc_format[0];
|
||||
adc_ch_valid_4 <= adc_ch_valid_d[4] & ~adc_format[1] & ~adc_format[0];
|
||||
adc_ch_valid_5 <= adc_ch_valid_d[5] & ~adc_format[1] & ~adc_format[0];
|
||||
adc_ch_valid_6 <= adc_ch_valid_d[6] & ~adc_format[1] & ~adc_format[0];
|
||||
adc_ch_valid_7 <= adc_ch_valid_d[7] & ~adc_format[1] & ~adc_format[0];
|
||||
adc_ch_data_0 <= adc_ch_data_d0[((32*0)+31):(32*0)];
|
||||
adc_ch_data_1 <= adc_ch_data_d1[((32*1)+31):(32*1)];
|
||||
adc_ch_data_2 <= adc_ch_data_d2[((32*2)+31):(32*2)];
|
||||
adc_ch_data_3 <= adc_ch_data_d3[((32*3)+31):(32*3)];
|
||||
adc_ch_data_4 <= adc_ch_data_d4[((32*4)+31):(32*4)];
|
||||
adc_ch_data_5 <= adc_ch_data_d5[((32*5)+31):(32*5)];
|
||||
adc_ch_data_6 <= adc_ch_data_d6[((32*6)+31):(32*6)];
|
||||
adc_ch_data_7 <= adc_ch_data_d7[((32*7)+31):(32*7)];
|
||||
end
|
||||
|
||||
always @(posedge adc_clk) begin
|
||||
adc_ch_valid <= adc_valid_p;
|
||||
if (adc_valid_p == 1'b1) begin
|
||||
adc_ch_data <= adc_data_p;
|
||||
end else begin
|
||||
adc_ch_data <= 256'd0;
|
||||
end
|
||||
end
|
||||
|
||||
// data (common)
|
||||
|
||||
assign adc_cnt_enable_1_s = (adc_cnt_p <= 9'h01f) ? 1'b1 : 1'b0;
|
||||
assign adc_cnt_enable_4_s = (adc_cnt_p <= 9'h07f) ? 1'b1 : 1'b0;
|
||||
assign adc_cnt_enable_8_s = (adc_cnt_p <= 9'h0ff) ? 1'b1 : 1'b0;
|
||||
|
||||
assign adc_cnt_enable_s = (adc_format == 2'b00) ? adc_cnt_enable_1_s :
|
||||
((adc_format == 2'b01) ? adc_cnt_enable_4_s : adc_cnt_enable_8_s);
|
||||
|
||||
always @(posedge adc_clk) begin
|
||||
if (adc_ready == 1'b0) begin
|
||||
adc_cnt_p <= 9'h000;
|
||||
end else if (adc_cnt_enable_s == 1'b1) begin
|
||||
adc_cnt_p <= adc_cnt_p + 1'b1;
|
||||
end
|
||||
if (adc_cnt_p[4:0] == 5'h1f) begin
|
||||
adc_valid_p <= 1'b1;
|
||||
end else begin
|
||||
adc_valid_p <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
// data (individual lanes)
|
||||
|
||||
genvar n;
|
||||
generate
|
||||
for (n = 0; n < 8; n = n + 1) begin: g_data
|
||||
|
||||
always @(posedge adc_clk) begin
|
||||
if (adc_cnt_p[4:0] == 5'h00) begin
|
||||
adc_data_p[((32*n)+31):(32*n)] <= {31'd0, adc_data_d2[n]};
|
||||
end else begin
|
||||
adc_data_p[((32*n)+31):(32*n)] <= {adc_data_p[((32*n)+30):(32*n)], adc_data_d2[n]};
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge adc_clk) begin
|
||||
adc_data_d1[n] <= adc_data_in_s[n];
|
||||
adc_data_d2[n] <= adc_data_d1[n];
|
||||
end
|
||||
|
||||
IBUF i_ibuf_data (
|
||||
.I (data_in[n]),
|
||||
.O (adc_data_in_s[n]));
|
||||
|
||||
end
|
||||
endgenerate
|
||||
|
||||
// ready (single shot or continous)
|
||||
|
||||
always @(posedge adc_clk) begin
|
||||
adc_ready_d1 <= adc_ready_in_s;
|
||||
adc_ready <= adc_sshot ~^ adc_ready_d1;
|
||||
adc_ready_d <= adc_ready;
|
||||
end
|
||||
|
||||
IBUF i_ibuf_ready (
|
||||
.I (ready_in),
|
||||
.O (adc_ready_in_s));
|
||||
|
||||
// clock (use bufg delay ~4ns on 29ns)
|
||||
|
||||
BUFG i_bufg_clk (
|
||||
.I (adc_clk_in_s),
|
||||
.O (adc_clk));
|
||||
|
||||
IBUFG i_ibufg_clk (
|
||||
.I (clk_in),
|
||||
.O (adc_clk_in_s));
|
||||
|
||||
// control signals
|
||||
|
||||
assign adc_status_clr_s = adc_status_clr & ~adc_status_clr_d;
|
||||
|
||||
always @(posedge adc_clk) begin
|
||||
adc_sshot_m1 <= up_sshot;
|
||||
adc_sshot <= adc_sshot_m1;
|
||||
adc_format_m1 <= up_format;
|
||||
adc_format <= adc_format_m1;
|
||||
adc_crc_enable_m1 <= up_crc_enable;
|
||||
adc_crc_enable <= adc_crc_enable_m1;
|
||||
adc_crc_4_or_16_n_m1 <= up_crc_4_or_16_n;
|
||||
adc_crc_4_or_16_n <= adc_crc_4_or_16_n_m1;
|
||||
adc_status_clr_m1 <= up_status_clr;
|
||||
adc_status_clr <= adc_status_clr_m1;
|
||||
adc_status_clr_d <= adc_status_clr;
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
|
@ -0,0 +1,62 @@
|
|||
|
||||
# ad7768 interface
|
||||
|
||||
create_bd_port -dir I adc_clk
|
||||
create_bd_port -dir I adc_valid
|
||||
create_bd_port -dir I -from 31 -to 0 adc_data
|
||||
create_bd_port -dir I -from 31 -to 0 adc_gpio_0_i
|
||||
create_bd_port -dir O -from 31 -to 0 adc_gpio_0_o
|
||||
create_bd_port -dir O -from 31 -to 0 adc_gpio_0_t
|
||||
create_bd_port -dir I -from 31 -to 0 adc_gpio_1_i
|
||||
create_bd_port -dir O -from 31 -to 0 adc_gpio_1_o
|
||||
create_bd_port -dir O -from 31 -to 0 adc_gpio_1_t
|
||||
|
||||
# instances
|
||||
|
||||
set ad7768_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 ad7768_dma]
|
||||
set_property -dict [list CONFIG.DMA_TYPE_SRC {2}] $ad7768_dma
|
||||
set_property -dict [list CONFIG.DMA_TYPE_DEST {0}] $ad7768_dma
|
||||
set_property -dict [list CONFIG.CYCLIC {0}] $ad7768_dma
|
||||
set_property -dict [list CONFIG.SYNC_TRANSFER_START {1}] $ad7768_dma
|
||||
set_property -dict [list CONFIG.AXI_SLICE_SRC {0}] $ad7768_dma
|
||||
set_property -dict [list CONFIG.AXI_SLICE_DEST {0}] $ad7768_dma
|
||||
set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $ad7768_dma
|
||||
set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {32}] $ad7768_dma
|
||||
|
||||
# ps7-hp1
|
||||
|
||||
set_property -dict [list CONFIG.PCW_USE_S_AXI_HP1 {1}] $sys_ps7
|
||||
|
||||
# gpio
|
||||
|
||||
set ad7768_gpio [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 ad7768_gpio]
|
||||
set_property -dict [list CONFIG.C_IS_DUAL {1}] $ad7768_gpio
|
||||
set_property -dict [list CONFIG.C_GPIO_WIDTH {32}] $ad7768_gpio
|
||||
set_property -dict [list CONFIG.C_GPIO2_WIDTH {32}] $ad7768_gpio
|
||||
set_property -dict [list CONFIG.C_INTERRUPT_PRESENT {1}] $ad7768_gpio
|
||||
|
||||
# interconnects
|
||||
|
||||
ad_connect adc_clk ad7768_dma/fifo_wr_clk
|
||||
ad_connect adc_valid ad7768_dma/fifo_wr_en
|
||||
ad_connect adc_data ad7768_dma/fifo_wr_din
|
||||
ad_connect adc_gpio_0_i ad7768_gpio/gpio_io_i
|
||||
ad_connect adc_gpio_0_o ad7768_gpio/gpio_io_o
|
||||
ad_connect adc_gpio_0_t ad7768_gpio/gpio_io_t
|
||||
ad_connect adc_gpio_1_i ad7768_gpio/gpio2_io_i
|
||||
ad_connect adc_gpio_1_o ad7768_gpio/gpio2_io_o
|
||||
ad_connect adc_gpio_1_t ad7768_gpio/gpio2_io_t
|
||||
|
||||
# interrupts
|
||||
|
||||
ad_cpu_interrupt ps-13 mb-13 ad7768_dma/irq
|
||||
ad_cpu_interrupt ps-12 mb-12 ad7768_gpio/ip2intc_irpt
|
||||
|
||||
# cpu / memory interconnects
|
||||
|
||||
ad_cpu_interconnect 0x7C400000 ad7768_dma
|
||||
ad_cpu_interconnect 0x7C420000 ad7768_gpio
|
||||
|
||||
ad_mem_hp1_interconnect sys_cpu_clk sys_ps7/S_AXI_HP1
|
||||
ad_mem_hp1_interconnect sys_cpu_clk ad7768_dma/m_dest_axi
|
||||
|
||||
|
|
@ -0,0 +1,78 @@
|
|||
####################################################################################
|
||||
####################################################################################
|
||||
## Copyright 2011(c) Analog Devices, Inc.
|
||||
## Auto-generated, do not modify!
|
||||
####################################################################################
|
||||
####################################################################################
|
||||
|
||||
M_DEPS += system_top.v
|
||||
M_DEPS += system_project.tcl
|
||||
M_DEPS += system_constr.xdc
|
||||
M_DEPS += system_bd.tcl
|
||||
M_DEPS += ../common/cftl_cip_bd.tcl
|
||||
M_DEPS += ../../scripts/adi_project.tcl
|
||||
M_DEPS += ../../scripts/adi_env.tcl
|
||||
M_DEPS += ../../scripts/adi_board.tcl
|
||||
M_DEPS += ../../common/zed/zed_system_constr.xdc
|
||||
M_DEPS += ../../common/zed/zed_system_bd.tcl
|
||||
M_DEPS += ../../../library/common/ad_iobuf.v
|
||||
M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
|
||||
M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
|
||||
M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr
|
||||
M_DEPS += ../../../library/axi_i2s_adi/axi_i2s_adi.xpr
|
||||
M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr
|
||||
M_DEPS += ../../../library/util_i2c_mixer/util_i2c_mixer.xpr
|
||||
M_DEPS += ../../../library/util_pmod_adc/util_pmod_adc.xpr
|
||||
M_DEPS += ../../../library/util_pmod_fmeter/util_pmod_fmeter.xpr
|
||||
|
||||
M_VIVADO := vivado -mode batch -source
|
||||
|
||||
M_FLIST := *.cache
|
||||
M_FLIST += *.data
|
||||
M_FLIST += *.xpr
|
||||
M_FLIST += *.log
|
||||
M_FLIST += *.jou
|
||||
M_FLIST += xgui
|
||||
M_FLIST += *.runs
|
||||
M_FLIST += *.srcs
|
||||
M_FLIST += *.sdk
|
||||
M_FLIST += .Xil
|
||||
|
||||
|
||||
|
||||
.PHONY: all lib clean clean-all
|
||||
all: lib cftl_custom_zed.sdk/system_top.hdf
|
||||
|
||||
|
||||
clean:
|
||||
rm -rf $(M_FLIST)
|
||||
|
||||
|
||||
clean-all:clean
|
||||
make -C ../../../library/axi_clkgen clean
|
||||
make -C ../../../library/axi_dmac clean
|
||||
make -C ../../../library/axi_hdmi_tx clean
|
||||
make -C ../../../library/axi_i2s_adi clean
|
||||
make -C ../../../library/axi_spdif_tx clean
|
||||
make -C ../../../library/util_i2c_mixer clean
|
||||
make -C ../../../library/util_pmod_adc clean
|
||||
make -C ../../../library/util_pmod_fmeter clean
|
||||
|
||||
|
||||
cftl_custom_zed.sdk/system_top.hdf: $(M_DEPS)
|
||||
rm -rf $(M_FLIST)
|
||||
$(M_VIVADO) system_project.tcl >> cftl_custom_zed_vivado.log 2>&1
|
||||
|
||||
|
||||
lib:
|
||||
make -C ../../../library/axi_clkgen
|
||||
make -C ../../../library/axi_dmac
|
||||
make -C ../../../library/axi_hdmi_tx
|
||||
make -C ../../../library/axi_i2s_adi
|
||||
make -C ../../../library/axi_spdif_tx
|
||||
make -C ../../../library/util_i2c_mixer
|
||||
make -C ../../../library/util_pmod_adc
|
||||
make -C ../../../library/util_pmod_fmeter
|
||||
|
||||
####################################################################################
|
||||
####################################################################################
|
||||
|
|
@ -0,0 +1,4 @@
|
|||
|
||||
source $ad_hdl_dir/projects/common/zed/zed_system_bd.tcl
|
||||
source ../common/ad7768evb_bd.tcl
|
||||
|
||||
|
|
@ -0,0 +1,29 @@
|
|||
|
||||
|
||||
set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVCMOS25} [get_ports clk_in] ; ## H04 FMC_LPC_CLK0_M2C_P IO_L12P_T1_MRCC_34
|
||||
set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVCMOS25} [get_ports ready_in] ; ## G06 FMC_LPC_LA00_CC_P IO_L13P_T2_MRCC_34
|
||||
set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVCMOS25} [get_ports data_in[0]] ; ## G07 FMC_LPC_LA00_CC_N IO_L13N_T2_MRCC_34
|
||||
set_property -dict {PACKAGE_PIN L22 IOSTANDARD LVCMOS25} [get_ports data_in[1]] ; ## C11 FMC_LPC_LA06_N IO_L10N_T1_34
|
||||
set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [get_ports data_in[2]] ; ## H07 FMC_LPC_LA02_P IO_L20P_T3_34
|
||||
set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS25} [get_ports data_in[3]] ; ## H08 FMC_LPC_LA02_N IO_L20N_T3_34
|
||||
set_property -dict {PACKAGE_PIN J21 IOSTANDARD LVCMOS25} [get_ports data_in[4]] ; ## G12 FMC_LPC_LA08_P IO_L8P_T1_34
|
||||
set_property -dict {PACKAGE_PIN J22 IOSTANDARD LVCMOS25} [get_ports data_in[5]] ; ## G13 FMC_LPC_LA08_N IO_L8N_T1_34
|
||||
set_property -dict {PACKAGE_PIN R20 IOSTANDARD LVCMOS25} [get_ports data_in[6]] ; ## D14 FMC_LPC_LA09_P IO_L17P_T2_34
|
||||
set_property -dict {PACKAGE_PIN R21 IOSTANDARD LVCMOS25} [get_ports data_in[7]] ; ## D15 FMC_LPC_LA09_N IO_L17N_T2_34
|
||||
set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS25} [get_ports spi_csn] ; ## D11 FMC_LPC_LA05_P IO_L7P_T1_34
|
||||
set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVCMOS25} [get_ports spi_clk] ; ## D08 FMC_LPC_LA01_CC_P IO_L14P_T2_SRCC_34
|
||||
set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVCMOS25} [get_ports spi_mosi] ; ## H11 FMC_LPC_LA04_N IO_L15N_T2_DQS_34
|
||||
set_property -dict {PACKAGE_PIN N22 IOSTANDARD LVCMOS25} [get_ports spi_miso] ; ## G09 FMC_LPC_LA03_P IO_L16P_T2_34
|
||||
set_property -dict {PACKAGE_PIN T19 IOSTANDARD LVCMOS25} [get_ports gpio_0_mode_0] ; ## C15 FMC_LPC_LA10_N IO_L22N_T3_34
|
||||
set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVCMOS25} [get_ports gpio_1_mode_1] ; ## H13 FMC_LPC_LA07_P IO_L21P_T3_DQS_34
|
||||
set_property -dict {PACKAGE_PIN T17 IOSTANDARD LVCMOS25} [get_ports gpio_2_mode_2] ; ## H14 FMC_LPC_LA07_N IO_L21N_T3_DQS_34
|
||||
set_property -dict {PACKAGE_PIN N17 IOSTANDARD LVCMOS25} [get_ports gpio_3_mode_3] ; ## H16 FMC_LPC_LA11_P IO_L5P_T0_34
|
||||
set_property -dict {PACKAGE_PIN R19 IOSTANDARD LVCMOS25} [get_ports gpio_4_filter] ; ## C14 FMC_LPC_LA10_P IO_L22P_T3_34
|
||||
set_property -dict {PACKAGE_PIN L21 IOSTANDARD LVCMOS25} [get_ports reset_n] ; ## C10 FMC_LPC_LA06_P IO_L10P_T1_34
|
||||
set_property -dict {PACKAGE_PIN P22 IOSTANDARD LVCMOS25} [get_ports start_n] ; ## G10 FMC_LPC_LA03_N IO_L16N_T2_34
|
||||
set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVCMOS25} [get_ports sync_n] ; ## H10 FMC_LPC_LA04_P IO_L15P_T2_DQS_34
|
||||
set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVCMOS25} [get_ports sync_in_n] ; ## D12 FMC_LPC_LA05_N IO_L7N_T1_34
|
||||
set_property -dict {PACKAGE_PIN N20 IOSTANDARD LVCMOS25} [get_ports mclk] ; ## D09 FMC_LPC_LA01_CC_N IO_L14N_T2_SRCC_34
|
||||
|
||||
create_clock -name adc_clk -period 20 [get_ports clk_in]
|
||||
|
||||
|
|
@ -0,0 +1,15 @@
|
|||
|
||||
source ../../scripts/adi_env.tcl
|
||||
source $ad_hdl_dir/projects/scripts/adi_project.tcl
|
||||
source $ad_hdl_dir/projects/scripts/adi_board.tcl
|
||||
|
||||
adi_project_create ad7768evb_zed
|
||||
adi_project_files ad7768evb_zed [list \
|
||||
"../common/ad7768_if.v" \
|
||||
"system_top.v" \
|
||||
"system_constr.xdc" \
|
||||
"$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc" \
|
||||
"$ad_hdl_dir/library/common/ad_iobuf.v" ]
|
||||
|
||||
adi_project_run ad7768evb_zed
|
||||
|
||||
|
|
@ -0,0 +1,341 @@
|
|||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2011(c) Analog Devices, Inc.
|
||||
//
|
||||
// All rights reserved.
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without modification,
|
||||
// are permitted provided that the following conditions are met:
|
||||
// - Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
// - Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in
|
||||
// the documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
// - Neither the name of Analog Devices, Inc. nor the names of its
|
||||
// contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
// - The use of this software may or may not infringe the patent rights
|
||||
// of one or more patent holders. This license does not release you
|
||||
// from the requirement that you obtain separate licenses from these
|
||||
// patent holders to use this software.
|
||||
// - Use of the software either in source or binary form, must be run
|
||||
// on or directly connected to an Analog Devices Inc. component.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
|
||||
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
|
||||
// PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
//
|
||||
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
|
||||
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
|
||||
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
|
||||
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
|
||||
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module system_top (
|
||||
|
||||
ddr_addr,
|
||||
ddr_ba,
|
||||
ddr_cas_n,
|
||||
ddr_ck_n,
|
||||
ddr_ck_p,
|
||||
ddr_cke,
|
||||
ddr_cs_n,
|
||||
ddr_dm,
|
||||
ddr_dq,
|
||||
ddr_dqs_n,
|
||||
ddr_dqs_p,
|
||||
ddr_odt,
|
||||
ddr_ras_n,
|
||||
ddr_reset_n,
|
||||
ddr_we_n,
|
||||
|
||||
fixed_io_ddr_vrn,
|
||||
fixed_io_ddr_vrp,
|
||||
fixed_io_mio,
|
||||
fixed_io_ps_clk,
|
||||
fixed_io_ps_porb,
|
||||
fixed_io_ps_srstb,
|
||||
|
||||
gpio_bd,
|
||||
|
||||
hdmi_out_clk,
|
||||
hdmi_vsync,
|
||||
hdmi_hsync,
|
||||
hdmi_data_e,
|
||||
hdmi_data,
|
||||
|
||||
i2s_mclk,
|
||||
i2s_bclk,
|
||||
i2s_lrclk,
|
||||
i2s_sdata_out,
|
||||
i2s_sdata_in,
|
||||
|
||||
spdif,
|
||||
|
||||
iic_scl,
|
||||
iic_sda,
|
||||
iic_mux_scl,
|
||||
iic_mux_sda,
|
||||
|
||||
otg_vbusoc,
|
||||
|
||||
clk_in,
|
||||
ready_in,
|
||||
data_in,
|
||||
|
||||
spi_csn,
|
||||
spi_clk,
|
||||
spi_mosi,
|
||||
spi_miso,
|
||||
|
||||
gpio_0_mode_0,
|
||||
gpio_1_mode_1,
|
||||
gpio_2_mode_2,
|
||||
gpio_3_mode_3,
|
||||
gpio_4_filter,
|
||||
reset_n,
|
||||
start_n,
|
||||
sync_n,
|
||||
sync_in_n,
|
||||
mclk);
|
||||
|
||||
inout [14:0] ddr_addr;
|
||||
inout [ 2:0] ddr_ba;
|
||||
inout ddr_cas_n;
|
||||
inout ddr_ck_n;
|
||||
inout ddr_ck_p;
|
||||
inout ddr_cke;
|
||||
inout ddr_cs_n;
|
||||
inout [ 3:0] ddr_dm;
|
||||
inout [31:0] ddr_dq;
|
||||
inout [ 3:0] ddr_dqs_n;
|
||||
inout [ 3:0] ddr_dqs_p;
|
||||
inout ddr_odt;
|
||||
inout ddr_ras_n;
|
||||
inout ddr_reset_n;
|
||||
inout ddr_we_n;
|
||||
|
||||
inout fixed_io_ddr_vrn;
|
||||
inout fixed_io_ddr_vrp;
|
||||
inout [53:0] fixed_io_mio;
|
||||
inout fixed_io_ps_clk;
|
||||
inout fixed_io_ps_porb;
|
||||
inout fixed_io_ps_srstb;
|
||||
|
||||
inout [31:0] gpio_bd;
|
||||
|
||||
output hdmi_out_clk;
|
||||
output hdmi_vsync;
|
||||
output hdmi_hsync;
|
||||
output hdmi_data_e;
|
||||
output [15:0] hdmi_data;
|
||||
|
||||
output spdif;
|
||||
|
||||
output i2s_mclk;
|
||||
output i2s_bclk;
|
||||
output i2s_lrclk;
|
||||
output i2s_sdata_out;
|
||||
input i2s_sdata_in;
|
||||
|
||||
inout iic_scl;
|
||||
inout iic_sda;
|
||||
inout [ 1:0] iic_mux_scl;
|
||||
inout [ 1:0] iic_mux_sda;
|
||||
|
||||
input otg_vbusoc;
|
||||
|
||||
input clk_in;
|
||||
input ready_in;
|
||||
input [ 7:0] data_in;
|
||||
|
||||
output spi_csn;
|
||||
output spi_clk;
|
||||
output spi_mosi;
|
||||
input spi_miso;
|
||||
|
||||
inout gpio_0_mode_0;
|
||||
inout gpio_1_mode_1;
|
||||
inout gpio_2_mode_2;
|
||||
inout gpio_3_mode_3;
|
||||
inout gpio_4_filter;
|
||||
inout reset_n;
|
||||
inout start_n;
|
||||
inout sync_n;
|
||||
inout sync_in_n;
|
||||
output mclk;
|
||||
|
||||
// internal signals
|
||||
|
||||
wire adc_clk;
|
||||
wire adc_valid;
|
||||
wire [31:0] adc_data;
|
||||
wire up_sshot;
|
||||
wire [ 1:0] up_format;
|
||||
wire up_crc_enable;
|
||||
wire up_crc_4_or_16_n;
|
||||
wire [63:0] adc_gpio_i;
|
||||
wire [63:0] adc_gpio_o;
|
||||
wire [63:0] adc_gpio_t;
|
||||
wire [63:0] gpio_i;
|
||||
wire [63:0] gpio_o;
|
||||
wire [63:0] gpio_t;
|
||||
wire [ 1:0] iic_mux_scl_i_s;
|
||||
wire [ 1:0] iic_mux_scl_o_s;
|
||||
wire iic_mux_scl_t_s;
|
||||
wire [ 1:0] iic_mux_sda_i_s;
|
||||
wire [ 1:0] iic_mux_sda_o_s;
|
||||
wire iic_mux_sda_t_s;
|
||||
|
||||
// use crystal
|
||||
|
||||
assign mclk = 1'b0;
|
||||
assign up_sshot = gpio_o[36];
|
||||
assign up_format = gpio_o[35:34];
|
||||
assign up_crc_enable = gpio_o[33];
|
||||
assign up_crc_4_or_16_n = gpio_o[32];
|
||||
|
||||
// instantiations
|
||||
|
||||
ad_iobuf #(.DATA_WIDTH(9)) i_iobuf (
|
||||
.dio_t ({gpio_t[52:48], gpio_t[43:40]}),
|
||||
.dio_i ({gpio_o[52:48], gpio_o[43:40]}),
|
||||
.dio_o ({gpio_i[52:48], gpio_i[43:40]}),
|
||||
.dio_p ({ gpio_4_filter, // 52
|
||||
gpio_3_mode_3, // 51
|
||||
gpio_2_mode_2, // 50
|
||||
gpio_1_mode_1, // 49
|
||||
gpio_0_mode_0, // 48
|
||||
sync_in_n, // 43
|
||||
sync_n, // 42
|
||||
start_n, // 41
|
||||
reset_n})); // 40
|
||||
|
||||
ad_iobuf #(.DATA_WIDTH(32)) i_iobuf_bd (
|
||||
.dio_t (gpio_t[31:0]),
|
||||
.dio_i (gpio_o[31:0]),
|
||||
.dio_o (gpio_i[31:0]),
|
||||
.dio_p (gpio_bd));
|
||||
|
||||
ad_iobuf #(.DATA_WIDTH(2)) i_iic_mux_scl (
|
||||
.dio_t ({iic_mux_scl_t_s, iic_mux_scl_t_s}),
|
||||
.dio_i (iic_mux_scl_o_s),
|
||||
.dio_o (iic_mux_scl_i_s),
|
||||
.dio_p (iic_mux_scl));
|
||||
|
||||
ad_iobuf #(.DATA_WIDTH(2)) i_iic_mux_sda (
|
||||
.dio_t ({iic_mux_sda_t_s, iic_mux_sda_t_s}),
|
||||
.dio_i (iic_mux_sda_o_s),
|
||||
.dio_o (iic_mux_sda_i_s),
|
||||
.dio_p (iic_mux_sda));
|
||||
|
||||
ad7768_if i_ad7768_if (
|
||||
.clk_in (clk_in),
|
||||
.ready_in (ready_in),
|
||||
.data_in (data_in),
|
||||
.adc_clk (adc_clk),
|
||||
.adc_valid (adc_valid),
|
||||
.adc_data (adc_data),
|
||||
.up_sshot (up_sshot),
|
||||
.up_format (up_format),
|
||||
.up_crc_enable (up_crc_enable),
|
||||
.up_crc_4_or_16_n (up_crc_4_or_16_n),
|
||||
.up_status_clr (adc_gpio_o[32:0]),
|
||||
.up_status (adc_gpio_i[32:0]));
|
||||
|
||||
system_wrapper i_system_wrapper (
|
||||
.adc_clk (adc_clk),
|
||||
.adc_data (adc_data),
|
||||
.adc_gpio_0_i (adc_gpio_i[31:0]),
|
||||
.adc_gpio_0_o (adc_gpio_o[31:0]),
|
||||
.adc_gpio_0_t (adc_gpio_t[31:0]),
|
||||
.adc_gpio_1_i (adc_gpio_i[63:32]),
|
||||
.adc_gpio_1_o (adc_gpio_o[63:32]),
|
||||
.adc_gpio_1_t (adc_gpio_t[63:32]),
|
||||
.adc_valid (adc_valid),
|
||||
.ddr_addr (ddr_addr),
|
||||
.ddr_ba (ddr_ba),
|
||||
.ddr_cas_n (ddr_cas_n),
|
||||
.ddr_ck_n (ddr_ck_n),
|
||||
.ddr_ck_p (ddr_ck_p),
|
||||
.ddr_cke (ddr_cke),
|
||||
.ddr_cs_n (ddr_cs_n),
|
||||
.ddr_dm (ddr_dm),
|
||||
.ddr_dq (ddr_dq),
|
||||
.ddr_dqs_n (ddr_dqs_n),
|
||||
.ddr_dqs_p (ddr_dqs_p),
|
||||
.ddr_odt (ddr_odt),
|
||||
.ddr_ras_n (ddr_ras_n),
|
||||
.ddr_reset_n (ddr_reset_n),
|
||||
.ddr_we_n (ddr_we_n),
|
||||
.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
|
||||
.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
|
||||
.fixed_io_mio (fixed_io_mio),
|
||||
.fixed_io_ps_clk (fixed_io_ps_clk),
|
||||
.fixed_io_ps_porb (fixed_io_ps_porb),
|
||||
.fixed_io_ps_srstb (fixed_io_ps_srstb),
|
||||
.gpio_i (gpio_i),
|
||||
.gpio_o (gpio_o),
|
||||
.gpio_t (gpio_t),
|
||||
.hdmi_data (hdmi_data),
|
||||
.hdmi_data_e (hdmi_data_e),
|
||||
.hdmi_hsync (hdmi_hsync),
|
||||
.hdmi_out_clk (hdmi_out_clk),
|
||||
.hdmi_vsync (hdmi_vsync),
|
||||
.i2s_bclk (i2s_bclk),
|
||||
.i2s_lrclk (i2s_lrclk),
|
||||
.i2s_mclk (i2s_mclk),
|
||||
.i2s_sdata_in (i2s_sdata_in),
|
||||
.i2s_sdata_out (i2s_sdata_out),
|
||||
.iic_fmc_scl_io (iic_scl),
|
||||
.iic_fmc_sda_io (iic_sda),
|
||||
.iic_mux_scl_i (iic_mux_scl_i_s),
|
||||
.iic_mux_scl_o (iic_mux_scl_o_s),
|
||||
.iic_mux_scl_t (iic_mux_scl_t_s),
|
||||
.iic_mux_sda_i (iic_mux_sda_i_s),
|
||||
.iic_mux_sda_o (iic_mux_sda_o_s),
|
||||
.iic_mux_sda_t (iic_mux_sda_t_s),
|
||||
.otg_vbusoc (otg_vbusoc),
|
||||
.ps_intr_00 (1'b0),
|
||||
.ps_intr_01 (1'b0),
|
||||
.ps_intr_02 (1'b0),
|
||||
.ps_intr_03 (1'b0),
|
||||
.ps_intr_04 (1'b0),
|
||||
.ps_intr_05 (1'b0),
|
||||
.ps_intr_06 (1'b0),
|
||||
.ps_intr_07 (1'b0),
|
||||
.ps_intr_08 (1'b0),
|
||||
.ps_intr_09 (1'b0),
|
||||
.ps_intr_10 (1'b0),
|
||||
.spdif (spdif),
|
||||
.spi0_clk_i (1'b0),
|
||||
.spi0_clk_o (spi_clk),
|
||||
.spi0_csn_0_o (spi_csn),
|
||||
.spi0_csn_1_o (),
|
||||
.spi0_csn_2_o (),
|
||||
.spi0_csn_i (1'b1),
|
||||
.spi0_sdi_i (spi_miso),
|
||||
.spi0_sdo_i (1'b0),
|
||||
.spi0_sdo_o (spi_mosi),
|
||||
.spi1_clk_i (1'b0),
|
||||
.spi1_clk_o (),
|
||||
.spi1_csn_0_o (),
|
||||
.spi1_csn_1_o (),
|
||||
.spi1_csn_2_o (),
|
||||
.spi1_csn_i (1'b1),
|
||||
.spi1_sdi_i (1'b0),
|
||||
.spi1_sdo_i (1'b0),
|
||||
.spi1_sdo_o ());
|
||||
|
||||
endmodule
|
||||
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
Loading…
Reference in New Issue