a10soc- updates
Rejeesh Kutty
parent
d36d1263c5
commit
0a3967b886
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@ -0,0 +1,756 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<system name="$${FILENAME}">
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<component
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name="$${FILENAME}"
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displayName="$${FILENAME}"
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version="1.0"
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description=""
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tags=""
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categories="System" />
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<parameter name="bonusData"><![CDATA[bonusData
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{
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element ad9361_clk_bridge
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{
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datum _sortIndex
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{
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value = "4";
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type = "int";
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}
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}
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element adc_pack
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{
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datum _sortIndex
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{
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value = "6";
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type = "int";
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}
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datum sopceditor_expanded
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{
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value = "1";
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type = "boolean";
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}
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}
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element arradio_bd
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{
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datum _originalDeviceFamily
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{
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value = "Cyclone V";
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type = "String";
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}
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}
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element arradio_bd
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{
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datum _originalDeviceFamily
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{
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value = "Cyclone V";
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type = "String";
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}
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}
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element arradio_bd
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{
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datum _originalDeviceFamily
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{
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value = "Cyclone V";
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type = "String";
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}
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}
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element arradio_bd
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{
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datum _originalDeviceFamily
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{
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value = "Cyclone V";
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type = "String";
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}
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}
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element arradio_bd
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{
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datum _originalDeviceFamily
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{
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value = "Cyclone V";
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type = "String";
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}
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}
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element arradio_bd
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{
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datum _originalDeviceFamily
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{
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value = "Cyclone V";
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type = "String";
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}
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}
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element arradio_bd
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{
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datum _originalDeviceFamily
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{
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value = "Cyclone V";
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type = "String";
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}
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}
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element axi_ad9361
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{
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datum _sortIndex
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{
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value = "5";
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type = "int";
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}
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datum sopceditor_expanded
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{
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value = "1";
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type = "boolean";
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}
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}
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element axi_ad9361.s_axi
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{
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datum baseAddress
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{
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value = "131072";
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type = "String";
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}
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}
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element axi_dmac_adc
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{
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datum _sortIndex
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{
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value = "7";
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type = "int";
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}
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datum sopceditor_expanded
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{
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value = "1";
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type = "boolean";
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}
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}
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element axi_dmac_adc.s_axi
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{
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datum baseAddress
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{
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value = "0";
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type = "String";
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}
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}
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element axi_dmac_dac
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{
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datum _sortIndex
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{
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value = "9";
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type = "int";
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}
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datum sopceditor_expanded
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{
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value = "1";
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type = "boolean";
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}
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}
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element axi_dmac_dac.s_axi
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{
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datum baseAddress
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{
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value = "16384";
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type = "String";
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}
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}
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element dac_upack
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{
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datum _sortIndex
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{
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value = "8";
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type = "int";
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}
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datum sopceditor_expanded
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{
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value = "1";
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type = "boolean";
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}
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}
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element gpio
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{
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datum _sortIndex
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{
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value = "11";
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type = "int";
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}
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}
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element mem_clk
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{
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datum _sortIndex
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{
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value = "2";
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type = "int";
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}
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}
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element mem_rst
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{
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datum _sortIndex
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{
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value = "3";
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type = "int";
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}
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}
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element spi_ad9361
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{
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datum _sortIndex
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{
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value = "10";
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type = "int";
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}
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datum sopceditor_expanded
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{
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value = "1";
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type = "boolean";
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}
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}
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element spi_ad9361.spi_control_port
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{
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datum baseAddress
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{
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value = "32768";
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type = "String";
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}
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}
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element sys_clk
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{
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datum _sortIndex
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{
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value = "0";
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type = "int";
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}
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}
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element sys_rst
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{
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datum _sortIndex
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{
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value = "1";
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type = "int";
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}
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}
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}
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]]></parameter>
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<parameter name="clockCrossingAdapter" value="FIFO" />
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<parameter name="device" value="5CSXFC6D6F31C8ES" />
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<parameter name="deviceFamily" value="Cyclone V" />
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<parameter name="deviceSpeedGrade" value="8_H6" />
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<parameter name="fabricMode" value="QSYS" />
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<parameter name="generateLegacySim" value="false" />
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<parameter name="generationId" value="0" />
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<parameter name="globalResetBus" value="false" />
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<parameter name="hdlLanguage" value="VERILOG" />
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<parameter name="hideFromIPCatalog" value="false" />
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<parameter name="lockedInterfaceDefinition" value="" />
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<parameter name="maxAdditionalLatency" value="2" />
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<parameter name="projectName" value="" />
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<parameter name="sopcBorderPoints" value="false" />
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<parameter name="systemHash" value="0" />
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<parameter name="testBenchDutName" value="" />
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<parameter name="timeStamp" value="0" />
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<parameter name="useTestBenchNamingPattern" value="false" />
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<instanceScript></instanceScript>
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<interface
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name="axi_ad9361_device_clock"
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internal="axi_ad9361.device_clock"
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type="clock"
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dir="end" />
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<interface
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name="axi_ad9361_device_if"
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internal="axi_ad9361.device_if"
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type="conduit"
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dir="end" />
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<interface
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name="axi_ad9361_l_clk"
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internal="ad9361_clk_bridge.out_clk"
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type="clock"
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dir="start" />
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<interface
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name="axi_ad9361_s_axi"
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internal="axi_ad9361.s_axi"
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type="axi4lite"
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dir="end" />
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<interface
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name="axi_dmac_adc_fifo_wr_clock"
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internal="axi_dmac_adc.fifo_wr_clock" />
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<interface name="axi_dmac_adc_fifo_wr_if" internal="axi_dmac_adc.fifo_wr_if" />
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<interface
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name="axi_dmac_adc_intr"
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internal="axi_dmac_adc.interrupt_sender"
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type="interrupt"
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dir="end" />
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<interface
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name="axi_dmac_adc_m_dest_axi"
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internal="axi_dmac_adc.m_dest_axi"
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type="axi4"
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dir="start" />
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<interface
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name="axi_dmac_adc_s_axi"
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internal="axi_dmac_adc.s_axi"
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type="axi4lite"
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dir="end" />
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<interface
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name="axi_dmac_dac_fifo_rd_clock"
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internal="axi_dmac_dac.fifo_rd_clock" />
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<interface name="axi_dmac_dac_fifo_rd_if" internal="axi_dmac_dac.fifo_rd_if" />
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<interface
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name="axi_dmac_dac_intr"
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internal="axi_dmac_dac.interrupt_sender"
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type="interrupt"
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dir="end" />
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<interface
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name="axi_dmac_dac_m_src_axi"
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internal="axi_dmac_dac.m_src_axi"
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type="axi4"
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dir="start" />
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<interface
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name="axi_dmac_dac_s_axi"
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internal="axi_dmac_dac.s_axi"
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type="axi4lite"
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dir="end" />
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<interface
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name="gpio_external_connection"
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internal="gpio.external_connection"
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type="conduit"
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dir="end" />
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<interface name="gpio_s1" internal="gpio.s1" type="avalon" dir="end" />
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<interface name="mem_clk" internal="mem_clk.in_clk" type="clock" dir="end" />
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<interface name="mem_rst" internal="mem_rst.in_reset" type="reset" dir="end" />
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<interface
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name="spi_ad9361_external"
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internal="spi_ad9361.external"
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type="conduit"
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dir="end" />
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<interface
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name="spi_ad9361_irq"
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internal="spi_ad9361.irq"
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type="interrupt"
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dir="end" />
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<interface
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name="spi_ad9361_spi_control_port"
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internal="spi_ad9361.spi_control_port"
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type="avalon"
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dir="end" />
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<interface name="sys_clk" internal="sys_clk.in_clk" type="clock" dir="end" />
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<interface name="sys_rst" internal="sys_rst.in_reset" type="reset" dir="end" />
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<module
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name="ad9361_clk_bridge"
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kind="altera_clock_bridge"
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version="15.1"
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enabled="1">
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<parameter name="DERIVED_CLOCK_RATE" value="0" />
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<parameter name="EXPLICIT_CLOCK_RATE" value="0" />
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<parameter name="NUM_CLOCK_OUTPUTS" value="1" />
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</module>
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<module name="adc_pack" kind="util_cpack" version="1.0" enabled="1">
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<parameter name="CHANNEL_DATA_WIDTH" value="16" />
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<parameter name="NUM_OF_CHANNELS" value="4" />
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</module>
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<module name="axi_ad9361" kind="axi_ad9361" version="1.0" enabled="1">
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<parameter name="DEVICE_TYPE" value="0" />
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<parameter name="ID" value="0" />
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</module>
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<module name="axi_dmac_adc" kind="axi_dmac" version="1.0" enabled="1">
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<parameter name="ASYNC_CLK_DEST_REQ" value="1" />
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<parameter name="ASYNC_CLK_REQ_SRC" value="1" />
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<parameter name="ASYNC_CLK_SRC_DEST" value="1" />
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<parameter name="AXI_SLICE_DEST" value="0" />
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<parameter name="AXI_SLICE_SRC" value="0" />
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<parameter name="CYCLIC" value="0" />
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<parameter name="DMA_2D_TRANSFER" value="0" />
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<parameter name="DMA_DATA_WIDTH_DEST" value="64" />
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<parameter name="DMA_DATA_WIDTH_SRC" value="64" />
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<parameter name="DMA_LENGTH_WIDTH" value="24" />
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<parameter name="DMA_TYPE_DEST" value="0" />
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<parameter name="DMA_TYPE_SRC" value="2" />
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<parameter name="FIFO_SIZE" value="4" />
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<parameter name="ID" value="0" />
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<parameter name="SYNC_TRANSFER_START" value="1" />
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</module>
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<module name="axi_dmac_dac" kind="axi_dmac" version="1.0" enabled="1">
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<parameter name="ASYNC_CLK_DEST_REQ" value="1" />
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<parameter name="ASYNC_CLK_REQ_SRC" value="1" />
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<parameter name="ASYNC_CLK_SRC_DEST" value="1" />
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<parameter name="AXI_SLICE_DEST" value="0" />
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<parameter name="AXI_SLICE_SRC" value="0" />
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<parameter name="CYCLIC" value="1" />
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<parameter name="DMA_2D_TRANSFER" value="0" />
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<parameter name="DMA_DATA_WIDTH_DEST" value="64" />
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<parameter name="DMA_DATA_WIDTH_SRC" value="64" />
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<parameter name="DMA_LENGTH_WIDTH" value="24" />
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<parameter name="DMA_TYPE_DEST" value="2" />
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<parameter name="DMA_TYPE_SRC" value="0" />
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<parameter name="FIFO_SIZE" value="4" />
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<parameter name="ID" value="0" />
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<parameter name="SYNC_TRANSFER_START" value="0" />
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</module>
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<module name="dac_upack" kind="util_upack" version="1.0" enabled="1">
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<parameter name="CHANNEL_DATA_WIDTH" value="16" />
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<parameter name="NUM_OF_CHANNELS" value="4" />
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</module>
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<module name="gpio" kind="altera_avalon_pio" version="15.1" enabled="1">
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<parameter name="bitClearingEdgeCapReg" value="false" />
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<parameter name="bitModifyingOutReg" value="false" />
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<parameter name="captureEdge" value="false" />
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<parameter name="clockRate" value="50000000" />
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<parameter name="direction" value="Output" />
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<parameter name="edgeType" value="RISING" />
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<parameter name="generateIRQ" value="false" />
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<parameter name="irqType" value="LEVEL" />
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<parameter name="resetValue" value="0" />
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<parameter name="simDoTestBenchWiring" value="false" />
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<parameter name="simDrivenValue" value="0" />
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<parameter name="width" value="5" />
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</module>
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<module name="mem_clk" kind="altera_clock_bridge" version="15.1" enabled="1">
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<parameter name="DERIVED_CLOCK_RATE" value="0" />
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<parameter name="EXPLICIT_CLOCK_RATE" value="0" />
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<parameter name="NUM_CLOCK_OUTPUTS" value="1" />
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</module>
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<module name="mem_rst" kind="altera_reset_bridge" version="15.1" enabled="1">
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<parameter name="ACTIVE_LOW_RESET" value="0" />
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<parameter name="AUTO_CLK_CLOCK_RATE" value="-1" />
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<parameter name="NUM_RESET_OUTPUTS" value="1" />
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<parameter name="SYNCHRONOUS_EDGES" value="none" />
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<parameter name="USE_RESET_REQUEST" value="0" />
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</module>
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<module name="spi_ad9361" kind="altera_avalon_spi" version="15.1" enabled="1">
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<parameter name="avalonSpec" value="2.0" />
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<parameter name="clockPhase" value="0" />
|
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<parameter name="clockPolarity" value="1" />
|
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<parameter name="dataWidth" value="8" />
|
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<parameter name="disableAvalonFlowControl" value="false" />
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<parameter name="inputClockRate" value="50000000" />
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<parameter name="insertDelayBetweenSlaveSelectAndSClk" value="false" />
|
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<parameter name="insertSync" value="false" />
|
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<parameter name="lsbOrderedFirst" value="false" />
|
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<parameter name="masterSPI" value="true" />
|
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<parameter name="numberOfSlaves" value="1" />
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<parameter name="syncRegDepth" value="2" />
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<parameter name="targetClockRate" value="50000000" />
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<parameter name="targetSlaveSelectToSClkDelay" value="0.0" />
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</module>
|
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<module name="sys_clk" kind="altera_clock_bridge" version="15.1" enabled="1">
|
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<parameter name="DERIVED_CLOCK_RATE" value="0" />
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<parameter name="EXPLICIT_CLOCK_RATE" value="50000000" />
|
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<parameter name="NUM_CLOCK_OUTPUTS" value="1" />
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</module>
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<module name="sys_rst" kind="altera_reset_bridge" version="15.1" enabled="1">
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<parameter name="ACTIVE_LOW_RESET" value="0" />
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<parameter name="AUTO_CLK_CLOCK_RATE" value="-1" />
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<parameter name="NUM_RESET_OUTPUTS" value="1" />
|
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<parameter name="SYNCHRONOUS_EDGES" value="none" />
|
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<parameter name="USE_RESET_REQUEST" value="0" />
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</module>
|
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<connection
|
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kind="clock"
|
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version="15.1"
|
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start="axi_ad9361.if_l_clk"
|
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end="adc_pack.if_adc_clk" />
|
||||
<connection
|
||||
kind="clock"
|
||||
version="15.1"
|
||||
start="axi_ad9361.if_l_clk"
|
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end="dac_upack.if_dac_clk" />
|
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<connection
|
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kind="clock"
|
||||
version="15.1"
|
||||
start="axi_ad9361.if_l_clk"
|
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end="axi_dmac_dac.if_fifo_rd_clk" />
|
||||
<connection
|
||||
kind="clock"
|
||||
version="15.1"
|
||||
start="axi_ad9361.if_l_clk"
|
||||
end="axi_dmac_adc.if_fifo_wr_clk" />
|
||||
<connection
|
||||
kind="clock"
|
||||
version="15.1"
|
||||
start="axi_ad9361.if_l_clk"
|
||||
end="ad9361_clk_bridge.in_clk" />
|
||||
<connection
|
||||
kind="clock"
|
||||
version="15.1"
|
||||
start="sys_clk.out_clk"
|
||||
end="spi_ad9361.clk" />
|
||||
<connection kind="clock" version="15.1" start="sys_clk.out_clk" end="gpio.clk" />
|
||||
<connection
|
||||
kind="clock"
|
||||
version="15.1"
|
||||
start="sys_clk.out_clk"
|
||||
end="axi_ad9361.delay_clock" />
|
||||
<connection
|
||||
kind="clock"
|
||||
version="15.1"
|
||||
start="mem_clk.out_clk"
|
||||
end="axi_dmac_adc.m_dest_axi_clock" />
|
||||
<connection
|
||||
kind="clock"
|
||||
version="15.1"
|
||||
start="mem_clk.out_clk"
|
||||
end="axi_dmac_dac.m_src_axi_clock" />
|
||||
<connection
|
||||
kind="clock"
|
||||
version="15.1"
|
||||
start="sys_clk.out_clk"
|
||||
end="axi_ad9361.s_axi_clock" />
|
||||
<connection
|
||||
kind="clock"
|
||||
version="15.1"
|
||||
start="sys_clk.out_clk"
|
||||
end="axi_dmac_adc.s_axi_clock" />
|
||||
<connection
|
||||
kind="clock"
|
||||
version="15.1"
|
||||
start="sys_clk.out_clk"
|
||||
end="axi_dmac_dac.s_axi_clock" />
|
||||
<connection
|
||||
kind="conduit"
|
||||
version="15.1"
|
||||
start="dac_upack.fifo_ch_0"
|
||||
end="axi_ad9361.fifo_ch_0_out">
|
||||
<parameter name="endPort" value="" />
|
||||
<parameter name="endPortLSB" value="0" />
|
||||
<parameter name="startPort" value="" />
|
||||
<parameter name="startPortLSB" value="0" />
|
||||
<parameter name="width" value="0" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="conduit"
|
||||
version="15.1"
|
||||
start="axi_ad9361.fifo_ch_0_in"
|
||||
end="adc_pack.fifo_ch_0">
|
||||
<parameter name="endPort" value="" />
|
||||
<parameter name="endPortLSB" value="0" />
|
||||
<parameter name="startPort" value="" />
|
||||
<parameter name="startPortLSB" value="0" />
|
||||
<parameter name="width" value="0" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="conduit"
|
||||
version="15.1"
|
||||
start="axi_ad9361.fifo_ch_1_in"
|
||||
end="adc_pack.fifo_ch_1">
|
||||
<parameter name="endPort" value="" />
|
||||
<parameter name="endPortLSB" value="0" />
|
||||
<parameter name="startPort" value="" />
|
||||
<parameter name="startPortLSB" value="0" />
|
||||
<parameter name="width" value="0" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="conduit"
|
||||
version="15.1"
|
||||
start="axi_ad9361.fifo_ch_1_out"
|
||||
end="dac_upack.fifo_ch_1">
|
||||
<parameter name="endPort" value="" />
|
||||
<parameter name="endPortLSB" value="0" />
|
||||
<parameter name="startPort" value="" />
|
||||
<parameter name="startPortLSB" value="0" />
|
||||
<parameter name="width" value="0" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="conduit"
|
||||
version="15.1"
|
||||
start="axi_ad9361.fifo_ch_2_in"
|
||||
end="adc_pack.fifo_ch_2">
|
||||
<parameter name="endPort" value="" />
|
||||
<parameter name="endPortLSB" value="0" />
|
||||
<parameter name="startPort" value="" />
|
||||
<parameter name="startPortLSB" value="0" />
|
||||
<parameter name="width" value="0" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="conduit"
|
||||
version="15.1"
|
||||
start="axi_ad9361.fifo_ch_2_out"
|
||||
end="dac_upack.fifo_ch_2">
|
||||
<parameter name="endPort" value="" />
|
||||
<parameter name="endPortLSB" value="0" />
|
||||
<parameter name="startPort" value="" />
|
||||
<parameter name="startPortLSB" value="0" />
|
||||
<parameter name="width" value="0" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="conduit"
|
||||
version="15.1"
|
||||
start="axi_ad9361.fifo_ch_3_in"
|
||||
end="adc_pack.fifo_ch_3">
|
||||
<parameter name="endPort" value="" />
|
||||
<parameter name="endPortLSB" value="0" />
|
||||
<parameter name="startPort" value="" />
|
||||
<parameter name="startPortLSB" value="0" />
|
||||
<parameter name="width" value="0" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="conduit"
|
||||
version="15.1"
|
||||
start="axi_ad9361.fifo_ch_3_out"
|
||||
end="dac_upack.fifo_ch_3">
|
||||
<parameter name="endPort" value="" />
|
||||
<parameter name="endPortLSB" value="0" />
|
||||
<parameter name="startPort" value="" />
|
||||
<parameter name="startPortLSB" value="0" />
|
||||
<parameter name="width" value="0" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="conduit"
|
||||
version="15.1"
|
||||
start="adc_pack.if_adc_data"
|
||||
end="axi_dmac_adc.if_fifo_wr_din">
|
||||
<parameter name="endPort" value="" />
|
||||
<parameter name="endPortLSB" value="0" />
|
||||
<parameter name="startPort" value="" />
|
||||
<parameter name="startPortLSB" value="0" />
|
||||
<parameter name="width" value="0" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="conduit"
|
||||
version="15.1"
|
||||
start="adc_pack.if_adc_sync"
|
||||
end="axi_dmac_adc.if_fifo_wr_sync">
|
||||
<parameter name="endPort" value="" />
|
||||
<parameter name="endPortLSB" value="0" />
|
||||
<parameter name="startPort" value="" />
|
||||
<parameter name="startPortLSB" value="0" />
|
||||
<parameter name="width" value="0" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="conduit"
|
||||
version="15.1"
|
||||
start="adc_pack.if_adc_valid"
|
||||
end="axi_dmac_adc.if_fifo_wr_en">
|
||||
<parameter name="endPort" value="" />
|
||||
<parameter name="endPortLSB" value="0" />
|
||||
<parameter name="startPort" value="" />
|
||||
<parameter name="startPortLSB" value="0" />
|
||||
<parameter name="width" value="0" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="conduit"
|
||||
version="15.1"
|
||||
start="dac_upack.if_dac_data"
|
||||
end="axi_dmac_dac.if_fifo_rd_dout">
|
||||
<parameter name="endPort" value="" />
|
||||
<parameter name="endPortLSB" value="0" />
|
||||
<parameter name="startPort" value="" />
|
||||
<parameter name="startPortLSB" value="0" />
|
||||
<parameter name="width" value="0" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="conduit"
|
||||
version="15.1"
|
||||
start="dac_upack.if_dma_xfer_in"
|
||||
end="axi_dmac_dac.if_fifo_rd_xfer_req">
|
||||
<parameter name="endPort" value="" />
|
||||
<parameter name="endPortLSB" value="0" />
|
||||
<parameter name="startPort" value="" />
|
||||
<parameter name="startPortLSB" value="0" />
|
||||
<parameter name="width" value="0" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="conduit"
|
||||
version="15.1"
|
||||
start="axi_dmac_dac.if_fifo_rd_en"
|
||||
end="dac_upack.if_dac_valid">
|
||||
<parameter name="endPort" value="" />
|
||||
<parameter name="endPortLSB" value="0" />
|
||||
<parameter name="startPort" value="" />
|
||||
<parameter name="startPortLSB" value="0" />
|
||||
<parameter name="width" value="0" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="conduit"
|
||||
version="15.1"
|
||||
start="axi_dmac_dac.if_fifo_rd_underflow"
|
||||
end="axi_ad9361.if_dac_dunf">
|
||||
<parameter name="endPort" value="" />
|
||||
<parameter name="endPortLSB" value="0" />
|
||||
<parameter name="startPort" value="" />
|
||||
<parameter name="startPortLSB" value="0" />
|
||||
<parameter name="width" value="0" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="conduit"
|
||||
version="15.1"
|
||||
start="axi_dmac_adc.if_fifo_wr_overflow"
|
||||
end="axi_ad9361.if_adc_dovf">
|
||||
<parameter name="endPort" value="" />
|
||||
<parameter name="endPortLSB" value="0" />
|
||||
<parameter name="startPort" value="" />
|
||||
<parameter name="startPortLSB" value="0" />
|
||||
<parameter name="width" value="0" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="reset"
|
||||
version="15.1"
|
||||
start="axi_ad9361.if_rst"
|
||||
end="adc_pack.if_adc_rst" />
|
||||
<connection
|
||||
kind="reset"
|
||||
version="15.1"
|
||||
start="sys_rst.out_reset"
|
||||
end="adc_pack.if_adc_rst" />
|
||||
<connection
|
||||
kind="reset"
|
||||
version="15.1"
|
||||
start="mem_rst.out_reset"
|
||||
end="adc_pack.if_adc_rst" />
|
||||
<connection
|
||||
kind="reset"
|
||||
version="15.1"
|
||||
start="mem_rst.out_reset"
|
||||
end="axi_dmac_adc.m_dest_axi_reset" />
|
||||
<connection
|
||||
kind="reset"
|
||||
version="15.1"
|
||||
start="mem_rst.out_reset"
|
||||
end="axi_dmac_dac.m_src_axi_reset" />
|
||||
<connection
|
||||
kind="reset"
|
||||
version="15.1"
|
||||
start="sys_rst.out_reset"
|
||||
end="spi_ad9361.reset" />
|
||||
<connection
|
||||
kind="reset"
|
||||
version="15.1"
|
||||
start="sys_rst.out_reset"
|
||||
end="gpio.reset" />
|
||||
<connection
|
||||
kind="reset"
|
||||
version="15.1"
|
||||
start="sys_rst.out_reset"
|
||||
end="axi_ad9361.s_axi_reset" />
|
||||
<connection
|
||||
kind="reset"
|
||||
version="15.1"
|
||||
start="sys_rst.out_reset"
|
||||
end="axi_dmac_adc.s_axi_reset" />
|
||||
<connection
|
||||
kind="reset"
|
||||
version="15.1"
|
||||
start="sys_rst.out_reset"
|
||||
end="axi_dmac_dac.s_axi_reset" />
|
||||
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="FIFO" />
|
||||
<interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="2" />
|
||||
<interconnectRequirement
|
||||
for="mm_interconnect_0|cmd_mux"
|
||||
name="qsys_mm.postTransform.pipelineCount"
|
||||
value="0" />
|
||||
<interconnectRequirement
|
||||
for="mm_interconnect_2|cmd_mux"
|
||||
name="qsys_mm.postTransform.pipelineCount"
|
||||
value="0" />
|
||||
<interconnectRequirement
|
||||
for="mm_interconnect_3|cmd_mux"
|
||||
name="qsys_mm.postTransform.pipelineCount"
|
||||
value="0" />
|
||||
<interconnectRequirement
|
||||
for="mm_interconnect_3|cmd_mux_001"
|
||||
name="qsys_mm.postTransform.pipelineCount"
|
||||
value="0" />
|
||||
<interconnectRequirement
|
||||
for="mm_interconnect_4|axi_dmac_dac_m_src_axi_agent.write_cp/router.sink"
|
||||
name="qsys_mm.postTransform.pipelineCount"
|
||||
value="0" />
|
||||
<interconnectRequirement
|
||||
for="mm_interconnect_4|cmd_mux"
|
||||
name="qsys_mm.postTransform.pipelineCount"
|
||||
value="0" />
|
||||
<interconnectRequirement
|
||||
for="mm_interconnect_4|cmd_mux_001"
|
||||
name="qsys_mm.postTransform.pipelineCount"
|
||||
value="0" />
|
||||
</system>
|
||||
Loading…
Reference in New Issue