adi_board.tcl: ad_xcvrcon: Handle ADI JESD204 core
Let the ad_xcvrcon handle the ADI JESD204 link layer cores. The function will detect the JESD204 core vendor and connect the appropriate signals based on it. This means it can still be used with the Xilinx JESD204 core as well. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>main
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1202286c3d
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0a72693d4d
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@ -178,6 +178,24 @@ proc ad_xcvrcon {u_xcvr a_xcvr a_jesd} {
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set qpll_enable [get_property CONFIG.QPLL_ENABLE [get_bd_cells $a_xcvr]]
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set qpll_enable [get_property CONFIG.QPLL_ENABLE [get_bd_cells $a_xcvr]]
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set tx_or_rx_n [get_property CONFIG.TX_OR_RX_N [get_bd_cells $a_xcvr]]
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set tx_or_rx_n [get_property CONFIG.TX_OR_RX_N [get_bd_cells $a_xcvr]]
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# set jesd204_vlnv [get_property VLNV $a_jesd]
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#
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# if {[string first "analog.com" $jesd204_vlnv] == 0} {
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# set jesd204_type 0
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# } elseif {[string first "xilinx.com" $jesd204_vlnv] == 0} {
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# set jesd204_type 1
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# } else {
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# return -code 1 "Unsupported JESD204 core type."
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# }
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set jesd204_bd_type [get_property TYPE [get_bd_cells $a_jesd]]
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if {$jesd204_bd_type == "hier"} {
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set jesd204_type 0
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} else {
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set jesd204_type 1
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}
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if {$xcvr_instance ne $u_xcvr} {
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if {$xcvr_instance ne $u_xcvr} {
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set xcvr_index [expr ($xcvr_index + 1)]
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set xcvr_index [expr ($xcvr_index + 1)]
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set xcvr_tx_index 0
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set xcvr_tx_index 0
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@ -219,16 +237,24 @@ proc ad_xcvrcon {u_xcvr a_xcvr a_jesd} {
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if {$tx_or_rx_n == 0} {
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if {$tx_or_rx_n == 0} {
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ad_connect ${a_xcvr}/up_es_${n} ${u_xcvr}/up_es_${m}
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ad_connect ${a_xcvr}/up_es_${n} ${u_xcvr}/up_es_${m}
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if {$jesd204_type == 0} {
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ad_connect ${a_jesd}/phy_en_char_align ${u_xcvr}/${txrx}_calign_${m}
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} else {
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ad_connect ${a_jesd}/rxencommaalign_out ${u_xcvr}/${txrx}_calign_${m}
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ad_connect ${a_jesd}/rxencommaalign_out ${u_xcvr}/${txrx}_calign_${m}
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}
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}
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}
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if {(($m%4) == 0) && ($qpll_enable == 1)} {
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if {(($m%4) == 0) && ($qpll_enable == 1)} {
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ad_connect ${a_xcvr}/up_cm_${n} ${u_xcvr}/up_cm_${m}
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ad_connect ${a_xcvr}/up_cm_${n} ${u_xcvr}/up_cm_${m}
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}
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}
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ad_connect ${a_xcvr}/up_ch_${n} ${u_xcvr}/up_${txrx}_${m}
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ad_connect ${a_xcvr}/up_ch_${n} ${u_xcvr}/up_${txrx}_${m}
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ad_connect ${u_xcvr}/${txrx}_${m} ${a_jesd}/gt${n}_${txrx}
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ad_connect ${u_xcvr}/${txrx}_out_clk_${index} ${u_xcvr}/${txrx}_clk_${m}
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ad_connect ${u_xcvr}/${txrx}_out_clk_${index} ${u_xcvr}/${txrx}_clk_${m}
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if {$jesd204_type == 0} {
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ad_connect ${u_xcvr}/${txrx}_${m} ${a_jesd}/${txrx}_phy${n}
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} else {
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ad_connect ${u_xcvr}/${txrx}_${m} ${a_jesd}/gt${n}_${txrx}
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}
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create_bd_port -dir ${data_dir} ${m_data}_${m}_p
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create_bd_port -dir ${data_dir} ${m_data}_${m}_p
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create_bd_port -dir ${data_dir} ${m_data}_${m}_n
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create_bd_port -dir ${data_dir} ${m_data}_${m}_n
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@ -236,13 +262,23 @@ proc ad_xcvrcon {u_xcvr a_xcvr a_jesd} {
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ad_connect ${u_xcvr}/${txrx}_${m}_n ${m_data}_${m}_n
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ad_connect ${u_xcvr}/${txrx}_${m}_n ${m_data}_${m}_n
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}
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}
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if {$jesd204_type == 0} {
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ad_connect ${a_jesd}/sysref $m_sysref
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ad_connect ${a_jesd}/sync $m_sync
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ad_connect ${u_xcvr}/${txrx}_out_clk_${index} ${a_jesd}/device_clk
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# if {$tx_or_rx_n == 0} {
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# ad_connect ${a_xcvr}/up_status ${a_jesd}/phy_ready
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# }
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} else {
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ad_connect ${a_jesd}/${txrx}_sysref $m_sysref
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ad_connect ${a_jesd}/${txrx}_sysref $m_sysref
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ad_connect ${a_jesd}/${txrx}_sync $m_sync
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ad_connect ${a_jesd}/${txrx}_sync $m_sync
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ad_connect ${u_xcvr}/${txrx}_out_clk_${index} ${a_jesd}/${txrx}_core_clk
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ad_connect ${u_xcvr}/${txrx}_out_clk_${index} ${a_jesd}/${txrx}_core_clk
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ad_connect ${a_xcvr}/up_status ${a_jesd}/${txrx}_reset_done
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ad_connect ${a_xcvr}/up_status ${a_jesd}/${txrx}_reset_done
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ad_connect ${a_jesd}_rstgen/peripheral_reset ${a_jesd}/${txrx}_reset
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}
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ad_connect ${u_xcvr}/${txrx}_out_clk_${index} ${a_jesd}_rstgen/slowest_sync_clk
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ad_connect ${u_xcvr}/${txrx}_out_clk_${index} ${a_jesd}_rstgen/slowest_sync_clk
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ad_connect sys_cpu_resetn ${a_jesd}_rstgen/ext_reset_in
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ad_connect sys_cpu_resetn ${a_jesd}_rstgen/ext_reset_in
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ad_connect ${a_jesd}_rstgen/peripheral_reset ${a_jesd}/${txrx}_reset
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if {$tx_or_rx_n == 0} {
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if {$tx_or_rx_n == 0} {
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set xcvr_rx_index [expr ($xcvr_rx_index + $no_of_lanes)]
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set xcvr_rx_index [expr ($xcvr_rx_index + $no_of_lanes)]
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