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daq2+base: board tcl updates

main
Rejeesh Kutty 2015-03-05 10:56:06 -05:00
parent 7fba7cc6e5
commit 0ac1676318
1 changed files with 97 additions and 38 deletions
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135
projects/scripts/adi_board.tcl
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@ -1,9 +1,6 @@
###################################################################################################
###################################################################################################
variable sys_zynq
variable sys_ddr_addr_seg
variable sys_addr_cntrl_space
variable sys_cpu_interconnect_index
variable sys_hp0_interconnect_index
variable sys_hp1_interconnect_index
@ -31,12 +28,12 @@ proc ad_connect_type {p_name} {
set m_name ""
if {$m_name eq ""} {set m_name [get_bd_nets -quiet $p_name]}
if {$m_name eq ""} {set m_name [get_bd_pins -quiet $p_name]}
if {$m_name eq ""} {set m_name [get_bd_ports -quiet $p_name]}
if {$m_name eq ""} {set m_name [get_bd_intf_nets -quiet $p_name]}
if {$m_name eq ""} {set m_name [get_bd_intf_pins -quiet $p_name]}
if {$m_name eq ""} {set m_name [get_bd_ports -quiet $p_name]}
if {$m_name eq ""} {set m_name [get_bd_intf_ports -quiet $p_name]}
if {$m_name eq ""} {set m_name [get_bd_nets -quiet $p_name]}
if {$m_name eq ""} {set m_name [get_bd_intf_nets -quiet $p_name]}
return $m_name
}
@ -46,6 +43,16 @@ proc ad_connect {p_name_1 p_name_2} {
set m_name_1 [ad_connect_type $p_name_1]
set m_name_2 [ad_connect_type $p_name_2]
if {$m_name_1 eq ""} {
if {[get_property CLASS $m_name_2] eq "bd_intf_pin"} {
create_bd_intf_net $p_name_1
}
if {[get_property CLASS $m_name_2] eq "bd_pin"} {
create_bd_net $p_name_1
}
set m_name_1 [ad_connect_type $p_name_1]
}
if {[get_property CLASS $m_name_1] eq "bd_intf_pin"} {
connect_bd_intf_net $m_name_1 $m_name_2
return
@ -57,8 +64,7 @@ proc ad_connect {p_name_1 p_name_2} {
}
if {[get_property CLASS $m_name_1] eq "bd_net"} {
set m_source_1 [filter [get_bd_pins -of_objects [get_bd_nets $m_name_1]] -regexp "DIR == O"]
connect_bd_net -net $m_name_1 $m_name_2 $m_source_1
connect_bd_net -net $m_name_1 $m_name_2
return
}
}
@ -70,6 +76,7 @@ proc ad_mem_hp0_interconnect {p_clk p_name} {
global sys_zynq
if {($sys_zynq == 0) && ($p_name eq "sys_ps7/S_AXI_HP0")} {return}
if {$sys_zynq == 0} {ad_mem_hpx_interconnect "MEM" $p_clk $p_name}
if {$sys_zynq == 1} {ad_mem_hpx_interconnect "HP0" $p_clk $p_name}
}
@ -78,6 +85,7 @@ proc ad_mem_hp1_interconnect {p_clk p_name} {
global sys_zynq
if {($sys_zynq == 0) && ($p_name eq "sys_ps7/S_AXI_HP1")} {return}
if {$sys_zynq == 0} {ad_mem_hpx_interconnect "MEM" $p_clk $p_name}
if {$sys_zynq == 1} {ad_mem_hpx_interconnect "HP1" $p_clk $p_name}
}
@ -86,14 +94,16 @@ proc ad_mem_hp2_interconnect {p_clk p_name} {
global sys_zynq
if {($sys_zynq == 0) && ($p_name eq "sys_ps7/S_AXI_HP2")} {return}
if {$sys_zynq == 0} {ad_mem_hpx_interconnect "MEM" $p_clk $p_name}
if {$sys_zynq == 1} {ad_mem_hpx_interconnect "HP2" $p_clk $p_name}
}
proc ad_mem_hp3_interconnect {p_name p_clk} {
proc ad_mem_hp3_interconnect {p_clk p_name} {
global sys_zynq
if {($sys_zynq == 0) && ($p_name eq "sys_ps7/S_AXI_HP3")} {return}
if {$sys_zynq == 0} {ad_mem_hpx_interconnect "MEM" $p_clk $p_name}
if {$sys_zynq == 1} {ad_mem_hpx_interconnect "HP3" $p_clk $p_name}
}
@ -113,34 +123,53 @@ proc ad_mem_hpx_interconnect {p_sel p_clk p_name} {
set p_intf_name [lrange [split $p_name "/"] end end]
set p_cell_name [lrange [split $p_name "/"] 0 0]
set p_intf_clock [filter [get_bd_pins -quiet -of_objects [get_bd_cells $p_cell_name]] \
-regexp "CONFIG.ASSOCIATED_BUSIF == ${p_intf_name}"]
set p_intf_clock [get_bd_pins -filter "TYPE == clk && (CONFIG.ASSOCIATED_BUSIF == ${p_intf_name} || \
CONFIG.ASSOCIATED_BUSIF =~ ${p_intf_name}:* || CONFIG.ASSOCIATED_BUSIF =~ *:${p_intf_name} || \
CONFIG.ASSOCIATED_BUSIF =~ *:${p_intf_name}:*)" -quiet -of_objects [get_bd_cells $p_cell_name]]
if {[find_bd_objs -quiet -relation connected_to $p_intf_clock] ne ""} {
set p_intf_clock ""
}
if {$p_sel eq "MEM"} {
if {$sys_mem_interconnect_index < 0} {
create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_mem_interconnect
}
set m_interconnect_index $sys_mem_interconnect_index
set m_interconnect_cell [get_bd_cells axi_mem_interconnect]
set m_addr_seg $sys_ddr_addr_seg
set m_addr_seg [get_bd_addr_segs -of_objects [get_bd_cells axi_ddr_cntrl]]
}
if {$p_sel eq "HP0"} {
if {$sys_hp0_interconnect_index < 0} {
create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_hp0_interconnect
}
set m_interconnect_index $sys_hp0_interconnect_index
set m_interconnect_cell [get_bd_cells axi_hp0_interconnect]
set m_addr_seg [get_bd_addr_segs sys_ps7/S_AXI_HP0/HP0_DDR_LOWOCM]
}
if {$p_sel eq "HP1"} {
if {$sys_hp1_interconnect_index < 0} {
create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_hp1_interconnect
}
set m_interconnect_index $sys_hp1_interconnect_index
set m_interconnect_cell [get_bd_cells axi_hp1_interconnect]
set m_addr_seg [get_bd_addr_segs sys_ps7/S_AXI_HP1/HP1_DDR_LOWOCM]
}
if {$p_sel eq "HP2"} {
if {$sys_hp2_interconnect_index < 0} {
create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_hp2_interconnect
}
set m_interconnect_index $sys_hp2_interconnect_index
set m_interconnect_cell [get_bd_cells axi_hp2_interconnect]
set m_addr_seg [get_bd_addr_segs sys_ps7/S_AXI_HP2/HP2_DDR_LOWOCM]
}
if {$p_sel eq "HP3"} {
if {$sys_hp3_interconnect_index < 0} {
create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_hp3_interconnect
}
set m_interconnect_index $sys_hp3_interconnect_index
set m_interconnect_cell [get_bd_cells axi_hp3_interconnect]
set m_addr_seg [get_bd_addr_segs sys_ps7/S_AXI_HP3/HP3_DDR_LOWOCM]
@ -152,22 +181,26 @@ proc ad_mem_hpx_interconnect {p_sel p_clk p_name} {
}
set m_interconnect_index [expr $m_interconnect_index + 1]
set_property CONFIG.NUM_MI 1 $m_interconnect_cell
if {$m_interconnect_index == 0} {
set_property CONFIG.NUM_MI 1 $m_interconnect_cell
set_property CONFIG.NUM_SI 1 $m_interconnect_cell
ad_connect sys_cpu_resetn $m_interconnect_cell/ARESETN
ad_connect $p_clk $m_interconnect_cell/ACLK
ad_connect sys_cpu_resetn $m_interconnect_cell/M00_ARESETN
ad_connect $p_clk $m_interconnect_cell/M00_ACLK
ad_connect $m_interconnect_cell/M00_AXI $p_name
ad_connect $p_clk $p_intf_clock
if {$p_intf_clock ne ""} {
ad_connect $p_clk $p_intf_clock
}
} else {
set_property CONFIG.NUM_SI $m_interconnect_index $m_interconnect_cell
ad_connect sys_cpu_resetn $m_interconnect_cell/${i_str}_ARESETN
ad_connect $p_clk $m_interconnect_cell/${i_str}_ACLK
ad_connect $m_interconnect_cell/${i_str}_AXI $p_name
ad_connect $p_clk $p_intf_clock
if {$p_intf_clock ne ""} {
ad_connect $p_clk $p_intf_clock
}
assign_bd_address $m_addr_seg
}
@ -184,7 +217,6 @@ proc ad_mem_hpx_interconnect {p_sel p_clk p_name} {
proc ad_cpu_interconnect {p_address p_name} {
global sys_zynq
global sys_addr_cntrl_space
global sys_cpu_interconnect_index
set i_str "M$sys_cpu_interconnect_index"
@ -192,37 +224,65 @@ proc ad_cpu_interconnect {p_address p_name} {
set i_str "M0$sys_cpu_interconnect_index"
}
if {($sys_cpu_interconnect_index == 0) && ($sys_zynq == 1)} {
ad_connect sys_cpu_clk sys_ps7/M_AXI_GP0_ACLK
ad_connect sys_cpu_clk axi_cpu_interconnect/ACLK
ad_connect sys_cpu_clk axi_cpu_interconnect/S00_ACLK
ad_connect sys_cpu_resetn axi_cpu_interconnect/ARESETN
ad_connect sys_cpu_resetn axi_cpu_interconnect/S00_ARESETN
ad_connect axi_cpu_interconnect/S00_AXI sys_ps7/M_AXI_GP0
if {$sys_cpu_interconnect_index == 0} {
create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_cpu_interconnect
if {$sys_zynq == 1} {
ad_connect sys_cpu_clk sys_ps7/M_AXI_GP0_ACLK
ad_connect sys_cpu_clk axi_cpu_interconnect/ACLK
ad_connect sys_cpu_clk axi_cpu_interconnect/S00_ACLK
ad_connect sys_cpu_resetn axi_cpu_interconnect/ARESETN
ad_connect sys_cpu_resetn axi_cpu_interconnect/S00_ARESETN
ad_connect axi_cpu_interconnect/S00_AXI sys_ps7/M_AXI_GP0
} else {
ad_connect sys_cpu_clk axi_cpu_interconnect/ACLK
ad_connect sys_cpu_clk axi_cpu_interconnect/S00_ACLK
ad_connect sys_cpu_resetn axi_cpu_interconnect/ARESETN
ad_connect sys_cpu_resetn axi_cpu_interconnect/S00_ARESETN
ad_connect axi_cpu_interconnect/S00_AXI sys_mb/M_AXI_DP
}
}
if {($sys_cpu_interconnect_index == 0) && ($sys_zynq == 0)} {
ad_connect sys_cpu_clk axi_cpu_interconnect/ACLK
ad_connect sys_cpu_clk axi_cpu_interconnect/S00_ACLK
ad_connect sys_cpu_resetn axi_cpu_interconnect/ARESETN
ad_connect sys_cpu_resetn axi_cpu_interconnect/S00_ARESETN
ad_connect axi_cpu_interconnect/S00_AXI sys_mb/M_AXI_DP
if {$sys_zynq == 1} {
set sys_addr_cntrl_space [get_bd_addr_spaces sys_ps7/Data]
} else {
set sys_addr_cntrl_space [get_bd_addr_spaces sys_mb/Data]
}
set sys_cpu_interconnect_index [expr $sys_cpu_interconnect_index + 1]
set p_intf [filter [get_bd_intf_pins -of_objects [get_bd_cells $p_name]] \
-regexp "MODE == Slave && VLNV == xilinx.com:interface:aximm_rtl:1.0"]
set p_intf [get_bd_intf_pins -filter "MODE == Slave && VLNV == xilinx.com:interface:aximm_rtl:1.0"\
-of_objects [get_bd_cells $p_name]]
set p_intf_name [lrange [split $p_intf "/"] end end]
set p_intf_clock [filter [get_bd_pins -quiet -of_objects [get_bd_cells $p_name]] \
-regexp "CONFIG.ASSOCIATED_BUSIF == ${p_intf_name}"]
set p_intf_reset [get_property CONFIG.ASSOCIATED_RESET [get_bd_pins ${p_intf_clock}]]
set p_intf_clock [get_bd_pins -filter "TYPE == clk && (CONFIG.ASSOCIATED_BUSIF == ${p_intf_name} || \
CONFIG.ASSOCIATED_BUSIF =~ ${p_intf_name}:* || CONFIG.ASSOCIATED_BUSIF =~ *:${p_intf_name} || \
CONFIG.ASSOCIATED_BUSIF =~ *:${p_intf_name}:*)" -quiet -of_objects [get_bd_cells $p_name]]
set p_intf_reset [get_bd_pins -filter "TYPE == rst && (CONFIG.ASSOCIATED_BUSIF == ${p_intf_name} || \
CONFIG.ASSOCIATED_BUSIF =~ ${p_intf_name}:* || CONFIG.ASSOCIATED_BUSIF =~ *:${p_intf_name} || \
CONFIG.ASSOCIATED_BUSIF =~ *:${p_intf_name}:*)" -quiet -of_objects [get_bd_cells $p_name]]
if {($p_intf_clock ne "") && ($p_intf_reset eq "")} {
set p_intf_reset [get_property CONFIG.ASSOCIATED_RESET [get_bd_pins ${p_intf_clock}]]
if {$p_intf_reset ne ""} {
set p_intf_reset [get_bd_pins $p_name/$p_intf_reset]
}
}
if {[find_bd_objs -quiet -relation connected_to $p_intf_clock] ne ""} {
set p_intf_clock ""
}
if {$p_intf_reset ne ""} {
if {[find_bd_objs -quiet -relation connected_to $p_intf_reset] ne ""} {
set p_intf_reset ""
}
}
set_property CONFIG.NUM_MI $sys_cpu_interconnect_index [get_bd_cells axi_cpu_interconnect]
ad_connect sys_cpu_clk axi_cpu_interconnect/${i_str}_ACLK
ad_connect sys_cpu_clk ${p_intf_clock}
if {$p_intf_clock ne ""} {
ad_connect sys_cpu_clk ${p_intf_clock}
}
ad_connect sys_cpu_resetn axi_cpu_interconnect/${i_str}_ARESETN
ad_connect sys_cpu_resetn ${p_name}/${p_intf_reset}
if {$p_intf_reset ne ""} {
ad_connect sys_cpu_resetn ${p_intf_reset}
}
ad_connect axi_cpu_interconnect/${i_str}_AXI ${p_intf}
set p_seg [get_bd_addr_segs -of_objects [get_bd_cells $p_name]]
@ -256,8 +316,7 @@ proc ad_cpu_interrupt {p_index p_name} {
}
set sys_interrupts_q($p_index) $p_name
set p_intr [filter [get_bd_pins -quiet -of_objects [get_bd_cells $p_name]] \
-regexp "TYPE == intr"]
set p_intr [get_bd_pins -filter "TYPE == intr" -quiet -of_objects [get_bd_cells $p_name]]
connect_bd_net -net "${p_name}_intr" \
[get_bd_pins sys_concat_intc/${i_str}] \