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adi_board.tcl: reset xilinx ip using cpu clock

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Rejeesh Kutty 2017-06-08 10:16:43 -04:00
parent ce90769cd8
commit 0b450a3dd7
1 changed files with 1 additions and 1 deletions
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2
projects/scripts/adi_board.tcl
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@ -214,7 +214,7 @@ proc ad_xcvrcon {u_xcvr a_xcvr a_jesd} {
ad_connect ${a_jesd}/${txrx}_sync $m_sync
ad_connect ${u_xcvr}/${txrx}_out_clk_${index} ${a_jesd}/${txrx}_core_clk
ad_connect ${a_xcvr}/up_status ${a_jesd}/${txrx}_reset_done
ad_connect ${u_xcvr}/${txrx}_out_clk_${index} ${a_jesd}_rstgen/slowest_sync_clk
ad_connect sys_cpu_clk ${a_jesd}_rstgen/slowest_sync_clk
ad_connect sys_cpu_resetn ${a_jesd}_rstgen/ext_reset_in
ad_connect ${a_jesd}_rstgen/peripheral_reset ${a_jesd}/${txrx}_reset