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daq2/vc707- 2016.2 updates

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Rejeesh Kutty 2016-08-17 10:34:06 -04:00
parent ce1fed1ce6
commit 0b6fbf2208
3 changed files with 18 additions and 11 deletions
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4
projects/daq2/vc707/system_constr.xdc
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@ -56,6 +56,6 @@ set_property -dict {PACKAGE_PIN G42 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports
create_clock -name tx_ref_clk -period 2.00 [get_ports tx_ref_clk_p] create_clock -name tx_ref_clk -period 2.00 [get_ports tx_ref_clk_p]
create_clock -name rx_ref_clk -period 2.00 [get_ports rx_ref_clk_p] create_clock -name rx_ref_clk -period 2.00 [get_ports rx_ref_clk_p]
create_clock -name tx_div_clk -period 4.00 [get_pins i_system_wrapper/system_i/axi_daq2_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/TXOUTCLK] create_clock -name tx_div_clk -period 4.00 [get_pins i_system_wrapper/system_i/util_daq2_xcvr/inst/i_xch_0/i_gtxe2_channel/TXOUTCLK]
create_clock -name rx_div_clk -period 4.00 [get_pins i_system_wrapper/system_i/axi_daq2_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK] create_clock -name rx_div_clk -period 4.00 [get_pins i_system_wrapper/system_i/util_daq2_xcvr/inst/i_xch_0/i_gtxe2_channel/RXOUTCLK]

5
projects/daq2/vc707/system_project.tcl
View File

@ -1,6 +1,4 @@
source ../../scripts/adi_env.tcl source ../../scripts/adi_env.tcl
source $ad_hdl_dir/projects/scripts/adi_project.tcl source $ad_hdl_dir/projects/scripts/adi_project.tcl
source $ad_hdl_dir/projects/scripts/adi_board.tcl source $ad_hdl_dir/projects/scripts/adi_board.tcl
@ -13,9 +11,6 @@ adi_project_files daq2_vc707 [list \
"$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \ "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
"$ad_hdl_dir/projects/common/vc707/vc707_system_constr.xdc" ] "$ad_hdl_dir/projects/common/vc707/vc707_system_constr.xdc" ]
set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/vc707/vc707_system_constr.xdc]
set_property PROCESSING_ORDER EARLY [get_files system_constr.xdc]
adi_project_run daq2_vc707 adi_project_run daq2_vc707

20
projects/daq2/vc707/system_top.v
View File

@ -354,8 +354,14 @@ module system_top (
.mgt_clk_clk_p (mgt_clk_p), .mgt_clk_clk_p (mgt_clk_p),
.phy_rstn (phy_rstn), .phy_rstn (phy_rstn),
.phy_sd (1'b1), .phy_sd (1'b1),
.rx_data_n (rx_data_n), .rx_data_0_n (rx_data_n[0]),
.rx_data_p (rx_data_p), .rx_data_0_p (rx_data_p[0]),
.rx_data_1_n (rx_data_n[1]),
.rx_data_1_p (rx_data_p[1]),
.rx_data_2_n (rx_data_n[2]),
.rx_data_2_p (rx_data_p[2]),
.rx_data_3_n (rx_data_n[3]),
.rx_data_3_p (rx_data_p[3]),
.rx_ref_clk (rx_ref_clk), .rx_ref_clk (rx_ref_clk),
.rx_sync (rx_sync), .rx_sync (rx_sync),
.rx_sysref (rx_sysref), .rx_sysref (rx_sysref),
@ -373,8 +379,14 @@ module system_top (
.sys_clk_n (sys_clk_n), .sys_clk_n (sys_clk_n),
.sys_clk_p (sys_clk_p), .sys_clk_p (sys_clk_p),
.sys_rst (sys_rst), .sys_rst (sys_rst),
.tx_data_n (tx_data_n), .tx_data_0_n (tx_data_n[0]),
.tx_data_p (tx_data_p), .tx_data_0_p (tx_data_p[0]),
.tx_data_1_n (tx_data_n[1]),
.tx_data_1_p (tx_data_p[1]),
.tx_data_2_n (tx_data_n[2]),
.tx_data_2_p (tx_data_p[2]),
.tx_data_3_n (tx_data_n[3]),
.tx_data_3_p (tx_data_p[3]),
.tx_ref_clk (tx_ref_clk), .tx_ref_clk (tx_ref_clk),
.tx_sync (tx_sync), .tx_sync (tx_sync),
.tx_sysref (tx_sysref), .tx_sysref (tx_sysref),