docs/regmap/adi_regmap_dac.txt : Updated and added some registers
-Updated description of some fields of these registers: REG_CHAN_CNTRL_1, REG_CHAN_CNTRL_2, REG_CHAN_CNTRL_3, REG_CHAN_CNTRL_4, REG_USR_CNTRL_4, and REG_USR_CNTRL_5 -Added two new registers, both with their own fields and description: REG_CHAN_CNTRL_9 and REG_CHAN_CNTRL_10 Signed-off-by: Cristian Mihai Popa <cristianmihai.popa@analog.com>main
Cristian Mihai Popa
AndreiGrozav
parent
8b07dfa033
commit
0baf3a7c4f
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@ -469,16 +469,24 @@ REG_CHAN_CNTRL_1
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DAC Channel Control & Status (channel - 0)
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ENDREG
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FIELD
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[21:16] 0x0000
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DDS_PHASE_DW[5:0]
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R
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The DDS phase data width offers the HDL parameter configuration with the same
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name. This information is used in conjunction with REG_CHAN_CNTRL_9 and REG_CHAN_CNTRL_10.
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More info at https://wiki.analog.com/resources/fpga/docs/dds
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ENDFIELD
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FIELD
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[15:0] 0x0000
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DDS_SCALE_1[15:0]
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RW
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The DDS scale for tone 1. Defines the amplitude of the tone. The format is
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1.1.14 fixed point (signed, integer, fractional). The DDS in general runs on
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16-bits, note that if you do use both channels and set both scale to 0x4000,
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it is over-range. The final output is (channel_1_fullscale * scale_1) +
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(channel_2 * scale_2).
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NOT-APPLICABLE if DDS_DISABLE is set (0x1).
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The DDS scale for tone 1. Sets the amplitude of the tone. The format is 1.1.14
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fixed point (signed, integer, fractional). The DDS in general runs on 16-bits,
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note that if you do use both channels and set both scale to 0x4000, it is
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over-range. The final output is (tone_1_fullscale * scale_1) +
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(tone_2_fullscale * scale_2). NOT-APPLICABLE if DDS_DISABLE is set (0x1).
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ENDFIELD
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############################################################################################
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@ -494,20 +502,21 @@ FIELD
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[31:16] 0x0000
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DDS_INIT_1[15:0]
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RW
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The DDS phase initialization for tone 1. Defines the initial phase offset of
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the tone.
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NOT-APPLICABLE if DDS_DISABLE is set (0x1).
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The DDS phase initialization for tone 1. Sets the initial phase offset
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of the tone. NOT-APPLICABLE if DDS_DISABLE is set (0x1).
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ENDFIELD
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FIELD
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[15:0] 0x0000
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DDS_INCR_1[15:0]
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RW
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Defines the resolution of the phase accumulator. Its value can be defined by
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<m>INCR = (f_out * 2^16) * clkratio / f_if</m>; where f_out is the generated
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output frequency, and f_if is the frequency of the digital interface, and
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clock_ratio is the ratio between the sampling clock and the interface clock.
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NOT-APPLICABLE if DDS_DISABLE is set (0x1).
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Sets the frequency of the phase accumulator. Its value can be calculated
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by <m>INCR = (f_out * 2^16) * clkratio / f_if</m>; where f_out is the
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generated output frequency, and f_if is the frequency of the digital
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interface, and clock_ratio is the ratio between the sampling clock and
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the interface clock. If DDS_PHASE_DW is greater than 16(from REG_CHAN_CNTRL_1),
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the phase increment for tone 1 is extended in REG_CHAN_CNTRL_9. NOT-APPLICABLE
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if DDS_DISABLE is set (0x1).
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ENDFIELD
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############################################################################################
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@ -523,11 +532,11 @@ FIELD
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[15:0] 0x0000
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DDS_SCALE_2[15:0]
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RW
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The DDS scale for tone 1. Defines the amplitude of the tone. The format is
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1.1.14 fixed point (signed, integer, fractional). The DDS in general runs on
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16-bits, note that if you do use both channels and set both scale to 0x4000,
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it is over-range. The final output is (channel_1_fullscale * scale_1) +
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(channel_2 * scale_2).
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The DDS scale for tone 2. Sets the amplitude of the tone. The format
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is 1.1.14 fixed point (signed, integer, fractional).
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The DDS in general runs on 16-bits, note that if you do use both
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channels and set both scale to 0x4000, it is over-range. The final
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output is (tone_1_fullscale * scale_1) + (tone_2_fullscale * scale_2).
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NOT-APPLICABLE if DDS_DISABLE is set (0x1).
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ENDFIELD
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@ -544,20 +553,23 @@ FIELD
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[31:16] 0x0000
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DDS_INIT_2[15:0]
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RW
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The DDS phase initialization for tone 1. Defines the initial phase offset of
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the tone.
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NOT-APPLICABLE if DDS_DISABLE is set (0x1).
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The DDS phase initialization for tone 2. Sets the initial phase offset of the
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tone. If DDS_PHASE_DW is greater than 16(from REG_CHAN_CNTRL_1), the phase init
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for tone 2 is extended in REG_CHAN_CNTRL_10. NOT-APPLICABLE if DDS_DISABLE is
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set (0x1).
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ENDFIELD
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FIELD
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[15:0] 0x0000
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DDS_INCR_2[15:0]
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RW
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Defines the resolution of the phase accumulator. Its value can be defined by
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Sets the frequency of the phase accumulator. Its value can be calculated by
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<m>INCR = (f_out * 2^16) * clkratio / f_if</m>; where f_out is the generated
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output frequency, and f_if is the frequency of the digital interface, and
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clock_ratio is the ratio between the sampling clock and the interface clock.
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NOT-APPLICABLE if DDS_DISABLE is set (0x1).
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clock_ratio is the ratio between the sampling clock and the interface clock.
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If DDS_PHASE_DW is greater than 16(from REG_CHAN_CNTRL_1), the phase increment
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for tone 2 is extended in REG_CHAN_CNTRL_10. NOT-APPLICABLE if DDS_DISABLE is
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set (0x1).
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ENDFIELD
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############################################################################################
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@ -737,9 +749,9 @@ FIELD
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[31:16] 0x0000
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USR_INTERPOLATION_M[15:0]
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RW
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This holds the user interpolation M value of the channel that is currently being selected on
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the multiplexer above. The total interpolation factor is of the form M/N.
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NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
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This holds the user interpolation M value of the channel that is currently being
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selected on the multiplexer above. The total interpolation factor is of the
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form M/N. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
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ENDFIELD
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FIELD
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@ -772,7 +784,70 @@ FIELD
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[1] 0x0
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DAC_IQ_SWAP[1]
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RW
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Allows IQ swapping in complex mode. Only takes effect if complex mode is enabled.
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Allows IQ swapping in complex mode. Only takes effect if complex mode
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is enabled.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x010B
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REG_CHAN_CNTRL_9
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DAC Channel Control & Status (channel - 0)
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ENDREG
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FIELD
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[31:16] 0x0000
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DDS_INIT_1_EXTENDED[15:0]
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RW
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The extended DDS phase initialization for tone 1. Sets the initial phase offset
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of the tone. The extended init(phase) value should be calculated according to
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DDS_PHASE_DW value from REG_CHAN_CNTRL_1 NOT-APPLICABLE if DDS_DISABLE is
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set (0x1).
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ENDFIELD
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FIELD
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[15:0] 0x0000
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DDS_INCR_1_EXTENDED[15:0]
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RW
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Sets the frequency of tone 1's phase accumulator. Its value can be calculated
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by <m>INCR = (f_out * 2^phaseDW) * clkratio / f_if</m>; Where f_out is the
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generated output frequency, DDS_PHASE_DW value can be found in REG_CHAN_CNTRL_1
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in case DDS_PHASE_DW is not 16, f_if is the frequency of the digital interface,
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and clock_ratio is the ratio between the sampling clock and the interface clock.
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NOT-APPLICABLE if DDS_DISABLE is set (0x1).
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x010C
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REG_CHAN_CNTRL_10
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DAC Channel Control & Status (channel - 0)
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ENDREG
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FIELD
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[31:16] 0x0000
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DDS_INIT_2_EXTENDED[15:0]
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RW
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The extended DDS phase initialization for tone 2. Sets the initial phase offset
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of the tone. The extended init(phase) value should be calculated according to
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DDS_PHASE_DW value from REG_CHAN_CNTRL_2 NOT-APPLICABLE if DDS_DISABLE is
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set (0x1).
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ENDFIELD
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FIELD
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[15:0] 0x0000
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DDS_INCR_2_EXTENDED[15:0]
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RW
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Sets the frequency of tone 2's phase accumulator. Its value can be calculated
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by <m>INCR = (f_out * 2^phaseDW) * clkratio / f_if</m>; Where f_out is the
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generated output frequency, DDS_PHASE_DW value can be found in REG_CHAN_CNTRL_2
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in case DDS_PHASE_DW is not 16, f_if is the frequency of the digital interface,
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and clock_ratio is the ratio between the sampling clock and the interface clock.
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NOT-APPLICABLE if DDS_DISABLE is set (0x1).
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ENDFIELD
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############################################################################################
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@ -797,4 +872,4 @@ Channel 15, similar to registers 0x100 to 0x10f.
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ENDREG
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############################################################################################
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############################################################################################
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############################################################################################
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