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altera- adi-project-create version

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Rejeesh Kutty 2017-06-05 15:24:35 -04:00
parent 1b1c7ffa61
commit 0bd22e78d9
4 changed files with 7 additions and 62 deletions
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33
projects/adrv9371x/a10gx/system_constr.sdc
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@ -6,35 +6,6 @@ create_clock -period "8.139 ns" -name ref_clk1_122mhz [get_ports {ref_clk1
derive_pll_clocks derive_pll_clocks
derive_clock_uncertainty derive_clock_uncertainty
set_false_path -from [get_clocks {sys_clk_100mhz}]\ set_false_path -from [get_clocks {sys_clk_100mhz}] -through [get_nets *altera_jesd204*] -to [get_clocks *outclk0*]
-through [get_nets *altera_jesd204_tx_csr_inst*]\ set_false_path -from [get_clocks *outclk0*] -through [get_nets *altera_jesd204*] -to [get_clocks {sys_clk_100mhz}]
-to [get_clocks {i_system_bd|avl_ad9371_tx_xcvr|alt_core_pll|outclk0}]
set_false_path -from [get_clocks {sys_clk_100mhz}]\
-through [get_nets *altera_jesd204_tx_ctl_inst*]\
-to [get_clocks {i_system_bd|avl_ad9371_tx_xcvr|alt_core_pll|outclk0}]
set_false_path -from [get_clocks {sys_clk_100mhz}]\
-through [get_nets *altera_jesd204_rx_csr_inst*]\
-to [get_clocks {i_system_bd|avl_ad9371_rx_xcvr|alt_core_pll|outclk0}]
set_false_path -from [get_clocks {sys_clk_100mhz}]\
-through [get_nets *altera_jesd204_rx_csr_inst*]\
-to [get_clocks {i_system_bd|avl_ad9371_rx_os_xcvr|alt_core_pll|outclk0}]
set_false_path -from [get_clocks {i_system_bd|avl_ad9371_tx_xcvr|alt_core_pll|outclk0}]\
-through [get_nets *altera_jesd204_tx_csr_inst*]\
-to [get_clocks {sys_clk_100mhz}]
set_false_path -from [get_clocks {i_system_bd|avl_ad9371_tx_xcvr|alt_core_pll|outclk0}]\
-through [get_nets *altera_jesd204_tx_ctl_inst*]\
-to [get_clocks {sys_clk_100mhz}]
set_false_path -from [get_clocks {i_system_bd|avl_ad9371_rx_xcvr|alt_core_pll|outclk0}]\
-through [get_nets *altera_jesd204_rx_csr_inst*]\
-to [get_clocks {sys_clk_100mhz}]
set_false_path -from [get_clocks {i_system_bd|avl_ad9371_rx_os_xcvr|alt_core_pll|outclk0}]\
-through [get_nets *altera_jesd204_rx_csr_inst*]\
-to [get_clocks {sys_clk_100mhz}]

13
projects/adrv9371x/a10gx/system_project.tcl
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@ -1,17 +1,11 @@
load_package flow
source ../../scripts/adi_env.tcl source ../../scripts/adi_env.tcl
project_new adrv9371x_a10gx -overwrite source ../../scripts/adi_project_alt.tcl
adi_project_create adrv9371x_a10gx
source "../../common/a10gx/a10gx_system_assign.tcl" source "../../common/a10gx/a10gx_system_assign.tcl"
set_global_assignment -name VERILOG_FILE system_top.v
set_global_assignment -name QSYS_FILE system_bd.qsys
set_global_assignment -name SDC_FILE system_constr.sdc
set_global_assignment -name TOP_LEVEL_ENTITY system_top
# lane interface # lane interface
set_location_assignment PIN_AL8 -to ref_clk0 ; ## D04 FMCA_GBTCLK0_M2C_P set_location_assignment PIN_AL8 -to ref_clk0 ; ## D04 FMCA_GBTCLK0_M2C_P
@ -61,7 +55,6 @@ set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_1 -to tx_data[1]
set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_2 -to tx_data[2] set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_2 -to tx_data[2]
set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_3 -to tx_data[3] set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_3 -to tx_data[3]
set_location_assignment PIN_AR20 -to rx_sync ; ## G09 FMCA_HPC_LA03_P set_location_assignment PIN_AR20 -to rx_sync ; ## G09 FMCA_HPC_LA03_P
set_location_assignment PIN_AR19 -to rx_sync(n) ; ## G10 FMCA_HPC_LA03_N set_location_assignment PIN_AR19 -to rx_sync(n) ; ## G10 FMCA_HPC_LA03_N
set_location_assignment PIN_AY15 -to rx_os_sync ; ## G27 FMCA_HPC_LA25_P (Sniffer) set_location_assignment PIN_AY15 -to rx_os_sync ; ## G27 FMCA_HPC_LA25_P (Sniffer)

16
projects/common/a10gx/a10gx_system_assign.tcl
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@ -1,14 +1,4 @@
# a10gx carrier defaults
# device settings
set_global_assignment -name FAMILY "Arria 10"
set_global_assignment -name DEVICE 10AX115S3F45E2SGE3
# ignored warnings and such
set_global_assignment -name MESSAGE_DISABLE 17951 ; ## disable unused RX channels message
set_global_assignment -name MESSAGE_DISABLE 18655 ; ## disable unused TX channels message
# clocks and resets # clocks and resets
set_location_assignment PIN_AR36 -to sys_clk set_location_assignment PIN_AR36 -to sys_clk
@ -232,7 +222,3 @@ set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_i[8]
set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_i[9] set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_i[9]
set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_i[10] set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_i[10]
# source defaults
source $ad_hdl_dir/projects/common/altera/sys_gen.tcl

7
projects/common/a10gx/a10gx_system_qsys.tcl
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@ -1,9 +1,4 @@
# a10gx carrier qsys
package require qsys
set_module_property NAME {system_bd}
set_project_property DEVICE_FAMILY {Arria 10}
set_project_property DEVICE {10AX115S3F45E2SGE3}
set system_type nios set system_type nios